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-rw-r--r--binutils-2.22/include/opcode/ChangeLog95
-rw-r--r--binutils-2.22/include/opcode/avr.h12
-rw-r--r--binutils-2.22/include/opcode/crx.h4
-rw-r--r--binutils-2.22/include/opcode/i386.h2
-rw-r--r--binutils-2.22/include/opcode/m68hc11.h50
-rw-r--r--binutils-2.22/include/opcode/mips.h18
-rw-r--r--binutils-2.22/include/opcode/ppc.h54
-rw-r--r--binutils-2.22/include/opcode/rl78.h168
-rw-r--r--binutils-2.22/include/opcode/sparc.h57
-rw-r--r--binutils-2.22/include/opcode/tilegx.h2
-rw-r--r--binutils-2.22/include/opcode/tilepro.h2
-rw-r--r--binutils-2.22/include/opcode/xgate.h120
12 files changed, 538 insertions, 46 deletions
diff --git a/binutils-2.22/include/opcode/ChangeLog b/binutils-2.22/include/opcode/ChangeLog
index 8f070a1..4b8d300 100644
--- a/binutils-2.22/include/opcode/ChangeLog
+++ b/binutils-2.22/include/opcode/ChangeLog
@@ -1,3 +1,98 @@
+2012-07-06 Maciej W. Rozycki <macro@codesourcery.com>
+
+ * mips.h: Fix a typo in description.
+
+2012-06-07 Georg-Johann Lay <avr@gjlay.de>
+
+ * avr.h: (AVR_ISA_XCH): New define.
+ (AVR_ISA_XMEGA): Use it.
+ (XCH, LAS, LAT, LAC): New XMEGA opcodes.
+
+2012-05-15 James Murray <jsm@jsm-net.demon.co.uk>
+
+ * m68hc11.h: Add XGate definitions.
+ (struct m68hc11_opcode): Add xg_mask field.
+
+2012-05-14 Catherine Moore <clm@codesourcery.com>
+ Maciej W. Rozycki <macro@codesourcery.com>
+ Rhonda Wittels <rhonda@codesourcery.com>
+
+ * ppc.h (PPC_OPCODE_VLE): New definition.
+ (PPC_OP_SA): New macro.
+ (PPC_OP_SE_VLE): New macro.
+ (PPC_OP): Use a variable shift amount.
+ (powerpc_operand): Update comments.
+ (PPC_OPSHIFT_INV): New macro.
+ (PPC_OPERAND_CR): Replace with...
+ (PPC_OPERAND_CR_BIT): ...this and
+ (PPC_OPERAND_CR_REG): ...this.
+
+
+2012-05-03 Sean Keys <skeys@ipdatasys.com>
+
+ * xgate.h: Header file for XGATE assembler.
+
+2012-04-27 David S. Miller <davem@davemloft.net>
+
+ * sparc.h: Document new arg code' )' for crypto RS3
+ immediates.
+
+ * sparc.h (struct sparc_opcode): New field 'hwcaps'.
+ F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
+ F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
+ F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
+ (HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
+ HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
+ HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
+ HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
+ HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
+ HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
+ HWCAP_CBCOND, HWCAP_CRC32): New defines.
+
+2012-03-10 Edmar Wienskoski <edmar@freescale.com>
+
+ * ppc.h: Add PPC_OPCODE_ALTIVEC2, PPC_OPCODE_E6500, PPC_OPCODE_TMR.
+
+2012-02-27 Alan Modra <amodra@gmail.com>
+
+ * crx.h (cst4_map): Update declaration.
+
+2012-02-25 Walter Lee <walt@tilera.com>
+
+ * tilegx.h (tilegx_mnemonic): Add TILEGX_OPC_LD4S_TLS,
+ TILEGX_OPC_LD_TLS.
+ * tilepro.h (tilepro_mnemonic): Add TILEPRO_OPC_LW_TLS,
+ TILEPRO_OPC_LW_TLS_SN.
+
+2012-02-08 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386.h (XACQUIRE_PREFIX_OPCODE): New.
+ (XRELEASE_PREFIX_OPCODE): Likewise.
+
+2011-12-08 Andrew Pinski <apinski@cavium.com>
+ Adam Nemet <anemet@caviumnetworks.com>
+
+ * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEON2.
+ (INSN_OCTEON2): New macro.
+ (CPU_OCTEON2): New macro.
+ (OPCODE_IS_MEMBER): Add Octeon2.
+
+2011-11-29 Andrew Pinski <apinski@cavium.com>
+
+ * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEONP.
+ (INSN_OCTEONP): New macro.
+ (CPU_OCTEONP): New macro.
+ (OPCODE_IS_MEMBER): Add Octeon+.
+ (M_SAA_AB, M_SAAD_AB, M_SAA_OB, M_SAAD_OB): New enum values.
+
+2011-11-01 DJ Delorie <dj@redhat.com>
+
+ * rl78.h: New file.
+
+2011-10-24 Maciej W. Rozycki <macro@codesourcery.com>
+
+ * mips.h: Fix a typo in description.
+
2011-09-21 David S. Miller <davem@davemloft.net>
* sparc.h (struct sparc_opcode): Expand 'flags' to unsigned int.
diff --git a/binutils-2.22/include/opcode/avr.h b/binutils-2.22/include/opcode/avr.h
index a6d7b47..6e86c07 100644
--- a/binutils-2.22/include/opcode/avr.h
+++ b/binutils-2.22/include/opcode/avr.h
@@ -1,6 +1,6 @@
/* Opcode table for the Atmel AVR micro controllers.
- Copyright 2000, 2001, 2004, 2006, 2008, 2010 Free Software Foundation, Inc.
+ Copyright 2000, 2001, 2004, 2006, 2008, 2010, 2012 Free Software Foundation, Inc.
Contributed by Denis Chertykov <denisc@overta.ru>
This program is free software; you can redistribute it and/or modify
@@ -33,6 +33,7 @@
#define AVR_ISA_MOVW 0x1000 /* device has MOVW */
#define AVR_ISA_SPMX 0x2000 /* device has SPM Z[+] */
#define AVR_ISA_DES 0x4000 /* device has DES */
+#define AVR_ISA_XCH 0x8000 /* device has XCH, LAC, LAS, LAT */
#define AVR_ISA_TINY1 (AVR_ISA_1200 | AVR_ISA_LPM)
#define AVR_ISA_2xxx (AVR_ISA_TINY1 | AVR_ISA_SRAM)
@@ -52,7 +53,7 @@
#define AVR_ISA_M323 (AVR_ISA_M161 | AVR_ISA_BRK)
#define AVR_ISA_M128 (AVR_ISA_M323 | AVR_ISA_ELPM | AVR_ISA_ELPMX)
#define AVR_ISA_M256 (AVR_ISA_M128 | AVR_ISA_EIND)
-#define AVR_ISA_XMEGA (AVR_ISA_M256 | AVR_ISA_SPMX | AVR_ISA_DES)
+#define AVR_ISA_XMEGA (AVR_ISA_M256 | AVR_ISA_SPMX | AVR_ISA_DES | AVR_ISA_XCH)
#define AVR_ISA_AVR1 AVR_ISA_TINY1
#define AVR_ISA_AVR2 AVR_ISA_2xxx
@@ -124,7 +125,6 @@
0x0001...0x00ff (255) (known to be decoded as `nop' by the old core)
"100100xxxxxxx011" (128) 0x9[0-3][0-9a-f][3b]
"100100xxxxxx1000" (64) 0x9[0-3][0-9a-f]8
- "1001001xxxxx01xx" (128) 0x9[23][0-9a-f][4-7]
"1001010xxxxx0100" (32) 0x9[45][0-9a-f]4
"1001010x001x1001" (4) 0x9[45][23]9
"1001010x01xx1001" (8) 0x9[45][4-7]9
@@ -265,6 +265,12 @@ AVR_INSN (push, "r", "1001001rrrrr1111", 1, AVR_ISA_2xxx, 0x920f)
AVR_INSN (ror, "r", "1001010rrrrr0111", 1, AVR_ISA_1200, 0x9407)
AVR_INSN (swap, "r", "1001010rrrrr0010", 1, AVR_ISA_1200, 0x9402)
+ /* Atomic memory operations for XMEGA. List before `sts'. */
+AVR_INSN (xch, "z,r", "1001001rrrrr0100", 1, AVR_ISA_XCH, 0x9204)
+AVR_INSN (las, "z,r", "1001001rrrrr0101", 1, AVR_ISA_XCH, 0x9205)
+AVR_INSN (lac, "z,r", "1001001rrrrr0110", 1, AVR_ISA_XCH, 0x9206)
+AVR_INSN (lat, "z,r", "1001001rrrrr0111", 1, AVR_ISA_XCH, 0x9207)
+
/* Known to be decoded as `nop' by the old core. */
AVR_INSN (movw, "v,v", "00000001ddddrrrr", 1, AVR_ISA_MOVW, 0x0100)
AVR_INSN (muls, "d,d", "00000010ddddrrrr", 1, AVR_ISA_MUL, 0x0200)
diff --git a/binutils-2.22/include/opcode/crx.h b/binutils-2.22/include/opcode/crx.h
index 5c484bf..6081ea3 100644
--- a/binutils-2.22/include/opcode/crx.h
+++ b/binutils-2.22/include/opcode/crx.h
@@ -1,5 +1,5 @@
/* crx.h -- Header file for CRX opcode and register tables.
- Copyright 2004, 2010 Free Software Foundation, Inc.
+ Copyright 2004, 2010, 2012 Free Software Foundation, Inc.
Contributed by Tomer Levi, NSC, Israel.
Originally written for GAS 2.12 by Tomer Levi, NSC, Israel.
Updates, BFDizing, GNUifying and ELF support by Tomer Levi.
@@ -384,7 +384,7 @@ extern const int crx_num_traps;
#define NUMTRAPS crx_num_traps
/* cst4 operand mapping. */
-extern const long cst4_map[];
+extern const int cst4_map[];
extern const int cst4_maps;
/* Table of instructions with no operands. */
diff --git a/binutils-2.22/include/opcode/i386.h b/binutils-2.22/include/opcode/i386.h
index b635334..ad6d3c6 100644
--- a/binutils-2.22/include/opcode/i386.h
+++ b/binutils-2.22/include/opcode/i386.h
@@ -76,6 +76,8 @@
#define SS_PREFIX_OPCODE 0x36
#define REPNE_PREFIX_OPCODE 0xf2
#define REPE_PREFIX_OPCODE 0xf3
+#define XACQUIRE_PREFIX_OPCODE 0xf2
+#define XRELEASE_PREFIX_OPCODE 0xf3
#define TWO_BYTE_OPCODE_ESCAPE 0x0f
#define NOP_OPCODE (char) 0x90
diff --git a/binutils-2.22/include/opcode/m68hc11.h b/binutils-2.22/include/opcode/m68hc11.h
index 83f5a9a..1a00200 100644
--- a/binutils-2.22/include/opcode/m68hc11.h
+++ b/binutils-2.22/include/opcode/m68hc11.h
@@ -1,5 +1,6 @@
/* m68hc11.h -- Header file for Motorola 68HC11 & 68HC12 opcode table
- Copyright 1999, 2000, 2002, 2003, 2010 Free Software Foundation, Inc.
+ Copyright 1999, 2000, 2002, 2003, 2010, 2012
+ Free Software Foundation, Inc.
Written by Stephane Carrez (stcarrez@nerim.fr)
This file is part of GDB, GAS, and the GNU binutils.
@@ -37,8 +38,7 @@
of the M6811_INIT register. At init time, the I/O registers are
mapped at 0x1000. Address of registers is then:
- 0x1000 + M6811_xxx
-*/
+ 0x1000 + M6811_xxx. */
#define M6811_PORTA 0x00 /* Port A register */
#define M6811__RES1 0x01 /* Unused/Reserved */
#define M6811_PIOC 0x02 /* Parallel I/O Control register */
@@ -364,6 +364,26 @@
#define M6812_INDEXED 0x20000000 /* n,r n = 5, 9 or 16-bits */
#define M6812_OP_IDX_P2 0x40000000
+/* XGATE defines.
+ These overlap with HC11/12 as above but not used at the same time. */
+#define M68XG_OP_NONE 0x0001
+#define M68XG_OP_IMM3 0x0002
+#define M68XG_OP_R 0x0004
+#define M68XG_OP_R_R 0x0008
+#define M68XG_OP_R_IMM4 0x0010
+#define M68XG_OP_R_R_R 0x0020
+#define M68XG_OP_REL9 0x0040
+#define M68XG_OP_REL10 0x0080
+#define M68XG_OP_R_R_OFFS5 0x0100
+#define M68XG_OP_RD_RB_RI 0x0200
+#define M68XG_OP_RD_RB_RIp 0x0400
+#define M68XG_OP_RD_RB_mRI 0x0800
+#define M68XG_OP_R_IMM8 0x1000
+#define M68XG_OP_R_IMM16 0x2000
+#define M68XG_OP_REG 0x4000 /* Register operand 1. */
+#define M68XG_OP_REG_2 0x8000 /* Register operand 2. */
+#define M68XG_MAX_OPERANDS 3 /* Max operands of triadic r1, r2, r3. */
+
/* Markers to identify some instructions. */
#define M6812_OP_EXG_MARKER 0x01000000 /* exg r1,r2 */
#define M6812_OP_TFR_MARKER 0x02000000 /* tfr r1,r2 */
@@ -374,35 +394,43 @@
#define M6812_OP_IBCC_MARKER 0x02000000 /* ibeq/ibne */
#define M6812_OP_TBCC_MARKER 0x01000000
+/* XGATE markers. */
+#define M68XG_OP_B_MARKER 0x04000000 /* bXX rel9 */
+#define M68XG_OP_BRA_MARKER 0x02000000 /* bra rel10 */
+
#define M6812_OP_TRAP_ID 0x80000000 /* trap #N */
#define M6811_OP_HIGH_ADDR 0x01000000 /* Used internally by gas. */
#define M6811_OP_LOW_ADDR 0x02000000
-#define M68HC12_BANK_VIRT 0x010000
-#define M68HC12_BANK_MASK 0x00003fff
-#define M68HC12_BANK_BASE 0x00008000
-#define M68HC12_BANK_SHIFT 14
-#define M68HC12_BANK_PAGE_MASK 0x0ff
+#define M68HC12_BANK_VIRT 0x010000
+#define M68HC12_BANK_MASK 0x00003fff
+#define M68HC12_BANK_BASE 0x00008000
+#define M68HC12_BANK_SHIFT 14
+#define M68HC12_BANK_PAGE_MASK 0x0ff
/* CPU identification. */
#define cpu6811 0x01
#define cpu6812 0x02
#define cpu6812s 0x04
+#define cpu9s12x 0x08 /* 9S12X main cpu. */
+#define cpuxgate 0x10 /* The XGATE module itself. */
/* The opcode table is an array of struct m68hc11_opcode. */
-struct m68hc11_opcode {
- const char* name; /* Op-code name */
+struct m68hc11_opcode
+{
+ const char * name; /* Op-code name. */
long format;
unsigned char size;
- unsigned char opcode;
+ unsigned int opcode;
unsigned char cycles_low;
unsigned char cycles_high;
unsigned char set_flags_mask;
unsigned char clr_flags_mask;
unsigned char chg_flags_mask;
unsigned char arch;
+ unsigned int xg_mask; /* Mask with zero in register place for xgate. */
};
/* Alias definition for 68HC12. */
diff --git a/binutils-2.22/include/opcode/mips.h b/binutils-2.22/include/opcode/mips.h
index e6703f8..9232508 100644
--- a/binutils-2.22/include/opcode/mips.h
+++ b/binutils-2.22/include/opcode/mips.h
@@ -713,10 +713,12 @@ static const unsigned int mips_isa_table[] =
{ 0x0001, 0x0003, 0x0607, 0x1e0f, 0x3e1f, 0x0a23, 0x3e63, 0x3ebf, 0x3fff };
/* Masks used for Chip specific instructions. */
-#define INSN_CHIP_MASK 0xc3ff0c20
+#define INSN_CHIP_MASK 0xc3ff0f20
/* Cavium Networks Octeon instructions. */
#define INSN_OCTEON 0x00000800
+#define INSN_OCTEONP 0x00000200
+#define INSN_OCTEON2 0x00000100
/* Masks used for MIPS-defined ASEs. */
#define INSN_ASE_MASK 0x3c00f010
@@ -823,6 +825,8 @@ static const unsigned int mips_isa_table[] =
#define CPU_LOONGSON_2F 3002
#define CPU_LOONGSON_3A 3003
#define CPU_OCTEON 6501
+#define CPU_OCTEONP 6601
+#define CPU_OCTEON2 6502
#define CPU_XLR 887682 /* decimal 'XLR' */
/* Test for membership in an ISA including chip specific ISAs. INSN
@@ -859,6 +863,10 @@ static const unsigned int mips_isa_table[] =
&& ((insn)->membership & INSN_LOONGSON_3A) != 0) \
|| (cpu == CPU_OCTEON \
&& ((insn)->membership & INSN_OCTEON) != 0) \
+ || (cpu == CPU_OCTEONP \
+ && ((insn)->membership & INSN_OCTEONP) != 0) \
+ || (cpu == CPU_OCTEON2 \
+ && ((insn)->membership & INSN_OCTEON2) != 0) \
|| (cpu == CPU_XLR && ((insn)->membership & INSN_XLR) != 0) \
|| 0) /* Please keep this term for easier source merging. */
@@ -1065,6 +1073,10 @@ enum
M_S_DOB,
M_S_DAB,
M_S_S,
+ M_SAA_AB,
+ M_SAA_OB,
+ M_SAAD_AB,
+ M_SAAD_OB,
M_SC_AB,
M_SC_OB,
M_SCD_AB,
@@ -1616,7 +1628,7 @@ extern const int bfd_mips16_num_opcodes;
"c" 10-bit higher breakpoint code (MICROMIPSOP_*_CODE)
"d" 5-bit destination register specifier (MICROMIPSOP_*_RD)
"h" 5-bit PREFX hint (MICROMIPSOP_*_PREFX)
- "i" 16 bit unsigned immediate (MICROMIPSOP_*_IMMEDIATE)
+ "i" 16-bit unsigned immediate (MICROMIPSOP_*_IMMEDIATE)
"j" 16-bit signed immediate (MICROMIPSOP_*_DELTA)
"k" 5-bit cache opcode in target register position (MICROMIPSOP_*_CACHE)
"n" register list for 32-bit LWM/SWM instruction (MICROMIPSOP_*_RT)
@@ -1634,7 +1646,7 @@ extern const int bfd_mips16_num_opcodes;
"y" 5-bit source 3 register for ALNV.PS (MICROMIPSOP_*_RS3)
"z" must be zero register
"C" 23-bit coprocessor function code (MICROMIPSOP_*_COPZ)
- "B" 8-bit syscall/wait function code (MICROMIPSOP_*_CODE10)
+ "B" 10-bit syscall/wait function code (MICROMIPSOP_*_CODE10)
"K" 5-bit Hardware Register (RDHWR instruction) (MICROMIPSOP_*_RS)
"+A" 5-bit INS/EXT/DINS/DEXT/DINSM/DEXTM position, which becomes
diff --git a/binutils-2.22/include/opcode/ppc.h b/binutils-2.22/include/opcode/ppc.h
index a0119dc..2e789d6 100644
--- a/binutils-2.22/include/opcode/ppc.h
+++ b/binutils-2.22/include/opcode/ppc.h
@@ -1,6 +1,6 @@
/* ppc.h -- Header file for PowerPC opcode table
Copyright 1994, 1995, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006,
- 2007, 2008, 2009, 2010 Free Software Foundation, Inc.
+ 2007, 2008, 2009, 2010, 2012 Free Software Foundation, Inc.
Written by Ian Lance Taylor, Cygnus Support
This file is part of GDB, GAS, and the GNU binutils.
@@ -65,6 +65,8 @@ struct powerpc_opcode
instructions. */
extern const struct powerpc_opcode powerpc_opcodes[];
extern const int powerpc_num_opcodes;
+extern const struct powerpc_opcode vle_opcodes[];
+extern const int vle_num_opcodes;
/* Values defined for the flags field of a struct powerpc_opcode. */
@@ -174,8 +176,29 @@ extern const int powerpc_num_opcodes;
/* Opcode which is supported by the e500 family */
#define PPC_OPCODE_E500 0x100000000ull
+/* Opcode is supported by Extended Altivec Vector Unit */
+#define PPC_OPCODE_ALTIVEC2 0x200000000ull
+
+/* Opcode is supported by Power E6500 */
+#define PPC_OPCODE_E6500 0x400000000ull
+
+/* Opcode is supported by Thread management APU */
+#define PPC_OPCODE_TMR 0x800000000ull
+
+/* Opcode which is supported by the VLE extension. */
+#define PPC_OPCODE_VLE 0x1000000000ull
+
/* A macro to extract the major opcode from an instruction. */
#define PPC_OP(i) (((i) >> 26) & 0x3f)
+
+/* A macro to determine if the instruction is a 2-byte VLE insn. */
+#define PPC_OP_SE_VLE(m) ((m) <= 0xffff)
+
+/* A macro to extract the major opcode from a VLE instruction. */
+#define VLE_OP(i,m) (((i) >> ((m) <= 0xffff ? 10 : 26)) & 0x3f)
+
+/* A macro to convert a VLE opcode to a VLE opcode segment. */
+#define VLE_OP_TO_SEG(i) ((i) >> 1)
/* The operands table is an array of struct powerpc_operand. */
@@ -184,16 +207,22 @@ struct powerpc_operand
/* A bitmask of bits in the operand. */
unsigned int bitm;
- /* How far the operand is left shifted in the instruction.
- -1 to indicate that BITM and SHIFT cannot be used to determine
- where the operand goes in the insn. */
+ /* The shift operation to be applied to the operand. No shift
+ is made if this is zero. For positive values, the operand
+ is shifted left by SHIFT. For negative values, the operand
+ is shifted right by -SHIFT. Use PPC_OPSHIFT_INV to indicate
+ that BITM and SHIFT cannot be used to determine where the
+ operand goes in the insn. */
int shift;
/* Insertion function. This is used by the assembler. To insert an
operand value into an instruction, check this field.
If it is NULL, execute
- i |= (op & o->bitm) << o->shift;
+ if (o->shift >= 0)
+ i |= (op & o->bitm) << o->shift;
+ else
+ i |= (op & o->bitm) >> -o->shift;
(i is the instruction which we are filling in, o is a pointer to
this structure, and op is the operand value).
@@ -211,7 +240,10 @@ struct powerpc_operand
extract this operand type from an instruction, check this field.
If it is NULL, compute
- op = (i >> o->shift) & o->bitm;
+ if (o->shift >= 0)
+ op = (i >> o->shift) & o->bitm;
+ else
+ op = (i << -o->shift) & o->bitm;
if ((o->flags & PPC_OPERAND_SIGNED) != 0)
sign_extend (op);
(i is the instruction, o is a pointer to this structure, and op
@@ -235,6 +267,11 @@ struct powerpc_operand
extern const struct powerpc_operand powerpc_operands[];
extern const unsigned int num_powerpc_operands;
+/* Use with the shift field of a struct powerpc_operand to indicate
+ that BITM and SHIFT cannot be used to determine where the operand
+ goes in the insn. */
+#define PPC_OPSHIFT_INV (-1 << 31)
+
/* Values defined for the flags field of a struct powerpc_operand. */
/* This operand takes signed values. */
@@ -268,7 +305,7 @@ extern const unsigned int num_powerpc_operands;
cr4 4 cr5 5 cr6 6 cr7 7
These may be combined arithmetically, as in cr2*4+gt. These are
only supported on the PowerPC, not the POWER. */
-#define PPC_OPERAND_CR (0x10)
+#define PPC_OPERAND_CR_BIT (0x10)
/* This operand names a register. The disassembler uses this to print
register names with a leading 'r'. */
@@ -333,6 +370,9 @@ extern const unsigned int num_powerpc_operands;
/* This operand names a vector-scalar unit register. The disassembler
prints these with a leading 'vs'. */
#define PPC_OPERAND_VSR (0x100000)
+
+/* This is a CR FIELD that does not use symbolic names. */
+#define PPC_OPERAND_CR_REG (0x200000)
/* The POWER and PowerPC assemblers use a few macros. We keep them
with the operands table for simplicity. The macro table is an
diff --git a/binutils-2.22/include/opcode/rl78.h b/binutils-2.22/include/opcode/rl78.h
new file mode 100644
index 0000000..0f3c64d
--- /dev/null
+++ b/binutils-2.22/include/opcode/rl78.h
@@ -0,0 +1,168 @@
+/* Opcode decoder for the Renesas RL78
+ Copyright 2011
+ Free Software Foundation, Inc.
+ Written by DJ Delorie <dj@redhat.com>
+
+ This file is part of GDB, the GNU Debugger and GAS, the GNU Assembler.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA
+ 02110-1301, USA. */
+
+/* The RL78 decoder in libopcodes is used by the simulator, gdb's
+ analyzer, and the disassembler. Given an opcode data source, it
+ decodes the next opcode into the following structures. */
+
+#ifndef RL78_OPCODES_H_INCLUDED
+#define RL78_OPCODES_H_INCLUDED
+
+/* For the purposes of these structures, the RL78 registers are as
+ follows, despite most of these being memory-mapped and
+ bank-switched: */
+typedef enum {
+ RL78_Reg_None,
+ /* The order of these matches the encodings. */
+ RL78_Reg_X,
+ RL78_Reg_A,
+ RL78_Reg_C,
+ RL78_Reg_B,
+ RL78_Reg_E,
+ RL78_Reg_D,
+ RL78_Reg_L,
+ RL78_Reg_H,
+ /* The order of these matches the encodings. */
+ RL78_Reg_AX,
+ RL78_Reg_BC,
+ RL78_Reg_DE,
+ RL78_Reg_HL,
+ /* Unordered. */
+ RL78_Reg_SP,
+ RL78_Reg_PSW,
+ RL78_Reg_CS,
+ RL78_Reg_ES,
+ RL78_Reg_PMC,
+ RL78_Reg_MEM
+} RL78_Register;
+
+typedef enum
+{
+ RL78_Byte = 0,
+ RL78_Word
+} RL78_Size;
+
+typedef enum {
+ RL78_Condition_T,
+ RL78_Condition_F,
+ RL78_Condition_C,
+ RL78_Condition_NC,
+ RL78_Condition_H,
+ RL78_Condition_NH,
+ RL78_Condition_Z,
+ RL78_Condition_NZ
+} RL78_Condition;
+
+typedef enum {
+ RL78_Operand_None = 0,
+ RL78_Operand_Immediate, /* #addend */
+ RL78_Operand_Register, /* reg */
+ RL78_Operand_Indirect, /* [reg + reg2 + addend] */
+ RL78_Operand_Bit, /* reg.bit */
+ RL78_Operand_BitIndirect, /* [reg+reg2+addend].bit */
+ RL78_Operand_PreDec, /* [--reg] = push */
+ RL78_Operand_PostInc /* [reg++] = pop */
+} RL78_Operand_Type;
+
+typedef enum
+{
+ RLO_unknown,
+ RLO_add, /* d += s */
+ RLO_addc, /* d += s + CY */
+ RLO_and, /* d &= s (byte, word, bit) */
+ RLO_branch, /* pc = d */
+ RLO_branch_cond, /* pc = d if cond(src) */
+ RLO_branch_cond_clear, /* pc = d if cond(src), and clear(src) */
+ RLO_break, /* BRK */
+ RLO_call, /* call */
+ RLO_cmp, /* cmp d, s */
+ RLO_divhu, /* DIVHU */
+ RLO_divwu, /* DIVWU */
+ RLO_halt, /* HALT */
+ RLO_mov, /* d = s */
+ RLO_mach, /* MACH */
+ RLO_machu, /* MACHU */
+ RLO_mulu, /* MULU */
+ RLO_mulh, /* MULH */
+ RLO_mulhu, /* MULHU */
+ RLO_nop, /* NOP */
+ RLO_or, /* d |= s */
+ RLO_ret, /* RET */
+ RLO_reti, /* RETI */
+ RLO_rol, /* d <<= s, MSB to LSB and CY */
+ RLO_rolc, /* d <<= s, MSB to CY, CY, to LSB */
+ RLO_ror, /* d >>= s, LSB to MSB and CY */
+ RLO_rorc, /* d >>= s, LSB to CY, CY, to MSB */
+ RLO_sar, /* d >>= s, signed */
+ RLO_sel, /* rb = s */
+ RLO_shr, /* d >>= s, unsigned */
+ RLO_shl, /* d <<= s */
+ RLO_skip, /* skip next insn is cond(s) */
+ RLO_stop, /* STOP */
+ RLO_sub, /* d -= s */
+ RLO_subc, /* d -= s - CY */
+ RLO_xch, /* swap d, s */
+ RLO_xor, /* d ^= s */
+} RL78_Opcode_ID;
+
+typedef struct {
+ RL78_Operand_Type type;
+ int addend;
+ RL78_Register reg : 8;
+ RL78_Register reg2 : 8;
+ unsigned char bit_number : 4;
+ unsigned char condition : 3;
+ unsigned char use_es : 1;
+} RL78_Opcode_Operand;
+
+/* PSW flag bits */
+#define RL78_PSW_IE 0x80
+#define RL78_PSW_Z 0x40
+#define RL78_PSW_RBS1 0x20
+#define RL78_PSW_AC 0x10
+#define RL78_PSW_RBS0 0x08
+#define RL78_PSW_ISP1 0x04
+#define RL78_PSW_ISP0 0x02
+#define RL78_PSW_CY 0x01
+
+#define RL78_SFR_SP 0xffff8
+#define RL78_SFR_PSW 0xffffa
+#define RL78_SFR_CS 0xffffc
+#define RL78_SFR_ES 0xffffd
+#define RL78_SFR_PMC 0xffffe
+#define RL78_SFR_MEM 0xfffff
+
+typedef struct
+{
+ int lineno;
+ RL78_Opcode_ID id:24;
+ unsigned flags:8; /* PSW mask, for side effects only */
+ int n_bytes;
+ char * syntax;
+ RL78_Size size;
+ /* By convention, these are destination, source. */
+ RL78_Opcode_Operand op[2];
+} RL78_Opcode_Decoded;
+
+int rl78_decode_opcode (unsigned long, RL78_Opcode_Decoded *, int (*)(void *), void *);
+
+#endif
diff --git a/binutils-2.22/include/opcode/sparc.h b/binutils-2.22/include/opcode/sparc.h
index 7ae3641..b1c5e42 100644
--- a/binutils-2.22/include/opcode/sparc.h
+++ b/binutils-2.22/include/opcode/sparc.h
@@ -99,6 +99,7 @@ typedef struct sparc_opcode
const char *args;
/* This was called "delayed" in versions before the flags. */
unsigned int flags;
+ unsigned int hwcaps;
short architecture; /* Bitmask of sparc_opcode_arch_val's. */
} sparc_opcode;
@@ -110,25 +111,39 @@ typedef struct sparc_opcode
#define F_JSR 0x00000010 /* Subroutine call. */
#define F_FLOAT 0x00000020 /* Floating point instruction (not a branch). */
#define F_FBR 0x00000040 /* Floating point branch. */
-#define F_MUL32 0x00000100 /* umul/umulcc/smul/smulcc insns */
-#define F_DIV32 0x00000200 /* udiv/udivcc/sdiv/sdivcc insns */
-#define F_FSMULD 0x00000400 /* 'fsmuld' insn */
-#define F_V8PLUS 0x00000800 /* v9 insns available to 32bit */
-#define F_POPC 0x00001000 /* 'popc' insn */
-#define F_VIS 0x00002000 /* VIS insns */
-#define F_VIS2 0x00004000 /* VIS2 insns */
-#define F_ASI_BLK_INIT 0x00008000 /* block init ASIs */
-#define F_FMAF 0x00010000 /* fused multiply-add */
-#define F_VIS3 0x00020000 /* VIS3 insns */
-#define F_HPC 0x00040000 /* HPC insns */
-#define F_RANDOM 0x00080000 /* 'random' insn */
-#define F_TRANS 0x00100000 /* transaction insns */
-#define F_FJFMAU 0x00200000 /* unfused multiply-add */
-#define F_IMA 0x00400000 /* integer multiply-add */
-#define F_ASI_CACHE_SPARING \
- 0x00800000 /* cache sparing ASIs */
-
-#define F_HWCAP_MASK 0x00ffff00
+
+/* These must match the HWCAP_* values precisely. */
+#define HWCAP_MUL32 0x00000001 /* umul/umulcc/smul/smulcc insns */
+#define HWCAP_DIV32 0x00000002 /* udiv/udivcc/sdiv/sdivcc insns */
+#define HWCAP_FSMULD 0x00000004 /* 'fsmuld' insn */
+#define HWCAP_V8PLUS 0x00000008 /* v9 insns available to 32bit */
+#define HWCAP_POPC 0x00000010 /* 'popc' insn */
+#define HWCAP_VIS 0x00000020 /* VIS insns */
+#define HWCAP_VIS2 0x00000040 /* VIS2 insns */
+#define HWCAP_ASI_BLK_INIT \
+ 0x00000080 /* block init ASIs */
+#define HWCAP_FMAF 0x00000100 /* fused multiply-add */
+#define HWCAP_VIS3 0x00000400 /* VIS3 insns */
+#define HWCAP_HPC 0x00000800 /* HPC insns */
+#define HWCAP_RANDOM 0x00001000 /* 'random' insn */
+#define HWCAP_TRANS 0x00002000 /* transaction insns */
+#define HWCAP_FJFMAU 0x00004000 /* unfused multiply-add */
+#define HWCAP_IMA 0x00008000 /* integer multiply-add */
+#define HWCAP_ASI_CACHE_SPARING \
+ 0x00010000 /* cache sparing ASIs */
+#define HWCAP_AES 0x00020000 /* AES crypto insns */
+#define HWCAP_DES 0x00040000 /* DES crypto insns */
+#define HWCAP_KASUMI 0x00080000 /* KASUMI crypto insns */
+#define HWCAP_CAMELLIA 0x00100000 /* CAMELLIA crypto insns */
+#define HWCAP_MD5 0x00200000 /* MD5 hashing insns */
+#define HWCAP_SHA1 0x00400000 /* SHA1 hashing insns */
+#define HWCAP_SHA256 0x00800000 /* SHA256 hashing insns */
+#define HWCAP_SHA512 0x01000000 /* SHA512 hashing insns */
+#define HWCAP_MPMUL 0x02000000 /* Multiple Precision Multiply */
+#define HWCAP_MONT 0x04000000 /* Montgomery Mult/Sqrt */
+#define HWCAP_PAUSE 0x08000000 /* Pause insn */
+#define HWCAP_CBCOND 0x10000000 /* Compare and Branch insns */
+#define HWCAP_CRC32C 0x20000000 /* CRC32C insn */
/* All sparc opcodes are 32 bits, except for the `set' instruction (really a
macro), which is 64 bits. It is handled as a special case.
@@ -208,7 +223,9 @@ typedef struct sparc_opcode
0 32/64 bit immediate for set or setx (v9) insns
_ Ancillary state register in rd (v9a)
/ Ancillary state register in rs1 (v9a)
- ( entire floating point state register (%efsr). */
+ ( entire floating point state register (%efsr)
+ ) 5 bit immediate placed in RS3 field
+ = 2+8 bit PC relative immediate. (v9) */
#define OP2(x) (((x) & 0x7) << 22) /* Op2 field of format2 insns. */
#define OP3(x) (((x) & 0x3f) << 19) /* Op3 field of format3 insns. */
diff --git a/binutils-2.22/include/opcode/tilegx.h b/binutils-2.22/include/opcode/tilegx.h
index 95a9ca7..c11fc16 100644
--- a/binutils-2.22/include/opcode/tilegx.h
+++ b/binutils-2.22/include/opcode/tilegx.h
@@ -34,6 +34,8 @@ typedef enum
TILEGX_OPC_BPT,
TILEGX_OPC_INFO,
TILEGX_OPC_INFOL,
+ TILEGX_OPC_LD4S_TLS,
+ TILEGX_OPC_LD_TLS,
TILEGX_OPC_MOVE,
TILEGX_OPC_MOVEI,
TILEGX_OPC_MOVELI,
diff --git a/binutils-2.22/include/opcode/tilepro.h b/binutils-2.22/include/opcode/tilepro.h
index 91e2a2b..767926b 100644
--- a/binutils-2.22/include/opcode/tilepro.h
+++ b/binutils-2.22/include/opcode/tilepro.h
@@ -36,6 +36,8 @@ typedef enum
TILEPRO_OPC_INFOL,
TILEPRO_OPC_J,
TILEPRO_OPC_JAL,
+ TILEPRO_OPC_LW_TLS,
+ TILEPRO_OPC_LW_TLS_SN,
TILEPRO_OPC_MOVE,
TILEPRO_OPC_MOVE_SN,
TILEPRO_OPC_MOVEI,
diff --git a/binutils-2.22/include/opcode/xgate.h b/binutils-2.22/include/opcode/xgate.h
new file mode 100644
index 0000000..77a521f
--- /dev/null
+++ b/binutils-2.22/include/opcode/xgate.h
@@ -0,0 +1,120 @@
+/* xgate.h -- Freescale XGATE opcode list
+ Copyright 2010, 2011, 2012 Free Software Foundation, Inc.
+ Written by Sean Keys (skeys@ipdatasys.com)
+
+ This file is part of the GNU opcodes library.
+
+ This library is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3, or (at your option)
+ any later version.
+
+ It is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this file; see the file COPYING. If not, write to the
+ Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
+ MA 02110-1301, USA. */
+
+#ifndef _OPCODE_XGATE_H
+#define _OPCODE_XGATE_H
+
+/* XGATE CCR flag definitions. */
+#define XGATE_N_BIT 0x08 /* XGN - Sign Flag */
+#define XGATE_Z_BIT 0x04 /* XGZ - Zero Flag */
+#define XGATE_V_BIT 0x02 /* XGV - Overflow Flag */
+#define XGATE_C_BIT 0x01 /* XGC - Carry Flag */
+
+/* Access Detail Notation
+ V — Vector fetch: always an aligned word read, lasts for at least one RISC core cycle
+ P — Program word fetch: always an aligned word read, lasts for at least one RISC core cycle
+ r — 8-bit data read: lasts for at least one RISC core cycle
+ R — 16-bit data read: lasts for at least one RISC core cycle
+ w — 8-bit data write: lasts for at least one RISC core cycle
+ W — 16-bit data write: lasts for at least one RISC core cycle
+ A — Alignment cycle: no read or write, lasts for zero or one RISC core cycles
+ f — Free cycle: no read or write, lasts for one RISC core cycles. */
+#define XGATE_CYCLE_V 0x01
+#define XGATE_CYCLE_P 0x02
+#define XGATE_CYCLE_r 0x04
+#define XGATE_CYCLE_R 0x08
+#define XGATE_CYCLE_w 0x10
+#define XGATE_CYCLE_W 0x20
+#define XGATE_CYCLE_A 0x40
+#define XGATE_CYCLE_f 0x80
+
+/* Opcode format abbreviations. */
+#define XG_INH 0x0001 /* Inherent. */
+#define XG_I 0x0002 /* 3-bit immediate address. */
+#define XG_R_I 0x0004 /* Register followed by 4/8-bit immediate value. */
+#define XG_R_R 0x0008 /* Register followed by a register. */
+#define XG_R_R_R 0x0010 /* Register followed by two registers. */
+#define XG_R 0x0020 /* Single register. */
+#define XG_PC 0x0040 /* PC relative 10 or 11 bit. */
+#define XG_R_C 0x0080 /* General register followed by ccr register. */
+#define XG_C_R 0x0100 /* CCR register followed by a general register. */
+#define XG_R_P 0x0200 /* General register followed by pc register. */
+#define XG_R_R_I 0x0400 /* Two general registers followed by an immediate value. */
+#define XG_PCREL 0x0800 /* Immediate value that is relative to the current pc. */
+
+/* XGATE operand formats as stored in the XGATE_opcode table.
+ They are only used by GAS to recognize operands. */
+#define XGATE_OP_INH ""
+#define XGATE_OP_TRI "r,r,r"
+#define XGATE_OP_DYA "r,r"
+#define XGATE_OP_IMM16 "r,if"
+#define XGATE_OP_IMM8 "r,i8"
+#define XGATE_OP_IMM4 "r,i4"
+#define XGATE_OP_IMM3 "i3"
+#define XGATE_OP_MON "r"
+#define XGATE_OP_MON_R_C "r,c"
+#define XGATE_OP_MON_C_R "c,r"
+#define XGATE_OP_MON_R_P "r,p"
+#define XGATE_OP_IDR "r,r,+"
+#define XGATE_OP_IDO5 "r,r,i5"
+#define XGATE_OP_REL9 "b9"
+#define XGATE_OP_REL10 "ba"
+#define XGATE_OP_DYA_MON "=r"
+/* Macro definitions. */
+#define XGATE_OP_IMM16mADD "r,if; addl addh"
+#define XGATE_OP_IMM16mAND "r,if; andl andh"
+#define XGATE_OP_IMM16mCPC "r,if; cmpl cpch"
+#define XGATE_OP_IMM16mSUB "r,if; subl subh"
+#define XGATE_OP_IMM16mLDW "r,if; ldl ldh"
+
+/* CPU variant identification. */
+#define XGATE_V1 0x1
+#define XGATE_V2 0x2
+#define XGATE_V3 0x4
+
+/* Max opcodes per opcode handle. */
+#define MAX_OPCODES 0x05
+
+#define MAX_DETECT_CHARS 0x10
+
+/* The opcode table definitions. */
+struct xgate_opcode
+{
+ char * name; /* Op-code name. */
+ char * constraints; /* Constraint chars. */
+ char * format; /* Bit definitions. */
+ unsigned int sh_format; /* Shorthand format mask. */
+ unsigned int size; /* Opcode size in bytes. */
+ unsigned int bin_opcode; /* Binary opcode with operands masked off. */
+ unsigned char cycles_min; /* Minimum cpu cycles needed. */
+ unsigned char cycles_max; /* Maximum cpu cycles needed. */
+ unsigned char set_flags_mask; /* CCR flags set. */
+ unsigned char clr_flags_mask; /* CCR flags cleared. */
+ unsigned char chg_flags_mask; /* CCR flags changed. */
+ unsigned char arch; /* CPU variant. */
+};
+
+/* The opcode table. The table contains all the opcodes (all pages).
+ You can't rely on the order. */
+extern const struct xgate_opcode xgate_opcodes[];
+extern const int xgate_num_opcodes;
+
+#endif /* _OPCODE_XGATE_H */
generated by cgit v1.1 at 2025-08-22 07:40:07 +0000