diff options
Diffstat (limited to 'binutils-2.24')
| -rw-r--r-- | binutils-2.24/gas/testsuite/gas/mips/mxu.d | 6 | ||||
| -rw-r--r-- | binutils-2.24/gas/testsuite/gas/mips/mxu.s | 6 | ||||
| -rw-r--r-- | binutils-2.24/opcodes/mips-opc.c | 6 |
3 files changed, 18 insertions, 0 deletions
diff --git a/binutils-2.24/gas/testsuite/gas/mips/mxu.d b/binutils-2.24/gas/testsuite/gas/mips/mxu.d index 926ddaf..99b34ba 100644 --- a/binutils-2.24/gas/testsuite/gas/mips/mxu.d +++ b/binutils-2.24/gas/testsuite/gas/mips/mxu.d @@ -8,6 +8,12 @@ Disassembly of section \.text: [0-9a-f]+ <[^>]*> 44021002 mfc1 v0,\$f2 [0-9a-f]+ <[^>]*> 44020802 mfc1 v0,\$f1 +[0-9a-f]+ <[^>]*> 44821002 mtc1 v0,\$f2 +[0-9a-f]+ <[^>]*> 44820802 mtc1 v0,\$f1 +[0-9a-f]+ <[^>]*> 44621002 mfhc1 v0,\$f2 +[0-9a-f]+ <[^>]*> 44621002 mfhc1 v0,\$f2 +[0-9a-f]+ <[^>]*> 44e21002 mthc1 v0,\$f2 +[0-9a-f]+ <[^>]*> 44e21002 mthc1 v0,\$f2 [0-9a-f]+ <[^>]*> 7010c84a d16mac xr1,xr2,xr3,xr4,AA,WW [0-9a-f]+ <[^>]*> 7050c84a d16mac xr1,xr2,xr3,xr4,AA,LW [0-9a-f]+ <[^>]*> 7090c84a d16mac xr1,xr2,xr3,xr4,AA,HW diff --git a/binutils-2.24/gas/testsuite/gas/mips/mxu.s b/binutils-2.24/gas/testsuite/gas/mips/mxu.s index 8b56264..fd06e61 100644 --- a/binutils-2.24/gas/testsuite/gas/mips/mxu.s +++ b/binutils-2.24/gas/testsuite/gas/mips/mxu.s @@ -106,6 +106,12 @@ test_mxu: .endm mfc1 $2, $2 mfc1 $2, $f1 + mtc1 $2, $2 + mtc1 $2, $f1 + mfhc1 $2, $2 + mfhc1 $2, $f2 + mthc1 $2, $2 + mthc1 $2, $f2 test1 d16mac test1 d16macf test1 d16madl diff --git a/binutils-2.24/opcodes/mips-opc.c b/binutils-2.24/opcodes/mips-opc.c index 3a1302f..74ebae2 100644 --- a/binutils-2.24/opcodes/mips-opc.c +++ b/binutils-2.24/opcodes/mips-opc.c @@ -1444,6 +1444,8 @@ const struct mips_opcode mips_builtin_opcodes[] = {"mfc1", "t,G", 0x44000002, 0xffe007ff, WR_1|RD_2|LCD|FP_S|F32M,0, 0, MXU, 0 }, {"mfc1", "t,S", 0x44000000, 0xffe007ff, WR_1|RD_2|LCD|FP_S|F32M,0, I1, 0, 0 }, {"mfc1", "t,G", 0x44000000, 0xffe007ff, WR_1|RD_2|LCD|FP_S|F32M,0, I1, 0, 0 }, +{"mfhc1", "t,S", 0x44600002, 0xffe007ff, WR_1|RD_2|LCD|FP_D, 0, 0, MXU, 0 }, +{"mfhc1", "t,G", 0x44600002, 0xffe007ff, WR_1|RD_2|LCD|FP_D, 0, 0, MXU, 0 }, {"mfhc1", "t,S", 0x44600000, 0xffe007ff, WR_1|RD_2|LCD|FP_D, 0, I33, 0, 0 }, {"mfhc1", "t,G", 0x44600000, 0xffe007ff, WR_1|RD_2|LCD|FP_D, 0, I33, 0, 0 }, /* mfc2 is at the bottom of the table. */ @@ -1540,8 +1542,12 @@ const struct mips_opcode mips_builtin_opcodes[] = {"mthc0", "t,G,H", 0x40c00000, 0xffe007f8, RD_1|WR_C0|WR_CC|COD, 0, I33, XPA, 0 }, {"mthgc0", "t,G", 0x40600600, 0xffe007ff, RD_1|WR_C0|WR_CC|COD, 0, I33, IVIRT|XPA, 0 }, {"mthgc0", "t,G,H", 0x40600600, 0xffe007f8, RD_1|WR_C0|WR_CC|COD, 0, I33, IVIRT|XPA, 0 }, +{"mtc1", "t,S", 0x44800002, 0xffe007ff, RD_1|WR_2|COD|FP_S|F32M,0, 0, MXU, 0 }, +{"mtc1", "t,G", 0x44800002, 0xffe007ff, RD_1|WR_2|COD|FP_S|F32M,0, 0, MXU, 0 }, {"mtc1", "t,S", 0x44800000, 0xffe007ff, RD_1|WR_2|COD|FP_S|F32M,0, I1, 0, 0 }, {"mtc1", "t,G", 0x44800000, 0xffe007ff, RD_1|WR_2|COD|FP_S|F32M,0, I1, 0, 0 }, +{"mthc1", "t,S", 0x44e00002, 0xffe007ff, RD_1|WR_2|COD|FP_D, 0, 0, MXU, 0 }, +{"mthc1", "t,G", 0x44e00002, 0xffe007ff, RD_1|WR_2|COD|FP_D, 0, 0, MXU, 0 }, {"mthc1", "t,S", 0x44e00000, 0xffe007ff, RD_1|WR_2|COD|FP_D, 0, I33, 0, 0 }, {"mthc1", "t,G", 0x44e00000, 0xffe007ff, RD_1|WR_2|COD|FP_D, 0, I33, 0, 0 }, /* mtc2 is at the bottom of the table. */ |