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authorStefan Roese <sr@denx.de>2008-04-08 10:33:29 +0200
committerStefan Roese <sr@denx.de>2008-04-18 16:30:49 +0200
commit499e7831e1baaac6bfb959213f1950c216fbc5ba (patch)
tree4466db197406c088d09b51996913276dc9c7a100
parent5e182dce04d68cc94407a1b1fa09307f2bb96719 (diff)
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ppc4xx: Change Canyonlands to support booting from 2k page NAND devices
Signed-off-by: Stefan Roese <sr@denx.de>
-rw-r--r--board/amcc/canyonlands/bootstrap.c13
-rw-r--r--board/amcc/canyonlands/init.S1
-rw-r--r--board/amcc/canyonlands/u-boot-nand.lds4
-rw-r--r--include/configs/canyonlands.h26
-rw-r--r--nand_spl/board/amcc/canyonlands/config.mk6
5 files changed, 35 insertions, 15 deletions
diff --git a/board/amcc/canyonlands/bootstrap.c b/board/amcc/canyonlands/bootstrap.c
index 37fa1c9..1d125b6 100644
--- a/board/amcc/canyonlands/bootstrap.c
+++ b/board/amcc/canyonlands/bootstrap.c
@@ -63,9 +63,22 @@ static u8 boot_configs[][17] = {
/*
* Bytes 5,6,8,9,11 change for NAND boot
*/
+#if 0
+/*
+ * Values for 512 page size NAND chips, not used anymore, just
+ * keep them here for reference
+ */
static u8 nand_boot[] = {
0x90, 0x01, 0xa0, 0x68, 0x58
};
+#else
+/*
+ * Values for 2k page size NAND chips
+ */
+static u8 nand_boot[] = {
+ 0x90, 0x01, 0xa0, 0xe8, 0x58
+};
+#endif
static int do_bootstrap(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
diff --git a/board/amcc/canyonlands/init.S b/board/amcc/canyonlands/init.S
index bd4cab5..258fb5d 100644
--- a/board/amcc/canyonlands/init.S
+++ b/board/amcc/canyonlands/init.S
@@ -51,6 +51,7 @@ tlbtab:
#else
tlbentry(CFG_NAND_BOOT_SPL_SRC, SZ_4K, CFG_NAND_BOOT_SPL_SRC, 4, AC_R|AC_W|AC_X|SA_G)
tlbentry(CFG_SDRAM_BASE, SZ_256M, CFG_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G|SA_I)
+ tlbentry(256 << 20, SZ_256M, 256 << 20, 0, AC_R|AC_W|AC_X|SA_G|SA_I)
#endif
/*
diff --git a/board/amcc/canyonlands/u-boot-nand.lds b/board/amcc/canyonlands/u-boot-nand.lds
index f0837d4..332e3aa 100644
--- a/board/amcc/canyonlands/u-boot-nand.lds
+++ b/board/amcc/canyonlands/u-boot-nand.lds
@@ -56,10 +56,10 @@ SECTIONS
cpu/ppc4xx/start.o (.text)
/* Align to next NAND block */
- . = ALIGN(0x4000);
+ . = ALIGN(0x20000);
common/environment.o (.ppcenv)
/* Keep some space here for redundant env and potential bad env blocks */
- . = ALIGN(0x10000);
+ . = ALIGN(0x80000);
*(.text)
*(.fixup)
diff --git a/include/configs/canyonlands.h b/include/configs/canyonlands.h
index be9432b..e7896aa 100644
--- a/include/configs/canyonlands.h
+++ b/include/configs/canyonlands.h
@@ -141,6 +141,9 @@
* On 440EPx the SPL is copied to SDRAM before the NAND controller is
* set up. While still running from cache, I experienced problems accessing
* the NAND controller. sr - 2006-08-25
+ *
+ * This is the first official implementation of booting from 2k page sized
+ * NAND devices (e.g. Micron 29F2G08AA 256Mbit * 8)
*/
#define CFG_NAND_BOOT_SPL_SRC 0xfffff000 /* SPL location */
#define CFG_NAND_BOOT_SPL_SIZE (4 << 10) /* SPL size */
@@ -153,24 +156,27 @@
/*
* Define the partitioning of the NAND chip (only RAM U-Boot is needed here)
*/
-#define CFG_NAND_U_BOOT_OFFS (16 << 10) /* Offset to RAM U-Boot image */
-#define CFG_NAND_U_BOOT_SIZE (384 << 10) /* Size of RAM U-Boot image */
+#define CFG_NAND_U_BOOT_OFFS (128 << 10) /* Offset to RAM U-Boot image */
+#define CFG_NAND_U_BOOT_SIZE (1 << 20) /* Size of RAM U-Boot image */
/*
* Now the NAND chip has to be defined (no autodetection used!)
*/
-#define CFG_NAND_PAGE_SIZE 512 /* NAND chip page size */
-#define CFG_NAND_BLOCK_SIZE (16 << 10) /* NAND chip block size */
-#define CFG_NAND_PAGE_COUNT 32 /* NAND chip page count */
-#define CFG_NAND_BAD_BLOCK_POS 5 /* Location of bad block marker */
-#undef CFG_NAND_4_ADDR_CYCLE /* No fourth addr used (<=32MB) */
+#define CFG_NAND_PAGE_SIZE (2 << 10) /* NAND chip page size */
+#define CFG_NAND_BLOCK_SIZE (128 << 10) /* NAND chip block size */
+#define CFG_NAND_PAGE_COUNT (CFG_NAND_BLOCK_SIZE / CFG_NAND_PAGE_SIZE)
+ /* NAND chip page count */
+#define CFG_NAND_BAD_BLOCK_POS 0 /* Location of bad block marker*/
+#define CFG_NAND_5_ADDR_CYCLE /* Fifth addr used (<=128MB) */
#define CFG_NAND_ECCSIZE 256
#define CFG_NAND_ECCBYTES 3
#define CFG_NAND_ECCSTEPS (CFG_NAND_PAGE_SIZE / CFG_NAND_ECCSIZE)
-#define CFG_NAND_OOBSIZE 16
+#define CFG_NAND_OOBSIZE 64
#define CFG_NAND_ECCTOTAL (CFG_NAND_ECCBYTES * CFG_NAND_ECCSTEPS)
-#define CFG_NAND_ECCPOS {0, 1, 2, 3, 6, 7}
+#define CFG_NAND_ECCPOS {40, 41, 42, 43, 44, 45, 46, 47, \
+ 48, 49, 50, 51, 52, 53, 54, 55, \
+ 56, 57, 58, 59, 60, 61, 62, 63}
#ifdef CFG_ENV_IS_IN_NAND
/*
@@ -231,7 +237,7 @@
#define CONFIG_DDR_ECC 1 /* with ECC support */
#define CONFIG_DDR_RQDC_FIXED 0x80000038 /* fixed value for RQDC */
#endif
-#define CFG_MBYTES_SDRAM 256 /* 256MB */
+#define CFG_MBYTES_SDRAM 512 /* 512MB */
/*-----------------------------------------------------------------------
* I2C
diff --git a/nand_spl/board/amcc/canyonlands/config.mk b/nand_spl/board/amcc/canyonlands/config.mk
index 6dad876..c8d7c23 100644
--- a/nand_spl/board/amcc/canyonlands/config.mk
+++ b/nand_spl/board/amcc/canyonlands/config.mk
@@ -34,9 +34,9 @@
#
TEXT_BASE = 0xE3003000
-# PAD_TO used to generate a 16kByte binary needed for the combined image
-# -> PAD_TO = TEXT_BASE + 0x4000
-PAD_TO = 0xE3007000
+# PAD_TO used to generate a 128kByte binary needed for the combined image
+# -> PAD_TO = TEXT_BASE + 0x20000
+PAD_TO = 0xE3023000
PLATFORM_CPPFLAGS += -DCONFIG_440=1