ColdFire: Add M5253DEMO platform support for MCF5253

Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>

9 files changed, 1077 insertions, 0 deletions

diff --git a/MAINTAINERS b/MAINTAINERS
index 7efef6a..323a3a6 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -698,6 +698,7 @@ TsiChung Liew <Tsi-Chung.Liew@freescale.com>
 
 	M52277EVB	mcf5227x
 	M5235EVB	mcf52x2
+	M5253DEMO	mcf52x2
 	M5329EVB	mcf532x
 	M5373EVB	mcf532x
 	M54455EVB	mcf5445x
diff --git a/MAKEALL b/MAKEALL
index ac4195f..8788210 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -694,6 +694,7 @@ LIST_coldfire="			\
 	M52277EVB		\
 	M5235EVB		\
 	M5249EVB		\
+	M5253DEMO		\
 	M5253EVBE		\
 	M5271EVB		\
 	M5272C3			\
diff --git a/Makefile b/Makefile
index a384d16..d802b03 100644
--- a/Makefile
+++ b/Makefile
@@ -1851,6 +1851,9 @@ M5235EVB_Flash32_config:	unconfig
 M5249EVB_config :		unconfig
 	@$(MKCONFIG) $(@:_config=) m68k mcf52x2 m5249evb freescale
 
+M5253DEMO_config :		unconfig
+	@$(MKCONFIG) $(@:_config=) m68k mcf52x2 m5253demo freescale
+
 M5253EVBE_config :		unconfig
 	@$(MKCONFIG) $(@:_config=) m68k mcf52x2 m5253evbe freescale
 
diff --git a/board/freescale/m5253demo/Makefile b/board/freescale/m5253demo/Makefile
new file mode 100644
index 0000000..cf07cf4
--- /dev/null
+++ b/board/freescale/m5253demo/Makefile
@@ -0,0 +1,44 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS	= $(BOARD).o flash.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/freescale/m5253demo/config.mk b/board/freescale/m5253demo/config.mk
new file mode 100644
index 0000000..fa66b75
--- /dev/null
+++ b/board/freescale/m5253demo/config.mk
@@ -0,0 +1,25 @@
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+TEXT_BASE = 0xFF800000
diff --git a/board/freescale/m5253demo/flash.c b/board/freescale/m5253demo/flash.c
new file mode 100644
index 0000000..1bf1e97
--- /dev/null
+++ b/board/freescale/m5253demo/flash.c
@@ -0,0 +1,467 @@
+/*
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#include <asm/immap.h>
+
+#ifndef CFG_FLASH_CFI
+typedef unsigned short FLASH_PORT_WIDTH;
+typedef volatile unsigned short FLASH_PORT_WIDTHV;
+
+#define FPW             FLASH_PORT_WIDTH
+#define FPWV            FLASH_PORT_WIDTHV
+
+#define FLASH_CYCLE1    0x5555
+#define FLASH_CYCLE2    0x2aaa
+
+#define SYNC			__asm__("nop")
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+
+ulong flash_get_size(FPWV * addr, flash_info_t * info);
+int flash_get_offsets(ulong base, flash_info_t * info);
+int write_word(flash_info_t * info, FPWV * dest, u16 data);
+void inline spin_wheel(void);
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+
+ulong flash_init(void)
+{
+	ulong size = 0;
+	ulong fbase = 0;
+
+	fbase = (ulong) CFG_FLASH_BASE;
+	flash_get_size((FPWV *) fbase, &flash_info[0]);
+	flash_get_offsets((ulong) fbase, &flash_info[0]);
+	fbase += flash_info[0].size;
+	size += flash_info[0].size;
+
+	/* Protect monitor and environment sectors */
+	flash_protect(FLAG_PROTECT_SET,
+		      CFG_MONITOR_BASE,
+		      CFG_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0]);
+
+	return size;
+}
+
+int flash_get_offsets(ulong base, flash_info_t * info)
+{
+	int j, k;
+
+	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
+
+		info->start[0] = base;
+		for (k = 0, j = 0; j < CFG_SST_SECT; j++, k++) {
+			info->start[k + 1] = info->start[k] + CFG_SST_SECTSZ;
+			info->protect[k] = 0;
+		}
+	}
+
+	return ERR_OK;
+}
+
+void flash_print_info(flash_info_t * info)
+{
+	int i;
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_SST:
+		printf("SST ");
+		break;
+	default:
+		printf("Unknown Vendor ");
+		break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_SST6401B:
+		printf("SST39VF6401B\n");
+		break;
+	default:
+		printf("Unknown Chip Type\n");
+		return;
+	}
+
+	if (info->size > 0x100000) {
+		int remainder;
+
+		printf("  Size: %ld", info->size >> 20);
+
+		remainder = (info->size % 0x100000);
+		if (remainder) {
+			remainder >>= 10;
+			remainder = (int)((float)
+					  (((float)remainder / (float)1024) *
+					   10000));
+			printf(".%d ", remainder);
+		}
+
+		printf("MB in %d Sectors\n", info->sector_count);
+	} else
+		printf("  Size: %ld KB in %d Sectors\n",
+		       info->size >> 10, info->sector_count);
+
+	printf("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf("\n   ");
+		printf(" %08lX%s",
+		       info->start[i], info->protect[i] ? " (RO)" : "     ");
+	}
+	printf("\n");
+}
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+ulong flash_get_size(FPWV * addr, flash_info_t * info)
+{
+	u16 value;
+
+	addr[FLASH_CYCLE1] = (FPWV) 0x00AA00AA;	/* for Atmel, Intel ignores this */
+	addr[FLASH_CYCLE2] = (FPWV) 0x00550055;	/* for Atmel, Intel ignores this */
+	addr[FLASH_CYCLE1] = (FPWV) 0x00900090;	/* selects Intel or Atmel */
+
+	switch (addr[0] & 0xffff) {
+	case (u8) SST_MANUFACT:
+		info->flash_id = FLASH_MAN_SST;
+		value = addr[1];
+		break;
+	default:
+		printf("Unknown Flash\n");
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+
+		*addr = (FPW) 0x00F000F0;
+		return (0);	/* no or unknown flash  */
+	}
+
+	switch (value) {
+	case (u16) SST_ID_xF6401B:
+		info->flash_id += FLASH_SST6401B;
+		break;
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		break;
+	}
+
+	info->sector_count = 0;
+	info->size = 0;
+	info->sector_count = CFG_SST_SECT;
+	info->size = CFG_SST_SECT * CFG_SST_SECTSZ;
+
+	/* reset ID mode */
+	*addr = (FPWV) 0x00F000F0;
+
+	if (info->sector_count > CFG_MAX_FLASH_SECT) {
+		printf("** ERROR: sector count %d > max (%d) **\n",
+		       info->sector_count, CFG_MAX_FLASH_SECT);
+		info->sector_count = CFG_MAX_FLASH_SECT;
+	}
+
+	return (info->size);
+}
+
+int flash_erase(flash_info_t * info, int s_first, int s_last)
+{
+	FPWV *addr;
+	int flag, prot, sect, count;
+	ulong type, start, last;
+	int rcode = 0, flashtype = 0;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN)
+			printf("- missing\n");
+		else
+			printf("- no sectors to erase\n");
+		return 1;
+	}
+
+	type = (info->flash_id & FLASH_VENDMASK);
+
+	switch (type) {
+	case FLASH_MAN_SST:
+		flashtype = 1;
+		break;
+	default:
+		type = (info->flash_id & FLASH_VENDMASK);
+		printf("Can't erase unknown flash type %08lx - aborted\n",
+		       info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot)
+		printf("- Warning: %d protected sectors will not be erased!\n",
+		       prot);
+	else
+		printf("\n");
+
+	flag = disable_interrupts();
+
+	start = get_timer(0);
+	last = start;
+
+	if ((s_last - s_first) == (CFG_SST_SECT - 1)) {
+		if (prot == 0) {
+			addr = (FPWV *) info->start[0];
+
+			addr[FLASH_CYCLE1] = 0x00AA;	/* unlock */
+			addr[FLASH_CYCLE2] = 0x0055;	/* unlock */
+			addr[FLASH_CYCLE1] = 0x0080;	/* erase mode */
+			addr[FLASH_CYCLE1] = 0x00AA;	/* unlock */
+			addr[FLASH_CYCLE2] = 0x0055;	/* unlock */
+			*addr = 0x0030;	/* erase chip */
+
+			count = 0;
+			start = get_timer(0);
+
+			while ((*addr & 0x0080) != 0x0080) {
+				if (count++ > 0x10000) {
+					spin_wheel();
+					count = 0;
+				}
+
+				if (get_timer(start) > CFG_FLASH_ERASE_TOUT) {
+					printf("Timeout\n");
+					*addr = 0x00F0;	/* reset to read mode */
+
+					return 1;
+				}
+			}
+
+			*addr = 0x00F0;	/* reset to read mode */
+
+			printf("\b. done\n");
+
+			if (flag)
+				enable_interrupts();
+
+			return 0;
+		} else if (prot == CFG_SST_SECT) {
+			return 1;
+		}
+	}
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+
+			addr = (FPWV *) (info->start[sect]);
+
+			printf(".");
+
+			/* arm simple, non interrupt dependent timer */
+			start = get_timer(0);
+
+			switch (flashtype) {
+			case 1:
+				{
+					FPWV *base;	/* first address in bank */
+
+					flag = disable_interrupts();
+
+					base = (FPWV *) (CFG_FLASH_BASE);	/* First sector */
+
+					base[FLASH_CYCLE1] = 0x00AA;	/* unlock */
+					base[FLASH_CYCLE2] = 0x0055;	/* unlock */
+					base[FLASH_CYCLE1] = 0x0080;	/* erase mode */
+					base[FLASH_CYCLE1] = 0x00AA;	/* unlock */
+					base[FLASH_CYCLE2] = 0x0055;	/* unlock */
+					*addr = 0x0050;	/* erase sector */
+
+					if (flag)
+						enable_interrupts();
+
+					while ((*addr & 0x0080) != 0x0080) {
+						if (get_timer(start) >
+						    CFG_FLASH_ERASE_TOUT) {
+							printf("Timeout\n");
+							*addr = 0x00F0;	/* reset to read mode */
+
+							rcode = 1;
+							break;
+						}
+					}
+
+					*addr = 0x00F0;	/* reset to read mode */
+					break;
+				}
+			}	/* switch (flashtype) */
+		}
+	}
+	printf(" done\n");
+
+	if (flag)
+		enable_interrupts();
+
+	return rcode;
+}
+
+int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	ulong wp, count;
+	u16 data;
+	int rc, port_width;
+
+	if (info->flash_id == FLASH_UNKNOWN)
+		return 4;
+
+	/* get lower word aligned address */
+	wp = addr;
+	port_width = sizeof(FPW);
+
+	/* handle unaligned start bytes */
+	if (wp & 1) {
+		data = *((FPWV *) wp);
+		data = (data << 8) | *src;
+
+		if ((rc = write_word(info, (FPWV *) wp, data)) != 0)
+			return (rc);
+
+		wp++;
+		cnt -= 1;
+		src++;
+	}
+
+	while (cnt >= 2) {
+		/*
+		 * handle word aligned part
+		 */
+		count = 0;
+		data = *((FPWV *) src);
+
+		if ((rc = write_word(info, (FPWV *) wp, data)) != 0)
+			return (rc);
+
+		wp += 2;
+		src += 2;
+		cnt -= 2;
+
+		if (count++ > 0x800) {
+			spin_wheel();
+			count = 0;
+		}
+	}
+	/* handle word aligned part */
+	if (cnt) {
+		/* handle word aligned part */
+		count = 0;
+		data = *((FPWV *) wp);
+
+		data = (data & 0x00FF) | (*src << 8);
+
+		if ((rc = write_word(info, (FPWV *) wp, data)) != 0)
+			return (rc);
+
+		wp++;
+		src++;
+		cnt -= 1;
+		if (count++ > 0x800) {
+			spin_wheel();
+			count = 0;
+		}
+	}
+
+	if (cnt == 0)
+		return ERR_OK;
+
+	return ERR_OK;
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash
+ * A word is 16 bits, whichever the bus width of the flash bank
+ * (not an individual chip) is.
+ *
+ * returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+int write_word(flash_info_t * info, FPWV * dest, u16 data)
+{
+	ulong start;
+	int flag;
+	int res = 0;		/* result, assume success */
+	FPWV *base;		/* first address in flash bank */
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*dest & (u8) data) != (u8) data) {
+		return (2);
+	}
+
+	base = (FPWV *) (CFG_FLASH_BASE);
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	base[FLASH_CYCLE1] = (u8) 0x00AA00AA;	/* unlock */
+	base[FLASH_CYCLE2] = (u8) 0x00550055;	/* unlock */
+	base[FLASH_CYCLE1] = (u8) 0x00A000A0;	/* selects program mode */
+
+	*dest = data;		/* start programming the data */
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	start = get_timer(0);
+
+	/* data polling for D7 */
+	while (res == 0
+	       && (*dest & (u8) 0x00800080) != (data & (u8) 0x00800080)) {
+		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+			*dest = (u8) 0x00F000F0;	/* reset bank */
+			res = 1;
+		}
+	}
+
+	*dest++ = (u8) 0x00F000F0;	/* reset bank */
+
+	return (res);
+}
+
+void inline spin_wheel(void)
+{
+	static int p = 0;
+	static char w[] = "\\/-";
+
+	printf("\010%c", w[p]);
+	(++p == 3) ? (p = 0) : 0;
+}
+
+#endif
diff --git a/board/freescale/m5253demo/m5253demo.c b/board/freescale/m5253demo/m5253demo.c
new file mode 100644
index 0000000..2eb6a04
--- /dev/null
+++ b/board/freescale/m5253demo/m5253demo.c
@@ -0,0 +1,140 @@
+/*
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Hayden Fraser (Hayden.Fraser@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/immap.h>
+
+int checkboard(void)
+{
+	puts("Board: ");
+	puts("Freescale MCF5253 DEMO\n");
+	return 0;
+};
+
+phys_size_t initdram(int board_type)
+{
+	u32 dramsize = 0;
+
+	/*
+	 * Check to see if the SDRAM has already been initialized
+	 * by a run control tool
+	 */
+	if (!(mbar_readLong(MCFSIM_DCR) & 0x8000)) {
+		u32 RC, temp;
+
+		RC = (CFG_CLK / 1000000) >> 1;
+		RC = (RC * 15) >> 4;
+
+		/* Initialize DRAM Control Register: DCR */
+		mbar_writeShort(MCFSIM_DCR, (0x8400 | RC));
+		__asm__("nop");
+
+		mbar_writeLong(MCFSIM_DACR0, 0x00003224);
+		__asm__("nop");
+
+		/* Initialize DMR0 */
+		dramsize = (CFG_SDRAM_SIZE << 20);
+		temp = (dramsize - 1) & 0xFFFC0000;
+		mbar_writeLong(MCFSIM_DMR0, temp | 1);
+		__asm__("nop");
+
+		mbar_writeLong(MCFSIM_DACR0, 0x0000322c);
+		__asm__("nop");
+
+		/* Write to this block to initiate precharge */
+		*(u32 *) (CFG_SDRAM_BASE) = 0xa5a5a5a5;
+		__asm__("nop");
+
+		/* Set RE bit in DACR */
+		mbar_writeLong(MCFSIM_DACR0,
+			       mbar_readLong(MCFSIM_DACR0) | 0x8000);
+		__asm__("nop");
+
+		/* Wait for at least 8 auto refresh cycles to occur */
+		udelay(500);
+
+		/* Finish the configuration by issuing the MRS */
+		mbar_writeLong(MCFSIM_DACR0,
+			       mbar_readLong(MCFSIM_DACR0) | 0x0040);
+		__asm__("nop");
+
+		*(u32 *) (CFG_SDRAM_BASE + 0x800) = 0xa5a5a5a5;
+	}
+
+	return dramsize;
+}
+
+int testdram(void)
+{
+	/* TODO: XXX XXX XXX */
+	printf("DRAM test not implemented!\n");
+
+	return (0);
+}
+
+#ifdef CONFIG_CMD_IDE
+#include <ata.h>
+int ide_preinit(void)
+{
+	return (0);
+}
+
+void ide_set_reset(int idereset)
+{
+	volatile atac_t *ata = (atac_t *) CFG_ATA_BASE_ADDR;
+	long period;
+	/*  t1,  t2,  t3,  t4,  t5,  t6,  t9, tRD,  tA */
+	int piotms[5][9] = { {70, 165, 60, 30, 50, 5, 20, 0, 35},	/* PIO 0 */
+	{50, 125, 45, 20, 35, 5, 15, 0, 35},	/* PIO 1 */
+	{30, 100, 30, 15, 20, 5, 10, 0, 35},	/* PIO 2 */
+	{30, 80, 30, 10, 20, 5, 10, 0, 35},	/* PIO 3 */
+	{25, 70, 20, 10, 20, 5, 10, 0, 35}	/* PIO 4 */
+	};
+
+	if (idereset) {
+		ata->cr = 0;	/* control reset */
+		udelay(100);
+	} else {
+		mbar2_writeLong(CIM_MISCCR, CIM_MISCCR_CPUEND);
+
+#define CALC_TIMING(t) (t + period - 1) / period
+		period = 1000000000 / (CFG_CLK / 2);	/* period in ns */
+
+		/*ata->ton = CALC_TIMING (180); */
+		ata->t1 = CALC_TIMING(piotms[2][0]);
+		ata->t2w = CALC_TIMING(piotms[2][1]);
+		ata->t2r = CALC_TIMING(piotms[2][1]);
+		ata->ta = CALC_TIMING(piotms[2][8]);
+		ata->trd = CALC_TIMING(piotms[2][7]);
+		ata->t4 = CALC_TIMING(piotms[2][3]);
+		ata->t9 = CALC_TIMING(piotms[2][6]);
+
+		ata->cr = 0x40;	/* IORDY enable */
+		udelay(2000);
+		ata->cr |= 0x01;	/* IORDY enable */
+	}
+}
+#endif				/* CONFIG_CMD_IDE */
diff --git a/board/freescale/m5253demo/u-boot.lds b/board/freescale/m5253demo/u-boot.lds
new file mode 100644
index 0000000..4bdea5e
--- /dev/null
+++ b/board/freescale/m5253demo/u-boot.lds
@@ -0,0 +1,144 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(m68k)
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)	}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)	}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)	}
+  .rela.got      : { *(.rela.got)	}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)	}
+  .rela.bss      : { *(.rela.bss)	}
+  .rel.plt       : { *(.rel.plt)	}
+  .rela.plt      : { *(.rela.plt)	}
+  .init          : { *(.init)		}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/mcf52x2/start.o		(.text)
+    lib_m68k/traps.o		(.text)
+    cpu/mcf52x2/interrupts.o	(.text)
+    common/dlmalloc.o		(.text)
+    lib_generic/zlib.o		(.text)
+
+    . = DEFINED(env_offset) ? env_offset : .;
+    common/environment.o	(.text)
+
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+
+  .reloc   :
+  {
+    __got_start = .;
+    *(.got)
+    __got_end = .;
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   _sbss = .;
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+   . = ALIGN(4);
+   _ebss = .;
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/include/configs/M5253DEMO.h b/include/configs/M5253DEMO.h
new file mode 100644
index 0000000..b91d7d6
--- /dev/null
+++ b/include/configs/M5253DEMO.h
@@ -0,0 +1,252 @@
+/*
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Hayden Fraser (Hayden.Fraser@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _M5253DEMO_H
+#define _M5253DEMO_H
+
+#define CONFIG_MCF52x2		/* define processor family */
+#define CONFIG_M5253		/* define processor type */
+#define CONFIG_M5253DEMO	/* define board type */
+
+#define CONFIG_MCFTMR
+
+#define CONFIG_MCFUART
+#define CFG_UART_PORT		(0)
+#define CONFIG_BAUDRATE		115200
+#define CFG_BAUDRATE_TABLE	{ 9600 , 19200 , 38400 , 57600, 115200 }
+
+#undef CONFIG_WATCHDOG		/* disable watchdog */
+
+#define CONFIG_BOOTDELAY	5
+
+/* Configuration for environment
+ * Environment is embedded in u-boot in the second sector of the flash
+ */
+#ifdef CONFIG_MONITOR_IS_IN_RAM
+#	define CFG_ENV_OFFSET		0x4000
+#	define CFG_ENV_SECT_SIZE	0x1000
+#	define CFG_ENV_IS_IN_FLASH	1
+#else
+#	define CFG_ENV_ADDR		(CFG_FLASH_BASE + 0x4000)
+#	define CFG_ENV_SECT_SIZE	0x1000
+#	define CFG_ENV_IS_IN_FLASH	1
+#endif
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_LOADB
+#define CONFIG_CMD_LOADS
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_MISC
+#define CONFIG_CMD_PING
+
+#ifdef CONFIG_CMD_IDE
+/* ATA */
+#	define CONFIG_DOS_PARTITION
+#	define CONFIG_MAC_PARTITION
+#	define CONFIG_IDE_RESET		1
+#	define CONFIG_IDE_PREINIT	1
+#	define CONFIG_ATAPI
+#	undef CONFIG_LBA48
+
+#	define CFG_IDE_MAXBUS		1
+#	define CFG_IDE_MAXDEVICE	2
+
+#	define CFG_ATA_BASE_ADDR	(CFG_MBAR2 + 0x800)
+#	define CFG_ATA_IDE0_OFFSET	0
+
+#	define CFG_ATA_DATA_OFFSET	0xA0	/* Offset for data I/O */
+#	define CFG_ATA_REG_OFFSET	0xA0	/* Offset for normal register accesses */
+#	define CFG_ATA_ALT_OFFSET	0xC0	/* Offset for alternate registers */
+#	define CFG_ATA_STRIDE		4	/* Interval between registers */
+#	define _IO_BASE			0
+#endif
+
+#define CONFIG_DRIVER_DM9000
+#ifdef CONFIG_DRIVER_DM9000
+#	define CONFIG_DM9000_BASE	((CFG_CSAR1 << 16) | 0x300)
+#	define DM9000_IO		CONFIG_DM9000_BASE
+#	define DM9000_DATA		(CONFIG_DM9000_BASE + 4)
+#	undef CONFIG_DM9000_DEBUG
+
+#	define CONFIG_ETHADDR		00:e0:0c:bc:e5:60
+#	define CONFIG_IPADDR		10.82.121.249
+#	define CONFIG_NETMASK		255.255.252.0
+#	define CONFIG_SERVERIP		10.82.120.80
+#	define CONFIG_GATEWAYIP		10.82.123.254
+#	define CONFIG_OVERWRITE_ETHADDR_ONCE
+
+#	define CONFIG_EXTRA_ENV_SETTINGS		\
+		"netdev=eth0\0"				\
+		"inpclk=" MK_STR(CFG_INPUT_CLKSRC) "\0"	\
+		"loadaddr=10000\0"			\
+		"u-boot=u-boot.bin\0"			\
+		"load=tftp ${loadaddr) ${u-boot}\0"	\
+		"upd=run load; run prog\0"		\
+		"prog=prot off 0 2ffff;"	\
+		"era 0 2ffff;"			\
+		"cp.b ${loadaddr} 0 ${filesize};"	\
+		"save\0"				\
+		""
+#endif
+
+#define CONFIG_HOSTNAME		M5253DEMO
+
+#define CFG_PROMPT		"=> "
+#define CFG_LONGHELP		/* undef to save memory */
+
+#if defined(CONFIG_CMD_KGDB)
+#	define CFG_CBSIZE		1024	/* Console I/O Buffer Size */
+#else
+#	define CFG_CBSIZE		256	/* Console I/O Buffer Size */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size */
+#define CFG_MAXARGS		16	/* max number of command args */
+#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size */
+
+#define CFG_LOAD_ADDR		0x00100000
+
+#define CFG_MEMTEST_START	0x400
+#define CFG_MEMTEST_END		0x380000
+
+#define CFG_HZ			1000
+
+#undef CFG_PLL_BYPASS		/* bypass PLL for test purpose */
+#define CFG_FAST_CLK
+#ifdef CFG_FAST_CLK
+#	define CFG_PLLCR	0x1243E054
+#	define CFG_CLK		140000000
+#else
+#	define CFG_PLLCR	0x135a4140
+#	define CFG_CLK		70000000
+#endif
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+
+#define CFG_MBAR		0x10000000	/* Register Base Addrs */
+#define CFG_MBAR2		0x80000000	/* Module Base Addrs 2 */
+
+/*
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR	0x20000000
+#define CFG_INIT_RAM_END	0x10000	/* End of used area in internal SRAM */
+#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/*
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE		0x00000000
+#define CFG_SDRAM_SIZE		16	/* SDRAM size in MB */
+
+#ifdef CONFIG_MONITOR_IS_IN_RAM
+#	define CFG_MONITOR_BASE	0x20000
+#else
+#	define CFG_MONITOR_BASE	(CFG_FLASH_BASE + 0x400)
+#endif
+
+#define CFG_MONITOR_LEN		0x40000
+#define CFG_MALLOC_LEN		(256 << 10)
+#define CFG_BOOTPARAMS_LEN	(64*1024)
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization ??
+ */
+#define CFG_BOOTMAPSZ		(CFG_SDRAM_BASE + (CFG_SDRAM_SIZE << 20))
+
+/* FLASH organization */
+#define CFG_FLASH_BASE		(CFG_CSAR0 << 16)
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks */
+#define CFG_MAX_FLASH_SECT	2048	/* max number of sectors on one chip */
+#define CFG_FLASH_ERASE_TOUT	1000
+
+#define FLASH_SST6401B		0x200
+#define SST_ID_xF6401B		0x236D236D
+
+#undef CFG_FLASH_CFI
+#ifdef CFG_FLASH_CFI
+/*
+ * Unable to use CFI driver, due to incompatible sector erase command by SST.
+ * Amd/Atmel use 0x30 for sector erase, SST use 0x50.
+ * 0x30 is block erase in SST
+ */
+#	define CFG_FLASH_CFI_DRIVER	1
+#	define CFG_FLASH_SIZE		0x800000
+#	define CFG_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
+#	define CONFIG_FLASH_CFI_LEGACY
+#else
+#	define CFG_SST_SECT		2048
+#	define CFG_SST_SECTSZ		0x1000
+#	define CFG_FLASH_WRITE_TOUT	500
+#endif
+
+/* Cache Configuration */
+#define CFG_CACHELINE_SIZE	16
+
+/* Port configuration */
+#define CFG_FECI2C		0xF0
+
+#define CFG_CSAR0		0xFF80
+#define CFG_CSMR0		0x007F0021
+#define CFG_CSCR0		0x1D80
+
+#define CFG_CSAR1               0xE000
+#define CFG_CSMR1               0x00000001
+#define CFG_CSCR1               0x3DD8
+
+#define CFG_CSAR2		0
+#define CFG_CSMR2		0
+#define CFG_CSCR2		0
+
+#define CFG_CSAR3		0
+#define CFG_CSMR3		0
+#define CFG_CSCR3		0
+
+/*-----------------------------------------------------------------------
+ * Port configuration
+ */
+#define CFG_GPIO_FUNC		0x00000008	/* Set gpio pins: none */
+#define CFG_GPIO1_FUNC		0x00df00f0	/* 36-39(SWITCH),48-52(FPGAs),54 */
+#define CFG_GPIO_EN		0x00000008	/* Set gpio output enable */
+#define CFG_GPIO1_EN		0x00c70000	/* Set gpio output enable */
+#define CFG_GPIO_OUT		0x00000008	/* Set outputs to default state */
+#define CFG_GPIO1_OUT		0x00c70000	/* Set outputs to default state */
+#define CFG_GPIO1_LED		0x00400000	/* user led */
+
+#endif				/* _M5253DEMO_H */