diff options
| author | Marian Balakowicz <m8@semihalf.com> | 2006-03-14 16:12:48 +0100 |
|---|---|---|
| committer | Marian Balakowicz <m8@semihalf.com> | 2006-03-14 16:12:48 +0100 |
| commit | 6d8ae5abb5311bd8e306a5a060dcfbeb0874a169 (patch) | |
| tree | 2eab4767461b8142b7cc24a96bb468dc07b8d8b5 | |
| parent | e24e0f0744f4d28d7642c88052b712e91dbbf203 (diff) | |
| download | bootable_bootloader_goldelico_gta04-6d8ae5abb5311bd8e306a5a060dcfbeb0874a169.zip bootable_bootloader_goldelico_gta04-6d8ae5abb5311bd8e306a5a060dcfbeb0874a169.tar.gz bootable_bootloader_goldelico_gta04-6d8ae5abb5311bd8e306a5a060dcfbeb0874a169.tar.bz2 | |
Add sync in do_reset() routine for MPC83xx after RPR register
was written to. It is need on some targets when BAT translation
is enabled.
| -rw-r--r-- | CHANGELOG | 4 | ||||
| -rw-r--r-- | cpu/mpc83xx/cpu.c | 2 |
2 files changed, 6 insertions, 0 deletions
@@ -2,6 +2,10 @@ Changes since U-Boot 1.1.4: ====================================================================== +* Add sync in do_reset() routine for MPC83xx after RPR register + was written to. It is need on some targets when BAT translation + is enabled. + * Add bit definitions for MPC83xx DDR controller registers. * Add Dcbz(), Dcbi() and Dcbf() routines for MPC83xx. diff --git a/cpu/mpc83xx/cpu.c b/cpu/mpc83xx/cpu.c index e49e4fe..63f8242 100644 --- a/cpu/mpc83xx/cpu.c +++ b/cpu/mpc83xx/cpu.c @@ -93,6 +93,8 @@ do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) /* enable Reset Control Reg */ immap->reset.rpr = 0x52535445; + __asm__ __volatile__ ("sync"); + __asm__ __volatile__ ("isync"); /* confirm Reset Control Reg is enabled */ while(!((immap->reset.rcer) & RCER_CRE)); |