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| author | Matthias Weisser <weisserm@arcor.de> | 2010-10-27 16:34:38 +0200 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2010-10-28 10:32:21 +0200 |
| commit | 81129d07a0e9f6e28029170b082d6f8810f72712 (patch) | |
| tree | b6c747f51a5ff896e3950d976cd4a0515668c896 | |
| parent | 95707aaa9ef2dd84649c257cdcf563641322c4d3 (diff) | |
| download | bootable_bootloader_goldelico_gta04-81129d07a0e9f6e28029170b082d6f8810f72712.zip bootable_bootloader_goldelico_gta04-81129d07a0e9f6e28029170b082d6f8810f72712.tar.gz bootable_bootloader_goldelico_gta04-81129d07a0e9f6e28029170b082d6f8810f72712.tar.bz2 | |
imx25: Fix reset
This patch fixes the reset command on imx25. The watchdog registers are 16
bits in size and not 32. This patch also adds the service register codes as
constants.
Signed-off-by: Matthias Weisser <weisserm@arcor.de>
| -rw-r--r-- | arch/arm/cpu/arm926ejs/mx25/reset.c | 8 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-mx25/imx-regs.h | 14 |
2 files changed, 12 insertions, 10 deletions
diff --git a/arch/arm/cpu/arm926ejs/mx25/reset.c b/arch/arm/cpu/arm926ejs/mx25/reset.c index 1e33150..1a43683 100644 --- a/arch/arm/cpu/arm926ejs/mx25/reset.c +++ b/arch/arm/cpu/arm926ejs/mx25/reset.c @@ -43,14 +43,14 @@ void reset_cpu (ulong ignored) { struct wdog_regs *regs = (struct wdog_regs *)IMX_WDT_BASE; /* Disable watchdog and set Time-Out field to 0 */ - writel (0x00000000, ®s->wcr); + writew(0, ®s->wcr); /* Write Service Sequence */ - writel (0x00005555, ®s->wsr); - writel (0x0000AAAA, ®s->wsr); + writew(WSR_UNLOCK1, ®s->wsr); + writew(WSR_UNLOCK2, ®s->wsr); /* Enable watchdog */ - writel (WCR_WDE, ®s->wcr); + writew(WCR_WDE, ®s->wcr); while (1) ; } diff --git a/arch/arm/include/asm/arch-mx25/imx-regs.h b/arch/arm/include/asm/arch-mx25/imx-regs.h index f709bd8..f5a2929 100644 --- a/arch/arm/include/asm/arch-mx25/imx-regs.h +++ b/arch/arm/include/asm/arch-mx25/imx-regs.h @@ -108,11 +108,11 @@ struct gpt_regs { /* Watchdog Timer (WDOG) registers */ struct wdog_regs { - u32 wcr; /* Control */ - u32 wsr; /* Service */ - u32 wrsr; /* Reset Status */ - u32 wicr; /* Interrupt Control */ - u32 wmcr; /* Misc Control */ + u16 wcr; /* Control */ + u16 wsr; /* Service */ + u16 wrsr; /* Reset Status */ + u16 wicr; /* Interrupt Control */ + u16 wmcr; /* Misc Control */ }; /* IIM control registers */ @@ -308,7 +308,9 @@ struct iim_regs { #define GPT_CTRL_TEN 1 /* Timer enable */ /* WDOG enable */ -#define WCR_WDE 0x04 +#define WCR_WDE 0x04 +#define WSR_UNLOCK1 0x5555 +#define WSR_UNLOCK2 0xAAAA /* FUSE bank offsets */ #define IIM0_MAC 0x1a |