diff options
| author | Graeme Russ <graeme.russ@gmail.com> | 2011-02-12 15:11:38 +1100 |
|---|---|---|
| committer | Graeme Russ <graeme.russ@gmail.com> | 2011-02-12 15:11:38 +1100 |
| commit | 870847f5c5709b623b0d094780a994312b8da5a5 (patch) | |
| tree | 517168f285825c926da3900d91a316cb0ed0045b | |
| parent | c2cbbaf0b4035f713f524b85b8f54fb7f7f3720d (diff) | |
| download | bootable_bootloader_goldelico_gta04-870847f5c5709b623b0d094780a994312b8da5a5.zip bootable_bootloader_goldelico_gta04-870847f5c5709b623b0d094780a994312b8da5a5.tar.gz bootable_bootloader_goldelico_gta04-870847f5c5709b623b0d094780a994312b8da5a5.tar.bz2 | |
sc520: Move board specific settings to board init function
| -rw-r--r-- | arch/i386/cpu/sc520/sc520.c | 19 | ||||
| -rw-r--r-- | board/eNET/eNET.c | 9 |
2 files changed, 9 insertions, 19 deletions
diff --git a/arch/i386/cpu/sc520/sc520.c b/arch/i386/cpu/sc520/sc520.c index 7caa4c8..19a678d 100644 --- a/arch/i386/cpu/sc520/sc520.c +++ b/arch/i386/cpu/sc520/sc520.c @@ -42,25 +42,6 @@ sc520_mmcr_t *sc520_mmcr = (sc520_mmcr_t *)SC520_MMCR_BASE; int cpu_init_f(void) { - /* - * Set the UARTxCTL register at it's slower, - * baud clock giving us a 1.8432 MHz reference - */ - writeb(0x07, &sc520_mmcr->uart1ctl); - writeb(0x07, &sc520_mmcr->uart2ctl); - - /* first set the timer pin mapping */ - writeb(0x72, &sc520_mmcr->clksel); /* no clock frequency selected, use 1.1892MHz */ - - /* enable PCI bus arbiter (concurrent mode) */ - writeb(0x02, &sc520_mmcr->sysarbctl); - - /* enable external grants */ - writeb(0x1f, &sc520_mmcr->sysarbmenb); - - /* enable posted-writes */ - writeb(0x04, &sc520_mmcr->hbctl); - if (CONFIG_SYS_SC520_HIGH_SPEED) { /* set it to 133 MHz and write back */ writeb(0x02, &sc520_mmcr->cpuctl); diff --git a/board/eNET/eNET.c b/board/eNET/eNET.c index 30d8750..b2f349f 100644 --- a/board/eNET/eNET.c +++ b/board/eNET/eNET.c @@ -94,12 +94,21 @@ int board_early_init_f(void) writew(0x0615, &sc520_mmcr->romcs1ctl); writew(0x0615, &sc520_mmcr->romcs2ctl); + /* + * Set the timer pin mapping + * no clock frequency selected, use 1.1892MHz + */ + writeb(0x72, &sc520_mmcr->clksel); + writeb(0x00, &sc520_mmcr->adddecctl); writeb(0x07, &sc520_mmcr->uart1ctl); writeb(0x07, &sc520_mmcr->uart2ctl); writeb(0x06, &sc520_mmcr->sysarbctl); writew(0x0003, &sc520_mmcr->sysarbmenb); + /* enable posted-writes */ + writeb(0x04, &sc520_mmcr->hbctl); + return 0; } |