Code cleanup.

1 files changed, 422 insertions, 0 deletions

diff --git a/CHANGELOG b/CHANGELOG
index 305cee8..b74f536 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -1,3 +1,9 @@
+commit 8d9a8610b8256331132227e9e6585c6bd5742787
+Author: Wolfgang Denk <wd@pollux.denx.de>
+Date:	Thu Nov 30 01:54:07 2006 +0100
+
+    Code cleanup. Update CHANGELOG.
+
 commit 726e90aacf0b1ecb0e7055be574622fbe3e450ba
 Author: Grant Likely <grant.likely@secretlab.ca>
 Date:	Wed Nov 29 16:23:42 2006 +0100
@@ -52,6 +58,49 @@ Date:	Wed Nov 29 12:03:57 2006 +0100
     Signed-off-by: Jeff Mann <mannj@embeddedplanet.com>
     Signed-off-by: Stefan Roese <sr@denx.de>
 
+commit 1939d969443ccf316cab2bf32ab1027d4db5ba1a
+Author: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
+Date:	Tue Nov 28 16:17:27 2006 -0600
+
+    Make fsl-i2c not conflict with SOFT I2C
+
+    Signed-off-by: Timur Tabi <timur@freescale.com>
+
+commit 14198bf768fdc958e3c1afd2404e5262208e98d7
+Author: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
+Date:	Tue Nov 28 16:17:18 2006 -0600
+
+    Fix I2C master address initialization.
+
+    Signed-off-by: Timur Tabi <timur@freescale.com>
+
+commit cf3d045e51ca8dcc6cf759827140861d6ac25c04
+Author: Kim Phillips <kim.phillips@freescale.com>
+Date:	Tue Nov 28 23:31:19 2006 -0600
+
+    Assign maintainers for mpc8349emds and mpc8360emds
+
+    Dave for mpc8360emds, and me for mpc8349emds.
+
+commit 1aa934c81b77f2080d3ca4b226eab67b17a33961
+Author: Kim Phillips <kim.phillips@freescale.com>
+Date:	Tue Nov 28 23:28:33 2006 -0600
+
+    Eliminate gcc 4 'used uninitialized' warnings in drivers/qe/uccf.c
+
+    give initial values for reg_num, shift, p_cmxucr in ucc_set_clk_src
+    since they are passed by reference to ucc_get_cmxucr_reg and assigned.
+
+commit e857a5bdb3954b896c0920cb9d8d2b1b9c107ce5
+Author: Timur Tabi <timur@freescale.com>
+Date:	Tue Nov 28 12:09:35 2006 -0600
+
+    mpc83xx: Miscellaneous code style fixes
+
+    Implement various code style fixes and similar changes.
+
+    Signed-off-by: Timur Tabi <timur@freescale.com>
+
 commit e59581c56ab5d6e0207ddac3b2c1d55cb36ec706
 Author: Stefan Roese <sr@denx.de>
 Date:	Tue Nov 28 17:55:49 2006 +0100
@@ -268,6 +317,379 @@ Date:	Mon Nov 6 17:06:36 2006 +0100
 
     This fixes get_ram_size() problems on MPC5200 Rev. B boards.
 
+commit be5e61815d5a1fac290ce9c0ef09cb6a8e4288fa
+Author: Timur Tabi <timur@freescale.com>
+Date:	Fri Nov 3 19:15:00 2006 -0600
+
+    mpc83xx: Update 83xx to use fsl_i2c.c
+
+    Update the 83xx tree to use I2C support in drivers/fsl_i2c.c.  Delete
+    cpu/mpc83xx/i2c.c, include/asm-ppc/i2c.h, and all references to those files.
+    Added multiple I2C bus support to fsl_i2c.c.
+
+    Signed-off-by: Timur Tabi <timur@freescale.com>
+
+commit d239d74b1c937984bc519083a8e7de373a390f06
+Author: Timur Tabi <timur@freescale.com>
+Date:	Fri Nov 3 12:00:28 2006 -0600
+
+    mpc83xx: Replace CFG_IMMRBAR with CFG_IMMR
+
+    Replace all instances of CFG_IMMRBAR with CFG_IMMR, so that the 83xx
+    tree matches the other 8xxx trees.
+
+    Signed-off-by: Timur Tabi <timur@freescale.com>
+
+commit f7fb2e703ec9688541416962724adff70a7322cb
+Author: Kim Phillips <kim.phillips@freescale.com>
+Date:	Thu Nov 2 19:47:11 2006 -0600
+
+    mpc83xx: Lindent and clean up cpu/mpc83xx/speed.c
+
+commit 90f30a710a3c619b5405860a686c4ddfc495d4b6
+Author: Dave Liu <daveliu@freescale.com>
+Date:	Thu Nov 2 18:05:50 2006 -0600
+
+    mpc83xx: Fix the incorrect dcbz operation
+
+    The 834x rev1.x silicon has one CPU5 errata.
+
+    The issue is when the data cache locked with
+    HID0[DLOCK], the dcbz instruction looks like no-op inst.
+
+    The right behavior of the data cache is when the data cache
+    Locked with HID0[DLOCK], the dcbz instruction allocates
+    new tags in cache.
+
+    The 834x rev3.0 and later and 8360 have not this bug inside.
+
+    So, when 834x rev3.0/8360 are working with ECC, the dcbz
+    instruction will corrupt the stack in cache, the processor will
+    checkstop reset.
+
+    However, the 834x rev1.x can work with ECC with these code,
+    because the sillicon has this cache bug. The dcbz will not
+    corrupt the stack in cache.
+    Really, it is the fault code running on fault sillicon.
+
+    This patch fix the incorrect dcbz operation. Instead of
+    CPU FP writing to initialise the ECC.
+
+    CHANGELOG:
+    * Fix the incorrect dcbz operation instead of CPU FP
+    writing to initialise the ECC memory. Otherwise, it
+    will corrupt the stack in cache, The processor will checkstop
+    reset.
+
+    Signed-off-by: Dave Liu <daveliu@freescale.com>
+
+commit bf0b542d6773a5a1cbce77691f009b06d9aeb57d
+Author: Kim Phillips <kim.phillips@freescale.com>
+Date:	Wed Nov 1 00:10:40 2006 -0600
+
+    mpc83xx: add OF_FLAT_TREE bits to 83xx boards
+
+    add ft_pci_setup, OF_CPU, OF_SOC, OF_TBCLK, and
+    STDOUT_PATH configuration bits to mpc8349emds,
+    mpc8349itx, and mpc8360emds board code.
+
+    redo environment to use bootm with the fdtaddr
+    for booting ARCH=powerpc kernels by default,
+    and provide default fdtaddr values.
+
+commit 48041365b3420589ad464ebc7752e0053538b729
+Author: Kim Phillips <kim.phillips@freescale.com>
+Date:	Wed Nov 1 00:07:25 2006 -0600
+
+    mpc83xx: change ft code to modify local-mac-address property
+
+    Update 83xx OF code to update local-mac-address properties
+    for ethernet instead of the obsolete 'address' property.
+
+commit 9ca880a250870a7d55754291b5591d2b5fe89b54
+Author: Timur Tabi <timur@freescale.com>
+Date:	Tue Oct 31 21:23:16 2006 -0600
+
+    mpc83xx: Fix dual I2C support for the MPC8349ITX, MPC8349EMDS, TQM834x, and MPC8360EMDS
+
+    This patch also adds an improved I2C set_speed(), which handles all clock
+    frequencies.
+
+    Signed-off-by: Timur Tabi <timur@freescale.com>
+
+commit ac4b5622ce050b5ee1e154b98df630d778661632
+Author: Dave Liu <daveliu@freescale.com>
+Date:	Tue Oct 31 19:54:59 2006 -0600
+
+    mpc83xx: add the README.mpc8360emds
+
+    add doc/README.mpc8360emds to accompany the new board support
+
+commit 7737d5c658c606f999dfbe3e86b0fed49e5c50ef
+Author: Dave Liu <daveliu@freescale.com>
+Date:	Fri Nov 3 12:11:15 2006 -0600
+
+    mpc83xx: add QE ethernet support
+
+    this patch adds support for the QUICC Engine based UCC gigabit ethernet device.
+
+commit 5f8204394e39bbe8cd9f08b8f8d145b6c01f7c73
+Author: Dave Liu <daveliu@freescale.com>
+Date:	Fri Nov 3 19:33:44 2006 -0600
+
+    mpc83xx: Add MPC8360EMDS basic board support
+
+    Add support for the Freescale MPC8360EMDS board.
+    Includes DDR, DUART, Local Bus, PCI.
+
+commit 23892e49352de74f7fac36ff90bb1be143d195e3
+Author: Dave Liu <daveliu@freescale.com>
+Date:	Tue Oct 31 19:30:40 2006 -0600
+
+    mpc83xx: add the QUICC Engine (QE) immap file
+
+    common QE immap file.  Also required for 8360.
+
+commit b701652a4992bdcc62fb1a6038a85beef9e55da4
+Author: Dave Liu <daveliu@freescale.com>
+Date:	Tue Oct 31 19:25:38 2006 -0600
+
+    mpc83xx: Add 8360 specifics to 83xx immap
+
+    Mainly add QE device dependencies, with appropriate 8360 protection.
+    Lindent also run.
+
+commit 988833324a7fda482c8ac3ca23eb539f8232e404
+Author: Timur Tabi <timur@freescale.com>
+Date:	Tue Oct 31 19:14:41 2006 -0600
+
+    mpc83xx: Fix PCI, USB, bootargs for MPC8349E-mITX
+
+    PREREQUISITE PATCHES:
+
+    * This patch can only be applied after the following patches have been applied:
+
+      1) DNX#2006092142000015 "Add support for the MPC8349E-mITX  1/2"
+      2) DNX#2006092142000024 "Add support for the MPC8349E-mITX  2/2"
+
+    CHANGELOG:
+
+    * For the 8349E-mITX, fix some size values in pci_init_board(), enable
+      the clock for the 2nd USB board (Linux kernel will hang otherwise),
+      and fix the CONFIG_BOOTARGS macro.
+
+    Signed-off-by: Timur Tabi <timur@freescale.com>
+
+commit 2ad6b513b31070bd0c003792ed1c3e7f5d740357
+Author: Timur Tabi <timur@freescale.com>
+Date:	Tue Oct 31 18:44:42 2006 -0600
+
+    mpc83xx: Add support for the MPC8349E-mITX
+
+    PREREQUISITE PATCHES:
+
+    * This patch can only be applied after the following patches have been applied:
+
+      1) DNX#2006090742000024 "Add support for multiple I2C buses"
+      2) DNX#2006090742000033 "Multi-bus I2C implementation of MPC834x"
+      3) DNX#2006091242000041 "Additional MPC8349 support for multibus i2c"
+      4) DNX#2006091242000078 "Add support for variable flash memory sizes on 83xx systems"
+      5) DNX#2006091242000069 "Add support for Errata DDR6 on MPC 834x systems"
+
+    CHANGELOG:
+
+    * Add support for the Freescale MPC8349E-mITX reference design platform.
+      The second TSEC (Vitesse 7385 switch) is not supported at this time.
+
+    Signed-off-by: Timur Tabi <timur@freescale.com>
+
+commit 183da6d9b446cc12123455844ad1187e2375626f
+Author: Ben Warren <bwarren@qstreams.com>
+Date:	Tue Sep 12 10:15:53 2006 -0400
+
+    Additional MPC8349 support for multibus i2c
+
+    Hello,
+
+    Here is a patch for a file that was accidentally left out of a previous
+    attempt.
+
+    It accompanies the patch with ticket DNX#2006090742000024
+
+    CHANGELOG:
+	    Change PCI initialization to use new multi-bus I2C API.
+
+    regards,
+    Ben
+
+commit b24f119d672b709d153ff2ac091d4aa63ec6877d
+Author: Ben Warren <bwarren@qstreams.com>
+Date:	Thu Sep 7 16:51:04 2006 -0400
+
+    Multi-bus I2C implementation of MPC834x
+
+    Hello,
+
+    Attached is a patch implementing multiple I2C buses on the MPC834x CPU
+    family and the MPC8349EMDS board in particular.
+    This patch requires Patch 1 (Add support for multiple I2C buses).
+    Testing was performed on a 533MHz board.
+
+    /*** Note: This patch replaces ticket DNX#2006083042000027 ***/
+
+    Signed-off-by: Ben Warren <bwarren@qstreams.com>
+
+    CHANGELOG:
+	    Implemented driver-level code to support two I2C buses on the
+    MPC834x CPU family and the MPC8349EMDS board.  Available I2C bus speeds
+    are 50kHz, 100kHz and 400kHz on each bus.
+
+    regards,
+    Ben
+
+commit bb99ad6d8257bf828f150d40f507b30d80a4a7ae
+Author: Ben Warren <bwarren@qstreams.com>
+Date:	Thu Sep 7 16:50:54 2006 -0400
+
+    Add support for multiple I2C buses
+
+    Hello,
+
+    Attached is a patch providing support for multiple I2C buses at the
+    command level.  The second part of the patch includes an implementation
+    for the MPC834x CPU and MPC8349EMDS board.
+
+    /*** Note: This patch replaces ticket DNX#2006083042000018 ***/
+
+    Signed-off-by: Ben Warren <bwarren@qstreams.com>
+
+    Overview:
+
+    1. Include new 'i2c' command (based on USB implementation) using
+    CONFIG_I2C_CMD_TREE.
+
+    2. Allow multiple buses by defining CONFIG_I2C_MULTI_BUS.  Note that
+    the commands to change bus number and speed are only available under the
+    new 'i2c' command mentioned in the first bullet.
+
+    3. The option CFG_I2C_NOPROBES has been expanded to work in multi-bus
+    systems.  When CONFIG_I2C_MULTI_BUS is used, this option takes the form
+    of an array of bus-device pairs.  Otherwise, it is an array of uchar.
+
+    CHANGELOG:
+	    Added new 'i2c' master command for all I2C interaction.  This is
+    conditionally compiled with CONFIG_I2C_CMD_TREE.  New commands added for
+    setting I2C bus speed as well as changing the active bus if the board
+    has more than one (conditionally compiled with
+    CONFIG_I2C_MULTI_BUS).  Updated NOPROBE logic to handle multiple buses.
+    Updated README.
+
+    regards,
+    Ben
+
+commit bed85caf872714ebf53013967a695c9d63acfc68
+Author: Timur Tabi <timur@freescale.com>
+Date:	Tue Oct 31 18:13:36 2006 -0600
+
+    mpc83xx: Add support for Errata DDR6 on MPC 834x systems
+
+    CHANGELOG:
+
+    * Errata DDR6, which affects all current MPC 834x processors, lists changes
+      required to maintain compatibility with various types of DDR memory.  This
+      patch implements those changes.
+
+    Signed-off-by: Timur Tabi <timur@freescale.com>
+
+commit afd6e470f639883002c7c59d562690a5cb0f4865
+Author: Timur Tabi <timur@freescale.com>
+Date:	Wed Oct 25 18:45:23 2006 -0500
+
+    mpc83xx: fix TQM build by defining a CFG_FLASH_SIZE for it
+
+commit 31068b7c4abeefcb2c8fd4fbeccc8ec6c6d0475a
+Author: Timur Tabi <timur@freescale.com>
+Date:	Tue Aug 22 17:07:00 2006 -0500
+
+    mpc83xx: Add support for variable flash memory sizes on 83xx systems
+
+    CHANGELOG:
+
+    * On 83xx systems, use the CFG_FLASH_SIZE macro to program the LBC local access
+       window registers, instead of using a hard-coded value of 8MB.
+
+    Signed-off-by: Timur Tabi <timur@freescale.com>
+
+commit 2fc34ae66e73fa7841d1a006dc1b5dcbc1f78965
+Author: Tanya Jiang <tanya.jiang@freescale.com>
+Date:	Thu Aug 3 18:38:13 2006 +0800
+
+    mpc83xx: Unified TQM834x variable names with 83xx and consolidated macros
+
+    Unified TQM834x variable names with 83xx and consolidated macro
+    in preparation for the 8360 and other upcoming 83xx devices.
+
+    Signed-off-by: Tanya Jiang <tanya.jiang@freescale.com>
+
+commit f6eda7f80ccc13d658020268c507d7173cf2e8aa
+Author: Dave Liu <daveliu@freescale.com>
+Date:	Wed Oct 25 14:41:21 2006 -0500
+
+    mpc83xx: Changed to unified mpx83xx names and added common 83xx changes
+
+    Incorporated the common unified variable names and the changes in preparation
+    for releasing mpc8360 patches.
+
+    Signed-off-by: Dave Liu <daveliu@freescale.com>
+
+commit 3894c46c27c64891f93ac04edde86a9fa9758d92
+Author: Tanya Jiang <tanya.jiang@freescale.com>
+Date:	Thu Aug 3 18:36:02 2006 +0800
+
+    mpc83xx: Fix missing build for mpc8349emds pci.c
+
+    Make pci build for mpc8349emds
+
+    Signed-off-by: Tanya Jiang <tanya.jiang@freescale.com>
+
+commit 09a81ff740b29deea1e2ab08a3c2ac136c2e6219
+Author: Tanya Jiang <tanya.jiang@freescale.com>
+Date:	Thu Aug 3 18:39:49 2006 +0800
+
+    mpc83xx: Removed unused file resetvec.S for mpc83xx cpu
+
+    Removed unused file resetvec.S for mpc83xx cpu
+
+    Signed-off-by: Tanya Jiang <tanya.jiang@freescale.com>
+
+commit 04f899fc465c3e44f2b55ecc70618f5696fc0ddf
+Author: Nick Spence <Nick.Spence@freescale.com>
+Date:	Sat Sep 30 00:32:59 2006 -0700
+
+    NAND Flash verify across block boundaries
+
+    This patch addresses a problem when CONFIG_MTD_NAND_VERIFY_WRITE is
+    defined
+    and the write crosses a block boundary. The pointer to the verification
+    buffer (bufstart) is not being updated to reflect the starting of the
+    new
+    block so the verification of the second block fails.
+
+    CHANGELOG:
+
+    * Fix NAND FLASH page verification across block boundaries
+
+commit f484dc791a3932537213c43c654cc1295c64b84c
+Author: Nick Spence <nick.spence@freescale.com>
+Date:	Thu Sep 7 07:39:46 2006 -0700
+
+    Added RGMII support to the TSECs and Marvell 881111 Phy
+
+    Added a phy initialization to adjust the RGMII RX and TX timing
+    Always set the R100 bit in 100 BaseT mode regardless of the TSEC mode
+
+    Signed-off-by: Nick Spence <nick.spence@freescale.com>
+
 commit c59200443072353044aa4bf737a5a60f9a9af231
 Author: Wolfgang Denk <wd@pollux.denx.de>
 Date:	Thu Nov 2 15:15:01 2006 +0100