added boot script files to repository

674 files changed, 0 insertions, 189978 deletions

diff --git a/arch/arm/config.mk b/arch/arm/config.mk
deleted file mode 100644
index a6a4742..0000000
--- a/arch/arm/config.mk
+++ /dev/null
@@ -1,71 +0,0 @@
-#
-# (C) Copyright 2000-2002
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-CROSS_COMPILE ?= arm-linux-
-
-ifeq ($(BOARD),omap2420h4)
-STANDALONE_LOAD_ADDR = 0x80300000
-else
-ifeq ($(SOC),omap3)
-STANDALONE_LOAD_ADDR = 0x80300000
-else
-STANDALONE_LOAD_ADDR = 0xc100000
-endif
-endif
-
-PLATFORM_CPPFLAGS += -DCONFIG_ARM -D__ARM__
-
-# Explicitly specifiy 32-bit ARM ISA since toolchain default can be -mthumb:
-PLATFORM_CPPFLAGS += $(call cc-option,-marm,)
-
-# Try if EABI is supported, else fall back to old API,
-# i. e. for example:
-# - with ELDK 4.2 (EABI supported), use:
-#	-mabi=aapcs-linux -mno-thumb-interwork
-# - with ELDK 4.1 (gcc 4.x, no EABI), use:
-#	-mabi=apcs-gnu -mno-thumb-interwork
-# - with ELDK 3.1 (gcc 3.x), use:
-#	-mapcs-32 -mno-thumb-interwork
-PLATFORM_CPPFLAGS += $(call cc-option,\
-				-mabi=aapcs-linux -mno-thumb-interwork,\
-				$(call cc-option,\
-					-mapcs-32,\
-					$(call cc-option,\
-						-mabi=apcs-gnu,\
-					)\
-				) $(call cc-option,-mno-thumb-interwork,)\
-			)
-
-# For EABI, make sure to provide raise()
-ifneq (,$(findstring -mabi=aapcs-linux,$(PLATFORM_CPPFLAGS)))
-# This file is parsed several times; make sure to add only once.
-ifeq (,$(findstring arch/arm/lib/eabi_compat.o,$(PLATFORM_LIBS)))
-PLATFORM_LIBS += $(OBJTREE)/arch/arm/lib/eabi_compat.o
-endif
-endif
-LDSCRIPT := $(SRCTREE)/$(CPUDIR)/u-boot.lds
-
-# needed for relocation
-ifndef CONFIG_NAND_SPL
-LDFLAGS_u-boot += -pie
-endif
diff --git a/arch/arm/cpu/arm1136/Makefile b/arch/arm/cpu/arm1136/Makefile
deleted file mode 100644
index 930e0d1..0000000
--- a/arch/arm/cpu/arm1136/Makefile
+++ /dev/null
@@ -1,47 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(CPU).o
-
-START	= start.o
-COBJS	= cpu.o
-
-SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS) $(SOBJS))
-START	:= $(addprefix $(obj),$(START))
-
-all:	$(obj).depend $(START) $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/arch/arm/cpu/arm1136/config.mk b/arch/arm/cpu/arm1136/config.mk
deleted file mode 100644
index 3e68535..0000000
--- a/arch/arm/cpu/arm1136/config.mk
+++ /dev/null
@@ -1,32 +0,0 @@
-#
-# (C) Copyright 2002
-# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float
-
-# Make ARMv5 to allow more compilers to work, even though its v6.
-PLATFORM_CPPFLAGS += -march=armv5
-# =========================================================================
-#
-# Supply options according to compiler version
-#
-# =========================================================================
-PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))
diff --git a/arch/arm/cpu/arm1136/cpu.c b/arch/arm/cpu/arm1136/cpu.c
deleted file mode 100644
index 2b91631..0000000
--- a/arch/arm/cpu/arm1136/cpu.c
+++ /dev/null
@@ -1,77 +0,0 @@
-/*
- * (C) Copyright 2004 Texas Insturments
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * CPU specific code
- */
-
-#include <common.h>
-#include <command.h>
-#include <asm/system.h>
-
-static void cache_flush(void);
-
-int cleanup_before_linux (void)
-{
-	/*
-	 * this function is called just before we call linux
-	 * it prepares the processor for linux
-	 *
-	 * we turn off caches etc ...
-	 */
-
-	disable_interrupts ();
-
-#ifdef CONFIG_LCD
-	{
-		extern void lcd_disable(void);
-		extern void lcd_panel_disable(void);
-
-		lcd_disable(); /* proper disable of lcd & panel */
-		lcd_panel_disable();
-	}
-#endif
-
-	/* turn off I/D-cache */
-	icache_disable();
-	dcache_disable();
-	/* flush I/D-cache */
-	cache_flush();
-
-	return 0;
-}
-
-static void cache_flush(void)
-{
-	unsigned long i = 0;
-
-	asm ("mcr p15, 0, %0, c7, c10, 0": :"r" (i)); /* clean entire data cache */
-	asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i));  /* invalidate both caches and flush btb */
-	asm ("mcr p15, 0, %0, c7, c10, 4": :"r" (i)); /* mem barrier to sync things */
-}
diff --git a/arch/arm/cpu/arm1136/mx31/Makefile b/arch/arm/cpu/arm1136/mx31/Makefile
deleted file mode 100644
index eaed371..0000000
--- a/arch/arm/cpu/arm1136/mx31/Makefile
+++ /dev/null
@@ -1,47 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(SOC).o
-
-COBJS	+= generic.o
-COBJS	+= timer.o
-COBJS	+= devices.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
-
-all:	$(obj).depend $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/arch/arm/cpu/arm1136/mx31/devices.c b/arch/arm/cpu/arm1136/mx31/devices.c
deleted file mode 100644
index 1f4ca7e..0000000
--- a/arch/arm/cpu/arm1136/mx31/devices.c
+++ /dev/null
@@ -1,56 +0,0 @@
-/*
- *
- * (C) Copyright 2009 Magnus Lilja <lilja.magnus@gmail.com>
- *
- * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/arch/mx31-regs.h>
-#include <asm/arch/mx31.h>
-
-#ifdef CONFIG_SYS_MX31_UART1
-void mx31_uart1_hw_init(void)
-{
-	/* setup pins for UART1 */
-	mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX);
-	mx31_gpio_mux(MUX_TXD1__UART1_TXD_MUX);
-	mx31_gpio_mux(MUX_RTS1__UART1_RTS_B);
-	mx31_gpio_mux(MUX_CTS1__UART1_CTS_B);
-}
-#endif
-
-#ifdef CONFIG_MXC_SPI
-void mx31_spi2_hw_init(void)
-{
-	/* SPI2 */
-	mx31_gpio_mux(MUX_CSPI2_SS2__CSPI2_SS2_B);
-	mx31_gpio_mux(MUX_CSPI2_SCLK__CSPI2_CLK);
-	mx31_gpio_mux(MUX_CSPI2_SPI_RDY__CSPI2_DATAREADY_B);
-	mx31_gpio_mux(MUX_CSPI2_MOSI__CSPI2_MOSI);
-	mx31_gpio_mux(MUX_CSPI2_MISO__CSPI2_MISO);
-	mx31_gpio_mux(MUX_CSPI2_SS0__CSPI2_SS0_B);
-	mx31_gpio_mux(MUX_CSPI2_SS1__CSPI2_SS1_B);
-
-	/* start SPI2 clock */
-	__REG(CCM_CGR2) = __REG(CCM_CGR2) | (3 << 4);
-}
-#endif
diff --git a/arch/arm/cpu/arm1136/mx31/generic.c b/arch/arm/cpu/arm1136/mx31/generic.c
deleted file mode 100644
index 8bd23ee..0000000
--- a/arch/arm/cpu/arm1136/mx31/generic.c
+++ /dev/null
@@ -1,116 +0,0 @@
-/*
- * (C) Copyright 2007
- * Sascha Hauer, Pengutronix
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/arch/mx31-regs.h>
-#include <asm/io.h>
-
-static u32 mx31_decode_pll(u32 reg, u32 infreq)
-{
-	u32 mfi = (reg >> 10) & 0xf;
-	u32 mfn = reg & 0x3ff;
-	u32 mfd = (reg >> 16) & 0x3ff;
-	u32 pd =  (reg >> 26) & 0xf;
-
-	mfi = mfi <= 5 ? 5 : mfi;
-	mfd += 1;
-	pd += 1;
-
-	return ((2 * (infreq >> 10) * (mfi * mfd + mfn)) /
-		(mfd * pd)) << 10;
-}
-
-static u32 mx31_get_mpl_dpdgck_clk(void)
-{
-	u32 infreq;
-
-	if ((__REG(CCM_CCMR) & CCMR_PRCS_MASK) == CCMR_FPM)
-		infreq = CONFIG_MX31_CLK32 * 1024;
-	else
-		infreq = CONFIG_MX31_HCLK_FREQ;
-
-	return mx31_decode_pll(__REG(CCM_MPCTL), infreq);
-}
-
-static u32 mx31_get_mcu_main_clk(void)
-{
-	/* For now we assume mpl_dpdgck_clk == mcu_main_clk
-	 * which should be correct for most boards
-	 */
-	return mx31_get_mpl_dpdgck_clk();
-}
-
-u32 mx31_get_ipg_clk(void)
-{
-	u32 freq = mx31_get_mcu_main_clk();
-	u32 pdr0 = __REG(CCM_PDR0);
-
-	freq /= ((pdr0 >> 3) & 0x7) + 1;
-	freq /= ((pdr0 >> 6) & 0x3) + 1;
-
-	return freq;
-}
-
-void mx31_dump_clocks(void)
-{
-	u32 cpufreq = mx31_get_mcu_main_clk();
-	printf("mx31 cpu clock: %dMHz\n",cpufreq / 1000000);
-	printf("ipg clock     : %dHz\n", mx31_get_ipg_clk());
-}
-
-void mx31_gpio_mux(unsigned long mode)
-{
-	unsigned long reg, shift, tmp;
-
-	reg = IOMUXC_BASE + (mode & 0x1fc);
-	shift = (~mode & 0x3) * 8;
-
-	tmp = __REG(reg);
-	tmp &= ~(0xff << shift);
-	tmp |= ((mode >> IOMUX_MODE_POS) & 0xff) << shift;
-	__REG(reg) = tmp;
-}
-
-void mx31_set_pad(enum iomux_pins pin, u32 config)
-{
-	u32 field, l, reg;
-
-	pin &= IOMUX_PADNUM_MASK;
-	reg = (IOMUXC_BASE + 0x154) + (pin + 2) / 3 * 4;
-	field = (pin + 2) % 3;
-
-	l = __REG(reg);
-	l &= ~(0x1ff << (field * 10));
-	l |= config << (field * 10);
-	__REG(reg) = l;
-
-}
-
-#if defined(CONFIG_DISPLAY_CPUINFO)
-int print_cpuinfo (void)
-{
-	printf("CPU:   Freescale i.MX31 at %d MHz\n",
-		mx31_get_mcu_main_clk() / 1000000);
-	return 0;
-}
-#endif
diff --git a/arch/arm/cpu/arm1136/mx31/timer.c b/arch/arm/cpu/arm1136/mx31/timer.c
deleted file mode 100644
index f6be3b9..0000000
--- a/arch/arm/cpu/arm1136/mx31/timer.c
+++ /dev/null
@@ -1,169 +0,0 @@
-/*
- * (C) Copyright 2007
- * Sascha Hauer, Pengutronix
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/arch/mx31-regs.h>
-#include <div64.h>
-
-#define TIMER_BASE 0x53f90000 /* General purpose timer 1 */
-
-/* General purpose timers registers */
-#define GPTCR	__REG(TIMER_BASE)		/* Control register	*/
-#define GPTPR	__REG(TIMER_BASE + 0x4)		/* Prescaler register	*/
-#define GPTSR	__REG(TIMER_BASE + 0x8)		/* Status register	*/
-#define GPTCNT	__REG(TIMER_BASE + 0x24)	/* Counter register	*/
-
-/* General purpose timers bitfields */
-#define GPTCR_SWR		(1 << 15)	/* Software reset	*/
-#define GPTCR_FRR		(1 << 9)	/* Freerun / restart	*/
-#define GPTCR_CLKSOURCE_32	(4 << 6)	/* Clock source		*/
-#define GPTCR_TEN		1		/* Timer enable		*/
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/* "time" is measured in 1 / CONFIG_SYS_HZ seconds, "tick" is internal timer period */
-#ifdef CONFIG_MX31_TIMER_HIGH_PRECISION
-/* ~0.4% error - measured with stop-watch on 100s boot-delay */
-static inline unsigned long long tick_to_time(unsigned long long tick)
-{
-	tick *= CONFIG_SYS_HZ;
-	do_div(tick, CONFIG_MX31_CLK32);
-	return tick;
-}
-
-static inline unsigned long long time_to_tick(unsigned long long time)
-{
-	time *= CONFIG_MX31_CLK32;
-	do_div(time, CONFIG_SYS_HZ);
-	return time;
-}
-
-static inline unsigned long long us_to_tick(unsigned long long us)
-{
-	us = us * CONFIG_MX31_CLK32 + 999999;
-	do_div(us, 1000000);
-	return us;
-}
-#else
-/* ~2% error */
-#define TICK_PER_TIME	((CONFIG_MX31_CLK32 + CONFIG_SYS_HZ / 2) / CONFIG_SYS_HZ)
-#define US_PER_TICK	(1000000 / CONFIG_MX31_CLK32)
-
-static inline unsigned long long tick_to_time(unsigned long long tick)
-{
-	do_div(tick, TICK_PER_TIME);
-	return tick;
-}
-
-static inline unsigned long long time_to_tick(unsigned long long time)
-{
-	return time * TICK_PER_TIME;
-}
-
-static inline unsigned long long us_to_tick(unsigned long long us)
-{
-	us += US_PER_TICK - 1;
-	do_div(us, US_PER_TICK);
-	return us;
-}
-#endif
-
-/* The 32768Hz 32-bit timer overruns in 131072 seconds */
-int timer_init (void)
-{
-	int i;
-
-	/* setup GP Timer 1 */
-	GPTCR = GPTCR_SWR;
-	for (i = 0; i < 100; i++)
-		GPTCR = 0; /* We have no udelay by now */
-	GPTPR = 0; /* 32Khz */
-	/* Freerun Mode, PERCLK1 input */
-	GPTCR |= GPTCR_CLKSOURCE_32 | GPTCR_TEN;
-
-	return 0;
-}
-
-void reset_timer_masked (void)
-{
-	/* reset time */
-	gd->lastinc = GPTCNT; /* capture current incrementer value time */
-	gd->tbl = 0; /* start "advancing" time stamp from 0 */
-}
-
-void reset_timer(void)
-{
-	reset_timer_masked();
-}
-
-unsigned long long get_ticks (void)
-{
-	ulong now = GPTCNT; /* current tick value */
-
-	if (now >= gd->lastinc)	/* normal mode (non roll) */
-		/* move stamp forward with absolut diff ticks */
-		gd->tbl += (now - gd->lastinc);
-	else			/* we have rollover of incrementer */
-		gd->tbl += (0xFFFFFFFF - gd->lastinc) + now;
-	gd->lastinc = now;
-	return gd->tbl;
-}
-
-ulong get_timer_masked (void)
-{
-	/*
-	 * get_ticks() returns a long long (64 bit), it wraps in
-	 * 2^64 / CONFIG_MX31_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~
-	 * 5 * 10^9 days... and get_ticks() * CONFIG_SYS_HZ wraps in
-	 * 5 * 10^6 days - long enough.
-	 */
-	return tick_to_time(get_ticks());
-}
-
-ulong get_timer (ulong base)
-{
-	return get_timer_masked () - base;
-}
-
-void set_timer (ulong t)
-{
-	gd->tbl = time_to_tick(t);
-}
-
-/* delay x useconds AND preserve advance timestamp value */
-void __udelay (unsigned long usec)
-{
-	unsigned long long tmp;
-	ulong tmo;
-
-	tmo = us_to_tick(usec);
-	tmp = get_ticks() + tmo;	/* get current timestamp */
-
-	while (get_ticks() < tmp)	/* loop till event */
-		 /*NOP*/;
-}
-
-void reset_cpu (ulong addr)
-{
-	__REG16(WDOG_BASE) = 4;
-}
diff --git a/arch/arm/cpu/arm1136/mx35/Makefile b/arch/arm/cpu/arm1136/mx35/Makefile
deleted file mode 100644
index 20f36e3..0000000
--- a/arch/arm/cpu/arm1136/mx35/Makefile
+++ /dev/null
@@ -1,63 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(SOC).o
-
-COBJS	+= generic.o
-COBJS	+= timer.o
-COBJS	+= iomux.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
-
-all:	$(obj).depend $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-$(OBJS) : $(TOPDIR)/include/asm/arch/asm-offsets.h
-
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
-
-$(TOPDIR)/include/asm/arch/asm-offsets.h:	$(TOPDIR)/include/autoconf.mk.dep \
-	./asm-offsets.s
-	@echo Generating $@
-	$(TOPDIR)/tools/scripts/make-asm-offsets ./asm-offsets.s $@
-
-asm-offsets.s:	$(TOPDIR)/include/autoconf.mk.dep \
-	./asm-offsets.c
-	$(CC) -DDO_DEPS_ONLY \
-		$(CFLAGS) $(CFLAGS_$(BCURDIR)/$(@F)) $(CFLAGS_$(BCURDIR)) \
-		-o $@ ./asm-offsets.c -c -S
diff --git a/arch/arm/cpu/arm1136/mx35/asm-offsets.c b/arch/arm/cpu/arm1136/mx35/asm-offsets.c
deleted file mode 100644
index d2678e2..0000000
--- a/arch/arm/cpu/arm1136/mx35/asm-offsets.c
+++ /dev/null
@@ -1,43 +0,0 @@
-/*
- * Adapted from Linux v2.6.36 kernel: arch/powerpc/kernel/asm-offsets.c
- *
- * This program is used to generate definitions needed by
- * assembly language modules.
- *
- * We use the technique used in the OSF Mach kernel code:
- * generate asm statements containing #defines,
- * compile this file to assembler, and then extract the
- * #defines from the assembly-language output.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#include <common.h>
-#include <asm/arch/imx-regs.h>
-
-#include <linux/kbuild.h>
-
-int main(void)
-{
-
-	/* Round up to make sure size gives nice stack alignment */
-	DEFINE(CLKCTL_CCMR, offsetof(struct ccm_regs, ccmr));
-	DEFINE(CLKCTL_PDR0, offsetof(struct ccm_regs, pdr0));
-	DEFINE(CLKCTL_PDR1, offsetof(struct ccm_regs, pdr1));
-	DEFINE(CLKCTL_PDR2, offsetof(struct ccm_regs, pdr2));
-	DEFINE(CLKCTL_PDR3, offsetof(struct ccm_regs, pdr3));
-	DEFINE(CLKCTL_PDR4, offsetof(struct ccm_regs, pdr4));
-	DEFINE(CLKCTL_RCSR, offsetof(struct ccm_regs, rcsr));
-	DEFINE(CLKCTL_MPCTL, offsetof(struct ccm_regs, mpctl));
-	DEFINE(CLKCTL_PPCTL, offsetof(struct ccm_regs, ppctl));
-	DEFINE(CLKCTL_ACMR, offsetof(struct ccm_regs, acmr));
-	DEFINE(CLKCTL_COSR, offsetof(struct ccm_regs, cosr));
-	DEFINE(CLKCTL_CGR0, offsetof(struct ccm_regs, cgr0));
-	DEFINE(CLKCTL_CGR1, offsetof(struct ccm_regs, cgr1));
-	DEFINE(CLKCTL_CGR2, offsetof(struct ccm_regs, cgr2));
-
-	return 0;
-}
diff --git a/arch/arm/cpu/arm1136/mx35/generic.c b/arch/arm/cpu/arm1136/mx35/generic.c
deleted file mode 100644
index 1b4ab75..0000000
--- a/arch/arm/cpu/arm1136/mx35/generic.c
+++ /dev/null
@@ -1,463 +0,0 @@
-/*
- * (C) Copyright 2007
- * Sascha Hauer, Pengutronix
- *
- * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/errno.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/crm_regs.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/sys_proto.h>
-#include <netdev.h>
-
-#define CLK_CODE(arm, ahb, sel) (((arm) << 16) + ((ahb) << 8) + (sel))
-#define CLK_CODE_ARM(c)		(((c) >> 16) & 0xFF)
-#define CLK_CODE_AHB(c)		(((c) >>  8) & 0xFF)
-#define CLK_CODE_PATH(c)	((c) & 0xFF)
-
-#define CCM_GET_DIVIDER(x, m, o) (((x) & (m)) >> (o))
-
-#ifdef CONFIG_FSL_ESDHC
-DECLARE_GLOBAL_DATA_PTR;
-#endif
-
-static int g_clk_mux_auto[8] = {
-	CLK_CODE(1, 3, 0), CLK_CODE(1, 2, 1), CLK_CODE(2, 1, 1), -1,
-	CLK_CODE(1, 6, 0), CLK_CODE(1, 4, 1), CLK_CODE(2, 2, 1), -1,
-};
-
-static int g_clk_mux_consumer[16] = {
-	CLK_CODE(1, 4, 0), CLK_CODE(1, 3, 1), CLK_CODE(1, 3, 1), -1,
-	-1, -1, CLK_CODE(4, 1, 0), CLK_CODE(1, 5, 0),
-	CLK_CODE(1, 8, 1), CLK_CODE(1, 6, 1), CLK_CODE(2, 4, 0), -1,
-	-1, -1, CLK_CODE(4, 2, 0), -1,
-};
-
-static int hsp_div_table[3][16] = {
-	{4, 3, 2, -1, -1, -1, 1, 5, 4, 3, 2, -1, -1, -1, 1, -1},
-	{-1, -1, -1, -1, -1, -1, -1, -1, 8, 6, 4, -1, -1, -1, 2, -1},
-	{3, -1, -1, -1, -1, -1, -1, -1, 3, -1, -1, -1, -1, -1, -1, -1},
-};
-
-u32 get_cpu_rev(void)
-{
-	int reg;
-	struct iim_regs *iim =
-		(struct iim_regs *)IIM_BASE_ADDR;
-	reg = readl(&iim->iim_srev);
-	if (!reg) {
-		reg = readw(ROMPATCH_REV);
-		reg <<= 4;
-	} else {
-		reg += CHIP_REV_1_0;
-	}
-
-	return 0x35000 + (reg & 0xFF);
-}
-
-static u32 get_arm_div(u32 pdr0, u32 *fi, u32 *fd)
-{
-	int *pclk_mux;
-	if (pdr0 & MXC_CCM_PDR0_AUTO_CON) {
-		pclk_mux = g_clk_mux_consumer +
-			((pdr0 & MXC_CCM_PDR0_CON_MUX_DIV_MASK) >>
-			MXC_CCM_PDR0_CON_MUX_DIV_OFFSET);
-	} else {
-		pclk_mux = g_clk_mux_auto +
-			((pdr0 & MXC_CCM_PDR0_AUTO_MUX_DIV_MASK) >>
-			MXC_CCM_PDR0_AUTO_MUX_DIV_OFFSET);
-	}
-
-	if ((*pclk_mux) == -1)
-		return -1;
-
-	if (fi && fd) {
-		if (!CLK_CODE_PATH(*pclk_mux)) {
-			*fi = *fd = 1;
-			return CLK_CODE_ARM(*pclk_mux);
-		}
-		if (pdr0 & MXC_CCM_PDR0_AUTO_CON) {
-			*fi = 3;
-			*fd = 4;
-		} else {
-			*fi = 2;
-			*fd = 3;
-		}
-	}
-	return CLK_CODE_ARM(*pclk_mux);
-}
-
-static int get_ahb_div(u32 pdr0)
-{
-	int *pclk_mux;
-
-	pclk_mux = g_clk_mux_consumer +
-		((pdr0 & MXC_CCM_PDR0_CON_MUX_DIV_MASK) >>
-		MXC_CCM_PDR0_CON_MUX_DIV_OFFSET);
-
-	if ((*pclk_mux) == -1)
-		return -1;
-
-	return CLK_CODE_AHB(*pclk_mux);
-}
-
-static u32 decode_pll(u32 reg, u32 infreq)
-{
-	u32 mfi = (reg >> 10) & 0xf;
-	u32 mfn = reg & 0x3f;
-	u32 mfd = (reg >> 16) & 0x3f;
-	u32 pd = (reg >> 26) & 0xf;
-
-	mfi = mfi <= 5 ? 5 : mfi;
-	mfd += 1;
-	pd += 1;
-
-	return ((2 * (infreq / 1000) * (mfi * mfd + mfn)) / (mfd * pd)) * 1000;
-}
-
-static u32 get_mcu_main_clk(void)
-{
-	u32 arm_div = 0, fi = 0, fd = 0;
-	struct ccm_regs *ccm =
-		(struct ccm_regs *)IMX_CCM_BASE;
-	arm_div = get_arm_div(readl(&ccm->pdr0), &fi, &fd);
-	fi *=
-		decode_pll(readl(&ccm->mpctl),
-			CONFIG_MX35_HCLK_FREQ);
-	return fi / (arm_div * fd);
-}
-
-static u32 get_ipg_clk(void)
-{
-	u32 freq = get_mcu_main_clk();
-	struct ccm_regs *ccm =
-		(struct ccm_regs *)IMX_CCM_BASE;
-	u32 pdr0 = readl(&ccm->pdr0);
-
-	return freq / (get_ahb_div(pdr0) * 2);
-}
-
-static u32 get_ipg_per_clk(void)
-{
-	u32 freq = get_mcu_main_clk();
-	struct ccm_regs *ccm =
-		(struct ccm_regs *)IMX_CCM_BASE;
-	u32 pdr0 = readl(&ccm->pdr0);
-	u32 pdr4 = readl(&ccm->pdr4);
-	u32 div;
-	if (pdr0 & MXC_CCM_PDR0_PER_SEL) {
-		div = (CCM_GET_DIVIDER(pdr4,
-			MXC_CCM_PDR4_PER0_PRDF_MASK,
-			MXC_CCM_PDR4_PER0_PODF_OFFSET) + 1) *
-			(CCM_GET_DIVIDER(pdr4,
-			MXC_CCM_PDR4_PER0_PODF_MASK,
-			MXC_CCM_PDR4_PER0_PODF_OFFSET) + 1);
-	} else {
-		div = CCM_GET_DIVIDER(pdr0,
-			MXC_CCM_PDR0_PER_PODF_MASK,
-			MXC_CCM_PDR0_PER_PODF_OFFSET) + 1;
-		freq /= get_ahb_div(pdr0);
-	}
-	return freq / div;
-}
-
-u32 imx_get_uartclk(void)
-{
-	u32 freq;
-	struct ccm_regs *ccm =
-		(struct ccm_regs *)IMX_CCM_BASE;
-	u32 pdr4 = readl(&ccm->pdr4);
-
-	if (readl(&ccm->pdr3) & MXC_CCM_PDR3_UART_M_U) {
-		freq = get_mcu_main_clk();
-	} else {
-		freq = decode_pll(readl(&ccm->ppctl),
-			CONFIG_MX35_HCLK_FREQ);
-	}
-	freq /= ((CCM_GET_DIVIDER(pdr4,
-			MXC_CCM_PDR4_UART_PRDF_MASK,
-			MXC_CCM_PDR4_UART_PRDF_OFFSET) + 1) *
-		(CCM_GET_DIVIDER(pdr4,
-			MXC_CCM_PDR4_UART_PODF_MASK,
-			MXC_CCM_PDR4_UART_PODF_OFFSET) + 1));
-	return freq;
-}
-
-unsigned int mxc_get_main_clock(enum mxc_main_clocks clk)
-{
-	u32 nfc_pdf, hsp_podf;
-	u32 pll, ret_val = 0, usb_prdf, usb_podf;
-	struct ccm_regs *ccm =
-		(struct ccm_regs *)IMX_CCM_BASE;
-
-	u32 reg = readl(&ccm->pdr0);
-	u32 reg4 = readl(&ccm->pdr4);
-
-	reg |= 0x1;
-
-	switch (clk) {
-	case CPU_CLK:
-		ret_val = get_mcu_main_clk();
-		break;
-	case AHB_CLK:
-		ret_val = get_mcu_main_clk();
-		break;
-	case HSP_CLK:
-		if (reg & CLKMODE_CONSUMER) {
-			hsp_podf = (reg >> 20) & 0x3;
-			pll = get_mcu_main_clk();
-			hsp_podf = hsp_div_table[hsp_podf][(reg>>16)&0xF];
-			if (hsp_podf > 0) {
-				ret_val = pll / hsp_podf;
-			} else {
-				puts("mismatch HSP with ARM clock setting\n");
-				ret_val = 0;
-			}
-		} else {
-			ret_val = get_mcu_main_clk();
-		}
-		break;
-	case IPG_CLK:
-		ret_val = get_ipg_clk();;
-		break;
-	case IPG_PER_CLK:
-		ret_val = get_ipg_per_clk();
-		break;
-	case NFC_CLK:
-		nfc_pdf = (reg4 >> 28) & 0xF;
-		pll = get_mcu_main_clk();
-		/* AHB/nfc_pdf */
-		ret_val = pll / (nfc_pdf + 1);
-		break;
-	case USB_CLK:
-		usb_prdf = (reg4 >> 25) & 0x7;
-		usb_podf = (reg4 >> 22) & 0x7;
-		if (reg4 & 0x200) {
-			pll = get_mcu_main_clk();
-		} else {
-			pll = decode_pll(readl(&ccm->ppctl),
-				CONFIG_MX35_HCLK_FREQ);
-		}
-
-		ret_val = pll / ((usb_prdf + 1) * (usb_podf + 1));
-		break;
-	default:
-		printf("Unknown clock: %d\n", clk);
-		break;
-	}
-
-	return ret_val;
-}
-unsigned int mxc_get_peri_clock(enum mxc_peri_clocks clk)
-{
-	u32 ret_val = 0, pdf, pre_pdf, clk_sel;
-	struct ccm_regs *ccm =
-		(struct ccm_regs *)IMX_CCM_BASE;
-	u32 mpdr2 = readl(&ccm->pdr2);
-	u32 mpdr3 = readl(&ccm->pdr3);
-	u32 mpdr4 = readl(&ccm->pdr4);
-
-	switch (clk) {
-	case UART1_BAUD:
-	case UART2_BAUD:
-	case UART3_BAUD:
-		clk_sel = mpdr3 & (1 << 14);
-		pre_pdf = (mpdr4 >> 13) & 0x7;
-		pdf = (mpdr4 >> 10) & 0x7;
-		ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
-			decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) /
-				((pre_pdf + 1) * (pdf + 1));
-		break;
-	case SSI1_BAUD:
-		pre_pdf = (mpdr2 >> 24) & 0x7;
-		pdf = mpdr2 & 0x3F;
-		clk_sel = mpdr2 & (1 << 6);
-		ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
-			decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) /
-				((pre_pdf + 1) * (pdf + 1));
-		break;
-	case SSI2_BAUD:
-		pre_pdf = (mpdr2 >> 27) & 0x7;
-		pdf = (mpdr2 >> 8) & 0x3F;
-		clk_sel = mpdr2 & (1 << 6);
-		ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
-			decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) /
-				((pre_pdf + 1) * (pdf + 1));
-		break;
-	case CSI_BAUD:
-		clk_sel = mpdr2 & (1 << 7);
-		pre_pdf = (mpdr2 >> 16) & 0x7;
-		pdf = (mpdr2 >> 19) & 0x7;
-		ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
-			decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) /
-				((pre_pdf + 1) * (pdf + 1));
-		break;
-	case MSHC_CLK:
-		pre_pdf = readl(&ccm->pdr1);
-		clk_sel = (pre_pdf & 0x80);
-		pdf = (pre_pdf >> 22) & 0x3F;
-		pre_pdf = (pre_pdf >> 28) & 0x7;
-		ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
-			decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) /
-				((pre_pdf + 1) * (pdf + 1));
-		break;
-	case ESDHC1_CLK:
-		clk_sel = mpdr3 & 0x40;
-		pre_pdf = mpdr3 & 0x7;
-		pdf = (mpdr3>>3) & 0x7;
-		ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
-			decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) /
-				((pre_pdf + 1) * (pdf + 1));
-		break;
-	case ESDHC2_CLK:
-		clk_sel = mpdr3 & 0x40;
-		pre_pdf = (mpdr3 >> 8) & 0x7;
-		pdf = (mpdr3 >> 11) & 0x7;
-		ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
-			decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) /
-				((pre_pdf + 1) * (pdf + 1));
-		break;
-	case ESDHC3_CLK:
-		clk_sel = mpdr3 & 0x40;
-		pre_pdf = (mpdr3 >> 16) & 0x7;
-		pdf = (mpdr3 >> 19) & 0x7;
-		ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
-			decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) /
-				((pre_pdf + 1) * (pdf + 1));
-		break;
-	case SPDIF_CLK:
-		clk_sel = mpdr3 & 0x400000;
-		pre_pdf = (mpdr3 >> 29) & 0x7;
-		pdf = (mpdr3 >> 23) & 0x3F;
-		ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
-			decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) /
-				((pre_pdf + 1) * (pdf + 1));
-		break;
-	default:
-		printf("%s(): This clock: %d not supported yet\n",
-				__func__, clk);
-		break;
-	}
-
-	return ret_val;
-}
-
-unsigned int mxc_get_clock(enum mxc_clock clk)
-{
-	switch (clk) {
-	case MXC_ARM_CLK:
-		return get_mcu_main_clk();
-	case MXC_AHB_CLK:
-		break;
-	case MXC_IPG_CLK:
-		return get_ipg_clk();
-	case MXC_IPG_PERCLK:
-		return get_ipg_per_clk();
-	case MXC_UART_CLK:
-		return imx_get_uartclk();
-	case MXC_ESDHC_CLK:
-		return mxc_get_peri_clock(ESDHC1_CLK);
-	case MXC_USB_CLK:
-		return mxc_get_main_clock(USB_CLK);
-	case MXC_FEC_CLK:
-		return get_ipg_clk();
-	case MXC_CSPI_CLK:
-		return get_ipg_clk();
-	}
-	return -1;
-}
-
-#ifdef CONFIG_FEC_MXC
-/*
- * The MX35 has no fuse for MAC, return a NULL MAC
- */
-void imx_get_mac_from_fuse(unsigned char *mac)
-{
-	memset(mac, 0, 6);
-}
-
-u32 imx_get_fecclk(void)
-{
-	return mxc_get_clock(MXC_IPG_CLK);
-}
-#endif
-
-int do_mx35_showclocks(cmd_tbl_t *cmdtp,
-	int flag, int argc, char * const argv[])
-{
-	u32 cpufreq = get_mcu_main_clk();
-	printf("mx35 cpu clock: %dMHz\n", cpufreq / 1000000);
-	printf("ipg clock     : %dHz\n", get_ipg_clk());
-	printf("ipg per clock : %dHz\n", get_ipg_per_clk());
-	printf("uart clock    : %dHz\n", mxc_get_clock(MXC_UART_CLK));
-
-	return 0;
-}
-
-U_BOOT_CMD(
-	clockinfo,	CONFIG_SYS_MAXARGS,	1,	do_mx35_showclocks,
-	"display clocks\n",
-	""
-);
-
-#if defined(CONFIG_DISPLAY_CPUINFO)
-int print_cpuinfo(void)
-{
-	printf("CPU:   Freescale i.MX35 at %d MHz\n",
-		get_mcu_main_clk() / 1000000);
-	/* mxc_dump_clocks(); */
-	return 0;
-}
-#endif
-
-/*
- * Initializes on-chip ethernet controllers.
- * to override, implement board_eth_init()
- */
-
-int cpu_eth_init(bd_t *bis)
-{
-	int rc = -ENODEV;
-
-#if defined(CONFIG_FEC_MXC)
-	rc = fecmxc_initialize(bis);
-#endif
-
-	return rc;
-}
-
-int get_clocks(void)
-{
-#ifdef CONFIG_FSL_ESDHC
-	gd->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
-#endif
-	return 0;
-}
-
-void reset_cpu(ulong addr)
-{
-	struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE_ADDR;
-	writew(4, &wdog->wcr);
-}
diff --git a/arch/arm/cpu/arm1136/mx35/iomux.c b/arch/arm/cpu/arm1136/mx35/iomux.c
deleted file mode 100644
index f93191d..0000000
--- a/arch/arm/cpu/arm1136/mx35/iomux.c
+++ /dev/null
@@ -1,116 +0,0 @@
-/*
- * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/mx35_pins.h>
-#include <asm/arch/iomux.h>
-
-/*
- * IOMUX register (base) addresses
- */
-enum iomux_reg_addr {
-	IOMUXGPR = IOMUXC_BASE_ADDR,			/* General purpose */
-	IOMUXSW_MUX_CTL = IOMUXC_BASE_ADDR + 4,		/* MUX control */
-	IOMUXSW_MUX_END = IOMUXC_BASE_ADDR + 0x324,	/* last MUX control */
-	IOMUXSW_PAD_CTL = IOMUXC_BASE_ADDR + 0x328,	/* Pad control */
-	IOMUXSW_PAD_END = IOMUXC_BASE_ADDR + 0x794,	/* last Pad control */
-	IOMUXSW_INPUT_CTL = IOMUXC_BASE_ADDR + 0x7AC,	/* input select */
-	IOMUXSW_INPUT_END = IOMUXC_BASE_ADDR + 0x9F4,	/* last input select */
-};
-
-#define MUX_PIN_NUM_MAX		\
-		(((IOMUXSW_PAD_END - IOMUXSW_PAD_CTL) >> 2) + 1)
-#define MUX_INPUT_NUM_MUX	\
-		(((IOMUXSW_INPUT_END - IOMUXSW_INPUT_CTL) >> 2) + 1)
-
-#define PIN_TO_IOMUX_INDEX(pin) ((PIN_TO_IOMUX_PAD(pin) - 0x328) >> 2)
-
-/*
- * Request ownership for an IO pin. This function has to be the first one
- * being called before that pin is used.
- */
-void mxc_request_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg)
-{
-	u32 mux_reg = PIN_TO_IOMUX_MUX(pin);
-
-	if (mux_reg != NON_MUX_I) {
-		mux_reg += IOMUXGPR;
-		writel(cfg, mux_reg);
-	}
-}
-
-/*
- * Release ownership for an IO pin
- */
-void mxc_free_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg)
-{
-}
-
-/*
- * This function configures the pad value for a IOMUX pin.
- *
- * @param  pin     a pin number as defined in iomux_pin_name_t
- * @param  config  the ORed value of elements defined in iomux_pad_config_t
- */
-void mxc_iomux_set_pad(iomux_pin_name_t pin, u32 config)
-{
-	u32 pad_reg = IOMUXGPR + PIN_TO_IOMUX_PAD(pin);
-
-	writel(config, pad_reg);
-}
-
-/*
- * This function enables/disables the general purpose function for a particular
- * signal.
- *
- * @param  gp   one signal as defined in iomux_gp_func_t
- * @param  en   enable/disable
- */
-void mxc_iomux_set_gpr(iomux_gp_func_t gp, int en)
-{
-	u32 l;
-
-	l = readl(IOMUXGPR);
-	if (en)
-		l |= gp;
-	else
-		l &= ~gp;
-
-	writel(l, IOMUXGPR);
-}
-
-/*
- * This function configures input path.
- *
- * @param input index of input select register as defined in
- *			iomux_input_select_t
- * @param config the binary value of elements defined in
- *			iomux_input_config_t
- */
-void mxc_iomux_set_input(iomux_input_select_t input, u32 config)
-{
-	u32 reg = IOMUXSW_INPUT_CTL + (input << 2);
-
-	writel(config, reg);
-}
diff --git a/arch/arm/cpu/arm1136/mx35/timer.c b/arch/arm/cpu/arm1136/mx35/timer.c
deleted file mode 100644
index db1e2c9..0000000
--- a/arch/arm/cpu/arm1136/mx35/timer.c
+++ /dev/null
@@ -1,120 +0,0 @@
-/*
- * (C) Copyright 2007
- * Sascha Hauer, Pengutronix
- *
- * (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/imx-regs.h>
-
-/* General purpose timers bitfields */
-#define GPTCR_SWR       (1<<15)	/* Software reset */
-#define GPTCR_FRR       (1<<9)	/* Freerun / restart */
-#define GPTCR_CLKSOURCE_32   (0x100<<6)	/* Clock source */
-#define GPTCR_CLKSOURCE_IPG (0x001<<6)	/* Clock source */
-#define GPTCR_TEN       (1)	/* Timer enable */
-#define GPTPR_VAL	(66)
-
-int timer_init(void)
-{
-	int i;
-	struct gpt_regs *gpt = (struct gpt_regs *)GPT1_BASE_ADDR;
-
-	/* setup GP Timer 1 */
-	writel(GPTCR_SWR, &gpt->ctrl);
-	for (i = 0; i < 100; i++)
-		writel(0, &gpt->ctrl);	/* We have no udelay by now */
-
-	writel(GPTPR_VAL, &gpt->pre);
-	/* Freerun Mode, PERCLK1 input */
-	writel(readl(&gpt->ctrl) |
-		GPTCR_CLKSOURCE_IPG | GPTCR_TEN,
-		&gpt->ctrl);
-
-	return 0;
-}
-
-void reset_timer_masked(void)
-{
-	struct gpt_regs *gpt = (struct gpt_regs *)GPT1_BASE_ADDR;
-
-	writel(0, &gpt->ctrl);
-	/* Freerun Mode, PERCLK1 input */
-	writel(GPTCR_CLKSOURCE_IPG | GPTCR_TEN,
-		&gpt->ctrl);
-}
-
-inline ulong get_timer_masked(void)
-{
-
-	struct gpt_regs *gpt = (struct gpt_regs *)GPT1_BASE_ADDR;
-	ulong val = readl(&gpt->counter);
-
-	return val;
-}
-
-void reset_timer(void)
-{
-	reset_timer_masked();
-}
-
-ulong get_timer(ulong base)
-{
-	ulong tmp;
-
-	tmp = get_timer_masked();
-
-	if (tmp <= (base * 1000)) {
-		/* Overflow */
-		tmp += (0xffffffff -  base);
-	}
-
-	return (tmp / 1000) - base;
-}
-
-void set_timer(ulong t)
-{
-}
-
-/*
- * delay x useconds AND preserve advance timstamp value
- * GPTCNT is now supposed to tick 1 by 1 us.
- */
-void __udelay(unsigned long usec)
-{
-	ulong tmp;
-
-	tmp = get_timer_masked();	/* get current timestamp */
-
-	/* if setting this forward will roll time stamp */
-	if ((usec + tmp + 1) < tmp) {
-		/* reset "advancing" timestamp to 0, set lastinc value */
-		reset_timer_masked();
-	} else {
-		/* else, set advancing stamp wake up time */
-		tmp += usec;
-	}
-
-	while (get_timer_masked() < tmp)	/* loop till event */
-		 /*NOP*/;
-}
diff --git a/arch/arm/cpu/arm1136/omap24xx/Makefile b/arch/arm/cpu/arm1136/omap24xx/Makefile
deleted file mode 100644
index 0776101..0000000
--- a/arch/arm/cpu/arm1136/omap24xx/Makefile
+++ /dev/null
@@ -1,47 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(SOC).o
-
-SOBJS	= reset.o
-
-COBJS	= timer.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
-
-all:	$(obj).depend $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/arch/arm/cpu/arm1136/omap24xx/reset.S b/arch/arm/cpu/arm1136/omap24xx/reset.S
deleted file mode 100644
index 5f8343f..0000000
--- a/arch/arm/cpu/arm1136/omap24xx/reset.S
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- *  armboot - Startup Code for OMP2420/ARM1136 CPU-core
- *
- *  Copyright (c) 2004	Texas Instruments <r-woodruff2@ti.com>
- *
- *  Copyright (c) 2001	Marius Gröger <mag@sysgo.de>
- *  Copyright (c) 2002	Alex Züpke <azu@sysgo.de>
- *  Copyright (c) 2002	Gary Jennejohn <garyj@denx.de>
- *  Copyright (c) 2003	Richard Woodruff <r-woodruff2@ti.com>
- *  Copyright (c) 2003	Kshitij <kshitij@ti.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <asm/arch/omap2420.h>
-
-.globl reset_cpu
-reset_cpu:
-	ldr	r1, rstctl	/* get addr for global reset reg */
-	mov	r3, #0x2	/* full reset pll+mpu */
-	str	r3, [r1]	/* force reset */
-	mov	r0, r0
-_loop_forever:
-	b	_loop_forever
-rstctl:
-	.word	PM_RSTCTRL_WKUP
diff --git a/arch/arm/cpu/arm1136/omap24xx/timer.c b/arch/arm/cpu/arm1136/omap24xx/timer.c
deleted file mode 100644
index 228ceba..0000000
--- a/arch/arm/cpu/arm1136/omap24xx/timer.c
+++ /dev/null
@@ -1,157 +0,0 @@
-/*
- * (C) Copyright 2004
- * Texas Instruments
- * Richard Woodruff <r-woodruff2@ti.com>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- * Alex Zuepke <azu@sysgo.de>
- *
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/arch/bits.h>
-#include <asm/arch/omap2420.h>
-
-#define TIMER_LOAD_VAL 0
-
-/* macro to read the 32 bit timer */
-#define READ_TIMER (*((volatile ulong *)(CONFIG_SYS_TIMERBASE+TCRR)))
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int timer_init (void)
-{
-	int32_t val;
-
-	/* Start the counter ticking up */
-	*((int32_t *) (CONFIG_SYS_TIMERBASE + TLDR)) = TIMER_LOAD_VAL;	/* reload value on overflow*/
-	val = (CONFIG_SYS_PTV << 2) | BIT5 | BIT1 | BIT0;		/* mask to enable timer*/
-	*((int32_t *) (CONFIG_SYS_TIMERBASE + TCLR)) = val;	/* start timer */
-
-	reset_timer_masked(); /* init the timestamp and lastinc value */
-
-	return(0);
-}
-/*
- * timer without interrupts
- */
-void reset_timer (void)
-{
-	reset_timer_masked ();
-}
-
-ulong get_timer (ulong base)
-{
-	return get_timer_masked () - base;
-}
-
-void set_timer (ulong t)
-{
-	gd->tbl	= t;
-}
-
-/* delay x useconds AND preserve advance timestamp value */
-void __udelay (unsigned long usec)
-{
-	ulong tmo, tmp;
-
-	if (usec >= 1000) {		/* if "big" number, spread normalization to seconds */
-		tmo = usec / 1000;	/* start to normalize for usec to ticks per sec */
-		tmo *= CONFIG_SYS_HZ;	/* find number of "ticks" to wait to achieve target */
-		tmo /= 1000;		/* finish normalize. */
-	} else {			/* else small number, don't kill it prior to HZ multiply */
-		tmo = usec * CONFIG_SYS_HZ;
-		tmo /= (1000*1000);
-	}
-
-	tmp = get_timer (0);		/* get current timestamp */
-	if ( (tmo + tmp + 1) < tmp )	/* if setting this forward will roll time stamp */
-		reset_timer_masked ();	/* reset "advancing" timestamp to 0, set lastinc value */
-	else
-		tmo	+= tmp;		/* else, set advancing stamp wake up time */
-	while (get_timer_masked () < tmo)/* loop till event */
-		/*NOP*/;
-}
-
-void reset_timer_masked (void)
-{
-	/* reset time */
-	gd->lastinc = READ_TIMER;	/* capture current incrementer value time */
-	gd->tbl = 0;			/* start "advancing" time stamp from 0 */
-}
-
-ulong get_timer_masked (void)
-{
-	ulong now = READ_TIMER;		/* current tick value */
-
-	if (now >= gd->lastinc)		/* normal mode (non roll) */
-		gd->tbl += (now - gd->lastinc); /* move stamp fordward with absoulte diff ticks */
-	else				/* we have rollover of incrementer */
-		gd->tbl += (0xFFFFFFFF - gd->lastinc) + now;
-	gd->lastinc = now;
-	return gd->tbl;
-}
-
-/* waits specified delay value and resets timestamp */
-void udelay_masked (unsigned long usec)
-{
-	ulong tmo;
-	ulong endtime;
-	signed long diff;
-
-	if (usec >= 1000) {			/* if "big" number, spread normalization to seconds */
-		tmo = usec / 1000;		/* start to normalize for usec to ticks per sec */
-		tmo *= CONFIG_SYS_HZ;			/* find number of "ticks" to wait to achieve target */
-		tmo /= 1000;			/* finish normalize. */
-	} else {					/* else small number, don't kill it prior to HZ multiply */
-		tmo = usec * CONFIG_SYS_HZ;
-		tmo /= (1000*1000);
-	}
-	endtime = get_timer_masked () + tmo;
-
-	do {
-		ulong now = get_timer_masked ();
-		diff = endtime - now;
-	} while (diff >= 0);
-}
-
-/*
- * This function is derived from PowerPC code (read timebase as long long).
- * On ARM it just returns the timer value.
- */
-unsigned long long get_ticks(void)
-{
-	return get_timer(0);
-}
-/*
- * This function is derived from PowerPC code (timebase clock frequency).
- * On ARM it returns the number of timer ticks per second.
- */
-ulong get_tbclk (void)
-{
-	ulong tbclk;
-	tbclk = CONFIG_SYS_HZ;
-	return tbclk;
-}
diff --git a/arch/arm/cpu/arm1136/start.S b/arch/arm/cpu/arm1136/start.S
deleted file mode 100644
index a05d36d..0000000
--- a/arch/arm/cpu/arm1136/start.S
+++ /dev/null
@@ -1,518 +0,0 @@
-/*
- *  armboot - Startup Code for OMP2420/ARM1136 CPU-core
- *
- *  Copyright (c) 2004	Texas Instruments <r-woodruff2@ti.com>
- *
- *  Copyright (c) 2001	Marius Gröger <mag@sysgo.de>
- *  Copyright (c) 2002	Alex Züpke <azu@sysgo.de>
- *  Copyright (c) 2002	Gary Jennejohn <garyj@denx.de>
- *  Copyright (c) 2003	Richard Woodruff <r-woodruff2@ti.com>
- *  Copyright (c) 2003	Kshitij <kshitij@ti.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <asm-offsets.h>
-#include <config.h>
-#include <version.h>
-.globl _start
-_start: b	reset
-#ifdef CONFIG_PRELOADER
-	ldr	pc, _hang
-	ldr	pc, _hang
-	ldr	pc, _hang
-	ldr	pc, _hang
-	ldr	pc, _hang
-	ldr	pc, _hang
-	ldr	pc, _hang
-
-_hang:
-	.word	do_hang
-	.word	0x12345678
-	.word	0x12345678
-	.word	0x12345678
-	.word	0x12345678
-	.word	0x12345678
-	.word	0x12345678
-	.word	0x12345678	/* now 16*4=64 */
-#else
-	ldr	pc, _undefined_instruction
-	ldr	pc, _software_interrupt
-	ldr	pc, _prefetch_abort
-	ldr	pc, _data_abort
-	ldr	pc, _not_used
-	ldr	pc, _irq
-	ldr	pc, _fiq
-
-_undefined_instruction: .word undefined_instruction
-_software_interrupt:	.word software_interrupt
-_prefetch_abort:	.word prefetch_abort
-_data_abort:		.word data_abort
-_not_used:		.word not_used
-_irq:			.word irq
-_fiq:			.word fiq
-_pad:			.word 0x12345678 /* now 16*4=64 */
-#endif	/* CONFIG_PRELOADER */
-.global _end_vect
-_end_vect:
-
-	.balignl 16,0xdeadbeef
-/*
- *************************************************************************
- *
- * Startup Code (reset vector)
- *
- * do important init only if we don't start from memory!
- * setup Memory and board specific bits prior to relocation.
- * relocate armboot to ram
- * setup stack
- *
- *************************************************************************
- */
-
-.globl _TEXT_BASE
-_TEXT_BASE:
-	.word	CONFIG_SYS_TEXT_BASE
-
-/*
- * These are defined in the board-specific linker script.
- * Subtracting _start from them lets the linker put their
- * relative position in the executable instead of leaving
- * them null.
- */
-.globl _bss_start_ofs
-_bss_start_ofs:
-	.word __bss_start - _start
-
-.globl _bss_end_ofs
-_bss_end_ofs:
-	.word _end - _start
-
-#ifdef CONFIG_USE_IRQ
-/* IRQ stack memory (calculated at run-time) */
-.globl IRQ_STACK_START
-IRQ_STACK_START:
-	.word	0x0badc0de
-
-/* IRQ stack memory (calculated at run-time) */
-.globl FIQ_STACK_START
-FIQ_STACK_START:
-	.word 0x0badc0de
-#endif
-
-/* IRQ stack memory (calculated at run-time) + 8 bytes */
-.globl IRQ_STACK_START_IN
-IRQ_STACK_START_IN:
-	.word	0x0badc0de
-
-/*
- * the actual reset code
- */
-
-reset:
-	/*
-	 * set the cpu to SVC32 mode
-	 */
-	mrs	r0,cpsr
-	bic	r0,r0,#0x1f
-	orr	r0,r0,#0xd3
-	msr	cpsr,r0
-
-#ifdef CONFIG_OMAP2420H4
-       /* Copy vectors to mask ROM indirect addr */
-	adr	r0, _start		/* r0 <- current position of code   */
-		add     r0, r0, #4				/* skip reset vector			*/
-	mov	r2, #64			/* r2 <- size to copy  */
-	add	r2, r0, r2		/* r2 <- source end address	    */
-	mov	r1, #SRAM_OFFSET0	  /* build vect addr */
-	mov	r3, #SRAM_OFFSET1
-	add	r1, r1, r3
-	mov	r3, #SRAM_OFFSET2
-	add	r1, r1, r3
-next:
-	ldmia	r0!, {r3-r10}		/* copy from source address [r0]    */
-	stmia	r1!, {r3-r10}		/* copy to   target address [r1]    */
-	cmp	r0, r2			/* until source end address [r2]    */
-	bne	next			/* loop until equal */
-	bl	cpy_clk_code		/* put dpll adjust code behind vectors */
-#endif
-	/* the mask ROM code should have PLL and others stable */
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
-	bl  cpu_init_crit
-#endif
-
-/* Set stackpointer in internal RAM to call board_init_f */
-call_board_init_f:
-	ldr	sp, =(CONFIG_SYS_INIT_SP_ADDR)
-	bic	sp, sp, #7 /* 8-byte alignment for ABI compliance */
-	ldr	r0,=0x00000000
-
-	bl	board_init_f
-
-/*------------------------------------------------------------------------------*/
-
-/*
- * void relocate_code (addr_sp, gd, addr_moni)
- *
- * This "function" does not return, instead it continues in RAM
- * after relocating the monitor code.
- *
- */
-	.globl	relocate_code
-relocate_code:
-	mov	r4, r0	/* save addr_sp */
-	mov	r5, r1	/* save addr of gd */
-	mov	r6, r2	/* save addr of destination */
-
-	/* Set up the stack						    */
-stack_setup:
-	mov	sp, r4
-
-	adr	r0, _start
-	cmp	r0, r6
-	beq	clear_bss		/* skip relocation */
-	mov	r1, r6			/* r1 <- scratch for copy_loop */
-	ldr	r3, _bss_start_ofs
-	add	r2, r0, r3		/* r2 <- source end address	    */
-
-copy_loop:
-	ldmia	r0!, {r9-r10}		/* copy from source address [r0]    */
-	stmia	r1!, {r9-r10}		/* copy to   target address [r1]    */
-	cmp	r0, r2			/* until source end address [r2]    */
-	blo	copy_loop
-
-#ifndef CONFIG_PRELOADER
-	/*
-	 * fix .rel.dyn relocations
-	 */
-	ldr	r0, _TEXT_BASE		/* r0 <- Text base */
-	sub	r9, r6, r0		/* r9 <- relocation offset */
-	ldr	r10, _dynsym_start_ofs	/* r10 <- sym table ofs */
-	add	r10, r10, r0		/* r10 <- sym table in FLASH */
-	ldr	r2, _rel_dyn_start_ofs	/* r2 <- rel dyn start ofs */
-	add	r2, r2, r0		/* r2 <- rel dyn start in FLASH */
-	ldr	r3, _rel_dyn_end_ofs	/* r3 <- rel dyn end ofs */
-	add	r3, r3, r0		/* r3 <- rel dyn end in FLASH */
-fixloop:
-	ldr	r0, [r2]		/* r0 <- location to fix up, IN FLASH! */
-	add	r0, r0, r9		/* r0 <- location to fix up in RAM */
-	ldr	r1, [r2, #4]
-	and	r7, r1, #0xff
-	cmp	r7, #23			/* relative fixup? */
-	beq	fixrel
-	cmp	r7, #2			/* absolute fixup? */
-	beq	fixabs
-	/* ignore unknown type of fixup */
-	b	fixnext
-fixabs:
-	/* absolute fix: set location to (offset) symbol value */
-	mov	r1, r1, LSR #4		/* r1 <- symbol index in .dynsym */
-	add	r1, r10, r1		/* r1 <- address of symbol in table */
-	ldr	r1, [r1, #4]		/* r1 <- symbol value */
-	add	r1, r1, r9		/* r1 <- relocated sym addr */
-	b	fixnext
-fixrel:
-	/* relative fix: increase location by offset */
-	ldr	r1, [r0]
-	add	r1, r1, r9
-fixnext:
-	str	r1, [r0]
-	add	r2, r2, #8		/* each rel.dyn entry is 8 bytes */
-	cmp	r2, r3
-	blo	fixloop
-#endif
-
-clear_bss:
-#ifndef CONFIG_PRELOADER
-	ldr	r0, _bss_start_ofs
-	ldr	r1, _bss_end_ofs
-	mov	r4, r6			/* reloc addr */
-	add	r0, r0, r4
-	add	r1, r1, r4
-	mov	r2, #0x00000000		/* clear			    */
-
-clbss_l:str	r2, [r0]		/* clear loop...		    */
-	add	r0, r0, #4
-	cmp	r0, r1
-	bne	clbss_l
-#endif	/* #ifndef CONFIG_PRELOADER */
-
-/*
- * We are done. Do not return, instead branch to second part of board
- * initialization, now running from RAM.
- */
-#ifdef CONFIG_NAND_SPL
-	ldr     r0, _nand_boot_ofs
-	mov	pc, r0
-
-_nand_boot_ofs:
-	.word nand_boot
-#else
-jump_2_ram:
-	ldr	r0, _board_init_r_ofs
-	ldr     r1, _TEXT_BASE
-	add	lr, r0, r1
-	add	lr, lr, r9
-	/* setup parameters for board_init_r */
-	mov	r0, r5		/* gd_t */
-	mov	r1, r6		/* dest_addr */
-	/* jump to it ... */
-	mov	pc, lr
-
-_board_init_r_ofs:
-	.word board_init_r - _start
-#endif
-
-_rel_dyn_start_ofs:
-	.word __rel_dyn_start - _start
-_rel_dyn_end_ofs:
-	.word __rel_dyn_end - _start
-_dynsym_start_ofs:
-	.word __dynsym_start - _start
-
-/*
- *************************************************************************
- *
- * CPU_init_critical registers
- *
- * setup important registers
- * setup memory timing
- *
- *************************************************************************
- */
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
-cpu_init_crit:
-	/*
-	 * flush v4 I/D caches
-	 */
-	mov	r0, #0
-	mcr	p15, 0, r0, c7, c7, 0	/* Invalidate I+D+BTB caches */
-	mcr	p15, 0, r0, c8, c7, 0	/* Invalidate Unified TLB */
-
-	/*
-	 * disable MMU stuff and caches
-	 */
-	mrc	p15, 0, r0, c1, c0, 0
-	bic	r0, r0, #0x00002300	@ clear bits 13, 9:8 (--V- --RS)
-	bic	r0, r0, #0x00000087	@ clear bits 7, 2:0 (B--- -CAM)
-	orr	r0, r0, #0x00000002	@ set bit 2 (A) Align
-	orr	r0, r0, #0x00001000	@ set bit 12 (I) I-Cache
-	mcr	p15, 0, r0, c1, c0, 0
-
-	/*
-	 * Jump to board specific initialization... The Mask ROM will have already initialized
-	 * basic memory.  Go here to bump up clock rate and handle wake up conditions.
-	 */
-	mov	ip, lr		/* persevere link reg across call */
-	bl	lowlevel_init	/* go setup pll,mux,memory */
-	mov	lr, ip		/* restore link */
-	mov	pc, lr		/* back to my caller */
-#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
-
-#ifndef CONFIG_PRELOADER
-/*
- *************************************************************************
- *
- * Interrupt handling
- *
- *************************************************************************
- */
-@
-@ IRQ stack frame.
-@
-#define S_FRAME_SIZE	72
-
-#define S_OLD_R0	68
-#define S_PSR		64
-#define S_PC		60
-#define S_LR		56
-#define S_SP		52
-
-#define S_IP		48
-#define S_FP		44
-#define S_R10		40
-#define S_R9		36
-#define S_R8		32
-#define S_R7		28
-#define S_R6		24
-#define S_R5		20
-#define S_R4		16
-#define S_R3		12
-#define S_R2		8
-#define S_R1		4
-#define S_R0		0
-
-#define MODE_SVC 0x13
-#define I_BIT	 0x80
-
-/*
- * use bad_save_user_regs for abort/prefetch/undef/swi ...
- * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
- */
-
-	.macro	bad_save_user_regs
-	sub	sp, sp, #S_FRAME_SIZE		@ carve out a frame on current user stack
-	stmia	sp, {r0 - r12}			@ Save user registers (now in svc mode) r0-r12
-
-	ldr	r2, IRQ_STACK_START_IN		@ set base 2 words into abort stack
-	ldmia	r2, {r2 - r3}			@ get values for "aborted" pc and cpsr (into parm regs)
-	add	r0, sp, #S_FRAME_SIZE		@ grab pointer to old stack
-
-	add	r5, sp, #S_SP
-	mov	r1, lr
-	stmia	r5, {r0 - r3}			@ save sp_SVC, lr_SVC, pc, cpsr
-	mov	r0, sp				@ save current stack into r0 (param register)
-	.endm
-
-	.macro	irq_save_user_regs
-	sub	sp, sp, #S_FRAME_SIZE
-	stmia	sp, {r0 - r12}			@ Calling r0-r12
-	add	r8, sp, #S_PC			@ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good.
-	stmdb	r8, {sp, lr}^			@ Calling SP, LR
-	str	lr, [r8, #0]			@ Save calling PC
-	mrs	r6, spsr
-	str	r6, [r8, #4]			@ Save CPSR
-	str	r0, [r8, #8]			@ Save OLD_R0
-	mov	r0, sp
-	.endm
-
-	.macro	irq_restore_user_regs
-	ldmia	sp, {r0 - lr}^			@ Calling r0 - lr
-	mov	r0, r0
-	ldr	lr, [sp, #S_PC]			@ Get PC
-	add	sp, sp, #S_FRAME_SIZE
-	subs	pc, lr, #4			@ return & move spsr_svc into cpsr
-	.endm
-
-	.macro get_bad_stack
-	ldr	r13, IRQ_STACK_START_IN		@ setup our mode stack (enter in banked mode)
-
-	str	lr, [r13]			@ save caller lr in position 0 of saved stack
-	mrs	lr, spsr			@ get the spsr
-	str	lr, [r13, #4]			@ save spsr in position 1 of saved stack
-
-	mov	r13, #MODE_SVC			@ prepare SVC-Mode
-	@ msr	spsr_c, r13
-	msr	spsr, r13			@ switch modes, make sure moves will execute
-	mov	lr, pc				@ capture return pc
-	movs	pc, lr				@ jump to next instruction & switch modes.
-	.endm
-
-	.macro get_bad_stack_swi
-	sub	r13, r13, #4			@ space on current stack for scratch reg.
-	str	r0, [r13]			@ save R0's value.
-	ldr	r0, IRQ_STACK_START_IN		@ get data regions start
-	str	lr, [r0]			@ save caller lr in position 0 of saved stack
-	mrs	r0, spsr			@ get the spsr
-	str	lr, [r0, #4]			@ save spsr in position 1 of saved stack
-	ldr	r0, [r13]			@ restore r0
-	add	r13, r13, #4			@ pop stack entry
-	.endm
-
-	.macro get_irq_stack			@ setup IRQ stack
-	ldr	sp, IRQ_STACK_START
-	.endm
-
-	.macro get_fiq_stack			@ setup FIQ stack
-	ldr	sp, FIQ_STACK_START
-	.endm
-#endif	/* CONFIG_PRELOADER */
-
-/*
- * exception handlers
- */
-#ifdef CONFIG_PRELOADER
-	.align	5
-do_hang:
-	ldr	sp, _TEXT_BASE			/* use 32 words about stack */
-	bl	hang				/* hang and never return */
-#else	/* !CONFIG_PRELOADER */
-	.align	5
-undefined_instruction:
-	get_bad_stack
-	bad_save_user_regs
-	bl	do_undefined_instruction
-
-	.align	5
-software_interrupt:
-	get_bad_stack_swi
-	bad_save_user_regs
-	bl	do_software_interrupt
-
-	.align	5
-prefetch_abort:
-	get_bad_stack
-	bad_save_user_regs
-	bl	do_prefetch_abort
-
-	.align	5
-data_abort:
-	get_bad_stack
-	bad_save_user_regs
-	bl	do_data_abort
-
-	.align	5
-not_used:
-	get_bad_stack
-	bad_save_user_regs
-	bl	do_not_used
-
-#ifdef CONFIG_USE_IRQ
-
-	.align	5
-irq:
-	get_irq_stack
-	irq_save_user_regs
-	bl	do_irq
-	irq_restore_user_regs
-
-	.align	5
-fiq:
-	get_fiq_stack
-	/* someone ought to write a more effiction fiq_save_user_regs */
-	irq_save_user_regs
-	bl	do_fiq
-	irq_restore_user_regs
-
-#else
-
-	.align	5
-irq:
-	get_bad_stack
-	bad_save_user_regs
-	bl	do_irq
-
-	.align	5
-fiq:
-	get_bad_stack
-	bad_save_user_regs
-	bl	do_fiq
-
-#endif
-	.align 5
-.global arm1136_cache_flush
-arm1136_cache_flush:
-#if !defined(CONFIG_SYS_NO_ICACHE)
-		mcr	p15, 0, r1, c7, c5, 0	@ invalidate I cache
-#endif
-#if !defined(CONFIG_SYS_NO_DCACHE)
-		mcr	p15, 0, r1, c7, c14, 0	@ invalidate D cache
-#endif
-		mov	pc, lr			@ back to caller
-#endif	/* CONFIG_PRELOADER */
diff --git a/arch/arm/cpu/arm1136/u-boot.lds b/arch/arm/cpu/arm1136/u-boot.lds
deleted file mode 100644
index 253adbe..0000000
--- a/arch/arm/cpu/arm1136/u-boot.lds
+++ /dev/null
@@ -1,87 +0,0 @@
-/*
- * (C) Copyright 2009
- * Ilya Yanok, Emcraft Systems Ltd, <yanok@emcraft.com>
- *
- * Copyright (C) 2005-2007 Samsung Electronics
- * Kyungin Park <kyugnmin.park@samsung.com>
- *
- * Copyright (c) 2004 Texas Instruments
- *
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-ENTRY(_start)
-SECTIONS
-{
-	. = 0x00000000;
-
-	. = ALIGN(4);
-	.text :
-	{
-		arch/arm/cpu/arm1136/start.o	(.text)
-		*(.text)
-	}
-
-	. = ALIGN(4);
-	.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
-
-	. = ALIGN(4);
-	.data : {
-		*(.data)
-	}
-
-	. = ALIGN(4);
-
-	. = .;
-	__u_boot_cmd_start = .;
-	.u_boot_cmd : { *(.u_boot_cmd) }
-	__u_boot_cmd_end = .;
-
-	. = ALIGN(4);
-
-	.rel.dyn : {
-		__rel_dyn_start = .;
-		*(.rel*)
-		__rel_dyn_end = .;
-	}
-
-	.dynsym : {
-		__dynsym_start = .;
-		*(.dynsym)
-	}
-
-	.bss __rel_dyn_start (OVERLAY) : {
-		__bss_start = .;
-		*(.bss)
-		 . = ALIGN(4);
-		_end = .;
-	}
-
-	/DISCARD/ : { *(.dynstr*) }
-	/DISCARD/ : { *(.dynamic*) }
-	/DISCARD/ : { *(.plt*) }
-	/DISCARD/ : { *(.interp*) }
-	/DISCARD/ : { *(.gnu*) }
-}
diff --git a/arch/arm/cpu/arm1176/Makefile b/arch/arm/cpu/arm1176/Makefile
deleted file mode 100644
index 7ec869b..0000000
--- a/arch/arm/cpu/arm1176/Makefile
+++ /dev/null
@@ -1,50 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# (C) Copyright 2008
-# Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(CPU).o
-
-START	= start.o
-COBJS	= cpu.o
-
-SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS) $(SOBJS))
-START	:= $(addprefix $(obj),$(START))
-
-all:	$(obj).depend $(START) $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/arch/arm/cpu/arm1176/config.mk b/arch/arm/cpu/arm1176/config.mk
deleted file mode 100644
index 14346cf..0000000
--- a/arch/arm/cpu/arm1176/config.mk
+++ /dev/null
@@ -1,32 +0,0 @@
-#
-# (C) Copyright 2002
-# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float
-
-# Make ARMv5 to allow more compilers to work, even though its v6.
-PLATFORM_CPPFLAGS += -march=armv5t
-# =========================================================================
-#
-# Supply options according to compiler version
-#
-# =========================================================================
-PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))
diff --git a/arch/arm/cpu/arm1176/cpu.c b/arch/arm/cpu/arm1176/cpu.c
deleted file mode 100644
index c0fd114..0000000
--- a/arch/arm/cpu/arm1176/cpu.c
+++ /dev/null
@@ -1,67 +0,0 @@
-/*
- * (C) Copyright 2004 Texas Insturments
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * CPU specific code
- */
-
-#include <common.h>
-#include <command.h>
-#include <asm/system.h>
-
-static void cache_flush (void);
-
-int cleanup_before_linux (void)
-{
-	/*
-	 * this function is called just before we call linux
-	 * it prepares the processor for linux
-	 *
-	 * we turn off caches etc ...
-	 */
-
-	disable_interrupts ();
-
-	/* turn off I/D-cache */
-	icache_disable();
-	dcache_disable();
-	/* flush I/D-cache */
-	cache_flush();
-
-	return 0;
-}
-
-/* flush I/D-cache */
-static void cache_flush (void)
-{
-	/* invalidate both caches and flush btb */
-	asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (0));
-	/* mem barrier to sync things */
-	asm ("mcr p15, 0, %0, c7, c10, 4": :"r" (0));
-}
diff --git a/arch/arm/cpu/arm1176/s3c64xx/Makefile b/arch/arm/cpu/arm1176/s3c64xx/Makefile
deleted file mode 100644
index 0785b19..0000000
--- a/arch/arm/cpu/arm1176/s3c64xx/Makefile
+++ /dev/null
@@ -1,50 +0,0 @@
-#
-# (C) Copyright 2000-2003
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# (C) Copyright 2008
-# Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(SOC).o
-
-SOBJS	= reset.o
-
-COBJS-$(CONFIG_S3C6400)	+= cpu_init.o speed.o
-COBJS-y	+= timer.o
-
-OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS-y))
-
-all:	$(obj).depend $(START) $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/arch/arm/cpu/arm1176/s3c64xx/config.mk b/arch/arm/cpu/arm1176/s3c64xx/config.mk
deleted file mode 100644
index 14346cf..0000000
--- a/arch/arm/cpu/arm1176/s3c64xx/config.mk
+++ /dev/null
@@ -1,32 +0,0 @@
-#
-# (C) Copyright 2002
-# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float
-
-# Make ARMv5 to allow more compilers to work, even though its v6.
-PLATFORM_CPPFLAGS += -march=armv5t
-# =========================================================================
-#
-# Supply options according to compiler version
-#
-# =========================================================================
-PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))
diff --git a/arch/arm/cpu/arm1176/s3c64xx/cpu_init.S b/arch/arm/cpu/arm1176/s3c64xx/cpu_init.S
deleted file mode 100644
index df88cba..0000000
--- a/arch/arm/cpu/arm1176/s3c64xx/cpu_init.S
+++ /dev/null
@@ -1,135 +0,0 @@
-/*
- * Originates from Samsung's u-boot 1.1.6 port to S3C6400 / SMDK6400
- *
- * Copyright (C) 2008
- * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <asm/arch/s3c6400.h>
-
-	.globl mem_ctrl_asm_init
-mem_ctrl_asm_init:
-	/* DMC1 base address 0x7e001000 */
-	ldr	r0, =ELFIN_DMC1_BASE
-
-	ldr	r1, =0x4
-	str	r1, [r0, #INDEX_DMC_MEMC_CMD]
-
-	ldr	r1, =DMC_DDR_REFRESH_PRD
-	str	r1, [r0, #INDEX_DMC_REFRESH_PRD]
-
-	ldr	r1, =DMC_DDR_CAS_LATENCY
-	str	r1, [r0, #INDEX_DMC_CAS_LATENCY]
-
-	ldr	r1, =DMC_DDR_t_DQSS
-	str	r1, [r0, #INDEX_DMC_T_DQSS]
-
-	ldr	r1, =DMC_DDR_t_MRD
-	str	r1, [r0, #INDEX_DMC_T_MRD]
-
-	ldr	r1, =DMC_DDR_t_RAS
-	str	r1, [r0, #INDEX_DMC_T_RAS]
-
-	ldr	r1, =DMC_DDR_t_RC
-	str	r1, [r0, #INDEX_DMC_T_RC]
-
-	ldr	r1, =DMC_DDR_t_RCD
-	ldr	r2, =DMC_DDR_schedule_RCD
-	orr	r1, r1, r2
-	str	r1, [r0, #INDEX_DMC_T_RCD]
-
-	ldr	r1, =DMC_DDR_t_RFC
-	ldr	r2, =DMC_DDR_schedule_RFC
-	orr	r1, r1, r2
-	str	r1, [r0, #INDEX_DMC_T_RFC]
-
-	ldr	r1, =DMC_DDR_t_RP
-	ldr	r2, =DMC_DDR_schedule_RP
-	orr	r1, r1, r2
-	str	r1, [r0, #INDEX_DMC_T_RP]
-
-	ldr	r1, =DMC_DDR_t_RRD
-	str	r1, [r0, #INDEX_DMC_T_RRD]
-
-	ldr	r1, =DMC_DDR_t_WR
-	str	r1, [r0, #INDEX_DMC_T_WR]
-
-	ldr	r1, =DMC_DDR_t_WTR
-	str	r1, [r0, #INDEX_DMC_T_WTR]
-
-	ldr	r1, =DMC_DDR_t_XP
-	str	r1, [r0, #INDEX_DMC_T_XP]
-
-	ldr	r1, =DMC_DDR_t_XSR
-	str	r1, [r0, #INDEX_DMC_T_XSR]
-
-	ldr	r1, =DMC_DDR_t_ESR
-	str	r1, [r0, #INDEX_DMC_T_ESR]
-
-	ldr	r1, =DMC1_MEM_CFG
-	str	r1, [r0, #INDEX_DMC_MEMORY_CFG]
-
-	ldr	r1, =DMC1_MEM_CFG2
-	str	r1, [r0, #INDEX_DMC_MEMORY_CFG2]
-
-	ldr	r1, =DMC1_CHIP0_CFG
-	str	r1, [r0, #INDEX_DMC_CHIP_0_CFG]
-
-	ldr	r1, =DMC_DDR_32_CFG
-	str	r1, [r0, #INDEX_DMC_USER_CONFIG]
-
-	/* DMC0 DDR Chip 0 configuration direct command reg */
-	ldr	r1, =DMC_NOP0
-	str	r1, [r0, #INDEX_DMC_DIRECT_CMD]
-
-	/* Precharge All */
-	ldr	r1, =DMC_PA0
-	str	r1, [r0, #INDEX_DMC_DIRECT_CMD]
-
-	/* Auto Refresh 2 time */
-	ldr	r1, =DMC_AR0
-	str	r1, [r0, #INDEX_DMC_DIRECT_CMD]
-	str	r1, [r0, #INDEX_DMC_DIRECT_CMD]
-
-	/* MRS */
-	ldr	r1, =DMC_mDDR_EMR0
-	str	r1, [r0, #INDEX_DMC_DIRECT_CMD]
-
-	/* Mode Reg */
-	ldr	r1, =DMC_mDDR_MR0
-	str	r1, [r0, #INDEX_DMC_DIRECT_CMD]
-
-	/* Enable DMC1 */
-	mov	r1, #0x0
-	str	r1, [r0, #INDEX_DMC_MEMC_CMD]
-
-check_dmc1_ready:
-	ldr	r1, [r0, #INDEX_DMC_MEMC_STATUS]
-	mov	r2, #0x3
-	and	r1, r1, r2
-	cmp	r1, #0x1
-	bne	check_dmc1_ready
-	nop
-
-	mov	pc, lr
-
-	.ltorg
diff --git a/arch/arm/cpu/arm1176/s3c64xx/reset.S b/arch/arm/cpu/arm1176/s3c64xx/reset.S
deleted file mode 100644
index eae572e..0000000
--- a/arch/arm/cpu/arm1176/s3c64xx/reset.S
+++ /dev/null
@@ -1,34 +0,0 @@
-/*
- * Copyright (c) 2009 Samsung Electronics.
- * Minkyu Kang <mk7.kang@samsung.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <asm/arch/s3c6400.h>
-
-.globl reset_cpu
-reset_cpu:
-	ldr	r1, =ELFIN_CLOCK_POWER_BASE
-	ldr	r2, [r1, #SYS_ID_OFFSET]
-	ldr	r3, =0xffff
-	and	r2, r3, r2, lsr #12
-	str	r2, [r1, #SW_RST_OFFSET]
-_loop_forever:
-	b	_loop_forever
diff --git a/arch/arm/cpu/arm1176/s3c64xx/speed.c b/arch/arm/cpu/arm1176/s3c64xx/speed.c
deleted file mode 100644
index 11962ac..0000000
--- a/arch/arm/cpu/arm1176/s3c64xx/speed.c
+++ /dev/null
@@ -1,145 +0,0 @@
-/*
- * (C) Copyright 2001-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2002
- * David Mueller, ELSOFT AG, d.mueller@elsoft.ch
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * This code should work for both the S3C2400 and the S3C2410
- * as they seem to have the same PLL and clock machinery inside.
- * The different address mapping is handled by the s3c24xx.h files below.
- */
-
-#include <common.h>
-#include <asm/arch/s3c6400.h>
-
-#define APLL 0
-#define MPLL 1
-#define EPLL 2
-
-/* ------------------------------------------------------------------------- */
-/*
- * NOTE: This describes the proper use of this file.
- *
- * CONFIG_SYS_CLK_FREQ should be defined as the input frequency of the PLL.
- *
- * get_FCLK(), get_HCLK(), get_PCLK() and get_UCLK() return the clock of
- * the specified bus in HZ.
- */
-/* ------------------------------------------------------------------------- */
-
-static ulong get_PLLCLK(int pllreg)
-{
-	ulong r, m, p, s;
-
-	switch (pllreg) {
-	case APLL:
-		r = APLL_CON_REG;
-		break;
-	case MPLL:
-		r = MPLL_CON_REG;
-		break;
-	case EPLL:
-		r = EPLL_CON0_REG;
-		break;
-	default:
-		hang();
-	}
-
-	m = (r >> 16) & 0x3ff;
-	p = (r >> 8) & 0x3f;
-	s = r & 0x7;
-
-	return m * (CONFIG_SYS_CLK_FREQ / (p * (1 << s)));
-}
-
-/* return ARMCORE frequency */
-ulong get_ARMCLK(void)
-{
-	ulong div;
-
-	div = CLK_DIV0_REG;
-
-	return get_PLLCLK(APLL) / ((div & 0x7) + 1);
-}
-
-/* return FCLK frequency */
-ulong get_FCLK(void)
-{
-	return get_PLLCLK(APLL);
-}
-
-/* return HCLK frequency */
-ulong get_HCLK(void)
-{
-	ulong fclk;
-
-	uint hclkx2_div = ((CLK_DIV0_REG >> 9) & 0x7) + 1;
-	uint hclk_div = ((CLK_DIV0_REG >> 8) & 0x1) + 1;
-
-	/*
-	 * Bit 7 exists on s3c6410, and not on s3c6400, it is reserved on
-	 * s3c6400 and is always 0, and it is indeed running in ASYNC mode
-	 */
-	if (OTHERS_REG & 0x80)
-		fclk = get_FCLK();		/* SYNC Mode	*/
-	else
-		fclk = get_PLLCLK(MPLL);	/* ASYNC Mode	*/
-
-	return fclk / (hclk_div * hclkx2_div);
-}
-
-/* return PCLK frequency */
-ulong get_PCLK(void)
-{
-	ulong fclk;
-	uint hclkx2_div = ((CLK_DIV0_REG >> 9) & 0x7) + 1;
-	uint pre_div = ((CLK_DIV0_REG >> 12) & 0xf) + 1;
-
-	if (OTHERS_REG & 0x80)
-		fclk = get_FCLK();		/* SYNC Mode	*/
-	else
-		fclk = get_PLLCLK(MPLL);	/* ASYNC Mode	*/
-
-	return fclk / (hclkx2_div * pre_div);
-}
-
-/* return UCLK frequency */
-ulong get_UCLK(void)
-{
-	return get_PLLCLK(EPLL);
-}
-
-int print_cpuinfo(void)
-{
-	printf("\nCPU:     S3C6400@%luMHz\n", get_ARMCLK() / 1000000);
-	printf("         Fclk = %luMHz, Hclk = %luMHz, Pclk = %luMHz ",
-	       get_FCLK() / 1000000, get_HCLK() / 1000000,
-	       get_PCLK() / 1000000);
-
-	if (OTHERS_REG & 0x80)
-		printf("(SYNC Mode) \n");
-	else
-		printf("(ASYNC Mode) \n");
-	return 0;
-}
diff --git a/arch/arm/cpu/arm1176/s3c64xx/timer.c b/arch/arm/cpu/arm1176/s3c64xx/timer.c
deleted file mode 100644
index 9768319..0000000
--- a/arch/arm/cpu/arm1176/s3c64xx/timer.c
+++ /dev/null
@@ -1,177 +0,0 @@
-/*
- * (C) Copyright 2003
- * Texas Instruments <www.ti.com>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Alex Zuepke <azu@sysgo.de>
- *
- * (C) Copyright 2002-2004
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * (C) Copyright 2004
- * Philippe Robin, ARM Ltd. <philippe.robin@arm.com>
- *
- * (C) Copyright 2008
- * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/proc-armv/ptrace.h>
-#include <asm/arch/s3c6400.h>
-#include <div64.h>
-
-static ulong timer_load_val;
-
-#define PRESCALER	167
-
-static s3c64xx_timers *s3c64xx_get_base_timers(void)
-{
-	return (s3c64xx_timers *)ELFIN_TIMER_BASE;
-}
-
-/* macro to read the 16 bit timer */
-static inline ulong read_timer(void)
-{
-	s3c64xx_timers *const timers = s3c64xx_get_base_timers();
-
-	return timers->TCNTO4;
-}
-
-/* Internal tick units */
-/* Last decremneter snapshot */
-static unsigned long lastdec;
-/* Monotonic incrementing timer */
-static unsigned long long timestamp;
-
-int timer_init(void)
-{
-	s3c64xx_timers *const timers = s3c64xx_get_base_timers();
-
-	/* use PWM Timer 4 because it has no output */
-	/*
-	 * We use the following scheme for the timer:
-	 * Prescaler is hard fixed at 167, divider at 1/4.
-	 * This gives at PCLK frequency 66MHz approx. 10us ticks
-	 * The timer is set to wrap after 100s, at 66MHz this obviously
-	 * happens after 10,000,000 ticks. A long variable can thus
-	 * keep values up to 40,000s, i.e., 11 hours. This should be
-	 * enough for most uses:-) Possible optimizations: select a
-	 * binary-friendly frequency, e.g., 1ms / 128. Also calculate
-	 * the prescaler automatically for other PCLK frequencies.
-	 */
-	timers->TCFG0 = PRESCALER << 8;
-	if (timer_load_val == 0) {
-		timer_load_val = get_PCLK() / PRESCALER * (100 / 4); /* 100s */
-		timers->TCFG1 = (timers->TCFG1 & ~0xf0000) | 0x20000;
-	}
-
-	/* load value for 10 ms timeout */
-	lastdec = timers->TCNTB4 = timer_load_val;
-	/* auto load, manual update of Timer 4 */
-	timers->TCON = (timers->TCON & ~0x00700000) | TCON_4_AUTO |
-		TCON_4_UPDATE;
-
-	/* auto load, start Timer 4 */
-	timers->TCON = (timers->TCON & ~0x00700000) | TCON_4_AUTO | COUNT_4_ON;
-	timestamp = 0;
-
-	return 0;
-}
-
-/*
- * timer without interrupts
- */
-
-/*
- * This function is derived from PowerPC code (read timebase as long long).
- * On ARM it just returns the timer value.
- */
-unsigned long long get_ticks(void)
-{
-	ulong now = read_timer();
-
-	if (lastdec >= now) {
-		/* normal mode */
-		timestamp += lastdec - now;
-	} else {
-		/* we have an overflow ... */
-		timestamp += lastdec + timer_load_val - now;
-	}
-	lastdec = now;
-
-	return timestamp;
-}
-
-/*
- * This function is derived from PowerPC code (timebase clock frequency).
- * On ARM it returns the number of timer ticks per second.
- */
-ulong get_tbclk(void)
-{
-	/* We overrun in 100s */
-	return (ulong)(timer_load_val / 100);
-}
-
-void reset_timer_masked(void)
-{
-	/* reset time */
-	lastdec = read_timer();
-	timestamp = 0;
-}
-
-void reset_timer(void)
-{
-	reset_timer_masked();
-}
-
-ulong get_timer_masked(void)
-{
-	unsigned long long res = get_ticks();
-	do_div (res, (timer_load_val / (100 * CONFIG_SYS_HZ)));
-	return res;
-}
-
-ulong get_timer(ulong base)
-{
-	return get_timer_masked() - base;
-}
-
-void set_timer(ulong t)
-{
-	timestamp = t * (timer_load_val / (100 * CONFIG_SYS_HZ));
-}
-
-void __udelay(unsigned long usec)
-{
-	unsigned long long tmp;
-	ulong tmo;
-
-	tmo = (usec + 9) / 10;
-	tmp = get_ticks() + tmo;	/* get current timestamp */
-
-	while (get_ticks() < tmp)/* loop till event */
-		 /*NOP*/;
-}
diff --git a/arch/arm/cpu/arm1176/start.S b/arch/arm/cpu/arm1176/start.S
deleted file mode 100644
index 363329a..0000000
--- a/arch/arm/cpu/arm1176/start.S
+++ /dev/null
@@ -1,572 +0,0 @@
-/*
- *  armboot - Startup Code for ARM1176 CPU-core
- *
- * Copyright (c) 2007	Samsung Electronics
- *
- * Copyright (C) 2008
- * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- * 2007-09-21 - Restructured codes by jsgood (jsgood.yang@samsung.com)
- * 2007-09-21 - Added MoviNAND and OneNAND boot codes by
- * jsgood (jsgood.yang@samsung.com)
- * Base codes by scsuh (sc.suh)
- */
-
-#include <asm-offsets.h>
-#include <config.h>
-#include <version.h>
-#ifdef CONFIG_ENABLE_MMU
-#include <asm/proc/domain.h>
-#endif
-
-#if !defined(CONFIG_ENABLE_MMU) && !defined(CONFIG_SYS_PHY_UBOOT_BASE)
-#define CONFIG_SYS_PHY_UBOOT_BASE	CONFIG_SYS_UBOOT_BASE
-#endif
-
-/*
- *************************************************************************
- *
- * Jump vector table as in table 3.1 in [1]
- *
- *************************************************************************
- */
-
-.globl _start
-_start: b	reset
-#ifndef CONFIG_NAND_SPL
-	ldr	pc, _undefined_instruction
-	ldr	pc, _software_interrupt
-	ldr	pc, _prefetch_abort
-	ldr	pc, _data_abort
-	ldr	pc, _not_used
-	ldr	pc, _irq
-	ldr	pc, _fiq
-
-_undefined_instruction:
-	.word undefined_instruction
-_software_interrupt:
-	.word software_interrupt
-_prefetch_abort:
-	.word prefetch_abort
-_data_abort:
-	.word data_abort
-_not_used:
-	.word not_used
-_irq:
-	.word irq
-_fiq:
-	.word fiq
-_pad:
-	.word 0x12345678 /* now 16*4=64 */
-#else
-	. = _start + 64
-#endif
-
-.global _end_vect
-_end_vect:
-	.balignl 16,0xdeadbeef
-/*
- *************************************************************************
- *
- * Startup Code (reset vector)
- *
- * do important init only if we don't start from memory!
- * setup Memory and board specific bits prior to relocation.
- * relocate armboot to ram
- * setup stack
- *
- *************************************************************************
- */
-
-.globl _TEXT_BASE
-_TEXT_BASE:
-	.word	CONFIG_SYS_TEXT_BASE
-
-/*
- * Below variable is very important because we use MMU in U-Boot.
- * Without it, we cannot run code correctly before MMU is ON.
- * by scsuh.
- */
-_TEXT_PHY_BASE:
-	.word	CONFIG_SYS_PHY_UBOOT_BASE
-
-/*
- * These are defined in the board-specific linker script.
- * Subtracting _start from them lets the linker put their
- * relative position in the executable instead of leaving
- * them null.
- */
-
-.globl _bss_start_ofs
-_bss_start_ofs:
-	.word __bss_start - _start
-
-.globl _bss_end_ofs
-_bss_end_ofs:
-	.word _end - _start
-
-/* IRQ stack memory (calculated at run-time) + 8 bytes */
-.globl IRQ_STACK_START_IN
-IRQ_STACK_START_IN:
-	.word	0x0badc0de
-
-/*
- * the actual reset code
- */
-
-reset:
-	/*
-	 * set the cpu to SVC32 mode
-	 */
-	mrs	r0, cpsr
-	bic	r0, r0, #0x3f
-	orr	r0, r0, #0xd3
-	msr	cpsr, r0
-
-/*
- *************************************************************************
- *
- * CPU_init_critical registers
- *
- * setup important registers
- * setup memory timing
- *
- *************************************************************************
- */
-	/*
-	 * we do sys-critical inits only at reboot,
-	 * not when booting from ram!
-	 */
-cpu_init_crit:
-	/*
-	 * When booting from NAND - it has definitely been a reset, so, no need
-	 * to flush caches and disable the MMU
-	 */
-#ifndef CONFIG_NAND_SPL
-	/*
-	 * flush v4 I/D caches
-	 */
-	mov	r0, #0
-	mcr	p15, 0, r0, c7, c7, 0	/* flush v3/v4 cache */
-	mcr	p15, 0, r0, c8, c7, 0	/* flush v4 TLB */
-
-	/*
-	 * disable MMU stuff and caches
-	 */
-	mrc	p15, 0, r0, c1, c0, 0
-	bic	r0, r0, #0x00002300	@ clear bits 13, 9:8 (--V- --RS)
-	bic	r0, r0, #0x00000087	@ clear bits 7, 2:0 (B--- -CAM)
-	orr	r0, r0, #0x00000002	@ set bit 2 (A) Align
-	orr	r0, r0, #0x00001000	@ set bit 12 (I) I-Cache
-
-	/* Prepare to disable the MMU */
-	adr	r2, mmu_disable_phys
-	sub	r2, r2, #(CONFIG_SYS_PHY_UBOOT_BASE - CONFIG_SYS_TEXT_BASE)
-	b	mmu_disable
-
-	.align 5
-	/* Run in a single cache-line */
-mmu_disable:
-	mcr	p15, 0, r0, c1, c0, 0
-	nop
-	nop
-	mov	pc, r2
-mmu_disable_phys:
-
-#ifdef CONFIG_DISABLE_TCM
-	/*
-	 * Disable the TCMs
-	 */
-	mrc	p15, 0, r0, c0, c0, 2	/* Return TCM details */
-	cmp	r0, #0
-	beq	skip_tcmdisable
-	mov	r1, #0
-	mov	r2, #1
-	tst	r0, r2
-	mcrne	p15, 0, r1, c9, c1, 1	/* Disable Instruction TCM if present*/
-	tst	r0, r2, LSL #16
-	mcrne	p15, 0, r1, c9, c1, 0	/* Disable Data TCM if present*/
-skip_tcmdisable:
-#endif
-#endif
-
-#ifdef CONFIG_PERIPORT_REMAP
-	/* Peri port setup */
-	ldr	r0, =CONFIG_PERIPORT_BASE
-	orr	r0, r0, #CONFIG_PERIPORT_SIZE
-	mcr	p15,0,r0,c15,c2,4
-#endif
-
-	/*
-	 * Go setup Memory and board specific bits prior to relocation.
-	 */
-	bl	lowlevel_init		/* go setup pll,mux,memory */
-
-/* Set stackpointer in internal RAM to call board_init_f */
-call_board_init_f:
-	ldr	sp, =(CONFIG_SYS_INIT_SP_ADDR)
-	bic	sp, sp, #7 /* 8-byte alignment for ABI compliance */
-	ldr	r0,=0x00000000
-	bl	board_init_f
-
-/*------------------------------------------------------------------------------*/
-
-/*
- * void relocate_code (addr_sp, gd, addr_moni)
- *
- * This "function" does not return, instead it continues in RAM
- * after relocating the monitor code.
- *
- */
-	.globl	relocate_code
-relocate_code:
-	mov	r4, r0	/* save addr_sp */
-	mov	r5, r1	/* save addr of gd */
-	mov	r6, r2	/* save addr of destination */
-
-	/* Set up the stack						    */
-stack_setup:
-	mov	sp, r4
-
-	adr	r0, _start
-	cmp	r0, r6
-	beq	clear_bss		/* skip relocation */
-	mov	r1, r6			/* r1 <- scratch for copy_loop */
-	ldr	r3, _bss_start_ofs
-	add	r2, r0, r3		/* r2 <- source end address	    */
-
-copy_loop:
-	ldmia	r0!, {r9-r10}		/* copy from source address [r0]    */
-	stmia	r1!, {r9-r10}		/* copy to   target address [r1]    */
-	cmp	r0, r2			/* until source end address [r2]    */
-	blo	copy_loop
-
-#ifndef CONFIG_PRELOADER
-	/*
-	 * fix .rel.dyn relocations
-	 */
-	ldr	r0, _TEXT_BASE		/* r0 <- Text base */
-	sub	r9, r6, r0		/* r9 <- relocation offset */
-	ldr	r10, _dynsym_start_ofs	/* r10 <- sym table ofs */
-	add	r10, r10, r0		/* r10 <- sym table in FLASH */
-	ldr	r2, _rel_dyn_start_ofs	/* r2 <- rel dyn start ofs */
-	add	r2, r2, r0		/* r2 <- rel dyn start in FLASH */
-	ldr	r3, _rel_dyn_end_ofs	/* r3 <- rel dyn end ofs */
-	add	r3, r3, r0		/* r3 <- rel dyn end in FLASH */
-fixloop:
-	ldr	r0, [r2]		/* r0 <- location to fix up, IN FLASH! */
-	add	r0, r0, r9		/* r0 <- location to fix up in RAM */
-	ldr	r1, [r2, #4]
-	and	r7, r1, #0xff
-	cmp	r7, #23			/* relative fixup? */
-	beq	fixrel
-	cmp	r7, #2			/* absolute fixup? */
-	beq	fixabs
-	/* ignore unknown type of fixup */
-	b	fixnext
-fixabs:
-	/* absolute fix: set location to (offset) symbol value */
-	mov	r1, r1, LSR #4		/* r1 <- symbol index in .dynsym */
-	add	r1, r10, r1		/* r1 <- address of symbol in table */
-	ldr	r1, [r1, #4]		/* r1 <- symbol value */
-	add	r1, r1, r9		/* r1 <- relocated sym addr */
-	b	fixnext
-fixrel:
-	/* relative fix: increase location by offset */
-	ldr	r1, [r0]
-	add	r1, r1, r9
-fixnext:
-	str	r1, [r0]
-	add	r2, r2, #8		/* each rel.dyn entry is 8 bytes */
-	cmp	r2, r3
-	blo	fixloop
-#endif
-
-#ifdef CONFIG_ENABLE_MMU
-enable_mmu:
-	/* enable domain access */
-	ldr	r5, =0x0000ffff
-	mcr	p15, 0, r5, c3, c0, 0	/* load domain access register */
-
-	/* Set the TTB register */
-	ldr	r0, _mmu_table_base
-	ldr	r1, =CONFIG_SYS_PHY_UBOOT_BASE
-	ldr	r2, =0xfff00000
-	bic	r0, r0, r2
-	orr	r1, r0, r1
-	mcr	p15, 0, r1, c2, c0, 0
-
-	/* Enable the MMU */
-	mrc	p15, 0, r0, c1, c0, 0
-	orr	r0, r0, #1		/* Set CR_M to enable MMU */
-
-	/* Prepare to enable the MMU */
-	adr	r1, skip_hw_init
-	and	r1, r1, #0x3fc
-	ldr	r2, _TEXT_BASE
-	ldr	r3, =0xfff00000
-	and	r2, r2, r3
-	orr	r2, r2, r1
-	b	mmu_enable
-
-	.align 5
-	/* Run in a single cache-line */
-mmu_enable:
-
-	mcr	p15, 0, r0, c1, c0, 0
-	nop
-	nop
-	mov	pc, r2
-skip_hw_init:
-#endif
-
-clear_bss:
-#ifndef CONFIG_PRELOADER
-	ldr	r0, _bss_start_ofs
-	ldr	r1, _bss_end_ofs
-	mov	r4, r6			/* reloc addr */
-	add	r0, r0, r4
-	add	r1, r1, r4
-	mov	r2, #0x00000000		/* clear			    */
-
-clbss_l:str	r2, [r0]		/* clear loop...		    */
-	add	r0, r0, #4
-	cmp	r0, r1
-	bne	clbss_l
-
-	bl coloured_LED_init
-	bl red_LED_on
-#endif
-
-/*
- * We are done. Do not return, instead branch to second part of board
- * initialization, now running from RAM.
- */
-#ifdef CONFIG_NAND_SPL
-	ldr     pc, _nand_boot
-
-_nand_boot: .word nand_boot
-#else
-	ldr	r0, _board_init_r_ofs
-	adr	r1, _start
-	add	lr, r0, r1
-	add     lr, lr, r9
-	/* setup parameters for board_init_r */
-	mov	r0, r5		/* gd_t */
-	mov	r1, r6		/* dest_addr */
-	/* jump to it ... */
-	mov	pc, lr
-
-_board_init_r_ofs:
-	.word board_init_r - _start
-#endif
-
-_rel_dyn_start_ofs:
-	.word __rel_dyn_start - _start
-_rel_dyn_end_ofs:
-	.word __rel_dyn_end - _start
-_dynsym_start_ofs:
-	.word __dynsym_start - _start
-
-#ifdef CONFIG_ENABLE_MMU
-_mmu_table_base:
-	.word mmu_table
-#endif
-
-#ifndef CONFIG_NAND_SPL
-/*
- * we assume that cache operation is done before. (eg. cleanup_before_linux())
- * actually, we don't need to do anything about cache if not use d-cache in
- * U-Boot. So, in this function we clean only MMU. by scsuh
- *
- * void	theLastJump(void *kernel, int arch_num, uint boot_params);
- */
-#ifdef CONFIG_ENABLE_MMU
-	.globl theLastJump
-theLastJump:
-	mov	r9, r0
-	ldr	r3, =0xfff00000
-	ldr	r4, _TEXT_PHY_BASE
-	adr	r5, phy_last_jump
-	bic	r5, r5, r3
-	orr	r5, r5, r4
-	mov	pc, r5
-phy_last_jump:
-	/*
-	 * disable MMU stuff
-	 */
-	mrc	p15, 0, r0, c1, c0, 0
-	bic	r0, r0, #0x00002300	/* clear bits 13, 9:8 (--V- --RS) */
-	bic	r0, r0, #0x00000087	/* clear bits 7, 2:0 (B--- -CAM) */
-	orr	r0, r0, #0x00000002	/* set bit 2 (A) Align */
-	orr	r0, r0, #0x00001000	/* set bit 12 (I) I-Cache */
-	mcr	p15, 0, r0, c1, c0, 0
-
-	mcr	p15, 0, r0, c8, c7, 0	/* flush v4 TLB */
-
-	mov	r0, #0
-	mov	pc, r9
-#endif
-
-
-/*
- *************************************************************************
- *
- * Interrupt handling
- *
- *************************************************************************
- */
-@
-@ IRQ stack frame.
-@
-#define S_FRAME_SIZE	72
-
-#define S_OLD_R0	68
-#define S_PSR		64
-#define S_PC		60
-#define S_LR		56
-#define S_SP		52
-
-#define S_IP		48
-#define S_FP		44
-#define S_R10		40
-#define S_R9		36
-#define S_R8		32
-#define S_R7		28
-#define S_R6		24
-#define S_R5		20
-#define S_R4		16
-#define S_R3		12
-#define S_R2		8
-#define S_R1		4
-#define S_R0		0
-
-#define MODE_SVC 0x13
-#define I_BIT	 0x80
-
-/*
- * use bad_save_user_regs for abort/prefetch/undef/swi ...
- */
-
-	.macro	bad_save_user_regs
-	/* carve out a frame on current user stack */
-	sub	sp, sp, #S_FRAME_SIZE
-	/* Save user registers (now in svc mode) r0-r12 */
-	stmia	sp, {r0 - r12}
-
-	ldr	r2, IRQ_STACK_START_IN
-	/* get values for "aborted" pc and cpsr (into parm regs) */
-	ldmia	r2, {r2 - r3}
-	/* grab pointer to old stack */
-	add	r0, sp, #S_FRAME_SIZE
-
-	add	r5, sp, #S_SP
-	mov	r1, lr
-	/* save sp_SVC, lr_SVC, pc, cpsr */
-	stmia	r5, {r0 - r3}
-	/* save current stack into r0 (param register) */
-	mov	r0, sp
-	.endm
-
-	.macro get_bad_stack
-	ldr	r13, IRQ_STACK_START_IN		@ setup our mode stack
-
-	/* save caller lr in position 0 of saved stack */
-	str	lr, [r13]
-	/* get the spsr */
-	mrs	lr, spsr
-	/* save spsr in position 1 of saved stack */
-	str	lr, [r13, #4]
-
-	/* prepare SVC-Mode */
-	mov	r13, #MODE_SVC
-	@ msr	spsr_c, r13
-	/* switch modes, make sure moves will execute */
-	msr	spsr, r13
-	/* capture return pc */
-	mov	lr, pc
-	/* jump to next instruction & switch modes. */
-	movs	pc, lr
-	.endm
-
-	.macro get_bad_stack_swi
-	/* space on current stack for scratch reg. */
-	sub	r13, r13, #4
-	/* save R0's value. */
-	str	r0, [r13]
-	ldr	r13, IRQ_STACK_START_IN		@ setup our mode stack
-	/* save caller lr in position 0 of saved stack */
-	str	lr, [r0]
-	/* get the spsr */
-	mrs	r0, spsr
-	/* save spsr in position 1 of saved stack */
-	str	lr, [r0, #4]
-	/* restore r0 */
-	ldr	r0, [r13]
-	/* pop stack entry */
-	add	r13, r13, #4
-	.endm
-
-/*
- * exception handlers
- */
-	.align	5
-undefined_instruction:
-	get_bad_stack
-	bad_save_user_regs
-	bl	do_undefined_instruction
-
-	.align	5
-software_interrupt:
-	get_bad_stack_swi
-	bad_save_user_regs
-	bl	do_software_interrupt
-
-	.align	5
-prefetch_abort:
-	get_bad_stack
-	bad_save_user_regs
-	bl	do_prefetch_abort
-
-	.align	5
-data_abort:
-	get_bad_stack
-	bad_save_user_regs
-	bl	do_data_abort
-
-	.align	5
-not_used:
-	get_bad_stack
-	bad_save_user_regs
-	bl	do_not_used
-
-	.align	5
-irq:
-	get_bad_stack
-	bad_save_user_regs
-	bl	do_irq
-
-	.align	5
-fiq:
-	get_bad_stack
-	bad_save_user_regs
-	bl	do_fiq
-#endif /* CONFIG_NAND_SPL */
diff --git a/arch/arm/cpu/arm1176/tnetv107x/Makefile b/arch/arm/cpu/arm1176/tnetv107x/Makefile
deleted file mode 100644
index c63dc92..0000000
--- a/arch/arm/cpu/arm1176/tnetv107x/Makefile
+++ /dev/null
@@ -1,44 +0,0 @@
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; either version 2 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
-#
-
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(SOC).o
-
-COBJS	+= aemif.o clock.o init.o mux.o timer.o wdt.o
-SOBJS	+= lowlevel_init.o
-
-SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
-
-OBJS	:= $(addprefix $(obj),$(COBJS) $(SOBJS))
-START	:= $(addprefix $(obj),$(START))
-
-all:	$(obj).depend $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/arch/arm/cpu/arm1176/tnetv107x/aemif.c b/arch/arm/cpu/arm1176/tnetv107x/aemif.c
deleted file mode 100644
index 172f583..0000000
--- a/arch/arm/cpu/arm1176/tnetv107x/aemif.c
+++ /dev/null
@@ -1,93 +0,0 @@
-/*
- * TNETV107X: Asynchronous EMIF Configuration
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/mux.h>
-
-#define ASYNC_EMIF_BASE			TNETV107X_ASYNC_EMIF_CNTRL_BASE
-#define ASYNC_EMIF_CONFIG(cs)		(ASYNC_EMIF_BASE+0x10+(cs)*4)
-#define ASYNC_EMIF_ONENAND_CONTROL	(ASYNC_EMIF_BASE+0x5c)
-#define ASYNC_EMIF_NAND_CONTROL		(ASYNC_EMIF_BASE+0x60)
-#define ASYNC_EMIF_WAITCYCLE_CONFIG	(ASYNC_EMIF_BASE+0x4)
-
-#define CONFIG_SELECT_STROBE(v)		((v) ? 1 << 31 : 0)
-#define CONFIG_EXTEND_WAIT(v)		((v) ? 1 << 30 : 0)
-#define CONFIG_WR_SETUP(v)		(((v) & 0x0f) << 26)
-#define CONFIG_WR_STROBE(v)		(((v) & 0x3f) << 20)
-#define CONFIG_WR_HOLD(v)		(((v) & 0x07) << 17)
-#define CONFIG_RD_SETUP(v)		(((v) & 0x0f) << 13)
-#define CONFIG_RD_STROBE(v)		(((v) & 0x3f) << 7)
-#define CONFIG_RD_HOLD(v)		(((v) & 0x07) << 4)
-#define CONFIG_TURN_AROUND(v)		(((v) & 0x03) << 2)
-#define CONFIG_WIDTH(v)			(((v) & 0x03) << 0)
-
-#define NUM_CS				4
-
-#define set_config_field(reg, field, val)			\
-	do {							\
-		if (val != -1) {				\
-			reg &= ~CONFIG_##field(0xffffffff);	\
-			reg |=	CONFIG_##field(val);		\
-		}						\
-	} while (0)
-
-void configure_async_emif(int cs, struct async_emif_config *cfg)
-{
-	unsigned long tmp;
-
-	if (cfg->mode == ASYNC_EMIF_MODE_NAND) {
-		tmp = __raw_readl(ASYNC_EMIF_NAND_CONTROL);
-		tmp |= (1 << cs);
-		__raw_writel(tmp, ASYNC_EMIF_NAND_CONTROL);
-
-	} else if (cfg->mode == ASYNC_EMIF_MODE_ONENAND) {
-		tmp = __raw_readl(ASYNC_EMIF_ONENAND_CONTROL);
-		tmp |= (1 << cs);
-		__raw_writel(tmp, ASYNC_EMIF_ONENAND_CONTROL);
-	}
-
-	tmp = __raw_readl(ASYNC_EMIF_CONFIG(cs));
-
-	set_config_field(tmp, SELECT_STROBE,	cfg->select_strobe);
-	set_config_field(tmp, EXTEND_WAIT,	cfg->extend_wait);
-	set_config_field(tmp, WR_SETUP,		cfg->wr_setup);
-	set_config_field(tmp, WR_STROBE,	cfg->wr_strobe);
-	set_config_field(tmp, WR_HOLD,		cfg->wr_hold);
-	set_config_field(tmp, RD_SETUP,		cfg->rd_setup);
-	set_config_field(tmp, RD_STROBE,	cfg->rd_strobe);
-	set_config_field(tmp, RD_HOLD,		cfg->rd_hold);
-	set_config_field(tmp, TURN_AROUND,	cfg->turn_around);
-	set_config_field(tmp, WIDTH,		cfg->width);
-
-	__raw_writel(tmp, ASYNC_EMIF_CONFIG(cs));
-}
-
-void init_async_emif(int num_cs, struct async_emif_config *config)
-{
-	int cs;
-
-	clk_enable(TNETV107X_LPSC_AEMIF);
-
-	for (cs = 0; cs < num_cs; cs++)
-		configure_async_emif(cs, config + cs);
-}
diff --git a/arch/arm/cpu/arm1176/tnetv107x/clock.c b/arch/arm/cpu/arm1176/tnetv107x/clock.c
deleted file mode 100644
index e26fec1..0000000
--- a/arch/arm/cpu/arm1176/tnetv107x/clock.c
+++ /dev/null
@@ -1,451 +0,0 @@
-/*
- * TNETV107X: Clock management APIs
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#include <common.h>
-#include <asm-generic/errno.h>
-#include <asm/io.h>
-#include <asm/processor.h>
-#include <asm/arch/clock.h>
-
-#define CLOCK_BASE		TNETV107X_CLOCK_CONTROL_BASE
-#define PSC_BASE		TNETV107X_PSC_BASE
-
-#define BIT(x)			(1 << (x))
-
-#define MAX_PREDIV		64
-#define MAX_POSTDIV		8
-#define MAX_MULT		512
-#define MAX_DIV			(MAX_PREDIV * MAX_POSTDIV)
-
-/* LPSC registers */
-#define PSC_PTCMD		0x120
-#define PSC_PTSTAT		0x128
-#define PSC_MDSTAT(n)		(0x800 + (n) * 4)
-#define PSC_MDCTL(n)		(0xA00 + (n) * 4)
-
-#define PSC_MDCTL_LRSTZ		BIT(8)
-
-#define psc_reg_read(reg)	__raw_readl((u32 *)(PSC_BASE + (reg)))
-#define psc_reg_write(reg, val)	__raw_writel(val, (u32 *)(PSC_BASE + (reg)))
-
-/* SSPLL registers */
-struct sspll_regs {
-	u32	modes;
-	u32	postdiv;
-	u32	prediv;
-	u32	mult_factor;
-	u32	divider_range;
-	u32	bw_divider;
-	u32	spr_amount;
-	u32	spr_rate_div;
-	u32	diag;
-};
-
-/* SSPLL base addresses */
-static struct sspll_regs *sspll_regs[] = {
-	(struct sspll_regs *)(CLOCK_BASE + 0x040),
-	(struct sspll_regs *)(CLOCK_BASE + 0x080),
-	(struct sspll_regs *)(CLOCK_BASE + 0x0c0),
-};
-
-#define sspll_reg(pll, reg)		(&(sspll_regs[pll]->reg))
-#define sspll_reg_read(pll, reg)	__raw_readl(sspll_reg(pll, reg))
-#define sspll_reg_write(pll, reg, val)	__raw_writel(val, sspll_reg(pll, reg))
-
-
-/* PLL Control Registers */
-struct pllctl_regs {
-	u32	ctl;		/* 00 */
-	u32	ocsel;		/* 04 */
-	u32	secctl;		/* 08 */
-	u32	__pad0;
-	u32	mult;		/* 10 */
-	u32	prediv;		/* 14 */
-	u32	div1;		/* 18 */
-	u32	div2;		/* 1c */
-	u32	div3;		/* 20 */
-	u32	oscdiv1;	/* 24 */
-	u32	postdiv;	/* 28 */
-	u32	bpdiv;		/* 2c */
-	u32	wakeup;		/* 30 */
-	u32	__pad1;
-	u32	cmd;		/* 38 */
-	u32	stat;		/* 3c */
-	u32	alnctl;		/* 40 */
-	u32	dchange;	/* 44 */
-	u32	cken;		/* 48 */
-	u32	ckstat;		/* 4c */
-	u32	systat;		/* 50 */
-	u32	ckctl;		/* 54 */
-	u32	__pad2[2];
-	u32	div4;		/* 60 */
-	u32	div5;		/* 64 */
-	u32	div6;		/* 68 */
-	u32	div7;		/* 6c */
-	u32	div8;		/* 70 */
-};
-
-struct lpsc_map {
-	int	pll, div;
-};
-
-static struct pllctl_regs *pllctl_regs[] = {
-	(struct pllctl_regs *)(CLOCK_BASE + 0x700),
-	(struct pllctl_regs *)(CLOCK_BASE + 0x300),
-	(struct pllctl_regs *)(CLOCK_BASE + 0x500),
-};
-
-#define pllctl_reg(pll, reg)		(&(pllctl_regs[pll]->reg))
-#define pllctl_reg_read(pll, reg)	__raw_readl(pllctl_reg(pll, reg))
-#define pllctl_reg_write(pll, reg, val)	__raw_writel(val, pllctl_reg(pll, reg))
-
-#define pllctl_reg_rmw(pll, reg, mask, val)			\
-	pllctl_reg_write(pll, reg,				\
-		(pllctl_reg_read(pll, reg) & ~(mask)) | val)
-
-#define pllctl_reg_setbits(pll, reg, mask)			\
-	pllctl_reg_rmw(pll, reg, 0, mask)
-
-#define pllctl_reg_clrbits(pll, reg, mask)			\
-	pllctl_reg_rmw(pll, reg, mask, 0)
-
-/* PLLCTL Bits */
-#define PLLCTL_CLKMODE		BIT(8)
-#define PLLCTL_PLLSELB		BIT(7)
-#define PLLCTL_PLLENSRC		BIT(5)
-#define PLLCTL_PLLDIS		BIT(4)
-#define PLLCTL_PLLRST		BIT(3)
-#define PLLCTL_PLLPWRDN		BIT(1)
-#define PLLCTL_PLLEN		BIT(0)
-
-#define PLLDIV_ENABLE		BIT(15)
-
-static int pll_div_offset[] = {
-#define div_offset(reg)	offsetof(struct pllctl_regs, reg)
-	div_offset(div1), div_offset(div2), div_offset(div3),
-	div_offset(div4), div_offset(div5), div_offset(div6),
-	div_offset(div7), div_offset(div8),
-};
-
-static unsigned long pll_bypass_mask[] = { 1, 4, 2 };
-static unsigned long pll_div_mask[] = { 0x01ff, 0x00ff, 0x00ff };
-
-/* Mappings from PLL+DIV to subsystem clocks */
-#define sys_arm1176_clk		{SYS_PLL, 0}
-#define sys_dsp_clk		{SYS_PLL, 1}
-#define sys_ddr_clk		{SYS_PLL, 2}
-#define sys_full_clk		{SYS_PLL, 3}
-#define sys_lcd_clk		{SYS_PLL, 4}
-#define sys_vlynq_ref_clk	{SYS_PLL, 5}
-#define sys_tsc_clk		{SYS_PLL, 6}
-#define sys_half_clk		{SYS_PLL, 7}
-
-#define eth_clk_5		{ETH_PLL, 0}
-#define eth_clk_50		{ETH_PLL, 1}
-#define eth_clk_125		{ETH_PLL, 2}
-#define eth_clk_250		{ETH_PLL, 3}
-#define eth_clk_25		{ETH_PLL, 4}
-
-#define tdm_clk			{TDM_PLL, 0}
-#define tdm_extra_clk		{TDM_PLL, 1}
-#define tdm1_clk		{TDM_PLL, 2}
-
-/* Optimization barrier */
-#define barrier()	\
-	__asm__ __volatile__("mov r0, r0\n" : : : "memory");
-
-static const struct lpsc_map lpsc_clk_map[] = {
-	[TNETV107X_LPSC_ARM]			= sys_arm1176_clk,
-	[TNETV107X_LPSC_GEM]			= sys_dsp_clk,
-	[TNETV107X_LPSC_DDR2_PHY]		= sys_ddr_clk,
-	[TNETV107X_LPSC_TPCC]			= sys_full_clk,
-	[TNETV107X_LPSC_TPTC0]			= sys_full_clk,
-	[TNETV107X_LPSC_TPTC1]			= sys_full_clk,
-	[TNETV107X_LPSC_RAM]			= sys_full_clk,
-	[TNETV107X_LPSC_MBX_LITE]		= sys_arm1176_clk,
-	[TNETV107X_LPSC_LCD]			= sys_lcd_clk,
-	[TNETV107X_LPSC_ETHSS]			= eth_clk_125,
-	[TNETV107X_LPSC_AEMIF]			= sys_full_clk,
-	[TNETV107X_LPSC_CHIP_CFG]		= sys_half_clk,
-	[TNETV107X_LPSC_TSC]			= sys_tsc_clk,
-	[TNETV107X_LPSC_ROM]			= sys_half_clk,
-	[TNETV107X_LPSC_UART2]			= sys_half_clk,
-	[TNETV107X_LPSC_PKTSEC]			= sys_half_clk,
-	[TNETV107X_LPSC_SECCTL]			= sys_half_clk,
-	[TNETV107X_LPSC_KEYMGR]			= sys_half_clk,
-	[TNETV107X_LPSC_KEYPAD]			= sys_half_clk,
-	[TNETV107X_LPSC_GPIO]			= sys_half_clk,
-	[TNETV107X_LPSC_MDIO]			= sys_half_clk,
-	[TNETV107X_LPSC_SDIO0]			= sys_half_clk,
-	[TNETV107X_LPSC_UART0]			= sys_half_clk,
-	[TNETV107X_LPSC_UART1]			= sys_half_clk,
-	[TNETV107X_LPSC_TIMER0]			= sys_half_clk,
-	[TNETV107X_LPSC_TIMER1]			= sys_half_clk,
-	[TNETV107X_LPSC_WDT_ARM]		= sys_half_clk,
-	[TNETV107X_LPSC_WDT_DSP]		= sys_half_clk,
-	[TNETV107X_LPSC_SSP]			= sys_half_clk,
-	[TNETV107X_LPSC_TDM0]			= tdm_clk,
-	[TNETV107X_LPSC_VLYNQ]			= sys_vlynq_ref_clk,
-	[TNETV107X_LPSC_MCDMA]			= sys_half_clk,
-	[TNETV107X_LPSC_USB0]			= sys_half_clk,
-	[TNETV107X_LPSC_TDM1]			= tdm1_clk,
-	[TNETV107X_LPSC_DEBUGSS]		= sys_half_clk,
-	[TNETV107X_LPSC_ETHSS_RGMII]		= eth_clk_250,
-	[TNETV107X_LPSC_SYSTEM]			= sys_half_clk,
-	[TNETV107X_LPSC_IMCOP]			= sys_dsp_clk,
-	[TNETV107X_LPSC_SPARE]			= sys_half_clk,
-	[TNETV107X_LPSC_SDIO1]			= sys_half_clk,
-	[TNETV107X_LPSC_USB1]			= sys_half_clk,
-	[TNETV107X_LPSC_USBSS]			= sys_half_clk,
-	[TNETV107X_LPSC_DDR2_EMIF1_VRST]	= sys_ddr_clk,
-	[TNETV107X_LPSC_DDR2_EMIF2_VCTL_RST]	= sys_ddr_clk,
-};
-
-static const unsigned long pll_ext_freq[] = {
-	[SYS_PLL] = CONFIG_PLL_SYS_EXT_FREQ,
-	[ETH_PLL] = CONFIG_PLL_ETH_EXT_FREQ,
-	[TDM_PLL] = CONFIG_PLL_TDM_EXT_FREQ,
-};
-
-static unsigned long pll_freq_get(int pll)
-{
-	unsigned long mult = 1, prediv = 1, postdiv = 1;
-	unsigned long ref = CONFIG_SYS_INT_OSC_FREQ;
-	unsigned long ret;
-	u32 bypass;
-
-	bypass = __raw_readl((u32 *)(CLOCK_BASE));
-	if (!(bypass & pll_bypass_mask[pll])) {
-		mult	= sspll_reg_read(pll, mult_factor);
-		prediv	= sspll_reg_read(pll, prediv) + 1;
-		postdiv	= sspll_reg_read(pll, postdiv) + 1;
-	}
-
-	if (pllctl_reg_read(pll, ctl) & PLLCTL_CLKMODE)
-		ref = pll_ext_freq[pll];
-
-	if (!(pllctl_reg_read(pll, ctl) & PLLCTL_PLLEN))
-		return ref;
-
-	ret = (unsigned long)(ref + ((unsigned long long)ref * mult) / 256);
-	ret /= (prediv * postdiv);
-
-	return ret;
-}
-
-static unsigned long __pll_div_freq_get(int pll, unsigned int fpll,
-					int div)
-{
-	int divider = 1;
-	unsigned long divreg;
-
-	divreg = __raw_readl((void *)pllctl_regs[pll] + pll_div_offset[div]);
-
-	if (divreg & PLLDIV_ENABLE)
-		divider = (divreg & pll_div_mask[pll]) + 1;
-
-	return fpll / divider;
-}
-
-static unsigned long pll_div_freq_get(int pll, int div)
-{
-	unsigned int fpll = pll_freq_get(pll);
-
-	return __pll_div_freq_get(pll, fpll, div);
-}
-
-static void __pll_div_freq_set(int pll, unsigned int fpll, int div,
-			       unsigned long hz)
-{
-	int divider = (fpll / hz - 1);
-
-	divider &= pll_div_mask[pll];
-	divider |= PLLDIV_ENABLE;
-
-	__raw_writel(divider, (void *)pllctl_regs[pll] + pll_div_offset[div]);
-	pllctl_reg_setbits(pll, alnctl, (1 << div));
-	pllctl_reg_setbits(pll, dchange, (1 << div));
-}
-
-static unsigned long pll_div_freq_set(int pll, int div, unsigned long hz)
-{
-	unsigned int fpll = pll_freq_get(pll);
-
-	__pll_div_freq_set(pll, fpll, div, hz);
-
-	pllctl_reg_write(pll, cmd, 1);
-
-	/* Wait until new divider takes effect */
-	while (pllctl_reg_read(pll, stat) & 0x01);
-
-	return __pll_div_freq_get(pll, fpll, div);
-}
-
-unsigned long clk_get_rate(unsigned int clk)
-{
-	return pll_div_freq_get(lpsc_clk_map[clk].pll, lpsc_clk_map[clk].div);
-}
-
-unsigned long clk_round_rate(unsigned int clk, unsigned long hz)
-{
-	unsigned long fpll, divider, pll;
-
-	pll = lpsc_clk_map[clk].pll;
-	fpll = pll_freq_get(pll);
-	divider = (fpll / hz - 1);
-	divider &= pll_div_mask[pll];
-
-	return fpll / (divider + 1);
-}
-
-int clk_set_rate(unsigned int clk, unsigned long _hz)
-{
-	unsigned long hz;
-
-	hz = clk_round_rate(clk, _hz);
-	if (hz != _hz)
-		return -EINVAL;	/* Cannot set to target freq */
-
-	pll_div_freq_set(lpsc_clk_map[clk].pll, lpsc_clk_map[clk].div, hz);
-	return 0;
-}
-
-void lpsc_control(int mod, unsigned long state, int lrstz)
-{
-	u32 mdctl;
-
-	mdctl = psc_reg_read(PSC_MDCTL(mod));
-	mdctl &= ~0x1f;
-	mdctl |= state;
-
-	if (lrstz == 0)
-		mdctl &= ~PSC_MDCTL_LRSTZ;
-	else if (lrstz == 1)
-		mdctl |= PSC_MDCTL_LRSTZ;
-
-	psc_reg_write(PSC_MDCTL(mod), mdctl);
-
-	psc_reg_write(PSC_PTCMD, 1);
-
-	/* wait for power domain transition to end */
-	while (psc_reg_read(PSC_PTSTAT) & 1);
-
-	/* Wait for module state change */
-	while ((psc_reg_read(PSC_MDSTAT(mod)) & 0x1f) != state);
-}
-
-int lpsc_status(unsigned int id)
-{
-	return psc_reg_read(PSC_MDSTAT(id)) & 0x1f;
-}
-
-static void init_pll(const struct pll_init_data *data)
-{
-	unsigned long fpll;
-	unsigned long best_pre = 0, best_post = 0, best_mult = 0;
-	unsigned long div, prediv, postdiv, mult;
-	unsigned long delta, actual;
-	long best_delta = -1;
-	int i;
-	u32 tmp;
-
-	if (data->pll == SYS_PLL)
-		return; /* cannot reconfigure system pll on the fly */
-
-	tmp = pllctl_reg_read(data->pll, ctl);
-	if (data->internal_osc) {
-		tmp &= ~PLLCTL_CLKMODE;
-		fpll = CONFIG_SYS_INT_OSC_FREQ;
-	} else {
-		tmp |= PLLCTL_CLKMODE;
-		fpll = pll_ext_freq[data->pll];
-	}
-	pllctl_reg_write(data->pll, ctl, tmp);
-
-	mult = data->pll_freq / fpll;
-	for (mult = MAX(mult, 1); mult <= MAX_MULT; mult++) {
-		div = (fpll * mult) / data->pll_freq;
-		if (div < 1 || div > MAX_DIV)
-			continue;
-
-		for (postdiv = 1; postdiv <= min(div, MAX_POSTDIV); postdiv++) {
-			prediv = div / postdiv;
-			if (prediv < 1 || prediv > MAX_PREDIV)
-				continue;
-
-			actual = (fpll / prediv) * (mult / postdiv);
-			delta = (actual - data->pll_freq);
-			if (delta < 0)
-				delta = -delta;
-			if ((delta < best_delta) || (best_delta == -1)) {
-				best_delta = delta;
-				best_mult = mult;
-				best_pre = prediv;
-				best_post = postdiv;
-				if (delta == 0)
-					goto done;
-			}
-		}
-	}
-done:
-
-	if (best_delta == -1) {
-		printf("pll cannot derive %lu from %lu\n",
-				data->pll_freq, fpll);
-		return;
-	}
-
-	fpll = fpll * best_mult;
-	fpll /= best_pre * best_post;
-
-	pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLENSRC);
-	pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLEN);
-
-	pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLRST);
-
-	pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLPWRDN);
-	pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLDIS);
-
-	sspll_reg_write(data->pll, mult_factor,	(best_mult - 1) << 8);
-	sspll_reg_write(data->pll, prediv,	best_pre - 1);
-	sspll_reg_write(data->pll, postdiv,	best_post - 1);
-
-	for (i = 0; i < 10; i++)
-		if (data->div_freq[i])
-			__pll_div_freq_set(data->pll, fpll, i,
-					   data->div_freq[i]);
-
-	pllctl_reg_write(data->pll, cmd, 1);
-
-	/* Wait until pll "go" operation completes */
-	while (pllctl_reg_read(data->pll, stat) & 0x01);
-
-	pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLRST);
-	pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLEN);
-}
-
-void init_plls(int num_pll, struct pll_init_data *config)
-{
-	int i;
-
-	for (i = 0; i < num_pll; i++)
-		init_pll(&config[i]);
-}
diff --git a/arch/arm/cpu/arm1176/tnetv107x/init.c b/arch/arm/cpu/arm1176/tnetv107x/init.c
deleted file mode 100644
index ce3a025..0000000
--- a/arch/arm/cpu/arm1176/tnetv107x/init.c
+++ /dev/null
@@ -1,37 +0,0 @@
-/*
- * TNETV107X: Architecture initialization
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#include <common.h>
-#include <asm/io.h>
-
-void chip_configuration_unlock(void)
-{
-       __raw_writel(TNETV107X_KICK0_MAGIC, TNETV107X_KICK0);
-       __raw_writel(TNETV107X_KICK1_MAGIC, TNETV107X_KICK1);
-}
-
-int arch_cpu_init(void)
-{
-       icache_enable();
-       chip_configuration_unlock();
-
-       return 0;
-}
diff --git a/arch/arm/cpu/arm1176/tnetv107x/lowlevel_init.S b/arch/arm/cpu/arm1176/tnetv107x/lowlevel_init.S
deleted file mode 100644
index 3ee32ef..0000000
--- a/arch/arm/cpu/arm1176/tnetv107x/lowlevel_init.S
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * TNETV107X: Low-level pre-relocation initialization
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-.globl lowlevel_init
-lowlevel_init:
-	/* nothing for now, maybe needed for more exotic boot modes */
-	mov	pc, lr
diff --git a/arch/arm/cpu/arm1176/tnetv107x/mux.c b/arch/arm/cpu/arm1176/tnetv107x/mux.c
deleted file mode 100644
index ccc5314..0000000
--- a/arch/arm/cpu/arm1176/tnetv107x/mux.c
+++ /dev/null
@@ -1,334 +0,0 @@
-/*
- * TNETV107X: Pinmux configuration
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/mux.h>
-
-#define MUX_MODE_1		0x00
-#define MUX_MODE_2		0x04
-#define MUX_MODE_3		0x0c
-#define MUX_MODE_4		0x1c
-
-#define MUX_DEBUG		0
-
-static const struct pin_config pin_table[] = {
-	/*		  reg	shift	mode	*/
-	TNETV107X_MUX_CFG(0,	0,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(0,	0,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(0,	5,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(0,	5,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(0,	10,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(0,	10,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(0,	15,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(0,	15,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(0,	20,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(0,	20,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(0,	25,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(0,	25,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(1,	0,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(1,	0,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(1,	5,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(1,	5,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(1,	10,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(1,	10,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(1,	15,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(1,	15,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(1,	20,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(1,	20,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(1,	25,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(1,	25,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(2,	0,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(2,	0,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(2,	5,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(2,	5,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(2,	10,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(2,	10,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(2,	15,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(2,	15,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(2,	20,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(2,	20,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(2,	25,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(2,	25,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(3,	0,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(3,	0,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(3,	0,	MUX_MODE_4),
-	TNETV107X_MUX_CFG(3,	5,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(3,	5,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(3,	5,	MUX_MODE_4),
-	TNETV107X_MUX_CFG(3,	10,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(3,	10,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(3,	10,	MUX_MODE_4),
-	TNETV107X_MUX_CFG(3,	15,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(3,	15,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(3,	15,	MUX_MODE_4),
-	TNETV107X_MUX_CFG(3,	20,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(3,	20,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(3,	20,	MUX_MODE_4),
-	TNETV107X_MUX_CFG(3,	25,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(3,	25,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(3,	25,	MUX_MODE_4),
-	TNETV107X_MUX_CFG(4,	0,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(4,	0,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(4,	0,	MUX_MODE_4),
-	TNETV107X_MUX_CFG(4,	5,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(4,	10,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(4,	15,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(4,	15,	MUX_MODE_4),
-	TNETV107X_MUX_CFG(4,	20,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(4,	20,	MUX_MODE_3),
-	TNETV107X_MUX_CFG(4,	25,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(4,	25,	MUX_MODE_4),
-	TNETV107X_MUX_CFG(5,	0,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(5,	0,	MUX_MODE_4),
-	TNETV107X_MUX_CFG(5,	5,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(5,	5,	MUX_MODE_4),
-	TNETV107X_MUX_CFG(5,	10,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(5,	10,	MUX_MODE_4),
-	TNETV107X_MUX_CFG(5,	15,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(5,	15,	MUX_MODE_4),
-	TNETV107X_MUX_CFG(5,	20,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(5,	20,	MUX_MODE_4),
-	TNETV107X_MUX_CFG(5,	25,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(5,	25,	MUX_MODE_4),
-	TNETV107X_MUX_CFG(6,	0,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(6,	0,	MUX_MODE_4),
-	TNETV107X_MUX_CFG(6,	5,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(6,	5,	MUX_MODE_4),
-	TNETV107X_MUX_CFG(6,	10,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(6,	10,	MUX_MODE_4),
-	TNETV107X_MUX_CFG(6,	15,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(6,	15,	MUX_MODE_4),
-	TNETV107X_MUX_CFG(6,	20,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(6,	20,	MUX_MODE_4),
-	TNETV107X_MUX_CFG(6,	25,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(6,	25,	MUX_MODE_4),
-	TNETV107X_MUX_CFG(7,	0,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(7,	0,	MUX_MODE_4),
-	TNETV107X_MUX_CFG(7,	5,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(7,	5,	MUX_MODE_4),
-	TNETV107X_MUX_CFG(7,	10,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(7,	10,	MUX_MODE_4),
-	TNETV107X_MUX_CFG(7,	15,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(7,	15,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(7,	20,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(7,	20,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(7,	25,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(7,	25,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(8,	0,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(8,	0,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(8,	5,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(8,	5,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(8,	5,	MUX_MODE_4),
-	TNETV107X_MUX_CFG(8,	10,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(8,	10,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(9,	0,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(9,	0,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(9,	0,	MUX_MODE_4),
-	TNETV107X_MUX_CFG(9,	5,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(9,	5,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(9,	5,	MUX_MODE_4),
-	TNETV107X_MUX_CFG(9,	10,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(9,	10,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(9,	10,	MUX_MODE_4),
-	TNETV107X_MUX_CFG(9,	15,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(9,	15,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(9,	15,	MUX_MODE_4),
-	TNETV107X_MUX_CFG(9,	20,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(9,	20,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(9,	20,	MUX_MODE_4),
-	TNETV107X_MUX_CFG(10,	0,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(10,	0,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(10,	5,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(10,	5,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(10,	10,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(10,	10,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(10,	15,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(10,	15,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(10,	20,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(10,	20,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(10,	25,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(10,	25,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(11,	0,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(11,	5,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(12,	0,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(12,	5,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(12,	10,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(12,	15,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(12,	20,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(12,	25,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(13,	0,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(13,	5,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(13,	10,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(13,	15,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(14,	0,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(14,	5,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(14,	10,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(14,	15,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(14,	20,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(14,	25,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(15,	0,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(15,	0,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(15,	5,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(15,	5,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(15,	10,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(15,	15,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(15,	20,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(15,	25,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(16,	0,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(16,	5,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(16,	10,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(16,	10,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(16,	10,	MUX_MODE_3),
-	TNETV107X_MUX_CFG(16,	15,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(16,	15,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(17,	0,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(17,	0,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(17,	0,	MUX_MODE_3),
-	TNETV107X_MUX_CFG(17,	5,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(17,	5,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(17,	5,	MUX_MODE_3),
-	TNETV107X_MUX_CFG(17,	10,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(17,	10,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(17,	10,	MUX_MODE_3),
-	TNETV107X_MUX_CFG(17,	15,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(17,	15,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(17,	15,	MUX_MODE_3),
-	TNETV107X_MUX_CFG(18,	0,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(18,	0,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(18,	0,	MUX_MODE_3),
-	TNETV107X_MUX_CFG(18,	5,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(18,	5,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(18,	5,	MUX_MODE_3),
-	TNETV107X_MUX_CFG(18,	10,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(18,	10,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(18,	10,	MUX_MODE_3),
-	TNETV107X_MUX_CFG(18,	15,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(18,	15,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(18,	15,	MUX_MODE_3),
-	TNETV107X_MUX_CFG(19,	0,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(19,	5,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(19,	10,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(19,	15,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(19,	20,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(19,	25,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(20,	0,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(20,	5,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(20,	10,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(20,	15,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(20,	15,	MUX_MODE_3),
-	TNETV107X_MUX_CFG(20,	20,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(20,	25,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(21,	0,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(21,	5,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(21,	10,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(21,	15,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(21,	20,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(21,	25,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(22,	0,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(22,	5,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(22,	5,	MUX_MODE_3),
-	TNETV107X_MUX_CFG(22,	10,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(22,	10,	MUX_MODE_3),
-	TNETV107X_MUX_CFG(22,	15,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(22,	15,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(22,	15,	MUX_MODE_3),
-	TNETV107X_MUX_CFG(22,	20,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(22,	20,	MUX_MODE_3),
-	TNETV107X_MUX_CFG(22,	25,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(22,	25,	MUX_MODE_3),
-	TNETV107X_MUX_CFG(23,	0,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(23,	0,	MUX_MODE_3),
-	TNETV107X_MUX_CFG(23,	5,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(23,	5,	MUX_MODE_3),
-	TNETV107X_MUX_CFG(23,	10,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(23,	10,	MUX_MODE_3),
-	TNETV107X_MUX_CFG(24,	0,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(24,	0,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(24,	5,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(24,	5,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(24,	10,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(24,	10,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(24,	10,	MUX_MODE_3),
-	TNETV107X_MUX_CFG(24,	15,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(24,	15,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(24,	15,	MUX_MODE_3),
-	TNETV107X_MUX_CFG(24,	20,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(24,	20,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(24,	25,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(24,	25,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(25,	0,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(25,	0,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(25,	0,	MUX_MODE_3),
-	TNETV107X_MUX_CFG(25,	5,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(25,	5,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(25,	5,	MUX_MODE_3),
-	TNETV107X_MUX_CFG(25,	10,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(25,	10,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(25,	10,	MUX_MODE_3),
-	TNETV107X_MUX_CFG(25,	15,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(25,	15,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(25,	15,	MUX_MODE_3),
-	TNETV107X_MUX_CFG(25,	15,	MUX_MODE_4),
-	TNETV107X_MUX_CFG(26,	0,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(26,	5,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(26,	10,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(26,	10,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(26,	15,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(26,	15,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(26,	20,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(26,	20,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(26,	25,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(26,	25,	MUX_MODE_2),
-};
-
-const int pin_table_size = sizeof(pin_table) / sizeof(pin_table[0]);
-
-int mux_select_pin(short index)
-{
-	const struct pin_config *cfg;
-	unsigned long mask, mode, reg;
-
-	if (index >= pin_table_size)
-		return 0;
-
-	cfg = &pin_table[index];
-
-	mask = 0x1f << cfg->mask_offset;
-	mode = cfg->mode << cfg->mask_offset;
-
-	reg = __raw_readl(TNETV107X_PINMUX(cfg->reg_index));
-	reg = (reg & ~mask) | mode;
-	__raw_writel(reg, TNETV107X_PINMUX(cfg->reg_index));
-
-	return 1;
-}
-
-int mux_select_pins(const short *pins)
-{
-	int i, ret = 1;
-
-	for (i = 0; pins[i] >= 0; i++)
-		ret &= mux_select_pin(pins[i]);
-
-	return ret;
-}
diff --git a/arch/arm/cpu/arm1176/tnetv107x/timer.c b/arch/arm/cpu/arm1176/tnetv107x/timer.c
deleted file mode 100644
index a7a400d..0000000
--- a/arch/arm/cpu/arm1176/tnetv107x/timer.c
+++ /dev/null
@@ -1,122 +0,0 @@
-/*
- * TNETV107X: Timer implementation
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/clock.h>
-
-struct timer_regs {
-	u_int32_t pid12;
-	u_int32_t pad[3];
-	u_int32_t tim12;
-	u_int32_t tim34;
-	u_int32_t prd12;
-	u_int32_t prd34;
-	u_int32_t tcr;
-	u_int32_t tgcr;
-	u_int32_t wdtcr;
-};
-
-#define regs ((struct timer_regs *)CONFIG_SYS_TIMERBASE)
-
-#define TIMER_LOAD_VAL	(CONFIG_SYS_HZ_CLOCK / CONFIG_SYS_HZ)
-#define TIM_CLK_DIV	16
-
-static ulong timestamp;
-static ulong lastinc;
-
-int timer_init(void)
-{
-	clk_enable(TNETV107X_LPSC_TIMER0);
-
-	lastinc = timestamp = 0;
-
-	/* We are using timer34 in unchained 32-bit mode, full speed */
-	__raw_writel(0x0, &regs->tcr);
-	__raw_writel(0x0, &regs->tgcr);
-	__raw_writel(0x06 | ((TIM_CLK_DIV - 1) << 8), &regs->tgcr);
-	__raw_writel(0x0, &regs->tim34);
-	__raw_writel(TIMER_LOAD_VAL, &regs->prd34);
-	__raw_writel(2 << 22, &regs->tcr);
-
-	return 0;
-}
-
-void reset_timer(void)
-{
-	lastinc = timestamp = 0;
-
-	__raw_writel(0,		&regs->tcr);
-	__raw_writel(0,		&regs->tim34);
-	__raw_writel(2 << 22,	&regs->tcr);
-}
-
-static ulong get_timer_raw(void)
-{
-	ulong now = __raw_readl(&regs->tim34);
-
-	if (now >= lastinc)
-		timestamp += now - lastinc;
-	else
-		timestamp += now + TIMER_LOAD_VAL - lastinc;
-
-	lastinc = now;
-
-	return timestamp;
-}
-
-ulong get_timer(ulong base)
-{
-	return (get_timer_raw() / (TIMER_LOAD_VAL / TIM_CLK_DIV)) - base;
-}
-
-void set_timer(ulong t)
-{
-	timestamp = t;
-}
-
-unsigned long long get_ticks(void)
-{
-	return get_timer(0);
-}
-
-void __udelay(unsigned long usec)
-{
-	ulong tmo;
-	ulong endtime;
-	signed long diff;
-
-	tmo = CONFIG_SYS_HZ_CLOCK / 1000;
-	tmo *= usec;
-	tmo /= (1000 * TIM_CLK_DIV);
-
-	endtime = get_timer_raw() + tmo;
-
-	do {
-		ulong now = get_timer_raw();
-		diff = endtime - now;
-	} while (diff >= 0);
-}
-
-ulong get_tbclk(void)
-{
-	return CONFIG_SYS_HZ;
-}
diff --git a/arch/arm/cpu/arm1176/tnetv107x/wdt.c b/arch/arm/cpu/arm1176/tnetv107x/wdt.c
deleted file mode 100644
index 18aadb0..0000000
--- a/arch/arm/cpu/arm1176/tnetv107x/wdt.c
+++ /dev/null
@@ -1,180 +0,0 @@
-/*
- * TNETV107X: Watchdog timer implementation (for reset)
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/clock.h>
-
-#define MAX_DIV		0xFFFE0001
-
-struct wdt_regs {
-	u32 kick_lock;
-#define KICK_LOCK_1	0x5555
-#define KICK_LOCK_2	0xaaaa
-	u32 kick;
-
-	u32 change_lock;
-#define CHANGE_LOCK_1	0x6666
-#define CHANGE_LOCK_2	0xbbbb
-	u32 change;
-
-	u32 disable_lock;
-#define DISABLE_LOCK_1	0x7777
-#define DISABLE_LOCK_2	0xcccc
-#define DISABLE_LOCK_3	0xdddd
-	u32 disable;
-
-	u32 prescale_lock;
-#define PRESCALE_LOCK_1	0x5a5a
-#define PRESCALE_LOCK_2	0xa5a5
-	u32 prescale;
-};
-
-static struct wdt_regs* regs = (struct wdt_regs *)TNETV107X_WDT0_ARM_BASE;
-
-#define wdt_reg_read(reg)	__raw_readl(&regs->reg)
-#define wdt_reg_write(reg, val)	__raw_writel((val), &regs->reg)
-
-static int write_prescale_reg(unsigned long prescale_value)
-{
-	wdt_reg_write(prescale_lock, PRESCALE_LOCK_1);
-	if ((wdt_reg_read(prescale_lock) & 0x3) != 0x1)
-		return -1;
-
-	wdt_reg_write(prescale_lock, PRESCALE_LOCK_2);
-	if ((wdt_reg_read(prescale_lock) & 0x3) != 0x3)
-		return -1;
-
-	wdt_reg_write(prescale, prescale_value);
-
-	return 0;
-}
-
-static int write_change_reg(unsigned long initial_timer_value)
-{
-	wdt_reg_write(change_lock, CHANGE_LOCK_1);
-	if ((wdt_reg_read(change_lock) & 0x3) != 0x1)
-		return -1;
-
-	wdt_reg_write(change_lock, CHANGE_LOCK_2);
-	if ((wdt_reg_read(change_lock) & 0x3) != 0x3)
-		return -1;
-
-	wdt_reg_write(change, initial_timer_value);
-
-	return 0;
-}
-
-static int wdt_control(unsigned long disable_value)
-{
-	wdt_reg_write(disable_lock, DISABLE_LOCK_1);
-	if ((wdt_reg_read(disable_lock) & 0x3) != 0x1)
-		return -1;
-
-	wdt_reg_write(disable_lock, DISABLE_LOCK_2);
-	if ((wdt_reg_read(disable_lock) & 0x3) != 0x2)
-		return -1;
-
-	wdt_reg_write(disable_lock, DISABLE_LOCK_3);
-	if ((wdt_reg_read(disable_lock) & 0x3) != 0x3)
-		return -1;
-
-	wdt_reg_write(disable, disable_value);
-	return 0;
-}
-
-static int wdt_set_period(unsigned long msec)
-{
-	unsigned long change_value, count_value;
-	unsigned long prescale_value = 1;
-	unsigned long refclk_khz, maxdiv;
-	int ret;
-
-	refclk_khz = clk_get_rate(TNETV107X_LPSC_WDT_ARM);
-	maxdiv = (MAX_DIV / refclk_khz);
-
-	if ((!msec) || (msec > maxdiv))
-		return -1;
-
-	count_value = refclk_khz * msec;
-	if (count_value > 0xffff) {
-		change_value = count_value / 0xffff + 1;
-		prescale_value = count_value / change_value;
-	} else {
-		change_value = count_value;
-	}
-
-	ret = write_prescale_reg(prescale_value - 1);
-	if (ret)
-		return ret;
-
-	ret = write_change_reg(change_value);
-	if (ret)
-		return ret;
-
-	return 0;
-}
-
-unsigned long last_wdt = -1;
-
-int wdt_start(unsigned long msecs)
-{
-	int ret;
-	ret = wdt_control(0);
-	if (ret)
-		return ret;
-	ret = wdt_set_period(msecs);
-	if (ret)
-		return ret;
-	ret = wdt_control(1);
-	if (ret)
-		return ret;
-	ret = wdt_kick();
-	last_wdt = msecs;
-	return ret;
-}
-
-int wdt_stop(void)
-{
-	last_wdt = -1;
-	return wdt_control(0);
-}
-
-int wdt_kick(void)
-{
-	wdt_reg_write(kick_lock, KICK_LOCK_1);
-	if ((wdt_reg_read(kick_lock) & 0x3) != 0x1)
-		return -1;
-
-	wdt_reg_write(kick_lock, KICK_LOCK_2);
-	if ((wdt_reg_read(kick_lock) & 0x3) != 0x3)
-		return -1;
-
-	wdt_reg_write(kick, 1);
-	return 0;
-}
-
-void reset_cpu(ulong addr)
-{
-	clk_enable(TNETV107X_LPSC_WDT_ARM);
-	wdt_start(1);
-	wdt_kick();
-}
diff --git a/arch/arm/cpu/arm1176/u-boot.lds b/arch/arm/cpu/arm1176/u-boot.lds
deleted file mode 100644
index fe31800..0000000
--- a/arch/arm/cpu/arm1176/u-boot.lds
+++ /dev/null
@@ -1,76 +0,0 @@
-/*
- * (C) Copyright 2002-2004
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-ENTRY(_start)
-SECTIONS
-{
-	. = 0x00000000;
-
-	. = ALIGN(4);
-	.text :
-	{
-		arch/arm/cpu/arm1176/start.o	(.text)
-		*(.text)
-	}
-
-	. = ALIGN(4);
-	.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
-
-	. = ALIGN(4);
-	.data : {
-		*(.data)
-	}
-
-	. = .;
-	__u_boot_cmd_start = .;
-	.u_boot_cmd : { *(.u_boot_cmd) }
-	__u_boot_cmd_end = .;
-
-	. = ALIGN(4);
-
-	.rel.dyn : {
-		__rel_dyn_start = .;
-		*(.rel*)
-		__rel_dyn_end = .;
-	}
-
-	.dynsym : {
-		__dynsym_start = .;
-		*(.dynsym)
-	}
-
-	.bss __rel_dyn_start (OVERLAY) : {
-		__bss_start = .;
-		*(.bss)
-		 . = ALIGN(4);
-		_end = .;
-	}
-
-	/DISCARD/ : { *(.dynstr*) }
-	/DISCARD/ : { *(.dynamic*) }
-	/DISCARD/ : { *(.plt*) }
-	/DISCARD/ : { *(.interp*) }
-	/DISCARD/ : { *(.gnu*) }
-}
diff --git a/arch/arm/cpu/arm720t/Makefile b/arch/arm/cpu/arm720t/Makefile
deleted file mode 100644
index 1a097b5..0000000
--- a/arch/arm/cpu/arm720t/Makefile
+++ /dev/null
@@ -1,47 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(CPU).o
-
-START	= start.o
-COBJS	= interrupts.o cpu.o
-
-SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS) $(SOBJS))
-START	:= $(addprefix $(obj),$(START))
-
-all:	$(obj).depend $(START) $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/arch/arm/cpu/arm720t/config.mk b/arch/arm/cpu/arm720t/config.mk
deleted file mode 100644
index 3844c62..0000000
--- a/arch/arm/cpu/arm720t/config.mk
+++ /dev/null
@@ -1,33 +0,0 @@
-#
-# (C) Copyright 2002
-# Sysgo Real-Time Solutions, GmbH <www.elinos.com>
-# Marius Groeger <mgroeger@sysgo.de>
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-PLATFORM_RELFLAGS +=  -fno-common -ffixed-r8 -msoft-float
-
-PLATFORM_CPPFLAGS += -march=armv4 -mtune=arm7tdmi
-# =========================================================================
-#
-# Supply options according to compiler version
-#
-# =========================================================================
-PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))
diff --git a/arch/arm/cpu/arm720t/cpu.c b/arch/arm/cpu/arm720t/cpu.c
deleted file mode 100644
index 88c71bf..0000000
--- a/arch/arm/cpu/arm720t/cpu.c
+++ /dev/null
@@ -1,90 +0,0 @@
-/*
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Alex Zuepke <azu@sysgo.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * CPU specific code
- */
-
-#include <common.h>
-#include <command.h>
-#include <clps7111.h>
-#include <asm/hardware.h>
-#include <asm/system.h>
-
-#if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_ARMADILLO)
-static void cache_flush(void);
-#endif
-
-int cleanup_before_linux (void)
-{
-	/*
-	 * this function is called just before we call linux
-	 * it prepares the processor for linux
-	 *
-	 * we turn off caches etc ...
-	 * and we set the CPU-speed to 73 MHz - see start.S for details
-	 */
-
-#if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_ARMADILLO)
-	disable_interrupts ();
-
-	/* turn off I-cache */
-	icache_disable();
-	dcache_disable();
-
-	/* flush I-cache */
-	cache_flush();
-#ifdef CONFIG_ARM7_REVD
-	/* go to high speed */
-	IO_SYSCON3 = (IO_SYSCON3 & ~CLKCTL) | CLKCTL_73;
-#endif
-#elif defined(CONFIG_NETARM) || defined(CONFIG_S3C4510B) || defined(CONFIG_LPC2292)
-	disable_interrupts ();
-	/* Nothing more needed */
-#elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
-	/* No cleanup before linux for IntegratorAP/CM720T as yet */
-#else
-#error No cleanup_before_linux() defined for this CPU type
-#endif
-	return 0;
-}
-
-#if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_ARMADILLO)
-/* flush I/D-cache */
-static void cache_flush (void)
-{
-	unsigned long i = 0;
-
-	asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i));
-}
-#elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
-	/* No specific cache setup for IntegratorAP/CM720T as yet */
-	void icache_enable (void)
-	{
-	}
-#endif
diff --git a/arch/arm/cpu/arm720t/interrupts.c b/arch/arm/cpu/arm720t/interrupts.c
deleted file mode 100644
index eb8d425..0000000
--- a/arch/arm/cpu/arm720t/interrupts.c
+++ /dev/null
@@ -1,316 +0,0 @@
-/*
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Alex Zuepke <azu@sysgo.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <clps7111.h>
-#include <asm/proc-armv/ptrace.h>
-#include <asm/hardware.h>
-
-#ifndef CONFIG_NETARM
-/* we always count down the max. */
-#define TIMER_LOAD_VAL 0xffff
-/* macro to read the 16 bit timer */
-#define READ_TIMER (IO_TC1D & 0xffff)
-
-#ifdef CONFIG_LPC2292
-#undef READ_TIMER
-#define READ_TIMER (0xFFFFFFFF - GET32(T0TC))
-#endif
-
-#else
-#define IRQEN	(*(volatile unsigned int *)(NETARM_GEN_MODULE_BASE + NETARM_GEN_INTR_ENABLE))
-#define TM2CTRL (*(volatile unsigned int *)(NETARM_GEN_MODULE_BASE + NETARM_GEN_TIMER2_CONTROL))
-#define TM2STAT (*(volatile unsigned int *)(NETARM_GEN_MODULE_BASE + NETARM_GEN_TIMER2_STATUS))
-#define TIMER_LOAD_VAL NETARM_GEN_TSTAT_CTC_MASK
-#define READ_TIMER (TM2STAT & NETARM_GEN_TSTAT_CTC_MASK)
-#endif
-
-#ifdef CONFIG_S3C4510B
-/* require interrupts for the S3C4510B */
-# ifndef CONFIG_USE_IRQ
-#  error CONFIG_USE_IRQ _must_ be defined when using CONFIG_S3C4510B
-# else
-static struct _irq_handler IRQ_HANDLER[N_IRQS];
-# endif
-#endif	/* CONFIG_S3C4510B */
-
-#ifdef CONFIG_USE_IRQ
-void do_irq (struct pt_regs *pt_regs)
-{
-#if defined(CONFIG_S3C4510B)
-	unsigned int pending;
-
-	while ( (pending = GET_REG( REG_INTOFFSET)) != 0x54) {  /* sentinal value for no pending interrutps */
-		IRQ_HANDLER[pending>>2].m_func( IRQ_HANDLER[pending>>2].m_data);
-
-		/* clear pending interrupt */
-		PUT_REG( REG_INTPEND, (1<<(pending>>2)));
-	}
-#elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
-	/* No do_irq() for IntegratorAP/CM720T as yet */
-#elif defined(CONFIG_LPC2292)
-
-    void (*pfnct)(void);
-
-    pfnct = (void (*)(void))VICVectAddr;
-
-    (*pfnct)();
-#else
-#error do_irq() not defined for this CPU type
-#endif
-}
-#endif
-
-#ifdef CONFIG_S3C4510B
-static void default_isr( void *data) {
-	printf ("default_isr():  called for IRQ %d\n", (int)data);
-}
-
-static void timer_isr( void *data) {
-	unsigned int *pTime = (unsigned int *)data;
-
-	(*pTime)++;
-	if ( !(*pTime % (CONFIG_SYS_HZ/4))) {
-		/* toggle LED 0 */
-		PUT_REG( REG_IOPDATA, GET_REG(REG_IOPDATA) ^ 0x1);
-	}
-
-}
-#endif
-
-#if defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
-	/* Use IntegratorAP routines in board/integratorap.c */
-#else
-
-static ulong timestamp;
-static ulong lastdec;
-
-#if defined(CONFIG_USE_IRQ) && defined(CONFIG_S3C4510B)
-int arch_interrupt_init (void)
-{
-	int i;
-
-	/* install default interrupt handlers */
-	for ( i = 0; i < N_IRQS; i++) {
-		IRQ_HANDLER[i].m_data = (void *)i;
-		IRQ_HANDLER[i].m_func = default_isr;
-	}
-
-	/* configure interrupts for IRQ mode */
-	PUT_REG( REG_INTMODE, 0x0);
-	/* clear any pending interrupts */
-	PUT_REG( REG_INTPEND, 0x1FFFFF);
-
-	lastdec = 0;
-
-	/* install interrupt handler for timer */
-	IRQ_HANDLER[INT_TIMER0].m_data = (void *)&timestamp;
-	IRQ_HANDLER[INT_TIMER0].m_func = timer_isr;
-
-	return 0;
-}
-#endif
-
-int timer_init (void)
-{
-#if defined(CONFIG_NETARM)
-	/* disable all interrupts */
-	IRQEN = 0;
-
-	/* operate timer 2 in non-prescale mode */
-	TM2CTRL = ( NETARM_GEN_TIMER_SET_HZ(CONFIG_SYS_HZ) |
-		    NETARM_GEN_TCTL_ENABLE |
-		    NETARM_GEN_TCTL_INIT_COUNT(TIMER_LOAD_VAL));
-
-	/* set timer 2 counter */
-	lastdec = TIMER_LOAD_VAL;
-#elif defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_ARMADILLO)
-	/* disable all interrupts */
-	IO_INTMR1 = 0;
-
-	/* operate timer 1 in prescale mode */
-	IO_SYSCON1 |= SYSCON1_TC1M;
-
-	/* select 2kHz clock source for timer 1 */
-	IO_SYSCON1 &= ~SYSCON1_TC1S;
-
-	/* set timer 1 counter */
-	lastdec = IO_TC1D = TIMER_LOAD_VAL;
-#elif defined(CONFIG_S3C4510B)
-	/* configure free running timer 0 */
-	PUT_REG( REG_TMOD, 0x0);
-	/* Stop timer 0 */
-	CLR_REG( REG_TMOD, TM0_RUN);
-
-	/* Configure for interval mode */
-	CLR_REG( REG_TMOD, TM1_TOGGLE);
-
-	/*
-	 * Load Timer data register with count down value.
-	 * count_down_val = CONFIG_SYS_SYS_CLK_FREQ/CONFIG_SYS_HZ
-	 */
-	PUT_REG( REG_TDATA0, (CONFIG_SYS_SYS_CLK_FREQ / CONFIG_SYS_HZ));
-
-	/*
-	 * Enable global interrupt
-	 * Enable timer0 interrupt
-	 */
-	CLR_REG( REG_INTMASK, ((1<<INT_GLOBAL) | (1<<INT_TIMER0)));
-
-	/* Start timer */
-	SET_REG( REG_TMOD, TM0_RUN);
-#elif defined(CONFIG_LPC2292)
-	PUT32(T0IR, 0);		/* disable all timer0 interrupts */
-	PUT32(T0TCR, 0);	/* disable timer0 */
-	PUT32(T0PR, CONFIG_SYS_SYS_CLK_FREQ / CONFIG_SYS_HZ);
-	PUT32(T0MCR, 0);
-	PUT32(T0TC, 0);
-	PUT32(T0TCR, 1);	/* enable timer0 */
-
-#else
-#error No timer_init() defined for this CPU type
-#endif
-	timestamp = 0;
-
-	return (0);
-}
-
-#endif /* ! IntegratorAP */
-
-/*
- * timer without interrupts
- */
-
-
-#if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_NETARM) || defined(CONFIG_ARMADILLO) || defined(CONFIG_LPC2292)
-
-void reset_timer (void)
-{
-	reset_timer_masked ();
-}
-
-ulong get_timer (ulong base)
-{
-	return get_timer_masked () - base;
-}
-
-void set_timer (ulong t)
-{
-	timestamp = t;
-}
-
-void __udelay (unsigned long usec)
-{
-	ulong tmo;
-
-	tmo = usec / 1000;
-	tmo *= CONFIG_SYS_HZ;
-	tmo /= 1000;
-
-	tmo += get_timer (0);
-
-	while (get_timer_masked () < tmo)
-#ifdef CONFIG_LPC2292
-		/* GJ - not sure whether this is really needed or a misunderstanding */
-		__asm__ __volatile__(" nop");
-#else
-		/*NOP*/;
-#endif
-}
-
-void reset_timer_masked (void)
-{
-	/* reset time */
-	lastdec = READ_TIMER;
-	timestamp = 0;
-}
-
-ulong get_timer_masked (void)
-{
-	ulong now = READ_TIMER;
-
-	if (lastdec >= now) {
-		/* normal mode */
-		timestamp += lastdec - now;
-	} else {
-		/* we have an overflow ... */
-		timestamp += lastdec + TIMER_LOAD_VAL - now;
-	}
-	lastdec = now;
-
-	return timestamp;
-}
-
-void udelay_masked (unsigned long usec)
-{
-	ulong tmo;
-	ulong endtime;
-	signed long diff;
-
-	if (usec >= 1000) {
-		tmo = usec / 1000;
-		tmo *= CONFIG_SYS_HZ;
-		tmo /= 1000;
-	} else {
-		tmo = usec * CONFIG_SYS_HZ;
-		tmo /= (1000*1000);
-	}
-
-	endtime = get_timer_masked () + tmo;
-
-	do {
-		ulong now = get_timer_masked ();
-		diff = endtime - now;
-	} while (diff >= 0);
-}
-
-#elif defined(CONFIG_S3C4510B)
-
-ulong get_timer (ulong base)
-{
-	return timestamp - base;
-}
-
-void __udelay (unsigned long usec)
-{
-	u32 ticks;
-
-	ticks = (usec * CONFIG_SYS_HZ) / 1000000;
-
-	ticks += get_timer (0);
-
-	while (get_timer (0) < ticks)
-		/*NOP*/;
-
-}
-
-#elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
-	/* No timer routines for IntegratorAP/CM720T as yet */
-#else
-#error Timer routines not defined for this CPU type
-#endif
diff --git a/arch/arm/cpu/arm720t/lpc2292/Makefile b/arch/arm/cpu/arm720t/lpc2292/Makefile
deleted file mode 100644
index 1b93008..0000000
--- a/arch/arm/cpu/arm720t/lpc2292/Makefile
+++ /dev/null
@@ -1,50 +0,0 @@
-#
-# (C) Copyright 2000-2007
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(SOC).o
-
-COBJS	= flash.o mmc.o mmc_hw.o spi.o
-SOBJS	= $(obj)iap_entry.o
-
-SRCS	:= $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-
-all:	$(obj).depend $(LIB)
-
-$(LIB):	$(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-# this MUST be compiled as thumb code!
-$(SOBJS):
-	$(CC) $(AFLAGS) -march=armv4t -c -o $(SOBJS) iap_entry.S
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/arch/arm/cpu/arm720t/lpc2292/flash.c b/arch/arm/cpu/arm720t/lpc2292/flash.c
deleted file mode 100644
index 3d2dc32..0000000
--- a/arch/arm/cpu/arm720t/lpc2292/flash.c
+++ /dev/null
@@ -1,249 +0,0 @@
-/*
- * (C) Copyright 2006 Embedded Artists AB <www.embeddedartists.com>
- *
- * Modified to remove all but the IAP-command related code by
- * Gary Jennejohn <garyj@denx.de>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/arch/hardware.h>
-
-/* IAP commands use 32 bytes at the top of CPU internal sram, we
-   use 512 bytes below that */
-#define COPY_BUFFER_LOCATION 0x40003de0
-
-#define IAP_LOCATION 0x7ffffff1
-#define IAP_CMD_PREPARE 50
-#define IAP_CMD_COPY 51
-#define IAP_CMD_ERASE 52
-#define IAP_CMD_CHECK 53
-#define IAP_CMD_ID 54
-#define IAP_CMD_VERSION 55
-#define IAP_CMD_COMPARE 56
-
-#define IAP_RET_CMD_SUCCESS 0
-
-static unsigned long command[5];
-static unsigned long result[2];
-
-extern void iap_entry(unsigned long * command, unsigned long * result);
-
-/*-----------------------------------------------------------------------
- *
- */
-static int get_flash_sector(flash_info_t * info, ulong flash_addr)
-{
-	int i;
-
-	for(i = 1; i < (info->sector_count); i++) {
-		if (flash_addr < (info->start[i]))
-			break;
-	}
-
-	return (i-1);
-}
-
-/*-----------------------------------------------------------------------
- * This function assumes that flash_addr is aligned on 512 bytes boundary
- * in flash. This function also assumes that prepare have been called
- * for the sector in question.
- */
-int lpc2292_copy_buffer_to_flash(flash_info_t * info, ulong flash_addr)
-{
-	int first_sector;
-	int last_sector;
-
-	first_sector = get_flash_sector(info, flash_addr);
-	last_sector = get_flash_sector(info, flash_addr + 512 - 1);
-
-	/* prepare sectors for write */
-	command[0] = IAP_CMD_PREPARE;
-	command[1] = first_sector;
-	command[2] = last_sector;
-	iap_entry(command, result);
-	if (result[0] != IAP_RET_CMD_SUCCESS) {
-		printf("IAP prepare failed\n");
-		return ERR_PROG_ERROR;
-	}
-
-	command[0] = IAP_CMD_COPY;
-	command[1] = flash_addr;
-	command[2] = COPY_BUFFER_LOCATION;
-	command[3] = 512;
-	command[4] = CONFIG_SYS_SYS_CLK_FREQ >> 10;
-	iap_entry(command, result);
-	if (result[0] != IAP_RET_CMD_SUCCESS) {
-		printf("IAP copy failed\n");
-		return 1;
-	}
-
-	return 0;
-}
-
-/*-----------------------------------------------------------------------
- */
-
-int lpc2292_flash_erase (flash_info_t * info, int s_first, int s_last)
-{
-	int flag;
-	int prot;
-	int sect;
-
-	prot = 0;
-	for (sect = s_first; sect <= s_last; ++sect) {
-		if (info->protect[sect]) {
-			prot++;
-		}
-	}
-	if (prot)
-		return ERR_PROTECTED;
-
-
-	flag = disable_interrupts();
-
-	printf ("Erasing %d sectors starting at sector %2d.\n"
-	"This make take some time ... ",
-	s_last - s_first + 1, s_first);
-
-	command[0] = IAP_CMD_PREPARE;
-	command[1] = s_first;
-	command[2] = s_last;
-	iap_entry(command, result);
-	if (result[0] != IAP_RET_CMD_SUCCESS) {
-		printf("IAP prepare failed\n");
-		return ERR_PROTECTED;
-	}
-
-	command[0] = IAP_CMD_ERASE;
-	command[1] = s_first;
-	command[2] = s_last;
-	command[3] = CONFIG_SYS_SYS_CLK_FREQ >> 10;
-	iap_entry(command, result);
-	if (result[0] != IAP_RET_CMD_SUCCESS) {
-		printf("IAP erase failed\n");
-		return ERR_PROTECTED;
-	}
-
-	if (flag)
-		enable_interrupts();
-
-	return ERR_OK;
-}
-
-int lpc2292_write_buff (flash_info_t * info, uchar * src, ulong addr,
-			ulong cnt)
-{
-	int first_copy_size;
-	int last_copy_size;
-	int first_block;
-	int last_block;
-	int nbr_mid_blocks;
-	uchar memmap_value;
-	ulong i;
-	uchar* src_org;
-	uchar* dst_org;
-	int ret = ERR_OK;
-
-	src_org = src;
-	dst_org = (uchar*)addr;
-
-	first_block = addr / 512;
-	last_block = (addr + cnt) / 512;
-	nbr_mid_blocks = last_block - first_block - 1;
-
-	first_copy_size = 512 - (addr % 512);
-	last_copy_size = (addr + cnt) % 512;
-
-	debug("\ncopy first block: (1) %lX -> %lX 0x200 bytes, "
-		"(2) %lX -> %lX 0x%X bytes, (3) %lX -> %lX 0x200 bytes\n",
-	(ulong)(first_block * 512),
-	(ulong)COPY_BUFFER_LOCATION,
-	(ulong)src,
-	(ulong)(COPY_BUFFER_LOCATION + 512 - first_copy_size),
-	first_copy_size,
-	(ulong)COPY_BUFFER_LOCATION,
-	(ulong)(first_block * 512));
-
-	/* copy first block */
-	memcpy((void*)COPY_BUFFER_LOCATION,
-		(void*)(first_block * 512), 512);
-	memcpy((void*)(COPY_BUFFER_LOCATION + 512 - first_copy_size),
-		src, first_copy_size);
-	lpc2292_copy_buffer_to_flash(info, first_block * 512);
-	src += first_copy_size;
-	addr += first_copy_size;
-
-	/* copy middle blocks */
-	for (i = 0; i < nbr_mid_blocks; i++) {
-		debug("copy middle block: %lX -> %lX 512 bytes, "
-		"%lX -> %lX 512 bytes\n",
-		(ulong)src,
-		(ulong)COPY_BUFFER_LOCATION,
-		(ulong)COPY_BUFFER_LOCATION,
-		(ulong)addr);
-
-		memcpy((void*)COPY_BUFFER_LOCATION, src, 512);
-		lpc2292_copy_buffer_to_flash(info, addr);
-		src += 512;
-		addr += 512;
-	}
-
-
-	if (last_copy_size > 0) {
-		debug("copy last block: (1) %lX -> %lX 0x200 bytes, "
-		"(2) %lX -> %lX 0x%X bytes, (3) %lX -> %lX x200 bytes\n",
-		(ulong)(last_block * 512),
-		(ulong)COPY_BUFFER_LOCATION,
-		(ulong)src,
-		(ulong)(COPY_BUFFER_LOCATION),
-		last_copy_size,
-		(ulong)COPY_BUFFER_LOCATION,
-		(ulong)addr);
-
-		/* copy last block */
-		memcpy((void*)COPY_BUFFER_LOCATION,
-			(void*)(last_block * 512), 512);
-		memcpy((void*)COPY_BUFFER_LOCATION,
-			src, last_copy_size);
-		lpc2292_copy_buffer_to_flash(info, addr);
-	}
-
-	/* verify write */
-	memmap_value = GET8(MEMMAP);
-
-	disable_interrupts();
-
-	PUT8(MEMMAP, 01);		/* we must make sure that initial 64
-							   bytes are taken from flash when we
-							   do the compare */
-
-	for (i = 0; i < cnt; i++) {
-		if (*dst_org != *src_org){
-			printf("Write failed. Byte %lX differs\n", i);
-			ret = ERR_PROG_ERROR;
-			break;
-		}
-		dst_org++;
-		src_org++;
-	}
-
-	PUT8(MEMMAP, memmap_value);
-	enable_interrupts();
-
-	return ret;
-}
diff --git a/arch/arm/cpu/arm720t/lpc2292/iap_entry.S b/arch/arm/cpu/arm720t/lpc2292/iap_entry.S
deleted file mode 100644
index c31d519..0000000
--- a/arch/arm/cpu/arm720t/lpc2292/iap_entry.S
+++ /dev/null
@@ -1,7 +0,0 @@
-IAP_ADDRESS:	.word	0x7FFFFFF1
-
-.globl iap_entry
-iap_entry:
-	ldr	r2, IAP_ADDRESS
-	bx	r2
-	mov	pc, lr
diff --git a/arch/arm/cpu/arm720t/lpc2292/mmc.c b/arch/arm/cpu/arm720t/lpc2292/mmc.c
deleted file mode 100644
index beaffe9..0000000
--- a/arch/arm/cpu/arm720t/lpc2292/mmc.c
+++ /dev/null
@@ -1,131 +0,0 @@
-/*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <common.h>
-#include <mmc.h>
-#include <asm/errno.h>
-#include <asm/arch/hardware.h>
-#include <part.h>
-#include <fat.h>
-#include "mmc_hw.h"
-#include <asm/arch/spi.h>
-
-#ifdef CONFIG_MMC
-
-#undef MMC_DEBUG
-
-static block_dev_desc_t mmc_dev;
-
-/* these are filled out by a call to mmc_hw_get_parameters */
-static int hw_size;		/* in kbytes */
-static int hw_nr_sects;
-static int hw_sect_size;	/* in bytes */
-
-block_dev_desc_t * mmc_get_dev(int dev)
-{
-	return (block_dev_desc_t *)(&mmc_dev);
-}
-
-unsigned long mmc_block_read(int dev,
-			     unsigned long start,
-			     lbaint_t blkcnt,
-			     void *buffer)
-{
-	unsigned long rc = 0;
-	unsigned char *p = (unsigned char *)buffer;
-	unsigned long i;
-	unsigned long addr = start;
-
-#ifdef MMC_DEBUG
-	printf("mmc_block_read: start=%lu, blkcnt=%lu\n", start,
-		 (unsigned long)blkcnt);
-#endif
-
-	for(i = 0; i < (unsigned long)blkcnt; i++) {
-#ifdef MMC_DEBUG
-		printf("mmc_read_sector: addr=%lu, buffer=%p\n", addr, p);
-#endif
-		(void)mmc_read_sector(addr, p);
-		rc++;
-		addr++;
-		p += hw_sect_size;
-	}
-
-	return rc;
-}
-
-/*-----------------------------------------------------------------------------
- * Read hardware paramterers (sector size, size, number of sectors)
- */
-static int mmc_hw_get_parameters(void)
-{
-	unsigned char csddata[16];
-	unsigned int sizemult;
-	unsigned int size;
-
-	mmc_read_csd(csddata);
-	hw_sect_size = 1<<(csddata[5] & 0x0f);
-	size = ((csddata[6]&0x03)<<10)+(csddata[7]<<2)+(csddata[8]&0xc0);
-	sizemult = ((csddata[10] & 0x80)>>7)+((csddata[9] & 0x03)<<1);
-	hw_nr_sects = (size+1)*(1<<(sizemult+2));
-	hw_size = hw_nr_sects*hw_sect_size/1024;
-
-#ifdef MMC_DEBUG
-	printf("mmc_hw_get_parameters: hw_sect_size=%d, hw_nr_sects=%d, "
-		 "hw_size=%d\n", hw_sect_size, hw_nr_sects, hw_size);
-#endif
-
-	return 0;
-}
-
-int mmc_legacy_init(int verbose)
-{
-	int ret = -ENODEV;
-
-	if (verbose)
-		printf("mmc_legacy_init\n");
-
-	spi_init();
-	/* this meeds to be done twice */
-	mmc_hw_init();
-	udelay(1000);
-	mmc_hw_init();
-
-	mmc_hw_get_parameters();
-
-	mmc_dev.if_type = IF_TYPE_MMC;
-	mmc_dev.part_type = PART_TYPE_DOS;
-	mmc_dev.dev = 0;
-	mmc_dev.lun = 0;
-	mmc_dev.type = 0;
-	mmc_dev.blksz = hw_sect_size;
-	mmc_dev.lba = hw_nr_sects;
-	sprintf((char*)mmc_dev.vendor, "Unknown vendor");
-	sprintf((char*)mmc_dev.product, "Unknown product");
-	sprintf((char*)mmc_dev.revision, "N/A");
-	mmc_dev.removable = 0;	/* should be true??? */
-	mmc_dev.block_read = mmc_block_read;
-
-	fat_register_device(&mmc_dev, 1);
-
-	ret = 0;
-
-	return ret;
-}
-
-#endif /* CONFIG_MMC */
diff --git a/arch/arm/cpu/arm720t/lpc2292/mmc_hw.c b/arch/arm/cpu/arm720t/lpc2292/mmc_hw.c
deleted file mode 100644
index b4dc4a6..0000000
--- a/arch/arm/cpu/arm720t/lpc2292/mmc_hw.c
+++ /dev/null
@@ -1,233 +0,0 @@
-/*
-    This code was original written by Ulrich Radig and modified by
-    Embedded Artists AB (www.embeddedartists.com).
-
-    This program is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 2 of the License, or
-    (at your option) any later version.
-
-    This program is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program; if not, write to the Free Software
-    Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
-*/
-
-#include <config.h>
-#include <common.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/spi.h>
-
-#define MMC_Enable() PUT32(IO1CLR, 1l << 22)
-#define MMC_Disable() PUT32(IO1SET, 1l << 22)
-#define mmc_spi_cfg() spi_set_clock(8); spi_set_cfg(0, 1, 0);
-
-static unsigned char Write_Command_MMC (unsigned char *CMD);
-static void MMC_Read_Block(unsigned char *CMD, unsigned char *Buffer,
-		    unsigned short int Bytes);
-
-/* initialize the hardware */
-int mmc_hw_init(void)
-{
-	unsigned long a;
-	unsigned short int Timeout = 0;
-	unsigned char b;
-	unsigned char CMD[] = {0x40, 0x00, 0x00, 0x00, 0x00, 0x95};
-
-	/* set-up GPIO and SPI */
-	(*((volatile unsigned long *)PINSEL2)) &= ~(1l << 3); /* clear bit 3 */
-	(*((volatile unsigned long *)IO1DIR)) |= (1l << 22); /* set bit 22 (output) */
-
-	MMC_Disable();
-
-	spi_lock();
-	spi_set_clock(248);
-	spi_set_cfg(0, 1, 0);
-	MMC_Enable();
-
-	/* waste some time */
-	for(a=0; a < 20000; a++)
-		asm("nop");
-
-	/* Put the MMC/SD-card into SPI-mode */
-	for (b = 0; b < 10; b++) /* Sends min 74+ clocks to the MMC/SD-card */
-		spi_write(0xff);
-
-	/* Sends command CMD0 to MMC/SD-card */
-	while (Write_Command_MMC(CMD) != 1) {
-		if (Timeout++ > 200) {
-			MMC_Disable();
-			spi_unlock();
-			return(1); /* Abort with command 1 (return 1) */
-		}
-	}
-	/* Sends Command CMD1 an MMC/SD-card */
-	Timeout = 0;
-	CMD[0] = 0x41;/* Command 1 */
-	CMD[5] = 0xFF;
-
-	while (Write_Command_MMC(CMD) != 0) {
-		if (Timeout++ > 200) {
-			MMC_Disable();
-			spi_unlock();
-			return (2); /* Abort with command 2 (return 2) */
-		}
-	}
-
-	MMC_Disable();
-	spi_unlock();
-
-	return 0;
-}
-
-/* ############################################################################
-   Sends a command to the MMC/SD-card
-   ######################################################################### */
-static unsigned char Write_Command_MMC (unsigned char *CMD)
-{
-	unsigned char a, tmp = 0xff;
-	unsigned short int Timeout = 0;
-
-	MMC_Disable();
-	spi_write(0xFF);
-	MMC_Enable();
-
-	for (a = 0; a < 0x06; a++)
-		spi_write(*CMD++);
-
-	while (tmp == 0xff) {
-		tmp = spi_read();
-		if (Timeout++ > 5000)
-		  break;
-	}
-
-	return (tmp);
-}
-
-/* ############################################################################
-   Routine to read the CID register from the MMC/SD-card (16 bytes)
-   ######################################################################### */
-void MMC_Read_Block(unsigned char *CMD, unsigned char *Buffer, unsigned short
-	int Bytes)
-{
-	unsigned short int a;
-
-	spi_lock();
-	mmc_spi_cfg();
-	MMC_Enable();
-
-	if (Write_Command_MMC(CMD) != 0) {
-		MMC_Disable();
-		spi_unlock();
-		return;
-	}
-
-	while (spi_read() != 0xfe) {};
-	for (a = 0; a < Bytes; a++)
-		*Buffer++ = spi_read();
-
-	/* Read the CRC-byte */
-	spi_read(); /* CRC - byte is discarded */
-	spi_read(); /* CRC - byte is discarded */
-	/* set MMC_Chip_Select to high (MMC/SD-card Inaktiv) */
-	MMC_Disable();
-	spi_unlock();
-
-	return;
-}
-
-/* ############################################################################
-   Routine to read a block (512 bytes) from the MMC/SD-card
-   ######################################################################### */
-unsigned char mmc_read_sector (unsigned long addr,unsigned char *Buffer)
-{
-	/* Command 16 to read aBlocks from the MMC/SD - caed */
-	unsigned char CMD[] = {0x51,0x00,0x00,0x00,0x00,0xFF};
-
-	/* The addres on the MMC/SD-card is in bytes,
-	addr is transformed from blocks to bytes and the result is
-	placed into the command */
-
-	addr = addr << 9; /* addr = addr * 512 */
-
-	CMD[1] = ((addr & 0xFF000000) >> 24);
-	CMD[2] = ((addr & 0x00FF0000) >> 16);
-	CMD[3] = ((addr & 0x0000FF00) >> 8 );
-
-	MMC_Read_Block(CMD, Buffer, 512);
-
-	return (0);
-}
-
-/* ############################################################################
-   Routine to write a block (512 byte) to the MMC/SD-card
-   ######################################################################### */
-unsigned char mmc_write_sector (unsigned long addr,unsigned char *Buffer)
-{
-	unsigned char tmp, a;
-	unsigned short int b;
-	/* Command 24 to write a block to the MMC/SD - card */
-	unsigned char CMD[] = {0x58, 0x00, 0x00, 0x00, 0x00, 0xFF};
-
-	/* The addres on the MMC/SD-card is in bytes,
-	addr is transformed from blocks to bytes and the result is
-	placed into the command */
-
-	addr = addr << 9; /* addr = addr * 512 */
-
-	CMD[1] = ((addr & 0xFF000000) >> 24);
-	CMD[2] = ((addr & 0x00FF0000) >> 16);
-	CMD[3] = ((addr & 0x0000FF00) >> 8 );
-
-	spi_lock();
-	mmc_spi_cfg();
-	MMC_Enable();
-
-	/* Send command CMD24 to the MMC/SD-card (Write 1 Block/512 Bytes) */
-	tmp = Write_Command_MMC(CMD);
-	if (tmp != 0) {
-		MMC_Disable();
-		spi_unlock();
-		return(tmp);
-	}
-
-	/* Do a short delay and send a clock-pulse to the MMC/SD-card */
-	for (a = 0; a < 100; a++)
-		spi_read();
-
-	/* Send a start byte to the MMC/SD-card */
-	spi_write(0xFE);
-
-	/* Write the block (512 bytes) to the MMC/SD-card */
-	for (b = 0; b < 512; b++)
-		spi_write(*Buffer++);
-
-	/* write the CRC-Byte */
-	spi_write(0xFF); /* write a dummy CRC */
-	spi_write(0xFF); /* CRC code is not used */
-
-	/* Wait for MMC/SD-card busy */
-	while (spi_read() != 0xff) {};
-
-	/* set MMC_Chip_Select to high (MMC/SD-card inactive) */
-	MMC_Disable();
-	spi_unlock();
-	return (0);
-}
-
-/* #########################################################################
-   Routine to read the CSD register from the MMC/SD-card (16 bytes)
-   ######################################################################### */
-unsigned char mmc_read_csd (unsigned char *Buffer)
-{
-	/* Command to read the CSD register */
-	unsigned char CMD[] = {0x49, 0x00, 0x00, 0x00, 0x00, 0xFF};
-
-	MMC_Read_Block(CMD, Buffer, 16);
-
-	return (0);
-}
diff --git a/arch/arm/cpu/arm720t/lpc2292/mmc_hw.h b/arch/arm/cpu/arm720t/lpc2292/mmc_hw.h
deleted file mode 100644
index 3687dbf..0000000
--- a/arch/arm/cpu/arm720t/lpc2292/mmc_hw.h
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
-    This module implements a linux character device driver for the 24c256 chip.
-    Copyright (C) 2006  Embedded Artists AB (www.embeddedartists.com)
-
-    This program is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 2 of the License, or
-    (at your option) any later version.
-
-    This program is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program; if not, write to the Free Software
-    Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
-*/
-
-#ifndef _MMC_HW_
-#define _MMC_HW_
-
-unsigned char mmc_read_csd(unsigned char *Buffer);
-unsigned char mmc_read_sector (unsigned long addr,
-			       unsigned char *Buffer);
-unsigned char mmc_write_sector (unsigned long addr,unsigned char *Buffer);
-int mmc_hw_init(void);
-
-#endif /* _MMC_HW_ */
diff --git a/arch/arm/cpu/arm720t/lpc2292/spi.c b/arch/arm/cpu/arm720t/lpc2292/spi.c
deleted file mode 100644
index d296bda..0000000
--- a/arch/arm/cpu/arm720t/lpc2292/spi.c
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
-    This module implements an interface to the SPI on the lpc22xx.
-    Copyright (C) 2006  Embedded Artists AB (www.embeddedartists.com)
-
-    This program is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 2 of the License, or
-    (at your option) any later version.
-
-    This program is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program; if not, write to the Free Software
-    Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
-*/
-
-#include <config.h>
-#include <common.h>
-#include <asm/errno.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/spi.h>
-
-unsigned long spi_flags;
-unsigned char spi_idle = 0x00;
-
-int spi_init(void)
-{
-	unsigned long pinsel0_value;
-
-	/* activate spi pins */
-	pinsel0_value = GET32(PINSEL0);
-	pinsel0_value &= ~(0xFFl << 8);
-	pinsel0_value |= (0x55l << 8);
-	PUT32(PINSEL0, pinsel0_value);
-
-	return 0;
-}
diff --git a/arch/arm/cpu/arm720t/s3c4510b/Makefile b/arch/arm/cpu/arm720t/s3c4510b/Makefile
deleted file mode 100644
index 5c6df08..0000000
--- a/arch/arm/cpu/arm720t/s3c4510b/Makefile
+++ /dev/null
@@ -1,45 +0,0 @@
-#
-# (C) Copyright 2000-2008
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(SOC).o
-
-COBJS-y	+= cache.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS-y))
-
-all:	$(obj).depend $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/arch/arm/cpu/arm720t/s3c4510b/cache.c b/arch/arm/cpu/arm720t/s3c4510b/cache.c
deleted file mode 100644
index 104d287..0000000
--- a/arch/arm/cpu/arm720t/s3c4510b/cache.c
+++ /dev/null
@@ -1,86 +0,0 @@
-/*
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Alex Zuepke <azu@sysgo.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/hardware.h>
-
-void icache_enable (void)
-{
-	s32 i;
-
-	/* disable all cache bits */
-	CLR_REG( REG_SYSCFG, 0x3F);
-
-	/* 8KB cache, write enable */
-	SET_REG( REG_SYSCFG, CACHE_WRITE_BUFF | CACHE_MODE_01);
-
-	/* clear TAG RAM bits */
-	for ( i = 0; i < 256; i++)
-	  PUT_REG( CACHE_TAG_RAM + 4*i, 0x00000000);
-
-	/* clear SET0 RAM */
-	for(i=0; i < 1024; i++)
-	  PUT_REG( CACHE_SET0_RAM + 4*i, 0x00000000);
-
-	/* clear SET1 RAM */
-	for(i=0; i < 1024; i++)
-	  PUT_REG( CACHE_SET1_RAM + 4*i, 0x00000000);
-
-	/* enable cache */
-	SET_REG( REG_SYSCFG, CACHE_ENABLE);
-
-}
-
-void icache_disable (void)
-{
-	/* disable all cache bits */
-	CLR_REG( REG_SYSCFG, 0x3F);
-}
-
-int icache_status (void)
-{
-	return GET_REG( REG_SYSCFG) & CACHE_ENABLE;
-}
-
-void dcache_enable (void)
-{
-	/* we don't have seperate instruction/data caches */
-	icache_enable();
-}
-
-void dcache_disable (void)
-{
-	/* we don't have seperate instruction/data caches */
-	icache_disable();
-}
-
-int dcache_status (void)
-{
-	/* we don't have seperate instruction/data caches */
-	return icache_status();
-}
diff --git a/arch/arm/cpu/arm720t/start.S b/arch/arm/cpu/arm720t/start.S
deleted file mode 100644
index c098118..0000000
--- a/arch/arm/cpu/arm720t/start.S
+++ /dev/null
@@ -1,677 +0,0 @@
-/*
- *  armboot - Startup Code for ARM720 CPU-core
- *
- *  Copyright (c) 2001	Marius Gröger <mag@sysgo.de>
- *  Copyright (c) 2002	Alex Züpke <azu@sysgo.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <asm-offsets.h>
-#include <config.h>
-#include <version.h>
-#include <asm/hardware.h>
-
-/*
- *************************************************************************
- *
- * Jump vector table as in table 3.1 in [1]
- *
- *************************************************************************
- */
-
-
-.globl _start
-_start: b	reset
-	ldr	pc, _undefined_instruction
-	ldr	pc, _software_interrupt
-	ldr	pc, _prefetch_abort
-	ldr	pc, _data_abort
-#ifdef CONFIG_LPC2292
-	.word	0xB4405F76 /* 2's complement of the checksum of the vectors */
-#else
-	ldr	pc, _not_used
-#endif
-	ldr	pc, _irq
-	ldr	pc, _fiq
-
-_undefined_instruction: .word undefined_instruction
-_software_interrupt:	.word software_interrupt
-_prefetch_abort:	.word prefetch_abort
-_data_abort:		.word data_abort
-_not_used:		.word not_used
-_irq:			.word irq
-_fiq:			.word fiq
-
-	.balignl 16,0xdeadbeef
-
-
-/*
- *************************************************************************
- *
- * Startup Code (reset vector)
- *
- * do important init only if we don't start from RAM!
- * relocate armboot to ram
- * setup stack
- * jump to second stage
- *
- *************************************************************************
- */
-
-.globl _TEXT_BASE
-_TEXT_BASE:
-	.word	CONFIG_SYS_TEXT_BASE
-
-/*
- * These are defined in the board-specific linker script.
- * Subtracting _start from them lets the linker put their
- * relative position in the executable instead of leaving
- * them null.
- */
-.globl _bss_start_ofs
-_bss_start_ofs:
-	.word __bss_start - _start
-
-.globl _bss_end_ofs
-_bss_end_ofs:
-	.word _end - _start
-
-#ifdef CONFIG_USE_IRQ
-/* IRQ stack memory (calculated at run-time) */
-.globl IRQ_STACK_START
-IRQ_STACK_START:
-	.word	0x0badc0de
-
-/* IRQ stack memory (calculated at run-time) */
-.globl FIQ_STACK_START
-FIQ_STACK_START:
-	.word 0x0badc0de
-#endif
-
-/* IRQ stack memory (calculated at run-time) + 8 bytes */
-.globl IRQ_STACK_START_IN
-IRQ_STACK_START_IN:
-	.word	0x0badc0de
-
-/*
- * the actual reset code
- */
-
-reset:
-	/*
-	 * set the cpu to SVC32 mode
-	 */
-	mrs	r0,cpsr
-	bic	r0,r0,#0x1f
-	orr	r0,r0,#0xd3
-	msr	cpsr,r0
-
-	/*
-	 * we do sys-critical inits only at reboot,
-	 * not when booting from ram!
-	 */
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
-	bl	cpu_init_crit
-#endif
-
-#ifdef CONFIG_LPC2292
-	bl	lowlevel_init
-#endif
-
-/* Set stackpointer in internal RAM to call board_init_f */
-call_board_init_f:
-	ldr	sp, =(CONFIG_SYS_INIT_SP_ADDR)
-	bic	sp, sp, #7 /* 8-byte alignment for ABI compliance */
-	ldr	r0,=0x00000000
-	bl	board_init_f
-
-/*------------------------------------------------------------------------------*/
-
-/*
- * void relocate_code (addr_sp, gd, addr_moni)
- *
- * This "function" does not return, instead it continues in RAM
- * after relocating the monitor code.
- *
- */
-	.globl	relocate_code
-relocate_code:
-	mov	r4, r0	/* save addr_sp */
-	mov	r5, r1	/* save addr of gd */
-	mov	r6, r2	/* save addr of destination */
-
-	/* Set up the stack						    */
-stack_setup:
-	mov	sp, r4
-
-	adr	r0, _start
-	cmp	r0, r6
-	beq	clear_bss		/* skip relocation */
-	mov	r1, r6			/* r1 <- scratch for copy_loop */
-	ldr	r3, _bss_start_ofs
-	add	r2, r0, r3		/* r2 <- source end address	    */
-
-copy_loop:
-	ldmia	r0!, {r9-r10}		/* copy from source address [r0]    */
-	stmia	r1!, {r9-r10}		/* copy to   target address [r1]    */
-	cmp	r0, r2			/* until source end address [r2]    */
-	blo	copy_loop
-
-#ifndef CONFIG_PRELOADER
-	/*
-	 * fix .rel.dyn relocations
-	 */
-	ldr	r0, _TEXT_BASE		/* r0 <- Text base */
-	sub	r9, r6, r0		/* r9 <- relocation offset */
-	ldr	r10, _dynsym_start_ofs	/* r10 <- sym table ofs */
-	add	r10, r10, r0		/* r10 <- sym table in FLASH */
-	ldr	r2, _rel_dyn_start_ofs	/* r2 <- rel dyn start ofs */
-	add	r2, r2, r0		/* r2 <- rel dyn start in FLASH */
-	ldr	r3, _rel_dyn_end_ofs	/* r3 <- rel dyn end ofs */
-	add	r3, r3, r0		/* r3 <- rel dyn end in FLASH */
-fixloop:
-	ldr	r0, [r2]		/* r0 <- location to fix up, IN FLASH! */
-	add	r0, r0, r9		/* r0 <- location to fix up in RAM */
-	ldr	r1, [r2, #4]
-	and	r7, r1, #0xff
-	cmp	r7, #23			/* relative fixup? */
-	beq	fixrel
-	cmp	r7, #2			/* absolute fixup? */
-	beq	fixabs
-	/* ignore unknown type of fixup */
-	b	fixnext
-fixabs:
-	/* absolute fix: set location to (offset) symbol value */
-	mov	r1, r1, LSR #4		/* r1 <- symbol index in .dynsym */
-	add	r1, r10, r1		/* r1 <- address of symbol in table */
-	ldr	r1, [r1, #4]		/* r1 <- symbol value */
-	add	r1, r1, r9		/* r1 <- relocated sym addr */
-	b	fixnext
-fixrel:
-	/* relative fix: increase location by offset */
-	ldr	r1, [r0]
-	add	r1, r1, r9
-fixnext:
-	str	r1, [r0]
-	add	r2, r2, #8		/* each rel.dyn entry is 8 bytes */
-	cmp	r2, r3
-	blo	fixloop
-#endif
-
-clear_bss:
-#ifndef CONFIG_PRELOADER
-	ldr	r0, _bss_start_ofs
-	ldr	r1, _bss_end_ofs
-	mov	r4, r6			/* reloc addr */
-	add	r0, r0, r4
-	add	r1, r1, r4
-	mov	r2, #0x00000000		/* clear			    */
-
-clbss_l:str	r2, [r0]		/* clear loop...		    */
-	add	r0, r0, #4
-	cmp	r0, r1
-	bne	clbss_l
-
-	bl coloured_LED_init
-	bl red_LED_on
-#endif
-
-/*
- * We are done. Do not return, instead branch to second part of board
- * initialization, now running from RAM.
- */
-	ldr	r0, _board_init_r_ofs
-	adr	r1, _start
-	add	lr, r0, r1
-	add	lr, lr, r9
-	/* setup parameters for board_init_r */
-	mov	r0, r5		/* gd_t */
-	mov	r1, r6		/* dest_addr */
-	/* jump to it ... */
-	mov	pc, lr
-
-_board_init_r_ofs:
-	.word board_init_r - _start
-
-_rel_dyn_start_ofs:
-	.word __rel_dyn_start - _start
-_rel_dyn_end_ofs:
-	.word __rel_dyn_end - _start
-_dynsym_start_ofs:
-	.word __dynsym_start - _start
-
-/*
- *************************************************************************
- *
- * CPU_init_critical registers
- *
- * setup important registers
- * setup memory timing
- *
- *************************************************************************
- */
-
-#if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_ARMADILLO)
-
-/* Interupt-Controller base addresses */
-INTMR1:		.word	0x80000280 @ 32 bit size
-INTMR2:		.word	0x80001280 @ 16 bit size
-INTMR3:		.word	0x80002280 @  8 bit size
-
-/* SYSCONs */
-SYSCON1:	.word	0x80000100
-SYSCON2:	.word	0x80001100
-SYSCON3:	.word	0x80002200
-
-#define CLKCTL	       0x6  /* mask */
-#define CLKCTL_18      0x0  /* 18.432 MHz */
-#define CLKCTL_36      0x2  /* 36.864 MHz */
-#define CLKCTL_49      0x4  /* 49.152 MHz */
-#define CLKCTL_73      0x6  /* 73.728 MHz */
-
-#elif defined(CONFIG_LPC2292)
-PLLCFG_ADR:	.word	PLLCFG
-PLLFEED_ADR:	.word	PLLFEED
-PLLCON_ADR:	.word	PLLCON
-PLLSTAT_ADR:	.word	PLLSTAT
-VPBDIV_ADR:	.word	VPBDIV
-MEMMAP_ADR:	.word	MEMMAP
-
-#endif
-
-cpu_init_crit:
-#if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_ARMADILLO)
-
-	/*
-	 * mask all IRQs by clearing all bits in the INTMRs
-	 */
-	mov	r1, #0x00
-	ldr	r0, INTMR1
-	str	r1, [r0]
-	ldr	r0, INTMR2
-	str	r1, [r0]
-	ldr	r0, INTMR3
-	str	r1, [r0]
-
-	/*
-	 * flush v4 I/D caches
-	 */
-	mov	r0, #0
-	mcr	p15, 0, r0, c7, c7, 0	/* flush v3/v4 cache */
-	mcr	p15, 0, r0, c8, c7, 0	/* flush v4 TLB */
-
-	/*
-	 * disable MMU stuff and caches
-	 */
-	mrc	p15,0,r0,c1,c0
-	bic	r0, r0, #0x00002300	@ clear bits 13, 9:8 (--V- --RS)
-	bic	r0, r0, #0x0000008f	@ clear bits 7, 3:0 (B--- WCAM)
-	orr	r0, r0, #0x00000002	@ set bit 2 (A) Align
-	mcr	p15,0,r0,c1,c0
-#elif defined(CONFIG_NETARM)
-	/*
-	 * prior to software reset : need to set pin PORTC4 to be *HRESET
-	 */
-	ldr	r0, =NETARM_GEN_MODULE_BASE
-	ldr	r1, =(NETARM_GEN_PORT_MODE(0x10) | \
-			NETARM_GEN_PORT_DIR(0x10))
-	str	r1, [r0, #+NETARM_GEN_PORTC]
-	/*
-	 * software reset : see HW Ref. Guide 8.2.4 : Software Service register
-	 *		    for an explanation of this process
-	 */
-	ldr	r0, =NETARM_GEN_MODULE_BASE
-	ldr	r1, =NETARM_GEN_SW_SVC_RESETA
-	str	r1, [r0, #+NETARM_GEN_SOFTWARE_SERVICE]
-	ldr	r1, =NETARM_GEN_SW_SVC_RESETB
-	str	r1, [r0, #+NETARM_GEN_SOFTWARE_SERVICE]
-	ldr	r1, =NETARM_GEN_SW_SVC_RESETA
-	str	r1, [r0, #+NETARM_GEN_SOFTWARE_SERVICE]
-	ldr	r1, =NETARM_GEN_SW_SVC_RESETB
-	str	r1, [r0, #+NETARM_GEN_SOFTWARE_SERVICE]
-	/*
-	 * setup PLL and System Config
-	 */
-	ldr	r0, =NETARM_GEN_MODULE_BASE
-
-	ldr	r1, =(	NETARM_GEN_SYS_CFG_LENDIAN | \
-			NETARM_GEN_SYS_CFG_BUSFULL | \
-			NETARM_GEN_SYS_CFG_USER_EN | \
-			NETARM_GEN_SYS_CFG_ALIGN_ABORT | \
-			NETARM_GEN_SYS_CFG_BUSARB_INT | \
-			NETARM_GEN_SYS_CFG_BUSMON_EN )
-
-	str	r1, [r0, #+NETARM_GEN_SYSTEM_CONTROL]
-
-#ifndef CONFIG_NETARM_PLL_BYPASS
-	ldr	r1, =(	NETARM_GEN_PLL_CTL_PLLCNT(NETARM_PLL_COUNT_VAL) | \
-			NETARM_GEN_PLL_CTL_POLTST_DEF | \
-			NETARM_GEN_PLL_CTL_INDIV(1) | \
-			NETARM_GEN_PLL_CTL_ICP_DEF | \
-			NETARM_GEN_PLL_CTL_OUTDIV(2) )
-	str	r1, [r0, #+NETARM_GEN_PLL_CONTROL]
-#endif
-
-	/*
-	 * mask all IRQs by clearing all bits in the INTMRs
-	 */
-	mov	r1, #0
-	ldr	r0, =NETARM_GEN_MODULE_BASE
-	str	r1, [r0, #+NETARM_GEN_INTR_ENABLE]
-
-#elif defined(CONFIG_S3C4510B)
-
-	/*
-	 * Mask off all IRQ sources
-	 */
-	ldr	r1, =REG_INTMASK
-	ldr	r0, =0x3FFFFF
-	str	r0, [r1]
-
-	/*
-	 * Disable Cache
-	 */
-	ldr r0, =REG_SYSCFG
-	ldr r1, =0x83ffffa0	/* cache-disabled  */
-	str r1, [r0]
-
-#elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
-	/* No specific initialisation for IntegratorAP/CM720T as yet */
-#elif defined(CONFIG_LPC2292)
-	/* Set-up PLL */
-	mov	r3, #0xAA
-	mov	r4, #0x55
-	/* First disconnect and disable the PLL */
-	ldr	r0, PLLCON_ADR
-	mov	r1, #0x00
-	str	r1, [r0]
-	ldr	r0, PLLFEED_ADR /* start feed sequence */
-	str	r3, [r0]
-	str	r4, [r0]	/* feed sequence done */
-	/* Set new M and P values */
-	ldr	r0, PLLCFG_ADR
-	mov	r1, #0x23	/* M=4 and P=2 */
-	str	r1, [r0]
-	ldr	r0, PLLFEED_ADR /* start feed sequence */
-	str	r3, [r0]
-	str	r4, [r0]	/* feed sequence done */
-	/* Then enable the PLL */
-	ldr	r0, PLLCON_ADR
-	mov	r1, #0x01	/* PLL enable bit */
-	str	r1, [r0]
-	ldr	r0, PLLFEED_ADR /* start feed sequence */
-	str	r3, [r0]
-	str	r4, [r0]	/* feed sequence done */
-	/* Wait for the lock */
-	ldr	r0, PLLSTAT_ADR
-	mov	r1, #0x400	/* lock bit */
-lock_loop:
-	ldr	r2, [r0]
-	and	r2, r1, r2
-	cmp	r2, #0
-	beq	lock_loop
-	/* And finally connect the PLL */
-	ldr	r0, PLLCON_ADR
-	mov	r1, #0x03	/* PLL enable bit and connect bit */
-	str	r1, [r0]
-	ldr	r0, PLLFEED_ADR /* start feed sequence */
-	str	r3, [r0]
-	str	r4, [r0]	/* feed sequence done */
-	/* Set-up VPBDIV register */
-	ldr	r0, VPBDIV_ADR
-	mov	r1, #0x01	/* VPB clock is same as process clock */
-	str	r1, [r0]
-#else
-#error No cpu_init_crit() defined for current CPU type
-#endif
-
-#ifdef CONFIG_ARM7_REVD
-	/* set clock speed */
-	/* !!! we run @ 36 MHz due to a hardware flaw in Rev. D processors */
-	/* !!! not doing DRAM refresh properly! */
-	ldr	r0, SYSCON3
-	ldr	r1, [r0]
-	bic	r1, r1, #CLKCTL
-	orr	r1, r1, #CLKCTL_36
-	str	r1, [r0]
-#endif
-
-#ifndef CONFIG_LPC2292
-	mov	ip, lr
-	/*
-	 * before relocating, we have to setup RAM timing
-	 * because memory timing is board-dependent, you will
-	 * find a lowlevel_init.S in your board directory.
-	 */
-	bl	lowlevel_init
-	mov	lr, ip
-#endif
-
-	mov	pc, lr
-
-
-/*
- *************************************************************************
- *
- * Interrupt handling
- *
- *************************************************************************
- */
-
-@
-@ IRQ stack frame.
-@
-#define S_FRAME_SIZE	72
-
-#define S_OLD_R0	68
-#define S_PSR		64
-#define S_PC		60
-#define S_LR		56
-#define S_SP		52
-
-#define S_IP		48
-#define S_FP		44
-#define S_R10		40
-#define S_R9		36
-#define S_R8		32
-#define S_R7		28
-#define S_R6		24
-#define S_R5		20
-#define S_R4		16
-#define S_R3		12
-#define S_R2		8
-#define S_R1		4
-#define S_R0		0
-
-#define MODE_SVC 0x13
-#define I_BIT	 0x80
-
-/*
- * use bad_save_user_regs for abort/prefetch/undef/swi ...
- * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
- */
-
-	.macro	bad_save_user_regs
-	sub	sp, sp, #S_FRAME_SIZE
-	stmia	sp, {r0 - r12}			@ Calling r0-r12
-	add	r8, sp, #S_PC
-
-	ldr	r2, IRQ_STACK_START_IN
-	ldmia	r2, {r2 - r4}			@ get pc, cpsr, old_r0
-	add	r0, sp, #S_FRAME_SIZE		@ restore sp_SVC
-
-	add	r5, sp, #S_SP
-	mov	r1, lr
-	stmia	r5, {r0 - r4}			@ save sp_SVC, lr_SVC, pc, cpsr, old_r
-	mov	r0, sp
-	.endm
-
-	.macro	irq_save_user_regs
-	sub	sp, sp, #S_FRAME_SIZE
-	stmia	sp, {r0 - r12}			@ Calling r0-r12
-	add	r8, sp, #S_PC
-	stmdb	r8, {sp, lr}^			@ Calling SP, LR
-	str	lr, [r8, #0]			@ Save calling PC
-	mrs	r6, spsr
-	str	r6, [r8, #4]			@ Save CPSR
-	str	r0, [r8, #8]			@ Save OLD_R0
-	mov	r0, sp
-	.endm
-
-	.macro	irq_restore_user_regs
-	ldmia	sp, {r0 - lr}^			@ Calling r0 - lr
-	mov	r0, r0
-	ldr	lr, [sp, #S_PC]			@ Get PC
-	add	sp, sp, #S_FRAME_SIZE
-	subs	pc, lr, #4			@ return & move spsr_svc into cpsr
-	.endm
-
-	.macro get_bad_stack
-	ldr	r13, IRQ_STACK_START_IN		@ setup our mode stack
-
-	str	lr, [r13]			@ save caller lr / spsr
-	mrs	lr, spsr
-	str	lr, [r13, #4]
-
-	mov	r13, #MODE_SVC			@ prepare SVC-Mode
-	msr	spsr_c, r13
-	mov	lr, pc
-	movs	pc, lr
-	.endm
-
-	.macro get_irq_stack			@ setup IRQ stack
-	ldr	sp, IRQ_STACK_START
-	.endm
-
-	.macro get_fiq_stack			@ setup FIQ stack
-	ldr	sp, FIQ_STACK_START
-	.endm
-
-/*
- * exception handlers
- */
-	.align	5
-undefined_instruction:
-	get_bad_stack
-	bad_save_user_regs
-	bl	do_undefined_instruction
-
-	.align	5
-software_interrupt:
-	get_bad_stack
-	bad_save_user_regs
-	bl	do_software_interrupt
-
-	.align	5
-prefetch_abort:
-	get_bad_stack
-	bad_save_user_regs
-	bl	do_prefetch_abort
-
-	.align	5
-data_abort:
-	get_bad_stack
-	bad_save_user_regs
-	bl	do_data_abort
-
-	.align	5
-not_used:
-	get_bad_stack
-	bad_save_user_regs
-	bl	do_not_used
-
-#ifdef CONFIG_USE_IRQ
-
-	.align	5
-irq:
-	get_irq_stack
-	irq_save_user_regs
-	bl	do_irq
-	irq_restore_user_regs
-
-	.align	5
-fiq:
-	get_fiq_stack
-	/* someone ought to write a more effiction fiq_save_user_regs */
-	irq_save_user_regs
-	bl	do_fiq
-	irq_restore_user_regs
-
-#else
-
-	.align	5
-irq:
-	get_bad_stack
-	bad_save_user_regs
-	bl	do_irq
-
-	.align	5
-fiq:
-	get_bad_stack
-	bad_save_user_regs
-	bl	do_fiq
-
-#endif
-
-#if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_ARMADILLO)
-	.align	5
-.globl reset_cpu
-reset_cpu:
-	mov	ip, #0
-	mcr	p15, 0, ip, c7, c7, 0		@ invalidate cache
-	mcr	p15, 0, ip, c8, c7, 0		@ flush TLB (v4)
-	mrc	p15, 0, ip, c1, c0, 0		@ get ctrl register
-	bic	ip, ip, #0x000f			@ ............wcam
-	bic	ip, ip, #0x2100			@ ..v....s........
-	mcr	p15, 0, ip, c1, c0, 0		@ ctrl register
-	mov	pc, r0
-#elif defined(CONFIG_NETARM)
-	.align	5
-.globl reset_cpu
-reset_cpu:
-	ldr	r1, =NETARM_MEM_MODULE_BASE
-	ldr	r0, [r1, #+NETARM_MEM_CS0_BASE_ADDR]
-	ldr	r1, =0xFFFFF000
-	and	r0, r1, r0
-	ldr	r1, =(relocate-CONFIG_SYS_TEXT_BASE)
-	add	r0, r1, r0
-	ldr	r4, =NETARM_GEN_MODULE_BASE
-	ldr	r1, =NETARM_GEN_SW_SVC_RESETA
-	str	r1, [r4, #+NETARM_GEN_SOFTWARE_SERVICE]
-	ldr	r1, =NETARM_GEN_SW_SVC_RESETB
-	str	r1, [r4, #+NETARM_GEN_SOFTWARE_SERVICE]
-	ldr	r1, =NETARM_GEN_SW_SVC_RESETA
-	str	r1, [r4, #+NETARM_GEN_SOFTWARE_SERVICE]
-	ldr	r1, =NETARM_GEN_SW_SVC_RESETB
-	str	r1, [r4, #+NETARM_GEN_SOFTWARE_SERVICE]
-	mov	pc, r0
-#elif defined(CONFIG_S3C4510B)
-/* Nothing done here as reseting the CPU is board specific, depending
- * on external peripherals such as watchdog timers, etc. */
-#elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
-	/* No specific reset actions for IntegratorAP/CM720T as yet */
-#elif defined(CONFIG_LPC2292)
-	.align	5
-.globl reset_cpu
-reset_cpu:
-	mov	pc, r0
-#else
-#error No reset_cpu() defined for current CPU type
-#endif
diff --git a/arch/arm/cpu/arm720t/u-boot.lds b/arch/arm/cpu/arm720t/u-boot.lds
deleted file mode 100644
index 0686e42..0000000
--- a/arch/arm/cpu/arm720t/u-boot.lds
+++ /dev/null
@@ -1,77 +0,0 @@
-/*
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-ENTRY(_start)
-SECTIONS
-{
-	. = 0x00000000;
-
-	. = ALIGN(4);
-	.text :
-	{
-		arch/arm/cpu/arm720t/start.o	(.text)
-		*(.text)
-	}
-
-	. = ALIGN(4);
-	.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
-
-	. = ALIGN(4);
-	.data : {
-	}
-
-	. = ALIGN(4);
-
-	. = .;
-	__u_boot_cmd_start = .;
-	.u_boot_cmd : { *(.u_boot_cmd) }
-	__u_boot_cmd_end = .;
-
-	. = ALIGN(4);
-
-	.rel.dyn : {
-		__rel_dyn_start = .;
-		*(.rel*)
-		__rel_dyn_end = .;
-	}
-
-	.dynsym : {
-		__dynsym_start = .;
-		*(.dynsym)
-	}
-
-	.bss __rel_dyn_start (OVERLAY) : {
-		__bss_start = .;
-		*(.bss)
-		 . = ALIGN(4);
-		_end = .;
-	}
-
-	/DISCARD/ : { *(.dynstr*) }
-	/DISCARD/ : { *(.dynamic*) }
-	/DISCARD/ : { *(.plt*) }
-	/DISCARD/ : { *(.interp*) }
-	/DISCARD/ : { *(.gnu*) }
-}
diff --git a/arch/arm/cpu/arm920t/Makefile b/arch/arm/cpu/arm920t/Makefile
deleted file mode 100644
index dcc7782..0000000
--- a/arch/arm/cpu/arm920t/Makefile
+++ /dev/null
@@ -1,49 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(CPU).o
-
-START	= start.o
-
-COBJS-y	+= cpu.o
-COBJS-$(CONFIG_USE_IRQ)	+= interrupts.o
-
-SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS-y) $(SOBJS))
-START	:= $(addprefix $(obj),$(START))
-
-all:	$(obj).depend $(START) $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/arch/arm/cpu/arm920t/a320/Makefile b/arch/arm/cpu/arm920t/a320/Makefile
deleted file mode 100644
index 31da706..0000000
--- a/arch/arm/cpu/arm920t/a320/Makefile
+++ /dev/null
@@ -1,47 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(SOC).o
-
-SOBJS	+= reset.o
-COBJS	+= timer.o
-COBJS	+= ftsmc020.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
-
-all:	$(obj).depend $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/arch/arm/cpu/arm920t/a320/ftsmc020.c b/arch/arm/cpu/arm920t/a320/ftsmc020.c
deleted file mode 100644
index 7646537..0000000
--- a/arch/arm/cpu/arm920t/a320/ftsmc020.c
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * (C) Copyright 2009 Faraday Technology
- * Po-Yu Chuang <ratbert@faraday-tech.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#include <config.h>
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/ftsmc020.h>
-
-struct ftsmc020_config {
-	unsigned int	config;
-	unsigned int	timing;
-};
-
-static struct ftsmc020_config config[] = CONFIG_SYS_FTSMC020_CONFIGS;
-
-static struct ftsmc020 *smc = (struct ftsmc020 *)CONFIG_FTSMC020_BASE;
-
-static void ftsmc020_setup_bank(unsigned int bank, struct ftsmc020_config *cfg)
-{
-	if (bank > 3) {
-		printf("bank # %u invalid\n", bank);
-		return;
-	}
-
-	writel(cfg->config, &smc->bank[bank].cr);
-	writel(cfg->timing, &smc->bank[bank].tpr);
-}
-
-void ftsmc020_init(void)
-{
-	int i;
-
-	for (i = 0; i < ARRAY_SIZE(config); i++)
-		ftsmc020_setup_bank(i, &config[i]);
-}
diff --git a/arch/arm/cpu/arm920t/a320/reset.S b/arch/arm/cpu/arm920t/a320/reset.S
deleted file mode 100644
index 12ca527..0000000
--- a/arch/arm/cpu/arm920t/a320/reset.S
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * (C) Copyright 2009 Faraday Technology
- * Po-Yu Chuang <ratbert@faraday-tech.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-.global reset_cpu
-reset_cpu:
-	b	reset_cpu
diff --git a/arch/arm/cpu/arm920t/a320/timer.c b/arch/arm/cpu/arm920t/a320/timer.c
deleted file mode 100644
index d2e316f..0000000
--- a/arch/arm/cpu/arm920t/a320/timer.c
+++ /dev/null
@@ -1,193 +0,0 @@
-/*
- * (C) Copyright 2009 Faraday Technology
- * Po-Yu Chuang <ratbert@faraday-tech.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/ftpmu010.h>
-#include <asm/arch/fttmr010.h>
-
-static ulong timestamp;
-static ulong lastdec;
-
-static struct fttmr010 *tmr = (struct fttmr010 *)CONFIG_FTTMR010_BASE;
-static struct ftpmu010 *pmu = (struct ftpmu010 *)CONFIG_FTPMU010_BASE;
-
-#define TIMER_CLOCK	32768
-#define TIMER_LOAD_VAL	0xffffffff
-
-int timer_init(void)
-{
-	unsigned int oscc;
-	unsigned int cr;
-
-	debug("%s()\n", __func__);
-
-	/* disable timers */
-	writel(0, &tmr->cr);
-
-	/*
-	 * use 32768Hz oscillator for RTC, WDT, TIMER
-	 */
-
-	/* enable the 32768Hz oscillator */
-	oscc = readl(&pmu->OSCC);
-	oscc &= ~(FTPMU010_OSCC_OSCL_OFF | FTPMU010_OSCC_OSCL_TRI);
-	writel(oscc, &pmu->OSCC);
-
-	/* wait until ready */
-	while (!(readl(&pmu->OSCC) & FTPMU010_OSCC_OSCL_STABLE))
-		;
-
-	/* select 32768Hz oscillator */
-	oscc = readl(&pmu->OSCC);
-	oscc |= FTPMU010_OSCC_OSCL_RTCLSEL;
-	writel(oscc, &pmu->OSCC);
-
-	/* setup timer */
-	writel(TIMER_LOAD_VAL, &tmr->timer3_load);
-	writel(TIMER_LOAD_VAL, &tmr->timer3_counter);
-	writel(0, &tmr->timer3_match1);
-	writel(0, &tmr->timer3_match2);
-
-	/* we don't want timer to issue interrupts */
-	writel(FTTMR010_TM3_MATCH1 |
-	       FTTMR010_TM3_MATCH2 |
-	       FTTMR010_TM3_OVERFLOW,
-	       &tmr->interrupt_mask);
-
-	cr = readl(&tmr->cr);
-	cr |= FTTMR010_TM3_CLOCK;	/* use external clock */
-	cr |= FTTMR010_TM3_ENABLE;
-	writel(cr, &tmr->cr);
-
-	/* init the timestamp and lastdec value */
-	reset_timer_masked();
-
-	return 0;
-}
-
-/*
- * timer without interrupts
- */
-
-/*
- * reset time
- */
-void reset_timer_masked(void)
-{
-	/* capure current decrementer value time */
-	lastdec = readl(&tmr->timer3_counter) / (TIMER_CLOCK / CONFIG_SYS_HZ);
-	timestamp = 0;		/* start "advancing" time stamp from 0 */
-
-	debug("%s(): lastdec = %lx\n", __func__, lastdec);
-}
-
-void reset_timer(void)
-{
-	debug("%s()\n", __func__);
-	reset_timer_masked();
-}
-
-/*
- * return timer ticks
- */
-ulong get_timer_masked(void)
-{
-	/* current tick value */
-	ulong now = readl(&tmr->timer3_counter) / (TIMER_CLOCK / CONFIG_SYS_HZ);
-
-	debug("%s(): now = %lx, lastdec = %lx\n", __func__, now, lastdec);
-
-	if (lastdec >= now) {
-		/*
-		 * normal mode (non roll)
-		 * move stamp fordward with absoulte diff ticks
-		 */
-		timestamp += lastdec - now;
-	} else {
-		/*
-		 * we have overflow of the count down timer
-		 *
-		 * nts = ts + ld + (TLV - now)
-		 * ts=old stamp, ld=time that passed before passing through -1
-		 * (TLV-now) amount of time after passing though -1
-		 * nts = new "advancing time stamp"...it could also roll and
-		 * cause problems.
-		 */
-		timestamp += lastdec + TIMER_LOAD_VAL - now;
-	}
-
-	lastdec = now;
-
-	debug("%s() returns %lx\n", __func__, timestamp);
-
-	return timestamp;
-}
-
-/*
- * return difference between timer ticks and base
- */
-ulong get_timer(ulong base)
-{
-	debug("%s(%lx)\n", __func__, base);
-	return get_timer_masked() - base;
-}
-
-void set_timer(ulong t)
-{
-	debug("%s(%lx)\n", __func__, t);
-	timestamp = t;
-}
-
-/* delay x useconds AND preserve advance timestamp value */
-void __udelay(unsigned long usec)
-{
-	long tmo = usec * (TIMER_CLOCK / 1000) / 1000;
-	unsigned long now, last = readl(&tmr->timer3_counter);
-
-	debug("%s(%lu)\n", __func__, usec);
-	while (tmo > 0) {
-		now = readl(&tmr->timer3_counter);
-		if (now > last) /* count down timer overflow */
-			tmo -= TIMER_LOAD_VAL + last - now;
-		else
-			tmo -= last - now;
-		last = now;
-	}
-}
-
-/*
- * This function is derived from PowerPC code (read timebase as long long).
- * On ARM it just returns the timer value.
- */
-unsigned long long get_ticks(void)
-{
-	debug("%s()\n", __func__);
-	return get_timer(0);
-}
-
-/*
- * This function is derived from PowerPC code (timebase clock frequency).
- * On ARM it returns the number of timer ticks per second.
- */
-ulong get_tbclk(void)
-{
-	debug("%s()\n", __func__);
-	return CONFIG_SYS_HZ;
-}
diff --git a/arch/arm/cpu/arm920t/at91/Makefile b/arch/arm/cpu/arm920t/at91/Makefile
deleted file mode 100644
index 5c71b77..0000000
--- a/arch/arm/cpu/arm920t/at91/Makefile
+++ /dev/null
@@ -1,47 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(SOC).o
-
-SOBJS	+= lowlevel_init.o
-COBJS	+= reset.o
-COBJS	+= timer.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
-
-all:	$(obj).depend $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/arch/arm/cpu/arm920t/at91/lowlevel_init.S b/arch/arm/cpu/arm920t/at91/lowlevel_init.S
deleted file mode 100644
index eaea9d2..0000000
--- a/arch/arm/cpu/arm920t/at91/lowlevel_init.S
+++ /dev/null
@@ -1,164 +0,0 @@
-/*
- * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
- *		       Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
- *
- * Modified for the at91rm9200dk board by
- * (C) Copyright 2004
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
-
-#include <asm/arch/hardware.h>
-#include <asm/arch/at91_mc.h>
-#include <asm/arch/at91_pmc.h>
-#include <asm/arch/at91_pio.h>
-
-#define ARM920T_CONTROL	0xC0000000	/* @ set bit 31 (iA) and 30 (nF) */
-
-_MTEXT_BASE:
-#undef START_FROM_MEM
-#ifdef START_FROM_MEM
-	.word	CONFIG_SYS_TEXT_BASE-PHYS_FLASH_1
-#else
-	.word	CONFIG_SYS_TEXT_BASE
-#endif
-
-.globl lowlevel_init
-lowlevel_init:
-	ldr     r1, =AT91_ASM_PMC_MOR
-	/* Main oscillator Enable register */
-#ifdef CONFIG_SYS_USE_MAIN_OSCILLATOR
-	ldr     r0, =0x0000FF01		/* Enable main oscillator */
-#else
-	ldr     r0, =0x0000FF00		/* Disable main oscillator */
-#endif
-	str     r0, [r1] /*AT91C_CKGR_MOR] */
-	/* Add loop to compensate Main Oscillator startup time */
-	ldr     r0, =0x00000010
-LoopOsc:
-	subs    r0, r0, #1
-	bhi     LoopOsc
-
-	/* memory control configuration */
-	/* this isn't very elegant, but	 what the heck */
-	ldr	r0, =SMRDATA
-	ldr	r1, _MTEXT_BASE
-	sub	r0, r0, r1
-	add	r2, r0, #80
-pllloop:
-	/* the address */
-	ldr	r1, [r0], #4
-	/* the value */
-	ldr	r3, [r0], #4
-	str	r3, [r1]
-	cmp	r2, r0
-	bne	pllloop
-	/* delay - this is all done by guess */
-	ldr	r0, =0x00010000
-	/* (vs reading PMC_SR for LOCKA, LOCKB ... or MOSCS earlier) */
-lock:
-	subs	r0, r0, #1
-	bhi	lock
-	ldr	r0, =SMRDATA1
-	ldr	r1, _MTEXT_BASE
-	sub	r0, r0, r1
-	add	r2, r0, #176
-sdinit:
-	/* the address */
-	ldr	r1, [r0], #4
-	/* the value */
-	ldr	r3, [r0], #4
-	str	r3, [r1]
-	cmp	r2, r0
-	bne	sdinit
-
-	/* switch from FastBus to Asynchronous clock mode */
-	mrc	p15, 0, r0, c1, c0, 0
-	orr	r0, r0, #ARM920T_CONTROL
-	mcr	p15, 0, r0, c1, c0, 0
-
-	/* everything is fine now */
-	mov	pc, lr
-
-	.ltorg
-
-SMRDATA:
-	.word AT91_ASM_MC_EBI_CFG
-	.word CONFIG_SYS_EBI_CFGR_VAL
-	.word AT91_ASM_MC_SMC_CSR0
-	.word CONFIG_SYS_SMC_CSR0_VAL
-	.word AT91_ASM_PMC_PLLAR
-	.word CONFIG_SYS_PLLAR_VAL
-	.word AT91_ASM_PMC_PLLBR
-	.word CONFIG_SYS_PLLBR_VAL
-	.word AT91_ASM_PMC_MCKR
-	.word CONFIG_SYS_MCKR_VAL
-	/* here there's a delay */
-SMRDATA1:
-	.word AT91_ASM_PIOC_ASR
-	.word CONFIG_SYS_PIOC_ASR_VAL
-	.word AT91_ASM_PIOC_BSR
-	.word CONFIG_SYS_PIOC_BSR_VAL
-	.word AT91_ASM_PIOC_PDR
-	.word CONFIG_SYS_PIOC_PDR_VAL
-	.word AT91_ASM_MC_EBI_CSA
-	.word CONFIG_SYS_EBI_CSA_VAL
-	.word AT91_ASM_MC_SDRAMC_CR
-	.word CONFIG_SYS_SDRC_CR_VAL
-	.word AT91_ASM_MC_SDRAMC_MR
-	.word CONFIG_SYS_SDRC_MR_VAL
-	.word CONFIG_SYS_SDRAM
-	.word CONFIG_SYS_SDRAM_VAL
-	.word AT91_ASM_MC_SDRAMC_MR
-	.word CONFIG_SYS_SDRC_MR_VAL1
-	.word CONFIG_SYS_SDRAM
-	.word CONFIG_SYS_SDRAM_VAL
-	.word CONFIG_SYS_SDRAM
-	.word CONFIG_SYS_SDRAM_VAL
-	.word CONFIG_SYS_SDRAM
-	.word CONFIG_SYS_SDRAM_VAL
-	.word CONFIG_SYS_SDRAM
-	.word CONFIG_SYS_SDRAM_VAL
-	.word CONFIG_SYS_SDRAM
-	.word CONFIG_SYS_SDRAM_VAL
-	.word CONFIG_SYS_SDRAM
-	.word CONFIG_SYS_SDRAM_VAL
-	.word CONFIG_SYS_SDRAM
-	.word CONFIG_SYS_SDRAM_VAL
-	.word CONFIG_SYS_SDRAM
-	.word CONFIG_SYS_SDRAM_VAL
-	.word AT91_ASM_MC_SDRAMC_MR
-	.word CONFIG_SYS_SDRC_MR_VAL2
-	.word CONFIG_SYS_SDRAM1
-	.word CONFIG_SYS_SDRAM_VAL
-	.word AT91_ASM_MC_SDRAMC_TR
-	.word CONFIG_SYS_SDRC_TR_VAL
-	.word CONFIG_SYS_SDRAM
-	.word CONFIG_SYS_SDRAM_VAL
-	.word AT91_ASM_MC_SDRAMC_MR
-	.word CONFIG_SYS_SDRC_MR_VAL3
-	.word CONFIG_SYS_SDRAM
-	.word CONFIG_SYS_SDRAM_VAL
-	/* SMRDATA1 is 176 bytes long */
-#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
diff --git a/arch/arm/cpu/arm920t/at91/reset.c b/arch/arm/cpu/arm920t/at91/reset.c
deleted file mode 100644
index 51043ec..0000000
--- a/arch/arm/cpu/arm920t/at91/reset.c
+++ /dev/null
@@ -1,61 +0,0 @@
-/*
- * (C) Copyright 2002
- * Lineo, Inc. <www.lineo.com>
- * Bernhard Kuhn <bkuhn@lineo.com>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Alex Zuepke <azu@sysgo.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/at91_st.h>
-
-void  __attribute__((weak)) board_reset(void)
-{
-	/* true empty function for defining weak symbol */
-}
-
-void reset_cpu(ulong ignored)
-{
-	at91_st_t *st = (at91_st_t *) AT91_ST_BASE;
-#if defined(CONFIG_AT91RM9200_USART)
-	/*shutdown the console to avoid strange chars during reset */
-	serial_exit();
-#endif
-
-	board_reset();
-
-	/* Reset the cpu by setting up the watchdog timer */
-	writel(AT91_ST_WDMR_RSTEN | AT91_ST_WDMR_EXTEN | AT91_ST_WDMR_WDV(2),
-		&st->wdmr);
-	writel(AT91_ST_CR_WDRST, &st->cr);
-	/* and let it timeout */
-	while (1)
-		;
-	/* Never reached */
-}
diff --git a/arch/arm/cpu/arm920t/at91/timer.c b/arch/arm/cpu/arm920t/at91/timer.c
deleted file mode 100644
index d9a024f..0000000
--- a/arch/arm/cpu/arm920t/at91/timer.c
+++ /dev/null
@@ -1,162 +0,0 @@
-/*
- * (C) Copyright 2002
- * Lineo, Inc. <www.lineo.com>
- * Bernhard Kuhn <bkuhn@lineo.com>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Alex Zuepke <azu@sysgo.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-
-#include <asm/arch/io.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/at91_tc.h>
-#include <asm/arch/at91_pmc.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/* the number of clocks per CONFIG_SYS_HZ */
-#define TIMER_LOAD_VAL (CONFIG_SYS_HZ_CLOCK/CONFIG_SYS_HZ)
-
-int timer_init(void)
-{
-	at91_tc_t *tc = (at91_tc_t *) AT91_TC_BASE;
-	at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
-
-	/* enables TC1.0 clock */
-	writel(1 << AT91_ID_TC0, &pmc->pcer);	/* enable clock */
-
-	writel(0, &tc->bcr);
-	writel(AT91_TC_BMR_TC0XC0S_NONE | AT91_TC_BMR_TC1XC1S_NONE |
-		AT91_TC_BMR_TC2XC2S_NONE , &tc->bmr);
-
-	writel(AT91_TC_CCR_CLKDIS, &tc->tc[0].ccr);
-	/* set to MCLK/2 and restart the timer
-	when the value in TC_RC is reached */
-	writel(AT91_TC_CMR_TCCLKS_CLOCK1 | AT91_TC_CMR_CPCTRG, &tc->tc[0].cmr);
-
-	writel(0xFFFFFFFF, &tc->tc[0].idr); /* disable interupts */
-	writel(TIMER_LOAD_VAL, &tc->tc[0].rc);
-
-	writel(AT91_TC_CCR_SWTRG | AT91_TC_CCR_CLKEN, &tc->tc[0].ccr);
-	gd->lastinc = 0;
-	gd->tbl = 0;
-
-	return 0;
-}
-
-/*
- * timer without interrupts
- */
-
-void reset_timer(void)
-{
-	reset_timer_masked();
-}
-
-ulong get_timer(ulong base)
-{
-	return get_timer_masked() - base;
-}
-
-void set_timer(ulong t)
-{
-	gd->tbl = t;
-}
-
-void __udelay(unsigned long usec)
-{
-	udelay_masked(usec);
-}
-
-void reset_timer_masked(void)
-{
-	/* reset time */
-	at91_tc_t *tc = (at91_tc_t *) AT91_TC_BASE;
-	gd->lastinc = readl(&tc->tc[0].cv) & 0x0000ffff;
-	gd->tbl = 0;
-}
-
-ulong get_timer_raw(void)
-{
-	at91_tc_t *tc = (at91_tc_t *) AT91_TC_BASE;
-	u32 now;
-
-	now = readl(&tc->tc[0].cv) & 0x0000ffff;
-
-	if (now >= gd->lastinc) {
-		/* normal mode */
-		gd->tbl += now - gd->lastinc;
-	} else {
-		/* we have an overflow ... */
-		gd->tbl += now + TIMER_LOAD_VAL - gd->lastinc;
-	}
-	gd->lastinc = now;
-
-	return gd->tbl;
-}
-
-ulong get_timer_masked(void)
-{
-	return get_timer_raw()/TIMER_LOAD_VAL;
-}
-
-void udelay_masked(unsigned long usec)
-{
-	u32 tmo;
-	u32 endtime;
-	signed long diff;
-
-	tmo = CONFIG_SYS_HZ_CLOCK / 1000;
-	tmo *= usec;
-	tmo /= 1000;
-
-	endtime = get_timer_raw() + tmo;
-
-	do {
-		u32 now = get_timer_raw();
-		diff = endtime - now;
-	} while (diff >= 0);
-}
-
-/*
- * This function is derived from PowerPC code (read timebase as long long).
- * On ARM it just returns the timer value.
- */
-unsigned long long get_ticks(void)
-{
-	return get_timer(0);
-}
-
-/*
- * This function is derived from PowerPC code (timebase clock frequency).
- * On ARM it returns the number of timer ticks per second.
- */
-ulong get_tbclk(void)
-{
-	return CONFIG_SYS_HZ;
-}
diff --git a/arch/arm/cpu/arm920t/at91rm9200/Makefile b/arch/arm/cpu/arm920t/at91rm9200/Makefile
deleted file mode 100644
index 7530e6a..0000000
--- a/arch/arm/cpu/arm920t/at91rm9200/Makefile
+++ /dev/null
@@ -1,56 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(SOC).o
-
-SOBJS	+= lowlevel_init.o
-
-COBJS	+= bcm5221.o
-COBJS	+= dm9161.o
-COBJS	+= ether.o
-COBJS	+= i2c.o
-COBJS-$(CONFIG_KS8721_PHY)	+= ks8721.o
-COBJS	+= lxt972.o
-COBJS	+= reset.o
-COBJS	+= spi.o
-COBJS	+= timer.o
-COBJS	+= usb.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS) $(COBJS-y))
-
-all:	$(obj).depend $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/arch/arm/cpu/arm920t/at91rm9200/bcm5221.c b/arch/arm/cpu/arm920t/at91rm9200/bcm5221.c
deleted file mode 100644
index 8de3cba..0000000
--- a/arch/arm/cpu/arm920t/at91rm9200/bcm5221.c
+++ /dev/null
@@ -1,232 +0,0 @@
-/*
- * Broadcom BCM5221 Ethernet PHY
- *
- * (C) Copyright 2005 REA Elektronik GmbH <www.rea.de>
- * Anders Larsen <alarsen@rea.de>
- *
- * (C) Copyright 2003
- * Author : Hamid Ikdoumi (Atmel)
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <at91rm9200_net.h>
-#include <net.h>
-#ifdef CONFIG_DRIVER_ETHER
-
-#include <bcm5221.h>
-
-#if defined(CONFIG_CMD_NET)
-
-/*
- * Name:
- *	bcm5221_IsPhyConnected
- * Description:
- *	Reads the 2 PHY ID registers
- * Arguments:
- *	p_mac - pointer to AT91S_EMAC struct
- * Return value:
- *	TRUE - if id read successfully
- *	FALSE- if error
- */
-unsigned int bcm5221_IsPhyConnected (AT91PS_EMAC p_mac)
-{
-	unsigned short Id1, Id2;
-
-	at91rm9200_EmacEnableMDIO (p_mac);
-	at91rm9200_EmacReadPhy (p_mac, BCM5221_PHYID1, &Id1);
-	at91rm9200_EmacReadPhy (p_mac, BCM5221_PHYID2, &Id2);
-	at91rm9200_EmacDisableMDIO (p_mac);
-
-	if ((Id1 == (BCM5221_PHYID1_OUI >> 6)) &&
-		((Id2 >> 10) == (BCM5221_PHYID1_OUI & BCM5221_LSB_MASK)))
-		return TRUE;
-
-	return FALSE;
-}
-
-/*
- * Name:
- *	bcm5221_GetLinkSpeed
- * Description:
- *	Link parallel detection status of MAC is checked and set in the
- *	MAC configuration registers
- * Arguments:
- *	p_mac - pointer to MAC
- * Return value:
- *	TRUE - if link status set succesfully
- *	FALSE - if link status not set
- */
-unsigned char bcm5221_GetLinkSpeed (AT91PS_EMAC p_mac)
-{
-	unsigned short stat1, stat2;
-
-	if (!at91rm9200_EmacReadPhy (p_mac, BCM5221_BMSR, &stat1))
-		return FALSE;
-
-	if (!(stat1 & BCM5221_LINK_STATUS))	/* link status up? */
-		return FALSE;
-
-	if (!at91rm9200_EmacReadPhy (p_mac, BCM5221_ACSR, &stat2))
-		return FALSE;
-
-	if ((stat1 & BCM5221_100BASE_TX_FD) && (stat2 & BCM5221_100) && (stat2 & BCM5221_FDX)) {
-		/*set Emac for 100BaseTX and Full Duplex  */
-		p_mac->EMAC_CFG |= AT91C_EMAC_SPD | AT91C_EMAC_FD;
-		return TRUE;
-	}
-
-	if ((stat1 & BCM5221_10BASE_T_FD) && !(stat2 & BCM5221_100) && (stat2 & BCM5221_FDX)) {
-		/*set MII for 10BaseT and Full Duplex  */
-		p_mac->EMAC_CFG = (p_mac->EMAC_CFG &
-				~(AT91C_EMAC_SPD | AT91C_EMAC_FD))
-				| AT91C_EMAC_FD;
-		return TRUE;
-	}
-
-	if ((stat1 & BCM5221_100BASE_TX_HD) && (stat2 & BCM5221_100) && !(stat2 & BCM5221_FDX)) {
-		/*set MII for 100BaseTX and Half Duplex  */
-		p_mac->EMAC_CFG = (p_mac->EMAC_CFG &
-				~(AT91C_EMAC_SPD | AT91C_EMAC_FD))
-				| AT91C_EMAC_SPD;
-		return TRUE;
-	}
-
-	if ((stat1 & BCM5221_10BASE_T_HD) && !(stat2 & BCM5221_100) && !(stat2 & BCM5221_FDX)) {
-		/*set MII for 10BaseT and Half Duplex  */
-		p_mac->EMAC_CFG &= ~(AT91C_EMAC_SPD | AT91C_EMAC_FD);
-		return TRUE;
-	}
-	return FALSE;
-}
-
-
-/*
- * Name:
- *	bcm5221_InitPhy
- * Description:
- *	MAC starts checking its link by using parallel detection and
- *	Autonegotiation and the same is set in the MAC configuration registers
- * Arguments:
- *	p_mac - pointer to struct AT91S_EMAC
- * Return value:
- *	TRUE - if link status set succesfully
- *	FALSE - if link status not set
- */
-unsigned char bcm5221_InitPhy (AT91PS_EMAC p_mac)
-{
-	unsigned char ret = TRUE;
-	unsigned short IntValue;
-
-	at91rm9200_EmacEnableMDIO (p_mac);
-
-	if (!bcm5221_GetLinkSpeed (p_mac)) {
-		/* Try another time */
-		ret = bcm5221_GetLinkSpeed (p_mac);
-	}
-
-	/* Disable PHY Interrupts */
-	at91rm9200_EmacReadPhy (p_mac, BCM5221_INTR, &IntValue);
-	/* clear FDX LED and INTR Enable */
-	IntValue &= ~(BCM5221_FDX_LED | BCM5221_INTR_ENABLE);
-	/* set FDX, SPD, Link, INTR masks */
-	IntValue |= (BCM5221_FDX_MASK  | BCM5221_SPD_MASK |
-		     BCM5221_LINK_MASK | BCM5221_INTR_MASK);
-	at91rm9200_EmacWritePhy (p_mac, BCM5221_INTR, &IntValue);
-	at91rm9200_EmacDisableMDIO (p_mac);
-
-	return (ret);
-}
-
-
-/*
- * Name:
- *	bcm5221_AutoNegotiate
- * Description:
- *	MAC Autonegotiates with the partner status of same is set in the
- *	MAC configuration registers
- * Arguments:
- *	dev - pointer to struct net_device
- * Return value:
- *	TRUE - if link status set successfully
- *	FALSE - if link status not set
- */
-unsigned char bcm5221_AutoNegotiate (AT91PS_EMAC p_mac, int *status)
-{
-	unsigned short value;
-	unsigned short PhyAnar;
-	unsigned short PhyAnalpar;
-
-	/* Set bcm5221 control register */
-	if (!at91rm9200_EmacReadPhy (p_mac, BCM5221_BMCR, &value))
-		return FALSE;
-	value &= ~BCM5221_AUTONEG;	/* remove autonegotiation enable */
-	value |=  BCM5221_ISOLATE;	/* Electrically isolate PHY */
-	if (!at91rm9200_EmacWritePhy (p_mac, BCM5221_BMCR, &value))
-		return FALSE;
-
-	/* Set the Auto_negotiation Advertisement Register */
-	/* MII advertising for 100BaseTxFD and HD, 10BaseTFD and HD, IEEE 802.3 */
-	PhyAnar = BCM5221_TX_FDX | BCM5221_TX_HDX |
-		  BCM5221_10_FDX | BCM5221_10_HDX | BCM5221_AN_IEEE_802_3;
-	if (!at91rm9200_EmacWritePhy (p_mac, BCM5221_ANAR, &PhyAnar))
-		return FALSE;
-
-	/* Read the Control Register     */
-	if (!at91rm9200_EmacReadPhy (p_mac, BCM5221_BMCR, &value))
-		return FALSE;
-
-	value |= BCM5221_SPEED_SELECT | BCM5221_AUTONEG | BCM5221_DUPLEX_MODE;
-	if (!at91rm9200_EmacWritePhy (p_mac, BCM5221_BMCR, &value))
-		return FALSE;
-	/* Restart Auto_negotiation  */
-	value |= BCM5221_RESTART_AUTONEG;
-	value &= ~BCM5221_ISOLATE;
-	if (!at91rm9200_EmacWritePhy (p_mac, BCM5221_BMCR, &value))
-		return FALSE;
-
-	/*check AutoNegotiate complete */
-	udelay (10000);
-	at91rm9200_EmacReadPhy (p_mac, BCM5221_BMSR, &value);
-	if (!(value & BCM5221_AUTONEG_COMP))
-		return FALSE;
-
-	/* Get the AutoNeg Link partner base page */
-	if (!at91rm9200_EmacReadPhy (p_mac, BCM5221_ANLPAR, &PhyAnalpar))
-		return FALSE;
-
-	if ((PhyAnar & BCM5221_TX_FDX) && (PhyAnalpar & BCM5221_TX_FDX)) {
-		/*set MII for 100BaseTX and Full Duplex  */
-		p_mac->EMAC_CFG |= AT91C_EMAC_SPD | AT91C_EMAC_FD;
-		return TRUE;
-	}
-
-	if ((PhyAnar & BCM5221_10_FDX) && (PhyAnalpar & BCM5221_10_FDX)) {
-		/*set MII for 10BaseT and Full Duplex  */
-		p_mac->EMAC_CFG = (p_mac->EMAC_CFG &
-				~(AT91C_EMAC_SPD | AT91C_EMAC_FD))
-				| AT91C_EMAC_FD;
-		return TRUE;
-	}
-	return FALSE;
-}
-
-#endif
-
-#endif	/* CONFIG_DRIVER_ETHER */
diff --git a/arch/arm/cpu/arm920t/at91rm9200/dm9161.c b/arch/arm/cpu/arm920t/at91rm9200/dm9161.c
deleted file mode 100644
index 6d4384f..0000000
--- a/arch/arm/cpu/arm920t/at91rm9200/dm9161.c
+++ /dev/null
@@ -1,225 +0,0 @@
-/*
- * (C) Copyright 2003
- * Author : Hamid Ikdoumi (Atmel)
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <at91rm9200_net.h>
-#include <net.h>
-#ifdef CONFIG_DRIVER_ETHER
-#include <dm9161.h>
-
-#if defined(CONFIG_CMD_NET)
-
-/*
- * Name:
- *	dm9161_IsPhyConnected
- * Description:
- *	Reads the 2 PHY ID registers
- * Arguments:
- *	p_mac - pointer to AT91S_EMAC struct
- * Return value:
- *	TRUE - if id read successfully
- *	FALSE- if error
- */
-unsigned int dm9161_IsPhyConnected (AT91PS_EMAC p_mac)
-{
-	unsigned short Id1, Id2;
-
-	at91rm9200_EmacEnableMDIO (p_mac);
-	at91rm9200_EmacReadPhy (p_mac, DM9161_PHYID1, &Id1);
-	at91rm9200_EmacReadPhy (p_mac, DM9161_PHYID2, &Id2);
-	at91rm9200_EmacDisableMDIO (p_mac);
-
-	if ((Id1 == (DM9161_PHYID1_OUI >> 6)) &&
-		((Id2 >> 10) == (DM9161_PHYID1_OUI & DM9161_LSB_MASK)))
-		return TRUE;
-
-	return FALSE;
-}
-
-/*
- * Name:
- *	dm9161_GetLinkSpeed
- * Description:
- *	Link parallel detection status of MAC is checked and set in the
- *	MAC configuration registers
- * Arguments:
- *	p_mac - pointer to MAC
- * Return value:
- *	TRUE - if link status set succesfully
- *	FALSE - if link status not set
- */
-UCHAR dm9161_GetLinkSpeed (AT91PS_EMAC p_mac)
-{
-	unsigned short stat1, stat2;
-
-	if (!at91rm9200_EmacReadPhy (p_mac, DM9161_BMSR, &stat1))
-		return FALSE;
-
-	if (!(stat1 & DM9161_LINK_STATUS))	/* link status up? */
-		return FALSE;
-
-	if (!at91rm9200_EmacReadPhy (p_mac, DM9161_DSCSR, &stat2))
-		return FALSE;
-
-	if ((stat1 & DM9161_100BASE_TX_FD) && (stat2 & DM9161_100FDX)) {
-		/*set Emac for 100BaseTX and Full Duplex  */
-		p_mac->EMAC_CFG |= AT91C_EMAC_SPD | AT91C_EMAC_FD;
-		return TRUE;
-	}
-
-	if ((stat1 & DM9161_10BASE_T_FD) && (stat2 & DM9161_10FDX)) {
-		/*set MII for 10BaseT and Full Duplex  */
-		p_mac->EMAC_CFG = (p_mac->EMAC_CFG &
-				~(AT91C_EMAC_SPD | AT91C_EMAC_FD))
-				| AT91C_EMAC_FD;
-		return TRUE;
-	}
-
-	if ((stat1 & DM9161_100BASE_TX_HD) && (stat2 & DM9161_100HDX)) {
-		/*set MII for 100BaseTX and Half Duplex  */
-		p_mac->EMAC_CFG = (p_mac->EMAC_CFG &
-				~(AT91C_EMAC_SPD | AT91C_EMAC_FD))
-				| AT91C_EMAC_SPD;
-		return TRUE;
-	}
-
-	if ((stat1 & DM9161_10BASE_T_HD) && (stat2 & DM9161_10HDX)) {
-		/*set MII for 10BaseT and Half Duplex  */
-		p_mac->EMAC_CFG &= ~(AT91C_EMAC_SPD | AT91C_EMAC_FD);
-		return TRUE;
-	}
-	return FALSE;
-}
-
-
-/*
- * Name:
- *	dm9161_InitPhy
- * Description:
- *	MAC starts checking its link by using parallel detection and
- *	Autonegotiation and the same is set in the MAC configuration registers
- * Arguments:
- *	p_mac - pointer to struct AT91S_EMAC
- * Return value:
- *	TRUE - if link status set succesfully
- *	FALSE - if link status not set
- */
-UCHAR dm9161_InitPhy (AT91PS_EMAC p_mac)
-{
-	UCHAR ret = TRUE;
-	unsigned short IntValue;
-
-	at91rm9200_EmacEnableMDIO (p_mac);
-
-	if (!dm9161_GetLinkSpeed (p_mac)) {
-		/* Try another time */
-		ret = dm9161_GetLinkSpeed (p_mac);
-	}
-
-	/* Disable PHY Interrupts */
-	at91rm9200_EmacReadPhy (p_mac, DM9161_MDINTR, &IntValue);
-	/* set FDX, SPD, Link, INTR masks */
-	IntValue |= (DM9161_FDX_MASK | DM9161_SPD_MASK |
-			DM9161_LINK_MASK | DM9161_INTR_MASK);
-	at91rm9200_EmacWritePhy (p_mac, DM9161_MDINTR, &IntValue);
-	at91rm9200_EmacDisableMDIO (p_mac);
-
-	return (ret);
-}
-
-
-/*
- * Name:
- *	dm9161_AutoNegotiate
- * Description:
- *	MAC Autonegotiates with the partner status of same is set in the
- *	MAC configuration registers
- * Arguments:
- *	dev - pointer to struct net_device
- * Return value:
- *	TRUE - if link status set successfully
- *	FALSE - if link status not set
- */
-UCHAR dm9161_AutoNegotiate (AT91PS_EMAC p_mac, int *status)
-{
-	unsigned short value;
-	unsigned short PhyAnar;
-	unsigned short PhyAnalpar;
-
-	/* Set dm9161 control register */
-	if (!at91rm9200_EmacReadPhy (p_mac, DM9161_BMCR, &value))
-		return FALSE;
-	value &= ~DM9161_AUTONEG;	/* remove autonegotiation enable */
-	value |= DM9161_ISOLATE;	/* Electrically isolate PHY */
-	if (!at91rm9200_EmacWritePhy (p_mac, DM9161_BMCR, &value))
-		return FALSE;
-
-	/* Set the Auto_negotiation Advertisement Register	*/
-	/* MII advertising for Next page, 100BaseTxFD and HD,	*/
-	/* 10BaseTFD and HD, IEEE 802.3 */
-	PhyAnar = DM9161_NP | DM9161_TX_FDX | DM9161_TX_HDX |
-			DM9161_10_FDX | DM9161_10_HDX | DM9161_AN_IEEE_802_3;
-	if (!at91rm9200_EmacWritePhy (p_mac, DM9161_ANAR, &PhyAnar))
-		return FALSE;
-
-	/* Read the Control Register     */
-	if (!at91rm9200_EmacReadPhy (p_mac, DM9161_BMCR, &value))
-		return FALSE;
-
-	value |= DM9161_SPEED_SELECT | DM9161_AUTONEG | DM9161_DUPLEX_MODE;
-	if (!at91rm9200_EmacWritePhy (p_mac, DM9161_BMCR, &value))
-		return FALSE;
-	/* Restart Auto_negotiation  */
-	value |= DM9161_RESTART_AUTONEG;
-	value &= ~DM9161_ISOLATE;
-	if (!at91rm9200_EmacWritePhy (p_mac, DM9161_BMCR, &value))
-		return FALSE;
-
-	/*check AutoNegotiate complete */
-	udelay (10000);
-	at91rm9200_EmacReadPhy (p_mac, DM9161_BMSR, &value);
-	if (!(value & DM9161_AUTONEG_COMP))
-		return FALSE;
-
-	/* Get the AutoNeg Link partner base page */
-	if (!at91rm9200_EmacReadPhy (p_mac, DM9161_ANLPAR, &PhyAnalpar))
-		return FALSE;
-
-	if ((PhyAnar & DM9161_TX_FDX) && (PhyAnalpar & DM9161_TX_FDX)) {
-		/*set MII for 100BaseTX and Full Duplex  */
-		p_mac->EMAC_CFG |= AT91C_EMAC_SPD | AT91C_EMAC_FD;
-		return TRUE;
-	}
-
-	if ((PhyAnar & DM9161_10_FDX) && (PhyAnalpar & DM9161_10_FDX)) {
-		/*set MII for 10BaseT and Full Duplex  */
-		p_mac->EMAC_CFG = (p_mac->EMAC_CFG &
-				~(AT91C_EMAC_SPD | AT91C_EMAC_FD))
-				| AT91C_EMAC_FD;
-		return TRUE;
-	}
-	return FALSE;
-}
-
-#endif
-
-#endif	/* CONFIG_DRIVER_ETHER */
diff --git a/arch/arm/cpu/arm920t/at91rm9200/ether.c b/arch/arm/cpu/arm920t/at91rm9200/ether.c
deleted file mode 100644
index e1cdeba..0000000
--- a/arch/arm/cpu/arm920t/at91rm9200/ether.c
+++ /dev/null
@@ -1,316 +0,0 @@
-/*
- * (C) Copyright 2003
- * Author : Hamid Ikdoumi (Atmel)
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <at91rm9200_net.h>
-#include <net.h>
-#include <miiphy.h>
-#include <asm/mach-types.h>
-
-/* ----- Ethernet Buffer definitions ----- */
-
-typedef struct {
-	unsigned long addr, size;
-} rbf_t;
-
-#define RBF_ADDR      0xfffffffc
-#define RBF_OWNER     (1<<0)
-#define RBF_WRAP      (1<<1)
-#define RBF_BROADCAST (1<<31)
-#define RBF_MULTICAST (1<<30)
-#define RBF_UNICAST   (1<<29)
-#define RBF_EXTERNAL  (1<<28)
-#define RBF_UNKOWN    (1<<27)
-#define RBF_SIZE      0x07ff
-#define RBF_LOCAL4    (1<<26)
-#define RBF_LOCAL3    (1<<25)
-#define RBF_LOCAL2    (1<<24)
-#define RBF_LOCAL1    (1<<23)
-
-#define RBF_FRAMEMAX 64
-#define RBF_FRAMELEN 0x600
-
-#ifdef CONFIG_DRIVER_ETHER
-
-#if defined(CONFIG_CMD_NET)
-
-/* alignment as per Errata #11 (64 bytes) is insufficient! */
-rbf_t rbfdt[RBF_FRAMEMAX] __attribute__((aligned(512)));
-rbf_t *rbfp;
-
-unsigned char rbf_framebuf[RBF_FRAMEMAX][RBF_FRAMELEN]
-	__attribute__((aligned(4)));
-
-/* structure to interface the PHY */
-AT91S_PhyOps PhyOps;
-
-AT91PS_EMAC p_mac;
-
-/*********** EMAC Phy layer Management functions *************************/
-/*
- * Name:
- *	at91rm9200_EmacEnableMDIO
- * Description:
- *	Enables the MDIO bit in MAC control register
- * Arguments:
- *	p_mac - pointer to struct AT91S_EMAC
- * Return value:
- *	none
- */
-void at91rm9200_EmacEnableMDIO (AT91PS_EMAC p_mac)
-{
-	/* Mac CTRL reg set for MDIO enable */
-	p_mac->EMAC_CTL |= AT91C_EMAC_MPE;	/* Management port enable */
-}
-
-/*
- * Name:
- *	at91rm9200_EmacDisableMDIO
- * Description:
- *	Disables the MDIO bit in MAC control register
- * Arguments:
- *	p_mac - pointer to struct AT91S_EMAC
- * Return value:
- *	none
- */
-void at91rm9200_EmacDisableMDIO (AT91PS_EMAC p_mac)
-{
-	/* Mac CTRL reg set for MDIO disable */
-	p_mac->EMAC_CTL &= ~AT91C_EMAC_MPE;	/* Management port disable */
-}
-
-
-/*
- * Name:
- *	at91rm9200_EmacReadPhy
- * Description:
- *	Reads data from the PHY register
- * Arguments:
- *	dev - pointer to struct net_device
- *	RegisterAddress - unsigned char
- *	pInput - pointer to value read from register
- * Return value:
- *	TRUE - if data read successfully
- */
-UCHAR at91rm9200_EmacReadPhy (AT91PS_EMAC p_mac,
-				     unsigned char RegisterAddress,
-				     unsigned short *pInput)
-{
-	p_mac->EMAC_MAN = (AT91C_EMAC_HIGH & ~AT91C_EMAC_LOW) |
-			  (AT91C_EMAC_RW_R) |
-			  (RegisterAddress << 18) |
-			  (AT91C_EMAC_CODE_802_3);
-
-	udelay (10000);
-
-	*pInput = (unsigned short) p_mac->EMAC_MAN;
-
-	return TRUE;
-}
-
-
-/*
- * Name:
- *	at91rm9200_EmacWritePhy
- * Description:
- *	Writes data to the PHY register
- * Arguments:
- *	dev - pointer to struct net_device
- *	RegisterAddress - unsigned char
- *	pOutput - pointer to value to be written in the register
- * Return value:
- *	TRUE - if data read successfully
- */
-UCHAR at91rm9200_EmacWritePhy (AT91PS_EMAC p_mac,
-				      unsigned char RegisterAddress,
-				      unsigned short *pOutput)
-{
-	p_mac->EMAC_MAN = (AT91C_EMAC_HIGH & ~AT91C_EMAC_LOW) |
-			AT91C_EMAC_CODE_802_3 | AT91C_EMAC_RW_W |
-			(RegisterAddress << 18) | *pOutput;
-
-	udelay (10000);
-
-	return TRUE;
-}
-
-int eth_init (bd_t * bd)
-{
-	int ret;
-	int i;
-	uchar enetaddr[6];
-
-	p_mac = AT91C_BASE_EMAC;
-
-	/* PIO Disable Register */
-	*AT91C_PIOA_PDR = AT91C_PA16_EMDIO | AT91C_PA15_EMDC | AT91C_PA14_ERXER |
-			  AT91C_PA13_ERX1 | AT91C_PA12_ERX0 | AT91C_PA11_ECRS_ECRSDV |
-			  AT91C_PA10_ETX1 | AT91C_PA9_ETX0 | AT91C_PA8_ETXEN |
-			  AT91C_PA7_ETXCK_EREFCK;
-
-#ifdef CONFIG_AT91C_USE_RMII
-	*AT91C_PIOB_PDR = AT91C_PB19_ERXCK;
-	*AT91C_PIOB_BSR = AT91C_PB19_ERXCK;
-#else
-	*AT91C_PIOB_PDR = AT91C_PB19_ERXCK | AT91C_PB18_ECOL | AT91C_PB17_ERXDV |
-			  AT91C_PB16_ERX3 | AT91C_PB15_ERX2 | AT91C_PB14_ETXER |
-			  AT91C_PB13_ETX3 | AT91C_PB12_ETX2;
-
-	/* Select B Register */
-	*AT91C_PIOB_BSR = AT91C_PB19_ERXCK | AT91C_PB18_ECOL |
-			  AT91C_PB17_ERXDV | AT91C_PB16_ERX3 | AT91C_PB15_ERX2 |
-			  AT91C_PB14_ETXER | AT91C_PB13_ETX3 | AT91C_PB12_ETX2;
-#endif
-
-	*AT91C_PMC_PCER = 1 << AT91C_ID_EMAC;	/* Peripheral Clock Enable Register */
-
-	p_mac->EMAC_CFG |= AT91C_EMAC_CSR;	/* Clear statistics */
-
-	/* Init Ethernet buffers */
-	for (i = 0; i < RBF_FRAMEMAX; i++) {
-		rbfdt[i].addr = (unsigned long)rbf_framebuf[i];
-		rbfdt[i].size = 0;
-	}
-	rbfdt[RBF_FRAMEMAX - 1].addr |= RBF_WRAP;
-	rbfp = &rbfdt[0];
-
-	eth_getenv_enetaddr("ethaddr", enetaddr);
-
-	/* The CSB337 originally used a version of the MicroMonitor bootloader
-	 * which saved Ethernet addresses in the "wrong" order.  Operating
-	 * systems (like Linux) know this, and apply a workaround.  Replicate
-	 * that MicroMonitor behavior so we avoid needing to make such OS code
-	 * care about which bootloader was used.
-	 */
-	if (machine_is_csb337()) {
-		p_mac->EMAC_SA2H = (enetaddr[0] <<  8) | (enetaddr[1]);
-		p_mac->EMAC_SA2L = (enetaddr[2] << 24) | (enetaddr[3] << 16)
-				 | (enetaddr[4] <<  8) | (enetaddr[5]);
-	} else {
-		p_mac->EMAC_SA2L = (enetaddr[3] << 24) | (enetaddr[2] << 16)
-				 | (enetaddr[1] <<  8) | (enetaddr[0]);
-		p_mac->EMAC_SA2H = (enetaddr[5] <<  8) | (enetaddr[4]);
-	}
-
-	p_mac->EMAC_RBQP = (long) (&rbfdt[0]);
-	p_mac->EMAC_RSR &= ~(AT91C_EMAC_RSR_OVR | AT91C_EMAC_REC | AT91C_EMAC_BNA);
-
-	p_mac->EMAC_CFG = (p_mac->EMAC_CFG | AT91C_EMAC_CAF | AT91C_EMAC_NBC)
-			& ~AT91C_EMAC_CLK;
-
-#ifdef CONFIG_AT91C_USE_RMII
-	p_mac->EMAC_CFG |= AT91C_EMAC_RMII;
-#endif
-
-#if (AT91C_MASTER_CLOCK > 40000000)
-	/* MDIO clock must not exceed 2.5 MHz, so enable MCK divider */
-	p_mac->EMAC_CFG |= AT91C_EMAC_CLK_HCLK_64;
-#endif
-
-	p_mac->EMAC_CTL |= AT91C_EMAC_TE | AT91C_EMAC_RE;
-
-	at91rm9200_GetPhyInterface (& PhyOps);
-
-	if (!PhyOps.IsPhyConnected (p_mac))
-		printf ("PHY not connected!!\n\r");
-
-	/* MII management start from here */
-	if (!(p_mac->EMAC_SR & AT91C_EMAC_LINK)) {
-		if (!(ret = PhyOps.Init (p_mac))) {
-			printf ("MAC: error during MII initialization\n");
-			return 0;
-		}
-	} else {
-		printf ("No link\n\r");
-		return 0;
-	}
-
-	return 0;
-}
-
-int eth_send (volatile void *packet, int length)
-{
-	while (!(p_mac->EMAC_TSR & AT91C_EMAC_BNQ));
-	p_mac->EMAC_TAR = (long) packet;
-	p_mac->EMAC_TCR = length;
-	while (p_mac->EMAC_TCR & 0x7ff);
-	p_mac->EMAC_TSR |= AT91C_EMAC_COMP;
-	return 0;
-}
-
-int eth_rx (void)
-{
-	int size;
-
-	if (!(rbfp->addr & RBF_OWNER))
-		return 0;
-
-	size = rbfp->size & RBF_SIZE;
-	NetReceive ((volatile uchar *) (rbfp->addr & RBF_ADDR), size);
-
-	rbfp->addr &= ~RBF_OWNER;
-	if (rbfp->addr & RBF_WRAP)
-		rbfp = &rbfdt[0];
-	else
-		rbfp++;
-
-	p_mac->EMAC_RSR |= AT91C_EMAC_REC;
-
-	return size;
-}
-
-void eth_halt (void)
-{
-};
-
-#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
-int  at91rm9200_miiphy_read(const char *devname, unsigned char addr,
-		unsigned char reg, unsigned short * value)
-{
-	at91rm9200_EmacEnableMDIO (p_mac);
-	at91rm9200_EmacReadPhy (p_mac, reg, value);
-	at91rm9200_EmacDisableMDIO (p_mac);
-	return 0;
-}
-
-int  at91rm9200_miiphy_write(const char *devname, unsigned char addr,
-		unsigned char reg, unsigned short value)
-{
-	at91rm9200_EmacEnableMDIO (p_mac);
-	at91rm9200_EmacWritePhy (p_mac, reg, &value);
-	at91rm9200_EmacDisableMDIO (p_mac);
-	return 0;
-}
-
-#endif
-
-int at91rm9200_miiphy_initialize(bd_t *bis)
-{
-#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
-	miiphy_register("at91rm9200phy", at91rm9200_miiphy_read, at91rm9200_miiphy_write);
-#endif
-	return 0;
-}
-
-#endif
-
-#endif	/* CONFIG_DRIVER_ETHER */
diff --git a/arch/arm/cpu/arm920t/at91rm9200/i2c.c b/arch/arm/cpu/arm920t/at91rm9200/i2c.c
deleted file mode 100644
index 1711088..0000000
--- a/arch/arm/cpu/arm920t/at91rm9200/i2c.c
+++ /dev/null
@@ -1,192 +0,0 @@
-/*
- *  i2c Support for Atmel's AT91RM9200 Two-Wire Interface
- *
- *  (c) Rick Bronson
- *
- *  Borrowed heavily from original work by:
- *  Copyright (c) 2000 Philip Edelbrock <phil@stimpy.netroedge.com>
- *
- *  Modified to work with u-boot by (C) 2004 Gary Jennejohn garyj@denx.de
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License
- *  along with this program; if not, write to the Free Software
- *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
-*/
-#include <common.h>
-
-#ifdef CONFIG_HARD_I2C
-
-#include <i2c.h>
-#include <asm/io.h>
-#include <asm/arch/hardware.h>
-
-#include <at91rm9200_i2c.h>
-
-/* define DEBUG */
-
-/*
- * Poll the i2c status register until the specified bit is set.
- * Returns 0 if timed out (100 msec)
- */
-static short at91_poll_status(AT91PS_TWI twi, unsigned long bit) {
-	int loop_cntr = 10000;
-	do {
-		udelay(10);
-	} while (!(twi->TWI_SR & bit) && (--loop_cntr > 0));
-
-	return (loop_cntr > 0);
-}
-
-/*
- * Generic i2c master transfer entrypoint
- *
- * rw == 1 means that this is a read
- */
-static int
-at91_xfer(unsigned char chip, unsigned int addr, int alen,
-						unsigned char *buffer, int len, int rw)
-{
-	AT91PS_TWI twi = (AT91PS_TWI) AT91_TWI_BASE;
-	int length;
-	unsigned char *buf;
-	/* Set the TWI Master Mode Register */
-	twi->TWI_MMR = (chip << 16) | (alen << 8)
-		| ((rw == 1) ? AT91C_TWI_MREAD : 0);
-
-	/* Set TWI Internal Address Register with first messages data field */
-	if (alen > 0)
-		twi->TWI_IADR = addr;
-
-	length = len;
-	buf = buffer;
-	if (length && buf) {	/* sanity check */
-		if (rw) {
-			twi->TWI_CR = AT91C_TWI_START;
-			while (length--) {
-				if (!length)
-					twi->TWI_CR = AT91C_TWI_STOP;
-				/* Wait until transfer is finished */
-				if (!at91_poll_status(twi, AT91C_TWI_RXRDY)) {
-					debug ("at91_i2c: timeout 1\n");
-					return 1;
-				}
-				*buf++ = twi->TWI_RHR;
-			}
-			if (!at91_poll_status(twi, AT91C_TWI_TXCOMP)) {
-				debug ("at91_i2c: timeout 2\n");
-				return 1;
-			}
-		} else {
-			twi->TWI_CR = AT91C_TWI_START;
-			while (length--) {
-				twi->TWI_THR = *buf++;
-				if (!length)
-					twi->TWI_CR = AT91C_TWI_STOP;
-				if (!at91_poll_status(twi, AT91C_TWI_TXRDY)) {
-					debug ("at91_i2c: timeout 3\n");
-					return 1;
-				}
-			}
-			/* Wait until transfer is finished */
-			if (!at91_poll_status(twi, AT91C_TWI_TXCOMP)) {
-				debug ("at91_i2c: timeout 4\n");
-				return 1;
-			}
-		}
-	}
-	return 0;
-}
-
-int
-i2c_probe(unsigned char chip)
-{
-	unsigned char buffer[1];
-
-	return at91_xfer(chip, 0, 0, buffer, 1, 1);
-}
-
-int
-i2c_read (unsigned char chip, unsigned int addr, int alen,
-	  unsigned char *buffer, int len)
-{
-#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
-	/* we only allow one address byte */
-	if (alen > 1)
-		return 1;
-	/* XXX assume an ATMEL AT24C16 */
-	if (alen == 1) {
-#if 0 /* EEPROM code already sets this correctly */
-		chip |= (addr >> 8) & 0xff;
-#endif
-		addr = addr & 0xff;
-	}
-#endif
-	return at91_xfer(chip, addr, alen, buffer, len, 1);
-}
-
-int
-i2c_write(unsigned char chip, unsigned int addr, int alen,
-	  unsigned char *buffer, int len)
-{
-#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
-	int i;
-	unsigned char *buf;
-
-	/* we only allow one address byte */
-	if (alen > 1)
-		return 1;
-	/* XXX assume an ATMEL AT24C16 */
-	if (alen == 1) {
-		buf = buffer;
-		/* do single byte writes */
-		for (i = 0; i < len; i++) {
-#if 0 /* EEPROM code already sets this correctly */
-			chip |= (addr >> 8) & 0xff;
-#endif
-			addr = addr & 0xff;
-			if (at91_xfer(chip, addr, alen, buf++, 1, 0))
-				return 1;
-			addr++;
-		}
-		return 0;
-	}
-#endif
-	return at91_xfer(chip, addr, alen, buffer, len, 0);
-}
-
-/*
- * Main initialization routine
- */
-void
-i2c_init(int speed, int slaveaddr)
-{
-	AT91PS_TWI twi = (AT91PS_TWI) AT91_TWI_BASE;
-
-	*AT91C_PIOA_PDR = AT91C_PA25_TWD | AT91C_PA26_TWCK;
-	*AT91C_PIOA_ASR = AT91C_PA25_TWD | AT91C_PA26_TWCK;
-	*AT91C_PIOA_MDER = AT91C_PA25_TWD | AT91C_PA26_TWCK;
-	*AT91C_PMC_PCER = 1 << AT91C_ID_TWI;		/* enable peripheral clock */
-
-	twi->TWI_IDR = 0x3ff;				/* Disable all interrupts */
-	twi->TWI_CR = AT91C_TWI_SWRST;			/* Reset peripheral */
-	twi->TWI_CR = AT91C_TWI_MSEN | AT91C_TWI_SVDIS;	/* Set Master mode */
-
-	/* Here, CKDIV = 1 and CHDIV=CLDIV  ==> CLDIV = CHDIV = 1/4*((Fmclk/FTWI) -6) */
-	twi->TWI_CWGR = AT91C_TWI_CKDIV1 | AT91C_TWI_CLDIV3 | (AT91C_TWI_CLDIV3 << 8);
-
-	debug ("Found AT91 i2c\n");
-	return;
-}
-
-#endif /* CONFIG_HARD_I2C */
diff --git a/arch/arm/cpu/arm920t/at91rm9200/ks8721.c b/arch/arm/cpu/arm920t/at91rm9200/ks8721.c
deleted file mode 100644
index 9fe3793..0000000
--- a/arch/arm/cpu/arm920t/at91rm9200/ks8721.c
+++ /dev/null
@@ -1,249 +0,0 @@
-/*
- * (C) Copyright 2006
- * Author : Eric Benard (Eukrea Electromatique)
- * based on dm9161.c which is :
- * (C) Copyright 2003
- * Author : Hamid Ikdoumi (Atmel)
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <at91rm9200_net.h>
-#include <net.h>
-#include <ks8721.h>
-
-#ifdef CONFIG_DRIVER_ETHER
-
-#if defined(CONFIG_CMD_NET)
-
-/*
- * Name:
- *	ks8721_isphyconnected
- * Description:
- *	Reads the 2 PHY ID registers
- * Arguments:
- *	p_mac - pointer to AT91S_EMAC struct
- * Return value:
- *	1 - if id read successfully
- *	0 - if error
- */
-unsigned int ks8721_isphyconnected(AT91PS_EMAC p_mac)
-{
-	unsigned short id1, id2;
-
-	at91rm9200_EmacEnableMDIO(p_mac);
-	at91rm9200_EmacReadPhy(p_mac,
-		CONFIG_PHY_ADDRESS | KS8721_PHYID1, &id1);
-	at91rm9200_EmacReadPhy(p_mac,
-		CONFIG_PHY_ADDRESS | KS8721_PHYID2, &id2);
-	at91rm9200_EmacDisableMDIO(p_mac);
-
-	if ((id1 == (KS8721_PHYID_OUI >> 6)) &&
-		((id2 >> 10) == (KS8721_PHYID_OUI & KS8721_LSB_MASK))) {
-		if ((id2 & KS8721_MODELMASK) == KS8721BL_MODEL)
-			printf("Micrel KS8721bL PHY detected : ");
-		else
-			printf("Unknown Micrel PHY detected : ");
-		return 1;
-	}
-	return 0;
-}
-
-/*
- * Name:
- *	ks8721_getlinkspeed
- * Description:
- *	Link parallel detection status of MAC is checked and set in the
- *	MAC configuration registers
- * Arguments:
- *	p_mac - pointer to MAC
- * Return value:
- *	1 - if link status set succesfully
- *	0 - if link status not set
- */
-unsigned char ks8721_getlinkspeed(AT91PS_EMAC p_mac)
-{
-	unsigned short stat1;
-
-	if (!at91rm9200_EmacReadPhy(p_mac, KS8721_BMSR, &stat1))
-		return 0;
-
-	if (!(stat1 & KS8721_LINK_STATUS)) {
-		/* link status up? */
-		printf("Link Down !\n");
-		return 0;
-	}
-
-	if (stat1 & KS8721_100BASE_TX_FD) {
-		/* set Emac for 100BaseTX and Full Duplex */
-		printf("100BT FD\n");
-		p_mac->EMAC_CFG |= AT91C_EMAC_SPD | AT91C_EMAC_FD;
-		return 1;
-	}
-
-	if (stat1 & KS8721_10BASE_T_FD) {
-		/* set MII for 10BaseT and Full Duplex */
-		printf("10BT FD\n");
-		p_mac->EMAC_CFG = (p_mac->EMAC_CFG &
-				~(AT91C_EMAC_SPD | AT91C_EMAC_FD))
-				| AT91C_EMAC_FD;
-		return 1;
-	}
-
-	if (stat1 & KS8721_100BASE_T4_HD) {
-		/* set MII for 100BaseTX and Half Duplex */
-		printf("100BT HD\n");
-		p_mac->EMAC_CFG = (p_mac->EMAC_CFG &
-				~(AT91C_EMAC_SPD | AT91C_EMAC_FD))
-				| AT91C_EMAC_SPD;
-		return 1;
-	}
-
-	if (stat1 & KS8721_10BASE_T_HD) {
-		/* set MII for 10BaseT and Half Duplex */
-		printf("10BT HD\n");
-		p_mac->EMAC_CFG &= ~(AT91C_EMAC_SPD | AT91C_EMAC_FD);
-		return 1;
-	}
-	return 0;
-}
-
-/*
- * Name:
- *	ks8721_initphy
- * Description:
- *	MAC starts checking its link by using parallel detection and
- *	Autonegotiation and the same is set in the MAC configuration registers
- * Arguments:
- *	p_mac - pointer to struct AT91S_EMAC
- * Return value:
- *	1 - if link status set succesfully
- *	0 - if link status not set
- */
-unsigned char ks8721_initphy(AT91PS_EMAC p_mac)
-{
-	unsigned char ret = 1;
-	unsigned short intvalue;
-
-	at91rm9200_EmacEnableMDIO(p_mac);
-
-	/* Try another time */
-	if (!ks8721_getlinkspeed(p_mac))
-		ret = ks8721_getlinkspeed(p_mac);
-
-	/* Disable PHY Interrupts */
-	intvalue = 0;
-	at91rm9200_EmacWritePhy(p_mac,
-		CONFIG_PHY_ADDRESS | KS8721_MDINTR, &intvalue);
-	at91rm9200_EmacDisableMDIO(p_mac);
-
-	return ret;
-}
-
-/*
- * Name:
- *	ks8721_autonegotiate
- * Description:
- *	MAC Autonegotiates with the partner status of same is set in the
- *	MAC configuration registers
- * Arguments:
- *	dev - pointer to struct net_device
- * Return value:
- *	1 - if link status set successfully
- *	0 - if link status not set
- */
-unsigned char ks8721_autonegotiate(AT91PS_EMAC p_mac, int *status)
-{
-	unsigned short value;
-	unsigned short phyanar;
-	unsigned short phyanalpar;
-
-	/* Set ks8721 control register */
-	if (!at91rm9200_EmacReadPhy(p_mac,
-		CONFIG_PHY_ADDRESS | KS8721_BMCR, &value))
-		return 0;
-
-	/* remove autonegotiation enable */
-	value &= ~KS8721_AUTONEG;
-	/* Electrically isolate PHY */
-	value |= KS8721_ISOLATE;
-	if (!at91rm9200_EmacWritePhy(p_mac,
-		CONFIG_PHY_ADDRESS | KS8721_BMCR, &value)) {
-		return 0;
-	}
-	/*
-	 * Set the Auto_negotiation Advertisement Register
-	 * MII advertising for Next page, 100BaseTxFD and HD,
-	 * 10BaseTFD and HD, IEEE 802.3
-	 */
-	phyanar = KS8721_NP | KS8721_TX_FDX | KS8721_TX_HDX |
-		  KS8721_10_FDX | KS8721_10_HDX | KS8721_AN_IEEE_802_3;
-	if (!at91rm9200_EmacWritePhy(p_mac,
-		CONFIG_PHY_ADDRESS | KS8721_ANAR, &phyanar)) {
-		return 0;
-	}
-	/* Read the Control Register */
-	if (!at91rm9200_EmacReadPhy(p_mac,
-		CONFIG_PHY_ADDRESS | KS8721_BMCR, &value)) {
-		return 0;
-	}
-	value |= KS8721_SPEED_SELECT | KS8721_AUTONEG | KS8721_DUPLEX_MODE;
-	if (!at91rm9200_EmacWritePhy(p_mac,
-		CONFIG_PHY_ADDRESS | KS8721_BMCR, &value)) {
-		return 0;
-	}
-	/* Restart Auto_negotiation */
-	value |= KS8721_RESTART_AUTONEG;
-	value &= ~KS8721_ISOLATE;
-	if (!at91rm9200_EmacWritePhy(p_mac,
-		CONFIG_PHY_ADDRESS | KS8721_BMCR, &value)) {
-		return 0;
-	}
-	/* Check AutoNegotiate complete */
-	udelay(10000);
-	at91rm9200_EmacReadPhy(p_mac,
-		CONFIG_PHY_ADDRESS | KS8721_BMSR, &value);
-	if (!(value & KS8721_AUTONEG_COMP))
-		return 0;
-
-	/* Get the AutoNeg Link partner base page */
-	if (!at91rm9200_EmacReadPhy(p_mac,
-		CONFIG_PHY_ADDRESS | KS8721_ANLPAR, &phyanalpar)) {
-		return 0;
-	}
-
-	if ((phyanar & KS8721_TX_FDX) && (phyanalpar & KS8721_TX_FDX)) {
-		/* Set MII for 100BaseTX and Full Duplex */
-		p_mac->EMAC_CFG |= AT91C_EMAC_SPD | AT91C_EMAC_FD;
-		return 1;
-	}
-
-	if ((phyanar & KS8721_10_FDX) && (phyanalpar & KS8721_10_FDX)) {
-		/* Set MII for 10BaseT and Full Duplex */
-		p_mac->EMAC_CFG = (p_mac->EMAC_CFG &
-				~(AT91C_EMAC_SPD | AT91C_EMAC_FD))
-				| AT91C_EMAC_FD;
-		return 1;
-	}
-	return 0;
-}
-
-#endif	/* CONFIG_CMD_NET */
-
-#endif	/* CONFIG_DRIVER_ETHER */
diff --git a/arch/arm/cpu/arm920t/at91rm9200/lowlevel_init.S b/arch/arm/cpu/arm920t/at91rm9200/lowlevel_init.S
deleted file mode 100644
index 2e7160f..0000000
--- a/arch/arm/cpu/arm920t/at91rm9200/lowlevel_init.S
+++ /dev/null
@@ -1,169 +0,0 @@
-/*
- * Memory Setup stuff - taken from blob memsetup.S
- *
- * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
- *		       Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
- *
- * Modified for the at91rm9200dk board by
- * (C) Copyright 2004
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <version.h>
-
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
-/*
- * some parameters for the board
- *
- * This is based on rm9200dk.cfg for the BDI2000 from ABATRON which in
- * turn is based on the boot.bin code from ATMEL
- *
- */
-#include <asm/arch/AT91RM9200.h>
-
-_MTEXT_BASE:
-#undef START_FROM_MEM
-#ifdef START_FROM_MEM
-	.word	CONFIG_SYS_TEXT_BASE-PHYS_FLASH_1
-#else
-	.word	CONFIG_SYS_TEXT_BASE
-#endif
-
-.globl lowlevel_init
-lowlevel_init:
-	/* Get the CKGR Base Address */
-	ldr     r1, =AT91C_BASE_CKGR
-	/* Main oscillator Enable register */
-#ifdef CONFIG_SYS_USE_MAIN_OSCILLATOR
-	ldr     r0, =0x0000FF01		/* Enable main oscillator,  OSCOUNT = 0xFF */
-#else
-	ldr     r0, =0x0000FF00		/* Disable main oscillator, OSCOUNT = 0xFF */
-#endif
-	str     r0, [r1, #AT91C_CKGR_MOR]
-	/* Add loop to compensate Main Oscillator startup time */
-	ldr     r0, =0x00000010
-LoopOsc:
-	subs    r0, r0, #1
-	bhi     LoopOsc
-
-	/* memory control configuration */
-	/* this isn't very elegant, but	 what the heck */
-	ldr	r0, =SMRDATA
-	ldr	r1, _MTEXT_BASE
-	sub	r0, r0, r1
-	add	r2, r0, #80
-0:
-	/* the address */
-	ldr	r1, [r0], #4
-	/* the value */
-	ldr	r3, [r0], #4
-	str	r3, [r1]
-	cmp	r2, r0
-	bne	0b
-	/* delay - this is all done by guess */
-	ldr	r0, =0x00010000
-	/* (vs reading PMC_SR for LOCKA, LOCKB ... or MOSCS earlier) */
-1:
-	subs	r0, r0, #1
-	bhi	1b
-	ldr	r0, =SMRDATA1
-	ldr	r1, _MTEXT_BASE
-	sub	r0, r0, r1
-	add	r2, r0, #176
-2:
-	/* the address */
-	ldr	r1, [r0], #4
-	/* the value */
-	ldr	r3, [r0], #4
-	str	r3, [r1]
-	cmp	r2, r0
-	bne	2b
-
-	/* switch from FastBus to Asynchronous clock mode */
-	mrc	p15, 0, r0, c1, c0, 0
-	orr	r0, r0, #0xC0000000	@ set bit 31 (iA) and 30 (nF)
-	mcr	p15, 0, r0, c1, c0, 0
-
-	/* everything is fine now */
-	mov	pc, lr
-
-	.ltorg
-
-SMRDATA:
-	.word AT91C_EBI_CFGR
-	.word CONFIG_SYS_EBI_CFGR_VAL
-	.word AT91C_SMC_CSR0
-	.word CONFIG_SYS_SMC_CSR0_VAL
-	.word AT91C_PLLAR
-	.word CONFIG_SYS_PLLAR_VAL
-	.word AT91C_PLLBR
-	.word CONFIG_SYS_PLLBR_VAL
-	.word AT91C_MCKR
-	.word CONFIG_SYS_MCKR_VAL
-	/* here there's a delay */
-SMRDATA1:
-	.word AT91C_PIOC_ASR
-	.word CONFIG_SYS_PIOC_ASR_VAL
-	.word AT91C_PIOC_BSR
-	.word CONFIG_SYS_PIOC_BSR_VAL
-	.word AT91C_PIOC_PDR
-	.word CONFIG_SYS_PIOC_PDR_VAL
-	.word AT91C_EBI_CSA
-	.word CONFIG_SYS_EBI_CSA_VAL
-	.word AT91C_SDRC_CR
-	.word CONFIG_SYS_SDRC_CR_VAL
-	.word AT91C_SDRC_MR
-	.word CONFIG_SYS_SDRC_MR_VAL
-	.word CONFIG_SYS_SDRAM
-	.word CONFIG_SYS_SDRAM_VAL
-	.word AT91C_SDRC_MR
-	.word CONFIG_SYS_SDRC_MR_VAL1
-	.word CONFIG_SYS_SDRAM
-	.word CONFIG_SYS_SDRAM_VAL
-	.word CONFIG_SYS_SDRAM
-	.word CONFIG_SYS_SDRAM_VAL
-	.word CONFIG_SYS_SDRAM
-	.word CONFIG_SYS_SDRAM_VAL
-	.word CONFIG_SYS_SDRAM
-	.word CONFIG_SYS_SDRAM_VAL
-	.word CONFIG_SYS_SDRAM
-	.word CONFIG_SYS_SDRAM_VAL
-	.word CONFIG_SYS_SDRAM
-	.word CONFIG_SYS_SDRAM_VAL
-	.word CONFIG_SYS_SDRAM
-	.word CONFIG_SYS_SDRAM_VAL
-	.word CONFIG_SYS_SDRAM
-	.word CONFIG_SYS_SDRAM_VAL
-	.word AT91C_SDRC_MR
-	.word CONFIG_SYS_SDRC_MR_VAL2
-	.word CONFIG_SYS_SDRAM1
-	.word CONFIG_SYS_SDRAM_VAL
-	.word AT91C_SDRC_TR
-	.word CONFIG_SYS_SDRC_TR_VAL
-	.word CONFIG_SYS_SDRAM
-	.word CONFIG_SYS_SDRAM_VAL
-	.word AT91C_SDRC_MR
-	.word CONFIG_SYS_SDRC_MR_VAL3
-	.word CONFIG_SYS_SDRAM
-	.word CONFIG_SYS_SDRAM_VAL
-	/* SMRDATA1 is 176 bytes long */
-#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
diff --git a/arch/arm/cpu/arm920t/at91rm9200/lxt972.c b/arch/arm/cpu/arm920t/at91rm9200/lxt972.c
deleted file mode 100644
index f02cfdd..0000000
--- a/arch/arm/cpu/arm920t/at91rm9200/lxt972.c
+++ /dev/null
@@ -1,192 +0,0 @@
-/*
- *
- * (C) Copyright 2003
- * Author : Hamid Ikdoumi (Atmel)
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * Adapted for KwikByte KB920x board: 22APR2005
- */
-
-#include <common.h>
-#include <at91rm9200_net.h>
-#include <net.h>
-#include <miiphy.h>
-#include <lxt971a.h>
-
-#ifdef CONFIG_DRIVER_ETHER
-
-#if defined(CONFIG_CMD_NET)
-
-/*
- * Name:
- *	lxt972_IsPhyConnected
- * Description:
- *	Reads the 2 PHY ID registers
- * Arguments:
- *	p_mac - pointer to AT91S_EMAC struct
- * Return value:
- *	TRUE - if id read successfully
- *	FALSE- if error
- */
-unsigned int lxt972_IsPhyConnected (AT91PS_EMAC p_mac)
-{
-	unsigned short Id1, Id2;
-
-	at91rm9200_EmacEnableMDIO (p_mac);
-	at91rm9200_EmacReadPhy(p_mac, MII_PHYSID1, &Id1);
-	at91rm9200_EmacReadPhy(p_mac, MII_PHYSID2, &Id2);
-	at91rm9200_EmacDisableMDIO (p_mac);
-
-	if ((Id1 == (0x0013)) && ((Id2  & 0xFFF0) == 0x78E0))
-		return TRUE;
-
-	return FALSE;
-}
-
-/*
- * Name:
- *	lxt972_GetLinkSpeed
- * Description:
- *	Link parallel detection status of MAC is checked and set in the
- *	MAC configuration registers
- * Arguments:
- *	p_mac - pointer to MAC
- * Return value:
- *	TRUE - if link status set succesfully
- *	FALSE - if link status not set
- */
-UCHAR lxt972_GetLinkSpeed (AT91PS_EMAC p_mac)
-{
-	unsigned short stat1;
-
-	if (!at91rm9200_EmacReadPhy (p_mac, PHY_LXT971_STAT2, &stat1))
-		return FALSE;
-
-	if (!(stat1 & PHY_LXT971_STAT2_LINK))	/* link status up? */
-		return FALSE;
-
-	if (stat1 & PHY_LXT971_STAT2_100BTX) {
-
-		if (stat1 & PHY_LXT971_STAT2_DUPLEX_MODE) {
-
-			/*set Emac for 100BaseTX and Full Duplex  */
-			p_mac->EMAC_CFG |= AT91C_EMAC_SPD | AT91C_EMAC_FD;
-		} else {
-
-			/*set Emac for 100BaseTX and Half Duplex  */
-			p_mac->EMAC_CFG = (p_mac->EMAC_CFG &
-					~(AT91C_EMAC_SPD | AT91C_EMAC_FD))
-					| AT91C_EMAC_SPD;
-		}
-
-		return TRUE;
-
-	} else {
-
-		if (stat1 & PHY_LXT971_STAT2_DUPLEX_MODE) {
-
-			/*set MII for 10BaseT and Full Duplex  */
-			p_mac->EMAC_CFG = (p_mac->EMAC_CFG &
-					~(AT91C_EMAC_SPD | AT91C_EMAC_FD))
-					| AT91C_EMAC_FD;
-		} else {
-
-			/*set MII for 10BaseT and Half Duplex  */
-			p_mac->EMAC_CFG &= ~(AT91C_EMAC_SPD | AT91C_EMAC_FD);
-		}
-
-		return TRUE;
-	}
-
-	return FALSE;
-}
-
-
-/*
- * Name:
- *	lxt972_InitPhy
- * Description:
- *	MAC starts checking its link by using parallel detection and
- *	Autonegotiation and the same is set in the MAC configuration registers
- * Arguments:
- *	p_mac - pointer to struct AT91S_EMAC
- * Return value:
- *	TRUE - if link status set succesfully
- *	FALSE - if link status not set
- */
-UCHAR lxt972_InitPhy (AT91PS_EMAC p_mac)
-{
-	UCHAR ret = TRUE;
-
-	at91rm9200_EmacEnableMDIO (p_mac);
-
-	if (!lxt972_GetLinkSpeed (p_mac)) {
-		/* Try another time */
-		ret = lxt972_GetLinkSpeed (p_mac);
-	}
-
-	/* Disable PHY Interrupts */
-	at91rm9200_EmacWritePhy (p_mac, PHY_LXT971_INT_ENABLE, 0);
-
-	at91rm9200_EmacDisableMDIO (p_mac);
-
-	return (ret);
-}
-
-
-/*
- * Name:
- *	lxt972_AutoNegotiate
- * Description:
- *	MAC Autonegotiates with the partner status of same is set in the
- *	MAC configuration registers
- * Arguments:
- *	dev - pointer to struct net_device
- * Return value:
- *	TRUE - if link status set successfully
- *	FALSE - if link status not set
- */
-UCHAR lxt972_AutoNegotiate (AT91PS_EMAC p_mac, int *status)
-{
-	unsigned short value;
-
-	/* Set lxt972 control register */
-	if (!at91rm9200_EmacReadPhy (p_mac, MII_BMCR, &value))
-		return FALSE;
-
-	/* Restart Auto_negotiation  */
-	value |= BMCR_ANRESTART;
-	if (!at91rm9200_EmacWritePhy (p_mac, MII_BMCR, &value))
-		return FALSE;
-
-	/*check AutoNegotiate complete */
-	udelay (10000);
-	at91rm9200_EmacReadPhy(p_mac, MII_BMSR, &value);
-	if (!(value & BMSR_ANEGCOMPLETE))
-		return FALSE;
-
-	return (lxt972_GetLinkSpeed (p_mac));
-}
-
-#endif
-
-#endif	/* CONFIG_DRIVER_ETHER */
diff --git a/arch/arm/cpu/arm920t/at91rm9200/reset.c b/arch/arm/cpu/arm920t/at91rm9200/reset.c
deleted file mode 100644
index 945ea2c..0000000
--- a/arch/arm/cpu/arm920t/at91rm9200/reset.c
+++ /dev/null
@@ -1,71 +0,0 @@
-/*
- * (C) Copyright 2002
- * Lineo, Inc. <www.lineo.com>
- * Bernhard Kuhn <bkuhn@lineo.com>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Alex Zuepke <azu@sysgo.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/arch/hardware.h>
-
-void board_reset(void) __attribute__((__weak__));
-
-/*
- * Reset the cpu by setting up the watchdog timer and let him time out
- * or toggle a GPIO pin on the AT91RM9200DK board
- */
-void reset_cpu (ulong ignored)
-{
-
-#if defined(CONFIG_AT91RM9200_USART)
-	/*shutdown the console to avoid strange chars during reset */
-	serial_exit();
-#endif
-
-	if (board_reset)
-		board_reset();
-
-	/* this is the way Linux does it */
-
-	/* FIXME:
-	 * These defines should be moved into
-	 * include/asm-arm/arch-at91rm9200/AT91RM9200.h
-	 * as soon as the whitespace fix gets applied.
-	 */
-	#define AT91C_ST_RSTEN (0x1 << 16)
-	#define AT91C_ST_EXTEN (0x1 << 17)
-	#define AT91C_ST_WDRST (0x1 <<  0)
-	#define ST_WDMR *((unsigned long *)0xfffffd08)	/* watchdog mode register */
-	#define ST_CR *((unsigned long *)0xfffffd00)	/* system clock control register */
-
-	ST_WDMR = AT91C_ST_RSTEN | AT91C_ST_EXTEN | 1 ;
-	ST_CR = AT91C_ST_WDRST;
-
-	while (1);
-	/* Never reached */
-}
diff --git a/arch/arm/cpu/arm920t/at91rm9200/spi.c b/arch/arm/cpu/arm920t/at91rm9200/spi.c
deleted file mode 100644
index f3cb5d8..0000000
--- a/arch/arm/cpu/arm920t/at91rm9200/spi.c
+++ /dev/null
@@ -1,151 +0,0 @@
-/* Driver for ATMEL DataFlash support
- * Author : Hamid Ikdoumi (Atmel)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- */
-
-#include <config.h>
-#include <common.h>
-#include <asm/hardware.h>
-
-#ifdef CONFIG_HAS_DATAFLASH
-#include <dataflash.h>
-
-#define AT91C_SPI_CLK	10000000	/* Max Value = 10MHz to be compliant to
-					the Continuous Array Read function */
-
-/* AC Characteristics */
-/* DLYBS = tCSS = 250ns min and DLYBCT = tCSH = 250ns */
-#define DATAFLASH_TCSS	(0xC << 16)
-#define DATAFLASH_TCHS	(0x1 << 24)
-
-#define AT91C_TIMEOUT_WRDY		200000
-#define AT91C_SPI_PCS0_SERIAL_DATAFLASH	0xE	/* Chip Select 0: NPCS0%1110 */
-#define AT91C_SPI_PCS3_DATAFLASH_CARD	0x7	/* Chip Select 3: NPCS3%0111 */
-
-/*-------------------------------------------------------------------*/
-/*	SPI DataFlash Init					     */
-/*-------------------------------------------------------------------*/
-void AT91F_SpiInit(void)
-{
-	/* Configure PIOs */
-	AT91C_BASE_PIOA->PIO_ASR =
-		AT91C_PA3_NPCS0 | AT91C_PA4_NPCS1 | AT91C_PA1_MOSI |
-		AT91C_PA5_NPCS2 | AT91C_PA6_NPCS3 | AT91C_PA0_MISO |
-		AT91C_PA2_SPCK;
-	AT91C_BASE_PIOA->PIO_PDR =
-		AT91C_PA3_NPCS0 | AT91C_PA4_NPCS1 | AT91C_PA1_MOSI |
-		AT91C_PA5_NPCS2 | AT91C_PA6_NPCS3 | AT91C_PA0_MISO |
-		AT91C_PA2_SPCK;
-	/* Enable CLock */
-	AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_SPI;
-
-	/* Reset the SPI */
-	AT91C_BASE_SPI->SPI_CR = AT91C_SPI_SWRST;
-
-	/* Configure SPI in Master Mode with No CS selected !!! */
-	AT91C_BASE_SPI->SPI_MR =
-		AT91C_SPI_MSTR | AT91C_SPI_MODFDIS | AT91C_SPI_PCS;
-
-	/* Configure CS0 and CS3 */
-	*(AT91C_SPI_CSR + 0) =
-		AT91C_SPI_CPOL | (AT91C_SPI_DLYBS & DATAFLASH_TCSS) |
-		(AT91C_SPI_DLYBCT & DATAFLASH_TCHS) |
-		((AT91C_MASTER_CLOCK / (2*AT91C_SPI_CLK)) << 8);
-
-	*(AT91C_SPI_CSR + 3) =
-		AT91C_SPI_CPOL | (AT91C_SPI_DLYBS & DATAFLASH_TCSS) |
-		(AT91C_SPI_DLYBCT & DATAFLASH_TCHS) |
-		((AT91C_MASTER_CLOCK / (2*AT91C_SPI_CLK)) << 8);
-}
-
-void AT91F_SpiEnable(int cs)
-{
-	switch(cs) {
-	case 0:	/* Configure SPI CS0 for Serial DataFlash AT45DBxx */
-		AT91C_BASE_SPI->SPI_MR &= 0xFFF0FFFF;
-		AT91C_BASE_SPI->SPI_MR |=
-			((AT91C_SPI_PCS0_SERIAL_DATAFLASH<<16) &
-				AT91C_SPI_PCS);
-		break;
-	case 3:	/* Configure SPI CS3 for Serial DataFlash Card */
-		/* Set up PIO SDC_TYPE to switch on DataFlash Card */
-		/* and not MMC/SDCard */
-		AT91C_BASE_PIOB->PIO_PER =
-			AT91C_PIO_PB7;	/* Set in PIO mode */
-		AT91C_BASE_PIOB->PIO_OER =
-			AT91C_PIO_PB7;	/* Configure in output */
-		/* Clear Output */
-		AT91C_BASE_PIOB->PIO_CODR = AT91C_PIO_PB7;
-		/* Configure PCS */
-		AT91C_BASE_SPI->SPI_MR &= 0xFFF0FFFF;
-		AT91C_BASE_SPI->SPI_MR |=
-			((AT91C_SPI_PCS3_DATAFLASH_CARD<<16) & AT91C_SPI_PCS);
-		break;
-	}
-
-	/* SPI_Enable */
-	AT91C_BASE_SPI->SPI_CR = AT91C_SPI_SPIEN; }
-
-/*---------------------------------------------------------------------------*/
-/* \fn    AT91F_SpiWrite						     */
-/* \brief Set the PDC registers for a transfert				     */
-/*---------------------------------------------------------------------------*/
-unsigned int AT91F_SpiWrite ( AT91PS_DataflashDesc pDesc )
-{
-	unsigned int timeout;
-
-	pDesc->state = BUSY;
-
-	AT91C_BASE_SPI->SPI_PTCR = AT91C_PDC_TXTDIS + AT91C_PDC_RXTDIS;
-
-	/* Initialize the Transmit and Receive Pointer */
-	AT91C_BASE_SPI->SPI_RPR = (unsigned int)pDesc->rx_cmd_pt ;
-	AT91C_BASE_SPI->SPI_TPR = (unsigned int)pDesc->tx_cmd_pt ;
-
-	/* Intialize the Transmit and Receive Counters */
-	AT91C_BASE_SPI->SPI_RCR = pDesc->rx_cmd_size;
-	AT91C_BASE_SPI->SPI_TCR = pDesc->tx_cmd_size;
-
-	if ( pDesc->tx_data_size != 0 ) {
-		/* Initialize the Next Transmit and Next Receive Pointer */
-		AT91C_BASE_SPI->SPI_RNPR = (unsigned int)pDesc->rx_data_pt ;
-		AT91C_BASE_SPI->SPI_TNPR = (unsigned int)pDesc->tx_data_pt ;
-
-		/* Intialize the Next Transmit and Next Receive Counters */
-		AT91C_BASE_SPI->SPI_RNCR = pDesc->rx_data_size ;
-		AT91C_BASE_SPI->SPI_TNCR = pDesc->tx_data_size ;
-	}
-
-	/* arm simple, non interrupt dependent timer */
-	reset_timer_masked();
-	timeout = 0;
-
-	AT91C_BASE_SPI->SPI_PTCR = AT91C_PDC_TXTEN + AT91C_PDC_RXTEN;
-	while(!(AT91C_BASE_SPI->SPI_SR & AT91C_SPI_RXBUFF) &&
-		((timeout = get_timer_masked() ) < CONFIG_SYS_SPI_WRITE_TOUT));
-	AT91C_BASE_SPI->SPI_PTCR = AT91C_PDC_TXTDIS + AT91C_PDC_RXTDIS;
-	pDesc->state = IDLE;
-
-	if (timeout >= CONFIG_SYS_SPI_WRITE_TOUT){
-		printf("Error Timeout\n\r");
-		return DATAFLASH_ERROR;
-	}
-
-	return DATAFLASH_OK;
-}
-#endif
diff --git a/arch/arm/cpu/arm920t/at91rm9200/timer.c b/arch/arm/cpu/arm920t/at91rm9200/timer.c
deleted file mode 100644
index 9c54bbe..0000000
--- a/arch/arm/cpu/arm920t/at91rm9200/timer.c
+++ /dev/null
@@ -1,160 +0,0 @@
-/*
- * (C) Copyright 2002
- * Lineo, Inc. <www.lineo.com>
- * Bernhard Kuhn <bkuhn@lineo.com>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Alex Zuepke <azu@sysgo.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-/*#include <asm/io.h>*/
-#include <asm/arch/hardware.h>
-/*#include <asm/proc/ptrace.h>*/
-
-/* the number of clocks per CONFIG_SYS_HZ */
-#define TIMER_LOAD_VAL (CONFIG_SYS_HZ_CLOCK/CONFIG_SYS_HZ)
-
-/* macro to read the 16 bit timer */
-#define READ_TIMER (tmr->TC_CV & 0x0000ffff)
-AT91PS_TC tmr;
-
-static ulong timestamp;
-static ulong lastinc;
-
-int timer_init (void)
-{
-	tmr = AT91C_BASE_TC0;
-
-	/* enables TC1.0 clock */
-	*AT91C_PMC_PCER = 1 << AT91C_ID_TC0;  /* enable clock */
-
-	*AT91C_TCB0_BCR = 0;
-	*AT91C_TCB0_BMR = AT91C_TCB_TC0XC0S_NONE | AT91C_TCB_TC1XC1S_NONE | AT91C_TCB_TC2XC2S_NONE;
-	tmr->TC_CCR = AT91C_TC_CLKDIS;
-#define AT91C_TC_CMR_CPCTRG (1 << 14)
-	/* set to MCLK/2 and restart the timer when the vlaue in TC_RC is reached */
-	tmr->TC_CMR = AT91C_TC_TIMER_DIV1_CLOCK | AT91C_TC_CMR_CPCTRG;
-
-	tmr->TC_IDR = ~0ul;
-	tmr->TC_RC = TIMER_LOAD_VAL;
-	lastinc = 0;
-	tmr->TC_CCR = AT91C_TC_SWTRG | AT91C_TC_CLKEN;
-	timestamp = 0;
-
-	return (0);
-}
-
-/*
- * timer without interrupts
- */
-
-void reset_timer (void)
-{
-	reset_timer_masked ();
-}
-
-ulong get_timer (ulong base)
-{
-	return get_timer_masked () - base;
-}
-
-void set_timer (ulong t)
-{
-	timestamp = t;
-}
-
-void __udelay (unsigned long usec)
-{
-	udelay_masked(usec);
-}
-
-void reset_timer_masked (void)
-{
-	/* reset time */
-	lastinc = READ_TIMER;
-	timestamp = 0;
-}
-
-ulong get_timer_raw (void)
-{
-	ulong now = READ_TIMER;
-
-	if (now >= lastinc) {
-		/* normal mode */
-		timestamp += now - lastinc;
-	} else {
-		/* we have an overflow ... */
-		timestamp += now + TIMER_LOAD_VAL - lastinc;
-	}
-	lastinc = now;
-
-	return timestamp;
-}
-
-ulong get_timer_masked (void)
-{
-	return get_timer_raw()/TIMER_LOAD_VAL;
-}
-
-void udelay_masked (unsigned long usec)
-{
-	ulong tmo;
-	ulong endtime;
-	signed long diff;
-
-	tmo = CONFIG_SYS_HZ_CLOCK / 1000;
-	tmo *= usec;
-	tmo /= 1000;
-
-	endtime = get_timer_raw () + tmo;
-
-	do {
-		ulong now = get_timer_raw ();
-		diff = endtime - now;
-	} while (diff >= 0);
-}
-
-/*
- * This function is derived from PowerPC code (read timebase as long long).
- * On ARM it just returns the timer value.
- */
-unsigned long long get_ticks(void)
-{
-	return get_timer(0);
-}
-
-/*
- * This function is derived from PowerPC code (timebase clock frequency).
- * On ARM it returns the number of timer ticks per second.
- */
-ulong get_tbclk (void)
-{
-	ulong tbclk;
-
-	tbclk = CONFIG_SYS_HZ;
-	return tbclk;
-}
diff --git a/arch/arm/cpu/arm920t/at91rm9200/usb.c b/arch/arm/cpu/arm920t/at91rm9200/usb.c
deleted file mode 100644
index 72355dc..0000000
--- a/arch/arm/cpu/arm920t/at91rm9200/usb.c
+++ /dev/null
@@ -1,53 +0,0 @@
-/*
- * (C) Copyright 2006
- * DENX Software Engineering <mk@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-
-#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT)
-# ifdef CONFIG_AT91RM9200
-
-#include <asm/arch/hardware.h>
-
-int usb_cpu_init(void)
-{
-	/* Enable USB host clock. */
-	*AT91C_PMC_SCER = AT91C_PMC_UHP;	/* 48MHz clock enabled for UHP */
-	*AT91C_PMC_PCER = 1 << AT91C_ID_UHP;	/* Peripheral Clock Enable Register */
-	return 0;
-}
-
-int usb_cpu_stop(void)
-{
-	/* Initialization failed */
-	*AT91C_PMC_PCDR = 1 << AT91C_ID_UHP;	/* Peripheral Clock Disable Register */
-	*AT91C_PMC_SCDR = AT91C_PMC_UHP;	/* 48MHz clock disabled for UHP */
-	return 0;
-}
-
-int usb_cpu_init_fail(void)
-{
-	return usb_cpu_stop();
-}
-
-# endif /* CONFIG_AT91RM9200 */
-#endif /* defined(CONFIG_USB_OHCI) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT) */
diff --git a/arch/arm/cpu/arm920t/config.mk b/arch/arm/cpu/arm920t/config.mk
deleted file mode 100644
index 8f6c1a3..0000000
--- a/arch/arm/cpu/arm920t/config.mk
+++ /dev/null
@@ -1,32 +0,0 @@
-#
-# (C) Copyright 2002
-# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float
-
-PLATFORM_CPPFLAGS += -march=armv4
-# =========================================================================
-#
-# Supply options according to compiler version
-#
-# =========================================================================
-PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))
diff --git a/arch/arm/cpu/arm920t/cpu.c b/arch/arm/cpu/arm920t/cpu.c
deleted file mode 100644
index be82c87..0000000
--- a/arch/arm/cpu/arm920t/cpu.c
+++ /dev/null
@@ -1,68 +0,0 @@
-/*
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * CPU specific code
- */
-
-#include <common.h>
-#include <command.h>
-#include <asm/system.h>
-
-#ifdef CONFIG_AT91_LEGACY
-#warning Your board is using legacy AT91RM9200 SoC access. Please update!
-#endif
-
-static void cache_flush(void);
-
-int cleanup_before_linux (void)
-{
-	/*
-	 * this function is called just before we call linux
-	 * it prepares the processor for linux
-	 *
-	 * we turn off caches etc ...
-	 */
-
-	disable_interrupts ();
-
-	/* turn off I/D-cache */
-	icache_disable();
-	dcache_disable();
-	/* flush I/D-cache */
-	cache_flush();
-
-	return 0;
-}
-
-/* flush I/D-cache */
-static void cache_flush (void)
-{
-	unsigned long i = 0;
-
-	asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i));
-}
diff --git a/arch/arm/cpu/arm920t/ep93xx/Makefile b/arch/arm/cpu/arm920t/ep93xx/Makefile
deleted file mode 100644
index 1d6a538..0000000
--- a/arch/arm/cpu/arm920t/ep93xx/Makefile
+++ /dev/null
@@ -1,55 +0,0 @@
-#
-# Cirrus Logic EP93xx CPU-specific Makefile
-#
-# Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
-#
-# Copyright (C) 2004, 2005
-# Cory T. Tusar, Videon Central, Inc., <ctusar@videon-central.com>
-#
-# Copyright (C) 2006
-# Dominic Rath <Dominic.Rath@gmx.de>
-#
-# Based on an original Makefile, which is
-#
-# (C) Copyright 2000, 2001, 2002
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this project.
-#
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; either version 2 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful, but
-# WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
-# or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
-# for more details.
-#
-# You should have received a copy of the GNU General Public License along
-# with this program; if not, write to the Free Software Foundation, Inc.,
-# 675 Mass Ave, Cambridge, MA 02139, USA.
-#
-include $(TOPDIR)/config.mk
-
-LIB = $(obj)lib$(SOC).o
-
-COBJS   = cpu.o led.o speed.o timer.o
-SOBJS   = lowlevel_init.o
-
-SRCS    := $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS    := $(addprefix $(obj),$(SOBJS) $(COBJS))
-
-all:    $(obj).depend $(LIB)
-
-$(LIB): $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/arch/arm/cpu/arm920t/ep93xx/cpu.c b/arch/arm/cpu/arm920t/ep93xx/cpu.c
deleted file mode 100644
index 1abb9c6..0000000
--- a/arch/arm/cpu/arm920t/ep93xx/cpu.c
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * Cirrus Logic EP93xx CPU-specific support.
- *
- * Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
- *
- * Copyright (C) 2004, 2005
- * Cory T. Tusar, Videon Central, Inc., <ctusar@videon-central.com>
- *
- * See file CREDITS for list of people who contributed to this project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
- * or FITNESS FOR A PARTICULAR PURPOSE.	See the GNU General Public License
- * for more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#include <common.h>
-#include <asm/arch/ep93xx.h>
-#include <asm/io.h>
-
-/* We reset the CPU by generating a 1-->0 transition on DeviceCfg bit 31. */
-extern void reset_cpu(ulong addr)
-{
-	struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
-	uint32_t value;
-
-	/* Unlock DeviceCfg and set SWRST */
-	writel(0xAA, &syscon->sysswlock);
-	value = readl(&syscon->devicecfg);
-	value |= SYSCON_DEVICECFG_SWRST;
-	writel(value, &syscon->devicecfg);
-
-	/* Unlock DeviceCfg and clear SWRST */
-	writel(0xAA, &syscon->sysswlock);
-	value = readl(&syscon->devicecfg);
-	value &= ~SYSCON_DEVICECFG_SWRST;
-	writel(value, &syscon->devicecfg);
-
-	/* Dying... */
-	while (1)
-		; /* noop */
-}
diff --git a/arch/arm/cpu/arm920t/ep93xx/led.c b/arch/arm/cpu/arm920t/ep93xx/led.c
deleted file mode 100644
index 7e2c897..0000000
--- a/arch/arm/cpu/arm920t/ep93xx/led.c
+++ /dev/null
@@ -1,101 +0,0 @@
-/*
- * Copyright (C) 2010, 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <asm/io.h>
-#include <asm/arch/ep93xx.h>
-#include <config.h>
-#include <status_led.h>
-
-static uint8_t saved_state[2] = {STATUS_LED_OFF, STATUS_LED_OFF};
-static uint32_t gpio_pin[2] = {1 << STATUS_LED_GREEN,
-			       1 << STATUS_LED_RED};
-
-inline void switch_LED_on(uint8_t led)
-{
-	register struct gpio_regs *gpio = (struct gpio_regs *)GPIO_BASE;
-
-	writel(readl(&gpio->pedr) | gpio_pin[led], &gpio->pedr);
-	saved_state[led] = STATUS_LED_ON;
-}
-
-inline void switch_LED_off(uint8_t led)
-{
-	register struct gpio_regs *gpio = (struct gpio_regs *)GPIO_BASE;
-
-	writel(readl(&gpio->pedr) & ~gpio_pin[led], &gpio->pedr);
-	saved_state[led] = STATUS_LED_OFF;
-}
-
-void red_LED_on(void)
-{
-	switch_LED_on(STATUS_LED_RED);
-}
-
-void red_LED_off(void)
-{
-	switch_LED_off(STATUS_LED_RED);
-}
-
-void green_LED_on(void)
-{
-	switch_LED_on(STATUS_LED_GREEN);
-}
-
-void green_LED_off(void)
-{
-	switch_LED_off(STATUS_LED_GREEN);
-}
-
-void __led_init(led_id_t mask, int state)
-{
-	__led_set(mask, state);
-}
-
-void __led_toggle(led_id_t mask)
-{
-	if (STATUS_LED_RED == mask) {
-		if (STATUS_LED_ON == saved_state[STATUS_LED_RED])
-			red_LED_off();
-		else
-			red_LED_on();
-	} else if (STATUS_LED_GREEN == mask) {
-		if (STATUS_LED_ON == saved_state[STATUS_LED_GREEN])
-			green_LED_off();
-		else
-			green_LED_on();
-	}
-}
-
-void __led_set(led_id_t mask, int state)
-{
-	if (STATUS_LED_RED == mask) {
-		if (STATUS_LED_ON == state)
-			red_LED_on();
-		else
-			red_LED_off();
-	} else if (STATUS_LED_GREEN == mask) {
-		if (STATUS_LED_ON == state)
-			green_LED_on();
-		else
-			green_LED_off();
-	}
-}
diff --git a/arch/arm/cpu/arm920t/ep93xx/lowlevel_init.S b/arch/arm/cpu/arm920t/ep93xx/lowlevel_init.S
deleted file mode 100644
index a20ec89..0000000
--- a/arch/arm/cpu/arm920t/ep93xx/lowlevel_init.S
+++ /dev/null
@@ -1,65 +0,0 @@
-/*
- * Low-level initialization for EP93xx
- *
- * Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
- *
- * Copyright (C) 2006 Dominic Rath <Dominic.Rath@gmx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <version.h>
-#include <asm/arch/ep93xx.h>
-
-.globl lowlevel_init
-lowlevel_init:
-	/* backup return address */
-	ldr r1, =SYSCON_SCRATCH0
-	str lr, [r1]
-
-	/* Turn on both LEDs */
-	bl red_LED_on
-	bl green_LED_on
-
-	/* Configure flash wait states before we switch to the PLL */
-	bl flash_cfg
-
-	/* Set up PLL */
-	bl pll_cfg
-
-	/* Turn off the Green LED and leave the Red LED on */
-	bl green_LED_off
-
-	/* Setup SDRAM */
-	bl sdram_cfg
-
-	/* Turn on Green LED, Turn off the Red LED */
-	bl green_LED_on
-	bl red_LED_off
-
-	/* FIXME: we use async mode for now */
-	mrc p15, 0, r0, c1, c0, 0
-	orr r0, r0, #0xc0000000
-	mcr p15, 0, r0, c1, c0, 0
-
-	/* restore return address */
-	ldr r1, =SYSCON_SCRATCH0
-	ldr lr, [r1]
-
-	mov pc, lr
diff --git a/arch/arm/cpu/arm920t/ep93xx/speed.c b/arch/arm/cpu/arm920t/ep93xx/speed.c
deleted file mode 100644
index c83a3bb..0000000
--- a/arch/arm/cpu/arm920t/ep93xx/speed.c
+++ /dev/null
@@ -1,110 +0,0 @@
-/*
- * Cirrus Logic EP93xx PLL support.
- *
- * Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
- *
- * See file CREDITS for list of people who contributed to this project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
- * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
- * for more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#include <common.h>
-#include <asm/arch/ep93xx.h>
-#include <asm/io.h>
-#include <div64.h>
-
-/*
- * CONFIG_SYS_CLK_FREQ should be defined as the input frequency of the PLL.
- *
- * get_FCLK(), get_HCLK(), get_PCLK() and get_UCLK() return the clock of
- * the specified bus in HZ.
- */
-
-/*
- * return the PLL output frequency
- *
- * PLL rate = CONFIG_SYS_CLK_FREQ * (X1FBD + 1) * (X2FBD + 1)
- * / (X2IPD + 1) / 2^PS
- */
-static ulong get_PLLCLK(uint32_t *pllreg)
-{
-	uint8_t i;
-	const uint32_t clkset = readl(pllreg);
-	uint64_t rate = CONFIG_SYS_CLK_FREQ;
-	rate *= ((clkset >> SYSCON_CLKSET_PLL_X1FBD1_SHIFT) & 0x1f) + 1;
-	rate *= ((clkset >> SYSCON_CLKSET_PLL_X2FBD2_SHIFT) & 0x3f) + 1;
-	do_div(rate, (clkset  & 0x1f) + 1);			/* X2IPD */
-	for (i = 0; i < ((clkset >> SYSCON_CLKSET_PLL_PS_SHIFT) & 3); i++)
-		rate >>= 1;
-
-	return (ulong)rate;
-}
-
-/* return FCLK frequency */
-ulong get_FCLK()
-{
-	const uint8_t fclk_divisors[] = { 1, 2, 4, 8, 16, 1, 1, 1 };
-	struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
-
-	const uint32_t clkset1 = readl(&syscon->clkset1);
-	const uint8_t fclk_div =
-		fclk_divisors[(clkset1 >> SYSCON_CLKSET1_FCLK_DIV_SHIFT) & 7];
-	const ulong fclk_rate = get_PLLCLK(&syscon->clkset1) / fclk_div;
-
-	return fclk_rate;
-}
-
-/* return HCLK frequency */
-ulong get_HCLK(void)
-{
-	const uint8_t hclk_divisors[] = { 1, 2, 4, 5, 6, 8, 16, 32 };
-	struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
-
-	const uint32_t clkset1 = readl(&syscon->clkset1);
-	const uint8_t hclk_div =
-		hclk_divisors[(clkset1 >> SYSCON_CLKSET1_HCLK_DIV_SHIFT) & 7];
-	const ulong hclk_rate = get_PLLCLK(&syscon->clkset1) / hclk_div;
-
-	return hclk_rate;
-}
-
-/* return PCLK frequency */
-ulong get_PCLK(void)
-{
-	const uint8_t pclk_divisors[] = { 1, 2, 4, 8 };
-	struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
-
-	const uint32_t clkset1 = readl(&syscon->clkset1);
-	const uint8_t pclk_div =
-		pclk_divisors[(clkset1 >> SYSCON_CLKSET1_PCLK_DIV_SHIFT) & 3];
-	const ulong pclk_rate = get_HCLK() / pclk_div;
-
-	return pclk_rate;
-}
-
-/* return UCLK frequency */
-ulong get_UCLK(void)
-{
-	struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
-	ulong uclk_rate;
-
-	const uint32_t value = readl(&syscon->pwrcnt);
-	if (value & SYSCON_PWRCNT_UART_BAUD)
-		uclk_rate = CONFIG_SYS_CLK_FREQ;
-	else
-		uclk_rate = CONFIG_SYS_CLK_FREQ / 2;
-
-	return uclk_rate;
-}
diff --git a/arch/arm/cpu/arm920t/ep93xx/timer.c b/arch/arm/cpu/arm920t/ep93xx/timer.c
deleted file mode 100644
index 4a0ce4d..0000000
--- a/arch/arm/cpu/arm920t/ep93xx/timer.c
+++ /dev/null
@@ -1,143 +0,0 @@
-/*
- * Cirrus Logic EP93xx timer support.
- *
- * Copyright (C) 2009, 2010 Matthias Kaehlcke <matthias@kaehlcke.net>
- *
- * Copyright (C) 2004, 2005
- * Cory T. Tusar, Videon Central, Inc., <ctusar@videon-central.com>
- *
- * Based on the original intr.c Cirrus Logic EP93xx Rev D. interrupt support,
- * author unknown.
- *
- * See file CREDITS for list of people who contributed to this project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
- * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
- * for more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#include <common.h>
-#include <linux/types.h>
-#include <asm/arch/ep93xx.h>
-#include <asm/io.h>
-#include <div64.h>
-
-#define TIMER_CLKSEL	(1 << 3)
-#define TIMER_ENABLE	(1 << 7)
-
-#define TIMER_FREQ			508469		/* ticks / second */
-#define TIMER_MAX_VAL			0xFFFFFFFF
-
-static struct ep93xx_timer
-{
-	unsigned long long ticks;
-	unsigned long last_read;
-} timer;
-
-static inline unsigned long long usecs_to_ticks(unsigned long usecs)
-{
-	unsigned long long ticks = (unsigned long long)usecs * TIMER_FREQ;
-	do_div(ticks, 1000 * 1000);
-
-	return ticks;
-}
-
-static inline void read_timer(void)
-{
-	struct timer_regs *timer_regs = (struct timer_regs *)TIMER_BASE;
-	const unsigned long now = TIMER_MAX_VAL - readl(&timer_regs->timer3.value);
-
-	if (now >= timer.last_read)
-		timer.ticks += now - timer.last_read;
-	else
-		/* an overflow occurred */
-		timer.ticks += TIMER_MAX_VAL - timer.last_read + now;
-
-	timer.last_read = now;
-}
-
-/*
- * Get the number of ticks (in CONFIG_SYS_HZ resolution)
- */
-unsigned long long get_ticks(void)
-{
-	unsigned long long sys_ticks;
-
-	read_timer();
-
-	sys_ticks = timer.ticks * CONFIG_SYS_HZ;
-	do_div(sys_ticks, TIMER_FREQ);
-
-	return sys_ticks;
-}
-
-unsigned long get_timer_masked(void)
-{
-	return get_ticks();
-}
-
-unsigned long get_timer(unsigned long base)
-{
-	return get_timer_masked() - base;
-}
-
-void reset_timer_masked(void)
-{
-	read_timer();
-	timer.ticks = 0;
-}
-
-void reset_timer(void)
-{
-	reset_timer_masked();
-}
-
-void __udelay(unsigned long usec)
-{
-	unsigned long long target;
-
-	read_timer();
-
-	target = timer.ticks + usecs_to_ticks(usec);
-
-	while (timer.ticks < target)
-		read_timer();
-}
-
-int timer_init(void)
-{
-	struct timer_regs *timer_regs = (struct timer_regs *)TIMER_BASE;
-
-	/* use timer 3 with 508KHz and free running, not enabled now */
-	writel(TIMER_CLKSEL, &timer_regs->timer3.control);
-
-	/* set initial timer value */
-	writel(TIMER_MAX_VAL, &timer_regs->timer3.load);
-
-	/* Enable the timer */
-	writel(TIMER_ENABLE | TIMER_CLKSEL,
-		&timer_regs->timer3.control);
-
-	reset_timer_masked();
-
-	return 0;
-}
-
-/*
- * This function is derived from PowerPC code (timebase clock frequency).
- * On ARM it returns the number of timer ticks per second.
- */
-unsigned long get_tbclk(void)
-{
-	return CONFIG_SYS_HZ;
-}
diff --git a/arch/arm/cpu/arm920t/ep93xx/u-boot.lds b/arch/arm/cpu/arm920t/ep93xx/u-boot.lds
deleted file mode 100644
index 5bfcb02..0000000
--- a/arch/arm/cpu/arm920t/ep93xx/u-boot.lds
+++ /dev/null
@@ -1,59 +0,0 @@
-/*
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-ENTRY(_start)
-SECTIONS
-{
-	. = 0x00000000;
-
-	. = ALIGN(4);
-	.text      :
-	{
-	  arch/arm/cpu/arm920t/start.o	(.text)
-		/* the EP93xx expects to find the pattern 'CRUS' at 0x1000 */
-	  . = 0x1000;
-	  LONG(0x53555243)
-	  *(.text)
-	}
-
-	. = ALIGN(4);
-	.rodata : { *(.rodata) }
-
-	. = ALIGN(4);
-	.data : { *(.data) }
-
-	. = ALIGN(4);
-	.got : { *(.got) }
-
-	. = .;
-	__u_boot_cmd_start = .;
-	.u_boot_cmd : { *(.u_boot_cmd) }
-	__u_boot_cmd_end = .;
-
-	. = ALIGN(4);
-	__bss_start = .;
-	.bss : { *(.bss) }
-	_end = .;
-}
diff --git a/arch/arm/cpu/arm920t/imx/Makefile b/arch/arm/cpu/arm920t/imx/Makefile
deleted file mode 100644
index 32b41b3..0000000
--- a/arch/arm/cpu/arm920t/imx/Makefile
+++ /dev/null
@@ -1,47 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(SOC).o
-
-COBJS	+= generic.o
-COBJS	+= speed.o
-COBJS	+= timer.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
-
-all:	$(obj).depend $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/arch/arm/cpu/arm920t/imx/generic.c b/arch/arm/cpu/arm920t/imx/generic.c
deleted file mode 100644
index aa7c8c1..0000000
--- a/arch/arm/cpu/arm920t/imx/generic.c
+++ /dev/null
@@ -1,90 +0,0 @@
-/*
- *  arch/arm/mach-imx/generic.c
- *
- *  author: Sascha Hauer
- *  Created: april 20th, 2004
- *  Copyright: Synertronixx GmbH
- *
- *  Common code for i.MX machines
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- *
- */
-
-#include <common.h>
-
-#ifdef CONFIG_IMX
-
-#include <asm/arch/imx-regs.h>
-
-void imx_gpio_mode(int gpio_mode)
-{
-	unsigned int pin = gpio_mode & GPIO_PIN_MASK;
-	unsigned int port = (gpio_mode & GPIO_PORT_MASK) >> 5;
-	unsigned int ocr = (gpio_mode & GPIO_OCR_MASK) >> 10;
-	unsigned int tmp;
-
-	/* Pullup enable */
-	if(gpio_mode & GPIO_PUEN)
-		PUEN(port) |= (1<<pin);
-	else
-		PUEN(port) &= ~(1<<pin);
-
-	/* Data direction */
-	if(gpio_mode & GPIO_OUT)
-		DDIR(port) |= 1<<pin;
-	else
-		DDIR(port) &= ~(1<<pin);
-
-	/* Primary / alternate function */
-	if(gpio_mode & GPIO_AF)
-		GPR(port) |= (1<<pin);
-	else
-		GPR(port) &= ~(1<<pin);
-
-	/* use as gpio? */
-	if( ocr == 3 )
-		GIUS(port) |= (1<<pin);
-	else
-		GIUS(port) &= ~(1<<pin);
-
-	/* Output / input configuration */
-	/* FIXME: I'm not very sure about OCR and ICONF, someone
-	 * should have a look over it
-	 */
-	if(pin<16) {
-		tmp = OCR1(port);
-		tmp &= ~( 3<<(pin*2));
-		tmp |= (ocr << (pin*2));
-		OCR1(port) = tmp;
-
-		if( gpio_mode &	GPIO_AOUT )
-			ICONFA1(port) &= ~( 3<<(pin*2));
-		if( gpio_mode &	GPIO_BOUT )
-			ICONFB1(port) &= ~( 3<<(pin*2));
-	} else {
-		tmp = OCR2(port);
-		tmp &= ~( 3<<((pin-16)*2));
-		tmp |= (ocr << ((pin-16)*2));
-		OCR2(port) = tmp;
-
-		if( gpio_mode &	GPIO_AOUT )
-			ICONFA2(port) &= ~( 3<<((pin-16)*2));
-		if( gpio_mode &	GPIO_BOUT )
-			ICONFB2(port) &= ~( 3<<((pin-16)*2));
-	}
-}
-
-#endif /* CONFIG_IMX */
diff --git a/arch/arm/cpu/arm920t/imx/speed.c b/arch/arm/cpu/arm920t/imx/speed.c
deleted file mode 100644
index 1e29698..0000000
--- a/arch/arm/cpu/arm920t/imx/speed.c
+++ /dev/null
@@ -1,102 +0,0 @@
-/*
- *
- * (c) 2004 Sascha Hauer <sascha@saschahauer.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-
-#include <common.h>
-#if defined (CONFIG_IMX)
-
-#include <asm/arch/imx-regs.h>
-
-/* ------------------------------------------------------------------------- */
-/* NOTE: This describes the proper use of this file.
- *
- * CONFIG_SYS_CLK_FREQ should be defined as the input frequency of the PLL.
- * SH FIXME: 16780000 in our case
- * get_FCLK(), get_HCLK(), get_PCLK() and get_UCLK() return the clock of
- * the specified bus in HZ.
- */
-/* ------------------------------------------------------------------------- */
-
-ulong get_systemPLLCLK(void)
-{
-	/* FIXME: We assume System_SEL = 0 here */
-	u32 spctl0 = SPCTL0;
-	u32 mfi = (spctl0 >> 10) & 0xf;
-	u32 mfn = spctl0 & 0x3f;
-	u32 mfd = (spctl0 >> 16) & 0x3f;
-	u32 pd =  (spctl0 >> 26) & 0xf;
-
-	mfi = mfi<=5 ? 5 : mfi;
-
-	return (2*(CONFIG_SYSPLL_CLK_FREQ>>10)*( (mfi<<10) + (mfn<<10)/(mfd+1)))/(pd+1);
-}
-
-ulong get_mcuPLLCLK(void)
-{
-	/* FIXME: We assume System_SEL = 0 here */
-	u32 mpctl0 = MPCTL0;
-	u32 mfi = (mpctl0 >> 10) & 0xf;
-	u32 mfn = mpctl0 & 0x3f;
-	u32 mfd = (mpctl0 >> 16) & 0x3f;
-	u32 pd =  (mpctl0 >> 26) & 0xf;
-
-	mfi = mfi<=5 ? 5 : mfi;
-
-	return (2*(CONFIG_SYS_CLK_FREQ>>10)*( (mfi<<10) + (mfn<<10)/(mfd+1)))/(pd+1);
-}
-
-ulong get_FCLK(void)
-{
-	return (( CSCR>>15)&1) ? get_mcuPLLCLK()>>1 : get_mcuPLLCLK();
-}
-
-/* return HCLK frequency */
-ulong get_HCLK(void)
-{
-	u32 bclkdiv = (( CSCR >> 10 ) & 0xf) + 1;
-	printf("bclkdiv: %d\n", bclkdiv);
-	return get_systemPLLCLK() / bclkdiv;
-}
-
-/* return BCLK frequency */
-ulong get_BCLK(void)
-{
-	return get_HCLK();
-}
-
-ulong get_PERCLK1(void)
-{
-	return get_systemPLLCLK() / (((PCDR) & 0xf)+1);
-}
-
-ulong get_PERCLK2(void)
-{
-	return get_systemPLLCLK() / (((PCDR>>4) & 0xf)+1);
-}
-
-ulong get_PERCLK3(void)
-{
-	return get_systemPLLCLK() / (((PCDR>>16) & 0x7f)+1);
-}
-
-#endif /* defined (CONFIG_IMX) */
diff --git a/arch/arm/cpu/arm920t/imx/timer.c b/arch/arm/cpu/arm920t/imx/timer.c
deleted file mode 100644
index b06b518..0000000
--- a/arch/arm/cpu/arm920t/imx/timer.c
+++ /dev/null
@@ -1,138 +0,0 @@
-/*
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Alex Zuepke <azu@sysgo.de>
- *
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#if defined (CONFIG_IMX)
-
-#include <asm/arch/imx-regs.h>
-
-int timer_init (void)
-{
-	int i;
-	/* setup GP Timer 1 */
-	TCTL1 = TCTL_SWR;
-	for ( i=0; i<100; i++) TCTL1 = 0; /* We have no udelay by now */
-	TPRER1 = get_PERCLK1() / 1000000; /* 1 MHz */
-	TCTL1 |= TCTL_FRR | (1<<1); /* Freerun Mode, PERCLK1 input */
-
-	reset_timer_masked();
-
-	return (0);
-}
-
-/*
- * timer without interrupts
- */
-
-void reset_timer (void)
-{
-	reset_timer_masked ();
-}
-
-ulong get_timer (ulong base)
-{
-	return get_timer_masked() - base;
-}
-
-void set_timer (ulong t)
-{
-	/* nop */
-}
-
-void reset_timer_masked (void)
-{
-	TCTL1 &= ~TCTL_TEN;
-	TCTL1 |= TCTL_TEN; /* Enable timer */
-}
-
-ulong get_timer_masked (void)
-{
-	return TCN1;
-}
-
-void udelay_masked (unsigned long usec)
-{
-	ulong endtime = get_timer_masked() + usec;
-	signed long diff;
-
-	do {
-		ulong now = get_timer_masked ();
-		diff = endtime - now;
-	} while (diff >= 0);
-}
-
-void __udelay (unsigned long usec)
-{
-	udelay_masked(usec);
-}
-
-/*
- * This function is derived from PowerPC code (read timebase as long long).
- * On ARM it just returns the timer value.
- */
-unsigned long long get_ticks(void)
-{
-	return get_timer(0);
-}
-
-/*
- * This function is derived from PowerPC code (timebase clock frequency).
- * On ARM it returns the number of timer ticks per second.
- */
-ulong get_tbclk (void)
-{
-	ulong tbclk;
-
-	tbclk = CONFIG_SYS_HZ;
-
-	return tbclk;
-}
-
-/*
- * Reset the cpu by setting up the watchdog timer and let him time out
- */
-void reset_cpu (ulong ignored)
-{
-	/* Disable watchdog and set Time-Out field to 0 */
-	WCR = 0x00000000;
-
-	/* Write Service Sequence */
-	WSR = 0x00005555;
-	WSR = 0x0000AAAA;
-
-	/* Enable watchdog */
-	WCR = 0x00000001;
-
-	while (1);
-	/*NOTREACHED*/
-}
-
-#endif /* defined (CONFIG_IMX) */
diff --git a/arch/arm/cpu/arm920t/interrupts.c b/arch/arm/cpu/arm920t/interrupts.c
deleted file mode 100644
index 561083e..0000000
--- a/arch/arm/cpu/arm920t/interrupts.c
+++ /dev/null
@@ -1,43 +0,0 @@
-/*
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Alex Zuepke <azu@sysgo.de>
- *
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/proc-armv/ptrace.h>
-
-#if defined (CONFIG_ARCH_INTEGRATOR)
-void do_irq (struct pt_regs *pt_regs)
-{
-	/* ASSUMED to be a timer interrupt  */
-	/* Just clear it - count handled in */
-	/* integratorap.c                   */
-	*(volatile ulong *)(CONFIG_SYS_TIMERBASE + 0x0C) = 0;
-}
-#endif
diff --git a/arch/arm/cpu/arm920t/ks8695/Makefile b/arch/arm/cpu/arm920t/ks8695/Makefile
deleted file mode 100644
index 00ce62b..0000000
--- a/arch/arm/cpu/arm920t/ks8695/Makefile
+++ /dev/null
@@ -1,47 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(SOC).o
-
-SOBJS	= lowlevel_init.o
-
-COBJS	= timer.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
-
-all:	$(obj).depend $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/arch/arm/cpu/arm920t/ks8695/lowlevel_init.S b/arch/arm/cpu/arm920t/ks8695/lowlevel_init.S
deleted file mode 100644
index e9f1227..0000000
--- a/arch/arm/cpu/arm920t/ks8695/lowlevel_init.S
+++ /dev/null
@@ -1,205 +0,0 @@
-/*
- *  lowlevel_init.S - basic hardware initialization for the KS8695 CPU
- *
- *  Copyright (c) 2004-2005, Greg Ungerer <greg.ungerer@opengear.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <version.h>
-#include <asm/arch/platform.h>
-
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
-
-/*
- *************************************************************************
- *
- * Handy dandy macros
- *
- *************************************************************************
- */
-
-/* Delay a bit */
-.macro DELAY_FOR cycles, reg0
-	ldr     \reg0, =\cycles
-	subs    \reg0, \reg0, #1
-	subne   pc,  pc, #0xc
-.endm
-
-/*
- *************************************************************************
- *
- * Some local storage.
- *
- *************************************************************************
- */
-
-/* Should we boot with an interactive console or not */
-.globl serial_console
-
-/*
- *************************************************************************
- *
- * Raw hardware initialization code. The important thing is to get
- * SDRAM setup and running. We do some other basic things here too,
- * like getting the PLL set for high speed, and init the LEDs.
- *
- *************************************************************************
- */
-
-.globl lowlevel_init
-lowlevel_init:
-
-#if DEBUG
-	/*
-	 * enable UART for early debug trace
-	 */
-	ldr	r1, =(KS8695_IO_BASE+KS8695_UART_DIVISOR)
-	mov	r2, #0xd9
-	str	r2, [r1]		/* 115200 baud */
-	ldr	r1, =(KS8695_IO_BASE+KS8695_UART_LINE_CTRL)
-	mov	r2, #0x03
-	str	r2, [r1]		/* 8 data bits, no parity, 1 stop */
-	ldr	r1, =(KS8695_IO_BASE+KS8695_UART_TX_HOLDING)
-	mov	r2, #0x41
-	str	r2, [r1]		/* write 'A' */
-#endif
-#if DEBUG
-	ldr	r1, =(KS8695_IO_BASE+KS8695_UART_TX_HOLDING)
-	mov	r2, #0x42
-	str	r2, [r1]
-#endif
-
-	/*
-	 * remap the memory and flash regions. we want to end up with
-	 * ram from address 0, and flash at 32MB.
-	 */
-	ldr	r1, =(KS8695_IO_BASE+KS8695_MEM_CTRL0)
-	ldr	r2, =0xbfc00040
-	str	r2, [r1]		/* large flash map */
-	ldr	pc, =(highflash+0x02000000-0x00f00000)	/* jump to high flash address */
-highflash:
-	ldr	r2, =0x8fe00040
-	str	r2, [r1]		/* remap flash range */
-
-	/*
-	 * remap the second select region to the 4MB immediately after
-	 * the first region. This way if you have a larger flash (say 8Mb)
-	 * then you can have it all mapped nicely. Has no effect if you
-	 * only have a 4Mb or smaller flash.
-	 */
-	ldr	r1, =(KS8695_IO_BASE+KS8695_MEM_CTRL1)
-	ldr	r2, =0x9fe40040
-	str	r2, [r1]		/* remap flash2 region, contiguous */
-	ldr	r1, =(KS8695_IO_BASE+KS8695_MEM_GENERAL)
-	ldr	r2, =0x30000005
-	str	r2, [r1]		/* enable both flash selects */
-
-#ifdef CONFIG_CM41xx
-	/*
-	 * map the second flash chip, using the external IO lines.
-	 */
-	ldr	r1, =(KS8695_IO_BASE+KS8695_IO_CTRL0)
-	ldr	r2, =0xafe80b6d
-	str	r2, [r1]		/* remap io0 region, contiguous */
-	ldr	r1, =(KS8695_IO_BASE+KS8695_IO_CTRL1)
-	ldr	r2, =0xbfec0b6d
-	str	r2, [r1]		/* remap io1 region, contiguous */
-	ldr	r1, =(KS8695_IO_BASE+KS8695_MEM_GENERAL)
-	ldr	r2, =0x30050005
-	str	r2, [r1]		/* enable second flash */
-#endif
-
-	/*
-	 * before relocating, we have to setup RAM timing
-	 */
-	ldr	r1, =(KS8695_IO_BASE+KS8695_SDRAM_CTRL0)
-#if (PHYS_SDRAM_1_SIZE == 0x02000000)
-	ldr	r2, =0x7fc0000e		/* 32MB */
-#else
-	ldr	r2, =0x3fc0000e		/* 16MB */
-#endif
-	str	r2, [r1]		/* configure sdram bank0 setup */
-	ldr	r1, =(KS8695_IO_BASE+KS8695_SDRAM_CTRL1)
-	mov	r2, #0
-	str	r2, [r1]		/* configure sdram bank1 setup */
-
-	ldr	r1, =(KS8695_IO_BASE+KS8695_SDRAM_GENERAL)
-	ldr	r2, =0x0000000a
-	str	r2, [r1]		/* set RAS/CAS timing */
-
-	ldr	r1, =(KS8695_IO_BASE+KS8695_SDRAM_BUFFER)
-	ldr	r2, =0x00030000
-	str	r2, [r1]		/* send NOP command */
-	DELAY_FOR 0x100, r0
-	ldr	r2, =0x00010000
-	str	r2, [r1]		/* send PRECHARGE-ALL */
-	DELAY_FOR 0x100, r0
-
-	ldr	r1, =(KS8695_IO_BASE+KS8695_SDRAM_REFRESH)
-	ldr	r2, =0x00000020
-	str	r2, [r1]		/* set for fast refresh */
-	DELAY_FOR 0x100, r0
-	ldr	r2, =0x00000190
-	str	r2, [r1]		/* set normal refresh timing */
-
-	ldr	r1, =(KS8695_IO_BASE+KS8695_SDRAM_BUFFER)
-	ldr	r2, =0x00020033
-	str	r2, [r1]		/* send mode command */
-	DELAY_FOR 0x100, r0
-	ldr	r2, =0x01f00000
-	str	r2, [r1]		/* enable sdram fifos */
-
-	/*
-	 * set pll to top speed
-	 */
-	ldr	r1, =(KS8695_IO_BASE+KS8695_SYSTEN_BUS_CLOCK)
-	mov	r2, #0
-	str	r2, [r1]		/* set pll clock to 166MHz */
-
-	ldr	r1, =(KS8695_IO_BASE+KS8695_SWITCH_CTRL0)
-	ldr	r2, [r1]		/* Get switch ctrl0 register       */
-	and	r2, r2, #0x0fc00000	/* Mask out LED control bits       */
-	orr	r2, r2, #0x01800000	/* Set Link/activity/speed actions */
-	str	r2, [r1]
-
-#ifdef CONFIG_CM4008
-	ldr	r1, =(KS8695_IO_BASE+KS8695_GPIO_MODE)
-	ldr	r2, =0x0000fe30
-	str	r2, [r1]		/* enable LED's as outputs	    */
-	ldr	r1, =(KS8695_IO_BASE+KS8695_GPIO_DATA)
-	ldr	r2, =0x0000fe20
-	str	r2, [r1]		/* turn on power LED		    */
-#endif
-#if defined(CONFIG_CM4008) || defined(CONFIG_CM41xx)
-	ldr	r2, [r1]		/* get current GPIO input data	    */
-	tst	r2, #0x8		/* check if "erase" depressed	    */
-	beq	nobutton
-	mov	r2, #0			/* be quiet on boot, no console	    */
-	ldr	r1, =serial_console
-	str	r2, [r1]
-nobutton:
-#endif
-
-	add	lr, lr, #0x02000000	/* flash is now mapped high */
-	add	ip, ip, #0x02000000	/* this is a hack */
-	mov	pc, lr			/* all done, return */
-
-#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
diff --git a/arch/arm/cpu/arm920t/ks8695/timer.c b/arch/arm/cpu/arm920t/ks8695/timer.c
deleted file mode 100644
index 886e370..0000000
--- a/arch/arm/cpu/arm920t/ks8695/timer.c
+++ /dev/null
@@ -1,108 +0,0 @@
-/*
- * (C) Copyright 2004-2005, Greg Ungerer <greg.ungerer@opengear.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/arch/platform.h>
-
-/*
- * Handy KS8695 register access functions.
- */
-#define	ks8695_read(a)    *((volatile ulong *) (KS8695_IO_BASE + (a)))
-#define	ks8695_write(a,v) *((volatile ulong *) (KS8695_IO_BASE + (a))) = (v)
-
-ulong timer_ticks;
-
-int timer_init (void)
-{
-	reset_timer();
-
-	return 0;
-}
-
-/*
- * Initial timer set constants. Nothing complicated, just set for a 1ms
- * tick.
- */
-#define	TIMER_INTERVAL	(TICKS_PER_uSEC * mSEC_1)
-#define	TIMER_COUNT	(TIMER_INTERVAL / 2)
-#define	TIMER_PULSE	TIMER_COUNT
-
-void reset_timer_masked(void)
-{
-	/* Set the hadware timer for 1ms */
-	ks8695_write(KS8695_TIMER1, TIMER_COUNT);
-	ks8695_write(KS8695_TIMER1_PCOUNT, TIMER_PULSE);
-	ks8695_write(KS8695_TIMER_CTRL, 0x2);
-	timer_ticks = 0;
-}
-
-void reset_timer(void)
-{
-	reset_timer_masked();
-}
-
-ulong get_timer_masked(void)
-{
-	/* Check for timer wrap */
-	if (ks8695_read(KS8695_INT_STATUS) & KS8695_INTMASK_TIMERINT1) {
-		/* Clear interrupt condition */
-		ks8695_write(KS8695_INT_STATUS, KS8695_INTMASK_TIMERINT1);
-		timer_ticks++;
-	}
-	return timer_ticks;
-}
-
-ulong get_timer(ulong base)
-{
-       return (get_timer_masked() - base);
-}
-
-void set_timer(ulong t)
-{
-	timer_ticks = t;
-}
-
-void __udelay(ulong usec)
-{
-	ulong start = get_timer_masked();
-	ulong end;
-
-	/* Only 1ms resolution :-( */
-	end = usec / 1000;
-	while (get_timer(start) < end)
-		;
-}
-
-void reset_cpu (ulong ignored)
-{
-	ulong tc;
-
-	/* Set timer0 to watchdog, and let it timeout */
-	tc = ks8695_read(KS8695_TIMER_CTRL) & 0x2;
-	ks8695_write(KS8695_TIMER_CTRL, tc);
-	ks8695_write(KS8695_TIMER0, ((10 << 8) | 0xff));
-	ks8695_write(KS8695_TIMER_CTRL, (tc | 0x1));
-
-	/* Should only wait here till watchdog resets */
-	for (;;)
-		;
-}
diff --git a/arch/arm/cpu/arm920t/s3c24x0/Makefile b/arch/arm/cpu/arm920t/s3c24x0/Makefile
deleted file mode 100644
index bd53724..0000000
--- a/arch/arm/cpu/arm920t/s3c24x0/Makefile
+++ /dev/null
@@ -1,50 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(SOC).o
-
-COBJS-$(CONFIG_USE_IRQ) += interrupts.o
-COBJS-y	+= speed.o
-COBJS-y	+= timer.o
-COBJS-y	+= usb.o
-COBJS-y	+= usb_ohci.o
-
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS-y))
-
-all:	$(obj).depend $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/arch/arm/cpu/arm920t/s3c24x0/interrupts.c b/arch/arm/cpu/arm920t/s3c24x0/interrupts.c
deleted file mode 100644
index 879fda6..0000000
--- a/arch/arm/cpu/arm920t/s3c24x0/interrupts.c
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Alex Zuepke <azu@sysgo.de>
- *
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-
-#include <asm/arch/s3c24x0_cpu.h>
-#include <asm/proc-armv/ptrace.h>
-
-void do_irq (struct pt_regs *pt_regs)
-{
-	struct s3c24x0_interrupt *irq = s3c24x0_get_base_interrupt();
-	u_int32_t intpnd = readl(&irq->INTPND);
-
-}
diff --git a/arch/arm/cpu/arm920t/s3c24x0/speed.c b/arch/arm/cpu/arm920t/s3c24x0/speed.c
deleted file mode 100644
index 3ae558d..0000000
--- a/arch/arm/cpu/arm920t/s3c24x0/speed.c
+++ /dev/null
@@ -1,118 +0,0 @@
-/*
- * (C) Copyright 2001-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2002
- * David Mueller, ELSOFT AG, d.mueller@elsoft.ch
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/* This code should work for both the S3C2400 and the S3C2410
- * as they seem to have the same PLL and clock machinery inside.
- * The different address mapping is handled by the s3c24xx.h files below.
- */
-
-#include <common.h>
-#ifdef CONFIG_S3C24X0
-
-#include <asm/io.h>
-#include <asm/arch/s3c24x0_cpu.h>
-
-#define MPLL 0
-#define UPLL 1
-
-/* ------------------------------------------------------------------------- */
-/* NOTE: This describes the proper use of this file.
- *
- * CONFIG_SYS_CLK_FREQ should be defined as the input frequency of the PLL.
- *
- * get_FCLK(), get_HCLK(), get_PCLK() and get_UCLK() return the clock of
- * the specified bus in HZ.
- */
-/* ------------------------------------------------------------------------- */
-
-static ulong get_PLLCLK(int pllreg)
-{
-	struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
-	ulong r, m, p, s;
-
-	if (pllreg == MPLL)
-		r = readl(&clk_power->mpllcon);
-	else if (pllreg == UPLL)
-		r = readl(&clk_power->upllcon);
-	else
-		hang();
-
-	m = ((r & 0xFF000) >> 12) + 8;
-	p = ((r & 0x003F0) >> 4) + 2;
-	s = r & 0x3;
-
-#if defined(CONFIG_S3C2440)
-	if (pllreg == MPLL)
-		return 2 * m * (CONFIG_SYS_CLK_FREQ / (p << s));
-#endif
-	return (CONFIG_SYS_CLK_FREQ * m) / (p << s);
-
-}
-
-/* return FCLK frequency */
-ulong get_FCLK(void)
-{
-	return get_PLLCLK(MPLL);
-}
-
-/* return HCLK frequency */
-ulong get_HCLK(void)
-{
-	struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
-#ifdef CONFIG_S3C2440
-	switch (readl(&clk_power->clkdivn) & 0x6) {
-	default:
-	case 0:
-		return get_FCLK();
-	case 2:
-		return get_FCLK() / 2;
-	case 4:
-		return (readl(&clk_power->camdivn) & (1 << 9)) ?
-			get_FCLK() / 8 : get_FCLK() / 4;
-	case 6:
-		return (readl(&clk_power->camdivn) & (1 << 8)) ?
-			get_FCLK() / 6 : get_FCLK() / 3;
-	}
-#else
-	return (readl(&clk_power->clkdivn) & 2) ? get_FCLK() / 2 : get_FCLK();
-#endif
-}
-
-/* return PCLK frequency */
-ulong get_PCLK(void)
-{
-	struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
-
-	return (readl(&clk_power->clkdivn) & 1) ? get_HCLK() / 2 : get_HCLK();
-}
-
-/* return UCLK frequency */
-ulong get_UCLK(void)
-{
-	return get_PLLCLK(UPLL);
-}
-
-#endif /* CONFIG_S3C24X0 */
diff --git a/arch/arm/cpu/arm920t/s3c24x0/timer.c b/arch/arm/cpu/arm920t/s3c24x0/timer.c
deleted file mode 100644
index 8cf9ff6..0000000
--- a/arch/arm/cpu/arm920t/s3c24x0/timer.c
+++ /dev/null
@@ -1,224 +0,0 @@
-/*
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Alex Zuepke <azu@sysgo.de>
- *
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#ifdef CONFIG_S3C24X0
-
-#include <asm/io.h>
-#include <asm/arch/s3c24x0_cpu.h>
-
-int timer_load_val = 0;
-static ulong timer_clk;
-
-/* macro to read the 16 bit timer */
-static inline ulong READ_TIMER(void)
-{
-	struct s3c24x0_timers *timers = s3c24x0_get_base_timers();
-
-	return readl(&timers->tcnto4) & 0xffff;
-}
-
-static ulong timestamp;
-static ulong lastdec;
-
-int timer_init(void)
-{
-	struct s3c24x0_timers *timers = s3c24x0_get_base_timers();
-	ulong tmr;
-
-	/* use PWM Timer 4 because it has no output */
-	/* prescaler for Timer 4 is 16 */
-	writel(0x0f00, &timers->tcfg0);
-	if (timer_load_val == 0) {
-		/*
-		 * for 10 ms clock period @ PCLK with 4 bit divider = 1/2
-		 * (default) and prescaler = 16. Should be 10390
-		 * @33.25MHz and 15625 @ 50 MHz
-		 */
-		timer_load_val = get_PCLK() / (2 * 16 * 100);
-		timer_clk = get_PCLK() / (2 * 16);
-	}
-	/* load value for 10 ms timeout */
-	lastdec = timer_load_val;
-	writel(timer_load_val, &timers->tcntb4);
-	/* auto load, manual update of timer 4 */
-	tmr = (readl(&timers->tcon) & ~0x0700000) | 0x0600000;
-	writel(tmr, &timers->tcon);
-	/* auto load, start timer 4 */
-	tmr = (tmr & ~0x0700000) | 0x0500000;
-	writel(tmr, &timers->tcon);
-	timestamp = 0;
-
-	return (0);
-}
-
-/*
- * timer without interrupts
- */
-
-void reset_timer(void)
-{
-	reset_timer_masked();
-}
-
-ulong get_timer(ulong base)
-{
-	return get_timer_masked() - base;
-}
-
-void set_timer(ulong t)
-{
-	timestamp = t;
-}
-
-void __udelay (unsigned long usec)
-{
-	ulong tmo;
-	ulong start = get_ticks();
-
-	tmo = usec / 1000;
-	tmo *= (timer_load_val * 100);
-	tmo /= 1000;
-
-	while ((ulong) (get_ticks() - start) < tmo)
-		/*NOP*/;
-}
-
-void reset_timer_masked(void)
-{
-	/* reset time */
-	lastdec = READ_TIMER();
-	timestamp = 0;
-}
-
-ulong get_timer_masked(void)
-{
-	ulong tmr = get_ticks();
-
-	return tmr / (timer_clk / CONFIG_SYS_HZ);
-}
-
-void udelay_masked(unsigned long usec)
-{
-	ulong tmo;
-	ulong endtime;
-	signed long diff;
-
-	if (usec >= 1000) {
-		tmo = usec / 1000;
-		tmo *= (timer_load_val * 100);
-		tmo /= 1000;
-	} else {
-		tmo = usec * (timer_load_val * 100);
-		tmo /= (1000 * 1000);
-	}
-
-	endtime = get_ticks() + tmo;
-
-	do {
-		ulong now = get_ticks();
-		diff = endtime - now;
-	} while (diff >= 0);
-}
-
-/*
- * This function is derived from PowerPC code (read timebase as long long).
- * On ARM it just returns the timer value.
- */
-unsigned long long get_ticks(void)
-{
-	ulong now = READ_TIMER();
-
-	if (lastdec >= now) {
-		/* normal mode */
-		timestamp += lastdec - now;
-	} else {
-		/* we have an overflow ... */
-		timestamp += lastdec + timer_load_val - now;
-	}
-	lastdec = now;
-
-	return timestamp;
-}
-
-/*
- * This function is derived from PowerPC code (timebase clock frequency).
- * On ARM it returns the number of timer ticks per second.
- */
-ulong get_tbclk(void)
-{
-	ulong tbclk;
-
-#if defined(CONFIG_SMDK2400) || defined(CONFIG_TRAB)
-	tbclk = timer_load_val * 100;
-#elif defined(CONFIG_SBC2410X) || \
-      defined(CONFIG_SMDK2410) || \
-	defined(CONFIG_S3C2440) || \
-      defined(CONFIG_VCMA9)
-	tbclk = CONFIG_SYS_HZ;
-#else
-#	error "tbclk not configured"
-#endif
-
-	return tbclk;
-}
-
-/*
- * reset the cpu by setting up the watchdog timer and let him time out
- */
-void reset_cpu(ulong ignored)
-{
-	struct s3c24x0_watchdog *watchdog;
-
-#ifdef CONFIG_TRAB
-	extern void disable_vfd(void);
-
-	disable_vfd();
-#endif
-
-	watchdog = s3c24x0_get_base_watchdog();
-
-	/* Disable watchdog */
-	writel(0x0000, &watchdog->wtcon);
-
-	/* Initialize watchdog timer count register */
-	writel(0x0001, &watchdog->wtcnt);
-
-	/* Enable watchdog timer; assert reset at timer timeout */
-	writel(0x0021, &watchdog->wtcon);
-
-	while (1)
-		/* loop forever and wait for reset to happen */;
-
-	/*NOTREACHED*/
-}
-
-#endif /* CONFIG_S3C24X0 */
diff --git a/arch/arm/cpu/arm920t/s3c24x0/usb.c b/arch/arm/cpu/arm920t/s3c24x0/usb.c
deleted file mode 100644
index 226a3f6..0000000
--- a/arch/arm/cpu/arm920t/s3c24x0/usb.c
+++ /dev/null
@@ -1,71 +0,0 @@
-/*
- * (C) Copyright 2006
- * DENX Software Engineering <mk@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-
-#if defined(CONFIG_USB_OHCI_NEW) && \
-    defined(CONFIG_SYS_USB_OHCI_CPU_INIT) && \
-    defined(CONFIG_S3C24X0)
-
-#include <asm/arch/s3c24x0_cpu.h>
-#include <asm/io.h>
-
-int usb_cpu_init(void)
-{
-	struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
-	struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio();
-
-	/*
-	 * Set the 48 MHz UPLL clocking. Values are taken from
-	 * "PLL value selection guide", 6-23, s3c2400_UM.pdf.
-	 */
-	writel((40 << 12) + (1 << 4) + 2, &clk_power->upllcon);
-	/* 1 = use pads related USB for USB host */
-	writel(readl(&gpio->misccr) | 0x8, &gpio->misccr);
-
-	/*
-	 * Enable USB host clock.
-	 */
-	writel(readl(&clk_power->clkcon) | (1 << 4), &clk_power->clkcon);
-
-	return 0;
-}
-
-int usb_cpu_stop(void)
-{
-	struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
-	/* may not want to do this */
-	writel(readl(&clk_power->clkcon) & ~(1 << 4), &clk_power->clkcon);
-	return 0;
-}
-
-int usb_cpu_init_fail(void)
-{
-	struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
-	writel(readl(&clk_power->clkcon) & ~(1 << 4), &clk_power->clkcon);
-	return 0;
-}
-
-#endif /* defined(CONFIG_USB_OHCI_NEW) && \
-	   defined(CONFIG_SYS_USB_OHCI_CPU_INIT) && \
-	   defined(CONFIG_S3C24X0) */
diff --git a/arch/arm/cpu/arm920t/s3c24x0/usb_ohci.c b/arch/arm/cpu/arm920t/s3c24x0/usb_ohci.c
deleted file mode 100644
index ccc9738..0000000
--- a/arch/arm/cpu/arm920t/s3c24x0/usb_ohci.c
+++ /dev/null
@@ -1,1755 +0,0 @@
-/*
- * URB OHCI HCD (Host Controller Driver) for USB on the S3C2400.
- *
- * (C) Copyright 2003
- * Gary Jennejohn, DENX Software Engineering <garyj@denx.de>
- *
- * Note: Much of this code has been derived from Linux 2.4
- * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
- * (C) Copyright 2000-2002 David Brownell
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- */
-/*
- * IMPORTANT NOTES
- * 1 - this driver is intended for use with USB Mass Storage Devices
- *     (BBB) ONLY. There is NO support for Interrupt or Isochronous pipes!
- */
-
-#include <common.h>
-/* #include <pci.h> no PCI on the S3C24X0 */
-
-#if defined(CONFIG_USB_OHCI) && defined(CONFIG_S3C24X0)
-
-#include <asm/arch/s3c24x0_cpu.h>
-#include <asm/io.h>
-#include <malloc.h>
-#include <usb.h>
-#include "usb_ohci.h"
-
-#define OHCI_USE_NPS		/* force NoPowerSwitching mode */
-#undef OHCI_VERBOSE_DEBUG	/* not always helpful */
-
-
-/* For initializing controller (mask in an HCFS mode too) */
-#define	OHCI_CONTROL_INIT \
-	(OHCI_CTRL_CBSR & 0x3) | OHCI_CTRL_IE | OHCI_CTRL_PLE
-
-#define min_t(type, x, y) \
-	({ type __x = (x); type __y = (y); __x < __y ? __x : __y; })
-
-#undef DEBUG
-#ifdef DEBUG
-#define dbg(format, arg...) printf("DEBUG: " format "\n", ## arg)
-#else
-#define dbg(format, arg...) do {} while(0)
-#endif /* DEBUG */
-#define err(format, arg...) printf("ERROR: " format "\n", ## arg)
-#undef SHOW_INFO
-#ifdef SHOW_INFO
-#define info(format, arg...) printf("INFO: " format "\n", ## arg)
-#else
-#define info(format, arg...) do {} while(0)
-#endif
-
-#define m16_swap(x) swap_16(x)
-#define m32_swap(x) swap_32(x)
-
-/* global struct ohci */
-static struct ohci gohci;
-/* this must be aligned to a 256 byte boundary */
-struct ohci_hcca ghcca[1];
-/* a pointer to the aligned storage */
-struct ohci_hcca *phcca;
-/* this allocates EDs for all possible endpoints */
-struct ohci_device ohci_dev;
-/* urb_priv */
-struct urb_priv urb_priv;
-/* RHSC flag */
-int got_rhsc;
-/* device which was disconnected */
-struct usb_device *devgone;
-/* flag guarding URB transation */
-int urb_finished = 0;
-
-/*-------------------------------------------------------------------------*/
-
-/* AMD-756 (D2 rev) reports corrupt register contents in some cases.
- * The erratum (#4) description is incorrect.  AMD's workaround waits
- * till some bits (mostly reserved) are clear; ok for all revs.
- */
-#define OHCI_QUIRK_AMD756 0xabcd
-#define read_roothub(hc, register, mask) ({ \
-	u32 temp = readl (&hc->regs->roothub.register); \
-	if (hc->flags & OHCI_QUIRK_AMD756) \
-		while (temp & mask) \
-			temp = readl (&hc->regs->roothub.register); \
-	temp; })
-
-static u32 roothub_a(struct ohci *hc)
-{
-	return read_roothub(hc, a, 0xfc0fe000);
-}
-static inline u32 roothub_b(struct ohci *hc)
-{
-	return readl(&hc->regs->roothub.b);
-}
-static inline u32 roothub_status(struct ohci *hc)
-{
-	return readl(&hc->regs->roothub.status);
-}
-static u32 roothub_portstatus(struct ohci *hc, int i)
-{
-	return read_roothub(hc, portstatus[i], 0xffe0fce0);
-}
-
-/* forward declaration */
-static int hc_interrupt(void);
-static void td_submit_job(struct usb_device *dev, unsigned long pipe,
-			  void *buffer, int transfer_len,
-			  struct devrequest *setup, struct urb_priv *urb,
-			  int interval);
-
-/*-------------------------------------------------------------------------*
- * URB support functions
- *-------------------------------------------------------------------------*/
-
-/* free HCD-private data associated with this URB */
-
-static void urb_free_priv(struct urb_priv *urb)
-{
-	int i;
-	int last;
-	struct td *td;
-
-	last = urb->length - 1;
-	if (last >= 0) {
-		for (i = 0; i <= last; i++) {
-			td = urb->td[i];
-			if (td) {
-				td->usb_dev = NULL;
-				urb->td[i] = NULL;
-			}
-		}
-	}
-}
-
-/*-------------------------------------------------------------------------*/
-
-#ifdef DEBUG
-static int sohci_get_current_frame_number(struct usb_device *dev);
-
-/* debug| print the main components of an URB
- * small: 0) header + data packets 1) just header */
-
-static void pkt_print(struct usb_device *dev, unsigned long pipe, void *buffer,
-		      int transfer_len, struct devrequest *setup, char *str,
-		      int small)
-{
-	struct urb_priv *purb = &urb_priv;
-
-	dbg("%s URB:[%4x] dev:%2d,ep:%2d-%c,type:%s,len:%d/%d stat:%#lx",
-	    str,
-	    sohci_get_current_frame_number(dev),
-	    usb_pipedevice(pipe),
-	    usb_pipeendpoint(pipe),
-	    usb_pipeout(pipe) ? 'O' : 'I',
-	    usb_pipetype(pipe) < 2 ?
-		(usb_pipeint(pipe) ? "INTR" : "ISOC") :
-		(usb_pipecontrol(pipe) ? "CTRL" : "BULK"),
-	    purb->actual_length, transfer_len, dev->status);
-#ifdef	OHCI_VERBOSE_DEBUG
-	if (!small) {
-		int i, len;
-
-		if (usb_pipecontrol(pipe)) {
-			printf(__FILE__ ": cmd(8):");
-			for (i = 0; i < 8; i++)
-				printf(" %02x", ((__u8 *) setup)[i]);
-			printf("\n");
-		}
-		if (transfer_len > 0 && buffer) {
-			printf(__FILE__ ": data(%d/%d):",
-			       purb->actual_length, transfer_len);
-			len = usb_pipeout(pipe) ?
-			    transfer_len : purb->actual_length;
-			for (i = 0; i < 16 && i < len; i++)
-				printf(" %02x", ((__u8 *) buffer)[i]);
-			printf("%s\n", i < len ? "..." : "");
-		}
-	}
-#endif
-}
-
-/* just for debugging; prints non-empty branches of the
-   int ed tree inclusive iso eds*/
-void ep_print_int_eds(struct ohci *ohci, char *str)
-{
-	int i, j;
-	__u32 *ed_p;
-	for (i = 0; i < 32; i++) {
-		j = 5;
-		ed_p = &(ohci->hcca->int_table[i]);
-		if (*ed_p == 0)
-			continue;
-		printf(__FILE__ ": %s branch int %2d(%2x):", str, i, i);
-		while (*ed_p != 0 && j--) {
-			struct ed *ed = (struct ed *) m32_swap(ed_p);
-			printf(" ed: %4x;", ed->hwINFO);
-			ed_p = &ed->hwNextED;
-		}
-		printf("\n");
-	}
-}
-
-static void ohci_dump_intr_mask(char *label, __u32 mask)
-{
-	dbg("%s: 0x%08x%s%s%s%s%s%s%s%s%s",
-	    label,
-	    mask,
-	    (mask & OHCI_INTR_MIE) ? " MIE" : "",
-	    (mask & OHCI_INTR_OC) ? " OC" : "",
-	    (mask & OHCI_INTR_RHSC) ? " RHSC" : "",
-	    (mask & OHCI_INTR_FNO) ? " FNO" : "",
-	    (mask & OHCI_INTR_UE) ? " UE" : "",
-	    (mask & OHCI_INTR_RD) ? " RD" : "",
-	    (mask & OHCI_INTR_SF) ? " SF" : "",
-	    (mask & OHCI_INTR_WDH) ? " WDH" : "",
-	    (mask & OHCI_INTR_SO) ? " SO" : "");
-}
-
-static void maybe_print_eds(char *label, __u32 value)
-{
-	struct ed *edp = (struct ed *) value;
-
-	if (value) {
-		dbg("%s %08x", label, value);
-		dbg("%08x", edp->hwINFO);
-		dbg("%08x", edp->hwTailP);
-		dbg("%08x", edp->hwHeadP);
-		dbg("%08x", edp->hwNextED);
-	}
-}
-
-static char *hcfs2string(int state)
-{
-	switch (state) {
-	case OHCI_USB_RESET:
-		return "reset";
-	case OHCI_USB_RESUME:
-		return "resume";
-	case OHCI_USB_OPER:
-		return "operational";
-	case OHCI_USB_SUSPEND:
-		return "suspend";
-	}
-	return "?";
-}
-
-/* dump control and status registers */
-static void ohci_dump_status(struct ohci *controller)
-{
-	struct ohci_regs *regs = controller->regs;
-	__u32 temp;
-
-	temp = readl(&regs->revision) & 0xff;
-	if (temp != 0x10)
-		dbg("spec %d.%d", (temp >> 4), (temp & 0x0f));
-
-	temp = readl(&regs->control);
-	dbg("control: 0x%08x%s%s%s HCFS=%s%s%s%s%s CBSR=%d", temp,
-	    (temp & OHCI_CTRL_RWE) ? " RWE" : "",
-	    (temp & OHCI_CTRL_RWC) ? " RWC" : "",
-	    (temp & OHCI_CTRL_IR) ? " IR" : "",
-	    hcfs2string(temp & OHCI_CTRL_HCFS),
-	    (temp & OHCI_CTRL_BLE) ? " BLE" : "",
-	    (temp & OHCI_CTRL_CLE) ? " CLE" : "",
-	    (temp & OHCI_CTRL_IE) ? " IE" : "",
-	    (temp & OHCI_CTRL_PLE) ? " PLE" : "", temp & OHCI_CTRL_CBSR);
-
-	temp = readl(&regs->cmdstatus);
-	dbg("cmdstatus: 0x%08x SOC=%d%s%s%s%s", temp,
-	    (temp & OHCI_SOC) >> 16,
-	    (temp & OHCI_OCR) ? " OCR" : "",
-	    (temp & OHCI_BLF) ? " BLF" : "",
-	    (temp & OHCI_CLF) ? " CLF" : "", (temp & OHCI_HCR) ? " HCR" : "");
-
-	ohci_dump_intr_mask("intrstatus", readl(&regs->intrstatus));
-	ohci_dump_intr_mask("intrenable", readl(&regs->intrenable));
-
-	maybe_print_eds("ed_periodcurrent", readl(&regs->ed_periodcurrent));
-
-	maybe_print_eds("ed_controlhead", readl(&regs->ed_controlhead));
-	maybe_print_eds("ed_controlcurrent", readl(&regs->ed_controlcurrent));
-
-	maybe_print_eds("ed_bulkhead", readl(&regs->ed_bulkhead));
-	maybe_print_eds("ed_bulkcurrent", readl(&regs->ed_bulkcurrent));
-
-	maybe_print_eds("donehead", readl(&regs->donehead));
-}
-
-static void ohci_dump_roothub(struct ohci *controller, int verbose)
-{
-	__u32 temp, ndp, i;
-
-	temp = roothub_a(controller);
-	ndp = (temp & RH_A_NDP);
-
-	if (verbose) {
-		dbg("roothub.a: %08x POTPGT=%d%s%s%s%s%s NDP=%d", temp,
-		    ((temp & RH_A_POTPGT) >> 24) & 0xff,
-		    (temp & RH_A_NOCP) ? " NOCP" : "",
-		    (temp & RH_A_OCPM) ? " OCPM" : "",
-		    (temp & RH_A_DT) ? " DT" : "",
-		    (temp & RH_A_NPS) ? " NPS" : "",
-		    (temp & RH_A_PSM) ? " PSM" : "", ndp);
-		temp = roothub_b(controller);
-		dbg("roothub.b: %08x PPCM=%04x DR=%04x",
-		    temp, (temp & RH_B_PPCM) >> 16, (temp & RH_B_DR)
-		    );
-		temp = roothub_status(controller);
-		dbg("roothub.status: %08x%s%s%s%s%s%s",
-		    temp,
-		    (temp & RH_HS_CRWE) ? " CRWE" : "",
-		    (temp & RH_HS_OCIC) ? " OCIC" : "",
-		    (temp & RH_HS_LPSC) ? " LPSC" : "",
-		    (temp & RH_HS_DRWE) ? " DRWE" : "",
-		    (temp & RH_HS_OCI) ? " OCI" : "",
-		    (temp & RH_HS_LPS) ? " LPS" : "");
-	}
-
-	for (i = 0; i < ndp; i++) {
-		temp = roothub_portstatus(controller, i);
-		dbg("roothub.portstatus [%d] = 0x%08x%s%s%s%s%s%s%s%s%s%s%s%s",
-		    i,
-		    temp,
-		    (temp & RH_PS_PRSC) ? " PRSC" : "",
-		    (temp & RH_PS_OCIC) ? " OCIC" : "",
-		    (temp & RH_PS_PSSC) ? " PSSC" : "",
-		    (temp & RH_PS_PESC) ? " PESC" : "",
-		    (temp & RH_PS_CSC) ? " CSC" : "",
-		    (temp & RH_PS_LSDA) ? " LSDA" : "",
-		    (temp & RH_PS_PPS) ? " PPS" : "",
-		    (temp & RH_PS_PRS) ? " PRS" : "",
-		    (temp & RH_PS_POCI) ? " POCI" : "",
-		    (temp & RH_PS_PSS) ? " PSS" : "",
-		    (temp & RH_PS_PES) ? " PES" : "",
-		    (temp & RH_PS_CCS) ? " CCS" : "");
-	}
-}
-
-static void ohci_dump(struct ohci *controller, int verbose)
-{
-	dbg("OHCI controller usb-%s state", controller->slot_name);
-
-	/* dumps some of the state we know about */
-	ohci_dump_status(controller);
-	if (verbose)
-		ep_print_int_eds(controller, "hcca");
-	dbg("hcca frame #%04x", controller->hcca->frame_no);
-	ohci_dump_roothub(controller, 1);
-}
-
-#endif /* DEBUG */
-
-/*-------------------------------------------------------------------------*
- * Interface functions (URB)
- *-------------------------------------------------------------------------*/
-
-/* get a transfer request */
-
-int sohci_submit_job(struct usb_device *dev, unsigned long pipe, void *buffer,
-		     int transfer_len, struct devrequest *setup, int interval)
-{
-	struct ohci *ohci;
-	struct ed *ed;
-	struct urb_priv *purb_priv;
-	int i, size = 0;
-
-	ohci = &gohci;
-
-	/* when controller's hung, permit only roothub cleanup attempts
-	 * such as powering down ports */
-	if (ohci->disabled) {
-		err("sohci_submit_job: EPIPE");
-		return -1;
-	}
-
-	/* if we have an unfinished URB from previous transaction let's
-	 * fail and scream as quickly as possible so as not to corrupt
-	 * further communication */
-	if (!urb_finished) {
-		err("sohci_submit_job: URB NOT FINISHED");
-		return -1;
-	}
-	/* we're about to begin a new transaction here
-	   so mark the URB unfinished */
-	urb_finished = 0;
-
-	/* every endpoint has a ed, locate and fill it */
-	ed = ep_add_ed(dev, pipe);
-	if (!ed) {
-		err("sohci_submit_job: ENOMEM");
-		return -1;
-	}
-
-	/* for the private part of the URB we need the number of TDs (size) */
-	switch (usb_pipetype(pipe)) {
-	case PIPE_BULK:
-		/* one TD for every 4096 Byte */
-		size = (transfer_len - 1) / 4096 + 1;
-		break;
-	case PIPE_CONTROL:
-		/* 1 TD for setup, 1 for ACK and 1 for every 4096 B */
-		size = (transfer_len == 0) ? 2 : (transfer_len - 1) / 4096 + 3;
-		break;
-	}
-
-	if (size >= (N_URB_TD - 1)) {
-		err("need %d TDs, only have %d", size, N_URB_TD);
-		return -1;
-	}
-	purb_priv = &urb_priv;
-	purb_priv->pipe = pipe;
-
-	/* fill the private part of the URB */
-	purb_priv->length = size;
-	purb_priv->ed = ed;
-	purb_priv->actual_length = 0;
-
-	/* allocate the TDs */
-	/* note that td[0] was allocated in ep_add_ed */
-	for (i = 0; i < size; i++) {
-		purb_priv->td[i] = td_alloc(dev);
-		if (!purb_priv->td[i]) {
-			purb_priv->length = i;
-			urb_free_priv(purb_priv);
-			err("sohci_submit_job: ENOMEM");
-			return -1;
-		}
-	}
-
-	if (ed->state == ED_NEW || (ed->state & ED_DEL)) {
-		urb_free_priv(purb_priv);
-		err("sohci_submit_job: EINVAL");
-		return -1;
-	}
-
-	/* link the ed into a chain if is not already */
-	if (ed->state != ED_OPER)
-		ep_link(ohci, ed);
-
-	/* fill the TDs and link it to the ed */
-	td_submit_job(dev, pipe, buffer, transfer_len, setup, purb_priv,
-		      interval);
-
-	return 0;
-}
-
-/*-------------------------------------------------------------------------*/
-
-#ifdef DEBUG
-/* tell us the current USB frame number */
-
-static int sohci_get_current_frame_number(struct usb_device *usb_dev)
-{
-	struct ohci *ohci = &gohci;
-
-	return m16_swap(ohci->hcca->frame_no);
-}
-#endif
-
-/*-------------------------------------------------------------------------*
- * ED handling functions
- *-------------------------------------------------------------------------*/
-
-/* link an ed into one of the HC chains */
-
-static int ep_link(struct ohci *ohci, struct ed *edi)
-{
-	struct ed *ed = edi;
-
-	ed->state = ED_OPER;
-
-	switch (ed->type) {
-	case PIPE_CONTROL:
-		ed->hwNextED = 0;
-		if (ohci->ed_controltail == NULL) {
-			writel((u32)ed, &ohci->regs->ed_controlhead);
-		} else {
-			ohci->ed_controltail->hwNextED = (__u32) m32_swap(ed);
-		}
-		ed->ed_prev = ohci->ed_controltail;
-		if (!ohci->ed_controltail && !ohci->ed_rm_list[0] &&
-		    !ohci->ed_rm_list[1] && !ohci->sleeping) {
-			ohci->hc_control |= OHCI_CTRL_CLE;
-			writel(ohci->hc_control, &ohci->regs->control);
-		}
-		ohci->ed_controltail = edi;
-		break;
-
-	case PIPE_BULK:
-		ed->hwNextED = 0;
-		if (ohci->ed_bulktail == NULL) {
-			writel((u32)ed, &ohci->regs->ed_bulkhead);
-		} else {
-			ohci->ed_bulktail->hwNextED = (__u32) m32_swap(ed);
-		}
-		ed->ed_prev = ohci->ed_bulktail;
-		if (!ohci->ed_bulktail && !ohci->ed_rm_list[0] &&
-		    !ohci->ed_rm_list[1] && !ohci->sleeping) {
-			ohci->hc_control |= OHCI_CTRL_BLE;
-			writel(ohci->hc_control, &ohci->regs->control);
-		}
-		ohci->ed_bulktail = edi;
-		break;
-	}
-	return 0;
-}
-
-/*-------------------------------------------------------------------------*/
-
-/* unlink an ed from one of the HC chains.
- * just the link to the ed is unlinked.
- * the link from the ed still points to another operational ed or 0
- * so the HC can eventually finish the processing of the unlinked ed */
-
-static int ep_unlink(struct ohci *ohci, struct ed *ed)
-{
-	struct ed *next;
-	ed->hwINFO |= m32_swap(OHCI_ED_SKIP);
-
-	switch (ed->type) {
-	case PIPE_CONTROL:
-		if (ed->ed_prev == NULL) {
-			if (!ed->hwNextED) {
-				ohci->hc_control &= ~OHCI_CTRL_CLE;
-				writel(ohci->hc_control, &ohci->regs->control);
-			}
-			writel(m32_swap(*((__u32 *) &ed->hwNextED)),
-			       &ohci->regs->ed_controlhead);
-		} else {
-			ed->ed_prev->hwNextED = ed->hwNextED;
-		}
-		if (ohci->ed_controltail == ed) {
-			ohci->ed_controltail = ed->ed_prev;
-		} else {
-			next = (struct ed *)m32_swap(*((__u32 *)&ed->hwNextED));
-			next->ed_prev = ed->ed_prev;
-		}
-		break;
-
-	case PIPE_BULK:
-		if (ed->ed_prev == NULL) {
-			if (!ed->hwNextED) {
-				ohci->hc_control &= ~OHCI_CTRL_BLE;
-				writel(ohci->hc_control, &ohci->regs->control);
-			}
-			writel(m32_swap(*((__u32 *) &ed->hwNextED)),
-			       &ohci->regs->ed_bulkhead);
-		} else {
-			ed->ed_prev->hwNextED = ed->hwNextED;
-		}
-		if (ohci->ed_bulktail == ed) {
-			ohci->ed_bulktail = ed->ed_prev;
-		} else {
-			next = (struct ed *)m32_swap(*((__u32 *)&ed->hwNextED));
-			next->ed_prev = ed->ed_prev;
-		}
-		break;
-	}
-	ed->state = ED_UNLINK;
-	return 0;
-}
-
-/*-------------------------------------------------------------------------*/
-
-/* add/reinit an endpoint; this should be done once at the usb_set_configuration
- * command, but the USB stack is a little bit stateless  so we do it at every
- * transaction. If the state of the ed is ED_NEW then a dummy td is added and
- * the state is changed to ED_UNLINK. In all other cases the state is left
- * unchanged. The ed info fields are setted anyway even though most of them
- * should not change */
-
-static struct ed *ep_add_ed(struct usb_device *usb_dev, unsigned long pipe)
-{
-	struct td *td;
-	struct ed *ed_ret;
-	struct ed *ed;
-
-	ed = ed_ret = &ohci_dev.ed[(usb_pipeendpoint(pipe) << 1) |
-				   (usb_pipecontrol(pipe) ? 0 :
-				    usb_pipeout(pipe))];
-
-	if ((ed->state & ED_DEL) || (ed->state & ED_URB_DEL)) {
-		err("ep_add_ed: pending delete");
-		/* pending delete request */
-		return NULL;
-	}
-
-	if (ed->state == ED_NEW) {
-		ed->hwINFO = m32_swap(OHCI_ED_SKIP);	/* skip ed */
-		/* dummy td; end of td list for ed */
-		td = td_alloc(usb_dev);
-		ed->hwTailP = (__u32) m32_swap(td);
-		ed->hwHeadP = ed->hwTailP;
-		ed->state = ED_UNLINK;
-		ed->type = usb_pipetype(pipe);
-		ohci_dev.ed_cnt++;
-	}
-
-	ed->hwINFO = m32_swap(usb_pipedevice(pipe)
-			      | usb_pipeendpoint(pipe) << 7
-			      | (usb_pipeisoc(pipe) ? 0x8000 : 0)
-			      | (usb_pipecontrol(pipe) ? 0 :
-				 (usb_pipeout(pipe) ? 0x800 : 0x1000))
-			      | usb_pipeslow(pipe) << 13 |
-			      usb_maxpacket(usb_dev, pipe) << 16);
-
-	return ed_ret;
-}
-
-/*-------------------------------------------------------------------------*
- * TD handling functions
- *-------------------------------------------------------------------------*/
-
-/* enqueue next TD for this URB (OHCI spec 5.2.8.2) */
-
-static void td_fill(struct ohci *ohci, unsigned int info, void *data, int len,
-		    struct usb_device *dev, int index,
-		    struct urb_priv *urb_priv)
-{
-	struct td *td, *td_pt;
-#ifdef OHCI_FILL_TRACE
-	int i;
-#endif
-
-	if (index > urb_priv->length) {
-		err("index > length");
-		return;
-	}
-	/* use this td as the next dummy */
-	td_pt = urb_priv->td[index];
-	td_pt->hwNextTD = 0;
-
-	/* fill the old dummy TD */
-	td = urb_priv->td[index] =
-	    (struct td *) (m32_swap(urb_priv->ed->hwTailP) & ~0xf);
-
-	td->ed = urb_priv->ed;
-	td->next_dl_td = NULL;
-	td->index = index;
-	td->data = (__u32) data;
-#ifdef OHCI_FILL_TRACE
-	if (usb_pipebulk(urb_priv->pipe) && usb_pipeout(urb_priv->pipe)) {
-		for (i = 0; i < len; i++)
-			printf("td->data[%d] %#2x ", i,
-			       ((unsigned char *)td->data)[i]);
-		printf("\n");
-	}
-#endif
-	if (!len)
-		data = 0;
-
-	td->hwINFO = (__u32) m32_swap(info);
-	td->hwCBP = (__u32) m32_swap(data);
-	if (data)
-		td->hwBE = (__u32) m32_swap(data + len - 1);
-	else
-		td->hwBE = 0;
-	td->hwNextTD = (__u32) m32_swap(td_pt);
-
-	/* append to queue */
-	td->ed->hwTailP = td->hwNextTD;
-}
-
-/*-------------------------------------------------------------------------*/
-
-/* prepare all TDs of a transfer */
-
-static void td_submit_job(struct usb_device *dev, unsigned long pipe,
-			  void *buffer, int transfer_len,
-			  struct devrequest *setup, struct urb_priv *urb,
-			  int interval)
-{
-	struct ohci *ohci = &gohci;
-	int data_len = transfer_len;
-	void *data;
-	int cnt = 0;
-	__u32 info = 0;
-	unsigned int toggle = 0;
-
-	/* OHCI handles the DATA-toggles itself, we just
-	   use the USB-toggle bits for reseting */
-	if (usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe))) {
-		toggle = TD_T_TOGGLE;
-	} else {
-		toggle = TD_T_DATA0;
-		usb_settoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe),
-			      1);
-	}
-	urb->td_cnt = 0;
-	if (data_len)
-		data = buffer;
-	else
-		data = 0;
-
-	switch (usb_pipetype(pipe)) {
-	case PIPE_BULK:
-		info = usb_pipeout(pipe) ? TD_CC | TD_DP_OUT : TD_CC | TD_DP_IN;
-		while (data_len > 4096) {
-			td_fill(ohci, info | (cnt ? TD_T_TOGGLE : toggle), data,
-				4096, dev, cnt, urb);
-			data += 4096;
-			data_len -= 4096;
-			cnt++;
-		}
-		info = usb_pipeout(pipe) ?
-				TD_CC | TD_DP_OUT :
-				TD_CC | TD_R | TD_DP_IN;
-		td_fill(ohci, info | (cnt ? TD_T_TOGGLE : toggle), data,
-			data_len, dev, cnt, urb);
-		cnt++;
-
-		if (!ohci->sleeping)
-			/* start bulk list */
-			writel(OHCI_BLF, &ohci->regs->cmdstatus);
-		break;
-
-	case PIPE_CONTROL:
-		info = TD_CC | TD_DP_SETUP | TD_T_DATA0;
-		td_fill(ohci, info, setup, 8, dev, cnt++, urb);
-		if (data_len > 0) {
-			info = usb_pipeout(pipe) ?
-			    TD_CC | TD_R | TD_DP_OUT | TD_T_DATA1 :
-			    TD_CC | TD_R | TD_DP_IN | TD_T_DATA1;
-			/* NOTE:  mishandles transfers >8K, some >4K */
-			td_fill(ohci, info, data, data_len, dev, cnt++, urb);
-		}
-		info = usb_pipeout(pipe) ?
-		    TD_CC | TD_DP_IN | TD_T_DATA1 :
-		    TD_CC | TD_DP_OUT | TD_T_DATA1;
-		td_fill(ohci, info, data, 0, dev, cnt++, urb);
-		if (!ohci->sleeping)
-			/* start Control list */
-			writel(OHCI_CLF, &ohci->regs->cmdstatus);
-		break;
-	}
-	if (urb->length != cnt)
-		dbg("TD LENGTH %d != CNT %d", urb->length, cnt);
-}
-
-/*-------------------------------------------------------------------------*
- * Done List handling functions
- *-------------------------------------------------------------------------*/
-
-
-/* calculate the transfer length and update the urb */
-
-static void dl_transfer_length(struct td *td)
-{
-	__u32 tdINFO, tdBE, tdCBP;
-	struct urb_priv *lurb_priv = &urb_priv;
-
-	tdINFO = m32_swap(td->hwINFO);
-	tdBE = m32_swap(td->hwBE);
-	tdCBP = m32_swap(td->hwCBP);
-
-	if (!(usb_pipecontrol(lurb_priv->pipe) &&
-	      ((td->index == 0) || (td->index == lurb_priv->length - 1)))) {
-		if (tdBE != 0) {
-			if (td->hwCBP == 0)
-				lurb_priv->actual_length += tdBE - td->data + 1;
-			else
-				lurb_priv->actual_length += tdCBP - td->data;
-		}
-	}
-}
-
-/*-------------------------------------------------------------------------*/
-
-/* replies to the request have to be on a FIFO basis so
- * we reverse the reversed done-list */
-
-static struct td *dl_reverse_done_list(struct ohci *ohci)
-{
-	__u32 td_list_hc;
-	__u32 tmp;
-	struct td *td_rev = NULL;
-	struct td *td_list = NULL;
-	struct urb_priv *lurb_priv = NULL;
-
-	td_list_hc = m32_swap(ohci->hcca->done_head) & 0xfffffff0;
-	ohci->hcca->done_head = 0;
-
-	while (td_list_hc) {
-		td_list = (struct td *) td_list_hc;
-
-		if (TD_CC_GET(m32_swap(td_list->hwINFO))) {
-			lurb_priv = &urb_priv;
-			dbg(" USB-error/status: %x : %p",
-			    TD_CC_GET(m32_swap(td_list->hwINFO)), td_list);
-			if (td_list->ed->hwHeadP & m32_swap(0x1)) {
-				if (lurb_priv &&
-				    ((td_list->index+1) < lurb_priv->length)) {
-					tmp = lurb_priv->length - 1;
-					td_list->ed->hwHeadP =
-						(lurb_priv->td[tmp]->hwNextTD &
-						 m32_swap(0xfffffff0)) |
-						 (td_list->ed->hwHeadP &
-						  m32_swap(0x2));
-					lurb_priv->td_cnt += lurb_priv->length -
-							     td_list->index - 1;
-				} else
-					td_list->ed->hwHeadP &=
-					    m32_swap(0xfffffff2);
-			}
-		}
-
-		td_list->next_dl_td = td_rev;
-		td_rev = td_list;
-		td_list_hc = m32_swap(td_list->hwNextTD) & 0xfffffff0;
-	}
-
-	return td_list;
-}
-
-/*-------------------------------------------------------------------------*/
-
-/* td done list */
-static int dl_done_list(struct ohci *ohci, struct td *td_list)
-{
-	struct td *td_list_next = NULL;
-	struct ed *ed;
-	int cc = 0;
-	int stat = 0;
-	/* urb_t *urb; */
-	struct urb_priv *lurb_priv;
-	__u32 tdINFO, edHeadP, edTailP;
-
-	while (td_list) {
-		td_list_next = td_list->next_dl_td;
-
-		lurb_priv = &urb_priv;
-		tdINFO = m32_swap(td_list->hwINFO);
-
-		ed = td_list->ed;
-
-		dl_transfer_length(td_list);
-
-		/* error code of transfer */
-		cc = TD_CC_GET(tdINFO);
-		if (cc != 0) {
-			dbg("ConditionCode %#x", cc);
-			stat = cc_to_error[cc];
-		}
-
-		/* see if this done list makes for all TD's of current URB,
-		 * and mark the URB finished if so */
-		if (++(lurb_priv->td_cnt) == lurb_priv->length) {
-			if ((ed->state & (ED_OPER | ED_UNLINK)))
-				urb_finished = 1;
-			else
-				dbg("dl_done_list: strange.., ED state %x, "
-				    "ed->state\n");
-		} else
-			dbg("dl_done_list: processing TD %x, len %x\n",
-			    lurb_priv->td_cnt, lurb_priv->length);
-
-		if (ed->state != ED_NEW) {
-			edHeadP = m32_swap(ed->hwHeadP) & 0xfffffff0;
-			edTailP = m32_swap(ed->hwTailP);
-
-			/* unlink eds if they are not busy */
-			if ((edHeadP == edTailP) && (ed->state == ED_OPER))
-				ep_unlink(ohci, ed);
-		}
-
-		td_list = td_list_next;
-	}
-	return stat;
-}
-
-/*-------------------------------------------------------------------------*
- * Virtual Root Hub
- *-------------------------------------------------------------------------*/
-
-/* Device descriptor */
-static __u8 root_hub_dev_des[] = {
-	0x12,	/*  __u8  bLength; */
-	0x01,	/*  __u8  bDescriptorType; Device */
-	0x10,	/*  __u16 bcdUSB; v1.1 */
-	0x01,
-	0x09,	/*  __u8  bDeviceClass; HUB_CLASSCODE */
-	0x00,	/*  __u8  bDeviceSubClass; */
-	0x00,	/*  __u8  bDeviceProtocol; */
-	0x08,	/*  __u8  bMaxPacketSize0; 8 Bytes */
-	0x00,	/*  __u16 idVendor; */
-	0x00,
-	0x00,	/*  __u16 idProduct; */
-	0x00,
-	0x00,	/*  __u16 bcdDevice; */
-	0x00,
-	0x00,	/*  __u8  iManufacturer; */
-	0x01,	/*  __u8  iProduct; */
-	0x00,	/*  __u8  iSerialNumber; */
-	0x01	/*  __u8  bNumConfigurations; */
-};
-
-/* Configuration descriptor */
-static __u8 root_hub_config_des[] = {
-	0x09,	/*  __u8  bLength; */
-	0x02,	/*  __u8  bDescriptorType; Configuration */
-	0x19,	/*  __u16 wTotalLength; */
-	0x00,
-	0x01,	/*  __u8  bNumInterfaces; */
-	0x01,	/*  __u8  bConfigurationValue; */
-	0x00,	/*  __u8  iConfiguration; */
-	0x40,	/*  __u8  bmAttributes;
-		   Bit 7: Bus-powered, 6: Self-powered,
-		   5 Remote-wakwup, 4..0: resvd */
-	0x00,	/*  __u8  MaxPower; */
-
-	/* interface */
-	0x09,	/*  __u8  if_bLength; */
-	0x04,	/*  __u8  if_bDescriptorType; Interface */
-	0x00,	/*  __u8  if_bInterfaceNumber; */
-	0x00,	/*  __u8  if_bAlternateSetting; */
-	0x01,	/*  __u8  if_bNumEndpoints; */
-	0x09,	/*  __u8  if_bInterfaceClass; HUB_CLASSCODE */
-	0x00,	/*  __u8  if_bInterfaceSubClass; */
-	0x00,	/*  __u8  if_bInterfaceProtocol; */
-	0x00,	/*  __u8  if_iInterface; */
-
-	/* endpoint */
-	0x07,	/*  __u8  ep_bLength; */
-	0x05,	/*  __u8  ep_bDescriptorType; Endpoint */
-	0x81,	/*  __u8  ep_bEndpointAddress; IN Endpoint 1 */
-	0x03,	/*  __u8  ep_bmAttributes; Interrupt */
-	0x02,	/*  __u16 ep_wMaxPacketSize; ((MAX_ROOT_PORTS + 1) / 8 */
-	0x00,
-	0xff	/*  __u8  ep_bInterval; 255 ms */
-};
-
-static unsigned char root_hub_str_index0[] = {
-	0x04,	/*  __u8  bLength; */
-	0x03,	/*  __u8  bDescriptorType; String-descriptor */
-	0x09,	/*  __u8  lang ID */
-	0x04,	/*  __u8  lang ID */
-};
-
-static unsigned char root_hub_str_index1[] = {
-	28,	/*  __u8  bLength; */
-	0x03,	/*  __u8  bDescriptorType; String-descriptor */
-	'O',	/*  __u8  Unicode */
-	0,	/*  __u8  Unicode */
-	'H',	/*  __u8  Unicode */
-	0,	/*  __u8  Unicode */
-	'C',	/*  __u8  Unicode */
-	0,	/*  __u8  Unicode */
-	'I',	/*  __u8  Unicode */
-	0,	/*  __u8  Unicode */
-	' ',	/*  __u8  Unicode */
-	0,	/*  __u8  Unicode */
-	'R',	/*  __u8  Unicode */
-	0,	/*  __u8  Unicode */
-	'o',	/*  __u8  Unicode */
-	0,	/*  __u8  Unicode */
-	'o',	/*  __u8  Unicode */
-	0,	/*  __u8  Unicode */
-	't',	/*  __u8  Unicode */
-	0,	/*  __u8  Unicode */
-	' ',	/*  __u8  Unicode */
-	0,	/*  __u8  Unicode */
-	'H',	/*  __u8  Unicode */
-	0,	/*  __u8  Unicode */
-	'u',	/*  __u8  Unicode */
-	0,	/*  __u8  Unicode */
-	'b',	/*  __u8  Unicode */
-	0,	/*  __u8  Unicode */
-};
-
-/* Hub class-specific descriptor is constructed dynamically */
-
-
-/*-------------------------------------------------------------------------*/
-
-#define OK(x)			len = (x); break
-#ifdef DEBUG
-#define WR_RH_STAT(x) \
-{ \
-	info("WR:status %#8x", (x)); \
-	writel((x), &gohci.regs->roothub.status); \
-}
-#define WR_RH_PORTSTAT(x) \
-{ \
-	info("WR:portstatus[%d] %#8x", wIndex-1, (x)); \
-	writel((x), &gohci.regs->roothub.portstatus[wIndex-1]); \
-}
-#else
-#define WR_RH_STAT(x) \
-	writel((x), &gohci.regs->roothub.status)
-#define WR_RH_PORTSTAT(x)\
-	writel((x), &gohci.regs->roothub.portstatus[wIndex-1])
-#endif
-#define RD_RH_STAT	roothub_status(&gohci)
-#define RD_RH_PORTSTAT	roothub_portstatus(&gohci, wIndex-1)
-
-/* request to virtual root hub */
-
-int rh_check_port_status(struct ohci *controller)
-{
-	__u32 temp, ndp, i;
-	int res;
-
-	res = -1;
-	temp = roothub_a(controller);
-	ndp = (temp & RH_A_NDP);
-	for (i = 0; i < ndp; i++) {
-		temp = roothub_portstatus(controller, i);
-		/* check for a device disconnect */
-		if (((temp & (RH_PS_PESC | RH_PS_CSC)) ==
-		     (RH_PS_PESC | RH_PS_CSC)) && ((temp & RH_PS_CCS) == 0)) {
-			res = i;
-			break;
-		}
-	}
-	return res;
-}
-
-static int ohci_submit_rh_msg(struct usb_device *dev, unsigned long pipe,
-			      void *buffer, int transfer_len,
-			      struct devrequest *cmd)
-{
-	void *data = buffer;
-	int leni = transfer_len;
-	int len = 0;
-	int stat = 0;
-	__u32 datab[4];
-	__u8 *data_buf = (__u8 *) datab;
-	__u16 bmRType_bReq;
-	__u16 wValue;
-	__u16 wIndex;
-	__u16 wLength;
-
-#ifdef DEBUG
-	urb_priv.actual_length = 0;
-	pkt_print(dev, pipe, buffer, transfer_len, cmd, "SUB(rh)",
-		  usb_pipein(pipe));
-#else
-	wait_ms(1);
-#endif
-	if (usb_pipeint(pipe)) {
-		info("Root-Hub submit IRQ: NOT implemented");
-		return 0;
-	}
-
-	bmRType_bReq = cmd->requesttype | (cmd->request << 8);
-	wValue = m16_swap(cmd->value);
-	wIndex = m16_swap(cmd->index);
-	wLength = m16_swap(cmd->length);
-
-	info("Root-Hub: adr: %2x cmd(%1x): %08x %04x %04x %04x",
-	     dev->devnum, 8, bmRType_bReq, wValue, wIndex, wLength);
-
-	switch (bmRType_bReq) {
-		/* Request Destination:
-		   without flags: Device,
-		   RH_INTERFACE: interface,
-		   RH_ENDPOINT: endpoint,
-		   RH_CLASS means HUB here,
-		   RH_OTHER | RH_CLASS  almost ever means HUB_PORT here
-		 */
-
-	case RH_GET_STATUS:
-		*(__u16 *) data_buf = m16_swap(1);
-		OK(2);
-	case RH_GET_STATUS | RH_INTERFACE:
-		*(__u16 *) data_buf = m16_swap(0);
-		OK(2);
-	case RH_GET_STATUS | RH_ENDPOINT:
-		*(__u16 *) data_buf = m16_swap(0);
-		OK(2);
-	case RH_GET_STATUS | RH_CLASS:
-		*(__u32 *) data_buf =
-		    m32_swap(RD_RH_STAT & ~(RH_HS_CRWE | RH_HS_DRWE));
-		OK(4);
-	case RH_GET_STATUS | RH_OTHER | RH_CLASS:
-		*(__u32 *) data_buf = m32_swap(RD_RH_PORTSTAT);
-		OK(4);
-
-	case RH_CLEAR_FEATURE | RH_ENDPOINT:
-		switch (wValue) {
-		case (RH_ENDPOINT_STALL):
-			OK(0);
-		}
-		break;
-
-	case RH_CLEAR_FEATURE | RH_CLASS:
-		switch (wValue) {
-		case RH_C_HUB_LOCAL_POWER:
-			OK(0);
-		case (RH_C_HUB_OVER_CURRENT):
-			WR_RH_STAT(RH_HS_OCIC);
-			OK(0);
-		}
-		break;
-
-	case RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS:
-		switch (wValue) {
-		case (RH_PORT_ENABLE):
-			WR_RH_PORTSTAT(RH_PS_CCS);
-			OK(0);
-		case (RH_PORT_SUSPEND):
-			WR_RH_PORTSTAT(RH_PS_POCI);
-			OK(0);
-		case (RH_PORT_POWER):
-			WR_RH_PORTSTAT(RH_PS_LSDA);
-			OK(0);
-		case (RH_C_PORT_CONNECTION):
-			WR_RH_PORTSTAT(RH_PS_CSC);
-			OK(0);
-		case (RH_C_PORT_ENABLE):
-			WR_RH_PORTSTAT(RH_PS_PESC);
-			OK(0);
-		case (RH_C_PORT_SUSPEND):
-			WR_RH_PORTSTAT(RH_PS_PSSC);
-			OK(0);
-		case (RH_C_PORT_OVER_CURRENT):
-			WR_RH_PORTSTAT(RH_PS_OCIC);
-			OK(0);
-		case (RH_C_PORT_RESET):
-			WR_RH_PORTSTAT(RH_PS_PRSC);
-			OK(0);
-		}
-		break;
-
-	case RH_SET_FEATURE | RH_OTHER | RH_CLASS:
-		switch (wValue) {
-		case (RH_PORT_SUSPEND):
-			WR_RH_PORTSTAT(RH_PS_PSS);
-			OK(0);
-		case (RH_PORT_RESET):	/* BUG IN HUP CODE ******** */
-			if (RD_RH_PORTSTAT & RH_PS_CCS)
-				WR_RH_PORTSTAT(RH_PS_PRS);
-			OK(0);
-		case (RH_PORT_POWER):
-			WR_RH_PORTSTAT(RH_PS_PPS);
-			OK(0);
-		case (RH_PORT_ENABLE):	/* BUG IN HUP CODE ******** */
-			if (RD_RH_PORTSTAT & RH_PS_CCS)
-				WR_RH_PORTSTAT(RH_PS_PES);
-			OK(0);
-		}
-		break;
-
-	case RH_SET_ADDRESS:
-		gohci.rh.devnum = wValue;
-		OK(0);
-
-	case RH_GET_DESCRIPTOR:
-		switch ((wValue & 0xff00) >> 8) {
-		case (0x01):	/* device descriptor */
-			len = min_t(unsigned int,
-				    leni,
-				    min_t(unsigned int,
-					  sizeof(root_hub_dev_des), wLength));
-			data_buf = root_hub_dev_des;
-			OK(len);
-		case (0x02):	/* configuration descriptor */
-			len = min_t(unsigned int,
-				    leni,
-				    min_t(unsigned int,
-					  sizeof(root_hub_config_des),
-					  wLength));
-			data_buf = root_hub_config_des;
-			OK(len);
-		case (0x03):	/* string descriptors */
-			if (wValue == 0x0300) {
-				len = min_t(unsigned int,
-					    leni,
-					    min_t(unsigned int,
-						  sizeof(root_hub_str_index0),
-						  wLength));
-				data_buf = root_hub_str_index0;
-				OK(len);
-			}
-			if (wValue == 0x0301) {
-				len = min_t(unsigned int,
-					    leni,
-					    min_t(unsigned int,
-						  sizeof(root_hub_str_index1),
-						  wLength));
-				data_buf = root_hub_str_index1;
-				OK(len);
-			}
-		default:
-			stat = USB_ST_STALLED;
-		}
-		break;
-
-	case RH_GET_DESCRIPTOR | RH_CLASS:
-		{
-			__u32 temp = roothub_a(&gohci);
-
-			data_buf[0] = 9;	/* min length; */
-			data_buf[1] = 0x29;
-			data_buf[2] = temp & RH_A_NDP;
-			data_buf[3] = 0;
-			if (temp & RH_A_PSM)
-				/* per-port power switching? */
-				data_buf[3] |= 0x1;
-			if (temp & RH_A_NOCP)
-				/* no overcurrent reporting? */
-				data_buf[3] |= 0x10;
-			else if (temp & RH_A_OCPM)
-				/* per-port overcurrent reporting? */
-				data_buf[3] |= 0x8;
-
-			/* corresponds to data_buf[4-7] */
-			datab[1] = 0;
-			data_buf[5] = (temp & RH_A_POTPGT) >> 24;
-			temp = roothub_b(&gohci);
-			data_buf[7] = temp & RH_B_DR;
-			if (data_buf[2] < 7) {
-				data_buf[8] = 0xff;
-			} else {
-				data_buf[0] += 2;
-				data_buf[8] = (temp & RH_B_DR) >> 8;
-				data_buf[10] = data_buf[9] = 0xff;
-			}
-
-			len = min_t(unsigned int, leni,
-				    min_t(unsigned int, data_buf[0], wLength));
-			OK(len);
-		}
-
-	case RH_GET_CONFIGURATION:
-		*(__u8 *) data_buf = 0x01;
-		OK(1);
-
-	case RH_SET_CONFIGURATION:
-		WR_RH_STAT(0x10000);
-		OK(0);
-
-	default:
-		dbg("unsupported root hub command");
-		stat = USB_ST_STALLED;
-	}
-
-#ifdef	DEBUG
-	ohci_dump_roothub(&gohci, 1);
-#else
-	wait_ms(1);
-#endif
-
-	len = min_t(int, len, leni);
-	if (data != data_buf)
-		memcpy(data, data_buf, len);
-	dev->act_len = len;
-	dev->status = stat;
-
-#ifdef DEBUG
-	if (transfer_len)
-		urb_priv.actual_length = transfer_len;
-	pkt_print(dev, pipe, buffer, transfer_len, cmd, "RET(rh)",
-		  0 /*usb_pipein(pipe) */);
-#else
-	wait_ms(1);
-#endif
-
-	return stat;
-}
-
-/*-------------------------------------------------------------------------*/
-
-/* common code for handling submit messages - used for all but root hub */
-/* accesses. */
-int submit_common_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
-		      int transfer_len, struct devrequest *setup, int interval)
-{
-	int stat = 0;
-	int maxsize = usb_maxpacket(dev, pipe);
-	int timeout;
-
-	/* device pulled? Shortcut the action. */
-	if (devgone == dev) {
-		dev->status = USB_ST_CRC_ERR;
-		return 0;
-	}
-#ifdef DEBUG
-	urb_priv.actual_length = 0;
-	pkt_print(dev, pipe, buffer, transfer_len, setup, "SUB",
-		  usb_pipein(pipe));
-#else
-	wait_ms(1);
-#endif
-	if (!maxsize) {
-		err("submit_common_message: pipesize for pipe %lx is zero",
-		    pipe);
-		return -1;
-	}
-
-	if (sohci_submit_job(dev, pipe, buffer, transfer_len, setup, interval) <
-	    0) {
-		err("sohci_submit_job failed");
-		return -1;
-	}
-
-	wait_ms(10);
-	/* ohci_dump_status(&gohci); */
-
-	/* allow more time for a BULK device to react - some are slow */
-#define BULK_TO	 5000		/* timeout in milliseconds */
-	if (usb_pipebulk(pipe))
-		timeout = BULK_TO;
-	else
-		timeout = 100;
-
-	/* wait for it to complete */
-	for (;;) {
-		/* check whether the controller is done */
-		stat = hc_interrupt();
-
-		if (stat < 0) {
-			stat = USB_ST_CRC_ERR;
-			break;
-		}
-
-		/* NOTE: since we are not interrupt driven in U-Boot and always
-		 * handle only one URB at a time, we cannot assume the
-		 * transaction finished on the first successful return from
-		 * hc_interrupt().. unless the flag for current URB is set,
-		 * meaning that all TD's to/from device got actually
-		 * transferred and processed. If the current URB is not
-		 * finished we need to re-iterate this loop so as
-		 * hc_interrupt() gets called again as there needs to be some
-		 * more TD's to process still */
-		if ((stat >= 0) && (stat != 0xff) && (urb_finished)) {
-			/* 0xff is returned for an SF-interrupt */
-			break;
-		}
-
-		if (--timeout) {
-			wait_ms(1);
-			if (!urb_finished)
-				dbg("\%");
-
-		} else {
-			err("CTL:TIMEOUT ");
-			dbg("submit_common_msg: TO status %x\n", stat);
-			stat = USB_ST_CRC_ERR;
-			urb_finished = 1;
-			break;
-		}
-	}
-
-#if 0
-	/* we got an Root Hub Status Change interrupt */
-	if (got_rhsc) {
-#ifdef DEBUG
-		ohci_dump_roothub(&gohci, 1);
-#endif
-		got_rhsc = 0;
-		/* abuse timeout */
-		timeout = rh_check_port_status(&gohci);
-		if (timeout >= 0) {
-#if 0			/* this does nothing useful, but leave it here
-			   in case that changes */
-			/* the called routine adds 1 to the passed value */
-			usb_hub_port_connect_change(gohci.rh.dev, timeout - 1);
-#endif
-			/*
-			 * XXX
-			 * This is potentially dangerous because it assumes
-			 * that only one device is ever plugged in!
-			 */
-			devgone = dev;
-		}
-	}
-#endif
-
-	dev->status = stat;
-	dev->act_len = transfer_len;
-
-#ifdef DEBUG
-	pkt_print(dev, pipe, buffer, transfer_len, setup, "RET(ctlr)",
-		  usb_pipein(pipe));
-#else
-	wait_ms(1);
-#endif
-
-	/* free TDs in urb_priv */
-	urb_free_priv(&urb_priv);
-	return 0;
-}
-
-/* submit routines called from usb.c */
-int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
-		    int transfer_len)
-{
-	info("submit_bulk_msg");
-	return submit_common_msg(dev, pipe, buffer, transfer_len, NULL, 0);
-}
-
-int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
-		       int transfer_len, struct devrequest *setup)
-{
-	int maxsize = usb_maxpacket(dev, pipe);
-
-	info("submit_control_msg");
-#ifdef DEBUG
-	urb_priv.actual_length = 0;
-	pkt_print(dev, pipe, buffer, transfer_len, setup, "SUB",
-		  usb_pipein(pipe));
-#else
-	wait_ms(1);
-#endif
-	if (!maxsize) {
-		err("submit_control_message: pipesize for pipe %lx is zero",
-		    pipe);
-		return -1;
-	}
-	if (((pipe >> 8) & 0x7f) == gohci.rh.devnum) {
-		gohci.rh.dev = dev;
-		/* root hub - redirect */
-		return ohci_submit_rh_msg(dev, pipe, buffer, transfer_len,
-					  setup);
-	}
-
-	return submit_common_msg(dev, pipe, buffer, transfer_len, setup, 0);
-}
-
-int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
-		   int transfer_len, int interval)
-{
-	info("submit_int_msg");
-	return -1;
-}
-
-/*-------------------------------------------------------------------------*
- * HC functions
- *-------------------------------------------------------------------------*/
-
-/* reset the HC and BUS */
-
-static int hc_reset(struct ohci *ohci)
-{
-	int timeout = 30;
-	int smm_timeout = 50;	/* 0,5 sec */
-
-	if (readl(&ohci->regs->control) & OHCI_CTRL_IR) {
-		/* SMM owns the HC - request ownership */
-		writel(OHCI_OCR, &ohci->regs->cmdstatus);
-		info("USB HC TakeOver from SMM");
-		while (readl(&ohci->regs->control) & OHCI_CTRL_IR) {
-			wait_ms(10);
-			if (--smm_timeout == 0) {
-				err("USB HC TakeOver failed!");
-				return -1;
-			}
-		}
-	}
-
-	/* Disable HC interrupts */
-	writel(OHCI_INTR_MIE, &ohci->regs->intrdisable);
-
-	dbg("USB HC reset_hc usb-%s: ctrl = 0x%X ;",
-	    ohci->slot_name, readl(&ohci->regs->control));
-
-	/* Reset USB (needed by some controllers) */
-	writel(0, &ohci->regs->control);
-
-	/* HC Reset requires max 10 us delay */
-	writel(OHCI_HCR, &ohci->regs->cmdstatus);
-	while ((readl(&ohci->regs->cmdstatus) & OHCI_HCR) != 0) {
-		if (--timeout == 0) {
-			err("USB HC reset timed out!");
-			return -1;
-		}
-		udelay(1);
-	}
-	return 0;
-}
-
-/*-------------------------------------------------------------------------*/
-
-/* Start an OHCI controller, set the BUS operational
- * enable interrupts
- * connect the virtual root hub */
-
-static int hc_start(struct ohci *ohci)
-{
-	__u32 mask;
-	unsigned int fminterval;
-
-	ohci->disabled = 1;
-
-	/* Tell the controller where the control and bulk lists are
-	 * The lists are empty now. */
-
-	writel(0, &ohci->regs->ed_controlhead);
-	writel(0, &ohci->regs->ed_bulkhead);
-
-	/* a reset clears this */
-	writel((__u32) ohci->hcca, &ohci->regs->hcca);
-
-	fminterval = 0x2edf;
-	writel((fminterval * 9) / 10, &ohci->regs->periodicstart);
-	fminterval |= ((((fminterval - 210) * 6) / 7) << 16);
-	writel(fminterval, &ohci->regs->fminterval);
-	writel(0x628, &ohci->regs->lsthresh);
-
-	/* start controller operations */
-	ohci->hc_control = OHCI_CONTROL_INIT | OHCI_USB_OPER;
-	ohci->disabled = 0;
-	writel(ohci->hc_control, &ohci->regs->control);
-
-	/* disable all interrupts */
-	mask = (OHCI_INTR_SO | OHCI_INTR_WDH | OHCI_INTR_SF | OHCI_INTR_RD |
-		OHCI_INTR_UE | OHCI_INTR_FNO | OHCI_INTR_RHSC |
-		OHCI_INTR_OC | OHCI_INTR_MIE);
-	writel(mask, &ohci->regs->intrdisable);
-	/* clear all interrupts */
-	mask &= ~OHCI_INTR_MIE;
-	writel(mask, &ohci->regs->intrstatus);
-	/* Choose the interrupts we care about now  - but w/o MIE */
-	mask = OHCI_INTR_RHSC | OHCI_INTR_UE | OHCI_INTR_WDH | OHCI_INTR_SO;
-	writel(mask, &ohci->regs->intrenable);
-
-#ifdef	OHCI_USE_NPS
-	/* required for AMD-756 and some Mac platforms */
-	writel((roothub_a(ohci) | RH_A_NPS) & ~RH_A_PSM,
-	       &ohci->regs->roothub.a);
-	writel(RH_HS_LPSC, &ohci->regs->roothub.status);
-#endif /* OHCI_USE_NPS */
-
-#define mdelay(n) ({unsigned long msec=(n); while (msec--) udelay(1000);})
-	/* POTPGT delay is bits 24-31, in 2 ms units. */
-	mdelay((roothub_a(ohci) >> 23) & 0x1fe);
-
-	/* connect the virtual root hub */
-	ohci->rh.devnum = 0;
-
-	return 0;
-}
-
-/*-------------------------------------------------------------------------*/
-
-/* an interrupt happens */
-
-static int hc_interrupt(void)
-{
-	struct ohci *ohci = &gohci;
-	struct ohci_regs *regs = ohci->regs;
-	int ints;
-	int stat = -1;
-
-	if ((ohci->hcca->done_head != 0) &&
-	    !(m32_swap(ohci->hcca->done_head) & 0x01)) {
-
-		ints = OHCI_INTR_WDH;
-
-	} else {
-		ints = readl(&regs->intrstatus);
-		if (ints == ~(u32) 0) {
-			ohci->disabled++;
-			err("%s device removed!", ohci->slot_name);
-			return -1;
-		}
-		ints &= readl(&regs->intrenable);
-		if (ints == 0) {
-			dbg("hc_interrupt: returning..\n");
-			return 0xff;
-		}
-	}
-
-	/* dbg("Interrupt: %x frame: %x", ints,
-	    le16_to_cpu(ohci->hcca->frame_no)); */
-
-	if (ints & OHCI_INTR_RHSC) {
-		got_rhsc = 1;
-		stat = 0xff;
-	}
-
-	if (ints & OHCI_INTR_UE) {
-		ohci->disabled++;
-		err("OHCI Unrecoverable Error, controller usb-%s disabled",
-		    ohci->slot_name);
-		/* e.g. due to PCI Master/Target Abort */
-
-#ifdef	DEBUG
-		ohci_dump(ohci, 1);
-#else
-		wait_ms(1);
-#endif
-		/* FIXME: be optimistic, hope that bug won't repeat often. */
-		/* Make some non-interrupt context restart the controller. */
-		/* Count and limit the retries though; either hardware or */
-		/* software errors can go forever... */
-		hc_reset(ohci);
-		return -1;
-	}
-
-	if (ints & OHCI_INTR_WDH) {
-		wait_ms(1);
-
-		writel(OHCI_INTR_WDH, &regs->intrdisable);
-		stat = dl_done_list(&gohci, dl_reverse_done_list(&gohci));
-		writel(OHCI_INTR_WDH, &regs->intrenable);
-	}
-
-	if (ints & OHCI_INTR_SO) {
-		dbg("USB Schedule overrun\n");
-		writel(OHCI_INTR_SO, &regs->intrenable);
-		stat = -1;
-	}
-
-	/* FIXME:  this assumes SOF (1/ms) interrupts don't get lost... */
-	if (ints & OHCI_INTR_SF) {
-		unsigned int frame = m16_swap(ohci->hcca->frame_no) & 1;
-		wait_ms(1);
-		writel(OHCI_INTR_SF, &regs->intrdisable);
-		if (ohci->ed_rm_list[frame] != NULL)
-			writel(OHCI_INTR_SF, &regs->intrenable);
-		stat = 0xff;
-	}
-
-	writel(ints, &regs->intrstatus);
-	return stat;
-}
-
-/*-------------------------------------------------------------------------*/
-
-/*-------------------------------------------------------------------------*/
-
-/* De-allocate all resources.. */
-
-static void hc_release_ohci(struct ohci *ohci)
-{
-	dbg("USB HC release ohci usb-%s", ohci->slot_name);
-
-	if (!ohci->disabled)
-		hc_reset(ohci);
-}
-
-/*-------------------------------------------------------------------------*/
-
-/*
- * low level initalisation routine, called from usb.c
- */
-static char ohci_inited = 0;
-
-int usb_lowlevel_init(void)
-{
-	struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
-	struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio();
-
-	/*
-	 * Set the 48 MHz UPLL clocking. Values are taken from
-	 * "PLL value selection guide", 6-23, s3c2400_UM.pdf.
-	 */
-	clk_power->upllcon = ((40 << 12) + (1 << 4) + 2);
-	gpio->misccr |= 0x8;	/* 1 = use pads related USB for USB host */
-
-	/*
-	 * Enable USB host clock.
-	 */
-	clk_power->clkcon |= (1 << 4);
-
-	memset(&gohci, 0, sizeof(struct ohci));
-	memset(&urb_priv, 0, sizeof(struct urb_priv));
-
-	/* align the storage */
-	if ((__u32) &ghcca[0] & 0xff) {
-		err("HCCA not aligned!!");
-		return -1;
-	}
-	phcca = &ghcca[0];
-	info("aligned ghcca %p", phcca);
-	memset(&ohci_dev, 0, sizeof(struct ohci_device));
-	if ((__u32) &ohci_dev.ed[0] & 0x7) {
-		err("EDs not aligned!!");
-		return -1;
-	}
-	memset(gtd, 0, sizeof(struct td) * (NUM_TD + 1));
-	if ((__u32) gtd & 0x7) {
-		err("TDs not aligned!!");
-		return -1;
-	}
-	ptd = gtd;
-	gohci.hcca = phcca;
-	memset(phcca, 0, sizeof(struct ohci_hcca));
-
-	gohci.disabled = 1;
-	gohci.sleeping = 0;
-	gohci.irq = -1;
-	gohci.regs = (struct ohci_regs *)S3C24X0_USB_HOST_BASE;
-
-	gohci.flags = 0;
-	gohci.slot_name = "s3c2400";
-
-	if (hc_reset(&gohci) < 0) {
-		hc_release_ohci(&gohci);
-		/* Initialization failed */
-		clk_power->clkcon &= ~(1 << 4);
-		return -1;
-	}
-
-	/* FIXME this is a second HC reset; why?? */
-	gohci.hc_control = OHCI_USB_RESET;
-	writel(gohci.hc_control, &gohci.regs->control);
-	wait_ms(10);
-
-	if (hc_start(&gohci) < 0) {
-		err("can't start usb-%s", gohci.slot_name);
-		hc_release_ohci(&gohci);
-		/* Initialization failed */
-		clk_power->clkcon &= ~(1 << 4);
-		return -1;
-	}
-#ifdef	DEBUG
-	ohci_dump(&gohci, 1);
-#else
-	wait_ms(1);
-#endif
-	ohci_inited = 1;
-	urb_finished = 1;
-
-	return 0;
-}
-
-int usb_lowlevel_stop(void)
-{
-	struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
-
-	/* this gets called really early - before the controller has */
-	/* even been initialized! */
-	if (!ohci_inited)
-		return 0;
-	/* TODO release any interrupts, etc. */
-	/* call hc_release_ohci() here ? */
-	hc_reset(&gohci);
-	/* may not want to do this */
-	clk_power->clkcon &= ~(1 << 4);
-	return 0;
-}
-
-#endif /* defined(CONFIG_USB_OHCI) && defined(CONFIG_S3C24X0) */
diff --git a/arch/arm/cpu/arm920t/s3c24x0/usb_ohci.h b/arch/arm/cpu/arm920t/s3c24x0/usb_ohci.h
deleted file mode 100644
index f272d78..0000000
--- a/arch/arm/cpu/arm920t/s3c24x0/usb_ohci.h
+++ /dev/null
@@ -1,409 +0,0 @@
-/*
- * URB OHCI HCD (Host Controller Driver) for USB.
- *
- * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
- * (C) Copyright 2000-2001 David Brownell <dbrownell@users.sourceforge.net>
- *
- * usb-ohci.h
- */
-
-
-static int cc_to_error[16] = {
-
-/* mapping of the OHCI CC status to error codes */
-	/* No  Error  */ 0,
-	/* CRC Error  */ USB_ST_CRC_ERR,
-	/* Bit Stuff  */ USB_ST_BIT_ERR,
-	/* Data Togg  */ USB_ST_CRC_ERR,
-	/* Stall      */ USB_ST_STALLED,
-	/* DevNotResp */ -1,
-	/* PIDCheck   */ USB_ST_BIT_ERR,
-	/* UnExpPID   */ USB_ST_BIT_ERR,
-	/* DataOver   */ USB_ST_BUF_ERR,
-	/* DataUnder  */ USB_ST_BUF_ERR,
-	/* reservd    */ -1,
-	/* reservd    */ -1,
-	/* BufferOver */ USB_ST_BUF_ERR,
-	/* BuffUnder  */ USB_ST_BUF_ERR,
-	/* Not Access */ -1,
-	/* Not Access */ -1
-};
-
-/* ED States */
-#define ED_NEW		0x00
-#define ED_UNLINK	0x01
-#define ED_OPER		0x02
-#define ED_DEL		0x04
-#define ED_URB_DEL	0x08
-
-/* usb_ohci_ed */
-struct ed {
-	__u32 hwINFO;
-	__u32 hwTailP;
-	__u32 hwHeadP;
-	__u32 hwNextED;
-
-	struct ed *ed_prev;
-	__u8 int_period;
-	__u8 int_branch;
-	__u8 int_load;
-	__u8 int_interval;
-	__u8 state;
-	__u8 type;
-	__u16 last_iso;
-	struct ed *ed_rm_list;
-
-	struct usb_device *usb_dev;
-	__u32 unused[3];
-} __attribute__ ((aligned(16)));
-
-/* TD info field */
-#define TD_CC			0xf0000000
-#define TD_CC_GET(td_p)		(((td_p) >> 28) & 0x0f)
-#define TD_CC_SET(td_p, cc) \
-	{(td_p) = ((td_p) & 0x0fffffff) | (((cc) & 0x0f) << 28)}
-#define TD_EC			0x0C000000
-#define TD_T			0x03000000
-#define TD_T_DATA0		0x02000000
-#define TD_T_DATA1		0x03000000
-#define TD_T_TOGGLE		0x00000000
-#define TD_R			0x00040000
-#define TD_DI			0x00E00000
-#define TD_DI_SET(X)		(((X) & 0x07)<< 21)
-#define TD_DP			0x00180000
-#define TD_DP_SETUP		0x00000000
-#define TD_DP_IN		0x00100000
-#define TD_DP_OUT		0x00080000
-
-#define TD_ISO			0x00010000
-#define TD_DEL			0x00020000
-
-/* CC Codes */
-#define TD_CC_NOERROR		0x00
-#define TD_CC_CRC		0x01
-#define TD_CC_BITSTUFFING	0x02
-#define TD_CC_DATATOGGLEM	0x03
-#define TD_CC_STALL		0x04
-#define TD_DEVNOTRESP		0x05
-#define TD_PIDCHECKFAIL	0x06
-#define TD_UNEXPECTEDPID	0x07
-#define TD_DATAOVERRUN		0x08
-#define TD_DATAUNDERRUN	0x09
-#define TD_BUFFEROVERRUN	0x0C
-#define TD_BUFFERUNDERRUN	0x0D
-#define TD_NOTACCESSED		0x0F
-
-
-#define MAXPSW 1
-
-struct td {
-	__u32 hwINFO;
-	__u32 hwCBP;		/* Current Buffer Pointer */
-	__u32 hwNextTD;		/* Next TD Pointer */
-	__u32 hwBE;		/* Memory Buffer End Pointer */
-
-	__u8 unused;
-	__u8 index;
-	struct ed *ed;
-	struct td *next_dl_td;
-	struct usb_device *usb_dev;
-	int transfer_len;
-	__u32 data;
-
-	__u32 unused2[2];
-} __attribute__ ((aligned(32)));
-
-#define OHCI_ED_SKIP	(1 << 14)
-
-/*
- * The HCCA (Host Controller Communications Area) is a 256 byte
- * structure defined in the OHCI spec. that the host controller is
- * told the base address of.  It must be 256-byte aligned.
- */
-
-#define NUM_INTS 32		/* part of the OHCI standard */
-struct ohci_hcca {
-	__u32 int_table[NUM_INTS];	/* Interrupt ED table */
-	__u16 frame_no;		/* current frame number */
-	__u16 pad1;		/* set to 0 on each frame_no change */
-	__u32 done_head;	/* info returned for an interrupt */
-	u8 reserved_for_hc[116];
-} __attribute__ ((aligned(256)));
-
-/*
- * Maximum number of root hub ports.
- */
-#define MAX_ROOT_PORTS	15	/* maximum OHCI root hub ports */
-
-/*
- * This is the structure of the OHCI controller's memory mapped I/O
- * region.  This is Memory Mapped I/O.	You must use the readl() and
- * writel() macros defined in asm/io.h to access these!!
- */
-struct ohci_regs {
-	/* control and status registers */
-	__u32 revision;
-	__u32 control;
-	__u32 cmdstatus;
-	__u32 intrstatus;
-	__u32 intrenable;
-	__u32 intrdisable;
-	/* memory pointers */
-	__u32 hcca;
-	__u32 ed_periodcurrent;
-	__u32 ed_controlhead;
-	__u32 ed_controlcurrent;
-	__u32 ed_bulkhead;
-	__u32 ed_bulkcurrent;
-	__u32 donehead;
-	/* frame counters */
-	__u32 fminterval;
-	__u32 fmremaining;
-	__u32 fmnumber;
-	__u32 periodicstart;
-	__u32 lsthresh;
-	/* Root hub ports */
-	struct ohci_roothub_regs {
-		__u32 a;
-		__u32 b;
-		__u32 status;
-		__u32 portstatus[MAX_ROOT_PORTS];
-	} roothub;
-} __attribute__ ((aligned(32)));
-
-/* OHCI CONTROL AND STATUS REGISTER MASKS */
-
-/*
- * HcControl (control) register masks
- */
-#define OHCI_CTRL_CBSR	(3 << 0)	/* control/bulk service ratio */
-#define OHCI_CTRL_PLE	(1 << 2)	/* periodic list enable */
-#define OHCI_CTRL_IE	(1 << 3)	/* isochronous enable */
-#define OHCI_CTRL_CLE	(1 << 4)	/* control list enable */
-#define OHCI_CTRL_BLE	(1 << 5)	/* bulk list enable */
-#define OHCI_CTRL_HCFS	(3 << 6)	/* host controller functional state */
-#define OHCI_CTRL_IR	(1 << 8)	/* interrupt routing */
-#define OHCI_CTRL_RWC	(1 << 9)	/* remote wakeup connected */
-#define OHCI_CTRL_RWE	(1 << 10)	/* remote wakeup enable */
-
-/* pre-shifted values for HCFS */
-#	define OHCI_USB_RESET	(0 << 6)
-#	define OHCI_USB_RESUME	(1 << 6)
-#	define OHCI_USB_OPER	(2 << 6)
-#	define OHCI_USB_SUSPEND	(3 << 6)
-
-/*
- * HcCommandStatus (cmdstatus) register masks
- */
-#define OHCI_HCR	(1 << 0)	/* host controller reset */
-#define OHCI_CLF	(1 << 1)	/* control list filled */
-#define OHCI_BLF	(1 << 2)	/* bulk list filled */
-#define OHCI_OCR	(1 << 3)	/* ownership change request */
-#define OHCI_SOC	(3 << 16)	/* scheduling overrun count */
-
-/*
- * masks used with interrupt registers:
- * HcInterruptStatus (intrstatus)
- * HcInterruptEnable (intrenable)
- * HcInterruptDisable (intrdisable)
- */
-#define OHCI_INTR_SO	(1 << 0)	/* scheduling overrun */
-#define OHCI_INTR_WDH	(1 << 1)	/* writeback of done_head */
-#define OHCI_INTR_SF	(1 << 2)	/* start frame */
-#define OHCI_INTR_RD	(1 << 3)	/* resume detect */
-#define OHCI_INTR_UE	(1 << 4)	/* unrecoverable error */
-#define OHCI_INTR_FNO	(1 << 5)	/* frame number overflow */
-#define OHCI_INTR_RHSC	(1 << 6)	/* root hub status change */
-#define OHCI_INTR_OC	(1 << 30)	/* ownership change */
-#define OHCI_INTR_MIE	(1 << 31)	/* master interrupt enable */
-
-/* Virtual Root HUB */
-struct virt_root_hub {
-	int devnum;		/* Address of Root Hub endpoint */
-	void *dev;		/* was urb */
-	void *int_addr;
-	int send;
-	int interval;
-};
-
-/* USB HUB CONSTANTS (not OHCI-specific; see hub.h) */
-
-/* destination of request */
-#define RH_INTERFACE		0x01
-#define RH_ENDPOINT		0x02
-#define RH_OTHER		0x03
-
-#define RH_CLASS		0x20
-#define RH_VENDOR		0x40
-
-/* Requests: bRequest << 8 | bmRequestType */
-#define RH_GET_STATUS		0x0080
-#define RH_CLEAR_FEATURE	0x0100
-#define RH_SET_FEATURE		0x0300
-#define RH_SET_ADDRESS		0x0500
-#define RH_GET_DESCRIPTOR	0x0680
-#define RH_SET_DESCRIPTOR	0x0700
-#define RH_GET_CONFIGURATION	0x0880
-#define RH_SET_CONFIGURATION	0x0900
-#define RH_GET_STATE		0x0280
-#define RH_GET_INTERFACE	0x0A80
-#define RH_SET_INTERFACE	0x0B00
-#define RH_SYNC_FRAME		0x0C80
-/* Our Vendor Specific Request */
-#define RH_SET_EP		0x2000
-
-
-/* Hub port features */
-#define RH_PORT_CONNECTION	0x00
-#define RH_PORT_ENABLE		0x01
-#define RH_PORT_SUSPEND		0x02
-#define RH_PORT_OVER_CURRENT	0x03
-#define RH_PORT_RESET		0x04
-#define RH_PORT_POWER		0x08
-#define RH_PORT_LOW_SPEED	0x09
-
-#define RH_C_PORT_CONNECTION	0x10
-#define RH_C_PORT_ENABLE	0x11
-#define RH_C_PORT_SUSPEND	0x12
-#define RH_C_PORT_OVER_CURRENT	0x13
-#define RH_C_PORT_RESET		0x14
-
-/* Hub features */
-#define RH_C_HUB_LOCAL_POWER	0x00
-#define RH_C_HUB_OVER_CURRENT	0x01
-
-#define RH_DEVICE_REMOTE_WAKEUP 0x00
-#define RH_ENDPOINT_STALL	0x01
-
-#define RH_ACK			0x01
-#define RH_REQ_ERR		-1
-#define RH_NACK			0x00
-
-
-/* OHCI ROOT HUB REGISTER MASKS */
-
-/* roothub.portstatus [i] bits */
-#define RH_PS_CCS		0x00000001 /* current connect status */
-#define RH_PS_PES		0x00000002 /* port enable status */
-#define RH_PS_PSS		0x00000004 /* port suspend status */
-#define RH_PS_POCI		0x00000008 /* port over current indicator */
-#define RH_PS_PRS		0x00000010 /* port reset status */
-#define RH_PS_PPS		0x00000100 /* port power status */
-#define RH_PS_LSDA		0x00000200 /* low speed device attached */
-#define RH_PS_CSC		0x00010000 /* connect status change */
-#define RH_PS_PESC		0x00020000 /* port enable status change */
-#define RH_PS_PSSC		0x00040000 /* port suspend status change */
-#define RH_PS_OCIC		0x00080000 /* over current indicator change */
-#define RH_PS_PRSC		0x00100000 /* port reset status change */
-
-/* roothub.status bits */
-#define RH_HS_LPS		0x00000001 /* local power status */
-#define RH_HS_OCI		0x00000002 /* over current indicator */
-#define RH_HS_DRWE		0x00008000 /* device remote wakeup enable */
-#define RH_HS_LPSC		0x00010000 /* local power status change */
-#define RH_HS_OCIC		0x00020000 /* over current indicator change */
-#define RH_HS_CRWE		0x80000000 /* clear remote wakeup enable */
-
-/* roothub.b masks */
-#define RH_B_DR			0x0000ffff /* device removable flags */
-#define RH_B_PPCM		0xffff0000 /* port power control mask */
-
-/* roothub.a masks */
-#define	RH_A_NDP		(0xff << 0)  /* number of downstream ports */
-#define	RH_A_PSM		(1 << 8)     /* power switching mode */
-#define	RH_A_NPS		(1 << 9)     /* no power switching */
-#define	RH_A_DT			(1 << 10)    /* device type (mbz) */
-#define	RH_A_OCPM		(1 << 11)    /* over current protection mode */
-#define	RH_A_NOCP		(1 << 12)    /* no over current protection */
-#define	RH_A_POTPGT		(0xff << 24) /* power on to power good time */
-
-/* urb */
-#define N_URB_TD 48
-struct urb_priv {
-	struct ed *ed;
-	__u16 length;		/* number of tds associated with this request */
-	__u16 td_cnt;		/* number of tds already serviced */
-	int state;
-	unsigned long pipe;
-	int actual_length;
-	struct td *td[N_URB_TD];	/* list pointer to all corresponding TDs
-					   associated with this request */
-};
-#define URB_DEL 1
-
-/*
- * This is the full ohci controller description
- *
- * Note how the "proper" USB information is just
- * a subset of what the full implementation needs. (Linus)
- */
-
-
-struct ohci {
-	struct ohci_hcca *hcca;	/* hcca */
-	/*dma_addr_t hcca_dma; */
-
-	int irq;
-	int disabled;		/* e.g. got a UE, we're hung */
-	int sleeping;
-	unsigned long flags;	/* for HC bugs */
-
-	struct ohci_regs *regs;	/* OHCI controller's memory */
-
-	struct ed *ed_rm_list[2];  /* lists of all endpoints to be removed */
-	struct ed *ed_bulktail;    /* last endpoint of bulk list */
-	struct ed *ed_controltail; /* last endpoint of control list */
-	int intrstatus;
-	__u32 hc_control;	/* copy of the hc control reg */
-	struct usb_device *dev[32];
-	struct virt_root_hub rh;
-
-	const char *slot_name;
-};
-
-#define NUM_EDS 8		/* num of preallocated endpoint descriptors */
-
-struct ohci_device {
-	struct ed ed[NUM_EDS];
-	int ed_cnt;
-};
-
-/* hcd */
-/* endpoint */
-static int ep_link(struct ohci *ohci, struct ed *ed);
-static int ep_unlink(struct ohci *ohci, struct ed *ed);
-static struct ed *ep_add_ed(struct usb_device *usb_dev, unsigned long pipe);
-
-/*-------------------------------------------------------------------------*/
-
-/* we need more TDs than EDs */
-#define NUM_TD 64
-
-/* +1 so we can align the storage */
-struct td gtd[NUM_TD + 1];
-
-/* pointers to aligned storage */
-struct td *ptd;
-
-/* TDs ... */
-static inline struct td *td_alloc(struct usb_device *usb_dev)
-{
-	int i;
-	struct td *td;
-
-	td = NULL;
-	for (i = 0; i < NUM_TD; i++) {
-		if (ptd[i].usb_dev == NULL) {
-			td = &ptd[i];
-			td->usb_dev = usb_dev;
-			break;
-		}
-	}
-
-	return td;
-}
-
-static inline void ed_free(struct ed *ed)
-{
-	ed->usb_dev = NULL;
-}
diff --git a/arch/arm/cpu/arm920t/start.S b/arch/arm/cpu/arm920t/start.S
deleted file mode 100644
index 2fc0abc..0000000
--- a/arch/arm/cpu/arm920t/start.S
+++ /dev/null
@@ -1,516 +0,0 @@
-/*
- *  armboot - Startup Code for ARM920 CPU-core
- *
- *  Copyright (c) 2001	Marius Gröger <mag@sysgo.de>
- *  Copyright (c) 2002	Alex Züpke <azu@sysgo.de>
- *  Copyright (c) 2002	Gary Jennejohn <garyj@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <asm-offsets.h>
-#include <common.h>
-#include <config.h>
-
-/*
- *************************************************************************
- *
- * Jump vector table as in table 3.1 in [1]
- *
- *************************************************************************
- */
-
-
-.globl _start
-_start:	b	start_code
-	ldr	pc, _undefined_instruction
-	ldr	pc, _software_interrupt
-	ldr	pc, _prefetch_abort
-	ldr	pc, _data_abort
-	ldr	pc, _not_used
-	ldr	pc, _irq
-	ldr	pc, _fiq
-
-_undefined_instruction:	.word undefined_instruction
-_software_interrupt:	.word software_interrupt
-_prefetch_abort:	.word prefetch_abort
-_data_abort:		.word data_abort
-_not_used:		.word not_used
-_irq:			.word irq
-_fiq:			.word fiq
-
-	.balignl 16,0xdeadbeef
-
-
-/*
- *************************************************************************
- *
- * Startup Code (called from the ARM reset exception vector)
- *
- * do important init only if we don't start from memory!
- * relocate armboot to ram
- * setup stack
- * jump to second stage
- *
- *************************************************************************
- */
-
-.globl _TEXT_BASE
-_TEXT_BASE:
-	.word	CONFIG_SYS_TEXT_BASE
-
-/*
- * These are defined in the board-specific linker script.
- * Subtracting _start from them lets the linker put their
- * relative position in the executable instead of leaving
- * them null.
- */
-.globl _bss_start_ofs
-_bss_start_ofs:
-	.word __bss_start - _start
-
-.globl _bss_end_ofs
-_bss_end_ofs:
-	.word _end - _start
-
-#ifdef CONFIG_USE_IRQ
-/* IRQ stack memory (calculated at run-time) */
-.globl IRQ_STACK_START
-IRQ_STACK_START:
-	.word	0x0badc0de
-
-/* IRQ stack memory (calculated at run-time) */
-.globl FIQ_STACK_START
-FIQ_STACK_START:
-	.word 0x0badc0de
-#endif
-
-/* IRQ stack memory (calculated at run-time) + 8 bytes */
-.globl IRQ_STACK_START_IN
-IRQ_STACK_START_IN:
-	.word	0x0badc0de
-
-/*
- * the actual start code
- */
-
-start_code:
-	/*
-	 * set the cpu to SVC32 mode
-	 */
-	mrs	r0, cpsr
-	bic	r0, r0, #0x1f
-	orr	r0, r0, #0xd3
-	msr	cpsr, r0
-
-#if	defined(CONFIG_AT91RM9200DK) || defined(CONFIG_AT91RM9200EK)
-	/*
-	 * relocate exception table
-	 */
-	ldr	r0, =_start
-	ldr	r1, =0x0
-	mov	r2, #16
-copyex:
-	subs	r2, r2, #1
-	ldr	r3, [r0], #4
-	str	r3, [r1], #4
-	bne	copyex
-#endif
-
-#ifdef CONFIG_S3C24X0
-	/* turn off the watchdog */
-
-# if defined(CONFIG_S3C2400)
-#  define pWTCON	0x15300000
-#  define INTMSK	0x14400008	/* Interupt-Controller base addresses */
-#  define CLKDIVN	0x14800014	/* clock divisor register */
-#else
-#  define pWTCON	0x53000000
-#  define INTMSK	0x4A000008	/* Interupt-Controller base addresses */
-#  define INTSUBMSK	0x4A00001C
-#  define CLKDIVN	0x4C000014	/* clock divisor register */
-# endif
-
-	ldr	r0, =pWTCON
-	mov	r1, #0x0
-	str	r1, [r0]
-
-	/*
-	 * mask all IRQs by setting all bits in the INTMR - default
-	 */
-	mov	r1, #0xffffffff
-	ldr	r0, =INTMSK
-	str	r1, [r0]
-# if defined(CONFIG_S3C2410)
-	ldr	r1, =0x3ff
-	ldr	r0, =INTSUBMSK
-	str	r1, [r0]
-# endif
-
-	/* FCLK:HCLK:PCLK = 1:2:4 */
-	/* default FCLK is 120 MHz ! */
-	ldr	r0, =CLKDIVN
-	mov	r1, #3
-	str	r1, [r0]
-#endif	/* CONFIG_S3C24X0 */
-
-	/*
-	 * we do sys-critical inits only at reboot,
-	 * not when booting from ram!
-	 */
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
-	bl	cpu_init_crit
-#endif
-
-/* Set stackpointer in internal RAM to call board_init_f */
-call_board_init_f:
-	ldr	sp, =(CONFIG_SYS_INIT_SP_ADDR)
-	bic	sp, sp, #7 /* 8-byte alignment for ABI compliance */
-	ldr	r0,=0x00000000
-	bl	board_init_f
-
-/*------------------------------------------------------------------------------*/
-
-/*
- * void relocate_code (addr_sp, gd, addr_moni)
- *
- * This "function" does not return, instead it continues in RAM
- * after relocating the monitor code.
- *
- */
-	.globl	relocate_code
-relocate_code:
-	mov	r4, r0	/* save addr_sp */
-	mov	r5, r1	/* save addr of gd */
-	mov	r6, r2	/* save addr of destination */
-
-	/* Set up the stack						    */
-stack_setup:
-	mov	sp, r4
-
-	adr	r0, _start
-	cmp	r0, r6
-	beq	clear_bss		/* skip relocation */
-	mov	r1, r6			/* r1 <- scratch for copy_loop */
-	ldr	r3, _bss_start_ofs
-	add	r2, r0, r3		/* r2 <- source end address	    */
-
-copy_loop:
-	ldmia	r0!, {r9-r10}		/* copy from source address [r0]    */
-	stmia	r1!, {r9-r10}		/* copy to   target address [r1]    */
-	cmp	r0, r2			/* until source end address [r2]    */
-	blo	copy_loop
-
-#ifndef CONFIG_PRELOADER
-	/*
-	 * fix .rel.dyn relocations
-	 */
-	ldr	r0, _TEXT_BASE		/* r0 <- Text base */
-	sub	r9, r6, r0		/* r9 <- relocation offset */
-	ldr	r10, _dynsym_start_ofs	/* r10 <- sym table ofs */
-	add	r10, r10, r0		/* r10 <- sym table in FLASH */
-	ldr	r2, _rel_dyn_start_ofs	/* r2 <- rel dyn start ofs */
-	add	r2, r2, r0		/* r2 <- rel dyn start in FLASH */
-	ldr	r3, _rel_dyn_end_ofs	/* r3 <- rel dyn end ofs */
-	add	r3, r3, r0		/* r3 <- rel dyn end in FLASH */
-fixloop:
-	ldr	r0, [r2]		/* r0 <- location to fix up, IN FLASH! */
-	add	r0, r0, r9		/* r0 <- location to fix up in RAM */
-	ldr	r1, [r2, #4]
-	and	r7, r1, #0xff
-	cmp	r7, #23			/* relative fixup? */
-	beq	fixrel
-	cmp	r7, #2			/* absolute fixup? */
-	beq	fixabs
-	/* ignore unknown type of fixup */
-	b	fixnext
-fixabs:
-	/* absolute fix: set location to (offset) symbol value */
-	mov	r1, r1, LSR #4		/* r1 <- symbol index in .dynsym */
-	add	r1, r10, r1		/* r1 <- address of symbol in table */
-	ldr	r1, [r1, #4]		/* r1 <- symbol value */
-	add	r1, r1, r9		/* r1 <- relocated sym addr */
-	b	fixnext
-fixrel:
-	/* relative fix: increase location by offset */
-	ldr	r1, [r0]
-	add	r1, r1, r9
-fixnext:
-	str	r1, [r0]
-	add	r2, r2, #8		/* each rel.dyn entry is 8 bytes */
-	cmp	r2, r3
-	blo	fixloop
-#endif
-
-clear_bss:
-#ifndef CONFIG_PRELOADER
-	ldr	r0, _bss_start_ofs
-	ldr	r1, _bss_end_ofs
-	mov	r4, r6			/* reloc addr */
-	add	r0, r0, r4
-	add	r1, r1, r4
-	mov	r2, #0x00000000		/* clear			    */
-
-clbss_l:str	r2, [r0]		/* clear loop...		    */
-	add	r0, r0, #4
-	cmp	r0, r1
-	bne	clbss_l
-
-	bl coloured_LED_init
-	bl red_LED_on
-#endif
-
-/*
- * We are done. Do not return, instead branch to second part of board
- * initialization, now running from RAM.
- */
-#ifdef CONFIG_NAND_SPL
-	ldr     r0, _nand_boot_ofs
-	mov	pc, r0
-
-_nand_boot_ofs:
-	.word nand_boot
-#else
-	ldr	r0, _board_init_r_ofs
-	adr	r1, _start
-	add	lr, r0, r1
-	add	lr, lr, r9
-	/* setup parameters for board_init_r */
-	mov	r0, r5		/* gd_t */
-	mov	r1, r6		/* dest_addr */
-	/* jump to it ... */
-	mov	pc, lr
-
-_board_init_r_ofs:
-	.word board_init_r - _start
-#endif
-
-_rel_dyn_start_ofs:
-	.word __rel_dyn_start - _start
-_rel_dyn_end_ofs:
-	.word __rel_dyn_end - _start
-_dynsym_start_ofs:
-	.word __dynsym_start - _start
-
-/*
- *************************************************************************
- *
- * CPU_init_critical registers
- *
- * setup important registers
- * setup memory timing
- *
- *************************************************************************
- */
-
-
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
-cpu_init_crit:
-	/*
-	 * flush v4 I/D caches
-	 */
-	mov	r0, #0
-	mcr	p15, 0, r0, c7, c7, 0	/* flush v3/v4 cache */
-	mcr	p15, 0, r0, c8, c7, 0	/* flush v4 TLB */
-
-	/*
-	 * disable MMU stuff and caches
-	 */
-	mrc	p15, 0, r0, c1, c0, 0
-	bic	r0, r0, #0x00002300	@ clear bits 13, 9:8 (--V- --RS)
-	bic	r0, r0, #0x00000087	@ clear bits 7, 2:0 (B--- -CAM)
-	orr	r0, r0, #0x00000002	@ set bit 2 (A) Align
-	orr	r0, r0, #0x00001000	@ set bit 12 (I) I-Cache
-	mcr	p15, 0, r0, c1, c0, 0
-
-	/*
-	 * before relocating, we have to setup RAM timing
-	 * because memory timing is board-dependend, you will
-	 * find a lowlevel_init.S in your board directory.
-	 */
-	mov	ip, lr
-
-	bl	lowlevel_init
-
-	mov	lr, ip
-	mov	pc, lr
-#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
-
-/*
- *************************************************************************
- *
- * Interrupt handling
- *
- *************************************************************************
- */
-
-@
-@ IRQ stack frame.
-@
-#define S_FRAME_SIZE	72
-
-#define S_OLD_R0	68
-#define S_PSR		64
-#define S_PC		60
-#define S_LR		56
-#define S_SP		52
-
-#define S_IP		48
-#define S_FP		44
-#define S_R10		40
-#define S_R9		36
-#define S_R8		32
-#define S_R7		28
-#define S_R6		24
-#define S_R5		20
-#define S_R4		16
-#define S_R3		12
-#define S_R2		8
-#define S_R1		4
-#define S_R0		0
-
-#define MODE_SVC	0x13
-#define I_BIT		0x80
-
-/*
- * use bad_save_user_regs for abort/prefetch/undef/swi ...
- * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
- */
-
-	.macro	bad_save_user_regs
-	sub	sp, sp, #S_FRAME_SIZE
-	stmia	sp, {r0 - r12}			@ Calling r0-r12
-	ldr	r2, IRQ_STACK_START_IN
-	ldmia	r2, {r2 - r3}			@ get pc, cpsr
-	add	r0, sp, #S_FRAME_SIZE		@ restore sp_SVC
-
-	add	r5, sp, #S_SP
-	mov	r1, lr
-	stmia	r5, {r0 - r3}			@ save sp_SVC, lr_SVC, pc, cpsr
-	mov	r0, sp
-	.endm
-
-	.macro	irq_save_user_regs
-	sub	sp, sp, #S_FRAME_SIZE
-	stmia	sp, {r0 - r12}			@ Calling r0-r12
-	add	r7, sp, #S_PC
-	stmdb	r7, {sp, lr}^			@ Calling SP, LR
-	str	lr, [r7, #0]			@ Save calling PC
-	mrs	r6, spsr
-	str	r6, [r7, #4]			@ Save CPSR
-	str	r0, [r7, #8]			@ Save OLD_R0
-	mov	r0, sp
-	.endm
-
-	.macro	irq_restore_user_regs
-	ldmia	sp, {r0 - lr}^			@ Calling r0 - lr
-	mov	r0, r0
-	ldr	lr, [sp, #S_PC]			@ Get PC
-	add	sp, sp, #S_FRAME_SIZE
-	/* return & move spsr_svc into cpsr */
-	subs	pc, lr, #4
-	.endm
-
-	.macro get_bad_stack
-	ldr	r13, IRQ_STACK_START_IN		@ setup our mode stack
-
-	str	lr, [r13]			@ save caller lr / spsr
-	mrs	lr, spsr
-	str	lr, [r13, #4]
-
-	mov	r13, #MODE_SVC			@ prepare SVC-Mode
-	@ msr	spsr_c, r13
-	msr	spsr, r13
-	mov	lr, pc
-	movs	pc, lr
-	.endm
-
-	.macro get_irq_stack			@ setup IRQ stack
-	ldr	sp, IRQ_STACK_START
-	.endm
-
-	.macro get_fiq_stack			@ setup FIQ stack
-	ldr	sp, FIQ_STACK_START
-	.endm
-
-/*
- * exception handlers
- */
-	.align  5
-undefined_instruction:
-	get_bad_stack
-	bad_save_user_regs
-	bl	do_undefined_instruction
-
-	.align	5
-software_interrupt:
-	get_bad_stack
-	bad_save_user_regs
-	bl	do_software_interrupt
-
-	.align	5
-prefetch_abort:
-	get_bad_stack
-	bad_save_user_regs
-	bl	do_prefetch_abort
-
-	.align	5
-data_abort:
-	get_bad_stack
-	bad_save_user_regs
-	bl	do_data_abort
-
-	.align	5
-not_used:
-	get_bad_stack
-	bad_save_user_regs
-	bl	do_not_used
-
-#ifdef CONFIG_USE_IRQ
-
-	.align	5
-irq:
-	get_irq_stack
-	irq_save_user_regs
-	bl	do_irq
-	irq_restore_user_regs
-
-	.align	5
-fiq:
-	get_fiq_stack
-	/* someone ought to write a more effiction fiq_save_user_regs */
-	irq_save_user_regs
-	bl	do_fiq
-	irq_restore_user_regs
-
-#else
-
-	.align	5
-irq:
-	get_bad_stack
-	bad_save_user_regs
-	bl	do_irq
-
-	.align	5
-fiq:
-	get_bad_stack
-	bad_save_user_regs
-	bl	do_fiq
-
-#endif
diff --git a/arch/arm/cpu/arm920t/u-boot.lds b/arch/arm/cpu/arm920t/u-boot.lds
deleted file mode 100644
index a6f8b56..0000000
--- a/arch/arm/cpu/arm920t/u-boot.lds
+++ /dev/null
@@ -1,86 +0,0 @@
-/*
- * (c) Copyright 2004
- * Techware Information Technology, Inc.
- * Ming-Len Wu <minglen_wu@techware.com.tw>
- *
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- */
-
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-ENTRY(_start)
-SECTIONS
-{
-	. = 0x00000000;
-
-	. = ALIGN(4);
-	.text :
-	{
-		arch/arm/cpu/arm920t/start.o	(.text)
-		*(.text)
-	}
-
-	. = ALIGN(4);
-	.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
-
-	. = ALIGN(4);
-	.data : {
-		*(.data)
-	}
-
-	. = ALIGN(4);
-
-	. = .;
-	__u_boot_cmd_start = .;
-	.u_boot_cmd : { *(.u_boot_cmd) }
-	__u_boot_cmd_end = .;
-
-	. = ALIGN(4);
-
-	.rel.dyn : {
-		__rel_dyn_start = .;
-		*(.rel*)
-		__rel_dyn_end = .;
-	}
-
-	.dynsym : {
-		__dynsym_start = .;
-		*(.dynsym)
-	}
-
-	.bss __rel_dyn_start (OVERLAY) : {
-		__bss_start = .;
-		*(.bss)
-		 . = ALIGN(4);
-		_end = .;
-	}
-
-	/DISCARD/ : { *(.dynstr*) }
-	/DISCARD/ : { *(.dynamic*) }
-	/DISCARD/ : { *(.plt*) }
-	/DISCARD/ : { *(.interp*) }
-	/DISCARD/ : { *(.gnu*) }
-}
diff --git a/arch/arm/cpu/arm925t/Makefile b/arch/arm/cpu/arm925t/Makefile
deleted file mode 100644
index 29465c2..0000000
--- a/arch/arm/cpu/arm925t/Makefile
+++ /dev/null
@@ -1,50 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(CPU).o
-
-START	= start.o
-
-COBJS	+= cpu.o
-COBJS	+= omap925.o
-COBJS	+= timer.o
-
-SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
-START	:= $(addprefix $(obj),$(START))
-
-all:	$(obj).depend $(START) $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/arch/arm/cpu/arm925t/config.mk b/arch/arm/cpu/arm925t/config.mk
deleted file mode 100644
index 8f6c1a3..0000000
--- a/arch/arm/cpu/arm925t/config.mk
+++ /dev/null
@@ -1,32 +0,0 @@
-#
-# (C) Copyright 2002
-# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float
-
-PLATFORM_CPPFLAGS += -march=armv4
-# =========================================================================
-#
-# Supply options according to compiler version
-#
-# =========================================================================
-PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))
diff --git a/arch/arm/cpu/arm925t/cpu.c b/arch/arm/cpu/arm925t/cpu.c
deleted file mode 100644
index 71700bb..0000000
--- a/arch/arm/cpu/arm925t/cpu.c
+++ /dev/null
@@ -1,66 +0,0 @@
-/*
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * CPU specific code
- */
-
-#include <common.h>
-#include <command.h>
-#include <arm925t.h>
-#include <asm/system.h>
-
-static void cache_flush(void);
-
-int cleanup_before_linux (void)
-{
-	/*
-	 * this function is called just before we call linux
-	 * it prepares the processor for linux
-	 *
-	 * we turn off caches etc ...
-	 */
-
-	disable_interrupts ();
-
-
-	/* turn off I/D-cache */
-	icache_disable();
-	dcache_disable();
-	/* flush I/D-cache */
-	cache_flush();
-
-	return 0;
-}
-
-/* flush I/D-cache */
-static void cache_flush (void)
-{
-	unsigned long i = 0;
-
-	asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i));
-}
diff --git a/arch/arm/cpu/arm925t/omap925.c b/arch/arm/cpu/arm925t/omap925.c
deleted file mode 100644
index 65dab9f..0000000
--- a/arch/arm/cpu/arm925t/omap925.c
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- * (C) Copyright 2003
- * Texas Instruments <www.ti.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <command.h>
-#include <arm925t.h>
-
-#define MIF_CONFIG_REG 0xFFFECC0C
-#define FLASH_GLOBAL_CTRL_NWP 1
-
-void archflashwp (void *archdata, int wp)
-{
-	ulong *fgc = (ulong *) MIF_CONFIG_REG;
-
-	if (wp == 1)
-		*fgc &= ~FLASH_GLOBAL_CTRL_NWP;
-	else
-		*fgc |= FLASH_GLOBAL_CTRL_NWP;
-}
diff --git a/arch/arm/cpu/arm925t/start.S b/arch/arm/cpu/arm925t/start.S
deleted file mode 100644
index 20ecdd5..0000000
--- a/arch/arm/cpu/arm925t/start.S
+++ /dev/null
@@ -1,515 +0,0 @@
-/*
- *  armboot - Startup Code for ARM925 CPU-core
- *
- *  Copyright (c) 2003  Texas Instruments
- *
- *  ----- Adapted for OMAP1510 from ARM920 code ------
- *
- *  Copyright (c) 2001	Marius Gröger <mag@sysgo.de>
- *  Copyright (c) 2002	Alex Züpke <azu@sysgo.de>
- *  Copyright (c) 2002	Gary Jennejohn <garyj@denx.de>
- *  Copyright (c) 2003	Richard Woodruff <r-woodruff2@ti.com>
- *  Copyright (c) 2003	Kshitij	 <kshitij@ti.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <asm-offsets.h>
-#include <config.h>
-#include <version.h>
-
-#if defined(CONFIG_OMAP1510)
-#include <./configs/omap1510.h>
-#endif
-
-/*
- *************************************************************************
- *
- * Jump vector table as in table 3.1 in [1]
- *
- *************************************************************************
- */
-
-
-.globl _start
-_start:	b       reset
-	ldr	pc, _undefined_instruction
-	ldr	pc, _software_interrupt
-	ldr	pc, _prefetch_abort
-	ldr	pc, _data_abort
-	ldr	pc, _not_used
-	ldr	pc, _irq
-	ldr	pc, _fiq
-
-_undefined_instruction:	.word undefined_instruction
-_software_interrupt:	.word software_interrupt
-_prefetch_abort:	.word prefetch_abort
-_data_abort:		.word data_abort
-_not_used:		.word not_used
-_irq:			.word irq
-_fiq:			.word fiq
-
-	.balignl 16,0xdeadbeef
-
-
-/*
- *************************************************************************
- *
- * Startup Code (reset vector)
- *
- * do important init only if we don't start from memory!
- * setup Memory and board specific bits prior to relocation.
- * relocate armboot to ram
- * setup stack
- *
- *************************************************************************
- */
-
-.globl _TEXT_BASE
-_TEXT_BASE:
-	.word	CONFIG_SYS_TEXT_BASE
-
-/*
- * These are defined in the board-specific linker script.
- * Subtracting _start from them lets the linker put their
- * relative position in the executable instead of leaving
- * them null.
- */
-.globl _bss_start_ofs
-_bss_start_ofs:
-	.word __bss_start - _start
-
-.globl _bss_end_ofs
-_bss_end_ofs:
-	.word _end - _start
-
-#ifdef CONFIG_USE_IRQ
-/* IRQ stack memory (calculated at run-time) */
-.globl IRQ_STACK_START
-IRQ_STACK_START:
-	.word	0x0badc0de
-
-/* IRQ stack memory (calculated at run-time) */
-.globl FIQ_STACK_START
-FIQ_STACK_START:
-	.word 0x0badc0de
-#endif
-
-/* IRQ stack memory (calculated at run-time) + 8 bytes */
-.globl IRQ_STACK_START_IN
-IRQ_STACK_START_IN:
-	.word	0x0badc0de
-
-/*
- * the actual reset code
- */
-
-reset:
-	/*
-	 * set the cpu to SVC32 mode
-	 */
-	mrs	r0,cpsr
-	bic	r0,r0,#0x1f
-	orr	r0,r0,#0xd3
-	msr	cpsr,r0
-
-	/*
-	 * Set up 925T mode
-	 */
-	mov r1, #0x81               /* Set ARM925T configuration. */
-	mcr p15, 0, r1, c15, c1, 0  /* Write ARM925T configuration register. */
-
-	/*
-	 * turn off the watchdog, unlock/diable sequence
-	 */
-	mov  r1, #0xF5
-	ldr  r0, =WDTIM_MODE
-	strh r1, [r0]
-	mov  r1, #0xA0
-	strh r1, [r0]
-
-	/*
-	 * mask all IRQs by setting all bits in the INTMR - default
-	 */
-	mov r1, #0xffffffff
-	ldr r0, =REG_IHL1_MIR
-	str r1, [r0]
-	ldr r0, =REG_IHL2_MIR
-	str r1, [r0]
-
-	/*
-	 * wait for dpll to lock
-	 */
-	ldr  r0, =CK_DPLL1
-	mov  r1, #0x10
-	strh r1, [r0]
-poll1:
-	ldrh r1, [r0]
-	ands r1, r1, #0x01
-	beq poll1
-
-	/*
-	 * we do sys-critical inits only at reboot,
-	 * not when booting from ram!
-	 */
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
-	bl  cpu_init_crit
-#endif
-
-/* Set stackpointer in internal RAM to call board_init_f */
-call_board_init_f:
-	ldr	sp, =(CONFIG_SYS_INIT_SP_ADDR)
-	bic	sp, sp, #7 /* 8-byte alignment for ABI compliance */
-	ldr	r0,=0x00000000
-	bl	board_init_f
-
-/*------------------------------------------------------------------------------*/
-
-/*
- * void relocate_code (addr_sp, gd, addr_moni)
- *
- * This "function" does not return, instead it continues in RAM
- * after relocating the monitor code.
- *
- */
-	.globl	relocate_code
-relocate_code:
-	mov	r4, r0	/* save addr_sp */
-	mov	r5, r1	/* save addr of gd */
-	mov	r6, r2	/* save addr of destination */
-
-	/* Set up the stack						    */
-stack_setup:
-	mov	sp, r4
-
-	adr	r0, _start
-	cmp	r0, r6
-	beq	clear_bss		/* skip relocation */
-	mov	r1, r6			/* r1 <- scratch for copy_loop */
-	ldr	r3, _bss_start_ofs
-	add	r2, r0, r3		/* r2 <- source end address	    */
-
-copy_loop:
-	ldmia	r0!, {r9-r10}		/* copy from source address [r0]    */
-	stmia	r1!, {r9-r10}		/* copy to   target address [r1]    */
-	cmp	r0, r2			/* until source end address [r2]    */
-	blo	copy_loop
-
-#ifndef CONFIG_PRELOADER
-	/*
-	 * fix .rel.dyn relocations
-	 */
-	ldr	r0, _TEXT_BASE		/* r0 <- Text base */
-	sub	r9, r6, r0		/* r9 <- relocation offset */
-	ldr	r10, _dynsym_start_ofs	/* r10 <- sym table ofs */
-	add	r10, r10, r0		/* r10 <- sym table in FLASH */
-	ldr	r2, _rel_dyn_start_ofs	/* r2 <- rel dyn start ofs */
-	add	r2, r2, r0		/* r2 <- rel dyn start in FLASH */
-	ldr	r3, _rel_dyn_end_ofs	/* r3 <- rel dyn end ofs */
-	add	r3, r3, r0		/* r3 <- rel dyn end in FLASH */
-fixloop:
-	ldr	r0, [r2]		/* r0 <- location to fix up, IN FLASH! */
-	add	r0, r0, r9		/* r0 <- location to fix up in RAM */
-	ldr	r1, [r2, #4]
-	and	r7, r1, #0xff
-	cmp	r7, #23			/* relative fixup? */
-	beq	fixrel
-	cmp	r7, #2			/* absolute fixup? */
-	beq	fixabs
-	/* ignore unknown type of fixup */
-	b	fixnext
-fixabs:
-	/* absolute fix: set location to (offset) symbol value */
-	mov	r1, r1, LSR #4		/* r1 <- symbol index in .dynsym */
-	add	r1, r10, r1		/* r1 <- address of symbol in table */
-	ldr	r1, [r1, #4]		/* r1 <- symbol value */
-	add	r1, r1, r9		/* r1 <- relocated sym addr */
-	b	fixnext
-fixrel:
-	/* relative fix: increase location by offset */
-	ldr	r1, [r0]
-	add	r1, r1, r9
-fixnext:
-	str	r1, [r0]
-	add	r2, r2, #8		/* each rel.dyn entry is 8 bytes */
-	cmp	r2, r3
-	blo	fixloop
-#endif
-
-clear_bss:
-#ifndef CONFIG_PRELOADER
-	ldr	r0, _bss_start_ofs
-	ldr	r1, _bss_end_ofs
-	mov	r4, r6			/* reloc addr */
-	add	r0, r0, r4
-	add	r1, r1, r4
-	mov	r2, #0x00000000		/* clear			    */
-
-clbss_l:str	r2, [r0]		/* clear loop...		    */
-	add	r0, r0, #4
-	cmp	r0, r1
-	bne	clbss_l
-
-	bl coloured_LED_init
-	bl red_LED_on
-#endif
-
-/*
- * We are done. Do not return, instead branch to second part of board
- * initialization, now running from RAM.
- */
-#ifdef CONFIG_NAND_SPL
-	ldr     r0, _nand_boot_ofs
-	mov	pc, r0
-
-_nand_boot_ofs:
-	.word nand_boot
-#else
-	ldr	r0, _board_init_r_ofs
-	adr	r1, _start
-	add	lr, r0, r1
-	add	lr, lr, r9
-	/* setup parameters for board_init_r */
-	mov	r0, r5		/* gd_t */
-	mov	r1, r6		/* dest_addr */
-	/* jump to it ... */
-	mov	pc, lr
-
-_board_init_r_ofs:
-	.word board_init_r - _start
-#endif
-
-_rel_dyn_start_ofs:
-	.word __rel_dyn_start - _start
-_rel_dyn_end_ofs:
-	.word __rel_dyn_end - _start
-_dynsym_start_ofs:
-	.word __dynsym_start - _start
-
-/*
- *************************************************************************
- *
- * CPU_init_critical registers
- *
- * setup important registers
- * setup memory timing
- *
- *************************************************************************
- */
-
-
-cpu_init_crit:
-	/*
-	 * flush v4 I/D caches
-	 */
-	mov	r0, #0
-	mcr	p15, 0, r0, c7, c7, 0	/* flush v3/v4 cache */
-	mcr	p15, 0, r0, c8, c7, 0	/* flush v4 TLB */
-
-	/*
-	 * disable MMU stuff and caches
-	 */
-	mrc	p15, 0, r0, c1, c0, 0
-	bic	r0, r0, #0x00002300	@ clear bits 13, 9:8 (--V- --RS)
-	bic	r0, r0, #0x00000087	@ clear bits 7, 2:0 (B--- -CAM)
-	orr	r0, r0, #0x00000002	@ set bit 2 (A) Align
-	orr	r0, r0, #0x00001000	@ set bit 12 (I) I-Cache
-	mcr	p15, 0, r0, c1, c0, 0
-
-	/*
-	 * Go setup Memory and board specific bits prior to relocation.
-	 */
-	mov	ip, lr          /* perserve link reg across call */
-	bl	lowlevel_init   /* go setup pll,mux,memory */
-	mov	lr, ip          /* restore link */
-	mov	pc, lr          /* back to my caller */
-/*
- *************************************************************************
- *
- * Interrupt handling
- *
- *************************************************************************
- */
-
-@
-@ IRQ stack frame.
-@
-#define S_FRAME_SIZE	72
-
-#define S_OLD_R0	68
-#define S_PSR		64
-#define S_PC		60
-#define S_LR		56
-#define S_SP		52
-
-#define S_IP		48
-#define S_FP		44
-#define S_R10		40
-#define S_R9		36
-#define S_R8		32
-#define S_R7		28
-#define S_R6		24
-#define S_R5		20
-#define S_R4		16
-#define S_R3		12
-#define S_R2		8
-#define S_R1		4
-#define S_R0		0
-
-#define MODE_SVC 0x13
-#define I_BIT	 0x80
-
-/*
- * use bad_save_user_regs for abort/prefetch/undef/swi ...
- * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
- */
-
-	.macro	bad_save_user_regs
-	sub	sp, sp, #S_FRAME_SIZE           @ carve out a frame on current user stack
-	stmia	sp, {r0 - r12}			@ Save user registers (now in svc mode) r0-r12
-
-	ldr	r2, IRQ_STACK_START_IN
-	ldmia	r2, {r2 - r3}                   @ get values for "aborted" pc and cpsr (into parm regs)
-	add	r0, sp, #S_FRAME_SIZE		@ grab pointer to old stack
-
-	add	r5, sp, #S_SP
-	mov	r1, lr
-	stmia	r5, {r0 - r3}                   @ save sp_SVC, lr_SVC, pc, cpsr
-	mov	r0, sp                          @ save current stack into r0 (param register)
-	.endm
-
-	.macro	irq_save_user_regs
-	sub	sp, sp, #S_FRAME_SIZE
-	stmia	sp, {r0 - r12}			@ Calling r0-r12
-	add     r8, sp, #S_PC                   @ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good.
-	stmdb   r8, {sp, lr}^                   @ Calling SP, LR
-	str     lr, [r8, #0]                    @ Save calling PC
-	mrs     r6, spsr
-	str     r6, [r8, #4]                    @ Save CPSR
-	str     r0, [r8, #8]                    @ Save OLD_R0
-	mov	r0, sp
-	.endm
-
-	.macro	irq_restore_user_regs
-	ldmia	sp, {r0 - lr}^			@ Calling r0 - lr
-	mov	r0, r0
-	ldr	lr, [sp, #S_PC]			@ Get PC
-	add	sp, sp, #S_FRAME_SIZE
-	subs	pc, lr, #4			@ return & move spsr_svc into cpsr
-	.endm
-
-	.macro get_bad_stack
-	ldr	r13, IRQ_STACK_START_IN
-
-	str	lr, [r13]			@ save caller lr in position 0 of saved stack
-	mrs	lr, spsr                        @ get the spsr
-	str     lr, [r13, #4]                   @ save spsr in position 1 of saved stack
-
-	mov	r13, #MODE_SVC			@ prepare SVC-Mode
-	@ msr	spsr_c, r13
-	msr	spsr, r13                       @ switch modes, make sure moves will execute
-	mov	lr, pc                          @ capture return pc
-	movs	pc, lr                          @ jump to next instruction & switch modes.
-	.endm
-
-	.macro get_irq_stack			@ setup IRQ stack
-	ldr	sp, IRQ_STACK_START
-	.endm
-
-	.macro get_fiq_stack			@ setup FIQ stack
-	ldr	sp, FIQ_STACK_START
-	.endm
-
-/*
- * exception handlers
- */
-	.align  5
-undefined_instruction:
-	get_bad_stack
-	bad_save_user_regs
-	bl	do_undefined_instruction
-
-	.align	5
-software_interrupt:
-	get_bad_stack
-	bad_save_user_regs
-	bl	do_software_interrupt
-
-	.align	5
-prefetch_abort:
-	get_bad_stack
-	bad_save_user_regs
-	bl	do_prefetch_abort
-
-	.align	5
-data_abort:
-	get_bad_stack
-	bad_save_user_regs
-	bl	do_data_abort
-
-	.align	5
-not_used:
-	get_bad_stack
-	bad_save_user_regs
-	bl	do_not_used
-
-#ifdef CONFIG_USE_IRQ
-
-	.align	5
-irq:
-	get_irq_stack
-	irq_save_user_regs
-	bl	do_irq
-	irq_restore_user_regs
-
-	.align	5
-fiq:
-	get_fiq_stack
-	/* someone ought to write a more effiction fiq_save_user_regs */
-	irq_save_user_regs
-	bl	do_fiq
-	irq_restore_user_regs
-
-#else
-
-	.align	5
-irq:
-	get_bad_stack
-	bad_save_user_regs
-	bl	do_irq
-
-	.align	5
-fiq:
-	get_bad_stack
-	bad_save_user_regs
-	bl	do_fiq
-
-#endif
-
-	.align	5
-.globl reset_cpu
-reset_cpu:
-	ldr	r1, rstctl1     /* get clkm1 reset ctl */
-	mov     r3, #0x3	/* dsp_en + arm_rst = global reset */
-	strh	r3, [r1]        /* force reset */
-	mov	r0, r0
-_loop_forever:
-	b	_loop_forever
-rstctl1:
-	.word	0xfffece10
diff --git a/arch/arm/cpu/arm925t/timer.c b/arch/arm/cpu/arm925t/timer.c
deleted file mode 100644
index 7dfe2b5..0000000
--- a/arch/arm/cpu/arm925t/timer.c
+++ /dev/null
@@ -1,137 +0,0 @@
-/*
- * (C) Copyright 2009
- * 2N Telekomunikace, <www.2n.cz>
- *
- * (C) Copyright 2003
- * Texas Instruments, <www.ti.com>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Alex Zuepke <azu@sysgo.de>
- *
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <arm925t.h>
-#include <configs/omap1510.h>
-#include <asm/io.h>
-
-#define TIMER_LOAD_VAL	0xffffffff
-#define TIMER_CLOCK	(CONFIG_SYS_CLK_FREQ / (2 << CONFIG_SYS_PTV))
-
-static uint32_t timestamp;
-static uint32_t lastdec;
-
-/* nothing really to do with interrupts, just starts up a counter. */
-int timer_init (void)
-{
-	/* Start the decrementer ticking down from 0xffffffff */
-	__raw_writel(TIMER_LOAD_VAL, CONFIG_SYS_TIMERBASE + LOAD_TIM);
-	__raw_writel(MPUTIM_ST | MPUTIM_AR | MPUTIM_CLOCK_ENABLE |
-		(CONFIG_SYS_PTV << MPUTIM_PTV_BIT),
-		CONFIG_SYS_TIMERBASE + CNTL_TIMER);
-
-	/* init the timestamp and lastdec value */
-	reset_timer_masked();
-
-	return 0;
-}
-
-/*
- * timer without interrupts
- */
-
-void reset_timer (void)
-{
-	reset_timer_masked ();
-}
-
-ulong get_timer (ulong base)
-{
-	return get_timer_masked () - base;
-}
-
-void set_timer (ulong t)
-{
-	timestamp = t;
-}
-
-/* delay x useconds AND preserve advance timestamp value */
-void __udelay (unsigned long usec)
-{
-	int32_t tmo = usec * (TIMER_CLOCK / 1000) / 1000;
-	uint32_t now, last = __raw_readl(CONFIG_SYS_TIMERBASE + READ_TIM);
-
-	while (tmo > 0) {
-		now = __raw_readl(CONFIG_SYS_TIMERBASE + READ_TIM);
-		if (last < now) /* count down timer underflow */
-			tmo -= TIMER_LOAD_VAL - now + last;
-		else
-			tmo -= last - now;
-		last = now;
-	}
-}
-
-void reset_timer_masked (void)
-{
-	/* reset time */
-	lastdec = __raw_readl(CONFIG_SYS_TIMERBASE + READ_TIM) /
-			(TIMER_CLOCK / CONFIG_SYS_HZ);
-	timestamp = 0;	       /* start "advancing" time stamp from 0 */
-}
-
-ulong get_timer_masked (void)
-{
-	uint32_t now = __raw_readl(CONFIG_SYS_TIMERBASE + READ_TIM) /
-			(TIMER_CLOCK / CONFIG_SYS_HZ);
-	if (lastdec < now)	/* count down timer underflow */
-		timestamp += TIMER_LOAD_VAL / (TIMER_CLOCK / CONFIG_SYS_HZ) -
-				now + lastdec;
-	else
-		timestamp += lastdec - now;
-	lastdec = now;
-
-	return timestamp;
-}
-
-/*
- * This function is derived from PowerPC code (read timebase as long long).
- * On ARM it just returns the timer value.
- */
-unsigned long long get_ticks(void)
-{
-	return get_timer(0);
-}
-
-/*
- * This function is derived from PowerPC code (timebase clock frequency).
- * On ARM it returns the number of timer ticks per second.
- */
-ulong get_tbclk (void)
-{
-	return CONFIG_SYS_HZ;
-}
diff --git a/arch/arm/cpu/arm925t/u-boot.lds b/arch/arm/cpu/arm925t/u-boot.lds
deleted file mode 100644
index 7b53edb..0000000
--- a/arch/arm/cpu/arm925t/u-boot.lds
+++ /dev/null
@@ -1,81 +0,0 @@
-/*
- * (C) Copyright 2004
- * Wolfgang Denk, DENX Software Engineering, <wg@denx.de>
- *
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-ENTRY(_start)
-SECTIONS
-{
-	. = 0x00000000;
-
-	. = ALIGN(4);
-	.text :
-	{
-		arch/arm/cpu/arm925t/start.o	(.text)
-		*(.text)
-	}
-
-	. = ALIGN(4);
-	.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
-
-	. = ALIGN(4);
-	.data : {
-		*(.data)
-	}
-
-	. = ALIGN(4);
-
-	. = .;
-	__u_boot_cmd_start = .;
-	.u_boot_cmd : { *(.u_boot_cmd) }
-	__u_boot_cmd_end = .;
-
-	. = ALIGN(4);
-
-	.rel.dyn : {
-		__rel_dyn_start = .;
-		*(.rel*)
-		__rel_dyn_end = .;
-	}
-
-	.dynsym : {
-		__dynsym_start = .;
-		*(.dynsym)
-	}
-
-	.bss __rel_dyn_start (OVERLAY) : {
-		__bss_start = .;
-		*(.bss)
-		 . = ALIGN(4);
-		_end = .;
-	}
-
-	/DISCARD/ : { *(.dynstr*) }
-	/DISCARD/ : { *(.dynamic*) }
-	/DISCARD/ : { *(.plt*) }
-	/DISCARD/ : { *(.interp*) }
-	/DISCARD/ : { *(.gnu*) }
-}
diff --git a/arch/arm/cpu/arm926ejs/Makefile b/arch/arm/cpu/arm926ejs/Makefile
deleted file mode 100644
index 930e0d1..0000000
--- a/arch/arm/cpu/arm926ejs/Makefile
+++ /dev/null
@@ -1,47 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(CPU).o
-
-START	= start.o
-COBJS	= cpu.o
-
-SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS) $(SOBJS))
-START	:= $(addprefix $(obj),$(START))
-
-all:	$(obj).depend $(START) $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/arch/arm/cpu/arm926ejs/armada100/Makefile b/arch/arm/cpu/arm926ejs/armada100/Makefile
deleted file mode 100644
index 76bd06d..0000000
--- a/arch/arm/cpu/arm926ejs/armada100/Makefile
+++ /dev/null
@@ -1,46 +0,0 @@
-#
-# (C) Copyright 2010
-# Marvell Semiconductor <www.marvell.com>
-# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
-# MA 02110-1301 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(SOC).o
-
-COBJS-y	= cpu.o timer.o dram.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS-y))
-
-all:	$(obj).depend $(LIB)
-
-$(LIB):	$(OBJS)
-	$(AR) $(ARFLAGS) $@ $(OBJS)
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/arch/arm/cpu/arm926ejs/armada100/cpu.c b/arch/arm/cpu/arm926ejs/armada100/cpu.c
deleted file mode 100644
index 62aa175..0000000
--- a/arch/arm/cpu/arm926ejs/armada100/cpu.c
+++ /dev/null
@@ -1,92 +0,0 @@
-/*
- * (C) Copyright 2010
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
- * Contributor: Mahavir Jain <mjain@marvell.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-#include <common.h>
-#include <asm/arch/armada100.h>
-#include <asm/io.h>
-
-#define UARTCLK14745KHZ	(APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(1))
-#define SET_MRVL_ID	(1<<8)
-#define L2C_RAM_SEL	(1<<4)
-
-int arch_cpu_init(void)
-{
-	u32 val;
-	struct armd1cpu_registers *cpuregs =
-		(struct armd1cpu_registers *) ARMD1_CPU_BASE;
-
-	struct armd1apb1_registers *apb1clkres =
-		(struct armd1apb1_registers *) ARMD1_APBC1_BASE;
-
-	struct armd1mpmu_registers *mpmu =
-		(struct armd1mpmu_registers *) ARMD1_MPMU_BASE;
-
-	/* set SEL_MRVL_ID bit in ARMADA100_CPU_CONF register */
-	val = readl(&cpuregs->cpu_conf);
-	val = val | SET_MRVL_ID;
-	writel(val, &cpuregs->cpu_conf);
-
-	/* Enable Clocks for all hardware units */
-	writel(0xFFFFFFFF, &mpmu->acgr);
-
-	/* Turn on AIB and AIB-APB Functional clock */
-	writel(APBC_APBCLK | APBC_FNCLK, &apb1clkres->aib);
-
-	/* ensure L2 cache is not mapped as SRAM */
-	val = readl(&cpuregs->cpu_conf);
-	val = val & ~(L2C_RAM_SEL);
-	writel(val, &cpuregs->cpu_conf);
-
-	/* Enable GPIO clock */
-	writel(APBC_APBCLK, &apb1clkres->gpio);
-
-	/*
-	 * Enable Functional and APB clock at 14.7456MHz
-	 * for configured UART console
-	 */
-#if (CONFIG_SYS_NS16550_COM1 == ARMD1_UART3_BASE)
-	writel(UARTCLK14745KHZ, &apb1clkres->uart3);
-#elif (CONFIG_SYS_NS16550_COM1 == ARMD1_UART2_BASE)
-	writel(UARTCLK14745KHZ, &apb1clkres->uart2);
-#else
-	writel(UARTCLK14745KHZ, &apb1clkres->uart1);
-#endif
-	icache_enable();
-
-	return 0;
-}
-
-#if defined(CONFIG_DISPLAY_CPUINFO)
-int print_cpuinfo(void)
-{
-	u32 id;
-	struct armd1cpu_registers *cpuregs =
-		(struct armd1cpu_registers *) ARMD1_CPU_BASE;
-
-	id = readl(&cpuregs->chip_id);
-	printf("SoC:   Armada 88AP%X-%X\n", (id & 0xFFF), (id >> 0x10));
-	return 0;
-}
-#endif
diff --git a/arch/arm/cpu/arm926ejs/armada100/dram.c b/arch/arm/cpu/arm926ejs/armada100/dram.c
deleted file mode 100644
index eacec23..0000000
--- a/arch/arm/cpu/arm926ejs/armada100/dram.c
+++ /dev/null
@@ -1,131 +0,0 @@
-/*
- * (C) Copyright 2010
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Prafulla Wadaskar <prafulla@marvell.com>,
- * Contributor: Mahavir Jain <mjain@marvell.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-#include <common.h>
-#include <asm/arch/armada100.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*
- * ARMADA100 DRAM controller supports upto 8 banks
- * for chip select 0 and 1
- */
-
-/*
- * DDR Memory Control Registers
- * Refer Datasheet Appendix A.17
- */
-struct armd1ddr_map_registers {
-	u32	cs;	/* Memory Address Map Register -CS */
-	u32	pad[3];
-};
-
-struct armd1ddr_registers {
-	u8	pad[0x100 - 0x000];
-	struct armd1ddr_map_registers mmap[2];
-};
-
-/*
- * armd1_sdram_base - reads SDRAM Base Address Register
- */
-u32 armd1_sdram_base(int chip_sel)
-{
-	struct armd1ddr_registers *ddr_regs =
-		(struct armd1ddr_registers *)ARMD1_DRAM_BASE;
-	u32 result = 0;
-	u32 CS_valid = 0x01 & readl(&ddr_regs->mmap[chip_sel].cs);
-
-	if (!CS_valid)
-		return 0;
-
-	result = readl(&ddr_regs->mmap[chip_sel].cs) & 0xFF800000;
-	return result;
-}
-
-/*
- * armd1_sdram_size - reads SDRAM size
- */
-u32 armd1_sdram_size(int chip_sel)
-{
-	struct armd1ddr_registers *ddr_regs =
-		(struct armd1ddr_registers *)ARMD1_DRAM_BASE;
-	u32 result = 0;
-	u32 CS_valid = 0x01 & readl(&ddr_regs->mmap[chip_sel].cs);
-
-	if (!CS_valid)
-		return 0;
-
-	result = readl(&ddr_regs->mmap[chip_sel].cs);
-	result = (result >> 16) & 0xF;
-	if (result < 0x7) {
-		printf("Unknown DRAM Size\n");
-		return -1;
-	} else {
-		return ((0x8 << (result - 0x7)) * 1024 * 1024);
-	}
-}
-
-#ifndef CONFIG_SYS_BOARD_DRAM_INIT
-int dram_init(void)
-{
-	int i;
-
-	gd->ram_size = 0;
-	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
-		gd->bd->bi_dram[i].start = armd1_sdram_base(i);
-		gd->bd->bi_dram[i].size = armd1_sdram_size(i);
-		/*
-		 * It is assumed that all memory banks are consecutive
-		 * and without gaps.
-		 * If the gap is found, ram_size will be reported for
-		 * consecutive memory only
-		 */
-		if (gd->bd->bi_dram[i].start != gd->ram_size)
-			break;
-
-		gd->ram_size += gd->bd->bi_dram[i].size;
-
-	}
-
-	for (; i < CONFIG_NR_DRAM_BANKS; i++) {
-		/* If above loop terminated prematurely, we need to set
-		 * remaining banks' start address & size as 0. Otherwise other
-		 * u-boot functions and Linux kernel gets wrong values which
-		 * could result in crash */
-		gd->bd->bi_dram[i].start = 0;
-		gd->bd->bi_dram[i].size = 0;
-	}
-	return 0;
-}
-
-/*
- * If this function is not defined here,
- * board.c alters dram bank zero configuration defined above.
- */
-void dram_init_banksize(void)
-{
-	dram_init();
-}
-#endif /* CONFIG_SYS_BOARD_DRAM_INIT */
diff --git a/arch/arm/cpu/arm926ejs/armada100/timer.c b/arch/arm/cpu/arm926ejs/armada100/timer.c
deleted file mode 100644
index 5d911c5..0000000
--- a/arch/arm/cpu/arm926ejs/armada100/timer.c
+++ /dev/null
@@ -1,207 +0,0 @@
-/*
- * (C) Copyright 2010
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
- * Contributor: Mahavir Jain <mjain@marvell.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-#include <common.h>
-#include <asm/arch/armada100.h>
-
-/*
- * Timer registers
- * Refer Section A.6 in Datasheet
- */
-struct armd1tmr_registers {
-	u32 clk_ctrl;	/* Timer clk control reg */
-	u32 match[9];	/* Timer match registers */
-	u32 count[3];	/* Timer count registers */
-	u32 status[3];
-	u32 ie[3];
-	u32 preload[3];	/* Timer preload value */
-	u32 preload_ctrl[3];
-	u32 wdt_match_en;
-	u32 wdt_match_r;
-	u32 wdt_val;
-	u32 wdt_sts;
-	u32 icr[3];
-	u32 wdt_icr;
-	u32 cer;	/* Timer count enable reg */
-	u32 cmr;
-	u32 ilr[3];
-	u32 wcr;
-	u32 wfar;
-	u32 wsar;
-	u32 cvwr;
-};
-
-#define TIMER			0	/* Use TIMER 0 */
-/* Each timer has 3 match registers */
-#define MATCH_CMP(x)		((3 * TIMER) + x)
-#define TIMER_LOAD_VAL 		0xffffffff
-#define	COUNT_RD_REQ		0x1
-
-DECLARE_GLOBAL_DATA_PTR;
-/* Using gd->tbu from timestamp and gd->tbl for lastdec */
-
-/* For preventing risk of instability in reading counter value,
- * first set read request to register cvwr and then read same
- * register after it captures counter value.
- */
-ulong read_timer(void)
-{
-	struct armd1tmr_registers *armd1timers =
-		(struct armd1tmr_registers *) ARMD1_TIMER_BASE;
-	volatile int loop=100;
-
-	writel(COUNT_RD_REQ, &armd1timers->cvwr);
-	while (loop--);
-	return(readl(&armd1timers->cvwr));
-}
-
-void reset_timer_masked(void)
-{
-	/* reset time */
-	gd->tbl = read_timer();
-	gd->tbu = 0;
-}
-
-ulong get_timer_masked(void)
-{
-	ulong now = read_timer();
-
-	if (now >= gd->tbl) {
-		/* normal mode */
-		gd->tbu += now - gd->tbl;
-	} else {
-		/* we have an overflow ... */
-		gd->tbu += now + TIMER_LOAD_VAL - gd->tbl;
-	}
-	gd->tbl = now;
-
-	return gd->tbu;
-}
-
-void reset_timer(void)
-{
-	reset_timer_masked();
-}
-
-ulong get_timer(ulong base)
-{
-	return ((get_timer_masked() / (CONFIG_SYS_HZ_CLOCK / 1000)) -
-		base);
-}
-
-void set_timer(ulong t)
-{
-	gd->tbu = t;
-}
-
-void __udelay(unsigned long usec)
-{
-	ulong delayticks;
-	ulong endtime;
-
-	delayticks = (usec * (CONFIG_SYS_HZ_CLOCK / 1000000));
-	endtime = get_timer_masked() + delayticks;
-
-	while (get_timer_masked() < endtime);
-}
-
-/*
- * init the Timer
- */
-int timer_init(void)
-{
-	struct armd1apb1_registers *apb1clkres =
-		(struct armd1apb1_registers *) ARMD1_APBC1_BASE;
-	struct armd1tmr_registers *armd1timers =
-		(struct armd1tmr_registers *) ARMD1_TIMER_BASE;
-
-	/* Enable Timer clock at 3.25 MHZ */
-	writel(APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(3), &apb1clkres->timers);
-
-	/* load value into timer */
-	writel(0x0, &armd1timers->clk_ctrl);
-	/* Use Timer 0 Match Resiger 0 */
-	writel(TIMER_LOAD_VAL, &armd1timers->match[MATCH_CMP(0)]);
-	/* Preload value is 0 */
-	writel(0x0, &armd1timers->preload[TIMER]);
-	/* Enable match comparator 0 for Timer 0 */
-	writel(0x1, &armd1timers->preload_ctrl[TIMER]);
-
-	/* Enable timer 0 */
-	writel(0x1, &armd1timers->cer);
-	/* init the gd->tbu and gd->tbl value */
-	reset_timer_masked();
-
-	return 0;
-}
-
-#define MPMU_APRR_WDTR	(1<<4)
-#define TMR_WFAR	0xbaba	/* WDT Register First key */
-#define TMP_WSAR	0xeb10	/* WDT Register Second key */
-
-/*
- * This function uses internal Watchdog Timer
- * based reset mechanism.
- * Steps to write watchdog registers (protected access)
- * 1. Write key value to TMR_WFAR reg.
- * 2. Write key value to TMP_WSAR reg.
- * 3. Perform write operation.
- */
-void reset_cpu (unsigned long ignored)
-{
-	struct armd1mpmu_registers *mpmu =
-		(struct armd1mpmu_registers *) ARMD1_MPMU_BASE;
-	struct armd1tmr_registers *armd1timers =
-		(struct armd1tmr_registers *) ARMD1_TIMER_BASE;
-	u32 val;
-
-	/* negate hardware reset to the WDT after system reset */
-	val = readl(&mpmu->aprr);
-	val = val | MPMU_APRR_WDTR;
-	writel(val, &mpmu->aprr);
-
-	/* reset/enable WDT clock */
-	writel(APBC_APBCLK | APBC_FNCLK | APBC_RST, &mpmu->wdtpcr);
-	readl(&mpmu->wdtpcr);
-	writel(APBC_APBCLK | APBC_FNCLK, &mpmu->wdtpcr);
-	readl(&mpmu->wdtpcr);
-
-	/* clear previous WDT status */
-	writel(TMR_WFAR, &armd1timers->wfar);
-	writel(TMP_WSAR, &armd1timers->wsar);
-	writel(0, &armd1timers->wdt_sts);
-
-	/* set match counter */
-	writel(TMR_WFAR, &armd1timers->wfar);
-	writel(TMP_WSAR, &armd1timers->wsar);
-	writel(0xf, &armd1timers->wdt_match_r);
-
-	/* enable WDT reset */
-	writel(TMR_WFAR, &armd1timers->wfar);
-	writel(TMP_WSAR, &armd1timers->wsar);
-	writel(0x3, &armd1timers->wdt_match_en);
-
-	while(1);
-}
diff --git a/arch/arm/cpu/arm926ejs/at91/Makefile b/arch/arm/cpu/arm926ejs/at91/Makefile
deleted file mode 100644
index be9f6dd..0000000
--- a/arch/arm/cpu/arm926ejs/at91/Makefile
+++ /dev/null
@@ -1,63 +0,0 @@
-#
-# (C) Copyright 2000-2008
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(SOC).o
-
-COBJS-$(CONFIG_AT91CAP9)	+= at91cap9_devices.o
-COBJS-$(CONFIG_AT91SAM9260)	+= at91sam9260_devices.o
-COBJS-$(CONFIG_AT91SAM9G20)	+= at91sam9260_devices.o
-COBJS-$(CONFIG_AT91SAM9261)	+= at91sam9261_devices.o
-COBJS-$(CONFIG_AT91SAM9G10)	+= at91sam9261_devices.o
-COBJS-$(CONFIG_AT91SAM9263)	+= at91sam9263_devices.o
-COBJS-$(CONFIG_AT91SAM9RL)	+= at91sam9rl_devices.o
-COBJS-$(CONFIG_AT91SAM9M10G45)	+= at91sam9m10g45_devices.o
-COBJS-$(CONFIG_AT91SAM9G45)	+= at91sam9m10g45_devices.o
-COBJS-$(CONFIG_AT91_EFLASH)	+= eflash.o
-COBJS-$(CONFIG_AT91_LED)	+= led.o
-COBJS-y += clock.o
-COBJS-y += cpu.o
-COBJS-y	+= reset.o
-COBJS-y	+= timer.o
-
-ifndef CONFIG_SKIP_LOWLEVEL_INIT
-SOBJS-y	:= lowlevel_init.o
-endif
-
-SRCS    := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
-OBJS    := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
-
-all:	$(obj).depend $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/arch/arm/cpu/arm926ejs/at91/at91cap9_devices.c b/arch/arm/cpu/arm926ejs/at91/at91cap9_devices.c
deleted file mode 100644
index 2d878fd..0000000
--- a/arch/arm/cpu/arm926ejs/at91/at91cap9_devices.c
+++ /dev/null
@@ -1,205 +0,0 @@
-/*
- * (C) Copyright 2007-2008
- * Stelian Pop <stelian.pop@leadtechdesign.com>
- * Lead Tech Design <www.leadtechdesign.com>
- *
- * (C) Copyright 2009
- * Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
- * esd electronic system design gmbh <www.esd.eu>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/arch/at91_common.h>
-#include <asm/arch/at91_pmc.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/io.h>
-
-void at91_serial0_hw_init(void)
-{
-	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
-
-	at91_set_a_periph(AT91_PIO_PORTA, 22, 1);		/* TXD0 */
-	at91_set_a_periph(AT91_PIO_PORTA, 23, 0);		/* RXD0 */
-	writel(1 << AT91CAP9_ID_US0, &pmc->pcer);
-}
-
-void at91_serial1_hw_init(void)
-{
-	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
-
-	at91_set_a_periph(AT91_PIO_PORTD, 0, 1);		/* TXD1 */
-	at91_set_a_periph(AT91_PIO_PORTD, 1, 0);		/* RXD1 */
-	writel(1 << AT91CAP9_ID_US1, &pmc->pcer);
-}
-
-void at91_serial2_hw_init(void)
-{
-	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
-
-	at91_set_a_periph(AT91_PIO_PORTD, 2, 1);		/* TXD2 */
-	at91_set_a_periph(AT91_PIO_PORTD, 3, 0);		/* RXD2 */
-	writel(1 << AT91CAP9_ID_US2, &pmc->pcer);
-}
-
-void at91_serial3_hw_init(void)
-{
-	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
-
-	at91_set_a_periph(AT91_PIO_PORTC, 30, 0);		/* DRXD */
-	at91_set_a_periph(AT91_PIO_PORTC, 31, 1);		/* DTXD */
-	writel(1 << AT91_ID_SYS, &pmc->pcer);
-}
-
-void at91_serial_hw_init(void)
-{
-#ifdef CONFIG_USART0
-	at91_serial0_hw_init();
-#endif
-
-#ifdef CONFIG_USART1
-	at91_serial1_hw_init();
-#endif
-
-#ifdef CONFIG_USART2
-	at91_serial2_hw_init();
-#endif
-
-#ifdef CONFIG_USART3	/* DBGU */
-	at91_serial3_hw_init();
-#endif
-}
-
-#ifdef CONFIG_HAS_DATAFLASH
-void at91_spi0_hw_init(unsigned long cs_mask)
-{
-	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
-
-	at91_set_b_periph(AT91_PIO_PORTA, 0, 0);	/* SPI0_MISO */
-	at91_set_b_periph(AT91_PIO_PORTA, 1, 0);	/* SPI0_MOSI */
-	at91_set_b_periph(AT91_PIO_PORTA, 2, 0);	/* SPI0_SPCK */
-
-	/* Enable clock */
-	writel(1 << AT91CAP9_ID_SPI0, &pmc->pcer);
-
-	if (cs_mask & (1 << 0)) {
-		at91_set_b_periph(AT91_PIO_PORTA, 5, 1);
-	}
-	if (cs_mask & (1 << 1)) {
-		at91_set_b_periph(AT91_PIO_PORTA, 3, 1);
-	}
-	if (cs_mask & (1 << 2)) {
-		at91_set_b_periph(AT91_PIO_PORTD, 0, 1);
-	}
-	if (cs_mask & (1 << 3)) {
-		at91_set_b_periph(AT91_PIO_PORTD, 1, 1);
-	}
-	if (cs_mask & (1 << 4)) {
-		at91_set_pio_output(AT91_PIO_PORTA, 5, 1);
-	}
-	if (cs_mask & (1 << 5)) {
-		at91_set_pio_output(AT91_PIO_PORTA, 3, 1);
-	}
-	if (cs_mask & (1 << 6)) {
-		at91_set_pio_output(AT91_PIO_PORTD, 0, 1);
-	}
-	if (cs_mask & (1 << 7)) {
-		at91_set_pio_output(AT91_PIO_PORTD, 1, 1);
-	}
-}
-
-void at91_spi1_hw_init(unsigned long cs_mask)
-{
-	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
-
-	at91_set_a_periph(AT91_PIO_PORTB, 12, 0);	/* SPI1_MISO */
-	at91_set_a_periph(AT91_PIO_PORTB, 13, 0);	/* SPI1_MOSI */
-	at91_set_a_periph(AT91_PIO_PORTB, 14, 0);	/* SPI1_SPCK */
-
-	/* Enable clock */
-	writel(1 << AT91CAP9_ID_SPI1, &pmc->pcer);
-
-	if (cs_mask & (1 << 0)) {
-		at91_set_a_periph(AT91_PIO_PORTB, 15, 1);
-	}
-	if (cs_mask & (1 << 1)) {
-		at91_set_a_periph(AT91_PIO_PORTB, 16, 1);
-	}
-	if (cs_mask & (1 << 2)) {
-		at91_set_a_periph(AT91_PIO_PORTB, 17, 1);
-	}
-	if (cs_mask & (1 << 3)) {
-		at91_set_a_periph(AT91_PIO_PORTB, 18, 1);
-	}
-	if (cs_mask & (1 << 4)) {
-		at91_set_pio_output(AT91_PIO_PORTB, 15, 1);
-	}
-	if (cs_mask & (1 << 5)) {
-		at91_set_pio_output(AT91_PIO_PORTB, 16, 1);
-	}
-	if (cs_mask & (1 << 6)) {
-		at91_set_pio_output(AT91_PIO_PORTB, 17, 1);
-	}
-	if (cs_mask & (1 << 7)) {
-		at91_set_pio_output(AT91_PIO_PORTB, 18, 1);
-	}
-
-}
-#endif
-
-#ifdef CONFIG_MACB
-void at91_macb_hw_init(void)
-{
-	at91_set_a_periph(AT91_PIO_PORTB, 21, 0);	/* ETXCK_EREFCK */
-	at91_set_a_periph(AT91_PIO_PORTB, 22, 0);	/* ERXDV */
-	at91_set_a_periph(AT91_PIO_PORTB, 25, 0);	/* ERX0 */
-	at91_set_a_periph(AT91_PIO_PORTB, 26, 0);	/* ERX1 */
-	at91_set_a_periph(AT91_PIO_PORTB, 27, 0);	/* ERXER */
-	at91_set_a_periph(AT91_PIO_PORTB, 28, 0);	/* ETXEN */
-	at91_set_a_periph(AT91_PIO_PORTB, 23, 0);	/* ETX0 */
-	at91_set_a_periph(AT91_PIO_PORTB, 24, 0);	/* ETX1 */
-	at91_set_a_periph(AT91_PIO_PORTB, 30, 0);	/* EMDIO */
-	at91_set_a_periph(AT91_PIO_PORTB, 29, 0);	/* EMDC */
-
-#ifndef CONFIG_RMII
-	at91_set_b_periph(AT91_PIO_PORTC, 25, 0);	/* ECRS */
-	at91_set_b_periph(AT91_PIO_PORTC, 26, 0);	/* ECOL */
-	at91_set_b_periph(AT91_PIO_PORTC, 22, 0);	/* ERX2 */
-	at91_set_b_periph(AT91_PIO_PORTC, 23, 0);	/* ERX3 */
-	at91_set_b_periph(AT91_PIO_PORTC, 27, 0);	/* ERXCK */
-	at91_set_b_periph(AT91_PIO_PORTC, 20, 0);	/* ETX2 */
-	at91_set_b_periph(AT91_PIO_PORTC, 21, 0);	/* ETX3 */
-	at91_set_b_periph(AT91_PIO_PORTC, 24, 0);	/* ETXER */
-#endif
-}
-#endif
-
-#ifdef CONFIG_AT91_CAN
-void at91_can_hw_init(void)
-{
-	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
-
-	at91_set_a_periph(AT91_PIO_PORTA, 12, 0);	/* CAN_TX */
-	at91_set_a_periph(AT91_PIO_PORTA, 13, 1);	/* CAN_RX */
-
-	/* Enable clock */
-	writel(1 << AT91CAP9_ID_CAN, &pmc->pcer);
-}
-#endif
diff --git a/arch/arm/cpu/arm926ejs/at91/at91sam9260_devices.c b/arch/arm/cpu/arm926ejs/at91/at91sam9260_devices.c
deleted file mode 100644
index c1822b7..0000000
--- a/arch/arm/cpu/arm926ejs/at91/at91sam9260_devices.c
+++ /dev/null
@@ -1,236 +0,0 @@
-/*
- * (C) Copyright 2007-2008
- * Stelian Pop <stelian.pop@leadtechdesign.com>
- * Lead Tech Design <www.leadtechdesign.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/arch/at91_common.h>
-#include <asm/arch/at91_pmc.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/io.h>
-
-/*
- * if CONFIG_AT91_GPIO_PULLUP ist set, keep pullups on on all
- * peripheral pins. Good to have if hardware is soldered optionally
- * or in case of SPI no slave is selected. Avoid lines to float
- * needlessly. Use a short local PUP define.
- *
- * Due to errata "TXD floats when CTS is inactive" pullups are always
- * on for TXD pins.
- */
-#ifdef CONFIG_AT91_GPIO_PULLUP
-# define PUP CONFIG_AT91_GPIO_PULLUP
-#else
-# define PUP 0
-#endif
-
-void at91_serial0_hw_init(void)
-{
-	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
-
-	at91_set_a_periph(AT91_PIO_PORTB, 4, 1);		/* TXD0 */
-	at91_set_a_periph(AT91_PIO_PORTB, 5, PUP);		/* RXD0 */
-	writel(1 << AT91SAM9260_ID_US0, &pmc->pcer);
-}
-
-void at91_serial1_hw_init(void)
-{
-	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
-
-	at91_set_a_periph(AT91_PIO_PORTB, 6, 1);		/* TXD1 */
-	at91_set_a_periph(AT91_PIO_PORTB, 7, PUP);		/* RXD1 */
-	writel(1 << AT91SAM9260_ID_US1, &pmc->pcer);
-}
-
-void at91_serial2_hw_init(void)
-{
-	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
-
-	at91_set_a_periph(AT91_PIO_PORTB, 8, 1);		/* TXD2 */
-	at91_set_a_periph(AT91_PIO_PORTB, 9, PUP);		/* RXD2 */
-	writel(1 << AT91SAM9260_ID_US2, &pmc->pcer);
-}
-
-void at91_serial3_hw_init(void)
-{
-	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
-
-	at91_set_a_periph(AT91_PIO_PORTB, 14, PUP);		/* DRXD */
-	at91_set_a_periph(AT91_PIO_PORTB, 15, 1);		/* DTXD */
-	writel(1 << AT91_ID_SYS, &pmc->pcer);
-}
-
-void at91_serial_hw_init(void)
-{
-#ifdef CONFIG_USART0
-	at91_serial0_hw_init();
-#endif
-
-#ifdef CONFIG_USART1
-	at91_serial1_hw_init();
-#endif
-
-#ifdef CONFIG_USART2
-	at91_serial2_hw_init();
-#endif
-
-#ifdef CONFIG_USART3	/* DBGU */
-	at91_serial3_hw_init();
-#endif
-}
-
-#if defined(CONFIG_HAS_DATAFLASH) || defined(CONFIG_ATMEL_SPI)
-void at91_spi0_hw_init(unsigned long cs_mask)
-{
-	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
-
-	at91_set_a_periph(AT91_PIO_PORTA, 0, PUP);	/* SPI0_MISO */
-	at91_set_a_periph(AT91_PIO_PORTA, 1, PUP);	/* SPI0_MOSI */
-	at91_set_a_periph(AT91_PIO_PORTA, 2, PUP);	/* SPI0_SPCK */
-
-	/* Enable clock */
-	writel(1 << AT91SAM9260_ID_SPI0, &pmc->pcer);
-
-	if (cs_mask & (1 << 0)) {
-		at91_set_a_periph(AT91_PIO_PORTA, 3, 1);
-	}
-	if (cs_mask & (1 << 1)) {
-		at91_set_b_periph(AT91_PIO_PORTC, 11, 1);
-	}
-	if (cs_mask & (1 << 2)) {
-		at91_set_b_periph(AT91_PIO_PORTC, 16, 1);
-	}
-	if (cs_mask & (1 << 3)) {
-		at91_set_b_periph(AT91_PIO_PORTC, 17, 1);
-	}
-	if (cs_mask & (1 << 4)) {
-		at91_set_pio_output(AT91_PIO_PORTA, 3, 1);
-	}
-	if (cs_mask & (1 << 5)) {
-		at91_set_pio_output(AT91_PIO_PORTC, 11, 1);
-	}
-	if (cs_mask & (1 << 6)) {
-		at91_set_pio_output(AT91_PIO_PORTC, 16, 1);
-	}
-	if (cs_mask & (1 << 7)) {
-		at91_set_pio_output(AT91_PIO_PORTC, 17, 1);
-	}
-}
-
-void at91_spi1_hw_init(unsigned long cs_mask)
-{
-	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
-
-	at91_set_a_periph(AT91_PIO_PORTB, 0, PUP);	/* SPI1_MISO */
-	at91_set_a_periph(AT91_PIO_PORTB, 1, PUP);	/* SPI1_MOSI */
-	at91_set_a_periph(AT91_PIO_PORTB, 2, PUP);	/* SPI1_SPCK */
-
-	/* Enable clock */
-	writel(1 << AT91SAM9260_ID_SPI1, &pmc->pcer);
-
-	if (cs_mask & (1 << 0)) {
-		at91_set_a_periph(AT91_PIO_PORTB, 3, 1);
-	}
-	if (cs_mask & (1 << 1)) {
-		at91_set_b_periph(AT91_PIO_PORTC, 5, 1);
-	}
-	if (cs_mask & (1 << 2)) {
-		at91_set_b_periph(AT91_PIO_PORTC, 4, 1);
-	}
-	if (cs_mask & (1 << 3)) {
-		at91_set_pio_output(AT91_PIO_PORTC, 3, 1);
-	}
-	if (cs_mask & (1 << 4)) {
-		at91_set_pio_output(AT91_PIO_PORTB, 3, 1);
-	}
-	if (cs_mask & (1 << 5)) {
-		at91_set_pio_output(AT91_PIO_PORTC, 5, 1);
-	}
-	if (cs_mask & (1 << 6)) {
-		at91_set_pio_output(AT91_PIO_PORTC, 4, 1);
-	}
-	if (cs_mask & (1 << 7)) {
-		at91_set_pio_output(AT91_PIO_PORTC, 3, 1);
-	}
-}
-#endif
-
-#ifdef CONFIG_MACB
-void at91_macb_hw_init(void)
-{
-	at91_set_a_periph(AT91_PIO_PORTA, 19, 0);	/* ETXCK_EREFCK */
-	at91_set_a_periph(AT91_PIO_PORTA, 17, 0);	/* ERXDV */
-	at91_set_a_periph(AT91_PIO_PORTA, 14, 0);	/* ERX0 */
-	at91_set_a_periph(AT91_PIO_PORTA, 15, 0);	/* ERX1 */
-	at91_set_a_periph(AT91_PIO_PORTA, 18, 0);	/* ERXER */
-	at91_set_a_periph(AT91_PIO_PORTA, 16, 0);	/* ETXEN */
-	at91_set_a_periph(AT91_PIO_PORTA, 12, 0);	/* ETX0 */
-	at91_set_a_periph(AT91_PIO_PORTA, 13, 0);	/* ETX1 */
-	at91_set_a_periph(AT91_PIO_PORTA, 21, 0);	/* EMDIO */
-	at91_set_a_periph(AT91_PIO_PORTA, 20, 0);	/* EMDC */
-
-#ifndef CONFIG_RMII
-	at91_set_b_periph(AT91_PIO_PORTA, 28, 0);	/* ECRS */
-	at91_set_b_periph(AT91_PIO_PORTA, 29, 0);	/* ECOL */
-	at91_set_b_periph(AT91_PIO_PORTA, 25, 0);	/* ERX2 */
-	at91_set_b_periph(AT91_PIO_PORTA, 26, 0);	/* ERX3 */
-	at91_set_b_periph(AT91_PIO_PORTA, 27, 0);	/* ERXCK */
-#if defined(CONFIG_AT91SAM9260EK) || defined(CONFIG_AFEB9260)
-	/*
-	 * use PA10, PA11 for ETX2, ETX3.
-	 * PA23 and PA24 are for TWI EEPROM
-	 */
-	at91_set_b_periph(AT91_PIO_PORTA, 10, 0);	/* ETX2 */
-	at91_set_b_periph(AT91_PIO_PORTA, 11, 0);	/* ETX3 */
-#else
-	at91_set_b_periph(AT91_PIO_PORTA, 23, 0);	/* ETX2 */
-	at91_set_b_periph(AT91_PIO_PORTA, 24, 0);	/* ETX3 */
-#if defined(CONFIG_AT91SAM9G20)
-	/* 9G20 BOOT ROM initializes those pins to multi-drive, undo that */
-	at91_set_pio_multi_drive(AT91_PIO_PORTA, 23, 0);
-	at91_set_pio_multi_drive(AT91_PIO_PORTA, 24, 0);
-#endif
-#endif
-	at91_set_b_periph(AT91_PIO_PORTA, 22, 0);	/* ETXER */
-#endif
-}
-#endif
-
-#if defined(CONFIG_ATMEL_MCI) || defined(CONFIG_GENERIC_ATMEL_MCI)
-void at91_mci_hw_init(void)
-{
-	at91_set_a_periph(AT91_PIO_PORTA, 8, 1);	/* MCCK */
-#if defined(CONFIG_ATMEL_MCI_PORTB)
-	at91_set_b_periph(AT91_PIO_PORTA, 1, 1);	/* MCCDB */
-	at91_set_b_periph(AT91_PIO_PORTA, 0, 1);	/* MCDB0 */
-	at91_set_b_periph(AT91_PIO_PORTA, 5, 1);	/* MCDB1 */
-	at91_set_b_periph(AT91_PIO_PORTA, 4, 1);	/* MCDB2 */
-	at91_set_b_periph(AT91_PIO_PORTA, 3, 1);	/* MCDB3 */
-#else
-	at91_set_a_periph(AT91_PIO_PORTA, 7, 1);	/* MCCDA */
-	at91_set_a_periph(AT91_PIO_PORTA, 6, 1);	/* MCDA0 */
-	at91_set_a_periph(AT91_PIO_PORTA, 9, 1);	/* MCDA1 */
-	at91_set_a_periph(AT91_PIO_PORTA, 10, 1);	/* MCDA2 */
-	at91_set_a_periph(AT91_PIO_PORTA, 11, 1);	/* MCDA3 */
-#endif
-}
-#endif
diff --git a/arch/arm/cpu/arm926ejs/at91/at91sam9261_devices.c b/arch/arm/cpu/arm926ejs/at91/at91sam9261_devices.c
deleted file mode 100644
index b4353ef..0000000
--- a/arch/arm/cpu/arm926ejs/at91/at91sam9261_devices.c
+++ /dev/null
@@ -1,160 +0,0 @@
-/*
- * (C) Copyright 2007-2008
- * Stelian Pop <stelian.pop@leadtechdesign.com>
- * Lead Tech Design <www.leadtechdesign.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/arch/at91_common.h>
-#include <asm/arch/at91_pmc.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/io.h>
-
-void at91_serial0_hw_init(void)
-{
-	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
-
-	at91_set_a_periph(AT91_PIO_PORTC, 8, 1);		/* TXD0 */
-	at91_set_a_periph(AT91_PIO_PORTC, 9, 0);		/* RXD0 */
-	writel(1 << AT91SAM9261_ID_US0, &pmc->pcer);
-}
-
-void at91_serial1_hw_init(void)
-{
-	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
-
-	at91_set_a_periph(AT91_PIO_PORTC, 12, 1);		/* TXD1 */
-	at91_set_a_periph(AT91_PIO_PORTC, 13, 0);		/* RXD1 */
-	writel(1 << AT91SAM9261_ID_US1, &pmc->pcer);
-}
-
-void at91_serial2_hw_init(void)
-{
-	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
-
-	at91_set_a_periph(AT91_PIO_PORTC, 14, 1);		/* TXD2 */
-	at91_set_a_periph(AT91_PIO_PORTC, 15, 0);		/* RXD2 */
-	writel(1 << AT91SAM9261_ID_US2, &pmc->pcer);
-}
-
-void at91_serial3_hw_init(void)
-{
-	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
-
-	at91_set_a_periph(AT91_PIO_PORTA, 9, 0);		/* DRXD */
-	at91_set_a_periph(AT91_PIO_PORTA, 10, 1);		/* DTXD */
-	writel(1 << AT91_ID_SYS, &pmc->pcer);
-}
-
-void at91_serial_hw_init(void)
-{
-#ifdef CONFIG_USART0
-	at91_serial0_hw_init();
-#endif
-
-#ifdef CONFIG_USART1
-	at91_serial1_hw_init();
-#endif
-
-#ifdef CONFIG_USART2
-	at91_serial2_hw_init();
-#endif
-
-#ifdef CONFIG_USART3	/* DBGU */
-	at91_serial3_hw_init();
-#endif
-}
-
-#ifdef CONFIG_HAS_DATAFLASH
-void at91_spi0_hw_init(unsigned long cs_mask)
-{
-	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
-
-	at91_set_a_periph(AT91_PIO_PORTA, 0, 0);	/* SPI0_MISO */
-	at91_set_a_periph(AT91_PIO_PORTA, 1, 0);	/* SPI0_MOSI */
-	at91_set_a_periph(AT91_PIO_PORTA, 2, 0);	/* SPI0_SPCK */
-
-	/* Enable clock */
-	writel(1 << AT91SAM9261_ID_SPI0, &pmc->pcer);
-
-	if (cs_mask & (1 << 0)) {
-		at91_set_a_periph(AT91_PIO_PORTA, 3, 1);
-	}
-	if (cs_mask & (1 << 1)) {
-		at91_set_a_periph(AT91_PIO_PORTA, 4, 1);
-	}
-	if (cs_mask & (1 << 2)) {
-		at91_set_a_periph(AT91_PIO_PORTA, 5, 1);
-	}
-	if (cs_mask & (1 << 3)) {
-		at91_set_a_periph(AT91_PIO_PORTA, 6, 1);
-	}
-	if (cs_mask & (1 << 4)) {
-		at91_set_pio_output(AT91_PIO_PORTA, 3, 1);
-	}
-	if (cs_mask & (1 << 5)) {
-		at91_set_pio_output(AT91_PIO_PORTA, 4, 1);
-	}
-	if (cs_mask & (1 << 6)) {
-		at91_set_pio_output(AT91_PIO_PORTA, 5, 1);
-	}
-	if (cs_mask & (1 << 7)) {
-		at91_set_pio_output(AT91_PIO_PORTA, 6, 1);
-	}
-}
-
-void at91_spi1_hw_init(unsigned long cs_mask)
-{
-	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
-
-	at91_set_a_periph(AT91_PIO_PORTB, 30, 0);	/* SPI1_MISO */
-	at91_set_a_periph(AT91_PIO_PORTB, 31, 0);	/* SPI1_MOSI */
-	at91_set_a_periph(AT91_PIO_PORTB, 29, 0);	/* SPI1_SPCK */
-
-	/* Enable clock */
-	writel(1 << AT91SAM9261_ID_SPI1, &pmc->pcer);
-
-	if (cs_mask & (1 << 0)) {
-		at91_set_a_periph(AT91_PIO_PORTB, 28, 1);
-	}
-	if (cs_mask & (1 << 1)) {
-		at91_set_b_periph(AT91_PIO_PORTA, 24, 1);
-	}
-	if (cs_mask & (1 << 2)) {
-		at91_set_b_periph(AT91_PIO_PORTA, 25, 1);
-	}
-	if (cs_mask & (1 << 3)) {
-		at91_set_a_periph(AT91_PIO_PORTA, 26, 1);
-	}
-	if (cs_mask & (1 << 4)) {
-		at91_set_pio_output(AT91_PIO_PORTB, 28, 1);
-	}
-	if (cs_mask & (1 << 5)) {
-		at91_set_pio_output(AT91_PIO_PORTA, 24, 1);
-	}
-	if (cs_mask & (1 << 6)) {
-		at91_set_pio_output(AT91_PIO_PORTA, 25, 1);
-	}
-	if (cs_mask & (1 << 7)) {
-		at91_set_pio_output(AT91_PIO_PORTA, 26, 1);
-	}
-}
-#endif
diff --git a/arch/arm/cpu/arm926ejs/at91/at91sam9263_devices.c b/arch/arm/cpu/arm926ejs/at91/at91sam9263_devices.c
deleted file mode 100644
index deda3e5..0000000
--- a/arch/arm/cpu/arm926ejs/at91/at91sam9263_devices.c
+++ /dev/null
@@ -1,214 +0,0 @@
-/*
- * (C) Copyright 2007-2008
- * Stelian Pop <stelian.pop@leadtechdesign.com>
- * Lead Tech Design <www.leadtechdesign.com>
- *
- * (C) Copyright 2009
- * Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
- * esd electronic system design gmbh <www.esd.eu>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/io.h>
-#include <asm/arch/at91_common.h>
-#include <asm/arch/at91_pmc.h>
-#include <asm/arch/at91_pio.h>
-
-void at91_serial0_hw_init(void)
-{
-	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
-
-	at91_set_a_periph(AT91_PIO_PORTA, 26, 1);		/* TXD0 */
-	at91_set_a_periph(AT91_PIO_PORTA, 27, 0);		/* RXD0 */
-	writel(1 << AT91SAM9263_ID_US0, &pmc->pcer);
-}
-
-void at91_serial1_hw_init(void)
-{
-	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
-
-	at91_set_a_periph(AT91_PIO_PORTD, 0, 1);		/* TXD1 */
-	at91_set_a_periph(AT91_PIO_PORTD, 1, 0);		/* RXD1 */
-	writel(1 << AT91SAM9263_ID_US1, &pmc->pcer);
-}
-
-void at91_serial2_hw_init(void)
-{
-	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
-
-	at91_set_a_periph(AT91_PIO_PORTD, 2, 1);		/* TXD2 */
-	at91_set_a_periph(AT91_PIO_PORTD, 3, 0);		/* RXD2 */
-	writel(1 << AT91SAM9263_ID_US2, &pmc->pcer);
-}
-
-void at91_serial3_hw_init(void)
-{
-	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
-
-	at91_set_a_periph(AT91_PIO_PORTC, 30, 0);		/* DRXD */
-	at91_set_a_periph(AT91_PIO_PORTC, 31, 1);		/* DTXD */
-	writel(1 << AT91_ID_SYS, &pmc->pcer);
-}
-
-void at91_serial_hw_init(void)
-{
-#ifdef CONFIG_USART0
-	at91_serial0_hw_init();
-#endif
-
-#ifdef CONFIG_USART1
-	at91_serial1_hw_init();
-#endif
-
-#ifdef CONFIG_USART2
-	at91_serial2_hw_init();
-#endif
-
-#ifdef CONFIG_USART3	/* DBGU */
-	at91_serial3_hw_init();
-#endif
-}
-
-#ifdef CONFIG_HAS_DATAFLASH
-void at91_spi0_hw_init(unsigned long cs_mask)
-{
-	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
-
-	at91_set_b_periph(AT91_PIO_PORTA, 0, 0);	/* SPI0_MISO */
-	at91_set_b_periph(AT91_PIO_PORTA, 1, 0);	/* SPI0_MOSI */
-	at91_set_b_periph(AT91_PIO_PORTA, 2, 0);	/* SPI0_SPCK */
-
-	/* Enable clock */
-	writel(1 << AT91SAM9263_ID_SPI0, &pmc->pcer);
-
-	if (cs_mask & (1 << 0)) {
-		at91_set_b_periph(AT91_PIO_PORTA, 5, 1);
-	}
-	if (cs_mask & (1 << 1)) {
-		at91_set_b_periph(AT91_PIO_PORTA, 3, 1);
-	}
-	if (cs_mask & (1 << 2)) {
-		at91_set_b_periph(AT91_PIO_PORTA, 4, 1);
-	}
-	if (cs_mask & (1 << 3)) {
-		at91_set_b_periph(AT91_PIO_PORTB, 11, 1);
-	}
-	if (cs_mask & (1 << 4)) {
-		at91_set_pio_output(AT91_PIO_PORTA, 5, 1);
-	}
-	if (cs_mask & (1 << 5)) {
-		at91_set_pio_output(AT91_PIO_PORTA, 3, 1);
-	}
-	if (cs_mask & (1 << 6)) {
-		at91_set_pio_output(AT91_PIO_PORTA, 4, 1);
-	}
-	if (cs_mask & (1 << 7)) {
-		at91_set_pio_output(AT91_PIO_PORTB, 11, 1);
-	}
-}
-
-void at91_spi1_hw_init(unsigned long cs_mask)
-{
-	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
-
-	at91_set_a_periph(AT91_PIO_PORTB, 12, 0);	/* SPI1_MISO */
-	at91_set_a_periph(AT91_PIO_PORTB, 13, 0);	/* SPI1_MOSI */
-	at91_set_a_periph(AT91_PIO_PORTB, 14, 0);	/* SPI1_SPCK */
-
-	/* Enable clock */
-	writel(1 << AT91SAM9263_ID_SPI1, &pmc->pcer);
-
-	if (cs_mask & (1 << 0)) {
-		at91_set_a_periph(AT91_PIO_PORTB, 15, 1);
-	}
-	if (cs_mask & (1 << 1)) {
-		at91_set_a_periph(AT91_PIO_PORTB, 16, 1);
-	}
-	if (cs_mask & (1 << 2)) {
-		at91_set_a_periph(AT91_PIO_PORTB, 17, 1);
-	}
-	if (cs_mask & (1 << 3)) {
-		at91_set_a_periph(AT91_PIO_PORTB, 18, 1);
-	}
-	if (cs_mask & (1 << 4)) {
-		at91_set_pio_output(AT91_PIO_PORTB, 15, 1);
-	}
-	if (cs_mask & (1 << 5)) {
-		at91_set_pio_output(AT91_PIO_PORTB, 16, 1);
-	}
-	if (cs_mask & (1 << 6)) {
-		at91_set_pio_output(AT91_PIO_PORTB, 17, 1);
-	}
-	if (cs_mask & (1 << 7)) {
-		at91_set_pio_output(AT91_PIO_PORTB, 18, 1);
-	}
-}
-#endif
-
-#ifdef CONFIG_MACB
-void at91_macb_hw_init(void)
-{
-	at91_set_a_periph(AT91_PIO_PORTE, 21, 0);	/* ETXCK_EREFCK */
-	at91_set_b_periph(AT91_PIO_PORTC, 25, 0);	/* ERXDV */
-	at91_set_a_periph(AT91_PIO_PORTE, 25, 0);	/* ERX0 */
-	at91_set_a_periph(AT91_PIO_PORTE, 26, 0);	/* ERX1 */
-	at91_set_a_periph(AT91_PIO_PORTE, 27, 0);	/* ERXER */
-	at91_set_a_periph(AT91_PIO_PORTE, 28, 0);	/* ETXEN */
-	at91_set_a_periph(AT91_PIO_PORTE, 23, 0);	/* ETX0 */
-	at91_set_a_periph(AT91_PIO_PORTE, 24, 0);	/* ETX1 */
-	at91_set_a_periph(AT91_PIO_PORTE, 30, 0);	/* EMDIO */
-	at91_set_a_periph(AT91_PIO_PORTE, 29, 0);	/* EMDC */
-
-#ifndef CONFIG_RMII
-	at91_set_a_periph(AT91_PIO_PORTE, 22, 0);	/* ECRS */
-	at91_set_b_periph(AT91_PIO_PORTC, 26, 0);	/* ECOL */
-	at91_set_b_periph(AT91_PIO_PORTC, 22, 0);	/* ERX2 */
-	at91_set_b_periph(AT91_PIO_PORTC, 23, 0);	/* ERX3 */
-	at91_set_b_periph(AT91_PIO_PORTC, 27, 0);	/* ERXCK */
-	at91_set_b_periph(AT91_PIO_PORTC, 20, 0);	/* ETX2 */
-	at91_set_b_periph(AT91_PIO_PORTC, 21, 0);	/* ETX3 */
-	at91_set_b_periph(AT91_PIO_PORTC, 24, 0);	/* ETXER */
-#endif
-}
-#endif
-
-#ifdef CONFIG_USB_OHCI_NEW
-void at91_uhp_hw_init(void)
-{
-	/* Enable VBus on UHP ports */
-	at91_set_pio_output(AT91_PIO_PORTA, 21, 0);
-	at91_set_pio_output(AT91_PIO_PORTA, 24, 0);
-}
-#endif
-
-#ifdef CONFIG_AT91_CAN
-void at91_can_hw_init(void)
-{
-	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
-
-	at91_set_a_periph(AT91_PIO_PORTA, 13, 0);	/* CAN_TX */
-	at91_set_a_periph(AT91_PIO_PORTA, 14, 1);	/* CAN_RX */
-
-	/* Enable clock */
-	writel(1 << AT91SAM9263_ID_CAN, &pmc->pcer);
-}
-#endif
diff --git a/arch/arm/cpu/arm926ejs/at91/at91sam9m10g45_devices.c b/arch/arm/cpu/arm926ejs/at91/at91sam9m10g45_devices.c
deleted file mode 100644
index 4ad9b1f..0000000
--- a/arch/arm/cpu/arm926ejs/at91/at91sam9m10g45_devices.c
+++ /dev/null
@@ -1,187 +0,0 @@
-/*
- * (C) Copyright 2007-2008
- * Stelian Pop <stelian.pop@leadtechdesign.com>
- * Lead Tech Design <www.leadtechdesign.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/arch/at91_common.h>
-#include <asm/arch/at91_pmc.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/io.h>
-
-void at91_serial0_hw_init(void)
-{
-	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
-
-	at91_set_a_periph(AT91_PIO_PORTB, 19, 1);	/* TXD0 */
-	at91_set_a_periph(AT91_PIO_PORTB, 18, 0);	/* RXD0 */
-	writel(1 << AT91SAM9G45_ID_US0, &pmc->pcer);
-}
-
-void at91_serial1_hw_init(void)
-{
-	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
-
-	at91_set_a_periph(AT91_PIO_PORTB, 4, 1);		/* TXD1 */
-	at91_set_a_periph(AT91_PIO_PORTB, 5, 0);		/* RXD1 */
-	writel(1 << AT91SAM9G45_ID_US1, &pmc->pcer);
-}
-
-void at91_serial2_hw_init(void)
-{
-	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
-
-	at91_set_a_periph(AT91_PIO_PORTD, 6, 1);		/* TXD2 */
-	at91_set_a_periph(AT91_PIO_PORTD, 7, 0);		/* RXD2 */
-	writel(1 << AT91SAM9G45_ID_US2, &pmc->pcer);
-}
-
-void at91_serial3_hw_init(void)
-{
-	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
-
-	at91_set_a_periph(AT91_PIO_PORTB, 12, 0);	/* DRXD */
-	at91_set_a_periph(AT91_PIO_PORTB, 13, 1);	/* DTXD */
-	writel(1 << AT91_ID_SYS, &pmc->pcer);
-}
-
-void at91_serial_hw_init(void)
-{
-#ifdef CONFIG_USART0
-	at91_serial0_hw_init();
-#endif
-
-#ifdef CONFIG_USART1
-	at91_serial1_hw_init();
-#endif
-
-#ifdef CONFIG_USART2
-	at91_serial2_hw_init();
-#endif
-
-#ifdef CONFIG_USART3	/* DBGU */
-	at91_serial3_hw_init();
-#endif
-}
-
-#ifdef CONFIG_ATMEL_SPI
-void at91_spi0_hw_init(unsigned long cs_mask)
-{
-	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
-
-	at91_set_a_periph(AT91_PIO_PORTB, 0, 0);	/* SPI0_MISO */
-	at91_set_a_periph(AT91_PIO_PORTB, 1, 0);	/* SPI0_MOSI */
-	at91_set_a_periph(AT91_PIO_PORTB, 2, 0);	/* SPI0_SPCK */
-
-	/* Enable clock */
-	writel(1 << AT91SAM9G45_ID_SPI0, &pmc->pcer);
-
-	if (cs_mask & (1 << 0)) {
-		at91_set_a_periph(AT91_PIO_PORTB, 3, 0);
-	}
-	if (cs_mask & (1 << 1)) {
-		at91_set_b_periph(AT91_PIO_PORTB, 18, 0);
-	}
-	if (cs_mask & (1 << 2)) {
-		at91_set_b_periph(AT91_PIO_PORTB, 19, 0);
-	}
-	if (cs_mask & (1 << 3)) {
-		at91_set_b_periph(AT91_PIO_PORTD, 27, 0);
-	}
-	if (cs_mask & (1 << 4)) {
-		at91_set_pio_output(AT91_PIO_PORTB, 3, 0);
-	}
-	if (cs_mask & (1 << 5)) {
-		at91_set_pio_output(AT91_PIO_PORTB, 18, 0);
-	}
-	if (cs_mask & (1 << 6)) {
-		at91_set_pio_output(AT91_PIO_PORTB, 19, 0);
-	}
-	if (cs_mask & (1 << 7)) {
-		at91_set_pio_output(AT91_PIO_PORTD, 27, 0);
-	}
-}
-
-void at91_spi1_hw_init(unsigned long cs_mask)
-{
-	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
-
-	at91_set_a_periph(AT91_PIO_PORTB, 14, 0);	/* SPI1_MISO */
-	at91_set_a_periph(AT91_PIO_PORTB, 15, 0);	/* SPI1_MOSI */
-	at91_set_a_periph(AT91_PIO_PORTB, 16, 0);	/* SPI1_SPCK */
-
-	/* Enable clock */
-	writel(1 << AT91SAM9G45_ID_SPI1, &pmc->pcer);
-
-	if (cs_mask & (1 << 0)) {
-		at91_set_a_periph(AT91_PIO_PORTB, 17, 0);
-	}
-	if (cs_mask & (1 << 1)) {
-		at91_set_b_periph(AT91_PIO_PORTD, 28, 0);
-	}
-	if (cs_mask & (1 << 2)) {
-		at91_set_a_periph(AT91_PIO_PORTD, 18, 0);
-	}
-	if (cs_mask & (1 << 3)) {
-		at91_set_a_periph(AT91_PIO_PORTD, 19, 0);
-	}
-	if (cs_mask & (1 << 4)) {
-		at91_set_pio_output(AT91_PIO_PORTB, 17, 0);
-	}
-	if (cs_mask & (1 << 5)) {
-		at91_set_pio_output(AT91_PIO_PORTD, 28, 0);
-	}
-	if (cs_mask & (1 << 6)) {
-		at91_set_pio_output(AT91_PIO_PORTD, 18, 0);
-	}
-	if (cs_mask & (1 << 7)) {
-		at91_set_pio_output(AT91_PIO_PORTD, 19, 0);
-	}
-
-}
-#endif
-
-#ifdef CONFIG_MACB
-void at91_macb_hw_init(void)
-{
-	at91_set_a_periph(AT91_PIO_PORTA, 17, 0);	/* ETXCK_EREFCK */
-	at91_set_a_periph(AT91_PIO_PORTA, 15, 0);	/* ERXDV */
-	at91_set_a_periph(AT91_PIO_PORTA, 12, 0);	/* ERX0 */
-	at91_set_a_periph(AT91_PIO_PORTA, 13, 0);	/* ERX1 */
-	at91_set_a_periph(AT91_PIO_PORTA, 16, 0);	/* ERXER */
-	at91_set_a_periph(AT91_PIO_PORTA, 14, 0);	/* ETXEN */
-	at91_set_a_periph(AT91_PIO_PORTA, 10, 0);	/* ETX0 */
-	at91_set_a_periph(AT91_PIO_PORTA, 11, 0);	/* ETX1 */
-	at91_set_a_periph(AT91_PIO_PORTA, 19, 0);	/* EMDIO */
-	at91_set_a_periph(AT91_PIO_PORTA, 18, 0);	/* EMDC */
-#ifndef CONFIG_RMII
-	at91_set_b_periph(AT91_PIO_PORTA, 29, 0);	/* ECRS */
-	at91_set_b_periph(AT91_PIO_PORTA, 30, 0);	/* ECOL */
-	at91_set_b_periph(AT91_PIO_PORTA, 8,  0);	/* ERX2 */
-	at91_set_b_periph(AT91_PIO_PORTA, 9,  0);	/* ERX3 */
-	at91_set_b_periph(AT91_PIO_PORTA, 28, 0);	/* ERXCK */
-	at91_set_b_periph(AT91_PIO_PORTA, 6,  0);	/* ETX2 */
-	at91_set_b_periph(AT91_PIO_PORTA, 7,  0);	/* ETX3 */
-	at91_set_b_periph(AT91_PIO_PORTA, 27, 0);	/* ETXER */
-#endif
-}
-#endif
diff --git a/arch/arm/cpu/arm926ejs/at91/at91sam9rl_devices.c b/arch/arm/cpu/arm926ejs/at91/at91sam9rl_devices.c
deleted file mode 100644
index 4f570f4..0000000
--- a/arch/arm/cpu/arm926ejs/at91/at91sam9rl_devices.c
+++ /dev/null
@@ -1,123 +0,0 @@
-/*
- * (C) Copyright 2007-2008
- * Stelian Pop <stelian.pop@leadtechdesign.com>
- * Lead Tech Design <www.leadtechdesign.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/arch/at91_common.h>
-#include <asm/arch/at91_pmc.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/io.h>
-
-void at91_serial0_hw_init(void)
-{
-	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
-
-	at91_set_a_periph(AT91_PIO_PORTA, 6, 1);		/* TXD0 */
-	at91_set_a_periph(AT91_PIO_PORTA, 7, 0);		/* RXD0 */
-	writel(1 << AT91SAM9RL_ID_US0, &pmc->pcer);
-}
-
-void at91_serial1_hw_init(void)
-{
-	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
-
-	at91_set_a_periph(AT91_PIO_PORTA, 11, 1);		/* TXD1 */
-	at91_set_a_periph(AT91_PIO_PORTA, 12, 0);		/* RXD1 */
-	writel(1 << AT91SAM9RL_ID_US1, &pmc->pcer);
-}
-
-void at91_serial2_hw_init(void)
-{
-	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
-
-	at91_set_a_periph(AT91_PIO_PORTA, 13, 1);		/* TXD2 */
-	at91_set_a_periph(AT91_PIO_PORTA, 14, 0);		/* RXD2 */
-	writel(1 << AT91SAM9RL_ID_US2, &pmc->pcer);
-}
-
-void at91_serial3_hw_init(void)
-{
-	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
-
-	at91_set_a_periph(AT91_PIO_PORTA, 21, 0);		/* DRXD */
-	at91_set_a_periph(AT91_PIO_PORTA, 22, 1);		/* DTXD */
-	writel(1 << AT91_ID_SYS, &pmc->pcer);
-}
-
-void at91_serial_hw_init(void)
-{
-#ifdef CONFIG_USART0
-	at91_serial0_hw_init();
-#endif
-
-#ifdef CONFIG_USART1
-	at91_serial1_hw_init();
-#endif
-
-#ifdef CONFIG_USART2
-	at91_serial2_hw_init();
-#endif
-
-#ifdef CONFIG_USART3	/* DBGU */
-	at91_serial3_hw_init();
-#endif
-}
-
-#ifdef CONFIG_HAS_DATAFLASH
-void at91_spi0_hw_init(unsigned long cs_mask)
-{
-	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
-
-	at91_set_a_periph(AT91_PIO_PORTA, 25, 0);	/* SPI0_MISO */
-	at91_set_a_periph(AT91_PIO_PORTA, 26, 0);	/* SPI0_MOSI */
-	at91_set_a_periph(AT91_PIO_PORTA, 27, 0);	/* SPI0_SPCK */
-
-	/* Enable clock */
-	writel(1 << AT91SAM9RL_ID_SPI, &pmc->pcer);
-
-	if (cs_mask & (1 << 0)) {
-		at91_set_a_periph(AT91_PIO_PORTA, 28, 1);
-	}
-	if (cs_mask & (1 << 1)) {
-		at91_set_b_periph(AT91_PIO_PORTB, 7, 1);
-	}
-	if (cs_mask & (1 << 2)) {
-		at91_set_a_periph(AT91_PIO_PORTD, 8, 1);
-	}
-	if (cs_mask & (1 << 3)) {
-		at91_set_b_periph(AT91_PIO_PORTD, 9, 1);
-	}
-	if (cs_mask & (1 << 4)) {
-		at91_set_pio_output(AT91_PIO_PORTA, 28, 1);
-	}
-	if (cs_mask & (1 << 5)) {
-		at91_set_pio_output(AT91_PIO_PORTB, 7, 1);
-	}
-	if (cs_mask & (1 << 6)) {
-		at91_set_pio_output(AT91_PIO_PORTD, 8, 1);
-	}
-	if (cs_mask & (1 << 7)) {
-		at91_set_pio_output(AT91_PIO_PORTD, 9, 1);
-	}
-}
-#endif
diff --git a/arch/arm/cpu/arm926ejs/at91/clock.c b/arch/arm/cpu/arm926ejs/at91/clock.c
deleted file mode 100644
index 7a10a77..0000000
--- a/arch/arm/cpu/arm926ejs/at91/clock.c
+++ /dev/null
@@ -1,215 +0,0 @@
-/*
- * [origin: Linux kernel linux/arch/arm/mach-at91/clock.c]
- *
- * Copyright (C) 2005 David Brownell
- * Copyright (C) 2005 Ivan Kokshaysky
- * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#include <common.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/io.h>
-#include <asm/arch/at91_pmc.h>
-#include <asm/arch/clk.h>
-
-#if !defined(CONFIG_AT91FAMILY)
-# error You need to define CONFIG_AT91FAMILY in your board config!
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-unsigned long get_cpu_clk_rate(void)
-{
-	return gd->cpu_clk_rate_hz;
-}
-
-unsigned long get_main_clk_rate(void)
-{
-	return gd->main_clk_rate_hz;
-}
-
-unsigned long get_mck_clk_rate(void)
-{
-	return gd->mck_rate_hz;
-}
-
-unsigned long get_plla_clk_rate(void)
-{
-	return gd->plla_rate_hz;
-}
-
-unsigned long get_pllb_clk_rate(void)
-{
-	return gd->pllb_rate_hz;
-}
-
-u32 get_pllb_init(void)
-{
-	return gd->at91_pllb_usb_init;
-}
-
-static unsigned long at91_css_to_rate(unsigned long css)
-{
-	switch (css) {
-	case AT91_PMC_MCKR_CSS_SLOW:
-		return AT91_SLOW_CLOCK;
-	case AT91_PMC_MCKR_CSS_MAIN:
-		return gd->main_clk_rate_hz;
-	case AT91_PMC_MCKR_CSS_PLLA:
-		return gd->plla_rate_hz;
-	case AT91_PMC_MCKR_CSS_PLLB:
-		return gd->pllb_rate_hz;
-	}
-
-	return 0;
-}
-
-#ifdef CONFIG_USB_ATMEL
-static unsigned at91_pll_calc(unsigned main_freq, unsigned out_freq)
-{
-	unsigned i, div = 0, mul = 0, diff = 1 << 30;
-	unsigned ret = (out_freq > 155000000) ? 0xbe00 : 0x3e00;
-
-	/* PLL output max 240 MHz (or 180 MHz per errata) */
-	if (out_freq > 240000000)
-		goto fail;
-
-	for (i = 1; i < 256; i++) {
-		int diff1;
-		unsigned input, mul1;
-
-		/*
-		 * PLL input between 1MHz and 32MHz per spec, but lower
-		 * frequences seem necessary in some cases so allow 100K.
-		 * Warning: some newer products need 2MHz min.
-		 */
-		input = main_freq / i;
-#if defined(CONFIG_AT91SAM9G20)
-		if (input < 2000000)
-			continue;
-#endif
-		if (input < 100000)
-			continue;
-		if (input > 32000000)
-			continue;
-
-		mul1 = out_freq / input;
-#if defined(CONFIG_AT91SAM9G20)
-		if (mul > 63)
-			continue;
-#endif
-		if (mul1 > 2048)
-			continue;
-		if (mul1 < 2)
-			goto fail;
-
-		diff1 = out_freq - input * mul1;
-		if (diff1 < 0)
-			diff1 = -diff1;
-		if (diff > diff1) {
-			diff = diff1;
-			div = i;
-			mul = mul1;
-			if (diff == 0)
-				break;
-		}
-	}
-	if (i == 256 && diff > (out_freq >> 5))
-		goto fail;
-	return ret | ((mul - 1) << 16) | div;
-fail:
-	return 0;
-}
-#endif
-
-static u32 at91_pll_rate(u32 freq, u32 reg)
-{
-	unsigned mul, div;
-
-	div = reg & 0xff;
-	mul = (reg >> 16) & 0x7ff;
-	if (div && mul) {
-		freq /= div;
-		freq *= mul + 1;
-	} else
-		freq = 0;
-
-	return freq;
-}
-
-int at91_clock_init(unsigned long main_clock)
-{
-	unsigned freq, mckr;
-	at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
-#ifndef CONFIG_SYS_AT91_MAIN_CLOCK
-	unsigned tmp;
-	/*
-	 * When the bootloader initialized the main oscillator correctly,
-	 * there's no problem using the cycle counter.  But if it didn't,
-	 * or when using oscillator bypass mode, we must be told the speed
-	 * of the main clock.
-	 */
-	if (!main_clock) {
-		do {
-			tmp = readl(&pmc->mcfr);
-		} while (!(tmp & AT91_PMC_MCFR_MAINRDY));
-		tmp &= AT91_PMC_MCFR_MAINF_MASK;
-		main_clock = tmp * (AT91_SLOW_CLOCK / 16);
-	}
-#endif
-	gd->main_clk_rate_hz = main_clock;
-
-	/* report if PLLA is more than mildly overclocked */
-	gd->plla_rate_hz = at91_pll_rate(main_clock, readl(&pmc->pllar));
-
-#ifdef CONFIG_USB_ATMEL
-	/*
-	 * USB clock init:  choose 48 MHz PLLB value,
-	 * disable 48MHz clock during usb peripheral suspend.
-	 *
-	 * REVISIT:  assumes MCK doesn't derive from PLLB!
-	 */
-	gd->at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) |
-			     AT91_PMC_PLLBR_USBDIV_2;
-	gd->pllb_rate_hz = at91_pll_rate(main_clock, gd->at91_pllb_usb_init);
-#endif
-
-	/*
-	 * MCK and CPU derive from one of those primary clocks.
-	 * For now, assume this parentage won't change.
-	 */
-	mckr = readl(&pmc->mckr);
-#if defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45)
-	/* plla divisor by 2 */
-	gd->plla_rate_hz /= (1 << ((mckr & 1 << 12) >> 12));
-#endif
-	gd->mck_rate_hz = at91_css_to_rate(mckr & AT91_PMC_MCKR_CSS_MASK);
-	freq = gd->mck_rate_hz;
-
-	freq /= (1 << ((mckr & AT91_PMC_MCKR_PRES_MASK) >> 2));	/* prescale */
-#if defined(CONFIG_AT91RM9200)
-	/* mdiv */
-	gd->mck_rate_hz = freq / (1 + ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8));
-#elif defined(CONFIG_AT91SAM9G20)
-	/* mdiv ; (x >> 7) = ((x >> 8) * 2) */
-	gd->mck_rate_hz = (mckr & AT91_PMC_MCKR_MDIV_MASK) ?
-		freq / ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 7) : freq;
-	if (mckr & AT91_PMC_MCKR_MDIV_MASK)
-		freq /= 2;			/* processor clock division */
-#elif defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45)
-	gd->mck_rate_hz = (mckr & AT91_PMC_MCKR_MDIV_MASK) ==
-		(AT91_PMC_MCKR_MDIV_2 | AT91_PMC_MCKR_MDIV_4)
-		? freq / 3
-		: freq / (1 << ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8));
-#else
-	gd->mck_rate_hz = freq / (1 << ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8));
-#endif
-	gd->cpu_clk_rate_hz = freq;
-
-	return 0;
-}
diff --git a/arch/arm/cpu/arm926ejs/at91/config.mk b/arch/arm/cpu/arm926ejs/at91/config.mk
deleted file mode 100644
index 19296fd..0000000
--- a/arch/arm/cpu/arm926ejs/at91/config.mk
+++ /dev/null
@@ -1 +0,0 @@
-PLATFORM_CPPFLAGS += $(call cc-option,-mtune=arm926ejs,)
diff --git a/arch/arm/cpu/arm926ejs/at91/cpu.c b/arch/arm/cpu/arm926ejs/at91/cpu.c
deleted file mode 100644
index 5e30f1d..0000000
--- a/arch/arm/cpu/arm926ejs/at91/cpu.c
+++ /dev/null
@@ -1,100 +0,0 @@
-/*
- * (C) Copyright 2010
- * Reinhard Meyer, reinhard.meyer@emk-elektronik.de
- * (C) Copyright 2009
- * Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-
-#include <asm/arch/hardware.h>
-#include <asm/arch/at91_pmc.h>
-#include <asm/arch/at91_pit.h>
-#include <asm/arch/at91_gpbr.h>
-#include <asm/arch/clk.h>
-#include <asm/arch/io.h>
-
-#ifndef CONFIG_SYS_AT91_MAIN_CLOCK
-#define CONFIG_SYS_AT91_MAIN_CLOCK 0
-#endif
-
-int arch_cpu_init(void)
-{
-	return at91_clock_init(CONFIG_SYS_AT91_MAIN_CLOCK);
-}
-
-void arch_preboot_os(void)
-{
-	ulong cpiv;
-	at91_pit_t *pit = (at91_pit_t *) AT91_PIT_BASE;
-
-	cpiv = AT91_PIT_MR_PIV_MASK(readl(&pit->piir));
-
-	/*
-	 * Disable PITC
-	 * Add 0x1000 to current counter to stop it faster
-	 * without waiting for wrapping back to 0
-	 */
-	writel(cpiv + 0x1000, &pit->mr);
-}
-
-#if defined(CONFIG_DISPLAY_CPUINFO)
-int print_cpuinfo(void)
-{
-	char buf[32];
-
-	printf("CPU: %s\n", CONFIG_SYS_AT91_CPU_NAME);
-	printf("Crystal frequency: %8s MHz\n",
-					strmhz(buf, get_main_clk_rate()));
-	printf("CPU clock        : %8s MHz\n",
-					strmhz(buf, get_cpu_clk_rate()));
-	printf("Master clock     : %8s MHz\n",
-					strmhz(buf, get_mck_clk_rate()));
-
-	return 0;
-}
-#endif
-
-#ifdef CONFIG_BOOTCOUNT_LIMIT
-/*
- * We combine the BOOTCOUNT_MAGIC and bootcount in one 32-bit register.
- * This is done so we need to use only one of the four GPBR registers.
- */
-void bootcount_store (ulong a)
-{
-	at91_gpbr_t *gpbr = (at91_gpbr_t *) AT91_GPR_BASE;
-
-	writel((BOOTCOUNT_MAGIC & 0xffff0000) | (a & 0x0000ffff),
-		&gpbr->reg[AT91_GPBR_INDEX_BOOTCOUNT]);
-}
-
-ulong bootcount_load (void)
-{
-	at91_gpbr_t *gpbr = (at91_gpbr_t *) AT91_GPR_BASE;
-
-	ulong val = readl(&gpbr->reg[AT91_GPBR_INDEX_BOOTCOUNT]);
-	if ((val & 0xffff0000) != (BOOTCOUNT_MAGIC & 0xffff0000))
-		return 0;
-	else
-		return val & 0x0000ffff;
-}
-
-#endif /* CONFIG_BOOTCOUNT_LIMIT */
diff --git a/arch/arm/cpu/arm926ejs/at91/eflash.c b/arch/arm/cpu/arm926ejs/at91/eflash.c
deleted file mode 100644
index 938c3b1..0000000
--- a/arch/arm/cpu/arm926ejs/at91/eflash.c
+++ /dev/null
@@ -1,270 +0,0 @@
-/*
- * (C) Copyright 2010
- * Reinhard Meyer, EMK Elektronik, reinhard.meyer@emk-elektronik.de
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * this driver supports the enhanced embedded flash in the Atmel
- * AT91SAM9XE devices with the following geometry:
- *
- * AT91SAM9XE128: 1 plane of  8 regions of 32 pages (total  256 pages)
- * AT91SAM9XE256: 1 plane of 16 regions of 32 pages (total  512 pages)
- * AT91SAM9XE512: 1 plane of 32 regions of 32 pages (total 1024 pages)
- * (the exact geometry is read from the flash at runtime, so any
- *  future devices should already be covered)
- *
- * Regions can be write/erase protected.
- * Whole (!) pages can be individually written with erase on the fly.
- * Writing partial pages will corrupt the rest of the page.
- *
- * The flash is presented to u-boot with each region being a sector,
- * having the following effects:
- * Each sector can be hardware protected (protect on/off).
- * Each page in a sector can be rewritten anytime.
- * Since pages are erased when written, the "erase" does nothing.
- * The first "CONFIG_EFLASH_PROTSECTORS" cannot be unprotected
- * by u-Boot commands.
- *
- * Note: Redundant environment will not work in this flash since
- * it does use partial page writes. Make sure the environent spans
- * whole pages!
- */
-
-/*
- * optional TODOs (nice to have features):
- *
- * make the driver coexist with other NOR flash drivers
- *	(use an index into flash_info[], requires work
- *	in those other drivers, too)
- * Make the erase command fill the sectors with 0xff
- *	(if the flashes grow larger in the future and
- *	someone puts a jffs2 into them)
- * do a read-modify-write for partially programmed pages
- */
-#include <common.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/io.h>
-#include <asm/arch/at91_common.h>
-#include <asm/arch/at91_eefc.h>
-#include <asm/arch/at91_dbu.h>
-
-/* checks to detect configuration errors */
-#if CONFIG_SYS_MAX_FLASH_BANKS!=1
-#error eflash: this driver can only handle 1 bank
-#endif
-
-/* global structure */
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
-static u32 pagesize;
-
-unsigned long flash_init (void)
-{
-	at91_eefc_t *eefc = (at91_eefc_t *) 0xfffffa00;
-	at91_dbu_t *dbu = (at91_dbu_t *) 0xfffff200;
-	u32 id, size, nplanes, planesize, nlocks;
-	u32 addr, i, tmp=0;
-
-	debug("eflash: init\n");
-
-	flash_info[0].flash_id = FLASH_UNKNOWN;
-
-	/* check if its an AT91ARM9XE SoC */
-	if ((readl(&dbu->cidr) & AT91_DBU_CID_ARCH_MASK) != AT91_DBU_CID_ARCH_9XExx) {
-		puts("eflash: not an AT91SAM9XE\n");
-		return 0;
-	}
-
-	/* now query the eflash for its structure */
-	writel(AT91_EEFC_FCR_KEY | AT91_EEFC_FCR_FCMD_GETD, &eefc->fcr);
-	while ((readl(&eefc->fsr) & AT91_EEFC_FSR_FRDY) == 0)
-		;
-	id = readl(&eefc->frr);		/* word 0 */
-	size = readl(&eefc->frr);	/* word 1 */
-	pagesize = readl(&eefc->frr);	/* word 2 */
-	nplanes = readl(&eefc->frr);	/* word 3 */
-	planesize = readl(&eefc->frr);	/* word 4 */
-	debug("id=%08x size=%u pagesize=%u planes=%u planesize=%u\n",
-		id, size, pagesize, nplanes, planesize);
-	for (i=1; i<nplanes; i++) {
-		tmp = readl(&eefc->frr);	/* words 5..4+nplanes-1 */
-	};
-	nlocks = readl(&eefc->frr);	/* word 4+nplanes */
-	debug("nlocks=%u\n", nlocks);
-	/* since we are going to use the lock regions as sectors, check count */
-	if (nlocks > CONFIG_SYS_MAX_FLASH_SECT) {
-		printf("eflash: number of lock regions(%u) "\
-			"> CONFIG_SYS_MAX_FLASH_SECT. reducing...\n",
-			nlocks);
-		nlocks = CONFIG_SYS_MAX_FLASH_SECT;
-	}
-	flash_info[0].size = size;
-	flash_info[0].sector_count = nlocks;
-	flash_info[0].flash_id = id;
-
-	addr = AT91SAM9XE_FLASH_BASE;
-	for (i=0; i<nlocks; i++) {
-		tmp = readl(&eefc->frr);	/* words 4+nplanes+1.. */
-		flash_info[0].start[i] = addr;
-		flash_info[0].protect[i] = 0;
-		addr += tmp;
-	};
-
-	/* now read the protection information for all regions */
-	writel(AT91_EEFC_FCR_KEY | AT91_EEFC_FCR_FCMD_GLB, &eefc->fcr);
-	while ((readl(&eefc->fsr) & AT91_EEFC_FSR_FRDY) == 0)
-		;
-	for (i=0; i<flash_info[0].sector_count; i++) {
-		if (i%32 == 0)
-			tmp = readl(&eefc->frr);
-		flash_info[0].protect[i] = (tmp >> (i%32)) & 1;
-#if defined(CONFIG_EFLASH_PROTSECTORS)
-		if (i < CONFIG_EFLASH_PROTSECTORS)
-			flash_info[0].protect[i] = 1;
-#endif
-	}
-
-	return size;
-}
-
-void flash_print_info (flash_info_t *info)
-{
-	int i;
-
-	puts("AT91SAM9XE embedded flash\n  Size: ");
-	print_size(info->size, " in ");
-	printf("%d Sectors\n", info->sector_count);
-
-	printf("  Sector Start Addresses:");
-	for (i=0; i<info->sector_count; ++i) {
-		if ((i % 5) == 0)
-			printf("\n   ");
-		printf(" %08lX%s",
-			info->start[i],
-			info->protect[i] ? " (RO)" : "     "
-		);
-	}
-	printf ("\n");
-	return;
-}
-
-int flash_real_protect (flash_info_t *info, long sector, int prot)
-{
-	at91_eefc_t *eefc = (at91_eefc_t *) 0xfffffa00;
-	u32 pagenum = (info->start[sector]-AT91SAM9XE_FLASH_BASE)/pagesize;
-	u32 i, tmp=0;
-
-	debug("protect sector=%ld prot=%d\n", sector, prot);
-
-#if defined(CONFIG_EFLASH_PROTSECTORS)
-	if (sector < CONFIG_EFLASH_PROTSECTORS) {
-		if (!prot) {
-			printf("eflash: sector %lu cannot be unprotected\n",
-				sector);
-		}
-		return 1; /* return anyway, caller does not care for result */
-	}
-#endif
-	if (prot) {
-		writel(AT91_EEFC_FCR_KEY | AT91_EEFC_FCR_FCMD_SLB |
-			(pagenum << AT91_EEFC_FCR_FARG_SHIFT), &eefc->fcr);
-	} else {
-		writel(AT91_EEFC_FCR_KEY | AT91_EEFC_FCR_FCMD_CLB |
-			(pagenum << AT91_EEFC_FCR_FARG_SHIFT), &eefc->fcr);
-	}
-	while ((readl(&eefc->fsr) & AT91_EEFC_FSR_FRDY) == 0)
-		;
-	/* now re-read the protection information for all regions */
-	writel(AT91_EEFC_FCR_KEY | AT91_EEFC_FCR_FCMD_GLB, &eefc->fcr);
-	while ((readl(&eefc->fsr) & AT91_EEFC_FSR_FRDY) == 0)
-		;
-	for (i=0; i<info->sector_count; i++) {
-		if (i%32 == 0)
-			tmp = readl(&eefc->frr);
-		info->protect[i] = (tmp >> (i%32)) & 1;
-	}
-	return 0;
-}
-
-static u32 erase_write_page (u32 pagenum)
-{
-	at91_eefc_t *eefc = (at91_eefc_t *) 0xfffffa00;
-
-	debug("erase+write page=%u\n", pagenum);
-
-	/* give erase and write page command */
-	writel(AT91_EEFC_FCR_KEY | AT91_EEFC_FCR_FCMD_EWP |
-		(pagenum << AT91_EEFC_FCR_FARG_SHIFT), &eefc->fcr);
-	while ((readl(&eefc->fsr) & AT91_EEFC_FSR_FRDY) == 0)
-		;
-	/* return status */
-	return readl(&eefc->fsr)
-		& (AT91_EEFC_FSR_FCMDE | AT91_EEFC_FSR_FLOCKE);
-}
-
-int flash_erase (flash_info_t *info, int s_first, int s_last)
-{
-	debug("erase first=%d last=%d\n", s_first, s_last);
-	puts("this flash does not need and support erasing!\n");
-	return 0;
-}
-
-/*
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- */
-
-int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
-{
-	u32 pagenum;
-	u32 *src32, *dst32;
-	u32 i;
-
-	debug("write src=%08lx addr=%08lx cnt=%lx\n",
-		(ulong)src, addr, cnt);
-
-	/* REQUIRE addr to be on a page start, abort if not */
-	if (addr % pagesize) {
-		printf ("eflash: start %08lx is not on page start\n"\
-			"        write aborted\n", addr);
-		return 1;
-	}
-
-	/* now start copying data */
-	pagenum = (addr-AT91SAM9XE_FLASH_BASE)/pagesize;
-	src32 = (u32 *) src;
-	dst32 = (u32 *) addr;
-	while (cnt > 0) {
-		i = pagesize / 4;
-		/* fill page buffer */
-		while (i--)
-			*dst32++ = *src32++;
-		/* write page */
-		if (erase_write_page(pagenum))
-			return 1;
-		pagenum++;
-		if (cnt > pagesize)
-			cnt -= pagesize;
-		else
-			cnt = 0;
-	}
-	return 0;
-}
diff --git a/arch/arm/cpu/arm926ejs/at91/led.c b/arch/arm/cpu/arm926ejs/at91/led.c
deleted file mode 100644
index 0a315c4..0000000
--- a/arch/arm/cpu/arm926ejs/at91/led.c
+++ /dev/null
@@ -1,65 +0,0 @@
-/*
- * (C) Copyright 2007-2008
- * Stelian Pop <stelian.pop@leadtechdesign.com>
- * Lead Tech Design <www.leadtechdesign.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/arch/at91_pmc.h>
-#include <asm/arch/at91_pio.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/io.h>
-
-#ifdef CONFIG_RED_LED
-void red_LED_on(void)
-{
-	at91_set_gpio_value(CONFIG_RED_LED, 1);
-}
-
-void red_LED_off(void)
-{
-	at91_set_gpio_value(CONFIG_RED_LED, 0);
-}
-#endif
-
-#ifdef CONFIG_GREEN_LED
-void green_LED_on(void)
-{
-	at91_set_gpio_value(CONFIG_GREEN_LED, 0);
-}
-
-void green_LED_off(void)
-{
-	at91_set_gpio_value(CONFIG_GREEN_LED, 1);
-}
-#endif
-
-#ifdef CONFIG_YELLOW_LED
-void yellow_LED_on(void)
-{
-	at91_set_gpio_value(CONFIG_YELLOW_LED, 0);
-}
-
-void yellow_LED_off(void)
-{
-	at91_set_gpio_value(CONFIG_YELLOW_LED, 1);
-}
-#endif
diff --git a/arch/arm/cpu/arm926ejs/at91/lowlevel_init.S b/arch/arm/cpu/arm926ejs/at91/lowlevel_init.S
deleted file mode 100644
index 7f7ca5e..0000000
--- a/arch/arm/cpu/arm926ejs/at91/lowlevel_init.S
+++ /dev/null
@@ -1,274 +0,0 @@
-/*
- * Memory Setup stuff - taken from blob memsetup.S
- *
- * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
- *		       Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
- *
- * Copyright (C) 2008 Ronetix Ilko Iliev (www.ronetix.at)
- * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/at91_pmc.h>
-#include <asm/arch/at91_wdt.h>
-#include <asm/arch/at91_pio.h>
-#include <asm/arch/at91_matrix.h>
-#include <asm/arch/at91sam9_sdramc.h>
-#include <asm/arch/at91sam9_smc.h>
-#include <asm/arch/at91_rstc.h>
-#ifdef CONFIG_AT91_LEGACY
-#include <asm/arch/at91sam9_matrix.h>
-#endif
-#ifndef CONFIG_SYS_MATRIX_EBICSA_VAL
-#define CONFIG_SYS_MATRIX_EBICSA_VAL CONFIG_SYS_MATRIX_EBI0CSA_VAL
-#endif
-
-_TEXT_BASE:
-	.word	CONFIG_SYS_TEXT_BASE
-
-.globl lowlevel_init
-.type lowlevel_init,function
-lowlevel_init:
-
-	mov	r5, pc		/* r5 = POS1 + 4 current */
-POS1:
-	ldr	r0, =POS1	/* r0 = POS1 compile */
-	ldr	r2, _TEXT_BASE
-	sub	r0, r0, r2	/* r0 = POS1-_TEXT_BASE (POS1 relative) */
-	sub	r5, r5, r0	/* r0 = CONFIG_SYS_TEXT_BASE-1 */
-	sub	r5, r5, #4	/* r1 = text base - current */
-
-	/* memory control configuration 1 */
-	ldr	r0, =SMRDATA
-	ldr	r2, =SMRDATA1
-	ldr	r1, _TEXT_BASE
-	sub	r0, r0, r1
-	sub	r2, r2, r1
-	add	r0, r0, r5
-	add	r2, r2, r5
-0:
-	/* the address */
-	ldr	r1, [r0], #4
-	/* the value */
-	ldr	r3, [r0], #4
-	str	r3, [r1]
-	cmp	r2, r0
-	bne	0b
-
-/* ----------------------------------------------------------------------------
- * PMC Init Step 1.
- * ----------------------------------------------------------------------------
- * - Check if the PLL is already initialized
- * ----------------------------------------------------------------------------
- */
-	ldr	r1, =(AT91_ASM_PMC_MCKR)
-	ldr	r0, [r1]
-	and	r0, r0, #3
-	cmp	r0, #0
-	bne	PLL_setup_end
-
-/* ---------------------------------------------------------------------------
- * - Enable the Main Oscillator
- * ---------------------------------------------------------------------------
- */
-	ldr	r1, =(AT91_ASM_PMC_MOR)
-	ldr	r2, =(AT91_ASM_PMC_SR)
-	/* Main oscillator Enable register PMC_MOR: */
-	ldr	r0, =CONFIG_SYS_MOR_VAL
-	str	r0, [r1]
-
-	/* Reading the PMC Status to detect when the Main Oscillator is enabled */
-	mov	r4, #AT91_PMC_IXR_MOSCS
-MOSCS_Loop:
-	ldr	r3, [r2]
-	and	r3, r4, r3
-	cmp	r3, #AT91_PMC_IXR_MOSCS
-	bne	MOSCS_Loop
-
-/* ----------------------------------------------------------------------------
- * PMC Init Step 2.
- * ----------------------------------------------------------------------------
- * Setup PLLA
- * ----------------------------------------------------------------------------
- */
-	ldr	r1, =(AT91_ASM_PMC_PLLAR)
-	ldr	r0, =CONFIG_SYS_PLLAR_VAL
-	str	r0, [r1]
-
-	/* Reading the PMC Status register to detect when the PLLA is locked */
-	mov	r4, #AT91_PMC_IXR_LOCKA
-MOSCS_Loop1:
-	ldr	r3, [r2]
-	and	r3, r4, r3
-	cmp	r3, #AT91_PMC_IXR_LOCKA
-	bne	MOSCS_Loop1
-
-/* ----------------------------------------------------------------------------
- * PMC Init Step 3.
- * ----------------------------------------------------------------------------
- * - Switch on the Main Oscillator
- * ----------------------------------------------------------------------------
- */
-	ldr	r1, =(AT91_ASM_PMC_MCKR)
-
-	/* -Master Clock Controller register PMC_MCKR */
-	ldr	r0, =CONFIG_SYS_MCKR1_VAL
-	str	r0, [r1]
-
-	/* Reading the PMC Status to detect when the Master clock is ready */
-	mov	r4, #AT91_PMC_IXR_MCKRDY
-MCKRDY_Loop:
-	ldr	r3, [r2]
-	and	r3, r4, r3
-	cmp	r3, #AT91_PMC_IXR_MCKRDY
-	bne	MCKRDY_Loop
-
-	ldr	r0, =CONFIG_SYS_MCKR2_VAL
-	str	r0, [r1]
-
-	/* Reading the PMC Status to detect when the Master clock is ready */
-	mov	r4, #AT91_PMC_IXR_MCKRDY
-MCKRDY_Loop1:
-	ldr	r3, [r2]
-	and	r3, r4, r3
-	cmp	r3, #AT91_PMC_IXR_MCKRDY
-	bne	MCKRDY_Loop1
-PLL_setup_end:
-
-/* ----------------------------------------------------------------------------
- * - memory control configuration 2
- * ----------------------------------------------------------------------------
- */
-	ldr	r0, =(AT91_ASM_SDRAMC_TR)
-	ldr	r1, [r0]
-	cmp	r1, #0
-	bne	SDRAM_setup_end
-
-	ldr	r0, =SMRDATA1
-	ldr	r2, =SMRDATA2
-	ldr	r1, _TEXT_BASE
-	sub	r0, r0, r1
-	sub	r2, r2, r1
-	add	r0, r0, r5
-	add	r2, r2, r5
-2:
-	/* the address */
-	ldr	r1, [r0], #4
-	/* the value */
-	ldr	r3, [r0], #4
-	str	r3, [r1]
-	cmp	r2, r0
-	bne	2b
-
-SDRAM_setup_end:
-	/* everything is fine now */
-	mov	pc, lr
-
-	.ltorg
-
-SMRDATA:
-	.word AT91_ASM_WDT_MR
-	.word CONFIG_SYS_WDTC_WDMR_VAL
-	/* configure PIOx as EBI0 D[16-31] */
-#if defined(CONFIG_AT91SAM9263)
-	.word AT91_ASM_PIOD_PDR
-	.word CONFIG_SYS_PIOD_PDR_VAL1
-	.word AT91_ASM_PIOD_PUDR
-	.word CONFIG_SYS_PIOD_PPUDR_VAL
-	.word AT91_ASM_PIOD_ASR
-	.word CONFIG_SYS_PIOD_PPUDR_VAL
-#elif defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9261) \
-	|| defined(CONFIG_AT91SAM9G20)
-	.word AT91_ASM_PIOC_PDR
-	.word CONFIG_SYS_PIOC_PDR_VAL1
-	.word AT91_ASM_PIOC_PUDR
-	.word CONFIG_SYS_PIOC_PPUDR_VAL
-#endif
-	.word AT91_ASM_MATRIX_CSA0
-	.word CONFIG_SYS_MATRIX_EBICSA_VAL
-
-	/* flash */
-	.word AT91_ASM_SMC_MODE0
-	.word CONFIG_SYS_SMC0_MODE0_VAL
-
-	.word AT91_ASM_SMC_CYCLE0
-	.word CONFIG_SYS_SMC0_CYCLE0_VAL
-
-	.word AT91_ASM_SMC_PULSE0
-	.word CONFIG_SYS_SMC0_PULSE0_VAL
-
-	.word AT91_ASM_SMC_SETUP0
-	.word CONFIG_SYS_SMC0_SETUP0_VAL
-
-SMRDATA1:
-	.word AT91_ASM_SDRAMC_MR
-	.word CONFIG_SYS_SDRC_MR_VAL1
-	.word AT91_ASM_SDRAMC_TR
-	.word CONFIG_SYS_SDRC_TR_VAL1
-	.word AT91_ASM_SDRAMC_CR
-	.word CONFIG_SYS_SDRC_CR_VAL
-	.word AT91_ASM_SDRAMC_MDR
-	.word CONFIG_SYS_SDRC_MDR_VAL
-	.word AT91_ASM_SDRAMC_MR
-	.word CONFIG_SYS_SDRC_MR_VAL2
-	.word AT91_SDRAM_BASE
-	.word CONFIG_SYS_SDRAM_VAL1
-	.word AT91_ASM_SDRAMC_MR
-	.word CONFIG_SYS_SDRC_MR_VAL3
-	.word AT91_SDRAM_BASE
-	.word CONFIG_SYS_SDRAM_VAL2
-	.word AT91_SDRAM_BASE
-	.word CONFIG_SYS_SDRAM_VAL3
-	.word AT91_SDRAM_BASE
-	.word CONFIG_SYS_SDRAM_VAL4
-	.word AT91_SDRAM_BASE
-	.word CONFIG_SYS_SDRAM_VAL5
-	.word AT91_SDRAM_BASE
-	.word CONFIG_SYS_SDRAM_VAL6
-	.word AT91_SDRAM_BASE
-	.word CONFIG_SYS_SDRAM_VAL7
-	.word AT91_SDRAM_BASE
-	.word CONFIG_SYS_SDRAM_VAL8
-	.word AT91_SDRAM_BASE
-	.word CONFIG_SYS_SDRAM_VAL9
-	.word AT91_ASM_SDRAMC_MR
-	.word CONFIG_SYS_SDRC_MR_VAL4
-	.word AT91_SDRAM_BASE
-	.word CONFIG_SYS_SDRAM_VAL10
-	.word AT91_ASM_SDRAMC_MR
-	.word CONFIG_SYS_SDRC_MR_VAL5
-	.word AT91_SDRAM_BASE
-	.word CONFIG_SYS_SDRAM_VAL11
-	.word AT91_ASM_SDRAMC_TR
-	.word CONFIG_SYS_SDRC_TR_VAL2
-	.word AT91_SDRAM_BASE
-	.word CONFIG_SYS_SDRAM_VAL12
-	/* User reset enable*/
-	.word AT91_ASM_RSTC_MR
-	.word CONFIG_SYS_RSTC_RMR_VAL
-#ifdef CONFIG_SYS_MATRIX_MCFG_REMAP
-	/* MATRIX_MCFG - REMAP all masters */
-	.word AT91_ASM_MATRIX_MCFG
-	.word 0x1FF
-#endif
-SMRDATA2:
-	.word 0
diff --git a/arch/arm/cpu/arm926ejs/at91/reset.c b/arch/arm/cpu/arm926ejs/at91/reset.c
deleted file mode 100644
index d2569d8..0000000
--- a/arch/arm/cpu/arm926ejs/at91/reset.c
+++ /dev/null
@@ -1,45 +0,0 @@
-/*
- * (C) Copyright 2007-2008
- * Stelian Pop <stelian.pop@leadtechdesign.com>
- * Lead Tech Design <www.leadtechdesign.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/at91_rstc.h>
-#include <asm/arch/io.h>
-
-/* Reset the cpu by telling the reset controller to do so */
-void reset_cpu(ulong ignored)
-{
-	at91_rstc_t *rstc = (at91_rstc_t *) AT91_RSTC_BASE;
-
-	writel(AT91_RSTC_KEY
-		| AT91_RSTC_CR_PROCRST	/* Processor Reset */
-		| AT91_RSTC_CR_PERRST	/* Peripheral Reset */
-#ifdef CONFIG_AT91RESET_EXTRST
-		| AT91_RSTC_CR_EXTRST	/* External Reset (assert nRST pin) */
-#endif
-		, &rstc->cr);
-	/* never reached */
-	while (1)
-		;
-}
diff --git a/arch/arm/cpu/arm926ejs/at91/timer.c b/arch/arm/cpu/arm926ejs/at91/timer.c
deleted file mode 100644
index 82b8d7e..0000000
--- a/arch/arm/cpu/arm926ejs/at91/timer.c
+++ /dev/null
@@ -1,141 +0,0 @@
-/*
- * (C) Copyright 2007-2008
- * Stelian Pop <stelian.pop@leadtechdesign.com>
- * Lead Tech Design <www.leadtechdesign.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/at91_pit.h>
-#include <asm/arch/at91_pmc.h>
-#include <asm/arch/clk.h>
-#include <asm/arch/io.h>
-#include <div64.h>
-
-#if !defined(CONFIG_AT91FAMILY)
-# error You need to define CONFIG_AT91FAMILY in your board config!
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*
- * We're using the AT91CAP9/SAM9 PITC in 32 bit mode, by
- * setting the 20 bit counter period to its maximum (0xfffff).
- * (See the relevant data sheets to understand that this really works)
- *
- * We do also mimic the typical powerpc way of incrementing
- * two 32 bit registers called tbl and tbu.
- *
- * Those registers increment at 1/16 the main clock rate.
- */
-
-#define TIMER_LOAD_VAL	0xfffff
-
-static inline unsigned long long tick_to_time(unsigned long long tick)
-{
-	tick *= CONFIG_SYS_HZ;
-	do_div(tick, gd->timer_rate_hz);
-
-	return tick;
-}
-
-static inline unsigned long long usec_to_tick(unsigned long long usec)
-{
-	usec *= gd->timer_rate_hz;
-	do_div(usec, 1000000);
-
-	return usec;
-}
-
-/*
- * Use the PITC in full 32 bit incrementing mode
- */
-int timer_init(void)
-{
-	at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
-	at91_pit_t *pit = (at91_pit_t *) AT91_PIT_BASE;
-
-	/* Enable PITC Clock */
-	writel(1 << AT91_ID_SYS, &pmc->pcer);
-
-	/* Enable PITC */
-	writel(TIMER_LOAD_VAL | AT91_PIT_MR_EN , &pit->mr);
-
-	gd->timer_rate_hz = gd->mck_rate_hz / 16;
-	gd->tbu = gd->tbl = 0;
-
-	return 0;
-}
-
-/*
- * Get the current 64 bit timer tick count
- */
-unsigned long long get_ticks(void)
-{
-	at91_pit_t *pit = (at91_pit_t *) AT91_PIT_BASE;
-
-	ulong now = readl(&pit->piir);
-
-	/* increment tbu if tbl has rolled over */
-	if (now < gd->tbl)
-		gd->tbu++;
-	gd->tbl = now;
-	return (((unsigned long long)gd->tbu) << 32) | gd->tbl;
-}
-
-void __udelay(unsigned long usec)
-{
-	unsigned long long tmp;
-	ulong tmo;
-
-	tmo = usec_to_tick(usec);
-	tmp = get_ticks() + tmo;	/* get current timestamp */
-
-	while (get_ticks() < tmp)	/* loop till event */
-		;
-}
-
-/*
- * reset_timer() and get_timer(base) are a pair of functions that are used by
- * some timeout/sleep mechanisms in u-boot.
- *
- * reset_timer() marks the current time as epoch and
- * get_timer(base) works relative to that epoch.
- *
- * The time is used in CONFIG_SYS_HZ units!
- */
-void reset_timer(void)
-{
-	gd->timer_reset_value = get_ticks();
-}
-
-ulong get_timer(ulong base)
-{
-	return tick_to_time(get_ticks() - gd->timer_reset_value) - base;
-}
-
-/*
- * Return the number of timer ticks per second.
- */
-ulong get_tbclk(void)
-{
-	return gd->timer_rate_hz;
-}
diff --git a/arch/arm/cpu/arm926ejs/config.mk b/arch/arm/cpu/arm926ejs/config.mk
deleted file mode 100644
index f8ef90f..0000000
--- a/arch/arm/cpu/arm926ejs/config.mk
+++ /dev/null
@@ -1,32 +0,0 @@
-#
-# (C) Copyright 2002
-# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float
-
-PLATFORM_CPPFLAGS += -march=armv5te
-# =========================================================================
-#
-# Supply options according to compiler version
-#
-# =========================================================================
-PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))
diff --git a/arch/arm/cpu/arm926ejs/cpu.c b/arch/arm/cpu/arm926ejs/cpu.c
deleted file mode 100644
index 5c902df..0000000
--- a/arch/arm/cpu/arm926ejs/cpu.c
+++ /dev/null
@@ -1,65 +0,0 @@
-/*
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * CPU specific code
- */
-
-#include <common.h>
-#include <command.h>
-#include <asm/system.h>
-
-static void cache_flush(void);
-
-int cleanup_before_linux (void)
-{
-	/*
-	 * this function is called just before we call linux
-	 * it prepares the processor for linux
-	 *
-	 * we turn off caches etc ...
-	 */
-
-	disable_interrupts ();
-
-
-	/* turn off I/D-cache */
-	icache_disable();
-	dcache_disable();
-	/* flush I/D-cache */
-	cache_flush();
-
-	return 0;
-}
-
-/* flush I/D-cache */
-static void cache_flush (void)
-{
-	unsigned long i = 0;
-
-	asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i));
-}
diff --git a/arch/arm/cpu/arm926ejs/davinci/Makefile b/arch/arm/cpu/arm926ejs/davinci/Makefile
deleted file mode 100644
index 3183e6a..0000000
--- a/arch/arm/cpu/arm926ejs/davinci/Makefile
+++ /dev/null
@@ -1,59 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(SOC).o
-
-COBJS-y				+= cpu.o timer.o psc.o
-COBJS-$(CONFIG_SOC_DM355)	+= dm355.o
-COBJS-$(CONFIG_SOC_DM365)	+= dm365.o
-COBJS-$(CONFIG_SOC_DM644X)	+= dm644x.o
-COBJS-$(CONFIG_SOC_DM646X)	+= dm646x.o
-COBJS-$(CONFIG_DRIVER_TI_EMAC)	+= lxt972.o dp83848.o et1011c.o
-
-SOBJS	= reset.o
-
-ifndef CONFIG_SKIP_LOWLEVEL_INIT
-SOBJS	+= lowlevel_init.o
-endif
-
-SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS-y) $(SOBJS))
-START	:= $(addprefix $(obj),$(START))
-
-all:	$(obj).depend $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/arch/arm/cpu/arm926ejs/davinci/config.mk b/arch/arm/cpu/arm926ejs/davinci/config.mk
deleted file mode 100644
index 565adda..0000000
--- a/arch/arm/cpu/arm926ejs/davinci/config.mk
+++ /dev/null
@@ -1,32 +0,0 @@
-#
-# (C) Copyright 2002
-# Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float
-
-PLATFORM_CPPFLAGS += -march=armv5te
-# =========================================================================
-#
-# Supply options according to compiler version
-#
-# =========================================================================
-PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))
diff --git a/arch/arm/cpu/arm926ejs/davinci/cpu.c b/arch/arm/cpu/arm926ejs/davinci/cpu.c
deleted file mode 100644
index 8b57205..0000000
--- a/arch/arm/cpu/arm926ejs/davinci/cpu.c
+++ /dev/null
@@ -1,201 +0,0 @@
-/*
- * Copyright (C) 2004 Texas Instruments.
- * Copyright (C) 2009 David Brownell
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#include <common.h>
-#include <netdev.h>
-#include <asm/arch/hardware.h>
-#include <asm/io.h>
-
-/* offsets from PLL controller base */
-#define PLLC_PLLCTL	0x100
-#define PLLC_PLLM	0x110
-#define PLLC_PREDIV	0x114
-#define PLLC_PLLDIV1	0x118
-#define PLLC_PLLDIV2	0x11c
-#define PLLC_PLLDIV3	0x120
-#define PLLC_POSTDIV	0x128
-#define PLLC_BPDIV	0x12c
-#define PLLC_PLLDIV4	0x160
-#define PLLC_PLLDIV5	0x164
-#define PLLC_PLLDIV6	0x168
-#define PLLC_PLLDIV8	0x170
-#define PLLC_PLLDIV9	0x174
-
-#define BIT(x)		(1 << (x))
-
-/* SOC-specific pll info */
-#ifdef CONFIG_SOC_DM355
-#define ARM_PLLDIV	PLLC_PLLDIV1
-#define DDR_PLLDIV	PLLC_PLLDIV1
-#endif
-
-#ifdef CONFIG_SOC_DM644X
-#define ARM_PLLDIV	PLLC_PLLDIV2
-#define DSP_PLLDIV	PLLC_PLLDIV1
-#define DDR_PLLDIV	PLLC_PLLDIV2
-#endif
-
-#ifdef CONFIG_SOC_DM646X
-#define DSP_PLLDIV	PLLC_PLLDIV1
-#define ARM_PLLDIV	PLLC_PLLDIV2
-#define DDR_PLLDIV	PLLC_PLLDIV1
-#endif
-
-#ifdef CONFIG_SOC_DA8XX
-const dv_reg * const sysdiv[7] = {
-	&davinci_pllc_regs->plldiv1, &davinci_pllc_regs->plldiv2,
-	&davinci_pllc_regs->plldiv3, &davinci_pllc_regs->plldiv4,
-	&davinci_pllc_regs->plldiv5, &davinci_pllc_regs->plldiv6,
-	&davinci_pllc_regs->plldiv7
-};
-
-int clk_get(enum davinci_clk_ids id)
-{
-	int pre_div;
-	int pllm;
-	int post_div;
-	int pll_out;
-
-	pll_out = CONFIG_SYS_OSCIN_FREQ;
-
-	if (id == DAVINCI_AUXCLK_CLKID)
-		goto out;
-
-	/*
-	 * Lets keep this simple. Combining operations can result in
-	 * unexpected approximations
-	 */
-	pre_div = (readl(&davinci_pllc_regs->prediv) &
-		   DAVINCI_PLLC_DIV_MASK) + 1;
-	pllm = readl(&davinci_pllc_regs->pllm) + 1;
-
-	pll_out /= pre_div;
-	pll_out *= pllm;
-
-	if (id == DAVINCI_PLLM_CLKID)
-		goto out;
-
-	post_div = (readl(&davinci_pllc_regs->postdiv) &
-		    DAVINCI_PLLC_DIV_MASK) + 1;
-
-	pll_out /= post_div;
-
-	if (id == DAVINCI_PLLC_CLKID)
-		goto out;
-
-	pll_out /= (readl(sysdiv[id - 1]) & DAVINCI_PLLC_DIV_MASK) + 1;
-
-out:
-	return pll_out;
-}
-#endif /* CONFIG_SOC_DA8XX */
-
-#ifdef CONFIG_DISPLAY_CPUINFO
-
-static unsigned pll_div(volatile void *pllbase, unsigned offset)
-{
-	u32	div;
-
-	div = REG(pllbase + offset);
-	return (div & BIT(15)) ? (1 + (div & 0x1f)) : 1;
-}
-
-static inline unsigned pll_prediv(volatile void *pllbase)
-{
-#ifdef CONFIG_SOC_DM355
-	/* this register read seems to fail on pll0 */
-	if (pllbase == (volatile void *)DAVINCI_PLL_CNTRL0_BASE)
-		return 8;
-	else
-		return pll_div(pllbase, PLLC_PREDIV);
-#endif
-	return 1;
-}
-
-static inline unsigned pll_postdiv(volatile void *pllbase)
-{
-#ifdef CONFIG_SOC_DM355
-	return pll_div(pllbase, PLLC_POSTDIV);
-#elif defined(CONFIG_SOC_DM6446)
-	if (pllbase == (volatile void *)DAVINCI_PLL_CNTRL0_BASE)
-		return pll_div(pllbase, PLLC_POSTDIV);
-#endif
-	return 1;
-}
-
-static unsigned pll_sysclk_mhz(unsigned pll_addr, unsigned div)
-{
-	volatile void	*pllbase = (volatile void *) pll_addr;
-#ifdef CONFIG_SOC_DM646X
-	unsigned	base = CFG_REFCLK_FREQ / 1000;
-#else
-	unsigned	base = CONFIG_SYS_HZ_CLOCK / 1000;
-#endif
-
-	/* the PLL might be bypassed */
-	if (REG(pllbase + PLLC_PLLCTL) & BIT(0)) {
-		base /= pll_prediv(pllbase);
-		base *= 1 + (REG(pllbase + PLLC_PLLM) & 0x0ff);
-		base /= pll_postdiv(pllbase);
-	}
-	return DIV_ROUND_UP(base, 1000 * pll_div(pllbase, div));
-}
-
-int print_cpuinfo(void)
-{
-	/* REVISIT fetch and display CPU ID and revision information
-	 * too ... that will matter as more revisions appear.
-	 */
-	printf("Cores: ARM %d MHz",
-			pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, ARM_PLLDIV));
-
-#ifdef DSP_PLLDIV
-	printf(", DSP %d MHz",
-			pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, DSP_PLLDIV));
-#endif
-
-	printf("\nDDR:   %d MHz\n",
-			/* DDR PHY uses an x2 input clock */
-			pll_sysclk_mhz(DAVINCI_PLL_CNTRL1_BASE, DDR_PLLDIV)
-				/ 2);
-	return 0;
-}
-
-#ifdef DAVINCI_DM6467EVM
-unsigned int davinci_arm_clk_get()
-{
-	return pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, ARM_PLLDIV) * 1000000;
-}
-#endif
-#endif
-
-/*
- * Initializes on-chip ethernet controllers.
- * to override, implement board_eth_init()
- */
-int cpu_eth_init(bd_t *bis)
-{
-#if defined(CONFIG_DRIVER_TI_EMAC)
-	davinci_emac_initialize();
-#endif
-	return 0;
-}
diff --git a/arch/arm/cpu/arm926ejs/davinci/dm355.c b/arch/arm/cpu/arm926ejs/davinci/dm355.c
deleted file mode 100644
index bc45b67..0000000
--- a/arch/arm/cpu/arm926ejs/davinci/dm355.c
+++ /dev/null
@@ -1,45 +0,0 @@
-/*
- * SoC-specific code for tms320dm355 and similar chips
- *
- * Copyright (C) 2009 David Brownell
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#include <common.h>
-#include <asm/arch/hardware.h>
-
-
-void davinci_enable_uart0(void)
-{
-	lpsc_on(DAVINCI_LPSC_UART0);
-
-	/* Bringup UART0 out of reset */
-	REG(UART0_PWREMU_MGMT) = 0x00006001;
-}
-
-
-#ifdef CONFIG_DRIVER_DAVINCI_I2C
-void davinci_enable_i2c(void)
-{
-	lpsc_on(DAVINCI_LPSC_I2C);
-
-	/* Enable I2C pin Mux */
-	REG(PINMUX3) |= (1 << 20) | (1 << 19);
-}
-#endif
diff --git a/arch/arm/cpu/arm926ejs/davinci/dm365.c b/arch/arm/cpu/arm926ejs/davinci/dm365.c
deleted file mode 100644
index 56c1bc0..0000000
--- a/arch/arm/cpu/arm926ejs/davinci/dm365.c
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- * SoC-specific code for tms320dm365 and similar chips
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#include <common.h>
-#include <asm/arch/hardware.h>
-
-void davinci_enable_uart0(void)
-{
-	lpsc_on(DAVINCI_LPSC_UART0);
-}
-
-#ifdef CONFIG_DRIVER_DAVINCI_I2C
-void davinci_enable_i2c(void)
-{
-	lpsc_on(DAVINCI_LPSC_I2C);
-}
-#endif
diff --git a/arch/arm/cpu/arm926ejs/davinci/dm644x.c b/arch/arm/cpu/arm926ejs/davinci/dm644x.c
deleted file mode 100644
index bb105b5..0000000
--- a/arch/arm/cpu/arm926ejs/davinci/dm644x.c
+++ /dev/null
@@ -1,96 +0,0 @@
-/*
- * SoC-specific code for tms320dm644x chips
- *
- * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
- * Copyright (C) 2008 Lyrtech <www.lyrtech.com>
- * Copyright (C) 2004 Texas Instruments.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#include <common.h>
-#include <asm/arch/hardware.h>
-
-
-#define PINMUX0_EMACEN (1 << 31)
-#define PINMUX0_AECS5  (1 << 11)
-#define PINMUX0_AECS4  (1 << 10)
-
-#define PINMUX1_I2C    (1 <<  7)
-#define PINMUX1_UART1  (1 <<  1)
-#define PINMUX1_UART0  (1 <<  0)
-
-
-void davinci_enable_uart0(void)
-{
-	lpsc_on(DAVINCI_LPSC_UART0);
-
-	/* Bringup UART0 out of reset */
-	REG(UART0_PWREMU_MGMT) = 0x00006001;
-
-	/* Enable UART0 MUX lines */
-	REG(PINMUX1) |= PINMUX1_UART0;
-}
-
-#ifdef CONFIG_DRIVER_TI_EMAC
-void davinci_enable_emac(void)
-{
-	lpsc_on(DAVINCI_LPSC_EMAC);
-	lpsc_on(DAVINCI_LPSC_EMAC_WRAPPER);
-	lpsc_on(DAVINCI_LPSC_MDIO);
-
-	/* Enable GIO3.3V cells used for EMAC */
-	REG(VDD3P3V_PWDN) = 0;
-
-	/* Enable EMAC. */
-	REG(PINMUX0) |= PINMUX0_EMACEN;
-}
-#endif
-
-#ifdef CONFIG_DRIVER_DAVINCI_I2C
-void davinci_enable_i2c(void)
-{
-	lpsc_on(DAVINCI_LPSC_I2C);
-
-	/* Enable I2C pin Mux */
-	REG(PINMUX1) |= PINMUX1_I2C;
-}
-#endif
-
-void davinci_errata_workarounds(void)
-{
-	/*
-	 * Workaround for TMS320DM6446 errata 1.3.22:
-	 *   PSC: PTSTAT Register Does Not Clear After Warm/Maximum Reset
-	 *   Revision(s) Affected: 1.3 and earlier
-	 */
-	REG(PSC_SILVER_BULLET) = 0;
-
-	/*
-	 * Set the PR_OLD_COUNT bits in the Bus Burst Priority Register (PBBPR)
-	 * as suggested in TMS320DM6446 errata 2.1.2:
-	 *
-	 * On DM6446 Silicon Revision 2.1 and earlier, under certain conditions
-	 * low priority modules can occupy the bus and prevent high priority
-	 * modules like the VPSS from getting the required DDR2 throughput.
-	 * A hex value of 0x20 should provide a good ARM (cache enabled)
-	 * performance and still allow good utilization by the VPSS or other
-	 * modules.
-	 */
-	REG(VBPR) = 0x20;
-}
diff --git a/arch/arm/cpu/arm926ejs/davinci/dm646x.c b/arch/arm/cpu/arm926ejs/davinci/dm646x.c
deleted file mode 100644
index 329825f..0000000
--- a/arch/arm/cpu/arm926ejs/davinci/dm646x.c
+++ /dev/null
@@ -1,41 +0,0 @@
-/*
- * SoC-specific code for TMS320DM646x chips
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#include <asm/arch/hardware.h>
-
-void davinci_enable_uart0(void)
-{
-	lpsc_on(DAVINCI_DM646X_LPSC_UART0);
-}
-
-#ifdef CONFIG_DRIVER_TI_EMAC
-void davinci_enable_emac(void)
-{
-	lpsc_on(DAVINCI_DM646X_LPSC_EMAC);
-}
-#endif
-
-#ifdef CONFIG_DRIVER_DAVINCI_I2C
-void davinci_enable_i2c(void)
-{
-	lpsc_on(DAVINCI_DM646X_LPSC_I2C);
-}
-#endif
diff --git a/arch/arm/cpu/arm926ejs/davinci/dp83848.c b/arch/arm/cpu/arm926ejs/davinci/dp83848.c
deleted file mode 100644
index c71c685..0000000
--- a/arch/arm/cpu/arm926ejs/davinci/dp83848.c
+++ /dev/null
@@ -1,143 +0,0 @@
-/*
- * National Semiconductor DP83848 PHY Driver for TI DaVinci
- * (TMS320DM644x) based boards.
- *
- * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
- *
- * --------------------------------------------------------
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <net.h>
-#include <dp83848.h>
-#include <asm/arch/emac_defs.h>
-
-#ifdef CONFIG_DRIVER_TI_EMAC
-
-#ifdef CONFIG_CMD_NET
-
-int dp83848_is_phy_connected(int phy_addr)
-{
-	u_int16_t	id1, id2;
-
-	if (!davinci_eth_phy_read(phy_addr, DP83848_PHYID1_REG, &id1))
-		return(0);
-	if (!davinci_eth_phy_read(phy_addr, DP83848_PHYID2_REG, &id2))
-		return(0);
-
-	if ((id1 == DP83848_PHYID1_OUI) && (id2 == DP83848_PHYID2_OUI))
-		return(1);
-
-	return(0);
-}
-
-int dp83848_get_link_speed(int phy_addr)
-{
-	u_int16_t		tmp;
-	volatile emac_regs*	emac = (emac_regs *)EMAC_BASE_ADDR;
-
-	if (!davinci_eth_phy_read(phy_addr, DP83848_STAT_REG, &tmp))
-		return(0);
-
-	if (!(tmp & DP83848_LINK_STATUS))	/* link up? */
-		return(0);
-
-	if (!davinci_eth_phy_read(phy_addr, DP83848_PHY_STAT_REG, &tmp))
-		return(0);
-
-	/* Speed doesn't matter, there is no setting for it in EMAC... */
-	if (tmp & DP83848_DUPLEX) {
-		/* set DM644x EMAC for Full Duplex  */
-		emac->MACCONTROL = EMAC_MACCONTROL_MIIEN_ENABLE |
-			EMAC_MACCONTROL_FULLDUPLEX_ENABLE;
-	} else {
-		/*set DM644x EMAC for Half Duplex  */
-		emac->MACCONTROL = EMAC_MACCONTROL_MIIEN_ENABLE;
-	}
-
-	return(1);
-}
-
-
-int dp83848_init_phy(int phy_addr)
-{
-	int	ret = 1;
-
-	if (!dp83848_get_link_speed(phy_addr)) {
-		/* Try another time */
-		udelay(100000);
-		ret = dp83848_get_link_speed(phy_addr);
-	}
-
-	/* Disable PHY Interrupts */
-	davinci_eth_phy_write(phy_addr, DP83848_PHY_INTR_CTRL_REG, 0);
-
-	return(ret);
-}
-
-
-int dp83848_auto_negotiate(int phy_addr)
-{
-	u_int16_t	tmp;
-
-
-	if (!davinci_eth_phy_read(phy_addr, DP83848_CTL_REG, &tmp))
-		return(0);
-
-	/* Restart Auto_negotiation  */
-	tmp &= ~DP83848_AUTONEG;	/* remove autonegotiation enable */
-	tmp |= DP83848_ISOLATE;		/* Electrically isolate PHY */
-	davinci_eth_phy_write(phy_addr, DP83848_CTL_REG, tmp);
-
-	/* Set the Auto_negotiation Advertisement Register
-	 * MII advertising for Next page, 100BaseTxFD and HD,
-	 * 10BaseTFD and HD, IEEE 802.3
-	 */
-	tmp = DP83848_NP | DP83848_TX_FDX | DP83848_TX_HDX |
-		DP83848_10_FDX | DP83848_10_HDX | DP83848_AN_IEEE_802_3;
-	davinci_eth_phy_write(phy_addr, DP83848_ANA_REG, tmp);
-
-
-	/* Read Control Register */
-	if (!davinci_eth_phy_read(phy_addr, DP83848_CTL_REG, &tmp))
-		return(0);
-
-	tmp |= DP83848_SPEED_SELECT | DP83848_AUTONEG | DP83848_DUPLEX_MODE;
-	davinci_eth_phy_write(phy_addr, DP83848_CTL_REG, tmp);
-
-	/* Restart Auto_negotiation  */
-	tmp |= DP83848_RESTART_AUTONEG;
-	davinci_eth_phy_write(phy_addr, DP83848_CTL_REG, tmp);
-
-	/*check AutoNegotiate complete */
-	udelay(10000);
-	if (!davinci_eth_phy_read(phy_addr, DP83848_STAT_REG, &tmp))
-		return(0);
-
-	if (!(tmp & DP83848_AUTONEG_COMP))
-		return(0);
-
-	return (dp83848_get_link_speed(phy_addr));
-}
-
-#endif	/* CONFIG_CMD_NET */
-
-#endif	/* CONFIG_DRIVER_ETHER */
diff --git a/arch/arm/cpu/arm926ejs/davinci/et1011c.c b/arch/arm/cpu/arm926ejs/davinci/et1011c.c
deleted file mode 100644
index da07345..0000000
--- a/arch/arm/cpu/arm926ejs/davinci/et1011c.c
+++ /dev/null
@@ -1,55 +0,0 @@
-/*
- * LSI ET1011C PHY Driver for TI DaVinci(TMS320DM6467) board.
- *
- * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#include <common.h>
-#include <net.h>
-#include <miiphy.h>
-#include <asm/arch/emac_defs.h>
-
-#ifdef CONFIG_DRIVER_TI_EMAC
-
-#ifdef CONFIG_CMD_NET
-
-/* LSI PHYSICAL LAYER TRANSCEIVER ET1011C */
-
-#define MII_PHY_CONFIG_REG		22
-
-/* PHY Config bits */
-#define PHY_SYS_CLK_EN			(1 << 4)
-
-int et1011c_get_link_speed(int phy_addr)
-{
-	u_int16_t	data;
-
-	if (davinci_eth_phy_read(phy_addr, MII_STATUS_REG, &data) && (data & 0x04)) {
-		davinci_eth_phy_read(EMAC_MDIO_PHY_NUM,
-				MII_PHY_CONFIG_REG, &data);
-		/* Enable 125MHz clock sourced from PHY */
-		davinci_eth_phy_write(EMAC_MDIO_PHY_NUM,
-			MII_PHY_CONFIG_REG,
-			data | PHY_SYS_CLK_EN);
-		return (1);
-	}
-	return (0);
-}
-
-#endif	/* CONFIG_CMD_NET */
-
-#endif	/* CONFIG_DRIVER_ETHER */
diff --git a/arch/arm/cpu/arm926ejs/davinci/lowlevel_init.S b/arch/arm/cpu/arm926ejs/davinci/lowlevel_init.S
deleted file mode 100644
index 0a4b2cf..0000000
--- a/arch/arm/cpu/arm926ejs/davinci/lowlevel_init.S
+++ /dev/null
@@ -1,707 +0,0 @@
-/*
- * Low-level board setup code for TI DaVinci SoC based boards.
- *
- * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
- *
- * Partially based on TI sources, original copyrights follow:
- */
-
-/*
- * Board specific setup info
- *
- * (C) Copyright 2003
- * Texas Instruments, <www.ti.com>
- * Kshitij Gupta <Kshitij@ti.com>
- *
- * Modified for OMAP 1610 H2 board by Nishant Kamat, Jan 2004
- *
- * Modified for OMAP 5912 OSK board by Rishi Bhattacharya, Apr 2004
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * Modified for DV-EVM board by Rishi Bhattacharya, Apr 2005
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * Modified for DV-EVM board by Swaminathan S, Nov 2005
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-
-.globl	lowlevel_init
-lowlevel_init:
-
-	/*-------------------------------------------------------*
-	 * Mask all IRQs by setting all bits in the EINT default *
-	 *-------------------------------------------------------*/
-	mov	r1, $0
-	ldr	r0, =EINT_ENABLE0
-	str	r1, [r0]
-	ldr	r0, =EINT_ENABLE1
-	str	r1, [r0]
-
-	/*------------------------------------------------------*
-	 * Put the GEM in reset					*
-	 *------------------------------------------------------*/
-
-	/* Put the GEM in reset */
-	ldr	r8, PSC_GEM_FLAG_CLEAR
-	ldr	r6, MDCTL_GEM
-	ldr	r7, [r6]
-	and	r7, r7, r8
-	str	r7, [r6]
-
-	/* Enable the Power Domain Transition Command */
-	ldr	r6, PTCMD
-	ldr	r7, [r6]
-	orr	r7, r7, $0x02
-	str	r7, [r6]
-
-	/* Check for Transition Complete(PTSTAT) */
-checkStatClkStopGem:
-	ldr	r6, PTSTAT
-	ldr	r7, [r6]
-	ands	r7, r7, $0x02
-	bne	checkStatClkStopGem
-
-	/* Check for GEM Reset Completion */
-checkGemStatClkStop:
-	ldr	r6, MDSTAT_GEM
-	ldr	r7, [r6]
-	ands	r7, r7, $0x100
-	bne	checkGemStatClkStop
-
-	/* Do this for enabling a WDT initiated reset this is a workaround
-	   for a chip bug.  Not required under normal situations */
-	ldr	r6, P1394
-	mov	r10, $0
-	str	r10, [r6]
-
-	/*------------------------------------------------------*
-	 * Enable L1 & L2 Memories in Fast mode                 *
-	 *------------------------------------------------------*/
-	ldr	r6, DFT_ENABLE
-	mov	r10, $0x01
-	str	r10, [r6]
-
-	ldr	r6, MMARG_BRF0
-	ldr	r10, MMARG_BRF0_VAL
-	str	r10, [r6]
-
-	ldr	r6, DFT_ENABLE
-	mov	r10, $0
-	str	r10, [r6]
-
-	/*------------------------------------------------------*
-	 * DDR2 PLL Initialization				*
-	 *------------------------------------------------------*/
-
-	/* Select the Clock Mode Depending on the Value written in the Boot Table by the run script */
-	mov	r10, $0
-	ldr	r6, PLL2_CTL
-	ldr	r7, PLL_CLKSRC_MASK
-	ldr	r8, [r6]
-	and	r8, r8, r7
-	mov	r9, r10, lsl $8
-	orr	r8, r8, r9
-	str	r8, [r6]
-
-	/* Select the PLLEN source */
-	ldr	r7, PLL_ENSRC_MASK
-	and	r8, r8, r7
-	str	r8, [r6]
-
-	/* Bypass the PLL */
-	ldr	r7, PLL_BYPASS_MASK
-	and	r8, r8, r7
-	str	r8, [r6]
-
-	/* Wait for few cycles to allow PLLEN Mux switch properly to bypass Clock */
-	mov	r10, $0x20
-WaitPPL2Loop:
-	subs	r10, r10, $1
-	bne	WaitPPL2Loop
-
-	/* Reset the PLL */
-	ldr	r7, PLL_RESET_MASK
-	and	r8, r8, r7
-	str	r8, [r6]
-
-	/* Power up the PLL */
-	ldr	r7, PLL_PWRUP_MASK
-	and	r8, r8, r7
-	str	r8, [r6]
-
-	/* Enable the PLL from Disable Mode */
-	ldr	r7, PLL_DISABLE_ENABLE_MASK
-	and	r8, r8, r7
-	str	r8, [r6]
-
-	/* Program the PLL Multiplier */
-	ldr	r6, PLL2_PLLM
-	mov	r2, $0x17	/* 162 MHz */
-	str	r2, [r6]
-
-	/* Program the PLL2 Divisor Value */
-	ldr	r6, PLL2_DIV2
-	mov	r3, $0x01
-	str	r3, [r6]
-
-	/* Program the PLL2 Divisor Value */
-	ldr	r6, PLL2_DIV1
-	mov	r4, $0x0b	/* 54 MHz */
-	str	r4, [r6]
-
-	/* PLL2 DIV2 MMR */
-	ldr	r8, PLL2_DIV_MASK
-	ldr	r6, PLL2_DIV2
-	ldr	r9, [r6]
-	and	r8, r8, r9
-	mov	r9, $0x01
-	mov	r9, r9, lsl $15
-	orr	r8, r8, r9
-	str	r8, [r6]
-
-	/* Program the GOSET bit to take new divider values */
-	ldr	r6, PLL2_PLLCMD
-	ldr	r7, [r6]
-	orr	r7, r7, $0x01
-	str	r7, [r6]
-
-	/* Wait for Done */
-	ldr	r6, PLL2_PLLSTAT
-doneLoop_0:
-	ldr	r7, [r6]
-	ands	r7, r7, $0x01
-	bne	doneLoop_0
-
-	/* PLL2 DIV1 MMR */
-	ldr	r8, PLL2_DIV_MASK
-	ldr	r6, PLL2_DIV1
-	ldr	r9, [r6]
-	and	r8, r8, r9
-	mov	r9, $0x01
-	mov	r9, r9, lsl $15
-	orr	r8, r8, r9
-	str	r8, [r6]
-
-	/* Program the GOSET bit to take new divider values */
-	ldr	r6, PLL2_PLLCMD
-	ldr	r7, [r6]
-	orr	r7, r7, $0x01
-	str	r7, [r6]
-
-	/* Wait for Done */
-	ldr	r6, PLL2_PLLSTAT
-doneLoop:
-	ldr	r7, [r6]
-	ands	r7, r7, $0x01
-	bne	doneLoop
-
-	/* Wait for PLL to Reset Properly */
-	mov	r10, $0x218
-ResetPPL2Loop:
-	subs	r10, r10, $1
-	bne	ResetPPL2Loop
-
-	/* Bring PLL out of Reset */
-	ldr	r6, PLL2_CTL
-	ldr	r8, [r6]
-	orr	r8, r8, $0x08
-	str	r8, [r6]
-
-	/* Wait for PLL to Lock */
-	ldr	r10, PLL_LOCK_COUNT
-PLL2Lock:
-	subs	r10, r10, $1
-	bne	PLL2Lock
-
-	/* Enable the PLL */
-	ldr	r6, PLL2_CTL
-	ldr	r8, [r6]
-	orr	r8, r8, $0x01
-	str	r8, [r6]
-
-	/*------------------------------------------------------*
-	 * Issue Soft Reset to DDR Module			*
-	 *------------------------------------------------------*/
-
-	/* Shut down the DDR2 LPSC Module */
-	ldr	r8, PSC_FLAG_CLEAR
-	ldr	r6, MDCTL_DDR2
-	ldr	r7, [r6]
-	and	r7, r7, r8
-	orr	r7, r7, $0x03
-	str	r7, [r6]
-
-	/* Enable the Power Domain Transition Command */
-	ldr	r6, PTCMD
-	ldr	r7, [r6]
-	orr	r7, r7, $0x01
-	str	r7, [r6]
-
-	/* Check for Transition Complete(PTSTAT) */
-checkStatClkStop:
-	ldr	r6, PTSTAT
-	ldr	r7, [r6]
-	ands	r7, r7, $0x01
-	bne	checkStatClkStop
-
-	/* Check for DDR2 Controller Enable Completion */
-checkDDRStatClkStop:
-	ldr	r6, MDSTAT_DDR2
-	ldr	r7, [r6]
-	and	r7, r7, $0x1f
-	cmp	r7, $0x03
-	bne	checkDDRStatClkStop
-
-	/*------------------------------------------------------*
-	 * Program DDR2 MMRs for 162MHz Setting			*
-	 *------------------------------------------------------*/
-
-	/* Program PHY Control Register */
-	ldr	r6, DDRCTL
-	ldr	r7, DDRCTL_VAL
-	str	r7, [r6]
-
-	/* Program SDRAM Bank Config Register */
-	ldr	r6, SDCFG
-	ldr	r7, SDCFG_VAL
-	str	r7, [r6]
-
-	/* Program SDRAM TIM-0 Config Register */
-	ldr	r6, SDTIM0
-	ldr	r7, SDTIM0_VAL_162MHz
-	str	r7, [r6]
-
-	/* Program SDRAM TIM-1 Config Register */
-	ldr	r6, SDTIM1
-	ldr	r7, SDTIM1_VAL_162MHz
-	str	r7, [r6]
-
-	/* Program the SDRAM Bank Config Control Register */
-	ldr	r10, MASK_VAL
-	ldr	r8, SDCFG
-	ldr	r9, SDCFG_VAL
-	and	r9, r9, r10
-	str	r9, [r8]
-
-	/* Program SDRAM SDREF Config Register */
-	ldr	r6, SDREF
-	ldr	r7, SDREF_VAL
-	str	r7, [r6]
-
-	/*------------------------------------------------------*
-	 * Issue Soft Reset to DDR Module			*
-	 *------------------------------------------------------*/
-
-	/* Issue a Dummy DDR2 read/write */
-	ldr	r8, DDR2_START_ADDR
-	ldr	r7, DUMMY_VAL
-	str	r7, [r8]
-	ldr	r7, [r8]
-
-	/* Shut down the DDR2 LPSC Module */
-	ldr	r8, PSC_FLAG_CLEAR
-	ldr	r6, MDCTL_DDR2
-	ldr	r7, [r6]
-	and	r7, r7, r8
-	orr	r7, r7, $0x01
-	str	r7, [r6]
-
-	/* Enable the Power Domain Transition Command */
-	ldr	r6, PTCMD
-	ldr	r7, [r6]
-	orr	r7, r7, $0x01
-	str	r7, [r6]
-
-	/* Check for Transition Complete(PTSTAT) */
-checkStatClkStop2:
-	ldr	r6, PTSTAT
-	ldr	r7, [r6]
-	ands	r7, r7, $0x01
-	bne	checkStatClkStop2
-
-	/* Check for DDR2 Controller Enable Completion */
-checkDDRStatClkStop2:
-	ldr	r6, MDSTAT_DDR2
-	ldr	r7, [r6]
-	and	r7, r7, $0x1f
-	cmp	r7, $0x01
-	bne	checkDDRStatClkStop2
-
-	/*------------------------------------------------------*
-	 * Turn DDR2 Controller Clocks On			*
-	 *------------------------------------------------------*/
-
-	/* Enable the DDR2 LPSC Module */
-	ldr	r6, MDCTL_DDR2
-	ldr	r7, [r6]
-	orr	r7, r7, $0x03
-	str	r7, [r6]
-
-	/* Enable the Power Domain Transition Command */
-	ldr	r6, PTCMD
-	ldr	r7, [r6]
-	orr	r7, r7, $0x01
-	str	r7, [r6]
-
-	/* Check for Transition Complete(PTSTAT) */
-checkStatClkEn2:
-	ldr	r6, PTSTAT
-	ldr	r7, [r6]
-	ands	r7, r7, $0x01
-	bne	checkStatClkEn2
-
-	/* Check for DDR2 Controller Enable Completion */
-checkDDRStatClkEn2:
-	ldr	r6, MDSTAT_DDR2
-	ldr	r7, [r6]
-	and	r7, r7, $0x1f
-	cmp	r7, $0x03
-	bne	checkDDRStatClkEn2
-
-	/*  DDR Writes and Reads */
-	ldr	r6, CFGTEST
-	mov	r3, $0x01
-	str	r3, [r6]
-
-	/*------------------------------------------------------*
-	 * System PLL Initialization				*
-	 *------------------------------------------------------*/
-
-	/* Select the Clock Mode Depending on the Value written in the Boot Table by the run script */
-	mov	r2, $0
-	ldr	r6, PLL1_CTL
-	ldr	r7, PLL_CLKSRC_MASK
-	ldr	r8, [r6]
-	and	r8, r8, r7
-	mov	r9, r2, lsl $8
-	orr	r8, r8, r9
-	str	r8, [r6]
-
-	/* Select the PLLEN source */
-	ldr	r7, PLL_ENSRC_MASK
-	and	r8, r8, r7
-	str	r8, [r6]
-
-	/* Bypass the PLL */
-	ldr	r7, PLL_BYPASS_MASK
-	and	r8, r8, r7
-	str	r8, [r6]
-
-	/* Wait for few cycles to allow PLLEN Mux switch properly to bypass Clock */
-	mov	r10, $0x20
-
-WaitLoop:
-	subs	r10, r10, $1
-	bne	WaitLoop
-
-	/* Reset the PLL */
-	ldr	r7, PLL_RESET_MASK
-	and	r8, r8, r7
-	str	r8, [r6]
-
-	/* Disable the PLL */
-	orr	r8, r8, $0x10
-	str	r8, [r6]
-
-	/* Power up the PLL */
-	ldr	r7, PLL_PWRUP_MASK
-	and	r8, r8, r7
-	str	r8, [r6]
-
-	/* Enable the PLL from Disable Mode */
-	ldr	r7, PLL_DISABLE_ENABLE_MASK
-	and	r8, r8, r7
-	str	r8, [r6]
-
-	/* Program the PLL Multiplier */
-	ldr	r6, PLL1_PLLM
-	mov	r3, $0x15	/* For 594MHz */
-	str	r3, [r6]
-
-	/* Wait for PLL to Reset Properly */
-	mov	r10, $0xff
-
-ResetLoop:
-	subs	r10, r10, $1
-	bne	ResetLoop
-
-	/* Bring PLL out of Reset */
-	ldr	r6, PLL1_CTL
-	orr	r8, r8, $0x08
-	str	r8, [r6]
-
-	/* Wait for PLL to Lock */
-	ldr	r10, PLL_LOCK_COUNT
-
-PLL1Lock:
-	subs	r10, r10, $1
-	bne	PLL1Lock
-
-	/* Enable the PLL */
-	orr	r8, r8, $0x01
-	str	r8, [r6]
-
-	nop
-	nop
-	nop
-	nop
-
-	/*------------------------------------------------------*
-	 * AEMIF configuration for NOR Flash (double check)     *
-	 *------------------------------------------------------*/
-	ldr	r0, _PINMUX0
-	ldr	r1, _DEV_SETTING
-	str	r1, [r0]
-
-	ldr	r0, WAITCFG
-	ldr	r1, WAITCFG_VAL
-	ldr	r2, [r0]
-	orr	r2, r2, r1
-	str	r2, [r0]
-
-	ldr	r0, ACFG3
-	ldr	r1, ACFG3_VAL
-	ldr	r2, [r0]
-	and	r1, r2, r1
-	str	r1, [r0]
-
-	ldr	r0, ACFG4
-	ldr	r1, ACFG4_VAL
-	ldr	r2, [r0]
-	and	r1, r2, r1
-	str	r1, [r0]
-
-	ldr	r0, ACFG5
-	ldr	r1, ACFG5_VAL
-	ldr	r2, [r0]
-	and	r1, r2, r1
-	str	r1, [r0]
-
-	/*--------------------------------------*
-	 * VTP manual Calibration               *
-	 *--------------------------------------*/
-	ldr	r0, VTPIOCR
-	ldr	r1, VTP_MMR0
-	str	r1, [r0]
-
-	ldr	r0, VTPIOCR
-	ldr	r1, VTP_MMR1
-	str	r1, [r0]
-
-	/* Wait for 33 VTP CLK cycles.  VRP operates at 27 MHz */
-	ldr	r10, VTP_LOCK_COUNT
-VTPLock:
-	subs	r10, r10, $1
-	bne	VTPLock
-
-	ldr	r6, DFT_ENABLE
-	mov	r10, $0x01
-	str	r10, [r6]
-
-	ldr	r6, DDRVTPR
-	ldr	r7, [r6]
-	and	r7, r7, $0x1f
-	and	r8, r7, $0x3e0
-	orr	r8, r7, r8
-	ldr	r7, VTP_RECAL
-	orr	r8, r7, r8
-	ldr	r7, VTP_EN
-	orr	r8, r7, r8
-	str	r8, [r0]
-
-
-	/* Wait for 33 VTP CLK cycles.  VRP operates at 27 MHz */
-	ldr	r10, VTP_LOCK_COUNT
-VTP1Lock:
-	subs	r10, r10, $1
-	bne	VTP1Lock
-
-	ldr	r1, [r0]
-	ldr	r2, VTP_MASK
-	and	r2, r1, r2
-	str	r2, [r0]
-
-	ldr	r6, DFT_ENABLE
-	mov	r10, $0
-	str	r10, [r6]
-
-	/*
-	 * Call board-specific lowlevel init.
-	 * That MUST be present and THAT returns
-	 * back to arch calling code with "mov pc, lr."
-	 */
-	b	dv_board_init
-
-.ltorg
-
-_PINMUX0:
-	.word	0x01c40000		/* Device Configuration Registers */
-_PINMUX1:
-	.word	0x01c40004		/* Device Configuration Registers */
-
-_DEV_SETTING:
-	.word	0x00000c1f
-
-WAITCFG:
-	.word	0x01e00004
-WAITCFG_VAL:
-	.word	0
-ACFG3:
-	.word	0x01e00014
-ACFG3_VAL:
-	.word	0x3ffffffd
-ACFG4:
-	.word	0x01e00018
-ACFG4_VAL:
-	.word	0x3ffffffd
-ACFG5:
-	.word	0x01e0001c
-ACFG5_VAL:
-	.word	0x3ffffffd
-
-MDCTL_DDR2:
-	.word	0x01c41a34
-MDSTAT_DDR2:
-	.word	0x01c41834
-
-PTCMD:
-	.word	0x01c41120
-PTSTAT:
-	.word	0x01c41128
-
-EINT_ENABLE0:
-	.word	0x01c48018
-EINT_ENABLE1:
-	.word	0x01c4801c
-
-PSC_FLAG_CLEAR:
-	.word	0xffffffe0
-PSC_GEM_FLAG_CLEAR:
-	.word	0xfffffeff
-
-/* DDR2 MMR & CONFIGURATION VALUES, 162 MHZ clock */
-DDRCTL:
-	.word	0x200000e4
-DDRCTL_VAL:
-	.word	0x50006405
-SDREF:
-	.word	0x2000000c
-SDREF_VAL:
-	.word	0x000005c3
-SDCFG:
-	.word	0x20000008
-SDCFG_VAL:
-#ifdef	DDR_4BANKS
-	.word	0x00178622
-#elif defined DDR_8BANKS
-	.word	0x00178632
-#else
-#error "Unknown DDR configuration!!!"
-#endif
-SDTIM0:
-	.word	0x20000010
-SDTIM0_VAL_162MHz:
-	.word	0x28923211
-SDTIM1:
-	.word	0x20000014
-SDTIM1_VAL_162MHz:
-	.word	0x0016c722
-VTPIOCR:
-	.word	0x200000f0	/* VTP IO Control register */
-DDRVTPR:
-	.word	0x01c42030	/* DDR VPTR MMR */
-VTP_MMR0:
-	.word	0x201f
-VTP_MMR1:
-	.word	0xa01f
-DFT_ENABLE:
-	.word	0x01c4004c
-VTP_LOCK_COUNT:
-	.word	0x5b0
-VTP_MASK:
-	.word	0xffffdfff
-VTP_RECAL:
-	.word	0x40000
-VTP_EN:
-	.word	0x02000
-CFGTEST:
-	.word	0x80010000
-MASK_VAL:
-	.word	0x00000fff
-
-/* GEM Power Up & LPSC Control Register */
-MDCTL_GEM:
-	.word	0x01c41a9c
-MDSTAT_GEM:
-	.word	0x01c4189c
-
-/* For WDT reset chip bug */
-P1394:
-	.word	0x01c41a20
-
-PLL_CLKSRC_MASK:
-	.word	0xfffffeff	/* Mask the Clock Mode bit */
-PLL_ENSRC_MASK:
-	.word	0xffffffdf	/* Select the PLLEN source */
-PLL_BYPASS_MASK:
-	.word	0xfffffffe	/* Put the PLL in BYPASS */
-PLL_RESET_MASK:
-	.word	0xfffffff7	/* Put the PLL in Reset Mode */
-PLL_PWRUP_MASK:
-	.word	0xfffffffd	/* PLL Power up Mask Bit  */
-PLL_DISABLE_ENABLE_MASK:
-	.word	0xffffffef	/* Enable the PLL from Disable */
-PLL_LOCK_COUNT:
-	.word	0x2000
-
-/* PLL1-SYSTEM PLL MMRs */
-PLL1_CTL:
-	.word	0x01c40900
-PLL1_PLLM:
-	.word	0x01c40910
-
-/* PLL2-SYSTEM PLL MMRs */
-PLL2_CTL:
-	.word	0x01c40d00
-PLL2_PLLM:
-	.word	0x01c40d10
-PLL2_DIV1:
-	.word	0x01c40d18
-PLL2_DIV2:
-	.word	0x01c40d1c
-PLL2_PLLCMD:
-	.word	0x01c40d38
-PLL2_PLLSTAT:
-	.word	0x01c40d3c
-PLL2_DIV_MASK:
-	.word	0xffff7fff
-
-MMARG_BRF0:
-	.word	0x01c42010	/* BRF margin mode 0 (R/W)*/
-MMARG_BRF0_VAL:
-	.word	0x00444400
-
-DDR2_START_ADDR:
-	.word	0x80000000
-DUMMY_VAL:
-	.word	0xa55aa55a
diff --git a/arch/arm/cpu/arm926ejs/davinci/lxt972.c b/arch/arm/cpu/arm926ejs/davinci/lxt972.c
deleted file mode 100644
index 733d413..0000000
--- a/arch/arm/cpu/arm926ejs/davinci/lxt972.c
+++ /dev/null
@@ -1,128 +0,0 @@
-/*
- * Intel LXT971/LXT972 PHY Driver for TI DaVinci
- * (TMS320DM644x) based boards.
- *
- * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
- *
- * --------------------------------------------------------
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <net.h>
-#include <miiphy.h>
-#include <lxt971a.h>
-#include <asm/arch/emac_defs.h>
-
-#ifdef CONFIG_DRIVER_TI_EMAC
-
-#ifdef CONFIG_CMD_NET
-
-int lxt972_is_phy_connected(int phy_addr)
-{
-	u_int16_t id1, id2;
-
-	if (!davinci_eth_phy_read(phy_addr, MII_PHYSID1, &id1))
-		return(0);
-	if (!davinci_eth_phy_read(phy_addr, MII_PHYSID2, &id2))
-		return(0);
-
-	if ((id1 == (0x0013)) && ((id2  & 0xfff0) == 0x78e0))
-		return(1);
-
-	return(0);
-}
-
-int lxt972_get_link_speed(int phy_addr)
-{
-	u_int16_t stat1, tmp;
-	volatile emac_regs *emac = (emac_regs *)EMAC_BASE_ADDR;
-
-	if (!davinci_eth_phy_read(phy_addr, PHY_LXT971_STAT2, &stat1))
-		return(0);
-
-	if (!(stat1 & PHY_LXT971_STAT2_LINK))	/* link up? */
-		return(0);
-
-	if (!davinci_eth_phy_read(phy_addr, PHY_LXT971_DIG_CFG, &tmp))
-		return(0);
-
-	tmp |= PHY_LXT971_DIG_CFG_MII_DRIVE;
-
-	davinci_eth_phy_write(phy_addr, PHY_LXT971_DIG_CFG, tmp);
-	/* Read back */
-	if (!davinci_eth_phy_read(phy_addr, PHY_LXT971_DIG_CFG, &tmp))
-		return(0);
-
-	/* Speed doesn't matter, there is no setting for it in EMAC... */
-	if (stat1 & PHY_LXT971_STAT2_DUPLEX_MODE) {
-		/* set DM644x EMAC for Full Duplex  */
-		emac->MACCONTROL = EMAC_MACCONTROL_MIIEN_ENABLE |
-			EMAC_MACCONTROL_FULLDUPLEX_ENABLE;
-	} else {
-		/*set DM644x EMAC for Half Duplex  */
-		emac->MACCONTROL = EMAC_MACCONTROL_MIIEN_ENABLE;
-	}
-
-	return(1);
-}
-
-
-int lxt972_init_phy(int phy_addr)
-{
-	int ret = 1;
-
-	if (!lxt972_get_link_speed(phy_addr)) {
-		/* Try another time */
-		ret = lxt972_get_link_speed(phy_addr);
-	}
-
-	/* Disable PHY Interrupts */
-	davinci_eth_phy_write(phy_addr, PHY_LXT971_INT_ENABLE, 0);
-
-	return(ret);
-}
-
-
-int lxt972_auto_negotiate(int phy_addr)
-{
-	u_int16_t tmp;
-
-	if (!davinci_eth_phy_read(phy_addr, MII_BMCR, &tmp))
-		return(0);
-
-	/* Restart Auto_negotiation  */
-	tmp |= BMCR_ANRESTART;
-	davinci_eth_phy_write(phy_addr, MII_BMCR, tmp);
-
-	/*check AutoNegotiate complete */
-	udelay (10000);
-	if (!davinci_eth_phy_read(phy_addr, MII_BMSR, &tmp))
-		return(0);
-
-	if (!(tmp & BMSR_ANEGCOMPLETE))
-		return(0);
-
-	return (lxt972_get_link_speed(phy_addr));
-}
-
-#endif	/* CONFIG_CMD_NET */
-
-#endif	/* CONFIG_DRIVER_ETHER */
diff --git a/arch/arm/cpu/arm926ejs/davinci/psc.c b/arch/arm/cpu/arm926ejs/davinci/psc.c
deleted file mode 100644
index 8273a7f..0000000
--- a/arch/arm/cpu/arm926ejs/davinci/psc.c
+++ /dev/null
@@ -1,160 +0,0 @@
-/*
- * Power and Sleep Controller (PSC) functions.
- *
- * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
- * Copyright (C) 2008 Lyrtech <www.lyrtech.com>
- * Copyright (C) 2004 Texas Instruments.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#include <common.h>
-#include <asm/arch/hardware.h>
-#include <asm/io.h>
-
-/*
- * The PSC manages three inputs to a "module" which may be a peripheral or
- * CPU.  Those inputs are the module's:  clock; reset signal; and sometimes
- * its power domain.  For our purposes, we only care whether clock and power
- * are active, and the module is out of reset.
- *
- * DaVinci chips may include two separate power domains: "Always On" and "DSP".
- * Chips without a DSP generally have only one domain.
- *
- * The "Always On" power domain is always on when the chip is on, and is
- * powered by the VDD pins (on DM644X). The majority of DaVinci modules
- * lie within the "Always On" power domain.
- *
- * A separate domain called the "DSP" domain houses the C64x+ and other video
- * hardware such as VICP. In some chips, the "DSP" domain is not always on.
- * The "DSP" power domain is powered by the CVDDDSP pins (on DM644X).
- */
-
-/* Works on Always On power domain only (no PD argument) */
-void lpsc_on(unsigned int id)
-{
-	dv_reg_p mdstat, mdctl, ptstat, ptcmd;
-#ifdef CONFIG_SOC_DA8XX
-	struct davinci_psc_regs *psc_regs;
-#endif
-
-#ifndef CONFIG_SOC_DA8XX
-	if (id >= DAVINCI_LPSC_GEM)
-		return;			/* Don't work on DSP Power Domain */
-
-	mdstat = REG_P(PSC_MDSTAT_BASE + (id * 4));
-	mdctl = REG_P(PSC_MDCTL_BASE + (id * 4));
-	ptstat = REG_P(PSC_PTSTAT);
-	ptcmd = REG_P(PSC_PTCMD);
-#else
-	if (id < DAVINCI_LPSC_PSC1_BASE) {
-		if (id >= PSC_PSC0_MODULE_ID_CNT)
-			return;
-		psc_regs = davinci_psc0_regs;
-		mdstat = &psc_regs->psc0.mdstat[id];
-		mdctl = &psc_regs->psc0.mdctl[id];
-	} else {
-		id -= DAVINCI_LPSC_PSC1_BASE;
-		if (id >= PSC_PSC1_MODULE_ID_CNT)
-			return;
-		psc_regs = davinci_psc1_regs;
-		mdstat = &psc_regs->psc1.mdstat[id];
-		mdctl = &psc_regs->psc1.mdctl[id];
-	}
-	ptstat = &psc_regs->ptstat;
-	ptcmd = &psc_regs->ptcmd;
-#endif
-
-	while (readl(ptstat) & 0x01)
-		continue;
-
-	if ((readl(mdstat) & 0x1f) == 0x03)
-		return; /* Already on and enabled */
-
-	writel(readl(mdctl) | 0x03, mdctl);
-
-	switch (id) {
-#ifdef CONFIG_SOC_DM644X
-	/* Special treatment for some modules as for sprue14 p.7.4.2 */
-	case DAVINCI_LPSC_VPSSSLV:
-	case DAVINCI_LPSC_EMAC:
-	case DAVINCI_LPSC_EMAC_WRAPPER:
-	case DAVINCI_LPSC_MDIO:
-	case DAVINCI_LPSC_USB:
-	case DAVINCI_LPSC_ATA:
-	case DAVINCI_LPSC_VLYNQ:
-	case DAVINCI_LPSC_UHPI:
-	case DAVINCI_LPSC_DDR_EMIF:
-	case DAVINCI_LPSC_AEMIF:
-	case DAVINCI_LPSC_MMC_SD:
-	case DAVINCI_LPSC_MEMSTICK:
-	case DAVINCI_LPSC_McBSP:
-	case DAVINCI_LPSC_GPIO:
-		writel(readl(mdctl) | 0x200, mdctl);
-		break;
-#endif
-	}
-
-	writel(0x01, ptcmd);
-
-	while (readl(ptstat) & 0x01)
-		continue;
-	while ((readl(mdstat) & 0x1f) != 0x03)
-		continue;
-}
-
-/* Not all DaVinci chips have a DSP power domain. */
-#ifdef CONFIG_SOC_DM644X
-
-/* If DSPLINK is used, we don't want U-Boot to power on the DSP. */
-#if !defined(CONFIG_SYS_USE_DSPLINK)
-void dsp_on(void)
-{
-	int i;
-
-	if (REG(PSC_PDSTAT1) & 0x1f)
-		return;			/* Already on */
-
-	REG(PSC_GBLCTL) |= 0x01;
-	REG(PSC_PDCTL1) |= 0x01;
-	REG(PSC_PDCTL1) &= ~0x100;
-	REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) |= 0x03;
-	REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) &= 0xfffffeff;
-	REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) |= 0x03;
-	REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) &= 0xfffffeff;
-	REG(PSC_PTCMD) = 0x02;
-
-	for (i = 0; i < 100; i++) {
-		if (REG(PSC_EPCPR) & 0x02)
-			break;
-	}
-
-	REG(PSC_CHP_SHRTSW) = 0x01;
-	REG(PSC_PDCTL1) |= 0x100;
-	REG(PSC_EPCCR) = 0x02;
-
-	for (i = 0; i < 100; i++) {
-		if (!(REG(PSC_PTSTAT) & 0x02))
-			break;
-	}
-
-	REG(PSC_GBLCTL) &= ~0x1f;
-}
-#endif /* CONFIG_SYS_USE_DSPLINK */
-
-#endif /* have a DSP */
diff --git a/arch/arm/cpu/arm926ejs/davinci/reset.S b/arch/arm/cpu/arm926ejs/davinci/reset.S
deleted file mode 100644
index ba0a7c3..0000000
--- a/arch/arm/cpu/arm926ejs/davinci/reset.S
+++ /dev/null
@@ -1,81 +0,0 @@
-/*
- * Processor reset using WDT for TI TMS320DM644x SoC.
- *
- * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
- *
- * -----------------------------------------------------
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-.globl reset_cpu
-reset_cpu:
-	ldr	r0, WDT_TGCR
-	mov	r1, $0x08
-	str	r1, [r0]
-	ldr	r1, [r0]
-	orr	r1, r1, $0x03
-	str	r1, [r0]
-	mov	r1, $0
-	ldr	r0, WDT_TIM12
-	str	r1, [r0]
-	ldr	r0, WDT_TIM34
-	str	r1, [r0]
-	ldr	r0, WDT_PRD12
-	str	r1, [r0]
-	ldr	r0, WDT_PRD34
-	str	r1, [r0]
-	ldr	r0, WDT_TCR
-	ldr	r1, [r0]
-	orr	r1, r1, $0x40
-	str	r1, [r0]
-	ldr	r0, WDT_WDTCR
-	ldr	r1, [r0]
-	orr	r1, r1, $0x4000
-	str	r1, [r0]
-	ldr	r1, WDTCR_VAL1
-	str	r1, [r0]
-	ldr	r1, WDTCR_VAL2
-	str	r1, [r0]
-	/* Write an invalid value to the WDKEY field to trigger
-	 * an immediate watchdog reset */
-	mov     r1, $0x4000
-	str     r1, [r0]
-	nop
-	nop
-	nop
-	nop
-reset_cpu_loop:
-	b	reset_cpu_loop
-
-WDT_TGCR:
-	.word	0x01c21c24
-WDT_TIM12:
-	.word	0x01c21c10
-WDT_TIM34:
-	.word	0x01c21c14
-WDT_PRD12:
-	.word	0x01c21c18
-WDT_PRD34:
-	.word	0x01c21c1c
-WDT_TCR:
-	.word	0x01c21c20
-WDT_WDTCR:
-	.word	0x01c21c28
-WDTCR_VAL1:
-	.word	0xa5c64000
-WDTCR_VAL2:
-	.word	0xda7e4000
diff --git a/arch/arm/cpu/arm926ejs/davinci/timer.c b/arch/arm/cpu/arm926ejs/davinci/timer.c
deleted file mode 100644
index 1c6fa4a..0000000
--- a/arch/arm/cpu/arm926ejs/davinci/timer.c
+++ /dev/null
@@ -1,128 +0,0 @@
-/*
- * (C) Copyright 2003
- * Texas Instruments <www.ti.com>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Alex Zuepke <azu@sysgo.de>
- *
- * (C) Copyright 2002-2004
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * (C) Copyright 2004
- * Philippe Robin, ARM Ltd. <philippe.robin@arm.com>
- *
- * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/io.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-struct davinci_timer {
-	u_int32_t	pid12;
-	u_int32_t	emumgt;
-	u_int32_t	na1;
-	u_int32_t	na2;
-	u_int32_t	tim12;
-	u_int32_t	tim34;
-	u_int32_t	prd12;
-	u_int32_t	prd34;
-	u_int32_t	tcr;
-	u_int32_t	tgcr;
-	u_int32_t	wdtcr;
-};
-
-static struct davinci_timer * const timer =
-	(struct davinci_timer *)CONFIG_SYS_TIMERBASE;
-
-#define TIMER_LOAD_VAL	0xffffffff
-
-#define TIM_CLK_DIV	16
-
-int timer_init(void)
-{
-	/* We are using timer34 in unchained 32-bit mode, full speed */
-	writel(0x0, &timer->tcr);
-	writel(0x0, &timer->tgcr);
-	writel(0x06 | ((TIM_CLK_DIV - 1) << 8), &timer->tgcr);
-	writel(0x0, &timer->tim34);
-	writel(TIMER_LOAD_VAL, &timer->prd34);
-	writel(2 << 22, &timer->tcr);
-	gd->timer_rate_hz = CONFIG_SYS_HZ_CLOCK / TIM_CLK_DIV;
-	gd->timer_reset_value = 0;
-
-	return(0);
-}
-
-void reset_timer(void)
-{
-	gd->timer_reset_value = get_ticks();
-}
-
-/*
- * Get the current 64 bit timer tick count
- */
-unsigned long long get_ticks(void)
-{
-	unsigned long now = readl(&timer->tim34);
-
-	/* increment tbu if tbl has rolled over */
-	if (now < gd->tbl)
-		gd->tbu++;
-	gd->tbl = now;
-
-	return (((unsigned long long)gd->tbu) << 32) | gd->tbl;
-}
-
-ulong get_timer(ulong base)
-{
-	unsigned long long timer_diff;
-
-	timer_diff = get_ticks() - gd->timer_reset_value;
-
-	return (timer_diff / (gd->timer_rate_hz / CONFIG_SYS_HZ)) - base;
-}
-
-void __udelay(unsigned long usec)
-{
-	unsigned long long endtime;
-
-	endtime = ((unsigned long long)usec * gd->timer_rate_hz) / 1000000UL;
-	endtime += get_ticks();
-
-	while (get_ticks() < endtime)
-		;
-}
-
-/*
- * This function is derived from PowerPC code (timebase clock frequency).
- * On ARM it returns the number of timer ticks per second.
- */
-ulong get_tbclk(void)
-{
-	return CONFIG_SYS_HZ;
-}
diff --git a/arch/arm/cpu/arm926ejs/kirkwood/Makefile b/arch/arm/cpu/arm926ejs/kirkwood/Makefile
deleted file mode 100644
index 0754297..0000000
--- a/arch/arm/cpu/arm926ejs/kirkwood/Makefile
+++ /dev/null
@@ -1,49 +0,0 @@
-#
-# (C) Copyright 2009
-# Marvell Semiconductor <www.marvell.com>
-# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
-# MA 02110-1301 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(SOC).o
-
-COBJS-y	= cpu.o
-COBJS-y	+= dram.o
-COBJS-y	+= mpp.o
-COBJS-y	+= timer.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS-y))
-
-all:	$(obj).depend $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/arch/arm/cpu/arm926ejs/kirkwood/cpu.c b/arch/arm/cpu/arm926ejs/kirkwood/cpu.c
deleted file mode 100644
index b4a4c04..0000000
--- a/arch/arm/cpu/arm926ejs/kirkwood/cpu.c
+++ /dev/null
@@ -1,399 +0,0 @@
-/*
- * (C) Copyright 2009
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-#include <common.h>
-#include <netdev.h>
-#include <asm/cache.h>
-#include <u-boot/md5.h>
-#include <asm/arch/kirkwood.h>
-#include <hush.h>
-
-#define BUFLEN	16
-
-void reset_cpu(unsigned long ignored)
-{
-	struct kwcpu_registers *cpureg =
-	    (struct kwcpu_registers *)KW_CPU_REG_BASE;
-
-	writel(readl(&cpureg->rstoutn_mask) | (1 << 2),
-		&cpureg->rstoutn_mask);
-	writel(readl(&cpureg->sys_soft_rst) | 1,
-		&cpureg->sys_soft_rst);
-	while (1) ;
-}
-
-/*
- * Generates Ramdom hex number reading some time varient system registers
- * and using md5 algorithm
- */
-unsigned char get_random_hex(void)
-{
-	int i;
-	u32 inbuf[BUFLEN];
-	u8 outbuf[BUFLEN];
-
-	/*
-	 * in case of 88F6281/88F6282/88F6192 A0,
-	 * Bit7 need to reset to generate random values in KW_REG_UNDOC_0x1470
-	 * Soc reg offsets KW_REG_UNDOC_0x1470 and KW_REG_UNDOC_0x1478 are
-	 * reserved regs and does not have names at this moment
-	 * (no errata available)
-	 */
-	writel(readl(KW_REG_UNDOC_0x1478) & ~(1 << 7), KW_REG_UNDOC_0x1478);
-	for (i = 0; i < BUFLEN; i++) {
-		inbuf[i] = readl(KW_REG_UNDOC_0x1470);
-	}
-	md5((u8 *) inbuf, (BUFLEN * sizeof(u32)), outbuf);
-	return outbuf[outbuf[7] % 0x0f];
-}
-
-/*
- * Window Size
- * Used with the Base register to set the address window size and location.
- * Must be programmed from LSB to MSB as sequence of ones followed by
- * sequence of zeros. The number of ones specifies the size of the window in
- * 64 KByte granularity (e.g., a value of 0x00FF specifies 256 = 16 MByte).
- * NOTE: A value of 0x0 specifies 64-KByte size.
- */
-unsigned int kw_winctrl_calcsize(unsigned int sizeval)
-{
-	int i;
-	unsigned int j = 0;
-	u32 val = sizeval >> 1;
-
-	for (i = 0; val >= 0x10000; i++) {
-		j |= (1 << i);
-		val = val >> 1;
-	}
-	return (0x0000ffff & j);
-}
-
-/*
- * kw_config_adr_windows - Configure address Windows
- *
- * There are 8 address windows supported by Kirkwood Soc to addess different
- * devices. Each window can be configured for size, BAR and remap addr
- * Below configuration is standard for most of the cases
- *
- * If remap function not used, remap_lo must be set as base
- *
- * Reference Documentation:
- * Mbus-L to Mbus Bridge Registers Configuration.
- * (Sec 25.1 and 25.3 of Datasheet)
- */
-int kw_config_adr_windows(void)
-{
-	struct kwwin_registers *winregs =
-		(struct kwwin_registers *)KW_CPU_WIN_BASE;
-
-	/* Window 0: PCIE MEM address space */
-	writel(KWCPU_WIN_CTRL_DATA(1024 * 1024 * 256, KWCPU_TARGET_PCIE,
-		KWCPU_ATTR_PCIE_MEM, KWCPU_WIN_ENABLE), &winregs[0].ctrl);
-
-	writel(KW_DEFADR_PCI_MEM, &winregs[0].base);
-	writel(KW_DEFADR_PCI_MEM, &winregs[0].remap_lo);
-	writel(0x0, &winregs[0].remap_hi);
-
-	/* Window 1: PCIE IO address space */
-	writel(KWCPU_WIN_CTRL_DATA(1024 * 64, KWCPU_TARGET_PCIE,
-		KWCPU_ATTR_PCIE_IO, KWCPU_WIN_ENABLE), &winregs[1].ctrl);
-	writel(KW_DEFADR_PCI_IO, &winregs[1].base);
-	writel(KW_DEFADR_PCI_IO_REMAP, &winregs[1].remap_lo);
-	writel(0x0, &winregs[1].remap_hi);
-
-	/* Window 2: NAND Flash address space */
-	writel(KWCPU_WIN_CTRL_DATA(1024 * 1024 * 128, KWCPU_TARGET_MEMORY,
-		KWCPU_ATTR_NANDFLASH, KWCPU_WIN_ENABLE), &winregs[2].ctrl);
-	writel(KW_DEFADR_NANDF, &winregs[2].base);
-	writel(KW_DEFADR_NANDF, &winregs[2].remap_lo);
-	writel(0x0, &winregs[2].remap_hi);
-
-	/* Window 3: SPI Flash address space */
-	writel(KWCPU_WIN_CTRL_DATA(1024 * 1024 * 128, KWCPU_TARGET_MEMORY,
-		KWCPU_ATTR_SPIFLASH, KWCPU_WIN_ENABLE), &winregs[3].ctrl);
-	writel(KW_DEFADR_SPIF, &winregs[3].base);
-	writel(KW_DEFADR_SPIF, &winregs[3].remap_lo);
-	writel(0x0, &winregs[3].remap_hi);
-
-	/* Window 4: BOOT Memory address space */
-	writel(KWCPU_WIN_CTRL_DATA(1024 * 1024 * 128, KWCPU_TARGET_MEMORY,
-		KWCPU_ATTR_BOOTROM, KWCPU_WIN_ENABLE), &winregs[4].ctrl);
-	writel(KW_DEFADR_BOOTROM, &winregs[4].base);
-
-	/* Window 5: Security SRAM address space */
-	writel(KWCPU_WIN_CTRL_DATA(1024 * 64, KWCPU_TARGET_SASRAM,
-		KWCPU_ATTR_SASRAM, KWCPU_WIN_ENABLE), &winregs[5].ctrl);
-	writel(KW_DEFADR_SASRAM, &winregs[5].base);
-
-	/* Window 6-7: Disabled */
-	writel(KWCPU_WIN_DISABLE, &winregs[6].ctrl);
-	writel(KWCPU_WIN_DISABLE, &winregs[7].ctrl);
-
-	return 0;
-}
-
-/*
- * kw_config_gpio - GPIO configuration
- */
-void kw_config_gpio(u32 gpp0_oe_val, u32 gpp1_oe_val, u32 gpp0_oe, u32 gpp1_oe)
-{
-	struct kwgpio_registers *gpio0reg =
-		(struct kwgpio_registers *)KW_GPIO0_BASE;
-	struct kwgpio_registers *gpio1reg =
-		(struct kwgpio_registers *)KW_GPIO1_BASE;
-
-	/* Init GPIOS to default values as per board requirement */
-	writel(gpp0_oe_val, &gpio0reg->dout);
-	writel(gpp1_oe_val, &gpio1reg->dout);
-	writel(gpp0_oe, &gpio0reg->oe);
-	writel(gpp1_oe, &gpio1reg->oe);
-}
-
-/*
- * kw_config_mpp - Multi-Purpose Pins Functionality configuration
- *
- * Each MPP can be configured to different functionality through
- * MPP control register, ref (sec 6.1 of kirkwood h/w specification)
- *
- * There are maximum 64 Multi-Pourpose Pins on Kirkwood
- * Each MPP functionality can be configuration by a 4bit value
- * of MPP control reg, the value and associated functionality depends
- * upon used SoC varient
- */
-int kw_config_mpp(u32 mpp0_7, u32 mpp8_15, u32 mpp16_23, u32 mpp24_31,
-		u32 mpp32_39, u32 mpp40_47, u32 mpp48_55)
-{
-	u32 *mppreg = (u32 *) KW_MPP_BASE;
-
-	/* program mpp registers */
-	writel(mpp0_7, &mppreg[0]);
-	writel(mpp8_15, &mppreg[1]);
-	writel(mpp16_23, &mppreg[2]);
-	writel(mpp24_31, &mppreg[3]);
-	writel(mpp32_39, &mppreg[4]);
-	writel(mpp40_47, &mppreg[5]);
-	writel(mpp48_55, &mppreg[6]);
-	return 0;
-}
-
-/*
- * SYSRSTn Duration Counter Support
- *
- * Kirkwood SoC implements a hardware-based SYSRSTn duration counter.
- * When SYSRSTn is asserted low, a SYSRSTn duration counter is running.
- * The SYSRSTn duration counter is useful for implementing a manufacturer
- * or factory reset. Upon a long reset assertion that is greater than a
- * pre-configured environment variable value for sysrstdelay,
- * The counter value is stored in the SYSRSTn Length Counter Register
- * The counter is based on the 25-MHz reference clock (40ns)
- * It is a 29-bit counter, yielding a maximum counting duration of
- * 2^29/25 MHz (21.4 seconds). When the counter reach its maximum value,
- * it remains at this value until counter reset is triggered by setting
- * bit 31 of KW_REG_SYSRST_CNT
- */
-static void kw_sysrst_action(void)
-{
-	int ret;
-	char *s = getenv("sysrstcmd");
-
-	if (!s) {
-		debug("Error.. %s failed, check sysrstcmd\n",
-			__FUNCTION__);
-		return;
-	}
-
-	debug("Starting %s process...\n", __FUNCTION__);
-#if !defined(CONFIG_SYS_HUSH_PARSER)
-	ret = run_command (s, 0);
-#else
-	ret = parse_string_outer(s, FLAG_PARSE_SEMICOLON
-				  | FLAG_EXIT_FROM_LOOP);
-#endif
-	if (ret < 0)
-		debug("Error.. %s failed\n", __FUNCTION__);
-	else
-		debug("%s process finished\n", __FUNCTION__);
-}
-
-static void kw_sysrst_check(void)
-{
-	u32 sysrst_cnt, sysrst_dly;
-	char *s;
-
-	/*
-	 * no action if sysrstdelay environment variable is not defined
-	 */
-	s = getenv("sysrstdelay");
-	if (s == NULL)
-		return;
-
-	/* read sysrstdelay value */
-	sysrst_dly = (u32) simple_strtoul(s, NULL, 10);
-
-	/* read SysRst Length counter register (bits 28:0) */
-	sysrst_cnt = (0x1fffffff & readl(KW_REG_SYSRST_CNT));
-	debug("H/w Rst hold time: %d.%d secs\n",
-		sysrst_cnt / SYSRST_CNT_1SEC_VAL,
-		sysrst_cnt % SYSRST_CNT_1SEC_VAL);
-
-	/* clear the counter for next valid read*/
-	writel(1 << 31, KW_REG_SYSRST_CNT);
-
-	/*
-	 * sysrst_action:
-	 * if H/w Reset key is pressed and hold for time
-	 * more than sysrst_dly in seconds
-	 */
-	if (sysrst_cnt >= SYSRST_CNT_1SEC_VAL * sysrst_dly)
-		kw_sysrst_action();
-}
-
-#if defined(CONFIG_DISPLAY_CPUINFO)
-int print_cpuinfo(void)
-{
-	char *rev;
-	u16 devid = (readl(KW_REG_PCIE_DEVID) >> 16) & 0xffff;
-	u8 revid = readl(KW_REG_PCIE_REVID) & 0xff;
-
-	if ((readl(KW_REG_DEVICE_ID) & 0x03) > 2) {
-		printf("Error.. %s:Unsupported Kirkwood SoC 88F%04x\n", __FUNCTION__, devid);
-		return -1;
-	}
-
-	switch (revid) {
-	case 0:
-		rev = "Z0";
-		break;
-	case 2:
-		rev = "A0";
-		break;
-	case 3:
-		rev = "A1";
-		break;
-	default:
-		rev = "??";
-		break;
-	}
-
-	printf("SoC:   Kirkwood 88F%04x_%s\n", devid, rev);
-	return 0;
-}
-#endif /* CONFIG_DISPLAY_CPUINFO */
-
-#ifdef CONFIG_ARCH_CPU_INIT
-int arch_cpu_init(void)
-{
-	u32 reg;
-	struct kwcpu_registers *cpureg =
-		(struct kwcpu_registers *)KW_CPU_REG_BASE;
-
-	/* Linux expects` the internal registers to be at 0xf1000000 */
-	writel(KW_REGS_PHY_BASE, KW_OFFSET_REG);
-
-	/* Enable and invalidate L2 cache in write through mode */
-	writel(readl(&cpureg->l2_cfg) | 0x18, &cpureg->l2_cfg);
-	invalidate_l2_cache();
-
-	kw_config_adr_windows();
-
-#ifdef CONFIG_KIRKWOOD_RGMII_PAD_1V8
-	/*
-	 * Configures the I/O voltage of the pads connected to Egigabit
-	 * Ethernet interface to 1.8V
-	 * By defult it is set to 3.3V
-	 */
-	reg = readl(KW_REG_MPP_OUT_DRV_REG);
-	reg |= (1 << 7);
-	writel(reg, KW_REG_MPP_OUT_DRV_REG);
-#endif
-#ifdef CONFIG_KIRKWOOD_EGIGA_INIT
-	/*
-	 * Set egiga port0/1 in normal functional mode
-	 * This is required becasue on kirkwood by default ports are in reset mode
-	 * OS egiga driver may not have provision to set them in normal mode
-	 * and if u-boot is build without network support, network may fail at OS level
-	 */
-	reg = readl(KWGBE_PORT_SERIAL_CONTROL1_REG(0));
-	reg &= ~(1 << 4);	/* Clear PortReset Bit */
-	writel(reg, (KWGBE_PORT_SERIAL_CONTROL1_REG(0)));
-	reg = readl(KWGBE_PORT_SERIAL_CONTROL1_REG(1));
-	reg &= ~(1 << 4);	/* Clear PortReset Bit */
-	writel(reg, (KWGBE_PORT_SERIAL_CONTROL1_REG(1)));
-#endif
-#ifdef CONFIG_KIRKWOOD_PCIE_INIT
-	/*
-	 * Enable PCI Express Port0
-	 */
-	reg = readl(&cpureg->ctrl_stat);
-	reg |= (1 << 0);	/* Set PEX0En Bit */
-	writel(reg, &cpureg->ctrl_stat);
-#endif
-	return 0;
-}
-#endif /* CONFIG_ARCH_CPU_INIT */
-
-/*
- * SOC specific misc init
- */
-#if defined(CONFIG_ARCH_MISC_INIT)
-int arch_misc_init(void)
-{
-	volatile u32 temp;
-
-	/*CPU streaming & write allocate */
-	temp = readfr_extra_feature_reg();
-	temp &= ~(1 << 28);	/* disable wr alloc */
-	writefr_extra_feature_reg(temp);
-
-	temp = readfr_extra_feature_reg();
-	temp &= ~(1 << 29);	/* streaming disabled */
-	writefr_extra_feature_reg(temp);
-
-	/* L2Cache settings */
-	temp = readfr_extra_feature_reg();
-	/* Disable L2C pre fetch - Set bit 24 */
-	temp |= (1 << 24);
-	/* enable L2C - Set bit 22 */
-	temp |= (1 << 22);
-	writefr_extra_feature_reg(temp);
-
-	icache_enable();
-	/* Change reset vector to address 0x0 */
-	temp = get_cr();
-	set_cr(temp & ~CR_V);
-
-	/* checks and execute resset to factory event */
-	kw_sysrst_check();
-
-	return 0;
-}
-#endif /* CONFIG_ARCH_MISC_INIT */
-
-#ifdef CONFIG_MVGBE
-int cpu_eth_init(bd_t *bis)
-{
-	mvgbe_initialize(bis);
-	return 0;
-}
-#endif
diff --git a/arch/arm/cpu/arm926ejs/kirkwood/dram.c b/arch/arm/cpu/arm926ejs/kirkwood/dram.c
deleted file mode 100644
index 2441554..0000000
--- a/arch/arm/cpu/arm926ejs/kirkwood/dram.c
+++ /dev/null
@@ -1,105 +0,0 @@
-/*
- * (C) Copyright 2009
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-#include <config.h>
-#include <common.h>
-#include <asm/arch/kirkwood.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define KW_REG_CPUCS_WIN_BAR(x)		(KW_REGISTER(0x1500) + (x * 0x08))
-#define KW_REG_CPUCS_WIN_SZ(x)		(KW_REGISTER(0x1504) + (x * 0x08))
-/*
- * kw_sdram_bar - reads SDRAM Base Address Register
- */
-u32 kw_sdram_bar(enum memory_bank bank)
-{
-	u32 result = 0;
-	u32 enable = 0x01 & readl(KW_REG_CPUCS_WIN_SZ(bank));
-
-	if ((!enable) || (bank > BANK3))
-		return 0;
-
-	result = readl(KW_REG_CPUCS_WIN_BAR(bank));
-	return result;
-}
-
-/*
- * kw_sdram_bs - reads SDRAM Bank size
- */
-u32 kw_sdram_bs(enum memory_bank bank)
-{
-	u32 result = 0;
-	u32 enable = 0x01 & readl(KW_REG_CPUCS_WIN_SZ(bank));
-
-	if ((!enable) || (bank > BANK3))
-		return 0;
-	result = 0xff000000 & readl(KW_REG_CPUCS_WIN_SZ(bank));
-	result += 0x01000000;
-	return result;
-}
-
-#ifndef CONFIG_SYS_BOARD_DRAM_INIT
-int dram_init(void)
-{
-	int i;
-
-	gd->ram_size = 0;
-	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
-		gd->bd->bi_dram[i].start = kw_sdram_bar(i);
-		gd->bd->bi_dram[i].size = kw_sdram_bs(i);
-		/*
-		 * It is assumed that all memory banks are consecutive
-		 * and without gaps.
-		 * If the gap is found, ram_size will be reported for
-		 * consecutive memory only
-		 */
-		if (gd->bd->bi_dram[i].start != gd->ram_size)
-			break;
-
-		gd->ram_size += gd->bd->bi_dram[i].size;
-
-	}
-
-	for (; i < CONFIG_NR_DRAM_BANKS; i++) {
-		/* If above loop terminated prematurely, we need to set
-		 * remaining banks' start address & size as 0. Otherwise other
-		 * u-boot functions and Linux kernel gets wrong values which
-		 * could result in crash */
-		gd->bd->bi_dram[i].start = 0;
-		gd->bd->bi_dram[i].size = 0;
-	}
-
-	return 0;
-}
-
-/*
- * If this function is not defined here,
- * board.c alters dram bank zero configuration defined above.
- */
-void dram_init_banksize(void)
-{
-	dram_init();
-}
-#endif /* CONFIG_SYS_BOARD_DRAM_INIT */
diff --git a/arch/arm/cpu/arm926ejs/kirkwood/mpp.c b/arch/arm/cpu/arm926ejs/kirkwood/mpp.c
deleted file mode 100644
index b2f0ad5..0000000
--- a/arch/arm/cpu/arm926ejs/kirkwood/mpp.c
+++ /dev/null
@@ -1,80 +0,0 @@
-/*
- * arch/arm/mach-kirkwood/mpp.c
- *
- * MPP functions for Marvell Kirkwood SoCs
- * Referenced from Linux kernel source
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include <common.h>
-#include <asm/arch/kirkwood.h>
-#include <asm/arch/mpp.h>
-
-static u32 kirkwood_variant(void)
-{
-	switch (readl(KW_REG_DEVICE_ID) & 0x03) {
-	case 1:
-		return MPP_F6192_MASK;
-	case 2:
-		return MPP_F6281_MASK;
-	default:
-		debug("MPP setup: unknown kirkwood variant\n");
-		return 0;
-	}
-}
-
-#define MPP_CTRL(i)	(KW_MPP_BASE + (i* 4))
-#define MPP_NR_REGS	(1 + MPP_MAX/8)
-
-void kirkwood_mpp_conf(u32 *mpp_list)
-{
-	u32 mpp_ctrl[MPP_NR_REGS];
-	unsigned int variant_mask;
-	int i;
-
-	variant_mask = kirkwood_variant();
-	if (!variant_mask)
-		return;
-
-	debug( "initial MPP regs:");
-	for (i = 0; i < MPP_NR_REGS; i++) {
-		mpp_ctrl[i] = readl(MPP_CTRL(i));
-		debug(" %08x", mpp_ctrl[i]);
-	}
-	debug("\n");
-
-
-	while (*mpp_list) {
-		unsigned int num = MPP_NUM(*mpp_list);
-		unsigned int sel = MPP_SEL(*mpp_list);
-		int shift;
-
-		if (num > MPP_MAX) {
-			debug("kirkwood_mpp_conf: invalid MPP "
-					"number (%u)\n", num);
-			continue;
-		}
-		if (!(*mpp_list & variant_mask)) {
-			debug("kirkwood_mpp_conf: requested MPP%u config "
-				"unavailable on this hardware\n", num);
-			continue;
-		}
-
-		shift = (num & 7) << 2;
-		mpp_ctrl[num / 8] &= ~(0xf << shift);
-		mpp_ctrl[num / 8] |= sel << shift;
-
-		mpp_list++;
-	}
-
-	debug("  final MPP regs:");
-	for (i = 0; i < MPP_NR_REGS; i++) {
-		writel(mpp_ctrl[i], MPP_CTRL(i));
-		debug(" %08x", mpp_ctrl[i]);
-	}
-	debug("\n");
-
-}
diff --git a/arch/arm/cpu/arm926ejs/kirkwood/timer.c b/arch/arm/cpu/arm926ejs/kirkwood/timer.c
deleted file mode 100644
index 3e80329..0000000
--- a/arch/arm/cpu/arm926ejs/kirkwood/timer.c
+++ /dev/null
@@ -1,170 +0,0 @@
-/*
- * Copyright (C) Marvell International Ltd. and its affiliates
- * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-#include <common.h>
-#include <asm/arch/kirkwood.h>
-
-#define UBOOT_CNTR	0	/* counter to use for uboot timer */
-
-/* Timer reload and current value registers */
-struct kwtmr_val {
-	u32 reload;	/* Timer reload reg */
-	u32 val;	/* Timer value reg */
-};
-
-/* Timer registers */
-struct kwtmr_registers {
-	u32 ctrl;	/* Timer control reg */
-	u32 pad[3];
-	struct kwtmr_val tmr[2];
-	u32 wdt_reload;
-	u32 wdt_val;
-};
-
-struct kwtmr_registers *kwtmr_regs = (struct kwtmr_registers *)KW_TIMER_BASE;
-
-/*
- * ARM Timers Registers Map
- */
-#define CNTMR_CTRL_REG			&kwtmr_regs->ctrl
-#define CNTMR_RELOAD_REG(tmrnum)	&kwtmr_regs->tmr[tmrnum].reload
-#define CNTMR_VAL_REG(tmrnum)		&kwtmr_regs->tmr[tmrnum].val
-
-/*
- * ARM Timers Control Register
- * CPU_TIMERS_CTRL_REG (CTCR)
- */
-#define CTCR_ARM_TIMER_EN_OFFS(cntr)	(cntr * 2)
-#define CTCR_ARM_TIMER_EN_MASK(cntr)	(1 << CTCR_ARM_TIMER_EN_OFFS)
-#define CTCR_ARM_TIMER_EN(cntr)		(1 << CTCR_ARM_TIMER_EN_OFFS(cntr))
-#define CTCR_ARM_TIMER_DIS(cntr)	(0 << CTCR_ARM_TIMER_EN_OFFS(cntr))
-
-#define CTCR_ARM_TIMER_AUTO_OFFS(cntr)	((cntr * 2) + 1)
-#define CTCR_ARM_TIMER_AUTO_MASK(cntr)	(1 << 1)
-#define CTCR_ARM_TIMER_AUTO_EN(cntr)	(1 << CTCR_ARM_TIMER_AUTO_OFFS(cntr))
-#define CTCR_ARM_TIMER_AUTO_DIS(cntr)	(0 << CTCR_ARM_TIMER_AUTO_OFFS(cntr))
-
-/*
- * ARM Timer\Watchdog Reload Register
- * CNTMR_RELOAD_REG (TRR)
- */
-#define TRG_ARM_TIMER_REL_OFFS		0
-#define TRG_ARM_TIMER_REL_MASK		0xffffffff
-
-/*
- * ARM Timer\Watchdog Register
- * CNTMR_VAL_REG (TVRG)
- */
-#define TVR_ARM_TIMER_OFFS		0
-#define TVR_ARM_TIMER_MASK		0xffffffff
-#define TVR_ARM_TIMER_MAX		0xffffffff
-#define TIMER_LOAD_VAL 			0xffffffff
-
-#define READ_TIMER			(readl(CNTMR_VAL_REG(UBOOT_CNTR)) /	\
-					 (CONFIG_SYS_TCLK / 1000))
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define timestamp gd->tbl
-#define lastdec gd->lastinc
-
-void reset_timer_masked(void)
-{
-	/* reset time */
-	lastdec = READ_TIMER;
-	timestamp = 0;
-}
-
-ulong get_timer_masked(void)
-{
-	ulong now = READ_TIMER;
-
-	if (lastdec >= now) {
-		/* normal mode */
-		timestamp += lastdec - now;
-	} else {
-		/* we have an overflow ... */
-		timestamp += lastdec +
-			(TIMER_LOAD_VAL / (CONFIG_SYS_TCLK / 1000)) - now;
-	}
-	lastdec = now;
-
-	return timestamp;
-}
-
-void reset_timer(void)
-{
-	reset_timer_masked();
-}
-
-ulong get_timer(ulong base)
-{
-	return get_timer_masked() - base;
-}
-
-void set_timer(ulong t)
-{
-	timestamp = t;
-}
-
-void __udelay(unsigned long usec)
-{
-	uint current;
-	ulong delayticks;
-
-	current = readl(CNTMR_VAL_REG(UBOOT_CNTR));
-	delayticks = (usec * (CONFIG_SYS_TCLK / 1000000));
-
-	if (current < delayticks) {
-		delayticks -= current;
-		while (readl(CNTMR_VAL_REG(UBOOT_CNTR)) < current) ;
-		while ((TIMER_LOAD_VAL - delayticks) <
-			readl(CNTMR_VAL_REG(UBOOT_CNTR))) ;
-	} else {
-		while (readl(CNTMR_VAL_REG(UBOOT_CNTR)) >
-			(current - delayticks)) ;
-	}
-}
-
-/*
- * init the counter
- */
-int timer_init(void)
-{
-	unsigned int cntmrctrl;
-
-	/* load value into timer */
-	writel(TIMER_LOAD_VAL, CNTMR_RELOAD_REG(UBOOT_CNTR));
-	writel(TIMER_LOAD_VAL, CNTMR_VAL_REG(UBOOT_CNTR));
-
-	/* enable timer in auto reload mode */
-	cntmrctrl = readl(CNTMR_CTRL_REG);
-	cntmrctrl |= CTCR_ARM_TIMER_EN(UBOOT_CNTR);
-	cntmrctrl |= CTCR_ARM_TIMER_AUTO_EN(UBOOT_CNTR);
-	writel(cntmrctrl, CNTMR_CTRL_REG);
-
-	/* init the timestamp and lastdec value */
-	reset_timer_masked();
-
-	return 0;
-}
diff --git a/arch/arm/cpu/arm926ejs/mb86r0x/Makefile b/arch/arm/cpu/arm926ejs/mb86r0x/Makefile
deleted file mode 100644
index bab048b..0000000
--- a/arch/arm/cpu/arm926ejs/mb86r0x/Makefile
+++ /dev/null
@@ -1,47 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(SOC).o
-
-COBJS	= clock.o reset.o timer.o
-SOBJS	=
-
-SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS) $(SOBJS))
-START	:= $(addprefix $(obj),$(START))
-
-all:	$(obj).depend $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/arch/arm/cpu/arm926ejs/mb86r0x/clock.c b/arch/arm/cpu/arm926ejs/mb86r0x/clock.c
deleted file mode 100644
index 70c8c8b..0000000
--- a/arch/arm/cpu/arm926ejs/mb86r0x/clock.c
+++ /dev/null
@@ -1,43 +0,0 @@
-/*
- * (C) Copyright 2010
- * Matthias Weisser <weisserm@arcor.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/hardware.h>
-
-/*
- * Get the peripheral bus frequency depending on pll pin settings
- */
-ulong get_bus_freq(ulong dummy)
-{
-	struct mb86r0x_crg * crg = (struct mb86r0x_crg *)
-					MB86R0x_CRG_BASE;
-	uint32_t pllmode;
-
-	pllmode = readl(&crg->crpr) & MB86R0x_CRG_CRPR_PLLMODE;
-
-	if (pllmode == MB86R0x_CRG_CRPR_PLLMODE_X20)
-		return 40000000;
-
-	return 41164767;
-}
diff --git a/arch/arm/cpu/arm926ejs/mb86r0x/reset.c b/arch/arm/cpu/arm926ejs/mb86r0x/reset.c
deleted file mode 100644
index e7f0f67..0000000
--- a/arch/arm/cpu/arm926ejs/mb86r0x/reset.c
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
- * (C) Copyright 2010
- * Matthias Weisser <weisserm@arcor.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/hardware.h>
-
-/*
- * Reset the cpu by setting software reset request bit
- */
-void reset_cpu(ulong ignored)
-{
-	struct mb86r0x_crg * crg = (struct mb86r0x_crg *)
-					MB86R0x_CRG_BASE;
-
-	writel(MB86R0x_CRSR_SWRSTREQ, &crg->crsr);
-	while (1)
-		/* NOP */;
-	/* Never reached */
-}
diff --git a/arch/arm/cpu/arm926ejs/mb86r0x/timer.c b/arch/arm/cpu/arm926ejs/mb86r0x/timer.c
deleted file mode 100644
index 6966b0d..0000000
--- a/arch/arm/cpu/arm926ejs/mb86r0x/timer.c
+++ /dev/null
@@ -1,144 +0,0 @@
-/*
- * (C) Copyright 2007-2008
- * Stelian Pop <stelian.pop@leadtechdesign.com>
- * Lead Tech Design <www.leadtechdesign.com>
- *
- * (C) Copyright 2010
- * Matthias Weisser, Graf-Syteco <weisserm@arcor.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <div64.h>
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/hardware.h>
-
-#define TIMER_LOAD_VAL	0xffffffff
-#define TIMER_FREQ	(CONFIG_MB86R0x_IOCLK  / 256)
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define timestamp gd->tbl
-#define lastdec gd->lastinc
-
-static inline unsigned long long tick_to_time(unsigned long long tick)
-{
-	tick *= CONFIG_SYS_HZ;
-	do_div(tick, TIMER_FREQ);
-
-	return tick;
-}
-
-static inline unsigned long long usec_to_tick(unsigned long long usec)
-{
-	usec *= TIMER_FREQ;
-	do_div(usec, 1000000);
-
-	return usec;
-}
-
-/* nothing really to do with interrupts, just starts up a counter. */
-int timer_init(void)
-{
-	struct mb86r0x_timer * timer = (struct mb86r0x_timer *)
-					MB86R0x_TIMER_BASE;
-	ulong ctrl = readl(&timer->control);
-
-	writel(TIMER_LOAD_VAL, &timer->load);
-
-	ctrl |= MB86R0x_TIMER_ENABLE | MB86R0x_TIMER_PRS_8S |
-		MB86R0x_TIMER_SIZE_32;
-
-	writel(ctrl, &timer->control);
-
-	reset_timer_masked();
-
-	return 0;
-}
-
-/*
- * timer without interrupts
- */
-unsigned long long get_ticks(void)
-{
-	struct mb86r0x_timer * timer = (struct mb86r0x_timer *)
-					MB86R0x_TIMER_BASE;
-	ulong now = readl(&timer->value);
-
-	if (now <= lastdec) {
-		/* normal mode (non roll) */
-		/* move stamp forward with absolut diff ticks */
-		timestamp += lastdec - now;
-	} else {
-		/* we have rollover of incrementer */
-		timestamp += lastdec + TIMER_LOAD_VAL - now;
-	}
-	lastdec = now;
-	return timestamp;
-}
-
-void reset_timer_masked(void)
-{
-	struct mb86r0x_timer * timer = (struct mb86r0x_timer *)
-					MB86R0x_TIMER_BASE;
-
-	/* capture current value time */
-	lastdec = readl(&timer->value);
-	timestamp = 0; /* start "advancing" time stamp from 0 */
-}
-
-ulong get_timer_masked(void)
-{
-	return tick_to_time(get_ticks());
-}
-
-void __udelay(unsigned long usec)
-{
-	unsigned long long tmp;
-	ulong tmo;
-
-	tmo = usec_to_tick(usec);
-	tmp = get_ticks();			/* get current timestamp */
-
-	while ((get_ticks() - tmp) < tmo)	/* loop till event */
-		 /*NOP*/;
-}
-
-void reset_timer(void)
-{
-	reset_timer_masked();
-}
-
-ulong get_timer(ulong base)
-{
-	return get_timer_masked() - base;
-}
-
-/*
- * This function is derived from PowerPC code (timebase clock frequency).
- * On ARM it returns the number of timer ticks per second.
- */
-ulong get_tbclk(void)
-{
-	ulong tbclk;
-
-	tbclk = TIMER_FREQ;
-	return tbclk;
-}
diff --git a/arch/arm/cpu/arm926ejs/mx25/Makefile b/arch/arm/cpu/arm926ejs/mx25/Makefile
deleted file mode 100644
index 38d7f03..0000000
--- a/arch/arm/cpu/arm926ejs/mx25/Makefile
+++ /dev/null
@@ -1,46 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(SOC).o
-
-COBJS	= generic.o timer.o
-MX27OBJS = reset.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-SRCS	+= $(addprefix $(SRCTREE)/arch/arm/cpu/arm926ejs/mx27/,$(MX27OBJS:.o=.c))
-OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS) $(MX27OBJS))
-
-all:	$(obj).depend $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/arch/arm/cpu/arm926ejs/mx25/generic.c b/arch/arm/cpu/arm926ejs/mx25/generic.c
deleted file mode 100644
index c6e1146..0000000
--- a/arch/arm/cpu/arm926ejs/mx25/generic.c
+++ /dev/null
@@ -1,275 +0,0 @@
-/*
- * (C) Copyright 2009 DENX Software Engineering
- * Author: John Rigby <jrigby@gmail.com>
- *
- * Based on mx27/generic.c:
- *  Copyright (c) 2008 Eric Jarrige <eric.jarrige@armadeus.org>
- *  Copyright (c) 2009 Ilya Yanok <yanok@emcraft.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <div64.h>
-#include <netdev.h>
-#include <asm/io.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/imx25-pinmux.h>
-#ifdef CONFIG_MXC_MMC
-#include <asm/arch/mxcmmc.h>
-#endif
-
-/*
- *  get the system pll clock in Hz
- *
- *                  mfi + mfn / (mfd +1)
- *  f = 2 * f_ref * --------------------
- *                        pd + 1
- */
-static unsigned int imx_decode_pll (unsigned int pll, unsigned int f_ref)
-{
-	unsigned int mfi = (pll >> CCM_PLL_MFI_SHIFT)
-	    & CCM_PLL_MFI_MASK;
-	unsigned int mfn = (pll >> CCM_PLL_MFN_SHIFT)
-	    & CCM_PLL_MFN_MASK;
-	unsigned int mfd = (pll >> CCM_PLL_MFD_SHIFT)
-	    & CCM_PLL_MFD_MASK;
-	unsigned int pd = (pll >> CCM_PLL_PD_SHIFT)
-	    & CCM_PLL_PD_MASK;
-
-	mfi = mfi <= 5 ? 5 : mfi;
-
-	return lldiv (2 * (u64) f_ref * (mfi * (mfd + 1) + mfn),
-		      (mfd + 1) * (pd + 1));
-}
-
-static ulong imx_get_mpllclk (void)
-{
-	struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
-	ulong fref = 24000000;
-
-	return imx_decode_pll (readl (&ccm->mpctl), fref);
-}
-
-ulong imx_get_armclk (void)
-{
-	struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
-	ulong cctl = readl (&ccm->cctl);
-	ulong fref = imx_get_mpllclk ();
-	ulong div;
-
-	if (cctl & CCM_CCTL_ARM_SRC)
-		fref = lldiv ((fref * 3), 4);
-
-	div = ((cctl >> CCM_CCTL_ARM_DIV_SHIFT)
-	       & CCM_CCTL_ARM_DIV_MASK) + 1;
-
-	return lldiv (fref, div);
-}
-
-ulong imx_get_ahbclk (void)
-{
-	struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
-	ulong cctl = readl (&ccm->cctl);
-	ulong fref = imx_get_armclk ();
-	ulong div;
-
-	div = ((cctl >> CCM_CCTL_AHB_DIV_SHIFT)
-	       & CCM_CCTL_AHB_DIV_MASK) + 1;
-
-	return lldiv (fref, div);
-}
-
-ulong imx_get_perclk (int clk)
-{
-	struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
-	ulong fref = imx_get_ahbclk ();
-	ulong div;
-
-	div = readl (&ccm->pcdr[CCM_PERCLK_REG (clk)]);
-	div = ((div >> CCM_PERCLK_SHIFT (clk)) & CCM_PERCLK_MASK) + 1;
-
-	return lldiv (fref, div);
-}
-
-#if defined(CONFIG_DISPLAY_CPUINFO)
-int print_cpuinfo (void)
-{
-	char buf[32];
-
-	printf ("CPU:   Freescale i.MX25 at %s MHz\n\n",
-		strmhz (buf, imx_get_armclk ()));
-	return 0;
-}
-#endif
-
-int cpu_eth_init (bd_t * bis)
-{
-#if defined(CONFIG_FEC_MXC)
-	struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
-	ulong val;
-
-	val = readl (&ccm->cgr0);
-	val |= (1 << 23);
-	writel (val, &ccm->cgr0);
-	return fecmxc_initialize (bis);
-#else
-	return 0;
-#endif
-}
-
-/*
- * Initializes on-chip MMC controllers.
- * to override, implement board_mmc_init()
- */
-int cpu_mmc_init (bd_t * bis)
-{
-#ifdef CONFIG_MXC_MMC
-	return mxc_mmc_init (bis);
-#else
-	return 0;
-#endif
-}
-
-#ifdef CONFIG_MXC_UART
-void mx25_uart_init_pins (void)
-{
-	struct iomuxc_mux_ctl *muxctl;
-	struct iomuxc_pad_ctl *padctl;
-	u32 inpadctl;
-	u32 outpadctl;
-	u32 muxmode0;
-
-	muxctl = (struct iomuxc_mux_ctl *)IMX_IOPADMUX_BASE;
-	padctl = (struct iomuxc_pad_ctl *)IMX_IOPADCTL_BASE;
-	muxmode0 = MX25_PIN_MUX_MODE (0);
-	/*
-	 * set up input pins with hysteresis and 100K pull-ups
-	 */
-	inpadctl = MX25_PIN_PAD_CTL_HYS
-	    | MX25_PIN_PAD_CTL_PKE
-	    | MX25_PIN_PAD_CTL_PUE | MX25_PIN_PAD_CTL_100K_PU;
-
-	/*
-	 * set up output pins with 100K pull-downs
-	 * FIXME: need to revisit this
-	 *      PUE is ignored if PKE is not set
-	 *      so the right value here is likely
-	 *        0x0 for no pull up/down
-	 *      or
-	 *        0xc0 for 100k pull down
-	 */
-	outpadctl = MX25_PIN_PAD_CTL_PUE | MX25_PIN_PAD_CTL_100K_PD;
-
-	/* UART1 */
-	/* rxd */
-	writel (muxmode0, &muxctl->pad_uart1_rxd);
-	writel (inpadctl, &padctl->pad_uart1_rxd);
-
-	/* txd */
-	writel (muxmode0, &muxctl->pad_uart1_txd);
-	writel (outpadctl, &padctl->pad_uart1_txd);
-
-	/* rts */
-	writel (muxmode0, &muxctl->pad_uart1_rts);
-	writel (outpadctl, &padctl->pad_uart1_rts);
-
-	/* cts */
-	writel (muxmode0, &muxctl->pad_uart1_cts);
-	writel (inpadctl, &padctl->pad_uart1_cts);
-}
-#endif /* CONFIG_MXC_UART */
-
-#ifdef CONFIG_FEC_MXC
-void mx25_fec_init_pins (void)
-{
-	struct iomuxc_mux_ctl *muxctl;
-	struct iomuxc_pad_ctl *padctl;
-	u32 inpadctl_100kpd;
-	u32 inpadctl_22kpu;
-	u32 outpadctl;
-	u32 muxmode0;
-
-	muxctl = (struct iomuxc_mux_ctl *)IMX_IOPADMUX_BASE;
-	padctl = (struct iomuxc_pad_ctl *)IMX_IOPADCTL_BASE;
-	muxmode0 = MX25_PIN_MUX_MODE (0);
-	inpadctl_100kpd = MX25_PIN_PAD_CTL_HYS
-	    | MX25_PIN_PAD_CTL_PKE
-	    | MX25_PIN_PAD_CTL_PUE | MX25_PIN_PAD_CTL_100K_PD;
-	inpadctl_22kpu = MX25_PIN_PAD_CTL_HYS
-	    | MX25_PIN_PAD_CTL_PKE
-	    | MX25_PIN_PAD_CTL_PUE | MX25_PIN_PAD_CTL_22K_PU;
-	/*
-	 * set up output pins with 100K pull-downs
-	 * FIXME: need to revisit this
-	 *      PUE is ignored if PKE is not set
-	 *      so the right value here is likely
-	 *        0x0 for no pull
-	 *      or
-	 *        0xc0 for 100k pull down
-	 */
-	outpadctl = MX25_PIN_PAD_CTL_PUE | MX25_PIN_PAD_CTL_100K_PD;
-
-	/* FEC_TX_CLK */
-	writel (muxmode0, &muxctl->pad_fec_tx_clk);
-	writel (inpadctl_100kpd, &padctl->pad_fec_tx_clk);
-
-	/* FEC_RX_DV */
-	writel (muxmode0, &muxctl->pad_fec_rx_dv);
-	writel (inpadctl_100kpd, &padctl->pad_fec_rx_dv);
-
-	/* FEC_RDATA0 */
-	writel (muxmode0, &muxctl->pad_fec_rdata0);
-	writel (inpadctl_100kpd, &padctl->pad_fec_rdata0);
-
-	/* FEC_TDATA0 */
-	writel (muxmode0, &muxctl->pad_fec_tdata0);
-	writel (outpadctl, &padctl->pad_fec_tdata0);
-
-	/* FEC_TX_EN */
-	writel (muxmode0, &muxctl->pad_fec_tx_en);
-	writel (outpadctl, &padctl->pad_fec_tx_en);
-
-	/* FEC_MDC */
-	writel (muxmode0, &muxctl->pad_fec_mdc);
-	writel (outpadctl, &padctl->pad_fec_mdc);
-
-	/* FEC_MDIO */
-	writel (muxmode0, &muxctl->pad_fec_mdio);
-	writel (inpadctl_22kpu, &padctl->pad_fec_mdio);
-
-	/* FEC_RDATA1 */
-	writel (muxmode0, &muxctl->pad_fec_rdata1);
-	writel (inpadctl_100kpd, &padctl->pad_fec_rdata1);
-
-	/* FEC_TDATA1 */
-	writel (muxmode0, &muxctl->pad_fec_tdata1);
-	writel (outpadctl, &padctl->pad_fec_tdata1);
-
-}
-
-void imx_get_mac_from_fuse(unsigned char *mac)
-{
-	int i;
-	struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
-	struct fuse_bank *bank = &iim->bank[0];
-	struct fuse_bank0_regs *fuse =
-			(struct fuse_bank0_regs *)bank->fuse_regs;
-
-	for (i = 0; i < 6; i++)
-		mac[i] = readl(&fuse->mac_addr[i]) & 0xff;
-}
-#endif /* CONFIG_FEC_MXC */
diff --git a/arch/arm/cpu/arm926ejs/mx25/reset.c b/arch/arm/cpu/arm926ejs/mx25/reset.c
deleted file mode 100644
index 1a43683..0000000
--- a/arch/arm/cpu/arm926ejs/mx25/reset.c
+++ /dev/null
@@ -1,56 +0,0 @@
-/*
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Alex Zuepke <azu@sysgo.de>
- *
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
- *
- * (C) Copyright 2009
- * Ilya Yanok, Emcraft Systems Ltd, <yanok@emcraft.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/imx-regs.h>
-
-/*
- * Reset the cpu by setting up the watchdog timer and let it time out
- */
-void reset_cpu (ulong ignored)
-{
-	struct wdog_regs *regs = (struct wdog_regs *)IMX_WDT_BASE;
-	/* Disable watchdog and set Time-Out field to 0 */
-	writew(0, &regs->wcr);
-
-	/* Write Service Sequence */
-	writew(WSR_UNLOCK1, &regs->wsr);
-	writew(WSR_UNLOCK2, &regs->wsr);
-
-	/* Enable watchdog */
-	writew(WCR_WDE, &regs->wcr);
-
-	while (1) ;
-}
diff --git a/arch/arm/cpu/arm926ejs/mx25/timer.c b/arch/arm/cpu/arm926ejs/mx25/timer.c
deleted file mode 100644
index 14f0c2d..0000000
--- a/arch/arm/cpu/arm926ejs/mx25/timer.c
+++ /dev/null
@@ -1,189 +0,0 @@
-/*
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Alex Zuepke <azu@sysgo.de>
- *
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
- *
- * (C) Copyright 2009
- * Ilya Yanok, Emcraft Systems Ltd, <yanok@emcraft.com>
- *
- * (C) Copyright 2009 DENX Software Engineering
- * Author: John Rigby <jrigby@gmail.com>
- * 	Add support for MX25
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <div64.h>
-#include <asm/io.h>
-#include <asm/arch/imx-regs.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define timestamp gd->tbl
-#define lastinc gd->lastinc
-
-/*
- * "time" is measured in 1 / CONFIG_SYS_HZ seconds,
- * "tick" is internal timer period
- */
-#ifdef CONFIG_MX25_TIMER_HIGH_PRECISION
-/* ~0.4% error - measured with stop-watch on 100s boot-delay */
-static inline unsigned long long tick_to_time(unsigned long long tick)
-{
-	tick *= CONFIG_SYS_HZ;
-	do_div(tick, CONFIG_MX25_CLK32);
-	return tick;
-}
-
-static inline unsigned long long time_to_tick(unsigned long long time)
-{
-	time *= CONFIG_MX25_CLK32;
-	do_div(time, CONFIG_SYS_HZ);
-	return time;
-}
-
-static inline unsigned long long us_to_tick(unsigned long long us)
-{
-	us = us * CONFIG_MX25_CLK32 + 999999;
-	do_div(us, 1000000);
-	return us;
-}
-#else
-/* ~2% error */
-#define TICK_PER_TIME	((CONFIG_MX25_CLK32 + CONFIG_SYS_HZ / 2) / \
-		CONFIG_SYS_HZ)
-#define US_PER_TICK	(1000000 / CONFIG_MX25_CLK32)
-
-static inline unsigned long long tick_to_time(unsigned long long tick)
-{
-	do_div(tick, TICK_PER_TIME);
-	return tick;
-}
-
-static inline unsigned long long time_to_tick(unsigned long long time)
-{
-	return time * TICK_PER_TIME;
-}
-
-static inline unsigned long long us_to_tick(unsigned long long us)
-{
-	us += US_PER_TICK - 1;
-	do_div(us, US_PER_TICK);
-	return us;
-}
-#endif
-
-/* nothing really to do with interrupts, just starts up a counter. */
-/* The 32KHz 32-bit timer overruns in 134217 seconds */
-int timer_init(void)
-{
-	int i;
-	struct gpt_regs *gpt = (struct gpt_regs *)IMX_GPT1_BASE;
-	struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
-
-	/* setup GP Timer 1 */
-	writel(GPT_CTRL_SWR, &gpt->ctrl);
-
-	writel(readl(&ccm->cgr1) | CCM_CGR1_GPT1, &ccm->cgr1);
-
-	for (i = 0; i < 100; i++)
-		writel(0, &gpt->ctrl); /* We have no udelay by now */
-	writel(0, &gpt->pre); /* prescaler = 1 */
-	/* Freerun Mode, 32KHz input */
-	writel(readl(&gpt->ctrl) | GPT_CTRL_CLKSOURCE_32 | GPT_CTRL_FRR,
-			&gpt->ctrl);
-	writel(readl(&gpt->ctrl) | GPT_CTRL_TEN, &gpt->ctrl);
-
-	return 0;
-}
-
-void reset_timer_masked(void)
-{
-	struct gpt_regs *gpt = (struct gpt_regs *)IMX_GPT1_BASE;
-	/* reset time */
-	/* capture current incrementer value time */
-	lastinc = readl(&gpt->counter);
-	timestamp = 0; /* start "advancing" time stamp from 0 */
-}
-
-void reset_timer(void)
-{
-	reset_timer_masked();
-}
-
-unsigned long long get_ticks (void)
-{
-	struct gpt_regs *gpt = (struct gpt_regs *)IMX_GPT1_BASE;
-	ulong now = readl(&gpt->counter); /* current tick value */
-
-	if (now >= lastinc) {
-		/*
-		 * normal mode (non roll)
-		 * move stamp forward with absolut diff ticks
-		 */
-		timestamp += (now - lastinc);
-	} else {
-		/* we have rollover of incrementer */
-		timestamp += (0xFFFFFFFF - lastinc) + now;
-	}
-	lastinc = now;
-	return timestamp;
-}
-
-ulong get_timer_masked (void)
-{
-	/*
-	 * get_ticks() returns a long long (64 bit), it wraps in
-	 * 2^64 / CONFIG_MX25_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~
-	 * 5 * 10^9 days... and get_ticks() * CONFIG_SYS_HZ wraps in
-	 * 5 * 10^6 days - long enough.
-	 */
-	return tick_to_time(get_ticks());
-}
-
-ulong get_timer (ulong base)
-{
-	return get_timer_masked () - base;
-}
-
-void set_timer (ulong t)
-{
-	timestamp = time_to_tick(t);
-}
-
-/* delay x useconds AND preserve advance timstamp value */
-void __udelay (unsigned long usec)
-{
-	unsigned long long tmp;
-	ulong tmo;
-
-	tmo = us_to_tick(usec);
-	tmp = get_ticks() + tmo;	/* get current timestamp */
-
-	while (get_ticks() < tmp)	/* loop till event */
-		 /*NOP*/;
-}
diff --git a/arch/arm/cpu/arm926ejs/mx27/Makefile b/arch/arm/cpu/arm926ejs/mx27/Makefile
deleted file mode 100644
index 0e112b3..0000000
--- a/arch/arm/cpu/arm926ejs/mx27/Makefile
+++ /dev/null
@@ -1,44 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(SOC).o
-
-COBJS	= generic.o reset.o timer.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
-
-all:	$(obj).depend $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/arch/arm/cpu/arm926ejs/mx27/generic.c b/arch/arm/cpu/arm926ejs/mx27/generic.c
deleted file mode 100644
index 27642bf..0000000
--- a/arch/arm/cpu/arm926ejs/mx27/generic.c
+++ /dev/null
@@ -1,364 +0,0 @@
-/*
- *  Copyright (c) 2008 Eric Jarrige <eric.jarrige@armadeus.org>
- *  Copyright (c) 2009 Ilya Yanok <yanok@emcraft.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <div64.h>
-#include <netdev.h>
-#include <asm/io.h>
-#include <asm/arch/imx-regs.h>
-#ifdef CONFIG_MXC_MMC
-#include <asm/arch/mxcmmc.h>
-#endif
-
-/*
- *  get the system pll clock in Hz
- *
- *                  mfi + mfn / (mfd +1)
- *  f = 2 * f_ref * --------------------
- *                        pd + 1
- */
-unsigned int imx_decode_pll(unsigned int pll, unsigned int f_ref)
-{
-	unsigned int mfi = (pll >> 10) & 0xf;
-	unsigned int mfn = pll & 0x3ff;
-	unsigned int mfd = (pll >> 16) & 0x3ff;
-	unsigned int pd =  (pll >> 26) & 0xf;
-
-	mfi = mfi <= 5 ? 5 : mfi;
-
-	return lldiv(2 * (u64)f_ref * (mfi * (mfd + 1) + mfn),
-			(mfd + 1) * (pd + 1));
-}
-
-static ulong clk_in_32k(void)
-{
-	return 1024 * CONFIG_MX27_CLK32;
-}
-
-static ulong clk_in_26m(void)
-{
-	struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
-
-	if (readl(&pll->cscr) & CSCR_OSC26M_DIV1P5) {
-		/* divide by 1.5 */
-		return 26000000 * 2 / 3;
-	} else {
-		return 26000000;
-	}
-}
-
-ulong imx_get_mpllclk(void)
-{
-	struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
-	ulong cscr = readl(&pll->cscr);
-	ulong fref;
-
-	if (cscr & CSCR_MCU_SEL)
-		fref = clk_in_26m();
-	else
-		fref = clk_in_32k();
-
-	return imx_decode_pll(readl(&pll->mpctl0), fref);
-}
-
-ulong imx_get_armclk(void)
-{
-	struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
-	ulong cscr = readl(&pll->cscr);
-	ulong fref = imx_get_mpllclk();
-	ulong div;
-
-	if (!(cscr & CSCR_ARM_SRC_MPLL))
-		fref = lldiv((fref * 2), 3);
-
-	div = ((cscr >> 12) & 0x3) + 1;
-
-	return lldiv(fref, div);
-}
-
-ulong imx_get_ahbclk(void)
-{
-	struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
-	ulong cscr = readl(&pll->cscr);
-	ulong fref = imx_get_mpllclk();
-	ulong div;
-
-	div = ((cscr >> 8) & 0x3) + 1;
-
-	return lldiv(fref * 2, 3 * div);
-}
-
-ulong imx_get_spllclk(void)
-{
-	struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
-	ulong cscr = readl(&pll->cscr);
-	ulong fref;
-
-	if (cscr & CSCR_SP_SEL)
-		fref = clk_in_26m();
-	else
-		fref = clk_in_32k();
-
-	return imx_decode_pll(readl(&pll->spctl0), fref);
-}
-
-static ulong imx_decode_perclk(ulong div)
-{
-	return lldiv((imx_get_mpllclk() * 2), (div * 3));
-}
-
-ulong imx_get_perclk1(void)
-{
-	struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
-
-	return imx_decode_perclk((readl(&pll->pcdr1) & 0x3f) + 1);
-}
-
-ulong imx_get_perclk2(void)
-{
-	struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
-
-	return imx_decode_perclk(((readl(&pll->pcdr1) >> 8) & 0x3f) + 1);
-}
-
-ulong imx_get_perclk3(void)
-{
-	struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
-
-	return imx_decode_perclk(((readl(&pll->pcdr1) >> 16) & 0x3f) + 1);
-}
-
-ulong imx_get_perclk4(void)
-{
-	struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
-
-	return imx_decode_perclk(((readl(&pll->pcdr1) >> 24) & 0x3f) + 1);
-}
-
-#if defined(CONFIG_DISPLAY_CPUINFO)
-int print_cpuinfo (void)
-{
-	char buf[32];
-
-	printf("CPU:   Freescale i.MX27 at %s MHz\n\n",
-			strmhz(buf, imx_get_mpllclk()));
-	return 0;
-}
-#endif
-
-int cpu_eth_init(bd_t *bis)
-{
-#if defined(CONFIG_FEC_MXC)
-	struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
-
-	/* enable FEC clock */
-	writel(readl(&pll->pccr1) | PCCR1_HCLK_FEC, &pll->pccr1);
-	writel(readl(&pll->pccr0) | PCCR0_FEC_EN, &pll->pccr0);
-	return fecmxc_initialize(bis);
-#else
-	return 0;
-#endif
-}
-
-/*
- * Initializes on-chip MMC controllers.
- * to override, implement board_mmc_init()
- */
-int cpu_mmc_init(bd_t *bis)
-{
-#ifdef CONFIG_MXC_MMC
-	return mxc_mmc_init(bis);
-#else
-	return 0;
-#endif
-}
-
-void imx_gpio_mode(int gpio_mode)
-{
-	struct gpio_regs *regs = (struct gpio_regs *)IMX_GPIO_BASE;
-	unsigned int pin = gpio_mode & GPIO_PIN_MASK;
-	unsigned int port = (gpio_mode & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
-	unsigned int ocr = (gpio_mode & GPIO_OCR_MASK) >> GPIO_OCR_SHIFT;
-	unsigned int aout = (gpio_mode & GPIO_AOUT_MASK) >> GPIO_AOUT_SHIFT;
-	unsigned int bout = (gpio_mode & GPIO_BOUT_MASK) >> GPIO_BOUT_SHIFT;
-	unsigned int tmp;
-
-	/* Pullup enable */
-	if (gpio_mode & GPIO_PUEN) {
-		writel(readl(&regs->port[port].puen) | (1 << pin),
-				&regs->port[port].puen);
-	} else {
-		writel(readl(&regs->port[port].puen) & ~(1 << pin),
-				&regs->port[port].puen);
-	}
-
-	/* Data direction */
-	if (gpio_mode & GPIO_OUT) {
-		writel(readl(&regs->port[port].ddir) | 1 << pin,
-				&regs->port[port].ddir);
-	} else {
-		writel(readl(&regs->port[port].ddir) & ~(1 << pin),
-				&regs->port[port].ddir);
-	}
-
-	/* Primary / alternate function */
-	if (gpio_mode & GPIO_AF) {
-		writel(readl(&regs->port[port].gpr) | (1 << pin),
-				&regs->port[port].gpr);
-	} else {
-		writel(readl(&regs->port[port].gpr) & ~(1 << pin),
-				&regs->port[port].gpr);
-	}
-
-	/* use as gpio? */
-	if (!(gpio_mode & (GPIO_PF | GPIO_AF))) {
-		writel(readl(&regs->port[port].gius) | (1 << pin),
-				&regs->port[port].gius);
-	} else {
-		writel(readl(&regs->port[port].gius) & ~(1 << pin),
-				&regs->port[port].gius);
-	}
-
-	/* Output / input configuration */
-	if (pin < 16) {
-		tmp = readl(&regs->port[port].ocr1);
-		tmp &= ~(3 << (pin * 2));
-		tmp |= (ocr << (pin * 2));
-		writel(tmp, &regs->port[port].ocr1);
-
-		writel(readl(&regs->port[port].iconfa1) & ~(3 << (pin * 2)),
-				&regs->port[port].iconfa1);
-		writel(readl(&regs->port[port].iconfa1) | aout << (pin * 2),
-				&regs->port[port].iconfa1);
-		writel(readl(&regs->port[port].iconfb1) & ~(3 << (pin * 2)),
-				&regs->port[port].iconfb1);
-		writel(readl(&regs->port[port].iconfb1) | bout << (pin * 2),
-				&regs->port[port].iconfb1);
-	} else {
-		pin -= 16;
-
-		tmp = readl(&regs->port[port].ocr2);
-		tmp &= ~(3 << (pin * 2));
-		tmp |= (ocr << (pin * 2));
-		writel(tmp, &regs->port[port].ocr2);
-
-		writel(readl(&regs->port[port].iconfa2) & ~(3 << (pin * 2)),
-				&regs->port[port].iconfa2);
-		writel(readl(&regs->port[port].iconfa2) | aout << (pin * 2),
-				&regs->port[port].iconfa2);
-		writel(readl(&regs->port[port].iconfb2) & ~(3 << (pin * 2)),
-				&regs->port[port].iconfb2);
-		writel(readl(&regs->port[port].iconfb2) | bout << (pin * 2),
-				&regs->port[port].iconfb2);
-	}
-}
-
-#ifdef CONFIG_MXC_UART
-void mx27_uart_init_pins(void)
-{
-	int i;
-	unsigned int mode[] = {
-		PE12_PF_UART1_TXD,
-		PE13_PF_UART1_RXD,
-	};
-
-	for (i = 0; i < ARRAY_SIZE(mode); i++)
-		imx_gpio_mode(mode[i]);
-
-}
-#endif /* CONFIG_MXC_UART */
-
-#ifdef CONFIG_FEC_MXC
-void mx27_fec_init_pins(void)
-{
-	int i;
-	unsigned int mode[] = {
-		PD0_AIN_FEC_TXD0,
-		PD1_AIN_FEC_TXD1,
-		PD2_AIN_FEC_TXD2,
-		PD3_AIN_FEC_TXD3,
-		PD4_AOUT_FEC_RX_ER,
-		PD5_AOUT_FEC_RXD1,
-		PD6_AOUT_FEC_RXD2,
-		PD7_AOUT_FEC_RXD3,
-		PD8_AF_FEC_MDIO,
-		PD9_AIN_FEC_MDC | GPIO_PUEN,
-		PD10_AOUT_FEC_CRS,
-		PD11_AOUT_FEC_TX_CLK,
-		PD12_AOUT_FEC_RXD0,
-		PD13_AOUT_FEC_RX_DV,
-		PD14_AOUT_FEC_CLR,
-		PD15_AOUT_FEC_COL,
-		PD16_AIN_FEC_TX_ER,
-		PF23_AIN_FEC_TX_EN,
-	};
-
-	for (i = 0; i < ARRAY_SIZE(mode); i++)
-		imx_gpio_mode(mode[i]);
-}
-
-void imx_get_mac_from_fuse(unsigned char *mac)
-{
-	int i;
-	struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
-	struct fuse_bank *bank = &iim->bank[0];
-	struct fuse_bank0_regs *fuse =
-			(struct fuse_bank0_regs *)bank->fuse_regs;
-
-	for (i = 0; i < 6; i++)
-		mac[6 - 1 - i] = readl(&fuse->mac_addr[i]) & 0xff;
-}
-#endif /* CONFIG_FEC_MXC */
-
-#ifdef CONFIG_MXC_MMC
-void mx27_sd1_init_pins(void)
-{
-	int i;
-	unsigned int mode[] = {
-		PE18_PF_SD1_D0,
-		PE19_PF_SD1_D1,
-		PE20_PF_SD1_D2,
-		PE21_PF_SD1_D3,
-		PE22_PF_SD1_CMD,
-		PE23_PF_SD1_CLK,
-	};
-
-	for (i = 0; i < ARRAY_SIZE(mode); i++)
-		imx_gpio_mode(mode[i]);
-
-}
-
-void mx27_sd2_init_pins(void)
-{
-	int i;
-	unsigned int mode[] = {
-		PB4_PF_SD2_D0,
-		PB5_PF_SD2_D1,
-		PB6_PF_SD2_D2,
-		PB7_PF_SD2_D3,
-		PB8_PF_SD2_CMD,
-		PB9_PF_SD2_CLK,
-	};
-
-	for (i = 0; i < ARRAY_SIZE(mode); i++)
-		imx_gpio_mode(mode[i]);
-
-}
-#endif /* CONFIG_MXC_MMC */
diff --git a/arch/arm/cpu/arm926ejs/mx27/reset.c b/arch/arm/cpu/arm926ejs/mx27/reset.c
deleted file mode 100644
index 6c54eaf..0000000
--- a/arch/arm/cpu/arm926ejs/mx27/reset.c
+++ /dev/null
@@ -1,57 +0,0 @@
-/*
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Alex Zuepke <azu@sysgo.de>
- *
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
- *
- * (C) Copyright 2009
- * Ilya Yanok, Emcraft Systems Ltd, <yanok@emcraft.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/imx-regs.h>
-
-/*
- * Reset the cpu by setting up the watchdog timer and let it time out
- */
-void reset_cpu (ulong ignored)
-{
-	struct wdog_regs *regs = (struct wdog_regs *)IMX_WDT_BASE;
-	/* Disable watchdog and set Time-Out field to 0 */
-	writel(0x00000000, &regs->wcr);
-
-	/* Write Service Sequence */
-	writel(0x00005555, &regs->wsr);
-	writel(0x0000AAAA, &regs->wsr);
-
-	/* Enable watchdog */
-	writel(WCR_WDE, &regs->wcr);
-
-	while (1);
-	/*NOTREACHED*/
-}
diff --git a/arch/arm/cpu/arm926ejs/mx27/timer.c b/arch/arm/cpu/arm926ejs/mx27/timer.c
deleted file mode 100644
index 5c1cf01..0000000
--- a/arch/arm/cpu/arm926ejs/mx27/timer.c
+++ /dev/null
@@ -1,192 +0,0 @@
-/*
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Alex Zuepke <azu@sysgo.de>
- *
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
- *
- * (C) Copyright 2009
- * Ilya Yanok, Emcraft Systems Ltd, <yanok@emcraft.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <div64.h>
-#include <asm/io.h>
-#include <asm/arch/imx-regs.h>
-
-/* General purpose timers bitfields */
-#define GPTCR_SWR		(1 << 15)	/* Software reset	*/
-#define GPTCR_FRR		(1 << 8)	/* Freerun / restart	*/
-#define GPTCR_CLKSOURCE_32	(4 << 1)	/* Clock source		*/
-#define GPTCR_TEN		1		/* Timer enable		*/
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define timestamp gd->tbl
-#define lastinc gd->lastinc
-
-/*
- * "time" is measured in 1 / CONFIG_SYS_HZ seconds,
- * "tick" is internal timer period
- */
-#ifdef CONFIG_MX27_TIMER_HIGH_PRECISION
-/* ~0.4% error - measured with stop-watch on 100s boot-delay */
-static inline unsigned long long tick_to_time(unsigned long long tick)
-{
-	tick *= CONFIG_SYS_HZ;
-	do_div(tick, CONFIG_MX27_CLK32);
-	return tick;
-}
-
-static inline unsigned long long time_to_tick(unsigned long long time)
-{
-	time *= CONFIG_MX27_CLK32;
-	do_div(time, CONFIG_SYS_HZ);
-	return time;
-}
-
-static inline unsigned long long us_to_tick(unsigned long long us)
-{
-	us = us * CONFIG_MX27_CLK32 + 999999;
-	do_div(us, 1000000);
-	return us;
-}
-#else
-/* ~2% error */
-#define TICK_PER_TIME	((CONFIG_MX27_CLK32 + CONFIG_SYS_HZ / 2) / \
-		CONFIG_SYS_HZ)
-#define US_PER_TICK	(1000000 / CONFIG_MX27_CLK32)
-
-static inline unsigned long long tick_to_time(unsigned long long tick)
-{
-	do_div(tick, TICK_PER_TIME);
-	return tick;
-}
-
-static inline unsigned long long time_to_tick(unsigned long long time)
-{
-	return time * TICK_PER_TIME;
-}
-
-static inline unsigned long long us_to_tick(unsigned long long us)
-{
-	us += US_PER_TICK - 1;
-	do_div(us, US_PER_TICK);
-	return us;
-}
-#endif
-
-/* nothing really to do with interrupts, just starts up a counter. */
-/* The 32768Hz 32-bit timer overruns in 131072 seconds */
-int timer_init(void)
-{
-	int i;
-	struct gpt_regs *regs = (struct gpt_regs *)IMX_TIM1_BASE;
-	struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
-
-	/* setup GP Timer 1 */
-	writel(GPTCR_SWR, &regs->gpt_tctl);
-
-	writel(readl(&pll->pccr0) | PCCR0_GPT1_EN, &pll->pccr0);
-	writel(readl(&pll->pccr1) | PCCR1_PERCLK1_EN, &pll->pccr1);
-
-	for (i = 0; i < 100; i++)
-		writel(0, &regs->gpt_tctl); /* We have no udelay by now */
-	writel(0, &regs->gpt_tprer); /* 32Khz */
-	/* Freerun Mode, PERCLK1 input */
-	writel(readl(&regs->gpt_tctl) | GPTCR_CLKSOURCE_32 | GPTCR_FRR,
-			&regs->gpt_tctl);
-	writel(readl(&regs->gpt_tctl) | GPTCR_TEN, &regs->gpt_tctl);
-
-	return 0;
-}
-
-void reset_timer_masked(void)
-{
-	struct gpt_regs *regs = (struct gpt_regs *)IMX_TIM1_BASE;
-	/* reset time */
-	/* capture current incrementer value time */
-	lastinc = readl(&regs->gpt_tcn);
-	timestamp = 0; /* start "advancing" time stamp from 0 */
-}
-
-void reset_timer(void)
-{
-	reset_timer_masked();
-}
-
-unsigned long long get_ticks (void)
-{
-	struct gpt_regs *regs = (struct gpt_regs *)IMX_TIM1_BASE;
-	ulong now = readl(&regs->gpt_tcn); /* current tick value */
-
-	if (now >= lastinc) {
-		/*
-		 * normal mode (non roll)
-		 * move stamp forward with absolut diff ticks
-		 */
-		timestamp += (now - lastinc);
-	} else {
-		/* we have rollover of incrementer */
-		timestamp += (0xFFFFFFFF - lastinc) + now;
-	}
-	lastinc = now;
-	return timestamp;
-}
-
-ulong get_timer_masked (void)
-{
-	/*
-	 * get_ticks() returns a long long (64 bit), it wraps in
-	 * 2^64 / CONFIG_MX27_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~
-	 * 5 * 10^9 days... and get_ticks() * CONFIG_SYS_HZ wraps in
-	 * 5 * 10^6 days - long enough.
-	 */
-	return tick_to_time(get_ticks());
-}
-
-ulong get_timer (ulong base)
-{
-	return get_timer_masked () - base;
-}
-
-void set_timer (ulong t)
-{
-	timestamp = time_to_tick(t);
-}
-
-/* delay x useconds AND preserve advance timstamp value */
-void __udelay (unsigned long usec)
-{
-	unsigned long long tmp;
-	ulong tmo;
-
-	tmo = us_to_tick(usec);
-	tmp = get_ticks() + tmo;	/* get current timestamp */
-
-	while (get_ticks() < tmp)	/* loop till event */
-		 /*NOP*/;
-}
diff --git a/arch/arm/cpu/arm926ejs/nomadik/Makefile b/arch/arm/cpu/arm926ejs/nomadik/Makefile
deleted file mode 100644
index 1c1f58e..0000000
--- a/arch/arm/cpu/arm926ejs/nomadik/Makefile
+++ /dev/null
@@ -1,46 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(SOC).o
-
-COBJS	= timer.o gpio.o
-SOBJS	= reset.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS)) $(addprefix $(obj),$(SOBJS))
-
-all:	$(obj).depend $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/arch/arm/cpu/arm926ejs/nomadik/gpio.c b/arch/arm/cpu/arm926ejs/nomadik/gpio.c
deleted file mode 100644
index 62a375b..0000000
--- a/arch/arm/cpu/arm926ejs/nomadik/gpio.c
+++ /dev/null
@@ -1,99 +0,0 @@
-/*
- * (C) Copyright 2009 Alessandro Rubini
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/gpio.h>
-
-static unsigned long gpio_base[4] = {
-	NOMADIK_GPIO0_BASE,
-	NOMADIK_GPIO1_BASE,
-	NOMADIK_GPIO2_BASE,
-	NOMADIK_GPIO3_BASE
-};
-
-enum gpio_registers {
-	GPIO_DAT =	0x00,		/* data register */
-	GPIO_DATS =	0x04,		/* data set */
-	GPIO_DATC =	0x08,		/* data clear */
-	GPIO_PDIS =	0x0c,		/* pull disable */
-	GPIO_DIR =	0x10,		/* direction */
-	GPIO_DIRS =	0x14,		/* direction set */
-	GPIO_DIRC =	0x18,		/* direction clear */
-	GPIO_AFSLA =	0x20,		/* alternate function select A */
-	GPIO_AFSLB =	0x24,		/* alternate function select B */
-};
-
-static inline unsigned long gpio_to_base(int gpio)
-{
-	return gpio_base[gpio / 32];
-}
-
-static inline u32 gpio_to_bit(int gpio)
-{
-	return 1 << (gpio & 0x1f);
-}
-
-void nmk_gpio_af(int gpio, int alternate_function)
-{
-	unsigned long base = gpio_to_base(gpio);
-	u32 bit = gpio_to_bit(gpio);
-	u32 afunc, bfunc;
-
-	/* alternate function is 0..3, with one bit per register */
-	afunc = readl(base + GPIO_AFSLA) & ~bit;
-	bfunc = readl(base + GPIO_AFSLB) & ~bit;
-	if (alternate_function & 1) afunc |= bit;
-	if (alternate_function & 2) bfunc |= bit;
-	writel(afunc, base + GPIO_AFSLA);
-	writel(bfunc, base + GPIO_AFSLB);
-}
-
-void nmk_gpio_dir(int gpio, int dir)
-{
-	unsigned long base = gpio_to_base(gpio);
-	u32 bit = gpio_to_bit(gpio);
-
-	if (dir)
-		writel(bit, base + GPIO_DIRS);
-	else
-		writel(bit, base + GPIO_DIRC);
-}
-
-void nmk_gpio_set(int gpio, int val)
-{
-	unsigned long base = gpio_to_base(gpio);
-	u32 bit = gpio_to_bit(gpio);
-
-	if (val)
-		writel(bit, base + GPIO_DATS);
-	else
-		writel(bit, base + GPIO_DATC);
-}
-
-int nmk_gpio_get(int gpio)
-{
-	unsigned long base = gpio_to_base(gpio);
-	u32 bit = gpio_to_bit(gpio);
-
-	return readl(base + GPIO_DAT) & bit;
-}
diff --git a/arch/arm/cpu/arm926ejs/nomadik/reset.S b/arch/arm/cpu/arm926ejs/nomadik/reset.S
deleted file mode 100644
index ec95472..0000000
--- a/arch/arm/cpu/arm926ejs/nomadik/reset.S
+++ /dev/null
@@ -1,14 +0,0 @@
-#include <config.h>
-/*
- * Processor reset for Nomadik
- */
-
-	.align 5
-.globl reset_cpu
-reset_cpu:
-	ldr	r0, =NOMADIK_SRC_BASE	/* System and Reset Controller */
-	ldr	r1, =0x1
-	str	r1, [r0, #0x18]
-
-_loop_forever:
-	b	_loop_forever
diff --git a/arch/arm/cpu/arm926ejs/nomadik/timer.c b/arch/arm/cpu/arm926ejs/nomadik/timer.c
deleted file mode 100644
index 1d98ef3..0000000
--- a/arch/arm/cpu/arm926ejs/nomadik/timer.c
+++ /dev/null
@@ -1,79 +0,0 @@
-/*
- * (C) Copyright 2009 Alessandro Rubini
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/mtu.h>
-
-/*
- * The timer is a decrementer, we'll left it free running at 2.4MHz.
- * We have 2.4 ticks per microsecond and an overflow in almost 30min
- */
-#define TIMER_CLOCK		(24 * 100 * 1000)
-#define COUNT_TO_USEC(x)	((x) * 5 / 12)	/* overflows at 6min */
-#define USEC_TO_COUNT(x)	((x) * 12 / 5)	/* overflows at 6min */
-#define TICKS_PER_HZ		(TIMER_CLOCK / CONFIG_SYS_HZ)
-#define TICKS_TO_HZ(x)		((x) / TICKS_PER_HZ)
-
-/* macro to read the decrementing 32 bit timer as an increasing count */
-#define READ_TIMER() (0 - readl(CONFIG_SYS_TIMERBASE + MTU_VAL(0)))
-
-/* Configure a free-running, auto-wrap counter with no prescaler */
-int timer_init(void)
-{
-	writel(MTU_CRn_ENA | MTU_CRn_PRESCALE_1 | MTU_CRn_32BITS,
-	       CONFIG_SYS_TIMERBASE + MTU_CR(0));
-	reset_timer();
-	return 0;
-}
-
-/* Restart counting from 0 */
-void reset_timer(void)
-{
-	ulong val;
-	writel(0, CONFIG_SYS_TIMERBASE + MTU_LR(0));
-	/*
-	 * The load-register isn't really immediate: it changes on clock
-	 * edges, so we must wait for our newly-written value to appear.
-	 * Since we might miss reading 0, wait for any change in value.
-	 */
-	val = READ_TIMER();
-	while (READ_TIMER() == val)
-		;
-}
-
-/* Return how many HZ passed since "base" */
-ulong get_timer(ulong base)
-{
-	return  TICKS_TO_HZ(READ_TIMER()) - base;
-}
-
-/* Delay x useconds */
-void __udelay(unsigned long usec)
-{
-	ulong ini, end;
-
-	ini = READ_TIMER();
-	end = ini + USEC_TO_COUNT(usec);
-	while ((signed)(end - READ_TIMER()) > 0)
-		;
-}
diff --git a/arch/arm/cpu/arm926ejs/omap/Makefile b/arch/arm/cpu/arm926ejs/omap/Makefile
deleted file mode 100644
index 862ca02..0000000
--- a/arch/arm/cpu/arm926ejs/omap/Makefile
+++ /dev/null
@@ -1,47 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(SOC).o
-
-COBJS	= timer.o cpuinfo.o
-SOBJS	= reset.o
-
-SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS) $(SOBJS))
-START	:= $(addprefix $(obj),$(START))
-
-all:	$(obj).depend $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/arch/arm/cpu/arm926ejs/omap/cpuinfo.c b/arch/arm/cpu/arm926ejs/omap/cpuinfo.c
deleted file mode 100644
index 0052dab..0000000
--- a/arch/arm/cpu/arm926ejs/omap/cpuinfo.c
+++ /dev/null
@@ -1,241 +0,0 @@
-/*
- * OMAP1 CPU identification code
- *
- * Copyright (C) 2004 Nokia Corporation
- * Written by Tony Lindgren <tony@atomide.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <common.h>
-#include <command.h>
-
-#if defined(CONFIG_DISPLAY_CPUINFO) && defined(CONFIG_OMAP)
-
-#define omap_readw(x)		*(volatile unsigned short *)(x)
-#define omap_readl(x)		*(volatile unsigned long *)(x)
-
-#define OMAP_DIE_ID_0		0xfffe1800
-#define OMAP_DIE_ID_1		0xfffe1804
-#define OMAP_PRODUCTION_ID_0	0xfffe2000
-#define OMAP_PRODUCTION_ID_1	0xfffe2004
-#define OMAP32_ID_0		0xfffed400
-#define OMAP32_ID_1		0xfffed404
-
-struct omap_id {
-	u16	jtag_id;	/* Used to determine OMAP type */
-	u8	die_rev;	/* Processor revision */
-	u32	omap_id;	/* OMAP revision */
-	u32	type;		/* Cpu id bits [31:08], cpu class bits [07:00] */
-};
-
-/* Register values to detect the OMAP version */
-static struct omap_id omap_ids[] = {
-	{ .jtag_id = 0xb574, .die_rev = 0x2, .omap_id = 0x03310315, .type = 0x03100000},
-	{ .jtag_id = 0x355f, .die_rev = 0x0, .omap_id = 0x03320000, .type = 0x07300100},
-	{ .jtag_id = 0xb55f, .die_rev = 0x0, .omap_id = 0x03320000, .type = 0x07300300},
-	{ .jtag_id = 0xb470, .die_rev = 0x0, .omap_id = 0x03310100, .type = 0x15100000},
-	{ .jtag_id = 0xb576, .die_rev = 0x0, .omap_id = 0x03320000, .type = 0x16100000},
-	{ .jtag_id = 0xb576, .die_rev = 0x2, .omap_id = 0x03320100, .type = 0x16110000},
-	{ .jtag_id = 0xb576, .die_rev = 0x3, .omap_id = 0x03320100, .type = 0x16100c00},
-	{ .jtag_id = 0xb576, .die_rev = 0x0, .omap_id = 0x03320200, .type = 0x16100d00},
-	{ .jtag_id = 0xb613, .die_rev = 0x0, .omap_id = 0x03320300, .type = 0x1610ef00},
-	{ .jtag_id = 0xb613, .die_rev = 0x0, .omap_id = 0x03320300, .type = 0x1610ef00},
-	{ .jtag_id = 0xb576, .die_rev = 0x1, .omap_id = 0x03320100, .type = 0x16110000},
-	{ .jtag_id = 0xb58c, .die_rev = 0x2, .omap_id = 0x03320200, .type = 0x16110b00},
-	{ .jtag_id = 0xb58c, .die_rev = 0x3, .omap_id = 0x03320200, .type = 0x16110c00},
-	{ .jtag_id = 0xb65f, .die_rev = 0x0, .omap_id = 0x03320400, .type = 0x16212300},
-	{ .jtag_id = 0xb65f, .die_rev = 0x1, .omap_id = 0x03320400, .type = 0x16212300},
-	{ .jtag_id = 0xb65f, .die_rev = 0x1, .omap_id = 0x03320500, .type = 0x16212300},
-	{ .jtag_id = 0xb5f7, .die_rev = 0x0, .omap_id = 0x03330000, .type = 0x17100000},
-	{ .jtag_id = 0xb5f7, .die_rev = 0x1, .omap_id = 0x03330100, .type = 0x17100000},
-	{ .jtag_id = 0xb5f7, .die_rev = 0x2, .omap_id = 0x03330100, .type = 0x17100000},
-};
-
-/*
- * Get OMAP type from PROD_ID.
- * 1710 has the PROD_ID in bits 15:00, not in 16:01 as documented in TRM.
- * 1510 PROD_ID is empty, and 1610 PROD_ID does not make sense.
- * Undocumented register in TEST BLOCK is used as fallback; This seems to
- * work on 1510, 1610 & 1710. The official way hopefully will work in future
- * processors.
- */
-static u16 omap_get_jtag_id(void)
-{
-	u32 prod_id, omap_id;
-
-	prod_id = omap_readl(OMAP_PRODUCTION_ID_1);
-	omap_id = omap_readl(OMAP32_ID_1);
-
-	/* Check for unusable OMAP_PRODUCTION_ID_1 on 1611B/5912 and 730 */
-	if (((prod_id >> 20) == 0) || (prod_id == omap_id))
-		prod_id = 0;
-	else
-		prod_id &= 0xffff;
-
-	if (prod_id)
-		return prod_id;
-
-	/* Use OMAP32_ID_1 as fallback */
-	prod_id = ((omap_id >> 12) & 0xffff);
-
-	return prod_id;
-}
-
-/*
- * Get OMAP revision from DIE_REV.
- * Early 1710 processors may have broken OMAP_DIE_ID, it contains PROD_ID.
- * Undocumented register in the TEST BLOCK is used as fallback.
- * REVISIT: This does not seem to work on 1510
- */
-static u8 omap_get_die_rev(void)
-{
-	u32 die_rev;
-
-	die_rev = omap_readl(OMAP_DIE_ID_1);
-
-	/* Check for broken OMAP_DIE_ID on early 1710 */
-	if (((die_rev >> 12) & 0xffff) == omap_get_jtag_id())
-		die_rev = 0;
-
-	die_rev = (die_rev >> 17) & 0xf;
-	if (die_rev)
-		return die_rev;
-
-	die_rev = (omap_readl(OMAP32_ID_1) >> 28) & 0xf;
-
-	return die_rev;
-}
-
-static unsigned long dpll1(void)
-{
-	unsigned short pll_ctl_val = omap_readw(DPLL_CTL_REG);
-	unsigned long rate;
-
-	rate = CONFIG_SYS_CLK_FREQ; /* Base xtal rate */
-	if (pll_ctl_val & 0x10) {
-		/* PLL enabled, apply multiplier and divisor */
-		if (pll_ctl_val & 0xf80)
-			rate *= (pll_ctl_val & 0xf80) >> 7;
-		rate /= ((pll_ctl_val & 0x60) >> 5) + 1;
-	} else {
-		/* PLL disabled, apply bypass divisor */
-		switch (pll_ctl_val & 0xc) {
-		case 0:
-			break;
-		case 0x4:
-			rate /= 2;
-			break;
-		default:
-			rate /= 4;
-			break;
-		}
-	}
-
-	return rate;
-}
-
-static unsigned long armcore(void)
-{
-	unsigned short arm_ckctl = omap_readw(ARM_CKCTL);
-
-	return (dpll1() >> ((arm_ckctl & 0x0030) >> 4));
-}
-
-int print_cpuinfo (void)
-{
-	int i;
-	u16 jtag_id;
-	u8 die_rev;
-	u32 omap_id;
-	u8 cpu_type;
-	u32 system_serial_high;
-	u32 system_serial_low;
-	u32 system_rev = 0;
-
-	jtag_id = omap_get_jtag_id();
-	die_rev = omap_get_die_rev();
-	omap_id = omap_readl(OMAP32_ID_0);
-
-#ifdef DEBUG
-	printf("OMAP_DIE_ID_0: 0x%08x\n", omap_readl(OMAP_DIE_ID_0));
-	printf("OMAP_DIE_ID_1: 0x%08x DIE_REV: %i\n",
-	       omap_readl(OMAP_DIE_ID_1),
-	       (omap_readl(OMAP_DIE_ID_1) >> 17) & 0xf);
-	printf("OMAP_PRODUCTION_ID_0: 0x%08x\n", omap_readl(OMAP_PRODUCTION_ID_0));
-	printf("OMAP_PRODUCTION_ID_1: 0x%08x JTAG_ID: 0x%04x\n",
-	       omap_readl(OMAP_PRODUCTION_ID_1),
-	       omap_readl(OMAP_PRODUCTION_ID_1) & 0xffff);
-	printf("OMAP32_ID_0: 0x%08x\n", omap_readl(OMAP32_ID_0));
-	printf("OMAP32_ID_1: 0x%08x\n", omap_readl(OMAP32_ID_1));
-	printf("JTAG_ID: 0x%04x DIE_REV: %i\n", jtag_id, die_rev);
-#endif
-
-	system_serial_high = omap_readl(OMAP_DIE_ID_0);
-	system_serial_low = omap_readl(OMAP_DIE_ID_1);
-
-	/* First check only the major version in a safe way */
-	for (i = 0; i < ARRAY_SIZE(omap_ids); i++) {
-		if (jtag_id == (omap_ids[i].jtag_id)) {
-			system_rev = omap_ids[i].type;
-			break;
-		}
-	}
-
-	/* Check if we can find the die revision */
-	for (i = 0; i < ARRAY_SIZE(omap_ids); i++) {
-		if (jtag_id == omap_ids[i].jtag_id && die_rev == omap_ids[i].die_rev) {
-			system_rev = omap_ids[i].type;
-			break;
-		}
-	}
-
-	/* Finally check also the omap_id */
-	for (i = 0; i < ARRAY_SIZE(omap_ids); i++) {
-		if (jtag_id == omap_ids[i].jtag_id
-		    && die_rev == omap_ids[i].die_rev
-		    && omap_id == omap_ids[i].omap_id) {
-			system_rev = omap_ids[i].type;
-			break;
-		}
-	}
-
-	/* Add the cpu class info (7xx, 15xx, 16xx, 24xx) */
-	cpu_type = system_rev >> 24;
-
-	switch (cpu_type) {
-	case 0x07:
-		system_rev |= 0x07;
-		break;
-	case 0x03:
-	case 0x15:
-		system_rev |= 0x15;
-		break;
-	case 0x16:
-	case 0x17:
-		system_rev |= 0x16;
-		break;
-	case 0x24:
-		system_rev |= 0x24;
-		break;
-	default:
-		printf("Unknown OMAP cpu type: 0x%02x\n", cpu_type);
-	}
-
-	printf("CPU:   OMAP%04x", system_rev >> 16);
-	if ((system_rev >> 8) & 0xff)
-		printf("%x", (system_rev >> 8) & 0xff);
-#ifdef DEBUG
-	printf(" revision %i handled as %02xxx id: %08x%08x",
-	       die_rev, system_rev & 0xff, system_serial_low, system_serial_high);
-#endif
-	printf(" at %ld.%01ld MHz (DPLL1=%ld.%01ld MHz)\n",
-	       armcore() / 1000000, (armcore() / 100000) % 10,
-	       dpll1() / 1000000, (dpll1() / 100000) % 10);
-
-	return 0;
-}
-
-#endif /* #if defined(CONFIG_DISPLAY_CPUINFO) && defined(CONFIG_OMAP) */
diff --git a/arch/arm/cpu/arm926ejs/omap/reset.S b/arch/arm/cpu/arm926ejs/omap/reset.S
deleted file mode 100644
index 4b20756..0000000
--- a/arch/arm/cpu/arm926ejs/omap/reset.S
+++ /dev/null
@@ -1,45 +0,0 @@
-/*
- *  armboot - Startup Code for ARM926EJS CPU-core
- *
- *  Copyright (c) 2003  Texas Instruments
- *
- *  ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------
- *
- *  Copyright (c) 2001	Marius Gröger <mag@sysgo.de>
- *  Copyright (c) 2002	Alex Züpke <azu@sysgo.de>
- *  Copyright (c) 2002	Gary Jennejohn <garyj@denx.de>
- *  Copyright (c) 2003	Richard Woodruff <r-woodruff2@ti.com>
- *  Copyright (c) 2003	Kshitij <kshitij@ti.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-	.align	5
-.globl reset_cpu
-reset_cpu:
-	ldr	r1, rstctl1	/* get clkm1 reset ctl */
-	mov	r3, #0x0
-	strh	r3, [r1]	/* clear it */
-	mov	r3, #0x8
-	strh	r3, [r1]	/* force dsp+arm reset */
-_loop_forever:
-	b	_loop_forever
-
-rstctl1:
-	.word	0xfffece10
diff --git a/arch/arm/cpu/arm926ejs/omap/timer.c b/arch/arm/cpu/arm926ejs/omap/timer.c
deleted file mode 100644
index 88a0ee6..0000000
--- a/arch/arm/cpu/arm926ejs/omap/timer.c
+++ /dev/null
@@ -1,178 +0,0 @@
-/*
- * (C) Copyright 2003
- * Texas Instruments <www.ti.com>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Alex Zuepke <azu@sysgo.de>
- *
- * (C) Copyright 2002-2004
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * (C) Copyright 2004
- * Philippe Robin, ARM Ltd. <philippe.robin@arm.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-
-#define TIMER_LOAD_VAL 0xffffffff
-
-/* macro to read the 32 bit timer */
-#define READ_TIMER (*(volatile ulong *)(CONFIG_SYS_TIMERBASE+8))
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define timestamp gd->tbl
-#define lastdec gd->lastinc
-
-int timer_init (void)
-{
-	int32_t val;
-
-	/* Start the decrementer ticking down from 0xffffffff */
-	*((int32_t *) (CONFIG_SYS_TIMERBASE + LOAD_TIM)) = TIMER_LOAD_VAL;
-	val = MPUTIM_ST | MPUTIM_AR | MPUTIM_CLOCK_ENABLE | (CONFIG_SYS_PTV << MPUTIM_PTV_BIT);
-	*((int32_t *) (CONFIG_SYS_TIMERBASE + CNTL_TIMER)) = val;
-
-	/* init the timestamp and lastdec value */
-	reset_timer_masked();
-
-	return 0;
-}
-
-/*
- * timer without interrupts
- */
-
-void reset_timer (void)
-{
-	reset_timer_masked ();
-}
-
-ulong get_timer (ulong base)
-{
-	return get_timer_masked () - base;
-}
-
-void set_timer (ulong t)
-{
-	timestamp = t;
-}
-
-/* delay x useconds AND preserve advance timestamp value */
-void __udelay (unsigned long usec)
-{
-	ulong tmo, tmp;
-
-	if(usec >= 1000){		/* if "big" number, spread normalization to seconds */
-		tmo = usec / 1000;	/* start to normalize for usec to ticks per sec */
-		tmo *= CONFIG_SYS_HZ;	/* find number of "ticks" to wait to achieve target */
-		tmo /= 1000;		/* finish normalize. */
-	}else{				/* else small number, don't kill it prior to HZ multiply */
-		tmo = usec * CONFIG_SYS_HZ;
-		tmo /= (1000*1000);
-	}
-
-	tmp = get_timer (0);		/* get current timestamp */
-	if( (tmo + tmp + 1) < tmp )	/* if setting this fordward will roll time stamp */
-		reset_timer_masked ();	/* reset "advancing" timestamp to 0, set lastdec value */
-	else
-		tmo += tmp;		/* else, set advancing stamp wake up time */
-
-	while (get_timer_masked () < tmo)/* loop till event */
-		/*NOP*/;
-}
-
-void reset_timer_masked (void)
-{
-	/* reset time */
-	lastdec = READ_TIMER;  /* capure current decrementer value time */
-	timestamp = 0;	       /* start "advancing" time stamp from 0 */
-}
-
-ulong get_timer_masked (void)
-{
-	ulong now = READ_TIMER;		/* current tick value */
-
-	if (lastdec >= now) {		/* normal mode (non roll) */
-		/* normal mode */
-		timestamp += lastdec - now; /* move stamp fordward with absoulte diff ticks */
-	} else {			/* we have overflow of the count down timer */
-		/* nts = ts + ld + (TLV - now)
-		 * ts=old stamp, ld=time that passed before passing through -1
-		 * (TLV-now) amount of time after passing though -1
-		 * nts = new "advancing time stamp"...it could also roll and cause problems.
-		 */
-		timestamp += lastdec + TIMER_LOAD_VAL - now;
-	}
-	lastdec = now;
-
-	return timestamp;
-}
-
-/* waits specified delay value and resets timestamp */
-void udelay_masked (unsigned long usec)
-{
-	ulong tmo;
-	ulong endtime;
-	signed long diff;
-
-	if (usec >= 1000) {		/* if "big" number, spread normalization to seconds */
-		tmo = usec / 1000;	/* start to normalize for usec to ticks per sec */
-		tmo *= CONFIG_SYS_HZ;		/* find number of "ticks" to wait to achieve target */
-		tmo /= 1000;		/* finish normalize. */
-	} else {			/* else small number, don't kill it prior to HZ multiply */
-		tmo = usec * CONFIG_SYS_HZ;
-		tmo /= (1000*1000);
-	}
-
-	endtime = get_timer_masked () + tmo;
-
-	do {
-		ulong now = get_timer_masked ();
-		diff = endtime - now;
-	} while (diff >= 0);
-}
-
-/*
- * This function is derived from PowerPC code (read timebase as long long).
- * On ARM it just returns the timer value.
- */
-unsigned long long get_ticks(void)
-{
-	return get_timer(0);
-}
-
-/*
- * This function is derived from PowerPC code (timebase clock frequency).
- * On ARM it returns the number of timer ticks per second.
- */
-ulong get_tbclk (void)
-{
-	ulong tbclk;
-
-	tbclk = CONFIG_SYS_HZ;
-	return tbclk;
-}
diff --git a/arch/arm/cpu/arm926ejs/orion5x/Makefile b/arch/arm/cpu/arm926ejs/orion5x/Makefile
deleted file mode 100644
index e5a9994..0000000
--- a/arch/arm/cpu/arm926ejs/orion5x/Makefile
+++ /dev/null
@@ -1,55 +0,0 @@
-#
-# Copyright (C) 2010 Albert ARIBAUD <albert.aribaud@free.fr>
-#
-# Based on original Kirkwood support which is
-# (C) Copyright 2009
-# Marvell Semiconductor <www.marvell.com>
-# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
-# MA 02110-1301 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(SOC).o
-
-COBJS-y	= cpu.o
-COBJS-y	+= dram.o
-COBJS-y	+= timer.o
-
-ifndef CONFIG_SKIP_LOWLEVEL_INIT
-SOBJS	:= lowlevel_init.o
-endif
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS-y))
-
-all:	$(obj).depend $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/arch/arm/cpu/arm926ejs/orion5x/cpu.c b/arch/arm/cpu/arm926ejs/orion5x/cpu.c
deleted file mode 100644
index 1894b52..0000000
--- a/arch/arm/cpu/arm926ejs/orion5x/cpu.c
+++ /dev/null
@@ -1,308 +0,0 @@
-/*
- * Copyright (C) 2010 Albert ARIBAUD <albert.aribaud@free.fr>
- *
- * Based on original Kirkwood support which is
- * (C) Copyright 2009
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-#include <common.h>
-#include <netdev.h>
-#include <asm/cache.h>
-#include <u-boot/md5.h>
-#include <asm/arch/orion5x.h>
-#include <hush.h>
-
-#define BUFLEN	16
-
-void reset_cpu(unsigned long ignored)
-{
-	struct orion5x_cpu_registers *cpureg =
-	    (struct orion5x_cpu_registers *)ORION5X_CPU_REG_BASE;
-
-	writel(readl(&cpureg->rstoutn_mask) | (1 << 2),
-		&cpureg->rstoutn_mask);
-	writel(readl(&cpureg->sys_soft_rst) | 1,
-		&cpureg->sys_soft_rst);
-	while (1)
-		;
-}
-
-/*
- * Compute Window Size field value from size expressed in bytes
- * Used with the Base register to set the address window size and location.
- * Must be programmed from LSB to MSB as sequence of ones followed by
- * sequence of zeros. The number of ones specifies the size of the window in
- * 64 KiB granularity (e.g., a value of 0x00FF specifies 256 = 16 MiB).
- * NOTES:
- * 1) A sizeval equal to 0x0 specifies 4 GiB.
- * 2) A return value of 0x0 specifies 64 KiB.
- */
-unsigned int orion5x_winctrl_calcsize(unsigned int sizeval)
-{
-	/*
-	 * Calculate the number of 64 KiB blocks needed minus one (rounding up).
-	 * For sizeval > 0 this is equivalent to:
-	 * sizeval = (u32) ceil((double) sizeval / 65536.0) - 1
-	 */
-	sizeval = (sizeval - 1) >> 16;
-
-	/*
-	 * Propagate 'one' bits to the right by 'oring' them.
-	 * We need only treat bits 15-0.
-	 */
-	sizeval |= sizeval >> 1;  /* 'Or' bit 15 onto bit 14 */
-	sizeval |= sizeval >> 2;  /* 'Or' bits 15-14 onto bits 13-12 */
-	sizeval |= sizeval >> 4;  /* 'Or' bits 15-12 onto bits 11-8 */
-	sizeval |= sizeval >> 8;  /* 'Or' bits 15-8 onto bits 7-0*/
-
-	return sizeval;
-}
-
-/*
- * orion5x_config_adr_windows - Configure address Windows
- *
- * There are 8 address windows supported by Orion5x Soc to addess different
- * devices. Each window can be configured for size, BAR and remap addr
- * Below configuration is standard for most of the cases
- *
- * If remap function not used, remap_lo must be set as base
- *
- * NOTES:
- *
- * 1) in order to avoid windows with inconsistent control and base values
- *    (which could prevent access to BOOTCS and hence execution from FLASH)
- *    always disable window before writing the base value then reenable it
- *    by writing the control value.
- *
- * 2) in order to avoid losing access to BOOTCS when disabling window 7,
- *    first configure window 6 for BOOTCS, then configure window 7 for BOOTCS,
- *    then configure windows 6 for its own target.
- *
- * Reference Documentation:
- * Mbus-L to Mbus Bridge Registers Configuration.
- * (Sec 25.1 and 25.3 of Datasheet)
- */
-int orion5x_config_adr_windows(void)
-{
-	struct orion5x_win_registers *winregs =
-		(struct orion5x_win_registers *)ORION5X_CPU_WIN_BASE;
-
-/* Disable window 0, configure it for its intended target, enable it. */
-	writel(0, &winregs[0].ctrl);
-	writel(ORION5X_ADR_PCIE_MEM, &winregs[0].base);
-	writel(ORION5X_ADR_PCIE_MEM_REMAP_LO, &winregs[0].remap_lo);
-	writel(ORION5X_ADR_PCIE_MEM_REMAP_HI, &winregs[0].remap_hi);
-	writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_PCIE_MEM,
-		ORION5X_TARGET_PCIE, ORION5X_ATTR_PCIE_MEM,
-		ORION5X_WIN_ENABLE), &winregs[0].ctrl);
-/* Disable window 1, configure it for its intended target, enable it. */
-	writel(0, &winregs[1].ctrl);
-	writel(ORION5X_ADR_PCIE_IO, &winregs[1].base);
-	writel(ORION5X_ADR_PCIE_IO_REMAP_LO, &winregs[1].remap_lo);
-	writel(ORION5X_ADR_PCIE_IO_REMAP_HI, &winregs[1].remap_hi);
-	writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_PCIE_IO,
-		ORION5X_TARGET_PCIE, ORION5X_ATTR_PCIE_IO,
-		ORION5X_WIN_ENABLE), &winregs[1].ctrl);
-/* Disable window 2, configure it for its intended target, enable it. */
-	writel(0, &winregs[2].ctrl);
-	writel(ORION5X_ADR_PCI_MEM, &winregs[2].base);
-	writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_PCI_MEM,
-		ORION5X_TARGET_PCI, ORION5X_ATTR_PCI_MEM,
-		ORION5X_WIN_ENABLE), &winregs[2].ctrl);
-/* Disable window 3, configure it for its intended target, enable it. */
-	writel(0, &winregs[3].ctrl);
-	writel(ORION5X_ADR_PCI_IO, &winregs[3].base);
-	writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_PCI_IO,
-		ORION5X_TARGET_PCI, ORION5X_ATTR_PCI_IO,
-		ORION5X_WIN_ENABLE), &winregs[3].ctrl);
-/* Disable window 4, configure it for its intended target, enable it. */
-	writel(0, &winregs[4].ctrl);
-	writel(ORION5X_ADR_DEV_CS0, &winregs[4].base);
-	writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_DEV_CS0,
-		ORION5X_TARGET_DEVICE, ORION5X_ATTR_DEV_CS0,
-		ORION5X_WIN_ENABLE), &winregs[4].ctrl);
-/* Disable window 5, configure it for its intended target, enable it. */
-	writel(0, &winregs[5].ctrl);
-	writel(ORION5X_ADR_DEV_CS1, &winregs[5].base);
-	writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_DEV_CS1,
-		ORION5X_TARGET_DEVICE, ORION5X_ATTR_DEV_CS1,
-		ORION5X_WIN_ENABLE), &winregs[5].ctrl);
-/* Disable window 6, configure it for FLASH, enable it. */
-	writel(0, &winregs[6].ctrl);
-	writel(ORION5X_ADR_BOOTROM, &winregs[6].base);
-	writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_BOOTROM,
-		ORION5X_TARGET_DEVICE, ORION5X_ATTR_BOOTROM,
-		ORION5X_WIN_ENABLE), &winregs[6].ctrl);
-/* Disable window 7, configure it for FLASH, enable it. */
-	writel(0, &winregs[7].ctrl);
-	writel(ORION5X_ADR_BOOTROM, &winregs[7].base);
-	writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_BOOTROM,
-		ORION5X_TARGET_DEVICE, ORION5X_ATTR_BOOTROM,
-		ORION5X_WIN_ENABLE), &winregs[7].ctrl);
-/* Disable window 6, configure it for its intended target, enable it. */
-	writel(0, &winregs[6].ctrl);
-	writel(ORION5X_ADR_DEV_CS2, &winregs[6].base);
-	writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_DEV_CS2,
-		ORION5X_TARGET_DEVICE, ORION5X_ATTR_DEV_CS2,
-		ORION5X_WIN_ENABLE), &winregs[6].ctrl);
-
-	return 0;
-}
-
-/*
- * Orion5x identification is done through PCIE space.
- */
-
-u32 orion5x_device_id(void)
-{
-	return readl(PCIE_DEV_ID_OFF) >> 16;
-}
-
-u32 orion5x_device_rev(void)
-{
-	return readl(PCIE_DEV_REV_OFF) & 0xff;
-}
-
-#if defined(CONFIG_DISPLAY_CPUINFO)
-
-/* Display device and revision IDs.
- * This function must cover all known device/revision
- * combinations, not only the one for which u-boot is
- * compiled; this way, one can identify actual HW in
- * case of a mismatch.
- */
-int print_cpuinfo(void)
-{
-	char dev_str[] = "0x0000";
-	char rev_str[] = "0x00";
-	char *dev_name = NULL;
-	char *rev_name = NULL;
-
-	u32 dev = orion5x_device_id();
-	u32 rev = orion5x_device_rev();
-
-	if (dev == MV88F5181_DEV_ID) {
-		dev_name = "MV88F5181";
-		if (rev == MV88F5181_REV_B1)
-			rev_name = "B1";
-		else if (rev == MV88F5181L_REV_A1) {
-			dev_name = "MV88F5181L";
-			rev_name = "A1";
-		} else if (rev == MV88F5181L_REV_A0) {
-			dev_name = "MV88F5181L";
-			rev_name = "A0";
-		}
-	} else if (dev == MV88F5182_DEV_ID) {
-		dev_name = "MV88F5182";
-		if (rev == MV88F5182_REV_A2)
-			rev_name = "A2";
-	} else if (dev == MV88F5281_DEV_ID) {
-		dev_name = "MV88F5281";
-		if (rev == MV88F5281_REV_D2)
-			rev_name = "D2";
-		else if (rev == MV88F5281_REV_D1)
-			rev_name = "D1";
-		else if (rev == MV88F5281_REV_D0)
-			rev_name = "D0";
-	} else if (dev == MV88F6183_DEV_ID) {
-		dev_name = "MV88F6183";
-		if (rev == MV88F6183_REV_B0)
-			rev_name = "B0";
-	}
-	if (dev_name == NULL) {
-		sprintf(dev_str, "0x%04x", dev);
-		dev_name = dev_str;
-	}
-	if (rev_name == NULL) {
-		sprintf(rev_str, "0x%02x", rev);
-		rev_name = rev_str;
-	}
-
-	printf("SoC:   Orion5x %s-%s\n", dev_name, rev_name);
-
-	return 0;
-}
-#endif /* CONFIG_DISPLAY_CPUINFO */
-
-#ifdef CONFIG_ARCH_CPU_INIT
-int arch_cpu_init(void)
-{
-	/* Enable and invalidate L2 cache in write through mode */
-	invalidate_l2_cache();
-
-	orion5x_config_adr_windows();
-
-	return 0;
-}
-#endif /* CONFIG_ARCH_CPU_INIT */
-
-/*
- * SOC specific misc init
- */
-#if defined(CONFIG_ARCH_MISC_INIT)
-int arch_misc_init(void)
-{
-	u32 temp;
-
-	/*CPU streaming & write allocate */
-	temp = readfr_extra_feature_reg();
-	temp &= ~(1 << 28);	/* disable wr alloc */
-	writefr_extra_feature_reg(temp);
-
-	temp = readfr_extra_feature_reg();
-	temp &= ~(1 << 29);	/* streaming disabled */
-	writefr_extra_feature_reg(temp);
-
-	/* L2Cache settings */
-	temp = readfr_extra_feature_reg();
-	/* Disable L2C pre fetch - Set bit 24 */
-	temp |= (1 << 24);
-	/* enable L2C - Set bit 22 */
-	temp |= (1 << 22);
-	writefr_extra_feature_reg(temp);
-
-	icache_enable();
-	/* Change reset vector to address 0x0 */
-	temp = get_cr();
-	set_cr(temp & ~CR_V);
-
-	/* Set CPIOs and MPPs - values provided by board
-	   include file */
-	writel(ORION5X_MPP0_7, ORION5X_MPP_BASE+0x00);
-	writel(ORION5X_MPP8_15, ORION5X_MPP_BASE+0x04);
-	writel(ORION5X_MPP16_23, ORION5X_MPP_BASE+0x50);
-	writel(ORION5X_GPIO_OUT_ENABLE, ORION5X_GPIO_BASE+0x04);
-
-	/* initialize timer */
-	timer_init_r();
-	return 0;
-}
-#endif /* CONFIG_ARCH_MISC_INIT */
-
-#ifdef CONFIG_MVGBE
-int cpu_eth_init(bd_t *bis)
-{
-	mvgbe_initialize(bis);
-	return 0;
-}
-#endif
diff --git a/arch/arm/cpu/arm926ejs/orion5x/dram.c b/arch/arm/cpu/arm926ejs/orion5x/dram.c
deleted file mode 100644
index b749282..0000000
--- a/arch/arm/cpu/arm926ejs/orion5x/dram.c
+++ /dev/null
@@ -1,71 +0,0 @@
-/*
- * Copyright (C) 2010 Albert ARIBAUD <albert.aribaud@free.fr>
- *
- * Based on original Kirkwood support which is
- * (C) Copyright 2009
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-#include <common.h>
-#include <config.h>
-#include <asm/arch/orion5x.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*
- * orion5x_sdram_bar - reads SDRAM Base Address Register
- */
-u32 orion5x_sdram_bar(enum memory_bank bank)
-{
-	struct orion5x_ddr_addr_decode_registers *winregs =
-		(struct orion5x_ddr_addr_decode_registers *)
-		ORION5X_CPU_WIN_BASE;
-
-	u32 result = 0;
-	u32 enable = 0x01 & winregs[bank].size;
-
-	if ((!enable) || (bank > BANK3))
-		return 0;
-
-	result = winregs[bank].base;
-	return result;
-}
-int dram_init (void)
-{
-	/* dram_init must store complete ramsize in gd->ram_size */
-	gd->ram_size = get_ram_size(
-			(volatile long *) orion5x_sdram_bar(0),
-			CONFIG_MAX_RAM_BANK_SIZE);
-	return 0;
-}
-
-void dram_init_banksize (void)
-{
-	int i;
-
-	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
-		gd->bd->bi_dram[i].start = orion5x_sdram_bar(i);
-		gd->bd->bi_dram[i].size = get_ram_size(
-			(volatile long *) (gd->bd->bi_dram[i].start),
-			CONFIG_MAX_RAM_BANK_SIZE);
-	}
-}
diff --git a/arch/arm/cpu/arm926ejs/orion5x/lowlevel_init.S b/arch/arm/cpu/arm926ejs/orion5x/lowlevel_init.S
deleted file mode 100644
index 0523bd4..0000000
--- a/arch/arm/cpu/arm926ejs/orion5x/lowlevel_init.S
+++ /dev/null
@@ -1,293 +0,0 @@
-/*
- * Copyright (C) 2010 Albert ARIBAUD <albert.aribaud@free.fr>
- *
- * (C) Copyright 2009
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-#include <config.h>
-#include "asm/arch/orion5x.h"
-
-/*
- * Configuration values for SDRAM access setup
- */
-
-#define SDRAM_CONFIG			0x3148400
-#define SDRAM_MODE			0x62
-#define SDRAM_CONTROL			0x4041000
-#define SDRAM_TIME_CTRL_LOW		0x11602220
-#define SDRAM_TIME_CTRL_HI		0x40c
-#define SDRAM_OPEN_PAGE_EN		0x0
-/* DDR 1 2x 32M NANYA NT5DS16M16CS-6K ==> 64MB */
-#define SDRAM_BANK0_SIZE		0x3ff0001
-#define SDRAM_ADDR_CTRL			0x10
-
-#define SDRAM_OP_NOP			0x05
-#define SDRAM_OP_SETMODE		0x03
-
-#define SDRAM_PAD_CTRL_WR_EN		0x80000000
-#define SDRAM_PAD_CTRL_TUNE_EN		0x00010000
-#define SDRAM_PAD_CTRL_DRVN_MASK	0x0000003f
-#define SDRAM_PAD_CTRL_DRVP_MASK	0x00000fc0
-
-/*
- * For Guideline MEM-3 - Drive Strength value
- */
-
-#define DDR1_PAD_STRENGTH_DEFAULT	0x00001000
-#define SDRAM_PAD_CTRL_DRV_STR_MASK	0x00003000
-
-/*
- * For Guideline MEM-4 - DQS Reference Delay Tuning
- */
-
-#define MSAR_ARMDDRCLCK_MASK		0x000000f0
-#define MSAR_ARMDDRCLCK_H_MASK		0x00000100
-
-#define MSAR_ARMDDRCLCK_333_167		0x00000000
-#define MSAR_ARMDDRCLCK_500_167		0x00000030
-#define MSAR_ARMDDRCLCK_667_167		0x00000060
-#define MSAR_ARMDDRCLCK_400_200_1	0x000001E0
-#define MSAR_ARMDDRCLCK_400_200		0x00000010
-#define MSAR_ARMDDRCLCK_600_200		0x00000050
-#define MSAR_ARMDDRCLCK_800_200		0x00000070
-
-#define FTDLL_DDR1_166MHZ		0x0047F001
-
-#define FTDLL_DDR1_200MHZ		0x0044D001
-
-/*
- * Low-level init happens right after start.S has switched to SVC32,
- * flushed and disabled caches and disabled MMU. We're still running
- * from the boot chip select, so the first thing we should do is set
- * up RAM for us to relocate into.
- */
-
-.globl lowlevel_init
-
-lowlevel_init:
-
-	/* Use 'r4 as the base for internal register accesses */
-	ldr	r4, =ORION5X_REGS_PHY_BASE
-
-	/* move internal registers from the default 0xD0000000
-	 * to their intended location, defined by SoC */
-	ldr	r3, =0xD0000000
-	add	r3, r3, #0x20000
-	str	r4, [r3, #0x80]
-
-	/* Use R3 as the base for DRAM registers */
-	add	r3, r4, #0x01000
-
-	/*DDR SDRAM Initialization Control */
-	ldr	r6, =0x00000001
-	str	r6, [r3, #0x480]
-
-	/* Use R3 as the base for PCI registers */
-	add	r3, r4, #0x31000
-
-	/* Disable arbiter */
-	ldr	r6, =0x00000030
-	str	r6, [r3, #0xd00]
-
-	/* Use R3 as the base for DRAM registers */
-	add	r3, r4, #0x01000
-
-	/* set all dram windows to 0 */
-	mov	r6, #0
-	str	r6, [r3, #0x504]
-	str	r6, [r3, #0x50C]
-	str	r6, [r3, #0x514]
-	str	r6, [r3, #0x51C]
-
-	/* 1) Configure SDRAM  */
-	ldr	r6, =SDRAM_CONFIG
-	str	r6, [r3, #0x400]
-
-	/* 2) Set SDRAM Control reg */
-	ldr	r6, =SDRAM_CONTROL
-	str	r6, [r3, #0x404]
-
-	/* 3) Write SDRAM address control register */
-	ldr	r6, =SDRAM_ADDR_CTRL
-	str	r6, [r3, #0x410]
-
-	/* 4) Write SDRAM bank 0 size register */
-	ldr	r6, =SDRAM_BANK0_SIZE
-	str	r6, [r3, #0x504]
-	/* keep other banks disabled */
-
-	/* 5) Write SDRAM open pages control register */
-	ldr	r6, =SDRAM_OPEN_PAGE_EN
-	str	r6, [r3, #0x414]
-
-	/* 6) Write SDRAM timing Low register */
-	ldr	r6, =SDRAM_TIME_CTRL_LOW
-	str	r6, [r3, #0x408]
-
-	/* 7) Write SDRAM timing High register */
-	ldr	r6, =SDRAM_TIME_CTRL_HI
-	str	r6, [r3, #0x40C]
-
-	/* 8) Write SDRAM mode register */
-	/* The CPU must not attempt to change the SDRAM Mode register setting */
-	/* prior to DRAM controller completion of the DRAM initialization     */
-	/* sequence. To guarantee this restriction, it is recommended that    */
-	/* the CPU sets the SDRAM Operation register to NOP command, performs */
-	/* read polling until the register is back in Normal operation value, */
-	/* and then sets SDRAM Mode register to its new value.		      */
-
-	/* 8.1 write 'nop' to SDRAM operation */
-	ldr	r6, =SDRAM_OP_NOP
-	str	r6, [r3, #0x418]
-
-	/* 8.2 poll SDRAM operation until back in 'normal' mode.  */
-1:
-	ldr	r6, [r3, #0x418]
-	cmp	r6, #0
-	bne	1b
-
-	/* 8.3 Now its safe to write new value to SDRAM Mode register	      */
-	ldr	r6, =SDRAM_MODE
-	str	r6, [r3, #0x41C]
-
-	/* 8.4 Set new mode */
-	ldr	r6, =SDRAM_OP_SETMODE
-	str	r6, [r3, #0x418]
-
-	/* 8.5 poll SDRAM operation until back in 'normal' mode.  */
-2:
-	ldr	r6, [r3, #0x418]
-	cmp	r6, #0
-	bne	2b
-
-	/* DDR SDRAM Address/Control Pads Calibration */
-	ldr	r6, [r3, #0x4C0]
-
-	/* Set Bit [31] to make the register writable			*/
-	orr	r6, r6, #SDRAM_PAD_CTRL_WR_EN
-	str	r6, [r3, #0x4C0]
-
-	bic	r6, r6, #SDRAM_PAD_CTRL_WR_EN
-	bic	r6, r6, #SDRAM_PAD_CTRL_TUNE_EN
-	bic	r6, r6, #SDRAM_PAD_CTRL_DRVN_MASK
-	bic	r6, r6, #SDRAM_PAD_CTRL_DRVP_MASK
-
-	/* Get the final N locked value of driving strength [22:17]	*/
-	mov	r1, r6
-	mov	r1, r1, LSL #9
-	mov	r1, r1, LSR #26	 /* r1[5:0]<DrvN>  = r3[22:17]<LockN>	*/
-	orr	r1, r1, r1, LSL #6 /* r1[11:6]<DrvP> = r1[5:0]<DrvN>	*/
-
-	/* Write to both <DrvN> bits [5:0] and <DrvP> bits [11:6]	*/
-	orr	r6, r6, r1
-	str	r6, [r3, #0x4C0]
-
-	/* DDR SDRAM Data Pads Calibration				*/
-	ldr	r6, [r3, #0x4C4]
-
-	/* Set Bit [31] to make the register writable			*/
-	orr	r6, r6, #SDRAM_PAD_CTRL_WR_EN
-	str	r6, [r3, #0x4C4]
-
-	bic	r6, r6, #SDRAM_PAD_CTRL_WR_EN
-	bic	r6, r6, #SDRAM_PAD_CTRL_TUNE_EN
-	bic	r6, r6, #SDRAM_PAD_CTRL_DRVN_MASK
-	bic	r6, r6, #SDRAM_PAD_CTRL_DRVP_MASK
-
-	/* Get the final N locked value of driving strength [22:17]	*/
-	mov	r1, r6
-	mov	r1, r1, LSL #9
-	mov	r1, r1, LSR #26
-	orr	r1, r1, r1, LSL #6 /* r1[5:0] = r3[22:17]<LockN>	*/
-
-	/* Write to both <DrvN> bits [5:0] and <DrvP> bits [11:6]	*/
-	orr	r6, r6, r1
-
-	str	r6, [r3, #0x4C4]
-
-	/* Implement Guideline (GL# MEM-3) Drive Strength Value		*/
-	/* Relevant for: 88F5181-A1/B0/B1 and 88F5281-A0/B0		*/
-
-	ldr	r1, =DDR1_PAD_STRENGTH_DEFAULT
-
-	/* Enable writes to DDR SDRAM Addr/Ctrl Pads Calibration register */
-	ldr	r6, [r3, #0x4C0]
-	orr	r6, r6, #SDRAM_PAD_CTRL_WR_EN
-	str	r6, [r3, #0x4C0]
-
-	/* Correct strength and disable writes again */
-	bic	r6, r6, #SDRAM_PAD_CTRL_WR_EN
-	bic	r6, r6, #SDRAM_PAD_CTRL_DRV_STR_MASK
-	orr	r6, r6, r1
-	str	r6, [r3, #0x4C0]
-
-	/* Enable writes to DDR SDRAM Data Pads Calibration register */
-	ldr	r6, [r3, #0x4C4]
-	orr	r6, r6, #SDRAM_PAD_CTRL_WR_EN
-	str	r6, [r3, #0x4C4]
-
-	/* Correct strength and disable writes again */
-	bic	r6, r6, #SDRAM_PAD_CTRL_DRV_STR_MASK
-	bic	r6, r6, #SDRAM_PAD_CTRL_WR_EN
-	orr	r6, r6, r1
-	str	r6, [r3, #0x4C4]
-
-	/* Implement Guideline (GL# MEM-4) DQS Reference Delay Tuning	*/
-	/* Relevant for: 88F5181-A1/B0/B1 and 88F5281-A0/B0		*/
-
-	/* Get the "sample on reset" register for the DDR frequancy	*/
-	ldr	r3, =0x10000
-	ldr	r6, [r3, #0x010]
-	ldr	r1, =MSAR_ARMDDRCLCK_MASK
-	and	r1, r6, r1
-
-	ldr	r6, =FTDLL_DDR1_166MHZ
-	cmp	r1, #MSAR_ARMDDRCLCK_333_167
-	beq	3f
-	cmp	r1, #MSAR_ARMDDRCLCK_500_167
-	beq	3f
-	cmp	r1, #MSAR_ARMDDRCLCK_667_167
-	beq	3f
-
-	ldr	r6, =FTDLL_DDR1_200MHZ
-	cmp	r1, #MSAR_ARMDDRCLCK_400_200_1
-	beq	3f
-	cmp	r1, #MSAR_ARMDDRCLCK_400_200
-	beq	3f
-	cmp	r1, #MSAR_ARMDDRCLCK_600_200
-	beq	3f
-	cmp	r1, #MSAR_ARMDDRCLCK_800_200
-	beq	3f
-
-	ldr	r6, =0
-
-3:
-	/* Use R3 as the base for DRAM registers */
-	add	r3, r4, #0x01000
-
-	ldr	r2, [r3, #0x484]
-	orr	r2, r2, r6
-	str	r2, [r3, #0x484]
-
-	/* Return to U-boot via saved link register */
-	mov	pc, lr
diff --git a/arch/arm/cpu/arm926ejs/orion5x/timer.c b/arch/arm/cpu/arm926ejs/orion5x/timer.c
deleted file mode 100644
index bbab226..0000000
--- a/arch/arm/cpu/arm926ejs/orion5x/timer.c
+++ /dev/null
@@ -1,185 +0,0 @@
-/*
-  * Copyright (C) 2010 Albert ARIBAUD <albert.aribaud@free.fr>
- *
- * Based on original Kirkwood support which is
- * Copyright (C) Marvell International Ltd. and its affiliates
- * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-#include <common.h>
-#include <asm/arch/orion5x.h>
-
-#define UBOOT_CNTR	0	/* counter to use for uboot timer */
-
-/* Timer reload and current value registers */
-struct orion5x_tmr_val {
-	u32 reload;	/* Timer reload reg */
-	u32 val;	/* Timer value reg */
-};
-
-/* Timer registers */
-struct orion5x_tmr_registers {
-	u32 ctrl;	/* Timer control reg */
-	u32 pad[3];
-	struct orion5x_tmr_val tmr[2];
-	u32 wdt_reload;
-	u32 wdt_val;
-};
-
-struct orion5x_tmr_registers *orion5x_tmr_regs =
-	(struct orion5x_tmr_registers *)ORION5X_TIMER_BASE;
-
-/*
- * ARM Timers Registers Map
- */
-#define CNTMR_CTRL_REG			(&orion5x_tmr_regs->ctrl)
-#define CNTMR_RELOAD_REG(tmrnum)	(&orion5x_tmr_regs->tmr[tmrnum].reload)
-#define CNTMR_VAL_REG(tmrnum)		(&orion5x_tmr_regs->tmr[tmrnum].val)
-
-/*
- * ARM Timers Control Register
- * CPU_TIMERS_CTRL_REG (CTCR)
- */
-#define CTCR_ARM_TIMER_EN_OFFS(cntr)	(cntr * 2)
-#define CTCR_ARM_TIMER_EN_MASK(cntr)	(1 << CTCR_ARM_TIMER_EN_OFFS)
-#define CTCR_ARM_TIMER_EN(cntr)		(1 << CTCR_ARM_TIMER_EN_OFFS(cntr))
-#define CTCR_ARM_TIMER_DIS(cntr)	(0 << CTCR_ARM_TIMER_EN_OFFS(cntr))
-
-#define CTCR_ARM_TIMER_AUTO_OFFS(cntr)	((cntr * 2) + 1)
-#define CTCR_ARM_TIMER_AUTO_MASK(cntr)	(1 << 1)
-#define CTCR_ARM_TIMER_AUTO_EN(cntr)	(1 << CTCR_ARM_TIMER_AUTO_OFFS(cntr))
-#define CTCR_ARM_TIMER_AUTO_DIS(cntr)	(0 << CTCR_ARM_TIMER_AUTO_OFFS(cntr))
-
-/*
- * ARM Timer\Watchdog Reload Register
- * CNTMR_RELOAD_REG (TRR)
- */
-#define TRG_ARM_TIMER_REL_OFFS		0
-#define TRG_ARM_TIMER_REL_MASK		0xffffffff
-
-/*
- * ARM Timer\Watchdog Register
- * CNTMR_VAL_REG (TVRG)
- */
-#define TVR_ARM_TIMER_OFFS		0
-#define TVR_ARM_TIMER_MASK		0xffffffff
-#define TVR_ARM_TIMER_MAX		0xffffffff
-#define TIMER_LOAD_VAL 			0xffffffff
-
-static inline ulong read_timer(void)
-{
-	return readl(CNTMR_VAL_REG(UBOOT_CNTR))
-	      / (CONFIG_SYS_TCLK / 1000);
-}
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define timestamp gd->tbl
-#define lastdec gd->lastinc
-
-void reset_timer_masked(void)
-{
-	/* reset time */
-	lastdec = read_timer();
-	timestamp = 0;
-}
-
-ulong get_timer_masked(void)
-{
-	ulong now = read_timer();
-
-	if (lastdec >= now) {
-		/* normal mode */
-		timestamp += lastdec - now;
-	} else {
-		/* we have an overflow ... */
-		timestamp += lastdec +
-			(TIMER_LOAD_VAL / (CONFIG_SYS_TCLK / 1000)) - now;
-	}
-	lastdec = now;
-
-	return timestamp;
-}
-
-void reset_timer(void)
-{
-	reset_timer_masked();
-}
-
-ulong get_timer(ulong base)
-{
-	return get_timer_masked() - base;
-}
-
-void set_timer(ulong t)
-{
-	timestamp = t;
-}
-
-static inline ulong uboot_cntr_val(void)
-{
-	return readl(CNTMR_VAL_REG(UBOOT_CNTR));
-}
-
-void __udelay(unsigned long usec)
-{
-	uint current;
-	ulong delayticks;
-
-	current = uboot_cntr_val();
-	delayticks = (usec * (CONFIG_SYS_TCLK / 1000000));
-
-	if (current < delayticks) {
-		delayticks -= current;
-		while (uboot_cntr_val() < current)
-			;
-		while ((TIMER_LOAD_VAL - delayticks) < uboot_cntr_val())
-			;
-	} else {
-		while (uboot_cntr_val() > (current - delayticks))
-			;
-	}
-}
-
-/*
- * init the counter
- */
-int timer_init(void)
-{
-	unsigned int cntmrctrl;
-
-	/* load value into timer */
-	writel(TIMER_LOAD_VAL, CNTMR_RELOAD_REG(UBOOT_CNTR));
-	writel(TIMER_LOAD_VAL, CNTMR_VAL_REG(UBOOT_CNTR));
-
-	/* enable timer in auto reload mode */
-	cntmrctrl = readl(CNTMR_CTRL_REG);
-	cntmrctrl |= CTCR_ARM_TIMER_EN(UBOOT_CNTR);
-	cntmrctrl |= CTCR_ARM_TIMER_AUTO_EN(UBOOT_CNTR);
-	writel(cntmrctrl, CNTMR_CTRL_REG);
-	return 0;
-}
-
-void timer_init_r(void)
-{
-	/* init the timestamp and lastdec value */
-	reset_timer_masked();
-}
diff --git a/arch/arm/cpu/arm926ejs/pantheon/Makefile b/arch/arm/cpu/arm926ejs/pantheon/Makefile
deleted file mode 100644
index ab94985..0000000
--- a/arch/arm/cpu/arm926ejs/pantheon/Makefile
+++ /dev/null
@@ -1,46 +0,0 @@
-#
-# (C) Copyright 2011
-# Marvell Semiconductor <www.marvell.com>
-# Written-by: Lei Wen <leiwen@marvell.com>
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
-# MA 02110-1301 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(SOC).o
-
-COBJS-y	= cpu.o timer.o dram.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS-y))
-
-all:	$(obj).depend $(LIB)
-
-$(LIB):	$(OBJS)
-	$(AR) $(ARFLAGS) $@ $(OBJS)
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/arch/arm/cpu/arm926ejs/pantheon/cpu.c b/arch/arm/cpu/arm926ejs/pantheon/cpu.c
deleted file mode 100644
index 9ddc77c..0000000
--- a/arch/arm/cpu/arm926ejs/pantheon/cpu.c
+++ /dev/null
@@ -1,78 +0,0 @@
-/*
- * (C) Copyright 2011
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Lei Wen <leiwen@marvell.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-#include <common.h>
-#include <asm/arch/pantheon.h>
-#include <asm/io.h>
-
-#define UARTCLK14745KHZ	(APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(1))
-#define SET_MRVL_ID	(1<<8)
-#define L2C_RAM_SEL	(1<<4)
-
-int arch_cpu_init(void)
-{
-	u32 val;
-	struct panthcpu_registers *cpuregs =
-		(struct panthcpu_registers*) PANTHEON_CPU_BASE;
-
-	struct panthapb_registers *apbclkres =
-		(struct panthapb_registers*) PANTHEON_APBC_BASE;
-
-	struct panthmpmu_registers *mpmu =
-		(struct panthmpmu_registers*) PANTHEON_MPMU_BASE;
-
-	/* set SEL_MRVL_ID bit in PANTHEON_CPU_CONF register */
-	val = readl(&cpuregs->cpu_conf);
-	val = val | SET_MRVL_ID;
-	writel(val, &cpuregs->cpu_conf);
-
-	/* Turn on clock gating (PMUM_CCGR) */
-	writel(0xFFFFFFFF, &mpmu->ccgr);
-
-	/* Turn on clock gating (PMUM_ACGR) */
-	writel(0xFFFFFFFF, &mpmu->acgr);
-
-	/* Turn on uart2 clock */
-	writel(UARTCLK14745KHZ, &apbclkres->uart0);
-
-	/* Enable GPIO clock */
-	writel(APBC_APBCLK, &apbclkres->gpio);
-
-	icache_enable();
-
-	return 0;
-}
-
-#if defined(CONFIG_DISPLAY_CPUINFO)
-int print_cpuinfo(void)
-{
-	u32 id;
-	struct panthcpu_registers *cpuregs =
-		(struct panthcpu_registers*) PANTHEON_CPU_BASE;
-
-	id = readl(&cpuregs->chip_id);
-	printf("SoC:   PANTHEON 88AP%X-%X\n", (id & 0xFFF), (id >> 0x10));
-	return 0;
-}
-#endif
diff --git a/arch/arm/cpu/arm926ejs/pantheon/dram.c b/arch/arm/cpu/arm926ejs/pantheon/dram.c
deleted file mode 100644
index bbca7ee..0000000
--- a/arch/arm/cpu/arm926ejs/pantheon/dram.c
+++ /dev/null
@@ -1,132 +0,0 @@
-/*
- * (C) Copyright 2011
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Lei Wen <leiwen@marvell.com>,
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-#include <common.h>
-#include <asm/arch/pantheon.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*
- * Pantheon DRAM controller supports upto 8 banks
- * for chip select 0 and 1
- */
-
-/*
- * DDR Memory Control Registers
- * Refer Datasheet 4.4
- */
-struct panthddr_map_registers {
-	u32	cs;	/* Memory Address Map Register -CS */
-	u32	pad[3];
-};
-
-struct panthddr_registers {
-	u8	pad[0x100 - 0x000];
-	struct panthddr_map_registers mmap[2];
-};
-
-/*
- * panth_sdram_base - reads SDRAM Base Address Register
- */
-u32 panth_sdram_base(int chip_sel)
-{
-	struct panthddr_registers *ddr_regs =
-		(struct panthddr_registers *)PANTHEON_DRAM_BASE;
-	u32 result = 0;
-	u32 CS_valid = 0x01 & readl(&ddr_regs->mmap[chip_sel].cs);
-
-	if (!CS_valid)
-		return 0;
-
-	result = readl(&ddr_regs->mmap[chip_sel].cs) & 0xFF800000;
-	return result;
-}
-
-/*
- * panth_sdram_size - reads SDRAM size
- */
-u32 panth_sdram_size(int chip_sel)
-{
-	struct panthddr_registers *ddr_regs =
-		(struct panthddr_registers *)PANTHEON_DRAM_BASE;
-	u32 result = 0;
-	u32 CS_valid = 0x01 & readl(&ddr_regs->mmap[chip_sel].cs);
-
-	if (!CS_valid)
-		return 0;
-
-	result = readl(&ddr_regs->mmap[chip_sel].cs);
-	result = (result >> 16) & 0xF;
-	if (result < 0x7) {
-		printf("Unknown DRAM Size\n");
-		return -1;
-	} else {
-		return ((0x8 << (result - 0x7)) * 1024 * 1024);
-	}
-}
-
-#ifndef CONFIG_SYS_BOARD_DRAM_INIT
-int dram_init(void)
-{
-	int i;
-
-	gd->ram_size = 0;
-	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
-		gd->bd->bi_dram[i].start = panth_sdram_base(i);
-		gd->bd->bi_dram[i].size = panth_sdram_size(i);
-		/*
-		 * It is assumed that all memory banks are consecutive
-		 * and without gaps.
-		 * If the gap is found, ram_size will be reported for
-		 * consecutive memory only
-		 */
-		if (gd->bd->bi_dram[i].start != gd->ram_size)
-			break;
-
-		gd->ram_size += gd->bd->bi_dram[i].size;
-
-	}
-
-	for (; i < CONFIG_NR_DRAM_BANKS; i++) {
-		/*
-		 * If above loop terminated prematurely, we need to set
-		 * remaining banks' start address & size as 0. Otherwise other
-		 * u-boot functions and Linux kernel gets wrong values which
-		 * could result in crash
-		 */
-		gd->bd->bi_dram[i].start = 0;
-		gd->bd->bi_dram[i].size = 0;
-	}
-	return 0;
-}
-
-/*
- * If this function is not defined here,
- * board.c alters dram bank zero configuration defined above.
- */
-void dram_init_banksize(void)
-{
-	dram_init();
-}
-#endif /* CONFIG_SYS_BOARD_DRAM_INIT */
diff --git a/arch/arm/cpu/arm926ejs/pantheon/timer.c b/arch/arm/cpu/arm926ejs/pantheon/timer.c
deleted file mode 100644
index ca7f7f0..0000000
--- a/arch/arm/cpu/arm926ejs/pantheon/timer.c
+++ /dev/null
@@ -1,214 +0,0 @@
-/*
- * (C) Copyright 2011
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Lei Wen <leiwen@marvell.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-#include <common.h>
-#include <asm/arch/pantheon.h>
-
-/*
- * Timer registers
- * Refer 6.2.9 in Datasheet
- */
-struct panthtmr_registers {
-	u32 clk_ctrl;	/* Timer clk control reg */
-	u32 match[9];	/* Timer match registers */
-	u32 count[3];	/* Timer count registers */
-	u32 status[3];
-	u32 ie[3];
-	u32 preload[3];	/* Timer preload value */
-	u32 preload_ctrl[3];
-	u32 wdt_match_en;
-	u32 wdt_match_r;
-	u32 wdt_val;
-	u32 wdt_sts;
-	u32 icr[3];
-	u32 wdt_icr;
-	u32 cer;	/* Timer count enable reg */
-	u32 cmr;
-	u32 ilr[3];
-	u32 wcr;
-	u32 wfar;
-	u32 wsar;
-	u32 cvwr[3];
-};
-
-#define TIMER			0	/* Use TIMER 0 */
-/* Each timer has 3 match registers */
-#define MATCH_CMP(x)		((3 * TIMER) + x)
-#define TIMER_LOAD_VAL 		0xffffffff
-#define	COUNT_RD_REQ		0x1
-
-DECLARE_GLOBAL_DATA_PTR;
-/* Using gd->tbu from timestamp and gd->tbl for lastdec */
-
-/*
- * For preventing risk of instability in reading counter value,
- * first set read request to register cvwr and then read same
- * register after it captures counter value.
- */
-ulong read_timer(void)
-{
-	struct panthtmr_registers *panthtimers =
-		(struct panthtmr_registers *) PANTHEON_TIMER_BASE;
-	volatile int loop=100;
-	ulong val;
-
-	writel(COUNT_RD_REQ, &panthtimers->cvwr);
-	while (loop--)
-		val = readl(&panthtimers->cvwr);
-
-	/*
-	 * This stop gcc complain and prevent loop mistake init to 0
-	 */
-	val = readl(&panthtimers->cvwr);
-
-	return val;
-}
-
-void reset_timer_masked(void)
-{
-	/* reset time */
-	gd->tbl = read_timer();
-	gd->tbu = 0;
-}
-
-ulong get_timer_masked(void)
-{
-	ulong now = read_timer();
-
-	if (now >= gd->tbl) {
-		/* normal mode */
-		gd->tbu += now - gd->tbl;
-	} else {
-		/* we have an overflow ... */
-		gd->tbu += now + TIMER_LOAD_VAL - gd->tbl;
-	}
-	gd->tbl = now;
-
-	return gd->tbu;
-}
-
-void reset_timer(void)
-{
-	reset_timer_masked();
-}
-
-ulong get_timer(ulong base)
-{
-	return ((get_timer_masked() / (CONFIG_SYS_HZ_CLOCK / 1000)) -
-		base);
-}
-
-void set_timer(ulong t)
-{
-	gd->tbu = t;
-}
-
-void __udelay(unsigned long usec)
-{
-	ulong delayticks;
-	ulong endtime;
-
-	delayticks = (usec * (CONFIG_SYS_HZ_CLOCK / 1000000));
-	endtime = get_timer_masked() + delayticks;
-
-	while (get_timer_masked() < endtime)
-		;
-}
-
-/*
- * init the Timer
- */
-int timer_init(void)
-{
-	struct panthapb_registers *apb1clkres =
-		(struct panthapb_registers *) PANTHEON_APBC_BASE;
-	struct panthtmr_registers *panthtimers =
-		(struct panthtmr_registers *) PANTHEON_TIMER_BASE;
-
-	/* Enable Timer clock at 3.25 MHZ */
-	writel(APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(3), &apb1clkres->timers);
-
-	/* load value into timer */
-	writel(0x0, &panthtimers->clk_ctrl);
-	/* Use Timer 0 Match Resiger 0 */
-	writel(TIMER_LOAD_VAL, &panthtimers->match[MATCH_CMP(0)]);
-	/* Preload value is 0 */
-	writel(0x0, &panthtimers->preload[TIMER]);
-	/* Enable match comparator 0 for Timer 0 */
-	writel(0x1, &panthtimers->preload_ctrl[TIMER]);
-
-	/* Enable timer 0 */
-	writel(0x1, &panthtimers->cer);
-	/* init the gd->tbu and gd->tbl value */
-	reset_timer_masked();
-
-	return 0;
-}
-
-#define MPMU_APRR_WDTR	(1<<4)
-#define TMR_WFAR	0xbaba	/* WDT Register First key */
-#define TMP_WSAR	0xeb10	/* WDT Register Second key */
-
-/*
- * This function uses internal Watchdog Timer
- * based reset mechanism.
- * Steps to write watchdog registers (protected access)
- * 1. Write key value to TMR_WFAR reg.
- * 2. Write key value to TMP_WSAR reg.
- * 3. Perform write operation.
- */
-void reset_cpu (unsigned long ignored)
-{
-	struct panthmpmu_registers *mpmu =
-		(struct panthmpmu_registers *) PANTHEON_MPMU_BASE;
-	struct panthtmr_registers *panthtimers =
-		(struct panthtmr_registers *) PANTHEON_WD_TIMER_BASE;
-	u32 val;
-
-	/* negate hardware reset to the WDT after system reset */
-	val = readl(&mpmu->aprr);
-	val = val | MPMU_APRR_WDTR;
-	writel(val, &mpmu->aprr);
-
-	/* reset/enable WDT clock */
-	writel(APBC_APBCLK, &mpmu->wdtpcr);
-
-	/* clear previous WDT status */
-	writel(TMR_WFAR, &panthtimers->wfar);
-	writel(TMP_WSAR, &panthtimers->wsar);
-	writel(0, &panthtimers->wdt_sts);
-
-	/* set match counter */
-	writel(TMR_WFAR, &panthtimers->wfar);
-	writel(TMP_WSAR, &panthtimers->wsar);
-	writel(0xf, &panthtimers->wdt_match_r);
-
-	/* enable WDT reset */
-	writel(TMR_WFAR, &panthtimers->wfar);
-	writel(TMP_WSAR, &panthtimers->wsar);
-	writel(0x3, &panthtimers->wdt_match_en);
-
-	/*enable functional WDT clock */
-	writel(APBC_APBCLK | APBC_FNCLK, &mpmu->wdtpcr);
-}
diff --git a/arch/arm/cpu/arm926ejs/spear/Makefile b/arch/arm/cpu/arm926ejs/spear/Makefile
deleted file mode 100644
index 1cbff43..0000000
--- a/arch/arm/cpu/arm926ejs/spear/Makefile
+++ /dev/null
@@ -1,52 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(SOC).o
-
-COBJS	:= reset.o \
-	   timer.o
-SOBJS	:=
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-clean:
-	rm -f $(SOBJS) $(OBJS)
-
-distclean:	clean
-	rm -f $(LIB) core *.bak $(obj).depend
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/arch/arm/cpu/arm926ejs/spear/reset.c b/arch/arm/cpu/arm926ejs/spear/reset.c
deleted file mode 100644
index 73ad86d..0000000
--- a/arch/arm/cpu/arm926ejs/spear/reset.c
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * (C) Copyright 2009
- * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/spr_syscntl.h>
-
-void reset_cpu(ulong ignored)
-{
-	struct syscntl_regs *syscntl_regs_p =
-	    (struct syscntl_regs *)CONFIG_SPEAR_SYSCNTLBASE;
-
-	printf("System is going to reboot ...\n");
-
-	/*
-	 * This 1 second delay will allow the above message
-	 * to be printed before reset
-	 */
-	udelay((1000 * 1000));
-
-	/* Going into slow mode before resetting SOC */
-	writel(0x02, &syscntl_regs_p->scctrl);
-
-	/*
-	 * Writing any value to the system status register will
-	 * reset the SoC
-	 */
-	writel(0x00, &syscntl_regs_p->scsysstat);
-
-	/* system will restart */
-	while (1)
-		;
-}
diff --git a/arch/arm/cpu/arm926ejs/spear/timer.c b/arch/arm/cpu/arm926ejs/spear/timer.c
deleted file mode 100644
index 66cf4de..0000000
--- a/arch/arm/cpu/arm926ejs/spear/timer.c
+++ /dev/null
@@ -1,155 +0,0 @@
-/*
- * (C) Copyright 2009
- * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/spr_gpt.h>
-#include <asm/arch/spr_misc.h>
-
-#define GPT_RESOLUTION	(CONFIG_SPEAR_HZ_CLOCK / CONFIG_SPEAR_HZ)
-#define READ_TIMER()	(readl(&gpt_regs_p->count) & GPT_FREE_RUNNING)
-
-static struct gpt_regs *const gpt_regs_p =
-    (struct gpt_regs *)CONFIG_SPEAR_TIMERBASE;
-
-static struct misc_regs *const misc_regs_p =
-    (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define timestamp gd->tbl
-#define lastdec gd->lastinc
-
-int timer_init(void)
-{
-	u32 synth;
-
-	/* Prescaler setting */
-#if defined(CONFIG_SPEAR3XX)
-	writel(MISC_PRSC_CFG, &misc_regs_p->prsc2_clk_cfg);
-	synth = MISC_GPT4SYNTH;
-#elif defined(CONFIG_SPEAR600)
-	writel(MISC_PRSC_CFG, &misc_regs_p->prsc1_clk_cfg);
-	synth = MISC_GPT3SYNTH;
-#else
-# error Incorrect config. Can only be spear{600|300|310|320}
-#endif
-
-	writel(readl(&misc_regs_p->periph_clk_cfg) | synth,
-	       &misc_regs_p->periph_clk_cfg);
-
-	/* disable timers */
-	writel(GPT_PRESCALER_1 | GPT_MODE_AUTO_RELOAD, &gpt_regs_p->control);
-
-	/* load value for free running */
-	writel(GPT_FREE_RUNNING, &gpt_regs_p->compare);
-
-	/* auto reload, start timer */
-	writel(readl(&gpt_regs_p->control) | GPT_ENABLE, &gpt_regs_p->control);
-
-	reset_timer_masked();
-
-	return 0;
-}
-
-/*
- * timer without interrupts
- */
-
-void reset_timer(void)
-{
-	reset_timer_masked();
-}
-
-ulong get_timer(ulong base)
-{
-	return (get_timer_masked() / GPT_RESOLUTION) - base;
-}
-
-void set_timer(ulong t)
-{
-	timestamp = t;
-}
-
-void __udelay(unsigned long usec)
-{
-	ulong tmo;
-	ulong start = get_timer_masked();
-	ulong tenudelcnt = CONFIG_SPEAR_HZ_CLOCK / (1000 * 100);
-	ulong rndoff;
-
-	rndoff = (usec % 10) ? 1 : 0;
-
-	/* tenudelcnt timer tick gives 10 microsecconds delay */
-	tmo = ((usec / 10) + rndoff) * tenudelcnt;
-
-	while ((ulong) (get_timer_masked() - start) < tmo)
-		;
-}
-
-void reset_timer_masked(void)
-{
-	/* reset time */
-	lastdec = READ_TIMER();
-	timestamp = 0;
-}
-
-ulong get_timer_masked(void)
-{
-	ulong now = READ_TIMER();
-
-	if (now >= lastdec) {
-		/* normal mode */
-		timestamp += now - lastdec;
-	} else {
-		/* we have an overflow ... */
-		timestamp += now + GPT_FREE_RUNNING - lastdec;
-	}
-	lastdec = now;
-
-	return timestamp;
-}
-
-void udelay_masked(unsigned long usec)
-{
-	return udelay(usec);
-}
-
-/*
- * This function is derived from PowerPC code (read timebase as long long).
- * On ARM it just returns the timer value.
- */
-unsigned long long get_ticks(void)
-{
-	return get_timer(0);
-}
-
-/*
- * This function is derived from PowerPC code (timebase clock frequency).
- * On ARM it returns the number of timer ticks per second.
- */
-ulong get_tbclk(void)
-{
-	return CONFIG_SPEAR_HZ;
-}
diff --git a/arch/arm/cpu/arm926ejs/start.S b/arch/arm/cpu/arm926ejs/start.S
deleted file mode 100644
index f4c177e..0000000
--- a/arch/arm/cpu/arm926ejs/start.S
+++ /dev/null
@@ -1,513 +0,0 @@
-/*
- *  armboot - Startup Code for ARM926EJS CPU-core
- *
- *  Copyright (c) 2003  Texas Instruments
- *
- *  ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------
- *
- *  Copyright (c) 2001	Marius Gröger <mag@sysgo.de>
- *  Copyright (c) 2002	Alex Züpke <azu@sysgo.de>
- *  Copyright (c) 2002	Gary Jennejohn <garyj@denx.de>
- *  Copyright (c) 2003	Richard Woodruff <r-woodruff2@ti.com>
- *  Copyright (c) 2003	Kshitij <kshitij@ti.com>
- *  Copyright (c) 2010	Albert Aribaud <albert.aribaud@free.fr>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <asm-offsets.h>
-#include <config.h>
-#include <common.h>
-#include <version.h>
-
-#if defined(CONFIG_OMAP1610)
-#include <./configs/omap1510.h>
-#elif defined(CONFIG_OMAP730)
-#include <./configs/omap730.h>
-#endif
-
-/*
- *************************************************************************
- *
- * Jump vector table as in table 3.1 in [1]
- *
- *************************************************************************
- */
-
-
-.globl _start
-_start:
-	b	reset
-#ifdef CONFIG_PRELOADER
-/* No exception handlers in preloader */
-	ldr	pc, _hang
-	ldr	pc, _hang
-	ldr	pc, _hang
-	ldr	pc, _hang
-	ldr	pc, _hang
-	ldr	pc, _hang
-	ldr	pc, _hang
-
-_hang:
-	.word	do_hang
-/* pad to 64 byte boundary */
-	.word	0x12345678
-	.word	0x12345678
-	.word	0x12345678
-	.word	0x12345678
-	.word	0x12345678
-	.word	0x12345678
-	.word	0x12345678
-#else
-	ldr	pc, _undefined_instruction
-	ldr	pc, _software_interrupt
-	ldr	pc, _prefetch_abort
-	ldr	pc, _data_abort
-	ldr	pc, _not_used
-	ldr	pc, _irq
-	ldr	pc, _fiq
-
-_undefined_instruction:
-	.word undefined_instruction
-_software_interrupt:
-	.word software_interrupt
-_prefetch_abort:
-	.word prefetch_abort
-_data_abort:
-	.word data_abort
-_not_used:
-	.word not_used
-_irq:
-	.word irq
-_fiq:
-	.word fiq
-
-#endif	/* CONFIG_PRELOADER */
-	.balignl 16,0xdeadbeef
-
-
-/*
- *************************************************************************
- *
- * Startup Code (reset vector)
- *
- * do important init only if we don't start from memory!
- * setup Memory and board specific bits prior to relocation.
- * relocate armboot to ram
- * setup stack
- *
- *************************************************************************
- */
-
-.globl _TEXT_BASE
-_TEXT_BASE:
-	.word	CONFIG_SYS_TEXT_BASE
-
-/*
- * These are defined in the board-specific linker script.
- * Subtracting _start from them lets the linker put their
- * relative position in the executable instead of leaving
- * them null.
- */
-.globl _bss_start_ofs
-_bss_start_ofs:
-	.word __bss_start - _start
-
-.globl _bss_end_ofs
-_bss_end_ofs:
-	.word _end - _start
-
-#ifdef CONFIG_USE_IRQ
-/* IRQ stack memory (calculated at run-time) */
-.globl IRQ_STACK_START
-IRQ_STACK_START:
-	.word	0x0badc0de
-
-/* IRQ stack memory (calculated at run-time) */
-.globl FIQ_STACK_START
-FIQ_STACK_START:
-	.word 0x0badc0de
-#endif
-
-/* IRQ stack memory (calculated at run-time) + 8 bytes */
-.globl IRQ_STACK_START_IN
-IRQ_STACK_START_IN:
-	.word	0x0badc0de
-
-/*
- * the actual reset code
- */
-
-reset:
-	/*
-	 * set the cpu to SVC32 mode
-	 */
-	mrs	r0,cpsr
-	bic	r0,r0,#0x1f
-	orr	r0,r0,#0xd3
-	msr	cpsr,r0
-
-	/*
-	 * we do sys-critical inits only at reboot,
-	 * not when booting from ram!
-	 */
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
-	bl	cpu_init_crit
-#endif
-
-/* Set stackpointer in internal RAM to call board_init_f */
-call_board_init_f:
-	ldr	sp, =(CONFIG_SYS_INIT_SP_ADDR)
-	bic	sp, sp, #7 /* 8-byte alignment for ABI compliance */
-	ldr	r0,=0x00000000
-	bl	board_init_f
-
-/*------------------------------------------------------------------------------*/
-
-/*
- * void relocate_code (addr_sp, gd, addr_moni)
- *
- * This "function" does not return, instead it continues in RAM
- * after relocating the monitor code.
- *
- */
-	.globl	relocate_code
-relocate_code:
-	mov	r4, r0	/* save addr_sp */
-	mov	r5, r1	/* save addr of gd */
-	mov	r6, r2	/* save addr of destination */
-
-	/* Set up the stack						    */
-stack_setup:
-	mov	sp, r4
-
-	adr	r0, _start
-	cmp	r0, r6
-	beq	clear_bss		/* skip relocation */
-	mov	r1, r6			/* r1 <- scratch for copy loop */
-	ldr	r3, _bss_start_ofs
-	add	r2, r0, r3		/* r2 <- source end address	    */
-
-copy_loop:
-	ldmia	r0!, {r9-r10}		/* copy from source address [r0]    */
-	stmia	r1!, {r9-r10}		/* copy to   target address [r1]    */
-	cmp	r0, r2			/* until source end address [r2]    */
-	blo	copy_loop
-
-#ifndef CONFIG_PRELOADER
-	/*
-	 * fix .rel.dyn relocations
-	 */
-	ldr	r0, _TEXT_BASE		/* r0 <- Text base */
-	sub	r9, r6, r0		/* r9 <- relocation offset */
-	ldr	r10, _dynsym_start_ofs	/* r10 <- sym table ofs */
-	add	r10, r10, r0		/* r10 <- sym table in FLASH */
-	ldr	r2, _rel_dyn_start_ofs	/* r2 <- rel dyn start ofs */
-	add	r2, r2, r0		/* r2 <- rel dyn start in FLASH */
-	ldr	r3, _rel_dyn_end_ofs	/* r3 <- rel dyn end ofs */
-	add	r3, r3, r0		/* r3 <- rel dyn end in FLASH */
-fixloop:
-	ldr	r0, [r2]		/* r0 <- location to fix up, IN FLASH! */
-	add	r0, r0, r9		/* r0 <- location to fix up in RAM */
-	ldr	r1, [r2, #4]
-	and	r7, r1, #0xff
-	cmp	r7, #23			/* relative fixup? */
-	beq	fixrel
-	cmp	r7, #2			/* absolute fixup? */
-	beq	fixabs
-	/* ignore unknown type of fixup */
-	b	fixnext
-fixabs:
-	/* absolute fix: set location to (offset) symbol value */
-	mov	r1, r1, LSR #4		/* r1 <- symbol index in .dynsym */
-	add	r1, r10, r1		/* r1 <- address of symbol in table */
-	ldr	r1, [r1, #4]		/* r1 <- symbol value */
-	add	r1, r1, r9		/* r1 <- relocated sym addr */
-	b	fixnext
-fixrel:
-	/* relative fix: increase location by offset */
-	ldr	r1, [r0]
-	add	r1, r1, r9
-fixnext:
-	str	r1, [r0]
-	add	r2, r2, #8		/* each rel.dyn entry is 8 bytes */
-	cmp	r2, r3
-	blo	fixloop
-#endif
-
-clear_bss:
-#ifndef CONFIG_PRELOADER
-	ldr	r0, _bss_start_ofs
-	ldr	r1, _bss_end_ofs
-	mov	r4, r6			/* reloc addr */
-	add	r0, r0, r4
-	add	r1, r1, r4
-	mov	r2, #0x00000000		/* clear			    */
-
-clbss_l:str	r2, [r0]		/* clear loop...		    */
-	add	r0, r0, #4
-	cmp	r0, r1
-	bne	clbss_l
-
-	bl coloured_LED_init
-	bl red_LED_on
-#endif
-
-/*
- * We are done. Do not return, instead branch to second part of board
- * initialization, now running from RAM.
- */
-#ifdef CONFIG_NAND_SPL
-	ldr     r0, _nand_boot_ofs
-	mov	pc, r0
-
-_nand_boot_ofs:
-	.word nand_boot
-#else
-	ldr	r0, _board_init_r_ofs
-	ldr	r1, _TEXT_BASE
-	add	lr, r0, r1
-	add	lr, lr, r9
-	/* setup parameters for board_init_r */
-	mov	r0, r5		/* gd_t */
-	mov	r1, r6		/* dest_addr */
-	/* jump to it ... */
-	mov	pc, lr
-
-_board_init_r_ofs:
-	.word board_init_r - _start
-#endif
-
-_rel_dyn_start_ofs:
-	.word __rel_dyn_start - _start
-_rel_dyn_end_ofs:
-	.word __rel_dyn_end - _start
-_dynsym_start_ofs:
-	.word __dynsym_start - _start
-
-/*
- *************************************************************************
- *
- * CPU_init_critical registers
- *
- * setup important registers
- * setup memory timing
- *
- *************************************************************************
- */
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
-cpu_init_crit:
-	/*
-	 * flush v4 I/D caches
-	 */
-	mov	r0, #0
-	mcr	p15, 0, r0, c7, c7, 0	/* flush v3/v4 cache */
-	mcr	p15, 0, r0, c8, c7, 0	/* flush v4 TLB */
-
-	/*
-	 * disable MMU stuff and caches
-	 */
-	mrc	p15, 0, r0, c1, c0, 0
-	bic	r0, r0, #0x00002300	/* clear bits 13, 9:8 (--V- --RS) */
-	bic	r0, r0, #0x00000087	/* clear bits 7, 2:0 (B--- -CAM) */
-	orr	r0, r0, #0x00000002	/* set bit 2 (A) Align */
-	orr	r0, r0, #0x00001000	/* set bit 12 (I) I-Cache */
-	mcr	p15, 0, r0, c1, c0, 0
-
-	/*
-	 * Go setup Memory and board specific bits prior to relocation.
-	 */
-	mov	ip, lr		/* perserve link reg across call */
-	bl	lowlevel_init	/* go setup pll,mux,memory */
-	mov	lr, ip		/* restore link */
-	mov	pc, lr		/* back to my caller */
-#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
-
-#ifndef CONFIG_PRELOADER
-/*
- *************************************************************************
- *
- * Interrupt handling
- *
- *************************************************************************
- */
-
-@
-@ IRQ stack frame.
-@
-#define S_FRAME_SIZE	72
-
-#define S_OLD_R0	68
-#define S_PSR		64
-#define S_PC		60
-#define S_LR		56
-#define S_SP		52
-
-#define S_IP		48
-#define S_FP		44
-#define S_R10		40
-#define S_R9		36
-#define S_R8		32
-#define S_R7		28
-#define S_R6		24
-#define S_R5		20
-#define S_R4		16
-#define S_R3		12
-#define S_R2		8
-#define S_R1		4
-#define S_R0		0
-
-#define MODE_SVC 0x13
-#define I_BIT	 0x80
-
-/*
- * use bad_save_user_regs for abort/prefetch/undef/swi ...
- * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
- */
-
-	.macro	bad_save_user_regs
-	@ carve out a frame on current user stack
-	sub	sp, sp, #S_FRAME_SIZE
-	stmia	sp, {r0 - r12}	@ Save user registers (now in svc mode) r0-r12
-	ldr	r2, IRQ_STACK_START_IN
-	@ get values for "aborted" pc and cpsr (into parm regs)
-	ldmia	r2, {r2 - r3}
-	add	r0, sp, #S_FRAME_SIZE		@ grab pointer to old stack
-	add	r5, sp, #S_SP
-	mov	r1, lr
-	stmia	r5, {r0 - r3}	@ save sp_SVC, lr_SVC, pc, cpsr
-	mov	r0, sp		@ save current stack into r0 (param register)
-	.endm
-
-	.macro	irq_save_user_regs
-	sub	sp, sp, #S_FRAME_SIZE
-	stmia	sp, {r0 - r12}			@ Calling r0-r12
-	@ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good.
-	add	r8, sp, #S_PC
-	stmdb	r8, {sp, lr}^		@ Calling SP, LR
-	str	lr, [r8, #0]		@ Save calling PC
-	mrs	r6, spsr
-	str	r6, [r8, #4]		@ Save CPSR
-	str	r0, [r8, #8]		@ Save OLD_R0
-	mov	r0, sp
-	.endm
-
-	.macro	irq_restore_user_regs
-	ldmia	sp, {r0 - lr}^			@ Calling r0 - lr
-	mov	r0, r0
-	ldr	lr, [sp, #S_PC]			@ Get PC
-	add	sp, sp, #S_FRAME_SIZE
-	subs	pc, lr, #4		@ return & move spsr_svc into cpsr
-	.endm
-
-	.macro get_bad_stack
-	ldr	r13, IRQ_STACK_START_IN		@ setup our mode stack
-
-	str	lr, [r13]	@ save caller lr in position 0 of saved stack
-	mrs	lr, spsr	@ get the spsr
-	str	lr, [r13, #4]	@ save spsr in position 1 of saved stack
-	mov	r13, #MODE_SVC	@ prepare SVC-Mode
-	@ msr	spsr_c, r13
-	msr	spsr, r13	@ switch modes, make sure moves will execute
-	mov	lr, pc		@ capture return pc
-	movs	pc, lr		@ jump to next instruction & switch modes.
-	.endm
-
-	.macro get_irq_stack			@ setup IRQ stack
-	ldr	sp, IRQ_STACK_START
-	.endm
-
-	.macro get_fiq_stack			@ setup FIQ stack
-	ldr	sp, FIQ_STACK_START
-	.endm
-#endif	/* CONFIG_PRELOADER */
-
-/*
- * exception handlers
- */
-#ifdef CONFIG_PRELOADER
-	.align	5
-do_hang:
-	ldr	sp, _TEXT_BASE			/* switch to abort stack */
-1:
-	bl	1b				/* hang and never return */
-#else	/* !CONFIG_PRELOADER */
-	.align  5
-undefined_instruction:
-	get_bad_stack
-	bad_save_user_regs
-	bl	do_undefined_instruction
-
-	.align	5
-software_interrupt:
-	get_bad_stack
-	bad_save_user_regs
-	bl	do_software_interrupt
-
-	.align	5
-prefetch_abort:
-	get_bad_stack
-	bad_save_user_regs
-	bl	do_prefetch_abort
-
-	.align	5
-data_abort:
-	get_bad_stack
-	bad_save_user_regs
-	bl	do_data_abort
-
-	.align	5
-not_used:
-	get_bad_stack
-	bad_save_user_regs
-	bl	do_not_used
-
-#ifdef CONFIG_USE_IRQ
-
-	.align	5
-irq:
-	get_irq_stack
-	irq_save_user_regs
-	bl	do_irq
-	irq_restore_user_regs
-
-	.align	5
-fiq:
-	get_fiq_stack
-	/* someone ought to write a more effiction fiq_save_user_regs */
-	irq_save_user_regs
-	bl	do_fiq
-	irq_restore_user_regs
-
-#else
-
-	.align	5
-irq:
-	get_bad_stack
-	bad_save_user_regs
-	bl	do_irq
-
-	.align	5
-fiq:
-	get_bad_stack
-	bad_save_user_regs
-	bl	do_fiq
-
-#endif
-#endif	/* CONFIG_PRELOADER */
diff --git a/arch/arm/cpu/arm926ejs/u-boot.lds b/arch/arm/cpu/arm926ejs/u-boot.lds
deleted file mode 100644
index 28c91f9..0000000
--- a/arch/arm/cpu/arm926ejs/u-boot.lds
+++ /dev/null
@@ -1,78 +0,0 @@
-/*
- * (C) Copyright 2002-2004
- * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-ENTRY(_start)
-SECTIONS
-{
-	. = 0x00000000;
-
-	. = ALIGN(4);
-	.text :
-	{
-		arch/arm/cpu/arm926ejs/start.o	(.text)
-		*(.text)
-	}
-
-	. = ALIGN(4);
-	.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
-
-	. = ALIGN(4);
-	.data : {
-		*(.data)
-	}
-
-	. = ALIGN(4);
-
-	. = .;
-	__u_boot_cmd_start = .;
-	.u_boot_cmd : { *(.u_boot_cmd) }
-	__u_boot_cmd_end = .;
-
-	. = ALIGN(4);
-
-	.rel.dyn : {
-		__rel_dyn_start = .;
-		*(.rel*)
-		__rel_dyn_end = .;
-	}
-
-	.dynsym : {
-		__dynsym_start = .;
-		*(.dynsym)
-	}
-
-	.bss __rel_dyn_start (OVERLAY) : {
-		__bss_start = .;
-		*(.bss)
-		 . = ALIGN(4);
-		_end = .;
-	}
-
-	/DISCARD/ : { *(.dynstr*) }
-	/DISCARD/ : { *(.dynamic*) }
-	/DISCARD/ : { *(.plt*) }
-	/DISCARD/ : { *(.interp*) }
-	/DISCARD/ : { *(.gnu*) }
-}
diff --git a/arch/arm/cpu/arm926ejs/versatile/Makefile b/arch/arm/cpu/arm926ejs/versatile/Makefile
deleted file mode 100644
index 64e6aae..0000000
--- a/arch/arm/cpu/arm926ejs/versatile/Makefile
+++ /dev/null
@@ -1,47 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(SOC).o
-
-COBJS	= timer.o
-SOBJS	= reset.o
-
-SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS) $(SOBJS))
-START	:= $(addprefix $(obj),$(START))
-
-all:	$(obj).depend $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/arch/arm/cpu/arm926ejs/versatile/reset.S b/arch/arm/cpu/arm926ejs/versatile/reset.S
deleted file mode 100644
index 4b20756..0000000
--- a/arch/arm/cpu/arm926ejs/versatile/reset.S
+++ /dev/null
@@ -1,45 +0,0 @@
-/*
- *  armboot - Startup Code for ARM926EJS CPU-core
- *
- *  Copyright (c) 2003  Texas Instruments
- *
- *  ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------
- *
- *  Copyright (c) 2001	Marius Gröger <mag@sysgo.de>
- *  Copyright (c) 2002	Alex Züpke <azu@sysgo.de>
- *  Copyright (c) 2002	Gary Jennejohn <garyj@denx.de>
- *  Copyright (c) 2003	Richard Woodruff <r-woodruff2@ti.com>
- *  Copyright (c) 2003	Kshitij <kshitij@ti.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-	.align	5
-.globl reset_cpu
-reset_cpu:
-	ldr	r1, rstctl1	/* get clkm1 reset ctl */
-	mov	r3, #0x0
-	strh	r3, [r1]	/* clear it */
-	mov	r3, #0x8
-	strh	r3, [r1]	/* force dsp+arm reset */
-_loop_forever:
-	b	_loop_forever
-
-rstctl1:
-	.word	0xfffece10
diff --git a/arch/arm/cpu/arm926ejs/versatile/timer.c b/arch/arm/cpu/arm926ejs/versatile/timer.c
deleted file mode 100644
index 2e243b1..0000000
--- a/arch/arm/cpu/arm926ejs/versatile/timer.c
+++ /dev/null
@@ -1,207 +0,0 @@
-/*
- * (C) Copyright 2003
- * Texas Instruments <www.ti.com>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Alex Zuepke <azu@sysgo.de>
- *
- * (C) Copyright 2002-2004
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * (C) Copyright 2004
- * Philippe Robin, ARM Ltd. <philippe.robin@arm.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-
-#define TIMER_LOAD_VAL 0xffffffff
-
-/* macro to read the 32 bit timer */
-#define READ_TIMER (*(volatile ulong *)(CONFIG_SYS_TIMERBASE+4))
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define timestamp gd->tbl
-#define lastdec gd->lastinc
-
-#define TIMER_ENABLE	(1 << 7)
-#define TIMER_MODE_MSK	(1 << 6)
-#define TIMER_MODE_FR	(0 << 6)
-#define TIMER_MODE_PD	(1 << 6)
-
-#define TIMER_INT_EN	(1 << 5)
-#define TIMER_PRS_MSK	(3 << 2)
-#define TIMER_PRS_8S	(1 << 3)
-#define TIMER_SIZE_MSK	(1 << 2)
-#define TIMER_ONE_SHT	(1 << 0)
-
-int timer_init (void)
-{
-	ulong	tmr_ctrl_val;
-
-	/* 1st disable the Timer */
-	tmr_ctrl_val = *(volatile ulong *)(CONFIG_SYS_TIMERBASE + 8);
-	tmr_ctrl_val &= ~TIMER_ENABLE;
-	*(volatile ulong *)(CONFIG_SYS_TIMERBASE + 8) = tmr_ctrl_val;
-
-	/*
-	 * The Timer Control Register has one Undefined/Shouldn't Use Bit
-	 * So we should do read/modify/write Operation
-	 */
-
-	/*
-	 * Timer Mode : Free Running
-	 * Interrupt : Disabled
-	 * Prescale : 8 Stage, Clk/256
-	 * Tmr Siz : 16 Bit Counter
-	 * Tmr in Wrapping Mode
-	 */
-	tmr_ctrl_val = *(volatile ulong *)(CONFIG_SYS_TIMERBASE + 8);
-	tmr_ctrl_val &= ~(TIMER_MODE_MSK | TIMER_INT_EN | TIMER_PRS_MSK | TIMER_SIZE_MSK | TIMER_ONE_SHT );
-	tmr_ctrl_val |= (TIMER_ENABLE | TIMER_PRS_8S);
-
-	*(volatile ulong *)(CONFIG_SYS_TIMERBASE + 8) = tmr_ctrl_val;
-
-	/* init the timestamp and lastdec value */
-	reset_timer_masked();
-
-	return 0;
-}
-
-/*
- * timer without interrupts
- */
-
-void reset_timer (void)
-{
-	reset_timer_masked ();
-}
-
-ulong get_timer (ulong base)
-{
-	return get_timer_masked () - base;
-}
-
-void set_timer (ulong t)
-{
-	timestamp = t;
-}
-
-/* delay x useconds AND preserve advance timestamp value */
-void __udelay (unsigned long usec)
-{
-	ulong tmo, tmp;
-
-	if(usec >= 1000){		/* if "big" number, spread normalization to seconds */
-		tmo = usec / 1000;	/* start to normalize for usec to ticks per sec */
-		tmo *= CONFIG_SYS_HZ;	/* find number of "ticks" to wait to achieve target */
-		tmo /= 1000;		/* finish normalize. */
-	}else{				/* else small number, don't kill it prior to HZ multiply */
-		tmo = usec * CONFIG_SYS_HZ;
-		tmo /= (1000*1000);
-	}
-
-	tmp = get_timer (0);		/* get current timestamp */
-	if( (tmo + tmp + 1) < tmp )	/* if setting this fordward will roll time stamp */
-		reset_timer_masked ();	/* reset "advancing" timestamp to 0, set lastdec value */
-	else
-		tmo += tmp;		/* else, set advancing stamp wake up time */
-
-	while (get_timer_masked () < tmo)/* loop till event */
-		/*NOP*/;
-}
-
-void reset_timer_masked (void)
-{
-	/* reset time */
-	lastdec = READ_TIMER;  /* capure current decrementer value time */
-	timestamp = 0;	       /* start "advancing" time stamp from 0 */
-}
-
-ulong get_timer_masked (void)
-{
-	ulong now = READ_TIMER;		/* current tick value */
-
-	if (lastdec >= now) {		/* normal mode (non roll) */
-		/* normal mode */
-		timestamp += lastdec - now; /* move stamp fordward with absoulte diff ticks */
-	} else {			/* we have overflow of the count down timer */
-		/* nts = ts + ld + (TLV - now)
-		 * ts=old stamp, ld=time that passed before passing through -1
-		 * (TLV-now) amount of time after passing though -1
-		 * nts = new "advancing time stamp"...it could also roll and cause problems.
-		 */
-		timestamp += lastdec + TIMER_LOAD_VAL - now;
-	}
-	lastdec = now;
-
-	return timestamp;
-}
-
-/* waits specified delay value and resets timestamp */
-void udelay_masked (unsigned long usec)
-{
-	ulong tmo;
-	ulong endtime;
-	signed long diff;
-
-	if (usec >= 1000) {		/* if "big" number, spread normalization to seconds */
-		tmo = usec / 1000;	/* start to normalize for usec to ticks per sec */
-		tmo *= CONFIG_SYS_HZ;		/* find number of "ticks" to wait to achieve target */
-		tmo /= 1000;		/* finish normalize. */
-	} else {			/* else small number, don't kill it prior to HZ multiply */
-		tmo = usec * CONFIG_SYS_HZ;
-		tmo /= (1000*1000);
-	}
-
-	endtime = get_timer_masked () + tmo;
-
-	do {
-		ulong now = get_timer_masked ();
-		diff = endtime - now;
-	} while (diff >= 0);
-}
-
-/*
- * This function is derived from PowerPC code (read timebase as long long).
- * On ARM it just returns the timer value.
- */
-unsigned long long get_ticks(void)
-{
-	return get_timer(0);
-}
-
-/*
- * This function is derived from PowerPC code (timebase clock frequency).
- * On ARM it returns the number of timer ticks per second.
- */
-ulong get_tbclk (void)
-{
-	ulong tbclk;
-
-	tbclk = CONFIG_SYS_HZ;
-	return tbclk;
-}
diff --git a/arch/arm/cpu/arm946es/Makefile b/arch/arm/cpu/arm946es/Makefile
deleted file mode 100644
index d4747f3..0000000
--- a/arch/arm/cpu/arm946es/Makefile
+++ /dev/null
@@ -1,48 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(CPU).o
-
-START	= start.o
-
-COBJS	= cpu.o
-
-SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS) $(SOBJS))
-START	:= $(addprefix $(obj),$(START))
-
-all:	$(obj).depend $(START) $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/arch/arm/cpu/arm946es/config.mk b/arch/arm/cpu/arm946es/config.mk
deleted file mode 100644
index e783f69..0000000
--- a/arch/arm/cpu/arm946es/config.mk
+++ /dev/null
@@ -1,32 +0,0 @@
-#
-# (C) Copyright 2002
-# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float
-
-PLATFORM_CPPFLAGS +=  -march=armv4
-# =========================================================================
-#
-# Supply options according to compiler version
-#
-# =========================================================================
-PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))
diff --git a/arch/arm/cpu/arm946es/cpu.c b/arch/arm/cpu/arm946es/cpu.c
deleted file mode 100644
index c63c98b..0000000
--- a/arch/arm/cpu/arm946es/cpu.c
+++ /dev/null
@@ -1,69 +0,0 @@
-/*
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * CPU specific code
- */
-
-#include <common.h>
-#include <command.h>
-#include <asm/system.h>
-
-static void cache_flush(void);
-
-int cleanup_before_linux (void)
-{
-	/*
-	 * this function is called just before we call linux
-	 * it prepares the processor for linux
-	 *
-	 * we turn off caches etc ...
-	 */
-
-	disable_interrupts ();
-
-	/* ARM926E-S needs the protection unit enabled for the icache to have
-	 * been enabled	 - left for possible later use
-	 * should turn off the protection unit as well....
-	 */
-	/* turn off I/D-cache */
-	icache_disable();
-	dcache_disable();
-	/* flush I/D-cache */
-	cache_flush();
-
-	return 0;
-}
-
-/* flush I/D-cache */
-static void cache_flush (void)
-{
-	unsigned long i = 0;
-
-	asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i));
-	asm ("mcr p15, 0, %0, c7, c6, 0": :"r" (i));
-}
diff --git a/arch/arm/cpu/arm946es/start.S b/arch/arm/cpu/arm946es/start.S
deleted file mode 100644
index 296effc..0000000
--- a/arch/arm/cpu/arm946es/start.S
+++ /dev/null
@@ -1,495 +0,0 @@
-/*
- *  armboot - Startup Code for ARM926EJS CPU-core
- *
- *  Copyright (c) 2003  Texas Instruments
- *
- *  ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------
- *
- *  Copyright (c) 2001	Marius Gröger <mag@sysgo.de>
- *  Copyright (c) 2002	Alex Züpke <azu@sysgo.de>
- *  Copyright (c) 2002	Gary Jennejohn <garyj@denx.de>
- *  Copyright (c) 2003	Richard Woodruff <r-woodruff2@ti.com>
- *  Copyright (c) 2003	Kshitij <kshitij@ti.com>
- *  Copyright (c) 2010	Albert Aribaud <albert.aribaud@free.fr>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <asm-offsets.h>
-#include <config.h>
-#include <version.h>
-
-/*
- *************************************************************************
- *
- * Jump vector table as in table 3.1 in [1]
- *
- *************************************************************************
- */
-
-
-.globl _start
-_start:
-	b	reset
-	ldr	pc, _undefined_instruction
-	ldr	pc, _software_interrupt
-	ldr	pc, _prefetch_abort
-	ldr	pc, _data_abort
-	ldr	pc, _not_used
-	ldr	pc, _irq
-	ldr	pc, _fiq
-
-_undefined_instruction:
-	.word undefined_instruction
-_software_interrupt:
-	.word software_interrupt
-_prefetch_abort:
-	.word prefetch_abort
-_data_abort:
-	.word data_abort
-_not_used:
-	.word not_used
-_irq:
-	.word irq
-_fiq:
-	.word fiq
-
-	.balignl 16,0xdeadbeef
-
-_vectors_end:
-
-/*
- *************************************************************************
- *
- * Startup Code (reset vector)
- *
- * do important init only if we don't start from memory!
- * setup Memory and board specific bits prior to relocation.
- * relocate armboot to ram
- * setup stack
- *
- *************************************************************************
- */
-
-.globl _TEXT_BASE
-_TEXT_BASE:
-	.word	CONFIG_SYS_TEXT_BASE
-
-/*
- * These are defined in the board-specific linker script.
- * Subtracting _start from them lets the linker put their
- * relative position in the executable instead of leaving
- * them null.
- */
-.globl _bss_start_ofs
-_bss_start_ofs:
-	.word __bss_start - _start
-
-.globl _bss_end_ofs
-_bss_end_ofs:
-	.word _end - _start
-
-#ifdef CONFIG_USE_IRQ
-/* IRQ stack memory (calculated at run-time) */
-.globl IRQ_STACK_START
-IRQ_STACK_START:
-	.word	0x0badc0de
-
-/* IRQ stack memory (calculated at run-time) */
-.globl FIQ_STACK_START
-FIQ_STACK_START:
-	.word 0x0badc0de
-#endif
-
-/* IRQ stack memory (calculated at run-time) + 8 bytes */
-.globl IRQ_STACK_START_IN
-IRQ_STACK_START_IN:
-	.word	0x0badc0de
-
-/*
- * the actual reset code
- */
-
-reset:
-	/*
-	 * set the cpu to SVC32 mode
-	 */
-	mrs	r0,cpsr
-	bic	r0,r0,#0x1f
-	orr	r0,r0,#0xd3
-	msr	cpsr,r0
-
-	/*
-	 * we do sys-critical inits only at reboot,
-	 * not when booting from ram!
-	 */
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
-	bl	cpu_init_crit
-#endif
-
-/* Set stackpointer in internal RAM to call board_init_f */
-call_board_init_f:
-	ldr	sp, =(CONFIG_SYS_INIT_SP_ADDR)
-	bic	sp, sp, #7 /* 8-byte alignment for ABI compliance */
-	ldr	r0,=0x00000000
-	bl	board_init_f
-
-/*------------------------------------------------------------------------------*/
-
-/*
- * void relocate_code (addr_sp, gd, addr_moni)
- *
- * This "function" does not return, instead it continues in RAM
- * after relocating the monitor code.
- *
- */
-	.globl	relocate_code
-relocate_code:
-	mov	r4, r0	/* save addr_sp */
-	mov	r5, r1	/* save addr of gd */
-	mov	r6, r2	/* save addr of destination */
-
-	/* Set up the stack						    */
-stack_setup:
-	mov	sp, r4
-
-	adr	r0, _start
-	cmp	r0, r6
-	beq	clear_bss		/* skip relocation */
-	mov	r1, r6			/* r1 <- scratch for copy_loop */
-	ldr	r3, _bss_start_ofs
-	add	r2, r0, r3		/* r2 <- source end address	    */
-
-copy_loop:
-	ldmia	r0!, {r9-r10}		/* copy from source address [r0]    */
-	stmia	r1!, {r9-r10}		/* copy to   target address [r1]    */
-	cmp	r0, r2			/* until source end address [r2]    */
-	blo	copy_loop
-
-#ifndef CONFIG_PRELOADER
-	/*
-	 * fix .rel.dyn relocations
-	 */
-	ldr	r0, _TEXT_BASE		/* r0 <- Text base */
-	sub	r9, r6, r0		/* r9 <- relocation offset */
-	ldr	r10, _dynsym_start_ofs	/* r10 <- sym table ofs */
-	add	r10, r10, r0		/* r10 <- sym table in FLASH */
-	ldr	r2, _rel_dyn_start_ofs	/* r2 <- rel dyn start ofs */
-	add	r2, r2, r0		/* r2 <- rel dyn start in FLASH */
-	ldr	r3, _rel_dyn_end_ofs	/* r3 <- rel dyn end ofs */
-	add	r3, r3, r0		/* r3 <- rel dyn end in FLASH */
-fixloop:
-	ldr	r0, [r2]		/* r0 <- location to fix up, IN FLASH! */
-	add	r0, r0, r9		/* r0 <- location to fix up in RAM */
-	ldr	r1, [r2, #4]
-	and	r7, r1, #0xff
-	cmp	r7, #23			/* relative fixup? */
-	beq	fixrel
-	cmp	r7, #2			/* absolute fixup? */
-	beq	fixabs
-	/* ignore unknown type of fixup */
-	b	fixnext
-fixabs:
-	/* absolute fix: set location to (offset) symbol value */
-	mov	r1, r1, LSR #4		/* r1 <- symbol index in .dynsym */
-	add	r1, r10, r1		/* r1 <- address of symbol in table */
-	ldr	r1, [r1, #4]		/* r1 <- symbol value */
-	add	r1, r1, r9		/* r1 <- relocated sym addr */
-	b	fixnext
-fixrel:
-	/* relative fix: increase location by offset */
-	ldr	r1, [r0]
-	add	r1, r1, r9
-fixnext:
-	str	r1, [r0]
-	add	r2, r2, #8		/* each rel.dyn entry is 8 bytes */
-	cmp	r2, r3
-	blo	fixloop
-#endif
-
-clear_bss:
-#ifndef CONFIG_PRELOADER
-	ldr	r0, _bss_start_ofs
-	ldr	r1, _bss_end_ofs
-	mov	r4, r6			/* reloc addr */
-	add	r0, r0, r4
-	add	r1, r1, r4
-	mov	r2, #0x00000000		/* clear			    */
-
-clbss_l:str	r2, [r0]		/* clear loop...		    */
-	add	r0, r0, #4
-	cmp	r0, r1
-	blo	clbss_l
-#endif
-
-/*
- * We are done. Do not return, instead branch to second part of board
- * initialization, now running from RAM.
- */
-#ifdef CONFIG_NAND_SPL
-	ldr     pc, _nand_boot
-
-_nand_boot: .word nand_boot
-#else
-	ldr	r0, _board_init_r_ofs
-	adr	r1, _start
-	add	lr, r0, r1
-	add	lr, lr, r9
-	/* setup parameters for board_init_r */
-	mov	r0, r5		/* gd_t */
-	mov	r1, r6		/* dest_addr */
-	/* jump to it ... */
-	mov	pc, lr
-
-_board_init_r_ofs:
-	.word board_init_r - _start
-#endif
-
-_rel_dyn_start_ofs:
-	.word __rel_dyn_start - _start
-_rel_dyn_end_ofs:
-	.word __rel_dyn_end - _start
-_dynsym_start_ofs:
-	.word __dynsym_start - _start
-
-/*
- *************************************************************************
- *
- * CPU_init_critical registers
- *
- * setup important registers
- * setup memory timing
- *
- *************************************************************************
- */
-
-
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
-cpu_init_crit:
-	/*
-	 * flush v4 I/D caches
-	 */
-	mov	r0, #0
-	mcr	p15, 0, r0, c7, c5, 0	/* flush v4 I-cache */
-	mcr	p15, 0, r0, c7, c6, 0	/* flush v4 D-cache */
-
-	/*
-	 * disable MMU stuff and caches
-	 */
-	mrc	p15, 0, r0, c1, c0, 0
-	bic	r0, r0, #0x00002300	/* clear bits 13, 9:8 (--V- --RS) */
-	bic	r0, r0, #0x00000087	/* clear bits 7, 2:0 (B--- -CAM) */
-	orr	r0, r0, #0x00000002	/* set bit 2 (A) Align */
-	orr	r0, r0, #0x00001000	/* set bit 12 (I) I-Cache */
-	mcr	p15, 0, r0, c1, c0, 0
-
-	/*
-	 * Go setup Memory and board specific bits prior to relocation.
-	 */
-	mov	ip, lr		/* perserve link reg across call */
-	bl	lowlevel_init	/* go setup memory */
-	mov	lr, ip		/* restore link */
-	mov	pc, lr		/* back to my caller */
-#endif
-/*
- *************************************************************************
- *
- * Interrupt handling
- *
- *************************************************************************
- */
-
-@
-@ IRQ stack frame.
-@
-#define S_FRAME_SIZE	72
-
-#define S_OLD_R0	68
-#define S_PSR		64
-#define S_PC		60
-#define S_LR		56
-#define S_SP		52
-
-#define S_IP		48
-#define S_FP		44
-#define S_R10		40
-#define S_R9		36
-#define S_R8		32
-#define S_R7		28
-#define S_R6		24
-#define S_R5		20
-#define S_R4		16
-#define S_R3		12
-#define S_R2		8
-#define S_R1		4
-#define S_R0		0
-
-#define MODE_SVC 0x13
-#define I_BIT	 0x80
-
-/*
- * use bad_save_user_regs for abort/prefetch/undef/swi ...
- * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
- */
-
-	.macro	bad_save_user_regs
-	@ carve out a frame on current user stack
-	sub	sp, sp, #S_FRAME_SIZE
-	stmia	sp, {r0 - r12}	@ Save user registers (now in svc mode) r0-r12
-
-	ldr	r2, IRQ_STACK_START_IN
-	@ get values for "aborted" pc and cpsr (into parm regs)
-	ldmia	r2, {r2 - r3}
-	add	r0, sp, #S_FRAME_SIZE		@ grab pointer to old stack
-	add	r5, sp, #S_SP
-	mov	r1, lr
-	stmia	r5, {r0 - r3}	@ save sp_SVC, lr_SVC, pc, cpsr
-	mov	r0, sp		@ save current stack into r0 (param register)
-	.endm
-
-	.macro	irq_save_user_regs
-	sub	sp, sp, #S_FRAME_SIZE
-	stmia	sp, {r0 - r12}			@ Calling r0-r12
-	@ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good.
-	add	r8, sp, #S_PC
-	stmdb	r8, {sp, lr}^		@ Calling SP, LR
-	str	lr, [r8, #0]		@ Save calling PC
-	mrs	r6, spsr
-	str	r6, [r8, #4]		@ Save CPSR
-	str	r0, [r8, #8]		@ Save OLD_R0
-	mov	r0, sp
-	.endm
-
-	.macro	irq_restore_user_regs
-	ldmia	sp, {r0 - lr}^			@ Calling r0 - lr
-	mov	r0, r0
-	ldr	lr, [sp, #S_PC]			@ Get PC
-	add	sp, sp, #S_FRAME_SIZE
-	subs	pc, lr, #4		@ return & move spsr_svc into cpsr
-	.endm
-
-	.macro get_bad_stack
-	ldr	r13, IRQ_STACK_START_IN		@ setup our mode stack
-
-	str	lr, [r13]	@ save caller lr in position 0 of saved stack
-	mrs	lr, spsr	@ get the spsr
-	str	lr, [r13, #4]	@ save spsr in position 1 of saved stack
-	mov	r13, #MODE_SVC	@ prepare SVC-Mode
-	@ msr	spsr_c, r13
-	msr	spsr, r13	@ switch modes, make sure moves will execute
-	mov	lr, pc		@ capture return pc
-	movs	pc, lr		@ jump to next instruction & switch modes.
-	.endm
-
-	.macro get_irq_stack			@ setup IRQ stack
-	ldr	sp, IRQ_STACK_START
-	.endm
-
-	.macro get_fiq_stack			@ setup FIQ stack
-	ldr	sp, FIQ_STACK_START
-	.endm
-
-/*
- * exception handlers
- */
-	.align  5
-undefined_instruction:
-	get_bad_stack
-	bad_save_user_regs
-	bl	do_undefined_instruction
-
-	.align	5
-software_interrupt:
-	get_bad_stack
-	bad_save_user_regs
-	bl	do_software_interrupt
-
-	.align	5
-prefetch_abort:
-	get_bad_stack
-	bad_save_user_regs
-	bl	do_prefetch_abort
-
-	.align	5
-data_abort:
-	get_bad_stack
-	bad_save_user_regs
-	bl	do_data_abort
-
-	.align	5
-not_used:
-	get_bad_stack
-	bad_save_user_regs
-	bl	do_not_used
-
-#ifdef CONFIG_USE_IRQ
-
-	.align	5
-irq:
-	get_irq_stack
-	irq_save_user_regs
-	bl	do_irq
-	irq_restore_user_regs
-
-	.align	5
-fiq:
-	get_fiq_stack
-	/* someone ought to write a more effiction fiq_save_user_regs */
-	irq_save_user_regs
-	bl	do_fiq
-	irq_restore_user_regs
-
-#else
-
-	.align	5
-irq:
-	get_bad_stack
-	bad_save_user_regs
-	bl	do_irq
-
-	.align	5
-fiq:
-	get_bad_stack
-	bad_save_user_regs
-	bl	do_fiq
-
-#endif
-
-# ifdef CONFIG_INTEGRATOR
-
-	/* Satisfied by general board level routine */
-
-#else
-
-	.align	5
-.globl reset_cpu
-reset_cpu:
-
-	ldr	r1, rstctl1	/* get clkm1 reset ctl */
-	mov	r3, #0x0
-	strh	r3, [r1]	/* clear it */
-	mov	r3, #0x8
-	strh	r3, [r1]	/* force dsp+arm reset */
-_loop_forever:
-	b	_loop_forever
-
-rstctl1:
-	.word	0xfffece10
-
-#endif	/* #ifdef CONFIG_INTEGRATOR */
diff --git a/arch/arm/cpu/arm946es/u-boot.lds b/arch/arm/cpu/arm946es/u-boot.lds
deleted file mode 100644
index eb91979..0000000
--- a/arch/arm/cpu/arm946es/u-boot.lds
+++ /dev/null
@@ -1,78 +0,0 @@
-/*
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-ENTRY(_start)
-SECTIONS
-{
-	. = 0x00000000;
-
-	. = ALIGN(4);
-	.text :
-	{
-		arch/arm/cpu/arm946es/start.o	(.text)
-		*(.text)
-	}
-
-	. = ALIGN(4);
-	.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
-
-	. = ALIGN(4);
-	.data : {
-		*(.data)
-	}
-
-	. = ALIGN(4);
-
-	. = .;
-	__u_boot_cmd_start = .;
-	.u_boot_cmd : { *(.u_boot_cmd) }
-	__u_boot_cmd_end = .;
-
-	. = ALIGN(4);
-
-	.rel.dyn : {
-		__rel_dyn_start = .;
-		*(.rel*)
-		__rel_dyn_end = .;
-	}
-
-	.dynsym : {
-		__dynsym_start = .;
-		*(.dynsym)
-	}
-
-	.bss __rel_dyn_start (OVERLAY) : {
-		__bss_start = .;
-		*(.bss)
-		 . = ALIGN(4);
-		_end = .;
-	}
-
-	/DISCARD/ : { *(.dynstr*) }
-	/DISCARD/ : { *(.dynamic*) }
-	/DISCARD/ : { *(.plt*) }
-	/DISCARD/ : { *(.interp*) }
-	/DISCARD/ : { *(.gnu*) }
-}
diff --git a/arch/arm/cpu/arm_intcm/Makefile b/arch/arm/cpu/arm_intcm/Makefile
deleted file mode 100644
index 930e0d1..0000000
--- a/arch/arm/cpu/arm_intcm/Makefile
+++ /dev/null
@@ -1,47 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(CPU).o
-
-START	= start.o
-COBJS	= cpu.o
-
-SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS) $(SOBJS))
-START	:= $(addprefix $(obj),$(START))
-
-all:	$(obj).depend $(START) $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/arch/arm/cpu/arm_intcm/config.mk b/arch/arm/cpu/arm_intcm/config.mk
deleted file mode 100644
index e783f69..0000000
--- a/arch/arm/cpu/arm_intcm/config.mk
+++ /dev/null
@@ -1,32 +0,0 @@
-#
-# (C) Copyright 2002
-# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float
-
-PLATFORM_CPPFLAGS +=  -march=armv4
-# =========================================================================
-#
-# Supply options according to compiler version
-#
-# =========================================================================
-PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))
diff --git a/arch/arm/cpu/arm_intcm/cpu.c b/arch/arm/cpu/arm_intcm/cpu.c
deleted file mode 100644
index c0748e8..0000000
--- a/arch/arm/cpu/arm_intcm/cpu.c
+++ /dev/null
@@ -1,52 +0,0 @@
-/*
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * CPU specific code for an unknown cpu
- * - hence fairly empty......
- */
-
-#include <common.h>
-#include <command.h>
-
-int cleanup_before_linux (void)
-{
-	/*
-	 * this function is called just before we call linux
-	 * it prepares the processor for linux
-	 *
-	 * we turn off caches etc ...
-	 */
-
-	disable_interrupts ();
-
-	/* Since the CM has unknown processor we do not support
-	 * cache operations
-	 */
-
-	return (0);
-}
diff --git a/arch/arm/cpu/arm_intcm/start.S b/arch/arm/cpu/arm_intcm/start.S
deleted file mode 100644
index e8518e2..0000000
--- a/arch/arm/cpu/arm_intcm/start.S
+++ /dev/null
@@ -1,460 +0,0 @@
-/*
- *  armboot - Startup Code for ARM926EJS CPU-core
- *
- *  Copyright (c) 2003  Texas Instruments
- *
- *  ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------
- *
- *  Copyright (c) 2001	Marius Gröger <mag@sysgo.de>
- *  Copyright (c) 2002	Alex Züpke <azu@sysgo.de>
- *  Copyright (c) 2002	Gary Jennejohn <garyj@denx.de>
- *  Copyright (c) 2003	Richard Woodruff <r-woodruff2@ti.com>
- *  Copyright (c) 2003	Kshitij <kshitij@ti.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <asm-offsets.h>
-#include <config.h>
-#include <version.h>
-
-/*
- *************************************************************************
- *
- * Jump vector table
- *
- *************************************************************************
- */
-
-.globl _start
-_start:
-	b	reset
-	ldr	pc, _undefined_instruction
-	ldr	pc, _software_interrupt
-	ldr	pc, _prefetch_abort
-	ldr	pc, _data_abort
-	ldr	pc, _not_used
-	ldr	pc, _irq
-	ldr	pc, _fiq
-
-_undefined_instruction:
-	.word undefined_instruction
-_software_interrupt:
-	.word software_interrupt
-_prefetch_abort:
-	.word prefetch_abort
-_data_abort:
-	.word data_abort
-_not_used:
-	.word not_used
-_irq:
-	.word irq
-_fiq:
-	.word fiq
-
-	.balignl 16,0xdeadbeef
-
-/*
- *************************************************************************
- *
- * Startup Code (reset vector)
- *
- * do important init only if we don't start from memory!
- * setup memory and board specific bits prior to relocation.
- * relocate armboot to ram
- * setup stack
- *
- *************************************************************************
- */
-
-.globl _TEXT_BASE
-_TEXT_BASE:
-	.word	CONFIG_SYS_TEXT_BASE /* address of _start in the linked image */
-
-/*
- * These are defined in the board-specific linker script.
- * Subtracting _start from them lets the linker put their
- * relative position in the executable instead of leaving
- * them null.
- */
-.globl _bss_start_ofs
-_bss_start_ofs:
-	.word __bss_start - _start
-
-.globl _bss_end_ofs
-_bss_end_ofs:
-	.word _end - _start
-
-#ifdef CONFIG_USE_IRQ
-/* IRQ stack memory (calculated at run-time) */
-.globl IRQ_STACK_START
-IRQ_STACK_START:
-	.word	0x0badc0de
-
-/* IRQ stack memory (calculated at run-time) */
-.globl FIQ_STACK_START
-FIQ_STACK_START:
-	.word 0x0badc0de
-#endif
-
-/* IRQ stack memory (calculated at run-time) + 8 bytes */
-.globl IRQ_STACK_START_IN
-IRQ_STACK_START_IN:
-	.word	0x0badc0de
-
-/*
- * the actual reset code
- */
-
-reset:
-	/*
-	 * set the cpu to SVC32 mode
-	 */
-	mrs	r0,cpsr
-	bic	r0,r0,#0x1f
-	orr	r0,r0,#0xd3
-	msr	cpsr,r0
-
-	/*
-	 * we do sys-critical inits only at reboot,
-	 * not when booting from ram!
-	 */
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
-	bl	cpu_init_crit
-#endif
-
-/* Set stackpointer in internal RAM to call board_init_f */
-call_board_init_f:
-	ldr	sp, =(CONFIG_SYS_INIT_SP_ADDR)
-	bic	sp, sp, #7 /* 8-byte alignment for ABI compliance */
-	ldr	r0,=0x00000000
-	bl	board_init_f
-
-/*------------------------------------------------------------------------------*/
-
-/*
- * void relocate_code (addr_sp, gd, addr_moni)
- *
- * This "function" does not return, instead it continues in RAM
- * after relocating the monitor code.
- *
- */
-	.globl	relocate_code
-relocate_code:
-	mov	r4, r0	/* save addr_sp */
-	mov	r5, r1	/* save addr of gd */
-	mov	r6, r2	/* save addr of destination */
-
-	/* Set up the stack						    */
-stack_setup:
-	mov	sp, r4
-
-	adr	r0, _start
-	cmp	r0, r6
-	beq	clear_bss		/* skip relocation */
-	mov	r1, r6			/* r1 <- scratch for copy_loop */
-	ldr	r3, _bss_start_ofs
-	add	r2, r0, r3		/* r2 <- source end address	    */
-
-copy_loop:
-	ldmia	r0!, {r9-r10}		/* copy from source address [r0]    */
-	stmia	r1!, {r9-r10}		/* copy to   target address [r1]    */
-	cmp	r0, r2			/* until source end address [r2]    */
-	blo	copy_loop
-
-#ifndef CONFIG_PRELOADER
-	/*
-	 * fix .rel.dyn relocations
-	 */
-	ldr	r0, _TEXT_BASE		/* r0 <- Text base */
-	sub	r9, r6, r0		/* r9 <- relocation offset */
-	ldr	r10, _dynsym_start_ofs	/* r10 <- sym table ofs */
-	add	r10, r10, r0		/* r10 <- sym table in FLASH */
-	ldr	r2, _rel_dyn_start_ofs	/* r2 <- rel dyn start ofs */
-	add	r2, r2, r0		/* r2 <- rel dyn start in FLASH */
-	ldr	r3, _rel_dyn_end_ofs	/* r3 <- rel dyn end ofs */
-	add	r3, r3, r0		/* r3 <- rel dyn end in FLASH */
-fixloop:
-	ldr	r0, [r2]		/* r0 <- location to fix up, IN FLASH! */
-	add	r0, r0, r9		/* r0 <- location to fix up in RAM */
-	ldr	r1, [r2, #4]
-	and	r7, r1, #0xff
-	cmp	r7, #23			/* relative fixup? */
-	beq	fixrel
-	cmp	r7, #2			/* absolute fixup? */
-	beq	fixabs
-	/* ignore unknown type of fixup */
-	b	fixnext
-fixabs:
-	/* absolute fix: set location to (offset) symbol value */
-	mov	r1, r1, LSR #4		/* r1 <- symbol index in .dynsym */
-	add	r1, r10, r1		/* r1 <- address of symbol in table */
-	ldr	r1, [r1, #4]		/* r1 <- symbol value */
-	add	r1, r1, r9		/* r1 <- relocated sym addr */
-	b	fixnext
-fixrel:
-	/* relative fix: increase location by offset */
-	ldr	r1, [r0]
-	add	r1, r1, r9
-fixnext:
-	str	r1, [r0]
-	add	r2, r2, #8		/* each rel.dyn entry is 8 bytes */
-	cmp	r2, r3
-	blo	fixloop
-#endif
-
-clear_bss:
-#ifndef CONFIG_PRELOADER
-	ldr	r0, _bss_start_ofs
-	ldr	r1, _bss_end_ofs
-	mov	r4, r6			/* reloc addr */
-	add	r0, r0, r4
-	add	r1, r1, r4
-	mov	r2, #0x00000000		/* clear			    */
-
-clbss_l:str	r2, [r0]		/* clear loop...		    */
-	add	r0, r0, #4
-	cmp	r0, r1
-	bne	clbss_l
-
-	bl coloured_LED_init
-	bl red_LED_on
-#endif
-
-/*
- * We are done. Do not return, instead branch to second part of board
- * initialization, now running from RAM.
- */
-#ifdef CONFIG_NAND_SPL
-	ldr     r0, _nand_boot_ofs
-	mov	pc, r0
-
-_nand_boot_ofs:
-	.word nand_boot
-#else
-	ldr	r0, _board_init_r_ofs
-	adr	r1, _start
-	add	lr, r0, r1
-	add	lr, lr, r9
-	/* setup parameters for board_init_r */
-	mov	r0, r5		/* gd_t */
-	mov	r1, r6		/* dest_addr */
-	/* jump to it ... */
-	mov	pc, lr
-
-_board_init_r_ofs:
-	.word board_init_r - _start
-#endif
-
-_rel_dyn_start_ofs:
-	.word __rel_dyn_start - _start
-_rel_dyn_end_ofs:
-	.word __rel_dyn_end - _start
-_dynsym_start_ofs:
-	.word __dynsym_start - _start
-
-/*
- *************************************************************************
- *
- * CPU_init_critical registers
- *
- * setup important registers
- * setup memory timing
- *
- *************************************************************************
- */
-
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
-cpu_init_crit:
-	/*  arm_int_generic assumes the ARM boot monitor, or user software,
-	 * has initialized the platform
-	 */
-	mov	pc, lr		/* back to my caller */
-#endif
-/*
- *************************************************************************
- *
- * Interrupt handling
- *
- *************************************************************************
- */
-
-@
-@ IRQ stack frame.
-@
-#define S_FRAME_SIZE	72
-
-#define S_OLD_R0	68
-#define S_PSR		64
-#define S_PC		60
-#define S_LR		56
-#define S_SP		52
-
-#define S_IP		48
-#define S_FP		44
-#define S_R10		40
-#define S_R9		36
-#define S_R8		32
-#define S_R7		28
-#define S_R6		24
-#define S_R5		20
-#define S_R4		16
-#define S_R3		12
-#define S_R2		8
-#define S_R1		4
-#define S_R0		0
-
-#define MODE_SVC 0x13
-#define I_BIT	 0x80
-
-/*
- * use bad_save_user_regs for abort/prefetch/undef/swi ...
- * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
- */
-
-	.macro	bad_save_user_regs
-	@ carve out a frame on current user stack
-	sub	sp, sp, #S_FRAME_SIZE
-	stmia	sp, {r0 - r12}	@ Save user registers (now in svc mode) r0-r12
-
-	ldr	r2, IRQ_STACK_START_IN
-	@ get values for "aborted" pc and cpsr (into parm regs)
-	ldmia	r2, {r2 - r3}
-	add	r0, sp, #S_FRAME_SIZE		@ grab pointer to old stack
-	add	r5, sp, #S_SP
-	mov	r1, lr
-	stmia	r5, {r0 - r3}	@ save sp_SVC, lr_SVC, pc, cpsr
-	mov	r0, sp		@ save current stack into r0 (param register)
-	.endm
-
-	.macro	irq_save_user_regs
-	sub	sp, sp, #S_FRAME_SIZE
-	stmia	sp, {r0 - r12}			@ Calling r0-r12
-	@ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good.
-	add	r8, sp, #S_PC
-	stmdb	r8, {sp, lr}^		@ Calling SP, LR
-	str	lr, [r8, #0]		@ Save calling PC
-	mrs	r6, spsr
-	str	r6, [r8, #4]		@ Save CPSR
-	str	r0, [r8, #8]		@ Save OLD_R0
-	mov	r0, sp
-	.endm
-
-	.macro	irq_restore_user_regs
-	ldmia	sp, {r0 - lr}^			@ Calling r0 - lr
-	mov	r0, r0
-	ldr	lr, [sp, #S_PC]			@ Get PC
-	add	sp, sp, #S_FRAME_SIZE
-	subs	pc, lr, #4		@ return & move spsr_svc into cpsr
-	.endm
-
-	.macro get_bad_stack
-	ldr	r13, IRQ_STACK_START_IN		@ setup our mode stack
-
-	str	lr, [r13]	@ save caller lr in position 0 of saved stack
-	mrs	lr, spsr	@ get the spsr
-	str	lr, [r13, #4]	@ save spsr in position 1 of saved stack
-	mov	r13, #MODE_SVC	@ prepare SVC-Mode
-	@ msr	spsr_c, r13
-	msr	spsr, r13	@ switch modes, make sure moves will execute
-	mov	lr, pc		@ capture return pc
-	movs	pc, lr		@ jump to next instruction & switch modes.
-	.endm
-
-	.macro get_irq_stack			@ setup IRQ stack
-	ldr	sp, IRQ_STACK_START
-	.endm
-
-	.macro get_fiq_stack			@ setup FIQ stack
-	ldr	sp, FIQ_STACK_START
-	.endm
-
-/*
- * exception handlers
- */
-	.align  5
-.globl undefined_instruction
-undefined_instruction:
-	get_bad_stack
-	bad_save_user_regs
-	bl	do_undefined_instruction
-
-	.align	5
-.globl software_interrupt
-software_interrupt:
-	get_bad_stack
-	bad_save_user_regs
-	bl	do_software_interrupt
-
-	.align	5
-.globl prefetch_abort
-prefetch_abort:
-	get_bad_stack
-	bad_save_user_regs
-	bl	do_prefetch_abort
-
-	.align	5
-.globl data_abort
-data_abort:
-	get_bad_stack
-	bad_save_user_regs
-	bl	do_data_abort
-
-	.align	5
-.globl not_used
-not_used:
-	get_bad_stack
-	bad_save_user_regs
-	bl	do_not_used
-
-#ifdef CONFIG_USE_IRQ
-	.align	5
-.globl irq
-irq:
-	get_irq_stack
-	irq_save_user_regs
-	bl	do_irq
-	irq_restore_user_regs
-
-	.align	5
-.globl fiq
-fiq:
-	get_fiq_stack
-	/* someone ought to write a more effiction fiq_save_user_regs */
-	irq_save_user_regs
-	bl	do_fiq
-	irq_restore_user_regs
-
-#else
-
-	.align	5
-.globl irq
-irq:
-	get_bad_stack
-	bad_save_user_regs
-	bl	do_irq
-
-	.align	5
-.globl fiq
-fiq:
-	get_bad_stack
-	bad_save_user_regs
-	bl	do_fiq
-
-#endif
diff --git a/arch/arm/cpu/arm_intcm/u-boot.lds b/arch/arm/cpu/arm_intcm/u-boot.lds
deleted file mode 100644
index 3b5c18d..0000000
--- a/arch/arm/cpu/arm_intcm/u-boot.lds
+++ /dev/null
@@ -1,78 +0,0 @@
-/*
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-ENTRY(_start)
-SECTIONS
-{
-	. = 0x00000000;
-
-	. = ALIGN(4);
-	.text :
-	{
-		arch/arm/cpu/arm_intcm/start.o	(.text)
-		*(.text)
-	}
-
-	. = ALIGN(4);
-	.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
-
-	. = ALIGN(4);
-	.data : {
-		*(.data)
-	}
-
-	. = ALIGN(4);
-
-	. = .;
-	__u_boot_cmd_start = .;
-	.u_boot_cmd : { *(.u_boot_cmd) }
-	__u_boot_cmd_end = .;
-
-	. = ALIGN(4);
-
-	.rel.dyn : {
-		__rel_dyn_start = .;
-		*(.rel*)
-		__rel_dyn_end = .;
-	}
-
-	.dynsym : {
-		__dynsym_start = .;
-		*(.dynsym)
-	}
-
-	.bss __rel_dyn_start (OVERLAY) : {
-		__bss_start = .;
-		*(.bss)
-		 . = ALIGN(4);
-		_end = .;
-	}
-
-	/DISCARD/ : { *(.dynstr*) }
-	/DISCARD/ : { *(.dynamic*) }
-	/DISCARD/ : { *(.plt*) }
-	/DISCARD/ : { *(.interp*) }
-	/DISCARD/ : { *(.gnu*) }
-}
diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile
deleted file mode 100644
index 8c0e915..0000000
--- a/arch/arm/cpu/armv7/Makefile
+++ /dev/null
@@ -1,48 +0,0 @@
-#
-# (C) Copyright 2000-2003
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(CPU).o
-
-START	:= start.o
-COBJS	:= cpu.o
-COBJS  += syslib.o
-
-SRCS	:= $(START:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-START	:= $(addprefix $(obj),$(START))
-
-all:	$(obj).depend $(START) $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/arch/arm/cpu/armv7/config.mk b/arch/arm/cpu/armv7/config.mk
deleted file mode 100644
index 49ac9c7..0000000
--- a/arch/arm/cpu/armv7/config.mk
+++ /dev/null
@@ -1,33 +0,0 @@
-#
-# (C) Copyright 2002
-# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float
-
-# Make ARMv5 to allow more compilers to work, even though its v7a.
-PLATFORM_CPPFLAGS += -march=armv5
-# =========================================================================
-#
-# Supply options according to compiler version
-#
-# =========================================================================
-PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,\
-		    $(call cc-option,-malignment-traps,))
diff --git a/arch/arm/cpu/armv7/cpu.c b/arch/arm/cpu/armv7/cpu.c
deleted file mode 100644
index a01e0d6..0000000
--- a/arch/arm/cpu/armv7/cpu.c
+++ /dev/null
@@ -1,83 +0,0 @@
-/*
- * (C) Copyright 2008 Texas Insturments
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * CPU specific code
- */
-
-#include <common.h>
-#include <command.h>
-#include <asm/system.h>
-#include <asm/cache.h>
-#ifndef CONFIG_L2_OFF
-#include <asm/arch/sys_proto.h>
-#endif
-
-static void cache_flush(void);
-
-int cleanup_before_linux(void)
-{
-	unsigned int i;
-
-	/*
-	 * this function is called just before we call linux
-	 * it prepares the processor for linux
-	 *
-	 * we turn off caches etc ...
-	 */
-	disable_interrupts();
-
-	/* turn off I/D-cache */
-	icache_disable();
-	dcache_disable();
-
-	/* invalidate I-cache */
-	cache_flush();
-
-#ifndef CONFIG_L2_OFF
-	/* turn off L2 cache */
-	l2_cache_disable();
-	/* invalidate L2 cache also */
-	invalidate_dcache(get_device_type());
-#endif
-	i = 0;
-	/* mem barrier to sync up things */
-	asm("mcr p15, 0, %0, c7, c10, 4": :"r"(i));
-
-#ifndef CONFIG_L2_OFF
-	l2_cache_enable();
-#endif
-
-	return 0;
-}
-
-static void cache_flush(void)
-{
-	asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (0));
-}
diff --git a/arch/arm/cpu/armv7/mx5/Makefile b/arch/arm/cpu/armv7/mx5/Makefile
deleted file mode 100644
index e8be9c9..0000000
--- a/arch/arm/cpu/armv7/mx5/Makefile
+++ /dev/null
@@ -1,48 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# (C) Copyright 2009 Freescale Semiconductor, Inc.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(SOC).o
-
-COBJS	= soc.o clock.o iomux.o timer.o speed.o
-SOBJS = lowlevel_init.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
-
-all:	$(obj).depend $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/arch/arm/cpu/armv7/mx5/clock.c b/arch/arm/cpu/armv7/mx5/clock.c
deleted file mode 100644
index 0b04a88..0000000
--- a/arch/arm/cpu/armv7/mx5/clock.c
+++ /dev/null
@@ -1,294 +0,0 @@
-/*
- * (C) Copyright 2007
- * Sascha Hauer, Pengutronix
- *
- * (C) Copyright 2009 Freescale Semiconductor, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/errno.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/crm_regs.h>
-#include <asm/arch/clock.h>
-
-enum pll_clocks {
-	PLL1_CLOCK = 0,
-	PLL2_CLOCK,
-	PLL3_CLOCK,
-	PLL_CLOCKS,
-};
-
-struct mxc_pll_reg *mxc_plls[PLL_CLOCKS] = {
-	[PLL1_CLOCK] = (struct mxc_pll_reg *)PLL1_BASE_ADDR,
-	[PLL2_CLOCK] = (struct mxc_pll_reg *)PLL2_BASE_ADDR,
-	[PLL3_CLOCK] = (struct mxc_pll_reg *)PLL3_BASE_ADDR,
-};
-
-struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE;
-
-/*
- * Calculate the frequency of this pll.
- */
-static u32 decode_pll(struct mxc_pll_reg *pll, u32 infreq)
-{
-	u32 mfi, mfn, mfd, pd;
-
-	mfn = __raw_readl(&pll->mfn);
-	mfd = __raw_readl(&pll->mfd) + 1;
-	mfi = __raw_readl(&pll->op);
-	pd = (mfi  & 0xF) + 1;
-	mfi = (mfi >> 4) & 0xF;
-	mfi = (mfi >= 5) ? mfi : 5;
-
-	return ((4 * (infreq / 1000) * (mfi * mfd + mfn)) / (mfd * pd)) * 1000;
-}
-
-/*
- * Get mcu main rate
- */
-u32 get_mcu_main_clk(void)
-{
-	u32 reg, freq;
-
-	reg = (__raw_readl(&mxc_ccm->cacrr) & MXC_CCM_CACRR_ARM_PODF_MASK) >>
-		MXC_CCM_CACRR_ARM_PODF_OFFSET;
-	freq = decode_pll(mxc_plls[PLL1_CLOCK], CONFIG_SYS_MX5_HCLK);
-	return freq / (reg + 1);
-}
-
-/*
- * Get the rate of peripheral's root clock.
- */
-static u32 get_periph_clk(void)
-{
-	u32 reg;
-
-	reg = __raw_readl(&mxc_ccm->cbcdr);
-	if (!(reg & MXC_CCM_CBCDR_PERIPH_CLK_SEL))
-		return decode_pll(mxc_plls[PLL2_CLOCK], CONFIG_SYS_MX5_HCLK);
-	reg = __raw_readl(&mxc_ccm->cbcmr);
-	switch ((reg & MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK) >>
-		MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET) {
-	case 0:
-		return decode_pll(mxc_plls[PLL1_CLOCK], CONFIG_SYS_MX5_HCLK);
-	case 1:
-		return decode_pll(mxc_plls[PLL3_CLOCK], CONFIG_SYS_MX5_HCLK);
-	default:
-		return 0;
-	}
-	/* NOTREACHED */
-}
-
-/*
- * Get the rate of ipg clock.
- */
-static u32 get_ipg_clk(void)
-{
-	u32 ahb_podf, ipg_podf;
-
-	ahb_podf = __raw_readl(&mxc_ccm->cbcdr);
-	ipg_podf = (ahb_podf & MXC_CCM_CBCDR_IPG_PODF_MASK) >>
-			MXC_CCM_CBCDR_IPG_PODF_OFFSET;
-	ahb_podf = (ahb_podf & MXC_CCM_CBCDR_AHB_PODF_MASK) >>
-			MXC_CCM_CBCDR_AHB_PODF_OFFSET;
-	return get_periph_clk() / ((ahb_podf + 1) * (ipg_podf + 1));
-}
-
-/*
- * Get the rate of ipg_per clock.
- */
-static u32 get_ipg_per_clk(void)
-{
-	u32 pred1, pred2, podf;
-
-	if (__raw_readl(&mxc_ccm->cbcmr) & MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL)
-		return get_ipg_clk();
-	/* Fixme: not handle what about lpm*/
-	podf = __raw_readl(&mxc_ccm->cbcdr);
-	pred1 = (podf & MXC_CCM_CBCDR_PERCLK_PRED1_MASK) >>
-		MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET;
-	pred2 = (podf & MXC_CCM_CBCDR_PERCLK_PRED2_MASK) >>
-		MXC_CCM_CBCDR_PERCLK_PRED2_OFFSET;
-	podf = (podf & MXC_CCM_CBCDR_PERCLK_PODF_MASK) >>
-		MXC_CCM_CBCDR_PERCLK_PODF_OFFSET;
-
-	return get_periph_clk() / ((pred1 + 1) * (pred2 + 1) * (podf + 1));
-}
-
-/*
- * Get the rate of uart clk.
- */
-static u32 get_uart_clk(void)
-{
-	unsigned int freq, reg, pred, podf;
-
-	reg = __raw_readl(&mxc_ccm->cscmr1);
-	switch ((reg & MXC_CCM_CSCMR1_UART_CLK_SEL_MASK) >>
-		MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET) {
-	case 0x0:
-		freq = decode_pll(mxc_plls[PLL1_CLOCK],
-				    CONFIG_SYS_MX5_HCLK);
-		break;
-	case 0x1:
-		freq = decode_pll(mxc_plls[PLL2_CLOCK],
-				    CONFIG_SYS_MX5_HCLK);
-		break;
-	case 0x2:
-		freq = decode_pll(mxc_plls[PLL3_CLOCK],
-				    CONFIG_SYS_MX5_HCLK);
-		break;
-	default:
-		return 66500000;
-	}
-
-	reg = __raw_readl(&mxc_ccm->cscdr1);
-
-	pred = (reg & MXC_CCM_CSCDR1_UART_CLK_PRED_MASK) >>
-		MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET;
-
-	podf = (reg & MXC_CCM_CSCDR1_UART_CLK_PODF_MASK) >>
-		MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET;
-	freq /= (pred + 1) * (podf + 1);
-
-	return freq;
-}
-
-/*
- * This function returns the low power audio clock.
- */
-u32 get_lp_apm(void)
-{
-	u32 ret_val = 0;
-	u32 ccsr = __raw_readl(&mxc_ccm->ccsr);
-
-	if (((ccsr >> 9) & 1) == 0)
-		ret_val = CONFIG_SYS_MX5_HCLK;
-	else
-		ret_val = ((32768 * 1024));
-
-	return ret_val;
-}
-
-/*
- * get cspi clock rate.
- */
-u32 imx_get_cspiclk(void)
-{
-	u32 ret_val = 0, pdf, pre_pdf, clk_sel;
-	u32 cscmr1 = __raw_readl(&mxc_ccm->cscmr1);
-	u32 cscdr2 = __raw_readl(&mxc_ccm->cscdr2);
-
-	pre_pdf = (cscdr2 & MXC_CCM_CSCDR2_CSPI_CLK_PRED_MASK) \
-			>> MXC_CCM_CSCDR2_CSPI_CLK_PRED_OFFSET;
-	pdf = (cscdr2 & MXC_CCM_CSCDR2_CSPI_CLK_PODF_MASK) \
-			>> MXC_CCM_CSCDR2_CSPI_CLK_PODF_OFFSET;
-	clk_sel = (cscmr1 & MXC_CCM_CSCMR1_CSPI_CLK_SEL_MASK) \
-			>> MXC_CCM_CSCMR1_CSPI_CLK_SEL_OFFSET;
-
-	switch (clk_sel) {
-	case 0:
-		ret_val = decode_pll(mxc_plls[PLL1_CLOCK],
-					CONFIG_SYS_MX5_HCLK) /
-					((pre_pdf + 1) * (pdf + 1));
-		break;
-	case 1:
-		ret_val = decode_pll(mxc_plls[PLL2_CLOCK],
-					CONFIG_SYS_MX5_HCLK) /
-					((pre_pdf + 1) * (pdf + 1));
-		break;
-	case 2:
-		ret_val = decode_pll(mxc_plls[PLL3_CLOCK],
-					CONFIG_SYS_MX5_HCLK) /
-					((pre_pdf + 1) * (pdf + 1));
-		break;
-	default:
-		ret_val = get_lp_apm() / ((pre_pdf + 1) * (pdf + 1));
-		break;
-	}
-
-	return ret_val;
-}
-
-/*
- * The API of get mxc clockes.
- */
-unsigned int mxc_get_clock(enum mxc_clock clk)
-{
-	switch (clk) {
-	case MXC_ARM_CLK:
-		return get_mcu_main_clk();
-	case MXC_AHB_CLK:
-		break;
-	case MXC_IPG_CLK:
-		return get_ipg_clk();
-	case MXC_IPG_PERCLK:
-		return get_ipg_per_clk();
-	case MXC_UART_CLK:
-		return get_uart_clk();
-	case MXC_CSPI_CLK:
-		return imx_get_cspiclk();
-	case MXC_FEC_CLK:
-		return decode_pll(mxc_plls[PLL1_CLOCK],
-				    CONFIG_SYS_MX5_HCLK);
-	default:
-		break;
-	}
-	return -1;
-}
-
-u32 imx_get_uartclk(void)
-{
-	return get_uart_clk();
-}
-
-
-u32 imx_get_fecclk(void)
-{
-	return mxc_get_clock(MXC_IPG_CLK);
-}
-
-/*
- * Dump some core clockes.
- */
-int do_mx5_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-	u32 freq;
-
-	freq = decode_pll(mxc_plls[PLL1_CLOCK], CONFIG_SYS_MX5_HCLK);
-	printf("pll1: %dMHz\n", freq / 1000000);
-	freq = decode_pll(mxc_plls[PLL2_CLOCK], CONFIG_SYS_MX5_HCLK);
-	printf("pll2: %dMHz\n", freq / 1000000);
-	freq = decode_pll(mxc_plls[PLL3_CLOCK], CONFIG_SYS_MX5_HCLK);
-	printf("pll3: %dMHz\n", freq / 1000000);
-	printf("ipg clock     : %dHz\n", mxc_get_clock(MXC_IPG_CLK));
-	printf("ipg per clock : %dHz\n", mxc_get_clock(MXC_IPG_PERCLK));
-
-	return 0;
-}
-
-/***************************************************/
-
-U_BOOT_CMD(
-	clockinfo,	CONFIG_SYS_MAXARGS,	1,	do_mx5_showclocks,
-	"display clocks\n",
-	""
-);
diff --git a/arch/arm/cpu/armv7/mx5/iomux.c b/arch/arm/cpu/armv7/mx5/iomux.c
deleted file mode 100644
index d4e3bbb..0000000
--- a/arch/arm/cpu/armv7/mx5/iomux.c
+++ /dev/null
@@ -1,186 +0,0 @@
-/*
- * (C) Copyright 2009 Freescale Semiconductor, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/mx5x_pins.h>
-#include <asm/arch/iomux.h>
-#include <asm/arch/sys_proto.h>
-
-/* IOMUX register (base) addresses */
-enum iomux_reg_addr {
-	IOMUXGPR0 = IOMUXC_BASE_ADDR,
-	IOMUXGPR1 = IOMUXC_BASE_ADDR + 0x004,
-	IOMUXSW_MUX_CTL = IOMUXC_BASE_ADDR,
-	IOMUXSW_MUX_END = IOMUXC_BASE_ADDR + MUX_I_END,
-	IOMUXSW_PAD_CTL = IOMUXC_BASE_ADDR + PAD_I_START,
-	IOMUXSW_INPUT_CTL = IOMUXC_BASE_ADDR + INPUT_CTL_START,
-};
-
-#define MUX_PIN_NUM_MAX (((MUX_I_END - MUX_I_START) >> 2) + 1)
-
-/* Get the iomux register address of this pin */
-static inline u32 get_mux_reg(iomux_pin_name_t pin)
-{
-	u32 mux_reg = PIN_TO_IOMUX_MUX(pin);
-
-#if defined(CONFIG_MX51)
-	if (is_soc_rev(CHIP_REV_2_0) < 0) {
-		/*
-		 * Fixup register address:
-		 * i.MX51 TO1 has offset with the register
-		 * which is define as TO2.
-		 */
-		if ((pin == MX51_PIN_NANDF_RB5) ||
-			(pin == MX51_PIN_NANDF_RB6) ||
-			(pin == MX51_PIN_NANDF_RB7))
-			; /* Do nothing */
-		else if (mux_reg >= 0x2FC)
-			mux_reg += 8;
-		else if (mux_reg >= 0x130)
-			mux_reg += 0xC;
-	}
-#endif
-	mux_reg += IOMUXSW_MUX_CTL;
-	return mux_reg;
-}
-
-/* Get the pad register address of this pin */
-static inline u32 get_pad_reg(iomux_pin_name_t pin)
-{
-	u32 pad_reg = PIN_TO_IOMUX_PAD(pin);
-
-#if defined(CONFIG_MX51)
-	if (is_soc_rev(CHIP_REV_2_0) < 0) {
-		/*
-		 * Fixup register address:
-		 * i.MX51 TO1 has offset with the register
-		 * which is define as TO2.
-		 */
-		if ((pin == MX51_PIN_NANDF_RB5) ||
-			(pin == MX51_PIN_NANDF_RB6) ||
-			(pin == MX51_PIN_NANDF_RB7))
-			; /* Do nothing */
-		else if (pad_reg == 0x4D0 - PAD_I_START)
-			pad_reg += 0x4C;
-		else if (pad_reg == 0x860 - PAD_I_START)
-			pad_reg += 0x9C;
-		else if (pad_reg >= 0x804 - PAD_I_START)
-			pad_reg += 0xB0;
-		else if (pad_reg >= 0x7FC - PAD_I_START)
-			pad_reg += 0xB4;
-		else if (pad_reg >= 0x4E4 - PAD_I_START)
-			pad_reg += 0xCC;
-		else
-			pad_reg += 8;
-	}
-#endif
-	pad_reg += IOMUXSW_PAD_CTL;
-	return pad_reg;
-}
-
-/* Get the last iomux register address */
-static inline u32 get_mux_end(void)
-{
-#if defined(CONFIG_MX51)
-	if (is_soc_rev(CHIP_REV_2_0) < 0)
-		return IOMUXC_BASE_ADDR + (0x3F8 - 4);
-	else
-		return IOMUXC_BASE_ADDR + (0x3F0 - 4);
-#endif
-	return IOMUXSW_MUX_END;
-}
-
-/*
- * This function is used to configure a pin through the IOMUX module.
- * @param  pin		a pin number as defined in iomux_pin_name_t
- * @param  cfg		an output function as defined in iomux_pin_cfg_t
- *
- * @return 		0 if successful; Non-zero otherwise
- */
-static void iomux_config_mux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg)
-{
-	u32 mux_reg = get_mux_reg(pin);
-
-	if ((mux_reg > get_mux_end()) || (mux_reg < IOMUXSW_MUX_CTL))
-		return ;
-	if (cfg == IOMUX_CONFIG_GPIO)
-		writel(PIN_TO_ALT_GPIO(pin), mux_reg);
-	else
-		writel(cfg, mux_reg);
-}
-
-/*
- * Request ownership for an IO pin. This function has to be the first one
- * being called before that pin is used. The caller has to check the
- * return value to make sure it returns 0.
- *
- * @param  pin		a name defined by iomux_pin_name_t
- * @param  cfg		an input function as defined in iomux_pin_cfg_t
- *
- */
-void mxc_request_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg)
-{
-	iomux_config_mux(pin, cfg);
-}
-
-/*
- * Release ownership for an IO pin
- *
- * @param  pin		a name defined by iomux_pin_name_t
- * @param  cfg		an input function as defined in iomux_pin_cfg_t
- */
-void mxc_free_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg)
-{
-}
-
-/*
- * This function configures the pad value for a IOMUX pin.
- *
- * @param  pin     a pin number as defined in iomux_pin_name_t
- * @param  config  the ORed value of elements defined in iomux_pad_config_t
- */
-void mxc_iomux_set_pad(iomux_pin_name_t pin, u32 config)
-{
-	u32 pad_reg = get_pad_reg(pin);
-	writel(config, pad_reg);
-}
-
-unsigned int mxc_iomux_get_pad(iomux_pin_name_t pin)
-{
-	u32 pad_reg = get_pad_reg(pin);
-	return readl(pad_reg);
-}
-
-/*
- * This function configures daisy-chain
- *
- * @param input    index of input select register
- * @param config   the binary value of elements
- */
-void mxc_iomux_set_input(iomux_input_select_t input, u32 config)
-{
-	u32 reg = IOMUXSW_INPUT_CTL + (input << 2);
-
-	writel(config, reg);
-}
diff --git a/arch/arm/cpu/armv7/mx5/lowlevel_init.S b/arch/arm/cpu/armv7/mx5/lowlevel_init.S
deleted file mode 100644
index 96ebfe2..0000000
--- a/arch/arm/cpu/armv7/mx5/lowlevel_init.S
+++ /dev/null
@@ -1,294 +0,0 @@
-/*
- * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
- *
- * (C) Copyright 2009 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/asm-offsets.h>
-
-/*
- * L2CC Cache setup/invalidation/disable
- */
-.macro init_l2cc
-	/* explicitly disable L2 cache */
-	mrc 15, 0, r0, c1, c0, 1
-	bic r0, r0, #0x2
-	mcr 15, 0, r0, c1, c0, 1
-
-	/* reconfigure L2 cache aux control reg */
-	mov r0, #0xC0			/* tag RAM */
-	add r0, r0, #0x4		/* data RAM */
-	orr r0, r0, #(1 << 24)		/* disable write allocate delay */
-	orr r0, r0, #(1 << 23)		/* disable write allocate combine */
-	orr r0, r0, #(1 << 22)		/* disable write allocate */
-
-	cmp r3, #0x10    /* r3 contains the silicon rev */
-
-	/* disable write combine for TO 2 and lower revs */
-	orrls r0, r0, #(1 << 25)
-
-	mcr 15, 1, r0, c9, c0, 2
-.endm /* init_l2cc */
-
-/* AIPS setup - Only setup MPROTx registers.
- * The PACR default values are good.*/
-.macro init_aips
-	/*
-	 * Set all MPROTx to be non-bufferable, trusted for R/W,
-	 * not forced to user-mode.
-	 */
-	ldr r0, =AIPS1_BASE_ADDR
-	ldr r1, =0x77777777
-	str r1, [r0, #0x0]
-	str r1, [r0, #0x4]
-	ldr r0, =AIPS2_BASE_ADDR
-	str r1, [r0, #0x0]
-	str r1, [r0, #0x4]
-	/*
-	 * Clear the on and off peripheral modules Supervisor Protect bit
-	 * for SDMA to access them. Did not change the AIPS control registers
-	 * (offset 0x20) access type
-	 */
-.endm /* init_aips */
-
-/* M4IF setup */
-.macro init_m4if
-#ifdef CONFIG_MX51
-	/* VPU and IPU given higher priority (0x4)
-	 * IPU accesses with ID=0x1 given highest priority (=0xA)
-	 */
-	ldr r0, =M4IF_BASE_ADDR
-
-	ldr r1, =0x00000203
-	str r1, [r0, #0x40]
-
-	ldr r1, =0x0
-	str r1, [r0, #0x44]
-
-	ldr r1, =0x00120125
-	str r1, [r0, #0x9C]
-
-	ldr r1, =0x001901A3
-	str r1, [r0, #0x48]
-
-#endif
-.endm /* init_m4if */
-
-.macro setup_pll pll, freq
-	ldr r0, =\pll
-	ldr r1, =0x00001232
-	str r1, [r0, #PLL_DP_CTL] /* Set DPLL ON (set UPEN bit): BRMO=1 */
-	mov r1, #0x2
-	str r1, [r0, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */
-
-	ldr r1, W_DP_OP_\freq
-	str r1, [r0, #PLL_DP_OP]
-	str r1, [r0, #PLL_DP_HFS_OP]
-
-	ldr r1,	W_DP_MFD_\freq
-	str r1, [r0, #PLL_DP_MFD]
-	str r1, [r0, #PLL_DP_HFS_MFD]
-
-	ldr r1,  W_DP_MFN_\freq
-	str r1, [r0, #PLL_DP_MFN]
-	str r1, [r0, #PLL_DP_HFS_MFN]
-
-	ldr r1, =0x00001232
-	str r1, [r0, #PLL_DP_CTL]
-1:	ldr r1, [r0, #PLL_DP_CTL]
-	ands r1, r1, #0x1
-	beq 1b
-.endm
-
-.macro init_clock
-	ldr r0, =CCM_BASE_ADDR
-
-#if defined(CONFIG_MX51)
-	/* Gate of clocks to the peripherals first */
-	ldr r1, =0x3FFFFFFF
-	str r1, [r0, #CLKCTL_CCGR0]
-	ldr r1, =0x0
-	str r1, [r0, #CLKCTL_CCGR1]
-	str r1, [r0, #CLKCTL_CCGR2]
-	str r1, [r0, #CLKCTL_CCGR3]
-
-	ldr r1, =0x00030000
-	str r1, [r0, #CLKCTL_CCGR4]
-	ldr r1, =0x00FFF030
-	str r1, [r0, #CLKCTL_CCGR5]
-	ldr r1, =0x00000300
-	str r1, [r0, #CLKCTL_CCGR6]
-
-	/* Disable IPU and HSC dividers */
-	mov r1, #0x60000
-	str r1, [r0, #CLKCTL_CCDR]
-
-	/* Make sure to switch the DDR away from PLL 1 */
-	ldr r1, =0x19239145
-	str r1, [r0, #CLKCTL_CBCDR]
-	/* make sure divider effective */
-1:	ldr r1, [r0, #CLKCTL_CDHIPR]
-	cmp r1, #0x0
-	bne 1b
-#endif
-
-	/* Switch ARM to step clock */
-	mov r1, #0x4
-	str r1, [r0, #CLKCTL_CCSR]
-
-	setup_pll PLL1_BASE_ADDR, 800
-
-#if defined(CONFIG_MX51)
-	setup_pll PLL3_BASE_ADDR, 665
-
-	/* Switch peripheral to PLL 3 */
-	ldr r0, =CCM_BASE_ADDR
-	ldr r1, =0x000010C0
-	orr r1,r1,#CONFIG_SYS_DDR_CLKSEL
-	str r1, [r0, #CLKCTL_CBCMR]
-	ldr r1, =0x13239145
-	str r1, [r0, #CLKCTL_CBCDR]
-	setup_pll PLL2_BASE_ADDR, 665
-
-	/* Switch peripheral to PLL2 */
-	ldr r0, =CCM_BASE_ADDR
-	ldr r1, =0x19239145
-	str r1, [r0, #CLKCTL_CBCDR]
-	ldr r1, =0x000020C0
-	orr r1,r1,#CONFIG_SYS_DDR_CLKSEL
-	str r1, [r0, #CLKCTL_CBCMR]
-#endif
-	setup_pll PLL3_BASE_ADDR, 216
-
-	/* Set the platform clock dividers */
-	ldr r0, =ARM_BASE_ADDR
-	ldr r1, =0x00000725
-	str r1, [r0, #0x14]
-
-	ldr r0, =CCM_BASE_ADDR
-
-#if defined(CONFIG_MX51)
-	/* Run 3.0 at Full speed, for other TO's wait till we increase VDDGP */
-	ldr r1, =0x0
-	ldr r3, [r1, #ROM_SI_REV]
-	cmp r3, #0x10
-	movls r1, #0x1
-	movhi r1, #0
-#else
-	mov r1, #0
-
-#endif
-	str r1, [r0, #CLKCTL_CACRR]
-	/* Switch ARM back to PLL 1 */
-	mov r1, #0
-	str r1, [r0, #CLKCTL_CCSR]
-
-#if defined(CONFIG_MX51)
-	/* setup the rest */
-	/* Use lp_apm (24MHz) source for perclk */
-	ldr r1, =0x000020C2
-	orr r1,r1,#CONFIG_SYS_DDR_CLKSEL
-	str r1, [r0, #CLKCTL_CBCMR]
-	/* ddr clock from PLL 1, all perclk dividers are 1 since using 24MHz */
-	ldr r1, =CONFIG_SYS_CLKTL_CBCDR
-	str r1, [r0, #CLKCTL_CBCDR]
-#endif
-
-	/* Restore the default values in the Gate registers */
-	ldr r1, =0xFFFFFFFF
-	str r1, [r0, #CLKCTL_CCGR0]
-	str r1, [r0, #CLKCTL_CCGR1]
-	str r1, [r0, #CLKCTL_CCGR2]
-	str r1, [r0, #CLKCTL_CCGR3]
-	str r1, [r0, #CLKCTL_CCGR4]
-	str r1, [r0, #CLKCTL_CCGR5]
-	str r1, [r0, #CLKCTL_CCGR6]
-#if defined(CONFIG_MX53)
-	str r1, [r0, #CLKCTL_CCGR7]
-#endif
-
-#if defined(CONFIG_MX51)
-	/* Use PLL 2 for UART's, get 66.5MHz from it */
-	ldr r1, =0xA5A2A020
-	str r1, [r0, #CLKCTL_CSCMR1]
-	ldr r1, =0x00C30321
-	str r1, [r0, #CLKCTL_CSCDR1]
-#elif defined(CONFIG_MX53)
-	ldr r1, [r0, #CLKCTL_CSCDR1]
-	orr r1, r1, #0x3f
-	eor r1, r1, #0x3f
-	orr r1, r1, #0x21
-	str r1, [r0, #CLKCTL_CSCDR1]
-#endif
-	/* make sure divider effective */
-1:	ldr r1, [r0, #CLKCTL_CDHIPR]
-	cmp r1, #0x0
-	bne 1b
-
-	mov r1, #0x0
-	str r1, [r0, #CLKCTL_CCDR]
-
-	/* for cko - for ARM div by 8 */
-	mov r1, #0x000A0000
-	add r1, r1, #0x00000F0
-	str r1, [r0, #CLKCTL_CCOSR]
-.endm
-
-.macro setup_wdog
-	ldr r0, =WDOG1_BASE_ADDR
-	mov r1, #0x30
-	strh r1, [r0]
-.endm
-
-.section ".text.init", "x"
-
-.globl lowlevel_init
-lowlevel_init:
-#if defined(CONFIG_MX51)
-	ldr r0, =GPIO1_BASE_ADDR
-	ldr r1, [r0, #0x0]
-	orr r1, r1, #(1 << 23)
-	str r1, [r0, #0x0]
-	ldr r1, [r0, #0x4]
-	orr r1, r1, #(1 << 23)
-	str r1, [r0, #0x4]
-#endif
-
-	init_l2cc
-
-	init_aips
-
-	init_m4if
-
-	init_clock
-
-	/* r12 saved upper lr*/
-	mov pc,lr
-
-/* Board level setting value */
-W_DP_OP_800:              .word DP_OP_800
-W_DP_MFD_800:             .word DP_MFD_800
-W_DP_MFN_800:             .word DP_MFN_800
-W_DP_OP_665:              .word DP_OP_665
-W_DP_MFD_665:             .word DP_MFD_665
-W_DP_MFN_665:             .word DP_MFN_665
-W_DP_OP_216:              .word DP_OP_216
-W_DP_MFD_216:             .word DP_MFD_216
-W_DP_MFN_216:             .word DP_MFN_216
diff --git a/arch/arm/cpu/armv7/mx5/soc.c b/arch/arm/cpu/armv7/mx5/soc.c
deleted file mode 100644
index 09500b3..0000000
--- a/arch/arm/cpu/armv7/mx5/soc.c
+++ /dev/null
@@ -1,146 +0,0 @@
-/*
- * (C) Copyright 2007
- * Sascha Hauer, Pengutronix
- *
- * (C) Copyright 2009 Freescale Semiconductor, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/clock.h>
-#include <asm/errno.h>
-#include <asm/io.h>
-
-#ifdef CONFIG_FSL_ESDHC
-#include <fsl_esdhc.h>
-#endif
-
-#if !(defined(CONFIG_MX51) || defined(CONFIG_MX53))
-#error "CPU_TYPE not defined"
-#endif
-
-u32 get_cpu_rev(void)
-{
-#ifdef CONFIG_MX51
-	int system_rev = 0x51000;
-#else
-	int system_rev = 0x53000;
-#endif
-	int reg = __raw_readl(ROM_SI_REV);
-
-#if defined(CONFIG_MX51)
-	switch (reg) {
-	case 0x02:
-		system_rev |= CHIP_REV_1_1;
-		break;
-	case 0x10:
-		if ((__raw_readl(GPIO1_BASE_ADDR + 0x0) & (0x1 << 22)) == 0)
-			system_rev |= CHIP_REV_2_5;
-		else
-			system_rev |= CHIP_REV_2_0;
-		break;
-	case 0x20:
-		system_rev |= CHIP_REV_3_0;
-		break;
-	default:
-		system_rev |= CHIP_REV_1_0;
-		break;
-	}
-#else
-	switch (reg) {
-	case 0x20:
-		system_rev |= CHIP_REV_2_0;
-		break;
-	default:
-		system_rev |= CHIP_REV_1_0;
-		break;
-	}
-#endif
-	return system_rev;
-}
-
-
-#if defined(CONFIG_DISPLAY_CPUINFO)
-int print_cpuinfo(void)
-{
-	u32 cpurev;
-
-	cpurev = get_cpu_rev();
-	printf("CPU:   Freescale i.MX%x family rev%d.%d at %d MHz\n",
-		(cpurev & 0xFF000) >> 12,
-		(cpurev & 0x000F0) >> 4,
-		(cpurev & 0x0000F) >> 0,
-		mxc_get_clock(MXC_ARM_CLK) / 1000000);
-	return 0;
-}
-#endif
-
-/*
- * Initializes on-chip ethernet controllers.
- * to override, implement board_eth_init()
- */
-#if defined(CONFIG_FEC_MXC)
-extern int fecmxc_initialize(bd_t *bis);
-#endif
-
-int cpu_eth_init(bd_t *bis)
-{
-	int rc = -ENODEV;
-
-#if defined(CONFIG_FEC_MXC)
-	rc = fecmxc_initialize(bis);
-#endif
-
-	return rc;
-}
-
-#if defined(CONFIG_FEC_MXC)
-void imx_get_mac_from_fuse(unsigned char *mac)
-{
-	int i;
-	struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
-	struct fuse_bank *bank = &iim->bank[1];
-	struct fuse_bank1_regs *fuse =
-			(struct fuse_bank1_regs *)bank->fuse_regs;
-
-	for (i = 0; i < 6; i++)
-		mac[i] = readl(&fuse->mac_addr[i]) & 0xff;
-}
-#endif
-
-/*
- * Initializes on-chip MMC controllers.
- * to override, implement board_mmc_init()
- */
-int cpu_mmc_init(bd_t *bis)
-{
-#ifdef CONFIG_FSL_ESDHC
-	return fsl_esdhc_mmc_init(bis);
-#else
-	return 0;
-#endif
-}
-
-
-void reset_cpu(ulong addr)
-{
-	__raw_writew(4, WDOG1_BASE_ADDR);
-}
diff --git a/arch/arm/cpu/armv7/mx5/speed.c b/arch/arm/cpu/armv7/mx5/speed.c
deleted file mode 100644
index 2187e8e..0000000
--- a/arch/arm/cpu/armv7/mx5/speed.c
+++ /dev/null
@@ -1,41 +0,0 @@
-/*
- * (C) Copyright 2000-2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
- * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/clock.h>
-
-#ifdef CONFIG_FSL_ESDHC
-DECLARE_GLOBAL_DATA_PTR;
-#endif
-
-int get_clocks(void)
-{
-#ifdef CONFIG_FSL_ESDHC
-	gd->sdhc_clk = mxc_get_clock(MXC_IPG_PERCLK);
-#endif
-	return 0;
-}
diff --git a/arch/arm/cpu/armv7/mx5/timer.c b/arch/arm/cpu/armv7/mx5/timer.c
deleted file mode 100644
index 1972f64..0000000
--- a/arch/arm/cpu/armv7/mx5/timer.c
+++ /dev/null
@@ -1,121 +0,0 @@
-/*
- * (C) Copyright 2007
- * Sascha Hauer, Pengutronix
- *
- * (C) Copyright 2009 Freescale Semiconductor, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/imx-regs.h>
-
-/* General purpose timers registers */
-struct mxc_gpt {
-	unsigned int control;
-	unsigned int prescaler;
-	unsigned int status;
-	unsigned int nouse[6];
-	unsigned int counter;
-};
-
-static struct mxc_gpt *cur_gpt = (struct mxc_gpt *)GPT1_BASE_ADDR;
-
-/* General purpose timers bitfields */
-#define GPTCR_SWR       (1<<15)	/* Software reset */
-#define GPTCR_FRR       (1<<9)	/* Freerun / restart */
-#define GPTCR_CLKSOURCE_32 (4<<6)	/* Clock source */
-#define GPTCR_TEN       (1)	/* Timer enable */
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define timestamp (gd->tbl)
-#define lastinc (gd->lastinc)
-
-int timer_init(void)
-{
-	int i;
-
-	/* setup GP Timer 1 */
-	__raw_writel(GPTCR_SWR, &cur_gpt->control);
-
-	/* We have no udelay by now */
-	for (i = 0; i < 100; i++)
-		__raw_writel(0, &cur_gpt->control);
-
-	__raw_writel(0, &cur_gpt->prescaler); /* 32Khz */
-
-	/* Freerun Mode, PERCLK1 input */
-	i = __raw_readl(&cur_gpt->control);
-	__raw_writel(i | GPTCR_CLKSOURCE_32 | GPTCR_TEN, &cur_gpt->control);
-	reset_timer_masked();
-	return 0;
-}
-
-void reset_timer(void)
-{
-	reset_timer_masked();
-}
-
-void reset_timer_masked(void)
-{
-	ulong val = __raw_readl(&cur_gpt->counter);
-	lastinc = val / (CONFIG_SYS_MX5_CLK32 / CONFIG_SYS_HZ);
-	timestamp = 0;
-}
-
-ulong get_timer_masked(void)
-{
-	ulong val = __raw_readl(&cur_gpt->counter);
-	val /= (CONFIG_SYS_MX5_CLK32 / CONFIG_SYS_HZ);
-	if (val >= lastinc)
-		timestamp += (val - lastinc);
-	else
-		timestamp += ((0xFFFFFFFF / (CONFIG_SYS_MX5_CLK32 / CONFIG_SYS_HZ))
-				- lastinc) + val;
-	lastinc = val;
-	return timestamp;
-}
-
-ulong get_timer(ulong base)
-{
-	return get_timer_masked() - base;
-}
-
-void set_timer(ulong t)
-{
-	timestamp = t;
-}
-
-/* delay x useconds AND preserve advance timestamp value */
-void __udelay(unsigned long usec)
-{
-	unsigned long now, start, tmo;
-	tmo = usec * (CONFIG_SYS_MX5_CLK32 / 1000) / 1000;
-
-	if (!tmo)
-		tmo = 1;
-
-	now = start = readl(&cur_gpt->counter);
-
-	while ((now - start) < tmo)
-		now = readl(&cur_gpt->counter);
-
-}
diff --git a/arch/arm/cpu/armv7/omap-common/Makefile b/arch/arm/cpu/armv7/omap-common/Makefile
deleted file mode 100644
index dc01ee5..0000000
--- a/arch/arm/cpu/armv7/omap-common/Makefile
+++ /dev/null
@@ -1,47 +0,0 @@
-#
-# (C) Copyright 2000-2003
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)libomap-common.o
-
-SOBJS	:= reset.o
-
-COBJS	:= timer.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
-
-all:	$(obj).depend $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/arch/arm/cpu/armv7/omap-common/config.mk b/arch/arm/cpu/armv7/omap-common/config.mk
deleted file mode 100644
index 49ac9c7..0000000
--- a/arch/arm/cpu/armv7/omap-common/config.mk
+++ /dev/null
@@ -1,33 +0,0 @@
-#
-# (C) Copyright 2002
-# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float
-
-# Make ARMv5 to allow more compilers to work, even though its v7a.
-PLATFORM_CPPFLAGS += -march=armv5
-# =========================================================================
-#
-# Supply options according to compiler version
-#
-# =========================================================================
-PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,\
-		    $(call cc-option,-malignment-traps,))
diff --git a/arch/arm/cpu/armv7/omap-common/reset.S b/arch/arm/cpu/armv7/omap-common/reset.S
deleted file mode 100644
index 838b122..0000000
--- a/arch/arm/cpu/armv7/omap-common/reset.S
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- * Copyright (c) 2009 Samsung Electronics.
- * Minkyu Kang <mk7.kang@samsung.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-
-.global reset_cpu
-reset_cpu:
-	ldr	r1, rstctl			@ get addr for global reset
-						@ reg
-	ldr	r3, rstbit			@ sw reset bit
-	str	r3, [r1]			@ force reset
-	mov	r0, r0
-_loop_forever:
-	b	_loop_forever
-rstctl:
-	.word	PRM_RSTCTRL
-rstbit:
-	.word	PRM_RSTCTRL_RESET
diff --git a/arch/arm/cpu/armv7/omap-common/timer.c b/arch/arm/cpu/armv7/omap-common/timer.c
deleted file mode 100644
index 9beebb1..0000000
--- a/arch/arm/cpu/armv7/omap-common/timer.c
+++ /dev/null
@@ -1,134 +0,0 @@
-/*
- * (C) Copyright 2008
- * Texas Instruments
- *
- * Richard Woodruff <r-woodruff2@ti.com>
- * Syed Moahmmed Khasim <khasim@ti.com>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- * Alex Zuepke <azu@sysgo.de>
- *
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/io.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static struct gptimer *timer_base = (struct gptimer *)CONFIG_SYS_TIMERBASE;
-
-/*
- * Nothing really to do with interrupts, just starts up a counter.
- */
-
-#define TIMER_CLOCK	(V_SCLK / (2 << CONFIG_SYS_PTV))
-#define TIMER_LOAD_VAL	0xffffffff
-
-int timer_init(void)
-{
-	/* start the counter ticking up, reload value on overflow */
-	writel(TIMER_LOAD_VAL, &timer_base->tldr);
-	/* enable timer */
-	writel((CONFIG_SYS_PTV << 2) | TCLR_PRE | TCLR_AR | TCLR_ST,
-		&timer_base->tclr);
-
-	reset_timer_masked();	/* init the timestamp and lastinc value */
-
-	return 0;
-}
-
-/*
- * timer without interrupts
- */
-void reset_timer(void)
-{
-	reset_timer_masked();
-}
-
-ulong get_timer(ulong base)
-{
-	return get_timer_masked() - base;
-}
-
-void set_timer(ulong t)
-{
-	gd->tbl = t;
-}
-
-/* delay x useconds */
-void __udelay(unsigned long usec)
-{
-	long tmo = usec * (TIMER_CLOCK / 1000) / 1000;
-	unsigned long now, last = readl(&timer_base->tcrr);
-
-	while (tmo > 0) {
-		now = readl(&timer_base->tcrr);
-		if (last > now) /* count up timer overflow */
-			tmo -= TIMER_LOAD_VAL - last + now;
-		else
-			tmo -= now - last;
-		last = now;
-	}
-}
-
-void reset_timer_masked(void)
-{
-	/* reset time, capture current incrementer value time */
-	gd->lastinc = readl(&timer_base->tcrr) / (TIMER_CLOCK / CONFIG_SYS_HZ);
-	gd->tbl = 0;		/* start "advancing" time stamp from 0 */
-}
-
-ulong get_timer_masked(void)
-{
-	/* current tick value */
-	ulong now = readl(&timer_base->tcrr) / (TIMER_CLOCK / CONFIG_SYS_HZ);
-
-	if (now >= gd->lastinc)	/* normal mode (non roll) */
-		/* move stamp fordward with absoulte diff ticks */
-		gd->tbl += (now - gd->lastinc);
-	else	/* we have rollover of incrementer */
-		gd->tbl += ((TIMER_LOAD_VAL / (TIMER_CLOCK / CONFIG_SYS_HZ))
-			     - gd->lastinc) + now;
-	gd->lastinc = now;
-	return gd->tbl;
-}
-
-/*
- * This function is derived from PowerPC code (read timebase as long long).
- * On ARM it just returns the timer value.
- */
-unsigned long long get_ticks(void)
-{
-	return get_timer(0);
-}
-
-/*
- * This function is derived from PowerPC code (timebase clock frequency).
- * On ARM it returns the number of timer ticks per second.
- */
-ulong get_tbclk(void)
-{
-	return CONFIG_SYS_HZ;
-}
diff --git a/arch/arm/cpu/armv7/omap3/Makefile b/arch/arm/cpu/armv7/omap3/Makefile
deleted file mode 100644
index 7164d50..0000000
--- a/arch/arm/cpu/armv7/omap3/Makefile
+++ /dev/null
@@ -1,55 +0,0 @@
-#
-# (C) Copyright 2000-2003
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB	=  $(obj)lib$(SOC).o
-
-SOBJS	:= lowlevel_init.o
-SOBJS	+= cache.o
-
-COBJS	+= board.o
-COBJS	+= clock.o
-COBJS	+= gpio.o
-COBJS	+= mem.o
-COBJS	+= sys_info.o
-
-COBJS-$(CONFIG_EMIF4)	+= emif4.o
-COBJS-$(CONFIG_SDRC)	+= sdrc.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS) $(COBJS-y) $(SOBJS))
-
-all:	 $(obj).depend $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/arch/arm/cpu/armv7/omap3/board.c b/arch/arm/cpu/armv7/omap3/board.c
deleted file mode 100644
index 6c2a132..0000000
--- a/arch/arm/cpu/armv7/omap3/board.c
+++ /dev/null
@@ -1,294 +0,0 @@
-/*
- *
- * Common board functions for OMAP3 based boards.
- *
- * (C) Copyright 2004-2008
- * Texas Instruments, <www.ti.com>
- *
- * Author :
- *      Sunil Kumar <sunilsaini05@gmail.com>
- *      Shashi Ranjan <shashiranjanmca05@gmail.com>
- *
- * Derived from Beagle Board and 3430 SDP code by
- *      Richard Woodruff <r-woodruff2@ti.com>
- *      Syed Mohammed Khasim <khasim@ti.com>
- *
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/mem.h>
-#include <asm/cache.h>
-
-extern omap3_sysinfo sysinfo;
-
-/******************************************************************************
- * Routine: delay
- * Description: spinning delay to use before udelay works
- *****************************************************************************/
-static inline void delay(unsigned long loops)
-{
-	__asm__ volatile ("1:\n" "subs %0, %1, #1\n"
-			  "bne 1b":"=r" (loops):"0"(loops));
-}
-
-/******************************************************************************
- * Routine: secure_unlock
- * Description: Setup security registers for access
- *              (GP Device only)
- *****************************************************************************/
-void secure_unlock_mem(void)
-{
-	struct pm *pm_rt_ape_base = (struct pm *)PM_RT_APE_BASE_ADDR_ARM;
-	struct pm *pm_gpmc_base = (struct pm *)PM_GPMC_BASE_ADDR_ARM;
-	struct pm *pm_ocm_ram_base = (struct pm *)PM_OCM_RAM_BASE_ADDR_ARM;
-	struct pm *pm_iva2_base = (struct pm *)PM_IVA2_BASE_ADDR_ARM;
-	struct sms *sms_base = (struct sms *)OMAP34XX_SMS_BASE;
-
-	/* Protection Module Register Target APE (PM_RT) */
-	writel(UNLOCK_1, &pm_rt_ape_base->req_info_permission_1);
-	writel(UNLOCK_1, &pm_rt_ape_base->read_permission_0);
-	writel(UNLOCK_1, &pm_rt_ape_base->wirte_permission_0);
-	writel(UNLOCK_2, &pm_rt_ape_base->addr_match_1);
-
-	writel(UNLOCK_3, &pm_gpmc_base->req_info_permission_0);
-	writel(UNLOCK_3, &pm_gpmc_base->read_permission_0);
-	writel(UNLOCK_3, &pm_gpmc_base->wirte_permission_0);
-
-	writel(UNLOCK_3, &pm_ocm_ram_base->req_info_permission_0);
-	writel(UNLOCK_3, &pm_ocm_ram_base->read_permission_0);
-	writel(UNLOCK_3, &pm_ocm_ram_base->wirte_permission_0);
-	writel(UNLOCK_2, &pm_ocm_ram_base->addr_match_2);
-
-	/* IVA Changes */
-	writel(UNLOCK_3, &pm_iva2_base->req_info_permission_0);
-	writel(UNLOCK_3, &pm_iva2_base->read_permission_0);
-	writel(UNLOCK_3, &pm_iva2_base->wirte_permission_0);
-
-	/* SDRC region 0 public */
-	writel(UNLOCK_1, &sms_base->rg_att0);
-}
-
-/******************************************************************************
- * Routine: secureworld_exit()
- * Description: If chip is EMU and boot type is external
- *		configure secure registers and exit secure world
- *              general use.
- *****************************************************************************/
-void secureworld_exit()
-{
-	unsigned long i;
-
-	/* configrue non-secure access control register */
-	__asm__ __volatile__("mrc p15, 0, %0, c1, c1, 2":"=r"(i));
-	/* enabling co-processor CP10 and CP11 accesses in NS world */
-	__asm__ __volatile__("orr %0, %0, #0xC00":"=r"(i));
-	/*
-	 * allow allocation of locked TLBs and L2 lines in NS world
-	 * allow use of PLE registers in NS world also
-	 */
-	__asm__ __volatile__("orr %0, %0, #0x70000":"=r"(i));
-	__asm__ __volatile__("mcr p15, 0, %0, c1, c1, 2":"=r"(i));
-
-	/* Enable ASA in ACR register */
-	__asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i));
-	__asm__ __volatile__("orr %0, %0, #0x10":"=r"(i));
-	__asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i));
-
-	/* Exiting secure world */
-	__asm__ __volatile__("mrc p15, 0, %0, c1, c1, 0":"=r"(i));
-	__asm__ __volatile__("orr %0, %0, #0x31":"=r"(i));
-	__asm__ __volatile__("mcr p15, 0, %0, c1, c1, 0":"=r"(i));
-}
-
-/******************************************************************************
- * Routine: try_unlock_sram()
- * Description: If chip is GP/EMU(special) type, unlock the SRAM for
- *              general use.
- *****************************************************************************/
-void try_unlock_memory()
-{
-	int mode;
-	int in_sdram = is_running_in_sdram();
-
-	/*
-	 * if GP device unlock device SRAM for general use
-	 * secure code breaks for Secure/Emulation device - HS/E/T
-	 */
-	mode = get_device_type();
-	if (mode == GP_DEVICE)
-		secure_unlock_mem();
-
-	/*
-	 * If device is EMU and boot is XIP external booting
-	 * Unlock firewalls and disable L2 and put chip
-	 * out of secure world
-	 *
-	 * Assuming memories are unlocked by the demon who put us in SDRAM
-	 */
-	if ((mode <= EMU_DEVICE) && (get_boot_type() == 0x1F)
-	    && (!in_sdram)) {
-		secure_unlock_mem();
-		secureworld_exit();
-	}
-
-	return;
-}
-
-/******************************************************************************
- * Routine: s_init
- * Description: Does early system init of muxing and clocks.
- *              - Called path is with SRAM stack.
- *****************************************************************************/
-void s_init(void)
-{
-	int in_sdram = is_running_in_sdram();
-
-	watchdog_init();
-
-	try_unlock_memory();
-
-	/*
-	 * Right now flushing at low MPU speed.
-	 * Need to move after clock init
-	 */
-	invalidate_dcache(get_device_type());
-#ifndef CONFIG_ICACHE_OFF
-	icache_enable();
-#endif
-
-#ifdef CONFIG_L2_OFF
-	l2_cache_disable();
-#else
-	l2_cache_enable();
-#endif
-	/*
-	 * Writing to AuxCR in U-boot using SMI for GP DEV
-	 * Currently SMI in Kernel on ES2 devices seems to have an issue
-	 * Once that is resolved, we can postpone this config to kernel
-	 */
-	if (get_device_type() == GP_DEVICE)
-		setup_auxcr();
-
-	set_muxconf_regs();
-	delay(100);
-
-	prcm_init();
-
-	per_clocks_enable();
-
-	if (!in_sdram)
-		mem_init();
-}
-
-/******************************************************************************
- * Routine: wait_for_command_complete
- * Description: Wait for posting to finish on watchdog
- *****************************************************************************/
-void wait_for_command_complete(struct watchdog *wd_base)
-{
-	int pending = 1;
-	do {
-		pending = readl(&wd_base->wwps);
-	} while (pending);
-}
-
-/******************************************************************************
- * Routine: watchdog_init
- * Description: Shut down watch dogs
- *****************************************************************************/
-void watchdog_init(void)
-{
-	struct watchdog *wd2_base = (struct watchdog *)WD2_BASE;
-	struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
-
-	/*
-	 * There are 3 watch dogs WD1=Secure, WD2=MPU, WD3=IVA. WD1 is
-	 * either taken care of by ROM (HS/EMU) or not accessible (GP).
-	 * We need to take care of WD2-MPU or take a PRCM reset. WD3
-	 * should not be running and does not generate a PRCM reset.
-	 */
-
-	sr32(&prcm_base->fclken_wkup, 5, 1, 1);
-	sr32(&prcm_base->iclken_wkup, 5, 1, 1);
-	wait_on_value(ST_WDT2, 0x20, &prcm_base->idlest_wkup, 5);
-
-	writel(WD_UNLOCK1, &wd2_base->wspr);
-	wait_for_command_complete(wd2_base);
-	writel(WD_UNLOCK2, &wd2_base->wspr);
-}
-
-/******************************************************************************
- * Dummy function to handle errors for EABI incompatibility
- *****************************************************************************/
-void abort(void)
-{
-}
-
-#ifdef CONFIG_NAND_OMAP_GPMC
-/******************************************************************************
- * OMAP3 specific command to switch between NAND HW and SW ecc
- *****************************************************************************/
-static int do_switch_ecc(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
-{
-	if (argc != 2)
-		goto usage;
-	if (strncmp(argv[1], "hw", 2) == 0)
-		omap_nand_switch_ecc(1);
-	else if (strncmp(argv[1], "sw", 2) == 0)
-		omap_nand_switch_ecc(0);
-	else
-		goto usage;
-
-	return 0;
-
-usage:
-	printf ("Usage: nandecc %s\n", cmdtp->usage);
-	return 1;
-}
-
-U_BOOT_CMD(
-	nandecc, 2, 1,	do_switch_ecc,
-	"switch OMAP3 NAND ECC calculation algorithm",
-	"[hw/sw] - Switch between NAND hardware (hw) or software (sw) ecc algorithm"
-);
-
-#endif /* CONFIG_NAND_OMAP_GPMC */
-
-#ifdef CONFIG_DISPLAY_BOARDINFO
-/**
- * Print board information
- */
-int checkboard (void)
-{
-	char *mem_s ;
-
-	if (is_mem_sdr())
-		mem_s = "mSDR";
-	else
-		mem_s = "LPDDR";
-
-	printf("%s + %s/%s\n", sysinfo.board_string, mem_s,
-			sysinfo.nand_string);
-
-	return 0;
-}
-#endif	/* CONFIG_DISPLAY_BOARDINFO */
diff --git a/arch/arm/cpu/armv7/omap3/cache.S b/arch/arm/cpu/armv7/omap3/cache.S
deleted file mode 100644
index cda87ba..0000000
--- a/arch/arm/cpu/armv7/omap3/cache.S
+++ /dev/null
@@ -1,263 +0,0 @@
-/*
- * Copyright (c) 2009 Wind River Systems, Inc.
- * Tom Rix <Tom.Rix@windriver.com>
- *
- * This file is based on and replaces the existing cache.c file
- * The copyrights for the cache.c file are:
- *
- * (C) Copyright 2008 Texas Insturments
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <asm/arch/omap3.h>
-
-/*
- * omap3 cache code
- */
-
-.align 5
-.global invalidate_dcache
-.global l2_cache_enable
-.global l2_cache_disable
-.global setup_auxcr
-
-/*
- *	invalidate_dcache()
- *
- *	Invalidate the whole D-cache.
- *
- *	Corrupted registers: r0-r5, r7, r9-r11
- *
- *	- mm	- mm_struct describing address space
- */
-invalidate_dcache:
-	stmfd	r13!, {r0 - r5, r7, r9 - r12, r14}
-
-	mov	r7, r0				@ take a backup of device type
-	cmp	r0, #0x3			@ check if the device type is
-						@ GP
-	moveq r12, #0x1				@ set up to invalide L2
-smi:	.word 0x01600070			@ Call SMI monitor (smieq)
-	cmp	r7, #0x3			@ compare again in case its
-						@ lost
-	beq	finished_inval			@ if GP device, inval done
-						@ above
-
-	mrc	p15, 1, r0, c0, c0, 1		@ read clidr
-	ands	r3, r0, #0x7000000		@ extract loc from clidr
-	mov	r3, r3, lsr #23			@ left align loc bit field
-	beq	finished_inval			@ if loc is 0, then no need to
-						@ clean
-	mov	r10, #0				@ start clean at cache level 0
-inval_loop1:
-	add	r2, r10, r10, lsr #1		@ work out 3x current cache
-						@ level
-	mov	r1, r0, lsr r2			@ extract cache type bits from
-						@ clidr
-	and	r1, r1, #7			@ mask of the bits for current
-						@ cache only
-	cmp	r1, #2				@ see what cache we have at
-						@ this level
-	blt	skip_inval			@ skip if no cache, or just
-						@ i-cache
-	mcr	p15, 2, r10, c0, c0, 0		@ select current cache level
-						@ in cssr
-	mov	r2, #0				@ operand for mcr SBZ
-	mcr	p15, 0, r2, c7, c5, 4		@ flush prefetch buffer to
-						@ sych the new cssr&csidr,
-						@ with armv7 this is 'isb',
-						@ but we compile with armv5
-	mrc	p15, 1, r1, c0, c0, 0		@ read the new csidr
-	and	r2, r1, #7			@ extract the length of the
-						@ cache lines
-	add	r2, r2, #4			@ add 4 (line length offset)
-	ldr	r4, =0x3ff
-	ands	r4, r4, r1, lsr #3		@ find maximum number on the
-						@ way size
-	clz	r5, r4				@ find bit position of way
-						@ size increment
-	ldr	r7, =0x7fff
-	ands	r7, r7, r1, lsr #13		@ extract max number of the
-						@ index size
-inval_loop2:
-	mov	r9, r4				@ create working copy of max
-						@ way size
-inval_loop3:
-	orr	r11, r10, r9, lsl r5		@ factor way and cache number
-						@ into r11
-	orr	r11, r11, r7, lsl r2		@ factor index number into r11
-	mcr	p15, 0, r11, c7, c6, 2		@ invalidate by set/way
-	subs	r9, r9, #1			@ decrement the way
-	bge	inval_loop3
-	subs	r7, r7, #1			@ decrement the index
-	bge	inval_loop2
-skip_inval:
-	add	r10, r10, #2			@ increment cache number
-	cmp	r3, r10
-	bgt	inval_loop1
-finished_inval:
-	mov	r10, #0				@ swith back to cache level 0
-	mcr	p15, 2, r10, c0, c0, 0		@ select current cache level
-						@ in cssr
-	mcr	p15, 0, r10, c7, c5, 4		@ flush prefetch buffer,
-						@ with armv7 this is 'isb',
-						@ but we compile with armv5
-
-	ldmfd	r13!, {r0 - r5, r7, r9 - r12, pc}
-
-l2_cache_set:
-	stmfd	r13!, {r4 - r6, lr}
-	mov	r5,  r0
-	bl	get_cpu_rev
-	mov	r4,  r0
-	bl	get_cpu_family
-	@ ES2 onwards we can disable/enable L2 ourselves
-	cmp	r0,  #CPU_OMAP34XX
-	cmpeq	r4,  #CPU_3XX_ES10
-	mrc	15, 0, r0, cr1, cr0, 1
-	bic	r0, r0, #2
-	orr	r0, r0, r5, lsl #1
-	mcreq	15, 0, r0, cr1, cr0, 1
-	@ GP Device ROM code API usage here
-	@ r12 = AUXCR Write function and r0 value
-	mov	ip, #3
-	@ SMCNE instruction to call ROM Code API
-	.word	0x11600070
-	ldmfd	r13!, {r4 - r6, pc}
-
-l2_cache_enable:
-	mov	r0, #1
-	b	l2_cache_set
-
-l2_cache_disable:
-	mov	r0, #0
-	b	l2_cache_set
-
-/******************************************************************************
- * Routine: setup_auxcr()
- * Description: Write to AuxCR desired value using SMI.
- *              general use.
- *****************************************************************************/
-setup_auxcr:
-	mrc	p15, 0, r0, c0, c0, 0		@ read main ID register
-	and	r2, r0, #0x00f00000		@ variant
-	and	r3, r0, #0x0000000f		@ revision
-	orr	r1, r3, r2, lsr #20-4		@ combine variant and revision
-	mov	r12, #0x3
-	mrc	p15, 0, r0, c1, c0, 1
-	orr	r0, r0, #0x10			@ Enable ASA
-	@ Enable L1NEON on pre-r2p1 (erratum 621766 workaround)
-	cmp	r1, #0x21
-	orrlt	r0, r0, #1 << 5
-	.word 0xE1600070			@ SMC
-	mov	r12, #0x2
-	mrc	p15, 1, r0, c9, c0, 2
-	@ Set PLD_FWD bit in L2AUXCR on pre-r2p1 (erratum 725233 workaround)
-	cmp	r1, #0x21
-	orrlt	r0, r0, #1 << 27
-	.word 0xE1600070			@ SMC
-	bx	lr
-
-.align 5
-.global v7_flush_dcache_all
-.global v7_flush_cache_all
-
-/*
- *	v7_flush_dcache_all()
- *
- *	Flush the whole D-cache.
- *
- *	Corrupted registers: r0-r7, r9-r11 (r6 only in Thumb mode)
- *
- *	- mm    - mm_struct describing address space
- */
-v7_flush_dcache_all:
-#	dmb					@ ensure ordering with previous memory accesses
-	mrc	p15, 1, r0, c0, c0, 1		@ read clidr
-	ands	r3, r0, #0x7000000		@ extract loc from clidr
-	mov	r3, r3, lsr #23			@ left align loc bit field
-	beq	finished			@ if loc is 0, then no need to clean
-	mov	r10, #0				@ start clean at cache level 0
-loop1:
-	add	r2, r10, r10, lsr #1		@ work out 3x current cache level
-	mov	r1, r0, lsr r2			@ extract cache type bits from clidr
-	and	r1, r1, #7			@ mask of the bits for current cache only
-	cmp	r1, #2				@ see what cache we have at this level
-	blt	skip				@ skip if no cache, or just i-cache
-	mcr	p15, 2, r10, c0, c0, 0		@ select current cache level in cssr
-	mcr	p15, 0, r10, c7, c5, 4		@ flush prefetch buffer,
-						@ with armv7 this is 'isb',
-						@ but we compile with armv5
-	mrc	p15, 1, r1, c0, c0, 0		@ read the new csidr
-	and	r2, r1, #7			@ extract the length of the cache lines
-	add	r2, r2, #4			@ add 4 (line length offset)
-	ldr	r4, =0x3ff
-	ands	r4, r4, r1, lsr #3		@ find maximum number on the way size
-	clz	r5, r4				@ find bit position of way size increment
-	ldr	r7, =0x7fff
-	ands	r7, r7, r1, lsr #13		@ extract max number of the index size
-loop2:
-	mov	r9, r4				@ create working copy of max way size
-loop3:
-	orr	r11, r10, r9, lsl r5		@ factor way and cache number into r11
-	orr	r11, r11, r7, lsl r2		@ factor index number into r11
-	mcr	p15, 0, r11, c7, c14, 2		@ clean & invalidate by set/way
-	subs	r9, r9, #1			@ decrement the way
-	bge	loop3
-	subs	r7, r7, #1			@ decrement the index
-	bge	loop2
-skip:
-	add	r10, r10, #2			@ increment cache number
-	cmp	r3, r10
-	bgt	loop1
-finished:
-	mov	r10, #0				@ swith back to cache level 0
-	mcr	p15, 2, r10, c0, c0, 0		@ select current cache level in cssr
-#	dsb
-	mcr	p15, 0, r10, c7, c5, 4		@ flush prefetch buffer,
-						@ with armv7 this is 'isb',
-						@ but we compile with armv5
-	mov	pc, lr
-
-/*
- *	v7_flush_cache_all()
- *
- *	Flush the entire cache system.
- *  The data cache flush is now achieved using atomic clean / invalidates
- *  working outwards from L1 cache. This is done using Set/Way based cache
- *  maintainance instructions.
- *  The instruction cache can still be invalidated back to the point of
- *  unification in a single instruction.
- *
- */
-v7_flush_cache_all:
-	stmfd	sp!, {r0-r7, r9-r11, lr}
-	bl	v7_flush_dcache_all
-	mov	r0, #0
-	mcr	p15, 0, r0, c7, c5, 0		@ I+BTB cache invalidate
-	ldmfd	sp!, {r0-r7, r9-r11, lr}
-	mov	pc, lr
diff --git a/arch/arm/cpu/armv7/omap3/clock.c b/arch/arm/cpu/armv7/omap3/clock.c
deleted file mode 100644
index cf533ac..0000000
--- a/arch/arm/cpu/armv7/omap3/clock.c
+++ /dev/null
@@ -1,674 +0,0 @@
-/*
- * (C) Copyright 2008
- * Texas Instruments, <www.ti.com>
- *
- * Author :
- *      Manikandan Pillai <mani.pillai@ti.com>
- *
- * Derived from Beagle Board and OMAP3 SDP code by
- *      Richard Woodruff <r-woodruff2@ti.com>
- *      Syed Mohammed Khasim <khasim@ti.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/clocks.h>
-#include <asm/arch/clocks_omap3.h>
-#include <asm/arch/mem.h>
-#include <asm/arch/sys_proto.h>
-#include <environment.h>
-#include <command.h>
-
-/******************************************************************************
- * get_sys_clk_speed() - determine reference oscillator speed
- *                       based on known 32kHz clock and gptimer.
- *****************************************************************************/
-u32 get_osc_clk_speed(void)
-{
-	u32 start, cstart, cend, cdiff, cdiv, val;
-	struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
-	struct prm *prm_base = (struct prm *)PRM_BASE;
-	struct gptimer *gpt1_base = (struct gptimer *)OMAP34XX_GPT1;
-	struct s32ktimer *s32k_base = (struct s32ktimer *)SYNC_32KTIMER_BASE;
-
-	val = readl(&prm_base->clksrc_ctrl);
-
-	if (val & SYSCLKDIV_2)
-		cdiv = 2;
-	else
-		cdiv = 1;
-
-	/* enable timer2 */
-	val = readl(&prcm_base->clksel_wkup) | CLKSEL_GPT1;
-
-	/* select sys_clk for GPT1 */
-	writel(val, &prcm_base->clksel_wkup);
-
-	/* Enable I and F Clocks for GPT1 */
-	val = readl(&prcm_base->iclken_wkup) | EN_GPT1 | EN_32KSYNC;
-	writel(val, &prcm_base->iclken_wkup);
-
-	val = readl(&prcm_base->fclken_wkup) | EN_GPT1;
-	writel(val, &prcm_base->fclken_wkup);
-
-	writel(0, &gpt1_base->tldr);		/* start counting at 0 */
-	writel(GPT_EN, &gpt1_base->tclr);	/* enable clock */
-
-	/* enable 32kHz source, determine sys_clk via gauging */
-
-	/* start time in 20 cycles */
-	start = 20 + readl(&s32k_base->s32k_cr);
-
-	/* dead loop till start time */
-	while (readl(&s32k_base->s32k_cr) < start);
-
-	/* get start sys_clk count */
-	cstart = readl(&gpt1_base->tcrr);
-
-	/* wait for 40 cycles */
-	while (readl(&s32k_base->s32k_cr) < (start + 20)) ;
-	cend = readl(&gpt1_base->tcrr);		/* get end sys_clk count */
-	cdiff = cend - cstart;			/* get elapsed ticks */
-	cdiff *= cdiv;
-
-	/* based on number of ticks assign speed */
-	if (cdiff > 19000)
-		return S38_4M;
-	else if (cdiff > 15200)
-		return S26M;
-	else if (cdiff > 13000)
-		return S24M;
-	else if (cdiff > 9000)
-		return S19_2M;
-	else if (cdiff > 7600)
-		return S13M;
-	else
-		return S12M;
-}
-
-/******************************************************************************
- * get_sys_clkin_sel() - returns the sys_clkin_sel field value based on
- *                       input oscillator clock frequency.
- *****************************************************************************/
-void get_sys_clkin_sel(u32 osc_clk, u32 *sys_clkin_sel)
-{
-	switch(osc_clk) {
-	case S38_4M:
-		*sys_clkin_sel = 4;
-		break;
-	case S26M:
-		*sys_clkin_sel = 3;
-		break;
-	case S19_2M:
-		*sys_clkin_sel = 2;
-		break;
-	case S13M:
-		*sys_clkin_sel = 1;
-		break;
-	case S12M:
-	default:
-		*sys_clkin_sel = 0;
-	}
-}
-
-/*
- * OMAP34XX/35XX specific functions
- */
-
-static void dpll3_init_34xx(u32 sil_index, u32 clk_index)
-{
-	struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
-	dpll_param *ptr = (dpll_param *) get_core_dpll_param();
-	void (*f_lock_pll) (u32, u32, u32, u32);
-	int xip_safe, p0, p1, p2, p3;
-
-	xip_safe = is_running_in_sram();
-
-	/* Moving to the right sysclk and ES rev base */
-	ptr = ptr + (3 * clk_index) + sil_index;
-
-	if (xip_safe) {
-		/*
-		 * CORE DPLL
-		 * sr32(CM_CLKSEL2_EMU) set override to work when asleep
-		 */
-		sr32(&prcm_base->clken_pll, 0, 3, PLL_FAST_RELOCK_BYPASS);
-		wait_on_value(ST_CORE_CLK, 0, &prcm_base->idlest_ckgen,
-				LDELAY);
-
-		/*
-		 * For OMAP3 ES1.0 Errata 1.50, default value directly doesn't
-		 * work. write another value and then default value.
-		 */
-
-		/* CM_CLKSEL1_EMU[DIV_DPLL3] */
-		sr32(&prcm_base->clksel1_emu, 16, 5, (CORE_M3X2 + 1)) ;
-		sr32(&prcm_base->clksel1_emu, 16, 5, CORE_M3X2);
-
-		/* M2 (CORE_DPLL_CLKOUT_DIV): CM_CLKSEL1_PLL[27:31] */
-		sr32(&prcm_base->clksel1_pll, 27, 5, ptr->m2);
-
-		/* M (CORE_DPLL_MULT): CM_CLKSEL1_PLL[16:26] */
-		sr32(&prcm_base->clksel1_pll, 16, 11, ptr->m);
-
-		/* N (CORE_DPLL_DIV): CM_CLKSEL1_PLL[8:14] */
-		sr32(&prcm_base->clksel1_pll, 8, 7, ptr->n);
-
-		/* Source is the CM_96M_FCLK: CM_CLKSEL1_PLL[6] */
-		sr32(&prcm_base->clksel1_pll, 6, 1, 0);
-
-		/* SSI */
-		sr32(&prcm_base->clksel_core, 8, 4, CORE_SSI_DIV);
-		/* FSUSB */
-		sr32(&prcm_base->clksel_core, 4, 2, CORE_FUSB_DIV);
-		/* L4 */
-		sr32(&prcm_base->clksel_core, 2, 2, CORE_L4_DIV);
-		/* L3 */
-		sr32(&prcm_base->clksel_core, 0, 2, CORE_L3_DIV);
-		/* GFX */
-		sr32(&prcm_base->clksel_gfx,  0, 3, GFX_DIV);
-		/* RESET MGR */
-		sr32(&prcm_base->clksel_wkup, 1, 2, WKUP_RSM);
-		/* FREQSEL (CORE_DPLL_FREQSEL): CM_CLKEN_PLL[4:7] */
-		sr32(&prcm_base->clken_pll,   4, 4, ptr->fsel);
-		/* LOCK MODE */
-		sr32(&prcm_base->clken_pll,   0, 3, PLL_LOCK);
-
-		wait_on_value(ST_CORE_CLK, 1, &prcm_base->idlest_ckgen,
-				LDELAY);
-	} else if (is_running_in_flash()) {
-		/*
-		 * if running from flash, jump to small relocated code
-		 * area in SRAM.
-		 */
-		f_lock_pll = (void *) ((u32) &_end_vect - (u32) &_start +
-				SRAM_VECT_CODE);
-
-		p0 = readl(&prcm_base->clken_pll);
-		sr32(&p0, 0, 3, PLL_FAST_RELOCK_BYPASS);
-		/* FREQSEL (CORE_DPLL_FREQSEL): CM_CLKEN_PLL[4:7] */
-		sr32(&p0, 4, 4, ptr->fsel);
-
-		p1 = readl(&prcm_base->clksel1_pll);
-		/* M2 (CORE_DPLL_CLKOUT_DIV): CM_CLKSEL1_PLL[27:31] */
-		sr32(&p1, 27, 5, ptr->m2);
-		/* M (CORE_DPLL_MULT): CM_CLKSEL1_PLL[16:26] */
-		sr32(&p1, 16, 11, ptr->m);
-		/* N (CORE_DPLL_DIV): CM_CLKSEL1_PLL[8:14] */
-		sr32(&p1, 8, 7, ptr->n);
-		/* Source is the CM_96M_FCLK: CM_CLKSEL1_PLL[6] */
-		sr32(&p1, 6, 1, 0);
-
-		p2 = readl(&prcm_base->clksel_core);
-		/* SSI */
-		sr32(&p2, 8, 4, CORE_SSI_DIV);
-		/* FSUSB */
-		sr32(&p2, 4, 2, CORE_FUSB_DIV);
-		/* L4 */
-		sr32(&p2, 2, 2, CORE_L4_DIV);
-		/* L3 */
-		sr32(&p2, 0, 2, CORE_L3_DIV);
-
-		p3 = (u32)&prcm_base->idlest_ckgen;
-
-		(*f_lock_pll) (p0, p1, p2, p3);
-	}
-}
-
-static void dpll4_init_34xx(u32 sil_index, u32 clk_index)
-{
-	struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
-	dpll_param *ptr = (dpll_param *) get_per_dpll_param();
-
-	/* Moving it to the right sysclk base */
-	ptr = ptr + clk_index;
-
-	/* EN_PERIPH_DPLL: CM_CLKEN_PLL[16:18] */
-	sr32(&prcm_base->clken_pll, 16, 3, PLL_STOP);
-	wait_on_value(ST_PERIPH_CLK, 0, &prcm_base->idlest_ckgen, LDELAY);
-
-	/*
-	 * Errata 1.50 Workaround for OMAP3 ES1.0 only
-	 * If using default divisors, write default divisor + 1
-	 * and then the actual divisor value
-	 */
-	/* M6 */
-	sr32(&prcm_base->clksel1_emu, 24, 5, (PER_M6X2 + 1));
-	sr32(&prcm_base->clksel1_emu, 24, 5, PER_M6X2);
-	/* M5 */
-	sr32(&prcm_base->clksel_cam, 0, 5, (PER_M5X2 + 1));
-	sr32(&prcm_base->clksel_cam, 0, 5, PER_M5X2);
-	/* M4 */
-	sr32(&prcm_base->clksel_dss, 0, 5, (PER_M4X2 + 1));
-	sr32(&prcm_base->clksel_dss, 0, 5, PER_M4X2);
-	/* M3 */
-	sr32(&prcm_base->clksel_dss, 8, 5, (PER_M3X2 + 1));
-	sr32(&prcm_base->clksel_dss, 8, 5, PER_M3X2);
-	/* M2 (DIV_96M): CM_CLKSEL3_PLL[0:4] */
-	sr32(&prcm_base->clksel3_pll, 0, 5, (ptr->m2 + 1));
-	sr32(&prcm_base->clksel3_pll, 0, 5, ptr->m2);
-	/* Workaround end */
-
-	/* M (PERIPH_DPLL_MULT): CM_CLKSEL2_PLL[8:18] */
-	sr32(&prcm_base->clksel2_pll, 8, 11, ptr->m);
-
-	/* N (PERIPH_DPLL_DIV): CM_CLKSEL2_PLL[0:6] */
-	sr32(&prcm_base->clksel2_pll, 0, 7, ptr->n);
-
-	/* FREQSEL (PERIPH_DPLL_FREQSEL): CM_CLKEN_PLL[20:23] */
-	sr32(&prcm_base->clken_pll, 20, 4, ptr->fsel);
-
-	/* LOCK MODE (EN_PERIPH_DPLL): CM_CLKEN_PLL[16:18] */
-	sr32(&prcm_base->clken_pll, 16, 3, PLL_LOCK);
-	wait_on_value(ST_PERIPH_CLK, 2, &prcm_base->idlest_ckgen, LDELAY);
-}
-
-static void mpu_init_34xx(u32 sil_index, u32 clk_index)
-{
-	struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
-	dpll_param *ptr = (dpll_param *) get_mpu_dpll_param();
-
-	/* Moving to the right sysclk and ES rev base */
-	ptr = ptr + (3 * clk_index) + sil_index;
-
-	/* MPU DPLL (unlocked already) */
-
-	/* M2 (MPU_DPLL_CLKOUT_DIV) : CM_CLKSEL2_PLL_MPU[0:4] */
-	sr32(&prcm_base->clksel2_pll_mpu, 0, 5, ptr->m2);
-
-	/* M (MPU_DPLL_MULT) : CM_CLKSEL2_PLL_MPU[8:18] */
-	sr32(&prcm_base->clksel1_pll_mpu, 8, 11, ptr->m);
-
-	/* N (MPU_DPLL_DIV) : CM_CLKSEL2_PLL_MPU[0:6] */
-	sr32(&prcm_base->clksel1_pll_mpu, 0, 7, ptr->n);
-
-	/* FREQSEL (MPU_DPLL_FREQSEL) : CM_CLKEN_PLL_MPU[4:7] */
-	sr32(&prcm_base->clken_pll_mpu, 4, 4, ptr->fsel);
-}
-
-static void iva_init_34xx(u32 sil_index, u32 clk_index)
-{
-	struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
-	dpll_param *ptr = (dpll_param *) get_iva_dpll_param();
-
-	/* Moving to the right sysclk and ES rev base */
-	ptr = ptr + (3 * clk_index) + sil_index;
-
-	/* IVA DPLL */
-	/* EN_IVA2_DPLL : CM_CLKEN_PLL_IVA2[0:2] */
-	sr32(&prcm_base->clken_pll_iva2, 0, 3, PLL_STOP);
-	wait_on_value(ST_IVA2_CLK, 0, &prcm_base->idlest_pll_iva2, LDELAY);
-
-	/* M2 (IVA2_DPLL_CLKOUT_DIV) : CM_CLKSEL2_PLL_IVA2[0:4] */
-	sr32(&prcm_base->clksel2_pll_iva2, 0, 5, ptr->m2);
-
-	/* M (IVA2_DPLL_MULT) : CM_CLKSEL1_PLL_IVA2[8:18] */
-	sr32(&prcm_base->clksel1_pll_iva2, 8, 11, ptr->m);
-
-	/* N (IVA2_DPLL_DIV) : CM_CLKSEL1_PLL_IVA2[0:6] */
-	sr32(&prcm_base->clksel1_pll_iva2, 0, 7, ptr->n);
-
-	/* FREQSEL (IVA2_DPLL_FREQSEL) : CM_CLKEN_PLL_IVA2[4:7] */
-	sr32(&prcm_base->clken_pll_iva2, 4, 4, ptr->fsel);
-
-	/* LOCK MODE (EN_IVA2_DPLL) : CM_CLKEN_PLL_IVA2[0:2] */
-	sr32(&prcm_base->clken_pll_iva2, 0, 3, PLL_LOCK);
-
-	wait_on_value(ST_IVA2_CLK, 1, &prcm_base->idlest_pll_iva2, LDELAY);
-}
-
-/*
- * OMAP3630 specific functions
- */
-
-static void dpll3_init_36xx(u32 sil_index, u32 clk_index)
-{
-	struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
-	dpll_param *ptr = (dpll_param *) get_36x_core_dpll_param();
-	void (*f_lock_pll) (u32, u32, u32, u32);
-	int xip_safe, p0, p1, p2, p3;
-
-	xip_safe = is_running_in_sram();
-
-	/* Moving it to the right sysclk base */
-	ptr += clk_index;
-
-	if (xip_safe) {
-		/* CORE DPLL */
-
-		/* Select relock bypass: CM_CLKEN_PLL[0:2] */
-		sr32(&prcm_base->clken_pll, 0, 3, PLL_FAST_RELOCK_BYPASS);
-		wait_on_value(ST_CORE_CLK, 0, &prcm_base->idlest_ckgen,
-				LDELAY);
-
-		/* CM_CLKSEL1_EMU[DIV_DPLL3] */
-		sr32(&prcm_base->clksel1_emu, 16, 5, CORE_M3X2);
-
-		/* M2 (CORE_DPLL_CLKOUT_DIV): CM_CLKSEL1_PLL[27:31] */
-		sr32(&prcm_base->clksel1_pll, 27, 5, ptr->m2);
-
-		/* M (CORE_DPLL_MULT): CM_CLKSEL1_PLL[16:26] */
-		sr32(&prcm_base->clksel1_pll, 16, 11, ptr->m);
-
-		/* N (CORE_DPLL_DIV): CM_CLKSEL1_PLL[8:14] */
-		sr32(&prcm_base->clksel1_pll, 8, 7, ptr->n);
-
-		/* Source is the CM_96M_FCLK: CM_CLKSEL1_PLL[6] */
-		sr32(&prcm_base->clksel1_pll, 6, 1, 0);
-
-		/* SSI */
-		sr32(&prcm_base->clksel_core, 8, 4, CORE_SSI_DIV);
-		/* FSUSB */
-		sr32(&prcm_base->clksel_core, 4, 2, CORE_FUSB_DIV);
-		/* L4 */
-		sr32(&prcm_base->clksel_core, 2, 2, CORE_L4_DIV);
-		/* L3 */
-		sr32(&prcm_base->clksel_core, 0, 2, CORE_L3_DIV);
-		/* GFX */
-		sr32(&prcm_base->clksel_gfx,  0, 3, GFX_DIV);
-		/* RESET MGR */
-		sr32(&prcm_base->clksel_wkup, 1, 2, WKUP_RSM);
-		/* FREQSEL (CORE_DPLL_FREQSEL): CM_CLKEN_PLL[4:7] */
-		sr32(&prcm_base->clken_pll,   4, 4, ptr->fsel);
-		/* LOCK MODE */
-		sr32(&prcm_base->clken_pll,   0, 3, PLL_LOCK);
-
-		wait_on_value(ST_CORE_CLK, 1, &prcm_base->idlest_ckgen,
-				LDELAY);
-	} else if (is_running_in_flash()) {
-		/*
-		 * if running from flash, jump to small relocated code
-		 * area in SRAM.
-		 */
-		f_lock_pll = (void *) ((u32) &_end_vect - (u32) &_start +
-				SRAM_VECT_CODE);
-
-		p0 = readl(&prcm_base->clken_pll);
-		sr32(&p0, 0, 3, PLL_FAST_RELOCK_BYPASS);
-		/* FREQSEL (CORE_DPLL_FREQSEL): CM_CLKEN_PLL[4:7] */
-		sr32(&p0, 4, 4, ptr->fsel);
-
-		p1 = readl(&prcm_base->clksel1_pll);
-		/* M2 (CORE_DPLL_CLKOUT_DIV): CM_CLKSEL1_PLL[27:31] */
-		sr32(&p1, 27, 5, ptr->m2);
-		/* M (CORE_DPLL_MULT): CM_CLKSEL1_PLL[16:26] */
-		sr32(&p1, 16, 11, ptr->m);
-		/* N (CORE_DPLL_DIV): CM_CLKSEL1_PLL[8:14] */
-		sr32(&p1, 8, 7, ptr->n);
-		/* Source is the CM_96M_FCLK: CM_CLKSEL1_PLL[6] */
-		sr32(&p1, 6, 1, 0);
-
-		p2 = readl(&prcm_base->clksel_core);
-		/* SSI */
-		sr32(&p2, 8, 4, CORE_SSI_DIV);
-		/* FSUSB */
-		sr32(&p2, 4, 2, CORE_FUSB_DIV);
-		/* L4 */
-		sr32(&p2, 2, 2, CORE_L4_DIV);
-		/* L3 */
-		sr32(&p2, 0, 2, CORE_L3_DIV);
-
-		p3 = (u32)&prcm_base->idlest_ckgen;
-
-		(*f_lock_pll) (p0, p1, p2, p3);
-	}
-}
-
-static void dpll4_init_36xx(u32 sil_index, u32 clk_index)
-{
-	struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
-	struct dpll_per_36x_param *ptr;
-
-	ptr = (struct dpll_per_36x_param *)get_36x_per_dpll_param();
-
-	/* Moving it to the right sysclk base */
-	ptr += clk_index;
-
-	/* EN_PERIPH_DPLL: CM_CLKEN_PLL[16:18] */
-	sr32(&prcm_base->clken_pll, 16, 3, PLL_STOP);
-	wait_on_value(ST_PERIPH_CLK, 0, &prcm_base->idlest_ckgen, LDELAY);
-
-	/* M6 (DIV_DPLL4): CM_CLKSEL1_EMU[24:29] */
-	sr32(&prcm_base->clksel1_emu, 24, 6, ptr->m6);
-
-	/* M5 (CLKSEL_CAM): CM_CLKSEL1_EMU[0:5] */
-	sr32(&prcm_base->clksel_cam, 0, 6, ptr->m5);
-
-	/* M4 (CLKSEL_DSS1): CM_CLKSEL_DSS[0:5] */
-	sr32(&prcm_base->clksel_dss, 0, 6, ptr->m4);
-
-	/* M3 (CLKSEL_DSS1): CM_CLKSEL_DSS[8:13] */
-	sr32(&prcm_base->clksel_dss, 8, 6, ptr->m3);
-
-	/* M2 (DIV_96M): CM_CLKSEL3_PLL[0:4] */
-	sr32(&prcm_base->clksel3_pll, 0, 5, ptr->m2);
-
-	/* M (PERIPH_DPLL_MULT): CM_CLKSEL2_PLL[8:19] */
-	sr32(&prcm_base->clksel2_pll, 8, 12, ptr->m);
-
-	/* N (PERIPH_DPLL_DIV): CM_CLKSEL2_PLL[0:6] */
-	sr32(&prcm_base->clksel2_pll, 0, 7, ptr->n);
-
-	/* M2DIV (CLKSEL_96M): CM_CLKSEL_CORE[12:13] */
-	sr32(&prcm_base->clksel_core, 12, 2, ptr->m2div);
-
-	/* LOCK MODE (EN_PERIPH_DPLL): CM_CLKEN_PLL[16:18] */
-	sr32(&prcm_base->clken_pll, 16, 3, PLL_LOCK);
-	wait_on_value(ST_PERIPH_CLK, 2, &prcm_base->idlest_ckgen, LDELAY);
-}
-
-static void mpu_init_36xx(u32 sil_index, u32 clk_index)
-{
-	struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
-	dpll_param *ptr = (dpll_param *) get_36x_mpu_dpll_param();
-
-	/* Moving to the right sysclk */
-	ptr += clk_index;
-
-	/* MPU DPLL (unlocked already */
-
-	/* M2 (MPU_DPLL_CLKOUT_DIV) : CM_CLKSEL2_PLL_MPU[0:4] */
-	sr32(&prcm_base->clksel2_pll_mpu, 0, 5, ptr->m2);
-
-	/* M (MPU_DPLL_MULT) : CM_CLKSEL2_PLL_MPU[8:18] */
-	sr32(&prcm_base->clksel1_pll_mpu, 8, 11, ptr->m);
-
-	/* N (MPU_DPLL_DIV) : CM_CLKSEL2_PLL_MPU[0:6] */
-	sr32(&prcm_base->clksel1_pll_mpu, 0, 7, ptr->n);
-}
-
-static void iva_init_36xx(u32 sil_index, u32 clk_index)
-{
-	struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
-	dpll_param *ptr = (dpll_param *)get_36x_iva_dpll_param();
-
-	/* Moving to the right sysclk */
-	ptr += clk_index;
-
-	/* IVA DPLL */
-	/* EN_IVA2_DPLL : CM_CLKEN_PLL_IVA2[0:2] */
-	sr32(&prcm_base->clken_pll_iva2, 0, 3, PLL_STOP);
-	wait_on_value(ST_IVA2_CLK, 0, &prcm_base->idlest_pll_iva2, LDELAY);
-
-	/* M2 (IVA2_DPLL_CLKOUT_DIV) : CM_CLKSEL2_PLL_IVA2[0:4] */
-	sr32(&prcm_base->clksel2_pll_iva2, 0, 5, ptr->m2);
-
-	/* M (IVA2_DPLL_MULT) : CM_CLKSEL1_PLL_IVA2[8:18] */
-	sr32(&prcm_base->clksel1_pll_iva2, 8, 11, ptr->m);
-
-	/* N (IVA2_DPLL_DIV) : CM_CLKSEL1_PLL_IVA2[0:6] */
-	sr32(&prcm_base->clksel1_pll_iva2, 0, 7, ptr->n);
-
-	/* LOCK (MODE (EN_IVA2_DPLL) : CM_CLKEN_PLL_IVA2[0:2] */
-	sr32(&prcm_base->clken_pll_iva2, 0, 3, PLL_LOCK);
-
-	wait_on_value(ST_IVA2_CLK, 1, &prcm_base->idlest_pll_iva2, LDELAY);
-}
-
-/******************************************************************************
- * prcm_init() - inits clocks for PRCM as defined in clocks.h
- *               called from SRAM, or Flash (using temp SRAM stack).
- *****************************************************************************/
-void prcm_init(void)
-{
-	u32 osc_clk = 0, sys_clkin_sel;
-	u32 clk_index, sil_index = 0;
-	struct prm *prm_base = (struct prm *)PRM_BASE;
-	struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
-
-	/*
-	 * Gauge the input clock speed and find out the sys_clkin_sel
-	 * value corresponding to the input clock.
-	 */
-	osc_clk = get_osc_clk_speed();
-	get_sys_clkin_sel(osc_clk, &sys_clkin_sel);
-
-	/* set input crystal speed */
-	sr32(&prm_base->clksel, 0, 3, sys_clkin_sel);
-
-	/* If the input clock is greater than 19.2M always divide/2 */
-	if (sys_clkin_sel > 2) {
-		/* input clock divider */
-		sr32(&prm_base->clksrc_ctrl, 6, 2, 2);
-		clk_index = sys_clkin_sel / 2;
-	} else {
-		/* input clock divider */
-		sr32(&prm_base->clksrc_ctrl, 6, 2, 1);
-		clk_index = sys_clkin_sel;
-	}
-
-	if (get_cpu_family() == CPU_OMAP36XX) {
-		/* Unlock MPU DPLL (slows things down, and needed later) */
-		sr32(&prcm_base->clken_pll_mpu, 0, 3, PLL_LOW_POWER_BYPASS);
-		wait_on_value(ST_MPU_CLK, 0, &prcm_base->idlest_pll_mpu,
-				LDELAY);
-
-		dpll3_init_36xx(0, clk_index);
-		dpll4_init_36xx(0, clk_index);
-		iva_init_36xx(0, clk_index);
-		mpu_init_36xx(0, clk_index);
-
-		/* Lock MPU DPLL to set frequency */
-		sr32(&prcm_base->clken_pll_mpu, 0, 3, PLL_LOCK);
-		wait_on_value(ST_MPU_CLK, 1, &prcm_base->idlest_pll_mpu,
-				LDELAY);
-	} else {
-		/*
-		 * The DPLL tables are defined according to sysclk value and
-		 * silicon revision. The clk_index value will be used to get
-		 * the values for that input sysclk from the DPLL param table
-		 * and sil_index will get the values for that SysClk for the
-		 * appropriate silicon rev.
-		 */
-		if (((get_cpu_family() == CPU_OMAP34XX)
-				&& (get_cpu_rev() >= CPU_3XX_ES20)) ||
-			(get_cpu_family() == CPU_AM35XX))
-			sil_index = 1;
-
-		/* Unlock MPU DPLL (slows things down, and needed later) */
-		sr32(&prcm_base->clken_pll_mpu, 0, 3, PLL_LOW_POWER_BYPASS);
-		wait_on_value(ST_MPU_CLK, 0, &prcm_base->idlest_pll_mpu,
-				LDELAY);
-
-		dpll3_init_34xx(sil_index, clk_index);
-		dpll4_init_34xx(sil_index, clk_index);
-		iva_init_34xx(sil_index, clk_index);
-		mpu_init_34xx(sil_index, clk_index);
-
-		/* Lock MPU DPLL to set frequency */
-		sr32(&prcm_base->clken_pll_mpu, 0, 3, PLL_LOCK);
-		wait_on_value(ST_MPU_CLK, 1, &prcm_base->idlest_pll_mpu,
-				LDELAY);
-	}
-
-	/* Set up GPTimers to sys_clk source only */
-	sr32(&prcm_base->clksel_per, 0, 8, 0xff);
-	sr32(&prcm_base->clksel_wkup, 0, 1, 1);
-
-	sdelay(5000);
-}
-
-/******************************************************************************
- * peripheral_enable() - Enable the clks & power for perifs (GPT2, UART1,...)
- *****************************************************************************/
-void per_clocks_enable(void)
-{
-	struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
-
-	/* Enable GP2 timer. */
-	sr32(&prcm_base->clksel_per, 0, 1, 0x1);	/* GPT2 = sys clk */
-	sr32(&prcm_base->iclken_per, 3, 1, 0x1);	/* ICKen GPT2 */
-	sr32(&prcm_base->fclken_per, 3, 1, 0x1);	/* FCKen GPT2 */
-
-#ifdef CONFIG_SYS_NS16550
-	/* Enable UART1 clocks */
-	sr32(&prcm_base->fclken1_core, 13, 1, 0x1);
-	sr32(&prcm_base->iclken1_core, 13, 1, 0x1);
-
-	/* UART 3 Clocks */
-	sr32(&prcm_base->fclken_per, 11, 1, 0x1);
-	sr32(&prcm_base->iclken_per, 11, 1, 0x1);
-#endif
-
-#ifdef CONFIG_OMAP3_GPIO_2
-	sr32(&prcm_base->fclken_per, 13, 1, 1);
-	sr32(&prcm_base->iclken_per, 13, 1, 1);
-#endif
-#ifdef CONFIG_OMAP3_GPIO_3
-	sr32(&prcm_base->fclken_per, 14, 1, 1);
-	sr32(&prcm_base->iclken_per, 14, 1, 1);
-#endif
-#ifdef CONFIG_OMAP3_GPIO_4
-	sr32(&prcm_base->fclken_per, 15, 1, 1);
-	sr32(&prcm_base->iclken_per, 15, 1, 1);
-#endif
-#ifdef CONFIG_OMAP3_GPIO_5
-	sr32(&prcm_base->fclken_per, 16, 1, 1);
-	sr32(&prcm_base->iclken_per, 16, 1, 1);
-#endif
-#ifdef CONFIG_OMAP3_GPIO_6
-	sr32(&prcm_base->fclken_per, 17, 1, 1);
-	sr32(&prcm_base->iclken_per, 17, 1, 1);
-#endif
-
-#ifdef CONFIG_DRIVER_OMAP34XX_I2C
-	/* Turn on all 3 I2C clocks */
-	sr32(&prcm_base->fclken1_core, 15, 3, 0x7);
-	sr32(&prcm_base->iclken1_core, 15, 3, 0x7);	/* I2C1,2,3 = on */
-#endif
-	/* Enable the ICLK for 32K Sync Timer as its used in udelay */
-	sr32(&prcm_base->iclken_wkup, 2, 1, 0x1);
-
-	sr32(&prcm_base->fclken_iva2, 0, 32, FCK_IVA2_ON);
-	sr32(&prcm_base->fclken1_core, 0, 32, FCK_CORE1_ON);
-	sr32(&prcm_base->iclken1_core, 0, 32, ICK_CORE1_ON);
-	sr32(&prcm_base->iclken2_core, 0, 32, ICK_CORE2_ON);
-	sr32(&prcm_base->fclken_wkup, 0, 32, FCK_WKUP_ON);
-	sr32(&prcm_base->iclken_wkup, 0, 32, ICK_WKUP_ON);
-	
-#ifndef CONFIG_OMAP3_GTA04A2	/* makes problems on GTA04A2 */
-	sr32(&prcm_base->fclken_dss, 0, 32, FCK_DSS_ON);
-	sr32(&prcm_base->iclken_dss, 0, 32, ICK_DSS_ON);
-	sr32(&prcm_base->fclken_cam, 0, 32, FCK_CAM_ON);
-	sr32(&prcm_base->iclken_cam, 0, 32, ICK_CAM_ON);
-#endif
-	sr32(&prcm_base->fclken_per, 0, 32, FCK_PER_ON);
-	sr32(&prcm_base->iclken_per, 0, 32, ICK_PER_ON);
-
-	sdelay(1000);
-}
diff --git a/arch/arm/cpu/armv7/omap3/emif4.c b/arch/arm/cpu/armv7/omap3/emif4.c
deleted file mode 100644
index 3085637..0000000
--- a/arch/arm/cpu/armv7/omap3/emif4.c
+++ /dev/null
@@ -1,178 +0,0 @@
-/*
- * Author :
- *     Vaibhav Hiremath <hvaibhav@ti.com>
- *
- * Based on mem.c and sdrc.c
- *
- * Copyright (C) 2010
- * Texas Instruments Incorporated - http://www.ti.com/
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/mem.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/emif4.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-extern omap3_sysinfo sysinfo;
-
-static emif4_t *emif4_base = (emif4_t *)OMAP34XX_SDRC_BASE;
-
-/*
- * is_mem_sdr -
- *  - Return 1 if mem type in use is SDR
- */
-u32 is_mem_sdr(void)
-{
-	return 0;
-}
-
-/*
- * get_sdr_cs_size -
- *  - Get size of chip select 0/1
- */
-u32 get_sdr_cs_size(u32 cs)
-{
-	u32 size = 0;
-
-	/* TODO: Calculate the size based on EMIF4 configuration */
-	if (cs == CS0)
-		size = CONFIG_SYS_CS0_SIZE;
-
-	return size;
-}
-
-/*
- * get_sdr_cs_offset -
- *  - Get offset of cs from cs0 start
- */
-u32 get_sdr_cs_offset(u32 cs)
-{
-	u32 offset = 0;
-
-	return offset;
-}
-
-/*
- * do_emif4_init -
- *  - Init the emif4 module for DDR access
- *  - Early init routines, called from flash or SRAM.
- */
-void do_emif4_init(void)
-{
-	unsigned int regval;
-	/* Set the DDR PHY parameters in PHY ctrl registers */
-	regval = (EMIF4_DDR1_READ_LAT | EMIF4_DDR1_PWRDN_DIS |
-		EMIF4_DDR1_EXT_STRB_DIS);
-	writel(regval, &emif4_base->ddr_phyctrl1);
-	writel(regval, &emif4_base->ddr_phyctrl1_shdw);
-	writel(0, &emif4_base->ddr_phyctrl2);
-
-	/* Reset the DDR PHY and wait till completed */
-	regval = readl(&emif4_base->sdram_iodft_tlgc);
-	regval |= (1<<10);
-	writel(regval, &emif4_base->sdram_iodft_tlgc);
-	/*Wait till that bit clears*/
-	while ((readl(&emif4_base->sdram_iodft_tlgc) & (1<<10)) == 0x1);
-	/*Re-verify the DDR PHY status*/
-	while ((readl(&emif4_base->sdram_sts) & (1<<2)) == 0x0);
-
-	regval |= (1<<0);
-	writel(regval, &emif4_base->sdram_iodft_tlgc);
-	/* Set SDR timing registers */
-	regval = (EMIF4_TIM1_T_WTR | EMIF4_TIM1_T_RRD |
-		EMIF4_TIM1_T_RC | EMIF4_TIM1_T_RAS |
-		EMIF4_TIM1_T_WR | EMIF4_TIM1_T_RCD |
-		EMIF4_TIM1_T_RP);
-	writel(regval, &emif4_base->sdram_time1);
-	writel(regval, &emif4_base->sdram_time1_shdw);
-
-	regval = (EMIF4_TIM2_T_CKE | EMIF4_TIM2_T_RTP |
-		EMIF4_TIM2_T_XSRD | EMIF4_TIM2_T_XSNR |
-		EMIF4_TIM2_T_ODT | EMIF4_TIM2_T_XP);
-	writel(regval, &emif4_base->sdram_time2);
-	writel(regval, &emif4_base->sdram_time2_shdw);
-
-	regval = (EMIF4_TIM3_T_RAS_MAX | EMIF4_TIM3_T_RFC);
-	writel(regval, &emif4_base->sdram_time3);
-	writel(regval, &emif4_base->sdram_time3_shdw);
-
-	/* Set the PWR control register */
-	regval = (EMIF4_PWR_PM_TIM | EMIF4_PWR_LP_MODE |
-		EMIF4_PWR_DPD_DIS | EMIF4_PWR_IDLE_MODE);
-	writel(regval, &emif4_base->sdram_pwr_mgmt);
-	writel(regval, &emif4_base->sdram_pwr_mgmt_shdw);
-
-	/* Set the DDR refresh rate control register */
-	regval = (EMIF4_REFRESH_RATE | EMIF4_INITREF_DIS);
-	writel(regval, &emif4_base->sdram_refresh_ctrl);
-	writel(regval, &emif4_base->sdram_refresh_ctrl_shdw);
-
-	/* set the SDRAM configuration register */
-	regval = (EMIF4_CFG_PGSIZE | EMIF4_CFG_EBANK |
-		EMIF4_CFG_IBANK | EMIF4_CFG_ROWSIZE |
-		EMIF4_CFG_CL | EMIF4_CFG_NARROW_MD |
-		EMIF4_CFG_SDR_DRV | EMIF4_CFG_DDR_DIS_DLL |
-		EMIF4_CFG_DDR2_DDQS | EMIF4_CFG_DDR_TERM |
-		EMIF4_CFG_IBANK_POS | EMIF4_CFG_SDRAM_TYP);
-	writel(regval, &emif4_base->sdram_config);
-}
-
-/*
- * dram_init -
- *  - Sets uboots idea of sdram size
- */
-int dram_init(void)
-{
-	unsigned int size0 = 0, size1 = 0;
-
-	size0 = get_sdr_cs_size(CS0);
-	/*
-	 * If a second bank of DDR is attached to CS1 this is
-	 * where it can be started.  Early init code will init
-	 * memory on CS0.
-	 */
-	if ((sysinfo.mtype == DDR_COMBO) || (sysinfo.mtype == DDR_STACKED))
-		size1 = get_sdr_cs_size(CS1);
-
-	gd->ram_size = size0 + size1;
-	return 0;
-}
-
-void dram_init_banksize (void)
-{
-	unsigned int size0 = 0, size1 = 0;
-
-	size0 = get_sdr_cs_size(CS0);
-	size1 = get_sdr_cs_size(CS1);
-
-	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
-	gd->bd->bi_dram[0].size = size0;
-	gd->bd->bi_dram[1].start = PHYS_SDRAM_1 + get_sdr_cs_offset(CS1);
-	gd->bd->bi_dram[1].size = size1;
-}
-
-/*
- * mem_init() -
- *  - Initialize memory subsystem
- */
-void mem_init(void)
-{
-	do_emif4_init();
-}
diff --git a/arch/arm/cpu/armv7/omap3/gpio.c b/arch/arm/cpu/armv7/omap3/gpio.c
deleted file mode 100644
index aeb6066..0000000
--- a/arch/arm/cpu/armv7/omap3/gpio.c
+++ /dev/null
@@ -1,185 +0,0 @@
-/*
- * Copyright (c) 2009 Wind River Systems, Inc.
- * Tom Rix <Tom.Rix@windriver.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- * This work is derived from the linux 2.6.27 kernel source
- * To fetch, use the kernel repository
- * git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6.git
- * Use the v2.6.27 tag.
- *
- * Below is the original's header including its copyright
- *
- *  linux/arch/arm/plat-omap/gpio.c
- *
- * Support functions for OMAP GPIO
- *
- * Copyright (C) 2003-2005 Nokia Corporation
- * Written by Juha Yrjölä <juha.yrjola@nokia.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <common.h>
-#include <asm/arch/gpio.h>
-#include <asm/io.h>
-#include <asm/errno.h>
-
-static struct gpio_bank gpio_bank_34xx[6] = {
-	{ (void *)OMAP34XX_GPIO1_BASE, METHOD_GPIO_24XX },
-	{ (void *)OMAP34XX_GPIO2_BASE, METHOD_GPIO_24XX },
-	{ (void *)OMAP34XX_GPIO3_BASE, METHOD_GPIO_24XX },
-	{ (void *)OMAP34XX_GPIO4_BASE, METHOD_GPIO_24XX },
-	{ (void *)OMAP34XX_GPIO5_BASE, METHOD_GPIO_24XX },
-	{ (void *)OMAP34XX_GPIO6_BASE, METHOD_GPIO_24XX },
-};
-
-static struct gpio_bank *gpio_bank = &gpio_bank_34xx[0];
-
-static inline struct gpio_bank *get_gpio_bank(int gpio)
-{
-	return &gpio_bank[gpio >> 5];
-}
-
-static inline int get_gpio_index(int gpio)
-{
-	return gpio & 0x1f;
-}
-
-static inline int gpio_valid(int gpio)
-{
-	if (gpio < 0)
-		return -1;
-	if (gpio < 192)
-		return 0;
-	return -1;
-}
-
-static int check_gpio(int gpio)
-{
-	if (gpio_valid(gpio) < 0) {
-		printf("ERROR : check_gpio: invalid GPIO %d\n", gpio);
-		return -1;
-	}
-	return 0;
-}
-
-static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
-{
-	void *reg = bank->base;
-	u32 l;
-
-	switch (bank->method) {
-	case METHOD_GPIO_24XX:
-		reg += OMAP24XX_GPIO_OE;
-		break;
-	default:
-		return;
-	}
-	l = __raw_readl(reg);
-	if (is_input)
-		l |= 1 << gpio;
-	else
-		l &= ~(1 << gpio);
-	__raw_writel(l, reg);
-}
-
-void omap_set_gpio_direction(int gpio, int is_input)
-{
-	struct gpio_bank *bank;
-
-	if (check_gpio(gpio) < 0)
-		return;
-	bank = get_gpio_bank(gpio);
-	_set_gpio_direction(bank, get_gpio_index(gpio), is_input);
-}
-
-static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
-{
-	void *reg = bank->base;
-	u32 l = 0;
-
-	switch (bank->method) {
-	case METHOD_GPIO_24XX:
-		if (enable)
-			reg += OMAP24XX_GPIO_SETDATAOUT;
-		else
-			reg += OMAP24XX_GPIO_CLEARDATAOUT;
-		l = 1 << gpio;
-		break;
-	default:
-		printf("omap3-gpio unknown bank method %s %d\n",
-		       __FILE__, __LINE__);
-		return;
-	}
-	__raw_writel(l, reg);
-}
-
-void omap_set_gpio_dataout(int gpio, int enable)
-{
-	struct gpio_bank *bank;
-
-	if (check_gpio(gpio) < 0)
-		return;
-	bank = get_gpio_bank(gpio);
-	_set_gpio_dataout(bank, get_gpio_index(gpio), enable);
-}
-
-int omap_get_gpio_datain(int gpio)
-{
-	struct gpio_bank *bank;
-	void *reg;
-
-	if (check_gpio(gpio) < 0)
-		return -EINVAL;
-	bank = get_gpio_bank(gpio);
-	reg = bank->base;
-	switch (bank->method) {
-	case METHOD_GPIO_24XX:
-		reg += OMAP24XX_GPIO_DATAIN;
-		break;
-	default:
-		return -EINVAL;
-	}
-	return (__raw_readl(reg)
-			& (1 << get_gpio_index(gpio))) != 0;
-}
-
-static void _reset_gpio(struct gpio_bank *bank, int gpio)
-{
-	_set_gpio_direction(bank, get_gpio_index(gpio), 1);
-}
-
-int omap_request_gpio(int gpio)
-{
-	if (check_gpio(gpio) < 0)
-		return -EINVAL;
-
-	return 0;
-}
-
-void omap_free_gpio(int gpio)
-{
-	struct gpio_bank *bank;
-
-	if (check_gpio(gpio) < 0)
-		return;
-	bank = get_gpio_bank(gpio);
-
-	_reset_gpio(bank, gpio);
-}
diff --git a/arch/arm/cpu/armv7/omap3/lowlevel_init.S b/arch/arm/cpu/armv7/omap3/lowlevel_init.S
deleted file mode 100644
index 109481e..0000000
--- a/arch/arm/cpu/armv7/omap3/lowlevel_init.S
+++ /dev/null
@@ -1,429 +0,0 @@
-/*
- * Board specific setup info
- *
- * (C) Copyright 2008
- * Texas Instruments, <www.ti.com>
- *
- * Initial Code by:
- * Richard Woodruff <r-woodruff2@ti.com>
- * Syed Mohammed Khasim <khasim@ti.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <version.h>
-#include <asm/arch/mem.h>
-#include <asm/arch/clocks_omap3.h>
-
-_TEXT_BASE:
-	.word	CONFIG_SYS_TEXT_BASE	/* sdram load addr from config.mk */
-
-#if !defined(CONFIG_SYS_NAND_BOOT) && !defined(CONFIG_SYS_NAND_BOOT)
-/**************************************************************************
- * cpy_clk_code: relocates clock code into SRAM where its safer to execute
- * R1 = SRAM destination address.
- *************************************************************************/
-.global cpy_clk_code
- cpy_clk_code:
-	/* Copy DPLL code into SRAM */
-	adr	r0, go_to_speed		/* get addr of clock setting code */
-	mov	r2, #384		/* r2 size to copy (div by 32 bytes) */
-	mov	r1, r1			/* r1 <- dest address (passed in) */
-	add	r2, r2, r0		/* r2 <- source end address */
-next2:
-	ldmia	r0!, {r3 - r10}		/* copy from source address [r0] */
-	stmia	r1!, {r3 - r10}		/* copy to   target address [r1] */
-	cmp	r0, r2			/* until source end address [r2] */
-	bne	next2
-	mov	pc, lr			/* back to caller */
-
-/* ***************************************************************************
- *  go_to_speed: -Moves to bypass, -Commits clock dividers, -puts dpll at speed
- *               -executed from SRAM.
- *  R0 = CM_CLKEN_PLL-bypass value
- *  R1 = CM_CLKSEL1_PLL-m, n, and divider values
- *  R2 = CM_CLKSEL_CORE-divider values
- *  R3 = CM_IDLEST_CKGEN - addr dpll lock wait
- *
- *  Note: If core unlocks/relocks and SDRAM is running fast already it gets
- *        confused.  A reset of the controller gets it back.  Taking away its
- *        L3 when its not in self refresh seems bad for it.  Normally, this
- *	  code runs from flash before SDR is init so that should be ok.
- ****************************************************************************/
-.global go_to_speed
- go_to_speed:
-	stmfd sp!, {r4 - r6}
-
-	/* move into fast relock bypass */
-	ldr	r4, pll_ctl_add
-	str	r0, [r4]
-wait1:
-	ldr	r5, [r3]		/* get status */
-	and	r5, r5, #0x1		/* isolate core status */
-	cmp	r5, #0x1		/* still locked? */
-	beq	wait1			/* if lock, loop */
-
-	/* set new dpll dividers _after_ in bypass */
-	ldr	r5, pll_div_add1
-	str	r1, [r5]		/* set m, n, m2 */
-	ldr	r5, pll_div_add2
-	str	r2, [r5]		/* set l3/l4/.. dividers*/
-	ldr	r5, pll_div_add3	/* wkup */
-	ldr	r2, pll_div_val3	/* rsm val */
-	str	r2, [r5]
-	ldr	r5, pll_div_add4	/* gfx */
-	ldr	r2, pll_div_val4
-	str	r2, [r5]
-	ldr	r5, pll_div_add5	/* emu */
-	ldr	r2, pll_div_val5
-	str	r2, [r5]
-
-	/* now prepare GPMC (flash) for new dpll speed */
-	/* flash needs to be stable when we jump back to it */
-	ldr	r5, flash_cfg3_addr
-	ldr	r2, flash_cfg3_val
-	str	r2, [r5]
-	ldr	r5, flash_cfg4_addr
-	ldr	r2, flash_cfg4_val
-	str	r2, [r5]
-	ldr	r5, flash_cfg5_addr
-	ldr	r2, flash_cfg5_val
-	str	r2, [r5]
-	ldr	r5, flash_cfg1_addr
-	ldr	r2, [r5]
-	orr	r2, r2, #0x3		/* up gpmc divider */
-	str	r2, [r5]
-
-	/* lock DPLL3 and wait a bit */
-	orr	r0, r0, #0x7	/* set up for lock mode */
-	str	r0, [r4]	/* lock */
-	nop			/* ARM slow at this point working at sys_clk */
-	nop
-	nop
-	nop
-wait2:
-	ldr	r5, [r3]	/* get status */
-	and	r5, r5, #0x1	/* isolate core status */
-	cmp	r5, #0x1	/* still locked? */
-	bne	wait2		/* if lock, loop */
-	nop
-	nop
-	nop
-	nop
-	ldmfd	sp!, {r4 - r6}
-	mov	pc, lr		/* back to caller, locked */
-
-_go_to_speed: .word go_to_speed
-
-/* these constants need to be close for PIC code */
-/* The Nor has to be in the Flash Base CS0 for this condition to happen */
-flash_cfg1_addr:
-	.word (GPMC_CONFIG_CS0_BASE + GPMC_CONFIG1)
-flash_cfg3_addr:
-	.word (GPMC_CONFIG_CS0_BASE + GPMC_CONFIG3)
-flash_cfg3_val:
-	.word STNOR_GPMC_CONFIG3
-flash_cfg4_addr:
-	.word (GPMC_CONFIG_CS0_BASE + GPMC_CONFIG4)
-flash_cfg4_val:
-	.word STNOR_GPMC_CONFIG4
-flash_cfg5_val:
-	.word STNOR_GPMC_CONFIG5
-flash_cfg5_addr:
-	.word (GPMC_CONFIG_CS0_BASE + GPMC_CONFIG5)
-pll_ctl_add:
-	.word CM_CLKEN_PLL
-pll_div_add1:
-	.word CM_CLKSEL1_PLL
-pll_div_add2:
-	.word CM_CLKSEL_CORE
-pll_div_add3:
-	.word CM_CLKSEL_WKUP
-pll_div_val3:
-	.word (WKUP_RSM << 1)
-pll_div_add4:
-	.word CM_CLKSEL_GFX
-pll_div_val4:
-	.word (GFX_DIV << 0)
-pll_div_add5:
-	.word CM_CLKSEL1_EMU
-pll_div_val5:
-	.word CLSEL1_EMU_VAL
-
-#endif
-
-.globl lowlevel_init
-lowlevel_init:
-	ldr	sp, SRAM_STACK
-	str	ip, [sp]	/* stash old link register */
-	mov	ip, lr		/* save link reg across call */
-	bl	s_init		/* go setup pll, mux, memory */
-	ldr	ip, [sp]	/* restore save ip */
-	mov	lr, ip		/* restore link reg */
-
-	/* back to arch calling code */
-	mov	pc, lr
-
-	/* the literal pools origin */
-	.ltorg
-
-REG_CONTROL_STATUS:
-	.word CONTROL_STATUS
-SRAM_STACK:
-	.word LOW_LEVEL_SRAM_STACK
-
-/* DPLL(1-4) PARAM TABLES */
-
-/*
- * Each of the tables has M, N, FREQSEL, M2 values defined for nominal
- * OPP (1.2V). The fields are defined according to dpll_param struct (clock.c).
- * The values are defined for all possible sysclk and for ES1 and ES2.
- */
-
-mpu_dpll_param:
-/* 12MHz */
-/* ES1 */
-.word MPU_M_12_ES1, MPU_N_12_ES1, MPU_FSEL_12_ES1, MPU_M2_12_ES1
-/* ES2 */
-.word MPU_M_12_ES2, MPU_N_12_ES2, MPU_FSEL_12_ES2, MPU_M2_ES2
-/* 3410 */
-.word MPU_M_12, MPU_N_12, MPU_FSEL_12, MPU_M2_12
-
-/* 13MHz */
-/* ES1 */
-.word MPU_M_13_ES1, MPU_N_13_ES1, MPU_FSEL_13_ES1, MPU_M2_13_ES1
-/* ES2 */
-.word MPU_M_13_ES2, MPU_N_13_ES2, MPU_FSEL_13_ES2, MPU_M2_13_ES2
-/* 3410 */
-.word MPU_M_13, MPU_N_13, MPU_FSEL_13, MPU_M2_13
-
-/* 19.2MHz */
-/* ES1 */
-.word MPU_M_19P2_ES1, MPU_N_19P2_ES1, MPU_FSEL_19P2_ES1, MPU_M2_19P2_ES1
-/* ES2 */
-.word MPU_M_19P2_ES2, MPU_N_19P2_ES2, MPU_FSEL_19P2_ES2, MPU_M2_19P2_ES2
-/* 3410 */
-.word MPU_M_19P2, MPU_N_19P2, MPU_FSEL_19P2, MPU_M2_19P2
-
-/* 26MHz */
-/* ES1 */
-.word MPU_M_26_ES1, MPU_N_26_ES1, MPU_FSEL_26_ES1, MPU_M2_26_ES1
-/* ES2 */
-.word MPU_M_26_ES2, MPU_N_26_ES2, MPU_FSEL_26_ES2, MPU_M2_26_ES2
-/* 3410 */
-.word MPU_M_26, MPU_N_26, MPU_FSEL_26, MPU_M2_26
-
-/* 38.4MHz */
-/* ES1 */
-.word MPU_M_38P4_ES1, MPU_N_38P4_ES1, MPU_FSEL_38P4_ES1, MPU_M2_38P4_ES1
-/* ES2 */
-.word MPU_M_38P4_ES2, MPU_N_38P4_ES2, MPU_FSEL_38P4_ES2, MPU_M2_38P4_ES2
-/* 3410 */
-.word MPU_M_38P4, MPU_N_38P4, MPU_FSEL_38P4, MPU_M2_38P4
-
-
-.globl get_mpu_dpll_param
-get_mpu_dpll_param:
-	adr	r0, mpu_dpll_param
-	mov	pc, lr
-
-iva_dpll_param:
-/* 12MHz */
-/* ES1 */
-.word IVA_M_12_ES1, IVA_N_12_ES1, IVA_FSEL_12_ES1, IVA_M2_12_ES1
-/* ES2 */
-.word IVA_M_12_ES2, IVA_N_12_ES2, IVA_FSEL_12_ES2, IVA_M2_12_ES2
-/* 3410 */
-.word IVA_M_12, IVA_N_12, IVA_FSEL_12, IVA_M2_12
-
-/* 13MHz */
-/* ES1 */
-.word IVA_M_13_ES1, IVA_N_13_ES1, IVA_FSEL_13_ES1, IVA_M2_13_ES1
-/* ES2 */
-.word IVA_M_13_ES2, IVA_N_13_ES2,  IVA_FSEL_13_ES2, IVA_M2_13_ES2
-/* 3410 */
-.word IVA_M_13, IVA_N_13, IVA_FSEL_13, IVA_M2_13
-
-/* 19.2MHz */
-/* ES1 */
-.word IVA_M_19P2_ES1, IVA_N_19P2_ES1, IVA_FSEL_19P2_ES1, IVA_M2_19P2_ES1
-/* ES2 */
-.word IVA_M_19P2_ES2, IVA_N_19P2_ES2, IVA_FSEL_19P2_ES2, IVA_M2_19P2_ES2
-/* 3410 */
-.word IVA_M_19P2, IVA_N_19P2, IVA_FSEL_19P2, IVA_M2_19P2
-
-/* 26MHz */
-/* ES1 */
-.word IVA_M_26_ES1, IVA_N_26_ES1, IVA_FSEL_26_ES1, IVA_M2_26_ES1
-/* ES2 */
-.word IVA_M_26_ES2, IVA_N_26_ES2, IVA_FSEL_26_ES2, IVA_M2_26_ES2
-/* 3410 */
-.word IVA_M_26, IVA_N_26, IVA_FSEL_26, IVA_M2_26
-
-/* 38.4MHz */
-/* ES1 */
-.word IVA_M_38P4_ES1, IVA_N_38P4_ES1, IVA_FSEL_38P4_ES1, IVA_M2_38P4_ES1
-/* ES2 */
-.word IVA_M_38P4_ES2, IVA_N_38P4_ES2, IVA_FSEL_38P4_ES2, IVA_M2_38P4_ES2
-/* 3410 */
-.word IVA_M_38P4, IVA_N_38P4, IVA_FSEL_38P4, IVA_M2_38P4
-
-
-.globl get_iva_dpll_param
-get_iva_dpll_param:
-	adr	r0, iva_dpll_param
-	mov	pc, lr
-
-/* Core DPLL targets for L3 at 166 & L133 */
-core_dpll_param:
-/* 12MHz */
-/* ES1 */
-.word CORE_M_12_ES1, CORE_N_12_ES1, CORE_FSL_12_ES1, CORE_M2_12_ES1
-/* ES2 */
-.word CORE_M_12, CORE_N_12, CORE_FSEL_12, CORE_M2_12
-/* 3410 */
-.word CORE_M_12, CORE_N_12, CORE_FSEL_12, CORE_M2_12
-
-/* 13MHz */
-/* ES1 */
-.word CORE_M_13_ES1, CORE_N_13_ES1, CORE_FSL_13_ES1, CORE_M2_13_ES1
-/* ES2 */
-.word CORE_M_13, CORE_N_13, CORE_FSEL_13, CORE_M2_13
-/* 3410 */
-.word CORE_M_13, CORE_N_13, CORE_FSEL_13, CORE_M2_13
-
-/* 19.2MHz */
-/* ES1 */
-.word CORE_M_19P2_ES1, CORE_N_19P2_ES1, CORE_FSL_19P2_ES1, CORE_M2_19P2_ES1
-/* ES2 */
-.word CORE_M_19P2, CORE_N_19P2, CORE_FSEL_19P2, CORE_M2_19P2
-/* 3410 */
-.word CORE_M_19P2, CORE_N_19P2, CORE_FSEL_19P2, CORE_M2_19P2
-
-/* 26MHz */
-/* ES1 */
-.word CORE_M_26_ES1, CORE_N_26_ES1, CORE_FSL_26_ES1, CORE_M2_26_ES1
-/* ES2 */
-.word CORE_M_26, CORE_N_26, CORE_FSEL_26, CORE_M2_26
-/* 3410 */
-.word CORE_M_26, CORE_N_26, CORE_FSEL_26, CORE_M2_26
-
-/* 38.4MHz */
-/* ES1 */
-.word CORE_M_38P4_ES1, CORE_N_38P4_ES1, CORE_FSL_38P4_ES1, CORE_M2_38P4_ES1
-/* ES2 */
-.word CORE_M_38P4, CORE_N_38P4, CORE_FSEL_38P4, CORE_M2_38P4
-/* 3410 */
-.word CORE_M_38P4, CORE_N_38P4, CORE_FSEL_38P4, CORE_M2_38P4
-
-.globl get_core_dpll_param
-get_core_dpll_param:
-	adr	r0, core_dpll_param
-	mov	pc, lr
-
-/* PER DPLL values are same for both ES1 and ES2 */
-per_dpll_param:
-/* 12MHz */
-.word PER_M_12, PER_N_12, PER_FSEL_12, PER_M2_12
-
-/* 13MHz */
-.word PER_M_13, PER_N_13, PER_FSEL_13, PER_M2_13
-
-/* 19.2MHz */
-.word PER_M_19P2, PER_N_19P2, PER_FSEL_19P2, PER_M2_19P2
-
-/* 26MHz */
-.word PER_M_26, PER_N_26, PER_FSEL_26, PER_M2_26
-
-/* 38.4MHz */
-.word PER_M_38P4, PER_N_38P4, PER_FSEL_38P4, PER_M2_38P4
-
-.globl get_per_dpll_param
-get_per_dpll_param:
-	adr	r0, per_dpll_param
-	mov	pc, lr
-
-/*
- * Tables for 36XX/37XX devices
- *
- */
-mpu_36x_dpll_param:
-/* 12MHz */
-.word 50, 0, 0, 1
-/* 13MHz */
-.word 600, 12, 0, 1
-/* 19.2MHz */
-.word 125, 3, 0, 1
-/* 26MHz */
-.word 300, 12, 0, 1
-/* 38.4MHz */
-.word 125, 7, 0, 1
-
-iva_36x_dpll_param:
-/* 12MHz */
-.word 130, 2, 0, 1
-/* 13MHz */
-.word 20, 0, 0, 1
-/* 19.2MHz */
-.word 325, 11, 0, 1
-/* 26MHz */
-.word 10, 0, 0, 1
-/* 38.4MHz */
-.word 325, 23, 0, 1
-
-core_36x_dpll_param:
-/* 12MHz */
-.word 100, 2, 0, 1
-/* 13MHz */
-.word 400, 12, 0, 1
-/* 19.2MHz */
-.word 375, 17, 0, 1
-/* 26MHz */
-.word 200, 12, 0, 1
-/* 38.4MHz */
-.word 375, 35, 0, 1
-
-per_36x_dpll_param:
-/*    SYSCLK    M       N      M2      M3      M4     M5      M6      m2DIV */
-.word 12000,    360,    4,     9,      16,     5,     4,      3,      1
-.word 13000,    864,   12,     9,      16,     9,     4,      3,      1
-.word 19200,    360,    7,     9,      16,     5,     4,      3,      1
-.word 26000,    432,   12,     9,      16,     9,     4,      3,      1
-.word 38400,    360,   15,     9,      16,     5,     4,      3,      1
-
-.globl get_36x_mpu_dpll_param
-get_36x_mpu_dpll_param:
-	adr	r0, mpu_36x_dpll_param
-	mov	pc, lr
-
-.globl get_36x_iva_dpll_param
-get_36x_iva_dpll_param:
-	adr	r0, iva_36x_dpll_param
-	mov	pc, lr
-
-.globl get_36x_core_dpll_param
-get_36x_core_dpll_param:
-	adr	r0, core_36x_dpll_param
-	mov	pc, lr
-
-.globl get_36x_per_dpll_param
-get_36x_per_dpll_param:
-	adr	r0, per_36x_dpll_param
-	mov	pc, lr
diff --git a/arch/arm/cpu/armv7/omap3/mem.c b/arch/arm/cpu/armv7/omap3/mem.c
deleted file mode 100644
index bd914b0..0000000
--- a/arch/arm/cpu/armv7/omap3/mem.c
+++ /dev/null
@@ -1,191 +0,0 @@
-/*
- * (C) Copyright 2008
- * Texas Instruments, <www.ti.com>
- *
- * Author :
- *     Manikandan Pillai <mani.pillai@ti.com>
- *
- * Initial Code from:
- *     Richard Woodruff <r-woodruff2@ti.com>
- *     Syed Mohammed Khasim <khasim@ti.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/mem.h>
-#include <asm/arch/sys_proto.h>
-#include <command.h>
-
-/*
- * Only One NAND allowed on board at a time.
- * The GPMC CS Base for the same
- */
-unsigned int boot_flash_base;
-unsigned int boot_flash_off;
-unsigned int boot_flash_sec;
-unsigned int boot_flash_type;
-volatile unsigned int boot_flash_env_addr;
-
-struct gpmc *gpmc_cfg;
-
-#if defined(CONFIG_CMD_NAND)
-static const u32 gpmc_m_nand[GPMC_MAX_REG] = {
-	M_NAND_GPMC_CONFIG1,
-	M_NAND_GPMC_CONFIG2,
-	M_NAND_GPMC_CONFIG3,
-	M_NAND_GPMC_CONFIG4,
-	M_NAND_GPMC_CONFIG5,
-	M_NAND_GPMC_CONFIG6, 0
-};
-
-#if defined(CONFIG_ENV_IS_IN_NAND)
-#define GPMC_CS 0
-#else
-#define GPMC_CS 1
-#endif
-
-#endif
-
-#if defined(CONFIG_CMD_ONENAND)
-static const u32 gpmc_onenand[GPMC_MAX_REG] = {
-	ONENAND_GPMC_CONFIG1,
-	ONENAND_GPMC_CONFIG2,
-	ONENAND_GPMC_CONFIG3,
-	ONENAND_GPMC_CONFIG4,
-	ONENAND_GPMC_CONFIG5,
-	ONENAND_GPMC_CONFIG6, 0
-};
-
-#if defined(CONFIG_ENV_IS_IN_ONENAND)
-#define GPMC_CS 0
-#else
-#define GPMC_CS 1
-#endif
-
-#endif
-
-/********************************************************
- *  mem_ok() - test used to see if timings are correct
- *             for a part. Helps in guessing which part
- *             we are currently using.
- *******************************************************/
-u32 mem_ok(u32 cs)
-{
-	u32 val1, val2, addr;
-	u32 pattern = 0x12345678;
-
-	addr = OMAP34XX_SDRC_CS0 + get_sdr_cs_offset(cs);
-
-	writel(0x0, addr + 0x400);	/* clear pos A */
-	writel(pattern, addr);		/* pattern to pos B */
-	writel(0x0, addr + 4);		/* remove pattern off the bus */
-	val1 = readl(addr + 0x400);	/* get pos A value */
-	val2 = readl(addr);		/* get val2 */
-
-	if ((val1 != 0) || (val2 != pattern))	/* see if pos A val changed */
-		return 0;
-	else
-		return 1;
-}
-
-void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base,
-			u32 size)
-{
-	writel(0, &cs->config7);
-	sdelay(1000);
-	/* Delay for settling */
-	writel(gpmc_config[0], &cs->config1);
-	writel(gpmc_config[1], &cs->config2);
-	writel(gpmc_config[2], &cs->config3);
-	writel(gpmc_config[3], &cs->config4);
-	writel(gpmc_config[4], &cs->config5);
-	writel(gpmc_config[5], &cs->config6);
-	/* Enable the config */
-	writel((((size & 0xF) << 8) | ((base >> 24) & 0x3F) |
-		(1 << 6)), &cs->config7);
-	sdelay(2000);
-}
-
-/*****************************************************
- * gpmc_init(): init gpmc bus
- * Init GPMC for x16, MuxMode (SDRAM in x32).
- * This code can only be executed from SRAM or SDRAM.
- *****************************************************/
-void gpmc_init(void)
-{
-	/* putting a blanket check on GPMC based on ZeBu for now */
-	gpmc_cfg = (struct gpmc *)GPMC_BASE;
-#if defined(CONFIG_CMD_NAND) || defined(CONFIG_CMD_ONENAND)
-	const u32 *gpmc_config = NULL;
-	u32 base = 0;
-	u32 size = 0;
-#if defined(CONFIG_ENV_IS_IN_NAND) || defined(CONFIG_ENV_IS_IN_ONENAND)
-	u32 f_off = CONFIG_SYS_MONITOR_LEN;
-	u32 f_sec = 0;
-#endif
-#endif
-	u32 config = 0;
-
-	/* global settings */
-	writel(0, &gpmc_cfg->irqenable); /* isr's sources masked */
-	writel(0, &gpmc_cfg->timeout_control);/* timeout disable */
-
-	config = readl(&gpmc_cfg->config);
-	config &= (~0xf00);
-	writel(config, &gpmc_cfg->config);
-
-	/*
-	 * Disable the GPMC0 config set by ROM code
-	 * It conflicts with our MPDB (both at 0x08000000)
-	 */
-	writel(0, &gpmc_cfg->cs[0].config7);
-	sdelay(1000);
-
-#if defined(CONFIG_CMD_NAND)	/* CS 0 */
-	gpmc_config = gpmc_m_nand;
-
-	base = PISMO1_NAND_BASE;
-	size = PISMO1_NAND_SIZE;
-	enable_gpmc_cs_config(gpmc_config, &gpmc_cfg->cs[0], base, size);
-#if defined(CONFIG_ENV_IS_IN_NAND)
-	f_off = SMNAND_ENV_OFFSET;
-	f_sec = (128 << 10);	/* 128 KiB */
-	/* env setup */
-	boot_flash_base = base;
-	boot_flash_off = f_off;
-	boot_flash_sec = f_sec;
-	boot_flash_env_addr = f_off;
-#endif
-#endif
-
-#if defined(CONFIG_CMD_ONENAND)
-	gpmc_config = gpmc_onenand;
-	base = PISMO1_ONEN_BASE;
-	size = PISMO1_ONEN_SIZE;
-	enable_gpmc_cs_config(gpmc_config, &gpmc_cfg->cs[0], base, size);
-#if defined(CONFIG_ENV_IS_IN_ONENAND)
-	f_off = ONENAND_ENV_OFFSET;
-	f_sec = (128 << 10);	/* 128 KiB */
-	/* env setup */
-	boot_flash_base = base;
-	boot_flash_off = f_off;
-	boot_flash_sec = f_sec;
-	boot_flash_env_addr = f_off;
-#endif
-#endif
-}
diff --git a/arch/arm/cpu/armv7/omap3/sdrc.c b/arch/arm/cpu/armv7/omap3/sdrc.c
deleted file mode 100644
index 2a7970b..0000000
--- a/arch/arm/cpu/armv7/omap3/sdrc.c
+++ /dev/null
@@ -1,217 +0,0 @@
-/*
- * Functions related to OMAP3 SDRC.
- *
- * This file has been created after exctracting and consolidating
- * the SDRC related content from mem.c and board.c, also created
- * generic init function (mem_init).
- *
- * Copyright (C) 2004-2010
- * Texas Instruments Incorporated - http://www.ti.com/
- *
- * Author :
- *     Vaibhav Hiremath <hvaibhav@ti.com>
- *
- * Original implementation by (mem.c, board.c) :
- *      Sunil Kumar <sunilsaini05@gmail.com>
- *      Shashi Ranjan <shashiranjanmca05@gmail.com>
- *      Manikandan Pillai <mani.pillai@ti.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/mem.h>
-#include <asm/arch/sys_proto.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-extern omap3_sysinfo sysinfo;
-
-static struct sdrc *sdrc_base = (struct sdrc *)OMAP34XX_SDRC_BASE;
-
-/*
- * is_mem_sdr -
- *  - Return 1 if mem type in use is SDR
- */
-u32 is_mem_sdr(void)
-{
-	if (readl(&sdrc_base->cs[CS0].mr) == SDRC_MR_0_SDR)
-		return 1;
-	return 0;
-}
-
-/*
- * make_cs1_contiguous -
- *  - For es2 and above remap cs1 behind cs0 to allow command line
- *    mem=xyz use all memory with out discontinuous support compiled in.
- *    Could do it at the ATAG, but there really is two banks...
- *  - Called as part of 2nd phase DDR init.
- */
-void make_cs1_contiguous(void)
-{
-	u32 size, a_add_low, a_add_high;
-
-	size = get_sdr_cs_size(CS0);
-	size >>= 25;	/* divide by 32 MiB to find size to offset CS1 */
-	a_add_high = (size & 3) << 8;	/* set up low field */
-	a_add_low = (size & 0x3C) >> 2;	/* set up high field */
-	writel((a_add_high | a_add_low), &sdrc_base->cs_cfg);
-
-}
-
-
-/*
- * get_sdr_cs_size -
- *  - Get size of chip select 0/1
- */
-u32 get_sdr_cs_size(u32 cs)
-{
-	u32 size;
-
-	/* get ram size field */
-	size = readl(&sdrc_base->cs[cs].mcfg) >> 8;
-	size &= 0x3FF;		/* remove unwanted bits */
-	size <<= 21;		/* multiply by 2 MiB to find size in MB */
-	return size;
-}
-
-/*
- * get_sdr_cs_offset -
- *  - Get offset of cs from cs0 start
- */
-u32 get_sdr_cs_offset(u32 cs)
-{
-	u32 offset;
-
-	if (!cs)
-		return 0;
-
-	offset = readl(&sdrc_base->cs_cfg);
-	offset = (offset & 15) << 27 | (offset & 0x30) << 17;
-
-	return offset;
-}
-
-/*
- * do_sdrc_init -
- *  - Initialize the SDRAM for use.
- *  - code called once in C-Stack only context for CS0 and a possible 2nd
- *    time depending on memory configuration from stack+global context
- */
-void do_sdrc_init(u32 cs, u32 early)
-{
-	struct sdrc_actim *sdrc_actim_base0, *sdrc_actim_base1;
-
-	if (early) {
-		/* reset sdrc controller */
-		writel(SOFTRESET, &sdrc_base->sysconfig);
-		wait_on_value(RESETDONE, RESETDONE, &sdrc_base->status,
-				12000000);
-		writel(0, &sdrc_base->sysconfig);
-
-		/* setup sdrc to ball mux */
-		writel(SDRC_SHARING, &sdrc_base->sharing);
-
-		/* Disable Power Down of CKE cuz of 1 CKE on combo part */
-		writel(WAKEUPPROC | SRFRONRESET | PAGEPOLICY_HIGH,
-				&sdrc_base->power);
-
-		writel(ENADLL | DLLPHASE_90, &sdrc_base->dlla_ctrl);
-		sdelay(0x20000);
-	}
-
-	/*
-	 * SDRC timings are set up by x-load or config header
-	 * We don't need to redo them here.
-	 * Older x-loads configure only CS0
-	 * configure CS1 to handle this ommission
-	 */
-	if (cs) {
-		sdrc_actim_base0 = (struct sdrc_actim *)SDRC_ACTIM_CTRL0_BASE;
-		sdrc_actim_base1 = (struct sdrc_actim *)SDRC_ACTIM_CTRL1_BASE;
-		writel(readl(&sdrc_base->cs[CS0].mcfg),
-			&sdrc_base->cs[CS1].mcfg);
-		writel(readl(&sdrc_base->cs[CS0].rfr_ctrl),
-			&sdrc_base->cs[CS1].rfr_ctrl);
-		writel(readl(&sdrc_actim_base0->ctrla),
-			&sdrc_actim_base1->ctrla);
-		writel(readl(&sdrc_actim_base0->ctrlb),
-			&sdrc_actim_base1->ctrlb);
-
-		writel(CMD_NOP, &sdrc_base->cs[cs].manual);
-		writel(CMD_PRECHARGE, &sdrc_base->cs[cs].manual);
-		writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual);
-		writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual);
-		writel(readl(&sdrc_base->cs[CS0].mr),
-			&sdrc_base->cs[CS1].mr);
-	}
-
-	/*
-	 * Test ram in this bank
-	 * Disable if bad or not present
-	 */
-	if (!mem_ok(cs))
-		writel(0, &sdrc_base->cs[cs].mcfg);
-}
-
-/*
- * dram_init -
- *  - Sets uboots idea of sdram size
- */
-int dram_init(void)
-{
-	unsigned int size0 = 0, size1 = 0;
-
-	size0 = get_sdr_cs_size(CS0);
-	/*
-	 * If a second bank of DDR is attached to CS1 this is
-	 * where it can be started.  Early init code will init
-	 * memory on CS0.
-	 */
-	if ((sysinfo.mtype == DDR_COMBO) || (sysinfo.mtype == DDR_STACKED)) {
-		do_sdrc_init(CS1, NOT_EARLY);
-		make_cs1_contiguous();
-
-		size1 = get_sdr_cs_size(CS1);
-	}
-	gd->ram_size = size0 + size1;
-
-	return 0;
-}
-
-void dram_init_banksize (void)
-{
-	unsigned int size0 = 0, size1 = 0;
-
-	size0 = get_sdr_cs_size(CS0);
-	size1 = get_sdr_cs_size(CS1);
-
-	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
-	gd->bd->bi_dram[0].size = size0;
-	gd->bd->bi_dram[1].start = PHYS_SDRAM_1 + get_sdr_cs_offset(CS1);
-	gd->bd->bi_dram[1].size = size1;
-}
-
-/*
- * mem_init -
- *  - Init the sdrc chip,
- *  - Selects CS0 and CS1,
- */
-void mem_init(void)
-{
-	/* only init up first bank here */
-	do_sdrc_init(CS0, EARLY_INIT);
-}
diff --git a/arch/arm/cpu/armv7/omap3/sys_info.c b/arch/arm/cpu/armv7/omap3/sys_info.c
deleted file mode 100644
index 549ac19..0000000
--- a/arch/arm/cpu/armv7/omap3/sys_info.c
+++ /dev/null
@@ -1,353 +0,0 @@
-/*
- * (C) Copyright 2008
- * Texas Instruments, <www.ti.com>
- *
- * Author :
- *      Manikandan Pillai <mani.pillai@ti.com>
- *
- * Derived from Beagle Board and 3430 SDP code by
- *      Richard Woodruff <r-woodruff2@ti.com>
- *      Syed Mohammed Khasim <khasim@ti.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/mem.h>	/* get mem tables */
-#include <asm/arch/sys_proto.h>
-#include <i2c.h>
-
-extern omap3_sysinfo sysinfo;
-static struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
-static char *rev_s[CPU_3XX_MAX_REV] = {
-				"1.0",
-				"2.0",
-				"2.1",
-				"3.0",
-				"3.1",
-				"UNKNOWN",
-				"UNKNOWN",
-				"3.1.2"};
-
-/*****************************************************************
- * dieid_num_r(void) - read and set die ID
- *****************************************************************/
-void dieid_num_r(void)
-{
-	struct ctrl_id *id_base = (struct ctrl_id *)OMAP34XX_ID_L4_IO_BASE;
-	char *uid_s, die_id[34];
-	u32 id[4];
-
-	memset(die_id, 0, sizeof(die_id));
-
-	uid_s = getenv("dieid#");
-
-	if (uid_s == NULL) {
-		id[3] = readl(&id_base->die_id_0);
-		id[2] = readl(&id_base->die_id_1);
-		id[1] = readl(&id_base->die_id_2);
-		id[0] = readl(&id_base->die_id_3);
-		sprintf(die_id, "%08x%08x%08x%08x", id[0], id[1], id[2], id[3]);
-		setenv("dieid#", die_id);
-		uid_s = die_id;
-	}
-
-	printf("Die ID #%s\n", uid_s);
-}
-
-/******************************************
- * get_cpu_type(void) - extract cpu info
- ******************************************/
-u32 get_cpu_type(void)
-{
-	return readl(&ctrl_base->ctrl_omap_stat);
-}
-
-/******************************************
- * get_cpu_id(void) - extract cpu id
- * returns 0 for ES1.0, cpuid otherwise
- ******************************************/
-u32 get_cpu_id(void)
-{
-	struct ctrl_id *id_base;
-	u32 cpuid = 0;
-
-	/*
-	 * On ES1.0 the IDCODE register is not exposed on L4
-	 * so using CPU ID to differentiate between ES1.0 and > ES1.0.
-	 */
-	__asm__ __volatile__("mrc p15, 0, %0, c0, c0, 0":"=r"(cpuid));
-	if ((cpuid & 0xf) == 0x0) {
-		return 0;
-	} else {
-		/* Decode the IDs on > ES1.0 */
-		id_base = (struct ctrl_id *) OMAP34XX_ID_L4_IO_BASE;
-
-		cpuid = readl(&id_base->idcode);
-	}
-
-	return cpuid;
-}
-
-/******************************************
- * get_cpu_family(void) - extract cpu info
- ******************************************/
-u32 get_cpu_family(void)
-{
-	u16 hawkeye;
-	u32 cpu_family;
-	u32 cpuid = get_cpu_id();
-
-	if (cpuid == 0)
-		return CPU_OMAP34XX;
-
-	hawkeye = (cpuid >> HAWKEYE_SHIFT) & 0xffff;
-	switch (hawkeye) {
-	case HAWKEYE_OMAP34XX:
-		cpu_family = CPU_OMAP34XX;
-		break;
-	case HAWKEYE_AM35XX:
-		cpu_family = CPU_AM35XX;
-		break;
-	case HAWKEYE_OMAP36XX:
-		cpu_family = CPU_OMAP36XX;
-		break;
-	default:
-		cpu_family = CPU_OMAP34XX;
-	}
-
-	return cpu_family;
-}
-
-/******************************************
- * get_cpu_rev(void) - extract version info
- ******************************************/
-u32 get_cpu_rev(void)
-{
-	u32 cpuid = get_cpu_id();
-
-	if (cpuid == 0)
-		return CPU_3XX_ES10;
-	else
-		return (cpuid >> CPU_3XX_ID_SHIFT) & 0xf;
-}
-
-/*****************************************************************
- * get_sku_id(void) - read sku_id to get info on max clock rate
- *****************************************************************/
-u32 get_sku_id(void)
-{
-	struct ctrl_id *id_base = (struct ctrl_id *)OMAP34XX_ID_L4_IO_BASE;
-	return readl(&id_base->sku_id) & SKUID_CLK_MASK;
-}
-
-/***************************************************************************
- *  get_gpmc0_base() - Return current address hardware will be
- *     fetching from. The below effectively gives what is correct, its a bit
- *   mis-leading compared to the TRM.  For the most general case the mask
- *   needs to be also taken into account this does work in practice.
- *   - for u-boot we currently map:
- *       -- 0 to nothing,
- *       -- 4 to flash
- *       -- 8 to enent
- *       -- c to wifi
- ****************************************************************************/
-u32 get_gpmc0_base(void)
-{
-	u32 b;
-
-	b = readl(&gpmc_cfg->cs[0].config7);
-	b &= 0x1F;		/* keep base [5:0] */
-	b = b << 24;		/* ret 0x0b000000 */
-	return b;
-}
-
-/*******************************************************************
- * get_gpmc0_width() - See if bus is in x8 or x16 (mainly for nand)
- *******************************************************************/
-u32 get_gpmc0_width(void)
-{
-	return WIDTH_16BIT;
-}
-
-/*************************************************************************
- * get_board_rev() - setup to pass kernel board revision information
- * returns:(bit[0-3] sub version, higher bit[7-4] is higher version)
- *************************************************************************/
-u32 get_board_rev(void)
-{
-	return 0x20;
-}
-
-/********************************************************
- *  get_base(); get upper addr of current execution
- *******************************************************/
-u32 get_base(void)
-{
-	u32 val;
-
-	__asm__ __volatile__("mov %0, pc \n":"=r"(val)::"memory");
-	val &= 0xF0000000;
-	val >>= 28;
-	return val;
-}
-
-/********************************************************
- *  is_running_in_flash() - tell if currently running in
- *  FLASH.
- *******************************************************/
-u32 is_running_in_flash(void)
-{
-	if (get_base() < 4)
-		return 1;	/* in FLASH */
-
-	return 0;		/* running in SRAM or SDRAM */
-}
-
-/********************************************************
- *  is_running_in_sram() - tell if currently running in
- *  SRAM.
- *******************************************************/
-u32 is_running_in_sram(void)
-{
-	if (get_base() == 4)
-		return 1;	/* in SRAM */
-
-	return 0;		/* running in FLASH or SDRAM */
-}
-
-/********************************************************
- *  is_running_in_sdram() - tell if currently running in
- *  SDRAM.
- *******************************************************/
-u32 is_running_in_sdram(void)
-{
-	if (get_base() > 4)
-		return 1;	/* in SDRAM */
-
-	return 0;		/* running in SRAM or FLASH */
-}
-
-/***************************************************************
- *  get_boot_type() - Is this an XIP type device or a stream one
- *  bits 4-0 specify type. Bit 5 says mem/perif
- ***************************************************************/
-u32 get_boot_type(void)
-{
-	return (readl(&ctrl_base->status) & SYSBOOT_MASK);
-}
-
-/*************************************************************
- *  get_device_type(): tell if GP/HS/EMU/TST
- *************************************************************/
-u32 get_device_type(void)
-{
-	return ((readl(&ctrl_base->status) & (DEVICE_MASK)) >> 8);
-}
-
-#ifdef CONFIG_DISPLAY_CPUINFO
-/**
- * Print CPU information
- */
-int print_cpuinfo (void)
-{
-	char *cpu_family_s, *cpu_s, *sec_s, *max_clk;
-
-	switch (get_cpu_family()) {
-	case CPU_OMAP34XX:
-		cpu_family_s = "OMAP";
-		switch (get_cpu_type()) {
-		case OMAP3503:
-			cpu_s = "3503";
-			break;
-		case OMAP3515:
-			cpu_s = "3515";
-			break;
-		case OMAP3525:
-			cpu_s = "3525";
-			break;
-		case OMAP3530:
-			cpu_s = "3530";
-			break;
-		default:
-			cpu_s = "35XX";
-			break;
-		}
-		if ((get_cpu_rev() >= CPU_3XX_ES31) &&
-		    (get_sku_id() == SKUID_CLK_720MHZ))
-			max_clk = "720 mHz";
-		else
-			max_clk = "600 mHz";
-
-		break;
-	case CPU_AM35XX:
-		cpu_family_s = "AM";
-		switch (get_cpu_type()) {
-		case AM3505:
-			cpu_s = "3505";
-			break;
-		case AM3517:
-			cpu_s = "3517";
-			break;
-		default:
-			cpu_s = "35XX";
-			break;
-		}
-		max_clk = "600 Mhz";
-		break;
-	case CPU_OMAP36XX:
-		cpu_family_s = "OMAP";
-		switch (get_cpu_type()) {
-		case OMAP3730:
-			cpu_s = "3630/3730";
-			break;
-		default:
-			cpu_s = "36XX/37XX";
-			break;
-		}
-		max_clk = "1 Ghz";
-		break;
-	default:
-		cpu_family_s = "OMAP";
-		cpu_s = "35XX";
-		max_clk = "600 Mhz";
-	}
-
-	switch (get_device_type()) {
-	case TST_DEVICE:
-		sec_s = "TST";
-		break;
-	case EMU_DEVICE:
-		sec_s = "EMU";
-		break;
-	case HS_DEVICE:
-		sec_s = "HS";
-		break;
-	case GP_DEVICE:
-		sec_s = "GP";
-		break;
-	default:
-		sec_s = "?";
-	}
-
-	printf("%s%s-%s ES%s, CPU-OPP2, L3-165MHz, Max CPU Clock %s\n",
-			cpu_family_s, cpu_s, sec_s,
-			rev_s[get_cpu_rev()], max_clk);
-
-	return 0;
-}
-#endif	/* CONFIG_DISPLAY_CPUINFO */
diff --git a/arch/arm/cpu/armv7/omap4/Makefile b/arch/arm/cpu/armv7/omap4/Makefile
deleted file mode 100644
index 987dc9d..0000000
--- a/arch/arm/cpu/armv7/omap4/Makefile
+++ /dev/null
@@ -1,49 +0,0 @@
-#
-# (C) Copyright 2000-2010
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB	=  $(obj)lib$(SOC).o
-
-SOBJS	+= lowlevel_init.o
-
-COBJS	+= board.o
-COBJS	+= mem.o
-COBJS	+= sys_info.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS) $(SOBJS))
-
-all:	 $(obj).depend $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/arch/arm/cpu/armv7/omap4/board.c b/arch/arm/cpu/armv7/omap4/board.c
deleted file mode 100644
index fcd29a7..0000000
--- a/arch/arm/cpu/armv7/omap4/board.c
+++ /dev/null
@@ -1,129 +0,0 @@
-/*
- *
- * Common functions for OMAP4 based boards
- *
- * (C) Copyright 2010
- * Texas Instruments, <www.ti.com>
- *
- * Author :
- *	Aneesh V	<aneesh@ti.com>
- *	Steve Sakoman	<steve@sakoman.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-#include <common.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/sizes.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*
- * Routine: s_init
- * Description: Does early system init of muxing and clocks.
- *              - Called path is with SRAM stack.
- */
-void s_init(void)
-{
-	watchdog_init();
-}
-
-/*
- * Routine: wait_for_command_complete
- * Description: Wait for posting to finish on watchdog
- */
-void wait_for_command_complete(struct watchdog *wd_base)
-{
-	int pending = 1;
-	do {
-		pending = readl(&wd_base->wwps);
-	} while (pending);
-}
-
-/*
- * Routine: watchdog_init
- * Description: Shut down watch dogs
- */
-void watchdog_init(void)
-{
-	struct watchdog *wd2_base = (struct watchdog *)WDT2_BASE;
-
-	writel(WD_UNLOCK1, &wd2_base->wspr);
-	wait_for_command_complete(wd2_base);
-	writel(WD_UNLOCK2, &wd2_base->wspr);
-}
-
-
-/*
- * This function finds the SDRAM size available in the system
- * based on DMM section configurations
- * This is needed because the size of memory installed may be
- * different on different versions of the board
- */
-u32 sdram_size(void)
-{
-	u32 section, i, total_size = 0, size, addr;
-	for (i = 0; i < 4; i++) {
-		section	= __raw_readl(DMM_LISA_MAP_BASE + i*4);
-		addr = section & DMM_LISA_MAP_SYS_ADDR_MASK;
-		/* See if the address is valid */
-		if ((addr >= OMAP44XX_DRAM_ADDR_SPACE_START) &&
-		    (addr < OMAP44XX_DRAM_ADDR_SPACE_END)) {
-			size	= ((section & DMM_LISA_MAP_SYS_SIZE_MASK) >>
-				    DMM_LISA_MAP_SYS_SIZE_SHIFT);
-			size	= 1 << size;
-			size	*= SZ_16M;
-			total_size += size;
-		}
-	}
-	return total_size;
-}
-
-
-/*
- * Routine: dram_init
- * Description: sets uboots idea of sdram size
- */
-int dram_init(void)
-{
-
-	gd->ram_size = sdram_size();
-
-	return 0;
-}
-
-/*
- * Print board information
- */
-int checkboard(void)
-{
-	puts(sysinfo.board_string);
-	return 0;
-}
-
-/*
-* This function is called by start_armboot. You can reliably use static
-* data. Any boot-time function that require static data should be
-* called from here
-*/
-int arch_cpu_init(void)
-{
-	set_muxconf_regs();
-	return 0;
-}
diff --git a/arch/arm/cpu/armv7/omap4/lowlevel_init.S b/arch/arm/cpu/armv7/omap4/lowlevel_init.S
deleted file mode 100644
index 026dfa4..0000000
--- a/arch/arm/cpu/armv7/omap4/lowlevel_init.S
+++ /dev/null
@@ -1,47 +0,0 @@
-/*
- * Board specific setup info
- *
- * (C) Copyright 2010
- * Texas Instruments, <www.ti.com>
- *
- * Author :
- *	Aneesh V	<aneesh@ti.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <asm/arch/omap4.h>
-
-.globl lowlevel_init
-lowlevel_init:
-	/*
-	 * Setup a temporary stack
-	 */
-	ldr	sp, =LOW_LEVEL_SRAM_STACK
-
-	/*
-	 * Save the old lr(passed in ip) and the current lr to stack
-	 */
-	push	{ip, lr}
-
-	/*
-	 * go setup pll, mux, memory
-	 */
-	bl	s_init
-	pop	{ip, pc}
diff --git a/arch/arm/cpu/armv7/omap4/mem.c b/arch/arm/cpu/armv7/omap4/mem.c
deleted file mode 100644
index 878f0e3..0000000
--- a/arch/arm/cpu/armv7/omap4/mem.c
+++ /dev/null
@@ -1,45 +0,0 @@
-/*
- * (C) Copyright 2010
- * Texas Instruments, <www.ti.com>
- *
- * Steve Sakoman <steve@sakoman.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <asm/arch/cpu.h>
-#include <asm/arch/sys_proto.h>
-
-struct gpmc *gpmc_cfg;
-
-/*****************************************************
- * gpmc_init(): init gpmc bus
- * This code can only be executed from SRAM or SDRAM.
- *****************************************************/
-void gpmc_init(void)
-{
-	gpmc_cfg = (struct gpmc *)GPMC_BASE;
-
-	/* global settings */
-	writel(0, &gpmc_cfg->irqenable); /* isr's sources masked */
-	writel(0, &gpmc_cfg->timeout_control);/* timeout disable */
-
-	/*
-	 * Disable the GPMC0 config set by ROM code
-	 * It conflicts with our MPDB (both at 0x08000000)
-	 */
-	writel(0, &gpmc_cfg->cs[0].config7);
-}
diff --git a/arch/arm/cpu/armv7/omap4/sys_info.c b/arch/arm/cpu/armv7/omap4/sys_info.c
deleted file mode 100644
index b9e5765..0000000
--- a/arch/arm/cpu/armv7/omap4/sys_info.c
+++ /dev/null
@@ -1,53 +0,0 @@
-/*
- * (C) Copyright 2010
- * Texas Instruments, <www.ti.com>
- *
- * Author :
- *	Aneesh V	<aneesh@ti.com>
- *	Steve Sakoman	<steve@sakoman.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/arch/sys_proto.h>
-
-/*
- *  get_device_type(): tell if GP/HS/EMU/TST
- */
-u32 get_device_type(void)
-{
-	return 0;
-}
-
-/*
- * get_board_rev() - get board revision
- */
-u32 get_board_rev(void)
-{
-	return 0x20;
-}
-
-/*
- * Print CPU information
- */
-int print_cpuinfo(void)
-{
-
-	puts("CPU  : OMAP4430\n");
-
-	return 0;
-}
diff --git a/arch/arm/cpu/armv7/s5p-common/Makefile b/arch/arm/cpu/armv7/s5p-common/Makefile
deleted file mode 100644
index 922cd95..0000000
--- a/arch/arm/cpu/armv7/s5p-common/Makefile
+++ /dev/null
@@ -1,46 +0,0 @@
-#
-# Copyright (C) 2009 Samsung Electronics
-# Minkyu Kang <mk7.kang@samsung.com>
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)libs5p-common.o
-
-COBJS-y		+= cpu_info.o
-COBJS-y		+= timer.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS-y) $(SOBJS))
-
-all:	 $(obj).depend $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/arch/arm/cpu/armv7/s5p-common/cpu_info.c b/arch/arm/cpu/armv7/s5p-common/cpu_info.c
deleted file mode 100644
index c8a543a..0000000
--- a/arch/arm/cpu/armv7/s5p-common/cpu_info.c
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * Copyright (C) 2009 Samsung Electronics
- * Minkyu Kang <mk7.kang@samsung.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/clk.h>
-
-/* Default is s5pc100 */
-unsigned int s5p_cpu_id = 0xC100;
-
-#ifdef CONFIG_ARCH_CPU_INIT
-int arch_cpu_init(void)
-{
-	s5p_set_cpu_id();
-
-	return 0;
-}
-#endif
-
-u32 get_device_type(void)
-{
-	return s5p_cpu_id;
-}
-
-#ifdef CONFIG_DISPLAY_CPUINFO
-int print_cpuinfo(void)
-{
-	char buf[32];
-
-	printf("CPU:\tS5P%X@%sMHz\n",
-			s5p_cpu_id, strmhz(buf, get_arm_clk()));
-
-	return 0;
-}
-#endif
diff --git a/arch/arm/cpu/armv7/s5p-common/timer.c b/arch/arm/cpu/armv7/s5p-common/timer.c
deleted file mode 100644
index 651fd5d..0000000
--- a/arch/arm/cpu/armv7/s5p-common/timer.c
+++ /dev/null
@@ -1,192 +0,0 @@
-/*
- * Copyright (C) 2009 Samsung Electronics
- * Heungjun Kim <riverful.kim@samsung.com>
- * Inki Dae <inki.dae@samsung.com>
- * Minkyu Kang <mk7.kang@samsung.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/pwm.h>
-#include <asm/arch/clk.h>
-
-#define PRESCALER_1		(16 - 1)	/* prescaler of timer 2, 3, 4 */
-#define MUX_DIV_2		1		/* 1/2 period */
-#define MUX_DIV_4		2		/* 1/4 period */
-#define MUX_DIV_8		3		/* 1/8 period */
-#define MUX_DIV_16		4		/* 1/16 period */
-#define MUX4_DIV_SHIFT		16
-
-#define TCON_TIMER4_SHIFT	20
-
-static unsigned long count_value;
-
-/* Internal tick units */
-static unsigned long long timestamp;	/* Monotonic incrementing timer */
-static unsigned long lastdec;		/* Last decremneter snapshot */
-
-/* macro to read the 16 bit timer */
-static inline struct s5p_timer *s5p_get_base_timer(void)
-{
-	return (struct s5p_timer *)samsung_get_base_timer();
-}
-
-int timer_init(void)
-{
-	struct s5p_timer *const timer = s5p_get_base_timer();
-	u32 val;
-
-	/*
-	 * @ PWM Timer 4
-	 * Timer Freq(HZ) =
-	 *	PWM_CLK / { (prescaler_value + 1) * (divider_value) }
-	 */
-
-	/* set prescaler : 16 */
-	/* set divider : 2 */
-	writel((PRESCALER_1 & 0xff) << 8, &timer->tcfg0);
-	writel((MUX_DIV_2 & 0xf) << MUX4_DIV_SHIFT, &timer->tcfg1);
-
-	/* count_value = 2085937.5(HZ) (per 1 sec)*/
-	count_value = get_pwm_clk() / ((PRESCALER_1 + 1) *
-			(MUX_DIV_2 + 1));
-
-	/* count_value / 100 = 20859.375(HZ) (per 10 msec) */
-	count_value = count_value / 100;
-
-	/* set count value */
-	writel(count_value, &timer->tcntb4);
-	lastdec = count_value;
-
-	val = (readl(&timer->tcon) & ~(0x07 << TCON_TIMER4_SHIFT)) |
-		TCON4_AUTO_RELOAD;
-
-	/* auto reload & manual update */
-	writel(val | TCON4_UPDATE, &timer->tcon);
-
-	/* start PWM timer 4 */
-	writel(val | TCON4_START, &timer->tcon);
-
-	timestamp = 0;
-
-	return 0;
-}
-
-/*
- * timer without interrupts
- */
-void reset_timer(void)
-{
-	reset_timer_masked();
-}
-
-unsigned long get_timer(unsigned long base)
-{
-	return get_timer_masked() - base;
-}
-
-void set_timer(unsigned long t)
-{
-	timestamp = t;
-}
-
-/* delay x useconds */
-void __udelay(unsigned long usec)
-{
-	struct s5p_timer *const timer = s5p_get_base_timer();
-	unsigned long tmo, tmp;
-
-	count_value = readl(&timer->tcntb4);
-
-	if (usec >= 1000) {
-		/*
-		 * if "big" number, spread normalization
-		 * to seconds
-		 * 1. start to normalize for usec to ticks per sec
-		 * 2. find number of "ticks" to wait to achieve target
-		 * 3. finish normalize.
-		 */
-		tmo = usec / 1000;
-		tmo *= (CONFIG_SYS_HZ * count_value / 10);
-		tmo /= 1000;
-	} else {
-		/* else small number, don't kill it prior to HZ multiply */
-		tmo = usec * CONFIG_SYS_HZ * count_value / 10;
-		tmo /= (1000 * 1000);
-	}
-
-	/* get current timestamp */
-	tmp = get_timer(0);
-
-	/* if setting this fordward will roll time stamp */
-	/* reset "advancing" timestamp to 0, set lastdec value */
-	/* else, set advancing stamp wake up time */
-	if ((tmo + tmp + 1) < tmp)
-		reset_timer_masked();
-	else
-		tmo += tmp;
-
-	/* loop till event */
-	while (get_timer_masked() < tmo)
-		;	/* nop */
-}
-
-void reset_timer_masked(void)
-{
-	struct s5p_timer *const timer = s5p_get_base_timer();
-
-	/* reset time */
-	lastdec = readl(&timer->tcnto4);
-	timestamp = 0;
-}
-
-unsigned long get_timer_masked(void)
-{
-	struct s5p_timer *const timer = s5p_get_base_timer();
-	unsigned long now = readl(&timer->tcnto4);
-
-	if (lastdec >= now)
-		timestamp += lastdec - now;
-	else
-		timestamp += lastdec + count_value - now;
-
-	lastdec = now;
-
-	return timestamp;
-}
-
-/*
- * This function is derived from PowerPC code (read timebase as long long).
- * On ARM it just returns the timer value.
- */
-unsigned long long get_ticks(void)
-{
-	return get_timer(0);
-}
-
-/*
- * This function is derived from PowerPC code (timebase clock frequency).
- * On ARM it returns the number of timer ticks per second.
- */
-unsigned long get_tbclk(void)
-{
-	return CONFIG_SYS_HZ;
-}
diff --git a/arch/arm/cpu/armv7/s5pc1xx/Makefile b/arch/arm/cpu/armv7/s5pc1xx/Makefile
deleted file mode 100644
index b182bf5..0000000
--- a/arch/arm/cpu/armv7/s5pc1xx/Makefile
+++ /dev/null
@@ -1,52 +0,0 @@
-#
-# (C) Copyright 2000-2003
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# (C) Copyright 2008
-# Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(SOC).o
-
-SOBJS	= cache.o
-SOBJS	+= reset.o
-
-COBJS	+= clock.o
-COBJS	+= sromc.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS) $(SOBJS))
-
-all:	 $(obj).depend $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/arch/arm/cpu/armv7/s5pc1xx/cache.S b/arch/arm/cpu/armv7/s5pc1xx/cache.S
deleted file mode 100644
index 7734b32..0000000
--- a/arch/arm/cpu/armv7/s5pc1xx/cache.S
+++ /dev/null
@@ -1,120 +0,0 @@
-/*
- * Copyright (C) 2009 Samsung Electronics
- * Minkyu Kang <mk7.kang@samsung.com>
- *
- * based on arch/arm/cpu/armv7/omap3/cache.S
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <asm/arch/cpu.h>
-
-.align 5
-.global invalidate_dcache
-.global l2_cache_enable
-.global l2_cache_disable
-
-/*
- * invalidate_dcache()
- * Invalidate the whole D-cache.
- *
- * Corrupted registers: r0-r5, r7, r9-r11
- */
-invalidate_dcache:
-	stmfd	r13!, {r0 - r5, r7, r9 - r12, r14}
-
-	cmp	r0, #0xC100			@ check if the cpu is s5pc100
-
-	beq	finished_inval			@ s5pc100 doesn't need this
-						@ routine
-	mrc	p15, 1, r0, c0, c0, 1		@ read clidr
-	ands	r3, r0, #0x7000000		@ extract loc from clidr
-	mov	r3, r3, lsr #23			@ left align loc bit field
-	beq	finished_inval			@ if loc is 0, then no need to
-						@ clean
-	mov	r10, #0				@ start clean at cache level 0
-inval_loop1:
-	add	r2, r10, r10, lsr #1		@ work out 3x current cache
-						@ level
-	mov	r1, r0, lsr r2			@ extract cache type bits from
-						@ clidr
-	and	r1, r1, #7			@ mask of the bits for current
-						@ cache only
-	cmp	r1, #2				@ see what cache we have at
-						@ this level
-	blt	skip_inval			@ skip if no cache, or just
-						@ i-cache
-	mcr	p15, 2, r10, c0, c0, 0		@ select current cache level
-						@ in cssr
-	mov	r2, #0				@ operand for mcr SBZ
-	mcr	p15, 0, r2, c7, c5, 4		@ flush prefetch buffer to
-						@ sych the new cssr&csidr,
-						@ with armv7 this is 'isb',
-						@ but we compile with armv5
-	mrc	p15, 1, r1, c0, c0, 0		@ read the new csidr
-	and	r2, r1, #7			@ extract the length of the
-						@ cache lines
-	add	r2, r2, #4			@ add 4 (line length offset)
-	ldr	r4, =0x3ff
-	ands	r4, r4, r1, lsr #3		@ find maximum number on the
-						@ way size
-	clz	r5, r4				@ find bit position of way
-						@ size increment
-	ldr	r7, =0x7fff
-	ands	r7, r7, r1, lsr #13		@ extract max number of the
-						@ index size
-inval_loop2:
-	mov	r9, r4				@ create working copy of max
-						@ way size
-inval_loop3:
-	orr	r11, r10, r9, lsl r5		@ factor way and cache number
-						@ into r11
-	orr	r11, r11, r7, lsl r2		@ factor index number into r11
-	mcr	p15, 0, r11, c7, c6, 2		@ invalidate by set/way
-	subs	r9, r9, #1			@ decrement the way
-	bge	inval_loop3
-	subs	r7, r7, #1			@ decrement the index
-	bge	inval_loop2
-skip_inval:
-	add	r10, r10, #2			@ increment cache number
-	cmp	r3, r10
-	bgt	inval_loop1
-finished_inval:
-	mov	r10, #0				@ swith back to cache level 0
-	mcr	p15, 2, r10, c0, c0, 0		@ select current cache level
-						@ in cssr
-	mcr	p15, 0, r10, c7, c5, 4		@ flush prefetch buffer,
-						@ with armv7 this is 'isb',
-						@ but we compile with armv5
-
-	ldmfd	r13!, {r0 - r5, r7, r9 - r12, pc}
-
-l2_cache_enable:
-	push	{r0, r1, r2, lr}
-	mrc	15, 0, r3, cr1, cr0, 1
-	orr	r3, r3, #2
-	mcr	15, 0, r3, cr1, cr0, 1
-	pop	{r1, r2, r3, pc}
-
-l2_cache_disable:
-	push	{r0, r1, r2, lr}
-	mrc	15, 0, r3, cr1, cr0, 1
-	bic	r3, r3, #2
-	mcr	15, 0, r3, cr1, cr0, 1
-	pop	{r1, r2, r3, pc}
diff --git a/arch/arm/cpu/armv7/s5pc1xx/clock.c b/arch/arm/cpu/armv7/s5pc1xx/clock.c
deleted file mode 100644
index e92647c..0000000
--- a/arch/arm/cpu/armv7/s5pc1xx/clock.c
+++ /dev/null
@@ -1,338 +0,0 @@
-/*
- * Copyright (C) 2009 Samsung Electronics
- * Minkyu Kang <mk7.kang@samsung.com>
- * Heungjun Kim <riverful.kim@samsung.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/clk.h>
-
-#define CLK_M	0
-#define CLK_D	1
-#define CLK_P	2
-
-#ifndef CONFIG_SYS_CLK_FREQ_C100
-#define CONFIG_SYS_CLK_FREQ_C100	12000000
-#endif
-#ifndef CONFIG_SYS_CLK_FREQ_C110
-#define CONFIG_SYS_CLK_FREQ_C110	24000000
-#endif
-
-/* s5pc110: return pll clock frequency */
-static unsigned long s5pc100_get_pll_clk(int pllreg)
-{
-	struct s5pc100_clock *clk =
-		(struct s5pc100_clock *)samsung_get_base_clock();
-	unsigned long r, m, p, s, mask, fout;
-	unsigned int freq;
-
-	switch (pllreg) {
-	case APLL:
-		r = readl(&clk->apll_con);
-		break;
-	case MPLL:
-		r = readl(&clk->mpll_con);
-		break;
-	case EPLL:
-		r = readl(&clk->epll_con);
-		break;
-	case HPLL:
-		r = readl(&clk->hpll_con);
-		break;
-	default:
-		printf("Unsupported PLL (%d)\n", pllreg);
-		return 0;
-	}
-
-	/*
-	 * APLL_CON: MIDV [25:16]
-	 * MPLL_CON: MIDV [23:16]
-	 * EPLL_CON: MIDV [23:16]
-	 * HPLL_CON: MIDV [23:16]
-	 */
-	if (pllreg == APLL)
-		mask = 0x3ff;
-	else
-		mask = 0x0ff;
-
-	m = (r >> 16) & mask;
-
-	/* PDIV [13:8] */
-	p = (r >> 8) & 0x3f;
-	/* SDIV [2:0] */
-	s = r & 0x7;
-
-	/* FOUT = MDIV * FIN / (PDIV * 2^SDIV) */
-	freq = CONFIG_SYS_CLK_FREQ_C100;
-	fout = m * (freq / (p * (1 << s)));
-
-	return fout;
-}
-
-/* s5pc100: return pll clock frequency */
-static unsigned long s5pc110_get_pll_clk(int pllreg)
-{
-	struct s5pc110_clock *clk =
-		(struct s5pc110_clock *)samsung_get_base_clock();
-	unsigned long r, m, p, s, mask, fout;
-	unsigned int freq;
-
-	switch (pllreg) {
-	case APLL:
-		r = readl(&clk->apll_con);
-		break;
-	case MPLL:
-		r = readl(&clk->mpll_con);
-		break;
-	case EPLL:
-		r = readl(&clk->epll_con);
-		break;
-	case VPLL:
-		r = readl(&clk->vpll_con);
-		break;
-	default:
-		printf("Unsupported PLL (%d)\n", pllreg);
-		return 0;
-	}
-
-	/*
-	 * APLL_CON: MIDV [25:16]
-	 * MPLL_CON: MIDV [25:16]
-	 * EPLL_CON: MIDV [24:16]
-	 * VPLL_CON: MIDV [24:16]
-	 */
-	if (pllreg == APLL || pllreg == MPLL)
-		mask = 0x3ff;
-	else
-		mask = 0x1ff;
-
-	m = (r >> 16) & mask;
-
-	/* PDIV [13:8] */
-	p = (r >> 8) & 0x3f;
-	/* SDIV [2:0] */
-	s = r & 0x7;
-
-	freq = CONFIG_SYS_CLK_FREQ_C110;
-	if (pllreg == APLL) {
-		if (s < 1)
-			s = 1;
-		/* FOUT = MDIV * FIN / (PDIV * 2^(SDIV - 1)) */
-		fout = m * (freq / (p * (1 << (s - 1))));
-	} else
-		/* FOUT = MDIV * FIN / (PDIV * 2^SDIV) */
-		fout = m * (freq / (p * (1 << s)));
-
-	return fout;
-}
-
-/* s5pc110: return ARM clock frequency */
-static unsigned long s5pc110_get_arm_clk(void)
-{
-	struct s5pc110_clock *clk =
-		(struct s5pc110_clock *)samsung_get_base_clock();
-	unsigned long div;
-	unsigned long dout_apll, armclk;
-	unsigned int apll_ratio;
-
-	div = readl(&clk->div0);
-
-	/* APLL_RATIO: [2:0] */
-	apll_ratio = div & 0x7;
-
-	dout_apll = get_pll_clk(APLL) / (apll_ratio + 1);
-	armclk = dout_apll;
-
-	return armclk;
-}
-
-/* s5pc100: return ARM clock frequency */
-static unsigned long s5pc100_get_arm_clk(void)
-{
-	struct s5pc100_clock *clk =
-		(struct s5pc100_clock *)samsung_get_base_clock();
-	unsigned long div;
-	unsigned long dout_apll, armclk;
-	unsigned int apll_ratio, arm_ratio;
-
-	div = readl(&clk->div0);
-
-	/* ARM_RATIO: [6:4] */
-	arm_ratio = (div >> 4) & 0x7;
-	/* APLL_RATIO: [0] */
-	apll_ratio = div & 0x1;
-
-	dout_apll = get_pll_clk(APLL) / (apll_ratio + 1);
-	armclk = dout_apll / (arm_ratio + 1);
-
-	return armclk;
-}
-
-/* s5pc100: return HCLKD0 frequency */
-static unsigned long get_hclk(void)
-{
-	struct s5pc100_clock *clk =
-		(struct s5pc100_clock *)samsung_get_base_clock();
-	unsigned long hclkd0;
-	uint div, d0_bus_ratio;
-
-	div = readl(&clk->div0);
-	/* D0_BUS_RATIO: [10:8] */
-	d0_bus_ratio = (div >> 8) & 0x7;
-
-	hclkd0 = get_arm_clk() / (d0_bus_ratio + 1);
-
-	return hclkd0;
-}
-
-/* s5pc100: return PCLKD1 frequency */
-static unsigned long get_pclkd1(void)
-{
-	struct s5pc100_clock *clk =
-		(struct s5pc100_clock *)samsung_get_base_clock();
-	unsigned long d1_bus, pclkd1;
-	uint div, d1_bus_ratio, pclkd1_ratio;
-
-	div = readl(&clk->div0);
-	/* D1_BUS_RATIO: [14:12] */
-	d1_bus_ratio = (div >> 12) & 0x7;
-	/* PCLKD1_RATIO: [18:16] */
-	pclkd1_ratio = (div >> 16) & 0x7;
-
-	/* ASYNC Mode */
-	d1_bus = get_pll_clk(MPLL) / (d1_bus_ratio + 1);
-	pclkd1 = d1_bus / (pclkd1_ratio + 1);
-
-	return pclkd1;
-}
-
-/* s5pc110: return HCLKs frequency */
-static unsigned long get_hclk_sys(int dom)
-{
-	struct s5pc110_clock *clk =
-		(struct s5pc110_clock *)samsung_get_base_clock();
-	unsigned long hclk;
-	unsigned int div;
-	unsigned int offset;
-	unsigned int hclk_sys_ratio;
-
-	if (dom == CLK_M)
-		return get_hclk();
-
-	div = readl(&clk->div0);
-
-	/*
-	 * HCLK_MSYS_RATIO: [10:8]
-	 * HCLK_DSYS_RATIO: [19:16]
-	 * HCLK_PSYS_RATIO: [27:24]
-	 */
-	offset = 8 + (dom << 0x3);
-
-	hclk_sys_ratio = (div >> offset) & 0xf;
-
-	hclk = get_pll_clk(MPLL) / (hclk_sys_ratio + 1);
-
-	return hclk;
-}
-
-/* s5pc110: return PCLKs frequency */
-static unsigned long get_pclk_sys(int dom)
-{
-	struct s5pc110_clock *clk =
-		(struct s5pc110_clock *)samsung_get_base_clock();
-	unsigned long pclk;
-	unsigned int div;
-	unsigned int offset;
-	unsigned int pclk_sys_ratio;
-
-	div = readl(&clk->div0);
-
-	/*
-	 * PCLK_MSYS_RATIO: [14:12]
-	 * PCLK_DSYS_RATIO: [22:20]
-	 * PCLK_PSYS_RATIO: [30:28]
-	 */
-	offset = 12 + (dom << 0x3);
-
-	pclk_sys_ratio = (div >> offset) & 0x7;
-
-	pclk = get_hclk_sys(dom) / (pclk_sys_ratio + 1);
-
-	return pclk;
-}
-
-/* s5pc110: return peripheral clock frequency */
-static unsigned long s5pc110_get_pclk(void)
-{
-	return get_pclk_sys(CLK_P);
-}
-
-/* s5pc100: return peripheral clock frequency */
-static unsigned long s5pc100_get_pclk(void)
-{
-	return get_pclkd1();
-}
-
-/* s5pc1xx: return uart clock frequency */
-static unsigned long s5pc1xx_get_uart_clk(int dev_index)
-{
-	if (cpu_is_s5pc110())
-		return s5pc110_get_pclk();
-	else
-		return s5pc100_get_pclk();
-}
-
-/* s5pc1xx: return pwm clock frequency */
-static unsigned long s5pc1xx_get_pwm_clk(void)
-{
-	if (cpu_is_s5pc110())
-		return s5pc110_get_pclk();
-	else
-		return s5pc100_get_pclk();
-}
-
-unsigned long get_pll_clk(int pllreg)
-{
-	if (cpu_is_s5pc110())
-		return s5pc110_get_pll_clk(pllreg);
-	else
-		return s5pc100_get_pll_clk(pllreg);
-}
-
-unsigned long get_arm_clk(void)
-{
-	if (cpu_is_s5pc110())
-		return s5pc110_get_arm_clk();
-	else
-		return s5pc100_get_arm_clk();
-}
-
-unsigned long get_pwm_clk(void)
-{
-	return s5pc1xx_get_pwm_clk();
-}
-
-unsigned long get_uart_clk(int dev_index)
-{
-	return s5pc1xx_get_uart_clk(dev_index);
-}
diff --git a/arch/arm/cpu/armv7/s5pc1xx/reset.S b/arch/arm/cpu/armv7/s5pc1xx/reset.S
deleted file mode 100644
index 70fa146..0000000
--- a/arch/arm/cpu/armv7/s5pc1xx/reset.S
+++ /dev/null
@@ -1,47 +0,0 @@
-/*
- * Copyright (c) 2009 Samsung Electronics.
- * Minkyu Kang <mk7.kang@samsung.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <asm/arch/cpu.h>
-
-#define S5PC100_SWRESET			0xE0200000
-#define S5PC110_SWRESET			0xE0102000
-
-.globl reset_cpu
-reset_cpu:
-	ldr	r1, =S5PC100_PRO_ID
-	ldr	r2, [r1]
-	ldr	r4, =0x00010000
-	and	r4, r2, r4
-	cmp	r4, #0
-	bne	110f
-	/* S5PC100 */
-	ldr	r1, =S5PC100_SWRESET
-	ldr	r2, =0xC100
-	b	200f
-110:	/* S5PC110 */
-	ldr	r1, =S5PC110_SWRESET
-	mov	r2, #1
-200:
-	str	r2, [r1]
-_loop_forever:
-	b	_loop_forever
diff --git a/arch/arm/cpu/armv7/s5pc1xx/sromc.c b/arch/arm/cpu/armv7/s5pc1xx/sromc.c
deleted file mode 100644
index 044d122..0000000
--- a/arch/arm/cpu/armv7/s5pc1xx/sromc.c
+++ /dev/null
@@ -1,49 +0,0 @@
-/*
- * Copyright (C) 2010 Samsung Electronics
- * Naveen Krishna Ch <ch.naveen@samsung.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/smc.h>
-
-/*
- * s5pc1xx_config_sromc() - select the proper SROMC Bank and configure the
- * 		    band width control and bank control registers
- * srom_bank	- SROM Bank 0 to 5
- * smc_bw_conf  - SMC Band witdh reg configuration value
- * smc_bc_conf  - SMC Bank Control reg configuration value
- */
-void s5pc1xx_config_sromc(u32 srom_bank, u32 smc_bw_conf, u32 smc_bc_conf)
-{
-	u32 tmp;
-	struct s5pc1xx_smc *srom =
-		(struct s5pc1xx_smc *)samsung_get_base_sromc();
-
-	/* Configure SMC_BW register to handle proper SROMC bank */
-	tmp = srom->bw;
-	tmp &= ~(0xF << (srom_bank * 4));
-	tmp |= smc_bw_conf;
-	srom->bw = tmp;
-
-	/* Configure SMC_BC register */
-	srom->bc[srom_bank] = smc_bc_conf;
-}
diff --git a/arch/arm/cpu/armv7/s5pc2xx/Makefile b/arch/arm/cpu/armv7/s5pc2xx/Makefile
deleted file mode 100644
index 124c380..0000000
--- a/arch/arm/cpu/armv7/s5pc2xx/Makefile
+++ /dev/null
@@ -1,42 +0,0 @@
-#
-# Copyright (C) 2009 Samsung Electronics
-# Minkyu Kang <mk7.kang@samsung.com>
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(SOC).o
-
-COBJS	+= clock.o soc.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS) $(SOBJS))
-
-all:	 $(obj).depend $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/arch/arm/cpu/armv7/s5pc2xx/clock.c b/arch/arm/cpu/armv7/s5pc2xx/clock.c
deleted file mode 100644
index 450a630..0000000
--- a/arch/arm/cpu/armv7/s5pc2xx/clock.c
+++ /dev/null
@@ -1,220 +0,0 @@
-/*
- * Copyright (C) 2010 Samsung Electronics
- * Minkyu Kang <mk7.kang@samsung.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/clk.h>
-
-#ifndef CONFIG_SYS_CLK_FREQ_C210
-#define CONFIG_SYS_CLK_FREQ_C210	24000000
-#endif
-
-/* s5pc210: return pll clock frequency */
-static unsigned long s5pc210_get_pll_clk(int pllreg)
-{
-	struct s5pc210_clock *clk =
-		(struct s5pc210_clock *)samsung_get_base_clock();
-	unsigned long r, m, p, s, k = 0, mask, fout;
-	unsigned int freq;
-
-	switch (pllreg) {
-	case APLL:
-		r = readl(&clk->apll_con0);
-		break;
-	case MPLL:
-		r = readl(&clk->mpll_con0);
-		break;
-	case EPLL:
-		r = readl(&clk->epll_con0);
-		k = readl(&clk->epll_con1);
-		break;
-	case VPLL:
-		r = readl(&clk->vpll_con0);
-		k = readl(&clk->vpll_con1);
-		break;
-	default:
-		printf("Unsupported PLL (%d)\n", pllreg);
-		return 0;
-	}
-
-	/*
-	 * APLL_CON: MIDV [25:16]
-	 * MPLL_CON: MIDV [25:16]
-	 * EPLL_CON: MIDV [24:16]
-	 * VPLL_CON: MIDV [24:16]
-	 */
-	if (pllreg == APLL || pllreg == MPLL)
-		mask = 0x3ff;
-	else
-		mask = 0x1ff;
-
-	m = (r >> 16) & mask;
-
-	/* PDIV [13:8] */
-	p = (r >> 8) & 0x3f;
-	/* SDIV [2:0] */
-	s = r & 0x7;
-
-	freq = CONFIG_SYS_CLK_FREQ_C210;
-
-	if (pllreg == EPLL) {
-		k = k & 0xffff;
-		/* FOUT = (MDIV + K / 65536) * FIN / (PDIV * 2^SDIV) */
-		fout = (m + k / 65536) * (freq / (p * (1 << s)));
-	} else if (pllreg == VPLL) {
-		k = k & 0xfff;
-		/* FOUT = (MDIV + K / 1024) * FIN / (PDIV * 2^SDIV) */
-		fout = (m + k / 1024) * (freq / (p * (1 << s)));
-	} else {
-		if (s < 1)
-			s = 1;
-		/* FOUT = MDIV * FIN / (PDIV * 2^(SDIV - 1)) */
-		fout = m * (freq / (p * (1 << (s - 1))));
-	}
-
-	return fout;
-}
-
-/* s5pc210: return ARM clock frequency */
-static unsigned long s5pc210_get_arm_clk(void)
-{
-	struct s5pc210_clock *clk =
-		(struct s5pc210_clock *)samsung_get_base_clock();
-	unsigned long div;
-	unsigned long dout_apll;
-	unsigned int apll_ratio;
-
-	div = readl(&clk->div_cpu0);
-
-	/* APLL_RATIO: [26:24] */
-	apll_ratio = (div >> 24) & 0x7;
-
-	dout_apll = get_pll_clk(APLL) / (apll_ratio + 1);
-
-	return dout_apll;
-}
-
-/* s5pc210: return pwm clock frequency */
-static unsigned long s5pc210_get_pwm_clk(void)
-{
-	struct s5pc210_clock *clk =
-		(struct s5pc210_clock *)samsung_get_base_clock();
-	unsigned long pclk, sclk;
-	unsigned int sel;
-	unsigned int ratio;
-
-	/*
-	 * CLK_SRC_PERIL0
-	 * PWM_SEL [27:24]
-	 */
-	sel = readl(&clk->src_peril0);
-	sel = (sel >> 24) & 0xf;
-
-	if (sel == 0x6)
-		sclk = get_pll_clk(MPLL);
-	else if (sel == 0x7)
-		sclk = get_pll_clk(EPLL);
-	else if (sel == 0x8)
-		sclk = get_pll_clk(VPLL);
-	else
-		return 0;
-
-	/*
-	 * CLK_DIV_PERIL3
-	 * PWM_RATIO [3:0]
-	 */
-	ratio = readl(&clk->div_peril3);
-	ratio = ratio & 0xf;
-
-	pclk = sclk / (ratio + 1);
-
-	return pclk;
-}
-
-/* s5pc210: return uart clock frequency */
-static unsigned long s5pc210_get_uart_clk(int dev_index)
-{
-	struct s5pc210_clock *clk =
-		(struct s5pc210_clock *)samsung_get_base_clock();
-	unsigned long uclk, sclk;
-	unsigned int sel;
-	unsigned int ratio;
-
-	/*
-	 * CLK_SRC_PERIL0
-	 * UART0_SEL [3:0]
-	 * UART1_SEL [7:4]
-	 * UART2_SEL [8:11]
-	 * UART3_SEL [12:15]
-	 * UART4_SEL [16:19]
-	 * UART5_SEL [23:20]
-	 */
-	sel = readl(&clk->src_peril0);
-	sel = (sel >> (dev_index << 2)) & 0xf;
-
-	if (sel == 0x6)
-		sclk = get_pll_clk(MPLL);
-	else if (sel == 0x7)
-		sclk = get_pll_clk(EPLL);
-	else if (sel == 0x8)
-		sclk = get_pll_clk(VPLL);
-	else
-		return 0;
-
-	/*
-	 * CLK_DIV_PERIL0
-	 * UART0_RATIO [3:0]
-	 * UART1_RATIO [7:4]
-	 * UART2_RATIO [8:11]
-	 * UART3_RATIO [12:15]
-	 * UART4_RATIO [16:19]
-	 * UART5_RATIO [23:20]
-	 */
-	ratio = readl(&clk->div_peril0);
-	ratio = (ratio >> (dev_index << 2)) & 0xf;
-
-	uclk = sclk / (ratio + 1);
-
-	return uclk;
-}
-
-unsigned long get_pll_clk(int pllreg)
-{
-	return s5pc210_get_pll_clk(pllreg);
-}
-
-unsigned long get_arm_clk(void)
-{
-	return s5pc210_get_arm_clk();
-}
-
-unsigned long get_pwm_clk(void)
-{
-	return s5pc210_get_pwm_clk();
-}
-
-unsigned long get_uart_clk(int dev_index)
-{
-	return s5pc210_get_uart_clk(dev_index);
-}
diff --git a/arch/arm/cpu/armv7/s5pc2xx/soc.c b/arch/arm/cpu/armv7/s5pc2xx/soc.c
deleted file mode 100644
index dcfcec2..0000000
--- a/arch/arm/cpu/armv7/s5pc2xx/soc.c
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * Copyright (c) 2010 Samsung Electronics.
- * Minkyu Kang <mk7.kang@samsung.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/io.h>
-
-void reset_cpu(ulong addr)
-{
-	writel(0x1, samsung_get_base_swreset());
-}
diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S
deleted file mode 100644
index cb4f92f..0000000
--- a/arch/arm/cpu/armv7/start.S
+++ /dev/null
@@ -1,485 +0,0 @@
-/*
- * armboot - Startup Code for OMAP3530/ARM Cortex CPU-core
- *
- * Copyright (c) 2004	Texas Instruments <r-woodruff2@ti.com>
- *
- * Copyright (c) 2001	Marius Gröger <mag@sysgo.de>
- * Copyright (c) 2002	Alex Züpke <azu@sysgo.de>
- * Copyright (c) 2002	Gary Jennejohn <garyj@denx.de>
- * Copyright (c) 2003	Richard Woodruff <r-woodruff2@ti.com>
- * Copyright (c) 2003	Kshitij <kshitij@ti.com>
- * Copyright (c) 2006-2008 Syed Mohammed Khasim <x0khasim@ti.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <asm-offsets.h>
-#include <config.h>
-#include <version.h>
-
-.globl _start
-_start: b	reset
-	ldr	pc, _undefined_instruction
-	ldr	pc, _software_interrupt
-	ldr	pc, _prefetch_abort
-	ldr	pc, _data_abort
-	ldr	pc, _not_used
-	ldr	pc, _irq
-	ldr	pc, _fiq
-
-_undefined_instruction: .word undefined_instruction
-_software_interrupt:	.word software_interrupt
-_prefetch_abort:	.word prefetch_abort
-_data_abort:		.word data_abort
-_not_used:		.word not_used
-_irq:			.word irq
-_fiq:			.word fiq
-_pad:			.word 0x12345678 /* now 16*4=64 */
-.global _end_vect
-_end_vect:
-
-	.balignl 16,0xdeadbeef
-/*************************************************************************
- *
- * Startup Code (reset vector)
- *
- * do important init only if we don't start from memory!
- * setup Memory and board specific bits prior to relocation.
- * relocate armboot to ram
- * setup stack
- *
- *************************************************************************/
-
-.globl _TEXT_BASE
-_TEXT_BASE:
-	.word	CONFIG_SYS_TEXT_BASE
-
-/*
- * These are defined in the board-specific linker script.
- */
-.globl _bss_start_ofs
-_bss_start_ofs:
-	.word __bss_start - _start
-
-.globl _bss_end_ofs
-_bss_end_ofs:
-	.word _end - _start
-
-#ifdef CONFIG_USE_IRQ
-/* IRQ stack memory (calculated at run-time) */
-.globl IRQ_STACK_START
-IRQ_STACK_START:
-	.word	0x0badc0de
-
-/* IRQ stack memory (calculated at run-time) */
-.globl FIQ_STACK_START
-FIQ_STACK_START:
-	.word 0x0badc0de
-#endif
-
-/* IRQ stack memory (calculated at run-time) + 8 bytes */
-.globl IRQ_STACK_START_IN
-IRQ_STACK_START_IN:
-	.word	0x0badc0de
-
-/*
- * the actual reset code
- */
-
-reset:
-	/*
-	 * set the cpu to SVC32 mode
-	 */
-	mrs	r0, cpsr
-	bic	r0, r0, #0x1f
-	orr	r0, r0, #0xd3
-	msr	cpsr,r0
-
-#if (CONFIG_OMAP34XX)
-	/* Copy vectors to mask ROM indirect addr */
-	adr	r0, _start		@ r0 <- current position of code
-	add	r0, r0, #4		@ skip reset vector
-	mov	r2, #64			@ r2 <- size to copy
-	add	r2, r0, r2		@ r2 <- source end address
-	mov	r1, #SRAM_OFFSET0	@ build vect addr
-	mov	r3, #SRAM_OFFSET1
-	add	r1, r1, r3
-	mov	r3, #SRAM_OFFSET2
-	add	r1, r1, r3
-next:
-	ldmia	r0!, {r3 - r10}		@ copy from source address [r0]
-	stmia	r1!, {r3 - r10}		@ copy to   target address [r1]
-	cmp	r0, r2			@ until source end address [r2]
-	bne	next			@ loop until equal */
-#if !defined(CONFIG_SYS_NAND_BOOT) && !defined(CONFIG_SYS_ONENAND_BOOT)
-	/* No need to copy/exec the clock code - DPLL adjust already done
-	 * in NAND/oneNAND Boot.
-	 */
-	bl	cpy_clk_code		@ put dpll adjust code behind vectors
-#endif /* NAND Boot */
-#endif
-	/* the mask ROM code should have PLL and others stable */
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
-	bl	cpu_init_crit
-#endif
-
-/* Set stackpointer in internal RAM to call board_init_f */
-call_board_init_f:
-	ldr	sp, =(CONFIG_SYS_INIT_SP_ADDR)
-	bic	sp, sp, #7 /* 8-byte alignment for ABI compliance */
-	ldr	r0,=0x00000000
-	bl	board_init_f
-
-/*------------------------------------------------------------------------------*/
-
-/*
- * void relocate_code (addr_sp, gd, addr_moni)
- *
- * This "function" does not return, instead it continues in RAM
- * after relocating the monitor code.
- *
- */
-	.globl	relocate_code
-relocate_code:
-	mov	r4, r0	/* save addr_sp */
-	mov	r5, r1	/* save addr of gd */
-	mov	r6, r2	/* save addr of destination */
-
-	/* Set up the stack						    */
-stack_setup:
-	mov	sp, r4
-
-	adr	r0, _start
-#ifndef CONFIG_PRELOADER
-	cmp	r0, r6
-	beq	clear_bss		/* skip relocation */
-#endif
-	mov	r1, r6			/* r1 <- scratch for copy_loop */
-	ldr	r3, _bss_start_ofs
-	add	r2, r0, r3		/* r2 <- source end address	    */
-
-copy_loop:
-	ldmia	r0!, {r9-r10}		/* copy from source address [r0]    */
-	stmia	r1!, {r9-r10}		/* copy to   target address [r1]    */
-	cmp	r0, r2			/* until source end address [r2]    */
-	blo	copy_loop
-
-#ifndef CONFIG_PRELOADER
-	/*
-	 * fix .rel.dyn relocations
-	 */
-	ldr	r0, _TEXT_BASE		/* r0 <- Text base */
-	sub	r9, r6, r0		/* r9 <- relocation offset */
-	ldr	r10, _dynsym_start_ofs	/* r10 <- sym table ofs */
-	add	r10, r10, r0		/* r10 <- sym table in FLASH */
-	ldr	r2, _rel_dyn_start_ofs	/* r2 <- rel dyn start ofs */
-	add	r2, r2, r0		/* r2 <- rel dyn start in FLASH */
-	ldr	r3, _rel_dyn_end_ofs	/* r3 <- rel dyn end ofs */
-	add	r3, r3, r0		/* r3 <- rel dyn end in FLASH */
-fixloop:
-	ldr	r0, [r2]		/* r0 <- location to fix up, IN FLASH! */
-	add	r0, r0, r9		/* r0 <- location to fix up in RAM */
-	ldr	r1, [r2, #4]
-	and	r7, r1, #0xff
-	cmp	r7, #23			/* relative fixup? */
-	beq	fixrel
-	cmp	r7, #2			/* absolute fixup? */
-	beq	fixabs
-	/* ignore unknown type of fixup */
-	b	fixnext
-fixabs:
-	/* absolute fix: set location to (offset) symbol value */
-	mov	r1, r1, LSR #4		/* r1 <- symbol index in .dynsym */
-	add	r1, r10, r1		/* r1 <- address of symbol in table */
-	ldr	r1, [r1, #4]		/* r1 <- symbol value */
-	add	r1, r1, r9		/* r1 <- relocated sym addr */
-	b	fixnext
-fixrel:
-	/* relative fix: increase location by offset */
-	ldr	r1, [r0]
-	add	r1, r1, r9
-fixnext:
-	str	r1, [r0]
-	add	r2, r2, #8		/* each rel.dyn entry is 8 bytes */
-	cmp	r2, r3
-	blo	fixloop
-
-clear_bss:
-	ldr	r0, _bss_start_ofs
-	ldr	r1, _bss_end_ofs
-	mov	r4, r6			/* reloc addr */
-	add	r0, r0, r4
-	add	r1, r1, r4
-	mov	r2, #0x00000000		/* clear			    */
-
-clbss_l:str	r2, [r0]		/* clear loop...		    */
-	add	r0, r0, #4
-	cmp	r0, r1
-	bne	clbss_l
-#endif	/* #ifndef CONFIG_PRELOADER */
-
-/*
- * We are done. Do not return, instead branch to second part of board
- * initialization, now running from RAM.
- */
-jump_2_ram:
-	ldr	r0, _board_init_r_ofs
-	adr	r1, _start
-	add	lr, r0, r1
-	add	lr, lr, r9
-	/* setup parameters for board_init_r */
-	mov	r0, r5		/* gd_t */
-	mov	r1, r6		/* dest_addr */
-	/* jump to it ... */
-	mov	pc, lr
-
-_board_init_r_ofs:
-	.word board_init_r - _start
-
-_rel_dyn_start_ofs:
-	.word __rel_dyn_start - _start
-_rel_dyn_end_ofs:
-	.word __rel_dyn_end - _start
-_dynsym_start_ofs:
-	.word __dynsym_start - _start
-
-/*************************************************************************
- *
- * CPU_init_critical registers
- *
- * setup important registers
- * setup memory timing
- *
- *************************************************************************/
-cpu_init_crit:
-	/*
-	 * Invalidate L1 I/D
-	 */
-	mov	r0, #0			@ set up for MCR
-	mcr	p15, 0, r0, c8, c7, 0	@ invalidate TLBs
-	mcr	p15, 0, r0, c7, c5, 0	@ invalidate icache
-
-	/*
-	 * disable MMU stuff and caches
-	 */
-	mrc	p15, 0, r0, c1, c0, 0
-	bic	r0, r0, #0x00002000	@ clear bits 13 (--V-)
-	bic	r0, r0, #0x00000007	@ clear bits 2:0 (-CAM)
-	orr	r0, r0, #0x00000002	@ set bit 1 (--A-) Align
-	orr	r0, r0, #0x00000800	@ set bit 12 (Z---) BTB
-	mcr	p15, 0, r0, c1, c0, 0
-
-	/*
-	 * Jump to board specific initialization...
-	 * The Mask ROM will have already initialized
-	 * basic memory. Go here to bump up clock rate and handle
-	 * wake up conditions.
-	 */
-	mov	ip, lr			@ persevere link reg across call
-	bl	lowlevel_init		@ go setup pll,mux,memory
-	mov	lr, ip			@ restore link
-	mov	pc, lr			@ back to my caller
-/*
- *************************************************************************
- *
- * Interrupt handling
- *
- *************************************************************************
- */
-@
-@ IRQ stack frame.
-@
-#define S_FRAME_SIZE	72
-
-#define S_OLD_R0	68
-#define S_PSR		64
-#define S_PC		60
-#define S_LR		56
-#define S_SP		52
-
-#define S_IP		48
-#define S_FP		44
-#define S_R10		40
-#define S_R9		36
-#define S_R8		32
-#define S_R7		28
-#define S_R6		24
-#define S_R5		20
-#define S_R4		16
-#define S_R3		12
-#define S_R2		8
-#define S_R1		4
-#define S_R0		0
-
-#define MODE_SVC 0x13
-#define I_BIT	 0x80
-
-/*
- * use bad_save_user_regs for abort/prefetch/undef/swi ...
- * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
- */
-
-	.macro	bad_save_user_regs
-	sub	sp, sp, #S_FRAME_SIZE		@ carve out a frame on current
-						@ user stack
-	stmia	sp, {r0 - r12}			@ Save user registers (now in
-						@ svc mode) r0-r12
-	ldr	r2, IRQ_STACK_START_IN		@ set base 2 words into abort
-						@ stack
-	ldmia	r2, {r2 - r3}			@ get values for "aborted" pc
-						@ and cpsr (into parm regs)
-	add	r0, sp, #S_FRAME_SIZE		@ grab pointer to old stack
-
-	add	r5, sp, #S_SP
-	mov	r1, lr
-	stmia	r5, {r0 - r3}			@ save sp_SVC, lr_SVC, pc, cpsr
-	mov	r0, sp				@ save current stack into r0
-						@ (param register)
-	.endm
-
-	.macro	irq_save_user_regs
-	sub	sp, sp, #S_FRAME_SIZE
-	stmia	sp, {r0 - r12}			@ Calling r0-r12
-	add	r8, sp, #S_PC			@ !! R8 NEEDS to be saved !!
-						@ a reserved stack spot would
-						@ be good.
-	stmdb	r8, {sp, lr}^			@ Calling SP, LR
-	str	lr, [r8, #0]			@ Save calling PC
-	mrs	r6, spsr
-	str	r6, [r8, #4]			@ Save CPSR
-	str	r0, [r8, #8]			@ Save OLD_R0
-	mov	r0, sp
-	.endm
-
-	.macro	irq_restore_user_regs
-	ldmia	sp, {r0 - lr}^			@ Calling r0 - lr
-	mov	r0, r0
-	ldr	lr, [sp, #S_PC]			@ Get PC
-	add	sp, sp, #S_FRAME_SIZE
-	subs	pc, lr, #4			@ return & move spsr_svc into
-						@ cpsr
-	.endm
-
-	.macro get_bad_stack
-	ldr	r13, IRQ_STACK_START_IN		@ setup our mode stack (enter
-						@ in banked mode)
-
-	str	lr, [r13]			@ save caller lr in position 0
-						@ of saved stack
-	mrs	lr, spsr			@ get the spsr
-	str	lr, [r13, #4]			@ save spsr in position 1 of
-						@ saved stack
-
-	mov	r13, #MODE_SVC			@ prepare SVC-Mode
-	@ msr	spsr_c, r13
-	msr	spsr, r13			@ switch modes, make sure
-						@ moves will execute
-	mov	lr, pc				@ capture return pc
-	movs	pc, lr				@ jump to next instruction &
-						@ switch modes.
-	.endm
-
-	.macro get_bad_stack_swi
-	sub	r13, r13, #4			@ space on current stack for
-						@ scratch reg.
-	str	r0, [r13]			@ save R0's value.
-	ldr	r0, IRQ_STACK_START_IN		@ get data regions start
-						@ spots for abort stack
-	str	lr, [r0]			@ save caller lr in position 0
-						@ of saved stack
-	mrs	r0, spsr			@ get the spsr
-	str	lr, [r0, #4]			@ save spsr in position 1 of
-						@ saved stack
-	ldr	r0, [r13]			@ restore r0
-	add	r13, r13, #4			@ pop stack entry
-	.endm
-
-	.macro get_irq_stack			@ setup IRQ stack
-	ldr	sp, IRQ_STACK_START
-	.endm
-
-	.macro get_fiq_stack			@ setup FIQ stack
-	ldr	sp, FIQ_STACK_START
-	.endm
-
-/*
- * exception handlers
- */
-	.align	5
-undefined_instruction:
-	get_bad_stack
-	bad_save_user_regs
-	bl	do_undefined_instruction
-
-	.align	5
-software_interrupt:
-	get_bad_stack_swi
-	bad_save_user_regs
-	bl	do_software_interrupt
-
-	.align	5
-prefetch_abort:
-	get_bad_stack
-	bad_save_user_regs
-	bl	do_prefetch_abort
-
-	.align	5
-data_abort:
-	get_bad_stack
-	bad_save_user_regs
-	bl	do_data_abort
-
-	.align	5
-not_used:
-	get_bad_stack
-	bad_save_user_regs
-	bl	do_not_used
-
-#ifdef CONFIG_USE_IRQ
-
-	.align	5
-irq:
-	get_irq_stack
-	irq_save_user_regs
-	bl	do_irq
-	irq_restore_user_regs
-
-	.align	5
-fiq:
-	get_fiq_stack
-	/* someone ought to write a more effective fiq_save_user_regs */
-	irq_save_user_regs
-	bl	do_fiq
-	irq_restore_user_regs
-
-#else
-
-	.align	5
-irq:
-	get_bad_stack
-	bad_save_user_regs
-	bl	do_irq
-
-	.align	5
-fiq:
-	get_bad_stack
-	bad_save_user_regs
-	bl	do_fiq
-
-#endif
diff --git a/arch/arm/cpu/armv7/syslib.c b/arch/arm/cpu/armv7/syslib.c
deleted file mode 100644
index 84d17f0..0000000
--- a/arch/arm/cpu/armv7/syslib.c
+++ /dev/null
@@ -1,69 +0,0 @@
-/*
- * (C) Copyright 2008
- * Texas Instruments, <www.ti.com>
- *
- * Richard Woodruff <r-woodruff2@ti.com>
- * Syed Mohammed Khasim <khasim@ti.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/io.h>
-
-/************************************************************
- * sdelay() - simple spin loop.  Will be constant time as
- *  its generally used in bypass conditions only.  This
- *  is necessary until timers are accessible.
- *
- *  not inline to increase chances its in cache when called
- *************************************************************/
-void sdelay(unsigned long loops)
-{
-	__asm__ volatile ("1:\n" "subs %0, %1, #1\n"
-			  "bne 1b":"=r" (loops):"0"(loops));
-}
-
-/*****************************************************************
- * sr32 - clear & set a value in a bit range for a 32 bit address
- *****************************************************************/
-void sr32(void *addr, u32 start_bit, u32 num_bits, u32 value)
-{
-	u32 tmp, msk = 0;
-	msk = 1 << num_bits;
-	--msk;
-	tmp = readl((u32)addr) & ~(msk << start_bit);
-	tmp |= value << start_bit;
-	writel(tmp, (u32)addr);
-}
-
-/*********************************************************************
- * wait_on_value() - common routine to allow waiting for changes in
- *   volatile regs.
- *********************************************************************/
-u32 wait_on_value(u32 read_bit_mask, u32 match_value, void *read_addr,
-		  u32 bound)
-{
-	u32 i = 0, val;
-	do {
-		++i;
-		val = readl((u32)read_addr) & read_bit_mask;
-		if (val == match_value)
-			return 1;
-		if (i == bound)
-			return 0;
-	} while (1);
-}
diff --git a/arch/arm/cpu/armv7/tegra2/Makefile b/arch/arm/cpu/armv7/tegra2/Makefile
deleted file mode 100644
index 687c887..0000000
--- a/arch/arm/cpu/armv7/tegra2/Makefile
+++ /dev/null
@@ -1,48 +0,0 @@
-#
-# (C) Copyright 2010,2011 Nvidia Corporation.
-#
-# (C) Copyright 2000-2003
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB	=  $(obj)lib$(SOC).o
-
-SOBJS	:= lowlevel_init.o
-COBJS	:= board.o sys_info.o timer.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS) $(SOBJS))
-
-all:	 $(obj).depend $(LIB)
-
-$(LIB):	$(OBJS)
-	$(AR) $(ARFLAGS) $@ $(OBJS)
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/arch/arm/cpu/armv7/tegra2/board.c b/arch/arm/cpu/armv7/tegra2/board.c
deleted file mode 100644
index 9061d18..0000000
--- a/arch/arm/cpu/armv7/tegra2/board.c
+++ /dev/null
@@ -1,88 +0,0 @@
-/*
- *  (C) Copyright 2010,2011
- *  NVIDIA Corporation <www.nvidia.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/tegra2.h>
-#include <asm/arch/pmc.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*
- * Boot ROM initializes the odmdata in APBDEV_PMC_SCRATCH20_0,
- * so we are using this value to identify memory size.
- */
-
-unsigned int query_sdram_size(void)
-{
-	struct pmc_ctlr *const pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
-	u32 reg;
-
-	reg = readl(&pmc->pmc_scratch20);
-	debug("pmc->pmc_scratch20 (ODMData) = 0x%08lX\n", reg);
-
-	/* bits 31:28 in OdmData are used for RAM size  */
-	switch ((reg) >> 28) {
-	case 1:
-		return 0x10000000;	/* 256 MB */
-	case 2:
-		return 0x20000000;	/* 512 MB */
-	case 3:
-	default:
-		return 0x40000000;	/* 1GB */
-	}
-}
-
-void s_init(void)
-{
-#ifndef CONFIG_ICACHE_OFF
-	icache_enable();
-#endif
-	invalidate_dcache();
-}
-
-int dram_init(void)
-{
-	unsigned long rs;
-
-	/* We do not initialise DRAM here. We just query the size */
-	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
-	gd->bd->bi_dram[0].size = gd->ram_size = query_sdram_size();
-
-	/* Now check it dynamically */
-	rs = get_ram_size(CONFIG_SYS_SDRAM_BASE, gd->ram_size);
-	if (rs) {
-		printf("dynamic ram_size = %lu\n", rs);
-		gd->bd->bi_dram[0].size = gd->ram_size = rs;
-	}
-	return 0;
-}
-
-#ifdef CONFIG_DISPLAY_BOARDINFO
-int checkboard(void)
-{
-	printf("Board: %s\n", sysinfo.board_string);
-	return 0;
-}
-#endif	/* CONFIG_DISPLAY_BOARDINFO */
diff --git a/arch/arm/cpu/armv7/tegra2/config.mk b/arch/arm/cpu/armv7/tegra2/config.mk
deleted file mode 100644
index 96c0795..0000000
--- a/arch/arm/cpu/armv7/tegra2/config.mk
+++ /dev/null
@@ -1,28 +0,0 @@
-#
-# (C) Copyright 2010,2011
-# NVIDIA Corporation <www.nvidia.com>
-#
-# (C) Copyright 2002
-# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-# Use ARMv4 for Tegra2 - initial code runs on the AVP, which is an ARM7TDI.
-PLATFORM_CPPFLAGS += -march=armv4
diff --git a/arch/arm/cpu/armv7/tegra2/lowlevel_init.S b/arch/arm/cpu/armv7/tegra2/lowlevel_init.S
deleted file mode 100644
index 7f15746..0000000
--- a/arch/arm/cpu/armv7/tegra2/lowlevel_init.S
+++ /dev/null
@@ -1,65 +0,0 @@
-/*
- * SoC-specific setup info
- *
- * (C) Copyright 2010,2011
- * NVIDIA Corporation <www.nvidia.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <version.h>
-
-_TEXT_BASE:
-	.word	CONFIG_SYS_TEXT_BASE	@ sdram load addr from config file
-
-.global invalidate_dcache
-invalidate_dcache:
-	mov pc, lr
-
-	.align	5
-.global reset_cpu
-reset_cpu:
-	ldr	r1, rstctl			@ get addr for global reset
-						@ reg
-	ldr	r3, [r1]
-	orr	r3, r3, #0x10
-	str	r3, [r1]			@ force reset
-	mov	r0, r0
-_loop_forever:
-	b	_loop_forever
-rstctl:
-	.word	PRM_RSTCTRL
-
-.globl lowlevel_init
-lowlevel_init:
-	ldr	sp, SRAM_STACK
-	str	ip, [sp]
-	mov	ip, lr
-	bl	s_init				@ go setup pll, mux & memory
-	ldr	ip, [sp]
-	mov	lr, ip
-
-	mov	pc, lr				@ back to arch calling code
-
-	@ the literal pools origin
-	.ltorg
-
-SRAM_STACK:
-	.word LOW_LEVEL_SRAM_STACK
diff --git a/arch/arm/cpu/armv7/tegra2/sys_info.c b/arch/arm/cpu/armv7/tegra2/sys_info.c
deleted file mode 100644
index 6d11dc1..0000000
--- a/arch/arm/cpu/armv7/tegra2/sys_info.c
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- * (C) Copyright 2010,2011
- * NVIDIA Corporation <www.nvidia.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-
-#ifdef CONFIG_DISPLAY_CPUINFO
-/* Print CPU information */
-int print_cpuinfo(void)
-{
-	puts("TEGRA2\n");
-
-	/* TBD: Add printf of major/minor rev info, stepping, etc. */
-	return 0;
-}
-#endif	/* CONFIG_DISPLAY_CPUINFO */
diff --git a/arch/arm/cpu/armv7/tegra2/timer.c b/arch/arm/cpu/armv7/tegra2/timer.c
deleted file mode 100644
index fb061d0..0000000
--- a/arch/arm/cpu/armv7/tegra2/timer.c
+++ /dev/null
@@ -1,122 +0,0 @@
-/*
- * (C) Copyright 2010,2011
- * NVIDIA Corporation <www.nvidia.com>
- *
- * (C) Copyright 2008
- * Texas Instruments
- *
- * Richard Woodruff <r-woodruff2@ti.com>
- * Syed Moahmmed Khasim <khasim@ti.com>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- * Alex Zuepke <azu@sysgo.de>
- *
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/tegra2.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-struct timerus *timer_base = (struct timerus *)NV_PA_TMRUS_BASE;
-
-/* counter runs at 1MHz */
-#define TIMER_CLK	(1000000)
-#define TIMER_LOAD_VAL	0xffffffff
-
-/* timer without interrupts */
-void reset_timer(void)
-{
-	reset_timer_masked();
-}
-
-ulong get_timer(ulong base)
-{
-	return get_timer_masked() - base;
-}
-
-void set_timer(ulong t)
-{
-	gd->tbl = t;
-}
-
-/* delay x useconds */
-void __udelay(unsigned long usec)
-{
-	long tmo = usec * (TIMER_CLK / 1000) / 1000;
-	unsigned long now, last = readl(&timer_base->cntr_1us);
-
-	while (tmo > 0) {
-		now = readl(&timer_base->cntr_1us);
-		if (last > now) /* count up timer overflow */
-			tmo -= TIMER_LOAD_VAL - last + now;
-		else
-			tmo -= now - last;
-		last = now;
-	}
-}
-
-void reset_timer_masked(void)
-{
-	/* reset time, capture current incrementer value time */
-	gd->lastinc = readl(&timer_base->cntr_1us) / (TIMER_CLK/CONFIG_SYS_HZ);
-	gd->tbl = 0;		/* start "advancing" time stamp from 0 */
-}
-
-ulong get_timer_masked(void)
-{
-	ulong now;
-
-	/* current tick value */
-	now = readl(&timer_base->cntr_1us) / (TIMER_CLK / CONFIG_SYS_HZ);
-
-	if (now >= gd->lastinc)	/* normal mode (non roll) */
-		/* move stamp forward with absolute diff ticks */
-		gd->tbl += (now - gd->lastinc);
-	else	/* we have rollover of incrementer */
-		gd->tbl += ((TIMER_LOAD_VAL / (TIMER_CLK / CONFIG_SYS_HZ))
-				- gd->lastinc) + now;
-	gd->lastinc = now;
-	return gd->tbl;
-}
-
-/*
- * This function is derived from PowerPC code (read timebase as long long).
- * On ARM it just returns the timer value.
- */
-unsigned long long get_ticks(void)
-{
-	return get_timer(0);
-}
-
-/*
- * This function is derived from PowerPC code (timebase clock frequency).
- * On ARM it returns the number of timer ticks per second.
- */
-ulong get_tbclk(void)
-{
-	return CONFIG_SYS_HZ;
-}
diff --git a/arch/arm/cpu/armv7/u-boot.lds b/arch/arm/cpu/armv7/u-boot.lds
deleted file mode 100644
index 5725c30..0000000
--- a/arch/arm/cpu/armv7/u-boot.lds
+++ /dev/null
@@ -1,81 +0,0 @@
-/*
- * January 2004 - Changed to support H4 device
- * Copyright (c) 2004-2008 Texas Instruments
- *
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-ENTRY(_start)
-SECTIONS
-{
-	. = 0x00000000;
-
-	. = ALIGN(4);
-	.text	:
-	{
-		arch/arm/cpu/armv7/start.o	(.text)
-		*(.text)
-	}
-
-	. = ALIGN(4);
-	.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
-
-	. = ALIGN(4);
-	.data : {
-		*(.data)
-	}
-
-	. = ALIGN(4);
-
-	. = .;
-	__u_boot_cmd_start = .;
-	.u_boot_cmd : { *(.u_boot_cmd) }
-	__u_boot_cmd_end = .;
-
-	. = ALIGN(4);
-
-	.rel.dyn : {
-		__rel_dyn_start = .;
-		*(.rel*)
-		__rel_dyn_end = .;
-	}
-
-	.dynsym : {
-		__dynsym_start = .;
-		*(.dynsym)
-	}
-
-	.bss __rel_dyn_start (OVERLAY) : {
-		__bss_start = .;
-		*(.bss)
-		 . = ALIGN(4);
-		_end = .;
-	}
-
-	/DISCARD/ : { *(.dynstr*) }
-	/DISCARD/ : { *(.dynamic*) }
-	/DISCARD/ : { *(.plt*) }
-	/DISCARD/ : { *(.interp*) }
-	/DISCARD/ : { *(.gnu*) }
-}
diff --git a/arch/arm/cpu/ixp/Makefile b/arch/arm/cpu/ixp/Makefile
deleted file mode 100644
index b0a466e..0000000
--- a/arch/arm/cpu/ixp/Makefile
+++ /dev/null
@@ -1,50 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(CPU).o
-
-START	= start.o
-
-COBJS-y	+= cpu.o
-COBJS-$(CONFIG_USE_IRQ)	+= interrupts.o
-COBJS-y	+= timer.o
-
-SRCS	:= $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
-START	:= $(addprefix $(obj),$(START))
-
-all:	$(obj).depend $(START) $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/arch/arm/cpu/ixp/config.mk b/arch/arm/cpu/ixp/config.mk
deleted file mode 100644
index deca3f4..0000000
--- a/arch/arm/cpu/ixp/config.mk
+++ /dev/null
@@ -1,35 +0,0 @@
-#
-# (C) Copyright 2002
-# Sysgo Real-Time Solutions, GmbH <www.elinos.com>
-# Marius Groeger <mgroeger@sysgo.de>
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-BIG_ENDIAN = y
-
-PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float -mbig-endian
-
-PLATFORM_CPPFLAGS += -mbig-endian -march=armv5te -mtune=strongarm1100
-# =========================================================================
-#
-# Supply options according to compiler version
-#
-# =========================================================================
-PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))
diff --git a/arch/arm/cpu/ixp/cpu.c b/arch/arm/cpu/ixp/cpu.c
deleted file mode 100644
index ce275e5..0000000
--- a/arch/arm/cpu/ixp/cpu.c
+++ /dev/null
@@ -1,143 +0,0 @@
-/*
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Alex Zuepke <azu@sysgo.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * CPU specific code
- */
-
-#include <common.h>
-#include <command.h>
-#include <netdev.h>
-#include <asm/arch/ixp425.h>
-#include <asm/system.h>
-
-ulong loops_per_jiffy;
-
-static void cache_flush(void);
-
-#if defined(CONFIG_DISPLAY_CPUINFO)
-int print_cpuinfo (void)
-{
-	unsigned long id;
-	int speed = 0;
-
-	asm ("mrc p15, 0, %0, c0, c0, 0":"=r" (id));
-
-	puts("CPU:   Intel IXP425 at ");
-	switch ((id & 0x000003f0) >> 4) {
-	case 0x1c:
-		loops_per_jiffy = 887467;
-		speed = 533;
-		break;
-
-	case 0x1d:
-		loops_per_jiffy = 666016;
-		speed = 400;
-		break;
-
-	case 0x1f:
-		loops_per_jiffy = 442901;
-		speed = 266;
-		break;
-	}
-
-	if (speed)
-		printf("%d MHz\n", speed);
-	else
-		puts("unknown revision\n");
-
-	return 0;
-}
-#endif /* CONFIG_DISPLAY_CPUINFO */
-
-int cleanup_before_linux (void)
-{
-	/*
-	 * this function is called just before we call linux
-	 * it prepares the processor for linux
-	 *
-	 * just disable everything that can disturb booting linux
-	 */
-
-	disable_interrupts ();
-
-	/* turn off I-cache */
-	icache_disable();
-	dcache_disable();
-
-	/* flush I-cache */
-	cache_flush();
-
-	return 0;
-}
-
-/* flush I/D-cache */
-static void cache_flush (void)
-{
-	unsigned long i = 0;
-
-	asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i));
-}
-
-/* FIXME */
-/*
-void pci_init(void)
-{
-	return;
-}
-*/
-
-#ifdef CONFIG_BOOTCOUNT_LIMIT
-
-void bootcount_store (ulong a)
-{
-	volatile ulong *save_addr = (volatile ulong *)(CONFIG_SYS_BOOTCOUNT_ADDR);
-
-	save_addr[0] = a;
-	save_addr[1] = BOOTCOUNT_MAGIC;
-}
-
-ulong bootcount_load (void)
-{
-	volatile ulong *save_addr = (volatile ulong *)(CONFIG_SYS_BOOTCOUNT_ADDR);
-
-	if (save_addr[1] != BOOTCOUNT_MAGIC)
-		return 0;
-	else
-		return save_addr[0];
-}
-
-#endif /* CONFIG_BOOTCOUNT_LIMIT */
-
-int cpu_eth_init(bd_t *bis)
-{
-#ifdef CONFIG_IXP4XX_NPE
-	npe_initialize(bis);
-#endif
-	return 0;
-}
diff --git a/arch/arm/cpu/ixp/interrupts.c b/arch/arm/cpu/ixp/interrupts.c
deleted file mode 100644
index 06a826a..0000000
--- a/arch/arm/cpu/ixp/interrupts.c
+++ /dev/null
@@ -1,82 +0,0 @@
-/*
- * (C) Copyright 2006
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Alex Zuepke <azu@sysgo.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/arch/ixp425.h>
-#include <asm/proc-armv/ptrace.h>
-
-struct _irq_handler {
-	void                *m_data;
-	void (*m_func)( void *data);
-};
-
-static struct _irq_handler IRQ_HANDLER[N_IRQS];
-
-static void default_isr(void *data)
-{
-	printf("default_isr():  called for IRQ %d, Interrupt Status=%x PR=%x\n",
-	       (int)data, *IXP425_ICIP, *IXP425_ICIH);
-}
-
-static int next_irq(void)
-{
-	return (((*IXP425_ICIH & 0x000000fc) >> 2) - 1);
-}
-
-void do_irq (struct pt_regs *pt_regs)
-{
-	int irq = next_irq();
-
-	IRQ_HANDLER[irq].m_func(IRQ_HANDLER[irq].m_data);
-}
-
-void irq_install_handler (int irq, interrupt_handler_t handle_irq, void *data)
-{
-	if (irq >= N_IRQS || !handle_irq)
-		return;
-
-	IRQ_HANDLER[irq].m_data = data;
-	IRQ_HANDLER[irq].m_func = handle_irq;
-}
-
-int arch_interrupt_init (void)
-{
-	int i;
-
-	/* install default interrupt handlers */
-	for (i = 0; i < N_IRQS; i++)
-		irq_install_handler(i, default_isr, (void *)i);
-
-	/* configure interrupts for IRQ mode */
-	*IXP425_ICLR = 0x00000000;
-
-	return (0);
-}
diff --git a/arch/arm/cpu/ixp/npe/IxEthAcc.c b/arch/arm/cpu/ixp/npe/IxEthAcc.c
deleted file mode 100644
index 061b24b..0000000
--- a/arch/arm/cpu/ixp/npe/IxEthAcc.c
+++ /dev/null
@@ -1,261 +0,0 @@
-/**
- * @file IxEthAcc.c
- *
- * @author Intel Corporation
- * @date 20-Feb-2001
- *
- * @brief This file contains the implementation of the IXP425 Ethernet Access Component
- *
- * Design Notes:
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
- */
-
-
-
-#include "IxEthAcc.h"
-#ifdef CONFIG_IXP425_COMPONENT_ETHDB
-#include "IxEthDB.h"
-#endif
-#include "IxFeatureCtrl.h"
-
-#include "IxEthAcc_p.h"
-#include "IxEthAccMac_p.h"
-#include "IxEthAccMii_p.h"
-
-/**
- * @addtogroup IxEthAcc
- *@{
- */
-
-
-/**
- * @brief System-wide information data strucure.
- *
- * @ingroup IxEthAccPri
- *
- */
-
-IxEthAccInfo ixEthAccDataInfo;
-extern PUBLIC IxEthAccMacState ixEthAccMacState[];
-extern PUBLIC IxOsalMutex ixEthAccControlInterfaceMutex;
-
-/**
- * @brief System-wide information
- *
- * @ingroup IxEthAccPri
- *
- */
-BOOL ixEthAccServiceInit = FALSE;
-
-/* global filtering bit mask */
-PUBLIC UINT32 ixEthAccNewSrcMask;
-
-/**
- * @brief Per port information data strucure.
- *
- * @ingroup IxEthAccPri
- *
- */
-
-IxEthAccPortDataInfo ixEthAccPortData[IX_ETH_ACC_NUMBER_OF_PORTS];
-
-PUBLIC IxEthAccStatus ixEthAccInit()
-{
-#ifdef CONFIG_IXP425_COMPONENT_ETHDB
-  /*
-   * Initialize Control plane
-   */
-  if (ixEthDBInit() != IX_ETH_ACC_SUCCESS)
-  {
-      IX_ETH_ACC_WARNING_LOG("ixEthAccInit: EthDB init failed\n", 0, 0, 0, 0, 0, 0);
-
-      return IX_ETH_ACC_FAIL;
-  }
-#endif
-
-  if (IX_FEATURE_CTRL_SWCONFIG_ENABLED == ixFeatureCtrlSwConfigurationCheck (IX_FEATURECTRL_ETH_LEARNING))
-  {
-      ixEthAccNewSrcMask = (~0); /* want all the bits */
-  }
-  else
-  {
-      ixEthAccNewSrcMask = (~IX_ETHACC_NE_NEWSRCMASK); /* want all but the NewSrc bit */
-  }
-
-  /*
-   * Initialize Data plane
-   */
-   if ( ixEthAccInitDataPlane()  != IX_ETH_ACC_SUCCESS )
-   {
-      IX_ETH_ACC_WARNING_LOG("ixEthAccInit: data plane init failed\n", 0, 0, 0, 0, 0, 0);
-
-       return IX_ETH_ACC_FAIL;
-   }
-
-
-   if ( ixEthAccQMgrQueuesConfig() != IX_ETH_ACC_SUCCESS )
-   {
-      IX_ETH_ACC_WARNING_LOG("ixEthAccInit: queue config failed\n", 0, 0, 0, 0, 0, 0);
-
-       return IX_ETH_ACC_FAIL;
-   }
-
-   /*
-    * Initialize MII
-    */
-   if ( ixEthAccMiiInit() != IX_ETH_ACC_SUCCESS )
-   {
-      IX_ETH_ACC_WARNING_LOG("ixEthAccInit: Mii init failed\n", 0, 0, 0, 0, 0, 0);
-
-       return IX_ETH_ACC_FAIL;
-   }
-
-   /*
-    * Initialize MAC I/O memory
-    */
-   if (ixEthAccMacMemInit() != IX_ETH_ACC_SUCCESS)
-   {
-      IX_ETH_ACC_WARNING_LOG("ixEthAccInit: Mac init failed\n", 0, 0, 0, 0, 0, 0);
-
-     return IX_ETH_ACC_FAIL;
-   }
-
-   /*
-    * Initialize control plane interface lock
-    */
-   if (ixOsalMutexInit(&ixEthAccControlInterfaceMutex) != IX_SUCCESS)
-   {
-       IX_ETH_ACC_WARNING_LOG("ixEthAccInit: Control plane interface lock initialization failed\n", 0, 0, 0, 0, 0, 0);
-
-       return IX_ETH_ACC_FAIL;
-   }
-
-   /* initialiasation is complete */
-   ixEthAccServiceInit = TRUE;
-
-   return IX_ETH_ACC_SUCCESS;
-
-}
-
-PUBLIC void ixEthAccUnload(void)
-{
-    IxEthAccPortId portId;
-
-    if ( IX_ETH_ACC_IS_SERVICE_INITIALIZED() )
-    {
-       /* check none of the port is still active */
-       for (portId = 0; portId < IX_ETH_ACC_NUMBER_OF_PORTS; portId++)
-       {
-	   if ( IX_ETH_IS_PORT_INITIALIZED(portId) )
-	   {
-	       if (ixEthAccMacState[portId].portDisableState == ACTIVE)
-	       {
-		   IX_ETH_ACC_WARNING_LOG("ixEthAccUnload: port %u still active, bail out\n", portId, 0, 0, 0, 0, 0);
-		   return;
-	       }
-	   }
-       }
-
-       /* unmap the memory areas */
-       ixEthAccMiiUnload();
-       ixEthAccMacUnload();
-
-       /* set all ports as uninitialized */
-       for (portId = 0; portId < IX_ETH_ACC_NUMBER_OF_PORTS; portId++)
-       {
-	       ixEthAccPortData[portId].portInitialized = FALSE;
-       }
-
-       /* uninitialize the service */
-       ixEthAccServiceInit = FALSE;
-   }
-}
-
-PUBLIC IxEthAccStatus ixEthAccPortInit( IxEthAccPortId portId)
-{
-
-  IxEthAccStatus ret=IX_ETH_ACC_SUCCESS;
-
-   if ( ! IX_ETH_ACC_IS_SERVICE_INITIALIZED() )
-   {
-	return(IX_ETH_ACC_FAIL);
-   }
-
-   /*
-    * Check for valid port
-    */
-
-   if ( ! IX_ETH_ACC_IS_PORT_VALID(portId) )
-   {
-       return (IX_ETH_ACC_INVALID_PORT);
-   }
-
-   if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
-   {
-       IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot initialize Eth port.\n",(INT32) portId,0,0,0,0,0);
-       return IX_ETH_ACC_SUCCESS ;
-   }
-
-   if ( IX_ETH_IS_PORT_INITIALIZED(portId) )
-   {
-	/* Already initialized */
-	return(IX_ETH_ACC_FAIL);
-   }
-
-   if(ixEthAccMacInit(portId)!=IX_ETH_ACC_SUCCESS)
-   {
-       return IX_ETH_ACC_FAIL;
-   }
-
-   /*
-     * Set the port init flag.
-     */
-
-    ixEthAccPortData[portId].portInitialized = TRUE;
-
-#ifdef CONFIG_IXP425_COMPONENT_ETHDB
-    /* init learning/filtering database structures for this port */
-    ixEthDBPortInit(portId);
-#endif
-
-    return(ret);
-}
-
-
diff --git a/arch/arm/cpu/ixp/npe/IxEthAccCommon.c b/arch/arm/cpu/ixp/npe/IxEthAccCommon.c
deleted file mode 100644
index 211203d..0000000
--- a/arch/arm/cpu/ixp/npe/IxEthAccCommon.c
+++ /dev/null
@@ -1,1049 +0,0 @@
-/**
- * @file IxEthAccCommon.c
- *
- * @author Intel Corporation
- * @date 12-Feb-2002
- *
- * @brief This file contains the implementation common support routines for the component
- *
- * Design Notes:
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
- */
-
-/*
- * Component header files
- */
-
-#include "IxOsal.h"
-#include "IxEthAcc.h"
-#include "IxEthDB.h"
-#include "IxNpeMh.h"
-#include "IxEthDBPortDefs.h"
-#include "IxFeatureCtrl.h"
-#include "IxEthAcc_p.h"
-#include "IxEthAccQueueAssign_p.h"
-
-#include "IxEthAccDataPlane_p.h"
-#include "IxEthAccMii_p.h"
-
-/**
- * @addtogroup IxEthAccPri
- *@{
- */
-
-extern IxEthAccInfo   ixEthAccDataInfo;
-
-/**
- *
- * @brief Maximum number of RX queues set to be the maximum number
- * of traffic calsses.
- *
- */
-#define IX_ETHACC_MAX_RX_QUEUES \
-      (IX_ETH_DB_QOS_TRAFFIC_CLASS_7_RX_QUEUE_PROPERTY \
-      - IX_ETH_DB_QOS_TRAFFIC_CLASS_0_RX_QUEUE_PROPERTY \
-      + 1)
-
-/**
- *
- * @brief Maximum number of 128 entry RX queues
- *
- */
-#define IX_ETHACC_MAX_LARGE_RX_QUEUES 4
-
-/**
- *
- * @brief Data structure template for Default RX Queues
- *
- */
-IX_ETH_ACC_PRIVATE
-IxEthAccQregInfo ixEthAccQmgrRxDefaultTemplate =
-  {
-    IX_ETH_ACC_RX_FRAME_ETH_Q,	     /**< Queue ID */
-    "Eth Rx Q",
-    ixEthRxFrameQMCallback,          /**< Functional callback */
-    (IxQMgrCallbackId) 0,	     /**< Callback tag	      */
-    IX_QMGR_Q_SIZE128,		     /**< Allocate Max Size Q */
-    IX_QMGR_Q_ENTRY_SIZE1,	     /**< Queue Entry Sizes - all Q entries are single word entries   */
-    TRUE,			     /**< Enable Q notification at startup */
-    IX_ETH_ACC_RX_FRAME_ETH_Q_SOURCE,/**< Q Condition to drive callback   */
-    IX_QMGR_Q_WM_LEVEL0,	     /**< Q Low water mark */
-    IX_QMGR_Q_WM_LEVEL1,	     /**< Q High water mark - needed by NPE */
-  };
-
-/**
- *
- * @brief Data structure template for Small RX Queues
- *
- */
-IX_ETH_ACC_PRIVATE
-IxEthAccQregInfo ixEthAccQmgrRxSmallTemplate =
-  {
-    IX_ETH_ACC_RX_FRAME_ETH_Q,	     /**< Queue ID */
-    "Eth Rx Q",
-    ixEthRxFrameQMCallback,          /**< Functional callback */
-    (IxQMgrCallbackId) 0,	     /**< Callback tag	      */
-    IX_QMGR_Q_SIZE64,		     /**< Allocate Smaller Q */
-    IX_QMGR_Q_ENTRY_SIZE1,	     /**< Queue Entry Sizes - all Q entries are single word entries   */
-    TRUE,			     /**< Enable Q notification at startup */
-    IX_ETH_ACC_RX_FRAME_ETH_Q_SOURCE,/**< Q Condition to drive callback   */
-    IX_QMGR_Q_WM_LEVEL0,	     /**< Q Low water mark */
-    IX_QMGR_Q_WM_LEVEL1,	     /**< Q High water mark - needed by NPE */
-  };
-
-
-/**
- *
- * @brief Data structure used to register & initialize the Queues
- *
- */
-IX_ETH_ACC_PRIVATE
-IxEthAccQregInfo ixEthAccQmgrStaticInfo[]=
-{
-  {
-    IX_ETH_ACC_RX_FREE_BUFF_ENET0_Q,
-    "Eth Rx Fr Q 1",
-    ixEthRxFreeQMCallback,
-    (IxQMgrCallbackId) IX_ETH_PORT_1,
-    IX_QMGR_Q_SIZE128,		     /**< Allocate Max Size Q */
-    IX_QMGR_Q_ENTRY_SIZE1,	     /**< Queue Entry Sizes - all Q entries are single word entries   */
-    FALSE,			     /**< Disable Q notification at startup */
-    IX_ETH_ACC_RX_FREE_BUFF_ENET0_Q_SOURCE, /**< Q Condition to drive callback  */
-    IX_QMGR_Q_WM_LEVEL0,	     /***< Q Low water mark */
-    IX_QMGR_Q_WM_LEVEL64,	     /**< Q High water mark */
-  },
-
-  {
-    IX_ETH_ACC_RX_FREE_BUFF_ENET1_Q,
-    "Eth Rx Fr Q 2",
-    ixEthRxFreeQMCallback,
-    (IxQMgrCallbackId) IX_ETH_PORT_2,
-    IX_QMGR_Q_SIZE128,		     /**< Allocate Max Size Q */
-    IX_QMGR_Q_ENTRY_SIZE1,	     /**< Queue Entry Sizes - all Q entries are single word entries   */
-    FALSE,			     /**< Disable Q notification at startup */
-    IX_ETH_ACC_RX_FREE_BUFF_ENET1_Q_SOURCE,  /**< Q Condition to drive callback  */
-    IX_QMGR_Q_WM_LEVEL0,	     /**< Q Low water mark */
-    IX_QMGR_Q_WM_LEVEL64,	     /**< Q High water mark */
-  },
-#ifdef __ixp46X
-  {
-    IX_ETH_ACC_RX_FREE_BUFF_ENET2_Q,
-    "Eth Rx Fr Q 3",
-    ixEthRxFreeQMCallback,
-    (IxQMgrCallbackId) IX_ETH_PORT_3,
-    IX_QMGR_Q_SIZE128,		     /**< Allocate Max Size Q */
-    IX_QMGR_Q_ENTRY_SIZE1,	     /**< Queue Entry Sizes - all Q entries are single word entries   */
-    FALSE,			     /**< Disable Q notification at startup */
-    IX_ETH_ACC_RX_FREE_BUFF_ENET2_Q_SOURCE,  /**< Q Condition to drive callback  */
-    IX_QMGR_Q_WM_LEVEL0,	     /**< Q Low water mark */
-    IX_QMGR_Q_WM_LEVEL64,	     /**< Q High water mark */
-  },
-#endif
-  {
-     IX_ETH_ACC_TX_FRAME_ENET0_Q,
-    "Eth Tx Q 1",
-     ixEthTxFrameQMCallback,
-     (IxQMgrCallbackId) IX_ETH_PORT_1,
-    IX_QMGR_Q_SIZE128,		     /**< Allocate Max Size Q */
-    IX_QMGR_Q_ENTRY_SIZE1,	     /**< Queue Entry Sizes - all Q entries are single word entries   */
-    FALSE,			     /**< Disable Q notification at startup */
-    IX_ETH_ACC_TX_FRAME_ENET0_Q_SOURCE,	 /**< Q Condition to drive callback  */
-    IX_QMGR_Q_WM_LEVEL0,	     /**< Q Low water mark */
-    IX_QMGR_Q_WM_LEVEL64,	     /**< Q High water mark */
-  },
-
-  {
-     IX_ETH_ACC_TX_FRAME_ENET1_Q,
-    "Eth Tx Q 2",
-     ixEthTxFrameQMCallback,
-     (IxQMgrCallbackId) IX_ETH_PORT_2,
-    IX_QMGR_Q_SIZE128,		     /**< Allocate Max Size Q */
-    IX_QMGR_Q_ENTRY_SIZE1,	     /**< Queue Entry Sizes - all Q entries are single word entries   */
-    FALSE,			     /**< Disable Q notification at startup */
-    IX_ETH_ACC_TX_FRAME_ENET1_Q_SOURCE,	     /**< Q Condition to drive callback  */
-    IX_QMGR_Q_WM_LEVEL0,	     /**< Q Low water mark */
-    IX_QMGR_Q_WM_LEVEL64,	     /**< Q High water mark */
-  },
-#ifdef __ixp46X
-  {
-     IX_ETH_ACC_TX_FRAME_ENET2_Q,
-    "Eth Tx Q 3",
-     ixEthTxFrameQMCallback,
-     (IxQMgrCallbackId) IX_ETH_PORT_3,
-    IX_QMGR_Q_SIZE128,		     /**< Allocate Max Size Q */
-    IX_QMGR_Q_ENTRY_SIZE1,	     /** Queue Entry Sizes - all Q entries are single ord entries   */
-    FALSE,			     /** Disable Q notification at startup */
-    IX_ETH_ACC_TX_FRAME_ENET2_Q_SOURCE,	     /** Q Condition to drive callback  */
-    IX_QMGR_Q_WM_LEVEL0,	     /* No queues use almost empty */
-    IX_QMGR_Q_WM_LEVEL64,	      /** Q High water mark - needed used  */
-  },
-#endif
-  {
-     IX_ETH_ACC_TX_FRAME_DONE_ETH_Q,
-    "Eth Tx Done Q",
-     ixEthTxFrameDoneQMCallback,
-     (IxQMgrCallbackId) 0,
-    IX_QMGR_Q_SIZE128,		     /**< Allocate Max Size Q */
-    IX_QMGR_Q_ENTRY_SIZE1,	     /**< Queue Entry Sizes - all Q entries are single word entries   */
-    TRUE,			     /**< Enable Q notification at startup */
-    IX_ETH_ACC_TX_FRAME_DONE_ETH_Q_SOURCE, /**< Q Condition to drive callback  */
-    IX_QMGR_Q_WM_LEVEL0,	     /**< Q Low water mark */
-    IX_QMGR_Q_WM_LEVEL2,	     /**< Q High water mark - needed by NPE */
-  },
-
-  {  /* Null Termination entry
-      */
-     (IxQMgrQId)0,
-     (char *) NULL,
-     (IxQMgrCallback) NULL,
-     (IxQMgrCallbackId) 0,
-     0,
-     0,
-     0,
-     0,
-     0,
-     0
-  }
-
-};
-
-/**
- *
- * @brief Data structure used to register & initialize the Queues
- *
- * The structure will be filled at run time depending on the NPE
- * image already loaded and the QoS configured in ethDB.
- *
- */
-IX_ETH_ACC_PRIVATE
-IxEthAccQregInfo ixEthAccQmgrRxQueuesInfo[IX_ETHACC_MAX_RX_QUEUES+1]=
-{
-  {  /* PlaceHolder for rx queues
-      * depending on the QoS configured
-      */
-     (IxQMgrQId)0,
-     (char *) NULL,
-     (IxQMgrCallback) NULL,
-     (IxQMgrCallbackId) 0,
-     0,
-     0,
-     0,
-     0,
-     0,
-     0
-  },
-
-  {  /* PlaceHolder for rx queues
-      * depending on the QoS configured
-      */
-     (IxQMgrQId)0,
-     (char *) NULL,
-     (IxQMgrCallback) NULL,
-     (IxQMgrCallbackId) 0,
-     0,
-     0,
-     0,
-     0,
-     0,
-     0
-  },
-
-  {  /* PlaceHolder for rx queues
-      * depending on the QoS configured
-      */
-     (IxQMgrQId)0,
-     (char *) NULL,
-     (IxQMgrCallback) NULL,
-     (IxQMgrCallbackId) 0,
-     0,
-     0,
-     0,
-     0,
-     0,
-     0
-  },
-
-  {  /* PlaceHolder for rx queues
-      * depending on the QoS configured
-      */
-     (IxQMgrQId)0,
-     (char *) NULL,
-     (IxQMgrCallback) NULL,
-     (IxQMgrCallbackId) 0,
-     0,
-     0,
-     0,
-     0,
-     0,
-     0
-  },
-
-  {  /* PlaceHolder for rx queues
-      * depending on the QoS configured
-      */
-     (IxQMgrQId)0,
-     (char *) NULL,
-     (IxQMgrCallback) NULL,
-     (IxQMgrCallbackId) 0,
-     0,
-     0,
-     0,
-     0,
-     0,
-     0
-  },
-
-  {  /* PlaceHolder for rx queues
-      * depending on the QoS configured
-      */
-      (IxQMgrQId)0,
-     (char *) NULL,
-     (IxQMgrCallback) NULL,
-     (IxQMgrCallbackId) 0,
-     0,
-     0,
-     0,
-     0,
-     0,
-     0
-  },
-
-  {  /* PlaceHolder for rx queues
-      * depending on the QoS configured
-      */
-     (IxQMgrQId)0,
-     (char *) NULL,
-     (IxQMgrCallback) NULL,
-     (IxQMgrCallbackId) 0,
-     0,
-     0,
-     0,
-     0,
-     0,
-     0
-  },
-
-  {  /* PlaceHolder for rx queues
-      * depending on the QoS configured
-      */
-     (IxQMgrQId)0,
-     (char *) NULL,
-     (IxQMgrCallback) NULL,
-     (IxQMgrCallbackId) 0,
-     0,
-     0,
-     0,
-     0,
-     0,
-     0
-  },
-
-  {  /* Null Termination entry
-      */
-     (IxQMgrQId)0,
-     (char *) NULL,
-     (IxQMgrCallback) NULL,
-     (IxQMgrCallbackId) 0,
-     0,
-     0,
-     0,
-     0,
-     0,
-     0
-  }
-
-};
-
-/* forward declarations */
-IX_ETH_ACC_PRIVATE IxEthAccStatus
-ixEthAccQMgrQueueSetup(IxEthAccQregInfo *qInfoDes);
-
-/**
- * @fn ixEthAccQMgrQueueSetup(void)
- *
- * @brief Setup one queue and its event, and register the callback required
- * by this component to the QMgr
- *
- * @internal
- */
-IX_ETH_ACC_PRIVATE IxEthAccStatus
-ixEthAccQMgrQueueSetup(IxEthAccQregInfo *qInfoDes)
-{
-    /*
-     * Configure each Q.
-     */
-    if ( ixQMgrQConfig( qInfoDes->qName,
-			qInfoDes->qId,
-			qInfoDes->qSize,
-			qInfoDes->qWords) != IX_SUCCESS)
-    {
-	return IX_ETH_ACC_FAIL;
-    }
-
-    if ( ixQMgrWatermarkSet( qInfoDes->qId,
-			     qInfoDes->AlmostEmptyThreshold,
-			     qInfoDes->AlmostFullThreshold
-			     ) != IX_SUCCESS)
-    {
-	return IX_ETH_ACC_FAIL;
-    }
-
-    /*
-     * Set dispatcher priority.
-     */
-    if ( ixQMgrDispatcherPrioritySet( qInfoDes->qId,
-				      IX_ETH_ACC_QM_QUEUE_DISPATCH_PRIORITY)
-	 != IX_SUCCESS)
-    {
-	return IX_ETH_ACC_FAIL;
-    }
-
-    /*
-     * Register callbacks for each Q.
-     */
-    if ( ixQMgrNotificationCallbackSet(qInfoDes->qId,
-				       qInfoDes->qCallback,
-				       qInfoDes->callbackTag)
-	 != IX_SUCCESS )
-    {
-	return IX_ETH_ACC_FAIL;
-    }
-
-    /*
-     * Set notification condition for Q
-     */
-    if ( qInfoDes->qNotificationEnableAtStartup == TRUE )
-    {
-	if (   ixQMgrNotificationEnable(qInfoDes->qId,
-					qInfoDes->qConditionSource)
-	       != IX_SUCCESS )
-	{
-	    return IX_ETH_ACC_FAIL;
-	}
-    }
-
-    return(IX_ETH_ACC_SUCCESS);
-}
-
-/**
- * @fn ixEthAccQMgrQueuesConfig(void)
- *
- * @brief Setup all the queues and register all callbacks required
- * by this component to the QMgr
- *
- * The RxFree queues, tx queues, rx queues are configured statically
- *
- * Rx queues configuration is driven by QoS setup.
- * Many Rx queues may be required when QoS is enabled (this depends
- * on IxEthDB setup and the images being downloaded). The configuration
- * of the rxQueues is done in many steps as follows:
- *
- * @li select all Rx queues as configured by ethDB for all ports
- * @li sort the queues by traffic class
- * @li build the priority dependency for all queues
- * @li fill the configuration for all rx queues
- * @li configure all statically configured queues
- * @li configure all dynamically configured queues
- *
- * @param none
- *
- * @return IxEthAccStatus
- *
- * @internal
- */
-IX_ETH_ACC_PUBLIC
-IxEthAccStatus ixEthAccQMgrQueuesConfig(void)
-{
-    struct
-    {
-	int npeCount;
-	UINT32 npeId;
-	IxQMgrQId qId;
-	IxEthDBProperty trafficClass;
-    } rxQueues[IX_ETHACC_MAX_RX_QUEUES];
-
-    UINT32 rxQueue = 0;
-    UINT32 rxQueueCount = 0;
-    IxQMgrQId ixQId =IX_QMGR_MAX_NUM_QUEUES;
-    IxEthDBStatus ixEthDBStatus = IX_ETH_DB_SUCCESS;
-    IxEthDBPortId ixEthDbPortId = 0;
-    IxEthAccPortId ixEthAccPortId = 0;
-    UINT32 ixNpeId = 0;
-    UINT32 ixHighestNpeId = 0;
-    UINT32 sortIterations = 0;
-    IxEthAccStatus ret = IX_ETH_ACC_SUCCESS;
-    IxEthAccQregInfo *qInfoDes = NULL;
-    IxEthDBProperty ixEthDBTrafficClass = IX_ETH_DB_QOS_TRAFFIC_CLASS_0_RX_QUEUE_PROPERTY;
-    IxEthDBPropertyType ixEthDBPropertyType = IX_ETH_DB_INTEGER_PROPERTY;
-    UINT32 ixEthDBParameter = 0;
-    BOOL completelySorted = FALSE;
-
-    /* Fill the corspondance between ports and queues
-     * This defines the mapping from port to queue Ids.
-     */
-
-    ixEthAccPortData[IX_ETH_PORT_1].ixEthAccRxData.rxFreeQueue
-	= IX_ETH_ACC_RX_FREE_BUFF_ENET0_Q;
-    ixEthAccPortData[IX_ETH_PORT_2].ixEthAccRxData.rxFreeQueue
-	= IX_ETH_ACC_RX_FREE_BUFF_ENET1_Q;
-#ifdef __ixp46X
-    ixEthAccPortData[IX_ETH_PORT_3].ixEthAccRxData.rxFreeQueue
-	= IX_ETH_ACC_RX_FREE_BUFF_ENET2_Q;
-#endif
-    ixEthAccPortData[IX_ETH_PORT_1].ixEthAccTxData.txQueue
-	= IX_ETH_ACC_TX_FRAME_ENET0_Q;
-    ixEthAccPortData[IX_ETH_PORT_2].ixEthAccTxData.txQueue
-	= IX_ETH_ACC_TX_FRAME_ENET1_Q;
-#ifdef __ixp46X
-    ixEthAccPortData[IX_ETH_PORT_3].ixEthAccTxData.txQueue
-	= IX_ETH_ACC_TX_FRAME_ENET2_Q;
-#endif
-    /* Fill the corspondance between ports and NPEs
-     * This defines the mapping from port to npeIds.
-     */
-
-    ixEthAccPortData[IX_ETH_PORT_1].npeId = IX_NPEMH_NPEID_NPEB;
-    ixEthAccPortData[IX_ETH_PORT_2].npeId = IX_NPEMH_NPEID_NPEC;
-#ifdef __ixp46X
-    ixEthAccPortData[IX_ETH_PORT_3].npeId = IX_NPEMH_NPEID_NPEA;
-#endif
-    /* set the default rx scheduling discipline */
-    ixEthAccDataInfo.schDiscipline = FIFO_NO_PRIORITY;
-
-    /*
-     * Queue Selection step:
-     *
-     * The following code selects all the queues and build
-     * a temporary array which contains for each queue
-     * - the queue Id,
-     * - the highest traffic class (in case of many
-     * priorities configured for the same queue on different
-     * ports)
-     * - the number of different Npes which are
-     * configured to write to this queue.
-     *
-     * The output of this loop is a temporary array of RX queues
-     * in any order.
-     *
-     */
-#ifdef CONFIG_IXP425_COMPONENT_ETHDB
-    for (ixEthAccPortId = 0;
-	 (ixEthAccPortId < IX_ETH_ACC_NUMBER_OF_PORTS)
-	     && (ret == IX_ETH_ACC_SUCCESS);
-	 ixEthAccPortId++)
-    {
-	/* map between ethDb and ethAcc port Ids */
-	ixEthDbPortId = (IxEthDBPortId)ixEthAccPortId;
-
-	/* map between npeId and ethAcc port Ids */
-	ixNpeId = IX_ETH_ACC_PORT_TO_NPE_ID(ixEthAccPortId);
-
-	/* Iterate thru the different priorities */
-	for (ixEthDBTrafficClass = IX_ETH_DB_QOS_TRAFFIC_CLASS_0_RX_QUEUE_PROPERTY;
-	     ixEthDBTrafficClass <= IX_ETH_DB_QOS_TRAFFIC_CLASS_7_RX_QUEUE_PROPERTY;
-	     ixEthDBTrafficClass++)
-	{
-	    ixEthDBStatus = ixEthDBFeaturePropertyGet(
-	      ixEthDbPortId,
-	      IX_ETH_DB_VLAN_QOS,
-	      ixEthDBTrafficClass,
-	      &ixEthDBPropertyType,
-	      (void *)&ixEthDBParameter);
-
-	    if (ixEthDBStatus == IX_ETH_DB_SUCCESS)
-	    {
-		/* This port and QoS class are mapped to
-		 * a RX queue.
-		 */
-		if (ixEthDBPropertyType == IX_ETH_DB_INTEGER_PROPERTY)
-		{
-		    /* remember the highest npe Id supporting ethernet */
-		    if (ixNpeId > ixHighestNpeId)
-		    {
-			ixHighestNpeId = ixNpeId;
-		    }
-
-		    /* search the queue in the list of queues
-		     * already used by an other port or QoS
-		     */
-		    for (rxQueue = 0;
-			 rxQueue < rxQueueCount;
-			 rxQueue++)
-		    {
-			if (rxQueues[rxQueue].qId == (IxQMgrQId)ixEthDBParameter)
-			{
-			    /* found an existing setup, update the number of ports
-			     * for this queue if the port maps to
-			     * a different NPE.
-			     */
-			    if (rxQueues[rxQueue].npeId != ixNpeId)
-			    {
-				rxQueues[rxQueue].npeCount++;
-				rxQueues[rxQueue].npeId = ixNpeId;
-			    }
-			    /* get the highest traffic class for this queue */
-			    if (rxQueues[rxQueue].trafficClass > ixEthDBTrafficClass)
-			    {
-				rxQueues[rxQueue].trafficClass = ixEthDBTrafficClass;
-			    }
-			    break;
-			}
-		    }
-		    if (rxQueue == rxQueueCount)
-		    {
-			/* new queue not found in the current list,
-			 * add a new entry.
-			 */
-			IX_OSAL_ASSERT(rxQueueCount < IX_ETHACC_MAX_RX_QUEUES);
-			rxQueues[rxQueueCount].qId = ixEthDBParameter;
-			rxQueues[rxQueueCount].npeCount = 1;
-			rxQueues[rxQueueCount].npeId = ixNpeId;
-			rxQueues[rxQueueCount].trafficClass = ixEthDBTrafficClass;
-			rxQueueCount++;
-		    }
-		}
-		else
-		{
-		    /* unexpected property type (not Integer) */
-		    ret = IX_ETH_ACC_FAIL;
-
-                    IX_ETH_ACC_WARNING_LOG("ixEthAccQMgrQueuesConfig: unexpected property type returned by EthDB\n", 0, 0, 0, 0, 0, 0);
-
-		    /* no point to continue to iterate */
-		    break;
-		}
-	    }
-	    else
-	    {
-		/* No Rx queue configured for this port
-		 * and this traffic class. Do nothing.
-		 */
-	    }
-	}
-
-        /* notify EthDB that queue initialization is complete and traffic class allocation is frozen */
-        ixEthDBFeaturePropertySet(ixEthDbPortId,
-            IX_ETH_DB_VLAN_QOS,
-            IX_ETH_DB_QOS_QUEUE_CONFIGURATION_COMPLETE,
-            NULL /* ignored */);
-    }
-
-#else
-
-    ixNpeId = IX_ETH_ACC_PORT_TO_NPE_ID(ixEthAccPortId);
-    rxQueues[0].qId = 4;
-    rxQueues[0].npeCount = 1;
-    rxQueues[0].npeId = ixNpeId;
-    rxQueues[0].trafficClass = IX_ETH_DB_QOS_TRAFFIC_CLASS_0_RX_QUEUE_PROPERTY;
-    rxQueueCount++;
-
-#endif
-
-    /* check there is at least 1 rx queue : there is no point
-     * to continue if there is no rx queue configured
-     */
-    if ((rxQueueCount == 0) || (ret == IX_ETH_ACC_FAIL))
-    {
-        IX_ETH_ACC_WARNING_LOG("ixEthAccQMgrQueuesConfig: no queues configured, bailing out\n", 0, 0, 0, 0, 0, 0);
-	return (IX_ETH_ACC_FAIL);
-    }
-
-    /* Queue sort step:
-     *
-     * Re-order the array of queues by decreasing traffic class
-     * using a bubble sort. (trafficClass 0 is the lowest
-     * priority traffic, trafficClass 7 is the highest priority traffic)
-     *
-     * Primary sort order is traffic class
-     * Secondary sort order is npeId
-     *
-     * Note that a bubble sort algorithm is not very efficient when
-     * the number of queues grows . However, this is not a very bad choice
-     * considering the very small number of entries to sort. Also, bubble
-     * sort is extremely fast when the list is already sorted.
-     *
-     * The output of this loop is a sorted array of queues.
-     *
-     */
-    sortIterations = 0;
-    do
-    {
-	sortIterations++;
-	completelySorted = TRUE;
-	for (rxQueue = 0;
-	     rxQueue < rxQueueCount - sortIterations;
-	     rxQueue++)
-	{
-	    /* compare adjacent elements */
-	    if ((rxQueues[rxQueue].trafficClass <
-		rxQueues[rxQueue+1].trafficClass)
-		|| ((rxQueues[rxQueue].trafficClass ==
-		     rxQueues[rxQueue+1].trafficClass)
-		    &&(rxQueues[rxQueue].npeId <
-		       rxQueues[rxQueue+1].npeId)))
-	    {
-		/* swap adjacent elements */
-		int npeCount = rxQueues[rxQueue].npeCount;
-		UINT32 npeId = rxQueues[rxQueue].npeId;
-		IxQMgrQId qId = rxQueues[rxQueue].qId;
-		IxEthDBProperty trafficClass = rxQueues[rxQueue].trafficClass;
-		rxQueues[rxQueue].npeCount = rxQueues[rxQueue+1].npeCount;
-		rxQueues[rxQueue].npeId = rxQueues[rxQueue+1].npeId;
-		rxQueues[rxQueue].qId = rxQueues[rxQueue+1].qId;
-		rxQueues[rxQueue].trafficClass = rxQueues[rxQueue+1].trafficClass;
-		rxQueues[rxQueue+1].npeCount = npeCount;
-		rxQueues[rxQueue+1].npeId = npeId;
-		rxQueues[rxQueue+1].qId = qId;
-		rxQueues[rxQueue+1].trafficClass = trafficClass;
-		completelySorted = FALSE;
-	    }
-	}
-    }
-    while (!completelySorted);
-
-    /* Queue traffic class list:
-     *
-     * Fill an array of rx queues linked by ascending traffic classes.
-     *
-     * If the queues are configured as follows
-     *   qId 6 -> traffic class 0 (lowest)
-     *   qId 7 -> traffic class 0
-     *   qId 8 -> traffic class 6
-     *   qId 12 -> traffic class 7 (highest)
-     *
-     * Then the output of this loop will be
-     *
-     * higherPriorityQueue[6] = 8
-     * higherPriorityQueue[7] = 8
-     * higherPriorityQueue[8] = 12
-     * higherPriorityQueue[12] = Invalid queueId
-     * higherPriorityQueue[...] = Invalid queueId
-     *
-     * Note that this queue ordering does not handle all possibilities
-     * that could result from different rules associated with different
-     * ports, and inconsistencies in the rules. In all cases, the
-     * output of this  algorithm is a simple linked list of queues,
-     * without closed circuit.
-
-     * This list is implemented as an array with invalid values initialized
-     * with an "invalid" queue id which is the maximum number of queues.
-     *
-     */
-
-    /*
-     * Initialise the rx queue list.
-     */
-    for (rxQueue = 0; rxQueue < IX_QMGR_MAX_NUM_QUEUES; rxQueue++)
-    {
-	ixEthAccDataInfo.higherPriorityQueue[rxQueue] = IX_QMGR_MAX_NUM_QUEUES;
-    }
-
-    /* build the linked list for this NPE.
-     */
-    for (ixNpeId = 0;
-	 ixNpeId <= ixHighestNpeId;
-	 ixNpeId++)
-    {
-	/* iterate thru the sorted list of queues
-	 */
-	ixQId = IX_QMGR_MAX_NUM_QUEUES;
-	for (rxQueue = 0;
-	     rxQueue < rxQueueCount;
-	     rxQueue++)
-	{
-	    if (rxQueues[rxQueue].npeId == ixNpeId)
-	    {
-		ixEthAccDataInfo.higherPriorityQueue[rxQueues[rxQueue].qId] = ixQId;
-		/* iterate thru queues with the same traffic class
-		 * than the current queue. (queues are ordered by descending
-		 * traffic classes and npeIds).
-		 */
-		while ((rxQueue < rxQueueCount - 1)
-		       && (rxQueues[rxQueue].trafficClass
-			   == rxQueues[rxQueue+1].trafficClass)
-		       && (ixNpeId == rxQueues[rxQueue].npeId))
-		{
-		    rxQueue++;
-		    ixEthAccDataInfo.higherPriorityQueue[rxQueues[rxQueue].qId] = ixQId;
-		}
-		ixQId = rxQueues[rxQueue].qId;
-	    }
-	}
-    }
-
-    /* point on the first dynamic queue description */
-    qInfoDes = ixEthAccQmgrRxQueuesInfo;
-
-    /* update the list of queues with the rx queues */
-    for (rxQueue = 0;
-	 (rxQueue < rxQueueCount) && (ret == IX_ETH_ACC_SUCCESS);
-	 rxQueue++)
-    {
-	/* Don't utilize more than IX_ETHACC_MAX_LARGE_RX_QUEUES queues
-	 * with the full 128 entries.  For the lower priority queues, use
-	 * a smaller number of entries.  This ensures queue resources
-	 * remain available for other components.
-	 */
-	if( (rxQueueCount > IX_ETHACC_MAX_LARGE_RX_QUEUES) &&
-	    (rxQueue < rxQueueCount - IX_ETHACC_MAX_LARGE_RX_QUEUES) )
-	{
-	    /* add the small RX Queue setup template to the list of queues */
-	    memcpy(qInfoDes, &ixEthAccQmgrRxSmallTemplate, sizeof(*qInfoDes));
-	} else {
-	    /* add the default RX Queue setup template to the list of queues */
-	    memcpy(qInfoDes, &ixEthAccQmgrRxDefaultTemplate, sizeof(*qInfoDes));
-	}
-
-	/* setup the RxQueue ID */
-	qInfoDes->qId = rxQueues[rxQueue].qId;
-
-	/* setup the RxQueue watermark level
-	 *
-	 * Each queue can be filled by many NPEs. To avoid the
-	 * NPEs to write to a full queue, need to set the
-	 * high watermark level for nearly full condition.
-	 * (the high watermark level are a power of 2
-	 * starting from the top of the queue)
-	 *
-	 * Number of     watermark
-         *   ports        level
-         *    1             0
-	 *    2             1
-	 *    3             2
-	 *    4             4
-	 *    5             4
-	 *    6             8
-	 *    n          approx. 2**ceil(log2(n))
-	 */
-	if (rxQueues[rxQueue].npeCount == 1)
-	{
-	    qInfoDes->AlmostFullThreshold = IX_QMGR_Q_WM_LEVEL0;
-	}
-	else if (rxQueues[rxQueue].npeCount == 2)
-	{
-	    qInfoDes->AlmostFullThreshold = IX_QMGR_Q_WM_LEVEL1;
-	}
-	else if (rxQueues[rxQueue].npeCount == 3)
-	{
-	    qInfoDes->AlmostFullThreshold = IX_QMGR_Q_WM_LEVEL2;
-	}
-	else
-	{
-	    /* reach the maximum number for CSR 2.0 */
-            IX_ETH_ACC_WARNING_LOG("ixEthAccQMgrQueuesConfig: maximum number of NPEs per queue reached, bailing out\n", 0, 0, 0, 0, 0, 0);
-	    ret = IX_ETH_ACC_FAIL;
-	    break;
-	}
-
-	/* move to next queue entry */
-	++qInfoDes;
-    }
-
-    /* configure the static list (RxFree, Tx and TxDone queues) */
-    for (qInfoDes = ixEthAccQmgrStaticInfo;
-	 (qInfoDes->qCallback != (IxQMgrCallback) NULL )
-	     && (ret == IX_ETH_ACC_SUCCESS);
-	 ++qInfoDes)
-    {
-	ret = ixEthAccQMgrQueueSetup(qInfoDes);
-    }
-
-    /* configure the dynamic list (Rx queues) */
-    for (qInfoDes = ixEthAccQmgrRxQueuesInfo;
-	 (qInfoDes->qCallback != (IxQMgrCallback) NULL )
-	     && (ret == IX_ETH_ACC_SUCCESS);
-	 ++qInfoDes)
-    {
-	ret = ixEthAccQMgrQueueSetup(qInfoDes);
-    }
-
-    return(ret);
-}
-
-/**
- * @fn ixEthAccQMgrRxQEntryGet(UINT32 *rxQueueEntries)
- *
- * @brief Add and return the total number of entries in all Rx queues
- *
- * @param UINT32 rxQueueEntries[in] number of entries in all queues
- *
- * @return void
- *
- * @note Rx queues configuration is driven by Qos Setup. There is a
- * variable number of rx queues which are set at initialisation.
- *
- * @internal
- */
-IX_ETH_ACC_PUBLIC
-void ixEthAccQMgrRxQEntryGet(UINT32 *numRxQueueEntries)
-{
-    UINT32 rxQueueLevel;
-    IxEthAccQregInfo *qInfoDes;;
-
-    *numRxQueueEntries = 0;
-
-    /* iterate thru rx queues */
-    for (qInfoDes = ixEthAccQmgrRxQueuesInfo;
-	 qInfoDes->qCallback != (IxQMgrCallback)NULL;
-	 ++qInfoDes)
-    {
-	/* retrieve the rx queue level */
-	rxQueueLevel = 0;
-	ixQMgrQNumEntriesGet(qInfoDes->qId, &rxQueueLevel);
-	(*numRxQueueEntries) += rxQueueLevel;
-    }
-}
-
-/**
- * @fn ixEthAccQMgrRxCallbacksRegister(IxQMgrCallback ixQMgrCallback)
- *
- * @brief Change the callback registered to all rx queues.
- *
- * @param IxQMgrCallback ixQMgrCallback[in] QMgr callback to register
- *
- * @return IxEthAccStatus
- *
- * @note The user may decide to use different Rx mechanisms
- * (e.g. receive many frames at the same time , or receive
- *  one frame at a time, depending on the overall application
- *  performances). A different QMgr callback is registered. This
- *  way, there is no excessive pointer checks in the datapath.
- *
- * @internal
- */
-IX_ETH_ACC_PUBLIC
-IxEthAccStatus ixEthAccQMgrRxCallbacksRegister(IxQMgrCallback ixQMgrCallback)
-{
-    IxEthAccQregInfo *qInfoDes;
-    IxEthAccStatus ret = IX_ETH_ACC_SUCCESS;
-
-    /* parameter check */
-    if (NULL == ixQMgrCallback)
-    {
-	ret = IX_ETH_ACC_FAIL;
-    }
-
-    /* iterate thru rx queues */
-    for (qInfoDes = ixEthAccQmgrRxQueuesInfo;
-	 (qInfoDes->qCallback != (IxQMgrCallback) NULL )
-	     && (ret == IX_ETH_ACC_SUCCESS);
-	 ++qInfoDes)
-    {
-	/* register the rx callback for all queues */
-	if (ixQMgrNotificationCallbackSet(qInfoDes->qId,
-					     ixQMgrCallback,
-					     qInfoDes->callbackTag
-					     ) != IX_SUCCESS)
-	{
-	    ret = IX_ETH_ACC_FAIL;
-	}
-    }
-    return(ret);
-}
-
-/**
- * @fn ixEthAccSingleEthNpeCheck(IxEthAccPortId portId)
- *
- * @brief Check the npe exists for this port
- *
- * @param IxEthAccPortId portId[in] port
- *
- * @return IxEthAccStatus
- *
- * @internal
- */
-IX_ETH_ACC_PUBLIC
-IxEthAccStatus ixEthAccSingleEthNpeCheck(IxEthAccPortId portId)
-{
-
-    /* If not IXP42X A0 stepping, proceed to check for existence of coprocessors */
-    if ((IX_FEATURE_CTRL_SILICON_TYPE_A0 !=
-        (ixFeatureCtrlProductIdRead() & IX_FEATURE_CTRL_SILICON_STEPPING_MASK))
-        || (IX_FEATURE_CTRL_DEVICE_TYPE_IXP42X != ixFeatureCtrlDeviceRead ()))
-      {
-            if ((IX_ETH_PORT_1 == portId) &&
-                (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_ETH0) ==
-                 IX_FEATURE_CTRL_COMPONENT_ENABLED))
-            {
-                return IX_ETH_ACC_SUCCESS;
-            }
-
-            if ((IX_ETH_PORT_2 == portId) &&
-                (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_ETH1) ==
-                 IX_FEATURE_CTRL_COMPONENT_ENABLED))
-            {
-                return IX_ETH_ACC_SUCCESS;
-            }
-
-            if ((IX_ETH_PORT_3 == portId) &&
-                (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEA_ETH) ==
-                 IX_FEATURE_CTRL_COMPONENT_ENABLED))
-            {
-                return IX_ETH_ACC_SUCCESS;
-            }
-
-            return IX_ETH_ACC_FAIL;
-      }
-
-    return IX_ETH_ACC_SUCCESS;
-}
-
-/**
- * @fn ixEthAccStatsShow(void)
- *
- * @brief Displays all EthAcc stats
- *
- * @return void
- *
- */
-void ixEthAccStatsShow(IxEthAccPortId portId)
-{
-    ixEthAccMdioShow();
-
-    printf("\nPort %u\nUnicast MAC : ", portId);
-    ixEthAccPortUnicastAddressShow(portId);
-    ixEthAccPortMulticastAddressShow(portId);
-    printf("\n");
-
-    ixEthAccDataPlaneShow();
-}
-
-
-
diff --git a/arch/arm/cpu/ixp/npe/IxEthAccControlInterface.c b/arch/arm/cpu/ixp/npe/IxEthAccControlInterface.c
deleted file mode 100644
index 4432847..0000000
--- a/arch/arm/cpu/ixp/npe/IxEthAccControlInterface.c
+++ /dev/null
@@ -1,533 +0,0 @@
-/**
- * @file IxEthAccControlInterface.c
- *
- * @author Intel Corporation
- * @date 
- *
- * @brief IX_ETH_ACC_PUBLIC wrappers for control plane functions
- *
- * Design Notes:
- *
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- * 
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- * 
- * @par
- * -- End of Copyright Notice --
- */
-
-#include "IxOsal.h"
-#include "IxEthAcc.h"
-#include "IxEthAcc_p.h"
-
-PUBLIC IxOsalMutex ixEthAccControlInterfaceMutex;
-
-IX_ETH_ACC_PUBLIC IxEthAccStatus
-ixEthAccPortEnable(IxEthAccPortId portId)
-{
-    IxEthAccStatus result;
-
-    if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
-    {
-        printf("EthAcc: (Mac) cannot enable port %d, service not initialized\n", portId);
-	return (IX_ETH_ACC_FAIL);
-    }
-
-    ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER);
-    result = ixEthAccPortEnablePriv(portId);
-    ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex);
-    return result;
-}
-
-IX_ETH_ACC_PUBLIC IxEthAccStatus 
-ixEthAccPortDisable(IxEthAccPortId portId)
-{
-    IxEthAccStatus result;
-
-    /* check the context is iinitialized */
-    if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
-    {
-	return (IX_ETH_ACC_FAIL);
-    }
-
-    ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER);
-    result = ixEthAccPortDisablePriv(portId);
-    ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex);
-    return result;
-}
-
-IX_ETH_ACC_PUBLIC IxEthAccStatus
-ixEthAccPortEnabledQuery(IxEthAccPortId portId, BOOL *enabled)
-{
-    IxEthAccStatus result;
-
-    if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
-    {
-	return (IX_ETH_ACC_FAIL);
-    }
-
-    ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER);
-    result = ixEthAccPortEnabledQueryPriv(portId, enabled);
-    ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex);
-    return result;
-}
-
-IX_ETH_ACC_PUBLIC IxEthAccStatus 
-ixEthAccPortPromiscuousModeClear(IxEthAccPortId portId)
-{
-    IxEthAccStatus result;
-
-    if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
-    {
-	return (IX_ETH_ACC_FAIL);
-    }
-
-    ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER);
-    result = ixEthAccPortPromiscuousModeClearPriv(portId);
-    ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex);
-    return result;
-}
-
-IX_ETH_ACC_PUBLIC IxEthAccStatus 
-ixEthAccPortPromiscuousModeSet(IxEthAccPortId portId)
-{
-    IxEthAccStatus result;
-
-    if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
-    {
-	return (IX_ETH_ACC_FAIL);
-    }
-
-    ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER);
-    result = ixEthAccPortPromiscuousModeSetPriv(portId);
-    ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex);
-    return result;
-}
-
-IX_ETH_ACC_PUBLIC IxEthAccStatus 
-ixEthAccPortUnicastMacAddressSet(IxEthAccPortId portId, IxEthAccMacAddr *macAddr)
-{
-    IxEthAccStatus result;
-
-    if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
-    {
-	return (IX_ETH_ACC_FAIL);
-    }
-
-    ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER);
-    result = ixEthAccPortUnicastMacAddressSetPriv(portId, macAddr);
-    ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex);
-    return result;
-}
-
-IX_ETH_ACC_PUBLIC IxEthAccStatus
-ixEthAccPortUnicastMacAddressGet(IxEthAccPortId portId, IxEthAccMacAddr *macAddr)
-{
-    IxEthAccStatus result;
-
-    if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
-    {
-	return (IX_ETH_ACC_FAIL);
-    }
-
-    ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER);
-    result = ixEthAccPortUnicastMacAddressGetPriv(portId, macAddr);
-    ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex);
-    return result;
-}
-
-IX_ETH_ACC_PUBLIC IxEthAccStatus
-ixEthAccPortMulticastAddressJoin(IxEthAccPortId portId, IxEthAccMacAddr *macAddr)
-{
-    IxEthAccStatus result;
-
-    if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
-    {
-	return (IX_ETH_ACC_FAIL);
-    }
-
-    ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER);
-    result = ixEthAccPortMulticastAddressJoinPriv(portId, macAddr);
-    ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex);
-    return result;
-}
-
-IX_ETH_ACC_PUBLIC IxEthAccStatus
-ixEthAccPortMulticastAddressJoinAll(IxEthAccPortId portId)
-{
-    IxEthAccStatus result;
-
-    if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
-    {
-	return (IX_ETH_ACC_FAIL);
-    }
-
-    ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER);
-    result = ixEthAccPortMulticastAddressJoinAllPriv(portId);
-    ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex);
-    return result;
-}
-
-IX_ETH_ACC_PUBLIC IxEthAccStatus
-ixEthAccPortMulticastAddressLeave(IxEthAccPortId portId, IxEthAccMacAddr *macAddr)
-{
-    IxEthAccStatus result;
-
-    if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
-    {
-	return (IX_ETH_ACC_FAIL);
-    }
-
-    ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER);
-    result = ixEthAccPortMulticastAddressLeavePriv(portId, macAddr);
-    ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex);
-    return result;
-}
-
-IX_ETH_ACC_PUBLIC IxEthAccStatus
-ixEthAccPortMulticastAddressLeaveAll(IxEthAccPortId portId)
-{
-    IxEthAccStatus result;
-
-    if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
-    {
-	return (IX_ETH_ACC_FAIL);
-    }
-
-    ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER);
-    result = ixEthAccPortMulticastAddressLeaveAllPriv(portId);
-    ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex);
-    return result;
-}
-
-IX_ETH_ACC_PUBLIC IxEthAccStatus 
-ixEthAccPortUnicastAddressShow(IxEthAccPortId portId)
-{
-    IxEthAccStatus result;
- 
-    if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
-    {
-	return (IX_ETH_ACC_FAIL);
-    }
-
-    ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER);
-    result = ixEthAccPortUnicastAddressShowPriv(portId);
-    ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex);
-    return result;
-}
-
-IX_ETH_ACC_PUBLIC void 
-ixEthAccPortMulticastAddressShow(IxEthAccPortId portId)
-{
-    if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
-    {
-	return;
-    }
-
-    ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER);
-    ixEthAccPortMulticastAddressShowPriv(portId);
-    ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex);
-}
-
-IX_ETH_ACC_PUBLIC IxEthAccStatus 
-ixEthAccPortDuplexModeSet(IxEthAccPortId portId, IxEthAccDuplexMode mode)
-{
-    IxEthAccStatus result;
-
-    if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
-    {
-	return (IX_ETH_ACC_FAIL);
-    }
-
-    ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER);
-    result = ixEthAccPortDuplexModeSetPriv(portId, mode);
-    ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex);
-    return result;
-}
-
-IX_ETH_ACC_PUBLIC IxEthAccStatus 
-ixEthAccPortDuplexModeGet(IxEthAccPortId portId, IxEthAccDuplexMode *mode)
-{
-    IxEthAccStatus result;
-
-    if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
-    {
-	return (IX_ETH_ACC_FAIL);
-    }
-
-    ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER);
-    result = ixEthAccPortDuplexModeGetPriv(portId, mode);
-    ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex);
-    return result;
-}
-
-IX_ETH_ACC_PUBLIC IxEthAccStatus
-ixEthAccPortTxFrameAppendPaddingEnable(IxEthAccPortId portId)
-{
-    IxEthAccStatus result;
-     
-    if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
-    {
-	return (IX_ETH_ACC_FAIL);
-    }
-
-    ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER);
-    result = ixEthAccPortTxFrameAppendPaddingEnablePriv(portId);
-    ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex);
-    return result;
-}
-
-IX_ETH_ACC_PUBLIC IxEthAccStatus
-ixEthAccPortTxFrameAppendPaddingDisable(IxEthAccPortId portId)
-{
-    IxEthAccStatus result;
-
-    if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
-    {
-	return (IX_ETH_ACC_FAIL);
-    }
-
-    ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER);
-    result = ixEthAccPortTxFrameAppendPaddingDisablePriv(portId);
-    ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex);
-    return result;
-}
-
-IX_ETH_ACC_PUBLIC IxEthAccStatus
-ixEthAccPortTxFrameAppendFCSEnable(IxEthAccPortId portId)
-{
-    IxEthAccStatus result;
-
-    if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
-    {
-	return (IX_ETH_ACC_FAIL);
-    }
-
-    ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER);
-    result = ixEthAccPortTxFrameAppendFCSEnablePriv(portId);
-    ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex);
-    return result;
-}
-
-IX_ETH_ACC_PUBLIC IxEthAccStatus
-ixEthAccPortTxFrameAppendFCSDisable(IxEthAccPortId portId)
-{
-    IxEthAccStatus result;
-
-    if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
-    {
-	return (IX_ETH_ACC_FAIL);
-    }
-
-    ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER);
-    result = ixEthAccPortTxFrameAppendFCSDisablePriv(portId);
-    ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex);
-    return result;
-}
-
-IX_ETH_ACC_PUBLIC IxEthAccStatus
-ixEthAccPortRxFrameAppendFCSEnable(IxEthAccPortId portId)
-{
-    IxEthAccStatus result;
-
-    if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
-    {
-	return (IX_ETH_ACC_FAIL);
-    }
-
-    ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER);
-    result = ixEthAccPortRxFrameAppendFCSEnablePriv(portId);
-    ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex);
-    return result;
-}
-
-IX_ETH_ACC_PUBLIC IxEthAccStatus
-ixEthAccPortRxFrameAppendFCSDisable(IxEthAccPortId portId)
-{
-    IxEthAccStatus result;
-
-    if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
-    {
-	return (IX_ETH_ACC_FAIL);
-    }
-
-    ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER);
-    result = ixEthAccPortRxFrameAppendFCSDisablePriv(portId);
-    ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex);
-    return result;
-}
-
-IX_ETH_ACC_PUBLIC IxEthAccStatus
-ixEthAccTxSchedulingDisciplineSet(IxEthAccPortId portId, IxEthAccSchedulerDiscipline sched)
-{
-    IxEthAccStatus result;
-
-    if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
-    {
-	return (IX_ETH_ACC_FAIL);
-    }
-
-    ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER);
-    result = ixEthAccTxSchedulingDisciplineSetPriv(portId, sched);
-    ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex);
-    return result;
-}
-
-IX_ETH_ACC_PUBLIC IxEthAccStatus
-ixEthAccRxSchedulingDisciplineSet(IxEthAccSchedulerDiscipline sched)
-{
-    IxEthAccStatus result;
-
-    if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
-    {
-	return (IX_ETH_ACC_FAIL);
-    }
-
-    ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER);
-    result = ixEthAccRxSchedulingDisciplineSetPriv(sched);
-    ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex);
-    return result;
-}
-
-IX_ETH_ACC_PUBLIC IxEthAccStatus 
-ixEthAccPortNpeLoopbackEnable(IxEthAccPortId portId)
-{
-    IxEthAccStatus result;
-
-    if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
-    {
-	return (IX_ETH_ACC_FAIL);
-    }
-
-    ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER);
-    result = ixEthAccNpeLoopbackEnablePriv(portId);
-    ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex);
-    return result;
-}
-
-IX_ETH_ACC_PUBLIC IxEthAccStatus 
-ixEthAccPortTxEnable(IxEthAccPortId portId)
-{
-    IxEthAccStatus result;
-
-    if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
-    {
-	return (IX_ETH_ACC_FAIL);
-    }
-
-    ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER);
-    result = ixEthAccPortTxEnablePriv(portId);
-    ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex);
-    return result;
-}
-
-IX_ETH_ACC_PUBLIC IxEthAccStatus 
-ixEthAccPortRxEnable(IxEthAccPortId portId)
-{
-    IxEthAccStatus result;
-
-    if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
-    {
-	return (IX_ETH_ACC_FAIL);
-    }
-
-    ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER);
-    result = ixEthAccPortRxEnablePriv(portId);
-    ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex);
-    return result;
-}
-
-IX_ETH_ACC_PUBLIC IxEthAccStatus 
-ixEthAccPortNpeLoopbackDisable(IxEthAccPortId portId)
-{
-    IxEthAccStatus result;
-
-    if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
-    {
-	return (IX_ETH_ACC_FAIL);
-    }
-
-    ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER);
-    result = ixEthAccNpeLoopbackDisablePriv(portId);
-    ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex);
-    return result;
-}
-
-IX_ETH_ACC_PUBLIC IxEthAccStatus 
-ixEthAccPortTxDisable(IxEthAccPortId portId)
-{
-    IxEthAccStatus result;
-
-    if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
-    {
-	return (IX_ETH_ACC_FAIL);
-    }
-
-    ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER);
-    result = ixEthAccPortTxDisablePriv(portId);
-    ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex);
-    return result;
-}
-
-IX_ETH_ACC_PUBLIC IxEthAccStatus 
-ixEthAccPortRxDisable(IxEthAccPortId portId)
-{
-    IxEthAccStatus result;
-
-    if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
-    {
-	return (IX_ETH_ACC_FAIL);
-    }
-
-    ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER);
-    result = ixEthAccPortRxDisablePriv(portId);
-    ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex);
-    return result;
-}
-
-IX_ETH_ACC_PUBLIC IxEthAccStatus 
-ixEthAccPortMacReset(IxEthAccPortId portId)
-{
-    IxEthAccStatus result;
-
-    if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
-    {
-	return (IX_ETH_ACC_FAIL);
-    }
-
-    ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER);
-    result = ixEthAccPortMacResetPriv(portId);
-    ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex);
-    return result;
-}
diff --git a/arch/arm/cpu/ixp/npe/IxEthAccDataPlane.c b/arch/arm/cpu/ixp/npe/IxEthAccDataPlane.c
deleted file mode 100644
index b62f0d0..0000000
--- a/arch/arm/cpu/ixp/npe/IxEthAccDataPlane.c
+++ /dev/null
@@ -1,2483 +0,0 @@
-/**
- * @file IxEthDataPlane.c
- *
- * @author Intel Corporation
- * @date 12-Feb-2002
- *
- * @brief This file contains the implementation of the IXPxxx
- * Ethernet Access Data plane component
- *
- * Design Notes:
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
- */
-
-#include "IxNpeMh.h"
-#include "IxEthAcc.h"
-#include "IxEthDB.h"
-#include "IxOsal.h"
-#include "IxEthDBPortDefs.h"
-#include "IxFeatureCtrl.h"
-#include "IxEthAcc_p.h"
-#include "IxEthAccQueueAssign_p.h"
-
-extern PUBLIC IxEthAccMacState ixEthAccMacState[];
-extern PUBLIC UINT32 ixEthAccNewSrcMask;
-
-/**
- * private functions prototype
- */
-PRIVATE IX_OSAL_MBUF *
-ixEthAccEntryFromQConvert(UINT32 qEntry, UINT32 mask);
-
-PRIVATE UINT32
-ixEthAccMbufRxQPrepare(IX_OSAL_MBUF *mbuf);
-
-PRIVATE UINT32
-ixEthAccMbufTxQPrepare(IX_OSAL_MBUF *mbuf);
-
-PRIVATE IxEthAccStatus
-ixEthAccTxSwQHighestPriorityGet(IxEthAccPortId portId,
-				IxEthAccTxPriority *priorityPtr);
-
-PRIVATE IxEthAccStatus
-ixEthAccTxFromSwQ(IxEthAccPortId portId,
-		  IxEthAccTxPriority priority);
-
-PRIVATE IxEthAccStatus
-ixEthAccRxFreeFromSwQ(IxEthAccPortId portId);
-
-PRIVATE void
-ixEthAccMbufFromTxQ(IX_OSAL_MBUF *mbuf);
-
-PRIVATE void
-ixEthAccMbufFromRxQ(IX_OSAL_MBUF *mbuf);
-
-PRIVATE IX_STATUS
-ixEthAccQmgrLockTxWrite(IxEthAccPortId portId,
-			UINT32 qBuffer);
-
-PRIVATE IX_STATUS
-ixEthAccQmgrLockRxWrite(IxEthAccPortId portId,
-			UINT32 qBuffer);
-
-PRIVATE IX_STATUS
-ixEthAccQmgrTxWrite(IxEthAccPortId portId,
-		    UINT32 qBuffer,
-		    UINT32 priority);
-
-/**
- * @addtogroup IxEthAccPri
- *@{
- */
-
-/* increment a counter only when stats are enabled */
-#define TX_STATS_INC(port,field) \
-        IX_ETH_ACC_STATS_INC(ixEthAccPortData[port].ixEthAccTxData.stats.field)
-#define RX_STATS_INC(port,field) \
-        IX_ETH_ACC_STATS_INC(ixEthAccPortData[port].ixEthAccRxData.stats.field)
-
-/* always increment the counter (mainly used for unexpected errors) */
-#define TX_INC(port,field) \
-        ixEthAccPortData[port].ixEthAccTxData.stats.field++
-#define RX_INC(port,field) \
-        ixEthAccPortData[port].ixEthAccRxData.stats.field++
-
-PRIVATE IxEthAccDataPlaneStats     ixEthAccDataStats;
-
-extern IxEthAccPortDataInfo   ixEthAccPortData[];
-extern IxEthAccInfo   ixEthAccDataInfo;
-
-PRIVATE IxOsalFastMutex txWriteMutex[IX_ETH_ACC_NUMBER_OF_PORTS];
-PRIVATE IxOsalFastMutex rxWriteMutex[IX_ETH_ACC_NUMBER_OF_PORTS];
-
-/**
- *
- * @brief Mbuf header conversion macros : they implement the
- *  different conversions using a temporary value. They also double-check
- *  that the parameters can be converted to/from NPE format.
- *
- */
-#if defined(__wince) && !defined(IN_KERNEL)
-#define PTR_VIRT2NPE(ptrSrc,dst) \
-  do { UINT32 temp; \
-      IX_OSAL_ENSURE(sizeof(ptrSrc) == sizeof(UINT32), "Wrong parameter type"); \
-      IX_OSAL_ENSURE(sizeof(dst) == sizeof(UINT32), "Wrong parameter type"); \
-      temp = (UINT32)IX_OSAL_MBUF_MBUF_VIRTUAL_TO_PHYSICAL_TRANSLATION((IX_OSAL_MBUF*)ptrSrc); \
-      (dst) = IX_OSAL_SWAP_BE_SHARED_LONG(temp); } \
-  while(0)
-
-#define PTR_NPE2VIRT(type,src,ptrDst) \
-  do { void *temp; \
-      IX_OSAL_ENSURE(sizeof(type) == sizeof(UINT32), "Wrong parameter type"); \
-      IX_OSAL_ENSURE(sizeof(src) == sizeof(UINT32), "Wrong parameter type"); \
-      IX_OSAL_ENSURE(sizeof(ptrDst) == sizeof(UINT32), "Wrong parameter type"); \
-      temp = (void *)IX_OSAL_SWAP_BE_SHARED_LONG(src); \
-      (ptrDst) = (type)IX_OSAL_MBUF_MBUF_PHYSICAL_TO_VIRTUAL_TRANSLATION(temp); } \
-  while(0)
-#else
-#define PTR_VIRT2NPE(ptrSrc,dst) \
-  do { UINT32 temp; \
-      IX_OSAL_ENSURE(sizeof(ptrSrc) == sizeof(UINT32), "Wrong parameter type"); \
-      IX_OSAL_ENSURE(sizeof(dst) == sizeof(UINT32), "Wrong parameter type"); \
-      temp = (UINT32)IX_OSAL_MMU_VIRT_TO_PHYS(ptrSrc); \
-      (dst) = IX_OSAL_SWAP_BE_SHARED_LONG(temp); } \
-  while(0)
-
-#define PTR_NPE2VIRT(type,src,ptrDst) \
-  do { void *temp; \
-      IX_OSAL_ENSURE(sizeof(type) == sizeof(UINT32), "Wrong parameter type"); \
-      IX_OSAL_ENSURE(sizeof(src) == sizeof(UINT32), "Wrong parameter type"); \
-      IX_OSAL_ENSURE(sizeof(ptrDst) == sizeof(UINT32), "Wrong parameter type"); \
-      temp = (void *)IX_OSAL_SWAP_BE_SHARED_LONG(src); \
-      (ptrDst) = (type)IX_OSAL_MMU_PHYS_TO_VIRT(temp); } \
-  while(0)
-#endif
-
-/**
- *
- * @brief Mbuf payload pointer conversion macros : Wince has its own
- *  method to convert the buffer pointers
- */
-#if defined(__wince) && !defined(IN_KERNEL)
-#define DATAPTR_VIRT2NPE(ptrSrc,dst) \
-  do { UINT32 temp; \
-      temp = (UINT32)IX_OSAL_MBUF_DATA_VIRTUAL_TO_PHYSICAL_TRANSLATION(ptrSrc); \
-      (dst) = IX_OSAL_SWAP_BE_SHARED_LONG(temp); } \
-  while(0)
-
-#else
-#define DATAPTR_VIRT2NPE(ptrSrc,dst) PTR_VIRT2NPE(IX_OSAL_MBUF_MDATA(ptrSrc),dst)
-#endif
-
-
-/* Flush the shared part of the mbuf header */
-#define IX_ETHACC_NE_CACHE_FLUSH(mbufPtr) \
-  do { \
-      IX_OSAL_CACHE_FLUSH(IX_ETHACC_NE_SHARED(mbufPtr), \
-			      sizeof(IxEthAccNe)); \
-    } \
-  while(0)
-
-/* Invalidate the shared part of the mbuf header */
-#define IX_ETHACC_NE_CACHE_INVALIDATE(mbufPtr) \
-  do { \
-      IX_OSAL_CACHE_INVALIDATE(IX_ETHACC_NE_SHARED(mbufPtr), \
-				   sizeof(IxEthAccNe)); \
-    } \
-  while(0)
-
-/* Preload one cache line (shared mbuf headers are aligned
- * and their size is 1 cache line)
- *
- * IX_OSAL_CACHED  is defined when the mbuf headers are
- * allocated from cached memory.
- *
- * Other processor on emulation environment may not implement
- * preload function
- */
-#ifdef IX_OSAL_CACHED
-	#if (CPU!=SIMSPARCSOLARIS) && !defined (__wince)
-		#define IX_ACC_DATA_CACHE_PRELOAD(ptr) \
-		do { /* preload a cache line (Xscale Processor) */ \
-			__asm__ (" pld [%0]\n": : "r" (ptr)); \
-		} \
-		while(0)
-	#else
-		/* preload not implemented on different processor */
-		#define IX_ACC_DATA_CACHE_PRELOAD(mbufPtr) \
-		do { /* nothing */ } while (0)
-	#endif
-#else
-	/* preload not needed if cache is not enabled */
-	#define IX_ACC_DATA_CACHE_PRELOAD(mbufPtr) \
-	do { /* nothing */ } while (0)
-#endif
-
-/**
- *
- * @brief function to retrieve the correct pointer from
- * a queue entry posted by the NPE
- *
- * @param qEntry : entry from qmgr queue
- *        mask : applicable mask for this queue
- *        (4 most significant bits are used for additional informations)
- *
- * @return IX_OSAL_MBUF * pointer to mbuf header
- *
- * @internal
- */
-PRIVATE IX_OSAL_MBUF *
-ixEthAccEntryFromQConvert(UINT32 qEntry, UINT32 mask)
-{
-    IX_OSAL_MBUF *mbufPtr;
-
-    if (qEntry != 0)
-    {
-        /* mask NPE bits (e.g. priority, port ...) */
-        qEntry &= mask;
-
-#if IX_ACC_DRAM_PHYS_OFFSET != 0
-        /* restore the original address pointer (if PHYS_OFFSET is not 0) */
-        qEntry |= (IX_ACC_DRAM_PHYS_OFFSET & ~IX_ETHNPE_QM_Q_RXENET_ADDR_MASK);
-#endif
-        /* get the mbuf pointer address from the npe-shared address */
-        qEntry -= offsetof(IX_OSAL_MBUF,ix_ne);
-
-        /* phys2virt mbuf */
-        mbufPtr = (IX_OSAL_MBUF *)IX_OSAL_MMU_PHYS_TO_VIRT(qEntry);
-
-        /* preload the cacheline shared with NPE */
-        IX_ACC_DATA_CACHE_PRELOAD(IX_ETHACC_NE_SHARED(mbufPtr));
-
-        /* preload the cacheline used by xscale */
-        IX_ACC_DATA_CACHE_PRELOAD(mbufPtr);
-    }
-    else
-    {
-	mbufPtr = NULL;
-    }
-
-    return mbufPtr;
-}
-
-/* Convert the mbuf header for NPE transmission */
-PRIVATE UINT32
-ixEthAccMbufTxQPrepare(IX_OSAL_MBUF *mbuf)
-{
-    UINT32 qbuf;
-    UINT32 len;
-
-    /* endianess swap for tci and flags
-       note: this is done only once, even for chained buffers */
-    IX_ETHACC_NE_FLAGS(mbuf)   = IX_OSAL_SWAP_BE_SHARED_SHORT(IX_ETHACC_NE_FLAGS(mbuf));
-    IX_ETHACC_NE_VLANTCI(mbuf) = IX_OSAL_SWAP_BE_SHARED_SHORT(IX_ETHACC_NE_VLANTCI(mbuf));
-
-    /* test for unchained mbufs */
-    if (IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR(mbuf) == NULL)
-    {
-	/* "best case" scenario : unchained mbufs */
-	IX_ETH_ACC_STATS_INC(ixEthAccDataStats.unchainedTxMBufs);
-
-	/* payload pointer conversion */
-	DATAPTR_VIRT2NPE(mbuf, IX_ETHACC_NE_DATA(mbuf));
-
-	/* unchained mbufs : the frame length is the mbuf length
-	 * and the 2 identical lengths are stored in the same
-	 * word.
-	 */
-	len = IX_OSAL_MBUF_MLEN(mbuf);
-
-	/* set the length in both length and pktLen 16-bits fields */
-	len |= (len << IX_ETHNPE_ACC_LENGTH_OFFSET);
-	IX_ETHACC_NE_LEN(mbuf) = IX_OSAL_SWAP_BE_SHARED_LONG(len);
-
-	/* unchained mbufs : next contains 0 */
-	IX_ETHACC_NE_NEXT(mbuf) = 0;
-
-	/* flush shared header after all address conversions */
-	IX_ETHACC_NE_CACHE_FLUSH(mbuf);
-    }
-    else
-    {
-	/* chained mbufs */
-	IX_OSAL_MBUF *ptr = mbuf;
-	IX_OSAL_MBUF *nextPtr;
-	UINT32 frmLen;
-
-	/* get the frame length from the header of the first buffer */
-	frmLen = IX_OSAL_MBUF_PKT_LEN(mbuf);
-
-	do
-	{
-	    IX_ETH_ACC_STATS_INC(ixEthAccDataStats.chainedTxMBufs);
-
-	    /* payload pointer */
-	    DATAPTR_VIRT2NPE(ptr,IX_ETHACC_NE_DATA(ptr));
-	    /* Buffer length and frame length are stored in the same word */
-	    len = IX_OSAL_MBUF_MLEN(ptr);
-	    len = frmLen | (len << IX_ETHNPE_ACC_LENGTH_OFFSET);
-	    IX_ETHACC_NE_LEN(ptr) = IX_OSAL_SWAP_BE_SHARED_LONG(len);
-
-	    /* get the virtual next chain pointer */
-	    nextPtr = IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR(ptr);
-	    if (nextPtr != NULL)
-	    {
-		/* shared pointer of the next buffer is chained */
-		PTR_VIRT2NPE(IX_ETHACC_NE_SHARED(nextPtr),
-			     IX_ETHACC_NE_NEXT(ptr));
-	    }
-	    else
-	    {
-		IX_ETHACC_NE_NEXT(ptr) = 0;
-	    }
-
-	    /* flush shared header after all address conversions */
-	    IX_ETHACC_NE_CACHE_FLUSH(ptr);
-
-	    /* move to next buffer */
-	    ptr = nextPtr;
-
-	    /* the frame length field is set only in the first buffer
-	     * and is zeroed in the next buffers
-	     */
-	    frmLen = 0;
-	}
-	while(ptr != NULL);
-
-    }
-
-    /* virt2phys mbuf itself */
-    qbuf = (UINT32)IX_OSAL_MMU_VIRT_TO_PHYS(
-		  IX_ETHACC_NE_SHARED(mbuf));
-
-    /* Ensure the bits which are reserved to exchange information with
-     * the NPE are cleared
-     *
-     * If the mbuf address is not correctly aligned, or from an
-     * incompatible memory range, there is no point to continue
-     */
-    IX_OSAL_ENSURE(((qbuf & ~IX_ETHNPE_QM_Q_TXENET_ADDR_MASK) == 0),
-	      "Invalid address range");
-
-    return qbuf;
-}
-
-/* Convert the mbuf header for NPE reception */
-PRIVATE UINT32
-ixEthAccMbufRxQPrepare(IX_OSAL_MBUF *mbuf)
-{
-    UINT32 len;
-    UINT32 qbuf;
-
-    if (IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR(mbuf) == NULL)
-    {
-	/* "best case" scenario : unchained mbufs */
-	IX_ETH_ACC_STATS_INC(ixEthAccDataStats.unchainedRxFreeMBufs);
-
-	/* unchained mbufs : payload pointer */
-	DATAPTR_VIRT2NPE(mbuf, IX_ETHACC_NE_DATA(mbuf));
-
-	/* unchained mbufs : set the buffer length
-	* and the frame length field is zeroed
-	*/
-	len = (IX_OSAL_MBUF_MLEN(mbuf) << IX_ETHNPE_ACC_LENGTH_OFFSET);
-	IX_ETHACC_NE_LEN(mbuf) = IX_OSAL_SWAP_BE_SHARED_LONG(len);
-
-	/* unchained mbufs : next pointer is null */
-	IX_ETHACC_NE_NEXT(mbuf) = 0;
-
-	/* flush shared header after all address conversions */
-	IX_ETHACC_NE_CACHE_FLUSH(mbuf);
-
-	/* remove shared header cache line */
-	IX_ETHACC_NE_CACHE_INVALIDATE(mbuf);
-    }
-    else
-    {
-	/* chained mbufs */
-	IX_OSAL_MBUF *ptr = mbuf;
-	IX_OSAL_MBUF *nextPtr;
-
-	do
-	{
-	    /* chained mbufs */
-	    IX_ETH_ACC_STATS_INC(ixEthAccDataStats.chainedRxFreeMBufs);
-
-	    /* we must save virtual next chain pointer */
-	    nextPtr = IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR(ptr);
-
-	    if (nextPtr != NULL)
-	    {
-		/* chaining pointer for NPE */
-		PTR_VIRT2NPE(IX_ETHACC_NE_SHARED(nextPtr),
-			     IX_ETHACC_NE_NEXT(ptr));
-	    }
-	    else
-	    {
-		IX_ETHACC_NE_NEXT(ptr) = 0;
-	    }
-
-	    /* payload pointer */
-	    DATAPTR_VIRT2NPE(ptr,IX_ETHACC_NE_DATA(ptr));
-
-	    /* buffer length */
-	    len = (IX_OSAL_MBUF_MLEN(ptr) << IX_ETHNPE_ACC_LENGTH_OFFSET);
-	    IX_ETHACC_NE_LEN(ptr) = IX_OSAL_SWAP_BE_SHARED_LONG(len);
-
-	    /* flush shared header after all address conversions */
-	    IX_ETHACC_NE_CACHE_FLUSH(ptr);
-
-	    /* remove shared header cache line */
-	    IX_ETHACC_NE_CACHE_INVALIDATE(ptr);
-
-	    /* next mbuf in the chain */
-	    ptr = nextPtr;
-	}
-	while(ptr != NULL);
-    }
-
-    /* virt2phys mbuf itself */
-    qbuf = (UINT32)IX_OSAL_MMU_VIRT_TO_PHYS(
-		  IX_ETHACC_NE_SHARED(mbuf));
-
-    /* Ensure the bits which are reserved to exchange information with
-     * the NPE are cleared
-     *
-     * If the mbuf address is not correctly aligned, or from an
-     * incompatible memory range, there is no point to continue
-     */
-    IX_OSAL_ENSURE(((qbuf & ~IX_ETHNPE_QM_Q_RXENET_ADDR_MASK) == 0),
-	      "Invalid address range");
-
-    return qbuf;
-}
-
-/* Convert the mbuf header after NPE transmission
- * Since there is nothing changed by the NPE, there is no need
- * to process anything but the update of internal stats
- * when they are enabled
-*/
-PRIVATE void
-ixEthAccMbufFromTxQ(IX_OSAL_MBUF *mbuf)
-{
-#ifndef NDEBUG
-    /* test for unchained mbufs */
-    if (IX_ETHACC_NE_NEXT(mbuf) == 0)
-    {
-	/* unchained mbufs : update the stats */
-	IX_ETH_ACC_STATS_INC(ixEthAccDataStats.unchainedTxDoneMBufs);
-    }
-    else
-    {
-	/* chained mbufs : walk the chain and update the stats */
-	IX_OSAL_MBUF *ptr = mbuf;
-
-	do
-	{
-	    IX_ETH_ACC_STATS_INC(ixEthAccDataStats.chainedTxDoneMBufs);
-	    ptr = IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR(ptr);
-	}
-	while (ptr != NULL);
-    }
-#endif
-}
-
-/* Convert the mbuf header after NPE reception */
-PRIVATE void
-ixEthAccMbufFromRxQ(IX_OSAL_MBUF *mbuf)
-{
-    UINT32 len;
-
-    /* endianess swap for tci and flags
-       note: this is done only once, even for chained buffers */
-    IX_ETHACC_NE_FLAGS(mbuf)   = IX_OSAL_SWAP_BE_SHARED_SHORT(IX_ETHACC_NE_FLAGS(mbuf));
-    IX_ETHACC_NE_VLANTCI(mbuf) = IX_OSAL_SWAP_BE_SHARED_SHORT(IX_ETHACC_NE_VLANTCI(mbuf));
-
-    /* test for unchained mbufs */
-    if (IX_ETHACC_NE_NEXT(mbuf) == 0)
-    {
-	/* unchained mbufs */
-	IX_ETH_ACC_STATS_INC(ixEthAccDataStats.unchainedRxMBufs);
-
-	/* get the frame length. it is the same than the buffer length */
-	len = IX_OSAL_SWAP_BE_SHARED_LONG(IX_ETHACC_NE_LEN(mbuf));
-	len &= IX_ETHNPE_ACC_PKTLENGTH_MASK;
-	IX_OSAL_MBUF_PKT_LEN(mbuf) = IX_OSAL_MBUF_MLEN(mbuf) = len;
-
-        /* clears the next packet field */
-	IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR(mbuf) = NULL;
-    }
-    else
-    {
-	IX_OSAL_MBUF *ptr = mbuf;
-	IX_OSAL_MBUF *nextPtr;
-	UINT32 frmLen;
-
-	/* convert the frame length */
-	frmLen = IX_OSAL_SWAP_BE_SHARED_LONG(IX_ETHACC_NE_LEN(mbuf));
-	IX_OSAL_MBUF_PKT_LEN(mbuf) = (frmLen & IX_ETHNPE_ACC_PKTLENGTH_MASK);
-
-        /* chained mbufs */
-	do
-	{
-	    IX_ETH_ACC_STATS_INC(ixEthAccDataStats.chainedRxMBufs);
-
-	    /* convert the length */
-	    len = IX_OSAL_SWAP_BE_SHARED_LONG(IX_ETHACC_NE_LEN(ptr));
-	    IX_OSAL_MBUF_MLEN(ptr) = (len >> IX_ETHNPE_ACC_LENGTH_OFFSET);
-
-            /* get the next pointer */
-	    PTR_NPE2VIRT(IX_OSAL_MBUF *,IX_ETHACC_NE_NEXT(ptr), nextPtr);
-	    if (nextPtr != NULL)
-	    {
-		nextPtr = (IX_OSAL_MBUF *)((UINT8 *)nextPtr - offsetof(IX_OSAL_MBUF,ix_ne));
-	    }
-	    /* set the next pointer */
-	    IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR(ptr) = nextPtr;
-
-	    /* move to the next buffer */
-	    ptr = nextPtr;
-	}
-	while (ptr != NULL);
-    }
-}
-
-/* write to qmgr if possible and report an overflow if not possible
- * Use a fast lock to protect the queue write.
- * This way, the tx feature is reentrant.
- */
-PRIVATE IX_STATUS
-ixEthAccQmgrLockTxWrite(IxEthAccPortId portId, UINT32 qBuffer)
-{
-    IX_STATUS qStatus;
-    if (ixOsalFastMutexTryLock(&txWriteMutex[portId]) == IX_SUCCESS)
-    {
-	qStatus = ixQMgrQWrite(
-	       IX_ETH_ACC_PORT_TO_TX_Q_ID(portId),
-	       &qBuffer);
-#ifndef NDEBUG
-	if (qStatus != IX_SUCCESS)
-	{
-	    TX_STATS_INC(portId, txOverflow);
-	}
-#endif
-	ixOsalFastMutexUnlock(&txWriteMutex[portId]);
-    }
-    else
-    {
-	TX_STATS_INC(portId, txLock);
-	qStatus = IX_QMGR_Q_OVERFLOW;
-    }
-    return qStatus;
-}
-
-/* write to qmgr if possible and report an overflow if not possible
- * Use a fast lock to protect the queue write.
- * This way, the Rx feature is reentrant.
- */
-PRIVATE IX_STATUS
-ixEthAccQmgrLockRxWrite(IxEthAccPortId portId, UINT32 qBuffer)
-{
-    IX_STATUS qStatus;
-    if (ixOsalFastMutexTryLock(&rxWriteMutex[portId]) == IX_SUCCESS)
-    {
-	qStatus = ixQMgrQWrite(
-	       IX_ETH_ACC_PORT_TO_RX_FREE_Q_ID(portId),
-	       &qBuffer);
-#ifndef NDEBUG
-	if (qStatus != IX_SUCCESS)
-	{
-	    RX_STATS_INC(portId, rxFreeOverflow);
-	}
-#endif
-	ixOsalFastMutexUnlock(&rxWriteMutex[portId]);
-    }
-    else
-    {
-	RX_STATS_INC(portId, rxFreeLock);
-	qStatus = IX_QMGR_Q_OVERFLOW;
-    }
-    return qStatus;
-}
-
-/*
- * Set the priority and write to a qmgr queue.
- */
-PRIVATE IX_STATUS
-ixEthAccQmgrTxWrite(IxEthAccPortId portId, UINT32 qBuffer, UINT32 priority)
-{
-    /* fill the priority field */
-    qBuffer |= (priority << IX_ETHNPE_QM_Q_FIELD_PRIOR_R);
-
-    return ixEthAccQmgrLockTxWrite(portId, qBuffer);
-}
-
-/**
- *
- * @brief This function will discover the highest priority S/W Tx Q that
- *        has entries in it
- *
- * @param portId - (in) the id of the port whose S/W Tx queues are to be searched
- *        priorityPtr - (out) the priority of the highest priority occupied q will be written
- *                      here
- *
- * @return IX_ETH_ACC_SUCCESS if an occupied Q is found
- *         IX_ETH_ACC_FAIL if no Q has entries
- *
- * @internal
- */
-PRIVATE IxEthAccStatus
-ixEthAccTxSwQHighestPriorityGet(IxEthAccPortId portId,
-				IxEthAccTxPriority *priorityPtr)
-{
-    if (ixEthAccPortData[portId].ixEthAccTxData.schDiscipline
-	== FIFO_NO_PRIORITY)
-    {
-	if(IX_ETH_ACC_DATAPLANE_IS_Q_EMPTY(ixEthAccPortData[portId].
-	       ixEthAccTxData.txQ[IX_ETH_ACC_TX_DEFAULT_PRIORITY]))
-	{
-	    return IX_ETH_ACC_FAIL;
-	}
-	else
-	{
-	    *priorityPtr = IX_ETH_ACC_TX_DEFAULT_PRIORITY;
-	    TX_STATS_INC(portId,txPriority[*priorityPtr]);
-	    return IX_ETH_ACC_SUCCESS;
-	}
-    }
-    else
-    {
-	IxEthAccTxPriority highestPriority = IX_ETH_ACC_TX_PRIORITY_7;
-	while(1)
-	{
-	    if(!IX_ETH_ACC_DATAPLANE_IS_Q_EMPTY(ixEthAccPortData[portId].
-	       ixEthAccTxData.txQ[highestPriority]))
-	    {
-
-		*priorityPtr = highestPriority;
-		TX_STATS_INC(portId,txPriority[highestPriority]);
-		return IX_ETH_ACC_SUCCESS;
-
-	    }
-	    if (highestPriority == IX_ETH_ACC_TX_PRIORITY_0)
-	    {
-		return IX_ETH_ACC_FAIL;
-	    }
-	    highestPriority--;
-	}
-    }
-}
-
-/**
- *
- * @brief This function will take a buffer from a TX S/W Q and attempt
- *        to add it to the relevant TX H/W Q
- *
- * @param portId - the port whose TX queue is to be written to
- *        priority - identifies the queue from which the entry is to be read
- *
- * @internal
- */
-PRIVATE IxEthAccStatus
-ixEthAccTxFromSwQ(IxEthAccPortId portId,
-		  IxEthAccTxPriority priority)
-{
-    IX_OSAL_MBUF        *mbuf;
-    IX_STATUS	   qStatus;
-
-    IX_OSAL_ENSURE((UINT32)priority <= (UINT32)7, "Invalid priority");
-
-    IX_ETH_ACC_DATAPLANE_REMOVE_MBUF_FROM_Q_HEAD(
-	ixEthAccPortData[portId].ixEthAccTxData.txQ[priority],
-	mbuf);
-
-    if (mbuf != NULL)
-    {
-	/*
-	 * Add the Tx buffer to the H/W Tx Q
-	 * We do not need to flush here as it is already done
-	 * in TxFrameSubmit().
-	 */
-	qStatus = ixEthAccQmgrTxWrite(
-	      portId,
-	      IX_OSAL_MMU_VIRT_TO_PHYS((UINT32)IX_ETHACC_NE_SHARED(mbuf)),
-	      priority);
-
-	if (qStatus == IX_SUCCESS)
-	{
-	    TX_STATS_INC(portId,txFromSwQOK);
-	    return IX_SUCCESS;
-	}
-	else if (qStatus == IX_QMGR_Q_OVERFLOW)
-	{
-	    /*
-	     * H/W Q overflow, need to save the buffer
-	     * back on the s/w Q.
-	     * we must put it back on the head of the q to avoid
-	     * reordering packet tx
-	     */
-	    TX_STATS_INC(portId,txFromSwQDelayed);
-	    IX_ETH_ACC_DATAPLANE_ADD_MBUF_TO_Q_HEAD(
-		ixEthAccPortData[portId].ixEthAccTxData.txQ[priority],
-		mbuf);
-
-	    /*enable Q notification*/
-	    qStatus = ixQMgrNotificationEnable(
-		IX_ETH_ACC_PORT_TO_TX_Q_ID(portId),
-		IX_ETH_ACC_PORT_TO_TX_Q_SOURCE(portId));
-
-            if (qStatus != IX_SUCCESS && qStatus != IX_QMGR_WARNING)
-            {
-		TX_INC(portId,txUnexpectedError);
-		IX_ETH_ACC_FATAL_LOG(
-	            "ixEthAccTxFromSwQ:Unexpected Error: %u\n",
-	            qStatus, 0, 0, 0, 0, 0);
-            }
-	}
-	else
-	{
-	    TX_INC(portId,txUnexpectedError);
-
-	    /* recovery attempt */
-	    IX_ETH_ACC_DATAPLANE_ADD_MBUF_TO_Q_HEAD(
-		ixEthAccPortData[portId].ixEthAccTxData.txQ[priority],
-		mbuf);
-
-	    IX_ETH_ACC_FATAL_LOG(
-		"ixEthAccTxFromSwQ:Error: unexpected QM status 0x%08X\n",
-		qStatus, 0, 0, 0, 0, 0);
-	}
-    }
-    else
-    {
-	/* sw queue is empty */
-    }
-    return IX_ETH_ACC_FAIL;
-}
-
-/**
- *
- * @brief This function will take a buffer from a RXfree S/W Q and attempt
- *        to add it to the relevant RxFree H/W Q
- *
- * @param portId - the port whose RXFree queue is to be written to
- *
- * @internal
- */
-PRIVATE IxEthAccStatus
-ixEthAccRxFreeFromSwQ(IxEthAccPortId portId)
-{
-    IX_OSAL_MBUF        *mbuf;
-    IX_STATUS	   qStatus = IX_SUCCESS;
-
-    IX_ETH_ACC_DATAPLANE_REMOVE_MBUF_FROM_Q_HEAD(
-	  ixEthAccPortData[portId].ixEthAccRxData.freeBufferList,
-	  mbuf);
-    if (mbuf != NULL)
-    {
-	/*
-	 * Add The Rx Buffer to the H/W Free buffer Q if possible
-	 */
-	qStatus = ixEthAccQmgrLockRxWrite(portId,
-		  IX_OSAL_MMU_VIRT_TO_PHYS(
-			 (UINT32)IX_ETHACC_NE_SHARED(mbuf)));
-
-	if (qStatus == IX_SUCCESS)
-	{
-	    RX_STATS_INC(portId,rxFreeRepFromSwQOK);
-	    /*
-	     * Buffer added to h/w Q.
-	     */
-	    return IX_SUCCESS;
-	}
-	else if (qStatus == IX_QMGR_Q_OVERFLOW)
-	{
-	    /*
-	     * H/W Q overflow, need to save the buffer back on the s/w Q.
-	     */
-	    RX_STATS_INC(portId,rxFreeRepFromSwQDelayed);
-
-	    IX_ETH_ACC_DATAPLANE_ADD_MBUF_TO_Q_HEAD(
-		   ixEthAccPortData[portId].ixEthAccRxData.freeBufferList,
-		   mbuf);
-	}
-	else
-	{
-	    /* unexpected qmgr error */
-	    RX_INC(portId,rxUnexpectedError);
-
-	    IX_ETH_ACC_DATAPLANE_ADD_MBUF_TO_Q_HEAD(
-		    ixEthAccPortData[portId].ixEthAccRxData.freeBufferList,
-		    mbuf);
-
-	    IX_ETH_ACC_FATAL_LOG("IxEthAccRxFreeFromSwQ:Error: unexpected QM status 0x%08X\n",
-				 qStatus, 0, 0, 0, 0, 0);
-	}
-    }
-    else
-    {
-	/* sw queue is empty */
-    }
-    return IX_ETH_ACC_FAIL;
-}
-
-
-IX_ETH_ACC_PUBLIC
-IxEthAccStatus ixEthAccInitDataPlane()
-{
-    UINT32 portId;
-
-    /*
-     * Initialize the service and register callback to other services.
-     */
-
-    IX_ETH_ACC_MEMSET(&ixEthAccDataStats,
-		      0,
-		      sizeof(ixEthAccDataStats));
-
-    for(portId=0; portId < IX_ETH_ACC_NUMBER_OF_PORTS; portId++)
-    {
-	ixOsalFastMutexInit(&txWriteMutex[portId]);
-	ixOsalFastMutexInit(&rxWriteMutex[portId]);
-
-	IX_ETH_ACC_MEMSET(&ixEthAccPortData[portId],
-			  0,
-			  sizeof(ixEthAccPortData[portId]));
-
-	ixEthAccPortData[portId].ixEthAccTxData.schDiscipline = FIFO_NO_PRIORITY;
-    }
-
-    return (IX_ETH_ACC_SUCCESS);
-}
-
-
-IX_ETH_ACC_PUBLIC
-IxEthAccStatus ixEthAccPortTxDoneCallbackRegister(IxEthAccPortId portId,
-						  IxEthAccPortTxDoneCallback
-						  txCallbackFn,
-						  UINT32 callbackTag)
-{
-    if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
-    {
-	return (IX_ETH_ACC_FAIL);
-    }
-    if (!IX_ETH_ACC_IS_PORT_VALID(portId))
-    {
-	return (IX_ETH_ACC_INVALID_PORT);
-    }
-
-/* HACK: removing this code to enable NPE-A preliminary testing
- *    if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
- *    {
- *        IX_ETH_ACC_WARNING_LOG("ixEthAccPortTxDoneCallbackRegister: Unavailable Eth %d: Cannot register TxDone Callback.\n",(INT32)portId,0,0,0,0,0);
- *        return IX_ETH_ACC_SUCCESS ;
- *    }
- */
-
-    if (!IX_ETH_IS_PORT_INITIALIZED(portId))
-    {
-	return (IX_ETH_ACC_PORT_UNINITIALIZED);
-    }
-    if (txCallbackFn == 0)
-	/* Check for null function pointer here. */
-    {
-	return (IX_ETH_ACC_INVALID_ARG);
-    }
-    ixEthAccPortData[portId].ixEthAccTxData.txBufferDoneCallbackFn = txCallbackFn;
-    ixEthAccPortData[portId].ixEthAccTxData.txCallbackTag = callbackTag;
-    return (IX_ETH_ACC_SUCCESS);
-}
-
-
-IX_ETH_ACC_PUBLIC
-IxEthAccStatus ixEthAccPortRxCallbackRegister(IxEthAccPortId portId,
-					      IxEthAccPortRxCallback
-					      rxCallbackFn,
-					      UINT32 callbackTag)
-{
-    IxEthAccPortId port;
-
-    if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
-    {
-	return (IX_ETH_ACC_FAIL);
-    }
-    if (!IX_ETH_ACC_IS_PORT_VALID(portId))
-    {
-	return (IX_ETH_ACC_INVALID_PORT);
-    }
-
-    if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
-    {
-        IX_ETH_ACC_WARNING_LOG("ixEthAccPortRxCallbackRegister: Unavailable Eth %d: Cannot register Rx Callback.\n",(INT32)portId,0,0,0,0,0);
-        return IX_ETH_ACC_SUCCESS ;
-    }
-
-    if (!IX_ETH_IS_PORT_INITIALIZED(portId))
-    {
-	return (IX_ETH_ACC_PORT_UNINITIALIZED);
-    }
-
-    /* Check for null function pointer here. */
-    if (rxCallbackFn == NULL)
-    {
-	return (IX_ETH_ACC_INVALID_ARG);
-    }
-
-    /* Check the user is not changing the callback type
-     * when the port is enabled.
-    */
-    if (ixEthAccMacState[portId].portDisableState == ACTIVE)
-    {
-	for (port = 0; port < IX_ETH_ACC_NUMBER_OF_PORTS; port++)
-	{
-	    if ((ixEthAccMacState[port].portDisableState == ACTIVE)
-		&& (ixEthAccPortData[port].ixEthAccRxData.rxMultiBufferCallbackInUse == TRUE))
-	    {
-		/* one of the active ports has a different rx callback type.
-		 * Changing the callback type when the port is enabled
-		 * is not safe
-		 */
-		return (IX_ETH_ACC_INVALID_ARG);
-	    }
-	}
-    }
-
-    /* update the callback pointer : this is done before
-     * registering the new qmgr callback
-     */
-    ixEthAccPortData[portId].ixEthAccRxData.rxCallbackFn = rxCallbackFn;
-    ixEthAccPortData[portId].ixEthAccRxData.rxCallbackTag = callbackTag;
-
-    /* update the qmgr callback for rx queues */
-    if (ixEthAccQMgrRxCallbacksRegister(ixEthRxFrameQMCallback)
-	!= IX_ETH_ACC_SUCCESS)
-    {
-	/* unexpected qmgr error */
-        IX_ETH_ACC_FATAL_LOG("ixEthAccPortRxCallbackRegister: unexpected QMgr error, " \
-            "could not register Rx single-buffer callback\n", 0, 0, 0, 0, 0, 0);
-
-	RX_INC(portId,rxUnexpectedError);
-	return (IX_ETH_ACC_INVALID_ARG);
-    }
-
-    ixEthAccPortData[portId].ixEthAccRxData.rxMultiBufferCallbackInUse = FALSE;
-
-    return (IX_ETH_ACC_SUCCESS);
-}
-
-IX_ETH_ACC_PUBLIC
-IxEthAccStatus ixEthAccPortMultiBufferRxCallbackRegister(
-			 IxEthAccPortId portId,
-			 IxEthAccPortMultiBufferRxCallback
-			 rxCallbackFn,
-			 UINT32 callbackTag)
-{
-    IxEthAccPortId port;
-
-    if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
-    {
-	return (IX_ETH_ACC_FAIL);
-    }
-    if (!IX_ETH_ACC_IS_PORT_VALID(portId))
-    {
-	return (IX_ETH_ACC_INVALID_PORT);
-    }
-
-    if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
-    {
-        IX_ETH_ACC_WARNING_LOG("ixEthAccPortMultiBufferRxCallbackRegister: Unavailable Eth %d: Cannot register Rx Callback.\n",(INT32)portId,0,0,0,0,0);
-        return IX_ETH_ACC_SUCCESS ;
-    }
-
-    if (!IX_ETH_IS_PORT_INITIALIZED(portId))
-    {
-	return (IX_ETH_ACC_PORT_UNINITIALIZED);
-    }
-
-    /* Check for null function pointer here. */
-    if (rxCallbackFn == NULL)
-    {
-	return (IX_ETH_ACC_INVALID_ARG);
-    }
-
-    /* Check the user is not changing the callback type
-     * when the port is enabled.
-    */
-    if (ixEthAccMacState[portId].portDisableState == ACTIVE)
-    {
-	for (port = 0; port < IX_ETH_ACC_NUMBER_OF_PORTS; port++)
-	{
-	    if ((ixEthAccMacState[port].portDisableState == ACTIVE)
-		&& (ixEthAccPortData[port].ixEthAccRxData.rxMultiBufferCallbackInUse == FALSE))
-	    {
-		/* one of the active ports has a different rx callback type.
-		 * Changing the callback type when the port is enabled
-		 * is not safe
-		 */
-		return (IX_ETH_ACC_INVALID_ARG);
-	    }
-	}
-    }
-
-    /* update the callback pointer : this is done before
-     * registering the new qmgr callback
-     */
-    ixEthAccPortData[portId].ixEthAccRxData.rxMultiBufferCallbackFn = rxCallbackFn;
-    ixEthAccPortData[portId].ixEthAccRxData.rxMultiBufferCallbackTag = callbackTag;
-
-    /* update the qmgr callback for rx queues */
-    if (ixEthAccQMgrRxCallbacksRegister(ixEthRxMultiBufferQMCallback)
-	!= IX_ETH_ACC_SUCCESS)
-    {
-	/* unexpected qmgr error */
-	RX_INC(portId,rxUnexpectedError);
-
-        IX_ETH_ACC_FATAL_LOG("ixEthAccPortMultiBufferRxCallbackRegister: unexpected QMgr error, " \
-            "could not register Rx multi-buffer callback\n", 0, 0, 0, 0, 0, 0);
-
-	return (IX_ETH_ACC_INVALID_ARG);
-    }
-
-    ixEthAccPortData[portId].ixEthAccRxData.rxMultiBufferCallbackInUse = TRUE;
-
-    return (IX_ETH_ACC_SUCCESS);
-}
-
-IX_ETH_ACC_PUBLIC
-IxEthAccStatus ixEthAccPortTxFrameSubmit(IxEthAccPortId portId,
-					 IX_OSAL_MBUF *buffer,
-					 IxEthAccTxPriority priority)
-{
-    IX_STATUS	qStatus = IX_SUCCESS;
-    UINT32      qBuffer;
-    IxEthAccTxPriority highestPriority;
-    IxQMgrQStatus txQStatus;
-
-#ifndef NDEBUG
-    if (buffer == NULL)
-    {
-	return (IX_ETH_ACC_FAIL);
-    }
-    if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
-    {
-	return (IX_ETH_ACC_FAIL);
-    }
-    if (!IX_ETH_ACC_IS_PORT_VALID(portId))
-    {
-	return (IX_ETH_ACC_INVALID_PORT);
-    }
-
-    if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
-    {
-        IX_ETH_ACC_FATAL_LOG("ixEthAccPortTxFrameSubmit: Unavailable Eth %d: Cannot submit Tx Frame.\n",
-			     (INT32)portId,0,0,0,0,0);
-        return IX_ETH_ACC_PORT_UNINITIALIZED ;
-    }
-
-    if (!IX_ETH_IS_PORT_INITIALIZED(portId))
-    {
-	return (IX_ETH_ACC_PORT_UNINITIALIZED);
-    }
-    if ((UINT32)priority > (UINT32)IX_ETH_ACC_TX_PRIORITY_7)
-    {
-	return (IX_ETH_ACC_INVALID_ARG);
-    }
-#endif
-
-    /*
-     * Need to Flush the MBUF and its contents (data) as it may be
-     * read from the NPE. Convert virtual addresses to physical addresses also.
-     */
-    qBuffer = ixEthAccMbufTxQPrepare(buffer);
-
-    /*
-     * If no fifo priority set on Xscale ...
-     */
-    if (ixEthAccPortData[portId].ixEthAccTxData.schDiscipline ==
-	FIFO_NO_PRIORITY)
-    {
-	/*
-	 * Add The Tx Buffer to the H/W Tx Q if possible
-	 * (the priority is passed to the NPE, because
-	 * the NPE is able to reorder the frames
-	 * before transmission to the underlying hardware)
-	 */
-	qStatus = ixEthAccQmgrTxWrite(portId,
-				      qBuffer,
-				      IX_ETH_ACC_TX_DEFAULT_PRIORITY);
-
-	if (qStatus == IX_SUCCESS)
-	{
-	    TX_STATS_INC(portId,txQOK);
-
-	    /*
-	     * "best case" scenario : Buffer added to h/w Q.
-	     */
-	    return (IX_SUCCESS);
-	}
-	else if (qStatus == IX_QMGR_Q_OVERFLOW)
-	{
-	    /*
-	     * We were unable to write the buffer to the
-	     * appropriate H/W Q,  Save it in the sw Q.
-	     * (use the default priority queue regardless of
-	     * input parameter)
-	     */
-	    priority = IX_ETH_ACC_TX_DEFAULT_PRIORITY;
-	}
-	else
-	{
-	    /* unexpected qmgr error */
-	    TX_INC(portId,txUnexpectedError);
-	    IX_ETH_ACC_FATAL_LOG(
-		"ixEthAccPortTxFrameSubmit:Error: qStatus = %u\n",
-		(UINT32)qStatus, 0, 0, 0, 0, 0);
-	    return (IX_ETH_ACC_FAIL);
-	}
-    }
-    else if (ixEthAccPortData[portId].ixEthAccTxData.schDiscipline ==
-	     FIFO_PRIORITY)
-    {
-
-	/*
-	 * For priority transmission, put the frame directly on the H/W queue
-	 * if the H/W queue is empty, otherwise, put it in a S/W Q
-	 */
-	ixQMgrQStatusGet(IX_ETH_ACC_PORT_TO_TX_Q_ID(portId), &txQStatus);
-	if((txQStatus & IX_QMGR_Q_STATUS_E_BIT_MASK) != 0)
-	{
-	    /*The tx queue is empty, check whether there are buffers on the s/w queues*/
-	    if(ixEthAccTxSwQHighestPriorityGet(portId,  &highestPriority)
-	       !=IX_ETH_ACC_FAIL)
-	    {
-		/*there are buffers on the s/w queues, submit them*/
-		ixEthAccTxFromSwQ(portId, highestPriority);
-
-		/* the queue was empty, 1 buffer is already supplied
-		 * but is likely to be immediately transmitted and the
-		 * hw queue is likely to be empty again, so submit
-		 * more from the sw queues
-		 */
-		if(ixEthAccTxSwQHighestPriorityGet(portId,  &highestPriority)
-		   !=IX_ETH_ACC_FAIL)
-		{
-		    ixEthAccTxFromSwQ(portId, highestPriority);
-		    /*
-		     * and force the buffer supplied to be placed
-		     * on a priority queue
-		     */
-		    qStatus = IX_QMGR_Q_OVERFLOW;
-		}
-		else
-		{
-		    /*there are no buffers in the s/w queues, submit directly*/
-		    qStatus = ixEthAccQmgrTxWrite(portId, qBuffer, priority);
-		}
-	    }
-	    else
-	    {
-		/*there are no buffers in the s/w queues, submit directly*/
-		qStatus = ixEthAccQmgrTxWrite(portId, qBuffer, priority);
-	    }
-	}
-	else
-	{
-	    qStatus = IX_QMGR_Q_OVERFLOW;
-	}
-    }
-    else
-    {
-	TX_INC(portId,txUnexpectedError);
-	IX_ETH_ACC_FATAL_LOG(
-	    "ixEthAccPortTxFrameSubmit:Error: wrong schedule discipline setup\n",
-	    0, 0, 0, 0, 0, 0);
-	return (IX_ETH_ACC_FAIL);
-    }
-
-    if(qStatus == IX_SUCCESS )
-    {
-	TX_STATS_INC(portId,txQOK);
-	return IX_ETH_ACC_SUCCESS;
-    }
-    else if(qStatus == IX_QMGR_Q_OVERFLOW)
-    {
-	TX_STATS_INC(portId,txQDelayed);
-	/*
-	 * We were unable to write the buffer to the
-	 * appropriate H/W Q,  Save it in a s/w Q.
-	 */
-	IX_ETH_ACC_DATAPLANE_ADD_MBUF_TO_Q_TAIL(
-		ixEthAccPortData[portId].
-		ixEthAccTxData.txQ[priority],
-		buffer);
-
-	qStatus = ixQMgrNotificationEnable(
-		IX_ETH_ACC_PORT_TO_TX_Q_ID(portId),
-		IX_ETH_ACC_PORT_TO_TX_Q_SOURCE(portId));
-
-        if (qStatus != IX_SUCCESS)
-	{
-	    if (qStatus == IX_QMGR_WARNING)
-	    {
-		/* notification is enabled for a queue
-		 * which is already empty (the condition is already met)
-		 * and there will be no more queue event to drain the sw queue
-		 */
-		TX_STATS_INC(portId,txLateNotificationEnabled);
-
-		/* pull a buffer from the sw queue */
-		if(ixEthAccTxSwQHighestPriorityGet(portId,  &highestPriority)
-		   !=IX_ETH_ACC_FAIL)
-		{
-		    /*there are buffers on the s/w queues, submit from them*/
-		    ixEthAccTxFromSwQ(portId, highestPriority);
-		}
-	    }
-	    else
-	    {
-		TX_INC(portId,txUnexpectedError);
-		IX_ETH_ACC_FATAL_LOG(
-		     "ixEthAccPortTxFrameSubmit: unexpected Error: %u\n",
-		     qStatus, 0, 0, 0, 0, 0);
-	    }
-        }
-    }
-    else
-    {
-	TX_INC(portId,txUnexpectedError);
-	IX_ETH_ACC_FATAL_LOG(
-	     "ixEthAccPortTxFrameSubmit: unexpected Error: %u\n",
-	     qStatus, 0, 0, 0, 0, 0);
-	return (IX_ETH_ACC_FAIL);
-    }
-
-    return (IX_ETH_ACC_SUCCESS);
-}
-
-
-/**
- *
- * @brief replenish: convert a chain of mbufs to the format
- *        expected by the NPE
- *
-  */
-
-IX_ETH_ACC_PUBLIC
-IxEthAccStatus ixEthAccPortRxFreeReplenish(IxEthAccPortId portId,
-					   IX_OSAL_MBUF *buffer)
-{
-    IX_STATUS	qStatus = IX_SUCCESS;
-    UINT32      qBuffer;
-
-    /*
-     * Check buffer is valid.
-     */
-
-#ifndef NDEBUG
-    /* check parameter value */
-    if (buffer == 0)
-    {
-	return (IX_ETH_ACC_FAIL);
-    }
-    if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
-    {
-	return (IX_ETH_ACC_FAIL);
-    }
-    if (!IX_ETH_ACC_IS_PORT_VALID(portId))
-    {
-	return (IX_ETH_ACC_INVALID_PORT);
-    }
-
-    /* check initialisation is done */
-    if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
-    {
-        IX_ETH_ACC_FATAL_LOG(" ixEthAccPortRxFreeReplenish: Unavailable Eth %d: Cannot replenish Rx Free Q.\n",(INT32)portId,0,0,0,0,0);
-        return IX_ETH_ACC_PORT_UNINITIALIZED ;
-    }
-
-    if (!IX_ETH_IS_PORT_INITIALIZED(portId))
-    {
-	return (IX_ETH_ACC_PORT_UNINITIALIZED);
-    }
-    /* check boundaries and constraints */
-    if (IX_OSAL_MBUF_MLEN(buffer) < IX_ETHNPE_ACC_RXFREE_BUFFER_LENGTH_MIN)
-    {
-	return (IX_ETH_ACC_FAIL);
-    }
-#endif
-
-    qBuffer = ixEthAccMbufRxQPrepare(buffer);
-
-    /*
-     * Add The Rx Buffer to the H/W Free buffer Q if possible
-     */
-    qStatus = ixEthAccQmgrLockRxWrite(portId, qBuffer);
-
-    if (qStatus == IX_SUCCESS)
-    {
-	RX_STATS_INC(portId,rxFreeRepOK);
-	/*
-	 * Buffer added to h/w Q.
-	 */
-	return (IX_SUCCESS);
-    }
-    else if (qStatus == IX_QMGR_Q_OVERFLOW)
-    {
-	RX_STATS_INC(portId,rxFreeRepDelayed);
-	/*
-	 * We were unable to write the buffer to the approprate H/W Q,
-	 * Save it in a s/w Q.
-	 */
-	IX_ETH_ACC_DATAPLANE_ADD_MBUF_TO_Q_TAIL(
-	    ixEthAccPortData[portId].ixEthAccRxData.freeBufferList,
-	    buffer);
-
-	qStatus = ixQMgrNotificationEnable(
-	    IX_ETH_ACC_PORT_TO_RX_FREE_Q_ID(portId),
-	    IX_ETH_ACC_PORT_TO_RX_FREE_Q_SOURCE(portId));
-
-        if (qStatus != IX_SUCCESS)
-	{
-	    if (qStatus == IX_QMGR_WARNING)
-	    {
-		/* notification is enabled for a queue
-		 * which is already empty (the condition is already met)
-		 * and there will be no more queue event to drain the sw queue
-		 * move an entry from the sw queue to the hw queue */
-		RX_STATS_INC(portId,rxFreeLateNotificationEnabled);
-		ixEthAccRxFreeFromSwQ(portId);
-	    }
-	    else
-	    {
-		RX_INC(portId,rxUnexpectedError);
-		IX_ETH_ACC_FATAL_LOG(
-		     "ixEthAccRxPortFreeReplenish:Error: %u\n",
-		     qStatus, 0, 0, 0, 0, 0);
-	    }
-        }
-    }
-    else
-    {
-	RX_INC(portId,rxUnexpectedError);
-	IX_ETH_ACC_FATAL_LOG(
-	    "ixEthAccRxPortFreeReplenish:Error: qStatus = %u\n",
-	    (UINT32)qStatus, 0, 0, 0, 0, 0);
-        return(IX_ETH_ACC_FAIL);
-    }
-    return (IX_ETH_ACC_SUCCESS);
-}
-
-
-IX_ETH_ACC_PUBLIC
-IxEthAccStatus ixEthAccTxSchedulingDisciplineSetPriv(IxEthAccPortId portId,
-						 IxEthAccSchedulerDiscipline
-						 sched)
-{
-    if (!IX_ETH_ACC_IS_PORT_VALID(portId))
-    {
-	return (IX_ETH_ACC_INVALID_PORT);
-    }
-
-    if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
-    {
-        IX_ETH_ACC_WARNING_LOG("ixEthAccTxSchedulingDisciplineSet: Unavailable Eth %d: Cannot set Tx Scheduling Discipline.\n",(INT32)portId,0,0,0,0,0);
-        return IX_ETH_ACC_SUCCESS ;
-    }
-
-    if (!IX_ETH_IS_PORT_INITIALIZED(portId))
-    {
-	return (IX_ETH_ACC_PORT_UNINITIALIZED);
-    }
-
-    if (sched != FIFO_PRIORITY && sched != FIFO_NO_PRIORITY)
-    {
-	return (IX_ETH_ACC_INVALID_ARG);
-    }
-
-    ixEthAccPortData[portId].ixEthAccTxData.schDiscipline = sched;
-    return (IX_ETH_ACC_SUCCESS);
-}
-
-IX_ETH_ACC_PUBLIC
-IxEthAccStatus ixEthAccRxSchedulingDisciplineSetPriv(IxEthAccSchedulerDiscipline
-						 sched)
-{
-    if (sched != FIFO_PRIORITY && sched != FIFO_NO_PRIORITY)
-    {
-	return (IX_ETH_ACC_INVALID_ARG);
-    }
-
-    ixEthAccDataInfo.schDiscipline = sched;
-
-    return (IX_ETH_ACC_SUCCESS);
-}
-
-
-/**
- * @fn ixEthRxFrameProcess(IxEthAccPortId portId, IX_OSAL_MBUF *mbufPtr)
- *
- * @brief process incoming frame :
- *
- * @param @ref IxQMgrCallback IxQMgrMultiBufferCallback
- *
- * @return none
- *
- * @internal
- *
- */
-IX_ETH_ACC_PRIVATE BOOL
-ixEthRxFrameProcess(IxEthAccPortId portId, IX_OSAL_MBUF *mbufPtr)
-{
-    UINT32 flags;
-    IxEthDBStatus result;
-
-#ifndef NDEBUG
-    /* Prudent to at least check the port is within range */
-    if (portId >= IX_ETH_ACC_NUMBER_OF_PORTS)
-    {
-	ixEthAccDataStats.unexpectedError++;
-	IX_ETH_ACC_FATAL_LOG(
-	     "ixEthRxFrameProcess: Illegal port: %u\n",
-	     (UINT32)portId, 0, 0, 0, 0, 0);
-	return FALSE;
-    }
-#endif
-
-    /* convert fields from mbuf header */
-    ixEthAccMbufFromRxQ(mbufPtr);
-
-    /* check about any special processing for this frame */
-    flags = IX_ETHACC_NE_FLAGS(mbufPtr);
-    if ((flags & (IX_ETHACC_NE_FILTERMASK | IX_ETHACC_NE_NEWSRCMASK)) == 0)
-    {
-	/* "best case" scenario : nothing special to do for this frame */
-	return TRUE;
-    }
-
-#ifdef CONFIG_IXP425_COMPONENT_ETHDB
-    /* if a new source MAC address is detected by the NPE,
-     * update IxEthDB with the portId and the MAC address.
-     */
-    if ((flags & IX_ETHACC_NE_NEWSRCMASK & ixEthAccNewSrcMask) != 0)
-    {
-        result = ixEthDBFilteringDynamicEntryProvision(portId,
-			  (IxEthDBMacAddr *) IX_ETHACC_NE_SOURCEMAC(mbufPtr));
-
-	if (result != IX_ETH_DB_SUCCESS && result != IX_ETH_DB_FEATURE_UNAVAILABLE)
-	{
-            if ((ixEthAccMacState[portId].portDisableState == ACTIVE) && (result != IX_ETH_DB_BUSY))
-            {
-	        RX_STATS_INC(portId, rxUnexpectedError);
-                IX_ETH_ACC_FATAL_LOG("ixEthRxFrameProcess: Failed to add source MAC \
-                                    to the Learning/Filtering database\n", 0, 0, 0, 0, 0, 0);
-            }
-            else
-            {
-                /* we expect this to fail during PortDisable, as EthDB is disabled for
-                 * that port and will refuse to learn new addresses
-		 */
-            }
-	}
-	else
-	{
-	    RX_STATS_INC(portId, rxUnlearnedMacAddress);
-	}
-    }
-#endif
-
-    /* check if this frame should have been filtered
-     * by the NPE and take the appropriate action
-     */
-    if (((flags & IX_ETHACC_NE_FILTERMASK) != 0)
-        && (ixEthAccMacState[portId].portDisableState == ACTIVE))
-    {
-        /* If the mbuf was allocated with a small data size, or the current data pointer is not
-         * within the allocated data area, then the buffer is non-standard and has to be
-         * replenished with the minimum size only
-         */
-        if( (IX_OSAL_MBUF_ALLOCATED_BUFF_LEN(mbufPtr) < IX_ETHNPE_ACC_RXFREE_BUFFER_LENGTH_MIN)
-           || ((UINT8 *)IX_OSAL_MBUF_ALLOCATED_BUFF_DATA(mbufPtr) > IX_OSAL_MBUF_MDATA(mbufPtr))
-           || ((UINT8 *)(IX_OSAL_MBUF_ALLOCATED_BUFF_DATA(mbufPtr) +
-              IX_OSAL_MBUF_ALLOCATED_BUFF_LEN(mbufPtr))
-               < IX_OSAL_MBUF_MDATA(mbufPtr)) )
-        {
-            /* set to minimum length */
-            IX_OSAL_MBUF_MLEN(mbufPtr) = IX_OSAL_MBUF_PKT_LEN(mbufPtr) =
-                IX_ETHNPE_ACC_RXFREE_BUFFER_LENGTH_MIN;
-        }
-        else
-        {
-            /* restore original length */
-            IX_OSAL_MBUF_MLEN(mbufPtr) = IX_OSAL_MBUF_PKT_LEN(mbufPtr) =
-                ( IX_OSAL_MBUF_ALLOCATED_BUFF_LEN(mbufPtr) -
-                 (IX_OSAL_MBUF_MDATA(mbufPtr) - (UINT8 *)IX_OSAL_MBUF_ALLOCATED_BUFF_DATA(mbufPtr)) );
-        }
-
-        /* replenish from here */
-        if (ixEthAccPortRxFreeReplenish(portId, mbufPtr) != IX_ETH_ACC_SUCCESS)
-        {
-                IX_ETH_ACC_FATAL_LOG("ixEthRxFrameProcess: Failed to replenish with filtered frame\
-                                      on port %d\n", portId, 0, 0, 0, 0, 0);
-        }
-
-        RX_STATS_INC(portId, rxFiltered);
-
-        /* indicate that frame should not be subjected to further processing */
-        return FALSE;
-    }
-
-    return TRUE;
-}
-
-
-/**
- * @fn ixEthRxFrameQMCallback
- *
- * @brief receive callback for Frame receive Q from NPE
- *
- * Frames are passed one-at-a-time to the user
- *
- * @param @ref IxQMgrCallback
- *
- * @return none
- *
- * @internal
- *
- * Design note : while processing the entry X, entry X+1 is preloaded
- * into memory to reduce the number of stall cycles
- *
- */
-void ixEthRxFrameQMCallback(IxQMgrQId qId, IxQMgrCallbackId callbackId)
-{
-    IX_OSAL_MBUF    *mbufPtr;
-    IX_OSAL_MBUF    *nextMbufPtr;
-    UINT32     qEntry;
-    UINT32     nextQEntry;
-    UINT32     *qEntryPtr;
-    UINT32     portId;
-    UINT32     destPortId;
-    UINT32     npeId;
-    UINT32     rxQReadStatus;
-
-    /*
-     * Design note : entries are read in a buffer, This buffer contains
-     * an extra zeroed entry so the loop will
-     * always terminate on a null entry, whatever the result of Burst read is.
-     */
-    UINT32 rxQEntry[IX_ETH_ACC_MAX_RX_FRAME_CONSUME_PER_CALLBACK + 1];
-
-    /*
-     * Indication of the number of times the callback is used.
-     */
-    IX_ETH_ACC_STATS_INC(ixEthAccDataStats.rxCallbackCounter);
-
-    do
-    {
-	/*
-	 * Indication of the number of times the queue is drained
-	 */
-	IX_ETH_ACC_STATS_INC(ixEthAccDataStats.rxCallbackBurstRead);
-
-	/* ensure the last entry of the array contains a zeroed value */
-	qEntryPtr = rxQEntry;
-	qEntryPtr[IX_ETH_ACC_MAX_RX_FRAME_CONSUME_PER_CALLBACK] = 0;
-
-	rxQReadStatus = ixQMgrQBurstRead(qId,
-		 IX_ETH_ACC_MAX_RX_FRAME_CONSUME_PER_CALLBACK,
-		 qEntryPtr);
-
-#ifndef NDEBUG
-	if ((rxQReadStatus != IX_QMGR_Q_UNDERFLOW)
-	    && (rxQReadStatus != IX_SUCCESS))
-	{
-	    ixEthAccDataStats.unexpectedError++;
-	    /*major error*/
-	    IX_ETH_ACC_FATAL_LOG(
-		"ixEthRxFrameQMCallback:Error: %u\n",
-		(UINT32)rxQReadStatus, 0, 0, 0, 0, 0);
-	    return;
-	}
-#endif
-
-	/* convert and preload the next entry
-	 * (the conversion function takes care about null pointers which
-	 * are used to mark the end of the loop)
-	 */
-	nextQEntry = *qEntryPtr;
-	nextMbufPtr = ixEthAccEntryFromQConvert(nextQEntry,
-			  IX_ETHNPE_QM_Q_RXENET_ADDR_MASK);
-
-	while(nextQEntry != 0)
-	{
-	    /* get the next entry */
-	    qEntry = nextQEntry;
-	    mbufPtr = nextMbufPtr;
-
-#ifndef NDEBUG
-	    if (mbufPtr == NULL)
-	    {
-		ixEthAccDataStats.unexpectedError++;
-		IX_ETH_ACC_FATAL_LOG(
-		    "ixEthRxFrameQMCallback: Null Mbuf Ptr\n",
-		    0, 0, 0, 0, 0, 0);
-		return;
-	    }
-#endif
-
-	    /* convert the next entry
-	     * (the conversion function takes care about null pointers which
-	     * are used to mark the end of the loop)
-	     */
-	    nextQEntry = *(++qEntryPtr);
-	    nextMbufPtr = ixEthAccEntryFromQConvert(nextQEntry,
-			      IX_ETHNPE_QM_Q_RXENET_ADDR_MASK);
-
-	    /*
-	     * Get Port and Npe ID from message.
-	     */
-	    npeId = ((IX_ETHNPE_QM_Q_RXENET_NPEID_MASK &
-		      qEntry) >> IX_ETHNPE_QM_Q_FIELD_NPEID_R);
-	    portId = IX_ETH_ACC_NPE_TO_PORT_ID(npeId);
-
-	    /* process frame, check the return code and skip the remaining of
-	     * the loop if the frame is to be filtered out
-	     */
-            if (ixEthRxFrameProcess(portId, mbufPtr))
-            {
-	        /* destination portId for this packet */
-	        destPortId = IX_ETHACC_NE_DESTPORTID(mbufPtr);
-
-                if (destPortId != IX_ETH_DB_UNKNOWN_PORT)
-                {
-                    destPortId = IX_ETH_DB_NPE_LOGICAL_ID_TO_PORT_ID(destPortId);
-                }
-
-	        /* test if QoS is enabled in ethAcc
-	        */
-	        if (ixEthAccDataInfo.schDiscipline == FIFO_PRIORITY)
-	        {
-		    /* check if there is a higher priority queue
-		    * which may require processing and then process it.
-		    */
-		    if (ixEthAccDataInfo.higherPriorityQueue[qId] < IX_QMGR_MAX_NUM_QUEUES)
-		    {
-		        ixEthRxFrameQMCallback(ixEthAccDataInfo.higherPriorityQueue[qId],
-					    callbackId);
-		    }
-	        }
-
-	        /*
-	        * increment priority stats
-	        */
-	        RX_STATS_INC(portId,rxPriority[IX_ETHACC_NE_QOS(mbufPtr)]);
-
-	        /*
-	        * increment callback count stats
-	        */
-	        RX_STATS_INC(portId,rxFrameClientCallback);
-
-	        /*
-	        * Call user level callback.
-	        */
-	        ixEthAccPortData[portId].ixEthAccRxData.rxCallbackFn(
-		    ixEthAccPortData[portId].ixEthAccRxData.rxCallbackTag,
-		    mbufPtr,
-		    destPortId);
-            }
-	}
-    } while (rxQReadStatus == IX_SUCCESS);
-}
-
-/**
- * @fn ixEthRxMultiBufferQMCallback
- *
- * @brief receive callback for Frame receive Q from NPE
- *
- * Frames are passed as an array to the user
- *
- * @param @ref IxQMgrCallback
- *
- * @return none
- *
- * @internal
- *
- * Design note : while processing the entry X, entry X+1 is preloaded
- * into memory to reduce the number of stall cycles
- *
- */
-void ixEthRxMultiBufferQMCallback(IxQMgrQId qId, IxQMgrCallbackId callbackId)
-{
-    IX_OSAL_MBUF    *mbufPtr;
-    IX_OSAL_MBUF    *nextMbufPtr;
-    UINT32     qEntry;
-    UINT32     nextQEntry;
-    UINT32     *qEntryPtr;
-    UINT32     portId;
-    UINT32     npeId;
-    UINT32     rxQReadStatus;
-    /*
-     * Design note : entries are read in a static buffer, This buffer contains
-     * an extra zeroed entry so the loop will
-     * always terminate on a null entry, whatever the result of Burst read is.
-     */
-    static UINT32 rxQEntry[IX_ETH_ACC_MAX_RX_FRAME_CONSUME_PER_CALLBACK + 1];
-    static IX_OSAL_MBUF *rxMbufPortArray[IX_ETH_ACC_NUMBER_OF_PORTS][IX_ETH_ACC_MAX_RX_FRAME_CONSUME_PER_CALLBACK + 1];
-    IX_OSAL_MBUF **rxMbufPtr[IX_ETH_ACC_NUMBER_OF_PORTS];
-
-    for (portId = 0; portId < IX_ETH_ACC_NUMBER_OF_PORTS; portId++)
-    {
-	rxMbufPtr[portId] = rxMbufPortArray[portId];
-    }
-
-    /*
-     * Indication of the number of times the callback is used.
-     */
-    IX_ETH_ACC_STATS_INC(ixEthAccDataStats.rxCallbackCounter);
-
-    do
-    {
-	/*
-	 * Indication of the number of times the queue is drained
-	 */
-	IX_ETH_ACC_STATS_INC(ixEthAccDataStats.rxCallbackBurstRead);
-
-	/* ensure the last entry of the array contains a zeroed value */
-	qEntryPtr = rxQEntry;
-	qEntryPtr[IX_ETH_ACC_MAX_RX_FRAME_CONSUME_PER_CALLBACK] = 0;
-
-	rxQReadStatus = ixQMgrQBurstRead(qId,
-		 IX_ETH_ACC_MAX_RX_FRAME_CONSUME_PER_CALLBACK,
-		 qEntryPtr);
-
-#ifndef NDEBUG
-	if ((rxQReadStatus != IX_QMGR_Q_UNDERFLOW)
-	    && (rxQReadStatus != IX_SUCCESS))
-	{
-	    ixEthAccDataStats.unexpectedError++;
-	    /*major error*/
-	    IX_ETH_ACC_FATAL_LOG(
-		"ixEthRxFrameMultiBufferQMCallback:Error: %u\n",
-		(UINT32)rxQReadStatus, 0, 0, 0, 0, 0);
-	    return;
-	}
-#endif
-
-	/* convert and preload the next entry
-	 * (the conversion function takes care about null pointers which
-	 * are used to mark the end of the loop)
-	 */
-	nextQEntry = *qEntryPtr;
-	nextMbufPtr = ixEthAccEntryFromQConvert(nextQEntry,
-			  IX_ETHNPE_QM_Q_RXENET_ADDR_MASK);
-
-	while(nextQEntry != 0)
-	{
-	    /* get the next entry */
-	    qEntry = nextQEntry;
-	    mbufPtr = nextMbufPtr;
-
-#ifndef NDEBUG
-	    if (mbufPtr == NULL)
-	    {
-		ixEthAccDataStats.unexpectedError++;
-		IX_ETH_ACC_FATAL_LOG(
-		    "ixEthRxFrameMultiBufferQMCallback:Error: Null Mbuf Ptr\n",
-		    0, 0, 0, 0, 0, 0);
-		return;
-	    }
-#endif
-
-	    /* convert the next entry
-	     * (the conversion function takes care about null pointers which
-	     * are used to mark the end of the loop)
-	     */
-	    nextQEntry = *(++qEntryPtr);
-	    nextMbufPtr = ixEthAccEntryFromQConvert(nextQEntry,
-			      IX_ETHNPE_QM_Q_RXENET_ADDR_MASK);
-
-	    /*
-	     * Get Port and Npe ID from message.
-	     */
-	    npeId = ((IX_ETHNPE_QM_Q_RXENET_NPEID_MASK &
-		      qEntry) >>
-		     IX_ETHNPE_QM_Q_FIELD_NPEID_R);
-	    portId = IX_ETH_ACC_NPE_TO_PORT_ID(npeId);
-
-	    /* skip the remaining of the loop if the frame is
-	     * to be filtered out
-	     */
-	    if (ixEthRxFrameProcess(portId, mbufPtr))
-	    {
-		/* store a mbuf pointer in an array */
-		*rxMbufPtr[portId]++ = mbufPtr;
-
-		/*
-		 * increment priority stats
-		 */
-		RX_STATS_INC(portId,rxPriority[IX_ETHACC_NE_QOS(mbufPtr)]);
-	    }
-
-	    /* test for QoS enabled in ethAcc */
-	    if (ixEthAccDataInfo.schDiscipline == FIFO_PRIORITY)
-	    {
-		/* check if there is a higher priority queue
-		 * which may require processing and then process it.
-		 */
-		if (ixEthAccDataInfo.higherPriorityQueue[qId] < IX_QMGR_MAX_NUM_QUEUES)
-		{
-		    ixEthRxMultiBufferQMCallback(ixEthAccDataInfo.higherPriorityQueue[qId],
-						 callbackId);
-		}
-	    }
-	}
-
-	/* check if any of the the arrays contains any entry */
-	for (portId = 0; portId < IX_ETH_ACC_NUMBER_OF_PORTS; portId++)
-	{
-	    if (rxMbufPtr[portId] != rxMbufPortArray[portId])
-	    {
-		/* add a last NULL pointer at the end of the
-		 * array of mbuf pointers
-		 */
-		*rxMbufPtr[portId] = NULL;
-
-		/*
-		 * increment callback count stats
-		 */
-		RX_STATS_INC(portId,rxFrameClientCallback);
-
-		/*
-		 * Call user level callback with an array of
-		 * buffers (NULL terminated)
-		 */
-		ixEthAccPortData[portId].ixEthAccRxData.
-		    rxMultiBufferCallbackFn(
-			    ixEthAccPortData[portId].ixEthAccRxData.
-			           rxMultiBufferCallbackTag,
-			    rxMbufPortArray[portId]);
-
-		/* reset the buffer pointer to the beginning of
-		 * the array
-		 */
-		rxMbufPtr[portId] = rxMbufPortArray[portId];
-	    }
-	}
-
-    } while (rxQReadStatus == IX_SUCCESS);
-}
-
-
-/**
- * @brief  rxFree low event handler
- *
- */
-void ixEthRxFreeQMCallback(IxQMgrQId qId, IxQMgrCallbackId callbackId)
-{
-    IxEthAccPortId	portId = (IxEthAccPortId) callbackId;
-    int		        lockVal;
-    UINT32		maxQWritesToPerform = IX_ETH_ACC_MAX_RX_FREE_BUFFERS_LOAD;
-    IX_STATUS	        qStatus = IX_SUCCESS;
-
-    /*
-     * We have reached a low threshold on one of the Rx Free Qs
-     */
-
-    /*note that due to the fact that we are working off an Empty threshold, this callback
-      need only write a single entry to the Rx Free queue in order to re-arm the notification
-    */
-
-    RX_STATS_INC(portId,rxFreeLowCallback);
-
-    /*
-     * Get buffers from approprite S/W Rx freeBufferList Q.
-     */
-
-#ifndef NDEBUG
-    if (!IX_ETH_ACC_IS_PORT_VALID(portId))
-    {
-	ixEthAccDataStats.unexpectedError++;
-	IX_ETH_ACC_FATAL_LOG(
-	    "ixEthRxFreeQMCallback:Error: Invalid Port 0x%08X\n",
-	    portId, 0, 0, 0, 0, 0);
-	return;
-    }
-#endif
-    IX_ETH_ACC_DATA_PLANE_LOCK(lockVal);
-    if (IX_ETH_ACC_DATAPLANE_IS_Q_EMPTY(ixEthAccPortData[portId].
-					ixEthAccRxData.freeBufferList))
-    {
-	/*
-	 * Turn off Q callback notification for Q in Question.
-	 */
-	qStatus = ixQMgrNotificationDisable(
-	    IX_ETH_ACC_PORT_TO_RX_FREE_Q_ID(portId));
-
-
-	IX_ETH_ACC_DATA_PLANE_UNLOCK(lockVal);
-
-	if (qStatus != IX_SUCCESS)
-	{
-	    RX_INC(portId,rxUnexpectedError);
-	    IX_ETH_ACC_FATAL_LOG(
-		"ixEthRxFreeQMCallback:Error: unexpected QM status 0x%08X\n",
-		qStatus, 0, 0, 0, 0, 0);
-	    return;
-	}
-    }
-    else
-    {
-	IX_ETH_ACC_DATA_PLANE_UNLOCK(lockVal);
-	/*
-	 * Load the H/W Q with buffers from the s/w Q.
-	 */
-
-	do
-	{
-	    /*
-	     * Consume Q entries. - Note Q contains Physical addresss,
-	     * and have already been flushed to memory,
-	     * And endianess converted if required.
-	     */
-	    if (ixEthAccRxFreeFromSwQ(portId) != IX_SUCCESS)
-	    {
-		/*
-		 * No more entries in s/w Q.
-		 * Turn off Q callback indication
-		 */
-
-		IX_ETH_ACC_DATA_PLANE_LOCK(lockVal);
-		if (IX_ETH_ACC_DATAPLANE_IS_Q_EMPTY(ixEthAccPortData[portId].
-		    ixEthAccRxData.freeBufferList))
-		{
-		    qStatus = ixQMgrNotificationDisable(
-			IX_ETH_ACC_PORT_TO_RX_FREE_Q_ID(portId));
-		}
-		IX_ETH_ACC_DATA_PLANE_UNLOCK(lockVal);
-		break;
-	    }
-	}
-	while (--maxQWritesToPerform);
-    }
-}
-/**
- * @fn Tx queue low event handler
- *
- */
-void
-ixEthTxFrameQMCallback(IxQMgrQId qId, IxQMgrCallbackId callbackId)
-{
-    IxEthAccPortId portId = (IxEthAccPortId) callbackId;
-    int		   lockVal;
-    UINT32	   maxQWritesToPerform = IX_ETH_ACC_MAX_TX_FRAME_TX_CONSUME_PER_CALLBACK;
-    IX_STATUS	   qStatus = IX_SUCCESS;
-    IxEthAccTxPriority highestPriority;
-
-
-    /*
-     * We have reached a low threshold on the Tx Q, and are being asked to
-     * supply a buffer for transmission from our S/W TX queues
-     */
-    TX_STATS_INC(portId,txLowThreshCallback);
-
-    /*
-     * Get buffers from approprite Q.
-     */
-
-#ifndef NDEBUG
-    if (!IX_ETH_ACC_IS_PORT_VALID(portId))
-    {
-	ixEthAccDataStats.unexpectedError++;
-	IX_ETH_ACC_FATAL_LOG(
-	    "ixEthTxFrameQMCallback:Error: Invalid Port 0x%08X\n",
-	    portId, 0, 0, 0, 0, 0);
-	return;
-    }
-#endif
-
-    do
-    {
-	/*
-	 * Consume Q entries. - Note Q contains Physical addresss,
-	 * and have already been flushed to memory,
-	 * and endianess already sone if required.
-	 */
-
-	IX_ETH_ACC_DATA_PLANE_LOCK(lockVal);
-
-	if(ixEthAccTxSwQHighestPriorityGet(portId, &highestPriority) ==
-	   IX_ETH_ACC_FAIL)
-	{
-	    /*
-	     * No more entries in s/w Q.
-	     * Turn off Q callback indication
-	     */
-	    qStatus = ixQMgrNotificationDisable(
-		IX_ETH_ACC_PORT_TO_TX_Q_ID(portId));
-
-	    IX_ETH_ACC_DATA_PLANE_UNLOCK(lockVal);
-
-	    if (qStatus != IX_SUCCESS)
-	    {
-		ixEthAccDataStats.unexpectedError++;
-		IX_ETH_ACC_FATAL_LOG(
-		    "ixEthTxFrameQMCallback:Error: unexpected QM status 0x%08X\n",
-		    qStatus, 0, 0, 0, 0, 0);
-	    }
-
-	    return;
-	}
-	else
-	{
-	    IX_ETH_ACC_DATA_PLANE_UNLOCK(lockVal);
-	    if (ixEthAccTxFromSwQ(portId,highestPriority)!=IX_SUCCESS)
-	    {
-                /* nothing left in the sw queue or the hw queues are
-                * full. There is no point to continue to drain the
-                * sw queues
-                */
-		return;
-	    }
-	}
-    }
-    while (--maxQWritesToPerform);
-}
-
-/**
- * @brief TxDone event handler
- *
- * Design note : while processing the entry X, entry X+1 is preloaded
- * into memory to reduce the number of stall cycles
- *
- */
-
-void
-ixEthTxFrameDoneQMCallback(IxQMgrQId qId, IxQMgrCallbackId callbackId)
-{
-    IX_OSAL_MBUF    *mbufPtr;
-    UINT32     qEntry;
-    UINT32     *qEntryPtr;
-    UINT32     txDoneQReadStatus;
-    UINT32     portId;
-    UINT32     npeId;
-
-    /*
-     * Design note : entries are read in a static buffer, This buffer contains
-     * an extra entyry (which is zeroed by the compiler), so the loop will
-     * always terminate on a null entry, whatever the result of Burst read is.
-     */
-    static UINT32 txDoneQEntry[IX_ETH_ACC_MAX_TX_FRAME_DONE_CONSUME_PER_CALLBACK + 1];
-
-    /*
-     * Indication that Tx frames have been transmitted from the NPE.
-     */
-
-    IX_ETH_ACC_STATS_INC(ixEthAccDataStats.txDoneCallbackCounter);
-
-    do{
-	qEntryPtr = txDoneQEntry;
-	txDoneQReadStatus = ixQMgrQBurstRead(IX_ETH_ACC_TX_FRAME_DONE_ETH_Q,
-		     IX_ETH_ACC_MAX_TX_FRAME_DONE_CONSUME_PER_CALLBACK,
-		     qEntryPtr);
-
-#ifndef NDEBUG
-	if (txDoneQReadStatus != IX_QMGR_Q_UNDERFLOW
-	    && (txDoneQReadStatus != IX_SUCCESS))
-	{
-	    /*major error*/
-	    ixEthAccDataStats.unexpectedError++;
-	    IX_ETH_ACC_FATAL_LOG(
-		"ixEthTxFrameDoneQMCallback:Error: %u\n",
-		(UINT32)txDoneQReadStatus, 0, 0, 0, 0, 0);
-	    return;
-	}
-#endif
-
-	qEntry = *qEntryPtr;
-
-	while(qEntry != 0)
-	{
-	    mbufPtr = ixEthAccEntryFromQConvert(qEntry,
-		      IX_ETHNPE_QM_Q_TXENET_ADDR_MASK);
-
-#ifndef NDEBUG
-	    if (mbufPtr == NULL)
-	    {
-		ixEthAccDataStats.unexpectedError++;
-		IX_ETH_ACC_FATAL_LOG(
-		    "ixEthTxFrameDoneQMCallback:Error: Null Mbuf Ptr\n",
-		    0, 0, 0, 0, 0, 0);
-		return;
-	    }
-#endif
-
-	    /* endianness conversions and stats updates */
-	    ixEthAccMbufFromTxQ(mbufPtr);
-
-	    /*
-	     * Get NPE id from message, then convert to portId.
-	     */
-	    npeId = ((IX_ETHNPE_QM_Q_TXENETDONE_NPEID_MASK &
-		       qEntry) >>
-		      IX_ETHNPE_QM_Q_FIELD_NPEID_R);
-	    portId = IX_ETH_ACC_NPE_TO_PORT_ID(npeId);
-
-#ifndef NDEBUG
-	    /* Prudent to at least check the port is within range */
-	    if (portId >= IX_ETH_ACC_NUMBER_OF_PORTS)
-	    {
-		ixEthAccDataStats.unexpectedError++;
-		IX_ETH_ACC_FATAL_LOG(
-		    "ixEthTxFrameDoneQMCallback: Illegal port: %u\n",
-		    (UINT32)portId, 0, 0, 0, 0, 0);
-		return;
-	    }
-#endif
-
-	    TX_STATS_INC(portId,txDoneClientCallback);
-
-	    /*
-	     * Call user level callback.
-	     */
-	    ixEthAccPortData[portId].ixEthAccTxData.txBufferDoneCallbackFn(
-		ixEthAccPortData[portId].ixEthAccTxData.txCallbackTag,
-		mbufPtr);
-
-	    /* move to next queue entry */
-	    qEntry = *(++qEntryPtr);
-
-	}
-    } while( txDoneQReadStatus == IX_SUCCESS );
-}
-
-IX_ETH_ACC_PUBLIC
-void ixEthAccDataPlaneShow(void)
-{
-    UINT32 numTx0Entries;
-    UINT32 numTx1Entries;
-    UINT32 numTxDoneEntries;
-    UINT32 numRxEntries;
-    UINT32 numRxFree0Entries;
-    UINT32 numRxFree1Entries;
-    UINT32 portId;
-#ifdef __ixp46X
-    UINT32 numTx2Entries;
-    UINT32 numRxFree2Entries;
-#endif
-#ifndef NDEBUG
-    UINT32 priority;
-    UINT32 numBuffersInRx=0;
-    UINT32 numBuffersInTx=0;
-    UINT32 numBuffersInSwQ=0;
-    UINT32 totalBuffers=0;
-    UINT32 rxFreeCallbackCounter = 0;
-    UINT32 txCallbackCounter = 0;
-#endif
-    UINT32 key;
-
-    /* snapshot of stats */
-    IxEthAccTxDataStats tx[IX_ETH_ACC_NUMBER_OF_PORTS];
-    IxEthAccRxDataStats rx[IX_ETH_ACC_NUMBER_OF_PORTS];
-    IxEthAccDataPlaneStats stats;
-
-    if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
-    {
-	return;
-    }
-
-    /* get a reliable snapshot */
-    key = ixOsalIrqLock();
-
-    numTx0Entries = 0;
-    ixQMgrQNumEntriesGet(IX_ETH_ACC_TX_FRAME_ENET0_Q, &numTx0Entries);
-    numTx1Entries = 0;
-    ixQMgrQNumEntriesGet(IX_ETH_ACC_TX_FRAME_ENET1_Q, &numTx1Entries);
-    numTxDoneEntries = 0;
-    ixQMgrQNumEntriesGet( IX_ETH_ACC_TX_FRAME_DONE_ETH_Q, &numTxDoneEntries);
-    numRxEntries = 0;
-    ixEthAccQMgrRxQEntryGet(&numRxEntries);
-    numRxFree0Entries = 0;
-    ixQMgrQNumEntriesGet(IX_ETH_ACC_RX_FREE_BUFF_ENET0_Q, &numRxFree0Entries);
-    numRxFree1Entries = 0;
-    ixQMgrQNumEntriesGet(IX_ETH_ACC_RX_FREE_BUFF_ENET1_Q, &numRxFree1Entries);
-
-#ifdef __ixp46X
-    numTx2Entries = 0;
-    ixQMgrQNumEntriesGet(IX_ETH_ACC_TX_FRAME_ENET2_Q, &numTx2Entries);
-    numRxFree2Entries = 0;
-    ixQMgrQNumEntriesGet(IX_ETH_ACC_RX_FREE_BUFF_ENET2_Q, &numRxFree2Entries);
-#endif
-
-    for(portId=IX_ETH_PORT_1; portId < IX_ETH_ACC_NUMBER_OF_PORTS; portId++)
-    {
-	memcpy(&tx[portId],
-	       &ixEthAccPortData[portId].ixEthAccTxData.stats,
-	       sizeof(tx[portId]));
-	memcpy(&rx[portId],
-	       &ixEthAccPortData[portId].ixEthAccRxData.stats,
-	       sizeof(rx[portId]));
-    }
-    memcpy(&stats, &ixEthAccDataStats, sizeof(stats));
-
-    ixOsalIrqUnlock(key);
-
-#ifdef NDEBUG
-    printf("Detailed statistics collection not supported in this load\n");
-#endif
-
-    /* print snapshot */
-    for(portId=0; portId < IX_ETH_ACC_NUMBER_OF_PORTS; portId++)
-    {
-        /* If not IXP42X A0 stepping, proceed to check for existence of coprocessors */
-        if ((IX_FEATURE_CTRL_SILICON_TYPE_A0 !=
-	     (ixFeatureCtrlProductIdRead() & IX_FEATURE_CTRL_SILICON_STEPPING_MASK))
-	    || (IX_FEATURE_CTRL_DEVICE_TYPE_IXP42X != ixFeatureCtrlDeviceRead ()))
-        {
-                if ((IX_ETH_PORT_1 == portId) &&
-                    (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_ETH0) ==
-                     IX_FEATURE_CTRL_COMPONENT_DISABLED))
-                {
-                   continue ;
-                }
-                if ((IX_ETH_PORT_2 == portId) &&
-                    (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_ETH1) ==
-                     IX_FEATURE_CTRL_COMPONENT_DISABLED))
-                {
-                    continue ;
-                }
-                if ((IX_ETH_PORT_3 == portId) &&
-                    (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEA_ETH) ==
-                     IX_FEATURE_CTRL_COMPONENT_DISABLED))
-                {
-                    continue ;
-                }
-        }
-
-	printf("PORT %u --------------------------------\n",
-	       portId);
-#ifndef NDEBUG
-	printf("Tx Done Frames                : %u\n",
-	       tx[portId].txDoneClientCallback +
-	       tx[portId].txDoneSwQDuringDisable +
-	       tx[portId].txDoneDuringDisable);
-	printf("Tx Frames                     : %u\n",
-	       tx[portId].txQOK + tx[portId].txQDelayed);
-	printf("Tx H/W Q Added OK             : %u\n",
-	       tx[portId].txQOK);
-	printf("Tx H/W Q Delayed              : %u\n",
-	       tx[portId].txQDelayed);
-	printf("Tx From S/W Q Added OK        : %u\n",
-	       tx[portId].txFromSwQOK);
-	printf("Tx From S/W Q Delayed         : %u\n",
-	       tx[portId].txFromSwQDelayed);
-	printf("Tx Overflow                   : %u\n",
-	       tx[portId].txOverflow);
-	printf("Tx Mutual Lock                : %u\n",
-	       tx[portId].txLock);
-	printf("Tx Late Ntf Enabled           : %u\n",
-	       tx[portId].txLateNotificationEnabled);
-	printf("Tx Low Thresh CB              : %u\n",
-	       tx[portId].txLowThreshCallback);
-	printf("Tx Done from H/W Q (Disable)  : %u\n",
-	       tx[portId].txDoneDuringDisable);
-	printf("Tx Done from S/W Q (Disable)  : %u\n",
-	       tx[portId].txDoneSwQDuringDisable);
-	for (priority = IX_ETH_ACC_TX_PRIORITY_0;
-	     priority <= IX_ETH_ACC_TX_PRIORITY_7;
-	     priority++)
-	{
-	    if (tx[portId].txPriority[priority])
-	    {
-		printf("Tx Priority %u                 : %u\n",
-		       priority,
-		       tx[portId].txPriority[priority]);
-	    }
-	}
-#endif
-	printf("Tx unexpected errors          : %u (should be 0)\n",
-	       tx[portId].txUnexpectedError);
-
-#ifndef NDEBUG
-	printf("Rx Frames                     : %u\n",
-	       rx[portId].rxFrameClientCallback +
-	       rx[portId].rxSwQDuringDisable+
-	       rx[portId].rxDuringDisable);
-	printf("Rx Free Replenish             : %u\n",
-	       rx[portId].rxFreeRepOK + rx[portId].rxFreeRepDelayed);
-	printf("Rx Free H/W Q Added OK        : %u\n",
-	       rx[portId].rxFreeRepOK);
-	printf("Rx Free H/W Q Delayed         : %u\n",
-	       rx[portId].rxFreeRepDelayed);
-	printf("Rx Free From S/W Q Added OK   : %u\n",
-	       rx[portId].rxFreeRepFromSwQOK);
-	printf("Rx Free From S/W Q Delayed    : %u\n",
-	       rx[portId].rxFreeRepFromSwQDelayed);
-	printf("Rx Free Overflow              : %u\n",
-	       rx[portId].rxFreeOverflow);
-	printf("Rx Free Mutual Lock           : %u\n",
-	       rx[portId].rxFreeLock);
-	printf("Rx Free Late Ntf Enabled      : %u\n",
-	       rx[portId].rxFreeLateNotificationEnabled);
-	printf("Rx Free Low CB                : %u\n",
-	       rx[portId].rxFreeLowCallback);
-	printf("Rx From H/W Q (Disable)       : %u\n",
-	       rx[portId].rxDuringDisable);
-	printf("Rx From S/W Q (Disable)       : %u\n",
-	       rx[portId].rxSwQDuringDisable);
-	printf("Rx unlearned Mac Address      : %u\n",
-	       rx[portId].rxUnlearnedMacAddress);
-        printf("Rx Filtered (Rx => RxFree)    : %u\n",
-            rx[portId].rxFiltered);
-
-	for (priority = IX_ETH_ACC_TX_PRIORITY_0;
-	     priority <= IX_ETH_ACC_TX_PRIORITY_7;
-	     priority++)
-	{
-	    if (rx[portId].rxPriority[priority])
-	    {
-		printf("Rx Priority %u                 : %u\n",
-		       priority,
-		       rx[portId].rxPriority[priority]);
-	    }
-	}
-#endif
-	printf("Rx unexpected errors          : %u (should be 0)\n",
-	       rx[portId].rxUnexpectedError);
-
-#ifndef NDEBUG
-	numBuffersInTx = tx[portId].txQOK +
-	    tx[portId].txQDelayed -
-	    tx[portId].txDoneClientCallback -
-	    tx[portId].txDoneSwQDuringDisable -
-	    tx[portId].txDoneDuringDisable;
-
-	printf("# Tx Buffers currently for transmission : %u\n",
-	       numBuffersInTx);
-
-	numBuffersInRx = rx[portId].rxFreeRepOK +
-	    rx[portId].rxFreeRepDelayed -
-	    rx[portId].rxFrameClientCallback -
-	    rx[portId].rxSwQDuringDisable -
-	    rx[portId].rxDuringDisable;
-
-	printf("# Rx Buffers currently for reception    : %u\n",
-	       numBuffersInRx);
-
-	totalBuffers += numBuffersInRx + numBuffersInTx;
-#endif
-    }
-
-    printf("---------------------------------------\n");
-
-#ifndef NDEBUG
-    printf("\n");
-    printf("Mbufs :\n");
-    printf("Tx Unchained mbufs            : %u\n",
-	   stats.unchainedTxMBufs);
-    printf("Tx Chained bufs               : %u\n",
-	   stats.chainedTxMBufs);
-    printf("TxDone Unchained mbufs        : %u\n",
-	   stats.unchainedTxDoneMBufs);
-    printf("TxDone Chained bufs           : %u\n",
-	   stats.chainedTxDoneMBufs);
-    printf("RxFree Unchained mbufs        : %u\n",
-	   stats.unchainedRxFreeMBufs);
-    printf("RxFree Chained bufs           : %u\n",
-	   stats.chainedRxFreeMBufs);
-    printf("Rx Unchained mbufs            : %u\n",
-	   stats.unchainedRxMBufs);
-    printf("Rx Chained bufs               : %u\n",
-	   stats.chainedRxMBufs);
-
-    printf("\n");
-    printf("Software queue usage :\n");
-    printf("Buffers added to S/W Q        : %u\n",
-	   stats.addToSwQ);
-    printf("Buffers removed from S/W Q    : %u\n",
-	   stats.removeFromSwQ);
-
-    printf("\n");
-    printf("Hardware queues callbacks :\n");
-
-    for(portId=0; portId < IX_ETH_ACC_NUMBER_OF_PORTS; portId++)
-    {
-	rxFreeCallbackCounter += rx[portId].rxFreeLowCallback;
-	txCallbackCounter += tx[portId].txLowThreshCallback;
-    }
-    printf("Tx Done QM Callback invoked   : %u\n",
-	   stats.txDoneCallbackCounter);
-    printf("Tx QM Callback invoked        : %u\n",
-	   txCallbackCounter);
-    printf("Rx QM Callback invoked        : %u\n",
-	   stats.rxCallbackCounter);
-    printf("Rx QM Callback burst read     : %u\n",
-	   stats.rxCallbackBurstRead);
-    printf("Rx Free QM Callback invoked   : %u\n",
-	   rxFreeCallbackCounter);
-#endif
-    printf("Unexpected errors in CB       : %u (should be 0)\n",
-	   stats.unexpectedError);
-    printf("\n");
-
-    printf("Hardware queues levels :\n");
-    printf("Transmit Port 1 Q             : %u \n",numTx0Entries);
-    printf("Transmit Port 2 Q             : %u \n",numTx1Entries);
-#ifdef __ixp46X
-    printf("Transmit Port 3 Q             : %u \n",numTx2Entries);
-#endif
-    printf("Transmit Done Q               : %u \n",numTxDoneEntries);
-    printf("Receive Q                     : %u \n",numRxEntries);
-    printf("Receive Free Port 1 Q         : %u \n",numRxFree0Entries);
-    printf("Receive Free Port 2 Q         : %u \n",numRxFree1Entries);
-#ifdef __ixp46X
-    printf("Receive Free Port 3 Q         : %u \n",numRxFree2Entries);
-#endif
-
-#ifndef NDEBUG
-    printf("\n");
-    printf("# Total Buffers accounted for : %u\n",
-	   totalBuffers);
-
-    numBuffersInSwQ = ixEthAccDataStats.addToSwQ -
-	ixEthAccDataStats.removeFromSwQ;
-
-    printf("    Buffers in S/W Qs         : %u\n",
-	   numBuffersInSwQ);
-    printf("    Buffers in H/W Qs or NPEs : %u\n",
-	   totalBuffers - numBuffersInSwQ);
-#endif
-
-    printf("Rx QoS Discipline             : %s\n",
-	   (ixEthAccDataInfo.schDiscipline ==
-	    FIFO_PRIORITY ) ? "Enabled" : "Disabled");
-
-    for(portId=0; portId < IX_ETH_ACC_NUMBER_OF_PORTS; portId++)
-    {
-	printf("Tx QoS Discipline port %u      : %s\n",
-	       portId,
-	       (ixEthAccPortData[portId].ixEthAccTxData.schDiscipline ==
-		FIFO_PRIORITY ) ? "Enabled" : "Disabled");
-    }
-    printf("\n");
-}
-
-
-
-
-
diff --git a/arch/arm/cpu/ixp/npe/IxEthAccMac.c b/arch/arm/cpu/ixp/npe/IxEthAccMac.c
deleted file mode 100644
index 369ee91..0000000
--- a/arch/arm/cpu/ixp/npe/IxEthAccMac.c
+++ /dev/null
@@ -1,2641 +0,0 @@
-/**
- * @file IxEthAccMac.c
- *
- * @author Intel Corporation
- * @date
- *
- * @brief  MAC control functions
- *
- * Design Notes:
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
- */
-
-#include "IxOsal.h"
-#include "IxNpeMh.h"
-#ifdef CONFIG_IXP425_COMPONENT_ETHDB
-#include "IxEthDB.h"
-#endif
-#include "IxEthDBPortDefs.h"
-#include "IxEthNpe.h"
-#include "IxEthAcc.h"
-#include "IxEthAccDataPlane_p.h"
-#include "IxEthAcc_p.h"
-#include "IxEthAccMac_p.h"
-
-/* Maximum number of retries during ixEthAccPortDisable, which
- * is approximately 10 seconds
-*/
-#define IX_ETH_ACC_MAX_RETRY 500
-
-/* Maximum number of retries during ixEthAccPortDisable when expecting
- * timeout
- */
-#define IX_ETH_ACC_MAX_RETRY_TIMEOUT 5
-
-#define IX_ETH_ACC_VALIDATE_PORT_ID(portId) \
-    do                                                           \
-    {                                                            \
-        if(!IX_ETH_ACC_IS_PORT_VALID(portId))   \
-        {                                                        \
-	    return IX_ETH_ACC_INVALID_PORT;                      \
-        }                                                        \
-    } while(0)
-
-PUBLIC IxEthAccMacState ixEthAccMacState[IX_ETH_ACC_NUMBER_OF_PORTS];
-
-PRIVATE UINT32 ixEthAccMacBase[IX_ETH_ACC_NUMBER_OF_PORTS];
-
-/*Forward function declarations*/
-PRIVATE void
-ixEthAccPortDisableRx (IxEthAccPortId portId,
-		       IX_OSAL_MBUF * mBufPtr,
-		       BOOL useMultiBufferCallback);
-
-PRIVATE void
-ixEthAccPortDisableRxAndReplenish (IxEthAccPortId portId,
-				   IX_OSAL_MBUF * mBufPtr,
-				   BOOL useMultiBufferCallback);
-
-PRIVATE void
-ixEthAccPortDisableTxDone (UINT32 cbTag,
-			   IX_OSAL_MBUF *mbuf);
-
-PRIVATE void
-ixEthAccPortDisableTxDoneAndSubmit (UINT32 cbTag,
-				    IX_OSAL_MBUF *mbuf);
-
-PRIVATE void
-ixEthAccPortDisableRxCallback (UINT32 cbTag,
-			       IX_OSAL_MBUF * mBufPtr,
-			       UINT32 learnedPortId);
-
-PRIVATE void
-ixEthAccPortDisableMultiBufferRxCallback (UINT32 cbTag,
-					  IX_OSAL_MBUF **mBufPtr);
-
-PRIVATE IxEthAccStatus
-ixEthAccPortDisableTryTransmit(UINT32 portId);
-
-PRIVATE IxEthAccStatus
-ixEthAccPortDisableTryReplenish(UINT32 portId);
-
-PRIVATE IxEthAccStatus
-ixEthAccPortMulticastMacAddressGet (IxEthAccPortId portId,
-				    IxEthAccMacAddr *macAddr);
-
-PRIVATE IxEthAccStatus
-ixEthAccPortMulticastMacFilterGet (IxEthAccPortId portId,
-				   IxEthAccMacAddr *macAddr);
-
-PRIVATE void
-ixEthAccMacNpeStatsMessageCallback (IxNpeMhNpeId npeId,
-				    IxNpeMhMessage msg);
-
-PRIVATE void
-ixEthAccMacNpeStatsResetMessageCallback (IxNpeMhNpeId npeId,
-					 IxNpeMhMessage msg);
-
-PRIVATE void
-ixEthAccNpeLoopbackMessageCallback (IxNpeMhNpeId npeId,
-				    IxNpeMhMessage msg);
-
-PRIVATE void
-ixEthAccMulticastAddressSet(IxEthAccPortId portId);
-
-PRIVATE BOOL
-ixEthAccMacEqual(IxEthAccMacAddr *macAddr1,
-		 IxEthAccMacAddr *macAddr2);
-
-PRIVATE void
-ixEthAccMacPrint(IxEthAccMacAddr *m);
-
-PRIVATE void
-ixEthAccMacStateUpdate(IxEthAccPortId portId);
-
-IxEthAccStatus
-ixEthAccMacMemInit(void)
-{
-    ixEthAccMacBase[IX_ETH_PORT_1] =
-	(UINT32) IX_OSAL_MEM_MAP(IX_ETH_ACC_MAC_0_BASE,
-				 IX_OSAL_IXP400_ETHA_MAP_SIZE);
-    ixEthAccMacBase[IX_ETH_PORT_2] =
-	(UINT32) IX_OSAL_MEM_MAP(IX_ETH_ACC_MAC_1_BASE,
-				 IX_OSAL_IXP400_ETHB_MAP_SIZE);
-#ifdef __ixp46X
-    ixEthAccMacBase[IX_ETH_PORT_3] =
-	(UINT32) IX_OSAL_MEM_MAP(IX_ETH_ACC_MAC_2_BASE,
-				 IX_OSAL_IXP400_ETH_NPEA_MAP_SIZE);
-    if (ixEthAccMacBase[IX_ETH_PORT_3] == 0)
-    {
-	ixOsalLog(IX_OSAL_LOG_LVL_FATAL,
-		  IX_OSAL_LOG_DEV_STDOUT,
-		  "EthAcc: Could not map MAC I/O memory\n",
-		  0, 0, 0, 0, 0 ,0);
-
-	return IX_ETH_ACC_FAIL;
-    }
-#endif
-
-    if (ixEthAccMacBase[IX_ETH_PORT_1] == 0
-	|| ixEthAccMacBase[IX_ETH_PORT_2] == 0)
-    {
-	ixOsalLog(IX_OSAL_LOG_LVL_FATAL,
-		  IX_OSAL_LOG_DEV_STDOUT,
-		  "EthAcc: Could not map MAC I/O memory\n",
-		  0, 0, 0, 0, 0 ,0);
-
-	return IX_ETH_ACC_FAIL;
-    }
-
-    return IX_ETH_ACC_SUCCESS;
-}
-
-void
-ixEthAccMacUnload(void)
-{
-    IX_OSAL_MEM_UNMAP(ixEthAccMacBase[IX_ETH_PORT_1]);
-    IX_OSAL_MEM_UNMAP(ixEthAccMacBase[IX_ETH_PORT_2]);
-#ifdef __ixp46X
-    IX_OSAL_MEM_UNMAP(ixEthAccMacBase[IX_ETH_PORT_3]);
-    ixEthAccMacBase[IX_ETH_PORT_3] = 0;
-#endif
-    ixEthAccMacBase[IX_ETH_PORT_2] = 0;
-    ixEthAccMacBase[IX_ETH_PORT_1] = 0;
-}
-
-IxEthAccStatus
-ixEthAccPortEnablePriv(IxEthAccPortId portId)
-{
-    IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
-    if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
-    {
-        IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot enable port.\n",(INT32)portId,0,0,0,0,0);
-        return IX_ETH_ACC_SUCCESS ;
-    }
-
-    if (!IX_ETH_IS_PORT_INITIALIZED(portId))
-    {
-        printf("EthAcc: (Mac) cannot enable port %d, port not initialized\n", portId);
-	return (IX_ETH_ACC_PORT_UNINITIALIZED);
-    }
-
-    if (ixEthAccPortData[portId].ixEthAccTxData.txBufferDoneCallbackFn == NULL)
-    {
-        /* TxDone callback not registered */
-        printf("EthAcc: (Mac) cannot enable port %d, TxDone callback not registered\n", portId);
-	return (IX_ETH_ACC_PORT_UNINITIALIZED);
-    }
-
-    if ((ixEthAccPortData[portId].ixEthAccRxData.rxCallbackFn == NULL)
-	&& (ixEthAccPortData[portId].ixEthAccRxData.rxMultiBufferCallbackFn == NULL))
-    {
-        /* Receive callback not registered */
-        printf("EthAcc: (Mac) cannot enable port %d, Rx callback not registered\n", portId);
-	return (IX_ETH_ACC_PORT_UNINITIALIZED);
-    }
-
-    if(!ixEthAccMacState[portId].initDone)
-    {
-        printf("EthAcc: (Mac) cannot enable port %d, MAC address not set\n", portId);
-	return (IX_ETH_ACC_MAC_UNINITIALIZED);
-    }
-
-    /* if the state is being set to what it is already at, do nothing*/
-    if (ixEthAccMacState[portId].enabled)
-    {
-        return IX_ETH_ACC_SUCCESS;
-    }
-
-#ifdef CONFIG_IXP425_COMPONENT_ETHDB
-    /* enable ethernet database for this port */
-    if (ixEthDBPortEnable(portId) != IX_ETH_DB_SUCCESS)
-    {
-        printf("EthAcc: (Mac) cannot enable port %d, EthDB failure\n", portId);
-        return IX_ETH_ACC_FAIL;
-    }
-#endif
-
-    /* set the MAC core registers */
-    REG_WRITE(ixEthAccMacBase[portId],
-	      IX_ETH_ACC_MAC_TX_CNTRL2,
-	      IX_ETH_ACC_TX_CNTRL2_RETRIES_MASK);
-
-    REG_WRITE(ixEthAccMacBase[portId],
-	      IX_ETH_ACC_MAC_RANDOM_SEED,
-	      IX_ETH_ACC_RANDOM_SEED_DEFAULT);
-
-    REG_WRITE(ixEthAccMacBase[portId],
-	      IX_ETH_ACC_MAC_THRESH_P_EMPTY,
-	      IX_ETH_ACC_MAC_THRESH_P_EMPTY_DEFAULT);
-
-    REG_WRITE(ixEthAccMacBase[portId],
-	      IX_ETH_ACC_MAC_THRESH_P_FULL,
-	      IX_ETH_ACC_MAC_THRESH_P_FULL_DEFAULT);
-
-    REG_WRITE(ixEthAccMacBase[portId],
-	      IX_ETH_ACC_MAC_TX_DEFER,
-	      IX_ETH_ACC_MAC_TX_DEFER_DEFAULT);
-
-    REG_WRITE(ixEthAccMacBase[portId],
-	      IX_ETH_ACC_MAC_TX_TWO_DEFER_1,
-	      IX_ETH_ACC_MAC_TX_TWO_DEFER_1_DEFAULT);
-
-    REG_WRITE(ixEthAccMacBase[portId],
-	      IX_ETH_ACC_MAC_TX_TWO_DEFER_2,
-	      IX_ETH_ACC_MAC_TX_TWO_DEFER_2_DEFAULT);
-
-    REG_WRITE(ixEthAccMacBase[portId],
-	      IX_ETH_ACC_MAC_SLOT_TIME,
-	      IX_ETH_ACC_MAC_SLOT_TIME_DEFAULT);
-
-    REG_WRITE(ixEthAccMacBase[portId],
-	      IX_ETH_ACC_MAC_INT_CLK_THRESH,
-	      IX_ETH_ACC_MAC_INT_CLK_THRESH_DEFAULT);
-
-    REG_WRITE(ixEthAccMacBase[portId],
-	      IX_ETH_ACC_MAC_BUF_SIZE_TX,
-	      IX_ETH_ACC_MAC_BUF_SIZE_TX_DEFAULT);
-
-    REG_WRITE(ixEthAccMacBase[portId],
-	      IX_ETH_ACC_MAC_TX_CNTRL1,
-	      IX_ETH_ACC_TX_CNTRL1_DEFAULT);
-
-    REG_WRITE(ixEthAccMacBase[portId],
-	      IX_ETH_ACC_MAC_RX_CNTRL1,
-	      IX_ETH_ACC_RX_CNTRL1_DEFAULT);
-
-    /* set the global state */
-    ixEthAccMacState[portId].portDisableState = ACTIVE;
-    ixEthAccMacState[portId].enabled = TRUE;
-
-    /* rewrite the setup (including mac filtering) depending
-     * on current options
-     */
-    ixEthAccMacStateUpdate(portId);
-
-    return IX_ETH_ACC_SUCCESS;
-}
-
-/*
- * PortDisable local variables. They contain the intermediate steps
- * while the port is being disabled and the buffers being drained out
- * of the NPE.
- */
-typedef void (*IxEthAccPortDisableRx)(IxEthAccPortId portId,
-				      IX_OSAL_MBUF * mBufPtr,
-				      BOOL useMultiBufferCallback);
-static IxEthAccPortRxCallback
-ixEthAccPortDisableFn[IX_ETH_ACC_NUMBER_OF_PORTS];
-static IxEthAccPortMultiBufferRxCallback
-ixEthAccPortDisableMultiBufferFn[IX_ETH_ACC_NUMBER_OF_PORTS];
-static IxEthAccPortDisableRx
-ixEthAccPortDisableRxTable[IX_ETH_ACC_NUMBER_OF_PORTS];
-static UINT32
-ixEthAccPortDisableCbTag[IX_ETH_ACC_NUMBER_OF_PORTS];
-static UINT32
-ixEthAccPortDisableMultiBufferCbTag[IX_ETH_ACC_NUMBER_OF_PORTS];
-
-static IxEthAccPortTxDoneCallback
-ixEthAccPortDisableTxDoneFn[IX_ETH_ACC_NUMBER_OF_PORTS];
-static UINT32
-ixEthAccPortDisableTxDoneCbTag[IX_ETH_ACC_NUMBER_OF_PORTS];
-
-static UINT32
-ixEthAccPortDisableUserBufferCount[IX_ETH_ACC_NUMBER_OF_PORTS];
-
-/*
- * PortDisable private callbacks functions. They handle the user
- * traffic, and the special buffers (one for tx, one for rx) used
- * in portDisable.
- */
-PRIVATE void
-ixEthAccPortDisableTxDone(UINT32 cbTag,
-			  IX_OSAL_MBUF *mbuf)
-{
-    IxEthAccPortId portId = (IxEthAccPortId)cbTag;
-    volatile IxEthAccPortDisableState *txState = &ixEthAccMacState[portId].txState;
-
-    /* check for the special mbuf used in portDisable */
-    if (mbuf == ixEthAccMacState[portId].portDisableTxMbufPtr)
-    {
-        *txState = TRANSMIT_DONE;
-    }
-    else
-    {
-	/* increment the count of user traffic during portDisable */
-	ixEthAccPortDisableUserBufferCount[portId]++;
-
-       /* call client TxDone function */
-        ixEthAccPortDisableTxDoneFn[portId](ixEthAccPortDisableTxDoneCbTag[portId], mbuf);
-    }
-}
-
-PRIVATE IxEthAccStatus
-ixEthAccPortDisableTryTransmit(UINT32 portId)
-{
-    int key;
-    IxEthAccStatus status = IX_ETH_ACC_SUCCESS;
-    volatile IxEthAccPortDisableState *txState = &ixEthAccMacState[portId].txState;
-    /* transmit the special buffer again if it is transmitted
-     * and update the txState
-     * This section is protected because the portDisable context
-     * run an identical code, so the system keeps transmitting at the
-     * maximum rate.
-     */
-    key = ixOsalIrqLock();
-    if (*txState == TRANSMIT_DONE)
-    {
-	IX_OSAL_MBUF *mbufTxPtr = ixEthAccMacState[portId].portDisableTxMbufPtr;
-	*txState = TRANSMIT;
-	status = ixEthAccPortTxFrameSubmit(portId,
-					   mbufTxPtr,
-					   IX_ETH_ACC_TX_DEFAULT_PRIORITY);
-    }
-    ixOsalIrqUnlock(key);
-
-    return status;
-}
-
-PRIVATE void
-ixEthAccPortDisableTxDoneAndSubmit(UINT32 cbTag,
-				   IX_OSAL_MBUF *mbuf)
-{
-    IxEthAccPortId portId = (IxEthAccPortId)cbTag;
-
-    /* call the callback which forwards the traffic to the client */
-    ixEthAccPortDisableTxDone(cbTag, mbuf);
-
-    /* try to transmit the buffer used in portDisable
-     * if seen in TxDone
-     */
-    ixEthAccPortDisableTryTransmit(portId);
-}
-
-PRIVATE void
-ixEthAccPortDisableRx (IxEthAccPortId portId,
-		       IX_OSAL_MBUF * mBufPtr,
-		       BOOL useMultiBufferCallback)
-{
-    volatile IxEthAccPortDisableState *rxState = &ixEthAccMacState[portId].rxState;
-    IX_OSAL_MBUF *mNextPtr;
-
-    while (mBufPtr)
-    {
-	mNextPtr = IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR(mBufPtr);
-	IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR(mBufPtr) = NULL;
-
-	/* check for the special mbuf used in portDisable */
-	if (mBufPtr == ixEthAccMacState[portId].portDisableRxMbufPtr)
-	{
-            *rxState = RECEIVE;
-	}
-	else
-	{
-	    /* increment the count of user traffic during portDisable */
-	    ixEthAccPortDisableUserBufferCount[portId]++;
-
-	    /* reset the received payload length during portDisable */
-	    IX_OSAL_MBUF_MLEN(mBufPtr)    = 0;
-	    IX_OSAL_MBUF_PKT_LEN(mBufPtr) = 0;
-
-	    if (useMultiBufferCallback)
-	    {
-		/* call the user callback with one unchained
-		 * buffer, without payload. A small array is built
-		 * to be used as a parameter (the user callback expects
-		 * to receive an array ended by a NULL pointer.
-		 */
-		IX_OSAL_MBUF *mBufPtrArray[2];
-
-		mBufPtrArray[0] = mBufPtr;
-		mBufPtrArray[1] = NULL;
-		ixEthAccPortDisableMultiBufferFn[portId](
-			 ixEthAccPortDisableMultiBufferCbTag[portId],
-			 mBufPtrArray);
-	    }
-	    else
-	    {
-		/* call the user callback with a unchained
-		 * buffer, without payload and the destination port is
-		 * unknown.
-		 */
-		ixEthAccPortDisableFn[portId](
-		      ixEthAccPortDisableCbTag[portId],
-		      mBufPtr,
-		      IX_ETH_DB_UNKNOWN_PORT /* port not found */);
-	    }
-        }
-
-        mBufPtr = mNextPtr;
-    }
-}
-
-PRIVATE IxEthAccStatus
-ixEthAccPortDisableTryReplenish(UINT32 portId)
-{
-    int key;
-    IxEthAccStatus status = IX_ETH_ACC_SUCCESS;
-    volatile IxEthAccPortDisableState *rxState = &ixEthAccMacState[portId].rxState;
-    /* replenish with the special buffer again if it is received
-     * and update the rxState
-     * This section is protected because the portDisable context
-     * run an identical code, so the system keeps replenishing at the
-     * maximum rate.
-     */
-    key = ixOsalIrqLock();
-    if (*rxState == RECEIVE)
-    {
-	IX_OSAL_MBUF *mbufRxPtr = ixEthAccMacState[portId].portDisableRxMbufPtr;
-	*rxState = REPLENISH;
-	IX_OSAL_MBUF_MLEN(mbufRxPtr) = IX_ETHACC_RX_MBUF_MIN_SIZE;
-	status = ixEthAccPortRxFreeReplenish(portId, mbufRxPtr);
-    }
-    ixOsalIrqUnlock(key);
-
-    return status;
-}
-
-PRIVATE void
-ixEthAccPortDisableRxAndReplenish (IxEthAccPortId portId,
-				   IX_OSAL_MBUF * mBufPtr,
-				   BOOL useMultiBufferCallback)
-{
-    /* call the callback which forwards the traffic to the client */
-    ixEthAccPortDisableRx(portId, mBufPtr, useMultiBufferCallback);
-
-    /* try to replenish with the buffer used in portDisable
-     * if seen in Rx
-     */
-    ixEthAccPortDisableTryReplenish(portId);
-}
-
-PRIVATE void
-ixEthAccPortDisableRxCallback (UINT32 cbTag,
-			       IX_OSAL_MBUF * mBufPtr,
-			       UINT32 learnedPortId)
-{
-    IxEthAccPortId portId = (IxEthAccPortId)cbTag;
-
-    /* call the portDisable receive callback */
-   (ixEthAccPortDisableRxTable[portId])(portId, mBufPtr, FALSE);
-}
-
-PRIVATE void
-ixEthAccPortDisableMultiBufferRxCallback (UINT32 cbTag,
-					  IX_OSAL_MBUF **mBufPtr)
-{
-    IxEthAccPortId portId = (IxEthAccPortId)cbTag;
-
-    while (*mBufPtr)
-    {
-	/* call the portDisable receive callback with one buffer at a time */
-	(ixEthAccPortDisableRxTable[portId])(portId, *mBufPtr++, TRUE);
-    }
-}
-
-IxEthAccStatus
-ixEthAccPortDisablePriv(IxEthAccPortId portId)
-{
-    IxEthAccStatus status = IX_ETH_ACC_SUCCESS;
-    int key;
-    int retry, retryTimeout;
-    volatile IxEthAccPortDisableState *state = &ixEthAccMacState[portId].portDisableState;
-    volatile IxEthAccPortDisableState *rxState = &ixEthAccMacState[portId].rxState;
-    volatile IxEthAccPortDisableState *txState = &ixEthAccMacState[portId].txState;
-
-    IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
-    if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
-    {
-        IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot disable port.\n",(INT32)portId,0,0,0,0,0);
-        return IX_ETH_ACC_SUCCESS ;
-    }
-
-    if (!IX_ETH_IS_PORT_INITIALIZED(portId))
-    {
-	return (IX_ETH_ACC_PORT_UNINITIALIZED);
-    }
-
-    /* if the state is being set to what it is already at, do nothing */
-    if (!ixEthAccMacState[portId].enabled)
-    {
-        return IX_ETH_ACC_SUCCESS;
-    }
-
-    *state = DISABLED;
-
-    /* disable MAC receive first */
-    ixEthAccPortRxDisablePriv(portId);
-
-#ifdef CONFIG_IXP425_COMPONENT_ETHDB
-    /* disable ethernet database for this port - It is done now to avoid
-     * issuing ELT maintenance after requesting 'port disable' in an NPE
-     */
-    if (ixEthDBPortDisable(portId) != IX_ETH_DB_SUCCESS)
-    {
-	status = IX_ETH_ACC_FAIL;
-        IX_ETH_ACC_FATAL_LOG("ixEthAccPortDisable: failed to disable EthDB for this port\n", 0, 0, 0, 0, 0, 0);
-    }
-#endif
-
-    /* enter the critical section */
-    key = ixOsalIrqLock();
-
-    /* swap the Rx and TxDone callbacks */
-    ixEthAccPortDisableFn[portId]            = ixEthAccPortData[portId].ixEthAccRxData.rxCallbackFn;
-    ixEthAccPortDisableMultiBufferFn[portId] = ixEthAccPortData[portId].ixEthAccRxData.rxMultiBufferCallbackFn;
-    ixEthAccPortDisableCbTag[portId]         = ixEthAccPortData[portId].ixEthAccRxData.rxCallbackTag;
-    ixEthAccPortDisableMultiBufferCbTag[portId] = ixEthAccPortData[portId].ixEthAccRxData.rxMultiBufferCallbackTag;
-    ixEthAccPortDisableTxDoneFn[portId]      = ixEthAccPortData[portId].ixEthAccTxData.txBufferDoneCallbackFn;
-    ixEthAccPortDisableTxDoneCbTag[portId]   = ixEthAccPortData[portId].ixEthAccTxData.txCallbackTag;
-    ixEthAccPortDisableRxTable[portId]       =  ixEthAccPortDisableRx;
-
-    /* register temporary callbacks */
-    ixEthAccPortData[portId].ixEthAccRxData.rxCallbackFn            = ixEthAccPortDisableRxCallback;
-    ixEthAccPortData[portId].ixEthAccRxData.rxCallbackTag           = portId;
-
-    ixEthAccPortData[portId].ixEthAccRxData.rxMultiBufferCallbackFn = ixEthAccPortDisableMultiBufferRxCallback;
-    ixEthAccPortData[portId].ixEthAccRxData.rxMultiBufferCallbackTag = portId;
-
-    ixEthAccPortData[portId].ixEthAccTxData.txBufferDoneCallbackFn  = ixEthAccPortDisableTxDone;
-    ixEthAccPortData[portId].ixEthAccTxData.txCallbackTag           = portId;
-
-    /* initialise the Rx state and Tx states */
-    *txState = TRANSMIT_DONE;
-    *rxState = RECEIVE;
-
-    /* exit the critical section */
-    ixOsalIrqUnlock(key);
-
-    /* enable a NPE loopback */
-    if (ixEthAccNpeLoopbackEnablePriv(portId) != IX_ETH_ACC_SUCCESS)
-    {
-	status = IX_ETH_ACC_FAIL;
-    }
-
-    if (status == IX_ETH_ACC_SUCCESS)
-    {
-	retry = 0;
-
-	/* Step 1 : Drain Tx traffic and TxDone queues :
-	 *
-	 * Transmit and replenish at least once with the
-	 * special buffers until both of them are seen
-	 * in the callback hook
-	 *
-	 * (the receive callback keeps replenishing, so once we see
-	 * the special Tx buffer, we can be sure that Tx drain is complete)
-	 */
-	ixEthAccPortDisableRxTable[portId]
-	    =  ixEthAccPortDisableRxAndReplenish;
-	ixEthAccPortData[portId].ixEthAccTxData.txBufferDoneCallbackFn
-	    = ixEthAccPortDisableTxDone;
-
-	do
-	{
-	    /* keep replenishing */
-	    status = ixEthAccPortDisableTryReplenish(portId);
-	    if (status == IX_ETH_ACC_SUCCESS)
-	    {
-		/* keep transmitting */
-		status = ixEthAccPortDisableTryTransmit(portId);
-	    }
-	    if (status == IX_ETH_ACC_SUCCESS)
-	    {
-		/* wait for some traffic being processed */
-		ixOsalSleep(IX_ETH_ACC_PORT_DISABLE_DELAY_MSECS);
-	    }
-	}
-	while ((status == IX_ETH_ACC_SUCCESS)
-	       && (retry++ < IX_ETH_ACC_MAX_RETRY)
-	       && (*txState == TRANSMIT));
-
-	/* Step 2 : Drain Rx traffic, RxFree and Rx queues :
-	 *
-	 * Transmit and replenish at least once with the
-	 * special buffers until both of them are seen
-	 * in the callback hook
-	 * (the transmit callback keeps transmitting, and when we see
-	 * the special Rx buffer, we can be sure that rxFree drain
-	 * is complete)
-	 *
-	 * The nested loop helps to retry if the user was keeping
-	 * replenishing or transmitting during portDisable.
-	 *
-	 * The 2 nested loops ensure more retries if user traffic is
-	 * seen during portDisable : the user should not replenish
-	 * or transmit while portDisable is running. However, because of
-	 * the queueing possibilities in ethAcc dataplane, it is possible
-	 * that a lot of traffic is left in the queues (e.g. when
-	 * transmitting over a low speed link) and therefore, more
-	 * retries are allowed to help flushing the buffers out.
-	 */
-	ixEthAccPortDisableRxTable[portId]
-	    =  ixEthAccPortDisableRx;
-	ixEthAccPortData[portId].ixEthAccTxData.txBufferDoneCallbackFn
-	    = ixEthAccPortDisableTxDoneAndSubmit;
-
-	do
-	{
-	    do
-	    {
-		ixEthAccPortDisableUserBufferCount[portId] = 0;
-
-		/* keep replenishing */
-		status = ixEthAccPortDisableTryReplenish(portId);
-		if (status == IX_ETH_ACC_SUCCESS)
-		{
-		    /* keep transmitting */
-		    status = ixEthAccPortDisableTryTransmit(portId);
-		}
-		if (status == IX_ETH_ACC_SUCCESS)
-		{
-		    /* wait for some traffic being processed */
-		    ixOsalSleep(IX_ETH_ACC_PORT_DISABLE_DELAY_MSECS);
-		}
-	    }
-	    while ((status == IX_ETH_ACC_SUCCESS)
-		   && (retry++ < IX_ETH_ACC_MAX_RETRY)
-		   && ((ixEthAccPortDisableUserBufferCount[portId] != 0)
-		       || (*rxState == REPLENISH)));
-
-	    /* After the first iteration, change the receive callbacks,
-	     * to process only 1 buffer at a time
-	     */
-	    ixEthAccPortDisableRxTable[portId]
-		= ixEthAccPortDisableRx;
-	    ixEthAccPortData[portId].ixEthAccTxData.txBufferDoneCallbackFn
-		= ixEthAccPortDisableTxDone;
-
-	    /* repeat the whole process while user traffic is seen in TxDone
-	     *
-	     * The conditions to stop the loop are
-	     * - Xscale has both Rx and Tx special buffers
-	     *   (txState = transmit, rxState = receive)
-	     * - any error in txSubmit or rxReplenish
-	     * - no user traffic seen
-	     * - an excessive amount of retries
-	     */
-	}
-	while ((status == IX_ETH_ACC_SUCCESS)
-	       && (retry < IX_ETH_ACC_MAX_RETRY)
-	       && (*txState == TRANSMIT));
-
-	/* check the loop exit conditions. The NPE should not hold
-	 * the special buffers.
-	 */
-	if ((*rxState == REPLENISH) || (*txState == TRANSMIT))
-	{
-	    status = IX_ETH_ACC_FAIL;
-	}
-
-	if (status == IX_ETH_ACC_SUCCESS)
-	{
-	    /* Step 3 : Replenish without transmitting until a timeout
-	     * occurs, in order to drain the internal NPE fifos
-	     *
-	     * we can expect a few frames srill held
-	     * in the NPE.
-	     *
-	     * The 2 nested loops take care about the NPE dropping traffic
-	     * (including loopback traffic) when the Rx queue is full.
-	     *
-	     * The timeout value is very conservative
-	     * since the loopback used keeps replenishhing.
-	     *
-	     */
-	    do
-	    {
-		ixEthAccPortDisableRxTable[portId] = ixEthAccPortDisableRxAndReplenish;
-		ixEthAccPortDisableUserBufferCount[portId] = 0;
-		retryTimeout = 0;
-		do
-		{
-		    /* keep replenishing */
-		    status = ixEthAccPortDisableTryReplenish(portId);
-		    if (status == IX_ETH_ACC_SUCCESS)
-		    {
-			/* wait for some traffic being processed */
-			ixOsalSleep(IX_ETH_ACC_PORT_DISABLE_DELAY_MSECS);
-		    }
-		}
-		while ((status == IX_ETH_ACC_SUCCESS)
-		       && (retryTimeout++ < IX_ETH_ACC_MAX_RETRY_TIMEOUT));
-
-		/* Step 4 : Transmit once. Stop replenish
-		 *
-		 * After the Rx timeout, we are sure that the NPE does not
-		 * hold any frame in its internal NPE fifos.
-		 *
-		 * At this point, the NPE still holds the last rxFree buffer.
-		 * By transmitting a single frame, this should unblock the
-		 * last rxFree buffer. This code just transmit once and
-		 * wait for both frames seen in TxDone and in rxFree.
-		 *
-		 */
-		ixEthAccPortDisableRxTable[portId] =  ixEthAccPortDisableRx;
-		status = ixEthAccPortDisableTryTransmit(portId);
-
-		/* the NPE should immediatelyt release
-		 * the last Rx buffer and the last transmitted buffer
-		 * unless the last Tx frame was dropped (rx queue full)
-		 */
-		if (status == IX_ETH_ACC_SUCCESS)
-		{
-		    retryTimeout = 0;
-		    do
-		    {
-			ixOsalSleep(IX_ETH_ACC_PORT_DISABLE_DELAY_MSECS);
-		    }
-		    while ((*rxState == REPLENISH)
-			   && (retryTimeout++ < IX_ETH_ACC_MAX_RETRY_TIMEOUT));
-		}
-
-		/* the NPE may have dropped the traffic because of Rx
-		 * queue being full. This code ensures that the last
-		 * Tx and Rx frames are both received.
-		 */
-	    }
-	    while ((status == IX_ETH_ACC_SUCCESS)
-		   && (retry++ < IX_ETH_ACC_MAX_RETRY)
-		   && ((*txState == TRANSMIT)
-		       || (*rxState == REPLENISH)
-		       || (ixEthAccPortDisableUserBufferCount[portId] != 0)));
-
-	    /* Step 5 : check the final states : the NPE has
-	     * no buffer left, nor in Tx , nor in Rx directions.
-	     */
-	    if ((*rxState == REPLENISH) || (*txState == TRANSMIT))
-	    {
-		status = IX_ETH_ACC_FAIL;
-	    }
-	}
-
-        /* now all the buffers are drained, disable NPE loopback
-	 * This is done regardless of the logic to drain the queues and
-	 * the internal buffers held by the NPE.
-	 */
-	if (ixEthAccNpeLoopbackDisablePriv(portId) != IX_ETH_ACC_SUCCESS)
-	{
-	    status = IX_ETH_ACC_FAIL;
-	}
-    }
-
-    /* disable MAC Tx and Rx services */
-    ixEthAccMacState[portId].enabled = FALSE;
-    ixEthAccMacStateUpdate(portId);
-
-    /* restore the Rx and TxDone callbacks (within a critical section) */
-    key = ixOsalIrqLock();
-
-    ixEthAccPortData[portId].ixEthAccRxData.rxCallbackFn            = ixEthAccPortDisableFn[portId];
-    ixEthAccPortData[portId].ixEthAccRxData.rxCallbackTag           = ixEthAccPortDisableCbTag[portId];
-    ixEthAccPortData[portId].ixEthAccRxData.rxMultiBufferCallbackFn = ixEthAccPortDisableMultiBufferFn[portId];
-    ixEthAccPortData[portId].ixEthAccRxData.rxMultiBufferCallbackTag = ixEthAccPortDisableMultiBufferCbTag[portId];
-    ixEthAccPortData[portId].ixEthAccTxData.txBufferDoneCallbackFn  = ixEthAccPortDisableTxDoneFn[portId];
-    ixEthAccPortData[portId].ixEthAccTxData.txCallbackTag           = ixEthAccPortDisableTxDoneCbTag[portId];
-
-    ixOsalIrqUnlock(key);
-
-    /* the MAC core rx/tx disable may left the MAC hardware in an
-     * unpredictable state. A hw reset is executed before resetting
-     * all the MAC parameters to a known value.
-     */
-    REG_WRITE(ixEthAccMacBase[portId],
-	      IX_ETH_ACC_MAC_CORE_CNTRL,
-	      IX_ETH_ACC_CORE_RESET);
-
-    ixOsalSleep(IX_ETH_ACC_MAC_RESET_DELAY);
-
-    /* rewrite all parameters to their current value */
-    ixEthAccMacStateUpdate(portId);
-
-    REG_WRITE(ixEthAccMacBase[portId],
-	      IX_ETH_ACC_MAC_INT_CLK_THRESH,
-	      IX_ETH_ACC_MAC_INT_CLK_THRESH_DEFAULT);
-
-    REG_WRITE(ixEthAccMacBase[portId],
-	      IX_ETH_ACC_MAC_CORE_CNTRL,
-	      IX_ETH_ACC_CORE_MDC_EN);
-
-    return status;
-}
-
-IxEthAccStatus
-ixEthAccPortEnabledQueryPriv(IxEthAccPortId portId, BOOL *enabled)
-{
-    IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
-    if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
-    {
-        IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot enable port.\n",(INT32)portId,0,0,0,0,0);
-
-        /* Since Eth NPE is not available, port must be disabled */
-        *enabled = FALSE ;
-        return IX_ETH_ACC_SUCCESS ;
-    }
-
-    if (!IX_ETH_IS_PORT_INITIALIZED(portId))
-    {
-        /* Since Eth NPE is not available, port must be disabled */
-        *enabled = FALSE ;
-	return (IX_ETH_ACC_PORT_UNINITIALIZED);
-    }
-
-    *enabled = ixEthAccMacState[portId].enabled;
-
-    return IX_ETH_ACC_SUCCESS;
-}
-
-IxEthAccStatus
-ixEthAccPortMacResetPriv(IxEthAccPortId portId)
-{
-    IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
-    if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
-    {
-        IX_ETH_ACC_WARNING_LOG("EthAcc: Eth %d: Cannot reset Ethernet coprocessor.\n",(INT32)portId,0,0,0,0,0);
-        return IX_ETH_ACC_SUCCESS ;
-    }
-
-    if (!IX_ETH_IS_PORT_INITIALIZED(portId))
-    {
-	return (IX_ETH_ACC_PORT_UNINITIALIZED);
-    }
-
-    REG_WRITE(ixEthAccMacBase[portId],
-	      IX_ETH_ACC_MAC_CORE_CNTRL,
-	      IX_ETH_ACC_CORE_RESET);
-
-    ixOsalSleep(IX_ETH_ACC_MAC_RESET_DELAY);
-
-    /* rewrite all parameters to their current value */
-    ixEthAccMacStateUpdate(portId);
-
-    REG_WRITE(ixEthAccMacBase[portId],
-	      IX_ETH_ACC_MAC_INT_CLK_THRESH,
-	      IX_ETH_ACC_MAC_INT_CLK_THRESH_DEFAULT);
-
-    REG_WRITE(ixEthAccMacBase[portId],
-	      IX_ETH_ACC_MAC_CORE_CNTRL,
-	      IX_ETH_ACC_CORE_MDC_EN);
-
-    return IX_ETH_ACC_SUCCESS;
-}
-
-IxEthAccStatus
-ixEthAccPortLoopbackEnable(IxEthAccPortId portId)
-{
-    UINT32 regval;
-
-    /* Turn off promiscuous mode */
-    IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
-    if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
-    {
-        IX_ETH_ACC_WARNING_LOG("EthAcc: Eth %d: Cannot enable loopback.\n",(INT32)portId,0,0,0,0,0);
-        return IX_ETH_ACC_SUCCESS ;
-    }
-
-    if (!IX_ETH_IS_PORT_INITIALIZED(portId))
-    {
-	return (IX_ETH_ACC_PORT_UNINITIALIZED);
-    }
-
-    /* read register */
-    REG_READ(ixEthAccMacBase[portId],
-	     IX_ETH_ACC_MAC_RX_CNTRL1,
-	     regval);
-
-    /* update register */
-    REG_WRITE(ixEthAccMacBase[portId],
-	      IX_ETH_ACC_MAC_RX_CNTRL1,
-	      regval | IX_ETH_ACC_RX_CNTRL1_LOOP_EN);
-
-    return IX_ETH_ACC_SUCCESS;
-}
-
-PRIVATE void
-ixEthAccNpeLoopbackMessageCallback (IxNpeMhNpeId npeId,
-				    IxNpeMhMessage msg)
-{
-    IxEthAccPortId portId = IX_ETH_ACC_NPE_TO_PORT_ID(npeId);
-
-#ifndef NDEBUG
-    /* Prudent to at least check the port is within range */
-    if (portId >= IX_ETH_ACC_NUMBER_OF_PORTS)
-    {
-	IX_ETH_ACC_FATAL_LOG("IXETHACC:ixEthAccPortDisableMessageCallback: Illegal port: %u\n",
-            (UINT32) portId, 0, 0, 0, 0, 0);
-
-	return;
-    }
-#endif
-
-    /* unlock message reception mutex */
-    ixOsalMutexUnlock(&ixEthAccMacState[portId].npeLoopbackMessageLock);
-}
-
-IxEthAccStatus
-ixEthAccNpeLoopbackEnablePriv(IxEthAccPortId portId)
-{
-    IX_STATUS npeMhStatus;
-    IxNpeMhMessage message;
-    IxEthAccStatus status = IX_ETH_ACC_SUCCESS;
-
-    /* Turn off promiscuous mode */
-    IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
-    if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
-    {
-        IX_ETH_ACC_WARNING_LOG("EthAcc: Eth %d: Cannot enable NPE loopback.\n",(INT32)portId,0,0,0,0,0);
-        return IX_ETH_ACC_SUCCESS ;
-    }
-
-    if (!IX_ETH_IS_PORT_INITIALIZED(portId))
-    {
-	return (IX_ETH_ACC_PORT_UNINITIALIZED);
-    }
-
-    /* enable NPE loopback (lsb of the message contains the value 1) */
-    message.data[0] = (IX_ETHNPE_SETLOOPBACK_MODE << IX_ETH_ACC_MAC_MSGID_SHL)
-	| 0x01;
-    message.data[1] = 0;
-
-    npeMhStatus = ixNpeMhMessageWithResponseSend(IX_ETH_ACC_PORT_TO_NPE_ID(portId),
-		message,
-		IX_ETHNPE_SETLOOPBACK_MODE_ACK,
-		ixEthAccNpeLoopbackMessageCallback,
-		IX_NPEMH_SEND_RETRIES_DEFAULT);
-
-    if (npeMhStatus != IX_SUCCESS)
-    {
-        status = IX_ETH_ACC_FAIL;
-    }
-    else
-    {
-	/* wait for NPE loopbackEnable response */
-        if (ixOsalMutexLock(&ixEthAccMacState[portId]. npeLoopbackMessageLock,
-			    IX_ETH_ACC_PORT_DISABLE_DELAY_MSECS)
-	    != IX_SUCCESS)
-        {
-            status = IX_ETH_ACC_FAIL;
-        }
-    }
-
-    return status;
-}
-
-IxEthAccStatus
-ixEthAccPortTxEnablePriv(IxEthAccPortId portId)
-{
-    UINT32 regval;
-
-    /* Turn off promiscuous mode */
-    IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
-    if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
-    {
-        IX_ETH_ACC_WARNING_LOG("EthAcc: Eth %d: Cannot enable TX.\n",(INT32)portId,0,0,0,0,0);
-        return IX_ETH_ACC_SUCCESS ;
-    }
-
-    if (!IX_ETH_IS_PORT_INITIALIZED(portId))
-    {
-	return (IX_ETH_ACC_PORT_UNINITIALIZED);
-    }
-
-    /* read register */
-    REG_READ(ixEthAccMacBase[portId],
-	     IX_ETH_ACC_MAC_TX_CNTRL1,
-	     regval);
-
-    /* update register */
-    REG_WRITE(ixEthAccMacBase[portId],
-	      IX_ETH_ACC_MAC_TX_CNTRL1,
-	      regval | IX_ETH_ACC_TX_CNTRL1_TX_EN);
-
-    return IX_ETH_ACC_SUCCESS;
-}
-
-IxEthAccStatus
-ixEthAccPortRxEnablePriv(IxEthAccPortId portId)
-{
-    UINT32 regval;
-
-    /* Turn off promiscuous mode */
-    IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
-    if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
-    {
-        IX_ETH_ACC_WARNING_LOG("EthAcc: Eth %d: Cannot enable RX.\n",(INT32)portId,0,0,0,0,0);
-        return IX_ETH_ACC_SUCCESS ;
-    }
-
-    if (!IX_ETH_IS_PORT_INITIALIZED(portId))
-    {
-	return (IX_ETH_ACC_PORT_UNINITIALIZED);
-    }
-
-    /* read register */
-    REG_READ(ixEthAccMacBase[portId],
-	     IX_ETH_ACC_MAC_RX_CNTRL1,
-	     regval);
-
-    /* update register */
-    REG_WRITE(ixEthAccMacBase[portId],
-	      IX_ETH_ACC_MAC_RX_CNTRL1,
-	      regval | IX_ETH_ACC_RX_CNTRL1_RX_EN);
-
-    return IX_ETH_ACC_SUCCESS;
-}
-
-IxEthAccStatus
-ixEthAccPortLoopbackDisable(IxEthAccPortId portId)
-{
-    UINT32 regval;
-
-    IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
-    if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
-    {
-        IX_ETH_ACC_WARNING_LOG("EthAcc: Eth %d: Cannot disable loopback.\n",(INT32)portId,0,0,0,0,0);
-        return IX_ETH_ACC_SUCCESS ;
-    }
-
-    if (!IX_ETH_IS_PORT_INITIALIZED(portId))
-    {
-	return (IX_ETH_ACC_PORT_UNINITIALIZED);
-    }
-
-    /*disable MAC loopabck */
-    REG_READ(ixEthAccMacBase[portId],
-	     IX_ETH_ACC_MAC_RX_CNTRL1,
-	     regval);
-
-    REG_WRITE(ixEthAccMacBase[portId],
-	      IX_ETH_ACC_MAC_RX_CNTRL1,
-	      (regval & ~IX_ETH_ACC_RX_CNTRL1_LOOP_EN));
-
-    return IX_ETH_ACC_SUCCESS;
-}
-
-IxEthAccStatus
-ixEthAccNpeLoopbackDisablePriv(IxEthAccPortId portId)
-{
-    IX_STATUS npeMhStatus;
-    IxNpeMhMessage message;
-    IxEthAccStatus status = IX_ETH_ACC_SUCCESS;
-
-    /* Turn off promiscuous mode */
-    IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
-    if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
-    {
-        IX_ETH_ACC_WARNING_LOG("EthAcc: Eth %d: Cannot enable NPE loopback.\n",(INT32)portId,0,0,0,0,0);
-        return IX_ETH_ACC_SUCCESS ;
-    }
-
-    if (!IX_ETH_IS_PORT_INITIALIZED(portId))
-    {
-	return (IX_ETH_ACC_PORT_UNINITIALIZED);
-    }
-
-    /* disable NPE loopback (lsb of the message contains the value 0) */
-    message.data[0] = (IX_ETHNPE_SETLOOPBACK_MODE << IX_ETH_ACC_MAC_MSGID_SHL);
-    message.data[1] = 0;
-
-    npeMhStatus = ixNpeMhMessageWithResponseSend(IX_ETH_ACC_PORT_TO_NPE_ID(portId),
-		message,
-		IX_ETHNPE_SETLOOPBACK_MODE_ACK,
-		ixEthAccNpeLoopbackMessageCallback,
-		IX_NPEMH_SEND_RETRIES_DEFAULT);
-
-    if (npeMhStatus != IX_SUCCESS)
-    {
-        status = IX_ETH_ACC_FAIL;
-    }
-    else
-    {
-	/* wait for NPE loopbackEnable response */
-        if (ixOsalMutexLock(&ixEthAccMacState[portId].npeLoopbackMessageLock,
-			    IX_ETH_ACC_PORT_DISABLE_DELAY_MSECS)
-	    != IX_SUCCESS)
-        {
-            status = IX_ETH_ACC_FAIL;
-        }
-    }
-
-    return status;
-}
-
-IxEthAccStatus
-ixEthAccPortTxDisablePriv(IxEthAccPortId portId)
-{
-    UINT32 regval;
-
-    /* Turn off promiscuous mode */
-    IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
-    if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
-    {
-        IX_ETH_ACC_WARNING_LOG("EthAcc: Eth %d: Cannot disable TX.\n", (INT32)portId,0,0,0,0,0);
-        return IX_ETH_ACC_SUCCESS ;
-    }
-
-    if (!IX_ETH_IS_PORT_INITIALIZED(portId))
-    {
-	return (IX_ETH_ACC_PORT_UNINITIALIZED);
-    }
-
-    /* read register */
-    REG_READ(ixEthAccMacBase[portId],
-	     IX_ETH_ACC_MAC_TX_CNTRL1,
-	     regval);
-
-    /* update register */
-    REG_WRITE(ixEthAccMacBase[portId],
-	      IX_ETH_ACC_MAC_TX_CNTRL1,
-	      (regval & ~IX_ETH_ACC_TX_CNTRL1_TX_EN));
-
-    return IX_ETH_ACC_SUCCESS;
-}
-
-IxEthAccStatus
-ixEthAccPortRxDisablePriv(IxEthAccPortId portId)
-{
-    UINT32 regval;
-
-    /* Turn off promiscuous mode */
-    IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
-    if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
-    {
-        IX_ETH_ACC_WARNING_LOG("EthAcc: Eth %d: Cannot disable RX.\n", (INT32)portId,0,0,0,0,0);
-        return IX_ETH_ACC_SUCCESS ;
-    }
-
-    if (!IX_ETH_IS_PORT_INITIALIZED(portId))
-    {
-	return (IX_ETH_ACC_PORT_UNINITIALIZED);
-    }
-
-    /* read register */
-    REG_READ(ixEthAccMacBase[portId],
-	     IX_ETH_ACC_MAC_RX_CNTRL1,
-	     regval);
-
-    /* update register */
-    REG_WRITE(ixEthAccMacBase[portId],
-	      IX_ETH_ACC_MAC_RX_CNTRL1,
-	      (regval & ~IX_ETH_ACC_RX_CNTRL1_RX_EN));
-
-    return IX_ETH_ACC_SUCCESS;
-}
-
-IxEthAccStatus
-ixEthAccPortPromiscuousModeClearPriv(IxEthAccPortId portId)
-{
-    UINT32 regval;
-
-    /* Turn off promiscuous mode */
-    IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
-    if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
-    {
-        IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot clear promiscuous mode.\n",(INT32)portId,0,0,0,0,0);
-        return IX_ETH_ACC_SUCCESS ;
-    }
-
-    if (!IX_ETH_IS_PORT_INITIALIZED(portId))
-    {
-	return (IX_ETH_ACC_PORT_UNINITIALIZED);
-    }
-
-    /*set bit 5 of Rx control 1 - enable address filtering*/
-    REG_READ(ixEthAccMacBase[portId],
-	     IX_ETH_ACC_MAC_RX_CNTRL1,
-	     regval);
-
-    REG_WRITE(ixEthAccMacBase[portId],
-	      IX_ETH_ACC_MAC_RX_CNTRL1,
-	      regval | IX_ETH_ACC_RX_CNTRL1_ADDR_FLTR_EN);
-
-    ixEthAccMacState[portId].promiscuous = FALSE;
-
-    ixEthAccMulticastAddressSet(portId);
-
-    return IX_ETH_ACC_SUCCESS;
-}
-
-IxEthAccStatus
-ixEthAccPortPromiscuousModeSetPriv(IxEthAccPortId portId)
-{
-    UINT32 regval;
-
-    IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
-    if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
-    {
-        IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot set promiscuous mode.\n",(INT32)portId,0,0,0,0,0);
-        return IX_ETH_ACC_SUCCESS ;
-    }
-
-    if (!IX_ETH_IS_PORT_INITIALIZED(portId))
-    {
-	return (IX_ETH_ACC_PORT_UNINITIALIZED);
-    }
-
-    /*
-     * Set bit 5 of Rx control 1 - We enable address filtering even in
-     * promiscuous mode because we want the MAC to set the appropriate
-     * bits in m_flags which doesn't happen if we turn off filtering.
-     */
-    REG_READ(ixEthAccMacBase[portId],
-	     IX_ETH_ACC_MAC_RX_CNTRL1,
-	     regval);
-
-    REG_WRITE(ixEthAccMacBase[portId],
-	      IX_ETH_ACC_MAC_RX_CNTRL1,
-	      regval | IX_ETH_ACC_RX_CNTRL1_ADDR_FLTR_EN);
-
-    ixEthAccMacState[portId].promiscuous = TRUE;
-
-    ixEthAccMulticastAddressSet(portId);
-
-    return IX_ETH_ACC_SUCCESS;
-}
-
-IxEthAccStatus
-ixEthAccPortUnicastMacAddressSetPriv (IxEthAccPortId portId,
-				  IxEthAccMacAddr *macAddr)
-{
-    UINT32 i;
-
-    IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
-    if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
-    {
-        IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot set Unicast Mac Address.\n",(INT32)portId,0,0,0,0,0);
-        return IX_ETH_ACC_SUCCESS ;
-    }
-
-    if (!IX_ETH_IS_PORT_INITIALIZED(portId))
-    {
-	return (IX_ETH_ACC_PORT_UNINITIALIZED);
-    }
-
-
-    if (macAddr == NULL)
-    {
-	return IX_ETH_ACC_FAIL;
-    }
-
-    if ( macAddr->macAddress[0] & IX_ETH_ACC_ETH_MAC_BCAST_MCAST_BIT )
-    {
-	/* This is a multicast/broadcast address cant set it ! */
-	return IX_ETH_ACC_FAIL;
-    }
-
-    if ( macAddr->macAddress[0] == 0 &&
-	 macAddr->macAddress[1] == 0 &&
-	 macAddr->macAddress[2] == 0 &&
-	 macAddr->macAddress[3] == 0 &&
-	 macAddr->macAddress[4] == 0 &&
-	 macAddr->macAddress[5] == 0  )
-    {
-	/* This is an invalid mac address cant set it ! */
-	return IX_ETH_ACC_FAIL;
-    }
-
-#ifdef CONFIG_IXP425_COMPONENT_ETHDB
-    /* update the MAC address in the ethernet database */
-    if (ixEthDBPortAddressSet(portId, (IxEthDBMacAddr *) macAddr) != IX_ETH_DB_SUCCESS)
-    {
-        return IX_ETH_ACC_FAIL;
-    }
-#endif
-
-    /*Set the Unicast MAC to the specified value*/
-    for(i=0;i<IX_IEEE803_MAC_ADDRESS_SIZE;i++)
-    {
-	REG_WRITE(ixEthAccMacBase[portId],
-		  IX_ETH_ACC_MAC_UNI_ADDR_1 + i*sizeof(UINT32),
-		  macAddr->macAddress[i]);
-    }
-    ixEthAccMacState[portId].initDone = TRUE;
-
-    return IX_ETH_ACC_SUCCESS;
-}
-
-IxEthAccStatus
-ixEthAccPortUnicastMacAddressGetPriv (IxEthAccPortId portId,
-				  IxEthAccMacAddr *macAddr)
-{
-    /*Return the current value of the Unicast MAC from h/w
-      for the specified port*/
-    UINT32 i;
-
-    IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
-    if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
-    {
-        IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot get Unicast Mac Address.\n",(INT32)portId,0,0,0,0,0);
-        /* Since Eth Npe is unavailable, return invalid MAC Address = 00:00:00:00:00:00 */
-        for(i=0;i<IX_IEEE803_MAC_ADDRESS_SIZE;i++)
-        {
-	    macAddr->macAddress[i] = 0;
-        }
-        return IX_ETH_ACC_SUCCESS ;
-    }
-
-    if(!ixEthAccMacState[portId].initDone)
-    {
-	return (IX_ETH_ACC_MAC_UNINITIALIZED);
-    }
-
-    if (macAddr == NULL)
-    {
-	return IX_ETH_ACC_FAIL;
-    }
-
-
-    for(i=0;i<IX_IEEE803_MAC_ADDRESS_SIZE;i++)
-    {
-	REG_READ(ixEthAccMacBase[portId],
-		 IX_ETH_ACC_MAC_UNI_ADDR_1 + i*sizeof(UINT32),
-		 macAddr->macAddress[i]);
-    }
-    return IX_ETH_ACC_SUCCESS;
-}
-
-PRIVATE IxEthAccStatus
-ixEthAccPortMulticastMacAddressGet (IxEthAccPortId portId,
-				    IxEthAccMacAddr *macAddr)
-{
-    /*Return the current value of the Multicast MAC from h/w
-      for the specified port*/
-    UINT32 i;
-
-    for(i=0;i<IX_IEEE803_MAC_ADDRESS_SIZE;i++)
-    {
-
-	REG_READ(ixEthAccMacBase[portId],
-		 IX_ETH_ACC_MAC_ADDR_1 + i*sizeof(UINT32),
-		 macAddr->macAddress[i]);
-    }
-
-    return IX_ETH_ACC_SUCCESS;
-}
-
-PRIVATE IxEthAccStatus
-ixEthAccPortMulticastMacFilterGet (IxEthAccPortId portId,
-				   IxEthAccMacAddr *macAddr)
-{
-    /*Return the current value of the Multicast MAC from h/w
-      for the specified port*/
-    UINT32 i;
-
-    for(i=0;i<IX_IEEE803_MAC_ADDRESS_SIZE;i++)
-    {
-
-	REG_READ(ixEthAccMacBase[portId],
-		 IX_ETH_ACC_MAC_ADDR_MASK_1 + i*sizeof(UINT32),
-		 macAddr->macAddress[i]);
-    }
-    return IX_ETH_ACC_SUCCESS;
-}
-
-IxEthAccStatus
-ixEthAccPortMulticastAddressJoinPriv (IxEthAccPortId portId,
-				  IxEthAccMacAddr *macAddr)
-{
-    UINT32 i;
-    IxEthAccMacAddr broadcastAddr = {{0xff,0xff,0xff,0xff,0xff,0xff}};
-
-    /*Check that the port parameter is valid*/
-    IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
-    if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
-    {
-        IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot join Multicast Mac Address.\n",(INT32)portId,0,0,0,0,0);
-        return IX_ETH_ACC_SUCCESS ;
-    }
-
-    if (!IX_ETH_IS_PORT_INITIALIZED(portId))
-    {
-	return (IX_ETH_ACC_PORT_UNINITIALIZED);
-    }
-
-    /*Check that the mac address is valid*/
-    if(macAddr == NULL)
-    {
-	return IX_ETH_ACC_FAIL;
-    }
-
-    /* Check that this is a multicast address */
-    if (!(macAddr->macAddress[0] & IX_ETH_ACC_ETH_MAC_BCAST_MCAST_BIT))
-    {
-	return IX_ETH_ACC_FAIL;
-    }
-
-    /* We don't add the Broadcast address */
-    if(ixEthAccMacEqual(&broadcastAddr, macAddr))
-    {
-	return IX_ETH_ACC_FAIL;
-    }
-
-    for (i = 0;
-	 i<ixEthAccMacState[portId].mcastAddrIndex;
-	 i++)
-    {
-	/*Check if the current entry already match an existing matches*/
-	if(ixEthAccMacEqual(&ixEthAccMacState[portId].mcastAddrsTable[i], macAddr))
-	{
-	    /* Address found in the list and already configured,
-	     * return a success status
-	     */
-	    return IX_ETH_ACC_SUCCESS;
-	}
-    }
-
-    /* check for availability at the end of the current table */
-    if(ixEthAccMacState[portId].mcastAddrIndex >= IX_ETH_ACC_MAX_MULTICAST_ADDRESSES)
-    {
-	return IX_ETH_ACC_FAIL;
-    }
-
-    /*First add the address to the multicast table for the
-      specified port*/
-    i=ixEthAccMacState[portId].mcastAddrIndex;
-
-    memcpy(&ixEthAccMacState[portId].mcastAddrsTable[i],
-	   &macAddr->macAddress,
-	   IX_IEEE803_MAC_ADDRESS_SIZE);
-
-    /*Increment the index into the table, this must be done here
-     as MulticastAddressSet below needs to know about the latest
-     entry.
-    */
-    ixEthAccMacState[portId].mcastAddrIndex++;
-
-    /*Then calculate the new value to be written to the address and
-      address mask registers*/
-    ixEthAccMulticastAddressSet(portId);
-
-    return IX_ETH_ACC_SUCCESS;
-}
-
-
-IxEthAccStatus
-ixEthAccPortMulticastAddressJoinAllPriv (IxEthAccPortId portId)
-{
-    IxEthAccMacAddr mcastMacAddr = {{0x1,0x0,0x0,0x0,0x0,0x0}};
-
-    /*Check that the port parameter is valid*/
-    IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
-    if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
-    {
-        IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot join all Multicast Address.\n",(INT32)portId,0,0,0,0,0);
-        return IX_ETH_ACC_SUCCESS ;
-    }
-
-    if (!IX_ETH_IS_PORT_INITIALIZED(portId))
-    {
-	return (IX_ETH_ACC_PORT_UNINITIALIZED);
-    }
-
-    /* remove all entries from the database and
-    *  insert a multicast entry
-    */
-    memcpy(&ixEthAccMacState[portId].mcastAddrsTable[0],
-	   &mcastMacAddr.macAddress,
-	   IX_IEEE803_MAC_ADDRESS_SIZE);
-
-    ixEthAccMacState[portId].mcastAddrIndex = 1;
-    ixEthAccMacState[portId].joinAll = TRUE;
-
-    ixEthAccMulticastAddressSet(portId);
-
-    return IX_ETH_ACC_SUCCESS;
-}
-
-IxEthAccStatus
-ixEthAccPortMulticastAddressLeavePriv (IxEthAccPortId portId,
-				   IxEthAccMacAddr *macAddr)
-{
-    UINT32 i;
-    IxEthAccMacAddr mcastMacAddr = {{0x1,0x0,0x0,0x0,0x0,0x0}};
-
-    /*Check that the port parameter is valid*/
-    IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
-    if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
-    {
-        IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot leave Multicast Address.\n",(INT32)portId,0,0,0,0,0);
-        return IX_ETH_ACC_SUCCESS ;
-    }
-
-    if (!IX_ETH_IS_PORT_INITIALIZED(portId))
-    {
-	return (IX_ETH_ACC_PORT_UNINITIALIZED);
-    }
-
-    /*Check that the mac address is valid*/
-    if(macAddr == NULL)
-    {
-	return IX_ETH_ACC_FAIL;
-    }
-    /* Remove this mac address from the mask for the specified port
-     * we copy down all entries above the blanked entry, and
-     * decrement the index
-     */
-    i=0;
-
-    while(i<ixEthAccMacState[portId].mcastAddrIndex)
-    {
-	/*Check if the current entry matches*/
-	if(ixEthAccMacEqual(&ixEthAccMacState[portId].mcastAddrsTable[i],
-			    macAddr))
-	{
-	    if(ixEthAccMacEqual(macAddr, &mcastMacAddr))
-	    {
-		ixEthAccMacState[portId].joinAll = FALSE;
-	    }
-	    /*Decrement the index into the multicast address table
-	      for the current port*/
-	    ixEthAccMacState[portId].mcastAddrIndex--;
-
-	    /*Copy down all entries above the current entry*/
-	    while(i<ixEthAccMacState[portId].mcastAddrIndex)
-	    {
-		memcpy(&ixEthAccMacState[portId].mcastAddrsTable[i],
-		       &ixEthAccMacState[portId].mcastAddrsTable[i+1],
-		       IX_IEEE803_MAC_ADDRESS_SIZE);
-                i++;
-	    }
-	    /*recalculate the mask and write it to the MAC*/
-	    ixEthAccMulticastAddressSet(portId);
-
-	    return IX_ETH_ACC_SUCCESS;
-	}
-	/* search the next entry */
-	i++;
-    }
-    /* no matching entry found */
-    return IX_ETH_ACC_NO_SUCH_ADDR;
-}
-
-IxEthAccStatus
-ixEthAccPortMulticastAddressLeaveAllPriv (IxEthAccPortId portId)
-{
-    /*Check that the port parameter is valid*/
-    IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
-    if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
-    {
-        IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot leave all Multicast Address.\n",(INT32)portId,0,0,0,0,0);
-        return IX_ETH_ACC_SUCCESS ;
-    }
-
-    if (!IX_ETH_IS_PORT_INITIALIZED(portId))
-    {
-	return (IX_ETH_ACC_PORT_UNINITIALIZED);
-    }
-
-    ixEthAccMacState[portId].mcastAddrIndex = 0;
-    ixEthAccMacState[portId].joinAll = FALSE;
-
-    ixEthAccMulticastAddressSet(portId);
-
-    return IX_ETH_ACC_SUCCESS;
-}
-
-
-IxEthAccStatus
-ixEthAccPortUnicastAddressShowPriv (IxEthAccPortId portId)
-{
-    IxEthAccMacAddr macAddr;
-
-    IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
-    if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
-    {
-        IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot show Unicast Address.\n",(INT32)portId,0,0,0,0,0);
-        return IX_ETH_ACC_SUCCESS ;
-    }
-
-    if (!IX_ETH_IS_PORT_INITIALIZED(portId))
-    {
-	return (IX_ETH_ACC_PORT_UNINITIALIZED);
-    }
-
-    /*Get the MAC (UINICAST) address from hardware*/
-    if(ixEthAccPortUnicastMacAddressGetPriv(portId, &macAddr) != IX_ETH_ACC_SUCCESS)
-    {
-        IX_ETH_ACC_WARNING_LOG("EthAcc: MAC address uninitialised port %u\n",
-			       (INT32)portId,0,0,0,0,0);
-	return IX_ETH_ACC_MAC_UNINITIALIZED;
-    }
-
-    /*print it out*/
-    ixEthAccMacPrint(&macAddr);
-    printf("\n");
-    return IX_ETH_ACC_SUCCESS;
-}
-
-
-
-void
-ixEthAccPortMulticastAddressShowPriv(IxEthAccPortId portId)
-{
-    IxEthAccMacAddr macAddr;
-    UINT32 i;
-
-    if(!IX_ETH_ACC_IS_PORT_VALID(portId))
-    {
-        return;
-    }
-
-    if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
-    {
-        IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot show Multicast Address.\n",(INT32)portId,0,0,0,0,0);
-        return ;
-    }
-
-    if (!IX_ETH_IS_PORT_INITIALIZED(portId))
-    {
-	return;
-    }
-
-    printf("Multicast MAC: ");
-    /*Get the MAC (MULTICAST) address from hardware*/
-    ixEthAccPortMulticastMacAddressGet(portId, &macAddr);
-    /*print it out*/
-    ixEthAccMacPrint(&macAddr);
-    /*Get the MAC (MULTICAST) filter from hardware*/
-    ixEthAccPortMulticastMacFilterGet(portId, &macAddr);
-    /*print it out*/
-    printf(" ( ");
-    ixEthAccMacPrint(&macAddr);
-    printf(" )\n");
-    printf("Constituent Addresses:\n");
-    for(i=0;i<ixEthAccMacState[portId].mcastAddrIndex;i++)
-    {
-	ixEthAccMacPrint(&ixEthAccMacState[portId].mcastAddrsTable[i]);
-	printf("\n");
-    }
-    return;
-}
-
-/*Set the duplex mode*/
-IxEthAccStatus
-ixEthAccPortDuplexModeSetPriv (IxEthAccPortId portId,
-			   IxEthAccDuplexMode mode)
-{
-    UINT32 txregval;
-    UINT32 rxregval;
-
-    /*This is bit 1 of the transmit control reg, set to 1 for half
-      duplex, 0 for full duplex*/
-    IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
-    if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
-    {
-        IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot set Duplex Mode.\n",(INT32)portId,0,0,0,0,0);
-        return IX_ETH_ACC_SUCCESS ;
-    }
-
-    if (!IX_ETH_IS_PORT_INITIALIZED(portId))
-    {
-	return (IX_ETH_ACC_PORT_UNINITIALIZED);
-    }
-
-    REG_READ(ixEthAccMacBase[portId],
-	     IX_ETH_ACC_MAC_TX_CNTRL1,
-	     txregval);
-
-    REG_READ(ixEthAccMacBase[portId],
-	     IX_ETH_ACC_MAC_RX_CNTRL1,
-	     rxregval);
-
-    if (mode ==  IX_ETH_ACC_FULL_DUPLEX)
-    {
-	/*Clear half duplex bit in TX*/
-	REG_WRITE(ixEthAccMacBase[portId],
-		  IX_ETH_ACC_MAC_TX_CNTRL1,
-		  txregval & ~IX_ETH_ACC_TX_CNTRL1_DUPLEX);
-
-	/*We must set the pause enable in the receive logic when in
-	  full duplex mode*/
-	REG_WRITE(ixEthAccMacBase[portId],
-		  IX_ETH_ACC_MAC_RX_CNTRL1,
-		  rxregval | IX_ETH_ACC_RX_CNTRL1_PAUSE_EN);
-	ixEthAccMacState[portId].fullDuplex = TRUE;
-
-    }
-    else if (mode ==  IX_ETH_ACC_HALF_DUPLEX)
-    {
-	/*Set half duplex bit in TX*/
-	REG_WRITE(ixEthAccMacBase[portId],
-		  IX_ETH_ACC_MAC_TX_CNTRL1,
-		  txregval | IX_ETH_ACC_TX_CNTRL1_DUPLEX);
-
-	/*We must clear pause enable in the receive logic when in
-	  half duplex mode*/
-	REG_WRITE(ixEthAccMacBase[portId],
-		  IX_ETH_ACC_MAC_RX_CNTRL1,
-		  rxregval & ~IX_ETH_ACC_RX_CNTRL1_PAUSE_EN);
-
-	ixEthAccMacState[portId].fullDuplex = FALSE;
-    }
-    else
-    {
-	return IX_ETH_ACC_FAIL;
-    }
-
-
-    return IX_ETH_ACC_SUCCESS;
-
-}
-
-
-
-IxEthAccStatus
-ixEthAccPortDuplexModeGetPriv (IxEthAccPortId portId,
-			   IxEthAccDuplexMode *mode)
-{
-    /*Return the duplex mode for the specified port*/
-    UINT32 regval;
-
-    /*This is bit 1 of the transmit control reg, set to 1 for half
-      duplex, 0 for full duplex*/
-    IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
-    if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
-    {
-        IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot get Duplex Mode.\n",(INT32)portId,0,0,0,0,0);
-        /* return hald duplex */
-        *mode = IX_ETH_ACC_HALF_DUPLEX ;
-        return IX_ETH_ACC_SUCCESS ;
-    }
-
-    if (!IX_ETH_IS_PORT_INITIALIZED(portId))
-    {
-	return (IX_ETH_ACC_PORT_UNINITIALIZED);
-    }
-
-    if (mode == NULL)
-    {
-	return (IX_ETH_ACC_FAIL);
-    }
-
-    REG_READ(ixEthAccMacBase[portId],
-	     IX_ETH_ACC_MAC_TX_CNTRL1,
-	     regval);
-
-    if( regval & IX_ETH_ACC_TX_CNTRL1_DUPLEX)
-    {
-	*mode = IX_ETH_ACC_HALF_DUPLEX;
-    }
-    else
-    {
-	*mode = IX_ETH_ACC_FULL_DUPLEX;
-    }
-
-    return IX_ETH_ACC_SUCCESS;
-}
-
-
-
-IxEthAccStatus
-ixEthAccPortTxFrameAppendPaddingEnablePriv (IxEthAccPortId portId)
-{
-    UINT32 regval;
-    /*Enable FCS computation by the MAC and appending to the
-      frame*/
-
-    IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
-    if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
-    {
-        IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot enable Tx Frame Append Padding.\n",(INT32)portId,0,0,0,0,0);
-        return IX_ETH_ACC_SUCCESS ;
-    }
-
-    if (!IX_ETH_IS_PORT_INITIALIZED(portId))
-    {
-	return (IX_ETH_ACC_PORT_UNINITIALIZED);
-    }
-
-    REG_READ(ixEthAccMacBase[portId],
-	     IX_ETH_ACC_MAC_TX_CNTRL1,
-	     regval);
-
-    REG_WRITE(ixEthAccMacBase[portId],
-	      IX_ETH_ACC_MAC_TX_CNTRL1,
-	      regval |
-	      IX_ETH_ACC_TX_CNTRL1_PAD_EN);
-
-    ixEthAccMacState[portId].txPADAppend = TRUE;
-    return IX_ETH_ACC_SUCCESS;
-}
-
-IxEthAccStatus
-ixEthAccPortTxFrameAppendPaddingDisablePriv (IxEthAccPortId portId)
-{
-    UINT32 regval;
-
-    /*disable FCS computation and appending*/
-    /*Set bit 4 of Tx control register one to zero*/
-    IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
-    if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
-    {
-        IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot disble Tx Frame Append Padding.\n",(INT32)portId,0,0,0,0,0);
-        return IX_ETH_ACC_SUCCESS ;
-    }
-
-    if (!IX_ETH_IS_PORT_INITIALIZED(portId))
-    {
-	return (IX_ETH_ACC_PORT_UNINITIALIZED);
-    }
-
-    REG_READ(ixEthAccMacBase[portId],
-	     IX_ETH_ACC_MAC_TX_CNTRL1,
-	     regval);
-
-    REG_WRITE(ixEthAccMacBase[portId],
-	      IX_ETH_ACC_MAC_TX_CNTRL1,
-	      regval & ~IX_ETH_ACC_TX_CNTRL1_PAD_EN);
-
-    ixEthAccMacState[portId].txPADAppend = FALSE;
-    return IX_ETH_ACC_SUCCESS;
-}
-
-IxEthAccStatus
-ixEthAccPortTxFrameAppendFCSEnablePriv (IxEthAccPortId portId)
-{
-    UINT32 regval;
-
-    /*Enable FCS computation by the MAC and appending to the
-      frame*/
-
-    IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
-    if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
-    {
-        IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot enable Tx Frame Append FCS.\n",(INT32)portId,0,0,0,0,0);
-        return IX_ETH_ACC_SUCCESS ;
-    }
-
-    if (!IX_ETH_IS_PORT_INITIALIZED(portId))
-    {
-	return (IX_ETH_ACC_PORT_UNINITIALIZED);
-    }
-
-    REG_READ(ixEthAccMacBase[portId],
-	     IX_ETH_ACC_MAC_TX_CNTRL1,
-	     regval);
-
-    REG_WRITE(ixEthAccMacBase[portId],
-	      IX_ETH_ACC_MAC_TX_CNTRL1,
-	      regval | IX_ETH_ACC_TX_CNTRL1_FCS_EN);
-
-    ixEthAccMacState[portId].txFCSAppend = TRUE;
-    return IX_ETH_ACC_SUCCESS;
-}
-
-IxEthAccStatus
-ixEthAccPortTxFrameAppendFCSDisablePriv (IxEthAccPortId portId)
-{
-    UINT32 regval;
-
-    /*disable FCS computation and appending*/
-    /*Set bit 4 of Tx control register one to zero*/
-    IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
-    if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
-    {
-        IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot disable Tx Frame Append FCS.\n",(INT32)portId,0,0,0,0,0);
-        return IX_ETH_ACC_SUCCESS ;
-    }
-
-    if (!IX_ETH_IS_PORT_INITIALIZED(portId))
-    {
-	return (IX_ETH_ACC_PORT_UNINITIALIZED);
-    }
-
-    REG_READ(ixEthAccMacBase[portId],
-	     IX_ETH_ACC_MAC_TX_CNTRL1,
-	     regval);
-
-    REG_WRITE(ixEthAccMacBase[portId],
-	      IX_ETH_ACC_MAC_TX_CNTRL1,
-	      regval & ~IX_ETH_ACC_TX_CNTRL1_FCS_EN);
-
-    ixEthAccMacState[portId].txFCSAppend = FALSE;
-    return IX_ETH_ACC_SUCCESS;
-}
-
-IxEthAccStatus
-ixEthAccPortRxFrameAppendFCSEnablePriv (IxEthAccPortId portId)
-{
-    /*Set bit 2 of Rx control 1*/
-    UINT32 regval;
-
-    IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
-    if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
-    {
-        IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot enable Rx Frame Append FCS.\n",(INT32)portId,0,0,0,0,0);
-        return IX_ETH_ACC_SUCCESS ;
-    }
-
-    if (!IX_ETH_IS_PORT_INITIALIZED(portId))
-    {
-	return (IX_ETH_ACC_PORT_UNINITIALIZED);
-    }
-
-    REG_READ(ixEthAccMacBase[portId],
-	     IX_ETH_ACC_MAC_RX_CNTRL1,
-	     regval);
-
-    REG_WRITE(ixEthAccMacBase[portId],
-	      IX_ETH_ACC_MAC_RX_CNTRL1,
-	      regval | IX_ETH_ACC_RX_CNTRL1_CRC_EN);
-
-    ixEthAccMacState[portId].rxFCSAppend = TRUE;
-    return IX_ETH_ACC_SUCCESS;
-}
-
-IxEthAccStatus
-ixEthAccPortRxFrameAppendFCSDisablePriv (IxEthAccPortId portId)
-{
-    UINT32 regval;
-
-    /*Clear bit 2 of Rx control 1*/
-    IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
-    if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
-    {
-        IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot disable Rx Frame Append FCS.\n",(INT32)portId,0,0,0,0,0);
-        return IX_ETH_ACC_SUCCESS ;
-    }
-
-    if (!IX_ETH_IS_PORT_INITIALIZED(portId))
-    {
-	return (IX_ETH_ACC_PORT_UNINITIALIZED);
-    }
-
-    REG_READ(ixEthAccMacBase[portId],
-	     IX_ETH_ACC_MAC_RX_CNTRL1,
-	     regval);
-
-    REG_WRITE(ixEthAccMacBase[portId],
-	      IX_ETH_ACC_MAC_RX_CNTRL1,
-	      regval & ~IX_ETH_ACC_RX_CNTRL1_CRC_EN);
-
-    ixEthAccMacState[portId].rxFCSAppend = FALSE;
-    return IX_ETH_ACC_SUCCESS;
-}
-
-
-
-PRIVATE void
-ixEthAccMacNpeStatsMessageCallback (IxNpeMhNpeId npeId,
-				    IxNpeMhMessage msg)
-{
-    IxEthAccPortId portId = IX_ETH_ACC_NPE_TO_PORT_ID(npeId);
-
-#ifndef NDEBUG
-    /* Prudent to at least check the port is within range */
-    if (portId >= IX_ETH_ACC_NUMBER_OF_PORTS)
-    {
-	IX_ETH_ACC_FATAL_LOG(
-     "IXETHACC:ixEthAccMacNpeStatsMessageCallback: Illegal port: %u\n",
-     (UINT32)portId, 0, 0, 0, 0, 0);
-	return;
-    }
-#endif
-
-    /*Unblock Stats Get call*/
-    ixOsalMutexUnlock(&ixEthAccMacState[portId].ackMIBStatsLock);
-
-}
-
-PRIVATE void
-ixEthAccMibIIStatsEndianConvert (IxEthEthObjStats *retStats)
-{
-    /* endianness conversion */
-
-    /* Rx stats */
-    retStats->dot3StatsAlignmentErrors =
-	IX_OSAL_SWAP_BE_SHARED_LONG(retStats->dot3StatsAlignmentErrors);
-    retStats->dot3StatsFCSErrors =
-	IX_OSAL_SWAP_BE_SHARED_LONG(retStats->dot3StatsFCSErrors);
-    retStats->dot3StatsInternalMacReceiveErrors =
-	IX_OSAL_SWAP_BE_SHARED_LONG(retStats->dot3StatsInternalMacReceiveErrors);
-    retStats->RxOverrunDiscards =
-	IX_OSAL_SWAP_BE_SHARED_LONG(retStats->RxOverrunDiscards);
-    retStats->RxLearnedEntryDiscards =
-	IX_OSAL_SWAP_BE_SHARED_LONG(retStats->RxLearnedEntryDiscards);
-    retStats->RxLargeFramesDiscards =
-	IX_OSAL_SWAP_BE_SHARED_LONG(retStats->RxLargeFramesDiscards);
-    retStats->RxSTPBlockedDiscards =
-	IX_OSAL_SWAP_BE_SHARED_LONG(retStats->RxSTPBlockedDiscards);
-    retStats->RxVLANTypeFilterDiscards =
-	IX_OSAL_SWAP_BE_SHARED_LONG(retStats->RxVLANTypeFilterDiscards);
-    retStats->RxVLANIdFilterDiscards =
-	IX_OSAL_SWAP_BE_SHARED_LONG(retStats->RxVLANIdFilterDiscards);
-    retStats->RxInvalidSourceDiscards =
-	IX_OSAL_SWAP_BE_SHARED_LONG(retStats->RxInvalidSourceDiscards);
-    retStats->RxBlackListDiscards =
-	IX_OSAL_SWAP_BE_SHARED_LONG(retStats->RxBlackListDiscards);
-    retStats->RxWhiteListDiscards =
-	IX_OSAL_SWAP_BE_SHARED_LONG(retStats->RxWhiteListDiscards);
-    retStats->RxUnderflowEntryDiscards =
-	IX_OSAL_SWAP_BE_SHARED_LONG(retStats->RxUnderflowEntryDiscards);
-
-    /* Tx stats */
-    retStats->dot3StatsSingleCollisionFrames =
-	IX_OSAL_SWAP_BE_SHARED_LONG(retStats->dot3StatsSingleCollisionFrames);
-    retStats->dot3StatsMultipleCollisionFrames =
-	IX_OSAL_SWAP_BE_SHARED_LONG(retStats->dot3StatsMultipleCollisionFrames);
-    retStats->dot3StatsDeferredTransmissions =
-	IX_OSAL_SWAP_BE_SHARED_LONG(retStats->dot3StatsDeferredTransmissions);
-    retStats->dot3StatsLateCollisions =
-	IX_OSAL_SWAP_BE_SHARED_LONG(retStats->dot3StatsLateCollisions);
-    retStats->dot3StatsExcessiveCollsions =
-	IX_OSAL_SWAP_BE_SHARED_LONG(retStats->dot3StatsExcessiveCollsions);
-    retStats->dot3StatsInternalMacTransmitErrors =
-	IX_OSAL_SWAP_BE_SHARED_LONG(retStats->dot3StatsInternalMacTransmitErrors);
-    retStats->dot3StatsCarrierSenseErrors =
-	IX_OSAL_SWAP_BE_SHARED_LONG(retStats->dot3StatsCarrierSenseErrors);
-    retStats->TxLargeFrameDiscards =
-	IX_OSAL_SWAP_BE_SHARED_LONG(retStats->TxLargeFrameDiscards);
-    retStats->TxVLANIdFilterDiscards =
-	IX_OSAL_SWAP_BE_SHARED_LONG(retStats->TxVLANIdFilterDiscards);
-}
-
-IxEthAccStatus
-ixEthAccMibIIStatsGet (IxEthAccPortId portId,
-		       IxEthEthObjStats *retStats )
-{
-    IxNpeMhMessage message;
-
-    if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
-    {
-        printf("EthAcc: ixEthAccMibIIStatsGet (Mac) EthAcc service is not initialized\n");
-	return (IX_ETH_ACC_FAIL);
-    }
-
-    IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
-    if (retStats == NULL)
-    {
-        printf("EthAcc: ixEthAccMibIIStatsGet (Mac) NULL argument\n");
-	return (IX_ETH_ACC_FAIL);
-    }
-
-    if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
-    {
-        printf("EthAcc: ixEthAccMibIIStatsGet (Mac) NPE for port %d is not available\n", portId);
-
-        IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot get MIB II Stats.\n",(INT32)portId,0,0,0,0,0);
-
-        /* Return all zero stats */
-        IX_ETH_ACC_MEMSET(retStats, 0, sizeof(IxEthEthObjStats));
-
-        return IX_ETH_ACC_SUCCESS ;
-    }
-
-    if (!IX_ETH_IS_PORT_INITIALIZED(portId))
-    {
-        printf("EthAcc: ixEthAccMibIIStatsGet (Mac) port %d is not initialized\n", portId);
-	return (IX_ETH_ACC_PORT_UNINITIALIZED);
-    }
-
-    IX_OSAL_CACHE_INVALIDATE(retStats, sizeof(IxEthEthObjStats));
-
-    message.data[0] = IX_ETHNPE_GETSTATS << IX_ETH_ACC_MAC_MSGID_SHL;
-    message.data[1] = (UINT32) IX_OSAL_MMU_VIRT_TO_PHYS(retStats);
-
-    /* Permit only one task to request MIB statistics Get operation
-       at a time */
-    ixOsalMutexLock(&ixEthAccMacState[portId].MIBStatsGetAccessLock, IX_OSAL_WAIT_FOREVER);
-
-    if(ixNpeMhMessageWithResponseSend(IX_ETH_ACC_PORT_TO_NPE_ID(portId),
-				      message,
-				      IX_ETHNPE_GETSTATS,
-				      ixEthAccMacNpeStatsMessageCallback,
-				      IX_NPEMH_SEND_RETRIES_DEFAULT)
-       != IX_SUCCESS)
-    {
-	ixOsalMutexUnlock(&ixEthAccMacState[portId].MIBStatsGetAccessLock);
-
-        printf("EthAcc: (Mac) StatsGet failed to send NPE message\n");
-
-	return IX_ETH_ACC_FAIL;
-    }
-
-    /* Wait for callback invocation indicating response to
-       this request - we need this mutex in order to ensure
-       that the return from this function is synchronous */
-    ixOsalMutexLock(&ixEthAccMacState[portId].ackMIBStatsLock, IX_ETH_ACC_MIB_STATS_DELAY_MSECS);
-
-    /* Permit other tasks to perform MIB statistics Get operation */
-    ixOsalMutexUnlock(&ixEthAccMacState[portId].MIBStatsGetAccessLock);
-
-    ixEthAccMibIIStatsEndianConvert (retStats);
-
-    return IX_ETH_ACC_SUCCESS;
-}
-
-
-PRIVATE void
-ixEthAccMacNpeStatsResetMessageCallback (IxNpeMhNpeId npeId,
-					 IxNpeMhMessage msg)
-{
-    IxEthAccPortId portId = IX_ETH_ACC_NPE_TO_PORT_ID(npeId);
-
-#ifndef NDEBUG
-    /* Prudent to at least check the port is within range */
-    if (portId >= IX_ETH_ACC_NUMBER_OF_PORTS)
-    {
-	IX_ETH_ACC_FATAL_LOG(
-     "IXETHACC:ixEthAccMacNpeStatsResetMessageCallback: Illegal port: %u\n",
-     (UINT32)portId, 0, 0, 0, 0, 0);
-	return;
-    }
-#endif
-
-    /*Unblock Stats Get & reset call*/
-    ixOsalMutexUnlock(&ixEthAccMacState[portId].ackMIBStatsResetLock);
-
-}
-
-
-
-IxEthAccStatus
-ixEthAccMibIIStatsGetClear (IxEthAccPortId portId,
-			    IxEthEthObjStats *retStats)
-{
-    IxNpeMhMessage message;
-
-    if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
-    {
-        printf("EthAcc: ixEthAccMibIIStatsGetClear (Mac) EthAcc service is not initialized\n");
-	return (IX_ETH_ACC_FAIL);
-    }
-
-    IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
-    if (retStats == NULL)
-    {
-        printf("EthAcc: ixEthAccMibIIStatsGetClear (Mac) NULL argument\n");
-	return (IX_ETH_ACC_FAIL);
-    }
-
-    if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
-    {
-        printf("EthAcc: ixEthAccMibIIStatsGetClear (Mac) NPE for port %d is not available\n", portId);
-
-        IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot get and clear MIB II Stats.\n", (INT32)portId, 0, 0, 0, 0, 0);
-
-        /* Return all zero stats */
-        IX_ETH_ACC_MEMSET(retStats, 0, sizeof(IxEthEthObjStats));
-
-        return IX_ETH_ACC_SUCCESS ;
-    }
-
-    if (!IX_ETH_IS_PORT_INITIALIZED(portId))
-    {
-        printf("EthAcc: ixEthAccMibIIStatsGetClear (Mac) port %d is not initialized\n", portId);
-	return (IX_ETH_ACC_PORT_UNINITIALIZED);
-    }
-
-    IX_OSAL_CACHE_INVALIDATE(retStats, sizeof(IxEthEthObjStats));
-
-    message.data[0] = IX_ETHNPE_RESETSTATS << IX_ETH_ACC_MAC_MSGID_SHL;
-    message.data[1] = (UINT32) IX_OSAL_MMU_VIRT_TO_PHYS(retStats);
-
-    /* Permit only one task to request MIB statistics Get-Reset operation at a time */
-    ixOsalMutexLock(&ixEthAccMacState[portId].MIBStatsGetResetAccessLock, IX_OSAL_WAIT_FOREVER);
-
-    if(ixNpeMhMessageWithResponseSend(IX_ETH_ACC_PORT_TO_NPE_ID(portId),
-				      message,
-				      IX_ETHNPE_RESETSTATS,
-				      ixEthAccMacNpeStatsResetMessageCallback,
-				      IX_NPEMH_SEND_RETRIES_DEFAULT)
-       != IX_SUCCESS)
-    {
-	ixOsalMutexUnlock(&ixEthAccMacState[portId].MIBStatsGetResetAccessLock);
-
-        printf("EthAcc: (Mac) ixEthAccMibIIStatsGetClear failed to send NPE message\n");
-
-	return IX_ETH_ACC_FAIL;
-    }
-
-    /* Wait for callback invocation indicating response to this request */
-    ixOsalMutexLock(&ixEthAccMacState[portId].ackMIBStatsResetLock, IX_ETH_ACC_MIB_STATS_DELAY_MSECS);
-
-    /* permit other tasks to get and reset MIB stats*/
-    ixOsalMutexUnlock(&ixEthAccMacState[portId].MIBStatsGetResetAccessLock);
-
-    ixEthAccMibIIStatsEndianConvert(retStats);
-
-    return IX_ETH_ACC_SUCCESS;
-}
-
-IxEthAccStatus
-ixEthAccMibIIStatsClear (IxEthAccPortId portId)
-{
-    static IxEthEthObjStats retStats;
-    IxEthAccStatus status;
-
-    if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
-    {
-	return (IX_ETH_ACC_FAIL);
-    }
-
-    IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
-    if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
-    {
-        IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot clear MIB II Stats.\n",(INT32)portId,0,0,0,0,0);
-        return IX_ETH_ACC_SUCCESS ;
-    }
-
-    /* there is no reset operation without a corresponding Get */
-    status = ixEthAccMibIIStatsGetClear(portId, &retStats);
-
-    return status;
-}
-
-/* Initialize the ethernet MAC settings */
-IxEthAccStatus
-ixEthAccMacInit(IxEthAccPortId portId)
-{
-    IX_OSAL_MBUF_POOL* portDisablePool;
-    UINT8 *data;
-
-    IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
-    if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
-    {
-        IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot initialize Mac.\n",(INT32)portId,0,0,0,0,0);
-        return IX_ETH_ACC_SUCCESS ;
-    }
-
-    if(ixEthAccMacState[portId].macInitialised == FALSE)
-    {
-	ixEthAccMacState[portId].fullDuplex  = TRUE;
-	ixEthAccMacState[portId].rxFCSAppend = TRUE;
-	ixEthAccMacState[portId].txFCSAppend = TRUE;
-	ixEthAccMacState[portId].txPADAppend = TRUE;
-	ixEthAccMacState[portId].enabled     = FALSE;
-	ixEthAccMacState[portId].promiscuous = TRUE;
-	ixEthAccMacState[portId].joinAll     = FALSE;
-	ixEthAccMacState[portId].initDone    = FALSE;
-	ixEthAccMacState[portId].macInitialised = TRUE;
-
-        /* initialize MIB stats mutexes */
-        ixOsalMutexInit(&ixEthAccMacState[portId].ackMIBStatsLock);
-        ixOsalMutexLock(&ixEthAccMacState[portId].ackMIBStatsLock, IX_OSAL_WAIT_FOREVER);
-
-        ixOsalMutexInit(&ixEthAccMacState[portId].ackMIBStatsResetLock);
-        ixOsalMutexLock(&ixEthAccMacState[portId].ackMIBStatsResetLock, IX_OSAL_WAIT_FOREVER);
-
-        ixOsalMutexInit(&ixEthAccMacState[portId].MIBStatsGetAccessLock);
-
-        ixOsalMutexInit(&ixEthAccMacState[portId].MIBStatsGetResetAccessLock);
-
-        ixOsalMutexInit(&ixEthAccMacState[portId].npeLoopbackMessageLock);
-
-	ixEthAccMacState[portId].portDisableRxMbufPtr = NULL;
-        ixEthAccMacState[portId].portDisableTxMbufPtr = NULL;
-
-	portDisablePool = IX_OSAL_MBUF_POOL_INIT(2,
-			  IX_ETHACC_RX_MBUF_MIN_SIZE,
-			  "portDisable Pool");
-
-        IX_OSAL_ENSURE(portDisablePool != NULL, "Failed to initialize PortDisable pool");
-
-	ixEthAccMacState[portId].portDisableRxMbufPtr = IX_OSAL_MBUF_POOL_GET(portDisablePool);
-        ixEthAccMacState[portId].portDisableTxMbufPtr = IX_OSAL_MBUF_POOL_GET(portDisablePool);
-
-	IX_OSAL_ENSURE(ixEthAccMacState[portId].portDisableRxMbufPtr != NULL,
-		  "Pool allocation failed");
-        IX_OSAL_ENSURE(ixEthAccMacState[portId].portDisableTxMbufPtr != NULL,
-		  "Pool allocation failed");
-	/* fill the payload of the Rx mbuf used in portDisable */
-        IX_OSAL_MBUF_MLEN(ixEthAccMacState[portId].portDisableRxMbufPtr) = IX_ETHACC_RX_MBUF_MIN_SIZE;
-
-        memset(IX_OSAL_MBUF_MDATA(ixEthAccMacState[portId].portDisableRxMbufPtr),
-	       0xAA,
-	       IX_ETHACC_RX_MBUF_MIN_SIZE);
-
-	/* fill the payload of the Tx mbuf used in portDisable (64 bytes) */
-        IX_OSAL_MBUF_MLEN(ixEthAccMacState[portId].portDisableTxMbufPtr) = 64;
-        IX_OSAL_MBUF_PKT_LEN(ixEthAccMacState[portId].portDisableTxMbufPtr) = 64;
-
-        data = (UINT8 *) IX_OSAL_MBUF_MDATA(ixEthAccMacState[portId].portDisableTxMbufPtr);
-        memset(data, 0xBB, 64);
-        data[0] = 0x00; /* unicast destination MAC address */
-        data[6] = 0x00; /* unicast source MAC address */
-        data[12] = 0x08; /* typelength : IP frame */
-        data[13] = 0x00; /* typelength : IP frame */
-
-	IX_OSAL_CACHE_FLUSH(data, 64);
-    }
-
-    IX_OSAL_ASSERT (ixEthAccMacBase[portId] != 0);
-
-    REG_WRITE(ixEthAccMacBase[portId],
-	      IX_ETH_ACC_MAC_CORE_CNTRL,
-	      IX_ETH_ACC_CORE_RESET);
-
-    ixOsalSleep(IX_ETH_ACC_MAC_RESET_DELAY);
-
-    REG_WRITE(ixEthAccMacBase[portId],
-	      IX_ETH_ACC_MAC_CORE_CNTRL,
-	      IX_ETH_ACC_CORE_MDC_EN);
-
-    REG_WRITE(ixEthAccMacBase[portId],
-	      IX_ETH_ACC_MAC_INT_CLK_THRESH,
-	      IX_ETH_ACC_MAC_INT_CLK_THRESH_DEFAULT);
-
-    ixEthAccMacStateUpdate(portId);
-
-    return IX_ETH_ACC_SUCCESS;
-}
-
-/* PRIVATE Functions*/
-
-PRIVATE void
-ixEthAccMacStateUpdate(IxEthAccPortId portId)
-{
-    UINT32 regval;
-
-    if ( ixEthAccMacState[portId].enabled == FALSE )
-    {
-	/*  Just disable both the transmitter and reciver in the MAC.  */
-        REG_READ(ixEthAccMacBase[portId],
-		 IX_ETH_ACC_MAC_RX_CNTRL1,
-		 regval);
-	REG_WRITE(ixEthAccMacBase[portId],
-		  IX_ETH_ACC_MAC_RX_CNTRL1,
-		  regval & ~IX_ETH_ACC_RX_CNTRL1_RX_EN);
-
-        REG_READ(ixEthAccMacBase[portId],
-		 IX_ETH_ACC_MAC_TX_CNTRL1,
-		 regval);
-	REG_WRITE(ixEthAccMacBase[portId],
-		  IX_ETH_ACC_MAC_TX_CNTRL1,
-		  regval & ~IX_ETH_ACC_TX_CNTRL1_TX_EN);
-    }
-
-    if(ixEthAccMacState[portId].fullDuplex)
-    {
-	ixEthAccPortDuplexModeSetPriv (portId, IX_ETH_ACC_FULL_DUPLEX);
-    }
-    else
-    {
-	ixEthAccPortDuplexModeSetPriv (portId, IX_ETH_ACC_HALF_DUPLEX);
-    }
-
-    if(ixEthAccMacState[portId].rxFCSAppend)
-    {
-	ixEthAccPortRxFrameAppendFCSEnablePriv (portId);
-    }
-    else
-    {
-	ixEthAccPortRxFrameAppendFCSDisablePriv (portId);
-    }
-
-    if(ixEthAccMacState[portId].txFCSAppend)
-    {
-	ixEthAccPortTxFrameAppendFCSEnablePriv (portId);
-    }
-    else
-    {
-	ixEthAccPortTxFrameAppendFCSDisablePriv (portId);
-    }
-
-    if(ixEthAccMacState[portId].txPADAppend)
-    {
-	ixEthAccPortTxFrameAppendPaddingEnablePriv (portId);
-    }
-    else
-    {
-	ixEthAccPortTxFrameAppendPaddingDisablePriv (portId);
-    }
-
-    if(ixEthAccMacState[portId].promiscuous)
-    {
-	ixEthAccPortPromiscuousModeSetPriv(portId);
-    }
-    else
-    {
-	ixEthAccPortPromiscuousModeClearPriv(portId);
-    }
-
-    if ( ixEthAccMacState[portId].enabled == TRUE )
-    {
-        /*   Enable both the transmitter and reciver in the MAC.  */
-        REG_READ(ixEthAccMacBase[portId],
-		 IX_ETH_ACC_MAC_RX_CNTRL1,
-		 regval);
-        REG_WRITE(ixEthAccMacBase[portId],
-		  IX_ETH_ACC_MAC_RX_CNTRL1,
-		  regval | IX_ETH_ACC_RX_CNTRL1_RX_EN);
-
-        REG_READ(ixEthAccMacBase[portId],
-		 IX_ETH_ACC_MAC_TX_CNTRL1,
-		 regval);
-	REG_WRITE(ixEthAccMacBase[portId],
-		  IX_ETH_ACC_MAC_TX_CNTRL1,
-		  regval | IX_ETH_ACC_TX_CNTRL1_TX_EN);
-    }
-}
-
-
-PRIVATE BOOL
-ixEthAccMacEqual(IxEthAccMacAddr *macAddr1,
-		 IxEthAccMacAddr *macAddr2)
-{
-    UINT32 i;
-    for(i=0;i<IX_IEEE803_MAC_ADDRESS_SIZE; i++)
-    {
-	if(macAddr1->macAddress[i] != macAddr2->macAddress[i])
-	{
-	    return FALSE;
-	}
-    }
-    return TRUE;
-}
-
-PRIVATE void
-ixEthAccMacPrint(IxEthAccMacAddr *m)
-{
-    printf("%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x",
-	   m->macAddress[0], m->macAddress[1],
-	   m->macAddress[2], m->macAddress[3],
-	   m->macAddress[4], m->macAddress[5]);
-}
-
-/* Set the multicast address and address mask registers
- *
- * A bit in the address mask register must be set if
- * all multicast addresses always have that bit set, or if
- * all multicast addresses always have that bit cleared.
- *
- * A bit in the address register must be set if all multicast
- * addresses have that bit set, otherwise, it should be cleared
- */
-
-PRIVATE void
-ixEthAccMulticastAddressSet(IxEthAccPortId portId)
-{
-    UINT32 i;
-    UINT32 j;
-    IxEthAccMacAddr addressMask;
-    IxEthAccMacAddr address;
-    IxEthAccMacAddr alwaysClearBits;
-    IxEthAccMacAddr alwaysSetBits;
-
-    /* calculate alwaysClearBits and alwaysSetBits:
-     * alwaysClearBits is calculated by ORing all
-     * multicast addresses, those bits that are always
-     * clear are clear in the result
-     *
-     * alwaysSetBits is calculated by ANDing all
-     * multicast addresses, those bits that are always set
-     * are set in the result
-     */
-
-    if (ixEthAccMacState[portId].promiscuous == TRUE)
-    {
-	/* Promiscuous Mode is set, and filtering
-	 * allow all packets, and enable the mcast and
-	 * bcast detection.
-	 */
-	memset(&addressMask.macAddress,
-	       0,
-	       IX_IEEE803_MAC_ADDRESS_SIZE);
-	memset(&address.macAddress,
-	       0,
-	       IX_IEEE803_MAC_ADDRESS_SIZE);
-    }
-    else
-    {
-	if(ixEthAccMacState[portId].joinAll == TRUE)
-	{
-	    /* Join all is set. The mask and address are
-	     * the multicast settings.
-	     */
-	    IxEthAccMacAddr macAddr = {{0x1,0x0,0x0,0x0,0x0,0x0}};
-
-	    memcpy(addressMask.macAddress,
-		   macAddr.macAddress,
-		   IX_IEEE803_MAC_ADDRESS_SIZE);
-	    memcpy(address.macAddress,
-		   macAddr.macAddress,
-		   IX_IEEE803_MAC_ADDRESS_SIZE);
-	}
-	else if(ixEthAccMacState[portId].mcastAddrIndex == 0)
-	{
-	    /* No entry in the filtering database,
-	     * Promiscuous Mode is cleared, Broadcast filtering
-	     * is configured.
-	     */
-	    memset(addressMask.macAddress,
-		   IX_ETH_ACC_MAC_ALL_BITS_SET,
-		   IX_IEEE803_MAC_ADDRESS_SIZE);
-	    memset(address.macAddress,
-		   IX_ETH_ACC_MAC_ALL_BITS_SET,
-		   IX_IEEE803_MAC_ADDRESS_SIZE);
-	}
-	else
-	{
-	    /* build a mask and an address which mix all entreis
-	     * from the list of multicast addresses
-	     */
-	    memset(alwaysClearBits.macAddress,
-		   0,
-		   IX_IEEE803_MAC_ADDRESS_SIZE);
-	    memset(alwaysSetBits.macAddress,
-		   IX_ETH_ACC_MAC_ALL_BITS_SET,
-		   IX_IEEE803_MAC_ADDRESS_SIZE);
-
-	    for(i=0;i<ixEthAccMacState[portId].mcastAddrIndex;i++)
-	    {
-		for(j=0;j<IX_IEEE803_MAC_ADDRESS_SIZE;j++)
-		{
-		    alwaysClearBits.macAddress[j] |=
-			ixEthAccMacState[portId].mcastAddrsTable[i].macAddress[j];
-		    alwaysSetBits.macAddress[j] &=
-			ixEthAccMacState[portId].mcastAddrsTable[i].macAddress[j];
-		}
-	    }
-
-	    for(i=0;i<IX_IEEE803_MAC_ADDRESS_SIZE;i++)
-	    {
-		addressMask.macAddress[i] = alwaysSetBits.macAddress[i]
-		    | ~alwaysClearBits.macAddress[i];
-		address.macAddress[i] = alwaysSetBits.macAddress[i];
-	    }
-	}
-    }
-
-    /*write the new addr filtering to h/w*/
-    for(i=0;i<IX_IEEE803_MAC_ADDRESS_SIZE;i++)
-    {
-	REG_WRITE(ixEthAccMacBase[portId],
-		  IX_ETH_ACC_MAC_ADDR_MASK_1+i*sizeof(UINT32),
-		  addressMask.macAddress[i]);
-	REG_WRITE(ixEthAccMacBase[portId],
-		  IX_ETH_ACC_MAC_ADDR_1+i*sizeof(UINT32),
-		  address.macAddress[i]);
-    }
-}
diff --git a/arch/arm/cpu/ixp/npe/IxEthAccMii.c b/arch/arm/cpu/ixp/npe/IxEthAccMii.c
deleted file mode 100644
index d282aa6..0000000
--- a/arch/arm/cpu/ixp/npe/IxEthAccMii.c
+++ /dev/null
@@ -1,410 +0,0 @@
-/**
- * @file IxEthAccMii.c
- *
- * @author Intel Corporation
- * @date 
- *
- * @brief  MII control functions
- *
- * Design Notes:
- *
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- * 
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- * 
- * @par
- * -- End of Copyright Notice --
- */
-
-#include "IxOsal.h"
-#include "IxEthAcc.h"
-#include "IxEthAcc_p.h"
-#include "IxEthAccMac_p.h"
-#include "IxEthAccMii_p.h"
-
-
-PRIVATE UINT32 miiBaseAddressVirt;
-PRIVATE IxOsalMutex miiAccessLock;
-
-PUBLIC UINT32 ixEthAccMiiRetryCount    = IX_ETH_ACC_MII_TIMEOUT_10TH_SECS;
-PUBLIC UINT32 ixEthAccMiiAccessTimeout = IX_ETH_ACC_MII_10TH_SEC_IN_MILLIS;
-
-/* -----------------------------------
- * private function prototypes
- */
-PRIVATE void
-ixEthAccMdioCmdWrite(UINT32 mdioCommand);
-
-PRIVATE void
-ixEthAccMdioCmdRead(UINT32 *data);
-
-PRIVATE void
-ixEthAccMdioStatusRead(UINT32 *data);
-
-
-PRIVATE void
-ixEthAccMdioCmdWrite(UINT32 mdioCommand)
-{
-    REG_WRITE(miiBaseAddressVirt,
-	      IX_ETH_ACC_MAC_MDIO_CMD_1,
-	      mdioCommand & 0xff);
-
-    REG_WRITE(miiBaseAddressVirt,
-	      IX_ETH_ACC_MAC_MDIO_CMD_2,
-	      (mdioCommand >> 8) & 0xff);
-
-    REG_WRITE(miiBaseAddressVirt,
-	      IX_ETH_ACC_MAC_MDIO_CMD_3,
-	      (mdioCommand >> 16) & 0xff);
-
-    REG_WRITE(miiBaseAddressVirt,
-	      IX_ETH_ACC_MAC_MDIO_CMD_4,
-	      (mdioCommand >> 24) & 0xff);
-}
-
-PRIVATE void
-ixEthAccMdioCmdRead(UINT32 *data)
-{
-    UINT32 regval;
-
-    REG_READ(miiBaseAddressVirt,
-	     IX_ETH_ACC_MAC_MDIO_CMD_1,
-	     regval);
-
-    *data = regval & 0xff;
-
-    REG_READ(miiBaseAddressVirt,
-	     IX_ETH_ACC_MAC_MDIO_CMD_2,
-	     regval);
-
-    *data |= (regval & 0xff) << 8;
-
-    REG_READ(miiBaseAddressVirt,
-	     IX_ETH_ACC_MAC_MDIO_CMD_3,
-	     regval);
-
-    *data |= (regval & 0xff) << 16;
-
-    REG_READ(miiBaseAddressVirt,
-	     IX_ETH_ACC_MAC_MDIO_CMD_4,
-	     regval);
-
-    *data |= (regval & 0xff) << 24;
-
-}
-
-PRIVATE void
-ixEthAccMdioStatusRead(UINT32 *data)
-{
-    UINT32 regval;
-
-    REG_READ(miiBaseAddressVirt,
-	     IX_ETH_ACC_MAC_MDIO_STS_1,
-	     regval);
-
-    *data = regval & 0xff;
-
-    REG_READ(miiBaseAddressVirt,
-	     IX_ETH_ACC_MAC_MDIO_STS_2,
-	     regval);
-
-    *data |= (regval & 0xff) << 8;
-
-    REG_READ(miiBaseAddressVirt,
-	     IX_ETH_ACC_MAC_MDIO_STS_3,
-	     regval);
-
-    *data |= (regval & 0xff) << 16;
-
-    REG_READ(miiBaseAddressVirt,
-	     IX_ETH_ACC_MAC_MDIO_STS_4,
-	     regval);
-    
-    *data |= (regval & 0xff) << 24;
-    
-}
-
-
-/********************************************************************
- * ixEthAccMiiInit
- */
-IxEthAccStatus
-ixEthAccMiiInit()
-{
-    if(ixOsalMutexInit(&miiAccessLock)!= IX_SUCCESS)
-    {
-	return IX_ETH_ACC_FAIL;
-    }
-
-    miiBaseAddressVirt = (UINT32) IX_OSAL_MEM_MAP(IX_ETH_ACC_MAC_0_BASE, IX_OSAL_IXP400_ETHA_MAP_SIZE);
-    
-    if (miiBaseAddressVirt == 0)
-    {
-      ixOsalLog(IX_OSAL_LOG_LVL_FATAL, 
-		IX_OSAL_LOG_DEV_STDOUT, 
-		"EthAcc: Could not map MII I/O mapped memory\n", 
-		0, 0, 0, 0, 0, 0);
-      
-      return IX_ETH_ACC_FAIL;
-    }
-    
-    return IX_ETH_ACC_SUCCESS;
-}
-
-void
-ixEthAccMiiUnload(void)
-{
-    IX_OSAL_MEM_UNMAP(miiBaseAddressVirt);
-  
-    miiBaseAddressVirt = 0;
-}
-
-PUBLIC IxEthAccStatus
-ixEthAccMiiAccessTimeoutSet(UINT32 timeout, UINT32 retryCount)
-{
-    if (retryCount < 1) return IX_ETH_ACC_FAIL;
-
-    ixEthAccMiiRetryCount    = retryCount;
-    ixEthAccMiiAccessTimeout = timeout;
-
-    return IX_ETH_ACC_SUCCESS;
-}
-
-/*********************************************************************
- * ixEthAccMiiReadRtn - read a 16 bit value from a PHY
- */
-IxEthAccStatus      
-ixEthAccMiiReadRtn (UINT8 phyAddr, 
-		    UINT8 phyReg, 
-		    UINT16 *value)
-{
-    UINT32 mdioCommand;
-    UINT32 regval;
-    UINT32 miiTimeout;
-
-    if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
-    {
-	return (IX_ETH_ACC_FAIL);
-    }
-
-    if ((phyAddr >= IXP425_ETH_ACC_MII_MAX_ADDR) 
-	|| (phyReg >= IXP425_ETH_ACC_MII_MAX_REG))
-    {
-	return (IX_ETH_ACC_FAIL);
-    }
-
-    if (value == NULL)
-    {
-	return (IX_ETH_ACC_FAIL);
-    }
-
-    ixOsalMutexLock(&miiAccessLock, IX_OSAL_WAIT_FOREVER);
-    mdioCommand = phyReg <<  IX_ETH_ACC_MII_REG_SHL 
-	| phyAddr << IX_ETH_ACC_MII_ADDR_SHL;
-    mdioCommand |= IX_ETH_ACC_MII_GO;
-
-    ixEthAccMdioCmdWrite(mdioCommand);
-    
-    miiTimeout = ixEthAccMiiRetryCount;
-
-    while(miiTimeout)
-    {
-	
-	ixEthAccMdioCmdRead(&regval);
-     
-	if((regval & IX_ETH_ACC_MII_GO) == 0x0)
-	{	    
-	    break;
-	}
-	/* Sleep for a while */
-	ixOsalSleep(ixEthAccMiiAccessTimeout);
-	miiTimeout--;
-    }
-    
-
-    
-    if(miiTimeout == 0)
-    {	
-	ixOsalMutexUnlock(&miiAccessLock);
-	*value = 0xffff;
-	return IX_ETH_ACC_FAIL;
-    }
-    
-    
-    ixEthAccMdioStatusRead(&regval);
-    if(regval & IX_ETH_ACC_MII_READ_FAIL)
-    {
-	ixOsalMutexUnlock(&miiAccessLock);
-	*value = 0xffff;
-	return IX_ETH_ACC_FAIL;
-    }
-
-    *value = regval & 0xffff;
-    ixOsalMutexUnlock(&miiAccessLock);
-    return IX_ETH_ACC_SUCCESS;
-    
-}
-
-
-/*********************************************************************
- * ixEthAccMiiWriteRtn - write a 16 bit value to a PHY
- */
-IxEthAccStatus
-ixEthAccMiiWriteRtn (UINT8 phyAddr, 
-		     UINT8 phyReg, 
-		     UINT16 value)
-{
-    UINT32 mdioCommand;
-    UINT32 regval;
-    UINT16 readVal;
-    UINT32 miiTimeout;
-
-    if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
-    {
-	return (IX_ETH_ACC_FAIL);
-    }
-
-    if ((phyAddr >= IXP425_ETH_ACC_MII_MAX_ADDR) 
-	|| (phyReg >= IXP425_ETH_ACC_MII_MAX_REG))
-    {
-	return (IX_ETH_ACC_FAIL);
-    }
-   
-    /* ensure that a PHY is present at this address */
-    if(ixEthAccMiiReadRtn(phyAddr,
-                          IX_ETH_ACC_MII_CTRL_REG,
-                          &readVal) != IX_ETH_ACC_SUCCESS)
-    {
-        return (IX_ETH_ACC_FAIL);
-    }
-
-    ixOsalMutexLock(&miiAccessLock, IX_OSAL_WAIT_FOREVER);
-    mdioCommand = phyReg << IX_ETH_ACC_MII_REG_SHL
-	| phyAddr << IX_ETH_ACC_MII_ADDR_SHL ;
-    mdioCommand |= IX_ETH_ACC_MII_GO | IX_ETH_ACC_MII_WRITE | value;
-
-    ixEthAccMdioCmdWrite(mdioCommand);
-    
-    miiTimeout = ixEthAccMiiRetryCount;
-
-    while(miiTimeout)
-    {
-	
-	ixEthAccMdioCmdRead(&regval);
-
-	/*The "GO" bit is reset to 0 when the write completes*/
-	if((regval & IX_ETH_ACC_MII_GO) == 0x0)
-	{		    
-	    break;
-	}
-	/* Sleep for a while */
-	ixOsalSleep(ixEthAccMiiAccessTimeout);
-        miiTimeout--;
-    }
-    
-    ixOsalMutexUnlock(&miiAccessLock);
-    if(miiTimeout == 0)
-    {
-	return IX_ETH_ACC_FAIL;
-    }
-    return IX_ETH_ACC_SUCCESS;
-}
-
-
-/*****************************************************************
- *
- *  Phy query functions
- *
- */
-IxEthAccStatus
-ixEthAccMiiStatsShow (UINT32 phyAddr)
-{
-    UINT16 regval;
-    printf("Regisers on PHY at address 0x%x\n", phyAddr);
-    ixEthAccMiiReadRtn(phyAddr, IX_ETH_ACC_MII_CTRL_REG, &regval);
-    printf("    Control Register                  :      0x%4.4x\n", regval);
-    ixEthAccMiiReadRtn(phyAddr,  IX_ETH_ACC_MII_STAT_REG, &regval);
-    printf("    Status Register                   :      0x%4.4x\n", regval);
-    ixEthAccMiiReadRtn(phyAddr,  IX_ETH_ACC_MII_PHY_ID1_REG, &regval);
-    printf("    PHY ID1 Register                  :      0x%4.4x\n", regval);
-    ixEthAccMiiReadRtn(phyAddr,  IX_ETH_ACC_MII_PHY_ID2_REG, &regval);
-    printf("    PHY ID2 Register                  :      0x%4.4x\n", regval);
-    ixEthAccMiiReadRtn(phyAddr,  IX_ETH_ACC_MII_AN_ADS_REG, &regval);
-    printf("    Auto Neg ADS Register             :      0x%4.4x\n", regval);
-    ixEthAccMiiReadRtn(phyAddr,  IX_ETH_ACC_MII_AN_PRTN_REG, &regval);
-    printf("    Auto Neg Partner Ability Register :      0x%4.4x\n", regval);
-    ixEthAccMiiReadRtn(phyAddr,  IX_ETH_ACC_MII_AN_EXP_REG, &regval);
-    printf("    Auto Neg Expansion Register       :      0x%4.4x\n", regval);
-    ixEthAccMiiReadRtn(phyAddr,  IX_ETH_ACC_MII_AN_NEXT_REG, &regval);
-    printf("    Auto Neg Next Register            :      0x%4.4x\n", regval);
-
-    return IX_ETH_ACC_SUCCESS;
-}
-
-
-/*****************************************************************
- *
- *  Interface query functions
- *
- */
-IxEthAccStatus
-ixEthAccMdioShow (void)
-{
-    UINT32 regval;
-
-    if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
-    {
-	return (IX_ETH_ACC_FAIL);
-    }
-
-    ixOsalMutexLock(&miiAccessLock, IX_OSAL_WAIT_FOREVER);
-    ixEthAccMdioCmdRead(&regval);
-    ixOsalMutexUnlock(&miiAccessLock);
-    
-    printf("MDIO command register\n");
-    printf("    Go bit      : 0x%x\n", (regval & BIT(31)) >> 31);
-    printf("    MDIO Write  : 0x%x\n", (regval & BIT(26)) >> 26);
-    printf("    PHY address : 0x%x\n", (regval >> 21) & 0x1f);
-    printf("    Reg address : 0x%x\n", (regval >> 16) & 0x1f);
-	
-    ixOsalMutexLock(&miiAccessLock, IX_OSAL_WAIT_FOREVER);
-    ixEthAccMdioStatusRead(&regval);
-    ixOsalMutexUnlock(&miiAccessLock);
-
-    printf("MDIO status register\n");
-    printf("    Read OK     : 0x%x\n", (regval & BIT(31)) >> 31);
-    printf("    Read Data   : 0x%x\n", (regval >> 16) & 0xff);
-
-    return IX_ETH_ACC_SUCCESS;   
-}
-
diff --git a/arch/arm/cpu/ixp/npe/IxEthDBAPI.c b/arch/arm/cpu/ixp/npe/IxEthDBAPI.c
deleted file mode 100644
index b2bfb72..0000000
--- a/arch/arm/cpu/ixp/npe/IxEthDBAPI.c
+++ /dev/null
@@ -1,448 +0,0 @@
-/**
- * @file IxEthDBAPI.c
- *
- * @brief Implementation of the public API
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- * 
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- * 
- * @par
- * -- End of Copyright Notice --
- */
-
-#include "IxEthDB_p.h"
-#include "IxFeatureCtrl.h"
-
-extern HashTable dbHashtable;
-extern IxEthDBPortMap overflowUpdatePortList;
-extern BOOL ixEthDBPortUpdateRequired[IX_ETH_DB_MAX_RECORD_TYPE_INDEX + 1];
-
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBFilteringStaticEntryProvision(IxEthDBPortId portID, IxEthDBMacAddr *macAddr)
-{
-    IX_ETH_DB_CHECK_PORT(portID);
-    
-    IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-    
-    IX_ETH_DB_CHECK_REFERENCE(macAddr);
-    
-    IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_LEARNING);
-
-    return ixEthDBTriggerAddPortUpdate(macAddr, portID, TRUE);
-}
-    
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBFilteringDynamicEntryProvision(IxEthDBPortId portID, IxEthDBMacAddr *macAddr)
-{
-    IX_ETH_DB_CHECK_PORT(portID);
-    
-    IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-        
-    IX_ETH_DB_CHECK_REFERENCE(macAddr);
-
-    IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_LEARNING);
-
-    return ixEthDBTriggerAddPortUpdate(macAddr, portID, FALSE);
-}
-
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBFilteringEntryDelete(IxEthDBMacAddr *macAddr)
-{
-    HashNode *searchResult;
-
-    IX_ETH_DB_CHECK_REFERENCE(macAddr);
-
-    searchResult = ixEthDBSearch(macAddr, IX_ETH_DB_ALL_FILTERING_RECORDS);
-
-    if (searchResult == NULL)
-    {
-        return IX_ETH_DB_NO_SUCH_ADDR; /* not found */
-    }
-    
-    ixEthDBReleaseHashNode(searchResult);
-    
-    /* build a remove event and place it on the event queue */
-    return ixEthDBTriggerRemovePortUpdate(macAddr, ((MacDescriptor *) searchResult->data)->portID);
-}
-       
-IX_ETH_DB_PUBLIC
-void ixEthDBDatabaseMaintenance()
-{
-    HashIterator iterator;
-    UINT32 portIndex;
-    BOOL agingRequired = FALSE;
-
-    /* ports who will have deleted records and therefore will need updating */
-    IxEthDBPortMap triggerPorts;
-
-    if (IX_FEATURE_CTRL_SWCONFIG_ENABLED !=
-        ixFeatureCtrlSwConfigurationCheck (IX_FEATURECTRL_ETH_LEARNING))
-    {
-        return;
-    }
-
-    SET_EMPTY_DEPENDENCY_MAP(triggerPorts);
-
-    /* check if there's at least a port that needs aging */
-    for (portIndex = 0 ; portIndex < IX_ETH_DB_NUMBER_OF_PORTS ; portIndex++)
-    {
-        if (ixEthDBPortInfo[portIndex].agingEnabled && ixEthDBPortInfo[portIndex].enabled)
-        {
-            agingRequired = TRUE;
-        }
-    }
-
-    if (agingRequired)
-    {
-        /* ask each NPE port to write back the database for aging inspection */
-        for (portIndex = 0 ; portIndex < IX_ETH_DB_NUMBER_OF_PORTS ; portIndex++)
-        {
-            if (ixEthDBPortDefinitions[portIndex].type == IX_ETH_NPE
-                && ixEthDBPortInfo[portIndex].agingEnabled
-                && ixEthDBPortInfo[portIndex].enabled)
-            {
-                IxNpeMhMessage message;
-                IX_STATUS result;
-                
-                /* send EDB_GetMACAddressDatabase message */
-                FILL_GETMACADDRESSDATABASE(message, 
-                    0 /* unused */, 
-                    IX_OSAL_MMU_VIRT_TO_PHYS(ixEthDBPortInfo[portIndex].updateMethod.npeUpdateZone));
-
-                IX_ETHDB_SEND_NPE_MSG(IX_ETH_DB_PORT_ID_TO_NPE(portIndex), message, result);
-
-                if (result == IX_SUCCESS)
-                {
-                    /* analyze NPE copy */
-                    ixEthDBNPESyncScan(portIndex, ixEthDBPortInfo[portIndex].updateMethod.npeUpdateZone, FULL_ELT_BYTE_SIZE);
-
-                    IX_ETH_DB_SUPPORT_TRACE("DB: (API) Finished scanning NPE tree on port %d\n", portIndex);
-                }
-                else
-                {
-                    ixEthDBPortInfo[portIndex].agingEnabled                = FALSE;
-                    ixEthDBPortInfo[portIndex].updateMethod.updateEnabled  = FALSE;
-                    ixEthDBPortInfo[portIndex].updateMethod.userControlled = TRUE;
-
-                    ixOsalLog(IX_OSAL_LOG_LVL_FATAL,
-                        IX_OSAL_LOG_DEV_STDOUT, 
-                        "EthDB: (Maintenance) warning, disabling aging and updates for port %d (assumed dead)\n",
-                        portIndex, 0, 0, 0, 0, 0);
-
-                    ixEthDBDatabaseClear(portIndex, IX_ETH_DB_ALL_RECORD_TYPES);
-                }
-            }
-        }
-
-        /* browse database and age entries */
-        BUSY_RETRY(ixEthDBInitHashIterator(&dbHashtable, &iterator));
-
-        while (IS_ITERATOR_VALID(&iterator))
-        {
-            MacDescriptor *descriptor = (MacDescriptor *) iterator.node->data;
-            UINT32 *age               = NULL;
-            BOOL staticEntry          = TRUE;
-
-            if (descriptor->type == IX_ETH_DB_FILTERING_RECORD)
-            {
-                age         = &descriptor->recordData.filteringData.age;
-                staticEntry = descriptor->recordData.filteringData.staticEntry;
-            }
-            else if (descriptor->type == IX_ETH_DB_FILTERING_VLAN_RECORD)
-            {
-                age         = &descriptor->recordData.filteringVlanData.age;
-                staticEntry = descriptor->recordData.filteringVlanData.staticEntry;
-            }
-            else
-            {
-                staticEntry = TRUE;
-            }
-
-            if (ixEthDBPortInfo[descriptor->portID].agingEnabled && (staticEntry == FALSE))
-            {
-                /* manually increment the age if the port has no such capability */
-                if ((ixEthDBPortDefinitions[descriptor->portID].capabilities & IX_ETH_ENTRY_AGING) == 0)
-                {
-                    *age += (IX_ETH_DB_MAINTENANCE_TIME / 60);
-                }
-
-                /* age entry if it exceeded the maximum time to live */
-                if (*age >= (IX_ETH_DB_LEARNING_ENTRY_AGE_TIME / 60))
-                {
-                    /* add port to the set of update trigger ports */
-                    JOIN_PORT_TO_MAP(triggerPorts, descriptor->portID);
-
-                    /* delete entry */
-                    BUSY_RETRY(ixEthDBRemoveEntryAtHashIterator(&dbHashtable, &iterator));
-                }
-                else
-                {
-                    /* move to the next record */
-                    BUSY_RETRY(ixEthDBIncrementHashIterator(&dbHashtable, &iterator));
-                }
-            }
-            else
-            {
-                /* move to the next record */
-                BUSY_RETRY(ixEthDBIncrementHashIterator(&dbHashtable, &iterator));
-            }
-        }
-
-        /* update ports which lost records */
-        ixEthDBUpdatePortLearningTrees(triggerPorts);
-    }
-}
-
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBDatabaseClear(IxEthDBPortId portID, IxEthDBRecordType recordType)
-{
-    IxEthDBPortMap triggerPorts;
-    HashIterator iterator;
-
-    if (portID >= IX_ETH_DB_NUMBER_OF_PORTS && portID != IX_ETH_DB_ALL_PORTS)
-    {
-        return IX_ETH_DB_INVALID_PORT;
-    }
-
-    /* check if the user passes some extra bits */
-    if ((recordType | IX_ETH_DB_ALL_RECORD_TYPES) != IX_ETH_DB_ALL_RECORD_TYPES)
-    {
-        return IX_ETH_DB_INVALID_ARG;
-    }
-
-    SET_EMPTY_DEPENDENCY_MAP(triggerPorts);
-    
-    /* browse database and age entries */
-    BUSY_RETRY(ixEthDBInitHashIterator(&dbHashtable, &iterator));
-
-    while (IS_ITERATOR_VALID(&iterator))
-    {
-        MacDescriptor *descriptor = (MacDescriptor *) iterator.node->data;
-
-        if (((descriptor->portID == portID) || (portID == IX_ETH_DB_ALL_PORTS))
-            && ((descriptor->type & recordType) != 0))
-        {
-            /* add to trigger if automatic updates are required */
-            if (ixEthDBPortUpdateRequired[descriptor->type])
-            {
-                /* add port to the set of update trigger ports */
-                JOIN_PORT_TO_MAP(triggerPorts, descriptor->portID);
-            }
-
-            /* delete entry */
-            BUSY_RETRY(ixEthDBRemoveEntryAtHashIterator(&dbHashtable, &iterator));
-        }
-        else
-        {
-            /* move to the next record */
-            BUSY_RETRY(ixEthDBIncrementHashIterator(&dbHashtable, &iterator));
-        }
-    }
-
-    /* update ports which lost records */
-    ixEthDBUpdatePortLearningTrees(triggerPorts);
-    
-    return IX_ETH_DB_SUCCESS;
-}
-
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBFilteringPortSearch(IxEthDBPortId portID, IxEthDBMacAddr *macAddr)
-{
-    HashNode *searchResult;
-    IxEthDBStatus result = IX_ETH_DB_NO_SUCH_ADDR;
-
-    IX_ETH_DB_CHECK_PORT(portID);
-    
-    IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-    
-    IX_ETH_DB_CHECK_REFERENCE(macAddr);
-
-    IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_LEARNING);
-
-    searchResult = ixEthDBSearch(macAddr, IX_ETH_DB_ALL_FILTERING_RECORDS);
-
-    if (searchResult == NULL)
-    {
-        return IX_ETH_DB_NO_SUCH_ADDR; /* not found */
-    }
-
-    if (((MacDescriptor *) (searchResult->data))->portID == portID)
-    {
-        result = IX_ETH_DB_SUCCESS; /* address and port match */
-    }
-
-    ixEthDBReleaseHashNode(searchResult);
-
-    return result;
-}
-
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBFilteringDatabaseSearch(IxEthDBPortId *portID, IxEthDBMacAddr *macAddr)
-{
-    HashNode *searchResult;
-
-    IX_ETH_DB_CHECK_REFERENCE(portID);
-    
-    IX_ETH_DB_CHECK_REFERENCE(macAddr);
-
-    searchResult = ixEthDBSearch(macAddr, IX_ETH_DB_ALL_FILTERING_RECORDS);
-
-    if (searchResult == NULL)
-    {
-        return IX_ETH_DB_NO_SUCH_ADDR; /* not found */
-    }
-
-    /* return the port ID */
-    *portID = ((MacDescriptor *) searchResult->data)->portID;
-
-    ixEthDBReleaseHashNode(searchResult);
-
-    return IX_ETH_DB_SUCCESS;
-}
-
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBPortAgingDisable(IxEthDBPortId portID)
-{
-    IX_ETH_DB_CHECK_PORT(portID);
-
-    IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
-    IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_LEARNING);
-
-    ixEthDBPortInfo[portID].agingEnabled = FALSE;
-
-    return IX_ETH_DB_SUCCESS;
-}
-
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBPortAgingEnable(IxEthDBPortId portID)
-{
-    IX_ETH_DB_CHECK_PORT(portID);
-
-    IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
-    IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_LEARNING);
-
-    ixEthDBPortInfo[portID].agingEnabled = TRUE;
-
-    return IX_ETH_DB_SUCCESS;
-}
-
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBFilteringPortUpdatingSearch(IxEthDBPortId *portID, IxEthDBMacAddr *macAddr)
-{
-    HashNode *searchResult;
-    MacDescriptor *descriptor;
-
-    IX_ETH_DB_CHECK_REFERENCE(portID);
-    
-    IX_ETH_DB_CHECK_REFERENCE(macAddr);
-
-    searchResult = ixEthDBSearch(macAddr, IX_ETH_DB_ALL_FILTERING_RECORDS);
-
-    if (searchResult == NULL)
-    {
-        return IX_ETH_DB_NO_SUCH_ADDR; /* not found */
-    }
-    
-    descriptor = (MacDescriptor *) searchResult->data;
-
-    /* return the port ID */
-    *portID = descriptor->portID;
-
-    /* reset entry age */
-    if (descriptor->type == IX_ETH_DB_FILTERING_RECORD)
-    {
-        descriptor->recordData.filteringData.age = 0;
-    }
-    else
-    {
-        descriptor->recordData.filteringVlanData.age = 0;
-    }
-
-    ixEthDBReleaseHashNode(searchResult);
-
-    return IX_ETH_DB_SUCCESS;
-}
-
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBPortDependencyMapSet(IxEthDBPortId portID, IxEthDBPortMap dependencyPortMap)
-{
-    IX_ETH_DB_CHECK_PORT(portID);
-    
-    IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-    
-    IX_ETH_DB_CHECK_REFERENCE(dependencyPortMap);
-    
-    IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_FILTERING);
-
-    /* force bit at offset 255 to 0 (reserved) */
-    dependencyPortMap[31] &= 0xFE;
-
-    COPY_DEPENDENCY_MAP(ixEthDBPortInfo[portID].dependencyPortMap, dependencyPortMap);
-
-    return IX_ETH_DB_SUCCESS;
-}
-
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBPortDependencyMapGet(IxEthDBPortId portID, IxEthDBPortMap dependencyPortMap)
-{
-    IX_ETH_DB_CHECK_PORT(portID);
-    
-    IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-    
-    IX_ETH_DB_CHECK_REFERENCE(dependencyPortMap);
-    
-    IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_FILTERING);
-
-    COPY_DEPENDENCY_MAP(dependencyPortMap, ixEthDBPortInfo[portID].dependencyPortMap);
-
-    return IX_ETH_DB_SUCCESS;
-}
-
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBPortUpdateEnableSet(IxEthDBPortId portID, BOOL enableUpdate)
-{
-    IX_ETH_DB_CHECK_PORT(portID);
-
-    IX_ETH_DB_CHECK_SINGLE_NPE(portID);    
-
-    IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_FILTERING);
-
-    ixEthDBPortInfo[portID].updateMethod.updateEnabled  = enableUpdate;
-    ixEthDBPortInfo[portID].updateMethod.userControlled = TRUE;
-
-    return IX_ETH_DB_SUCCESS;
-}
diff --git a/arch/arm/cpu/ixp/npe/IxEthDBAPISupport.c b/arch/arm/cpu/ixp/npe/IxEthDBAPISupport.c
deleted file mode 100644
index 25633a3..0000000
--- a/arch/arm/cpu/ixp/npe/IxEthDBAPISupport.c
+++ /dev/null
@@ -1,678 +0,0 @@
-/**
- * @file IxEthDBAPISupport.c
- *
- * @brief Public API support functions
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
- */
-
-#include <IxEthDB.h>
-#include <IxNpeMh.h>
-#include <IxFeatureCtrl.h>
-
-#include "IxEthDB_p.h"
-#include "IxEthDBMessages_p.h"
-#include "IxEthDB_p.h"
-#include "IxEthDBLog_p.h"
-
-#ifdef IX_UNIT_TEST
-
-int dbAccessCounter = 0;
-int overflowEvent   = 0;
-
-#endif
-
-/*
- * External declaration
- */
-extern HashTable dbHashtable;
-
-/*
- * Internal declaration
- */
-IX_ETH_DB_PUBLIC
-PortInfo ixEthDBPortInfo[IX_ETH_DB_NUMBER_OF_PORTS];
-
-IX_ETH_DB_PRIVATE
-struct
-{
-    BOOL saved;
-    IxEthDBPriorityTable priorityTable;
-    IxEthDBVlanSet vlanMembership;
-    IxEthDBVlanSet transmitTaggingInfo;
-    IxEthDBFrameFilter frameFilter;
-    IxEthDBTaggingAction taggingAction;
-    IxEthDBFirewallMode firewallMode;
-    BOOL stpBlocked;
-    BOOL srcAddressFilterEnabled;
-    UINT32 maxRxFrameSize;
-    UINT32 maxTxFrameSize;
-} ixEthDBPortState[IX_ETH_DB_NUMBER_OF_PORTS];
-
-#define IX_ETH_DB_DEFAULT_FRAME_SIZE (1518)
-
-/**
- * @brief initializes a port
- *
- * @param portID ID of the port to be initialized
- *
- * Note that redundant initializations are silently
- * dealt with and do not constitute an error
- *
- * This function is fully documented in the main
- * header file, IxEthDB.h
- */
-IX_ETH_DB_PUBLIC
-void ixEthDBPortInit(IxEthDBPortId portID)
-{
-    PortInfo *portInfo;
-
-    if (portID >= IX_ETH_DB_NUMBER_OF_PORTS)
-    {
-        return;
-    }
-
-    portInfo = &ixEthDBPortInfo[portID];
-
-    if (ixEthDBSingleEthNpeCheck(portID) != IX_ETH_DB_SUCCESS)
-    {
-        WARNING_LOG("EthDB: Unavailable Eth %d: Cannot initialize EthDB Port.\n", (UINT32) portID);
-
-        return;
-    }
-
-    if (portInfo->initialized)
-    {
-        /* redundant */
-        return;
-    }
-
-    /* initialize core fields */
-    portInfo->portID = portID;
-    SET_DEPENDENCY_MAP(portInfo->dependencyPortMap, portID);
-
-    /* default values */
-    portInfo->agingEnabled       = FALSE;
-    portInfo->enabled            = FALSE;
-    portInfo->macAddressUploaded = FALSE;
-    portInfo->maxRxFrameSize     = IX_ETHDB_DEFAULT_FRAME_SIZE;
-    portInfo->maxTxFrameSize     = IX_ETHDB_DEFAULT_FRAME_SIZE;
-
-    /* default update control values */
-    portInfo->updateMethod.searchTree              = NULL;
-    portInfo->updateMethod.searchTreePendingWrite  = FALSE;
-    portInfo->updateMethod.treeInitialized         = FALSE;
-    portInfo->updateMethod.updateEnabled           = FALSE;
-    portInfo->updateMethod.userControlled          = FALSE;
-
-    /* default WiFi parameters */
-    memset(portInfo->bbsid, 0, sizeof (portInfo->bbsid));
-    portInfo->frameControlDurationID = 0;
-
-    /* Ethernet NPE-specific initializations */
-    if (ixEthDBPortDefinitions[portID].type == IX_ETH_NPE)
-    {
-        /* update handler */
-        portInfo->updateMethod.updateHandler = ixEthDBNPEUpdateHandler;
-    }
-
-    /* initialize state save */
-    ixEthDBPortState[portID].saved = FALSE;
-
-    portInfo->initialized = TRUE;
-}
-
-/**
- * @brief enables a port
- *
- * @param portID ID of the port to enable
- *
- * This function is fully documented in the main
- * header file, IxEthDB.h
- *
- * @return IX_ETH_DB_SUCCESS if enabling was
- * accomplished, or a meaningful error message otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBPortEnable(IxEthDBPortId portID)
-{
-    IxEthDBPortMap triggerPorts;
-    PortInfo *portInfo;
-
-    IX_ETH_DB_CHECK_PORT_EXISTS(portID);
-
-    IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
-    portInfo = &ixEthDBPortInfo[portID];
-
-    if (portInfo->enabled)
-    {
-        /* redundant */
-        return IX_ETH_DB_SUCCESS;
-    }
-
-    SET_DEPENDENCY_MAP(triggerPorts, portID);
-
-    /* mark as enabled */
-    portInfo->enabled = TRUE;
-
-    /* Operation stops here when Ethernet Learning is not enabled */
-    if(IX_FEATURE_CTRL_SWCONFIG_DISABLED ==
-       ixFeatureCtrlSwConfigurationCheck(IX_FEATURECTRL_ETH_LEARNING))
-    {
-        return IX_ETH_DB_SUCCESS;
-    }
-
-    if (ixEthDBPortDefinitions[portID].type == IX_ETH_NPE && !portInfo->macAddressUploaded)
-    {
-        IX_ETH_DB_SUPPORT_TRACE("DB: (Support) MAC address not set on port %d, enable failed\n", portID);
-
-        /* must use UnicastAddressSet() before enabling an NPE port */
-        return IX_ETH_DB_MAC_UNINITIALIZED;
-    }
-
-    if (ixEthDBPortDefinitions[portID].type == IX_ETH_NPE)
-    {
-        IX_ETH_DB_SUPPORT_TRACE("DB: (Support) Attempting to enable the NPE callback for port %d...\n", portID);
-
-        if (!portInfo->updateMethod.userControlled
-                && ((portInfo->featureCapability & IX_ETH_DB_FILTERING) != 0))
-        {
-            portInfo->updateMethod.updateEnabled = TRUE;
-        }
-
-        /* if this is first time initialization then we already have
-           write access to the tree and can AccessRelease directly */
-        if (!portInfo->updateMethod.treeInitialized)
-        {
-            IX_ETH_DB_SUPPORT_TRACE("DB: (Support) Initializing tree for port %d\n", portID);
-
-            /* create an initial tree and release access into it */
-            ixEthDBUpdatePortLearningTrees(triggerPorts);
-
-            /* mark tree as being initialized */
-            portInfo->updateMethod.treeInitialized = TRUE;
-        }
-    }
-
-    if (ixEthDBPortState[portID].saved)
-    {
-        /* previous configuration data stored, restore state */
-        if ((portInfo->featureCapability & IX_ETH_DB_FIREWALL) != 0)
-        {
-            ixEthDBFirewallModeSet(portID, ixEthDBPortState[portID].firewallMode);
-            ixEthDBFirewallInvalidAddressFilterEnable(portID, ixEthDBPortState[portID].srcAddressFilterEnabled);
-        }
-
-#if 0 /* test-only */
-        if ((portInfo->featureCapability & IX_ETH_DB_VLAN_QOS) != 0)
-        {
-            ixEthDBAcceptableFrameTypeSet(portID, ixEthDBPortState[portID].frameFilter);
-            ixEthDBIngressVlanTaggingEnabledSet(portID, ixEthDBPortState[portID].taggingAction);
-
-            ixEthDBEgressVlanTaggingEnabledSet(portID, ixEthDBPortState[portID].transmitTaggingInfo);
-            ixEthDBPortVlanMembershipSet(portID, ixEthDBPortState[portID].vlanMembership);
-
-            ixEthDBPriorityMappingTableSet(portID, ixEthDBPortState[portID].priorityTable);
-        }
-#endif
-
-        if ((portInfo->featureCapability & IX_ETH_DB_SPANNING_TREE_PROTOCOL) != 0)
-        {
-            ixEthDBSpanningTreeBlockingStateSet(portID, ixEthDBPortState[portID].stpBlocked);
-        }
-
-        ixEthDBFilteringPortMaximumRxFrameSizeSet(portID, ixEthDBPortState[portID].maxRxFrameSize);
-        ixEthDBFilteringPortMaximumTxFrameSizeSet(portID, ixEthDBPortState[portID].maxTxFrameSize);
-
-        /* discard previous save */
-        ixEthDBPortState[portID].saved = FALSE;
-    }
-
-    IX_ETH_DB_SUPPORT_TRACE("DB: (Support) Enabling succeeded for port %d\n", portID);
-
-    return IX_ETH_DB_SUCCESS;
-}
-
-/**
- * @brief disables a port
- *
- * @param portID ID of the port to disable
- *
- * This function is fully documented in the
- * main header file, IxEthDB.h
- *
- * @return IX_ETH_DB_SUCCESS if disabling was
- * successful or an appropriate error message
- * otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBPortDisable(IxEthDBPortId portID)
-{
-    HashIterator iterator;
-    IxEthDBPortMap triggerPorts; /* ports who will have deleted records and therefore will need updating */
-    BOOL result;
-    PortInfo *portInfo;
-    IxEthDBFeature learningEnabled;
-#if 0 /* test-only */
-    IxEthDBPriorityTable classZeroTable;
-#endif
-
-    IX_ETH_DB_CHECK_PORT_EXISTS(portID);
-
-    IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
-    portInfo = &ixEthDBPortInfo[portID];
-
-    if (!portInfo->enabled)
-    {
-        /* redundant */
-        return IX_ETH_DB_SUCCESS;
-    }
-
-    if (ixEthDBPortDefinitions[portID].type == IX_ETH_NPE)
-    {
-        /* save filtering state */
-        ixEthDBPortState[portID].firewallMode            = portInfo->firewallMode;
-        ixEthDBPortState[portID].frameFilter             = portInfo->frameFilter;
-        ixEthDBPortState[portID].taggingAction           = portInfo->taggingAction;
-        ixEthDBPortState[portID].stpBlocked              = portInfo->stpBlocked;
-        ixEthDBPortState[portID].srcAddressFilterEnabled = portInfo->srcAddressFilterEnabled;
-        ixEthDBPortState[portID].maxRxFrameSize          = portInfo->maxRxFrameSize;
-        ixEthDBPortState[portID].maxTxFrameSize          = portInfo->maxTxFrameSize;
-
-        memcpy(ixEthDBPortState[portID].vlanMembership, portInfo->vlanMembership, sizeof (IxEthDBVlanSet));
-        memcpy(ixEthDBPortState[portID].transmitTaggingInfo, portInfo->transmitTaggingInfo, sizeof (IxEthDBVlanSet));
-        memcpy(ixEthDBPortState[portID].priorityTable, portInfo->priorityTable, sizeof (IxEthDBPriorityTable));
-
-        ixEthDBPortState[portID].saved = TRUE;
-
-        /* now turn off all EthDB filtering features on the port */
-
-#if 0 /* test-only */
-        /* VLAN & QoS */
-        if ((portInfo->featureCapability & IX_ETH_DB_VLAN_QOS) != 0)
-        {
-            ixEthDBPortVlanMembershipRangeAdd((IxEthDBPortId) portID, 0, IX_ETH_DB_802_1Q_MAX_VLAN_ID);
-            ixEthDBEgressVlanRangeTaggingEnabledSet((IxEthDBPortId) portID, 0, IX_ETH_DB_802_1Q_MAX_VLAN_ID, FALSE);
-            ixEthDBAcceptableFrameTypeSet((IxEthDBPortId) portID, IX_ETH_DB_ACCEPT_ALL_FRAMES);
-            ixEthDBIngressVlanTaggingEnabledSet((IxEthDBPortId) portID, IX_ETH_DB_PASS_THROUGH);
-
-            memset(classZeroTable, 0, sizeof (classZeroTable));
-            ixEthDBPriorityMappingTableSet((IxEthDBPortId) portID, classZeroTable);
-        }
-#endif
-
-        /* STP */
-        if ((portInfo->featureCapability & IX_ETH_DB_SPANNING_TREE_PROTOCOL) != 0)
-        {
-            ixEthDBSpanningTreeBlockingStateSet((IxEthDBPortId) portID, FALSE);
-        }
-
-        /* Firewall */
-        if ((portInfo->featureCapability & IX_ETH_DB_FIREWALL) != 0)
-        {
-            ixEthDBFirewallModeSet((IxEthDBPortId) portID, IX_ETH_DB_FIREWALL_BLACK_LIST);
-            ixEthDBFirewallTableDownload((IxEthDBPortId) portID);
-            ixEthDBFirewallInvalidAddressFilterEnable((IxEthDBPortId) portID, FALSE);
-        }
-
-        /* Frame size filter */
-        ixEthDBFilteringPortMaximumFrameSizeSet((IxEthDBPortId) portID, IX_ETH_DB_DEFAULT_FRAME_SIZE);
-
-        /* WiFi */
-        if ((portInfo->featureCapability & IX_ETH_DB_WIFI_HEADER_CONVERSION) != 0)
-        {
-            ixEthDBWiFiConversionTableDownload((IxEthDBPortId) portID);
-        }
-
-        /* save and disable the learning feature bit */
-        learningEnabled          = portInfo->featureStatus & IX_ETH_DB_LEARNING;
-        portInfo->featureStatus &= ~IX_ETH_DB_LEARNING;
-    }
-    else
-    {
-        /* save the learning feature bit */
-        learningEnabled          = portInfo->featureStatus & IX_ETH_DB_LEARNING;
-    }
-
-    SET_EMPTY_DEPENDENCY_MAP(triggerPorts);
-
-    ixEthDBUpdateLock();
-
-    /* wipe out current entries for this port */
-    BUSY_RETRY(ixEthDBInitHashIterator(&dbHashtable, &iterator));
-
-    while (IS_ITERATOR_VALID(&iterator))
-    {
-        MacDescriptor *descriptor =  (MacDescriptor *) iterator.node->data;
-
-        /* check if the port match. If so, remove the entry  */
-        if (descriptor->portID == portID
-                && (descriptor->type == IX_ETH_DB_FILTERING_RECORD || descriptor->type == IX_ETH_DB_FILTERING_VLAN_RECORD)
-                && !descriptor->recordData.filteringData.staticEntry)
-        {
-            /* delete entry */
-            BUSY_RETRY(ixEthDBRemoveEntryAtHashIterator(&dbHashtable, &iterator));
-
-            /* add port to the set of update trigger ports */
-            JOIN_PORT_TO_MAP(triggerPorts, portID);
-        }
-        else
-        {
-            /* move to the next record */
-            BUSY_RETRY(ixEthDBIncrementHashIterator(&dbHashtable, &iterator));
-        }
-    }
-
-    if (ixEthDBPortDefinitions[portID].type == IX_ETH_NPE)
-    {
-        if (portInfo->updateMethod.searchTree != NULL)
-        {
-            ixEthDBFreeMacTreeNode(portInfo->updateMethod.searchTree);
-            portInfo->updateMethod.searchTree = NULL;
-        }
-
-        ixEthDBNPEUpdateHandler(portID, IX_ETH_DB_FILTERING_RECORD);
-    }
-
-    /* mark as disabled */
-    portInfo->enabled = FALSE;
-
-    /* disable updates unless the user has specifically altered the default behavior */
-    if (ixEthDBPortDefinitions[portID].type == IX_ETH_NPE)
-    {
-        if (!portInfo->updateMethod.userControlled)
-        {
-            portInfo->updateMethod.updateEnabled = FALSE;
-        }
-
-        /* make sure we re-initialize the NPE learning tree when the port is re-enabled */
-        portInfo->updateMethod.treeInitialized = FALSE;
-    }
-
-    ixEthDBUpdateUnlock();
-
-    /* restore learning feature bit */
-    portInfo->featureStatus |= learningEnabled;
-
-    /* if we've removed any records or lost any events make sure to force an update */
-    IS_EMPTY_DEPENDENCY_MAP(result, triggerPorts);
-
-    if (!result)
-    {
-        ixEthDBUpdatePortLearningTrees(triggerPorts);
-    }
-
-    return IX_ETH_DB_SUCCESS;
-}
-
-/**
- * @brief sends the updated maximum Tx/Rx frame lengths to the NPE
- *
- * @param portID ID of the port to update
- *
- * @return IX_ETH_DB_SUCCESS if the update completed
- * successfully or an appropriate error message otherwise
- *
- * @internal
- */
-IX_ETH_DB_PRIVATE
-IxEthDBStatus ixEthDBPortFrameLengthsUpdate(IxEthDBPortId portID)
-{
-    IxNpeMhMessage message;
-    PortInfo *portInfo = &ixEthDBPortInfo[portID];
-    IX_STATUS result;
-
-    FILL_SETMAXFRAMELENGTHS_MSG(message, portID, portInfo->maxRxFrameSize, portInfo->maxTxFrameSize);
-
-    IX_ETHDB_SEND_NPE_MSG(IX_ETH_DB_PORT_ID_TO_NPE(portID), message, result);
-
-    return result;
-}
-
-/**
- * @brief sets the port maximum Rx frame size
- *
- * @param portID ID of the port to set the frame size on
- * @param maximumRxFrameSize maximum Rx frame size
- *
- * This function updates the internal data structures and
- * calls ixEthDBPortFrameLengthsUpdate() for NPE update.
- *
- * This function is fully documented in the main header
- * file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation was
- * successfull or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBFilteringPortMaximumRxFrameSizeSet(IxEthDBPortId portID, UINT32 maximumRxFrameSize)
-{
-    IX_ETH_DB_CHECK_PORT_EXISTS(portID);
-
-    IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
-	if (!ixEthDBPortInfo[portID].initialized)
-	{
-		return IX_ETH_DB_PORT_UNINITIALIZED;
-	}
-
-    if (ixEthDBPortDefinitions[portID].type == IX_ETH_NPE)
-    {
-	if ((maximumRxFrameSize < IX_ETHDB_MIN_NPE_FRAME_SIZE) ||
-	    (maximumRxFrameSize > IX_ETHDB_MAX_NPE_FRAME_SIZE))
-	{
-	    return IX_ETH_DB_INVALID_ARG;
-	}
-    }
-    else
-    {
-        return IX_ETH_DB_NO_PERMISSION;
-    }
-
-    /* update internal structure */
-    ixEthDBPortInfo[portID].maxRxFrameSize = maximumRxFrameSize;
-
-    /* update the maximum frame size in the NPE */
-    return ixEthDBPortFrameLengthsUpdate(portID);
-}
-
-/**
- * @brief sets the port maximum Tx frame size
- *
- * @param portID ID of the port to set the frame size on
- * @param maximumTxFrameSize maximum Tx frame size
- *
- * This function updates the internal data structures and
- * calls ixEthDBPortFrameLengthsUpdate() for NPE update.
- *
- * This function is fully documented in the main header
- * file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation was
- * successfull or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBFilteringPortMaximumTxFrameSizeSet(IxEthDBPortId portID, UINT32 maximumTxFrameSize)
-{
-    IX_ETH_DB_CHECK_PORT_EXISTS(portID);
-
-    IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
-	if (!ixEthDBPortInfo[portID].initialized)
-	{
-		return IX_ETH_DB_PORT_UNINITIALIZED;
-	}
-
-    if (ixEthDBPortDefinitions[portID].type == IX_ETH_NPE)
-    {
-	if ((maximumTxFrameSize < IX_ETHDB_MIN_NPE_FRAME_SIZE) ||
-	    (maximumTxFrameSize > IX_ETHDB_MAX_NPE_FRAME_SIZE))
-	{
-	    return IX_ETH_DB_INVALID_ARG;
-	}
-    }
-    else
-    {
-        return IX_ETH_DB_NO_PERMISSION;
-    }
-
-    /* update internal structure */
-    ixEthDBPortInfo[portID].maxTxFrameSize = maximumTxFrameSize;
-
-    /* update the maximum frame size in the NPE */
-    return ixEthDBPortFrameLengthsUpdate(portID);
-}
-
-/**
- * @brief sets the port maximum Tx and Rx frame sizes
- *
- * @param portID ID of the port to set the frame size on
- * @param maximumFrameSize maximum Tx and Rx frame sizes
- *
- * This function updates the internal data structures and
- * calls ixEthDBPortFrameLengthsUpdate() for NPE update.
- *
- * Note that both the maximum Tx and Rx frame size are set
- * to the same value. This function is kept for compatibility
- * reasons.
- *
- * This function is fully documented in the main header
- * file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation was
- * successfull or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBFilteringPortMaximumFrameSizeSet(IxEthDBPortId portID, UINT32 maximumFrameSize)
-{
-    IX_ETH_DB_CHECK_PORT_EXISTS(portID);
-
-    IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
-    if (!ixEthDBPortInfo[portID].initialized)
-    {
-        return IX_ETH_DB_PORT_UNINITIALIZED;
-    }
-
-    if (ixEthDBPortDefinitions[portID].type == IX_ETH_NPE)
-    {
-	if ((maximumFrameSize < IX_ETHDB_MIN_NPE_FRAME_SIZE) ||
-	    (maximumFrameSize > IX_ETHDB_MAX_NPE_FRAME_SIZE))
-	{
-	    return IX_ETH_DB_INVALID_ARG;
-	}
-    }
-    else
-    {
-        return IX_ETH_DB_NO_PERMISSION;
-    }
-
-    /* update internal structure */
-    ixEthDBPortInfo[portID].maxRxFrameSize = maximumFrameSize;
-    ixEthDBPortInfo[portID].maxTxFrameSize = maximumFrameSize;
-
-    /* update the maximum frame size in the NPE */
-    return ixEthDBPortFrameLengthsUpdate(portID);
-}
-
-/**
- * @brief sets the MAC address of an NPE port
- *
- * @param portID port ID to set the MAC address on
- * @param macAddr pointer to the 6-byte MAC address
- *
- * This function is called by the EthAcc
- * ixEthAccUnicastMacAddressSet() and should not be
- * manually invoked unless required by special circumstances.
- *
- * @return IX_ETH_DB_SUCCESS if the operation succeeded
- * or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBPortAddressSet(IxEthDBPortId portID, IxEthDBMacAddr *macAddr)
-{
-    IxNpeMhMessage message;
-    IxOsalMutex *ackPortAddressLock;
-    IX_STATUS result;
-
-    /* use this macro instead CHECK_PORT
-       as the port doesn't need to be enabled */
-    IX_ETH_DB_CHECK_PORT_EXISTS(portID);
-
-    IX_ETH_DB_CHECK_REFERENCE(macAddr);
-
-    if (!ixEthDBPortInfo[portID].initialized)
-    {
-        return IX_ETH_DB_PORT_UNINITIALIZED;
-    }
-
-    ackPortAddressLock = &ixEthDBPortInfo[portID].npeAckLock;
-
-    /* Operation stops here when Ethernet Learning is not enabled */
-    if(IX_FEATURE_CTRL_SWCONFIG_DISABLED ==
-       ixFeatureCtrlSwConfigurationCheck(IX_FEATURECTRL_ETH_LEARNING))
-    {
-        return IX_ETH_DB_SUCCESS;
-    }
-
-    IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
-    /* exit if the port is not an Ethernet NPE */
-    if (ixEthDBPortDefinitions[portID].type != IX_ETH_NPE)
-    {
-        return IX_ETH_DB_INVALID_PORT;
-    }
-
-    /* populate message */
-    FILL_SETPORTADDRESS_MSG(message, portID, macAddr->macAddress);
-
-    IX_ETH_DB_SUPPORT_TRACE("DB: (Support) Sending SetPortAddress on port %d...\n", portID);
-
-    /* send a SetPortAddress message */
-    IX_ETHDB_SEND_NPE_MSG(IX_ETH_DB_PORT_ID_TO_NPE(portID), message, result);
-
-    if (result == IX_SUCCESS)
-    {
-        ixEthDBPortInfo[portID].macAddressUploaded = TRUE;
-    }
-
-    return result;
-}
diff --git a/arch/arm/cpu/ixp/npe/IxEthDBCore.c b/arch/arm/cpu/ixp/npe/IxEthDBCore.c
deleted file mode 100644
index 25b7cbb..0000000
--- a/arch/arm/cpu/ixp/npe/IxEthDBCore.c
+++ /dev/null
@@ -1,463 +0,0 @@
-/**
- * @file IxEthDBDBCore.c
- *
- * @brief Database support functions
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
- */
-
-#include "IxEthDB_p.h"
-
-/* list of database hashtables */
-IX_ETH_DB_PUBLIC HashTable dbHashtable;
-IX_ETH_DB_PUBLIC MatchFunction matchFunctions[IX_ETH_DB_MAX_KEY_INDEX + 1];
-IX_ETH_DB_PUBLIC BOOL ixEthDBPortUpdateRequired[IX_ETH_DB_MAX_RECORD_TYPE_INDEX + 1];
-IX_ETH_DB_PUBLIC UINT32 ixEthDBKeyType[IX_ETH_DB_MAX_RECORD_TYPE_INDEX + 1];
-
-/* private initialization flag */
-IX_ETH_DB_PRIVATE BOOL ethDBInitializationComplete = FALSE;
-
-/**
- * @brief initializes EthDB
- *
- * This function must be called to initialize the component.
- *
- * It does the following things:
- * - checks the port definition structure
- * - scans the capabilities of the NPE images and sets the
- *   capabilities of the ports accordingly
- * - initializes the memory pools internally used in EthDB
- *   for storing database records and handling data
- * - registers automatic update handlers for add and remove
- *   operations
- * - registers hashing match functions, depending on key sets
- * - initializes the main database hashtable
- * - allocates contiguous memory zones to be used for NPE
- *   updates
- * - registers the serialize methods used to convert data
- *   into NPE-readable format
- * - starts the event processor
- *
- * Note that this function is documented in the public
- * component header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS or an appropriate error if the
- * component failed to initialize correctly
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBInit(void)
-{
-    IxEthDBStatus result;
-
-    if (ethDBInitializationComplete)
-    {
-        /* redundant */
-        return IX_ETH_DB_SUCCESS;
-    }
-
-    /* trap an invalid port definition structure */
-    IX_ETH_DB_PORTS_ASSERTION;
-
-    /* memory management */
-    ixEthDBInitMemoryPools();
-
-    /* register hashing search methods */
-    ixEthDBMatchMethodsRegister(matchFunctions);
-
-    /* register type-based automatic port updates */
-    ixEthDBUpdateTypeRegister(ixEthDBPortUpdateRequired);
-
-    /* register record to key type mappings */
-    ixEthDBKeyTypeRegister(ixEthDBKeyType);
-
-    /* hash table */
-    ixEthDBInitHash(&dbHashtable, NUM_BUCKETS, ixEthDBEntryXORHash, matchFunctions, (FreeFunction) ixEthDBFreeMacDescriptor);
-
-    /* NPE update zones */
-    ixEthDBNPEUpdateAreasInit();
-
-    /* register record serialization methods */
-    ixEthDBRecordSerializeMethodsRegister();
-
-    /* start the event processor */
-    result = ixEthDBEventProcessorInit();
-
-    /* scan NPE features */
-    if (result == IX_ETH_DB_SUCCESS)
-    {
-        ixEthDBFeatureCapabilityScan();
-    }
-
-    ethDBInitializationComplete = TRUE;
-
-    return result;
-}
-
-/**
- * @brief prepares EthDB for unloading
- *
- * This function must be called before removing the
- * EthDB component from memory (e.g. doing rmmod in
- * Linux) if the component is to be re-initialized again
- * without rebooting the platform.
- *
- * All the EthDB ports must be disabled before this
- * function is to be called. Failure to disable all
- * the ports will return the IX_ETH_DB_BUSY error.
- *
- * This function will destroy mutexes, deallocate
- * memory and stop the event processor.
- *
- * Note that this function is fully documented in the
- * main component header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if de-initialization
- * completed successfully or an appropriate error
- * message otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBUnload(void)
-{
-    IxEthDBPortId portIndex;
-
-    if (!ethDBInitializationComplete)
-    {
-        /* redundant */
-        return IX_ETH_DB_SUCCESS;
-    }
-
-    /* check if any ports are enabled */
-    for (portIndex = 0 ; portIndex < IX_ETH_DB_NUMBER_OF_PORTS ; portIndex++)
-    {
-        if (ixEthDBPortInfo[portIndex].enabled)
-        {
-            return IX_ETH_DB_BUSY;
-        }
-    }
-
-    /* free port resources */
-    for (portIndex = 0 ; portIndex < IX_ETH_DB_NUMBER_OF_PORTS ; portIndex++)
-    {
-        if (ixEthDBPortDefinitions[portIndex].type == IX_ETH_NPE)
-        {
-            ixOsalMutexDestroy(&ixEthDBPortInfo[portIndex].npeAckLock);
-        }
-
-        ixEthDBPortInfo[portIndex].initialized = FALSE;
-    }
-
-    /* shutdown event processor */
-    ixEthDBStopLearningFunction();
-
-    /* deallocate NPE update zones */
-    ixEthDBNPEUpdateAreasUnload();
-
-    ethDBInitializationComplete = FALSE;
-
-    return IX_ETH_DB_SUCCESS;
-}
-
-/**
- * @brief adds a new entry to the Ethernet database
- *
- * @param newRecordTemplate address of the record template to use
- * @param updateTrigger port map containing the update triggers
- * resulting from this update operation
- *
- * Creates a new database entry, populates it with the data
- * copied from the given template and adds the record to the
- * database hash table.
- * It also checks whether the new record type is registered to trigger
- * automatic updates; if it is, the update trigger will contain the
- * port on which the record insertion was performed, as well as the
- * old port in case the addition was a record migration (from one port
- * to the other). The caller can use the updateTrigger to trigger
- * automatic updates on the ports changed as a result of this addition.
- *
- * @retval IX_ETH_DB_SUCCESS addition successful
- * @retval IX_ETH_DB_NOMEM insertion failed, no memory left in the mac descriptor memory pool
- * @retval IX_ETH_DB_BUSY database busy, cannot insert due to locking
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBAdd(MacDescriptor *newRecordTemplate, IxEthDBPortMap updateTrigger)
-{
-    IxEthDBStatus result;
-    MacDescriptor *newDescriptor;
-    IxEthDBPortId originalPortID;
-    HashNode *node = NULL;
-
-    BUSY_RETRY(ixEthDBSearchHashEntry(&dbHashtable, ixEthDBKeyType[newRecordTemplate->type], newRecordTemplate, &node));
-
-    TEST_FIXTURE_INCREMENT_DB_CORE_ACCESS_COUNTER;
-
-    if (node == NULL)
-    {
-        /* not found, create a new one */
-        newDescriptor = ixEthDBAllocMacDescriptor();
-
-        if (newDescriptor == NULL)
-        {
-            return IX_ETH_DB_NOMEM; /* no memory */
-        }
-
-        /* old port does not exist, avoid unnecessary updates */
-        originalPortID = newRecordTemplate->portID;
-    }
-    else
-    {
-        /* a node with the same key exists, will update node */
-        newDescriptor = (MacDescriptor *) node->data;
-
-        /* save original port id */
-        originalPortID = newDescriptor->portID;
-    }
-
-    /* copy/update fields into new record */
-    memcpy(newDescriptor->macAddress, newRecordTemplate->macAddress, sizeof (IxEthDBMacAddr));
-    memcpy(&newDescriptor->recordData, &newRecordTemplate->recordData, sizeof (IxEthDBRecordData));
-
-    newDescriptor->type   = newRecordTemplate->type;
-    newDescriptor->portID = newRecordTemplate->portID;
-    newDescriptor->user   = newRecordTemplate->user;
-
-    if (node == NULL)
-    {
-        /* new record, insert into hashtable */
-        BUSY_RETRY_WITH_RESULT(ixEthDBAddHashEntry(&dbHashtable, newDescriptor), result);
-
-        if (result != IX_ETH_DB_SUCCESS)
-        {
-            ixEthDBFreeMacDescriptor(newDescriptor);
-
-            return result; /* insertion failed */
-        }
-    }
-
-    if (node != NULL)
-    {
-        /* release access */
-        ixEthDBReleaseHashNode(node);
-    }
-
-    /* trigger add/remove update if required by type */
-    if (updateTrigger != NULL &&
-        ixEthDBPortUpdateRequired[newRecordTemplate->type])
-    {
-        /* add new port to update list */
-        JOIN_PORT_TO_MAP(updateTrigger, newRecordTemplate->portID);
-
-        /* check if record has moved, we'll need to update the old port as well */
-        if (originalPortID != newDescriptor->portID)
-        {
-            JOIN_PORT_TO_MAP(updateTrigger, originalPortID);
-        }
-    }
-
-    return IX_ETH_DB_SUCCESS;
-}
-
-/**
- * @brief remove a record from the Ethernet database
- *
- * @param templateRecord template record used to determine
- * what record is to be removed
- * @param updateTrigger port map containing the update triggers
- * resulting from this update operation
- *
- * This function will examine the template record it receives
- * and attempts to delete a record of the same type and containing
- * the same keys as the template record. If deletion is successful
- * and the record type is registered for automatic port updates the
- * port will also be set in the updateTrigger port map, so that the
- * client can perform an update of the port.
- *
- * @retval IX_ETH_DB_SUCCESS removal was successful
- * @retval IX_ETH_DB_NO_SUCH_ADDR the record with the given MAC address was not found
- * @retval IX_ETH_DB_BUSY database busy, cannot remove due to locking
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBRemove(MacDescriptor *templateRecord, IxEthDBPortMap updateTrigger)
-{
-    IxEthDBStatus result;
-
-    TEST_FIXTURE_INCREMENT_DB_CORE_ACCESS_COUNTER;
-
-    BUSY_RETRY_WITH_RESULT(ixEthDBRemoveHashEntry(&dbHashtable, ixEthDBKeyType[templateRecord->type], templateRecord), result);
-
-    if (result != IX_ETH_DB_SUCCESS)
-    {
-        return IX_ETH_DB_NO_SUCH_ADDR; /* not found */
-    }
-
-    /* trigger add/remove update if required by type */
-    if (updateTrigger != NULL
-        &&ixEthDBPortUpdateRequired[templateRecord->type])
-    {
-        /* add new port to update list */
-        JOIN_PORT_TO_MAP(updateTrigger, templateRecord->portID);
-    }
-
-    return IX_ETH_DB_SUCCESS;
-}
-
-/**
- * @brief register record key types
- *
- * This function registers the appropriate key types,
- * depending on record types.
- *
- * All filtering records use the MAC address as the key.
- * WiFi and Firewall records use a compound key consisting
- * in both the MAC address and the port ID.
- *
- * @return the number of registered record types
- */
-IX_ETH_DB_PUBLIC
-UINT32 ixEthDBKeyTypeRegister(UINT32 *keyType)
-{
-    /* safety */
-    memset(keyType, 0, sizeof (keyType));
-
-    /* register all known record types */
-    keyType[IX_ETH_DB_FILTERING_RECORD]      = IX_ETH_DB_MAC_KEY;
-    keyType[IX_ETH_DB_FILTERING_VLAN_RECORD] = IX_ETH_DB_MAC_KEY;
-    keyType[IX_ETH_DB_ALL_FILTERING_RECORDS] = IX_ETH_DB_MAC_KEY;
-    keyType[IX_ETH_DB_WIFI_RECORD]           = IX_ETH_DB_MAC_PORT_KEY;
-    keyType[IX_ETH_DB_FIREWALL_RECORD]       = IX_ETH_DB_MAC_PORT_KEY;
-
-    return 5;
-}
-
-/**
- * @brief Sets a user-defined field into a database record
- *
- * Note that this function is fully documented in the main component
- * header file.
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBUserFieldSet(IxEthDBRecordType recordType, IxEthDBMacAddr *macAddr, IxEthDBPortId portID, IxEthDBVlanId vlanID, void *field)
-{
-    HashNode *result = NULL;
-
-    if (macAddr == NULL)
-    {
-        return IX_ETH_DB_INVALID_ARG;
-    }
-
-    if (recordType == IX_ETH_DB_FILTERING_RECORD)
-    {
-        result = ixEthDBSearch(macAddr, recordType);
-    }
-    else if (recordType == IX_ETH_DB_FILTERING_VLAN_RECORD)
-    {
-        result = ixEthDBVlanSearch(macAddr, vlanID, recordType);
-    }
-    else if (recordType == IX_ETH_DB_WIFI_RECORD || recordType == IX_ETH_DB_FIREWALL_RECORD)
-    {
-        IX_ETH_DB_CHECK_PORT_EXISTS(portID);
-
-        result = ixEthDBPortSearch(macAddr, portID, recordType);
-    }
-    else
-    {
-        return IX_ETH_DB_INVALID_ARG;
-    }
-
-    if (result == NULL)
-    {
-        return IX_ETH_DB_NO_SUCH_ADDR;
-    }
-
-    ((MacDescriptor *) result->data)->user = field;
-
-    ixEthDBReleaseHashNode(result);
-
-    return IX_ETH_DB_SUCCESS;
-}
-
-/**
- * @brief Retrieves a user-defined field from a database record
- *
- * Note that this function is fully documented in the main component
- * header file.
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBUserFieldGet(IxEthDBRecordType recordType, IxEthDBMacAddr *macAddr, IxEthDBPortId portID, IxEthDBVlanId vlanID, void **field)
-{
-    HashNode *result = NULL;
-
-    if (macAddr == NULL || field == NULL)
-    {
-        return IX_ETH_DB_INVALID_ARG;
-    }
-
-    if (recordType == IX_ETH_DB_FILTERING_RECORD)
-    {
-        result = ixEthDBSearch(macAddr, recordType);
-    }
-    else if (recordType == IX_ETH_DB_FILTERING_VLAN_RECORD)
-    {
-        result = ixEthDBVlanSearch(macAddr, vlanID, recordType);
-    }
-    else if (recordType == IX_ETH_DB_WIFI_RECORD || recordType == IX_ETH_DB_FIREWALL_RECORD)
-    {
-        IX_ETH_DB_CHECK_PORT_EXISTS(portID);
-
-        result = ixEthDBPortSearch(macAddr, portID, recordType);
-    }
-    else
-    {
-        return IX_ETH_DB_INVALID_ARG;
-    }
-
-    if (result == NULL)
-    {
-        return IX_ETH_DB_NO_SUCH_ADDR;
-    }
-
-    *field = ((MacDescriptor *) result->data)->user;
-
-    ixEthDBReleaseHashNode(result);
-
-    return IX_ETH_DB_SUCCESS;
-}
diff --git a/arch/arm/cpu/ixp/npe/IxEthDBEvents.c b/arch/arm/cpu/ixp/npe/IxEthDBEvents.c
deleted file mode 100644
index 4d44e03..0000000
--- a/arch/arm/cpu/ixp/npe/IxEthDBEvents.c
+++ /dev/null
@@ -1,520 +0,0 @@
-/**
- * @file IxEthDBEvents.c
- *
- * @brief Implementation of the event processor component
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- * 
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- * 
- * @par
- * -- End of Copyright Notice --
- */
-
-#include <IxNpeMh.h>
-#include <IxFeatureCtrl.h>
-
-#include "IxEthDB_p.h"
-
-/* forward prototype declarations */
-IX_ETH_DB_PUBLIC void ixEthDBEventProcessorLoop(void *); 
-IX_ETH_DB_PUBLIC void ixEthDBNPEEventCallback(IxNpeMhNpeId npeID, IxNpeMhMessage msg);
-IX_ETH_DB_PRIVATE void ixEthDBProcessEvent(PortEvent *local_event, IxEthDBPortMap triggerPorts);
-IX_ETH_DB_PRIVATE IxEthDBStatus ixEthDBTriggerPortUpdate(UINT32 eventType, IxEthDBMacAddr *macAddr, IxEthDBPortId portID, BOOL staticEntry);
-IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBStartLearningFunction(void);
-IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBStopLearningFunction(void);
-
-/* data */
-IX_ETH_DB_PRIVATE IxOsalSemaphore eventQueueSemaphore;
-IX_ETH_DB_PRIVATE PortEventQueue eventQueue;
-IX_ETH_DB_PRIVATE IxOsalMutex eventQueueLock;
-IX_ETH_DB_PRIVATE IxOsalMutex portUpdateLock;
-
-IX_ETH_DB_PRIVATE BOOL ixEthDBLearningShutdown      = FALSE;
-IX_ETH_DB_PRIVATE BOOL ixEthDBEventProcessorRunning = FALSE;
-
-/* imported data */
-extern HashTable dbHashtable;
-
-/**
- * @brief initializes the event processor
- *
- * Initializes the event processor queue and processing thread.
- * Called from ixEthDBInit() DB-subcomponent master init function.
- *
- * @warning do not call directly
- *
- * @retval IX_ETH_DB_SUCCESS initialization was successful
- * @retval IX_ETH_DB_FAIL initialization failed (OSAL or mutex init failure)
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBEventProcessorInit(void)
-{
-    if (ixOsalMutexInit(&portUpdateLock) != IX_SUCCESS)
-    {
-        return IX_ETH_DB_FAIL;
-    }
-
-    if (ixOsalMutexInit(&eventQueueLock) != IX_SUCCESS)
-    {
-        return IX_ETH_DB_FAIL;
-    }
-
-    if (IX_FEATURE_CTRL_SWCONFIG_ENABLED ==
-        ixFeatureCtrlSwConfigurationCheck (IX_FEATURECTRL_ETH_LEARNING))
-    {
-
-        /* start processor loop thread */
-        if (ixEthDBStartLearningFunction() != IX_ETH_DB_SUCCESS)
-        {
-            return IX_ETH_DB_FAIL;
-        }
-    }
-
-    return IX_ETH_DB_SUCCESS;
-}
-
-/**
- * @brief initializes the event queue and the event processor
- *
- * This function is called by the component initialization
- * function, ixEthDBInit().
- *
- * @warning do not call directly
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed
- * successfully or IX_ETH_DB_FAIL otherwise
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBStartLearningFunction(void)
-{
-    IxOsalThread eventProcessorThread;
-    IxOsalThreadAttr threadAttr;
-
-    threadAttr.name      = "EthDB event thread";
-    threadAttr.stackSize = 32 * 1024; /* 32kbytes */
-    threadAttr.priority  = 128;
-
-    /* reset event queue */
-    ixOsalMutexLock(&eventQueueLock, IX_OSAL_WAIT_FOREVER);
-
-    RESET_QUEUE(&eventQueue);
-
-    ixOsalMutexUnlock(&eventQueueLock);
-
-    /* init event queue semaphore */
-    if (ixOsalSemaphoreInit(&eventQueueSemaphore, 0) != IX_SUCCESS)
-    {
-        return IX_ETH_DB_FAIL;
-    }
-
-    ixEthDBLearningShutdown = FALSE;
-
-    /* create processor loop thread */
-    if (ixOsalThreadCreate(&eventProcessorThread, &threadAttr, ixEthDBEventProcessorLoop, NULL) != IX_SUCCESS)
-    {
-        return IX_ETH_DB_FAIL;
-    }
-
-    /* start event processor */
-    ixOsalThreadStart(&eventProcessorThread);
-
-    return IX_ETH_DB_SUCCESS;
-}
-
-/**
- * @brief stops the event processor
- *
- * Stops the event processor and frees the event queue semaphore
- * Called by the component de-initialization function, ixEthDBUnload()
- *
- * @warning do not call directly
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed 
- * successfully or IX_ETH_DB_FAIL otherwise;
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBStopLearningFunction(void)
-{
-    ixEthDBLearningShutdown = TRUE;
-
-    /* wake up event processing loop to actually process the shutdown event */
-    ixOsalSemaphorePost(&eventQueueSemaphore);
-
-    if (ixOsalSemaphoreDestroy(&eventQueueSemaphore) != IX_SUCCESS)
-    {
-        return IX_ETH_DB_FAIL;
-    }
-
-    return IX_ETH_DB_SUCCESS;
-}
-
-/**
- * @brief default NPE event processing callback
- *
- * @param npeID ID of the NPE that generated the event
- * @param msg NPE message (encapsulated event)
- *
- * Creates an event object on the Ethernet event processor queue
- * and signals the new event by incrementing the event queue semaphore.
- * Events are processed by @ref ixEthDBEventProcessorLoop() which runs
- * at user level.
- *
- * @see ixEthDBEventProcessorLoop()
- *
- * @warning do not call directly
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-void ixEthDBNPEEventCallback(IxNpeMhNpeId npeID, IxNpeMhMessage msg)
-{
-    PortEvent *local_event;
-
-    IX_ETH_DB_IRQ_EVENTS_TRACE("DB: (Events) new event received by processor callback from port %d, id 0x%X\n", IX_ETH_DB_NPE_TO_PORT_ID(npeID), NPE_MSG_ID(msg), 0, 0, 0, 0);
-
-    if (CAN_ENQUEUE(&eventQueue))
-    {
-        TEST_FIXTURE_LOCK_EVENT_QUEUE;
-
-        local_event = QUEUE_HEAD(&eventQueue);
-
-        /* create event structure on queue */
-        local_event->eventType = NPE_MSG_ID(msg);
-        local_event->portID    = IX_ETH_DB_NPE_TO_PORT_ID(npeID);
-        
-        /* update queue */
-        PUSH_UPDATE_QUEUE(&eventQueue);
-
-        TEST_FIXTURE_UNLOCK_EVENT_QUEUE;
-
-        IX_ETH_DB_IRQ_EVENTS_TRACE("DB: (Events) Waking up main processor loop...\n", 0, 0, 0, 0, 0, 0);
-
-        /* increment event queue semaphore */
-        ixOsalSemaphorePost(&eventQueueSemaphore);
-    }
-    else
-    {
-        IX_ETH_DB_IRQ_EVENTS_TRACE("DB: (Events) Warning: could not enqueue event (overflow)\n", 0, 0, 0, 0, 0, 0);
-    }
-}
-
-/**
- * @brief Ethernet event processor loop
- *
- * Extracts at most EVENT_PROCESSING_LIMIT batches of events and
- * sends them for processing to @ref ixEthDBProcessEvent().
- * Triggers port updates which normally follow learning events.
- *
- * @warning do not call directly, executes in separate thread
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-void ixEthDBEventProcessorLoop(void *unused1)
-{
-    IxEthDBPortMap triggerPorts;
-    IxEthDBPortId portIndex;
-
-    ixEthDBEventProcessorRunning = TRUE;
-
-    IX_ETH_DB_EVENTS_TRACE("DB: (Events) Event processor loop was started\n");
-
-    while (!ixEthDBLearningShutdown)
-    {
-        BOOL keepProcessing    = TRUE;
-        UINT32 processedEvents = 0;
-
-        IX_ETH_DB_EVENTS_VERBOSE_TRACE("DB: (Events) Waiting for new learning event...\n");
-
-        ixOsalSemaphoreWait(&eventQueueSemaphore, IX_OSAL_WAIT_FOREVER);
-
-        IX_ETH_DB_EVENTS_VERBOSE_TRACE("DB: (Events) Received new event\n");
-
-        if (!ixEthDBLearningShutdown)
-        {
-            /* port update handling */
-            SET_EMPTY_DEPENDENCY_MAP(triggerPorts);
-
-            while (keepProcessing)
-            {
-                PortEvent local_event;
-                UINT32 intLockKey;
-
-                /* lock queue */
-                ixOsalMutexLock(&eventQueueLock, IX_OSAL_WAIT_FOREVER);
-
-                /* lock NPE interrupts */
-                intLockKey = ixOsalIrqLock();
-
-                /* extract event */
-                local_event = *(QUEUE_TAIL(&eventQueue));
-
-                SHIFT_UPDATE_QUEUE(&eventQueue);
-
-                ixOsalIrqUnlock(intLockKey);
-
-                ixOsalMutexUnlock(&eventQueueLock);
-
-                IX_ETH_DB_EVENTS_TRACE("DB: (Events) Processing event with ID 0x%X\n", local_event.eventType);
-
-                ixEthDBProcessEvent(&local_event, triggerPorts);
-
-                processedEvents++;
-
-                if (processedEvents > EVENT_PROCESSING_LIMIT /* maximum burst reached? */
-                    || ixOsalSemaphoreTryWait(&eventQueueSemaphore) != IX_SUCCESS) /* or empty queue? */
-                {
-                    keepProcessing = FALSE;
-                }
-            }
-
-            ixEthDBUpdatePortLearningTrees(triggerPorts);
-        }
-    }
-
-    /* turn off automatic updates */
-    for (portIndex = 0 ; portIndex < IX_ETH_DB_NUMBER_OF_PORTS ; portIndex++)
-    {
-        ixEthDBPortInfo[portIndex].updateMethod.updateEnabled = FALSE;
-    }
-
-    ixEthDBEventProcessorRunning = FALSE;
-}
-
-/**
- * @brief event processor routine
- *
- * @param event event to be processed
- * @param triggerPorts port map accumulating ports to be updated
- *
- * Processes learning events by synchronizing the database with
- * newly learnt data. Called only by @ref ixEthDBEventProcessorLoop().
- *
- * @warning do not call directly
- *
- * @internal
- */
-IX_ETH_DB_PRIVATE
-void ixEthDBProcessEvent(PortEvent *local_event, IxEthDBPortMap triggerPorts)
-{
-    MacDescriptor recordTemplate;
-
-    switch (local_event->eventType)
-    {
-        case IX_ETH_DB_ADD_FILTERING_RECORD:
-            /* add record */
-            memset(&recordTemplate, 0, sizeof (recordTemplate));
-            memcpy(recordTemplate.macAddress, local_event->macAddr.macAddress, sizeof (IxEthDBMacAddr));
-            
-            recordTemplate.type   = IX_ETH_DB_FILTERING_RECORD;
-            recordTemplate.portID = local_event->portID;
-            recordTemplate.recordData.filteringData.staticEntry = local_event->staticEntry;
-            
-            ixEthDBAdd(&recordTemplate, triggerPorts);
-
-            IX_ETH_DB_EVENTS_TRACE("DB: (Events) Added record on port %d\n", local_event->portID);
-
-            break;
-
-        case IX_ETH_DB_REMOVE_FILTERING_RECORD:
-            /* remove record */
-            memset(&recordTemplate, 0, sizeof (recordTemplate));
-            memcpy(recordTemplate.macAddress, local_event->macAddr.macAddress, sizeof (IxEthDBMacAddr));
-            
-            recordTemplate.type = IX_ETH_DB_FILTERING_RECORD | IX_ETH_DB_FILTERING_VLAN_RECORD;
-            
-            ixEthDBRemove(&recordTemplate, triggerPorts);
-            
-            IX_ETH_DB_EVENTS_TRACE("DB: (Events) Removed record on port %d\n", local_event->portID);
-
-            break;
-
-        default:
-            /* can't handle/not interested in this event type */
-            ERROR_LOG("DB: (Events) Event processor received an unknown event type (0x%X)\n", local_event->eventType);
-
-            return;
-    }
-}
-
-/**
- * @brief asynchronously adds a filtering record
- * by posting an ADD_FILTERING_RECORD event to the event queue
- *
- * @param macAddr MAC address of the new record
- * @param portID port ID of the new record
- * @param staticEntry TRUE if record is static, FALSE if dynamic
- *
- * @return IX_ETH_DB_SUCCESS if the event creation was
- * successfull or IX_ETH_DB_BUSY if the event queue is full
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBTriggerAddPortUpdate(IxEthDBMacAddr *macAddr, IxEthDBPortId portID, BOOL staticEntry)
-{
-    MacDescriptor reference;
-    
-    TEST_FIXTURE_INCREMENT_DB_CORE_ACCESS_COUNTER;
-
-    /* fill search fields */
-    memcpy(reference.macAddress, macAddr, sizeof (IxEthDBMacAddr));
-    reference.portID = portID;
-    
-    /* set acceptable record types */
-    reference.type = IX_ETH_DB_ALL_FILTERING_RECORDS;
-
-    if (ixEthDBPeekHashEntry(&dbHashtable, IX_ETH_DB_MAC_PORT_KEY, &reference) == IX_ETH_DB_SUCCESS)
-    {
-        /* already have an identical record */
-        return IX_ETH_DB_SUCCESS;
-    }
-    else
-    {
-        return ixEthDBTriggerPortUpdate(IX_ETH_DB_ADD_FILTERING_RECORD, macAddr, portID, staticEntry);
-    }
-}
-
-/**
- * @brief asynchronously removes a filtering record
- * by posting a REMOVE_FILTERING_RECORD event to the event queue
- *
- * @param macAddr MAC address of the record to remove
- * @param portID port ID of the record to remove
- *
- * @return IX_ETH_DB_SUCCESS if the event creation was
- * successfull or IX_ETH_DB_BUSY if the event queue is full
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBTriggerRemovePortUpdate(IxEthDBMacAddr *macAddr, IxEthDBPortId portID)
-{
-    if (ixEthDBPeek(macAddr, IX_ETH_DB_ALL_FILTERING_RECORDS) != IX_ETH_DB_NO_SUCH_ADDR)
-    {
-        return ixEthDBTriggerPortUpdate(IX_ETH_DB_REMOVE_FILTERING_RECORD, macAddr, portID, FALSE);
-    }
-    else
-    {
-        return IX_ETH_DB_NO_SUCH_ADDR;
-    }
-}
-
-/**
- * @brief adds an ADD or REMOVE event to the main event queue
- *
- * @param eventType event type - IX_ETH_DB_ADD_FILTERING_RECORD 
- * to add and IX_ETH_DB_REMOVE_FILTERING_RECORD to remove a
- * record.
- *
- * @return IX_ETH_DB_SUCCESS if the event was successfully
- * sent or IX_ETH_DB_BUSY if the event queue is full
- *
- * @internal
- */
-IX_ETH_DB_PRIVATE
-IxEthDBStatus ixEthDBTriggerPortUpdate(UINT32 eventType, IxEthDBMacAddr *macAddr, IxEthDBPortId portID, BOOL staticEntry)
-{
-    UINT32 intLockKey;
-
-    /* lock interrupts to protect queue */
-    intLockKey = ixOsalIrqLock();
-
-    if (CAN_ENQUEUE(&eventQueue))
-    {
-        PortEvent *queueEvent = QUEUE_HEAD(&eventQueue);
-
-        /* update fields on the queue */
-        memcpy(queueEvent->macAddr.macAddress, macAddr->macAddress, sizeof (IxEthDBMacAddr));
-        
-        queueEvent->eventType     = eventType;
-        queueEvent->portID        = portID;
-        queueEvent->staticEntry   = staticEntry;
-
-        PUSH_UPDATE_QUEUE(&eventQueue);
-
-        /* imcrement event queue semaphore */
-        ixOsalSemaphorePost(&eventQueueSemaphore);
-        
-        /* unlock interrupts */
-        ixOsalIrqUnlock(intLockKey);
-
-        return IX_ETH_DB_SUCCESS;
-    }
-    else /* event queue full */
-    {
-        /* unlock interrupts */
-        ixOsalIrqUnlock(intLockKey);
-
-        return IX_ETH_DB_BUSY;
-    }
-}
-
-/**
- * @brief Locks learning tree updates and port disable
- *
- *
- * This function locks portUpdateLock single mutex. It is primarily used
- * to avoid executing 'port disable' during ELT maintenance.
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-void ixEthDBUpdateLock(void)
-{
-    ixOsalMutexLock(&portUpdateLock, IX_OSAL_WAIT_FOREVER);
-}
-
-/**
- * @brief Unlocks learning tree updates and port disable
- *
- *
- * This function unlocks a portUpdateLock mutex. It is primarily used
- * to avoid executing 'port disable' during ELT maintenance.
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-void ixEthDBUpdateUnlock(void)
-{
-    ixOsalMutexUnlock(&portUpdateLock);
-}
-
diff --git a/arch/arm/cpu/ixp/npe/IxEthDBFeatures.c b/arch/arm/cpu/ixp/npe/IxEthDBFeatures.c
deleted file mode 100644
index 7a58d26..0000000
--- a/arch/arm/cpu/ixp/npe/IxEthDBFeatures.c
+++ /dev/null
@@ -1,662 +0,0 @@
-/**
- * @file IxEthDBFeatures.c
- *
- * @brief Implementation of the EthDB feature control API
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
- */
-
-#include "IxNpeDl.h"
-#include "IxEthDBQoS.h"
-#include "IxEthDB_p.h"
-
-/**
- * @brief scans the capabilities of the loaded NPE images
- *
- * This function MUST be called by the ixEthDBInit() function.
- * No EthDB features (including learning and filtering) are enabled
- * before this function is called.
- *
- * @return none
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-void ixEthDBFeatureCapabilityScan(void)
-{
-    IxNpeDlImageId imageId, npeAImageId;
-    IxEthDBPortId portIndex;
-    PortInfo *portInfo;
-    IxEthDBPriorityTable defaultPriorityTable;
-    IX_STATUS result;
-    UINT32 queueIndex;
-    UINT32 queueStructureIndex;
-    UINT32 trafficClassDefinitionIndex;
-
-    /* read version of NPE A - required to set the AQM queues for B and C */
-    npeAImageId.functionalityId = 0;
-    ixNpeDlLoadedImageGet(IX_NPEDL_NPEID_NPEA, &npeAImageId);
-
-    for (portIndex = 0 ; portIndex < IX_ETH_DB_NUMBER_OF_PORTS ; portIndex++)
-    {
-        IxNpeMhMessage msg;
-
-        portInfo = &ixEthDBPortInfo[portIndex];
-
-        /* check and bypass if NPE B or C is fused out */
-        if (ixEthDBSingleEthNpeCheck(portIndex) != IX_ETH_DB_SUCCESS) continue;
-
-        /* all ports are capable of LEARNING by default */
-        portInfo->featureCapability |= IX_ETH_DB_LEARNING;
-        portInfo->featureStatus     |= IX_ETH_DB_LEARNING;
-
-        if (ixEthDBPortDefinitions[portIndex].type == IX_ETH_NPE)
-        {
-
-            if (ixNpeDlLoadedImageGet(IX_ETH_DB_PORT_ID_TO_NPE(portIndex), &imageId) != IX_SUCCESS)
-            {
-                WARNING_LOG("DB: (FeatureScan) NpeDl did not provide the image ID for NPE port %d\n", portIndex);
-            }
-            else
-            {
-                /* initialize and empty NPE response mutex */
-                ixOsalMutexInit(&portInfo->npeAckLock);
-                ixOsalMutexLock(&portInfo->npeAckLock, IX_OSAL_WAIT_FOREVER);
-
-                /* check NPE response to GetStatus */
-                msg.data[0] = IX_ETHNPE_NPE_GETSTATUS << 24;
-                msg.data[1] = 0;
-                IX_ETHDB_SEND_NPE_MSG(IX_ETH_DB_PORT_ID_TO_NPE(portIndex), msg, result);
-                if (result != IX_SUCCESS)
-                {
-                    WARNING_LOG("DB: (FeatureScan) warning, could not send message to the NPE\n");
-                    continue;
-                }
-
-
-                if (imageId.functionalityId == 0x00
-                    || imageId.functionalityId == 0x03
-                    || imageId.functionalityId == 0x04
-                    || imageId.functionalityId == 0x80)
-                {
-                    portInfo->featureCapability |= IX_ETH_DB_FILTERING;
-                    portInfo->featureCapability |= IX_ETH_DB_FIREWALL;
-                    portInfo->featureCapability |= IX_ETH_DB_SPANNING_TREE_PROTOCOL;
-                }
-                else if (imageId.functionalityId == 0x01
-                         || imageId.functionalityId == 0x81)
-                {
-                    portInfo->featureCapability |= IX_ETH_DB_FILTERING;
-                    portInfo->featureCapability |= IX_ETH_DB_FIREWALL;
-                    portInfo->featureCapability |= IX_ETH_DB_SPANNING_TREE_PROTOCOL;
-                    portInfo->featureCapability |= IX_ETH_DB_VLAN_QOS;
-                }
-                else if (imageId.functionalityId == 0x02
-                         || imageId.functionalityId == 0x82)
-                {
-                    portInfo->featureCapability |= IX_ETH_DB_WIFI_HEADER_CONVERSION;
-                    portInfo->featureCapability |= IX_ETH_DB_FIREWALL;
-                    portInfo->featureCapability |= IX_ETH_DB_SPANNING_TREE_PROTOCOL;
-                    portInfo->featureCapability |= IX_ETH_DB_VLAN_QOS;
-                }
-
-                /* reset AQM queues */
-                memset(portInfo->ixEthDBTrafficClassAQMAssignments, 0, sizeof (portInfo->ixEthDBTrafficClassAQMAssignments));
-
-                /* ensure there's at least one traffic class record in the definition table, otherwise we have no default case, hence no queues */
-                IX_ENSURE(sizeof (ixEthDBTrafficClassDefinitions) != 0, "DB: no traffic class definitions found, check IxEthDBQoS.h");
-
-                /* find the traffic class definition index compatible with the current NPE A functionality ID */
-                for (trafficClassDefinitionIndex = 0 ;
-                    trafficClassDefinitionIndex < sizeof (ixEthDBTrafficClassDefinitions) / sizeof (ixEthDBTrafficClassDefinitions[0]);
-                    trafficClassDefinitionIndex++)
-                {
-                    if (ixEthDBTrafficClassDefinitions[trafficClassDefinitionIndex][IX_ETH_DB_NPE_A_FUNCTIONALITY_ID_INDEX] == npeAImageId.functionalityId)
-                    {
-                        /* found it */
-                        break;
-                    }
-                }
-
-                /* select the default case if we went over the array boundary */
-                if (trafficClassDefinitionIndex == sizeof (ixEthDBTrafficClassDefinitions) / sizeof (ixEthDBTrafficClassDefinitions[0]))
-                {
-                    trafficClassDefinitionIndex = 0; /* the first record is the default case */
-                }
-
-                /* select queue assignment structure based on the traffic class configuration index */
-                queueStructureIndex = ixEthDBTrafficClassDefinitions[trafficClassDefinitionIndex][IX_ETH_DB_QUEUE_ASSIGNMENT_INDEX];
-
-                /* only traffic class 0 is active at initialization time */
-                portInfo->ixEthDBTrafficClassCount = 1;
-
-                /* enable port, VLAN and Firewall feature bits to initialize QoS/VLAN/Firewall configuration */
-                portInfo->featureStatus |= IX_ETH_DB_VLAN_QOS;
-                portInfo->featureStatus |= IX_ETH_DB_FIREWALL;
-                portInfo->enabled        = TRUE;
-
-#define CONFIG_WITH_VLAN  /* test-only: VLAN support not included to save space!!! */
-#ifdef CONFIG_WITH_VLAN /* test-only: VLAN support not included to save space!!! */
-                /* set VLAN initial configuration (permissive) */
-                if ((portInfo->featureCapability & IX_ETH_DB_VLAN_QOS) != 0) /* QoS-enabled image */
-                {
-                    /* QoS capable */
-                    portInfo->ixEthDBTrafficClassAvailable = ixEthDBTrafficClassDefinitions[trafficClassDefinitionIndex][IX_ETH_DB_TRAFFIC_CLASS_COUNT_INDEX];
-
-                    /* set AQM queues */
-                    for (queueIndex = 0 ; queueIndex < IX_IEEE802_1Q_QOS_PRIORITY_COUNT ; queueIndex++)
-                    {
-                        portInfo->ixEthDBTrafficClassAQMAssignments[queueIndex] = ixEthDBQueueAssignments[queueStructureIndex][queueIndex];
-                    }
-
-                    /* set default PVID (0) and default traffic class 0 */
-                    ixEthDBPortVlanTagSet(portIndex, 0);
-
-                    /* enable reception of all frames */
-                    ixEthDBAcceptableFrameTypeSet(portIndex, IX_ETH_DB_ACCEPT_ALL_FRAMES);
-
-                    /* clear full VLAN membership */
-                    ixEthDBPortVlanMembershipRangeRemove(portIndex, 0, IX_ETH_DB_802_1Q_MAX_VLAN_ID);
-
-                    /* clear TTI table - no VLAN tagged frames will be transmitted */
-                    ixEthDBEgressVlanRangeTaggingEnabledSet(portIndex, 0, 4094, FALSE);
-
-                    /* set membership on 0, otherwise no Tx or Rx is working */
-                    ixEthDBPortVlanMembershipAdd(portIndex, 0);
-                }
-                else /* QoS not available in this image */
-#endif /* test-only */
-                {
-                    /* initialize traffic class availability (only class 0 is available) */
-                    portInfo->ixEthDBTrafficClassAvailable = 1;
-
-                    /* point all AQM queues to traffic class 0 */
-                    for (queueIndex = 0 ; queueIndex < IX_IEEE802_1Q_QOS_PRIORITY_COUNT ; queueIndex++)
-                    {
-                        portInfo->ixEthDBTrafficClassAQMAssignments[queueIndex] =
-                            ixEthDBQueueAssignments[queueStructureIndex][0];
-                    }
-                }
-
-#ifdef CONFIG_WITH_VLAN /* test-only: VLAN support not included to save space!!! */
-                /* download priority mapping table and Rx queue configuration */
-                memset (defaultPriorityTable, 0, sizeof (defaultPriorityTable));
-                ixEthDBPriorityMappingTableSet(portIndex, defaultPriorityTable);
-#endif
-
-                /* by default we turn off invalid source MAC address filtering */
-                ixEthDBFirewallInvalidAddressFilterEnable(portIndex, FALSE);
-
-                /* disable port, VLAN, Firewall feature bits */
-                portInfo->featureStatus &= ~IX_ETH_DB_VLAN_QOS;
-                portInfo->featureStatus &= ~IX_ETH_DB_FIREWALL;
-                portInfo->enabled        = FALSE;
-
-                /* enable filtering by default if present */
-                if ((portInfo->featureCapability & IX_ETH_DB_FILTERING) != 0)
-                {
-                    portInfo->featureStatus |= IX_ETH_DB_FILTERING;
-                }
-            }
-        }
-    }
-}
-
-/**
- * @brief returns the capability of a port
- *
- * @param portID ID of the port
- * @param featureSet location to store the port capability in
- *
- * This function will save the capability set of the given port
- * into the given location. Capabilities are bit-ORed, each representing
- * a bit of the feature set.
- *
- * Note that this function is documented in the main component
- * public header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or IX_ETH_DB_INVALID_PORT if the given port is invalid
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBFeatureCapabilityGet(IxEthDBPortId portID, IxEthDBFeature *featureSet)
-{
-    IX_ETH_DB_CHECK_PORT_INITIALIZED(portID);
-
-    IX_ETH_DB_CHECK_REFERENCE(featureSet);
-
-    *featureSet = ixEthDBPortInfo[portID].featureCapability;
-
-    return IX_ETH_DB_SUCCESS;
-}
-
-/**
- * @brief enables or disables a port capability
- *
- * @param portID ID of the port
- * @param feature feature to enable or disable
- * @param enabled TRUE to enable the selected feature or FALSE to disable it
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed
- * successfully or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBFeatureEnable(IxEthDBPortId portID, IxEthDBFeature feature, BOOL enable)
-{
-    PortInfo *portInfo;
-    IxEthDBPriorityTable defaultPriorityTable;
-    IxEthDBVlanSet vlanSet;
-    IxEthDBStatus status = IX_ETH_DB_SUCCESS;
-    BOOL portEnabled;
-
-    IX_ETH_DB_CHECK_PORT_INITIALIZED(portID);
-
-    portInfo    = &ixEthDBPortInfo[portID];
-    portEnabled = portInfo->enabled;
-
-    /* check that only one feature is selected */
-    if (!ixEthDBCheckSingleBitValue(feature))
-    {
-        return IX_ETH_DB_FEATURE_UNAVAILABLE;
-    }
-
-    /* port capable of this feature? */
-    if ((portInfo->featureCapability & feature) == 0)
-    {
-        return IX_ETH_DB_FEATURE_UNAVAILABLE;
-    }
-
-    /* mutual exclusion between learning and WiFi header conversion */
-    if (enable && ((feature | portInfo->featureStatus) & (IX_ETH_DB_FILTERING | IX_ETH_DB_WIFI_HEADER_CONVERSION))
-            == (IX_ETH_DB_FILTERING | IX_ETH_DB_WIFI_HEADER_CONVERSION))
-    {
-        return IX_ETH_DB_NO_PERMISSION;
-    }
-
-    /* learning must be enabled before filtering */
-    if (enable && (feature == IX_ETH_DB_FILTERING) && ((portInfo->featureStatus & IX_ETH_DB_LEARNING) == 0))
-    {
-        return IX_ETH_DB_NO_PERMISSION;
-    }
-
-    /* filtering must be disabled before learning */
-    if (!enable && (feature == IX_ETH_DB_LEARNING) && ((portInfo->featureStatus & IX_ETH_DB_FILTERING) != 0))
-    {
-        return IX_ETH_DB_NO_PERMISSION;
-    }
-
-    /* redundant enabling or disabling */
-    if ((!enable && ((portInfo->featureStatus & feature) == 0))
-        || (enable && ((portInfo->featureStatus & feature) != 0)))
-    {
-        /* do nothing */
-        return IX_ETH_DB_SUCCESS;
-    }
-
-    /* force port enabled */
-    portInfo->enabled = TRUE;
-
-    if (enable)
-    {
-        /* turn on enable bit */
-        portInfo->featureStatus |= feature;
-
-#ifdef CONFIG_WITH_VLAN /* test-only: VLAN support not included to save space!!! */
-        /* if this is VLAN/QoS set the default priority table */
-        if (feature == IX_ETH_DB_VLAN_QOS)
-        {
-            /* turn on VLAN/QoS (most permissive mode):
-                - set default 802.1Q priority mapping table, in accordance to the
-                  availability of traffic classes
-                - set the acceptable frame filter to accept all
-                - set the Ingress tagging mode to pass-through
-                - set full VLAN membership list
-                - set full TTI table
-                - set the default 802.1Q tag to 0 (VLAN ID 0, Pri 0, CFI 0)
-                - enable TPID port extraction
-            */
-
-            portInfo->ixEthDBTrafficClassCount = portInfo->ixEthDBTrafficClassAvailable;
-
-            /* set default 802.1Q priority mapping table - note that C indexing starts from 0, so we substract 1 here */
-            memcpy (defaultPriorityTable,
-                (const void *) ixEthIEEE802_1QUserPriorityToTrafficClassMapping[portInfo->ixEthDBTrafficClassCount - 1],
-                sizeof (defaultPriorityTable));
-
-            /* update priority mapping and AQM queue assignments */
-            status = ixEthDBPriorityMappingTableSet(portID, defaultPriorityTable);
-
-            if (status == IX_ETH_DB_SUCCESS)
-            {
-                status = ixEthDBAcceptableFrameTypeSet(portID, IX_ETH_DB_ACCEPT_ALL_FRAMES);
-            }
-
-            if (status == IX_ETH_DB_SUCCESS)
-            {
-                status = ixEthDBIngressVlanTaggingEnabledSet(portID, IX_ETH_DB_PASS_THROUGH);
-            }
-
-            /* set membership and TTI tables */
-            memset (vlanSet, 0xFF, sizeof (vlanSet));
-
-            if (status == IX_ETH_DB_SUCCESS)
-            {
-                /* use the internal function to bypass PVID check */
-                status = ixEthDBPortVlanTableSet(portID, portInfo->vlanMembership, vlanSet);
-            }
-
-            if (status == IX_ETH_DB_SUCCESS)
-            {
-                /* use the internal function to bypass PVID check */
-                status = ixEthDBPortVlanTableSet(portID, portInfo->transmitTaggingInfo, vlanSet);
-            }
-
-            /* reset the PVID */
-            if (status == IX_ETH_DB_SUCCESS)
-            {
-                status = ixEthDBPortVlanTagSet(portID, 0);
-            }
-
-            /* enable TPID port extraction */
-            if (status == IX_ETH_DB_SUCCESS)
-            {
-                status = ixEthDBVlanPortExtractionEnable(portID, TRUE);
-            }
-        }
-        else if (feature == IX_ETH_DB_FIREWALL)
-#endif
-        {
-            /* firewall starts in black-list mode unless otherwise configured before *
-             * note that invalid source MAC address filtering is disabled by default */
-            if (portInfo->firewallMode != IX_ETH_DB_FIREWALL_BLACK_LIST
-                && portInfo->firewallMode != IX_ETH_DB_FIREWALL_WHITE_LIST)
-            {
-                status = ixEthDBFirewallModeSet(portID, IX_ETH_DB_FIREWALL_BLACK_LIST);
-
-                if (status == IX_ETH_DB_SUCCESS)
-                {
-                    status = ixEthDBFirewallInvalidAddressFilterEnable(portID, FALSE);
-                }
-            }
-        }
-
-        if (status != IX_ETH_DB_SUCCESS)
-        {
-            /* checks failed, disable */
-            portInfo->featureStatus &= ~feature;
-        }
-    }
-    else
-    {
-        /* turn off features */
-        if (feature == IX_ETH_DB_FIREWALL)
-        {
-            /* turning off the firewall is equivalent to:
-                - set to black-list mode
-                - clear all the entries and download the new table
-                - turn off the invalid source address checking
-            */
-
-            status = ixEthDBDatabaseClear(portID, IX_ETH_DB_FIREWALL_RECORD);
-
-            if (status == IX_ETH_DB_SUCCESS)
-            {
-                status = ixEthDBFirewallModeSet(portID, IX_ETH_DB_FIREWALL_BLACK_LIST);
-            }
-
-            if (status == IX_ETH_DB_SUCCESS)
-            {
-                status = ixEthDBFirewallInvalidAddressFilterEnable(portID, FALSE);
-            }
-
-            if (status == IX_ETH_DB_SUCCESS)
-            {
-                status = ixEthDBFirewallTableDownload(portID);
-            }
-        }
-        else if (feature == IX_ETH_DB_WIFI_HEADER_CONVERSION)
-        {
-            /* turn off header conversion */
-            status = ixEthDBDatabaseClear(portID, IX_ETH_DB_WIFI_RECORD);
-
-            if (status == IX_ETH_DB_SUCCESS)
-            {
-                status = ixEthDBWiFiConversionTableDownload(portID);
-            }
-        }
-#ifdef CONFIG_WITH_VLAN /* test-only: VLAN support not included to save space!!! */
-        else if (feature == IX_ETH_DB_VLAN_QOS)
-        {
-            /* turn off VLAN/QoS:
-                - set a priority mapping table with one traffic class
-                - set the acceptable frame filter to accept all
-                - set the Ingress tagging mode to pass-through
-                - clear the VLAN membership list
-                - clear the TTI table
-                - set the default 802.1Q tag to 0 (VLAN ID 0, Pri 0, CFI 0)
-                - disable TPID port extraction
-            */
-
-            /* initialize all => traffic class 0 priority mapping table */
-            memset (defaultPriorityTable, 0, sizeof (defaultPriorityTable));
-            portInfo->ixEthDBTrafficClassCount = 1;
-            status = ixEthDBPriorityMappingTableSet(portID, defaultPriorityTable);
-
-            if (status == IX_ETH_DB_SUCCESS)
-            {
-                status = ixEthDBAcceptableFrameTypeSet(portID, IX_ETH_DB_ACCEPT_ALL_FRAMES);
-            }
-
-            if (status == IX_ETH_DB_SUCCESS)
-            {
-                status = ixEthDBIngressVlanTaggingEnabledSet(portID, IX_ETH_DB_PASS_THROUGH);
-            }
-
-            /* clear membership and TTI tables */
-            memset (vlanSet, 0, sizeof (vlanSet));
-
-            if (status == IX_ETH_DB_SUCCESS)
-            {
-                /* use the internal function to bypass PVID check */
-                status = ixEthDBPortVlanTableSet(portID, portInfo->vlanMembership, vlanSet);
-            }
-
-            if (status == IX_ETH_DB_SUCCESS)
-            {
-                /* use the internal function to bypass PVID check */
-                status = ixEthDBPortVlanTableSet(portID, portInfo->transmitTaggingInfo, vlanSet);
-            }
-
-            /* reset the PVID */
-            if (status == IX_ETH_DB_SUCCESS)
-            {
-                status = ixEthDBPortVlanTagSet(portID, 0);
-            }
-
-            /* disable TPID port extraction */
-            if (status == IX_ETH_DB_SUCCESS)
-            {
-                status = ixEthDBVlanPortExtractionEnable(portID, FALSE);
-            }
-        }
-#endif
-
-        if (status == IX_ETH_DB_SUCCESS)
-        {
-            /* checks passed, disable */
-            portInfo->featureStatus &= ~feature;
-        }
-    }
-
-    /* restore port enabled state */
-    portInfo->enabled = portEnabled;
-
-    return status;
-}
-
-/**
- * @brief returns the status of a feature
- *
- * @param portID port ID
- * @param present location to store a boolean value indicating
- * if the feature is present (TRUE) or not (FALSE)
- * @param enabled location to store a booleam value indicating
- * if the feature is present (TRUE) or not (FALSE)
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed
- * successfully or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBFeatureStatusGet(IxEthDBPortId portID, IxEthDBFeature feature, BOOL *present, BOOL *enabled)
-{
-    PortInfo *portInfo;
-
-    IX_ETH_DB_CHECK_PORT(portID);
-
-    IX_ETH_DB_CHECK_REFERENCE(present);
-
-    IX_ETH_DB_CHECK_REFERENCE(enabled);
-
-    portInfo = &ixEthDBPortInfo[portID];
-
-    *present = (portInfo->featureCapability & feature) != 0;
-    *enabled = (portInfo->featureStatus & feature) != 0;
-
-    return IX_ETH_DB_SUCCESS;
-}
-
-/**
- * @brief returns the value of an EthDB property
- *
- * @param portID ID of the port
- * @param feature feature owning the property
- * @param property ID of the property
- * @param type location to store the property type into
- * @param value location to store the property value into
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed
- * successfully or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBFeaturePropertyGet(IxEthDBPortId portID, IxEthDBFeature feature, IxEthDBProperty property, IxEthDBPropertyType *type, void *value)
-{
-    IX_ETH_DB_CHECK_PORT_EXISTS(portID);
-
-    IX_ETH_DB_CHECK_REFERENCE(type);
-
-    IX_ETH_DB_CHECK_REFERENCE(value);
-
-    if (feature == IX_ETH_DB_VLAN_QOS)
-    {
-        if (property == IX_ETH_DB_QOS_TRAFFIC_CLASS_COUNT_PROPERTY)
-        {
-            * (UINT32 *) value = ixEthDBPortInfo[portID].ixEthDBTrafficClassCount;
-            *type              = IX_ETH_DB_INTEGER_PROPERTY;
-
-            return IX_ETH_DB_SUCCESS;
-        }
-        else if (property >= IX_ETH_DB_QOS_TRAFFIC_CLASS_0_RX_QUEUE_PROPERTY
-            && property <= IX_ETH_DB_QOS_TRAFFIC_CLASS_7_RX_QUEUE_PROPERTY)
-        {
-            UINT32 classDelta = property - IX_ETH_DB_QOS_TRAFFIC_CLASS_0_RX_QUEUE_PROPERTY;
-
-            if (classDelta >= ixEthDBPortInfo[portID].ixEthDBTrafficClassCount)
-            {
-                return IX_ETH_DB_FAIL;
-            }
-
-            * (UINT32 *) value = ixEthDBPortInfo[portID].ixEthDBTrafficClassAQMAssignments[classDelta];
-            *type              = IX_ETH_DB_INTEGER_PROPERTY;
-
-            return IX_ETH_DB_SUCCESS;
-        }
-    }
-
-    return IX_ETH_DB_INVALID_ARG;
-}
-
-/**
- * @brief sets the value of an EthDB property
- *
- * @param portID ID of the port
- * @param feature feature owning the property
- * @param property ID of the property
- * @param value location containing the property value
- *
- * This function implements a private property intended
- * only for EthAcc usage. Upon setting the IX_ETH_DB_QOS_QUEUE_CONFIGURATION_COMPLETE
- * property (the value is ignored), the availability of traffic classes is
- * frozen to whatever traffic class structure is currently in use.
- * This means that if VLAN_QOS has been enabled before EthAcc
- * initialization then all the defined traffic classes will be available;
- * otherwise only one traffic class (0) will be available.
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h as not accepting any parameters. The
- * current implementation is only intended for the private use of EthAcc.
- *
- * Also note that once this function is called the effect is irreversible,
- * unless EthDB is complete unloaded and re-initialized.
- *
- * @return IX_ETH_DB_INVALID_ARG (no read-write properties are
- * supported in this release)
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBFeaturePropertySet(IxEthDBPortId portID, IxEthDBFeature feature, IxEthDBProperty property, void *value)
-{
-    IX_ETH_DB_CHECK_PORT_EXISTS(portID);
-
-    if ((feature == IX_ETH_DB_VLAN_QOS) && (property == IX_ETH_DB_QOS_QUEUE_CONFIGURATION_COMPLETE))
-    {
-        ixEthDBPortInfo[portID].ixEthDBTrafficClassAvailable = ixEthDBPortInfo[portID].ixEthDBTrafficClassCount;
-
-        return IX_ETH_DB_SUCCESS;
-    }
-
-    return IX_ETH_DB_INVALID_ARG;
-}
diff --git a/arch/arm/cpu/ixp/npe/IxEthDBFirewall.c b/arch/arm/cpu/ixp/npe/IxEthDBFirewall.c
deleted file mode 100644
index eb46174..0000000
--- a/arch/arm/cpu/ixp/npe/IxEthDBFirewall.c
+++ /dev/null
@@ -1,266 +0,0 @@
-/**
- * @file IxEthDBFirewall.c
- *
- * @brief Implementation of the firewall API
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- * 
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- * 
- * @par
- * -- End of Copyright Notice --
- */
-
-
-#include "IxEthDB_p.h"
-
-/**
- * @brief updates the NPE firewall operating mode and 
- * firewall address table
- *
- * @param portID ID of the port
- * @param epDelta initial entry point for binary searches (NPE optimization)
- * @param address address of the firewall MAC address table
- *
- * This function will send a message to the NPE configuring the
- * firewall mode (white list or black list), invalid source 
- * address filtering and downloading a new MAC address database 
- * to be used for firewall matching.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed 
- * successfully or IX_ETH_DB_FAIL otherwise
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBFirewallUpdate(IxEthDBPortId portID, void *address, UINT32 epDelta)
-{
-    IxNpeMhMessage message;
-    IX_STATUS result;
-    
-    UINT32 mode        = 0;    
-    PortInfo *portInfo = &ixEthDBPortInfo[portID];
-
-    mode = (portInfo->srcAddressFilterEnabled != FALSE) << 1 | (portInfo->firewallMode == IX_ETH_DB_FIREWALL_WHITE_LIST);
-
-    FILL_SETFIREWALLMODE_MSG(message, 
-        IX_ETH_DB_PORT_ID_TO_NPE_LOGICAL_ID(portID), 
-        epDelta, 
-        mode, 
-        IX_OSAL_MMU_VIRT_TO_PHYS(address));
-
-    IX_ETHDB_SEND_NPE_MSG(IX_ETH_DB_PORT_ID_TO_NPE(portID), message, result);
-    
-    return result;
-}
-
-/**
- * @brief configures the firewall white list/black list
- * access mode
- *
- * @param portID ID of the port
- * @param mode firewall filtering mode (IX_ETH_DB_FIREWALL_WHITE_LIST
- * or IX_ETH_DB_FIREWALL_BLACK_LIST)
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed
- * successfully or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBFirewallModeSet(IxEthDBPortId portID, IxEthDBFirewallMode mode)
-{
-    IX_ETH_DB_CHECK_PORT(portID);
-    
-    IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-     
-    IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_FIREWALL);
-    
-    if (mode != IX_ETH_DB_FIREWALL_WHITE_LIST
-        && mode != IX_ETH_DB_FIREWALL_BLACK_LIST)
-    {
-        return IX_ETH_DB_INVALID_ARG;
-    }    
-    
-    ixEthDBPortInfo[portID].firewallMode = mode;
-    
-    return ixEthDBFirewallTableDownload(portID);
-}
-
-/**
- * @brief enables or disables the invalid source MAC address filter
- *
- * @param portID ID of the port
- * @param enable TRUE to enable invalid source MAC address filtering
- * or FALSE to disable it
- *
- * The invalid source MAC address filter will discard, when enabled,
- * frames whose source MAC address is a multicast or the broadcast MAC
- * address.
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed 
- * successfully or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBFirewallInvalidAddressFilterEnable(IxEthDBPortId portID, BOOL enable)
-{
-    IX_ETH_DB_CHECK_PORT(portID);
-    
-    IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-    
-    IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_FIREWALL);
-
-    ixEthDBPortInfo[portID].srcAddressFilterEnabled = enable;
-    
-    return ixEthDBFirewallTableDownload(portID);
-}
-
-/**
- * @brief adds a firewall record
- *
- * @param portID ID of the port
- * @param macAddr MAC address of the new record
- *
- * This function will add a new firewall record
- * on the specified port, using the specified 
- * MAC address. If the record already exists this
- * function will silently return IX_ETH_DB_SUCCESS,
- * although no duplicate records are added.
- *
- * Note that this function is documented in the main
- * component header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed
- * successfully or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBFirewallEntryAdd(IxEthDBPortId portID, IxEthDBMacAddr *macAddr)
-{
-    MacDescriptor recordTemplate;
-
-    IX_ETH_DB_CHECK_PORT(portID);
-
-    IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
-    IX_ETH_DB_CHECK_REFERENCE(macAddr);
-
-    IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_FIREWALL);
-    
-    memcpy(recordTemplate.macAddress, macAddr, sizeof (IxEthDBMacAddr));
-    
-    recordTemplate.type   = IX_ETH_DB_FIREWALL_RECORD;
-    recordTemplate.portID = portID;
-    
-    return ixEthDBAdd(&recordTemplate, NULL);
-}
-
-/**
- * @brief removes a firewall record
- *
- * @param portID ID of the port
- * @param macAddr MAC address of the record to remove
- *
- * This function will attempt to remove a firewall
- * record from the given port, using the specified
- * MAC address.
- *
- * Note that this function is documented in the main
- * component header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed
- * successfully of an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBFirewallEntryRemove(IxEthDBPortId portID, IxEthDBMacAddr *macAddr)
-{
-    MacDescriptor recordTemplate;
-    
-    IX_ETH_DB_CHECK_PORT(portID);
-
-    IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
-    IX_ETH_DB_CHECK_REFERENCE(macAddr);
-
-    IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_FIREWALL);
-    
-    memcpy(recordTemplate.macAddress, macAddr, sizeof (IxEthDBMacAddr));
-    
-    recordTemplate.type   = IX_ETH_DB_FIREWALL_RECORD;
-    recordTemplate.portID = portID;
-    
-    return ixEthDBRemove(&recordTemplate, NULL);
-}
-
-/**
- * @brief downloads the firewall address table to an NPE
- *
- * @param portID ID of the port
- *
- * This function will download the firewall address table to
- * an NPE port.
- *
- * Note that this function is documented in the main 
- * component header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed
- * successfully or IX_ETH_DB_FAIL otherwise
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBFirewallTableDownload(IxEthDBPortId portID)
-{
-    IxEthDBPortMap query;
-    IxEthDBStatus result;
-    
-    IX_ETH_DB_CHECK_PORT(portID);
-
-    IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
-    IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_FIREWALL);
-    
-    SET_DEPENDENCY_MAP(query, portID);
-
-    ixEthDBUpdateLock();
-    
-    ixEthDBPortInfo[portID].updateMethod.searchTree = ixEthDBQuery(NULL, query, IX_ETH_DB_FIREWALL_RECORD, MAX_FW_SIZE);
-    
-    result = ixEthDBNPEUpdateHandler(portID, IX_ETH_DB_FIREWALL_RECORD);
-
-    ixEthDBUpdateUnlock();
-
-    return result;
-}
diff --git a/arch/arm/cpu/ixp/npe/IxEthDBHashtable.c b/arch/arm/cpu/ixp/npe/IxEthDBHashtable.c
deleted file mode 100644
index f1b18e6..0000000
--- a/arch/arm/cpu/ixp/npe/IxEthDBHashtable.c
+++ /dev/null
@@ -1,642 +0,0 @@
-/**
- * @file ethHash.c
- *
- * @brief Hashtable implementation
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- * 
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- * 
- * @par
- * -- End of Copyright Notice --
- */
-
-
-#include "IxEthDB_p.h"
-#include "IxEthDBLocks_p.h"
-
-/**
- * @addtogroup EthDB
- *
- * @{
- */
-
-/**
- * @brief initializes a hash table object
- *
- * @param hashTable uninitialized hash table structure
- * @param numBuckets number of buckets to use
- * @param entryHashFunction hash function used 
- * to hash entire hash node data block (for adding)
- * @param matchFunctions array of match functions, indexed on type,
- * used to differentiate records with the same hash value
- * @param freeFunction function used to free node data blocks
- *
- * Initializes the given hash table object.
- *
- * @internal
- */
-void ixEthDBInitHash(HashTable *hashTable, 
-                     UINT32 numBuckets, 
-                     HashFunction entryHashFunction, 
-                     MatchFunction *matchFunctions, 
-                     FreeFunction freeFunction)
-{
-    UINT32 bucketIndex;
-    UINT32 hashSize = numBuckets * sizeof(HashNode *);
-
-    /* entry hashing, matching and freeing methods */
-    hashTable->entryHashFunction  = entryHashFunction;
-    hashTable->matchFunctions     = matchFunctions;
-    hashTable->freeFunction       = freeFunction;
-
-    /* buckets */
-    hashTable->numBuckets = numBuckets;
-
-    /* set to 0 all buckets */
-    memset(hashTable->hashBuckets, 0, hashSize);
-
-    /* init bucket locks - note that initially all mutexes are unlocked after MutexInit()*/
-    for (bucketIndex = 0 ; bucketIndex < numBuckets ; bucketIndex++)
-    {
-        ixOsalFastMutexInit(&hashTable->bucketLocks[bucketIndex]);
-    }
-}
-
-/**
- * @brief adds an entry to the hash table
- *
- * @param hashTable hash table to add the entry to
- * @param entry entry to add
- *
- * The entry will be hashed using the entry hashing function and added to the
- * hash table, unless a locking blockage occurs, in which case the caller
- * should retry.
- *
- * @retval IX_ETH_DB_SUCCESS if adding <i>entry</i> has succeeded
- * @retval IX_ETH_DB_NOMEM if there's no memory left in the hash node pool
- * @retval IX_ETH_DB_BUSY if there's a locking failure on the insertion path
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBAddHashEntry(HashTable *hashTable, void *entry)
-{
-    UINT32 hashValue   = hashTable->entryHashFunction(entry);
-    UINT32 bucketIndex = hashValue % hashTable->numBuckets;
-    HashNode *bucket   = hashTable->hashBuckets[bucketIndex];
-    HashNode *newNode;
-
-    LockStack locks;
-
-    INIT_STACK(&locks);
-
-    /* lock bucket */
-    PUSH_LOCK(&locks, &hashTable->bucketLocks[bucketIndex]);
-
-    /* lock insertion element (first in chain), if any */
-    if (bucket != NULL)
-    {
-        PUSH_LOCK(&locks, &bucket->lock);
-    }
-
-    /* get new node */
-    newNode = ixEthDBAllocHashNode();
-
-    if (newNode == NULL)
-    {
-        /* unlock everything */
-        UNROLL_STACK(&locks);
-
-        return IX_ETH_DB_NOMEM;
-    }
-
-    /* init lock - note that mutexes are unlocked after MutexInit */
-    ixOsalFastMutexInit(&newNode->lock);
-
-    /* populate new link */
-    newNode->data = entry;
-
-    /* add to bucket */
-    newNode->next                       = bucket;
-    hashTable->hashBuckets[bucketIndex] = newNode;
-
-    /* unlock bucket and insertion point */
-    UNROLL_STACK(&locks);
-
-    return IX_ETH_DB_SUCCESS;
-}
-
-/**
- * @brief removes an entry from the hashtable
- *
- * @param hashTable hash table to remove entry from
- * @param keyType type of record key used for matching
- * @param reference reference key used to identify the entry
- *
- * The reference key will be hashed using the key hashing function,
- * the entry is searched using the hashed value and then examined
- * against the reference entry using the match function. A positive
- * match will trigger the deletion of the entry.
- * Locking failures are reported and the caller should retry.
- *
- * @retval IX_ETH_DB_SUCCESS if the removal was successful
- * @retval IX_ETH_DB_NO_SUCH_ADDR if the entry was not found
- * @retval IX_ETH_DB_BUSY if a locking failure occured during the process
- *
- * @internal
- */
-IxEthDBStatus ixEthDBRemoveHashEntry(HashTable *hashTable, int keyType, void *reference)
-{
-    UINT32 hashValue       = hashTable->entryHashFunction(reference);
-    UINT32 bucketIndex     = hashValue % hashTable->numBuckets;
-    HashNode *node         = hashTable->hashBuckets[bucketIndex];
-    HashNode *previousNode = NULL;
-    
-    LockStack locks;
-
-    INIT_STACK(&locks);
-
-    while (node != NULL)
-    {
-        /* try to lock node */
-        PUSH_LOCK(&locks, &node->lock);
-
-        if (hashTable->matchFunctions[keyType](reference, node->data))
-        {
-            /* found entry */
-            if (node->next != NULL)
-            {
-                PUSH_LOCK(&locks, &node->next->lock);
-            }
-
-            if (previousNode == NULL)
-            {
-                /* node is head of chain */
-                PUSH_LOCK(&locks, &hashTable->bucketLocks[bucketIndex]);
-
-                hashTable->hashBuckets[bucketIndex] = node->next;
-
-                POP_LOCK(&locks);
-            }
-            else
-            {
-                /* relink */
-                previousNode->next = node->next;
-            }
-
-            UNROLL_STACK(&locks);
-
-            /* free node */
-            hashTable->freeFunction(node->data);
-            ixEthDBFreeHashNode(node);
-
-            return IX_ETH_DB_SUCCESS;
-        }
-        else
-        {
-            if (previousNode != NULL)
-            {
-                /* unlock previous node */
-                SHIFT_STACK(&locks);
-            }
-
-            /* advance to next element in chain */
-            previousNode = node;
-            node         = node->next;
-        }
-    }
-
-    UNROLL_STACK(&locks);
-
-    /* not found */
-    return IX_ETH_DB_NO_SUCH_ADDR;
-}
-
-/**
- * @brief retrieves an entry from the hash table
- *
- * @param hashTable hash table to perform the search into
- * @param reference search key (a MAC address)
- * @param keyType type of record key used for matching
- * @param searchResult pointer where a reference to the located hash node 
- * is placed
- *
- * Searches the entry with the same key as <i>reference</i> and places the
- * pointer to the resulting node in <i>searchResult</i>.
- * An implicit write access lock is granted after a search, which gives the 
- * caller the opportunity to modify the entry.
- * Access should be released as soon as possible using @ref ixEthDBReleaseHashNode().
- *
- * @see ixEthDBReleaseHashNode()
- *
- * @retval IX_ETH_DB_SUCCESS if the search was completed successfully
- * @retval IX_ETH_DB_NO_SUCH_ADDRESS if no entry with the given key was found
- * @retval IX_ETH_DB_BUSY if a locking failure has occured, in which case
- * the caller should retry
- *
- * @warning unless the return value is <b>IX_ETH_DB_SUCCESS</b> the searchResult
- * location is NOT modified and therefore using a NULL comparison test when the
- * value was not properly initialized would be an error
- *
- * @internal
- */
-IxEthDBStatus ixEthDBSearchHashEntry(HashTable *hashTable, int keyType, void *reference, HashNode **searchResult)
-{
-    UINT32 hashValue;
-    HashNode *node;
-
-    hashValue = hashTable->entryHashFunction(reference);
-    node      = hashTable->hashBuckets[hashValue % hashTable->numBuckets];
-
-    while (node != NULL)
-    {
-        TRY_LOCK(&node->lock);
-
-        if (hashTable->matchFunctions[keyType](reference, node->data))
-        {
-            *searchResult = node;
-
-            return IX_ETH_DB_SUCCESS;
-        }
-        else
-        {
-            UNLOCK(&node->lock);
-
-            node = node->next;
-        }
-    }
-
-    /* not found */
-    return IX_ETH_DB_NO_SUCH_ADDR;
-}
-
-/**
- * @brief reports the existence of an entry in the hash table
- *
- * @param hashTable hash table to perform the search into
- * @param reference search key (a MAC address)
- * @param keyType type of record key used for matching
- *
- * Searches the entry with the same key as <i>reference</i>.
- * No implicit write access lock is granted after a search, hence the 
- * caller cannot access or modify the entry. The result is only temporary.
- *
- * @see ixEthDBReleaseHashNode()
- *
- * @retval IX_ETH_DB_SUCCESS if the search was completed successfully
- * @retval IX_ETH_DB_NO_SUCH_ADDRESS if no entry with the given key was found
- * @retval IX_ETH_DB_BUSY if a locking failure has occured, in which case
- * the caller should retry
- *
- * @internal
- */
-IxEthDBStatus ixEthDBPeekHashEntry(HashTable *hashTable, int keyType, void *reference)
-{
-    UINT32 hashValue;
-    HashNode *node;
-
-    hashValue = hashTable->entryHashFunction(reference);
-    node      = hashTable->hashBuckets[hashValue % hashTable->numBuckets];
-
-    while (node != NULL)
-    {
-        TRY_LOCK(&node->lock);
-
-        if (hashTable->matchFunctions[keyType](reference, node->data))
-        {
-            UNLOCK(&node->lock);
-
-            return IX_ETH_DB_SUCCESS;
-        }
-        else
-        {
-            UNLOCK(&node->lock);
-
-            node = node->next;
-        }
-    }
-
-    /* not found */
-    return IX_ETH_DB_NO_SUCH_ADDR;
-}
-
-/**
- * @brief releases the write access lock
- *
- * @pre the node should have been obtained via @ref ixEthDBSearchHashEntry()
- *
- * @see ixEthDBSearchHashEntry()
- *
- * @internal
- */
-void ixEthDBReleaseHashNode(HashNode *node)
-{
-    UNLOCK(&node->lock);
-}
-
-/**
- * @brief initializes a hash iterator
- *
- * @param hashTable hash table to be iterated
- * @param iterator iterator object
- *
- * If the initialization is successful the iterator will point to the
- * first hash table record (if any).
- * Testing if the iterator has not passed the end of the table should be
- * done using the IS_ITERATOR_VALID(iteratorPtr) macro.
- * An implicit write access lock is granted on the entry pointed by the iterator.
- * The access is automatically revoked when the iterator is incremented.
- * If the caller decides to terminate the iteration before the end of the table is
- * passed then the manual access release method, @ref ixEthDBReleaseHashIterator,
- * must be called.
- *
- * @see ixEthDBReleaseHashIterator()
- *
- * @retval IX_ETH_DB_SUCCESS if initialization was successful and the iterator points
- * to the first valid table node
- * @retval IX_ETH_DB_FAIL if the table is empty
- * @retval IX_ETH_DB_BUSY if a locking failure has occured, in which case the caller
- * should retry
- *
- * @warning do not use ixEthDBReleaseHashNode() on entries pointed by the iterator, as this
- * might place the database in a permanent invalid lock state
- *
- * @internal
- */
-IxEthDBStatus ixEthDBInitHashIterator(HashTable *hashTable, HashIterator *iterator)
-{
-    iterator->bucketIndex  = 0;
-    iterator->node         = NULL;
-    iterator->previousNode = NULL;
-
-    return ixEthDBIncrementHashIterator(hashTable, iterator);
-}
-
-/**
- * @brief releases the write access locks of the iterator nodes
- *
- * @warning use of this function is required only when the caller terminates an iteration
- * before reaching the end of the table
- *
- * @see ixEthDBInitHashIterator()
- * @see ixEthDBIncrementHashIterator()
- *
- * @param iterator iterator whose node(s) should be unlocked
- *
- * @internal
- */
-void ixEthDBReleaseHashIterator(HashIterator *iterator)
-{
-    if (iterator->previousNode != NULL)
-    {
-        UNLOCK(&iterator->previousNode->lock);
-    }
-
-    if (iterator->node != NULL)
-    {
-        UNLOCK(&iterator->node->lock);
-    }
-}
-
-/**
- * @brief incremenents an iterator so that it points to the next valid entry of the table
- * (if any)
- *
- * @param hashTable hash table to iterate
- * @param iterator iterator object
- *
- * @pre the iterator object must be initialized using @ref ixEthDBInitHashIterator()
- *
- * If the increment operation is successful the iterator will point to the
- * next hash table record (if any).
- * Testing if the iterator has not passed the end of the table should be
- * done using the IS_ITERATOR_VALID(iteratorPtr) macro.
- * An implicit write access lock is granted on the entry pointed by the iterator.
- * The access is automatically revoked when the iterator is re-incremented.
- * If the caller decides to terminate the iteration before the end of the table is
- * passed then the manual access release method, @ref ixEthDBReleaseHashIterator,
- * must be called.
- * Is is guaranteed that no other thread can remove or change the iterated entry until
- * the iterator is incremented successfully.
- *
- * @see ixEthDBReleaseHashIterator()
- *
- * @retval IX_ETH_DB_SUCCESS if the operation was successful and the iterator points
- * to the next valid table node
- * @retval IX_ETH_DB_FAIL if the iterator has passed the end of the table
- * @retval IX_ETH_DB_BUSY if a locking failure has occured, in which case the caller
- * should retry
- *
- * @warning do not use ixEthDBReleaseHashNode() on entries pointed by the iterator, as this
- * might place the database in a permanent invalid lock state
- *
- * @internal
- */
-IxEthDBStatus ixEthDBIncrementHashIterator(HashTable *hashTable, HashIterator *iterator)
-{
-    /* unless iterator is just initialized... */
-    if (iterator->node != NULL)
-    {
-        /* try next in chain */
-        if (iterator->node->next != NULL)
-        {
-            TRY_LOCK(&iterator->node->next->lock);
-
-            if (iterator->previousNode != NULL)
-            {
-                UNLOCK(&iterator->previousNode->lock);
-            }
-
-            iterator->previousNode = iterator->node;
-            iterator->node         = iterator->node->next;
-
-            return IX_ETH_DB_SUCCESS;
-        }
-        else
-        {
-            /* last in chain, prepare for next bucket */
-            iterator->bucketIndex++;
-        }
-    }
-
-   /* try next used bucket */
-    for (; iterator->bucketIndex < hashTable->numBuckets ; iterator->bucketIndex++)
-    {
-        HashNode **nodePtr = &(hashTable->hashBuckets[iterator->bucketIndex]);
-        HashNode *node = *nodePtr;
-#if (CPU!=SIMSPARCSOLARIS) && !defined (__wince)
-        if (((iterator->bucketIndex & IX_ETHDB_BUCKET_INDEX_MASK) == 0) &&
-            (iterator->bucketIndex < (hashTable->numBuckets - IX_ETHDB_BUCKETPTR_AHEAD)))
-        {
-            /* preload next cache line (2 cache line ahead) */
-            nodePtr += IX_ETHDB_BUCKETPTR_AHEAD;
-            __asm__ ("pld [%0];\n": : "r" (nodePtr));
-        }
-#endif
-        if (node != NULL)
-        {
-            TRY_LOCK(&node->lock);
-
-            /* unlock last one or two nodes in the previous chain */
-            if (iterator->node != NULL)
-            {
-                UNLOCK(&iterator->node->lock);
-
-                if (iterator->previousNode != NULL)
-                {
-                    UNLOCK(&iterator->previousNode->lock);
-                }
-            }
-            
-            /* redirect iterator */
-            iterator->previousNode = NULL;
-            iterator->node         = node;
-
-            return IX_ETH_DB_SUCCESS;
-        }
-    }
-
-    /* could not advance iterator */
-    if (iterator->node != NULL)
-    {
-        UNLOCK(&iterator->node->lock);
-
-        if (iterator->previousNode != NULL)
-        {
-            UNLOCK(&iterator->previousNode->lock);
-        }
-
-        iterator->node = NULL;
-    }
-
-    return IX_ETH_DB_END;
-}
-
-/**
- * @brief removes an entry pointed by an iterator
- *
- * @param hashTable iterated hash table
- * @param iterator iterator object
- *
- * Removes the entry currently pointed by the iterator and repositions the iterator
- * on the next valid entry (if any). Handles locking issues automatically and
- * implicitely grants write access lock to the new pointed entry.
- * Failures due to concurrent threads having write access locks in the same region
- * preserve the state of the database and the iterator object, leaving the caller
- * free to retry without loss of access. It is guaranteed that only the thread owning
- * the iterator can remove the object pointed by the iterator.
- *
- * @retval IX_ETH_DB_SUCCESS if removal has succeeded
- * @retval IX_ETH_DB_BUSY if a locking failure has occured, in which case the caller
- * should retry
- *
- * @internal
- */
-IxEthDBStatus ixEthDBRemoveEntryAtHashIterator(HashTable *hashTable, HashIterator *iterator)
-{
-    HashIterator nextIteratorPos;
-    LockStack locks;
-
-    INIT_STACK(&locks);
-
-    /* set initial bucket index for next position */
-    nextIteratorPos.bucketIndex = iterator->bucketIndex;
-
-    /* compute iterator position before removing anything and lock ahead */
-    if (iterator->node->next != NULL)
-    {
-        PUSH_LOCK(&locks, &iterator->node->next->lock);
-
-        /* reposition on the next node in the chain */
-        nextIteratorPos.node         = iterator->node->next;
-        nextIteratorPos.previousNode = iterator->previousNode;
-    }
-    else
-    {
-        /* try next chain - don't know yet if we'll find anything */
-        nextIteratorPos.node = NULL;
-
-        /* if we find something it's a chain head */
-        nextIteratorPos.previousNode = NULL;
-
-        /* browse up in the buckets to find a non-null chain */
-        while (++nextIteratorPos.bucketIndex < hashTable->numBuckets)
-        {
-            nextIteratorPos.node = hashTable->hashBuckets[nextIteratorPos.bucketIndex];
-
-            if (nextIteratorPos.node != NULL)
-            {
-                /* found a non-empty chain, try to lock head */
-                PUSH_LOCK(&locks, &nextIteratorPos.node->lock);
-
-                break;
-            }
-        }
-    }
-
-    /* restore links over the to-be-deleted item */
-    if (iterator->previousNode == NULL)
-    {
-        /* first in chain, lock bucket */
-        PUSH_LOCK(&locks, &hashTable->bucketLocks[iterator->bucketIndex]);
-
-        hashTable->hashBuckets[iterator->bucketIndex] = iterator->node->next;
-
-        POP_LOCK(&locks);
-    }
-    else
-    {
-        /* relink */
-        iterator->previousNode->next = iterator->node->next;
-
-        /* unlock last remaining node in current chain when moving between chains */
-        if (iterator->node->next == NULL)
-        {
-            UNLOCK(&iterator->previousNode->lock);
-        }
-    }
-
-    /* delete entry */
-    hashTable->freeFunction(iterator->node->data);
-    ixEthDBFreeHashNode(iterator->node);
-
-    /* reposition iterator */
-    *iterator = nextIteratorPos;
-
-    return IX_ETH_DB_SUCCESS;
-}
-
-/**
- * @}
- */
diff --git a/arch/arm/cpu/ixp/npe/IxEthDBLearning.c b/arch/arm/cpu/ixp/npe/IxEthDBLearning.c
deleted file mode 100644
index 2287dbe..0000000
--- a/arch/arm/cpu/ixp/npe/IxEthDBLearning.c
+++ /dev/null
@@ -1,149 +0,0 @@
-/**
- * @file IxEthDBLearning.c
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- * 
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- * 
- * @par
- * -- End of Copyright Notice --
- */
-
-#include "IxEthDB_p.h"
-
-/**
- * @brief hashes the mac address in a mac descriptor with a XOR function
- *
- * @param entry pointer to a mac descriptor to be hashed
- * 
- * This function only extracts the mac address and employs ixEthDBKeyXORHash()
- * to do the actual hashing.
- * Used only to add a whole entry to a hash table, as opposed to searching which
- * takes only a key and uses the key hashing directly.
- *
- * @see ixEthDBKeyXORHash()
- *
- * @return the hash value
- *
- * @internal
- */
-UINT32 ixEthDBEntryXORHash(void *entry)
-{
-    MacDescriptor *descriptor = (MacDescriptor *) entry;
-
-    return ixEthDBKeyXORHash(descriptor->macAddress);
-}
-
-/**
- * @brief hashes a mac address
- *
- * @param key pointer to a 6 byte structure (typically an IxEthDBMacAddr pointer)
- * to be hashed
- *
- * Given a 6 bytes MAC address, the hash used is:
- *
- * hash(MAC[0:5]) = MAC[0:1] ^ MAC[2:3] ^ MAC[4:5]
- *
- * Used by the hash table to search and remove entries based
- * solely on their keys (mac addresses).
- *
- * @return the hash value
- *
- * @internal
- */
-UINT32 ixEthDBKeyXORHash(void *key)
-{
-    UINT32 hashValue;
-    UINT8 *value = (UINT8 *) key;
-    
-    hashValue  = (value[5] << 8) | value[4];
-    hashValue ^= (value[3] << 8) | value[2];
-    hashValue ^= (value[1] << 8) | value[0];
-
-    return hashValue;
-}
-
-/**
- * @brief mac descriptor match function
- *
- * @param reference mac address (typically an IxEthDBMacAddr pointer) structure
- * @param entry pointer to a mac descriptor whose key (mac address) is to be 
- * matched against the reference key
- *
- * Used by the hash table to retrieve entries. Hashing entries can produce
- * collisions, i.e. descriptors with different mac addresses and the same
- * hash value, where this function is used to differentiate entries.
- *
- * @retval TRUE if the entry matches the reference key (equal addresses)
- * @retval FALSE if the entry does not match the reference key
- *
- * @internal
- */
-BOOL ixEthDBAddressMatch(void *reference, void *entry)
-{
-    return (ixEthDBAddressCompare(reference, ((MacDescriptor *) entry)->macAddress) == 0);
-}
-
-/**
- * @brief compares two mac addresses
- *
- * @param mac1 first mac address to compare
- * @param mac2 second mac address to compare
- * 
- * This comparison works in a similar way to strcmp, producing similar results.
- * Used to insert values keyed on mac addresses into binary search trees.
- *
- * @retval -1 if mac1 < mac2
- * @retval 0 if ma1 == mac2
- * @retval 1 if mac1 > mac2
- */
-UINT32 ixEthDBAddressCompare(UINT8 *mac1, UINT8 *mac2)
-{
-    UINT32 local_index;
-
-    for (local_index = 0 ; local_index < IX_IEEE803_MAC_ADDRESS_SIZE ; local_index++)
-    {
-        if (mac1[local_index] > mac2[local_index])
-        {
-            return 1;
-        }
-        else if (mac1[local_index] < mac2[local_index])
-        {
-            return -1;
-        }
-    }
-
-    return 0;
-}
-
diff --git a/arch/arm/cpu/ixp/npe/IxEthDBMem.c b/arch/arm/cpu/ixp/npe/IxEthDBMem.c
deleted file mode 100644
index 133cbef..0000000
--- a/arch/arm/cpu/ixp/npe/IxEthDBMem.c
+++ /dev/null
@@ -1,649 +0,0 @@
-/**
- * @file IxEthDBDBMem.c
- *
- * @brief Memory handling routines for the MAC address database
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- * 
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- * 
- * @par
- * -- End of Copyright Notice --
- */
-
-
-#include "IxEthDB_p.h"
-
-IX_ETH_DB_PRIVATE HashNode *nodePool     = NULL;
-IX_ETH_DB_PRIVATE MacDescriptor *macPool = NULL;
-IX_ETH_DB_PRIVATE MacTreeNode *treePool  = NULL;
-
-IX_ETH_DB_PRIVATE HashNode nodePoolArea[NODE_POOL_SIZE];
-IX_ETH_DB_PRIVATE MacDescriptor macPoolArea[MAC_POOL_SIZE];
-IX_ETH_DB_PRIVATE MacTreeNode treePoolArea[TREE_POOL_SIZE];
-
-IX_ETH_DB_PRIVATE IxOsalMutex nodePoolLock;
-IX_ETH_DB_PRIVATE IxOsalMutex macPoolLock;
-IX_ETH_DB_PRIVATE IxOsalMutex treePoolLock;
-
-#define LOCK_NODE_POOL   { ixOsalMutexLock(&nodePoolLock, IX_OSAL_WAIT_FOREVER); }
-#define UNLOCK_NODE_POOL { ixOsalMutexUnlock(&nodePoolLock); }
-
-#define LOCK_MAC_POOL    { ixOsalMutexLock(&macPoolLock, IX_OSAL_WAIT_FOREVER); }
-#define UNLOCK_MAC_POOL  { ixOsalMutexUnlock(&macPoolLock); }
-
-#define LOCK_TREE_POOL   { ixOsalMutexLock(&treePoolLock, IX_OSAL_WAIT_FOREVER); }
-#define UNLOCK_TREE_POOL { ixOsalMutexUnlock(&treePoolLock); }
-
-/* private function prototypes */
-IX_ETH_DB_PRIVATE MacDescriptor* ixEthDBPoolAllocMacDescriptor(void);
-IX_ETH_DB_PRIVATE void ixEthDBPoolFreeMacDescriptor(MacDescriptor *macDescriptor);
-
-/**
- * @addtogroup EthMemoryManagement
- *
- * @{
- */
-
-/**
- * @brief initializes the memory pools used by the ethernet database component
- *
- * Initializes the hash table node, mac descriptor and mac tree node pools.
- * Called at initialization time by @ref ixEthDBInit().
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-void ixEthDBInitMemoryPools(void)
-{
-    int local_index;
-
-    /* HashNode pool */
-    ixOsalMutexInit(&nodePoolLock);
-
-    for (local_index = 0 ; local_index < NODE_POOL_SIZE ; local_index++)
-    {
-        HashNode *freeNode = &nodePoolArea[local_index];
-
-        freeNode->nextFree = nodePool;
-        nodePool           = freeNode;
-    }
-
-    /* MacDescriptor pool */
-    ixOsalMutexInit(&macPoolLock);
-
-    for (local_index = 0 ; local_index < MAC_POOL_SIZE ; local_index++)
-    {
-        MacDescriptor *freeDescriptor = &macPoolArea[local_index];
-
-        freeDescriptor->nextFree = macPool;
-        macPool                  = freeDescriptor;
-    }
-
-    /* MacTreeNode pool */
-    ixOsalMutexInit(&treePoolLock);
-
-    for (local_index = 0 ; local_index < TREE_POOL_SIZE ; local_index++)
-    {
-        MacTreeNode *freeNode = &treePoolArea[local_index];
-
-        freeNode->nextFree = treePool;
-        treePool           = freeNode;
-    }
-}
-
-/**
- * @brief allocates a hash node from the pool
- *
- * Allocates a hash node and resets its value.
- *
- * @return the allocated hash node or NULL if the pool is empty
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-HashNode* ixEthDBAllocHashNode(void)
-{
-    HashNode *allocatedNode = NULL;
-
-    if (nodePool != NULL)
-    {
-        LOCK_NODE_POOL;
-
-        allocatedNode = nodePool;
-        nodePool      = nodePool->nextFree;
-
-        UNLOCK_NODE_POOL;
-
-        memset(allocatedNode, 0, sizeof(HashNode));
-    }
-
-    return allocatedNode;
-}
-
-/**
- * @brief frees a hash node into the pool
- *
- * @param hashNode node to be freed
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-void ixEthDBFreeHashNode(HashNode *hashNode)
-{
-    if (hashNode != NULL)
-    {
-        LOCK_NODE_POOL;
-
-        hashNode->nextFree = nodePool;
-        nodePool           = hashNode;
-
-        UNLOCK_NODE_POOL;
-    }
-}
-
-/**
- * @brief allocates a mac descriptor from the pool
- *
- * Allocates a mac descriptor and resets its value.
- * This function is not used directly, instead @ref ixEthDBAllocMacDescriptor()
- * is used, which keeps track of the pointer reference count.
- *
- * @see ixEthDBAllocMacDescriptor()
- * 
- * @warning this function is not used directly by any other function
- * apart from ixEthDBAllocMacDescriptor()
- *
- * @return the allocated mac descriptor or NULL if the pool is empty
- *
- * @internal
- */
-IX_ETH_DB_PRIVATE
-MacDescriptor* ixEthDBPoolAllocMacDescriptor(void)
-{
-    MacDescriptor *allocatedDescriptor = NULL;
-
-    if (macPool != NULL)
-    {
-        LOCK_MAC_POOL;
-
-        allocatedDescriptor = macPool;
-        macPool             = macPool->nextFree;
-
-        UNLOCK_MAC_POOL;
-
-        memset(allocatedDescriptor, 0, sizeof(MacDescriptor));
-    }
-
-    return allocatedDescriptor;
-}
-
-/**
- * @brief allocates and initializes a mac descriptor smart pointer
- *
- * Uses @ref ixEthDBPoolAllocMacDescriptor() to allocate a mac descriptor
- * from the pool and initializes its reference count.
- *
- * @see ixEthDBPoolAllocMacDescriptor()
- *
- * @return the allocated mac descriptor or NULL if the pool is empty
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-MacDescriptor* ixEthDBAllocMacDescriptor(void)
-{
-    MacDescriptor *allocatedDescriptor = ixEthDBPoolAllocMacDescriptor();
-
-    if (allocatedDescriptor != NULL)
-    {
-        LOCK_MAC_POOL;
-
-        allocatedDescriptor->refCount++;
-
-        UNLOCK_MAC_POOL;
-    }
-
-    return allocatedDescriptor;
-}
-
-/**
- * @brief frees a mac descriptor back into the pool
- *
- * @param macDescriptor mac descriptor to be freed
- *
- * @warning this function is not to be called by anyone but
- * ixEthDBFreeMacDescriptor()
- *
- * @see ixEthDBFreeMacDescriptor()
- *
- * @internal
- */
-IX_ETH_DB_PRIVATE
-void ixEthDBPoolFreeMacDescriptor(MacDescriptor *macDescriptor)
-{
-    LOCK_MAC_POOL;
-
-    macDescriptor->nextFree = macPool;
-    macPool                 = macDescriptor;
-
-    UNLOCK_MAC_POOL;
-}
-
-/**
- * @brief frees or reduces the usage count of a mac descriptor smart pointer
- *
- * If the reference count reaches 0 (structure is no longer used anywhere)
- * then the descriptor is freed back into the pool using ixEthDBPoolFreeMacDescriptor().
- *
- * @see ixEthDBPoolFreeMacDescriptor()
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-void ixEthDBFreeMacDescriptor(MacDescriptor *macDescriptor)
-{
-    if (macDescriptor != NULL)
-    {
-        LOCK_MAC_POOL;
-
-        if (macDescriptor->refCount > 0)
-        {
-            macDescriptor->refCount--;
-
-            if (macDescriptor->refCount == 0)
-            {
-                UNLOCK_MAC_POOL;
-
-                ixEthDBPoolFreeMacDescriptor(macDescriptor);
-            }
-            else
-            {
-                UNLOCK_MAC_POOL;
-            }
-        }
-        else
-        {
-            UNLOCK_MAC_POOL;
-        }
-    }
-}
-
-/**
- * @brief clones a mac descriptor smart pointer
- *
- * @param macDescriptor mac descriptor to clone
- *
- * Increments the usage count of the smart pointer
- *
- * @returns the cloned smart pointer
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-MacDescriptor* ixEthDBCloneMacDescriptor(MacDescriptor *macDescriptor)
-{
-    LOCK_MAC_POOL;
-
-    if (macDescriptor->refCount == 0)
-    {
-        UNLOCK_MAC_POOL;
-
-        return NULL;
-    }
-
-    macDescriptor->refCount++;
-
-    UNLOCK_MAC_POOL;
-
-    return macDescriptor;
-}
-
-/**
- * @brief allocates a mac tree node from the pool
- *
- * Allocates and initializes a mac tree node from the pool.
- *
- * @return the allocated mac tree node or NULL if the pool is empty
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-MacTreeNode* ixEthDBAllocMacTreeNode(void)
-{
-    MacTreeNode *allocatedNode = NULL;
-
-    if (treePool != NULL)
-    {
-        LOCK_TREE_POOL;
-
-        allocatedNode = treePool;
-        treePool      = treePool->nextFree;
-
-        UNLOCK_TREE_POOL;
-
-        memset(allocatedNode, 0, sizeof(MacTreeNode));
-    }
-
-    return allocatedNode;
-}
-
-/**
- * @brief frees a mac tree node back into the pool
- *
- * @param macNode mac tree node to be freed
- *
- * @warning not to be used except from ixEthDBFreeMacTreeNode().
- *
- * @see ixEthDBFreeMacTreeNode()
- *
- * @internal
- */
-void ixEthDBPoolFreeMacTreeNode(MacTreeNode *macNode)
-{
-    if (macNode != NULL)
-    {
-        LOCK_TREE_POOL;
-
-        macNode->nextFree = treePool;
-        treePool          = macNode;
-
-        UNLOCK_TREE_POOL;
-    }
-}
-
-/**
- * @brief frees or reduces the usage count of a mac tree node smart pointer
- *
- * @param macNode mac tree node to free
- *
- * Reduces the usage count of the given mac node. If the usage count
- * reaches 0 the node is freed back into the pool using ixEthDBPoolFreeMacTreeNode()
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-void ixEthDBFreeMacTreeNode(MacTreeNode *macNode)
-{
-    if (macNode->descriptor != NULL)
-    {
-        ixEthDBFreeMacDescriptor(macNode->descriptor);
-    }
-
-    if (macNode->left != NULL)
-    {
-        ixEthDBFreeMacTreeNode(macNode->left);
-    }
-
-    if (macNode->right != NULL)
-    {
-        ixEthDBFreeMacTreeNode(macNode->right);
-    }
-
-    ixEthDBPoolFreeMacTreeNode(macNode);
-}
-
-/**
- * @brief clones a mac tree node
- *
- * @param macNode mac tree node to be cloned
- *
- * Increments the usage count of the node, <i>its associated descriptor 
- * and <b>recursively</b> of all its child nodes</i>.
- *
- * @warning this function is recursive and clones whole trees/subtrees, use only for
- * root nodes
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-MacTreeNode* ixEthDBCloneMacTreeNode(MacTreeNode *macNode)
-{
-    if (macNode != NULL)
-    {
-        MacTreeNode *clonedMacNode = ixEthDBAllocMacTreeNode();
-
-        if (clonedMacNode != NULL)
-        {
-            if (macNode->right != NULL)
-            {
-                clonedMacNode->right = ixEthDBCloneMacTreeNode(macNode->right);
-            }
-
-            if (macNode->left != NULL)
-            {
-                clonedMacNode->left = ixEthDBCloneMacTreeNode(macNode->left);
-            }
-
-            if (macNode->descriptor != NULL)
-            {
-                clonedMacNode->descriptor = ixEthDBCloneMacDescriptor(macNode->descriptor);
-            }
-        }
-
-        return clonedMacNode;
-    }
-    else
-    {
-        return NULL;
-    }
-}
-
-#ifndef NDEBUG
-/* Debug statistical functions for memory usage */
-
-extern HashTable dbHashtable;
-int ixEthDBNumHashElements(void);
-
-int ixEthDBNumHashElements(void)
-{   
-    UINT32 bucketIndex;
-    int numElements = 0;
-    HashTable *hashTable = &dbHashtable;
-
-    for (bucketIndex = 0 ; bucketIndex < hashTable->numBuckets ; bucketIndex++)
-    {
-        if (hashTable->hashBuckets[bucketIndex] != NULL)
-        {
-            HashNode *node = hashTable->hashBuckets[bucketIndex];
-
-            while (node != NULL)
-            {
-                numElements++;
-
-                node = node->next;
-            }
-        }
-    }
-
-    return numElements;
-}
-
-UINT32 ixEthDBSearchTreeUsageGet(MacTreeNode *tree)
-{
-    if (tree == NULL)
-    {
-        return 0;
-    }
-    else
-    {
-        return 1 /* this node */ + ixEthDBSearchTreeUsageGet(tree->left) + ixEthDBSearchTreeUsageGet(tree->right);
-    }
-}
-
-int ixEthDBShowMemoryStatus(void)
-{
-    MacDescriptor *mac;
-    MacTreeNode *tree;
-    HashNode *node;
-
-    int macCounter  = 0;
-    int treeCounter = 0;
-    int nodeCounter = 0;
-
-    int totalTreeUsage            = 0;
-    int totalDescriptorUsage      = 0;
-    int totalCloneDescriptorUsage = 0;
-    int totalNodeUsage            = 0;
-
-    UINT32 portIndex;
-
-    LOCK_NODE_POOL;
-    LOCK_MAC_POOL;
-    LOCK_TREE_POOL;
-
-    mac  = macPool;
-    tree = treePool;
-    node = nodePool;
-
-    while (mac != NULL)
-    {
-        macCounter++;
-
-        mac = mac->nextFree;
-
-        if (macCounter > MAC_POOL_SIZE)
-        {
-            break;
-        }
-    }
-
-    while (tree != NULL)
-    {
-        treeCounter++;
-
-        tree = tree->nextFree;
-
-        if (treeCounter > TREE_POOL_SIZE)
-        {
-            break;
-        }
-    }
-
-    while (node != NULL)
-    {
-        nodeCounter++;
-
-        node = node->nextFree;
-
-        if (nodeCounter > NODE_POOL_SIZE)
-        {
-            break;
-        }
-    }
-
-    for (portIndex = 0 ; portIndex < IX_ETH_DB_NUMBER_OF_PORTS ; portIndex++)
-    {
-        int treeUsage = ixEthDBSearchTreeUsageGet(ixEthDBPortInfo[portIndex].updateMethod.searchTree);
-
-        totalTreeUsage            += treeUsage;
-        totalCloneDescriptorUsage += treeUsage; /* each tree node contains a descriptor */
-    }
-
-    totalNodeUsage        = ixEthDBNumHashElements();
-    totalDescriptorUsage += totalNodeUsage; /* each hash table entry contains a descriptor */
-
-    UNLOCK_NODE_POOL;
-    UNLOCK_MAC_POOL;
-    UNLOCK_TREE_POOL;
-
-    printf("Ethernet database memory usage stats:\n\n");
-
-    if (macCounter <= MAC_POOL_SIZE)
-    {
-        printf("\tMAC descriptor pool  : %d free out of %d entries (%d%%)\n", macCounter, MAC_POOL_SIZE, macCounter * 100 / MAC_POOL_SIZE);
-    }
-    else
-    {
-        printf("\tMAC descriptor pool  : invalid state (ring within the pool), normally %d entries\n", MAC_POOL_SIZE);
-    }
-
-    if (treeCounter <= TREE_POOL_SIZE)
-    {
-	printf("\tTree node pool       : %d free out of %d entries (%d%%)\n", treeCounter, TREE_POOL_SIZE, treeCounter * 100 / TREE_POOL_SIZE);
-    }
-    else
-    {
-        printf("\tTREE descriptor pool  : invalid state (ring within the pool), normally %d entries\n", TREE_POOL_SIZE);
-    }
-
-    if (nodeCounter <= NODE_POOL_SIZE)
-    {
-	printf("\tHash node pool       : %d free out of %d entries (%d%%)\n", nodeCounter, NODE_POOL_SIZE, nodeCounter * 100 / NODE_POOL_SIZE);
-    }
-    else
-    {
-        printf("\tNODE descriptor pool  : invalid state (ring within the pool), normally %d entries\n", NODE_POOL_SIZE);
-    }
-
-    printf("\n");
-    printf("\tMAC descriptor usage : %d entries, %d cloned\n", totalDescriptorUsage, totalCloneDescriptorUsage);
-    printf("\tTree node usage      : %d entries\n", totalTreeUsage);
-    printf("\tHash node usage      : %d entries\n", totalNodeUsage);
-    printf("\n");
-
-    /* search for duplicate nodes in the mac pool */
-    {
-        MacDescriptor *reference = macPool;
-
-        while (reference != NULL)
-        {
-            MacDescriptor *comparison = reference->nextFree;
-
-            while (comparison != NULL)
-            {
-                if (reference == comparison)
-                {
-                    printf("Warning: reached a duplicate (%p), invalid MAC pool state\n", reference);
-
-                    return 1;
-                }
-
-                comparison = comparison->nextFree;
-            }
-
-            reference = reference->nextFree;
-        }
-    }
-
-    printf("No duplicates found in the MAC pool (sanity check ok)\n");
-
-    return 0;
-}
-
-#endif /* NDEBUG */
-
-/**
- * @} EthMemoryManagement
- */
diff --git a/arch/arm/cpu/ixp/npe/IxEthDBNPEAdaptor.c b/arch/arm/cpu/ixp/npe/IxEthDBNPEAdaptor.c
deleted file mode 100644
index 112a46c..0000000
--- a/arch/arm/cpu/ixp/npe/IxEthDBNPEAdaptor.c
+++ /dev/null
@@ -1,719 +0,0 @@
-/**
- * @file IxEthDBDBNPEAdaptor.c
- *
- * @brief Routines that read and write learning/search trees in NPE-specific format
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- * 
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- * 
- * @par
- * -- End of Copyright Notice --
- */
-
-#include "IxEthDB_p.h"
-#include "IxEthDBLog_p.h"
-
-/* forward prototype declarations */
-IX_ETH_DB_PUBLIC void ixEthDBELTShow(IxEthDBPortId portID);
-IX_ETH_DB_PUBLIC void ixEthDBShowNpeMsgHistory(void);
-
-/* data */
-UINT8* ixEthDBNPEUpdateArea[IX_ETH_DB_NUMBER_OF_PORTS];
-UINT32 dumpEltSize;
-
-/* private data */
-IX_ETH_DB_PRIVATE IxEthDBNoteWriteFn ixEthDBNPENodeWrite[IX_ETH_DB_MAX_RECORD_TYPE_INDEX + 1];
-
-#define IX_ETH_DB_MAX_DELTA_ZONES (6) /* at most 6 EP Delta zones, according to NPE FS */
-IX_ETH_DB_PRIVATE UINT32 ixEthDBEPDeltaOffset[IX_ETH_DB_MAX_RECORD_TYPE_INDEX + 1][IX_ETH_DB_MAX_DELTA_ZONES]; 
-IX_ETH_DB_PRIVATE UINT32 ixEthDBEPDelta[IX_ETH_DB_MAX_RECORD_TYPE_INDEX + 1][IX_ETH_DB_MAX_DELTA_ZONES];
-
-/**
- * @brief allocates non-cached or contiguous NPE tree update areas for all the ports
- *
- * This function is called only once at initialization time from
- * @ref ixEthDBInit().
- *
- * @warning do not call manually
- *
- * @see ixEthDBInit()
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-void ixEthDBNPEUpdateAreasInit(void)
-{
-    UINT32 portIndex;
-    PortUpdateMethod *update;
-
-    for (portIndex = 0 ; portIndex < IX_ETH_DB_NUMBER_OF_PORTS ; portIndex++)
-    {
-        update = &ixEthDBPortInfo[portIndex].updateMethod;
-
-        if (ixEthDBPortDefinitions[portIndex].type == IX_ETH_NPE)
-        {
-            update->npeUpdateZone   = IX_OSAL_CACHE_DMA_MALLOC(FULL_ELT_BYTE_SIZE);
-            update->npeGwUpdateZone = IX_OSAL_CACHE_DMA_MALLOC(FULL_GW_BYTE_SIZE);
-            update->vlanUpdateZone  = IX_OSAL_CACHE_DMA_MALLOC(FULL_VLAN_BYTE_SIZE);
-
-            if (update->npeUpdateZone == NULL
-                || update->npeGwUpdateZone == NULL
-                || update->vlanUpdateZone == NULL)
-            {
-                ERROR_LOG("Fatal error: IX_ACC_DRV_DMA_MALLOC() returned NULL, no NPE update zones available\n");
-            }
-            else
-            {
-                memset(update->npeUpdateZone, 0, FULL_ELT_BYTE_SIZE);
-                memset(update->npeGwUpdateZone, 0, FULL_GW_BYTE_SIZE);
-                memset(update->vlanUpdateZone, 0, FULL_VLAN_BYTE_SIZE);
-            }
-        }
-        else
-        {
-            /* unused */
-            update->npeUpdateZone   = NULL;
-            update->npeGwUpdateZone = NULL;
-            update->vlanUpdateZone  = NULL;
-        }
-    }
-}
-
-/**
- * @brief deallocates the NPE update areas for all the ports
- *
- * This function is called at component de-initialization time
- * by @ref ixEthDBUnload().
- *
- * @warning do not call manually
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-void ixEthDBNPEUpdateAreasUnload(void)
-{
-    UINT32 portIndex;
-
-    for (portIndex = 0 ; portIndex < IX_ETH_DB_NUMBER_OF_PORTS ; portIndex++)
-    {
-        if (ixEthDBPortDefinitions[portIndex].type == IX_ETH_NPE)
-        {
-            IX_OSAL_CACHE_DMA_FREE(ixEthDBPortInfo[portIndex].updateMethod.npeUpdateZone);
-            IX_OSAL_CACHE_DMA_FREE(ixEthDBPortInfo[portIndex].updateMethod.npeGwUpdateZone);
-            IX_OSAL_CACHE_DMA_FREE(ixEthDBPortInfo[portIndex].updateMethod.vlanUpdateZone);
-        }
-    }
-}
-
-/**
- * @brief general-purpose NPE callback function
- *
- * @param npeID NPE ID
- * @param msg NPE message
- *
- * This function will unblock the caller by unlocking
- * the npeAckLock mutex defined for each NPE port
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-void ixEthDBNpeMsgAck(IxNpeMhNpeId npeID, IxNpeMhMessage msg)
-{
-    IxEthDBPortId portID = IX_ETH_DB_NPE_TO_PORT_ID(npeID);
-    PortInfo *portInfo;
-
-    if (portID >= IX_ETH_DB_NUMBER_OF_PORTS)
-    {
-        /* invalid port */
-        return;
-    }
-
-    if (ixEthDBPortDefinitions[portID].type != IX_ETH_NPE)
-    {
-        /* not an NPE */
-        return;
-    }
-
-    portInfo = &ixEthDBPortInfo[portID];
-    
-    ixOsalMutexUnlock(&portInfo->npeAckLock);
-}
-
-/**
- * @brief synchronizes the database with tree
- *
- * @param portID port ID of the NPE whose tree is to be scanned
- * @param eltBaseAddress memory base address of the NPE serialized tree
- * @param eltSize size in bytes of the NPE serialized tree
- *
- * Scans the NPE learning tree and resets the age of active database records.
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-void ixEthDBNPESyncScan(IxEthDBPortId portID, void *eltBaseAddress, UINT32 eltSize)
-{
-    UINT32 eltEntryOffset;
-    UINT32 entryPortID;
-
-    /* invalidate cache */
-    IX_OSAL_CACHE_INVALIDATE(eltBaseAddress, eltSize);
-
-    for (eltEntryOffset = ELT_ROOT_OFFSET ; eltEntryOffset < eltSize ; eltEntryOffset += ELT_ENTRY_SIZE)
-    {
-        /* (eltBaseAddress + eltEntryOffset) points to a valid NPE tree node
-         *
-         * the format of the node is MAC[6 bytes]:PortID[1 byte]:Reserved[6 bits]:Active[1 bit]:Valid[1 bit]
-         * therefore we can just use the pointer for database searches as only the first 6 bytes are checked
-         */
-        void *eltNodeAddress       = (void *) ((UINT32) eltBaseAddress + eltEntryOffset);
-
-        /* debug */
-        IX_ETH_DB_NPE_VERBOSE_TRACE("DB: (NPEAdaptor) checking node at offset %d...\n", eltEntryOffset / ELT_ENTRY_SIZE);
-
-        if (IX_EDB_NPE_NODE_VALID(eltNodeAddress) != TRUE)
-        {
-            IX_ETH_DB_NPE_VERBOSE_TRACE("\t... node is empty\n");
-        }
-        else if (eltEntryOffset == ELT_ROOT_OFFSET)
-        {
-            IX_ETH_DB_NPE_VERBOSE_TRACE("\t... node is root\n");
-        }
-
-        if (IX_EDB_NPE_NODE_VALID(eltNodeAddress))
-        {
-            entryPortID = IX_ETH_DB_NPE_LOGICAL_ID_TO_PORT_ID(IX_EDB_NPE_NODE_PORT_ID(eltNodeAddress));
-
-            /* check only active entries belonging to this port */
-            if (ixEthDBPortInfo[portID].agingEnabled && IX_EDB_NPE_NODE_ACTIVE(eltNodeAddress) && (portID == entryPortID)
-                && ((ixEthDBPortDefinitions[portID].capabilities & IX_ETH_ENTRY_AGING) == 0))
-            {
-                /* search record */
-                HashNode *node = ixEthDBSearch((IxEthDBMacAddr *) eltNodeAddress, IX_ETH_DB_ALL_FILTERING_RECORDS);
-
-                /* safety check, maybe user deleted record right before sync? */
-                if (node != NULL)
-                {
-                    /* found record */
-                    MacDescriptor *descriptor = (MacDescriptor *) node->data;
-
-                    IX_ETH_DB_NPE_VERBOSE_TRACE("DB: (NPEAdaptor) synced entry [%s] already in the database, updating fields\n", mac2string(eltNodeAddress));
-
-                    /* reset age - set to -1 so that maintenance will restore it to 0 (or more) when incrementing */
-                    if (!descriptor->recordData.filteringData.staticEntry)
-                    {
-                        if (descriptor->type == IX_ETH_DB_FILTERING_RECORD)
-                        {
-                            descriptor->recordData.filteringData.age = AGE_RESET;
-                        }
-                        else if (descriptor->type == IX_ETH_DB_FILTERING_VLAN_RECORD)
-                        {
-                            descriptor->recordData.filteringVlanData.age = AGE_RESET;
-                        }
-                    }
-
-                    /* end transaction */
-                    ixEthDBReleaseHashNode(node);
-                }
-            }
-            else
-            {
-                IX_ETH_DB_NPE_VERBOSE_TRACE("\t... found portID %d, we check only port %d\n", entryPortID, portID);
-            }
-        }
-    }
-}
-
-/**
- * @brief writes a search tree in NPE format
- *
- * @param type type of records to be written into the NPE update zone
- * @param totalSize maximum size of the linearized tree
- * @param baseAddress memory base address where to write the NPE tree into
- * @param tree search tree to write in NPE format
- * @param blocks number of written 64-byte blocks
- * @param startIndex optimal binary search start index
- *
- * Serializes the given tree in NPE linear format
- *
- * @return none
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-void ixEthDBNPETreeWrite(IxEthDBRecordType type, UINT32 totalSize, void *baseAddress, MacTreeNode *tree, UINT32 *epDelta, UINT32 *blocks)
-{
-    MacTreeNodeStack *stack;
-    UINT32 maxOffset = 0;
-    UINT32 emptyOffset;
-
-    stack = ixOsalCacheDmaMalloc(sizeof (MacTreeNodeStack));
-    
-    if (stack == NULL)
-    {
-        ERROR_LOG("DB: (NPEAdaptor) failed to allocate the node stack for learning tree linearization, out of memory?\n");
-        return;
-    }
-
-    /* zero out empty root */
-    memset(baseAddress, 0, ELT_ENTRY_SIZE);
-
-    NODE_STACK_INIT(stack);
-
-    if (tree != NULL)
-    {
-        /* push tree root at offset 1 */
-        NODE_STACK_PUSH(stack, tree, 1);
-
-        maxOffset = 1;
-    }
-
-    while (NODE_STACK_NONEMPTY(stack))
-    {
-        MacTreeNode *node;
-        UINT32 offset;
-
-        NODE_STACK_POP(stack, node, offset);
-
-        /* update maximum offset */
-        if (offset > maxOffset)
-        {
-            maxOffset = offset;
-        }
-
-        IX_ETH_DB_NPE_VERBOSE_TRACE("DB: (NPEAdaptor) writing MAC [%s] at offset %d\n", mac2string(node->descriptor->macAddress), offset);
-
-        /* add node to NPE ELT at position indicated by offset */
-        if (offset < MAX_ELT_SIZE)
-        {
-            ixEthDBNPENodeWrite[type]((void *) (((UINT32) baseAddress) + offset * ELT_ENTRY_SIZE), node);
-        }
-
-        if (node->left != NULL)
-        {
-            NODE_STACK_PUSH(stack, node->left, LEFT_CHILD_OFFSET(offset));
-        }
-        else
-        {
-            /* ensure this entry is zeroed */
-            memset((void *) ((UINT32) baseAddress + LEFT_CHILD_OFFSET(offset) * ELT_ENTRY_SIZE), 0, ELT_ENTRY_SIZE);
-        }
-
-        if (node->right != NULL)
-        {
-            NODE_STACK_PUSH(stack, node->right, RIGHT_CHILD_OFFSET(offset));
-        }
-        else
-        {
-            /* ensure this entry is zeroed */
-            memset((void *) ((UINT32) baseAddress + RIGHT_CHILD_OFFSET(offset) * ELT_ENTRY_SIZE), 0, ELT_ENTRY_SIZE);
-        }
-    }
-    
-    emptyOffset = maxOffset + 1;
-
-    /* zero out rest of the tree */
-    IX_ETH_DB_NPE_TRACE("DB: (NPEAdaptor) Emptying tree from offset %d, address 0x%08X, %d bytes\n", 
-        emptyOffset, ((UINT32) baseAddress) + emptyOffset * ELT_ENTRY_SIZE, totalSize - (emptyOffset * ELT_ENTRY_SIZE));
-
-    if (emptyOffset < MAX_ELT_SIZE - 1)
-    {
-        memset((void *) (((UINT32) baseAddress) + (emptyOffset * ELT_ENTRY_SIZE)), 0, totalSize - (emptyOffset * ELT_ENTRY_SIZE));
-    }
-
-    /* flush cache */
-    IX_OSAL_CACHE_FLUSH(baseAddress, totalSize);
-
-    /* debug */
-    IX_ETH_DB_NPE_TRACE("DB: (NPEAdaptor) Ethernet learning/filtering tree XScale wrote at address 0x%08X (max %d bytes):\n\n",
-        (UINT32) baseAddress, FULL_ELT_BYTE_SIZE);
-
-    IX_ETH_DB_NPE_DUMP_ELT(baseAddress, FULL_ELT_BYTE_SIZE);
-    
-    /* compute number of 64-byte blocks */
-    if (blocks != NULL)
-    {
-        *blocks = maxOffset != 0 ? 1 + maxOffset / 8 : 0;
-
-        IX_ETH_DB_NPE_TRACE("DB: (NPEAdaptor) Wrote %d 64-byte blocks\n", *blocks);
-    }
-    
-    /* compute epDelta - start index for binary search */
-    if (epDelta != NULL)
-    {
-        UINT32 deltaIndex = 0;
-
-        *epDelta = 0;
-        
-        for (; deltaIndex < IX_ETH_DB_MAX_DELTA_ZONES ; deltaIndex ++)
-        {
-            if (ixEthDBEPDeltaOffset[type][deltaIndex] >= maxOffset)
-            {
-                *epDelta = ixEthDBEPDelta[type][deltaIndex];
-                break;
-            }
-        }
-
-        IX_ETH_DB_NPE_TRACE("DB: (NPEAdaptor) Computed epDelta %d (based on maxOffset %d)\n", *epDelta, maxOffset);
-    }
-
-    ixOsalCacheDmaFree(stack);
-}
-
-/**
- * @brief implements a dummy node serialization function
- *
- * @param address address of where the node is to be serialized (unused)
- * @param node tree node to be serialized (unused)
- *
- * This function is registered for safety reasons and should
- * never be called. It will display an error message if this
- * function is called.
- *
- * @return none
- *
- * @internal
- */
-IX_ETH_DB_PRIVATE
-void ixEthDBNullSerialize(void *address, MacTreeNode *node)
-{
-    IX_ETH_DB_NPE_TRACE("DB: (NPEAdaptor) Warning, the NullSerialize function was called, wrong record type?\n");
-}
-
-/**
- * @brief writes a filtering entry in NPE linear format
- *
- * @param address memory address to write node to
- * @param node node to be written
- *
- * Used by @ref ixEthDBNPETreeWrite to liniarize a search tree
- * in NPE-readable format.
- *
- * @internal
- */
-IX_ETH_DB_PRIVATE
-void ixEthDBNPELearningNodeWrite(void *address, MacTreeNode *node)
-{
-    /* copy mac address */
-    memcpy(address, node->descriptor->macAddress, IX_IEEE803_MAC_ADDRESS_SIZE);
-
-    /* copy port ID */
-    NPE_NODE_BYTE(address, IX_EDB_NPE_NODE_ELT_PORT_ID_OFFSET) = IX_ETH_DB_PORT_ID_TO_NPE_LOGICAL_ID(node->descriptor->portID);
-
-    /* copy flags (valid and not active, as the NPE sets it to active) and clear reserved section (bits 2-7) */
-    NPE_NODE_BYTE(address, IX_EDB_NPE_NODE_ELT_FLAGS_OFFSET) = (UINT8) IX_EDB_FLAGS_INACTIVE_VALID;
-
-    IX_ETH_DB_NPE_VERBOSE_TRACE("DB: (NPEAdaptor) writing ELT node 0x%08x:0x%08x\n", * (UINT32 *) address, * (((UINT32 *) (address)) + 1));
-}
-
-/**
- * @brief writes a WiFi header conversion record in
- * NPE linear format
- *
- * @param address memory address to write node to
- * @param node node to be written
- *
- * Used by @ref ixEthDBNPETreeWrite to liniarize a search tree
- * in NPE-readable format.
- *
- * @internal
- */
-IX_ETH_DB_PRIVATE
-void ixEthDBNPEWiFiNodeWrite(void *address, MacTreeNode *node)
-{
-    /* copy mac address */
-    memcpy(address, node->descriptor->macAddress, IX_IEEE803_MAC_ADDRESS_SIZE);
-
-    /* copy index */
-    NPE_NODE_BYTE(address, IX_EDB_NPE_NODE_WIFI_INDEX_OFFSET) = node->descriptor->recordData.wifiData.gwAddressIndex;
-
-    /* copy flags (type and valid) */
-    NPE_NODE_BYTE(address, IX_EDB_NPE_NODE_WIFI_FLAGS_OFFSET) = node->descriptor->recordData.wifiData.type << 1 | IX_EDB_FLAGS_VALID;
-}
-
-/**
- * @brief writes a WiFi gateway header conversion record in
- * NPE linear format
- *
- * @param address memory address to write node to
- * @param node node to be written
- *
- * Used by @ref ixEthDBNPETreeWrite to liniarize a search tree
- * in NPE-readable format.
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-void ixEthDBNPEGatewayNodeWrite(void *address, MacTreeNode *node)
-{
-    /* copy mac address */
-    memcpy(address, node->descriptor->recordData.wifiData.gwMacAddress, IX_IEEE803_MAC_ADDRESS_SIZE);
-
-    /* set reserved field, two bytes */
-    NPE_NODE_BYTE(address, IX_EDB_NPE_NODE_FW_RESERVED_OFFSET)     = 0;
-    NPE_NODE_BYTE(address, IX_EDB_NPE_NODE_FW_RESERVED_OFFSET + 1) = 0;
-}
-
-/**
- * @brief writes a firewall record in
- * NPE linear format
- *
- * @param address memory address to write node to
- * @param node node to be written
- *
- * Used by @ref ixEthDBNPETreeWrite to liniarize a search tree
- * in NPE-readable format.
- *
- * @internal
- */
-IX_ETH_DB_PRIVATE
-void ixEthDBNPEFirewallNodeWrite(void *address, MacTreeNode *node)
-{
-    /* set reserved field */
-    NPE_NODE_BYTE(address, IX_EDB_NPE_NODE_FW_RESERVED_OFFSET) = 0;
-
-    /* set flags */
-    NPE_NODE_BYTE(address, IX_EDB_NPE_NODE_FW_FLAGS_OFFSET) = IX_EDB_FLAGS_VALID;
-
-    /* copy mac address */
-    memcpy((void *) ((UINT32) address + IX_EDB_NPE_NODE_FW_ADDR_OFFSET), node->descriptor->macAddress, IX_IEEE803_MAC_ADDRESS_SIZE);
-}
-
-/**
- * @brief registers the NPE serialization methods
- *
- * This functions registers NPE serialization methods
- * for writing the following types of records in NPE
- * readable linear format:
- * - filtering records
- * - WiFi header conversion records
- * - WiFi gateway header conversion records
- * - firewall records
- *
- * Note that this function should be called by the
- * component initialization function.
- *
- * @return number of registered record types
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-UINT32 ixEthDBRecordSerializeMethodsRegister()
-{
-    int i;
-    
-    /* safety - register a blank method for everybody first */
-    for ( i = 0 ; i < IX_ETH_DB_MAX_RECORD_TYPE_INDEX + 1 ; i++)
-    {
-        ixEthDBNPENodeWrite[i] = ixEthDBNullSerialize;
-    }
-    
-    /* register real methods */
-    ixEthDBNPENodeWrite[IX_ETH_DB_FILTERING_RECORD]      = ixEthDBNPELearningNodeWrite;
-    ixEthDBNPENodeWrite[IX_ETH_DB_FILTERING_VLAN_RECORD] = ixEthDBNPELearningNodeWrite;
-    ixEthDBNPENodeWrite[IX_ETH_DB_WIFI_RECORD]           = ixEthDBNPEWiFiNodeWrite;
-    ixEthDBNPENodeWrite[IX_ETH_DB_FIREWALL_RECORD]       = ixEthDBNPEFirewallNodeWrite;
-    ixEthDBNPENodeWrite[IX_ETH_DB_GATEWAY_RECORD]        = ixEthDBNPEGatewayNodeWrite;
-    
-    /* EP Delta arrays */
-    memset(ixEthDBEPDeltaOffset, 0, sizeof (ixEthDBEPDeltaOffset));
-    memset(ixEthDBEPDelta, 0, sizeof (ixEthDBEPDelta));
-    
-    /* filtering records */
-    ixEthDBEPDeltaOffset[IX_ETH_DB_FILTERING_RECORD][0] = 1;
-    ixEthDBEPDelta[IX_ETH_DB_FILTERING_RECORD][0]       = 0;
-    
-    ixEthDBEPDeltaOffset[IX_ETH_DB_FILTERING_RECORD][1] = 3;
-    ixEthDBEPDelta[IX_ETH_DB_FILTERING_RECORD][1]       = 7;
-    
-    ixEthDBEPDeltaOffset[IX_ETH_DB_FILTERING_RECORD][2] = 511;
-    ixEthDBEPDelta[IX_ETH_DB_FILTERING_RECORD][2]       = 14;
-    
-    /* wifi records */
-    ixEthDBEPDeltaOffset[IX_ETH_DB_WIFI_RECORD][0] = 1;
-    ixEthDBEPDelta[IX_ETH_DB_WIFI_RECORD][0]       = 0;
-    
-    ixEthDBEPDeltaOffset[IX_ETH_DB_WIFI_RECORD][1] = 3;
-    ixEthDBEPDelta[IX_ETH_DB_WIFI_RECORD][1]       = 7;
-    
-    ixEthDBEPDeltaOffset[IX_ETH_DB_WIFI_RECORD][2] = 511;
-    ixEthDBEPDelta[IX_ETH_DB_WIFI_RECORD][2]       = 14;
-
-    /* firewall records */
-    ixEthDBEPDeltaOffset[IX_ETH_DB_FIREWALL_RECORD][0] = 0;
-    ixEthDBEPDelta[IX_ETH_DB_FIREWALL_RECORD][0]       = 0;
-    
-    ixEthDBEPDeltaOffset[IX_ETH_DB_FIREWALL_RECORD][1] = 1;
-    ixEthDBEPDelta[IX_ETH_DB_FIREWALL_RECORD][1]       = 5;
-    
-    ixEthDBEPDeltaOffset[IX_ETH_DB_FIREWALL_RECORD][2] = 3;
-    ixEthDBEPDelta[IX_ETH_DB_FIREWALL_RECORD][2]       = 13;
-    
-    ixEthDBEPDeltaOffset[IX_ETH_DB_FIREWALL_RECORD][3] = 7;
-    ixEthDBEPDelta[IX_ETH_DB_FIREWALL_RECORD][3]       = 21;
-    
-    ixEthDBEPDeltaOffset[IX_ETH_DB_FIREWALL_RECORD][4] = 15;
-    ixEthDBEPDelta[IX_ETH_DB_FIREWALL_RECORD][4]       = 29;
-    
-    ixEthDBEPDeltaOffset[IX_ETH_DB_FIREWALL_RECORD][5] = 31;
-    ixEthDBEPDelta[IX_ETH_DB_FIREWALL_RECORD][5]       = 37;
-    
-    return 5; /* 5 methods registered */
-}
-
-#ifndef IX_NDEBUG
-
-IX_ETH_DB_PUBLIC UINT32 npeMsgHistory[IX_ETH_DB_NPE_MSG_HISTORY_DEPTH][2];
-IX_ETH_DB_PUBLIC UINT32 npeMsgHistoryLen = 0;
-
-/**
- * When compiled in DEBUG mode, this function can be used to display
- * the history of messages sent to the NPEs (up to 100).
- */
-IX_ETH_DB_PUBLIC
-void ixEthDBShowNpeMsgHistory()
-{
-    UINT32 i = 0;
-    UINT32 base, len;
-
-    if (npeMsgHistoryLen <= IX_ETH_DB_NPE_MSG_HISTORY_DEPTH)
-    {
-        base = 0;
-        len  = npeMsgHistoryLen;
-    }
-    else
-    {
-        base = npeMsgHistoryLen % IX_ETH_DB_NPE_MSG_HISTORY_DEPTH;
-        len  = IX_ETH_DB_NPE_MSG_HISTORY_DEPTH;
-    }
-
-    printf("NPE message history [last %d messages, from least to most recent]:\n", len);
-
-    for (; i < len ; i++)
-    {
-        UINT32 pos = (base + i) % IX_ETH_DB_NPE_MSG_HISTORY_DEPTH;
-        printf("msg[%d]: 0x%08x:0x%08x\n", i, npeMsgHistory[pos][0], npeMsgHistory[pos][1]);
-    }
-}
-
-IX_ETH_DB_PUBLIC
-void ixEthDBELTShow(IxEthDBPortId portID)
-{
-    IxNpeMhMessage message;
-    IX_STATUS result;
-    
-    /* send EDB_GetMACAddressDatabase message */
-    FILL_GETMACADDRESSDATABASE(message, 
-        0 /* reserved */, 
-        IX_OSAL_MMU_VIRT_TO_PHYS(ixEthDBPortInfo[portID].updateMethod.npeUpdateZone));
-
-    IX_ETHDB_SEND_NPE_MSG(IX_ETH_DB_PORT_ID_TO_NPE(portID), message, result);
-
-    if (result == IX_SUCCESS)
-    {
-        /* analyze NPE copy */
-        UINT32 eltEntryOffset;
-        UINT32 entryPortID;
-
-        UINT32 eltBaseAddress = (UINT32) ixEthDBPortInfo[portID].updateMethod.npeUpdateZone;
-        UINT32 eltSize        = FULL_ELT_BYTE_SIZE;
-
-        /* invalidate cache */
-        IX_OSAL_CACHE_INVALIDATE((void *) eltBaseAddress, eltSize);
-
-        printf("Listing records in main learning tree for port %d\n", portID);
-
-        for (eltEntryOffset = ELT_ROOT_OFFSET ; eltEntryOffset < eltSize ; eltEntryOffset += ELT_ENTRY_SIZE)
-        {
-            /* (eltBaseAddress + eltEntryOffset) points to a valid NPE tree node
-            *
-            * the format of the node is MAC[6 bytes]:PortID[1 byte]:Reserved[6 bits]:Active[1 bit]:Valid[1 bit]
-            * therefore we can just use the pointer for database searches as only the first 6 bytes are checked
-            */
-            void *eltNodeAddress = (void *) ((UINT32) eltBaseAddress + eltEntryOffset);
-
-            if (IX_EDB_NPE_NODE_VALID(eltNodeAddress))
-            {
-                HashNode *node;
-
-                entryPortID = IX_ETH_DB_NPE_LOGICAL_ID_TO_PORT_ID(IX_EDB_NPE_NODE_PORT_ID(eltNodeAddress));
-
-                /* search record */
-                node = ixEthDBSearch((IxEthDBMacAddr *) eltNodeAddress, IX_ETH_DB_ALL_RECORD_TYPES);
-
-                printf("%s - port %d - %s ", mac2string((unsigned char *) eltNodeAddress), entryPortID, 
-                    IX_EDB_NPE_NODE_ACTIVE(eltNodeAddress) ? "active" : "inactive");
-
-                /* safety check, maybe user deleted record right before sync? */
-                if (node != NULL)
-                {
-                    /* found record */
-                    MacDescriptor *descriptor = (MacDescriptor *) node->data;
-
-                    printf("- %s ",
-                        descriptor->type == IX_ETH_DB_FILTERING_RECORD ? "filtering" :
-                        descriptor->type == IX_ETH_DB_FILTERING_VLAN_RECORD ? "vlan" :
-                        descriptor->type == IX_ETH_DB_WIFI_RECORD ? "wifi" : "other (check main DB)");
-
-                    if (descriptor->type == IX_ETH_DB_FILTERING_RECORD) printf("- age %d - %s ", 
-                        descriptor->recordData.filteringData.age,
-                        descriptor->recordData.filteringData.staticEntry ? "static" : "dynamic");
-
-                    if (descriptor->type == IX_ETH_DB_FILTERING_VLAN_RECORD) printf("- age %d - %s - tci %d ",
-                        descriptor->recordData.filteringVlanData.age,
-                        descriptor->recordData.filteringVlanData.staticEntry ? "static" : "dynamic",
-                        descriptor->recordData.filteringVlanData.ieee802_1qTag);
-
-                    /* end transaction */
-                    ixEthDBReleaseHashNode(node);
-                }
-                else
-                {
-                    printf("- not synced");
-                }
-
-                printf("\n");
-            }
-        }
-    }
-    else
-    {
-        ixOsalLog(IX_OSAL_LOG_LVL_FATAL, IX_OSAL_LOG_DEV_STDOUT, 
-            "EthDB: (ShowELT) Could not complete action (communication failure)\n",
-            portID, 0, 0, 0, 0, 0);
-    }
-}
-
-#endif
diff --git a/arch/arm/cpu/ixp/npe/IxEthDBPortUpdate.c b/arch/arm/cpu/ixp/npe/IxEthDBPortUpdate.c
deleted file mode 100644
index cdf114b..0000000
--- a/arch/arm/cpu/ixp/npe/IxEthDBPortUpdate.c
+++ /dev/null
@@ -1,740 +0,0 @@
-/**
- * @file IxEthDBDBPortUpdate.c
- *
- * @brief Implementation of dependency and port update handling
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- * 
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- * 
- * @par
- * -- End of Copyright Notice --
- */
-
-#include "IxEthDB_p.h"
-
-/* forward prototype declarations */
-IX_ETH_DB_PRIVATE MacTreeNode* ixEthDBTreeInsert(MacTreeNode *searchTree, MacDescriptor *descriptor);
-IX_ETH_DB_PRIVATE void ixEthDBCreateTrees(IxEthDBPortMap updatePorts);
-IX_ETH_DB_PRIVATE MacTreeNode* ixEthDBTreeRebalance(MacTreeNode *searchTree);
-IX_ETH_DB_PRIVATE void ixEthDBRebalanceTreeToVine(MacTreeNode *root, UINT32 *size);
-IX_ETH_DB_PRIVATE void ixEthDBRebalanceVineToTree(MacTreeNode *root, UINT32 size);
-IX_ETH_DB_PRIVATE void ixEthDBRebalanceCompression(MacTreeNode *root, UINT32 count);
-IX_ETH_DB_PRIVATE UINT32 ixEthDBRebalanceLog2Floor(UINT32 x);
-
-extern HashTable dbHashtable;
-
-/**
- * @brief register types requiring automatic updates
- *
- * @param typeArray array indexed on record types, each
- * element indicating whether the record type requires an
- * automatic update (TRUE) or not (FALSE)
- * 
- * Automatic updates are done for registered record types
- * upon adding, updating (that is, updating the record portID) 
- * and removing records. Whenever an automatic update is triggered
- * the appropriate ports will be provided with new database
- * information.
- *
- * It is assumed that the typeArray parameter is allocated large
- * enough to hold all the user defined types. Also, the type
- * array should be initialized to FALSE as this function only
- * caters for types which do require automatic updates.
- *
- * Note that this function should be called by the component
- * initialization function.
- *
- * @return number of record types registered for automatic
- * updates
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-UINT32 ixEthDBUpdateTypeRegister(BOOL *typeArray)
-{
-    typeArray[IX_ETH_DB_FILTERING_RECORD]      = TRUE;
-    typeArray[IX_ETH_DB_FILTERING_VLAN_RECORD] = TRUE;
-
-    return 2;
-}
-
-/**
- * @brief computes dependencies and triggers port learning tree updates
- *
- * @param triggerPorts port map consisting in the ports which triggered the update
- *
- * This function browses through all the ports and determines how to waterfall the update
- * event from the trigger ports to all other ports depending on them.
- *
- * Once the list of ports to be updated is determined this function 
- * calls @ref ixEthDBCreateTrees.
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-void ixEthDBUpdatePortLearningTrees(IxEthDBPortMap triggerPorts)
-{
-    IxEthDBPortMap updatePorts;
-    UINT32 portIndex;
-    
-    ixEthDBUpdateLock();
-    
-    SET_EMPTY_DEPENDENCY_MAP(updatePorts);
-    
-    for (portIndex = 0 ; portIndex < IX_ETH_DB_NUMBER_OF_PORTS ; portIndex++)
-    {
-        PortInfo *port   = &ixEthDBPortInfo[portIndex];
-        BOOL mapsCollide;
-        
-        MAPS_COLLIDE(mapsCollide, triggerPorts, port->dependencyPortMap);
-
-        if (mapsCollide                                   /* do triggers influence this port? */
-            && !IS_PORT_INCLUDED(portIndex, updatePorts)  /* and it's not already in the update list */
-            && port->updateMethod.updateEnabled)          /* and we're allowed to update it */
-        {
-            IX_ETH_DB_UPDATE_TRACE("DB: (Update) Adding port %d to update set\n", portIndex);
-
-            JOIN_PORT_TO_MAP(updatePorts, portIndex);
-        }
-        else
-        {
-            IX_ETH_DB_UPDATE_TRACE("DB: (Update) Didn't add port %d to update set, reasons follow:\n", portIndex);
-
-            if (!mapsCollide)
-            {
-                IX_ETH_DB_UPDATE_TRACE("\tMaps don't collide on port %d\n", portIndex);
-            }
-
-            if (IS_PORT_INCLUDED(portIndex, updatePorts))
-            {
-                IX_ETH_DB_UPDATE_TRACE("\tPort %d is already in the update set\n", portIndex);
-            }
-
-            if (!port->updateMethod.updateEnabled)
-            {
-                IX_ETH_DB_UPDATE_TRACE("\tPort %d doesn't have updateEnabled set\n", portIndex);
-            }
-        }
-    }
-    
-    IX_ETH_DB_UPDATE_TRACE("DB: (Update) Updating port set\n");
-
-    ixEthDBCreateTrees(updatePorts);
-        
-    ixEthDBUpdateUnlock();
-}
-
-/**
- * @brief creates learning trees and calls the port update handlers
- *
- * @param updatePorts set of ports in need of learning trees
- *
- * This function determines the optimal method of creating learning
- * trees using a minimal number of database queries, keeping in mind
- * that different ports can either use the same learning trees or they
- * can partially share them. The actual tree building routine is
- * @ref ixEthDBQuery.
- *
- * @internal
- */
-IX_ETH_DB_PRIVATE
-void ixEthDBCreateTrees(IxEthDBPortMap updatePorts)
-{
-    UINT32 portIndex;
-    BOOL result;
-    BOOL portsLeft = TRUE;
-
-    while (portsLeft)
-    {
-        /* get port with minimal dependency map and NULL search tree */
-        UINT32 minPortIndex = MAX_PORT_SIZE;
-        UINT32 minimalSize  = MAX_PORT_SIZE;
-
-        for (portIndex = 0 ; portIndex < IX_ETH_DB_NUMBER_OF_PORTS ; portIndex++)
-        {
-            UINT32 size;
-            PortInfo *port = &ixEthDBPortInfo[portIndex];
-
-            /* generate trees only for ports that need them */
-            if (!port->updateMethod.searchTreePendingWrite && IS_PORT_INCLUDED(portIndex, updatePorts))
-            {
-                GET_MAP_SIZE(port->dependencyPortMap, size);
-                
-                IX_ETH_DB_UPDATE_TRACE("DB: (Update) Dependency map for port %d: size %d\n",
-                    portIndex, size);
-
-                if (size < minimalSize)
-                {
-                    minPortIndex = portIndex;
-                    minimalSize  = size;
-                }
-            }
-            else
-            {
-                IX_ETH_DB_UPDATE_TRACE("DB: (Update) Skipped port %d from tree diff (%s)\n", portIndex,
-                    port->updateMethod.searchTreePendingWrite ? "pending write access" : "ignored by query");
-            }            
-        }
-
-        /* if a port was found than minimalSize is not MAX_PORT_SIZE */
-        if (minimalSize != MAX_PORT_SIZE)
-        {
-            /* minPortIndex is the port we seek */
-            PortInfo *port = &ixEthDBPortInfo[minPortIndex];
-
-            IxEthDBPortMap query;
-            MacTreeNode *baseTree;
-
-            /* now try to find a port with minimal map difference */
-            PortInfo *minimalDiffPort = NULL;
-            UINT32 minimalDiff        = MAX_PORT_SIZE;
-            
-            IX_ETH_DB_UPDATE_TRACE("DB: (Update) Minimal size port is %d\n", minPortIndex);
-
-            for (portIndex = 0 ; portIndex < IX_ETH_DB_NUMBER_OF_PORTS ; portIndex++)
-            {   
-                PortInfo *diffPort = &ixEthDBPortInfo[portIndex];
-                BOOL mapIsSubset;
-                
-                IS_MAP_SUBSET(mapIsSubset, diffPort->dependencyPortMap, port->dependencyPortMap);
-                
-
-                if (portIndex != minPortIndex
-                    && diffPort->updateMethod.searchTree != NULL
-                    && mapIsSubset)
-                {
-                    /* compute size and pick only minimal size difference */
-                    UINT32 diffPortSize;
-                    UINT32 sizeDifference;
-
-                    GET_MAP_SIZE(diffPort->dependencyPortMap, diffPortSize);
-                     
-                    IX_ETH_DB_UPDATE_TRACE("DB: (Update) Checking port %d for differences...\n", portIndex);
-
-                    sizeDifference = minimalSize - diffPortSize;
-
-                    if (sizeDifference < minimalDiff)
-                    {
-                        minimalDiffPort = diffPort;
-                        minimalDiff     = sizeDifference;
-                        
-                        IX_ETH_DB_UPDATE_TRACE("DB: (Update) Minimal difference 0x%x was found on port %d\n",
-                            minimalDiff, portIndex);
-                    }
-                }
-            }
-
-            /* check if filtering is enabled on this port */
-            if ((port->featureStatus & IX_ETH_DB_FILTERING) != 0)
-            {
-                /* if minimalDiff is not MAX_PORT_SIZE minimalDiffPort points to the most similar port */
-                if (minimalDiff != MAX_PORT_SIZE)
-                {
-                    baseTree = ixEthDBCloneMacTreeNode(minimalDiffPort->updateMethod.searchTree);
-                    DIFF_MAPS(query, port->dependencyPortMap , minimalDiffPort->dependencyPortMap);
-                    
-                    IX_ETH_DB_UPDATE_TRACE("DB: (Update) Found minimal diff, extending tree %d on query\n",
-                        minimalDiffPort->portID);
-                }
-                else /* .. otherwise no similar port was found, build tree from scratch */
-                {
-                    baseTree = NULL;
-                    
-                    COPY_DEPENDENCY_MAP(query, port->dependencyPortMap);
-                    
-                    IX_ETH_DB_UPDATE_TRACE("DB: (Update) No similar diff, creating tree from query\n");
-                }
-
-                IS_EMPTY_DEPENDENCY_MAP(result, query);
-                
-                if (!result) /* otherwise we don't need anything more on top of the cloned tree */
-                {
-                    IX_ETH_DB_UPDATE_TRACE("DB: (Update) Adding query tree to port %d\n", minPortIndex);
-                        
-                    /* build learning tree */
-                    port->updateMethod.searchTree = ixEthDBQuery(baseTree, query, IX_ETH_DB_ALL_FILTERING_RECORDS, MAX_ELT_SIZE);
-                }
-                else
-                {
-                    IX_ETH_DB_UPDATE_TRACE("DB: (Update) Query is empty, assuming identical nearest tree\n");
-                      
-                    port->updateMethod.searchTree = baseTree;
-                }
-            }
-            else
-            {
-                /* filtering is not enabled, will download an empty tree */
-                if (port->updateMethod.searchTree != NULL)
-                {
-                    ixEthDBFreeMacTreeNode(port->updateMethod.searchTree);
-                }
-
-                port->updateMethod.searchTree = NULL;
-            }
-
-            /* mark tree as valid */
-            port->updateMethod.searchTreePendingWrite = TRUE;
-        }
-        else
-        {
-            portsLeft = FALSE;
-
-            IX_ETH_DB_UPDATE_TRACE("DB: (Update) No trees to create this round\n");            
-        }
-    }
-    
-    for (portIndex = 0 ; portIndex < IX_ETH_DB_NUMBER_OF_PORTS ; portIndex++)
-    {
-        PortInfo *updatePort = &ixEthDBPortInfo[portIndex];
-
-        if (updatePort->updateMethod.searchTreePendingWrite)
-        {
-            IX_ETH_DB_UPDATE_TRACE("DB: (PortUpdate) Starting procedure to upload new search tree (%snull) into NPE %d\n", 
-                updatePort->updateMethod.searchTree != NULL ? "not " : "",
-                portIndex);
-
-            updatePort->updateMethod.updateHandler(portIndex, IX_ETH_DB_FILTERING_RECORD);
-        }
-    }
-}
-
-/**
- * @brief standard NPE update handler
- *
- * @param portID id of the port to be updated
- * @param type record type to be pushed during this update
- *
- * The NPE update handler manages updating the NPE databases
- * given a certain record type.
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBNPEUpdateHandler(IxEthDBPortId portID, IxEthDBRecordType type)
-{
-    UINT32 epDelta, blockCount;
-    IxNpeMhMessage message;
-    UINT32 treeSize = 0;
-    PortInfo *port = &ixEthDBPortInfo[portID];
-
-    /* size selection and type check */
-    if (type == IX_ETH_DB_FILTERING_RECORD || type == IX_ETH_DB_WIFI_RECORD)
-    {
-        treeSize = FULL_ELT_BYTE_SIZE;
-    }
-    else if (type == IX_ETH_DB_FIREWALL_RECORD)
-    {
-        treeSize = FULL_FW_BYTE_SIZE;
-    }
-    else
-    {
-        return IX_ETH_DB_INVALID_ARG;
-    }
-    
-    /* serialize tree into memory */
-    ixEthDBNPETreeWrite(type, treeSize, port->updateMethod.npeUpdateZone, port->updateMethod.searchTree, &epDelta, &blockCount);
-
-    /* free internal copy */
-    if (port->updateMethod.searchTree != NULL)
-    {
-        ixEthDBFreeMacTreeNode(port->updateMethod.searchTree);
-    }
-
-    /* forget last used search tree */
-    port->updateMethod.searchTree             = NULL;
-    port->updateMethod.searchTreePendingWrite = FALSE;
-
-    /* dependending on the update type we do different things */
-    if (type == IX_ETH_DB_FILTERING_RECORD || type == IX_ETH_DB_WIFI_RECORD)
-    {
-        IX_STATUS result;
-
-        FILL_SETMACADDRESSDATABASE_MSG(message, IX_ETH_DB_PORT_ID_TO_NPE_LOGICAL_ID(portID), 
-            epDelta, blockCount, 
-            IX_OSAL_MMU_VIRT_TO_PHYS(port->updateMethod.npeUpdateZone));
-
-        IX_ETHDB_SEND_NPE_MSG(IX_ETH_DB_PORT_ID_TO_NPE(portID), message, result);
-
-        if (result == IX_SUCCESS)
-	{
-            IX_ETH_DB_UPDATE_TRACE("DB: (PortUpdate) Finished downloading NPE tree on port %d\n", portID);
-        }
-        else
-        {
-            ixEthDBPortInfo[portID].agingEnabled                = FALSE;
-            ixEthDBPortInfo[portID].updateMethod.updateEnabled  = FALSE;
-            ixEthDBPortInfo[portID].updateMethod.userControlled = TRUE;
-
-            ERROR_LOG("EthDB: (PortUpdate) disabling aging and updates on port %d (assumed dead)\n", portID);
-
-            ixEthDBDatabaseClear(portID, IX_ETH_DB_ALL_RECORD_TYPES);
-
-            return IX_ETH_DB_FAIL;
-        }
-
-	return IX_ETH_DB_SUCCESS;
-    }
-    else if (type == IX_ETH_DB_FIREWALL_RECORD)
-    {
-        return ixEthDBFirewallUpdate(portID, port->updateMethod.npeUpdateZone, epDelta);
-    }
-    
-    return IX_ETH_DB_INVALID_ARG;
-}
-
-/**
- * @brief queries the database for a set of records to be inserted into a given tree
- *
- * @param searchTree pointer to a tree where insertions will be performed; can be NULL
- * @param query set of ports that a database record must match to be inserted into the tree
- *
- * The query method browses through the database, extracts all the descriptors matching
- * the given query parameter and inserts them into the given learning tree.
- * Note that this is an append procedure, the given tree needs not to be empty.
- * A "descriptor matching the query" is a descriptor whose port id is in the query map.
- * If the given tree is empty (NULL) a new tree is created and returned.
- * 
- * @return the tree root
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-MacTreeNode* ixEthDBQuery(MacTreeNode *searchTree, IxEthDBPortMap query, IxEthDBRecordType recordFilter, UINT32 maxEntries)
-{
-    HashIterator iterator;
-    UINT32 entryCount = 0;
-
-    /* browse database */
-    BUSY_RETRY(ixEthDBInitHashIterator(&dbHashtable, &iterator));
-
-    while (IS_ITERATOR_VALID(&iterator))
-    {
-        MacDescriptor *descriptor = (MacDescriptor *) iterator.node->data;
-
-        IX_ETH_DB_UPDATE_TRACE("DB: (PortUpdate) querying [%s]:%d on port map ... ", 
-            mac2string(descriptor->macAddress), 
-            descriptor->portID);
-
-	if ((descriptor->type & recordFilter) != 0 
-            && IS_PORT_INCLUDED(descriptor->portID, query))
-	{
-            MacDescriptor *descriptorClone = ixEthDBCloneMacDescriptor(descriptor);
-
-            IX_ETH_DB_UPDATE_TRACE("match\n");
-
-            if (descriptorClone != NULL)
-            {
-                /* add descriptor to tree */
-                searchTree = ixEthDBTreeInsert(searchTree, descriptorClone);
-
-                entryCount++;
-            }
-        }
-        else
-        {
-            IX_ETH_DB_UPDATE_TRACE("no match\n");
-        }
-
-        if (entryCount < maxEntries)
-        {
-            /* advance to the next record */
-	        BUSY_RETRY(ixEthDBIncrementHashIterator(&dbHashtable, &iterator));
-        }
-        else
-        {
-            /* the NPE won't accept more entries so we can stop now */
-            ixEthDBReleaseHashIterator(&iterator);
-
-            IX_ETH_DB_UPDATE_TRACE("DB: (PortUpdate) number of elements reached maximum supported by port\n");
-
-            break;
-        }
-    }
-
-    IX_ETH_DB_UPDATE_TRACE("DB: (PortUpdate) query inserted %d records in the search tree\n", entryCount);
-
-    return ixEthDBTreeRebalance(searchTree);
-}
-
-/**
- * @brief inserts a mac descriptor into an tree
- *
- * @param searchTree tree where the insertion is to be performed (may be NULL)
- * @param descriptor descriptor to insert into tree
- *
- * @return the tree root
- *
- * @internal
- */
-IX_ETH_DB_PRIVATE
-MacTreeNode* ixEthDBTreeInsert(MacTreeNode *searchTree, MacDescriptor *descriptor)
-{
-    MacTreeNode *currentNode    = searchTree;
-    MacTreeNode *insertLocation = NULL;
-    MacTreeNode *newNode;
-    INT32 insertPosition = RIGHT;
-
-    if (descriptor == NULL)
-    {
-        return searchTree;
-    }
-
-    /* create a new node */
-    newNode = ixEthDBAllocMacTreeNode();
-
-    if (newNode == NULL)
-    {
-        /* out of memory */
-        ERROR_LOG("Warning: ixEthDBAllocMacTreeNode returned NULL in file %s:%d (out of memory?)\n", __FILE__, __LINE__);
-
-        ixEthDBFreeMacDescriptor(descriptor);
-
-        return NULL;
-    }
-
-    /* populate node */
-    newNode->descriptor = descriptor;
-
-    /* an empty initial tree is a special case */
-    if (searchTree == NULL)
-    {
-        return newNode;
-    }
-
-    /* get insertion location */
-    while (insertLocation == NULL)
-    {
-        MacTreeNode *nextNode;
-
-        /* compare given key with current node key */
-        insertPosition = ixEthDBAddressCompare(descriptor->macAddress, currentNode->descriptor->macAddress);
-
-        /* navigate down */
-        if (insertPosition == RIGHT)
-        {
-            nextNode = currentNode->right;
-        }
-        else if (insertPosition == LEFT)
-        {
-            nextNode = currentNode->left;
-        }
-        else
-        {
-            /* error, duplicate key */
-            ERROR_LOG("Warning: trapped insertion of a duplicate MAC address in an NPE search tree\n");
-
-            /* this will free the MAC descriptor as well */
-            ixEthDBFreeMacTreeNode(newNode);
-
-            return searchTree;
-        }
-
-        /* when we can no longer dive through the tree we found the insertion place */
-        if (nextNode != NULL)
-        {
-            currentNode = nextNode;
-        }
-        else
-        {
-            insertLocation = currentNode;
-        }
-    }
-
-    /* insert node */
-    if (insertPosition == RIGHT)
-    {
-        insertLocation->right = newNode;
-    }
-    else
-    {
-        insertLocation->left = newNode;
-    }
-
-    return searchTree;
-}
-
-/**
- * @brief balance a tree
- *
- * @param searchTree tree to balance
- *
- * Converts a tree into a balanced tree and returns the root of
- * the balanced tree. The resulting tree is <i>route balanced</i>
- * not <i>perfectly balanced</i>. This makes no difference to the
- * average tree search time which is the same in both cases, O(log2(n)).
- *
- * @return root of the balanced tree or NULL if there's no memory left
- *
- * @internal
- */
-IX_ETH_DB_PRIVATE
-MacTreeNode* ixEthDBTreeRebalance(MacTreeNode *searchTree)
-{
-    MacTreeNode *pseudoRoot = ixEthDBAllocMacTreeNode();
-    UINT32 size;
-
-    if (pseudoRoot == NULL)
-    {
-        /* out of memory */
-        return NULL;
-    }
-
-    pseudoRoot->right = searchTree;
-
-    ixEthDBRebalanceTreeToVine(pseudoRoot, &size);
-    ixEthDBRebalanceVineToTree(pseudoRoot, size);
-
-    searchTree = pseudoRoot->right;
-
-    /* remove pseudoRoot right branch, otherwise it will free the entire tree */
-    pseudoRoot->right = NULL;
-
-    ixEthDBFreeMacTreeNode(pseudoRoot);
-
-    return searchTree;
-}
-
-/**
- * @brief converts a tree into a vine
- *
- * @param root root of tree to convert
- * @param size depth of vine (equal to the number of nodes in the tree)
- *
- * @internal
- */
-IX_ETH_DB_PRIVATE
-void ixEthDBRebalanceTreeToVine(MacTreeNode *root, UINT32 *size)
-{
-    MacTreeNode *vineTail  = root;
-    MacTreeNode *remainder = vineTail->right;
-    MacTreeNode *tempPtr;
-
-    *size = 0;
-
-    while (remainder != NULL)
-    {
-        if (remainder->left == NULL)
-        {
-            /* move tail down one */
-            vineTail  = remainder;
-            remainder = remainder->right;
-            (*size)++;
-        }
-        else
-        {
-            /* rotate around remainder */
-            tempPtr         = remainder->left;
-            remainder->left = tempPtr->right;
-            tempPtr->right  = remainder;
-            remainder       = tempPtr;
-            vineTail->right = tempPtr;
-        }
-    }
-}
-
-/**
- * @brief converts a vine into a balanced tree
- *
- * @param root vine to convert
- * @param size depth of vine
- *
- * @internal
- */
-IX_ETH_DB_PRIVATE
-void ixEthDBRebalanceVineToTree(MacTreeNode *root, UINT32 size)
-{
-    UINT32 leafCount = size + 1 - (1 << ixEthDBRebalanceLog2Floor(size + 1));
-
-    ixEthDBRebalanceCompression(root, leafCount);
-
-    size = size - leafCount;
-
-    while (size > 1)
-    {
-        ixEthDBRebalanceCompression(root, size / 2);
-
-        size /= 2;
-    }
-}
-
-/**
- * @brief compresses a vine/tree stage into a more balanced vine/tree
- *
- * @param root root of the tree to compress
- * @param count number of "spine" nodes
- *
- * @internal
- */
-IX_ETH_DB_PRIVATE
-void ixEthDBRebalanceCompression(MacTreeNode *root, UINT32 count)
-{
-    MacTreeNode *scanner = root;
-    MacTreeNode *child;
-    UINT32 local_index;
-
-    for (local_index = 0 ; local_index < count ; local_index++)
-    {
-        child          = scanner->right;
-        scanner->right = child->right;
-        scanner        = scanner->right;
-        child->right   = scanner->left;
-        scanner->left  = child;
-    }
-}
-
-/**
- * @brief computes |_log2(x)_| (a.k.a. floor(log2(x)))
- *
- * @param x number to compute |_log2(x)_| for
- *
- * @return |_log2(x)_|
- *
- * @internal
- */
-IX_ETH_DB_PRIVATE
-UINT32 ixEthDBRebalanceLog2Floor(UINT32 x)
-{
-    UINT32 log = 0;
-    UINT32 val = 1;
-
-    while (val < x)
-    {
-        log++;
-        val <<= 1;
-    }
-
-    return val == x ? log : log - 1;
-}
-
diff --git a/arch/arm/cpu/ixp/npe/IxEthDBReports.c b/arch/arm/cpu/ixp/npe/IxEthDBReports.c
deleted file mode 100644
index 9c7ae1c..0000000
--- a/arch/arm/cpu/ixp/npe/IxEthDBReports.c
+++ /dev/null
@@ -1,652 +0,0 @@
-/**
- * @file IxEthDBAPI.c
- *
- * @brief Implementation of the public API
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- * 
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- * 
- * @par
- * -- End of Copyright Notice --
- */
-
-#include "IxEthDB_p.h"
-
-extern HashTable dbHashtable;
-IX_ETH_DB_PRIVATE void ixEthDBPortInfoShow(IxEthDBPortId portID, IxEthDBRecordType recordFilter);
-IX_ETH_DB_PRIVATE IxEthDBStatus ixEthDBHeaderShow(IxEthDBRecordType recordFilter);
-IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBDependencyPortMapShow(IxEthDBPortId portID, IxEthDBPortMap map);
-
-/**
- * @brief displays a port dependency map
- *
- * @param portID ID of the port
- * @param map port map to display
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed
- * successfully
- */ 
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBDependencyPortMapShow(IxEthDBPortId portID, IxEthDBPortMap map)
-{
-    UINT32 portIndex;
-    BOOL mapSelf = TRUE, mapNone = TRUE, firstPort = TRUE;
-    
-    /* dependency port maps */
-    printf("Dependency port map: ");
-    
-    /* browse the port map */
-    for (portIndex = 0 ; portIndex < IX_ETH_DB_NUMBER_OF_PORTS ; portIndex++)
-    {
-        if (IS_PORT_INCLUDED(portIndex, map))
-        {
-            mapNone   = FALSE;
-            
-            if (portIndex != portID)
-            {
-                mapSelf = FALSE;
-            }
-            
-            printf("%s%d", firstPort ? "{" : ", ", portIndex);
-            
-            firstPort = FALSE;
-        }
-    }
-    
-    if (mapNone)
-    {
-        mapSelf = FALSE;
-    }
-    
-    printf("%s (%s)\n", firstPort ? "" : "}", mapSelf ? "self" : mapNone ? "none" : "group");
-    
-    return IX_ETH_DB_SUCCESS;
-}
-
-/**
- * @brief displays all the filtering records belonging to a port
- *
- * @param portID ID of the port to display
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @warning deprecated, use @ref ixEthDBFilteringDatabaseShowRecords() 
- * instead. Calling this function is equivalent to calling
- * ixEthDBFilteringDatabaseShowRecords(portID, IX_ETH_DB_FILTERING_RECORD)
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBFilteringDatabaseShow(IxEthDBPortId portID)
-{
-    IxEthDBStatus local_result;
-    HashIterator iterator;
-    PortInfo *portInfo;
-    UINT32 recordCount = 0;
-
-    IX_ETH_DB_CHECK_PORT(portID);
-
-    IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
-    portInfo = &ixEthDBPortInfo[portID];
-
-    /* display table header */
-    printf("Ethernet database records for port ID [%d]\n", portID);
-    
-    ixEthDBDependencyPortMapShow(portID, portInfo->dependencyPortMap);
-    
-    if (ixEthDBPortDefinitions[portID].type == IX_ETH_NPE)
-    {
-        printf("NPE updates are %s\n\n", portInfo->updateMethod.updateEnabled ? "enabled" : "disabled");
-    }
-    else
-    {
-        printf("updates disabled (not an NPE)\n\n");
-    }
-
-    printf("    MAC address    |   Age  | Type \n");
-    printf("___________________________________\n");
-
-    /* browse database */
-    BUSY_RETRY(ixEthDBInitHashIterator(&dbHashtable, &iterator));
-
-    while (IS_ITERATOR_VALID(&iterator))
-    {
-      MacDescriptor *descriptor = (MacDescriptor *) iterator.node->data;
-
-      if (descriptor->portID == portID && descriptor->type == IX_ETH_DB_FILTERING_RECORD)
-      {
-          recordCount++;
-
-          /* display entry */
-          printf(" %02X:%02X:%02X:%02X:%02X:%02X | %5d  | %s\n",
-              descriptor->macAddress[0],
-              descriptor->macAddress[1],
-              descriptor->macAddress[2],
-              descriptor->macAddress[3],
-              descriptor->macAddress[4],
-              descriptor->macAddress[5],
-              descriptor->recordData.filteringData.age,
-              descriptor->recordData.filteringData.staticEntry ? "static" : "dynamic");
-      }
-
-      /* move to the next record */
-      BUSY_RETRY_WITH_RESULT(ixEthDBIncrementHashIterator(&dbHashtable, &iterator), local_result);
-
-      /* debug */
-      if (local_result == IX_ETH_DB_BUSY)
-      {
-          return IX_ETH_DB_FAIL;
-      }
-    }
-
-    /* display number of records */
-    printf("\nFound %d records\n", recordCount);
-
-    return IX_ETH_DB_SUCCESS;
-}
-
-/**
- * @brief displays all the filtering records belonging to all the ports
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @warning deprecated, use @ref ixEthDBFilteringDatabaseShowRecords() 
- * instead. Calling this function is equivalent to calling
- * ixEthDBFilteringDatabaseShowRecords(IX_ETH_DB_ALL_PORTS, IX_ETH_DB_FILTERING_RECORD)
- */
-IX_ETH_DB_PUBLIC
-void ixEthDBFilteringDatabaseShowAll()
-{
-    IxEthDBPortId portIndex;
-
-    printf("\nEthernet learning/filtering database: listing %d ports\n\n", (UINT32) IX_ETH_DB_NUMBER_OF_PORTS);
-
-    for (portIndex = 0 ; portIndex < IX_ETH_DB_NUMBER_OF_PORTS ; portIndex++)
-    {
-        ixEthDBFilteringDatabaseShow(portIndex);
-
-        if (portIndex < IX_ETH_DB_NUMBER_OF_PORTS - 1)
-        {
-            printf("\n");
-        }
-    }
-}
-
-/**
- * @brief displays one record in a format depending on the record filter
- *
- * @param descriptor pointer to the record
- * @param recordFilter format filter
- *
- * This function will display the fields in a record depending on the
- * selected record filter.
- *
- * @internal
- */
-IX_ETH_DB_PRIVATE
-void ixEthDBRecordShow(MacDescriptor *descriptor, IxEthDBRecordType recordFilter)
-{
-    if (recordFilter == IX_ETH_DB_FILTERING_VLAN_RECORD
-        || recordFilter == (IX_ETH_DB_FILTERING_RECORD | IX_ETH_DB_FILTERING_VLAN_RECORD))
-    {
-        /* display VLAN record header - leave this commented code in place, its purpose is to align the print format with the header
-        printf("    MAC address    |   Age  |   Type   | VLAN ID | CFI | QoS class \n");
-        printf("___________________________________________________________________\n"); */
-
-        if (descriptor->type == IX_ETH_DB_FILTERING_VLAN_RECORD)
-        {
-            printf("%02X:%02X:%02X:%02X:%02X:%02X | %3d | %s | %d | %d | %d\n",
-                descriptor->macAddress[0],
-                descriptor->macAddress[1],
-                descriptor->macAddress[2],
-                descriptor->macAddress[3],
-                descriptor->macAddress[4],
-                descriptor->macAddress[5],
-                descriptor->recordData.filteringVlanData.age,
-                descriptor->recordData.filteringVlanData.staticEntry ? "static" : "dynamic",
-                IX_ETH_DB_GET_VLAN_ID(descriptor->recordData.filteringVlanData.ieee802_1qTag),
-                (descriptor->recordData.filteringVlanData.ieee802_1qTag & 0x1000) >> 12,
-                IX_ETH_DB_GET_QOS_PRIORITY(descriptor->recordData.filteringVlanData.ieee802_1qTag));
-         }
-         else if (descriptor->type == IX_ETH_DB_FILTERING_RECORD)
-         {
-            printf("%02X:%02X:%02X:%02X:%02X:%02X | %3d | %s | - | - | -\n",
-                descriptor->macAddress[0],
-                descriptor->macAddress[1],
-                descriptor->macAddress[2],
-                descriptor->macAddress[3],
-                descriptor->macAddress[4],
-                descriptor->macAddress[5],
-                descriptor->recordData.filteringData.age,
-                descriptor->recordData.filteringData.staticEntry ? "static" : "dynamic");
-         }
-    }
-    else if (recordFilter == IX_ETH_DB_FILTERING_RECORD)
-    {
-        /* display filtering record header - leave this commented code in place, its purpose is to align the print format with the header
-        printf("    MAC address    |   Age  |   Type   \n");
-        printf("_______________________________________\n");  */
-
-        if (descriptor->type == IX_ETH_DB_FILTERING_RECORD)
-        {
-         printf("%02X:%02X:%02X:%02X:%02X:%02X | %3d | %s \n",
-             descriptor->macAddress[0],
-             descriptor->macAddress[1],
-             descriptor->macAddress[2],
-             descriptor->macAddress[3],
-             descriptor->macAddress[4],
-             descriptor->macAddress[5],
-             descriptor->recordData.filteringData.age,
-             descriptor->recordData.filteringData.staticEntry ? "static" : "dynamic");
-        }
-    }
-    else if (recordFilter == IX_ETH_DB_WIFI_RECORD)
-    {
-        /* display WiFi record header - leave this commented code in place, its purpose is to align the print format with the header 
-        printf("    MAC address    |   GW MAC address  \n");
-        printf("_______________________________________\n"); */
-
-        if (descriptor->type == IX_ETH_DB_WIFI_RECORD)
-        {
-            if (descriptor->recordData.wifiData.type == IX_ETH_DB_WIFI_AP_TO_AP)
-            {
-                /* gateway address present */
-                printf("%02X:%02X:%02X:%02X:%02X:%02X | %02X:%02X:%02X:%02X:%02X:%02X \n",
-                    descriptor->macAddress[0],
-                    descriptor->macAddress[1],
-                    descriptor->macAddress[2],
-                    descriptor->macAddress[3],
-                    descriptor->macAddress[4],
-                    descriptor->macAddress[5],
-                    descriptor->recordData.wifiData.gwMacAddress[0],
-                    descriptor->recordData.wifiData.gwMacAddress[1],
-                    descriptor->recordData.wifiData.gwMacAddress[2],
-                    descriptor->recordData.wifiData.gwMacAddress[3],
-                    descriptor->recordData.wifiData.gwMacAddress[4],
-                    descriptor->recordData.wifiData.gwMacAddress[5]);
-            }
-            else
-            {
-                /* no gateway */
-                printf("%02X:%02X:%02X:%02X:%02X:%02X | ----no gateway----- \n",
-                    descriptor->macAddress[0],
-                    descriptor->macAddress[1],
-                    descriptor->macAddress[2],
-                    descriptor->macAddress[3],
-                    descriptor->macAddress[4],
-                    descriptor->macAddress[5]);
-            }
-        }
-    }
-    else if (recordFilter == IX_ETH_DB_FIREWALL_RECORD)
-    {
-        /* display Firewall record header - leave this commented code in place, its purpose is to align the print format with the header 
-        printf("    MAC address   \n");
-        printf("__________________\n"); */
-
-        if (descriptor->type == IX_ETH_DB_FIREWALL_RECORD)
-        {
-            printf("%02X:%02X:%02X:%02X:%02X:%02X \n",
-                descriptor->macAddress[0],
-                descriptor->macAddress[1],
-                descriptor->macAddress[2],
-                descriptor->macAddress[3],
-                descriptor->macAddress[4],
-                descriptor->macAddress[5]);
-        }
-    }
-    else if (recordFilter == IX_ETH_DB_ALL_RECORD_TYPES)
-    {
-        /* display composite record header - leave this commented code in place, its purpose is to align the print format with the header 
-        printf("    MAC address   | Record | Age|  Type   | VLAN |CFI| QoS |  GW MAC address   \n");
-        printf("_______________________________________________________________________________\n"); */
-
-        if (descriptor->type == IX_ETH_DB_FILTERING_VLAN_RECORD)
-        {
-            printf("%02X:%02X:%02X:%02X:%02X:%02X |  VLAN  | %2d | %s | %4d | %1d |  %1d  | -----------------\n",
-                descriptor->macAddress[0],
-                descriptor->macAddress[1],
-                descriptor->macAddress[2],
-                descriptor->macAddress[3],
-                descriptor->macAddress[4],
-                descriptor->macAddress[5],
-                descriptor->recordData.filteringVlanData.age,
-                descriptor->recordData.filteringVlanData.staticEntry ? "static " : "dynamic",
-                IX_ETH_DB_GET_VLAN_ID(descriptor->recordData.filteringVlanData.ieee802_1qTag),
-                (descriptor->recordData.filteringVlanData.ieee802_1qTag & 0x1000) >> 12,
-                IX_ETH_DB_GET_QOS_PRIORITY(descriptor->recordData.filteringVlanData.ieee802_1qTag));
-         }
-         else if (descriptor->type == IX_ETH_DB_FILTERING_RECORD)
-         {
-            printf("%02X:%02X:%02X:%02X:%02X:%02X | Filter | %2d | %s | ---- | - | --- | -----------------\n",
-                descriptor->macAddress[0],
-                descriptor->macAddress[1],
-                descriptor->macAddress[2],
-                descriptor->macAddress[3],
-                descriptor->macAddress[4],
-                descriptor->macAddress[5],
-                descriptor->recordData.filteringData.age,
-                descriptor->recordData.filteringData.staticEntry ? "static " : "dynamic");
-         }
-        else if (descriptor->type == IX_ETH_DB_WIFI_RECORD)
-        {
-            if (descriptor->recordData.wifiData.type == IX_ETH_DB_WIFI_AP_TO_AP)
-            {
-                /* gateway address present */
-                printf("%02X:%02X:%02X:%02X:%02X:%02X |  WiFi  | -- | AP=>AP  | ---- | - | --- | %02X:%02X:%02X:%02X:%02X:%02X\n",
-                    descriptor->macAddress[0],
-                    descriptor->macAddress[1],
-                    descriptor->macAddress[2],
-                    descriptor->macAddress[3],
-                    descriptor->macAddress[4],
-                    descriptor->macAddress[5],
-                    descriptor->recordData.wifiData.gwMacAddress[0],
-                    descriptor->recordData.wifiData.gwMacAddress[1],
-                    descriptor->recordData.wifiData.gwMacAddress[2],
-                    descriptor->recordData.wifiData.gwMacAddress[3],
-                    descriptor->recordData.wifiData.gwMacAddress[4],
-                    descriptor->recordData.wifiData.gwMacAddress[5]);
-            }
-            else
-            {
-                /* no gateway */
-                printf("%02X:%02X:%02X:%02X:%02X:%02X |  WiFi  | -- | AP=>ST  | ---- | - | --- | -- no gateway -- \n",
-                    descriptor->macAddress[0],
-                    descriptor->macAddress[1],
-                    descriptor->macAddress[2],
-                    descriptor->macAddress[3],
-                    descriptor->macAddress[4],
-                    descriptor->macAddress[5]);
-            }
-        }
-        else if (descriptor->type == IX_ETH_DB_FIREWALL_RECORD)
-        {
-            printf("%02X:%02X:%02X:%02X:%02X:%02X |   FW   | -- | ------- | ---- | - | --- | -----------------\n",
-                descriptor->macAddress[0],
-                descriptor->macAddress[1],
-                descriptor->macAddress[2],
-                descriptor->macAddress[3],
-                descriptor->macAddress[4],
-                descriptor->macAddress[5]);
-        }
-    }
-    else
-    {
-        printf("invalid record filter\n");
-    }
-}
-
-/**
- * @brief displays the status, records and configuration information of a port
- *
- * @param portID ID of the port
- * @param recordFilter record filter to display
- *
- * @internal
- */
-IX_ETH_DB_PRIVATE
-void ixEthDBPortInfoShow(IxEthDBPortId portID, IxEthDBRecordType recordFilter)
-{
-    PortInfo *portInfo = &ixEthDBPortInfo[portID];
-    UINT32 recordCount = 0;
-    HashIterator iterator;
-    IxEthDBStatus local_result;
-
-    /* display port status */
-    printf("== Port ID %d ==\n", portID);
-
-    /* display capabilities */
-    printf("- Capabilities: ");
-
-    if ((portInfo->featureCapability & IX_ETH_DB_LEARNING) != 0)
-    {
-        printf("Learning (%s) ", ((portInfo->featureStatus & IX_ETH_DB_LEARNING) != 0) ? "on" : "off");
-    }
-
-    if ((portInfo->featureCapability & IX_ETH_DB_VLAN_QOS) != 0)
-    {
-        printf("VLAN/QoS (%s) ", ((portInfo->featureStatus & IX_ETH_DB_VLAN_QOS) != 0) ? "on" : "off");
-    }
-
-    if ((portInfo->featureCapability & IX_ETH_DB_FIREWALL) != 0)
-    {
-        printf("Firewall (%s) ", ((portInfo->featureStatus & IX_ETH_DB_FIREWALL) != 0) ? "on" : "off");
-    }
-
-    if ((portInfo->featureCapability & IX_ETH_DB_WIFI_HEADER_CONVERSION) != 0)
-    {
-        printf("WiFi (%s) ", ((portInfo->featureStatus & IX_ETH_DB_WIFI_HEADER_CONVERSION) != 0) ? "on" : "off");
-    }
-
-    if ((portInfo->featureCapability & IX_ETH_DB_SPANNING_TREE_PROTOCOL) != 0)
-    {
-        printf("STP (%s) ", ((portInfo->featureStatus & IX_ETH_DB_SPANNING_TREE_PROTOCOL) != 0) ? "on" : "off");
-    }
-
-    printf("\n");
-
-    /* dependency map */
-    ixEthDBDependencyPortMapShow(portID, portInfo->dependencyPortMap);
-
-    /* NPE dynamic updates */
-    if (ixEthDBPortDefinitions[portID].type == IX_ETH_NPE) 
-    {
-        printf(" - NPE dynamic update is %s\n", portInfo->updateMethod.updateEnabled ? "enabled" : "disabled");
-    }
-    else
-    {
-        printf(" - dynamic update disabled (not an NPE)\n");
-    }
-
-    if ((portInfo->featureCapability & IX_ETH_DB_WIFI_HEADER_CONVERSION) != 0)
-    {
-        if ((portInfo->featureStatus & IX_ETH_DB_WIFI_HEADER_CONVERSION) != 0)
-        {
-            /* WiFi header conversion */
-            if ((portInfo->frameControlDurationID 
-                + portInfo->bbsid[0] 
-                + portInfo->bbsid[1] 
-                + portInfo->bbsid[2] 
-                + portInfo->bbsid[3] 
-                + portInfo->bbsid[4] 
-                + portInfo->bbsid[5]) == 0)
-            {
-                printf(" - WiFi header conversion not configured\n");
-            }
-            else
-            {  
-                printf(" - WiFi header conversion: BBSID [%02X:%02X:%02X:%02X:%02X:%02X], Frame Control 0x%X, Duration/ID 0x%X\n", 
-                    portInfo->bbsid[0],
-                    portInfo->bbsid[1],
-                    portInfo->bbsid[2],
-                    portInfo->bbsid[3],
-                    portInfo->bbsid[4],
-                    portInfo->bbsid[5],
-                    portInfo->frameControlDurationID >> 16,
-                    portInfo->frameControlDurationID & 0xFFFF);
-            }
-        }
-        else
-        {
-            printf(" - WiFi header conversion not enabled\n");
-        }
-    }
-
-    /* Firewall */
-    if ((portInfo->featureCapability & IX_ETH_DB_FIREWALL) != 0)
-    {
-        if ((portInfo->featureStatus & IX_ETH_DB_FIREWALL) != 0)
-        {
-            printf(" - Firewall is in %s-list mode\n", portInfo->firewallMode == IX_ETH_DB_FIREWALL_BLACK_LIST ? "black" : "white");
-            printf(" - Invalid source MAC address filtering is %s\n", portInfo->srcAddressFilterEnabled ? "enabled" : "disabled");
-        }
-        else
-        {
-            printf(" - Firewall not enabled\n");
-        }
-    }
-  
-    /* browse database if asked to display records */
-    if (recordFilter != IX_ETH_DB_NO_RECORD_TYPE)
-    {
-        printf("\n");
-        ixEthDBHeaderShow(recordFilter);
-
-        BUSY_RETRY(ixEthDBInitHashIterator(&dbHashtable, &iterator));
-
-        while (IS_ITERATOR_VALID(&iterator))
-        {
-            MacDescriptor *descriptor = (MacDescriptor *) iterator.node->data;
-
-            if (descriptor->portID == portID && (descriptor->type & recordFilter) != 0)
-            {
-                recordCount++;
-
-                /* display entry */
-                ixEthDBRecordShow(descriptor, recordFilter);
-            }
-
-            /* move to the next record */
-            BUSY_RETRY_WITH_RESULT(ixEthDBIncrementHashIterator(&dbHashtable, &iterator), local_result);
-
-            /* debug */
-            if (local_result == IX_ETH_DB_BUSY)
-            {
-                printf("EthDB (API): Error, database browser failed (no access), giving up\n");
-            }
-        }
-        
-        printf("\nFound %d records\n\n", recordCount);
-    }
-}
-
-/**
- * @brief displays a record header
- *
- * @param recordFilter record type filter
- *
- * This function displays a record header, depending on
- * the given record type filter. It is useful when used
- * in conjunction with ixEthDBRecordShow which will display
- * record fields formatted for the header, provided the same
- * record filter is used.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed
- * successfully or IX_ETH_DB_INVALID_ARG if the recordFilter
- * parameter is invalid or not supported
- *
- * @internal
- */
-IX_ETH_DB_PRIVATE
-IxEthDBStatus ixEthDBHeaderShow(IxEthDBRecordType recordFilter)
-{
-  if (recordFilter == IX_ETH_DB_FILTERING_VLAN_RECORD
-      || recordFilter == (IX_ETH_DB_FILTERING_RECORD | IX_ETH_DB_FILTERING_VLAN_RECORD))
-  {
-    /* display VLAN record header */
-    printf("    MAC address    |   Age  |   Type   | VLAN ID | CFI | QoS class \n");
-    printf("___________________________________________________________________\n");
-  }
-  else if (recordFilter == IX_ETH_DB_FILTERING_RECORD)
-  {
-    /* display filtering record header */
-    printf("    MAC address    |   Age  |   Type   \n");
-    printf("_______________________________________\n");
-  }
-  else if (recordFilter == IX_ETH_DB_WIFI_RECORD)
-  {
-    /* display WiFi record header */
-    printf("    MAC address    |   GW MAC address  \n");
-    printf("_______________________________________\n");
-  }
-  else if (recordFilter == IX_ETH_DB_FIREWALL_RECORD)
-  {
-    /* display Firewall record header */
-    printf("    MAC address   \n");
-    printf("__________________\n");
-  }
-  else if (recordFilter == IX_ETH_DB_ALL_RECORD_TYPES)
-  {
-    /* display composite record header */
-    printf("    MAC address   | Record | Age|  Type   | VLAN |CFI| QoS |  GW MAC address   \n");
-    printf("_______________________________________________________________________________\n");
-  }
-  else
-  {
-    return IX_ETH_DB_INVALID_ARG;
-  }
-  
-  return IX_ETH_DB_SUCCESS;
-}
-
-/**
- * @brief displays database information (records and port information)
- *
- * @param portID ID of the port to display (or IX_ETH_DB_ALL_PORTS for all the ports)
- * @param recordFilter record filter (use IX_ETH_DB_NO_RECORD_TYPE to display only
- * port information)
- * 
- * Note that this function is documented in the main component header
- * file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully or
- * an appropriate error code otherwise
- * 
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBFilteringDatabaseShowRecords(IxEthDBPortId portID, IxEthDBRecordType recordFilter)
-{
-  IxEthDBPortId currentPort;
-  BOOL showAllPorts = (portID == IX_ETH_DB_ALL_PORTS);
-  
-  IX_ETH_DB_CHECK_PORT_ALL(portID);
-
-  printf("\nEthernet learning/filtering database: listing %d port(s)\n\n", showAllPorts ? (UINT32) IX_ETH_DB_NUMBER_OF_PORTS : 1);
-  
-  currentPort = showAllPorts ? 0 : portID;
-  
-  while (currentPort != IX_ETH_DB_NUMBER_OF_PORTS)
-  {
-    /* display port info */
-    ixEthDBPortInfoShow(currentPort, recordFilter);
-    
-    /* next port */
-    currentPort = showAllPorts ? currentPort + 1 : IX_ETH_DB_NUMBER_OF_PORTS;
-  }
-  
-  return IX_ETH_DB_SUCCESS;
-}
-
diff --git a/arch/arm/cpu/ixp/npe/IxEthDBSearch.c b/arch/arm/cpu/ixp/npe/IxEthDBSearch.c
deleted file mode 100644
index 4a10878..0000000
--- a/arch/arm/cpu/ixp/npe/IxEthDBSearch.c
+++ /dev/null
@@ -1,327 +0,0 @@
-/**
- * @file IxEthDBSearch.c
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- * 
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- * 
- * @par
- * -- End of Copyright Notice --
- */
-
-#include "IxEthDB_p.h"
-
-extern HashTable dbHashtable;
-
-/**
- * @brief matches two database records based on their MAC addresses
- *
- * @param untypedReference record to match against
- * @param untypedEntry record to match
- *
- * @return TRUE if the match is successful or FALSE otherwise
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-BOOL ixEthDBAddressRecordMatch(void *untypedReference, void *untypedEntry)
-{
-    MacDescriptor *entry     = (MacDescriptor *) untypedEntry;
-    MacDescriptor *reference = (MacDescriptor *) untypedReference;
-    
-    /* check accepted record types */
-    if ((entry->type & reference->type) == 0) return FALSE;
-       
-    return (ixEthDBAddressCompare((UINT8 *) entry->macAddress, (UINT8 *) reference->macAddress) == 0);
-}
-
-/**
- * @brief matches two database records based on their MAC addresses
- * and VLAN IDs
- *
- * @param untypedReference record to match against
- * @param untypedEntry record to match
- *
- * @return TRUE if the match is successful or FALSE otherwise
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-BOOL ixEthDBVlanRecordMatch(void *untypedReference, void *untypedEntry)
-{
-    MacDescriptor *entry     = (MacDescriptor *) untypedEntry;
-    MacDescriptor *reference = (MacDescriptor *) untypedReference;
-    
-    /* check accepted record types */
-    if ((entry->type & reference->type) == 0) return FALSE;
-    
-    return (IX_ETH_DB_GET_VLAN_ID(entry->recordData.filteringVlanData.ieee802_1qTag) ==
-        IX_ETH_DB_GET_VLAN_ID(reference->recordData.filteringVlanData.ieee802_1qTag)) &&
-        (ixEthDBAddressCompare(entry->macAddress, reference->macAddress) == 0);
-}
-
-/**
- * @brief matches two database records based on their MAC addresses
- * and port IDs
- *
- * @param untypedReference record to match against
- * @param untypedEntry record to match
- *
- * @return TRUE if the match is successful or FALSE otherwise
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-BOOL ixEthDBPortRecordMatch(void *untypedReference, void *untypedEntry)
-{
-    MacDescriptor *entry     = (MacDescriptor *) untypedEntry;
-    MacDescriptor *reference = (MacDescriptor *) untypedReference;
-    
-    /* check accepted record types */
-    if ((entry->type & reference->type) == 0) return FALSE;
-    
-    return (entry->portID == reference->portID) &&
-        (ixEthDBAddressCompare(entry->macAddress, reference->macAddress) == 0);
-}
-
-/**
- * @brief dummy matching function, registered for safety
- *
- * @param reference record to match against (unused)
- * @param entry record to match (unused)
- *
- * This function is registered in the matching functions
- * array on invalid types. Calling it will display an 
- * error message, indicating an error in the component logic.
- *
- * @return FALSE
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-BOOL ixEthDBNullMatch(void *reference, void *entry)
-{
-    /* display an error message */
-
-    ixOsalLog(IX_OSAL_LOG_LVL_WARNING, IX_OSAL_LOG_DEV_STDOUT, "DB: (Search) The NullMatch function was called, wrong key type?\n", 0, 0, 0, 0, 0, 0);
-
-
-    return FALSE;
-}
-
-/**
- * @brief registers hash matching methods
- *
- * @param matchFunctions table of match functions to be populated
- *
- * This function registers the available record matching functions
- * by indexing them on record types into the given function array.
- * 
- * Note that it is compulsory to call this in ixEthDBInit(), 
- * otherwise hashtable searching and removal will not work
- *
- * @return number of registered functions
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-UINT32 ixEthDBMatchMethodsRegister(MatchFunction *matchFunctions)
-{
-    UINT32 i;
-    
-    /* safety first */
-    for ( i = 0 ; i < IX_ETH_DB_MAX_KEY_INDEX + 1 ; i++)
-    {
-        matchFunctions[i] = ixEthDBNullMatch;
-    }
-    
-    /* register MAC search method */
-    matchFunctions[IX_ETH_DB_MAC_KEY] = ixEthDBAddressRecordMatch;
-    
-    /* register MAC/PortID search method */
-    matchFunctions[IX_ETH_DB_MAC_PORT_KEY] = ixEthDBPortRecordMatch;
-    
-    /* register MAC/VLAN ID search method */
-    matchFunctions[IX_ETH_DB_MAC_VLAN_KEY] = ixEthDBVlanRecordMatch;
-    
-    return 3; /* three methods */
-}
-
-/**
- * @brief search a record in the Ethernet datbase
- *
- * @param macAddress MAC address to perform the search on
- * @param typeFilter type of records to consider for matching
- *
- * @warning if searching is successful an implicit write lock
- * to the search result is granted, therefore unlock the 
- * entry using @ref ixEthDBReleaseHashNode() as soon as possible.
- *
- * @see ixEthDBReleaseHashNode()
- *
- * @return the search result, or NULL if a record with the given
- * MAC address was not found
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-HashNode* ixEthDBSearch(IxEthDBMacAddr *macAddress, IxEthDBRecordType typeFilter)
-{
-    HashNode *searchResult = NULL;
-    MacDescriptor reference;
-    
-    TEST_FIXTURE_INCREMENT_DB_CORE_ACCESS_COUNTER;
-
-    if (macAddress == NULL)
-    {
-        return NULL;
-    }
-
-    /* fill search fields */
-    memcpy(reference.macAddress, macAddress, sizeof (IxEthDBMacAddr));
-    
-    /* set acceptable record types */
-    reference.type = typeFilter;
-    
-    BUSY_RETRY(ixEthDBSearchHashEntry(&dbHashtable, IX_ETH_DB_MAC_KEY, &reference, &searchResult));
-
-    return searchResult;
-}
-
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBPeek(IxEthDBMacAddr *macAddress, IxEthDBRecordType typeFilter)
-{
-    MacDescriptor reference;
-    IxEthDBStatus result;
-    
-    TEST_FIXTURE_INCREMENT_DB_CORE_ACCESS_COUNTER;
-
-    if (macAddress == NULL)
-    {
-        return IX_ETH_DB_INVALID_ARG;
-    }
-
-    /* fill search fields */
-    memcpy(reference.macAddress, macAddress, sizeof (IxEthDBMacAddr));
-    
-    /* set acceptable record types */
-    reference.type = typeFilter;
-    
-    result = ixEthDBPeekHashEntry(&dbHashtable, IX_ETH_DB_MAC_KEY, &reference);
-
-    return result;
-}
-
-/**
- * @brief search a record in the Ethernet datbase
- *
- * @param macAddress MAC address to perform the search on
- * @param portID port ID to perform the search on
- * @param typeFilter type of records to consider for matching
- *
- * @warning if searching is successful an implicit write lock
- * to the search result is granted, therefore unlock the 
- * entry using @ref ixEthDBReleaseHashNode() as soon as possible.
- *
- * @see ixEthDBReleaseHashNode()
- *
- * @return the search result, or NULL if a record with the given
- * MAC address/port ID combination was not found
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-HashNode* ixEthDBPortSearch(IxEthDBMacAddr *macAddress, IxEthDBPortId portID, IxEthDBRecordType typeFilter)
-{
-    HashNode *searchResult = NULL;
-    MacDescriptor reference;
-    
-    if (macAddress == NULL)
-    {
-        return NULL;
-    }
-    
-    /* fill search fields */
-    memcpy(reference.macAddress, macAddress, sizeof (IxEthDBMacAddr));
-    reference.portID = portID;
-    
-    /* set acceptable record types */
-    reference.type = typeFilter;
-
-    BUSY_RETRY(ixEthDBSearchHashEntry(&dbHashtable, IX_ETH_DB_MAC_PORT_KEY, &reference, &searchResult));
-
-    return searchResult;
-}
-
-/**
- * @brief search a record in the Ethernet datbase
- *
- * @param macAddress MAC address to perform the search on
- * @param vlanID VLAN ID to perform the search on
- * @param typeFilter type of records to consider for matching
- *
- * @warning if searching is successful an implicit write lock
- * to the search result is granted, therefore unlock the 
- * entry using @ref ixEthDBReleaseHashNode() as soon as possible.
- *
- * @see ixEthDBReleaseHashNode()
- *
- * @return the search result, or NULL if a record with the given
- * MAC address/VLAN ID combination was not found
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-HashNode* ixEthDBVlanSearch(IxEthDBMacAddr *macAddress, IxEthDBVlanId vlanID, IxEthDBRecordType typeFilter)
-{
-    HashNode *searchResult = NULL;
-    MacDescriptor reference;
-    
-    if (macAddress == NULL)
-    {
-        return NULL;
-    }
-    
-    /* fill search fields */
-    memcpy(reference.macAddress, macAddress, sizeof (IxEthDBMacAddr));
-    reference.recordData.filteringVlanData.ieee802_1qTag = 
-            IX_ETH_DB_SET_VLAN_ID(reference.recordData.filteringVlanData.ieee802_1qTag, vlanID);
-    
-    /* set acceptable record types */
-    reference.type = typeFilter;
-
-    BUSY_RETRY(ixEthDBSearchHashEntry(&dbHashtable, IX_ETH_DB_MAC_VLAN_KEY, &reference, &searchResult));
-
-    return searchResult;
-}
diff --git a/arch/arm/cpu/ixp/npe/IxEthDBSpanningTree.c b/arch/arm/cpu/ixp/npe/IxEthDBSpanningTree.c
deleted file mode 100644
index 6d9fd6e..0000000
--- a/arch/arm/cpu/ixp/npe/IxEthDBSpanningTree.c
+++ /dev/null
@@ -1,107 +0,0 @@
-/**
- * @file IxEthDBSpanningTree.c
- *
- * @brief Implementation of the STP API
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- * 
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- * 
- * @par
- * -- End of Copyright Notice --
- */
-
-
-#include "IxEthDB_p.h"
-
-/**
- * @brief sets the STP blocking state of a port
- *
- * @param portID ID of the port
- * @param blocked TRUE to block the port or FALSE to unblock it
- * 
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBSpanningTreeBlockingStateSet(IxEthDBPortId portID, BOOL blocked)
-{
-    IxNpeMhMessage message;
-    IX_STATUS result;
-    
-    IX_ETH_DB_CHECK_PORT(portID);
-    
-    IX_ETH_DB_CHECK_SINGLE_NPE(portID);
- 
-    IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_SPANNING_TREE_PROTOCOL);
-    
-    ixEthDBPortInfo[portID].stpBlocked = blocked;
-
-    FILL_SETBLOCKINGSTATE_MSG(message, portID, blocked);
-    
-    IX_ETHDB_SEND_NPE_MSG(IX_ETH_DB_PORT_ID_TO_NPE(portID), message, result);
-    
-    return result;
-}
-
-/**
- * @brief retrieves the STP blocking state of a port
- *
- * @param portID ID of the port
- * @param blocked address to write the blocked status into
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBSpanningTreeBlockingStateGet(IxEthDBPortId portID, BOOL *blocked)
-{
-    IX_ETH_DB_CHECK_PORT(portID);
-    
-    IX_ETH_DB_CHECK_SINGLE_NPE(portID);
- 
-    IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_SPANNING_TREE_PROTOCOL);
-    
-    IX_ETH_DB_CHECK_REFERENCE(blocked);
-    
-    *blocked = ixEthDBPortInfo[portID].stpBlocked;
-    
-    return IX_ETH_DB_SUCCESS;
-}
diff --git a/arch/arm/cpu/ixp/npe/IxEthDBUtil.c b/arch/arm/cpu/ixp/npe/IxEthDBUtil.c
deleted file mode 100644
index e708bf1..0000000
--- a/arch/arm/cpu/ixp/npe/IxEthDBUtil.c
+++ /dev/null
@@ -1,120 +0,0 @@
-/**
- * @file ethUtil.c
- *
- * @brief Utility functions
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- * 
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- * 
- * @par
- * -- End of Copyright Notice --
- */
-
-
-#include "IxFeatureCtrl.h"
-#include "IxEthDB_p.h"
-
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBSingleEthNpeCheck(IxEthDBPortId portID)
-{
-    /* If not IXP42X A0 stepping, proceed to check for existence of coprocessors */ 
-    if ((IX_FEATURE_CTRL_SILICON_TYPE_A0 != 
-        (ixFeatureCtrlProductIdRead() & IX_FEATURE_CTRL_SILICON_STEPPING_MASK))
-        || (IX_FEATURE_CTRL_DEVICE_TYPE_IXP42X != ixFeatureCtrlDeviceRead ()))
-    {  
-        if ((portID == 0) && 
-            (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_ETH0) ==
-             IX_FEATURE_CTRL_COMPONENT_DISABLED))
-        {
-	    return IX_ETH_DB_FAIL;
-        }
-
-        if ((portID == 1) &&
-            (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_ETH1) ==
-             IX_FEATURE_CTRL_COMPONENT_DISABLED))
-        {
-	    return IX_ETH_DB_FAIL;	    
-        }
-
-        if ((portID == 2) &&
-            (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEA_ETH) ==
-             IX_FEATURE_CTRL_COMPONENT_DISABLED))
-        {
-	    return IX_ETH_DB_FAIL;	    
-        }
-    }
-    
-    return IX_ETH_DB_SUCCESS;
-}
-
-IX_ETH_DB_PUBLIC
-BOOL ixEthDBCheckSingleBitValue(UINT32 value)
-{
-#if (CPU != SIMSPARCSOLARIS) && !defined (__wince)
-    UINT32 shift;
-    
-    /* use the count-leading-zeros XScale instruction */
-    __asm__ ("clz %0, %1\n" : "=r" (shift) : "r" (value));
-    
-    return ((value << shift) == 0x80000000UL);
-    
-#else
-	
-    while (value != 0)
-    {
-        if (value == 1) return TRUE;
-        else if ((value & 1) == 1) return FALSE;
-
-        value >>= 1;
-    }
-    
-    return FALSE;
-
-#endif
-}
-
-const char *mac2string(const unsigned char *mac)
-{
-  static char str[19];
-  
-  if (mac == NULL)
-  {
-    return NULL;
-  }  
-
-  sprintf(str, "%02X:%02X:%02X:%02X:%02X:%02X", mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
-
-  return str;
-}
diff --git a/arch/arm/cpu/ixp/npe/IxEthDBVlan.c b/arch/arm/cpu/ixp/npe/IxEthDBVlan.c
deleted file mode 100644
index e2efb9b..0000000
--- a/arch/arm/cpu/ixp/npe/IxEthDBVlan.c
+++ /dev/null
@@ -1,1179 +0,0 @@
-/**
- * @file IxEthDBVlan.c
- *
- * @brief Implementation of the VLAN API
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- * 
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- * 
- * @par
- * -- End of Copyright Notice --
- */
-
-#include "IxEthDB.h"
-#include "IxEthDB_p.h"
-
-/* forward prototypes */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBUpdateTrafficClass(IxEthDBPortId portID, UINT32 classIndex);
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBVlanTableGet(IxEthDBPortId portID, IxEthDBVlanSet portVlanTable, IxEthDBVlanSet vlanSet);
-
-/* contants used by various functions as "action" parameter */
-#define ADD_VLAN    (0x1)
-#define REMOVE_VLAN (0x2)
-
-/**
- * @brief adds or removes a VLAN from a VLAN set
- *
- * @param vlanID VLAN ID to add or remove
- * @param table VLAN set to add into or remove from
- * @param action ADD_VLAN or REMOVE_VLAN
- * 
- * @internal
- */
-IX_ETH_DB_PRIVATE
-void ixEthDBLocalVlanMembershipChange(UINT32 vlanID, IxEthDBVlanSet table, UINT32 action)
-{
-    UINT32 setOffset;
-    
-    /* add/remove VID to membership table */
-    setOffset = VLAN_SET_OFFSET(vlanID); /* we need 9 bits to index the 512 byte membership array */
-
-    if (action == ADD_VLAN)
-    {
-        table[setOffset] |= 1 << VLAN_SET_MASK(vlanID);
-    }
-    else if (action == REMOVE_VLAN)
-    {
-        table[setOffset] &= ~(1 << VLAN_SET_MASK(vlanID));
-    }
-}
-
-/**
- * @brief updates a set of 8 VLANs in an NPE
- *
- * @param portID ID of the port
- * @param setOffset offset of the 8 VLANs
- *
- * This function updates the VLAN membership table
- * and Transmit Tagging Info table for 8 consecutive
- * VLAN IDs indexed by setOffset.
- *
- * For example, a setOffset of 0 indexes VLAN IDs 0
- * through 7, 1 indexes VLAN IDs 8 through 9 etc.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed
- * successfully or an appropriate error message otherwise
- *
- * @internal
- */
-IX_ETH_DB_PRIVATE
-IxEthDBStatus ixEthDBVlanTableEntryUpdate(IxEthDBPortId portID, UINT32 setOffset)
-{
-    PortInfo *portInfo = &ixEthDBPortInfo[portID];
-    IxNpeMhMessage message;
-    IX_STATUS result;
-        
-    FILL_SETPORTVLANTABLEENTRY_MSG(message, IX_ETH_DB_PORT_ID_TO_NPE_LOGICAL_ID(portID), 
-        2 * setOffset, 
-        portInfo->vlanMembership[setOffset], 
-        portInfo->transmitTaggingInfo[setOffset]);
-    
-    IX_ETHDB_SEND_NPE_MSG(IX_ETH_DB_PORT_ID_TO_NPE(portID), message, result);
-    
-    return result;
-}
-
-/**
- * @brief updates a VLAN range in an NPE
- *
- * @param portID ID of the port
- *
- * This function is similar to @ref ixEthDBVlanTableEntryUpdate
- * except that it can update more than one VLAN set (up to
- * the entire VLAN membership and TTI tables if the offset is 0
- * and length is sizeof (IxEthDBVlanSet) (512 bytes).
- *
- * Updating the NPE via this method is slower as it requires
- * a memory copy from SDRAM, hence it is recommended that the
- * ixEthDBVlanTableEntryUpdate function is used where possible.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed
- * successfully or an appropriate error message otherwise
- *
- * @internal
- */
-IX_ETH_DB_PRIVATE
-IxEthDBStatus ixEthDBVlanTableRangeUpdate(IxEthDBPortId portID)
-{
-    PortInfo *portInfo    = &ixEthDBPortInfo[portID];
-    UINT8 *vlanUpdateZone = (UINT8 *) portInfo->updateMethod.vlanUpdateZone;
-    IxNpeMhMessage message;
-    UINT32 setIndex;
-    IX_STATUS result;
-
-    /* copy membership info and transmit tagging into into exchange area */
-    for (setIndex = 0 ; setIndex < sizeof (portInfo->vlanMembership) ; setIndex++)
-    {
-        /* membership and TTI data are interleaved */
-        vlanUpdateZone[setIndex * 2]     = portInfo->vlanMembership[setIndex];
-        vlanUpdateZone[setIndex * 2 + 1] = portInfo->transmitTaggingInfo[setIndex];
-    }
-
-    IX_OSAL_CACHE_FLUSH(vlanUpdateZone, FULL_VLAN_BYTE_SIZE);
-    
-    /* build NPE message */
-    FILL_SETPORTVLANTABLERANGE_MSG(message, IX_ETH_DB_PORT_ID_TO_NPE_LOGICAL_ID(portID), 0, 0, 
-        IX_OSAL_MMU_VIRT_TO_PHYS(vlanUpdateZone));
-
-    /* send message */    
-    IX_ETHDB_SEND_NPE_MSG(IX_ETH_DB_PORT_ID_TO_NPE(portID), message, result);
-
-    return result;
-}
-
-/**
- * @brief adds or removes a VLAN from a port's VLAN membership table
- * or Transmit Tagging Information table
- *
- * @param portID ID of the port
- * @param vlanID VLAN ID to add or remove
- * @param table to add or remove from
- * @param action ADD_VLAN or REMOVE_VLAN
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed
- * successfully or an appropriate error message otherwise
- *
- * @internal
- */
-IX_ETH_DB_PRIVATE
-IxEthDBStatus ixEthDBPortVlanMembershipChange(IxEthDBPortId portID, IxEthDBVlanId vlanID, IxEthDBVlanSet table, UINT32 action)
-{
-    /* change VLAN in local membership table */
-    ixEthDBLocalVlanMembershipChange(vlanID, table, action);
-    
-    /* send updated entry to NPE */
-    return ixEthDBVlanTableEntryUpdate(portID, VLAN_SET_OFFSET(vlanID));
-}
-
-/**
- * @brief sets the default port VLAN tag (the lower 3 bytes are the PVID)
- *
- * @param portID ID of the port
- * @param vlanTag port VLAN tag (802.1Q tag)
- * 
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBPortVlanTagSet(IxEthDBPortId portID, IxEthDBVlanTag vlanTag)
-{
-    IxNpeMhMessage message;
-    IX_STATUS result;
-    
-    IX_ETH_DB_CHECK_PORT(portID);
-    
-    IX_ETH_DB_CHECK_SINGLE_NPE(portID);
- 
-    IX_ETH_DB_CHECK_VLAN_TAG(vlanTag);
-    
-    IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_VLAN_QOS);
-        
-    /* add VLAN ID to local membership table */
-    ixEthDBPortVlanMembershipChange(portID, 
-        vlanTag & IX_ETH_DB_802_1Q_VLAN_MASK, 
-        ixEthDBPortInfo[portID].vlanMembership, 
-        ADD_VLAN);
-        
-    /* set tag in portInfo */
-    ixEthDBPortInfo[portID].vlanTag = vlanTag;
-    
-    /* build VLAN_SetDefaultRxVID message */
-    FILL_SETDEFAULTRXVID_MSG(message, 
-        IX_ETH_DB_PORT_ID_TO_NPE_LOGICAL_ID(portID), 
-        IX_IEEE802_1Q_VLAN_TPID, 
-        vlanTag);
-    
-    IX_ETHDB_SEND_NPE_MSG(IX_ETH_DB_PORT_ID_TO_NPE(portID), message, result);
-    
-    return result;
-}
-
-/**
- * @brief retrieves the default port VLAN tag (the lower 3 bytes are the PVID)
- *
- * @param portID ID of the port
- * @param vlanTag address to write the port VLAN tag (802.1Q tag) into
- * 
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBPortVlanTagGet(IxEthDBPortId portID, IxEthDBVlanTag *vlanTag)
-{
-    IX_ETH_DB_CHECK_PORT(portID);
-    
-    IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-    
-    IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_VLAN_QOS);
-    
-    IX_ETH_DB_CHECK_REFERENCE(vlanTag);
-    
-    *vlanTag = ixEthDBPortInfo[portID].vlanTag;
-    
-    return IX_ETH_DB_SUCCESS;
-}
-
-/**
- * @brief sets the VLAN tag (the lower 3 bytes are the PVID) of a 
- * database filtering record
- *
- * @param portID ID of the port
- * @param vlanTag VLAN tag (802.1Q tag)
- * 
- * Important: filtering records are automatically converted to 
- * IX_ETH_DB_FILTERING_VLAN record when added a VLAN tag.
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBVlanTagSet(IxEthDBMacAddr *macAddr, IxEthDBVlanTag vlanTag)
-{
-    HashNode *searchResult;
-    MacDescriptor *descriptor;
-    
-    IX_ETH_DB_CHECK_REFERENCE(macAddr);
-    
-    IX_ETH_DB_CHECK_VLAN_TAG(vlanTag);
-    
-    searchResult = ixEthDBSearch(macAddr, IX_ETH_DB_ALL_FILTERING_RECORDS);
-    
-    if (searchResult == NULL)
-    {
-        return IX_ETH_DB_NO_SUCH_ADDR;
-    }
-    
-    descriptor = (MacDescriptor *) searchResult->data;
-    
-    /* set record type to VLAN if not already set */
-    descriptor->type = IX_ETH_DB_FILTERING_VLAN_RECORD;
-    
-    /* add vlan tag */
-    descriptor->recordData.filteringVlanData.ieee802_1qTag = vlanTag;
-    
-    /* transaction completed */
-    ixEthDBReleaseHashNode(searchResult);
-    
-    return IX_ETH_DB_SUCCESS;
-}
-
-/**
- * @brief retrieves the VLAN tag (the lower 3 bytes are the PVID) from a 
- * database VLAN filtering record
- *
- * @param portID ID of the port
- * @param vlanTag address to write the VLAN tag (802.1Q tag) into
- * 
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBVlanTagGet(IxEthDBMacAddr *macAddr, IxEthDBVlanTag *vlanTag)
-{
-    HashNode *searchResult;
-    MacDescriptor *descriptor;
-    
-    IX_ETH_DB_CHECK_REFERENCE(macAddr);
-    
-    IX_ETH_DB_CHECK_REFERENCE(vlanTag);
-    
-    searchResult = ixEthDBSearch(macAddr, IX_ETH_DB_FILTERING_VLAN_RECORD);
-    
-    if (searchResult == NULL)
-    {
-        return IX_ETH_DB_NO_SUCH_ADDR;
-    }
-    
-    descriptor = (MacDescriptor *) searchResult->data;
-        
-    /* get vlan tag */
-    *vlanTag = descriptor->recordData.filteringVlanData.ieee802_1qTag;
-    
-    /* transaction completed */
-    ixEthDBReleaseHashNode(searchResult);
-    
-    return IX_ETH_DB_SUCCESS;
-}
-
-/**
- * @brief adds a VLAN to a port's VLAN membership table
- *
- * @param portID ID of the port
- * @param vlanID VLAN ID to add
- * 
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBPortVlanMembershipAdd(IxEthDBPortId portID, IxEthDBVlanId vlanID)
-{
-    IX_ETH_DB_CHECK_PORT(portID);
-
-    IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
-    IX_ETH_DB_CHECK_VLAN_ID(vlanID);
-
-    IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_VLAN_QOS);
-
-    return ixEthDBPortVlanMembershipChange(portID, vlanID, ixEthDBPortInfo[portID].vlanMembership, ADD_VLAN);
-}
-
-/**
- * @brief removes a VLAN from a port's VLAN membership table
- *
- * @param portID ID of the port
- * @param vlanID VLAN ID to remove
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBPortVlanMembershipRemove(IxEthDBPortId portID, IxEthDBVlanId vlanID)
-{
-    IX_ETH_DB_CHECK_PORT(portID);
-
-    IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
-    IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_VLAN_QOS);
-
-    IX_ETH_DB_CHECK_VLAN_ID(vlanID);
-
-    /* for safety isolate only the VLAN ID in the tag (the lower 12 bits) */
-    vlanID = vlanID & IX_ETH_DB_802_1Q_VLAN_MASK;
-    
-    /* check we're not asked to remove the default port VID */
-    if (vlanID == IX_ETH_DB_GET_VLAN_ID(ixEthDBPortInfo[portID].vlanTag))
-    {
-        return IX_ETH_DB_NO_PERMISSION;
-    }
-    
-    return ixEthDBPortVlanMembershipChange(portID, vlanID, ixEthDBPortInfo[portID].vlanMembership, REMOVE_VLAN);
-}
-
-/**
- * @brief adds or removes a VLAN range from a port's 
- * VLAN membership table or TTI table
- *
- * @param portID ID of the port
- * @param vlanIDMin start of the VLAN range
- * @param vlanIDMax end of the VLAN range
- * @param table VLAN set to add or remove from
- * @param action ADD_VLAN or REMOVE_VLAN
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- *
- * @internal
- */
-IX_ETH_DB_PRIVATE
-IxEthDBStatus ixEthDBPortVlanMembershipRangeChange(IxEthDBPortId portID, IxEthDBVlanId vlanIDMin, IxEthDBVlanId vlanIDMax, IxEthDBVlanSet table, UINT32 action)
-{
-    UINT32 setOffsetMin, setOffsetMax;
-    
-    IX_ETH_DB_CHECK_PORT(portID);
-    
-    IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-    
-    IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_VLAN_QOS);
-    
-    IX_ETH_DB_CHECK_VLAN_ID(vlanIDMin);
-    
-    IX_ETH_DB_CHECK_VLAN_ID(vlanIDMax);
-    
-    /* for safety isolate only the VLAN ID in the tags (the lower 12 bits) */
-    vlanIDMin = vlanIDMin & IX_ETH_DB_802_1Q_VLAN_MASK;
-    vlanIDMax = vlanIDMax & IX_ETH_DB_802_1Q_VLAN_MASK;
-    
-    /* is this a range? */
-    if (vlanIDMax < vlanIDMin)
-    {
-        return IX_ETH_DB_INVALID_VLAN;
-    }
-    
-    /* check that we're not specifically asked to remove the default port VID */
-    if (action == REMOVE_VLAN && vlanIDMax == vlanIDMin && IX_ETH_DB_GET_VLAN_ID(ixEthDBPortInfo[portID].vlanTag) == vlanIDMin)
-    {
-        return IX_ETH_DB_NO_PERMISSION;
-    }
-    
-    /* compute set offsets */
-    setOffsetMin = VLAN_SET_OFFSET(vlanIDMin);
-    setOffsetMax = VLAN_SET_OFFSET(vlanIDMax);
-
-    /* change VLAN range */
-    for (; vlanIDMin <= vlanIDMax ; vlanIDMin++)
-    {
-        /* change vlan in local membership table */
-        ixEthDBLocalVlanMembershipChange(vlanIDMin, table, action);
-    }
-
-    /* if the range is within one set (max 8 VLANs in one table byte) we can just update that entry in the NPE */
-    if (setOffsetMin == setOffsetMax)
-    {
-        /* send updated entry to NPE */
-        return ixEthDBVlanTableEntryUpdate(portID, setOffsetMin);
-    }
-    else
-    {
-        /* update a zone of the membership/transmit tag info table */
-        return ixEthDBVlanTableRangeUpdate(portID);
-    }
-}
-
-/**
- * @brief adds a VLAN range to a port's VLAN membership table
- *
- * @param portID ID of the port
- * @param vlanIDMin start of the VLAN range
- * @param vlanIDMax end of the VLAN range
- * 
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBPortVlanMembershipRangeAdd(IxEthDBPortId portID, IxEthDBVlanId vlanIDMin, IxEthDBVlanId vlanIDMax)
-{
-    IX_ETH_DB_CHECK_PORT(portID);
-
-    IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
-    return ixEthDBPortVlanMembershipRangeChange(portID, vlanIDMin, vlanIDMax, ixEthDBPortInfo[portID].vlanMembership, ADD_VLAN);
-}
-
-/**
- * @brief removes a VLAN range from a port's VLAN membership table
- *
- * @param portID ID of the port
- * @param vlanIDMin start of the VLAN range
- * @param vlanIDMax end of the VLAN range
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBPortVlanMembershipRangeRemove(IxEthDBPortId portID, IxEthDBVlanId vlanIDMin, IxEthDBVlanId vlanIDMax)
-{
-    IX_ETH_DB_CHECK_PORT(portID);
-
-    IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
-    return ixEthDBPortVlanMembershipRangeChange(portID, vlanIDMin, vlanIDMax, ixEthDBPortInfo[portID].vlanMembership, REMOVE_VLAN);
-}
-
-/**
- * @brief sets a port's VLAN membership table or TTI table and
- * updates the NPE VLAN configuration
- *
- * @param portID ID of the port
- * @param portVlanTable port VLAN table to set
- * @param vlanSet new set contents
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBPortVlanTableSet(IxEthDBPortId portID, IxEthDBVlanSet portVlanTable, IxEthDBVlanSet vlanSet)
-{
-    IX_ETH_DB_CHECK_PORT(portID);
-    
-    IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-    
-    IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_VLAN_QOS);
-    
-    IX_ETH_DB_CHECK_REFERENCE(vlanSet);
-
-    memcpy(portVlanTable, vlanSet, sizeof (IxEthDBVlanSet));
-    
-    return ixEthDBVlanTableRangeUpdate(portID);
-}
-
-/**
- * @brief retireves a port's VLAN membership table or TTI table
- *
- * @param portID ID of the port
- * @param portVlanTable port VLAN table to retrieve
- * @param vlanSet address to 
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBVlanTableGet(IxEthDBPortId portID, IxEthDBVlanSet portVlanTable, IxEthDBVlanSet vlanSet)
-{
-    IX_ETH_DB_CHECK_PORT(portID);
-    
-    IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-    
-    IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_VLAN_QOS);
-    
-    IX_ETH_DB_CHECK_REFERENCE(vlanSet);
-    
-    memcpy(vlanSet, portVlanTable, sizeof (IxEthDBVlanSet));
-    
-    return IX_ETH_DB_SUCCESS;
-}
-
-/**
- * @brief sets a port's VLAN membership table
- *
- * @param portID ID of the port
- * @param vlanSet new VLAN membership table
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBPortVlanMembershipSet(IxEthDBPortId portID, IxEthDBVlanSet vlanSet)
-{
-    IxEthDBVlanId vlanID;
-
-    IX_ETH_DB_CHECK_PORT(portID);
-    
-    IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
-    IX_ETH_DB_CHECK_REFERENCE(vlanSet);
-
-    /* set the bit corresponding to the PVID just in case */
-    vlanID = IX_ETH_DB_GET_VLAN_ID(ixEthDBPortInfo[portID].vlanTag);
-    vlanSet[VLAN_SET_OFFSET(vlanID)] |= 1 << VLAN_SET_MASK(vlanID);
-    
-    return ixEthDBPortVlanTableSet(portID, ixEthDBPortInfo[portID].vlanMembership, vlanSet);
-}
-
-/**
- * @brief retrieves a port's VLAN membership table
- *
- * @param portID ID of the port
- * @param vlanSet location to store the port's VLAN membership table
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBPortVlanMembershipGet(IxEthDBPortId portID, IxEthDBVlanSet vlanSet)
-{
-    IX_ETH_DB_CHECK_PORT(portID);
-    
-    IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-    
-    return ixEthDBVlanTableGet(portID, ixEthDBPortInfo[portID].vlanMembership, vlanSet);
-}
-
-/**
- * @brief enables or disables Egress tagging for one VLAN ID
- *
- * @param portID ID of the port
- * @param vlanID VLAN ID to enable or disable Egress tagging on
- * @param enabled TRUE to enable and FALSE to disable tagging
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBEgressVlanEntryTaggingEnabledSet(IxEthDBPortId portID, IxEthDBVlanId vlanID, BOOL enabled)
-{
-    IX_ETH_DB_CHECK_PORT(portID);
-    
-    IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
-    IX_ETH_DB_CHECK_VLAN_ID(vlanID);
-
-    IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_VLAN_QOS);
-
-    return ixEthDBPortVlanMembershipChange(portID, vlanID, ixEthDBPortInfo[portID].transmitTaggingInfo, enabled? ADD_VLAN : REMOVE_VLAN);
-}
-
-/**
- * @brief retrieves the Egress tagging status for one VLAN ID
- *
- * @param portID ID of the port
- * @param vlanID VLAN ID to retrieve the tagging status for
- * @param enabled location to store the tagging status
- * (TRUE - tagging enabled, FALSE - tagging disabled)
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBEgressVlanEntryTaggingEnabledGet(IxEthDBPortId portID, IxEthDBVlanId vlanID, BOOL *enabled)
-{
-    IX_ETH_DB_CHECK_PORT(portID);
-    
-    IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-    
-    IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_VLAN_QOS);
-    
-    IX_ETH_DB_CHECK_REFERENCE(enabled);
-
-    IX_ETH_DB_CHECK_VLAN_ID(vlanID);
-    
-    *enabled = ((ixEthDBPortInfo[portID].transmitTaggingInfo[VLAN_SET_OFFSET(vlanID)] & (1 << VLAN_SET_MASK(vlanID))) != 0);
-    
-    return IX_ETH_DB_SUCCESS;
-}
-
-/**
- * @brief enables or disables Egress VLAN tagging for a VLAN range
- *
- * @param portID ID of the port
- * @param vlanIDMin start of VLAN range
- * @param vlanIDMax end of VLAN range
- * @param enabled TRUE to enable or FALSE to disable VLAN tagging
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBEgressVlanRangeTaggingEnabledSet(IxEthDBPortId portID, IxEthDBVlanId vlanIDMin, IxEthDBVlanId vlanIDMax, BOOL enabled)
-{
-    IX_ETH_DB_CHECK_PORT(portID);
-    
-    IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-    
-    return ixEthDBPortVlanMembershipRangeChange(portID, vlanIDMin, vlanIDMax, ixEthDBPortInfo[portID].transmitTaggingInfo, enabled? ADD_VLAN : REMOVE_VLAN);
-}
-
-/**
- * @brief sets the Egress VLAN tagging table (the Transmit Tagging
- * Information table)
- *
- * @param portID ID of the port
- * @param vlanSet new TTI table
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBEgressVlanTaggingEnabledSet(IxEthDBPortId portID, IxEthDBVlanSet vlanSet)
-{
-    IxEthDBVlanId vlanID;
-
-    IX_ETH_DB_CHECK_PORT(portID);
-    
-    IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
-    IX_ETH_DB_CHECK_REFERENCE(vlanSet);
-
-    /* set the PVID bit just in case */
-    vlanID = IX_ETH_DB_GET_VLAN_ID(ixEthDBPortInfo[portID].vlanTag);
-    vlanSet[VLAN_SET_OFFSET(vlanID)] |= 1 << VLAN_SET_MASK(vlanID);
-    
-    return ixEthDBPortVlanTableSet(portID, ixEthDBPortInfo[portID].transmitTaggingInfo, vlanSet);
-}
-
-/**
- * @brief retrieves the Egress VLAN tagging table (the Transmit 
- * Tagging Information table)
- *
- * @param portID ID of the port
- * @param vlanSet location to store the port's TTI table
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBEgressVlanTaggingEnabledGet(IxEthDBPortId portID, IxEthDBVlanSet vlanSet)
-{
-    IX_ETH_DB_CHECK_PORT(portID);
-    
-    IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-    
-    return ixEthDBVlanTableGet(portID, ixEthDBPortInfo[portID].transmitTaggingInfo, vlanSet);
-}
-
-/**
- * @brief sends the NPE the updated frame filter and default
- * Ingress tagging
- *
- * @param portID ID of the port
- * 
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- *
- * @internal
- */
-IX_ETH_DB_PRIVATE
-IxEthDBStatus ixEthDBIngressVlanModeUpdate(IxEthDBPortId portID)
-{
-    PortInfo *portInfo = &ixEthDBPortInfo[portID];
-    IxNpeMhMessage message;
-    IX_STATUS result;
-
-    FILL_SETRXTAGMODE_MSG(message, portID, portInfo->npeFrameFilter, portInfo->npeTaggingAction);
-    IX_ETHDB_SEND_NPE_MSG(IX_ETH_DB_PORT_ID_TO_NPE(portID), message, result);
-
-    return result;
-}
-
-/**
- * @brief sets the default Ingress tagging behavior
- *
- * @param portID ID of the port
- * @param taggingAction default tagging behavior
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBIngressVlanTaggingEnabledSet(IxEthDBPortId portID, IxEthDBTaggingAction taggingAction)
-{
-    PortInfo *portInfo;
-    
-    IX_ETH_DB_CHECK_PORT(portID);
-    
-    IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-    
-    IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_VLAN_QOS);
-    
-    portInfo = &ixEthDBPortInfo[portID];
-    
-    if (taggingAction == IX_ETH_DB_PASS_THROUGH)
-    {
-        portInfo->npeTaggingAction = 0x00;
-    }
-    else if (taggingAction == IX_ETH_DB_ADD_TAG)
-    {
-        portInfo->npeTaggingAction = 0x02;
-    }
-    else if (taggingAction == IX_ETH_DB_REMOVE_TAG)
-    {
-        portInfo->npeTaggingAction = 0x01;
-    }
-    else
-    {
-        return IX_ETH_DB_INVALID_ARG;
-    }
-    
-    portInfo->taggingAction = taggingAction;
-    
-    return ixEthDBIngressVlanModeUpdate(portID);
-}
-
-/**
- * @brief retrieves the default Ingress tagging behavior of a port
- *
- * @param portID ID of the port
- * @param taggingAction location to save the default tagging behavior
- * 
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBIngressVlanTaggingEnabledGet(IxEthDBPortId portID, IxEthDBTaggingAction *taggingAction)
-{
-    IX_ETH_DB_CHECK_PORT(portID);
-    
-    IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-    
-    IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_VLAN_QOS);
-
-    IX_ETH_DB_CHECK_REFERENCE(taggingAction);
-    
-    *taggingAction = ixEthDBPortInfo[portID].taggingAction;
-    
-    return IX_ETH_DB_SUCCESS;
-}
-
-/**
- * @brief sets the Ingress acceptable frame type filter
- *
- * @param portID ID of the port
- * @param frameFilter acceptable frame type filter
- * 
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBAcceptableFrameTypeSet(IxEthDBPortId portID, IxEthDBFrameFilter frameFilter)
-{
-    PortInfo *portInfo;
-    IxEthDBStatus result = IX_ETH_DB_SUCCESS;
-        
-    IX_ETH_DB_CHECK_PORT(portID);
-    
-    IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-    
-    IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_VLAN_QOS);
-    
-    /* check parameter range 
-       the ORed value of the valid values is 0x7
-       a value having extra bits is invalid */
-    if ((frameFilter | 0x7) != 0x7 || frameFilter == 0)
-    {
-        return IX_ETH_DB_INVALID_ARG;
-    }
-    
-    portInfo = &ixEthDBPortInfo[portID];
-    
-    portInfo->frameFilter    = frameFilter;
-    portInfo->npeFrameFilter = 0; /* allow all by default */
-    
-    /* if accepting priority tagged but not all VLAN tagged
-       set the membership table to contain only VLAN ID 0 
-       hence remove vlans 1-4094 and add VLAN ID 0 */
-    if (((frameFilter & IX_ETH_DB_PRIORITY_TAGGED_FRAMES) != 0)
-        && ((frameFilter & IX_ETH_DB_VLAN_TAGGED_FRAMES) == 0))
-    {
-        result = ixEthDBPortVlanMembershipRangeChange(portID, 
-            1, IX_ETH_DB_802_1Q_MAX_VLAN_ID, portInfo->vlanMembership, REMOVE_VLAN);
-
-        if (result == IX_ETH_DB_SUCCESS)
-        {
-            ixEthDBLocalVlanMembershipChange(0, portInfo->vlanMembership, ADD_VLAN);
-            result = ixEthDBVlanTableRangeUpdate(portID);
-        }
-    }
-    
-    /* untagged only? */
-    if (frameFilter == IX_ETH_DB_UNTAGGED_FRAMES)
-    {
-        portInfo->npeFrameFilter = 0x01;
-    }
-    
-    /* tagged only? */
-    if ((frameFilter & IX_ETH_DB_UNTAGGED_FRAMES) == 0)
-    {
-        portInfo->npeFrameFilter = 0x02;
-    }
-
-    if (result == IX_ETH_DB_SUCCESS)
-    {
-        result = ixEthDBIngressVlanModeUpdate(portID);
-    }
-
-    return result;
-}
-
-/**
- * @brief retrieves the acceptable frame type filter for a port
- *
- * @param portID ID of the port
- * @param frameFilter location to store the frame filter
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBAcceptableFrameTypeGet(IxEthDBPortId portID, IxEthDBFrameFilter *frameFilter)
-{
-    IX_ETH_DB_CHECK_PORT(portID);
-    
-    IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-    
-    IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_VLAN_QOS);
-    
-    IX_ETH_DB_CHECK_REFERENCE(frameFilter);
-    
-    *frameFilter = ixEthDBPortInfo[portID].frameFilter;
-    
-    return IX_ETH_DB_SUCCESS;
-}
-
-/**
- * @brief sends an NPE the updated configuration related
- * to one QoS priority (associated traffic class and AQM mapping)
- *
- * @param portID ID of the port
- * @param classIndex QoS priority (traffic class index)
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBUpdateTrafficClass(IxEthDBPortId portID, UINT32 classIndex)
-{
-    IxNpeMhMessage message;
-    IX_STATUS result;
-
-    UINT32 trafficClass = ixEthDBPortInfo[portID].priorityTable[classIndex];
-    UINT32 aqmQueue     = ixEthDBPortInfo[portID].ixEthDBTrafficClassAQMAssignments[trafficClass];
-    
-    FILL_SETRXQOSENTRY(message, IX_ETH_DB_PORT_ID_TO_NPE_LOGICAL_ID(portID), classIndex, trafficClass, aqmQueue);
-    
-    IX_ETHDB_SEND_NPE_MSG(IX_ETH_DB_PORT_ID_TO_NPE(portID), message, result);
-    
-    return result;
-}
-
-/**
- * @brief sets the priority mapping table
- *
- * @param portID ID of the port
- * @param priorityTable new priority mapping table
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBPriorityMappingTableSet(IxEthDBPortId portID, IxEthDBPriorityTable priorityTable)
-{
-    UINT32 classIndex;
-    
-    IX_ETH_DB_CHECK_PORT(portID);
-    
-    IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-    
-    IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_VLAN_QOS);
-    
-    IX_ETH_DB_CHECK_REFERENCE(priorityTable);
-           
-    for (classIndex = 0 ; classIndex < IX_IEEE802_1Q_QOS_PRIORITY_COUNT ; classIndex++)
-    {
-        /* check range */
-        if (priorityTable[classIndex] >= ixEthDBPortInfo[portID].ixEthDBTrafficClassCount)
-        {
-            return IX_ETH_DB_INVALID_PRIORITY;
-        }
-    }
-    
-    /* set new traffic classes */
-    for (classIndex = 0 ; classIndex < IX_IEEE802_1Q_QOS_PRIORITY_COUNT ; classIndex++)
-    {
-        ixEthDBPortInfo[portID].priorityTable[classIndex] = priorityTable[classIndex];
-        
-        if (ixEthDBUpdateTrafficClass(portID, classIndex) != IX_ETH_DB_SUCCESS)
-        {
-            return IX_ETH_DB_FAIL;
-        }
-    }
-    
-    return IX_ETH_DB_SUCCESS;
- }
-
-/**
- * @brief retrieves a port's priority mapping table
- *
- * @param portID ID of the port
- * @param priorityTable location to store the priority table
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBPriorityMappingTableGet(IxEthDBPortId portID, IxEthDBPriorityTable priorityTable)
-{
-    IX_ETH_DB_CHECK_PORT(portID);
-    
-    IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-    
-    IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_VLAN_QOS);
-    
-    IX_ETH_DB_CHECK_REFERENCE(priorityTable);
-    
-    memcpy(priorityTable, ixEthDBPortInfo[portID].priorityTable, sizeof (IxEthDBPriorityTable));
-    
-    return IX_ETH_DB_SUCCESS;
-}
-
-/**
- * @brief sets one QoS priority => traffic class mapping
- *
- * @param portID ID of the port
- * @param userPriority QoS (user) priority
- * @param trafficClass associated traffic class
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBPriorityMappingClassSet(IxEthDBPortId portID, IxEthDBPriority userPriority, IxEthDBPriority trafficClass)
-{
-    IX_ETH_DB_CHECK_PORT(portID);
-    
-    IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-    
-    IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_VLAN_QOS);
-
-    /* check ranges for userPriority and trafficClass */
-    if (userPriority >= IX_IEEE802_1Q_QOS_PRIORITY_COUNT || trafficClass >= ixEthDBPortInfo[portID].ixEthDBTrafficClassCount)
-    {
-        return IX_ETH_DB_INVALID_PRIORITY;
-    }
-    
-    ixEthDBPortInfo[portID].priorityTable[userPriority] = trafficClass;
-    
-    return ixEthDBUpdateTrafficClass(portID, userPriority);
-}
-
-/**
- * @brief retrieves one QoS priority => traffic class mapping
- *
- * @param portID ID of the port
- * @param userPriority QoS (user) priority
- * @param trafficClass location to store the associated traffic class
- * 
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBPriorityMappingClassGet(IxEthDBPortId portID, IxEthDBPriority userPriority, IxEthDBPriority *trafficClass)
-{
-    IX_ETH_DB_CHECK_PORT(portID);
-    
-    IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-    
-    IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_VLAN_QOS);
-    
-    IX_ETH_DB_CHECK_REFERENCE(trafficClass);
-    
-    /* check userPriority range */
-    if (userPriority >= IX_IEEE802_1Q_QOS_PRIORITY_COUNT)
-    {
-        return IX_ETH_DB_INVALID_PRIORITY;
-    }
-    
-    *trafficClass = ixEthDBPortInfo[portID].priorityTable[userPriority];
-    
-    return IX_ETH_DB_SUCCESS;
-}
-
-/**
- * @brief enables or disables the source port extraction
- * from the VLAN TPID field
- *
- * @param portID ID of the port
- * @param enable TRUE to enable or FALSE to disable
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBVlanPortExtractionEnable(IxEthDBPortId portID, BOOL enable)
-{
-    IxNpeMhMessage message;
-    IX_STATUS result;
-
-    IX_ETH_DB_CHECK_PORT(portID);
-    
-    IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-    
-    IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_VLAN_QOS);
-
-    FILL_SETPORTIDEXTRACTIONMODE(message, portID, enable);
-
-    IX_ETHDB_SEND_NPE_MSG(IX_ETH_DB_PORT_ID_TO_NPE(portID), message, result);
-    
-    return result;
-}
diff --git a/arch/arm/cpu/ixp/npe/IxEthDBWiFi.c b/arch/arm/cpu/ixp/npe/IxEthDBWiFi.c
deleted file mode 100644
index 0a6043f..0000000
--- a/arch/arm/cpu/ixp/npe/IxEthDBWiFi.c
+++ /dev/null
@@ -1,480 +0,0 @@
-/**
- * @file IxEthDBAPI.c
- *
- * @brief Implementation of the public API
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- * 
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- * 
- * @par
- * -- End of Copyright Notice --
- */
-
-#include "IxEthDB_p.h"
-
-/* forward prototypes */
-IX_ETH_DB_PUBLIC
-MacTreeNode *ixEthDBGatewaySelect(MacTreeNode *stations);
-
-/**
- * @brief sets the BBSID value for the WiFi header conversion feature
- *
- * @param portID ID of the port
- * @param bbsid pointer to the 6-byte BBSID value
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBWiFiBBSIDSet(IxEthDBPortId portID, IxEthDBMacAddr *bbsid)
-{
-    IxNpeMhMessage message;
-    IX_STATUS result;
-    
-    IX_ETH_DB_CHECK_PORT(portID);
-    
-    IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-    
-    IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_WIFI_HEADER_CONVERSION);
- 
-    IX_ETH_DB_CHECK_REFERENCE(bbsid);
-    
-    memcpy(ixEthDBPortInfo[portID].bbsid, bbsid, sizeof (IxEthDBMacAddr));
-
-    FILL_SETBBSID_MSG(message, portID, bbsid);
-
-    IX_ETHDB_SEND_NPE_MSG(IX_ETH_DB_PORT_ID_TO_NPE(portID), message, result);
-    
-    return result;
-}
-
-/**
- * @brief updates the Frame Control and Duration/ID WiFi header
- * conversion parameters in an NPE
- *
- * @param portID ID of the port
- *
- * This function will send a message to the NPE updating the 
- * frame conversion parameters for 802.3 => 802.11 header conversion.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or IX_ETH_DB_FAIL otherwise
- *
- * @internal
- */
-IX_ETH_DB_PRIVATE
-IxEthDBStatus ixEthDBWiFiFrameControlDurationIDUpdate(IxEthDBPortId portID)
-{
-    IxNpeMhMessage message;
-    IX_STATUS result;
-
-    FILL_SETFRAMECONTROLDURATIONID(message, portID, ixEthDBPortInfo[portID].frameControlDurationID);
-    
-    IX_ETHDB_SEND_NPE_MSG(IX_ETH_DB_PORT_ID_TO_NPE(portID), message, result);
-    
-    return result;
-}
-
-/**
- * @brief sets the Duration/ID WiFi frame header conversion parameter
- *
- * @param portID ID of the port
- * @param durationID 16-bit value containing the new Duration/ID parameter
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBWiFiDurationIDSet(IxEthDBPortId portID, UINT16 durationID)
-{
-    IX_ETH_DB_CHECK_PORT(portID);
-    
-    IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-    
-    IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_WIFI_HEADER_CONVERSION);
-
-    ixEthDBPortInfo[portID].frameControlDurationID = (ixEthDBPortInfo[portID].frameControlDurationID & 0xFFFF0000) | durationID;
-    
-    return ixEthDBWiFiFrameControlDurationIDUpdate(portID);
-}
-
-/**
- * @brief sets the Frame Control WiFi frame header conversion parameter
- *
- * @param portID ID of the port
- * @param durationID 16-bit value containing the new Frame Control parameter
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBWiFiFrameControlSet(IxEthDBPortId portID, UINT16 frameControl)
-{
-    IX_ETH_DB_CHECK_PORT(portID);
-    
-    IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-    
-    IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_WIFI_HEADER_CONVERSION);
-
-    ixEthDBPortInfo[portID].frameControlDurationID = (ixEthDBPortInfo[portID].frameControlDurationID & 0xFFFF) | (frameControl << 16); 
-    
-    return ixEthDBWiFiFrameControlDurationIDUpdate(portID);
-}
-
-/**
- * @brief removes a WiFi header conversion record
- *
- * @param portID ID of the port
- * @param macAddr MAC address of the record to remove
- *
- * Note that this function is documented in the main
- * component header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed
- * successfully or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBWiFiEntryRemove(IxEthDBPortId portID, IxEthDBMacAddr *macAddr)
-{
-    MacDescriptor recordTemplate;
-    
-    IX_ETH_DB_CHECK_PORT(portID);
-    
-    IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-    
-    IX_ETH_DB_CHECK_REFERENCE(macAddr);
-    
-    IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_WIFI_HEADER_CONVERSION);
-    
-    memcpy(recordTemplate.macAddress, macAddr, sizeof (IxEthDBMacAddr));
-    
-    recordTemplate.type   = IX_ETH_DB_WIFI_RECORD;
-    recordTemplate.portID = portID;
-    
-    return ixEthDBRemove(&recordTemplate, NULL);
-}
-
-/**
- * @brief adds a WiFi header conversion record
- *
- * @param portID ID of the port
- * @param macAddr MAC address of the record to add
- * @param gatewayMacAddr address of the gateway (or
- * NULL if this is a station record)
- *
- * This function adds a record of type AP_TO_AP (gateway is not NULL)
- * or AP_TO_STA (gateway is NULL) in the main database as a 
- * WiFi header conversion record.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed
- * successfully or an appropriate error message otherwise
- *
- * @internal
- */
-IX_ETH_DB_PRIVATE
-IxEthDBStatus ixEthDBWiFiEntryAdd(IxEthDBPortId portID, IxEthDBMacAddr *macAddr, IxEthDBMacAddr *gatewayMacAddr)
-{
-    MacDescriptor recordTemplate;
-
-    IX_ETH_DB_CHECK_PORT(portID);
-
-    IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
-    IX_ETH_DB_CHECK_REFERENCE(macAddr);
-    
-    IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_WIFI_HEADER_CONVERSION);
-
-    memcpy(recordTemplate.macAddress, macAddr, sizeof (IxEthDBMacAddr));
-    
-    recordTemplate.type   = IX_ETH_DB_WIFI_RECORD;
-    recordTemplate.portID = portID;
-    
-    if (gatewayMacAddr != NULL)
-    {
-        memcpy(recordTemplate.recordData.wifiData.gwMacAddress, gatewayMacAddr, sizeof (IxEthDBMacAddr));
-        
-        recordTemplate.recordData.wifiData.type = IX_ETH_DB_WIFI_AP_TO_AP;
-    }
-    else
-    {
-        memset(recordTemplate.recordData.wifiData.gwMacAddress, 0, sizeof (IxEthDBMacAddr));
-
-        recordTemplate.recordData.wifiData.type = IX_ETH_DB_WIFI_AP_TO_STA;
-    }
-    
-    return ixEthDBAdd(&recordTemplate, NULL);
-}
-
-/**
- * @brief adds a WiFi header conversion record
- *
- * @param portID ID of the port
- * @param macAddr MAC address of the record to add
- * @param gatewayMacAddr address of the gateway 
- *
- * This function adds a record of type AP_TO_AP
- * in the main database as a WiFi header conversion record.
- *
- * This is simply a wrapper over @ref ixEthDBWiFiEntryAdd().
- *
- * Note that this function is documented in the main
- * component header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed
- * successfully or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBWiFiAccessPointEntryAdd(IxEthDBPortId portID, IxEthDBMacAddr *macAddr, IxEthDBMacAddr *gatewayMacAddr)
-{
-    IX_ETH_DB_CHECK_REFERENCE(gatewayMacAddr);
-
-    return ixEthDBWiFiEntryAdd(portID, macAddr, gatewayMacAddr);
-}
-
-/**
- * @brief adds a WiFi header conversion record
- *
- * @param portID ID of the port
- * @param macAddr MAC address of the record to add
- *
- * This function adds a record of type AP_TO_STA
- * in the main database as a WiFi header conversion record.
- *
- * This is simply a wrapper over @ref ixEthDBWiFiEntryAdd().
- *
- * Note that this function is documented in the main
- * component header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed
- * successfully or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBWiFiStationEntryAdd(IxEthDBPortId portID, IxEthDBMacAddr *macAddr)
-{
-    return ixEthDBWiFiEntryAdd(portID, macAddr, NULL);
-}
-
-/**
- * @brief selects a set of gateways from a tree of 
- * WiFi header conversion records
- *
- * @param stations binary tree containing pointers to WiFi header
- * conversion records
- *
- * This function browses through the input binary tree, identifies
- * records of type AP_TO_AP, clones these records and appends them
- * to a vine (a single right-branch binary tree) which is returned
- * as result. A maximum of MAX_GW_SIZE entries containing gateways
- * will be cloned from the original tree.
- *
- * @return vine (linear binary tree) containing record
- * clones of AP_TO_AP type, which have a gateway field
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-MacTreeNode *ixEthDBGatewaySelect(MacTreeNode *stations)
-{
-    MacTreeNodeStack *stack;
-    MacTreeNode *gateways, *insertionPlace;
-    UINT32 gwIndex = 1; /* skip the empty root */
-    
-    if (stations == NULL)
-    {
-        return NULL;
-    }
-
-    stack = ixOsalCacheDmaMalloc(sizeof (MacTreeNodeStack));
-
-    if (stack == NULL)
-    {
-        ERROR_LOG("DB: (WiFi) failed to allocate the node stack for gateway tree linearization, out of memory?\n");
-        return NULL;
-    }
-    
-    /* initialize root node */
-    gateways = insertionPlace = NULL;
-        
-    /* start browsing the station tree */
-    NODE_STACK_INIT(stack);
-    
-    /* initialize stack by pushing the tree root at offset 0 */
-    NODE_STACK_PUSH(stack, stations, 0);
-    
-    while (NODE_STACK_NONEMPTY(stack))
-    {
-        MacTreeNode *node;
-        UINT32 offset;
-       
-        NODE_STACK_POP(stack, node, offset);
-
-        /* we can store maximum 31 (32 total, 1 empty root) entries in the gateway tree */
-        if (offset > (MAX_GW_SIZE - 1)) break;
-        
-        /* check if this record has a gateway address */
-        if (node->descriptor != NULL && node->descriptor->recordData.wifiData.type == IX_ETH_DB_WIFI_AP_TO_AP)
-        {
-            /* found a record, create an insertion place */
-            if (insertionPlace != NULL)
-            {
-                insertionPlace->right = ixEthDBAllocMacTreeNode();
-                insertionPlace        = insertionPlace->right;
-            }
-            else
-            {
-                gateways       = ixEthDBAllocMacTreeNode();
-                insertionPlace = gateways;
-            }
-
-            if (insertionPlace == NULL)
-            {
-                /* no nodes left, bail out with what we have */
-                ixOsalCacheDmaFree(stack);
-                return gateways;
-            }
-            
-            /* clone the original record for the gateway tree */
-            insertionPlace->descriptor = ixEthDBCloneMacDescriptor(node->descriptor);
-            
-            /* insert and update the offset in the original record */
-            node->descriptor->recordData.wifiData.gwAddressIndex = gwIndex++;
-        }
-        
-        /* browse the tree */
-        if (node->left != NULL)
-        {
-            NODE_STACK_PUSH(stack, node->left, LEFT_CHILD_OFFSET(offset));
-        }
-
-        if (node->right != NULL)
-        {
-            NODE_STACK_PUSH(stack, node->right, RIGHT_CHILD_OFFSET(offset));
-        }
-    }
-    
-    ixOsalCacheDmaFree(stack);
-    return gateways;    
-}
-
-/**
- * @brief downloads the WiFi header conversion table to an NPE
- *
- * @param portID ID of the port
- *
- * This function prepares the WiFi header conversion tables and
- * downloads them to the specified NPE port.
- *
- * The header conversion tables consist in the main table of
- * addresses and the secondary table of gateways. AP_TO_AP records
- * from the first table contain index fields into the second table
- * for gateway selection.
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBWiFiConversionTableDownload(IxEthDBPortId portID)
-{
-    IxEthDBPortMap query;
-    MacTreeNode *stations = NULL, *gateways = NULL, *gateway = NULL;
-    IxNpeMhMessage message;
-    PortInfo *portInfo;
-    IX_STATUS result;
-
-    IX_ETH_DB_CHECK_PORT(portID);
-
-    IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-    
-    IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_WIFI_HEADER_CONVERSION);
-
-    portInfo = &ixEthDBPortInfo[portID];
-   
-    SET_DEPENDENCY_MAP(query, portID);
-    
-    ixEthDBUpdateLock();
-
-    stations = ixEthDBQuery(NULL, query, IX_ETH_DB_WIFI_RECORD, MAX_ELT_SIZE);
-    gateways = ixEthDBGatewaySelect(stations);
-    
-    /* clean up gw area */
-    memset((void *) portInfo->updateMethod.npeGwUpdateZone, FULL_GW_BYTE_SIZE, 0);
-
-    /* write all gateways */
-    gateway = gateways;
-
-    while (gateway != NULL)
-    {
-        ixEthDBNPEGatewayNodeWrite((void *) (((UINT32) portInfo->updateMethod.npeGwUpdateZone) 
-            + gateway->descriptor->recordData.wifiData.gwAddressIndex * ELT_ENTRY_SIZE), 
-            gateway);
-
-        gateway = gateway->right;
-    }
-
-    /* free the gateway tree */
-    if (gateways != NULL)
-    {
-        ixEthDBFreeMacTreeNode(gateways);
-    }
-
-    FILL_SETAPMACTABLE_MSG(message, 
-        IX_OSAL_MMU_VIRT_TO_PHYS(portInfo->updateMethod.npeGwUpdateZone));
-
-    IX_ETHDB_SEND_NPE_MSG(IX_ETH_DB_PORT_ID_TO_NPE(portID), message, result);
-
-    if (result == IX_SUCCESS)
-    {
-        /* update the main tree (the stations tree) */
-        portInfo->updateMethod.searchTree = stations;
-        
-        result = ixEthDBNPEUpdateHandler(portID, IX_ETH_DB_WIFI_RECORD);
-    }
-
-    ixEthDBUpdateUnlock();
-
-    return result;
-}
diff --git a/arch/arm/cpu/ixp/npe/IxEthMii.c b/arch/arm/cpu/ixp/npe/IxEthMii.c
deleted file mode 100644
index 4d92f17..0000000
--- a/arch/arm/cpu/ixp/npe/IxEthMii.c
+++ /dev/null
@@ -1,497 +0,0 @@
-/**
- * @file IxEthMii.c
- *
- * @author Intel Corporation
- * @date
- *
- * @brief  MII control functions
- *
- * Design Notes:
- *
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- * 
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- * 
- * @par
- * -- End of Copyright Notice --
- */
-
-#include "IxOsal.h"
-
-#include "IxEthAcc.h"
-#include "IxEthMii_p.h"
-
-#ifdef __wince
-#include "IxOsPrintf.h"
-#endif
-
-/* Array to store the phy IDs of the discovered phys */
-PRIVATE UINT32 ixEthMiiPhyId[IXP425_ETH_ACC_MII_MAX_ADDR];
-
-/*********************************************************
- *
- * Scan for PHYs on the MII bus. This function returns
- * an array of booleans, one for each PHY address.
- * If a PHY is found at a particular address, the
- * corresponding entry in the array is set to TRUE.
- *
- */
-
-PUBLIC IX_STATUS
-ixEthMiiPhyScan(BOOL phyPresent[], UINT32 maxPhyCount)
-{
-    UINT32 i;
-    UINT16 regval, regvalId1, regvalId2;
-
-    /*Search for PHYs on the MII*/
-    /*Search for existant phys on the MDIO bus*/
-
-    if ((phyPresent == NULL) || 
-	(maxPhyCount > IXP425_ETH_ACC_MII_MAX_ADDR))
-    {
-	return IX_FAIL;
-    }
-
-    /* fill the array */
-    for(i=0;
-        i<IXP425_ETH_ACC_MII_MAX_ADDR;
-	i++)
-    {
-	phyPresent[i] = FALSE;
-    }
-
-    /* iterate through the PHY addresses */
-    for(i=0;
-	maxPhyCount > 0 && i<IXP425_ETH_ACC_MII_MAX_ADDR;
-	i++)
-    {
-	ixEthMiiPhyId[i] = IX_ETH_MII_INVALID_PHY_ID;
-	if(ixEthAccMiiReadRtn(i,
-			      IX_ETH_MII_CTRL_REG,
-			      &regval) == IX_ETH_ACC_SUCCESS)
-	{
-	    if((regval & 0xffff) != 0xffff)
-	    {
-		maxPhyCount--;
-		/*Need to read the register twice here to flush PHY*/
-		ixEthAccMiiReadRtn(i,  IX_ETH_MII_PHY_ID1_REG, &regvalId1);
-		ixEthAccMiiReadRtn(i,  IX_ETH_MII_PHY_ID1_REG, &regvalId1);
-		ixEthAccMiiReadRtn(i,  IX_ETH_MII_PHY_ID2_REG, &regvalId2);
-		ixEthMiiPhyId[i] = (regvalId1 << IX_ETH_MII_REG_SHL) | regvalId2;
-		if ((ixEthMiiPhyId[i] == IX_ETH_MII_KS8995_PHY_ID)
-		    || (ixEthMiiPhyId[i] == IX_ETH_MII_LXT971_PHY_ID)
-		    || (ixEthMiiPhyId[i] == IX_ETH_MII_LXT972_PHY_ID)
-		    || (ixEthMiiPhyId[i] == IX_ETH_MII_LXT973_PHY_ID)
-		    || (ixEthMiiPhyId[i] == IX_ETH_MII_LXT973A3_PHY_ID)
-		    || (ixEthMiiPhyId[i] == IX_ETH_MII_LXT9785_PHY_ID)
-		    )
-		{
-		    /* supported phy */
-		    phyPresent[i] = TRUE;
-		} /* end of if(ixEthMiiPhyId) */
-		else
-		{
-		    if (ixEthMiiPhyId[i] != IX_ETH_MII_INVALID_PHY_ID)
-		    {
-			/* unsupported phy */
-                        ixOsalLog (IX_OSAL_LOG_LVL_ERROR,
-                                   IX_OSAL_LOG_DEV_STDOUT,
-				    "ixEthMiiPhyScan : unexpected Mii PHY ID %8.8x\n", 
-				    ixEthMiiPhyId[i], 2, 3, 4, 5, 6);
-			ixEthMiiPhyId[i] = IX_ETH_MII_UNKNOWN_PHY_ID;
-			phyPresent[i] = TRUE;
-		    }
-		} 
-	    }
-	}
-    }
-    return IX_SUCCESS;
-}
-
-/************************************************************
- *
- * Configure the PHY at the specified address
- *
- */
-PUBLIC IX_STATUS
-ixEthMiiPhyConfig(UINT32 phyAddr,
-		  BOOL speed100,
-		  BOOL fullDuplex,
-		  BOOL autonegotiate)
-{
-    UINT16 regval=0;
-
-    /* parameter check */
-    if ((phyAddr < IXP425_ETH_ACC_MII_MAX_ADDR) &&
-	(ixEthMiiPhyId[phyAddr] != IX_ETH_MII_INVALID_PHY_ID))
-    {
-    /*
-     * set the control register
-     */
-	if(autonegotiate)
-	{
-	    regval |= IX_ETH_MII_CR_AUTO_EN | IX_ETH_MII_CR_RESTART;
-	}
-	else
-	{
-	    if(speed100)
-	    {
-		regval |= IX_ETH_MII_CR_100;
-	    }
-	    if(fullDuplex)
-	    {
-		regval |= IX_ETH_MII_CR_FDX;
-	    }
-	} /* end of if-else() */
-	if (ixEthAccMiiWriteRtn(phyAddr, 
-				IX_ETH_MII_CTRL_REG, 
-				regval) == IX_ETH_ACC_SUCCESS)
-	{
-	    return IX_SUCCESS;
-	}
-    } /* end of if(phyAddr) */
-    return IX_FAIL;
-}
-
-/******************************************************************
- *
- *  Enable the PHY Loopback at the specified address
- */
-PUBLIC IX_STATUS
-ixEthMiiPhyLoopbackEnable (UINT32 phyAddr)
-{
-  UINT16 regval ;  
-
-  if ((phyAddr < IXP425_ETH_ACC_MII_MAX_ADDR) && 
-      (IX_ETH_MII_INVALID_PHY_ID != ixEthMiiPhyId[phyAddr]))
-  {
-      /* read/write the control register */
-      if(ixEthAccMiiReadRtn (phyAddr,
-			     IX_ETH_MII_CTRL_REG, 
-			     &regval) 
-	 == IX_ETH_ACC_SUCCESS)
-      {
-	  if(ixEthAccMiiWriteRtn (phyAddr, 
-				  IX_ETH_MII_CTRL_REG, 
-				  regval | IX_ETH_MII_CR_LOOPBACK)
-	     == IX_ETH_ACC_SUCCESS)
-	  {
-	      return IX_SUCCESS;
-	  }
-      }
-  }
-  return IX_FAIL;
-}
-
-/******************************************************************
- *
- *  Disable the PHY Loopback at the specified address
- */
-PUBLIC IX_STATUS
-ixEthMiiPhyLoopbackDisable (UINT32 phyAddr)
-{
-  UINT16 regval ;  
-
-  if ((phyAddr < IXP425_ETH_ACC_MII_MAX_ADDR) && 
-      (IX_ETH_MII_INVALID_PHY_ID != ixEthMiiPhyId[phyAddr]))
-  {
-      /* read/write the control register */
-      if(ixEthAccMiiReadRtn (phyAddr,
-			     IX_ETH_MII_CTRL_REG, 
-			     &regval) 
-	 == IX_ETH_ACC_SUCCESS)
-      {
-	  if(ixEthAccMiiWriteRtn (phyAddr, 
-				  IX_ETH_MII_CTRL_REG, 
-				  regval & (~IX_ETH_MII_CR_LOOPBACK))
-	     == IX_ETH_ACC_SUCCESS)
-	  {
-	      return IX_SUCCESS;
-	  }
-      }
-  }
-  return IX_FAIL;
-}
-
-/******************************************************************
- *
- *  Reset the PHY at the specified address
- */
-PUBLIC IX_STATUS
-ixEthMiiPhyReset(UINT32 phyAddr)
-{
-    UINT32 timeout;
-    UINT16 regval;
-
-    if ((phyAddr < IXP425_ETH_ACC_MII_MAX_ADDR) &&
-	(ixEthMiiPhyId[phyAddr] != IX_ETH_MII_INVALID_PHY_ID))
-    {
-	if ((ixEthMiiPhyId[phyAddr] == IX_ETH_MII_LXT971_PHY_ID)	||
-	    (ixEthMiiPhyId[phyAddr] == IX_ETH_MII_LXT972_PHY_ID)	||
-	    (ixEthMiiPhyId[phyAddr] == IX_ETH_MII_LXT973_PHY_ID)	||
-	    (ixEthMiiPhyId[phyAddr] == IX_ETH_MII_LXT973A3_PHY_ID)	||
-		(ixEthMiiPhyId[phyAddr] == IX_ETH_MII_LXT9785_PHY_ID)
-	    )
-	{
-	    /* use the control register to reset the phy */
-	    ixEthAccMiiWriteRtn(phyAddr, 
-				IX_ETH_MII_CTRL_REG,
-				IX_ETH_MII_CR_RESET);
-	 
-	    /* poll until the reset bit is cleared */
-	    timeout = 0;
-	    do
-	    {
-		ixOsalSleep (IX_ETH_MII_RESET_POLL_MS);
-
-		/* read the control register and check for timeout */
-		ixEthAccMiiReadRtn(phyAddr, 
-				   IX_ETH_MII_CTRL_REG,
-				   &regval);
-		if ((regval & IX_ETH_MII_CR_RESET) == 0)
-		{
-		    /* timeout bit is self-cleared */
-		    break;
-		}
-		timeout += IX_ETH_MII_RESET_POLL_MS;
-	    }
-	    while (timeout < IX_ETH_MII_RESET_DELAY_MS);
-
-	    /* check for timeout */
-	    if (timeout >= IX_ETH_MII_RESET_DELAY_MS)
-	    {
-		ixEthAccMiiWriteRtn(phyAddr, IX_ETH_MII_CTRL_REG,
-				    IX_ETH_MII_CR_NORM_EN);
-		return IX_FAIL;
-	    }
-
-	    return IX_SUCCESS;
-	} /* end of if(ixEthMiiPhyId) */
-	else if (ixEthMiiPhyId[phyAddr] == IX_ETH_MII_KS8995_PHY_ID)
-	{
-	    /* reset bit is reserved, just reset the control register */
-	    ixEthAccMiiWriteRtn(phyAddr, IX_ETH_MII_CTRL_REG,
-				IX_ETH_MII_CR_NORM_EN);
-	    return IX_SUCCESS;
-	}
-	else
-	{
-	    /* unknown PHY, set the control register reset bit,
-	     * wait 2 s. and clear the control register.
-	     */
-	    ixEthAccMiiWriteRtn(phyAddr, IX_ETH_MII_CTRL_REG,
-				IX_ETH_MII_CR_RESET);
-	    
-	    ixOsalSleep (IX_ETH_MII_RESET_DELAY_MS);
-	    
-	    ixEthAccMiiWriteRtn(phyAddr, IX_ETH_MII_CTRL_REG,
-				IX_ETH_MII_CR_NORM_EN);
-	    return IX_SUCCESS;
-	} /* end of if-else(ixEthMiiPhyId) */
-    } /* end of if(phyAddr) */
-    return IX_FAIL;
-}
-
-/*****************************************************************
- *
- *  Link state query functions
- */
-
-PUBLIC IX_STATUS
-ixEthMiiLinkStatus(UINT32 phyAddr,
-           BOOL *linkUp,
-           BOOL *speed100,
-           BOOL *fullDuplex,
-           BOOL *autoneg)
-{
-    UINT16 ctrlRegval, statRegval, regval, regval4, regval5;
-
-    /* check the parameters */
-    if ((linkUp == NULL) || 
-	(speed100 == NULL) || 
-	(fullDuplex == NULL) ||
-	(autoneg == NULL))
-    {
-	return IX_FAIL;
-    }
-
-    *linkUp = FALSE;
-    *speed100 = FALSE;
-    *fullDuplex = FALSE;
-    *autoneg = FALSE;
-
-    if ((phyAddr < IXP425_ETH_ACC_MII_MAX_ADDR) &&
-	(ixEthMiiPhyId[phyAddr] != IX_ETH_MII_INVALID_PHY_ID))
-    {
-	if ((ixEthMiiPhyId[phyAddr] == IX_ETH_MII_LXT971_PHY_ID)	||
-	    (ixEthMiiPhyId[phyAddr] == IX_ETH_MII_LXT972_PHY_ID)	||
-	    (ixEthMiiPhyId[phyAddr] == IX_ETH_MII_LXT9785_PHY_ID)
-		)
-	{
-	    /* --------------------------------------------------*/
-	    /* Retrieve information from PHY specific register   */
-	    /* --------------------------------------------------*/
-	    if (ixEthAccMiiReadRtn(phyAddr, 
-				   IX_ETH_MII_STAT2_REG, 
-				   &regval) != IX_ETH_ACC_SUCCESS)
-	    {
-		return IX_FAIL;
-	    }
-	    *linkUp = ((regval & IX_ETH_MII_SR2_LINK) != 0);
-	    *speed100 = ((regval & IX_ETH_MII_SR2_100) != 0);
-	    *fullDuplex = ((regval & IX_ETH_MII_SR2_FD) != 0);
-	    *autoneg = ((regval & IX_ETH_MII_SR2_AUTO) != 0);
-	    return IX_SUCCESS;
-	} /* end of if(ixEthMiiPhyId) */
-	else
-	{    
-	    /* ----------------------------------------------------*/
-	    /* Retrieve information from status and ctrl registers */
-	    /* ----------------------------------------------------*/
-	    if (ixEthAccMiiReadRtn(phyAddr,  
-				   IX_ETH_MII_CTRL_REG, 
-				   &ctrlRegval) != IX_ETH_ACC_SUCCESS)
-	    {
-		return IX_FAIL;
-	    }
-	    ixEthAccMiiReadRtn(phyAddr,  IX_ETH_MII_STAT_REG, &statRegval);
-	    
-	    *linkUp = ((statRegval & IX_ETH_MII_SR_LINK_STATUS) != 0);
-	    if (*linkUp)
-	    {
-		*autoneg = ((ctrlRegval & IX_ETH_MII_CR_AUTO_EN) != 0) &&
-		    ((statRegval &  IX_ETH_MII_SR_AUTO_SEL) != 0) &&
-		    ((statRegval & IX_ETH_MII_SR_AUTO_NEG) != 0);
-		
-		if (*autoneg)
-		{
-		    /* mask the current stat values with the capabilities */
-		    ixEthAccMiiReadRtn(phyAddr, IX_ETH_MII_AN_ADS_REG, &regval4);
-		    ixEthAccMiiReadRtn(phyAddr, IX_ETH_MII_AN_PRTN_REG, &regval5);
-		    /* merge the flags from the 3 registers */
-		    regval = (statRegval & ((regval4 & regval5) << 6));
-		    /* initialise from status register values */
-		    if ((regval & IX_ETH_MII_SR_TX_FULL_DPX) != 0)
-		    {
-			/* 100 Base X full dplx */
-			*speed100 = TRUE;
-			*fullDuplex = TRUE;
-			return IX_SUCCESS;
-		    }
-		    if ((regval & IX_ETH_MII_SR_TX_HALF_DPX) != 0)
-		    {
-			/* 100 Base X half dplx */
-			*speed100 = TRUE;
-			return IX_SUCCESS;
-		    }
-		    if ((regval & IX_ETH_MII_SR_10T_FULL_DPX) != 0)
-		    {
-			/* 10 mb full dplx */
-			*fullDuplex = TRUE;
-			return IX_SUCCESS;
-		    }
-		    if ((regval & IX_ETH_MII_SR_10T_HALF_DPX) != 0)
-		    {
-			/* 10 mb half dplx */
-			return IX_SUCCESS;
-		    }
-		} /* end of if(autoneg) */
-		else
-		{
-		    /* autonegotiate not complete, return setup parameters */
-		    *speed100 = ((ctrlRegval & IX_ETH_MII_CR_100) != 0);
-		    *fullDuplex = ((ctrlRegval & IX_ETH_MII_CR_FDX) != 0);
-		}
-	    } /* end of if(linkUp) */
-	} /* end of if-else(ixEthMiiPhyId) */
-    } /* end of if(phyAddr) */
-    else
-    {
-	return IX_FAIL;
-    } /* end of if-else(phyAddr) */
-    return IX_SUCCESS;
-}
-
-/*****************************************************************
- *
- *  Link state display functions
- */
-
-PUBLIC IX_STATUS
-ixEthMiiPhyShow (UINT32 phyAddr)
-{
-    BOOL linkUp, speed100, fullDuplex, autoneg;
-    UINT16 cregval;
-    UINT16 sregval;
-    
-
-    ixEthAccMiiReadRtn(phyAddr,  IX_ETH_MII_STAT_REG, &sregval);
-    ixEthAccMiiReadRtn(phyAddr,  IX_ETH_MII_CTRL_REG, &cregval);
-
-    /* get link information */
-    if (ixEthMiiLinkStatus(phyAddr,
-			   &linkUp,
-			   &speed100,
-			   &fullDuplex,
-			   &autoneg) != IX_ETH_ACC_SUCCESS)
-    {
-	printf("PHY Status unknown\n");
-	return IX_FAIL;
-    }
-
-    printf("PHY ID [phyAddr]: %8.8x\n",ixEthMiiPhyId[phyAddr]);
-    printf( " Status reg:  %4.4x\n",sregval);
-    printf( " control reg: %4.4x\n",cregval);
-    /* display link information */
-    printf("PHY Status:\n");
-    printf("    Link is %s\n",
-	   (linkUp ? "Up" : "Down"));
-    if((sregval & IX_ETH_MII_SR_REMOTE_FAULT) != 0)
-    {
-	printf("    Remote fault detected\n");
-    }
-    printf("    Auto Negotiation %s\n",
-	   (autoneg ? "Completed" : "Not Completed"));
-
-    printf("PHY Configuration:\n");
-    printf("    Speed %sMb/s\n",
-	   (speed100 ? "100" : "10"));
-    printf("    %s Duplex\n",
-	   (fullDuplex ? "Full" : "Half"));
-    printf("    Auto Negotiation %s\n",
-	   (autoneg ? "Enabled" : "Disabled"));
-    return IX_SUCCESS;
-}
-
diff --git a/arch/arm/cpu/ixp/npe/IxFeatureCtrl.c b/arch/arm/cpu/ixp/npe/IxFeatureCtrl.c
deleted file mode 100644
index 2e196a1..0000000
--- a/arch/arm/cpu/ixp/npe/IxFeatureCtrl.c
+++ /dev/null
@@ -1,422 +0,0 @@
-/**
- * @file IxFeatureCtrl.c
- *
- * @author Intel Corporation
- * @date 29-Jan-2003
- *
- * @brief Feature Control Public API Implementation
- *
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- * 
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- * 
- * @par
- * -- End of Copyright Notice --
-*/
-
-#include "IxOsal.h"
-#include "IxVersionId.h"
-#include "IxFeatureCtrl.h"
-
-/* Macro to read from the Feature Control Register */
-#define IX_FEATURE_CTRL_READ(result) \
-do { \
-ixFeatureCtrlExpMap(); \
-(result) = IX_OSAL_READ_LONG(ixFeatureCtrlRegister); \
-} while (0)
-
-/* Macro to write to the Feature Control Register */
-#define IX_FEATURE_CTRL_WRITE(value) \
-do { \
-ixFeatureCtrlExpMap(); \
-IX_OSAL_WRITE_LONG(ixFeatureCtrlRegister, (value)); \
-} while (0)
-
-/*
- * This is the offset of the feature register relative to the base of the
- * Expansion Bus Controller MMR.
- */
-#define IX_FEATURE_CTRL_REG_OFFSET (0x00000028)
-
-
-/* Boolean to mark the fact that the EXP_CONFIG address space was mapped */
-PRIVATE BOOL ixFeatureCtrlExpCfgRegionMapped = FALSE;
-
-/* Pointer holding the virtual address of the Feature Control Register */
-PRIVATE VUINT32 *ixFeatureCtrlRegister = NULL;
-
-/* Place holder to store the software configuration */
-PRIVATE BOOL swConfiguration[IX_FEATURECTRL_SWCONFIG_MAX];
-
-/* Flag to control swConfiguration[] is initialized once */
-PRIVATE BOOL swConfigurationFlag = FALSE ;
-
-/* Array containing component mask values */
-#ifdef __ixp42X
-UINT32 componentMask[IX_FEATURECTRL_MAX_COMPONENTS] = {
-    (0x1<<IX_FEATURECTRL_RCOMP),
-    (0x1<<IX_FEATURECTRL_USB),
-    (0x1<<IX_FEATURECTRL_HASH),
-    (0x1<<IX_FEATURECTRL_AES),
-    (0x1<<IX_FEATURECTRL_DES),
-    (0x1<<IX_FEATURECTRL_HDLC),
-    (0x1<<IX_FEATURECTRL_AAL),
-    (0x1<<IX_FEATURECTRL_HSS),
-    (0x1<<IX_FEATURECTRL_UTOPIA),
-    (0x1<<IX_FEATURECTRL_ETH0),
-    (0x1<<IX_FEATURECTRL_ETH1),
-    (0x1<<IX_FEATURECTRL_NPEA),
-    (0x1<<IX_FEATURECTRL_NPEB),
-    (0x1<<IX_FEATURECTRL_NPEC),
-    (0x1<<IX_FEATURECTRL_PCI),
-    IX_FEATURECTRL_COMPONENT_NOT_AVAILABLE,
-    (0x3<<IX_FEATURECTRL_UTOPIA_PHY_LIMIT),
-    (0x1<<IX_FEATURECTRL_UTOPIA_PHY_LIMIT_BIT2),
-    IX_FEATURECTRL_COMPONENT_NOT_AVAILABLE,
-    IX_FEATURECTRL_COMPONENT_NOT_AVAILABLE,
-    IX_FEATURECTRL_COMPONENT_NOT_AVAILABLE,
-    IX_FEATURECTRL_COMPONENT_NOT_AVAILABLE,
-    IX_FEATURECTRL_COMPONENT_NOT_AVAILABLE
-};
-#elif defined (__ixp46X)
-UINT32 componentMask[IX_FEATURECTRL_MAX_COMPONENTS] = {
-    (0x1<<IX_FEATURECTRL_RCOMP),
-    (0x1<<IX_FEATURECTRL_USB),
-    (0x1<<IX_FEATURECTRL_HASH),
-    (0x1<<IX_FEATURECTRL_AES),
-    (0x1<<IX_FEATURECTRL_DES),
-    (0x1<<IX_FEATURECTRL_HDLC),
-    IX_FEATURECTRL_COMPONENT_ALWAYS_AVAILABLE,  /* AAL component is always on */
-    (0x1<<IX_FEATURECTRL_HSS),
-    (0x1<<IX_FEATURECTRL_UTOPIA),
-    (0x1<<IX_FEATURECTRL_ETH0),
-    (0x1<<IX_FEATURECTRL_ETH1),
-    (0x1<<IX_FEATURECTRL_NPEA),
-    (0x1<<IX_FEATURECTRL_NPEB),
-    (0x1<<IX_FEATURECTRL_NPEC),
-    (0x1<<IX_FEATURECTRL_PCI),
-    (0x1<<IX_FEATURECTRL_ECC_TIMESYNC),
-    (0x3<<IX_FEATURECTRL_UTOPIA_PHY_LIMIT),
-    (0x1<<IX_FEATURECTRL_UTOPIA_PHY_LIMIT_BIT2), /* NOT TO BE USED */
-    (0x1<<IX_FEATURECTRL_USB_HOST_CONTROLLER),
-    (0x1<<IX_FEATURECTRL_NPEA_ETH),
-    (0x1<<IX_FEATURECTRL_NPEB_ETH),
-    (0x1<<IX_FEATURECTRL_RSA),
-    (0x3<<IX_FEATURECTRL_XSCALE_MAX_FREQ),
-    (0x1<<IX_FEATURECTRL_XSCALE_MAX_FREQ_BIT2)
-};
-#endif /* __ixp42X */
-
-/**
- * Forward declaration
- */
-PRIVATE
-void ixFeatureCtrlExpMap(void);
-
-PRIVATE 
-void ixFeatureCtrlSwConfigurationInit(void);
-
-/**
- * Function to map EXP_CONFIG space
- */
-PRIVATE
-void ixFeatureCtrlExpMap(void)
-{
-    UINT32 expCfgBaseAddress = 0;
-
-    /* If the EXP Configuration space has already been mapped then
-     * return */
-    if (ixFeatureCtrlExpCfgRegionMapped == TRUE)
-    {
-	return;
-    }
-
-    /* Map (get virtual address) for the EXP_CONFIG space */
-    expCfgBaseAddress = (UINT32)
-	(IX_OSAL_MEM_MAP(IX_OSAL_IXP400_EXP_BUS_REGS_PHYS_BASE,
-			   IX_OSAL_IXP400_EXP_REG_MAP_SIZE));
-
-    /* Assert that the mapping operation succeeded */
-    IX_OSAL_ASSERT(expCfgBaseAddress);
-
-    /* Set the address of the Feature register */
-    ixFeatureCtrlRegister =
-	(VUINT32 *) (expCfgBaseAddress + IX_FEATURE_CTRL_REG_OFFSET);
-
-    /* Mark the fact that the EXP_CONFIG space has already been mapped */
-    ixFeatureCtrlExpCfgRegionMapped = TRUE;
-}
-
-/**
- * Function definition: ixFeatureCtrlSwConfigurationInit
- * This function will only initialize software configuration once.
- */
-PRIVATE void ixFeatureCtrlSwConfigurationInit(void)
-{
-  UINT32 i;
-  if (FALSE == swConfigurationFlag)
-  {
-    for (i=0; i<IX_FEATURECTRL_SWCONFIG_MAX ; i++)
-    {
-        /* By default, all software configuration are enabled */
-        swConfiguration[i]= TRUE ;
-    }
-    /*Make sure this function only initializes swConfiguration[] once*/
-    swConfigurationFlag = TRUE ;
-  }  
-}
-
-/**
- * Function definition: ixFeatureCtrlRead
- */
-IxFeatureCtrlReg 
-ixFeatureCtrlRead (void)
-{
-    IxFeatureCtrlReg result;
-
-#if CPU!=SIMSPARCSOLARIS
-    /* Read the feature control register */
-    IX_FEATURE_CTRL_READ(result);
-    return result;
-#else
-    /* Return an invalid value for VxWorks simulation */
-    result = 0xFFFFFFFF;
-    return result;
-#endif
-}
-
-/**
- * Function definition: ixFeatureCtrlWrite
- */
-void
-ixFeatureCtrlWrite (IxFeatureCtrlReg expUnitReg)
-{
-#if CPU!=SIMSPARCSOLARIS
-    /* Write value to feature control register */
-    IX_FEATURE_CTRL_WRITE(expUnitReg);
-#endif
-}
-
-
-/**
- * Function definition: ixFeatureCtrlHwCapabilityRead
- */
-IxFeatureCtrlReg
-ixFeatureCtrlHwCapabilityRead (void)
-{ 
-  IxFeatureCtrlReg currentReg, hwCapability;
-  
-  /* Capture a copy of feature control register */
-  currentReg = ixFeatureCtrlRead(); 
-
-  /* Try to enable all hardware components. 
-   * Only software disable hardware can be enabled again */
-  ixFeatureCtrlWrite(0);
-  
-  /* Read feature control register to know the hardware capability. */ 
-  hwCapability = ixFeatureCtrlRead();
-     
-  /* Restore initial feature control value */
-  ixFeatureCtrlWrite(currentReg);
-
-  /* return Hardware Capability */
-  return hwCapability;  
-}
-
-
-/**
- * Function definition: ixFeatureCtrlComponentCheck
- */
-IX_STATUS 
-ixFeatureCtrlComponentCheck (IxFeatureCtrlComponentType componentType)
-{
-  IxFeatureCtrlReg expUnitReg; 
-  UINT32 mask = 0;
-
-  /* Lookup mask of component */
-  mask=componentMask[componentType];
-
-  /* Check if mask is available or not */
-  if(IX_FEATURECTRL_COMPONENT_NOT_AVAILABLE == mask)
-  {
-      return IX_FEATURE_CTRL_COMPONENT_DISABLED;
-  }
-
-  if(IX_FEATURECTRL_COMPONENT_ALWAYS_AVAILABLE == mask)
-  {
-      return IX_FEATURE_CTRL_COMPONENT_ENABLED;
-  }
-
-  /* Read feature control register to know current hardware capability. */ 
-  expUnitReg = ixFeatureCtrlRead();
-
-  /* For example: To check for Hashing Coprocessor (bit-2) 
-   *                   expUniteg    = 0x0010
-   *                  ~expUnitReg   = 0x1101 
-   *                  componentType = 0x0100
-   *    ~expUnitReg & componentType = 0x0100 (Not zero)                      
-   */
- 
-  /* 
-   * Inverse the bit value because available component is 0 in value 
-   */
-  expUnitReg = ~expUnitReg ;
-
-  if (expUnitReg & mask)
-  {
-     return (IX_FEATURE_CTRL_COMPONENT_ENABLED);
-  }   
-  else
-  {  
-     return (IX_FEATURE_CTRL_COMPONENT_DISABLED);
-  } 
-}
-
-
-/**
- * Function definition: ixFeatureCtrlProductIdRead
- */
-IxFeatureCtrlProductId
-ixFeatureCtrlProductIdRead ()
-{
-#if CPU!=SIMSPARCSOLARIS
-  IxFeatureCtrlProductId  pdId = 0 ;
-   
-  /* Use ARM instruction to move register0 from coprocessor to ARM register */ 
-    
-#ifndef __wince
-    __asm__("mrc p15, 0, %0, cr0, cr0, 0;" : "=r"(pdId) :);
-#else
-      
-#ifndef IN_KERNEL
-        BOOL  mode;
-#endif
-    extern  IxFeatureCtrlProductId AsmixFeatureCtrlProductIdRead();
-    
-#ifndef IN_KERNEL
-    mode = SetKMode(TRUE);
-#endif
-    pdId = AsmixFeatureCtrlProductIdRead();
-#ifndef IN_KERNEL
-    SetKMode(mode);
-#endif
-
-#endif
-  return (pdId);
-#else
-  /* Return an invalid value for VxWorks simulation */
-  return 0xffffffff;
-#endif
-}
-
-/**
- * Function definition: ixFeatureCtrlDeviceRead
- */
-IxFeatureCtrlDeviceId
-ixFeatureCtrlDeviceRead ()
-{
-  return ((ixFeatureCtrlProductIdRead() >> IX_FEATURE_CTRL_DEVICE_TYPE_OFFSET) 
-             & IX_FEATURE_CTRL_DEVICE_TYPE_MASK);
-} /* End function ixFeatureCtrlDeviceRead */
-
-
-/**
- * Function definition: ixFeatureCtrlSwConfigurationCheck
- */
-IX_STATUS
-ixFeatureCtrlSwConfigurationCheck (IxFeatureCtrlSwConfig swConfigType)
-{
-  if (swConfigType >= IX_FEATURECTRL_SWCONFIG_MAX)  
-  {
-     ixOsalLog(IX_OSAL_LOG_LVL_WARNING, 
-               IX_OSAL_LOG_DEV_STDOUT,
-               "FeatureCtrl: Invalid software configuraiton input.\n",
-               0, 0, 0, 0, 0, 0);  
-
-     return IX_FEATURE_CTRL_SWCONFIG_DISABLED;
-  }
-
-  /* The function will only initialize once. */
-  ixFeatureCtrlSwConfigurationInit();
-  
-  /* Check and return software configuration */
-  return  ((swConfiguration[(UINT32)swConfigType] == TRUE) ? IX_FEATURE_CTRL_SWCONFIG_ENABLED: IX_FEATURE_CTRL_SWCONFIG_DISABLED);
-}
-
-/**
- * Function definition: ixFeatureCtrlSwConfigurationWrite
- */
-void
-ixFeatureCtrlSwConfigurationWrite (IxFeatureCtrlSwConfig swConfigType, BOOL enabled)
-{
-  if (swConfigType >= IX_FEATURECTRL_SWCONFIG_MAX)  
-  {
-     ixOsalLog(IX_OSAL_LOG_LVL_WARNING, 
-               IX_OSAL_LOG_DEV_STDOUT,
-               "FeatureCtrl: Invalid software configuraiton input.\n",
-               0, 0, 0, 0, 0, 0);  
-
-     return;
-  }
-
-  /* The function will only initialize once. */
-  ixFeatureCtrlSwConfigurationInit();
-  
-  /* Write software configuration */
-  swConfiguration[(UINT32)swConfigType]=enabled ;
-}
-
-/**
- * Function definition: ixFeatureCtrlIxp400SwVersionShow
- */
-void
-ixFeatureCtrlIxp400SwVersionShow (void)
-{
-    printf ("\nIXP400 Software Release %s %s\n\n", IX_VERSION_ID, IX_VERSION_INTERNAL_ID);
-
-}
-
-/**
- * Function definition: ixFeatureCtrlSoftwareBuildGet
- */
-IxFeatureCtrlBuildDevice
-ixFeatureCtrlSoftwareBuildGet (void)
-{
-    #ifdef __ixp42X
-    return IX_FEATURE_CTRL_SW_BUILD_IXP42X;
-    #else
-    return IX_FEATURE_CTRL_SW_BUILD_IXP46X;
-    #endif
-}
diff --git a/arch/arm/cpu/ixp/npe/IxNpeDl.c b/arch/arm/cpu/ixp/npe/IxNpeDl.c
deleted file mode 100644
index 3738337..0000000
--- a/arch/arm/cpu/ixp/npe/IxNpeDl.c
+++ /dev/null
@@ -1,940 +0,0 @@
-/**
- * @file IxNpeDl.c
- *
- * @author Intel Corporation
- * @date 08 January 2002
- *
- * @brief This file contains the implementation of the public API for the
- *        IXP425 NPE Downloader component
- *
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
-*/
-
-/*
- * Put the system defined include files required
- */
-
-/*
- * Put the user defined include files required
- */
-#include "IxNpeDl.h"
-#include "IxNpeDlImageMgr_p.h"
-#include "IxNpeDlNpeMgr_p.h"
-#include "IxNpeDlMacros_p.h"
-#include "IxFeatureCtrl.h"
-#include "IxOsal.h"
-/*
- * #defines used in this file
- */
- #define IMAGEID_MAJOR_NUMBER_DEFAULT 0
- #define IMAGEID_MINOR_NUMBER_DEFAULT 0
-
-/*
- * Typedefs whose scope is limited to this file.
- */
-typedef struct
-{
-    BOOL validImage;
-    IxNpeDlImageId imageId;
-} IxNpeDlNpeState;
-
-/* module statistics counters */
-typedef struct
-{
-    UINT32 attemptedDownloads;
-    UINT32 successfulDownloads;
-    UINT32 criticalFailDownloads;
-} IxNpeDlStats;
-
-/*
- * Variable declarations global to this file only.  Externs are followed
- * by static variables.
- */
-static IxNpeDlNpeState ixNpeDlNpeState[IX_NPEDL_NPEID_MAX] =
-{
-    {FALSE, {IX_NPEDL_NPEID_MAX, 0, 0, 0}},
-    {FALSE, {IX_NPEDL_NPEID_MAX, 0, 0, 0}},
-    {FALSE, {IX_NPEDL_NPEID_MAX, 0, 0, 0}}
-};
-
-static IxNpeDlStats ixNpeDlStats;
-
-/*
- * Software guard to prevent NPE from being started multiple times.
- */
-static BOOL ixNpeDlNpeStarted[IX_NPEDL_NPEID_MAX] ={FALSE, FALSE, FALSE} ;
-
-
-/*
- * static function prototypes.
- */
-PRIVATE IX_STATUS
-ixNpeDlNpeInitAndStartInternal (UINT32 *imageLibrary, UINT32 imageId);
-
-/*
- * Function definition: ixNpeDlImageDownload
- */
-PUBLIC IX_STATUS
-ixNpeDlImageDownload (IxNpeDlImageId *imageIdPtr,
-                      BOOL verify)
-{
-    UINT32        imageSize;
-    UINT32       *imageCodePtr  = NULL;
-    IX_STATUS     status;
-    IxNpeDlNpeId  npeId           = imageIdPtr->npeId;
-
-    IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT,
-                     "Entering ixNpeDlImageDownload\n");
-
-    ixNpeDlStats.attemptedDownloads++;
-
-    /* Check input parameters */
-    if ((npeId >= IX_NPEDL_NPEID_MAX) || (npeId < 0))
-    {
-        status = IX_NPEDL_PARAM_ERR;
-        IX_NPEDL_ERROR_REPORT ("ixNpeDlImageDownload - invalid parameter\n");
-    }
-    else
-    {
-        /* Ensure initialisation has been completed */
-        ixNpeDlNpeMgrInit();
-
-	/* If not IXP42X A0 stepping, proceed to check for existence of npe's */
-	if ((IX_FEATURE_CTRL_SILICON_TYPE_A0 !=
-	     (ixFeatureCtrlProductIdRead() & IX_FEATURE_CTRL_SILICON_STEPPING_MASK))
-	    || (IX_FEATURE_CTRL_DEVICE_TYPE_IXP42X != ixFeatureCtrlDeviceRead ()))
-	{
-            if (npeId == IX_NPEDL_NPEID_NPEA)
-            {
-                if (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEA) ==
-                    IX_FEATURE_CTRL_COMPONENT_DISABLED)
-                {
-                    IX_NPEDL_WARNING_REPORT("Warning: the NPE A component you specified does"
-                                            " not exist\n");
-                    return IX_SUCCESS;
-                }
-            } /* end of if(npeId) */
-            else if (npeId == IX_NPEDL_NPEID_NPEB)
-            {
-                if (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEB)==
-                    IX_FEATURE_CTRL_COMPONENT_DISABLED)
-                {
-                    IX_NPEDL_WARNING_REPORT("Warning: the NPE B component you specified"
-                                            " does not exist\n");
-                    return IX_SUCCESS;
-                }
-            } /* end of elseif(npeId) */
-            else if (npeId == IX_NPEDL_NPEID_NPEC)
-            {
-                if (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEC)==
-                    IX_FEATURE_CTRL_COMPONENT_DISABLED)
-                {
-                    IX_NPEDL_WARNING_REPORT("Warning: the NPE C component you specified"
-                                            " does not exist\n");
-                    return IX_SUCCESS;
-                }
-            } /* end of elseif(npeId) */
-        } /* end of if(IX_FEATURE_CTRL_SILICON_TYPE_B0) */ /*End of Silicon Type Check*/
-
-        /* stop and reset the NPE */
-        if (IX_SUCCESS != ixNpeDlNpeStopAndReset (npeId))
-        {
-            IX_NPEDL_ERROR_REPORT ("Failed to stop and reset NPE\n");
-            return IX_FAIL;
-        }
-
-        /* Locate image */
-        status = ixNpeDlImageMgrImageLocate (imageIdPtr, &imageCodePtr,
-                                             &imageSize);
-        if (IX_SUCCESS == status)
-        {
-            /*
-             * If download was successful, store image Id in list of
-             * currently loaded images. If a critical error occured
-             * during download, record that the NPE has an invalid image
-             */
-            status = ixNpeDlNpeMgrImageLoad (npeId, imageCodePtr,
-                                             verify);
-            if (IX_SUCCESS == status)
-            {
-                ixNpeDlNpeState[npeId].imageId = *imageIdPtr;
-                ixNpeDlNpeState[npeId].validImage = TRUE;
-                ixNpeDlStats.successfulDownloads++;
-
-                status =  ixNpeDlNpeExecutionStart (npeId);
-            }
-            else if ((status == IX_NPEDL_CRITICAL_NPE_ERR) ||
-                     (status == IX_NPEDL_CRITICAL_MICROCODE_ERR))
-            {
-                ixNpeDlNpeState[npeId].imageId = *imageIdPtr;
-                ixNpeDlNpeState[npeId].validImage = FALSE;
-                ixNpeDlStats.criticalFailDownloads++;
-            }
-        } /* end of if(IX_SUCCESS) */ /* condition: image located successfully in microcode image */
-    } /* end of if-else(npeId) */ /* condition: parameter checks ok */
-
-    IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT,
-                     "Exiting ixNpeDlImageDownload : status = %d\n", status);
-    return status;
-}
-
-/*
- * Function definition: ixNpeDlAvailableImagesCountGet
- */
-PUBLIC IX_STATUS
-ixNpeDlAvailableImagesCountGet (UINT32 *numImagesPtr)
-{
-    IX_STATUS status;
-
-    IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT,
-                     "Entering ixNpeDlAvailableImagesCountGet\n");
-
-    /* Check input parameters */
-    if (numImagesPtr == NULL)
-    {
-        status = IX_NPEDL_PARAM_ERR;
-        IX_NPEDL_ERROR_REPORT ("ixNpeDlAvailableImagesCountGet - "
-                               "invalid parameter\n");
-    }
-    else
-    {
-        /*
-         * Use ImageMgr module to get no. of images listed in Image Library Header.
-         * If NULL is passed as imageListPtr parameter to following function,
-         * it will only fill number of images into numImagesPtr
-         */
-        status = ixNpeDlImageMgrImageListExtract (NULL, numImagesPtr);
-    } /* end of if-else(numImagesPtr) */
-
-    IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT,
-                     "Exiting ixNpeDlAvailableImagesCountGet : "
-                     "status = %d\n", status);
-    return status;
-}
-
-/*
- * Function definition: ixNpeDlAvailableImagesListGet
- */
-PUBLIC IX_STATUS
-ixNpeDlAvailableImagesListGet (IxNpeDlImageId *imageIdListPtr,
-                               UINT32 *listSizePtr)
-{
-    IX_STATUS status;
-
-    IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT,
-                     "Entering ixNpeDlAvailableImagesListGet\n");
-
-    /* Check input parameters */
-    if ((imageIdListPtr == NULL) || (listSizePtr == NULL))
-    {
-        status = IX_NPEDL_PARAM_ERR;
-        IX_NPEDL_ERROR_REPORT ("ixNpeDlAvailableImagesListGet - "
-                               "invalid parameter\n");
-    }
-    else
-    {
-        /* Call ImageMgr to get list of images listed in Image Library Header */
-        status = ixNpeDlImageMgrImageListExtract (imageIdListPtr,
-                                                  listSizePtr);
-    } /* end of if-else(imageIdListPtr) */
-
-    IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT,
-                     "Exiting ixNpeDlAvailableImagesListGet : status = %d\n",
-                     status);
-    return status;
-}
-
-/*
- * Function definition: ixNpeDlLoadedImageGet
- */
-PUBLIC IX_STATUS
-ixNpeDlLoadedImageGet (IxNpeDlNpeId npeId,
-                       IxNpeDlImageId *imageIdPtr)
-{
-    IX_STATUS status = IX_SUCCESS;
-
-    IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT,
-                     "Entering ixNpeDlLoadedImageGet\n");
-
-    /* Check input parameters */
-    if ((npeId >= IX_NPEDL_NPEID_MAX) || (npeId < 0) || (imageIdPtr == NULL))
-    {
-        status = IX_NPEDL_PARAM_ERR;
-        IX_NPEDL_ERROR_REPORT ("ixNpeDlLoadedImageGet - invalid parameter\n");
-    }
-    else
-    {
-
-         /* If not IXP42X A0 stepping, proceed to check for existence of npe's */
-         if ((IX_FEATURE_CTRL_SILICON_TYPE_A0 !=
-	      (ixFeatureCtrlProductIdRead() & IX_FEATURE_CTRL_SILICON_STEPPING_MASK))
-	     || (IX_FEATURE_CTRL_DEVICE_TYPE_IXP42X != ixFeatureCtrlDeviceRead ()))
-        {
-            if (npeId == IX_NPEDL_NPEID_NPEA &&
-                (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEA) ==
-                 IX_FEATURE_CTRL_COMPONENT_DISABLED))
-            {
-                IX_NPEDL_WARNING_REPORT("Warning: the NPE A component you specified does"
-                                        " not exist\n");
-                return IX_SUCCESS;
-            } /* end of if(npeId) */
-
-            if (npeId == IX_NPEDL_NPEID_NPEB &&
-                (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEB) ==
-                 IX_FEATURE_CTRL_COMPONENT_DISABLED))
-            {
-                IX_NPEDL_WARNING_REPORT("Warning: the NPE B component you specified does"
-                                        " not exist\n");
-                return IX_SUCCESS;
-            } /* end of if(npeId) */
-
-            if (npeId == IX_NPEDL_NPEID_NPEC &&
-                (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEC) ==
-                 IX_FEATURE_CTRL_COMPONENT_DISABLED))
-            {
-                IX_NPEDL_WARNING_REPORT("Warning: the NPE C component you specified does"
-                                        " not exist\n");
-                return IX_SUCCESS;
-            } /* end of if(npeId) */
-        } /* end of if not IXP42x-A0 silicon */
-
-        if (ixNpeDlNpeState[npeId].validImage)
-        {
-            /* use npeId to get imageId from list of currently loaded
-               images */
-            *imageIdPtr = ixNpeDlNpeState[npeId].imageId;
-        }
-        else
-        {
-            status = IX_FAIL;
-        } /* end of if-else(ixNpeDlNpeState) */
-    } /* end of if-else(npeId) */
-
-    IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT,
-                     "Exiting ixNpeDlLoadedImageGet : status = %d\n",
-                     status);
-    return status;
-}
-
-/*
- * Function definition: ixNpeDlLatestImageGet
- */
-PUBLIC IX_STATUS
-ixNpeDlLatestImageGet (
-    IxNpeDlNpeId npeId,
-    IxNpeDlFunctionalityId functionalityId,
-    IxNpeDlImageId *imageIdPtr)
-{
-    IX_STATUS status;
-
-    IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT,
-                     "Entering ixNpeDlLatestImageGet\n");
-
-    /* Check input parameters */
-    if ((npeId >= IX_NPEDL_NPEID_MAX) ||
-        (npeId < 0) ||
-        (imageIdPtr == NULL))
-    {
-        status = IX_NPEDL_PARAM_ERR;
-        IX_NPEDL_ERROR_REPORT ("ixNpeDlLatestImageGet - "
-                               "invalid parameter\n");
-    } /* end of if(npeId) */
-    else
-    {
-
-	/* If not IXP42X A0 stepping, proceed to check for existence of npe's */
-	if ((IX_FEATURE_CTRL_SILICON_TYPE_A0 !=
-	     (ixFeatureCtrlProductIdRead() & IX_FEATURE_CTRL_SILICON_STEPPING_MASK))
-	    || (IX_FEATURE_CTRL_DEVICE_TYPE_IXP42X != ixFeatureCtrlDeviceRead ()))
-        {
-            if (npeId == IX_NPEDL_NPEID_NPEA &&
-                (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEA) ==
-                 IX_FEATURE_CTRL_COMPONENT_DISABLED))
-            {
-                IX_NPEDL_WARNING_REPORT("Warning: the NPE A component you specified does"
-                                        " not exist\n");
-                return IX_SUCCESS;
-            } /* end of if(npeId) */
-
-            if (npeId == IX_NPEDL_NPEID_NPEB &&
-                (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEB) ==
-                 IX_FEATURE_CTRL_COMPONENT_DISABLED))
-            {
-                IX_NPEDL_WARNING_REPORT("Warning: the NPE B component you specified does"
-                                        " not exist\n");
-                return IX_SUCCESS;
-            } /* end of if(npeId) */
-
-            if (npeId == IX_NPEDL_NPEID_NPEC &&
-                (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEC) ==
-                 IX_FEATURE_CTRL_COMPONENT_DISABLED))
-            {
-                IX_NPEDL_WARNING_REPORT("Warning: the NPE C component you specified does"
-                                        " not exist\n");
-                return IX_SUCCESS;
-            } /* end of if(npeId) */
-        } /* end of if not IXP42x-A0 silicon */
-
-        imageIdPtr->npeId = npeId;
-        imageIdPtr->functionalityId = functionalityId;
-        imageIdPtr->major = IMAGEID_MAJOR_NUMBER_DEFAULT;
-        imageIdPtr->minor = IMAGEID_MINOR_NUMBER_DEFAULT;
-        /* Call ImageMgr to get list of images listed in Image Library Header */
-        status = ixNpeDlImageMgrLatestImageExtract(imageIdPtr);
-    } /* end of if-else(npeId) */
-
-    IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT,
-                     "Exiting ixNpeDlLatestImageGet : status = %d\n",
-                     status);
-
-    return status;
-}
-
-/*
- * Function definition: ixNpeDlNpeStopAndReset
- */
-PUBLIC IX_STATUS
-ixNpeDlNpeStopAndReset (IxNpeDlNpeId npeId)
-{
-    IX_STATUS status = IX_SUCCESS;
-
-    IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT,
-                     "Entering ixNpeDlNpeStopAndReset\n");
-
-    /* Ensure initialisation has been completed */
-    ixNpeDlNpeMgrInit();
-
-    /* If not IXP42X A0 stepping, proceed to check for existence of npe's */
-    if ((IX_FEATURE_CTRL_SILICON_TYPE_A0 !=
-	 (ixFeatureCtrlProductIdRead() & IX_FEATURE_CTRL_SILICON_STEPPING_MASK))
-	|| (IX_FEATURE_CTRL_DEVICE_TYPE_IXP42X != ixFeatureCtrlDeviceRead ()))
-    {
-        /*
-         * Check whether NPE is present
-         */
-        if (IX_NPEDL_NPEID_NPEA == npeId)
-        {
-            /* Check whether NPE A is present */
-            if (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEA)==
-                IX_FEATURE_CTRL_COMPONENT_DISABLED)
-            {
-                /* NPE A does not present */
-                IX_NPEDL_WARNING_REPORT ("ixNpeDlNpeStopAndReset - Warning:NPEA does not present.\n");
-                return IX_SUCCESS;
-            }
-        } /* end of if(IX_NPEDL_NPEID_NPEA) */
-        else if (IX_NPEDL_NPEID_NPEB == npeId)
-        {
-            /* Check whether NPE B is present */
-            if (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEB)==
-                IX_FEATURE_CTRL_COMPONENT_DISABLED)
-            {
-                /* NPE B does not present */
-                IX_NPEDL_WARNING_REPORT ("ixNpeDlNpeStopAndReset - Warning:NPEB does not present.\n");
-                return IX_SUCCESS;
-            }
-        } /* end of elseif(IX_NPEDL_NPEID_NPEB) */
-        else if (IX_NPEDL_NPEID_NPEC == npeId)
-        {
-            /* Check whether NPE C is present */
-            if (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEC)==
-                IX_FEATURE_CTRL_COMPONENT_DISABLED)
-            {
-                /* NPE C does not present */
-                IX_NPEDL_WARNING_REPORT ("ixNpeDlNpeStopAndReset - Warning:NPEC does not present.\n");
-                return IX_SUCCESS;
-            }
-        } /* end of elseif(IX_NPEDL_NPEID_NPEC) */
-        else
-        {
-            /* Invalid NPE ID */
-            IX_NPEDL_ERROR_REPORT ("ixNpeDlNpeStopAndReset - invalid Npe ID\n");
-            status = IX_NPEDL_PARAM_ERR;
-        } /* end of if-else(IX_NPEDL_NPEID_NPEC) */
-    } /* end of if not IXP42x-A0 Silicon */
-
-    if (status == IX_SUCCESS)
-    {
-        /* call NpeMgr function to stop the NPE */
-        status = ixNpeDlNpeMgrNpeStop (npeId);
-        if (status == IX_SUCCESS)
-        {
-            /* call NpeMgr function to reset the NPE */
-            status = ixNpeDlNpeMgrNpeReset (npeId);
-        }
-    } /* end of if(status) */
-
-    IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT,
-                     "Exiting ixNpeDlNpeStopAndReset : status = %d\n", status);
-
-    if (IX_SUCCESS == status)
-    {
-        /* Indicate NPE has been stopped */
-        ixNpeDlNpeStarted[npeId] = FALSE ;
-    }
-
-    return status;
-}
-
-/*
- * Function definition: ixNpeDlNpeExecutionStart
- */
-PUBLIC IX_STATUS
-ixNpeDlNpeExecutionStart (IxNpeDlNpeId npeId)
-{
-    IX_STATUS status = IX_SUCCESS;
-
-    IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT,
-                     "Entering ixNpeDlNpeExecutionStart\n");
-
-    /* If not IXP42X A0 stepping, proceed to check for existence of npe's */
-    if ((IX_FEATURE_CTRL_SILICON_TYPE_A0 !=
-	 (ixFeatureCtrlProductIdRead() & IX_FEATURE_CTRL_SILICON_STEPPING_MASK))
-	|| (IX_FEATURE_CTRL_DEVICE_TYPE_IXP42X != ixFeatureCtrlDeviceRead ()))
-    {
-        /*
-         * Check whether NPE is present
-         */
-        if (IX_NPEDL_NPEID_NPEA == npeId)
-        {
-            /* Check whether NPE A is present */
-            if (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEA)==
-                IX_FEATURE_CTRL_COMPONENT_DISABLED)
-            {
-                /* NPE A does not present */
-                IX_NPEDL_WARNING_REPORT ("ixNpeDlNpeExecutionStart - Warning:NPEA does not present.\n");
-                return IX_SUCCESS;
-            }
-        } /* end of if(IX_NPEDL_NPEID_NPEA) */
-        else if (IX_NPEDL_NPEID_NPEB == npeId)
-        {
-            /* Check whether NPE B is present */
-            if (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEB)==
-                IX_FEATURE_CTRL_COMPONENT_DISABLED)
-            {
-                /* NPE B does not present */
-                IX_NPEDL_WARNING_REPORT ("ixNpeDlNpeExecutionStart - Warning:NPEB does not present.\n");
-                return IX_SUCCESS;
-            }
-        } /* end of elseif(IX_NPEDL_NPEID_NPEB) */
-        else if (IX_NPEDL_NPEID_NPEC ==  npeId)
-        {
-            /* Check whether NPE C is present */
-            if (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEC)==
-                IX_FEATURE_CTRL_COMPONENT_DISABLED)
-            {
-                /* NPE C does not present */
-                IX_NPEDL_WARNING_REPORT ("ixNpeDlNpeExecutionStart - Warning:NPEC does not present.\n");
-                return IX_SUCCESS;
-            }
-        } /* end of elseif(IX_NPEDL_NPEID_NPEC) */
-        else
-        {
-            /* Invalid NPE ID */
-            IX_NPEDL_ERROR_REPORT ("ixNpeDlNpeExecutionStart - invalid Npe ID\n");
-            return IX_NPEDL_PARAM_ERR;
-        } /* end of if-else(IX_NPEDL_NPEID_NPEC) */
-    } /* end of if not IXP42x-A0 Silicon */
-
-    if (TRUE == ixNpeDlNpeStarted[npeId])
-    {
-        /* NPE has been started. */
-        return IX_SUCCESS ;
-    }
-
-    /* Ensure initialisation has been completed */
-    ixNpeDlNpeMgrInit();
-
-    /* call NpeMgr function to start the NPE */
-    status = ixNpeDlNpeMgrNpeStart (npeId);
-
-    if (IX_SUCCESS == status)
-    {
-        /* Indicate NPE has started */
-        ixNpeDlNpeStarted[npeId] = TRUE ;
-    }
-
-    IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT,
-                     "Exiting ixNpeDlNpeExecutionStart : status = %d\n",
-                     status);
-
-    return status;
-}
-
-/*
- * Function definition: ixNpeDlNpeExecutionStop
- */
-PUBLIC IX_STATUS
-ixNpeDlNpeExecutionStop (IxNpeDlNpeId npeId)
-{
-    IX_STATUS status = IX_SUCCESS;
-
-    IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT,
-                     "Entering ixNpeDlNpeExecutionStop\n");
-
-    /* Ensure initialisation has been completed */
-    ixNpeDlNpeMgrInit();
-
-    /* If not IXP42X A0 stepping, proceed to check for existence of npe's */
-    if ((IX_FEATURE_CTRL_SILICON_TYPE_A0 !=
-	 (ixFeatureCtrlProductIdRead() & IX_FEATURE_CTRL_SILICON_STEPPING_MASK))
-	|| (IX_FEATURE_CTRL_DEVICE_TYPE_IXP42X != ixFeatureCtrlDeviceRead ()))
-    {
-        /*
-         * Check whether NPE is present
-         */
-        if (IX_NPEDL_NPEID_NPEA == npeId)
-        {
-            /* Check whether NPE A is present */
-            if (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEA)==
-                IX_FEATURE_CTRL_COMPONENT_DISABLED)
-            {
-                /* NPE A does not present */
-                IX_NPEDL_WARNING_REPORT ("ixNpeDlNpeExecutionStop - Warning:NPEA does not present.\n");
-                return IX_SUCCESS;
-            }
-        } /* end of if(IX_NPEDL_NPEID_NPEA) */
-        else if (IX_NPEDL_NPEID_NPEB == npeId)
-        {
-            /* Check whether NPE B is present */
-            if (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEB)==
-                IX_FEATURE_CTRL_COMPONENT_DISABLED)
-            {
-                /* NPE B does not present */
-                IX_NPEDL_WARNING_REPORT ("ixNpeDlNpeExecutionStop - Warning:NPEB does not present.\n");
-                return IX_SUCCESS;
-            }
-        } /* end of elseif(IX_NPEDL_NPEID_NPEB) */
-        else if (IX_NPEDL_NPEID_NPEC == npeId)
-        {
-            /* Check whether NPE C is present */
-            if (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEC)==
-                IX_FEATURE_CTRL_COMPONENT_DISABLED)
-            {
-                /* NPE C does not present */
-                IX_NPEDL_WARNING_REPORT ("ixNpeDlNpeExecutionStop - Warning:NPEC does not present.\n");
-                return IX_SUCCESS;
-            }
-        } /* end of elseif(IX_NPEDL_NPEID_NPEC) */
-        else
-        {
-            /* Invalid NPE ID */
-            IX_NPEDL_ERROR_REPORT ("ixNpeDlNpeExecutionStop - invalid Npe ID\n");
-            status = IX_NPEDL_PARAM_ERR;
-        } /* end of if-else(IX_NPEDL_NPEID_NPEC) */
-    } /* end of if not IXP42X-AO Silicon */
-
-    if (status == IX_SUCCESS)
-    {
-        /* call NpeMgr function to stop the NPE */
-        status = ixNpeDlNpeMgrNpeStop (npeId);
-    }
-
-    IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT,
-                     "Exiting ixNpeDlNpeExecutionStop : status = %d\n",
-                     status);
-
-    if (IX_SUCCESS == status)
-    {
-        /* Indicate NPE has been stopped */
-        ixNpeDlNpeStarted[npeId] = FALSE ;
-    }
-
-    return status;
-}
-
-/*
- * Function definition: ixNpeDlUnload
- */
-PUBLIC IX_STATUS
-ixNpeDlUnload (void)
-{
-    IX_STATUS status;
-
-    IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT,
-                     "Entering ixNpeDlUnload\n");
-
-    status = ixNpeDlNpeMgrUninit();
-
-    IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT,
-                     "Exiting ixNpeDlUnload : status = %d\n",
-                     status);
-    return status;
-}
-
-/*
- * Function definition: ixNpeDlStatsShow
- */
-PUBLIC void
-ixNpeDlStatsShow (void)
-{
-    ixOsalLog (IX_OSAL_LOG_LVL_USER,
-               IX_OSAL_LOG_DEV_STDOUT,
-               "\nixNpeDlStatsShow:\n"
-               "\tDownloads Attempted by user: %u\n"
-               "\tSuccessful Downloads: %u\n"
-               "\tFailed Downloads (due to Critical Error): %u\n\n",
-               ixNpeDlStats.attemptedDownloads,
-               ixNpeDlStats.successfulDownloads,
-               ixNpeDlStats.criticalFailDownloads,
-               0,0,0);
-
-    ixNpeDlImageMgrStatsShow ();
-    ixNpeDlNpeMgrStatsShow ();
-}
-
-/*
- * Function definition: ixNpeDlStatsReset
- */
-PUBLIC void
-ixNpeDlStatsReset (void)
-{
-    ixNpeDlStats.attemptedDownloads = 0;
-    ixNpeDlStats.successfulDownloads = 0;
-    ixNpeDlStats.criticalFailDownloads = 0;
-
-    ixNpeDlImageMgrStatsReset ();
-    ixNpeDlNpeMgrStatsReset ();
-}
-
-/*
- * Function definition: ixNpeDlNpeInitAndStartInternal
- */
-PRIVATE IX_STATUS
-ixNpeDlNpeInitAndStartInternal (UINT32 *imageLibrary,
-                                UINT32 imageId)
-{
-    UINT32        imageSize;
-    UINT32       *imageCodePtr  = NULL;
-    IX_STATUS     status;
-    IxNpeDlNpeId  npeId = IX_NPEDL_NPEID_FROM_IMAGEID_GET(imageId);
-    IxFeatureCtrlDeviceId deviceId = IX_NPEDL_DEVICEID_FROM_IMAGEID_GET(imageId);
-
-    IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT,
-                     "Entering ixNpeDlNpeInitAndStartInternal\n");
-
-    ixNpeDlStats.attemptedDownloads++;
-
-    /* Check input parameter device correctness */
-    if ((deviceId >= IX_FEATURE_CTRL_DEVICE_TYPE_MAX) ||
-        (deviceId < IX_FEATURE_CTRL_DEVICE_TYPE_IXP42X))
-    {
-        status = IX_NPEDL_PARAM_ERR;
-        IX_NPEDL_ERROR_REPORT ("ixNpeDlNpeInitAndStartInternal - "
-                               "invalid parameter\n");
-    } /* End valid device id checking */
-
-    /* Check input parameters */
-    else if ((npeId >= IX_NPEDL_NPEID_MAX) || (npeId < 0))
-    {
-        status = IX_NPEDL_PARAM_ERR;
-        IX_NPEDL_ERROR_REPORT ("ixNpeDlNpeInitAndStartInternal - "
-                               "invalid parameter\n");
-    }
-
-    else
-    {
-        /* Ensure initialisation has been completed */
-        ixNpeDlNpeMgrInit();
-
-        /* Checking if image being loaded is meant for device that is running.
-         * Image is forward compatible. i.e Image built for IXP42X should run
-         * on IXP46X but not vice versa.*/
-        if (deviceId > (ixFeatureCtrlDeviceRead() & IX_FEATURE_CTRL_DEVICE_TYPE_MASK))
-        {
-            IX_NPEDL_ERROR_REPORT ("ixNpeDlNpeInitAndStartInternal - "
-                                   "Device type mismatch. NPE Image not "
-                                   "meant for device in use \n");
-            return IX_NPEDL_DEVICE_ERR;
-        }/* if statement - matching image device and current device */
-
-	/* If not IXP42X A0 stepping, proceed to check for existence of npe's */
-	if ((IX_FEATURE_CTRL_SILICON_TYPE_A0 !=
-	     (ixFeatureCtrlProductIdRead() & IX_FEATURE_CTRL_SILICON_STEPPING_MASK))
-	    || (IX_FEATURE_CTRL_DEVICE_TYPE_IXP42X != ixFeatureCtrlDeviceRead ()))
-        {
-            if (npeId == IX_NPEDL_NPEID_NPEA)
-            {
-                if (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEA) ==
-                    IX_FEATURE_CTRL_COMPONENT_DISABLED)
-                {
-                    IX_NPEDL_WARNING_REPORT("Warning: the NPE A component you specified does"
-                                            " not exist\n");
-                    return IX_SUCCESS;
-                }
-            } /* end of if(npeId) */
-            else if (npeId == IX_NPEDL_NPEID_NPEB)
-            {
-                if (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEB)==
-                    IX_FEATURE_CTRL_COMPONENT_DISABLED)
-                {
-                    IX_NPEDL_WARNING_REPORT("Warning: the NPE B component you specified"
-                                            " does not exist\n");
-                    return IX_SUCCESS;
-                }
-            } /* end of elseif(npeId) */
-            else if (npeId == IX_NPEDL_NPEID_NPEC)
-            {
-                if (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEC)==
-                    IX_FEATURE_CTRL_COMPONENT_DISABLED)
-                {
-                    IX_NPEDL_WARNING_REPORT("Warning: the NPE C component you specified"
-                                            " does not exist\n");
-                    return IX_SUCCESS;
-                }
-            } /* end of elseif(npeId) */
-        } /* end of if not IXP42X-A0 Silicon */
-
-        /* stop and reset the NPE */
-        status = ixNpeDlNpeStopAndReset (npeId);
-        if (IX_SUCCESS != status)
-        {
-            IX_NPEDL_ERROR_REPORT ("Failed to stop and reset NPE\n");
-            return status;
-        }
-
-        /* Locate image */
-        status = ixNpeDlImageMgrImageFind (imageLibrary, imageId,
-                                           &imageCodePtr, &imageSize);
-        if (IX_SUCCESS == status)
-        {
-            /*
-             * If download was successful, store image Id in list of
-             * currently loaded images. If a critical error occured
-             * during download, record that the NPE has an invalid image
-             */
-            status = ixNpeDlNpeMgrImageLoad (npeId, imageCodePtr, TRUE);
-            if (IX_SUCCESS == status)
-            {
-                ixNpeDlNpeState[npeId].validImage = TRUE;
-                ixNpeDlStats.successfulDownloads++;
-
-                status = ixNpeDlNpeExecutionStart (npeId);
-            }
-            else if ((status == IX_NPEDL_CRITICAL_NPE_ERR) ||
-                     (status == IX_NPEDL_CRITICAL_MICROCODE_ERR))
-            {
-                ixNpeDlNpeState[npeId].validImage = FALSE;
-                ixNpeDlStats.criticalFailDownloads++;
-            }
-
-            /* NOTE - The following section of code is here to support
-             * a deprecated function ixNpeDlLoadedImageGet().  When that
-             * function is removed from the API, this code should be revised.
-             */
-            ixNpeDlNpeState[npeId].imageId.npeId = npeId;
-            ixNpeDlNpeState[npeId].imageId.functionalityId =
-                IX_NPEDL_FUNCTIONID_FROM_IMAGEID_GET(imageId);
-            ixNpeDlNpeState[npeId].imageId.major =
-                IX_NPEDL_MAJOR_FROM_IMAGEID_GET(imageId);
-            ixNpeDlNpeState[npeId].imageId.minor =
-                IX_NPEDL_MINOR_FROM_IMAGEID_GET(imageId);
-        } /* end of if(IX_SUCCESS) */ /* condition: image located successfully in microcode image */
-    } /* end of if-else(npeId-deviceId) */ /* condition: parameter checks ok */
-
-    IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT,
-                     "Exiting ixNpeDlNpeInitAndStartInternal : "
-                     "status = %d\n", status);
-    return status;
-}
-
-/*
- * Function definition: ixNpeDlCustomImageNpeInitAndStart
- */
-PUBLIC IX_STATUS
-ixNpeDlCustomImageNpeInitAndStart (UINT32 *imageLibrary,
-                                   UINT32 imageId)
-{
-    IX_STATUS status;
-
-    if (imageLibrary == NULL)
-    {
-        status = IX_NPEDL_PARAM_ERR;
-        IX_NPEDL_ERROR_REPORT ("ixNpeDlCustomImageNpeInitAndStart "
-                               "- invalid parameter\n");
-    }
-    else
-    {
-        status = ixNpeDlNpeInitAndStartInternal (imageLibrary, imageId);
-    } /* end of if-else(imageLibrary) */
-
-    return status;
-}
-
-/*
- * Function definition: ixNpeDlNpeInitAndStart
- */
-PUBLIC IX_STATUS
-ixNpeDlNpeInitAndStart (UINT32 imageId)
-{
-    return ixNpeDlNpeInitAndStartInternal (NULL, imageId);
-}
-
-/*
- * Function definition: ixNpeDlLoadedImageFunctionalityGet
- */
-PUBLIC IX_STATUS
-ixNpeDlLoadedImageFunctionalityGet (IxNpeDlNpeId npeId,
-                                    UINT8 *functionalityId)
-{
-    /* Check input parameters */
-    if ((npeId >= IX_NPEDL_NPEID_MAX) || (npeId < 0))
-    {
-        IX_NPEDL_ERROR_REPORT ("ixNpeDlLoadedImageFunctionalityGet "
-                               "- invalid parameter\n");
-        return IX_NPEDL_PARAM_ERR;
-    }
-    if (functionalityId == NULL)
-    {
-        IX_NPEDL_ERROR_REPORT ("ixNpeDlLoadedImageFunctionalityGet "
-                               "- invalid parameter\n");
-        return IX_NPEDL_PARAM_ERR;
-    }
-
-    if (ixNpeDlNpeState[npeId].validImage)
-    {
-        *functionalityId = ixNpeDlNpeState[npeId].imageId.functionalityId;
-        return IX_SUCCESS;
-    }
-    else
-    {
-        return IX_FAIL;
-    }
-}
diff --git a/arch/arm/cpu/ixp/npe/IxNpeDlImageMgr.c b/arch/arm/cpu/ixp/npe/IxNpeDlImageMgr.c
deleted file mode 100644
index 9bcdc9c..0000000
--- a/arch/arm/cpu/ixp/npe/IxNpeDlImageMgr.c
+++ /dev/null
@@ -1,687 +0,0 @@
-/**
- * @file IxNpeDlImageMgr.c
- *
- * @author Intel Corporation
- * @date 09 January 2002
- *
- * @brief This file contains the implementation of the private API for the 
- *        IXP425 NPE Downloader ImageMgr module
- *
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- * 
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- * 
- * @par
- * -- End of Copyright Notice --
-*/
-
-
-/*
- * Put the system defined include files required.
- */
-#include "IxOsal.h"
-
-/*
- * Put the user defined include files required.
- */
-#include "IxNpeDlImageMgr_p.h"
-#include "IxNpeDlMacros_p.h"
-
-/*
- * define the flag which toggles the firmare inclusion
- */
-#define IX_NPE_MICROCODE_FIRMWARE_INCLUDED 1
-#include "IxNpeMicrocode.h"
-
-/*
- * Indicates the start of an NPE Image, in new NPE Image Library format.
- * 2 consecutive occurances indicates the end of the NPE Image Library
- */
-#define NPE_IMAGE_MARKER 0xfeedf00d
-
-/*
- * Typedefs whose scope is limited to this file.
- */
-
-/*
- * FOR BACKWARD-COMPATIBILITY WITH OLD NPE IMAGE LIBRARY FORMAT
- * TO BE DEPRECATED IN A FUTURE RELEASE
- */
-typedef struct
-{
-    UINT32 size;
-    UINT32 offset;
-    UINT32 id;
-} IxNpeDlImageMgrImageEntry;
-
-/*
- * FOR BACKWARD-COMPATIBILITY WITH OLD NPE IMAGE LIBRARY FORMAT
- * TO BE DEPRECATED IN A FUTURE RELEASE
- */
-typedef union
-{
-    IxNpeDlImageMgrImageEntry image;
-    UINT32 eohMarker;
-} IxNpeDlImageMgrHeaderEntry;
-
-/*
- * FOR BACKWARD-COMPATIBILITY WITH OLD NPE IMAGE LIBRARY FORMAT
- * TO BE DEPRECATED IN A FUTURE RELEASE
- */
-typedef struct
-{
-    UINT32 signature;
-    /* 1st entry in the header (there may be more than one) */
-    IxNpeDlImageMgrHeaderEntry entry[1];
-} IxNpeDlImageMgrImageLibraryHeader;
-
-
-/*
- * NPE Image Header definition, used in new NPE Image Library format
- */
-typedef struct
-{
-    UINT32 marker;
-    UINT32 id;
-    UINT32 size;
-} IxNpeDlImageMgrImageHeader;
-
-/* module statistics counters */
-typedef struct
-{
-    UINT32 invalidSignature;
-    UINT32 imageIdListOverflow;
-    UINT32 imageIdNotFound;
-} IxNpeDlImageMgrStats;
-
-
-/*
- * Variable declarations global to this file only.  Externs are followed by
- * static variables.
- */
-static IxNpeDlImageMgrStats ixNpeDlImageMgrStats;
-
-static UINT32* getIxNpeMicroCodeImageLibrary(void)
-{
-	char *s;
-
-	if ((s = getenv("npe_ucode")) != NULL)
-		return (UINT32*) simple_strtoul(s, NULL, 16);
-	else
-		return NULL;
-}
-
-/*
- * static function prototypes.
- */
-PRIVATE BOOL
-ixNpeDlImageMgrSignatureCheck (UINT32 *microCodeImageLibrary);
-
-PRIVATE void  
-ixNpeDlImageMgrImageIdFormat (UINT32 rawImageId, IxNpeDlImageId *imageId);
-
-PRIVATE BOOL
-ixNpeDlImageMgrImageIdCompare (IxNpeDlImageId *imageIdA, 
-				 IxNpeDlImageId *imageIdB);
-				 
-PRIVATE BOOL
-ixNpeDlImageMgrNpeFunctionIdCompare (IxNpeDlImageId *imageIdA,
-				       IxNpeDlImageId *imageIdB);
-
-#if 0
-PRIVATE IX_STATUS
-ixNpeDlImageMgrImageFind_legacy (UINT32 *imageLibrary,
-                                 UINT32 imageId,
-                                 UINT32 **imagePtr,
-                                 UINT32 *imageSize);
-
-/*
- * Function definition: ixNpeDlImageMgrMicrocodeImageLibraryOverride
- *
- * FOR BACKWARD-COMPATIBILITY WITH OLD NPE IMAGE LIBRARY FORMAT
- * AND/OR LEGACY API FUNCTIONS. TO BE DEPRECATED IN A FUTURE RELEASE
- */
-IX_STATUS
-ixNpeDlImageMgrMicrocodeImageLibraryOverride (
-    UINT32 *clientImageLibrary)
-{
-    IX_STATUS status = IX_SUCCESS;
-
-    IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT, 
-		     "Entering ixNpeDlImageMgrMicrocodeImageLibraryOverride\n");
-
-    if (ixNpeDlImageMgrSignatureCheck (clientImageLibrary))
-    {
-	IxNpeMicroCodeImageLibrary = clientImageLibrary;
-    }
-    else
-    {
-	IX_NPEDL_ERROR_REPORT ("ixNpeDlImageMgrMicrocodeImageLibraryOverride: "
-			       "Client-supplied image has invalid signature\n");
-	status = IX_FAIL;
-    }
-
-    IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT, 
-		     "Exiting ixNpeDlImageMgrMicrocodeImageLibraryOverride: status = %d\n",
-		     status);
-    return status;
-}
-#endif
-
-/*
- * Function definition: ixNpeDlImageMgrImageListExtract
- *
- * FOR BACKWARD-COMPATIBILITY WITH OLD NPE IMAGE LIBRARY FORMAT
- * AND/OR LEGACY API FUNCTIONS. TO BE DEPRECATED IN A FUTURE RELEASE
- */
-IX_STATUS
-ixNpeDlImageMgrImageListExtract (
-    IxNpeDlImageId *imageListPtr,
-    UINT32 *numImages)
-{
-    UINT32 rawImageId;
-    IxNpeDlImageId formattedImageId;
-    IX_STATUS status = IX_SUCCESS;
-    UINT32 imageCount = 0;
-    IxNpeDlImageMgrImageLibraryHeader *header;
-
-    IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT, 
-		     "Entering ixNpeDlImageMgrImageListExtract\n");
-
-    header = (IxNpeDlImageMgrImageLibraryHeader *) getIxNpeMicroCodeImageLibrary();
-
-    if (ixNpeDlImageMgrSignatureCheck (getIxNpeMicroCodeImageLibrary()))
-    {
-	/* for each image entry in the image header ... */
-	while (header->entry[imageCount].eohMarker !=
-	       IX_NPEDL_IMAGEMGR_END_OF_HEADER)
-	{
-	    /*
-	     * if the image list container from calling function has capacity,
-	     * add the image id to the list 
-	     */
-	    if ((imageListPtr != NULL) && (imageCount < *numImages))
-	    {
-		rawImageId = header->entry[imageCount].image.id;
-	        ixNpeDlImageMgrImageIdFormat (rawImageId, &formattedImageId);
-		imageListPtr[imageCount] = formattedImageId;
-	    }
-	    /* imageCount reflects no. of image entries in image library header */
-	    imageCount++;  
-	}
-	
-	/*
-	 * if image list container from calling function was too small to
-	 * contain all image ids in the header, set return status to FAIL
-	 */
-	if ((imageListPtr != NULL) && (imageCount > *numImages))
-	{
-	    status = IX_FAIL;
-	    IX_NPEDL_ERROR_REPORT ("ixNpeDlImageMgrImageListExtract: "
-				   "number of Ids found exceeds list capacity\n");
-	    ixNpeDlImageMgrStats.imageIdListOverflow++;
-	}
-	/* return number of image ids found in image library header */
-	*numImages = imageCount;  
-    }
-    else
-    {
-	status = IX_FAIL;
-	IX_NPEDL_ERROR_REPORT ("ixNpeDlImageMgrImageListExtract: "
-			       "invalid signature in image\n");
-    }
-    
-    IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT, 
-		     "Exiting ixNpeDlImageMgrImageListExtract: status = %d\n",
-		     status);
-    return status;
-}
-
-
-/*
- * Function definition: ixNpeDlImageMgrImageLocate
- *
- * FOR BACKWARD-COMPATIBILITY WITH OLD NPE IMAGE LIBRARY FORMAT
- * AND/OR LEGACY API FUNCTIONS. TO BE DEPRECATED IN A FUTURE RELEASE
- */
-IX_STATUS
-ixNpeDlImageMgrImageLocate (
-    IxNpeDlImageId *imageId,
-    UINT32 **imagePtr,
-    UINT32 *imageSize)
-{
-    UINT32 imageOffset;
-    UINT32 rawImageId;
-    IxNpeDlImageId formattedImageId;
-    /* used to index image entries in image library header */
-    UINT32 imageCount = 0;   
-    IX_STATUS status = IX_FAIL;
-    IxNpeDlImageMgrImageLibraryHeader *header;
-
-    IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT,
-		     "Entering ixNpeDlImageMgrImageLocate\n");
-
-    header = (IxNpeDlImageMgrImageLibraryHeader *) getIxNpeMicroCodeImageLibrary();
-
-    if (ixNpeDlImageMgrSignatureCheck (getIxNpeMicroCodeImageLibrary()))
-    {
-	/* for each image entry in the image library header ... */
-	while (header->entry[imageCount].eohMarker !=
-	       IX_NPEDL_IMAGEMGR_END_OF_HEADER)
-	{
-	    rawImageId = header->entry[imageCount].image.id;
-	    ixNpeDlImageMgrImageIdFormat (rawImageId, &formattedImageId);
-	    /* if a match for imageId is found in the image library header... */
-	    if (ixNpeDlImageMgrImageIdCompare (imageId, &formattedImageId))
-	    {
-		/*
-		 * get pointer to the image in the image library using offset from
-		 * 1st word in image library
-		 */
-		UINT32 *tmp=getIxNpeMicroCodeImageLibrary();
-		imageOffset = header->entry[imageCount].image.offset;
-		*imagePtr = &tmp[imageOffset];
-		/* get the image size */
-		*imageSize = header->entry[imageCount].image.size;
-		status = IX_SUCCESS;
-		break;
-	    }
-	    imageCount++;
-	}
-	if (status != IX_SUCCESS)
-	{
-	    IX_NPEDL_ERROR_REPORT ("ixNpeDlImageMgrImageLocate: "
-				   "imageId not found in image library header\n");
-	    ixNpeDlImageMgrStats.imageIdNotFound++;
-	}
-    }
-    else
-    {
-	IX_NPEDL_ERROR_REPORT ("ixNpeDlImageMgrImageLocate: "
-			       "invalid signature in image library\n");
-    }
-
-    IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT,
-		     "Exiting ixNpeDlImageMgrImageLocate: status = %d\n", status);
-    return status;
-}
-
-/*
- * Function definition: ixNpeDlImageMgrLatestImageExtract
- *
- * FOR BACKWARD-COMPATIBILITY WITH OLD NPE IMAGE LIBRARY FORMAT
- * AND/OR LEGACY API FUNCTIONS. TO BE DEPRECATED IN A FUTURE RELEASE
- */
-IX_STATUS
-ixNpeDlImageMgrLatestImageExtract (IxNpeDlImageId *imageId)
-{
-    UINT32 imageCount = 0; 
-    UINT32 rawImageId;
-    IxNpeDlImageId formattedImageId;
-    IX_STATUS status = IX_FAIL;
-    IxNpeDlImageMgrImageLibraryHeader *header;
-    
-    
-    IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT,
-		     "Entering ixNpeDlImageMgrLatestImageExtract\n");
-		     
-    header = (IxNpeDlImageMgrImageLibraryHeader *) getIxNpeMicroCodeImageLibrary();
-    
-    if (ixNpeDlImageMgrSignatureCheck (getIxNpeMicroCodeImageLibrary()))
-    {
-	/* for each image entry in the image library header ... */
-	while (header->entry[imageCount].eohMarker !=
-	       IX_NPEDL_IMAGEMGR_END_OF_HEADER)
-	{
-	    rawImageId = header->entry[imageCount].image.id;
-	    ixNpeDlImageMgrImageIdFormat (rawImageId, &formattedImageId);
-	    /* 
-	     * if a match for the npe Id and functionality Id of the imageId is
-	     *  found in the image library header... 
-	     */
-            if(ixNpeDlImageMgrNpeFunctionIdCompare(imageId, &formattedImageId))
-            {
-                if(imageId->major <= formattedImageId.major)
-                {
-                    if(imageId->minor < formattedImageId.minor)
-                    {
-                        imageId->minor = formattedImageId.minor;
-                    }
-                    imageId->major = formattedImageId.major;
-                }
-                status = IX_SUCCESS;
-            }
-            imageCount++;
-	}
-	if (status != IX_SUCCESS)
-	{
-	    IX_NPEDL_ERROR_REPORT ("ixNpeDlImageMgrLatestImageExtract: "
-				   "imageId not found in image library header\n");
-	    ixNpeDlImageMgrStats.imageIdNotFound++;
-	}
-    }
-    else
-    {
-	IX_NPEDL_ERROR_REPORT ("ixNpeDlImageMgrLatestImageGet: "
-			       "invalid signature in image library\n");
-    }
-
-    IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT,
-		     "Exiting ixNpeDlImageMgrLatestImageGet: status = %d\n", status);
-    return status;
-}
-
-/*
- * Function definition: ixNpeDlImageMgrSignatureCheck
- *
- * FOR BACKWARD-COMPATIBILITY WITH OLD NPE IMAGE LIBRARY FORMAT
- * AND/OR LEGACY API FUNCTIONS. TO BE DEPRECATED IN A FUTURE RELEASE
- */
-PRIVATE BOOL
-ixNpeDlImageMgrSignatureCheck (UINT32 *microCodeImageLibrary)
-{
-    IxNpeDlImageMgrImageLibraryHeader *header =
-	(IxNpeDlImageMgrImageLibraryHeader *) microCodeImageLibrary;
-    BOOL result = TRUE;
-
-    if (!header || header->signature != IX_NPEDL_IMAGEMGR_SIGNATURE)
-    {
-	result = FALSE;
-	ixNpeDlImageMgrStats.invalidSignature++;
-    }
-
-    return result;
-}
-
-
-/*
- * Function definition: ixNpeDlImageMgrImageIdFormat
- *
- * FOR BACKWARD-COMPATIBILITY WITH OLD NPE IMAGE LIBRARY FORMAT
- * AND/OR LEGACY API FUNCTIONS. TO BE DEPRECATED IN A FUTURE RELEASE
- */
-PRIVATE void
-ixNpeDlImageMgrImageIdFormat (
-    UINT32 rawImageId, 
-    IxNpeDlImageId *imageId)
-{  
-    imageId->npeId = (rawImageId >>
-				IX_NPEDL_IMAGEID_NPEID_OFFSET) &
-	IX_NPEDL_NPEIMAGE_FIELD_MASK;
-    imageId->functionalityId = (rawImageId >> 
-				  IX_NPEDL_IMAGEID_FUNCTIONID_OFFSET) &
-	IX_NPEDL_NPEIMAGE_FIELD_MASK;
-    imageId->major = (rawImageId >>
-				IX_NPEDL_IMAGEID_MAJOR_OFFSET) &
-	IX_NPEDL_NPEIMAGE_FIELD_MASK;
-    imageId->minor = (rawImageId >>
-				IX_NPEDL_IMAGEID_MINOR_OFFSET) &
-	IX_NPEDL_NPEIMAGE_FIELD_MASK;
-
-}
-
-
-/*
- * Function definition: ixNpeDlImageMgrImageIdCompare
- *
- * FOR BACKWARD-COMPATIBILITY WITH OLD NPE IMAGE LIBRARY FORMAT
- * AND/OR LEGACY API FUNCTIONS. TO BE DEPRECATED IN A FUTURE RELEASE
- */
-PRIVATE BOOL
-ixNpeDlImageMgrImageIdCompare (
-    IxNpeDlImageId *imageIdA,
-    IxNpeDlImageId *imageIdB)
-{
-    if ((imageIdA->npeId   == imageIdB->npeId)   &&
-	(imageIdA->functionalityId == imageIdB->functionalityId) &&
-	(imageIdA->major   == imageIdB->major)   &&
-	(imageIdA->minor   == imageIdB->minor))
-    {
-	return TRUE;
-    }
-    else
-    {
-	return FALSE;
-    }
-}
-
-/*
- * Function definition: ixNpeDlImageMgrNpeFunctionIdCompare
- *
- * FOR BACKWARD-COMPATIBILITY WITH OLD NPE IMAGE LIBRARY FORMAT
- * AND/OR LEGACY API FUNCTIONS. TO BE DEPRECATED IN A FUTURE RELEASE
- */
-PRIVATE BOOL
-ixNpeDlImageMgrNpeFunctionIdCompare (
-    IxNpeDlImageId *imageIdA,
-    IxNpeDlImageId *imageIdB)
-{
-    if ((imageIdA->npeId   == imageIdB->npeId)   &&
-	(imageIdA->functionalityId == imageIdB->functionalityId))
-    {
-	return TRUE;
-    }
-    else
-    {
-	return FALSE;
-    }
-}
-
-
-/*
- * Function definition: ixNpeDlImageMgrStatsShow
- */
-void
-ixNpeDlImageMgrStatsShow (void)
-{
-    ixOsalLog (IX_OSAL_LOG_LVL_USER,
-               IX_OSAL_LOG_DEV_STDOUT,
-               "\nixNpeDlImageMgrStatsShow:\n"
-               "\tInvalid Image Signatures: %u\n"
-               "\tImage Id List capacity too small: %u\n"
-               "\tImage Id not found: %u\n\n",
-               ixNpeDlImageMgrStats.invalidSignature,
-               ixNpeDlImageMgrStats.imageIdListOverflow,
-               ixNpeDlImageMgrStats.imageIdNotFound,
-               0,0,0);
-}
-
-
-/*
- * Function definition: ixNpeDlImageMgrStatsReset
- */
-void
-ixNpeDlImageMgrStatsReset (void)
-{
-    ixNpeDlImageMgrStats.invalidSignature = 0;
-    ixNpeDlImageMgrStats.imageIdListOverflow = 0;
-    ixNpeDlImageMgrStats.imageIdNotFound = 0;
-}
-
-
-#if 0
-/*
- * Function definition: ixNpeDlImageMgrImageFind_legacy
- *
- * FOR BACKWARD-COMPATIBILITY WITH OLD NPE IMAGE LIBRARY FORMAT
- * AND/OR LEGACY API FUNCTIONS. TO BE DEPRECATED IN A FUTURE RELEASE
- */
-PRIVATE IX_STATUS
-ixNpeDlImageMgrImageFind_legacy (
-    UINT32 *imageLibrary,
-    UINT32 imageId,
-    UINT32 **imagePtr,
-    UINT32 *imageSize)
-{
-    UINT32 imageOffset;
-    /* used to index image entries in image library header */
-    UINT32 imageCount = 0;   
-    IX_STATUS status = IX_FAIL;
-    IxNpeDlImageMgrImageLibraryHeader *header;
-    BOOL imageFound = FALSE;
-
-    IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT,
-		     "Entering ixNpeDlImageMgrImageFind\n");
-
-
-    /* If user didn't specify a library to use, use the default
-     * one from IxNpeMicrocode.h
-     */
-    if (imageLibrary == NULL)
-    {
-	imageLibrary = IxNpeMicroCodeImageLibrary;
-    }
-    
-    if (ixNpeDlImageMgrSignatureCheck (imageLibrary))
-    {
-	header = (IxNpeDlImageMgrImageLibraryHeader *) imageLibrary;
-    
-	/* for each image entry in the image library header ... */
-	while ((header->entry[imageCount].eohMarker !=
-               IX_NPEDL_IMAGEMGR_END_OF_HEADER) && !(imageFound))
-	{
-	    /* if a match for imageId is found in the image library header... */
-	    if (imageId == header->entry[imageCount].image.id)
-	    {
-		/*
-		 * get pointer to the image in the image library using offset from
-		 * 1st word in image library
-		 */
-		imageOffset = header->entry[imageCount].image.offset;
-		*imagePtr = &imageLibrary[imageOffset];
-		/* get the image size */
-		*imageSize = header->entry[imageCount].image.size;
-		status = IX_SUCCESS;
-		imageFound = TRUE;
-	    }
-	    imageCount++;
-	}
-	if (status != IX_SUCCESS)
-	{
-	    IX_NPEDL_ERROR_REPORT ("ixNpeDlImageMgrImageFind: "
-				   "imageId not found in image library header\n");
-	    ixNpeDlImageMgrStats.imageIdNotFound++;
-	}
-    }
-    else
-    {
-	IX_NPEDL_ERROR_REPORT ("ixNpeDlImageMgrImageFind: "
-			       "invalid signature in image library\n");
-    }
-
-    IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT,
-		     "Exiting ixNpeDlImageMgrImageFind: status = %d\n", status);
-    return status;
-}
-#endif
-
-/*
- * Function definition: ixNpeDlImageMgrImageFind
- */
-IX_STATUS
-ixNpeDlImageMgrImageFind (
-    UINT32 *imageLibrary,
-    UINT32 imageId,
-    UINT32 **imagePtr,
-    UINT32 *imageSize)
-{
-    IxNpeDlImageMgrImageHeader *image;
-    UINT32 offset = 0;
-
-    /* If user didn't specify a library to use, use the default
-     * one from IxNpeMicrocode.h
-     */
-    if (imageLibrary == NULL)
-    {
-#ifdef IX_NPEDL_READ_MICROCODE_FROM_FILE
-	if (ixNpeMicrocode_binaryArray == NULL)
-        {
-	    printk (KERN_ERR "ixp400.o:  ERROR, no Microcode found in memory\n");
-	    return IX_FAIL;
-	}
-	else
-	{
-	    imageLibrary = ixNpeMicrocode_binaryArray;
-	}
-#else
-	imageLibrary = getIxNpeMicroCodeImageLibrary();
-	if (imageLibrary == NULL)
-        {
-	    printf ("npe:  ERROR, no Microcode found in memory\n");
-	    return IX_FAIL;
-	}
-#endif /* IX_NPEDL_READ_MICROCODE_FROM_FILE */
-    }
-
-#if 0
-    /* For backward's compatibility with previous image format */
-    if (ixNpeDlImageMgrSignatureCheck(imageLibrary))
-    {
-        return ixNpeDlImageMgrImageFind_legacy(imageLibrary,
-                                               imageId,
-                                               imagePtr,
-                                               imageSize);
-    }
-#endif
-
-    while (*(imageLibrary+offset) == NPE_IMAGE_MARKER)
-    {
-        image = (IxNpeDlImageMgrImageHeader *)(imageLibrary+offset);
-        offset += sizeof(IxNpeDlImageMgrImageHeader)/sizeof(UINT32);
-        
-        if (image->id == imageId)
-        {
-            *imagePtr = imageLibrary + offset;
-            *imageSize = image->size;
-            return IX_SUCCESS;
-        }
-        /* 2 consecutive NPE_IMAGE_MARKER's indicates end of library */
-        else if (image->id == NPE_IMAGE_MARKER)
-        {
-	    IX_NPEDL_ERROR_REPORT ("ixNpeDlImageMgrImageFind: "
-				   "imageId not found in image library header\n");
-	    ixNpeDlImageMgrStats.imageIdNotFound++;
-            /* reached end of library, image not found */
-            return IX_FAIL;
-        }
-        offset += image->size;
-    }
-
-    /* If we get here, our image library may be corrupted */
-    IX_NPEDL_ERROR_REPORT ("ixNpeDlImageMgrImageFind: "
-                           "image library format may be invalid or corrupted\n");
-    return IX_FAIL;
-}
-
diff --git a/arch/arm/cpu/ixp/npe/IxNpeDlNpeMgr.c b/arch/arm/cpu/ixp/npe/IxNpeDlNpeMgr.c
deleted file mode 100644
index a9ea8bc..0000000
--- a/arch/arm/cpu/ixp/npe/IxNpeDlNpeMgr.c
+++ /dev/null
@@ -1,931 +0,0 @@
-/**
- * @file IxNpeDlNpeMgr.c
- *
- * @author Intel Corporation
- * @date 09 January 2002
- *
- * @brief This file contains the implementation of the private API for the
- *        IXP425 NPE Downloader NpeMgr module
- *
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- * 
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- * 
- * @par
- * -- End of Copyright Notice --
-*/
-
-
-/*
- * Put the user defined include files required.
- */
-#include "IxOsal.h"
-#include "IxNpeDl.h"
-#include "IxNpeDlNpeMgr_p.h"
-#include "IxNpeDlNpeMgrUtils_p.h"
-#include "IxNpeDlNpeMgrEcRegisters_p.h"
-#include "IxNpeDlMacros_p.h"
-#include "IxFeatureCtrl.h"
-
-/*
- * #defines and macros used in this file.
- */
-#define IX_NPEDL_BYTES_PER_WORD                   4
-
-/* used to read download map from version in microcode image */
-#define IX_NPEDL_BLOCK_TYPE_INSTRUCTION           0x00000000
-#define IX_NPEDL_BLOCK_TYPE_DATA                  0x00000001
-#define IX_NPEDL_BLOCK_TYPE_STATE                 0x00000002
-#define IX_NPEDL_END_OF_DOWNLOAD_MAP              0x0000000F
-
-/*
- * masks used to extract address info from State information context
- * register addresses as read from microcode image 
- */
-#define IX_NPEDL_MASK_STATE_ADDR_CTXT_REG         0x0000000F
-#define IX_NPEDL_MASK_STATE_ADDR_CTXT_NUM         0x000000F0
-
-/* LSB offset of Context Number field in State-Info Context Address */
-#define IX_NPEDL_OFFSET_STATE_ADDR_CTXT_NUM       4
-
-/* size (in words) of single State Information entry (ctxt reg address|data) */
-#define IX_NPEDL_STATE_INFO_ENTRY_SIZE            2
-
-
- #define IX_NPEDL_RESET_NPE_PARITY  0x0800
- #define IX_NPEDL_PARITY_BIT_MASK   0x3F00FFFF
- #define IX_NPEDL_CONFIG_CTRL_REG_MASK  0x3F3FFFFF
-
-
-/*
- * Typedefs whose scope is limited to this file.
- */
-
-typedef struct
-{
-    UINT32 type;
-    UINT32 offset;
-} IxNpeDlNpeMgrDownloadMapBlockEntry;
-
-typedef union
-{
-    IxNpeDlNpeMgrDownloadMapBlockEntry block;
-    UINT32 eodmMarker;
-} IxNpeDlNpeMgrDownloadMapEntry;
-
-typedef struct
-{
-    /* 1st entry in the download map (there may be more than one) */
-    IxNpeDlNpeMgrDownloadMapEntry entry[1];
-} IxNpeDlNpeMgrDownloadMap;
-
-
-/* used to access an instruction or data block in a microcode image */
-typedef struct
-{
-    UINT32 npeMemAddress;
-    UINT32 size;
-    UINT32 data[1];
-} IxNpeDlNpeMgrCodeBlock;
-
-/* used to access each Context Reg entry state-information block */
-typedef struct
-{
-    UINT32 addressInfo;
-    UINT32 value;
-} IxNpeDlNpeMgrStateInfoCtxtRegEntry;
-
-/* used to access a state-information block in a microcode image */
-typedef struct
-{
-    UINT32 size;
-    IxNpeDlNpeMgrStateInfoCtxtRegEntry ctxtRegEntry[1];
-} IxNpeDlNpeMgrStateInfoBlock;
- 
-/* used to store some useful NPE information for easy access */
-typedef struct
-{
-    UINT32 baseAddress;
-    UINT32 insMemSize;
-    UINT32 dataMemSize;
-} IxNpeDlNpeInfo;
-
-/* used to distinguish instruction and data memory operations */
-typedef enum 
-{
-  IX_NPEDL_MEM_TYPE_INSTRUCTION = 0,
-  IX_NPEDL_MEM_TYPE_DATA
-} IxNpeDlNpeMemType;
-
-/* used to hold a reset value for a particular ECS register */
-typedef struct
-{
-    UINT32 regAddr;
-    UINT32 regResetVal;
-} IxNpeDlEcsRegResetValue;
-
-/* prototype of function to write either Instruction or Data memory */
-typedef IX_STATUS (*IxNpeDlNpeMgrMemWrite) (UINT32 npeBaseAddress,
-					    UINT32 npeMemAddress,
-					    UINT32 npeMemData,
-					    BOOL verify);
-
-/* module statistics counters */
-typedef struct
-{
-    UINT32 instructionBlocksLoaded;
-    UINT32 dataBlocksLoaded;
-    UINT32 stateInfoBlocksLoaded;
-    UINT32 criticalNpeErrors;
-    UINT32 criticalMicrocodeErrors;
-    UINT32 npeStarts;
-    UINT32 npeStops;
-    UINT32 npeResets;
-} IxNpeDlNpeMgrStats;
-
-
-/*
- * Variable declarations global to this file only.  Externs are followed by
- * static variables.
- */
-static IxNpeDlNpeInfo ixNpeDlNpeInfo[] =
-{
-    {
-	0,
-	IX_NPEDL_INS_MEMSIZE_WORDS_NPEA,
-	IX_NPEDL_DATA_MEMSIZE_WORDS_NPEA
-    },
-    {
-	0,
-	IX_NPEDL_INS_MEMSIZE_WORDS_NPEB,
-	IX_NPEDL_DATA_MEMSIZE_WORDS_NPEB
-    },
-    {
-	0,
-	IX_NPEDL_INS_MEMSIZE_WORDS_NPEC,
-	IX_NPEDL_DATA_MEMSIZE_WORDS_NPEC
-    }
-};
-
-/* contains Reset values for Context Store Registers  */
-static UINT32 ixNpeDlCtxtRegResetValues[] =
-{
-    IX_NPEDL_CTXT_REG_RESET_STEVT,
-    IX_NPEDL_CTXT_REG_RESET_STARTPC,
-    IX_NPEDL_CTXT_REG_RESET_REGMAP,
-    IX_NPEDL_CTXT_REG_RESET_CINDEX,
-};
-
-/* contains Reset values for Context Store Registers  */
-static IxNpeDlEcsRegResetValue ixNpeDlEcsRegResetValues[] =
-{
-    {IX_NPEDL_ECS_BG_CTXT_REG_0,    IX_NPEDL_ECS_BG_CTXT_REG_0_RESET},
-    {IX_NPEDL_ECS_BG_CTXT_REG_1,    IX_NPEDL_ECS_BG_CTXT_REG_1_RESET},
-    {IX_NPEDL_ECS_BG_CTXT_REG_2,    IX_NPEDL_ECS_BG_CTXT_REG_2_RESET},
-    {IX_NPEDL_ECS_PRI_1_CTXT_REG_0, IX_NPEDL_ECS_PRI_1_CTXT_REG_0_RESET},
-    {IX_NPEDL_ECS_PRI_1_CTXT_REG_1, IX_NPEDL_ECS_PRI_1_CTXT_REG_1_RESET},
-    {IX_NPEDL_ECS_PRI_1_CTXT_REG_2, IX_NPEDL_ECS_PRI_1_CTXT_REG_2_RESET},
-    {IX_NPEDL_ECS_PRI_2_CTXT_REG_0, IX_NPEDL_ECS_PRI_2_CTXT_REG_0_RESET},
-    {IX_NPEDL_ECS_PRI_2_CTXT_REG_1, IX_NPEDL_ECS_PRI_2_CTXT_REG_1_RESET},
-    {IX_NPEDL_ECS_PRI_2_CTXT_REG_2, IX_NPEDL_ECS_PRI_2_CTXT_REG_2_RESET},
-    {IX_NPEDL_ECS_DBG_CTXT_REG_0,   IX_NPEDL_ECS_DBG_CTXT_REG_0_RESET},
-    {IX_NPEDL_ECS_DBG_CTXT_REG_1,   IX_NPEDL_ECS_DBG_CTXT_REG_1_RESET},
-    {IX_NPEDL_ECS_DBG_CTXT_REG_2,   IX_NPEDL_ECS_DBG_CTXT_REG_2_RESET},
-    {IX_NPEDL_ECS_INSTRUCT_REG,     IX_NPEDL_ECS_INSTRUCT_REG_RESET}
-};
-
-static IxNpeDlNpeMgrStats ixNpeDlNpeMgrStats;
-
-/* Set when NPE register memory has been mapped */
-static BOOL ixNpeDlMemInitialised = FALSE;
-
-
-/*
- * static function prototypes.
- */
-PRIVATE IX_STATUS
-ixNpeDlNpeMgrMemLoad (IxNpeDlNpeId npeId, UINT32 npeBaseAddress,
-		      IxNpeDlNpeMgrCodeBlock *codeBlockPtr,
-		      BOOL verify, IxNpeDlNpeMemType npeMemType);
-PRIVATE IX_STATUS
-ixNpeDlNpeMgrStateInfoLoad (UINT32 npeBaseAddress,
-			    IxNpeDlNpeMgrStateInfoBlock *codeBlockPtr,
-			    BOOL verify);
-PRIVATE BOOL
-ixNpeDlNpeMgrBitsSetCheck (UINT32 npeBaseAddress, UINT32 regOffset,
-			   UINT32 expectedBitsSet);
-
-PRIVATE UINT32
-ixNpeDlNpeMgrBaseAddressGet (IxNpeDlNpeId npeId);
-
-/*
- * Function definition: ixNpeDlNpeMgrBaseAddressGet
- */
-PRIVATE UINT32
-ixNpeDlNpeMgrBaseAddressGet (IxNpeDlNpeId npeId)
-{
-    IX_OSAL_ASSERT (ixNpeDlMemInitialised);
-    return ixNpeDlNpeInfo[npeId].baseAddress;
-}
-
-
-/*
- * Function definition: ixNpeDlNpeMgrInit
- */
-void
-ixNpeDlNpeMgrInit (void)
-{
-    /* Only map the memory once */
-    if (!ixNpeDlMemInitialised)
-    {
-	UINT32 virtAddr;
-
-	/* map the register memory for NPE-A */
-	virtAddr = (UINT32) IX_OSAL_MEM_MAP (IX_NPEDL_NPEBASEADDRESS_NPEA,
-					    IX_OSAL_IXP400_NPEA_MAP_SIZE); 
-	IX_OSAL_ASSERT(virtAddr);
-	ixNpeDlNpeInfo[IX_NPEDL_NPEID_NPEA].baseAddress = virtAddr;
-
-	/* map the register memory for NPE-B */
-	virtAddr = (UINT32) IX_OSAL_MEM_MAP (IX_NPEDL_NPEBASEADDRESS_NPEB,
-					    IX_OSAL_IXP400_NPEB_MAP_SIZE); 
-	IX_OSAL_ASSERT(virtAddr);
-	ixNpeDlNpeInfo[IX_NPEDL_NPEID_NPEB].baseAddress = virtAddr;
-
-	/* map the register memory for NPE-C */
-	virtAddr = (UINT32) IX_OSAL_MEM_MAP (IX_NPEDL_NPEBASEADDRESS_NPEC,
-					    IX_OSAL_IXP400_NPEC_MAP_SIZE); 
-	IX_OSAL_ASSERT(virtAddr);
-	ixNpeDlNpeInfo[IX_NPEDL_NPEID_NPEC].baseAddress = virtAddr;
-
-	ixNpeDlMemInitialised = TRUE;
-    }
-}
-
-
-/*
- * Function definition: ixNpeDlNpeMgrUninit
- */
-IX_STATUS
-ixNpeDlNpeMgrUninit (void)
-{
-    if (!ixNpeDlMemInitialised)
-    {
-	return IX_FAIL;
-    }
-
-    IX_OSAL_MEM_UNMAP (ixNpeDlNpeInfo[IX_NPEDL_NPEID_NPEA].baseAddress);
-    IX_OSAL_MEM_UNMAP (ixNpeDlNpeInfo[IX_NPEDL_NPEID_NPEB].baseAddress);
-    IX_OSAL_MEM_UNMAP (ixNpeDlNpeInfo[IX_NPEDL_NPEID_NPEC].baseAddress);
-
-    ixNpeDlNpeInfo[IX_NPEDL_NPEID_NPEA].baseAddress = 0;
-    ixNpeDlNpeInfo[IX_NPEDL_NPEID_NPEB].baseAddress = 0;
-    ixNpeDlNpeInfo[IX_NPEDL_NPEID_NPEC].baseAddress = 0;
-
-    ixNpeDlMemInitialised = FALSE;
-
-    return IX_SUCCESS;
-}
-
-/*
- * Function definition: ixNpeDlNpeMgrImageLoad
- */
-IX_STATUS
-ixNpeDlNpeMgrImageLoad (
-    IxNpeDlNpeId npeId,
-    UINT32 *imageCodePtr,
-    BOOL verify)
-{
-    UINT32 npeBaseAddress;
-    IxNpeDlNpeMgrDownloadMap *downloadMap;
-    UINT32 *blockPtr;
-    UINT32 mapIndex = 0;
-    IX_STATUS status = IX_SUCCESS;
-    
-    IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT,
-		     "Entering ixNpeDlNpeMgrImageLoad\n");
-
-    /* get base memory address of NPE from npeId */
-    npeBaseAddress = ixNpeDlNpeMgrBaseAddressGet (npeId);
-
-    /* check execution status of NPE to verify NPE Stop was successful */
-    if (!ixNpeDlNpeMgrBitsSetCheck (npeBaseAddress, IX_NPEDL_REG_OFFSET_EXCTL,
-				    IX_NPEDL_EXCTL_STATUS_STOP))
-    {
-	IX_NPEDL_ERROR_REPORT ("ixNpeDlNpeMgrImageDownload - "
-			       "NPE was not stopped before download\n");
-	status = IX_FAIL;
-    }
-    else
-    {
-	/*
-	 * Read Download Map, checking each block type and calling
-	 * appropriate function to perform download 
-	 */
-	downloadMap = (IxNpeDlNpeMgrDownloadMap *) imageCodePtr;
-	while ((downloadMap->entry[mapIndex].eodmMarker != 
-		IX_NPEDL_END_OF_DOWNLOAD_MAP)
-	       && (status == IX_SUCCESS))
-	{
-	    /* calculate pointer to block to be downloaded */
-	    blockPtr = imageCodePtr +
-		downloadMap->entry[mapIndex].block.offset;
-
-	    switch (downloadMap->entry[mapIndex].block.type)
-	    {
-	    case IX_NPEDL_BLOCK_TYPE_INSTRUCTION:
-		status = ixNpeDlNpeMgrMemLoad (npeId, npeBaseAddress, 
-					     (IxNpeDlNpeMgrCodeBlock *)blockPtr,
-					       verify,
-					       IX_NPEDL_MEM_TYPE_INSTRUCTION);
-		break;
-	    case IX_NPEDL_BLOCK_TYPE_DATA:
-		status = ixNpeDlNpeMgrMemLoad (npeId, npeBaseAddress,
-                                             (IxNpeDlNpeMgrCodeBlock *)blockPtr,
-					       verify, IX_NPEDL_MEM_TYPE_DATA);
-		break;
-	    case IX_NPEDL_BLOCK_TYPE_STATE:
-		status = ixNpeDlNpeMgrStateInfoLoad (npeBaseAddress,
-				       (IxNpeDlNpeMgrStateInfoBlock *) blockPtr,
-						     verify);
-		break;
-	    default:
-		IX_NPEDL_ERROR_REPORT ("ixNpeDlNpeMgrImageLoad: "
-				       "unknown block type in download map\n");
-		status = IX_NPEDL_CRITICAL_MICROCODE_ERR;
-		ixNpeDlNpeMgrStats.criticalMicrocodeErrors++;
-		break;
-	    }
-	    mapIndex++;
-	}/* loop: for each entry in download map, while status == SUCCESS */
-    }/* condition: NPE stopped before attempting download */
-    
-    IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT, 
-		     "Exiting ixNpeDlNpeMgrImageLoad : status = %d\n",
-		     status);
-    return status;
-}
-
-
-/*
- * Function definition: ixNpeDlNpeMgrMemLoad
- */
-PRIVATE IX_STATUS
-ixNpeDlNpeMgrMemLoad (
-    IxNpeDlNpeId npeId,
-    UINT32 npeBaseAddress,
-    IxNpeDlNpeMgrCodeBlock *blockPtr,
-    BOOL verify,
-    IxNpeDlNpeMemType npeMemType)
-{
-    UINT32 npeMemAddress;
-    UINT32 blockSize;
-    UINT32 memSize = 0;
-    IxNpeDlNpeMgrMemWrite memWriteFunc = NULL;
-    UINT32 localIndex = 0;
-    IX_STATUS status = IX_SUCCESS;
-
-    IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT,
-		     "Entering ixNpeDlNpeMgrMemLoad\n");
-    
-    /*
-     * select NPE EXCTL reg read/write commands depending on memory
-     * type (instruction/data) to be accessed
-     */
-    if (npeMemType == IX_NPEDL_MEM_TYPE_INSTRUCTION)
-    {
-	memSize = ixNpeDlNpeInfo[npeId].insMemSize;
-	memWriteFunc = (IxNpeDlNpeMgrMemWrite) ixNpeDlNpeMgrInsMemWrite;
-    }
-    else if (npeMemType == IX_NPEDL_MEM_TYPE_DATA)
-    {
-	memSize = ixNpeDlNpeInfo[npeId].dataMemSize;
-	memWriteFunc = (IxNpeDlNpeMgrMemWrite) ixNpeDlNpeMgrDataMemWrite;
-    }
-
-    /*
-     * NPE memory is loaded contiguously from each block, so only address
-     * of 1st word in block is needed
-     */
-    npeMemAddress = blockPtr->npeMemAddress;
-    /* number of words of instruction/data microcode in block to download */
-    blockSize = blockPtr->size;
-    if ((npeMemAddress + blockSize) > memSize)
-    {
-	IX_NPEDL_ERROR_REPORT ("ixNpeDlNpeMgrMemLoad: "
-			       "Block size too big for NPE memory\n");
-	status = IX_NPEDL_CRITICAL_MICROCODE_ERR;
-	ixNpeDlNpeMgrStats.criticalMicrocodeErrors++;
-    }
-    else
-    {
-	for (localIndex = 0; localIndex < blockSize; localIndex++)
-	{
-	    status = memWriteFunc (npeBaseAddress, npeMemAddress,
-				   blockPtr->data[localIndex], verify);
-
-	    if (status != IX_SUCCESS)
-	    {
-		IX_NPEDL_ERROR_REPORT ("ixNpeDlNpeMgrMemLoad: "
-				       "write to NPE memory failed\n");
-		status = IX_NPEDL_CRITICAL_NPE_ERR;
-		ixNpeDlNpeMgrStats.criticalNpeErrors++;
-		break;   /* abort download */
-	    }
-	    /* increment target (word)address in NPE memory */
-	    npeMemAddress++;   
-	}
-    }/* condition: block size will fit in NPE memory */
-
-    if (status == IX_SUCCESS)
-    {
-	if (npeMemType == IX_NPEDL_MEM_TYPE_INSTRUCTION)
-	{
-	    ixNpeDlNpeMgrStats.instructionBlocksLoaded++;
-	}
-	else if (npeMemType == IX_NPEDL_MEM_TYPE_DATA)
-	{
-	    ixNpeDlNpeMgrStats.dataBlocksLoaded++;
-	}
-    }
-
-    IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT,
-		     "Exiting ixNpeDlNpeMgrMemLoad : status = %d\n", status);
-    return status;
-}
-
-
-/*
- * Function definition: ixNpeDlNpeMgrStateInfoLoad
- */
-PRIVATE IX_STATUS
-ixNpeDlNpeMgrStateInfoLoad (
-    UINT32 npeBaseAddress,
-    IxNpeDlNpeMgrStateInfoBlock *blockPtr,
-    BOOL verify)
-{
-    UINT32 blockSize;
-    UINT32 ctxtRegAddrInfo; 
-    UINT32 ctxtRegVal;
-    IxNpeDlCtxtRegNum ctxtReg; /* identifies Context Store reg (0-3) */
-    UINT32 ctxtNum;            /* identifies Context number (0-16)   */
-    UINT32 i;
-    IX_STATUS status = IX_SUCCESS;
-
-    IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT,
-		     "Entering ixNpeDlNpeMgrStateInfoLoad\n");
-
-    /* block size contains number of words of state-info in block */
-    blockSize = blockPtr->size;
-    
-    ixNpeDlNpeMgrDebugInstructionPreExec (npeBaseAddress);
-
-    /* for each state-info context register entry in block */
-    for (i = 0; i < (blockSize/IX_NPEDL_STATE_INFO_ENTRY_SIZE); i++)
-    {
-	/* each state-info entry is 2 words (address, value) in length */
-	ctxtRegAddrInfo = (blockPtr->ctxtRegEntry[i]).addressInfo;
-	ctxtRegVal      = (blockPtr->ctxtRegEntry[i]).value;
-	
-	ctxtReg = (ctxtRegAddrInfo & IX_NPEDL_MASK_STATE_ADDR_CTXT_REG);
-	ctxtNum = (ctxtRegAddrInfo & IX_NPEDL_MASK_STATE_ADDR_CTXT_NUM) >> 
-	    IX_NPEDL_OFFSET_STATE_ADDR_CTXT_NUM;
-	
-	/* error-check Context Register No. and Context Number values  */
-	/* NOTE that there is no STEVT register for Context 0 */
-	if ((ctxtReg < 0) ||
-	    (ctxtReg >= IX_NPEDL_CTXT_REG_MAX) ||
-	    (ctxtNum > IX_NPEDL_CTXT_NUM_MAX) ||
-	    ((ctxtNum == 0) && (ctxtReg == IX_NPEDL_CTXT_REG_STEVT)))
-	{
-	    IX_NPEDL_ERROR_REPORT ("ixNpeDlNpeMgrStateInfoLoad: "
-				   "invalid Context Register Address\n");
-	    status = IX_NPEDL_CRITICAL_MICROCODE_ERR;
-	    ixNpeDlNpeMgrStats.criticalMicrocodeErrors++;
-	    break;   /* abort download */
-	}    
-	
-	status = ixNpeDlNpeMgrCtxtRegWrite (npeBaseAddress, ctxtNum, ctxtReg,
-					    ctxtRegVal, verify);
-	if (status != IX_SUCCESS)
-	{
-	    IX_NPEDL_ERROR_REPORT ("ixNpeDlNpeMgrStateInfoLoad: "
-				   "write of state-info to NPE failed\n");
-	    status = IX_NPEDL_CRITICAL_NPE_ERR;
-	    ixNpeDlNpeMgrStats.criticalNpeErrors++;
-	    break;   /* abort download */
-	}
-    }/* loop: for each context reg entry in State Info block */
-    
-    ixNpeDlNpeMgrDebugInstructionPostExec (npeBaseAddress);
-
-    if (status == IX_SUCCESS)
-    {
-	ixNpeDlNpeMgrStats.stateInfoBlocksLoaded++;
-    }
-
-    IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT,
-		     "Exiting ixNpeDlNpeMgrStateInfoLoad : status = %d\n",
-		     status);
-    return status;
-}
-
-
-/*
- * Function definition: ixNpeDlNpeMgrNpeReset
- */
-IX_STATUS
-ixNpeDlNpeMgrNpeReset (
-    IxNpeDlNpeId npeId)
-{
-    UINT32 npeBaseAddress;
-    IxNpeDlCtxtRegNum ctxtReg; /* identifies Context Store reg (0-3) */
-    UINT32 ctxtNum;            /* identifies Context number (0-16)   */
-    UINT32 regAddr;
-    UINT32 regVal;
-    UINT32 localIndex;
-    UINT32 indexMax;
-    IX_STATUS status = IX_SUCCESS;
-    IxFeatureCtrlReg unitFuseReg;
-    UINT32 ixNpeConfigCtrlRegVal;
-    
-    IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT, 
-		     "Entering ixNpeDlNpeMgrNpeReset\n");
-    
-    /* get base memory address of NPE from npeId */
-    npeBaseAddress = ixNpeDlNpeMgrBaseAddressGet (npeId);
-
-    /* pre-store the NPE Config Control Register Value */
-    IX_NPEDL_REG_READ (npeBaseAddress, IX_NPEDL_REG_OFFSET_CTL, &ixNpeConfigCtrlRegVal);
-    
-    ixNpeConfigCtrlRegVal |= 0x3F000000;
-    
-    /* disable the parity interrupt */
-    IX_NPEDL_REG_WRITE (npeBaseAddress, IX_NPEDL_REG_OFFSET_CTL, (ixNpeConfigCtrlRegVal & IX_NPEDL_PARITY_BIT_MASK));
-    
-    ixNpeDlNpeMgrDebugInstructionPreExec (npeBaseAddress);
-
-    /*
-     * clear the FIFOs
-     */
-    while (ixNpeDlNpeMgrBitsSetCheck (npeBaseAddress,
-				      IX_NPEDL_REG_OFFSET_WFIFO,
-				      IX_NPEDL_MASK_WFIFO_VALID))
-    {
-	/* read from the Watch-point FIFO until empty */
-	IX_NPEDL_REG_READ (npeBaseAddress, IX_NPEDL_REG_OFFSET_WFIFO,
-			   &regVal);
-    }
-    
-    while (ixNpeDlNpeMgrBitsSetCheck (npeBaseAddress,
-					  IX_NPEDL_REG_OFFSET_STAT,
-				      IX_NPEDL_MASK_STAT_OFNE))
-    {
-	/* read from the outFIFO until empty */
-	IX_NPEDL_REG_READ (npeBaseAddress, IX_NPEDL_REG_OFFSET_FIFO,
-			   &regVal);
-    }
-    
-    while (ixNpeDlNpeMgrBitsSetCheck (npeBaseAddress,
-				      IX_NPEDL_REG_OFFSET_STAT,
-				      IX_NPEDL_MASK_STAT_IFNE))
-    {
-	/*
-	 * step execution of the NPE intruction to read inFIFO using
-	 * the Debug Executing Context stack
-	 */
-	status = ixNpeDlNpeMgrDebugInstructionExec (npeBaseAddress,
-					   IX_NPEDL_INSTR_RD_FIFO, 0, 0);
-
-    if (IX_SUCCESS != status)
-    {
-        return status;   
-    }
-    
-    }
-    
-    /*
-     * Reset the mailbox reg
-     */
-    /* ...from XScale side */
-    IX_NPEDL_REG_WRITE (npeBaseAddress, IX_NPEDL_REG_OFFSET_MBST,
-			IX_NPEDL_REG_RESET_MBST);
-    /* ...from NPE side */
-    status = ixNpeDlNpeMgrDebugInstructionExec (npeBaseAddress,
-				       IX_NPEDL_INSTR_RESET_MBOX, 0, 0);
-
-    if (IX_SUCCESS != status)
-    {
-        return status;   
-    }
-
-    /* 
-     *   Reset the physical registers in the NPE register file:
-     *   Note: no need to save/restore REGMAP for Context 0 here
-     *   since all Context Store regs are reset in subsequent code
-     */
-    for (regAddr = 0;
-	 (regAddr < IX_NPEDL_TOTAL_NUM_PHYS_REG) && (status != IX_FAIL);
-	 regAddr++)
-    {
-	/* for each physical register in the NPE reg file, write 0 : */
-	status = ixNpeDlNpeMgrPhysicalRegWrite (npeBaseAddress, regAddr,
-						0, TRUE);
-	if (status != IX_SUCCESS)
-	{
-	    return status;  /* abort reset */
-	}
-    }
-    
-
-    /*
-     * Reset the context store:
-     */
-    for (ctxtNum = IX_NPEDL_CTXT_NUM_MIN;
-	 ctxtNum <= IX_NPEDL_CTXT_NUM_MAX; ctxtNum++)
-    {	
-	/* set each context's Context Store registers to reset values: */
-	for (ctxtReg = 0; ctxtReg < IX_NPEDL_CTXT_REG_MAX; ctxtReg++)
-	{
-	    /* NOTE that there is no STEVT register for Context 0 */
-	    if (!((ctxtNum == 0) && (ctxtReg == IX_NPEDL_CTXT_REG_STEVT)))
-	    { 
-		regVal = ixNpeDlCtxtRegResetValues[ctxtReg];
-		status = ixNpeDlNpeMgrCtxtRegWrite (npeBaseAddress, ctxtNum,
-						    ctxtReg, regVal, TRUE);
-		if (status != IX_SUCCESS)
-		{
-		    return status;  /* abort reset */
-		}
-	    }
-	}
-    }
-
-    ixNpeDlNpeMgrDebugInstructionPostExec (npeBaseAddress);
-
-    /* write Reset values to Execution Context Stack registers */
-    indexMax = sizeof (ixNpeDlEcsRegResetValues) /
-	sizeof (IxNpeDlEcsRegResetValue);
-    for (localIndex = 0; localIndex < indexMax; localIndex++)
-    {
-	regAddr = ixNpeDlEcsRegResetValues[localIndex].regAddr;
-	regVal = ixNpeDlEcsRegResetValues[localIndex].regResetVal;
-	ixNpeDlNpeMgrExecAccRegWrite (npeBaseAddress, regAddr, regVal);
-    }
-    
-    /* clear the profile counter */
-    ixNpeDlNpeMgrCommandIssue (npeBaseAddress, 
-			       IX_NPEDL_EXCTL_CMD_CLR_PROFILE_CNT);
-    
-    /* clear registers EXCT, AP0, AP1, AP2 and AP3 */
-    for (regAddr = IX_NPEDL_REG_OFFSET_EXCT;
-	     regAddr <= IX_NPEDL_REG_OFFSET_AP3;
-	 regAddr += IX_NPEDL_BYTES_PER_WORD)
-    {
-	IX_NPEDL_REG_WRITE (npeBaseAddress, regAddr, 0);
-    }
-    
-    /* Reset the Watch-count register */
-    IX_NPEDL_REG_WRITE (npeBaseAddress, IX_NPEDL_REG_OFFSET_WC, 0);
-    
-    /*
-     * WR IXA00055043 - Remove IMEM Parity Introduced by NPE Reset Operation
-     */
-
-    /*
-     * Call the feature control API to fused out and reset the NPE and its
-     * coprocessor - to reset internal states and remove parity error
-     */
-    unitFuseReg = ixFeatureCtrlRead ();
-    unitFuseReg |= (IX_NPEDL_RESET_NPE_PARITY << npeId);
-    ixFeatureCtrlWrite (unitFuseReg);
-
-    /* call the feature control API to un-fused and un-reset the NPE & COP */
-    unitFuseReg &= (~(IX_NPEDL_RESET_NPE_PARITY << npeId));
-    ixFeatureCtrlWrite (unitFuseReg);
-
-    /*
-     * Call NpeMgr function to stop the NPE again after the Feature Control
-     * has unfused and Un-Reset the NPE and its associated Coprocessors
-     */
-    status = ixNpeDlNpeMgrNpeStop (npeId);
-
-    /* restore NPE configuration bus Control Register - Parity Settings  */
-    IX_NPEDL_REG_WRITE (npeBaseAddress, IX_NPEDL_REG_OFFSET_CTL, 
-        (ixNpeConfigCtrlRegVal & IX_NPEDL_CONFIG_CTRL_REG_MASK));
-
-    ixNpeDlNpeMgrStats.npeResets++;
-
-    IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT,
-		     "Exiting ixNpeDlNpeMgrNpeReset : status = %d\n", status);
-    return status;
-}
-
-
-/*
- * Function definition: ixNpeDlNpeMgrNpeStart
- */
-IX_STATUS
-ixNpeDlNpeMgrNpeStart (
-    IxNpeDlNpeId npeId)
-{
-    UINT32    npeBaseAddress;
-    UINT32    ecsRegVal;
-    BOOL      npeRunning;
-    IX_STATUS status = IX_SUCCESS;
-
-    IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT, 
-		     "Entering ixNpeDlNpeMgrNpeStart\n");
-
-    /* get base memory address of NPE from npeId */
-    npeBaseAddress = ixNpeDlNpeMgrBaseAddressGet (npeId);
-
-    /*
-     * ensure only Background Context Stack Level is Active by turning off
-     * the Active bit in each of the other Executing Context Stack levels
-     */
-    ecsRegVal = ixNpeDlNpeMgrExecAccRegRead (npeBaseAddress,
-					     IX_NPEDL_ECS_PRI_1_CTXT_REG_0);
-    ecsRegVal &= ~IX_NPEDL_MASK_ECS_REG_0_ACTIVE;
-    ixNpeDlNpeMgrExecAccRegWrite (npeBaseAddress, IX_NPEDL_ECS_PRI_1_CTXT_REG_0,
-				  ecsRegVal);
-
-    ecsRegVal = ixNpeDlNpeMgrExecAccRegRead (npeBaseAddress,
-					     IX_NPEDL_ECS_PRI_2_CTXT_REG_0);
-    ecsRegVal &= ~IX_NPEDL_MASK_ECS_REG_0_ACTIVE;
-    ixNpeDlNpeMgrExecAccRegWrite (npeBaseAddress, IX_NPEDL_ECS_PRI_2_CTXT_REG_0,
-				  ecsRegVal);
-
-    ecsRegVal = ixNpeDlNpeMgrExecAccRegRead (npeBaseAddress,
-					     IX_NPEDL_ECS_DBG_CTXT_REG_0);
-    ecsRegVal &= ~IX_NPEDL_MASK_ECS_REG_0_ACTIVE;
-    ixNpeDlNpeMgrExecAccRegWrite (npeBaseAddress, IX_NPEDL_ECS_DBG_CTXT_REG_0,
-				  ecsRegVal);
-    
-    /* clear the pipeline */
-    ixNpeDlNpeMgrCommandIssue (npeBaseAddress, IX_NPEDL_EXCTL_CMD_NPE_CLR_PIPE);
-    
-    /* start NPE execution by issuing command through EXCTL register on NPE */
-    ixNpeDlNpeMgrCommandIssue (npeBaseAddress, IX_NPEDL_EXCTL_CMD_NPE_START);
-
-    /*
-     * check execution status of NPE to verify NPE Start operation was
-     * successful
-     */
-    npeRunning = ixNpeDlNpeMgrBitsSetCheck (npeBaseAddress,
-					    IX_NPEDL_REG_OFFSET_EXCTL,
-					    IX_NPEDL_EXCTL_STATUS_RUN);
-    if (npeRunning)
-    {
-	ixNpeDlNpeMgrStats.npeStarts++;
-    }
-    else
-    {
-	IX_NPEDL_ERROR_REPORT ("ixNpeDlNpeMgrNpeStart: "
-			       "failed to start NPE execution\n");
-	status = IX_FAIL;
-    }
-
-    
-    IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT,
-		     "Exiting ixNpeDlNpeMgrNpeStart : status = %d\n", status);
-    return status;
-}
-
-
-/*
- * Function definition: ixNpeDlNpeMgrNpeStop
- */
-IX_STATUS
-ixNpeDlNpeMgrNpeStop (
-    IxNpeDlNpeId npeId)
-{
-    UINT32    npeBaseAddress;
-    IX_STATUS status = IX_SUCCESS;
-    
-    IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT,
-		     "Entering ixNpeDlNpeMgrNpeStop\n");
-    
-    /* get base memory address of NPE from npeId */
-    npeBaseAddress = ixNpeDlNpeMgrBaseAddressGet (npeId);
-
-    /* stop NPE execution by issuing command through EXCTL register on NPE */
-    ixNpeDlNpeMgrCommandIssue (npeBaseAddress, IX_NPEDL_EXCTL_CMD_NPE_STOP);
-
-    /* verify that NPE Stop was successful */
-    if (! ixNpeDlNpeMgrBitsSetCheck (npeBaseAddress, IX_NPEDL_REG_OFFSET_EXCTL,
-				     IX_NPEDL_EXCTL_STATUS_STOP))
-    {
-	IX_NPEDL_ERROR_REPORT ("ixNpeDlNpeMgrNpeStop: "
-			       "failed to stop NPE execution\n");
-	status = IX_FAIL;
-    }
-
-    ixNpeDlNpeMgrStats.npeStops++;
-    
-    IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT,
-		     "Exiting ixNpeDlNpeMgrNpeStop : status = %d\n", status);
-    return status;
-}
-
-
-/*
- * Function definition: ixNpeDlNpeMgrBitsSetCheck
- */
-PRIVATE BOOL
-ixNpeDlNpeMgrBitsSetCheck (
-    UINT32 npeBaseAddress,
-    UINT32 regOffset,
-    UINT32 expectedBitsSet)
-{
-    UINT32 regVal;
-    IX_NPEDL_REG_READ (npeBaseAddress, regOffset, &regVal);
-
-    return expectedBitsSet == (expectedBitsSet & regVal);
-}
-
-
-/*
- * Function definition: ixNpeDlNpeMgrStatsShow
- */
-void
-ixNpeDlNpeMgrStatsShow (void)
-{
-    ixOsalLog (IX_OSAL_LOG_LVL_USER,
-               IX_OSAL_LOG_DEV_STDOUT,
-               "\nixNpeDlNpeMgrStatsShow:\n"
-               "\tInstruction Blocks loaded: %u\n"
-               "\tData Blocks loaded: %u\n"
-               "\tState Information Blocks loaded: %u\n"
-               "\tCritical NPE errors: %u\n"
-               "\tCritical Microcode errors: %u\n",
-               ixNpeDlNpeMgrStats.instructionBlocksLoaded,
-               ixNpeDlNpeMgrStats.dataBlocksLoaded,
-               ixNpeDlNpeMgrStats.stateInfoBlocksLoaded,
-               ixNpeDlNpeMgrStats.criticalNpeErrors,
-               ixNpeDlNpeMgrStats.criticalMicrocodeErrors,
-               0);
-
-    ixOsalLog (IX_OSAL_LOG_LVL_USER,
-               IX_OSAL_LOG_DEV_STDOUT,
-               "\tSuccessful NPE Starts: %u\n"
-               "\tSuccessful NPE Stops: %u\n"
-               "\tSuccessful NPE Resets: %u\n\n",
-               ixNpeDlNpeMgrStats.npeStarts,
-               ixNpeDlNpeMgrStats.npeStops,
-               ixNpeDlNpeMgrStats.npeResets,
-               0,0,0);
-
-    ixNpeDlNpeMgrUtilsStatsShow ();
-}
-
-
-/*
- * Function definition: ixNpeDlNpeMgrStatsReset
- */
-void
-ixNpeDlNpeMgrStatsReset (void)
-{
-    ixNpeDlNpeMgrStats.instructionBlocksLoaded = 0;
-    ixNpeDlNpeMgrStats.dataBlocksLoaded = 0;
-    ixNpeDlNpeMgrStats.stateInfoBlocksLoaded = 0;
-    ixNpeDlNpeMgrStats.criticalNpeErrors = 0;
-    ixNpeDlNpeMgrStats.criticalMicrocodeErrors = 0;
-    ixNpeDlNpeMgrStats.npeStarts = 0;
-    ixNpeDlNpeMgrStats.npeStops = 0;
-    ixNpeDlNpeMgrStats.npeResets = 0;
-
-    ixNpeDlNpeMgrUtilsStatsReset ();
-}
diff --git a/arch/arm/cpu/ixp/npe/IxNpeDlNpeMgrUtils.c b/arch/arm/cpu/ixp/npe/IxNpeDlNpeMgrUtils.c
deleted file mode 100644
index 18cac50..0000000
--- a/arch/arm/cpu/ixp/npe/IxNpeDlNpeMgrUtils.c
+++ /dev/null
@@ -1,806 +0,0 @@
-/**
- * @file IxNpeDlNpeMgrUtils.c
- *
- * @author Intel Corporation
- * @date 18 February 2002
- *
- * @brief This file contains the implementation of the private API for the 
- *        IXP425 NPE Downloader NpeMgr Utils module
- *
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- * 
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- * 
- * @par
- * -- End of Copyright Notice --
-*/
-
-
-/*
- * Put the system defined include files required.
- */
-#define IX_NPE_DL_MAX_NUM_OF_RETRIES 1000000 /**< Maximum number of
-                                              * retries before
-                                              * timeout
-					                          */  
-
-/*
- * Put the user defined include files required.
- */
-#include "IxOsal.h"
-#include "IxNpeDl.h"
-#include "IxNpeDlNpeMgrUtils_p.h"
-#include "IxNpeDlNpeMgrEcRegisters_p.h"
-#include "IxNpeDlMacros_p.h"
-
-/*
- * #defines and macros used in this file.
- */
-
-/* used to bit-mask a number of bytes */
-#define IX_NPEDL_MASK_LOWER_BYTE_OF_WORD  0x000000FF
-#define IX_NPEDL_MASK_LOWER_SHORT_OF_WORD 0x0000FFFF
-#define IX_NPEDL_MASK_FULL_WORD           0xFFFFFFFF
-
-#define IX_NPEDL_BYTES_PER_WORD           4
-#define IX_NPEDL_BYTES_PER_SHORT          2
-
-#define IX_NPEDL_REG_SIZE_BYTE            8
-#define IX_NPEDL_REG_SIZE_SHORT           16
-#define IX_NPEDL_REG_SIZE_WORD            32
-
-/*
- * Introduce extra read cycles after issuing read command to NPE
- * so that we read the register after the NPE has updated it
- * This is to overcome race condition between XScale and NPE
- */
-#define IX_NPEDL_DELAY_READ_CYCLES        2
-/*
- * To mask top three MSBs of 32bit word to download into NPE IMEM
- */
-#define IX_NPEDL_MASK_UNUSED_IMEM_BITS    0x1FFFFFFF;
-
-
-/*
- * typedefs
- */
-typedef struct
-{
-    UINT32 regAddress;
-    UINT32 regSize;
-} IxNpeDlCtxtRegAccessInfo;
-
-/* module statistics counters */
-typedef struct
-{
-    UINT32 insMemWrites;
-    UINT32 insMemWriteFails;
-    UINT32 dataMemWrites;
-    UINT32 dataMemWriteFails;
-    UINT32 ecsRegWrites;
-    UINT32 ecsRegReads;
-    UINT32 dbgInstructionExecs;
-    UINT32 contextRegWrites;
-    UINT32 physicalRegWrites;
-    UINT32 nextPcWrites;
-} IxNpeDlNpeMgrUtilsStats;
-
-
-/*
- * Variable declarations global to this file only.  Externs are followed by
- * static variables.
- */
-
-/* 
- * contains useful address and function pointers to read/write Context Regs, 
- * eliminating some switch or if-else statements in places
- */
-static IxNpeDlCtxtRegAccessInfo ixNpeDlCtxtRegAccInfo[IX_NPEDL_CTXT_REG_MAX] =
-{
-    {
-	IX_NPEDL_CTXT_REG_ADDR_STEVT,
-	IX_NPEDL_REG_SIZE_BYTE
-    },
-    {
-	IX_NPEDL_CTXT_REG_ADDR_STARTPC,
-	IX_NPEDL_REG_SIZE_SHORT
-    },
-    {
-	IX_NPEDL_CTXT_REG_ADDR_REGMAP,
-	IX_NPEDL_REG_SIZE_SHORT
-    },
-    {
-	IX_NPEDL_CTXT_REG_ADDR_CINDEX,
-	IX_NPEDL_REG_SIZE_BYTE
-    }
-};
-
-static UINT32 ixNpeDlSavedExecCount = 0;
-static UINT32 ixNpeDlSavedEcsDbgCtxtReg2 = 0;
-
-static IxNpeDlNpeMgrUtilsStats ixNpeDlNpeMgrUtilsStats;
-
-
-/*
- * static function prototypes.
- */
-PRIVATE __inline__ void
-ixNpeDlNpeMgrWriteCommandIssue (UINT32 npeBaseAddress, UINT32 cmd,
-				UINT32 addr, UINT32 data);
-
-PRIVATE __inline__ UINT32
-ixNpeDlNpeMgrReadCommandIssue (UINT32 npeBaseAddress, UINT32 cmd, UINT32 addr);
-
-PRIVATE IX_STATUS
-ixNpeDlNpeMgrLogicalRegRead (UINT32 npeBaseAddress, UINT32 regAddr,
-			     UINT32 regSize, UINT32 ctxtNum, UINT32 *regVal);
-
-PRIVATE IX_STATUS
-ixNpeDlNpeMgrLogicalRegWrite (UINT32 npeBaseAddress, UINT32 regAddr,
-			      UINT32 regVal, UINT32 regSize,
-			      UINT32 ctxtNum, BOOL verify);
-
-/*
- * Function definition: ixNpeDlNpeMgrWriteCommandIssue
- */
-PRIVATE __inline__ void
-ixNpeDlNpeMgrWriteCommandIssue (
-    UINT32 npeBaseAddress,
-    UINT32 cmd,
-    UINT32 addr,
-    UINT32 data)
-{
-    IX_NPEDL_REG_WRITE (npeBaseAddress, IX_NPEDL_REG_OFFSET_EXDATA, data);
-    IX_NPEDL_REG_WRITE (npeBaseAddress, IX_NPEDL_REG_OFFSET_EXAD, addr);
-    IX_NPEDL_REG_WRITE (npeBaseAddress, IX_NPEDL_REG_OFFSET_EXCTL, cmd);
-}
-
-
-/*
- * Function definition: ixNpeDlNpeMgrReadCommandIssue
- */
-PRIVATE __inline__ UINT32
-ixNpeDlNpeMgrReadCommandIssue (
-    UINT32 npeBaseAddress,
-    UINT32 cmd,
-    UINT32 addr)
-{
-    UINT32 data = 0;
-    int i;
-
-    IX_NPEDL_REG_WRITE (npeBaseAddress, IX_NPEDL_REG_OFFSET_EXAD, addr);
-    IX_NPEDL_REG_WRITE (npeBaseAddress, IX_NPEDL_REG_OFFSET_EXCTL, cmd);
-    for (i = 0; i <= IX_NPEDL_DELAY_READ_CYCLES; i++)
-    {
-	IX_NPEDL_REG_READ (npeBaseAddress, IX_NPEDL_REG_OFFSET_EXDATA, &data);
-    }
-
-    return data;
-}
-
-/*
- * Function definition: ixNpeDlNpeMgrInsMemWrite
- */
-IX_STATUS
-ixNpeDlNpeMgrInsMemWrite (
-    UINT32 npeBaseAddress,
-    UINT32 insMemAddress,
-    UINT32 insMemData,
-    BOOL verify)
-{
-    UINT32 insMemDataRtn;
-
-    ixNpeDlNpeMgrWriteCommandIssue (npeBaseAddress,
-				    IX_NPEDL_EXCTL_CMD_WR_INS_MEM,
-				    insMemAddress, insMemData);
-    if (verify)
-    {
-        /* write invalid data to this reg, so we can see if we're reading 
-	   the EXDATA register too early */
-	IX_NPEDL_REG_WRITE (npeBaseAddress, IX_NPEDL_REG_OFFSET_EXDATA,
-			    ~insMemData);
-
-        /*Disabled since top 3 MSB are not used for Azusa hardware Refer WR:IXA00053900*/
-        insMemData&=IX_NPEDL_MASK_UNUSED_IMEM_BITS;
-
-        insMemDataRtn=ixNpeDlNpeMgrReadCommandIssue (npeBaseAddress,
-                                           IX_NPEDL_EXCTL_CMD_RD_INS_MEM,
-                                           insMemAddress);
-
-        insMemDataRtn&=IX_NPEDL_MASK_UNUSED_IMEM_BITS;
-
-	if (insMemData != insMemDataRtn)
-	{
-	    ixNpeDlNpeMgrUtilsStats.insMemWriteFails++;
-	    return IX_FAIL;
-	}
-    }
-
-    ixNpeDlNpeMgrUtilsStats.insMemWrites++;
-    return IX_SUCCESS;
-}
-
-
-/*
- * Function definition: ixNpeDlNpeMgrDataMemWrite
- */
-IX_STATUS
-ixNpeDlNpeMgrDataMemWrite (
-    UINT32 npeBaseAddress,
-    UINT32 dataMemAddress,
-    UINT32 dataMemData,
-    BOOL verify)
-{
-    ixNpeDlNpeMgrWriteCommandIssue (npeBaseAddress,
-				    IX_NPEDL_EXCTL_CMD_WR_DATA_MEM,
-				    dataMemAddress, dataMemData);
-    if (verify)
-    {
-        /* write invalid data to this reg, so we can see if we're reading 
-	   the EXDATA register too early */
-	IX_NPEDL_REG_WRITE (npeBaseAddress, IX_NPEDL_REG_OFFSET_EXDATA, ~dataMemData);
-
-	if (dataMemData !=
-	    ixNpeDlNpeMgrReadCommandIssue (npeBaseAddress,
-					   IX_NPEDL_EXCTL_CMD_RD_DATA_MEM,
-					   dataMemAddress))
-	{
-	    ixNpeDlNpeMgrUtilsStats.dataMemWriteFails++;
-	    return IX_FAIL;
-	}
-    }
-
-    ixNpeDlNpeMgrUtilsStats.dataMemWrites++;
-    return IX_SUCCESS;
-}
-
-
-/*
- * Function definition: ixNpeDlNpeMgrExecAccRegWrite
- */
-void
-ixNpeDlNpeMgrExecAccRegWrite (
-    UINT32 npeBaseAddress,
-    UINT32 regAddress,
-    UINT32 regData)
-{
-    ixNpeDlNpeMgrWriteCommandIssue (npeBaseAddress,
-				    IX_NPEDL_EXCTL_CMD_WR_ECS_REG,
-				    regAddress, regData);
-    ixNpeDlNpeMgrUtilsStats.ecsRegWrites++;
-}
-
-
-/*
- * Function definition: ixNpeDlNpeMgrExecAccRegRead
- */
-UINT32
-ixNpeDlNpeMgrExecAccRegRead (
-    UINT32 npeBaseAddress,
-    UINT32 regAddress)
-{
-    ixNpeDlNpeMgrUtilsStats.ecsRegReads++;
-    return ixNpeDlNpeMgrReadCommandIssue (npeBaseAddress,
-					  IX_NPEDL_EXCTL_CMD_RD_ECS_REG,
-					  regAddress);
-}
-
-
-/*
- * Function definition: ixNpeDlNpeMgrCommandIssue
- */
-void
-ixNpeDlNpeMgrCommandIssue (
-    UINT32 npeBaseAddress,
-    UINT32 command)     
-{
-    IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT,
-		     "Entering ixNpeDlNpeMgrCommandIssue\n");
-
-    IX_NPEDL_REG_WRITE (npeBaseAddress, IX_NPEDL_REG_OFFSET_EXCTL, command);
-
-    IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT,
-		     "Exiting ixNpeDlNpeMgrCommandIssue\n");
-}
-
-
-/*
- * Function definition: ixNpeDlNpeMgrDebugInstructionPreExec
- */
-void
-ixNpeDlNpeMgrDebugInstructionPreExec(
-    UINT32 npeBaseAddress)
-{
-    /* turn off the halt bit by clearing Execution Count register. */
-    /* save reg contents 1st and restore later */
-    IX_NPEDL_REG_READ (npeBaseAddress, IX_NPEDL_REG_OFFSET_EXCT,
-		       &ixNpeDlSavedExecCount);
-    IX_NPEDL_REG_WRITE (npeBaseAddress, IX_NPEDL_REG_OFFSET_EXCT, 0);
-
-    /* ensure that IF and IE are on (temporarily), so that we don't end up
-     * stepping forever */
-    ixNpeDlSavedEcsDbgCtxtReg2 = ixNpeDlNpeMgrExecAccRegRead (npeBaseAddress,
-				                   IX_NPEDL_ECS_DBG_CTXT_REG_2);
-
-    ixNpeDlNpeMgrExecAccRegWrite (npeBaseAddress, IX_NPEDL_ECS_DBG_CTXT_REG_2,
-				  (ixNpeDlSavedEcsDbgCtxtReg2 |
-				   IX_NPEDL_MASK_ECS_DBG_REG_2_IF |
-				   IX_NPEDL_MASK_ECS_DBG_REG_2_IE));
-}
-
-
-/*
- * Function definition: ixNpeDlNpeMgrDebugInstructionExec
- */
-IX_STATUS
-ixNpeDlNpeMgrDebugInstructionExec(
-    UINT32 npeBaseAddress,
-    UINT32 npeInstruction,
-    UINT32 ctxtNum,
-    UINT32 ldur)
-{
-    UINT32 ecsDbgRegVal;
-    UINT32 oldWatchcount, newWatchcount;
-    UINT32 retriesCount = 0;
-    IX_STATUS status = IX_SUCCESS;
-
-    IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT,
-		     "Entering ixNpeDlNpeMgrDebugInstructionExec\n");
-
-    /* set the Active bit, and the LDUR, in the debug level */
-    ecsDbgRegVal = IX_NPEDL_MASK_ECS_REG_0_ACTIVE |
-	(ldur << IX_NPEDL_OFFSET_ECS_REG_0_LDUR);
-
-    ixNpeDlNpeMgrExecAccRegWrite (npeBaseAddress, IX_NPEDL_ECS_DBG_CTXT_REG_0,
-				  ecsDbgRegVal);
-
-    /*
-     * set CCTXT at ECS DEBUG L3 to specify in which context to execute the
-     * instruction, and set SELCTXT at ECS DEBUG Level to specify which context
-     * store to access.
-     * Debug ECS Level Reg 1 has form  0x000n000n, where n = context number
-     */
-    ecsDbgRegVal = (ctxtNum << IX_NPEDL_OFFSET_ECS_REG_1_CCTXT) |
-	(ctxtNum << IX_NPEDL_OFFSET_ECS_REG_1_SELCTXT);
-
-    ixNpeDlNpeMgrExecAccRegWrite (npeBaseAddress, IX_NPEDL_ECS_DBG_CTXT_REG_1,
-				  ecsDbgRegVal);
-
-    /* clear the pipeline */
-    ixNpeDlNpeMgrCommandIssue (npeBaseAddress, IX_NPEDL_EXCTL_CMD_NPE_CLR_PIPE);
-
-    /* load NPE instruction into the instruction register */
-    ixNpeDlNpeMgrExecAccRegWrite (npeBaseAddress, IX_NPEDL_ECS_INSTRUCT_REG,
-				  npeInstruction);
-
-    /* we need this value later to wait for completion of NPE execution step */
-    IX_NPEDL_REG_READ (npeBaseAddress, IX_NPEDL_REG_OFFSET_WC, &oldWatchcount);
-
-    /* issue a Step One command via the Execution Control register */
-    ixNpeDlNpeMgrCommandIssue (npeBaseAddress, IX_NPEDL_EXCTL_CMD_NPE_STEP);
-
-	/* Watch Count register increments when NPE completes an instruction */
-	IX_NPEDL_REG_READ (npeBaseAddress, IX_NPEDL_REG_OFFSET_WC,
-        &newWatchcount);
-        
-    /*
-     * force the XScale to wait until the NPE has finished execution step
-     * NOTE that this delay will be very small, just long enough to allow a
-     * single NPE instruction to complete execution; if instruction execution
-     * is not completed before timeout retries, exit the while loop
-     */
-    while ((IX_NPE_DL_MAX_NUM_OF_RETRIES > retriesCount) 
-        && (newWatchcount == oldWatchcount))
-    {
-	    /* Watch Count register increments when NPE completes an instruction */
-	    IX_NPEDL_REG_READ (npeBaseAddress, IX_NPEDL_REG_OFFSET_WC,
-		    &newWatchcount);
-			   
-        retriesCount++;
-    }    
-
-    if (IX_NPE_DL_MAX_NUM_OF_RETRIES > retriesCount)
-    {
-        ixNpeDlNpeMgrUtilsStats.dbgInstructionExecs++;
-    }
-    else
-    {
-        /* Return timeout status as the instruction has not been executed
-         * after maximum retries */
-        status = IX_NPEDL_CRITICAL_NPE_ERR;
-    }
-    
-    IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT,
-		     "Exiting ixNpeDlNpeMgrDebugInstructionExec\n");
-		     
-    return status;
-}    
-
-
-/*
- * Function definition: ixNpeDlNpeMgrDebugInstructionPostExec
- */
-void
-ixNpeDlNpeMgrDebugInstructionPostExec(
-    UINT32 npeBaseAddress)
-{
-    /* clear active bit in debug level */
-    ixNpeDlNpeMgrExecAccRegWrite (npeBaseAddress, IX_NPEDL_ECS_DBG_CTXT_REG_0,
-				  0);
-
-    /* clear the pipeline */
-    ixNpeDlNpeMgrCommandIssue (npeBaseAddress, IX_NPEDL_EXCTL_CMD_NPE_CLR_PIPE);
-    
-    /* restore Execution Count register contents. */
-    IX_NPEDL_REG_WRITE (npeBaseAddress, IX_NPEDL_REG_OFFSET_EXCT,
-			ixNpeDlSavedExecCount);
-
-    /* restore IF and IE bits to original values */
-    ixNpeDlNpeMgrExecAccRegWrite (npeBaseAddress, IX_NPEDL_ECS_DBG_CTXT_REG_2,
-				  ixNpeDlSavedEcsDbgCtxtReg2);
-}
-
-
-/*
- * Function definition: ixNpeDlNpeMgrLogicalRegRead
- */
-PRIVATE IX_STATUS
-ixNpeDlNpeMgrLogicalRegRead (
-    UINT32 npeBaseAddress, 
-    UINT32 regAddr,
-    UINT32 regSize,
-    UINT32 ctxtNum,
-    UINT32 *regVal)
-{
-    IX_STATUS status = IX_SUCCESS;
-    UINT32 npeInstruction = 0;
-    UINT32 mask = 0;
-
-    IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT,
-		     "Entering ixNpeDlNpeMgrLogicalRegRead\n");
-
-    switch (regSize)
-    {
-    case IX_NPEDL_REG_SIZE_BYTE:
-      npeInstruction = IX_NPEDL_INSTR_RD_REG_BYTE;
-      mask = IX_NPEDL_MASK_LOWER_BYTE_OF_WORD;  break;
-    case IX_NPEDL_REG_SIZE_SHORT:
-      npeInstruction = IX_NPEDL_INSTR_RD_REG_SHORT;
-      mask = IX_NPEDL_MASK_LOWER_SHORT_OF_WORD;  break;
-    case IX_NPEDL_REG_SIZE_WORD:
-      npeInstruction = IX_NPEDL_INSTR_RD_REG_WORD;
-      mask = IX_NPEDL_MASK_FULL_WORD;  break;
-    }
-
-    /* make regAddr be the SRC and DEST operands (e.g. movX d0, d0) */
-    npeInstruction |= (regAddr << IX_NPEDL_OFFSET_INSTR_SRC) |
-	(regAddr << IX_NPEDL_OFFSET_INSTR_DEST);
-
-    /* step execution of NPE intruction using Debug Executing Context stack */
-    status = ixNpeDlNpeMgrDebugInstructionExec (npeBaseAddress, npeInstruction,
-				       ctxtNum, IX_NPEDL_RD_INSTR_LDUR);
-
-    if (IX_SUCCESS != status)
-    {
-        return status;
-    }
-    
-    /* read value of register from Execution Data register */
-    IX_NPEDL_REG_READ (npeBaseAddress,	IX_NPEDL_REG_OFFSET_EXDATA, regVal);
-
-   /* align value from left to right */
-    *regVal = (*regVal >> (IX_NPEDL_REG_SIZE_WORD - regSize)) & mask;
-
-    IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT,
-		     "Exiting ixNpeDlNpeMgrLogicalRegRead\n");
-    
-    return IX_SUCCESS;
-}
-
-
-/*
- * Function definition: ixNpeDlNpeMgrLogicalRegWrite
- */
-PRIVATE IX_STATUS
-ixNpeDlNpeMgrLogicalRegWrite (
-    UINT32 npeBaseAddress, 
-    UINT32 regAddr,
-    UINT32 regVal,
-    UINT32 regSize,
-    UINT32 ctxtNum,
-    BOOL verify)
-{
-    UINT32 npeInstruction = 0;
-    UINT32 mask = 0;
-    IX_STATUS status = IX_SUCCESS;
-    UINT32 retRegVal;
-
-    IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT,
-		     "Entering ixNpeDlNpeMgrLogicalRegWrite\n");
-
-    if (regSize == IX_NPEDL_REG_SIZE_WORD)
-    {
-	/* NPE register addressing is left-to-right: e.g. |d0|d1|d2|d3| */
-	/* Write upper half-word (short) to |d0|d1| */
-	status = ixNpeDlNpeMgrLogicalRegWrite (npeBaseAddress, regAddr,
-				      regVal >> IX_NPEDL_REG_SIZE_SHORT,
-				      IX_NPEDL_REG_SIZE_SHORT,
-				      ctxtNum, verify);
-				      
-	if (IX_SUCCESS != status)
-	{
-	    return status;
-	}
-	
-	/* Write lower half-word (short) to |d2|d3| */
-	status = ixNpeDlNpeMgrLogicalRegWrite (npeBaseAddress,
-				      regAddr + IX_NPEDL_BYTES_PER_SHORT,
-                                    regVal & IX_NPEDL_MASK_LOWER_SHORT_OF_WORD,
-				      IX_NPEDL_REG_SIZE_SHORT,
-				      ctxtNum, verify);
-    
-    if (IX_SUCCESS != status)
-	{
-	    return status;
-	}
-	}
-    else
-    {
-        switch (regSize)
-	{ 
-	case IX_NPEDL_REG_SIZE_BYTE:
-	    npeInstruction = IX_NPEDL_INSTR_WR_REG_BYTE;
-	    mask = IX_NPEDL_MASK_LOWER_BYTE_OF_WORD;  break;
-	case IX_NPEDL_REG_SIZE_SHORT:
-            npeInstruction = IX_NPEDL_INSTR_WR_REG_SHORT;
-	    mask = IX_NPEDL_MASK_LOWER_SHORT_OF_WORD;  break;
-	}
-	/* mask out any redundant bits, so verify will work later */
-	regVal &= mask;
-
-	/* fill dest operand field of  instruction with destination reg addr */
-	npeInstruction |= (regAddr << IX_NPEDL_OFFSET_INSTR_DEST);
-
-	/* fill src operand field of instruction with least-sig 5 bits of val*/
-	npeInstruction |= ((regVal & IX_NPEDL_MASK_IMMED_INSTR_SRC_DATA) <<
-			   IX_NPEDL_OFFSET_INSTR_SRC);
-
-	/* fill coprocessor field of instruction with most-sig 11 bits of val*/
-	npeInstruction |= ((regVal & IX_NPEDL_MASK_IMMED_INSTR_COPROC_DATA) <<
-			   IX_NPEDL_DISPLACE_IMMED_INSTR_COPROC_DATA);
-
-	/* step execution of NPE intruction using Debug ECS */
-	status = ixNpeDlNpeMgrDebugInstructionExec(npeBaseAddress, npeInstruction,
-					  ctxtNum, IX_NPEDL_WR_INSTR_LDUR);
-					  
-	if (IX_SUCCESS != status)
-	{
-	    return status;  
-	} 
-    }/* condition: if reg to be written is 8-bit or 16-bit (not 32-bit) */
-
-    if (verify)
-    {
-	status = ixNpeDlNpeMgrLogicalRegRead (npeBaseAddress, regAddr,
-						   regSize, ctxtNum, &retRegVal);
-						   
-        if (IX_SUCCESS == status)
-        {
-            if (regVal != retRegVal)
-            {
-                status = IX_FAIL;
-            }
-        }        
-    }
-
-    IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT,
-		     "Exiting ixNpeDlNpeMgrLogicalRegWrite : status = %d\n",
-		     status);
-    
-    return status;
-}
-
-
-/*
- * Function definition: ixNpeDlNpeMgrPhysicalRegWrite
- */
-IX_STATUS
-ixNpeDlNpeMgrPhysicalRegWrite (
-    UINT32 npeBaseAddress,
-    UINT32 regAddr,
-    UINT32 regValue,
-    BOOL verify)
-{
-    IX_STATUS status;
-
-    IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT,
-		     "Entering ixNpeDlNpeMgrPhysicalRegWrite\n");
-
-/*
- * There are 32 physical registers used in an NPE.  These are
- * treated as 16 pairs of 32-bit registers.  To write one of the pair,
- * write the pair number (0-16) to the REGMAP for Context 0.  Then write
- * the value to register  0 or 4 in the regfile, depending on which
- * register of the pair is to be written
- */
-
-    /*
-     * set REGMAP for context 0 to (regAddr >> 1) to choose which pair (0-16)
-     * of physical registers to write 
-     */
-    status = ixNpeDlNpeMgrLogicalRegWrite (npeBaseAddress,
-					   IX_NPEDL_CTXT_REG_ADDR_REGMAP,
-					   (regAddr >>
-					  IX_NPEDL_OFFSET_PHYS_REG_ADDR_REGMAP),
-					   IX_NPEDL_REG_SIZE_SHORT, 0, verify);
-    if (status == IX_SUCCESS)
-    {
-	/* regAddr = 0 or 4  */
-	regAddr = (regAddr & IX_NPEDL_MASK_PHYS_REG_ADDR_LOGICAL_ADDR) *
-	    IX_NPEDL_BYTES_PER_WORD;
-    
-    status = ixNpeDlNpeMgrLogicalRegWrite (npeBaseAddress, regAddr, regValue, 
-					   IX_NPEDL_REG_SIZE_WORD, 0, verify);
-    }
-    
-    if (status != IX_SUCCESS)
-    {
-	IX_NPEDL_ERROR_REPORT ("ixNpeDlNpeMgrPhysicalRegWrite: "
-			       "error writing to physical register\n");
-    }
-
-    ixNpeDlNpeMgrUtilsStats.physicalRegWrites++;
-
-    IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT,
-		     "Exiting ixNpeDlNpeMgrPhysicalRegWrite : status = %d\n",
-		     status);
-    return status;
-}
-
-
-/*
- * Function definition: ixNpeDlNpeMgrCtxtRegWrite
- */
-IX_STATUS
-ixNpeDlNpeMgrCtxtRegWrite (
-    UINT32 npeBaseAddress,
-    UINT32 ctxtNum,
-    IxNpeDlCtxtRegNum ctxtReg,
-    UINT32 ctxtRegVal,
-    BOOL verify)
-{
-    UINT32 tempRegVal;
-    UINT32 ctxtRegAddr;
-    UINT32 ctxtRegSize;
-    IX_STATUS status = IX_SUCCESS;
-
-    IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT, 
-		     "Entering ixNpeDlNpeMgrCtxtRegWrite\n");
-
-    /*
-     * Context 0 has no STARTPC. Instead, this value is used to set
-     * NextPC for Background ECS, to set where NPE starts executing code
-     */
-    if ((ctxtNum == 0) && (ctxtReg == IX_NPEDL_CTXT_REG_STARTPC))
-    {
-	/* read BG_CTXT_REG_0, update NEXTPC bits, and write back to reg */
-	tempRegVal = ixNpeDlNpeMgrExecAccRegRead (npeBaseAddress,
-						  IX_NPEDL_ECS_BG_CTXT_REG_0);
-	tempRegVal &= ~IX_NPEDL_MASK_ECS_REG_0_NEXTPC;
-	tempRegVal |= (ctxtRegVal << IX_NPEDL_OFFSET_ECS_REG_0_NEXTPC) &
-	    IX_NPEDL_MASK_ECS_REG_0_NEXTPC;
-	
-	ixNpeDlNpeMgrExecAccRegWrite (npeBaseAddress,
-				      IX_NPEDL_ECS_BG_CTXT_REG_0, tempRegVal);
-
-	ixNpeDlNpeMgrUtilsStats.nextPcWrites++;
-    }
-    else
-    {
-	ctxtRegAddr = ixNpeDlCtxtRegAccInfo[ctxtReg].regAddress;
-	ctxtRegSize = ixNpeDlCtxtRegAccInfo[ctxtReg].regSize;
-	status = ixNpeDlNpeMgrLogicalRegWrite (npeBaseAddress, ctxtRegAddr,
-					       ctxtRegVal, ctxtRegSize,
-					       ctxtNum, verify);
-	if (status != IX_SUCCESS)
-	{
-	    IX_NPEDL_ERROR_REPORT ("ixNpeDlNpeMgrCtxtRegWrite: "
-				   "error writing to context store register\n");
-	}
-	
-	ixNpeDlNpeMgrUtilsStats.contextRegWrites++;
-    }
-
-    IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT, 
-		     "Exiting ixNpeDlNpeMgrCtxtRegWrite : status = %d\n",
-		     status);
-
-    return status;
-}
-
-
-/*
- * Function definition: ixNpeDlNpeMgrUtilsStatsShow
- */
-void
-ixNpeDlNpeMgrUtilsStatsShow (void)
-{
-    ixOsalLog (IX_OSAL_LOG_LVL_USER,
-               IX_OSAL_LOG_DEV_STDOUT,
-               "\nixNpeDlNpeMgrUtilsStatsShow:\n"
-               "\tInstruction Memory writes: %u\n"
-               "\tInstruction Memory writes failed: %u\n"
-               "\tData Memory writes: %u\n"
-               "\tData Memory writes failed: %u\n",
-               ixNpeDlNpeMgrUtilsStats.insMemWrites,
-               ixNpeDlNpeMgrUtilsStats.insMemWriteFails,
-               ixNpeDlNpeMgrUtilsStats.dataMemWrites,
-               ixNpeDlNpeMgrUtilsStats.dataMemWriteFails,
-               0,0);
-
-    ixOsalLog (IX_OSAL_LOG_LVL_USER,
-               IX_OSAL_LOG_DEV_STDOUT,
-               "\tExecuting Context Stack Register writes: %u\n"
-               "\tExecuting Context Stack Register reads: %u\n"
-               "\tPhysical Register writes: %u\n"
-               "\tContext Store Register writes: %u\n"
-               "\tExecution Backgound Context NextPC writes: %u\n"
-               "\tDebug Instructions Executed: %u\n\n",
-               ixNpeDlNpeMgrUtilsStats.ecsRegWrites,
-               ixNpeDlNpeMgrUtilsStats.ecsRegReads,
-               ixNpeDlNpeMgrUtilsStats.physicalRegWrites,
-               ixNpeDlNpeMgrUtilsStats.contextRegWrites,
-               ixNpeDlNpeMgrUtilsStats.nextPcWrites,
-               ixNpeDlNpeMgrUtilsStats.dbgInstructionExecs);
-}
-
-
-/*
- * Function definition: ixNpeDlNpeMgrUtilsStatsReset
- */
-void
-ixNpeDlNpeMgrUtilsStatsReset (void)
-{
-    ixNpeDlNpeMgrUtilsStats.insMemWrites = 0;
-    ixNpeDlNpeMgrUtilsStats.insMemWriteFails = 0;
-    ixNpeDlNpeMgrUtilsStats.dataMemWrites = 0;
-    ixNpeDlNpeMgrUtilsStats.dataMemWriteFails = 0;
-    ixNpeDlNpeMgrUtilsStats.ecsRegWrites = 0;
-    ixNpeDlNpeMgrUtilsStats.ecsRegReads = 0;
-    ixNpeDlNpeMgrUtilsStats.physicalRegWrites = 0;
-    ixNpeDlNpeMgrUtilsStats.contextRegWrites = 0;
-    ixNpeDlNpeMgrUtilsStats.nextPcWrites = 0;
-    ixNpeDlNpeMgrUtilsStats.dbgInstructionExecs = 0;
-}
diff --git a/arch/arm/cpu/ixp/npe/IxNpeMh.c b/arch/arm/cpu/ixp/npe/IxNpeMh.c
deleted file mode 100644
index 8703def..0000000
--- a/arch/arm/cpu/ixp/npe/IxNpeMh.c
+++ /dev/null
@@ -1,582 +0,0 @@
-/**
- * @file IxNpeMh.c
- *
- * @author Intel Corporation
- * @date 18 Jan 2002
- *
- * @brief This file contains the implementation of the public API for the
- * IXP425 NPE Message Handler component.
- *
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
-*/
-
-/*
- * Put the system defined include files required.
- */
-
-/*
- * Put the user defined include files required.
- */
-
-#include "IxOsal.h"
-#include "IxNpeMhMacros_p.h"
-
-#include "IxNpeMh.h"
-
-#include "IxNpeMhConfig_p.h"
-#include "IxNpeMhReceive_p.h"
-#include "IxNpeMhSend_p.h"
-#include "IxNpeMhSolicitedCbMgr_p.h"
-#include "IxNpeMhUnsolicitedCbMgr_p.h"
-
-/*
- * #defines and macros used in this file.
- */
-
-/*
- * Typedefs whose scope is limited to this file.
- */
-
-/*
- * Variable declarations global to this file only.  Externs are followed by
- * static variables.
- */
-
-PRIVATE BOOL ixNpeMhInitialized = FALSE;
-
-/*
- * Extern function prototypes.
- */
-
-/*
- * Static function prototypes.
- */
-
-/*
- * Function definition: ixNpeMhInitialize
- */
-
-PUBLIC IX_STATUS ixNpeMhInitialize (
-    IxNpeMhNpeInterrupts npeInterrupts)
-{
-    IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering "
-                     "ixNpeMhInitialize\n");
-
-    /* check the npeInterrupts parameter */
-    if ((npeInterrupts != IX_NPEMH_NPEINTERRUPTS_NO) &&
-        (npeInterrupts != IX_NPEMH_NPEINTERRUPTS_YES))
-    {
-        IX_NPEMH_ERROR_REPORT ("Illegal npeInterrupts parameter value\n");
-        return IX_FAIL;
-    }
-
-    /* parameters are ok ... */
-
-    /* initialize the Receive module */
-    ixNpeMhReceiveInitialize ();
-
-    /* initialize the Solicited Callback Manager module */
-    ixNpeMhSolicitedCbMgrInitialize ();
-
-    /* initialize the Unsolicited Callback Manager module */
-    ixNpeMhUnsolicitedCbMgrInitialize ();
-
-    /* initialize the Configuration module
-     *
-     * NOTE: This module was originally configured before the
-     * others, but the sequence was changed so that interrupts
-     * would only be enabled after the handler functions were
-     * set up.  The above modules need to be initialised to
-     * handle the NPE interrupts.  See SCR #2231.
-     */
-    ixNpeMhConfigInitialize (npeInterrupts);
-
-    ixNpeMhInitialized = TRUE;
-
-    IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting "
-                     "ixNpeMhInitialize\n");
-
-    return IX_SUCCESS;
-}
-
-/*
- * Function definition: ixNpeMhUnload
- */
-
-PUBLIC IX_STATUS ixNpeMhUnload (void)
-{
-    IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering "
-                     "ixNpeMhUnload\n");
-
-    if (!ixNpeMhInitialized)
-    {
-	return IX_FAIL;
-    }
-
-    /* Uninitialize the Configuration module */
-    ixNpeMhConfigUninit ();
-
-    ixNpeMhInitialized = FALSE;
-
-    IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting "
-                     "ixNpeMhUnload\n");
-
-    return IX_SUCCESS;
-}
-
-
-/*
- * Function definition: ixNpeMhUnsolicitedCallbackRegister
- */
-
-PUBLIC IX_STATUS ixNpeMhUnsolicitedCallbackRegister (
-    IxNpeMhNpeId npeId,
-    IxNpeMhMessageId messageId,
-    IxNpeMhCallback unsolicitedCallback)
-{
-    IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering "
-                     "ixNpeMhUnsolicitedCallbackRegister\n");
-
-    /* check that we are initialized */
-    if (!ixNpeMhInitialized)
-    {
-        IX_NPEMH_ERROR_REPORT ("IxNpeMh component is not initialized\n");
-        return IX_FAIL;
-    }
-
-    /* check the npeId parameter */
-    if (!ixNpeMhConfigNpeIdIsValid (npeId))
-    {
-        IX_NPEMH_ERROR_REPORT ("NPE ID invalid\n");
-        return IX_FAIL;
-    }
-
-    /* check the messageId parameter */
-    if ((messageId < IX_NPEMH_MIN_MESSAGE_ID)
-        || (messageId > IX_NPEMH_MAX_MESSAGE_ID))
-    {
-        IX_NPEMH_ERROR_REPORT ("Message ID is out of range\n");
-        return IX_FAIL;
-    }
-
-    /* the unsolicitedCallback parameter is allowed to be NULL */
-
-    /* parameters are ok ... */
-
-    /* get the lock to prevent other clients from entering */
-    ixNpeMhConfigLockGet (npeId);
-
-    /* save the unsolicited callback for the message ID */
-    ixNpeMhUnsolicitedCbMgrCallbackSave (
-        npeId, messageId, unsolicitedCallback);
-
-    /* release the lock to allow other clients back in */
-    ixNpeMhConfigLockRelease (npeId);
-
-    IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting "
-                     "ixNpeMhUnsolicitedCallbackRegister\n");
-
-    return IX_SUCCESS;
-}
-
-/*
- * Function definition: ixNpeMhUnsolicitedCallbackForRangeRegister
- */
-
-PUBLIC IX_STATUS ixNpeMhUnsolicitedCallbackForRangeRegister (
-    IxNpeMhNpeId npeId,
-    IxNpeMhMessageId minMessageId,
-    IxNpeMhMessageId maxMessageId,
-    IxNpeMhCallback unsolicitedCallback)
-{
-    IxNpeMhMessageId messageId;
-
-    IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering "
-                     "ixNpeMhUnsolicitedCallbackForRangeRegister\n");
-
-    /* check that we are initialized */
-    if (!ixNpeMhInitialized)
-    {
-        IX_NPEMH_ERROR_REPORT ("IxNpeMh component is not initialized\n");
-        return IX_FAIL;
-    }
-
-    /* check the npeId parameter */
-    if (!ixNpeMhConfigNpeIdIsValid (npeId))
-    {
-        IX_NPEMH_ERROR_REPORT ("NPE ID invalid\n");
-        return IX_FAIL;
-    }
-
-    /* check the minMessageId parameter */
-    if ((minMessageId < IX_NPEMH_MIN_MESSAGE_ID)
-        || (minMessageId > IX_NPEMH_MAX_MESSAGE_ID))
-    {
-        IX_NPEMH_ERROR_REPORT ("Min message ID is out of range\n");
-        return IX_FAIL;
-    }
-
-    /* check the maxMessageId parameter */
-    if ((maxMessageId < IX_NPEMH_MIN_MESSAGE_ID)
-        || (maxMessageId > IX_NPEMH_MAX_MESSAGE_ID))
-    {
-        IX_NPEMH_ERROR_REPORT ("Max message ID is out of range\n");
-        return IX_FAIL;
-    }
-
-    /* check the semantics of the message range parameters */
-    if (minMessageId > maxMessageId)
-    {
-        IX_NPEMH_ERROR_REPORT ("Min message ID greater than max message "
-                               "ID\n");
-        return IX_FAIL;
-    }
-
-    /* the unsolicitedCallback parameter is allowed to be NULL */
-
-    /* parameters are ok ... */
-
-    /* get the lock to prevent other clients from entering */
-    ixNpeMhConfigLockGet (npeId);
-
-    /* for each message ID in the range ... */
-    for (messageId = minMessageId; messageId <= maxMessageId; messageId++)
-    {
-        /* save the unsolicited callback for the message ID */
-        ixNpeMhUnsolicitedCbMgrCallbackSave (
-            npeId, messageId, unsolicitedCallback);
-    }
-
-    /* release the lock to allow other clients back in */
-    ixNpeMhConfigLockRelease (npeId);
-
-    IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting "
-                     "ixNpeMhUnsolicitedCallbackForRangeRegister\n");
-
-    return IX_SUCCESS;
-}
-
-/*
- * Function definition: ixNpeMhMessageSend
- */
-
-PUBLIC IX_STATUS ixNpeMhMessageSend (
-    IxNpeMhNpeId npeId,
-    IxNpeMhMessage message,
-    UINT32 maxSendRetries)
-{
-    IX_STATUS status = IX_SUCCESS;
-
-    IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering "
-                     "ixNpeMhMessageSend\n");
-
-    /* check that we are initialized */
-    if (!ixNpeMhInitialized)
-    {
-        IX_NPEMH_ERROR_REPORT ("IxNpeMh component is not initialized\n");
-        return IX_FAIL;
-    }
-
-    /* check the npeId parameter */
-    if (!ixNpeMhConfigNpeIdIsValid (npeId))
-    {
-        IX_NPEMH_ERROR_REPORT ("NPE ID invalid\n");
-        return IX_FAIL;
-    }
-
-    /* parameters are ok ... */
-
-    /* get the lock to prevent other clients from entering */
-    ixNpeMhConfigLockGet (npeId);
-
-    /* send the message */
-    status = ixNpeMhSendMessageSend (npeId, message, maxSendRetries);
-    if (status != IX_SUCCESS)
-    {
-        IX_NPEMH_ERROR_REPORT ("Failed to send message\n");
-    }
-
-    /* release the lock to allow other clients back in */
-    ixNpeMhConfigLockRelease (npeId);
-
-    IX_NPEMH_TRACE1 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting "
-                     "ixNpeMhMessageSend"
-                     " : status = %d\n", status);
-
-    return status;
-}
-
-/*
- * Function definition: ixNpeMhMessageWithResponseSend
- */
-
-PUBLIC IX_STATUS ixNpeMhMessageWithResponseSend (
-    IxNpeMhNpeId npeId,
-    IxNpeMhMessage message,
-    IxNpeMhMessageId solicitedMessageId,
-    IxNpeMhCallback solicitedCallback,
-    UINT32 maxSendRetries)
-{
-    IX_STATUS status = IX_SUCCESS;
-    IxNpeMhCallback unsolicitedCallback = NULL;
-
-    IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering "
-                     "ixNpeMhMessageWithResponseSend\n");
-
-    /* check that we are initialized */
-    if (!ixNpeMhInitialized)
-    {
-        IX_NPEMH_ERROR_REPORT ("IxNpeMh component is not initialized\n");
-        return IX_FAIL;
-    }
-
-    /* the solicitecCallback parameter is allowed to be NULL.  this */
-    /* signifies the client is not interested in the response message */
-
-    /* check the npeId parameter */
-    if (!ixNpeMhConfigNpeIdIsValid (npeId))
-    {
-        IX_NPEMH_ERROR_REPORT ("NPE ID invalid\n");
-        return IX_FAIL;
-    }
-
-    /* check the solicitedMessageId parameter */
-    if ((solicitedMessageId < IX_NPEMH_MIN_MESSAGE_ID)
-        || (solicitedMessageId > IX_NPEMH_MAX_MESSAGE_ID))
-    {
-        IX_NPEMH_ERROR_REPORT ("Solicited message ID is out of range\n");
-        return IX_FAIL;
-    }
-
-    /* check the solicitedMessageId parameter.  if an unsolicited */
-    /* callback has been registered for the specified message ID then */
-    /* report an error and return failure */
-    ixNpeMhUnsolicitedCbMgrCallbackRetrieve (
-        npeId, solicitedMessageId, &unsolicitedCallback);
-    if (unsolicitedCallback != NULL)
-    {
-        IX_NPEMH_ERROR_REPORT ("Solicited message ID conflicts with "
-                               "unsolicited message ID\n");
-        return IX_FAIL;
-    }
-
-    /* parameters are ok ... */
-
-    /* get the lock to prevent other clients from entering */
-    ixNpeMhConfigLockGet (npeId);
-
-    /* send the message */
-    status = ixNpeMhSendMessageWithResponseSend (
-        npeId, message, solicitedMessageId, solicitedCallback,
-        maxSendRetries);
-    if (status != IX_SUCCESS)
-    {
-        IX_NPEMH_ERROR_REPORT ("Failed to send message\n");
-    }
-
-    /* release the lock to allow other clients back in */
-    ixNpeMhConfigLockRelease (npeId);
-
-    IX_NPEMH_TRACE1 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting "
-                     "ixNpeMhMessageWithResponseSend"
-                     " : status = %d\n", status);
-
-    return status;
-}
-
-/*
- * Function definition: ixNpeMhMessagesReceive
- */
-
-PUBLIC IX_STATUS ixNpeMhMessagesReceive (
-    IxNpeMhNpeId npeId)
-{
-    IX_STATUS status = IX_SUCCESS;
-
-    IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering "
-                     "ixNpeMhMessagesReceive\n");
-
-    /* check that we are initialized */
-    if (!ixNpeMhInitialized)
-    {
-        IX_NPEMH_ERROR_REPORT ("IxNpeMh component is not initialized\n");
-        return IX_FAIL;
-    }
-
-    /* check the npeId parameter */
-    if (!ixNpeMhConfigNpeIdIsValid (npeId))
-    {
-        IX_NPEMH_ERROR_REPORT ("NPE ID invalid\n");
-        return IX_FAIL;
-    }
-
-    /* parameters are ok ... */
-
-    /* get the lock to prevent other clients from entering */
-    ixNpeMhConfigLockGet (npeId);
-
-    /* receive messages from the NPE */
-    status = ixNpeMhReceiveMessagesReceive (npeId);
-
-    if (status != IX_SUCCESS)
-    {
-        IX_NPEMH_ERROR_REPORT ("Failed to receive message\n");
-    }
-
-    /* release the lock to allow other clients back in */
-    ixNpeMhConfigLockRelease (npeId);
-
-    IX_NPEMH_TRACE1 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting "
-                     "ixNpeMhMessagesReceive"
-                     " : status = %d\n", status);
-
-    return status;
-}
-
-/*
- * Function definition: ixNpeMhShow
- */
-
-PUBLIC IX_STATUS ixNpeMhShow (
-    IxNpeMhNpeId npeId)
-{
-    IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering "
-                     "ixNpeMhShow\n");
-
-    /* check that we are initialized */
-    if (!ixNpeMhInitialized)
-    {
-        IX_NPEMH_ERROR_REPORT ("IxNpeMh component is not initialized\n");
-        return IX_FAIL;
-    }
-
-    /* check the npeId parameter */
-    if (!ixNpeMhConfigNpeIdIsValid (npeId))
-    {
-        IX_NPEMH_ERROR_REPORT ("NPE ID invalid\n");
-        return IX_FAIL;
-    }
-
-    /* parameters are ok ... */
-
-    /* note we don't get the lock here as printing the statistics */
-    /* to a console may take some time and we don't want to impact */
-    /* system performance.  this means that the statistics displayed */
-    /* may be in a state of flux and make not represent a consistent */
-    /* snapshot. */
-
-    /* display a header */
-    ixOsalLog (IX_OSAL_LOG_LVL_USER, IX_OSAL_LOG_DEV_STDOUT,
-	       "Current state of NPE ID %d:\n\n", npeId, 0, 0, 0, 0, 0);
-
-    /* show the current state of each module */
-
-    /* show the current state of the Configuration module */
-    ixNpeMhConfigShow (npeId);
-
-    /* show the current state of the Receive module */
-    ixNpeMhReceiveShow (npeId);
-
-    /* show the current state of the Send module */
-    ixNpeMhSendShow (npeId);
-
-    /* show the current state of the Solicited Callback Manager module */
-    ixNpeMhSolicitedCbMgrShow (npeId);
-
-    /* show the current state of the Unsolicited Callback Manager module */
-    ixNpeMhUnsolicitedCbMgrShow (npeId);
-
-    IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting "
-                     "ixNpeMhShow\n");
-
-    return IX_SUCCESS;
-}
-
-/*
- * Function definition: ixNpeMhShowReset
- */
-
-PUBLIC IX_STATUS ixNpeMhShowReset (
-    IxNpeMhNpeId npeId)
-{
-    IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering "
-                     "ixNpeMhShowReset\n");
-
-    /* check that we are initialized */
-    if (!ixNpeMhInitialized)
-    {
-        IX_NPEMH_ERROR_REPORT ("IxNpeMh component is not initialized\n");
-        return IX_FAIL;
-    }
-
-    /* check the npeId parameter */
-    if (!ixNpeMhConfigNpeIdIsValid (npeId))
-    {
-        IX_NPEMH_ERROR_REPORT ("NPE ID invalid\n");
-        return IX_FAIL;
-    }
-
-    /* parameters are ok ... */
-
-    /* note we don't get the lock here as resetting the statistics */
-    /* shouldn't impact system performance. */
-
-    /* reset the current state of each module */
-
-    /* reset the current state of the Configuration module */
-    ixNpeMhConfigShowReset (npeId);
-
-    /* reset the current state of the Receive module */
-    ixNpeMhReceiveShowReset (npeId);
-
-    /* reset the current state of the Send module */
-    ixNpeMhSendShowReset (npeId);
-
-    /* reset the current state of the Solicited Callback Manager module */
-    ixNpeMhSolicitedCbMgrShowReset (npeId);
-
-    /* reset the current state of the Unsolicited Callback Manager module */
-    ixNpeMhUnsolicitedCbMgrShowReset (npeId);
-
-    IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting "
-                     "ixNpeMhShowReset\n");
-
-    return IX_SUCCESS;
-}
diff --git a/arch/arm/cpu/ixp/npe/IxNpeMhConfig.c b/arch/arm/cpu/ixp/npe/IxNpeMhConfig.c
deleted file mode 100644
index 50c8f21..0000000
--- a/arch/arm/cpu/ixp/npe/IxNpeMhConfig.c
+++ /dev/null
@@ -1,608 +0,0 @@
-/**
- * @file IxNpeMhConfig.c
- *
- * @author Intel Corporation
- * @date 18 Jan 2002
- *
- * @brief This file contains the implementation of the private API for the
- * Configuration module.
- *
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- * 
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- * 
- * @par
- * -- End of Copyright Notice --
-*/
-
-/*
- * Put the system defined include files required.
- */
-
-
-/*
- * Put the user defined include files required.
- */
-
-#include "IxOsal.h"
-
-#include "IxNpeMhMacros_p.h"
-
-#include "IxNpeMhConfig_p.h"
-
-/*
- * #defines and macros used in this file.
- */
-#define IX_NPE_MH_MAX_NUM_OF_RETRIES 1000000 /**< Maximum number of
-                                              * retries before
-                                              * timeout
-					                          */  
-
-/*
- * Typedefs whose scope is limited to this file.
- */
-
-/**
- * @struct IxNpeMhConfigStats
- *
- * @brief This structure is used to maintain statistics for the
- * Configuration module.
- */
-
-typedef struct
-{
-    UINT32 outFifoReads;        /**< outFifo reads */
-    UINT32 inFifoWrites;        /**< inFifo writes */
-    UINT32 maxInFifoFullRetries;   /**< max retries if inFIFO full   */
-    UINT32 maxOutFifoEmptyRetries; /**< max retries if outFIFO empty */
-} IxNpeMhConfigStats;
-
-/*
- * Variable declarations global to this file only.  Externs are followed by
- * static variables.
- */
-
-IxNpeMhConfigNpeInfo ixNpeMhConfigNpeInfo[IX_NPEMH_NUM_NPES] =
-{
-    {
-        0,
-        IX_NPEMH_NPEA_INT,
-	0,
-        0,
-        0,
-        0,
-        0,
-        NULL,
-        FALSE
-    },
-    {
-        0,
-        IX_NPEMH_NPEB_INT,
-	0,
-	0,
-        0,
-        0,
-        0,
-        NULL,
-        FALSE
-    },
-    {
-        0,
-        IX_NPEMH_NPEC_INT,
-        0,
-        0,
-        0,
-        0,
-        0,
-        NULL,
-        FALSE
-    }
-};
-
-PRIVATE IxNpeMhConfigStats ixNpeMhConfigStats[IX_NPEMH_NUM_NPES];
-
-/*
- * Extern function prototypes.
- */
-
-/*
- * Static function prototypes.
- */
-PRIVATE
-void ixNpeMhConfigIsr (void *parameter);
-
-/*
- * Function definition: ixNpeMhConfigIsr
- */
-
-PRIVATE
-void ixNpeMhConfigIsr (void *parameter)
-{
-    IxNpeMhNpeId npeId = (IxNpeMhNpeId)parameter;
-    UINT32 ofint;
-    volatile UINT32 *statusReg =
-        (UINT32 *)ixNpeMhConfigNpeInfo[npeId].statusRegister;
-
-    IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering "
-                     "ixNpeMhConfigIsr\n");
-
-    /* get the OFINT (OutFifo interrupt) bit of the status register */
-    IX_NPEMH_REGISTER_READ_BITS (statusReg, &ofint, IX_NPEMH_NPE_STAT_OFINT);
-
-    /* if the OFINT status bit is set */
-    if (ofint)
-    {
-        /* if there is an ISR registered for this NPE */
-        if (ixNpeMhConfigNpeInfo[npeId].isr != NULL)
-        {
-            /* invoke the ISR routine */
-            ixNpeMhConfigNpeInfo[npeId].isr (npeId);
-        }
-        else
-        {
-            /* if we don't service the interrupt the NPE will continue */
-            /* to trigger the interrupt indefinitely */
-            IX_NPEMH_ERROR_REPORT ("No ISR registered to service "
-                                   "interrupt\n");
-        }
-    }
-
-    IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting "
-                     "ixNpeMhConfigIsr\n");
-}
-
-/*
- * Function definition: ixNpeMhConfigInitialize
- */
-
-void ixNpeMhConfigInitialize (
-    IxNpeMhNpeInterrupts npeInterrupts)
-{
-    IxNpeMhNpeId npeId;
-    UINT32 virtualAddr[IX_NPEMH_NUM_NPES];
-
-    IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering "
-                     "ixNpeMhConfigInitialize\n");
-
-    /* Request a mapping for the NPE-A config register address space */
-    virtualAddr[IX_NPEMH_NPEID_NPEA] =
-	(UINT32) IX_OSAL_MEM_MAP (IX_NPEMH_NPEA_BASE,
-				     IX_OSAL_IXP400_NPEA_MAP_SIZE);
-    IX_OSAL_ASSERT (virtualAddr[IX_NPEMH_NPEID_NPEA]);
-
-    /* Request a mapping for the NPE-B config register address space */
-    virtualAddr[IX_NPEMH_NPEID_NPEB] =
-	(UINT32) IX_OSAL_MEM_MAP (IX_NPEMH_NPEB_BASE,
-				     IX_OSAL_IXP400_NPEB_MAP_SIZE);
-    IX_OSAL_ASSERT (virtualAddr[IX_NPEMH_NPEID_NPEB]);
-    
-    /* Request a mapping for the NPE-C config register address space */
-    virtualAddr[IX_NPEMH_NPEID_NPEC] =
-	(UINT32) IX_OSAL_MEM_MAP (IX_NPEMH_NPEC_BASE,
-				     IX_OSAL_IXP400_NPEC_MAP_SIZE);
-    IX_OSAL_ASSERT (virtualAddr[IX_NPEMH_NPEID_NPEC]);
-
-    /* for each NPE ... */
-    for (npeId = 0; npeId < IX_NPEMH_NUM_NPES; npeId++)
-    {
-        /* declare a convenience pointer */
-        IxNpeMhConfigNpeInfo *npeInfo = &ixNpeMhConfigNpeInfo[npeId];
-	
-	/* store the virtual addresses of the NPE registers for later use */
-	npeInfo->virtualRegisterBase  = virtualAddr[npeId];
-	npeInfo->statusRegister  = virtualAddr[npeId] + IX_NPEMH_NPESTAT_OFFSET;
-	npeInfo->controlRegister = virtualAddr[npeId] + IX_NPEMH_NPECTL_OFFSET;
-	npeInfo->inFifoRegister  = virtualAddr[npeId] + IX_NPEMH_NPEFIFO_OFFSET;
-	npeInfo->outFifoRegister = virtualAddr[npeId] + IX_NPEMH_NPEFIFO_OFFSET;
-
-        /* for test purposes - to verify the register addresses */
-        IX_NPEMH_TRACE2 (IX_NPEMH_DEBUG, "NPE %d status register  = "
-                         "0x%08X\n", npeId, npeInfo->statusRegister);
-        IX_NPEMH_TRACE2 (IX_NPEMH_DEBUG, "NPE %d control register = "
-                         "0x%08X\n", npeId, npeInfo->controlRegister);
-        IX_NPEMH_TRACE2 (IX_NPEMH_DEBUG, "NPE %d inFifo register  = "
-                         "0x%08X\n", npeId, npeInfo->inFifoRegister);
-        IX_NPEMH_TRACE2 (IX_NPEMH_DEBUG, "NPE %d outFifo register = "
-                         "0x%08X\n", npeId, npeInfo->outFifoRegister);
-
-        /* connect our ISR to the NPE interrupt */
-        (void) ixOsalIrqBind (
-            npeInfo->interruptId, ixNpeMhConfigIsr, (void *)npeId);
-
-        /* initialise a mutex for this NPE */
-        (void) ixOsalMutexInit (&npeInfo->mutex);
-
-        /* if we should service the NPE's "outFIFO not empty" interrupt */
-        if (npeInterrupts == IX_NPEMH_NPEINTERRUPTS_YES)
-        {
-            /* enable the NPE's "outFIFO not empty" interrupt */
-            ixNpeMhConfigNpeInterruptEnable (npeId);
-        }
-        else
-        {
-            /* disable the NPE's "outFIFO not empty" interrupt */
-            ixNpeMhConfigNpeInterruptDisable (npeId);
-        }
-    }
-
-    IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting "
-                     "ixNpeMhConfigInitialize\n");
-}
-
-/*
- * Function definition: ixNpeMhConfigUninit
- */
-
-void ixNpeMhConfigUninit (void)
-{
-    IxNpeMhNpeId npeId;
-
-    IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering "
-                     "ixNpeMhConfigUninit\n");
-
-    /* for each NPE ... */
-    for (npeId = 0; npeId < IX_NPEMH_NUM_NPES; npeId++)
-    {
-        /* declare a convenience pointer */
-        IxNpeMhConfigNpeInfo *npeInfo = &ixNpeMhConfigNpeInfo[npeId];
-        
-        /* disconnect ISR */
-        ixOsalIrqUnbind(npeInfo->interruptId);
-
-        /* destroy mutex associated with this NPE */
-        ixOsalMutexDestroy(&npeInfo->mutex);
-	
-	IX_OSAL_MEM_UNMAP (npeInfo->virtualRegisterBase);
-
-	npeInfo->virtualRegisterBase  = 0;
-	npeInfo->statusRegister  = 0;
-	npeInfo->controlRegister = 0;
-	npeInfo->inFifoRegister  = 0;
-	npeInfo->outFifoRegister = 0;
-    }
-
-    IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting "
-                     "ixNpeMhConfigUninit\n");
-}
-
-/*
- * Function definition: ixNpeMhConfigIsrRegister
- */
-
-void ixNpeMhConfigIsrRegister (
-    IxNpeMhNpeId npeId,
-    IxNpeMhConfigIsr isr)
-{
-    IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering "
-                     "ixNpeMhConfigIsrRegister\n");
-
-    /* check if there is already an ISR registered for this NPE */
-    if (ixNpeMhConfigNpeInfo[npeId].isr != NULL)
-    {
-        IX_NPEMH_TRACE0 (IX_NPEMH_DEBUG, "Over-writing registered NPE ISR\n");
-    }
-
-    /* save the ISR routine with the NPE info */
-    ixNpeMhConfigNpeInfo[npeId].isr = isr;
-
-    IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting "
-                     "ixNpeMhConfigIsrRegister\n");
-}
-
-/*
- * Function definition: ixNpeMhConfigNpeInterruptEnable
- */
-
-BOOL ixNpeMhConfigNpeInterruptEnable (
-    IxNpeMhNpeId npeId)
-{
-    UINT32 ofe;
-    volatile UINT32 *controlReg =
-        (UINT32 *)ixNpeMhConfigNpeInfo[npeId].controlRegister;
-
-    /* get the OFE (OutFifoEnable) bit of the control register */
-    IX_NPEMH_REGISTER_READ_BITS (controlReg, &ofe, IX_NPEMH_NPE_CTL_OFE);
-
-    /* if the interrupt is disabled then we must enable it */
-    if (!ofe)
-    {
-        /* set the OFE (OutFifoEnable) bit of the control register */
-        /* we must set the OFEWE (OutFifoEnableWriteEnable) at the same */
-        /* time for the write to have effect */
-        IX_NPEMH_REGISTER_WRITE_BITS (controlReg,
-                                      (IX_NPEMH_NPE_CTL_OFE |
-                                       IX_NPEMH_NPE_CTL_OFEWE),
-                                      (IX_NPEMH_NPE_CTL_OFE |
-                                       IX_NPEMH_NPE_CTL_OFEWE));
-    }
-
-    /* return the previous state of the interrupt */
-    return (ofe != 0);
-}
-
-/*
- * Function definition: ixNpeMhConfigNpeInterruptDisable
- */
-
-BOOL ixNpeMhConfigNpeInterruptDisable (
-    IxNpeMhNpeId npeId)
-{
-    UINT32 ofe;
-    volatile UINT32 *controlReg =
-        (UINT32 *)ixNpeMhConfigNpeInfo[npeId].controlRegister;
-
-    /* get the OFE (OutFifoEnable) bit of the control register */
-    IX_NPEMH_REGISTER_READ_BITS (controlReg, &ofe, IX_NPEMH_NPE_CTL_OFE);
-
-    /* if the interrupt is enabled then we must disable it */
-    if (ofe)
-    {
-        /* unset the OFE (OutFifoEnable) bit of the control register */
-        /* we must set the OFEWE (OutFifoEnableWriteEnable) at the same */
-        /* time for the write to have effect */
-        IX_NPEMH_REGISTER_WRITE_BITS (controlReg,
-                                      (0                    |
-                                       IX_NPEMH_NPE_CTL_OFEWE),
-                                      (IX_NPEMH_NPE_CTL_OFE |
-                                       IX_NPEMH_NPE_CTL_OFEWE));
-    }
-
-    /* return the previous state of the interrupt */
-    return (ofe != 0);
-}
-
-/*
- * Function definition: ixNpeMhConfigMessageIdGet
- */
-
-IxNpeMhMessageId ixNpeMhConfigMessageIdGet (
-    IxNpeMhMessage message)
-{
-    /* return the most-significant byte of the first word of the */
-    /* message */
-    return ((IxNpeMhMessageId) ((message.data[0] >> 24) & 0xFF));
-}
-
-/*
- * Function definition: ixNpeMhConfigNpeIdIsValid
- */
-
-BOOL ixNpeMhConfigNpeIdIsValid (
-    IxNpeMhNpeId npeId)
-{
-    /* check that the npeId parameter is within the range of valid IDs */
-    return (npeId >= 0 && npeId < IX_NPEMH_NUM_NPES);
-}
-
-/*
- * Function definition: ixNpeMhConfigLockGet
- */
-
-void ixNpeMhConfigLockGet (
-    IxNpeMhNpeId npeId)
-{
-    IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering "
-                     "ixNpeMhConfigLockGet\n");
-
-    /* lock the mutex for this NPE */
-    (void) ixOsalMutexLock (&ixNpeMhConfigNpeInfo[npeId].mutex, 
-			    IX_OSAL_WAIT_FOREVER);
-
-    /* disable the NPE's "outFIFO not empty" interrupt */
-    ixNpeMhConfigNpeInfo[npeId].oldInterruptState =
-        ixNpeMhConfigNpeInterruptDisable (npeId);
-
-    IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting "
-                     "ixNpeMhConfigLockGet\n");
-}
-
-/*
- * Function definition: ixNpeMhConfigLockRelease
- */
-
-void ixNpeMhConfigLockRelease (
-    IxNpeMhNpeId npeId)
-{
-    IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering "
-                     "ixNpeMhConfigLockRelease\n");
-
-    /* if the interrupt was previously enabled */
-    if (ixNpeMhConfigNpeInfo[npeId].oldInterruptState)
-    {
-        /* enable the NPE's "outFIFO not empty" interrupt */
-        ixNpeMhConfigNpeInfo[npeId].oldInterruptState =
-            ixNpeMhConfigNpeInterruptEnable (npeId);
-    }
-
-    /* unlock the mutex for this NPE */
-    (void) ixOsalMutexUnlock (&ixNpeMhConfigNpeInfo[npeId].mutex);
-
-    IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting "
-                     "ixNpeMhConfigLockRelease\n");
-}
-
-/*
- * Function definition: ixNpeMhConfigInFifoWrite
- */
-
-IX_STATUS ixNpeMhConfigInFifoWrite (
-    IxNpeMhNpeId npeId,
-    IxNpeMhMessage message)
-{
-    volatile UINT32 *npeInFifo =
-        (UINT32 *)ixNpeMhConfigNpeInfo[npeId].inFifoRegister;
-    UINT32 retriesCount = 0;
-
-    /* write the first word of the message to the NPE's inFIFO */
-    IX_NPEMH_REGISTER_WRITE (npeInFifo, message.data[0]);
-
-    /* need to wait for room to write second word - see SCR #493,
-       poll for maximum number of retries, if exceed maximum
-       retries, exit from while loop */
-    while ((IX_NPE_MH_MAX_NUM_OF_RETRIES > retriesCount)
-        && ixNpeMhConfigInFifoIsFull (npeId))
-    {
-        retriesCount++;
-    }
-
-    /* Return TIMEOUT status to caller, indicate that NPE Hang / Halt */
-    if (IX_NPE_MH_MAX_NUM_OF_RETRIES == retriesCount)
-    {
-        return IX_NPEMH_CRITICAL_NPE_ERR;   
-    }    
-    
-    /* write the second word of the message to the NPE's inFIFO */
-    IX_NPEMH_REGISTER_WRITE (npeInFifo, message.data[1]);
-
-    /* record in the stats the maximum number of retries needed */
-    if (ixNpeMhConfigStats[npeId].maxInFifoFullRetries < retriesCount)
-    {
-	ixNpeMhConfigStats[npeId].maxInFifoFullRetries = retriesCount;
-    }
-
-    /* update statistical info */
-    ixNpeMhConfigStats[npeId].inFifoWrites++;
-    
-    return IX_SUCCESS;
-}
-
-/*
- * Function definition: ixNpeMhConfigOutFifoRead
- */
-
-IX_STATUS ixNpeMhConfigOutFifoRead (
-    IxNpeMhNpeId npeId,
-    IxNpeMhMessage *message)
-{
-    volatile UINT32 *npeOutFifo =
-        (UINT32 *)ixNpeMhConfigNpeInfo[npeId].outFifoRegister;
-    UINT32 retriesCount = 0;
-
-    /* read the first word of the message from the NPE's outFIFO */
-    IX_NPEMH_REGISTER_READ (npeOutFifo, &message->data[0]);
-
-    /* need to wait for NPE to write second word - see SCR #493 
-       poll for maximum number of retries, if exceed maximum
-       retries, exit from while loop */
-    while ((IX_NPE_MH_MAX_NUM_OF_RETRIES > retriesCount)
-        && ixNpeMhConfigOutFifoIsEmpty (npeId))
-    {
-        retriesCount++;
-    }
-
-    /* Return TIMEOUT status to caller, indicate that NPE Hang / Halt */
-    if (IX_NPE_MH_MAX_NUM_OF_RETRIES == retriesCount)
-    {
-        return IX_NPEMH_CRITICAL_NPE_ERR;   
-    } 
-    
-    /* read the second word of the message from the NPE's outFIFO */
-    IX_NPEMH_REGISTER_READ (npeOutFifo, &message->data[1]);
-
-    /* record in the stats the maximum number of retries needed */
-    if (ixNpeMhConfigStats[npeId].maxOutFifoEmptyRetries < retriesCount)
-    {
-	ixNpeMhConfigStats[npeId].maxOutFifoEmptyRetries = retriesCount;
-    }
-
-    /* update statistical info */
-    ixNpeMhConfigStats[npeId].outFifoReads++;
-    
-    return IX_SUCCESS;
-}
-
-/*
- * Function definition: ixNpeMhConfigShow
- */
-
-void ixNpeMhConfigShow (
-    IxNpeMhNpeId npeId)
-{
-    /* show the message fifo read counter */
-    IX_NPEMH_SHOW ("Message FIFO reads",
-                   ixNpeMhConfigStats[npeId].outFifoReads);
-
-    /* show the message fifo write counter */
-    IX_NPEMH_SHOW ("Message FIFO writes",
-                   ixNpeMhConfigStats[npeId].inFifoWrites);
-
-    /* show the max retries performed when inFIFO full */
-    IX_NPEMH_SHOW ("Max inFIFO Full retries",
-		   ixNpeMhConfigStats[npeId].maxInFifoFullRetries);
-
-    /* show the max retries performed when outFIFO empty */
-    IX_NPEMH_SHOW ("Max outFIFO Empty retries",
-		   ixNpeMhConfigStats[npeId].maxOutFifoEmptyRetries);
-
-    /* show the current status of the inFifo */
-    ixOsalLog (IX_OSAL_LOG_LVL_USER, IX_OSAL_LOG_DEV_STDOUT,
-	       "InFifo is %s and %s\n",
-	       (ixNpeMhConfigInFifoIsEmpty (npeId) ? 
-		(int) "EMPTY" : (int) "NOT EMPTY"),
-	       (ixNpeMhConfigInFifoIsFull (npeId) ? 
-		(int) "FULL" : (int) "NOT FULL"),
-	       0, 0, 0, 0);
-
-    /* show the current status of the outFifo */
-    ixOsalLog (IX_OSAL_LOG_LVL_USER, IX_OSAL_LOG_DEV_STDOUT,
-	       "OutFifo is %s and %s\n",
-	       (ixNpeMhConfigOutFifoIsEmpty (npeId) ? 
-		(int) "EMPTY" : (int) "NOT EMPTY"),
-	       (ixNpeMhConfigOutFifoIsFull (npeId) ? 
-		(int) "FULL" : (int) "NOT FULL"),
-	       0, 0, 0, 0);
-}
-
-/*
- * Function definition: ixNpeMhConfigShowReset
- */
-
-void ixNpeMhConfigShowReset (
-    IxNpeMhNpeId npeId)
-{
-    /* reset the message fifo read counter */
-    ixNpeMhConfigStats[npeId].outFifoReads = 0;
-
-    /* reset the message fifo write counter */
-    ixNpeMhConfigStats[npeId].inFifoWrites = 0;
-
-    /* reset the max inFIFO Full retries counter */
-    ixNpeMhConfigStats[npeId].maxInFifoFullRetries = 0;
-
-    /* reset the max outFIFO empty retries counter */
-    ixNpeMhConfigStats[npeId].maxOutFifoEmptyRetries = 0;
-}
-
-
diff --git a/arch/arm/cpu/ixp/npe/IxNpeMhReceive.c b/arch/arm/cpu/ixp/npe/IxNpeMhReceive.c
deleted file mode 100644
index 57c8be3..0000000
--- a/arch/arm/cpu/ixp/npe/IxNpeMhReceive.c
+++ /dev/null
@@ -1,320 +0,0 @@
-/**
- * @file IxNpeMhReceive.c
- *
- * @author Intel Corporation
- * @date 18 Jan 2002
- *
- * @brief This file contains the implementation of the private API for the
- * Receive module.
- *
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- * 
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- * 
- * @par
- * -- End of Copyright Notice --
-*/
-
-/*
- * Put the system defined include files required.
- */
-
-
-/*
- * Put the user defined include files required.
- */
-#include "IxOsal.h"
-#include "IxNpeMhMacros_p.h"
-#include "IxNpeMhConfig_p.h"
-#include "IxNpeMhReceive_p.h"
-#include "IxNpeMhSolicitedCbMgr_p.h"
-#include "IxNpeMhUnsolicitedCbMgr_p.h"
-
-/*
- * #defines and macros used in this file.
- */
-
-/*
- * Typedefs whose scope is limited to this file.
- */
-
-/**
- * @struct IxNpeMhReceiveStats
- *
- * @brief This structure is used to maintain statistics for the Receive
- * module.
- */
-
-typedef struct
-{
-    UINT32 isrs;        /**< receive ISR invocations */
-    UINT32 receives;    /**< receive messages invocations */
-    UINT32 messages;    /**< messages received */
-    UINT32 solicited;   /**< solicited messages received */
-    UINT32 unsolicited; /**< unsolicited messages received */
-    UINT32 callbacks;   /**< callbacks invoked */
-} IxNpeMhReceiveStats;
-
-/*
- * Variable declarations global to this file only.  Externs are followed by
- * static variables.
- */
-
-PRIVATE IxNpeMhReceiveStats ixNpeMhReceiveStats[IX_NPEMH_NUM_NPES];
-
-/*
- * Extern function prototypes.
- */
-
-/*
- * Static function prototypes.
- */
-PRIVATE
-void ixNpeMhReceiveIsr (int npeId);
-
-PRIVATE
-void ixNpeMhReceiveIsr (int npeId)
-{
-    int lockKey;
-
-    IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering "
-                     "ixNpeMhReceiveIsr\n");
-
-    lockKey = ixOsalIrqLock ();
-
-    /* invoke the message receive routine to get messages from the NPE */
-    ixNpeMhReceiveMessagesReceive (npeId);
-
-    /* update statistical info */
-    ixNpeMhReceiveStats[npeId].isrs++;
-
-    ixOsalIrqUnlock (lockKey);
-
-    IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting "
-                     "ixNpeMhReceiveIsr\n");
-}
-
-/*
- * Function definition: ixNpeMhReceiveInitialize
- */
-
-void ixNpeMhReceiveInitialize (void)
-{
-    IxNpeMhNpeId npeId = 0;
-
-    IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering "
-                     "ixNpeMhReceiveInitialize\n");
-
-    /* for each NPE ... */
-    for (npeId = 0; npeId < IX_NPEMH_NUM_NPES; npeId++)
-    {
-        /* register our internal ISR for the NPE to handle "outFIFO not */
-        /* empty" interrupts */
-        ixNpeMhConfigIsrRegister (npeId, ixNpeMhReceiveIsr);
-    }
-
-    IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting "
-                     "ixNpeMhReceiveInitialize\n");
-}
-
-/*
- * Function definition: ixNpeMhReceiveMessagesReceive
- */
-
-IX_STATUS ixNpeMhReceiveMessagesReceive (
-    IxNpeMhNpeId npeId)
-{
-    IxNpeMhMessage message = { { 0, 0 } };
-    IxNpeMhMessageId messageId = 0;
-    IxNpeMhCallback callback = NULL;
-    IX_STATUS status;
-
-    IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering "
-                     "ixNpeMhReceiveMessagesReceive\n");
-
-    /* update statistical info */
-    ixNpeMhReceiveStats[npeId].receives++;
-
-    /* while the NPE has messages in its outFIFO */
-    while (!ixNpeMhConfigOutFifoIsEmpty (npeId))
-    {
-        /* read a message from the NPE's outFIFO */
-        status = ixNpeMhConfigOutFifoRead (npeId, &message);
-
-        if (IX_SUCCESS != status)
-        {
-            return status;
-        }
-        
-        /* get the ID of the message */
-        messageId = ixNpeMhConfigMessageIdGet (message);
-
-	    IX_NPEMH_TRACE2 (IX_NPEMH_DEBUG,
-			 "Received message from NPE %d with ID 0x%02X\n",
-			 npeId, messageId);
-
-        /* update statistical info */
-        ixNpeMhReceiveStats[npeId].messages++;
-
-        /* try to find a matching unsolicited callback for this message. */
-
-        /* we assume the message is unsolicited.  only if there is no */
-        /* unsolicited callback for this message type do we assume the */
-        /* message is solicited.  it is much faster to check for an */
-        /* unsolicited callback, so doing this check first should result */
-        /* in better performance. */
-
-        ixNpeMhUnsolicitedCbMgrCallbackRetrieve (
-            npeId, messageId, &callback);
-
-        if (callback != NULL)
-        {
-	    IX_NPEMH_TRACE0 (IX_NPEMH_DEBUG,
-			     "Found matching unsolicited callback\n");
-
-            /* update statistical info */
-            ixNpeMhReceiveStats[npeId].unsolicited++;
-        }
-
-        /* if no unsolicited callback was found try to find a matching */
-        /* solicited callback for this message */
-        if (callback == NULL)
-        {
-            ixNpeMhSolicitedCbMgrCallbackRetrieve (
-                npeId, messageId, &callback);
-
-            if (callback != NULL)
-            {
-		IX_NPEMH_TRACE0 (IX_NPEMH_DEBUG,
-				 "Found matching solicited callback\n");
-
-                /* update statistical info */
-                ixNpeMhReceiveStats[npeId].solicited++;
-            }
-        }
-
-        /* if a callback (either unsolicited or solicited) was found */
-        if (callback != NULL)
-        {
-            /* invoke the callback to pass the message back to the client */
-            callback (npeId, message);
-
-            /* update statistical info */
-            ixNpeMhReceiveStats[npeId].callbacks++;
-        }
-        else /* no callback (neither unsolicited nor solicited) was found */
-        {
-	    IX_NPEMH_TRACE2 (IX_NPEMH_WARNING,
-			     "No matching callback for NPE %d"
-			     " and ID 0x%02X, discarding message\n",
-			     npeId, messageId);
-
-            /* the message will be discarded.  this is normal behaviour */
-            /* if the client passes a NULL solicited callback when */
-            /* sending a message.  this indicates that the client is not */
-            /* interested in receiving the response.  alternatively a */
-            /* NULL callback here may signify an unsolicited message */
-            /* with no appropriate registered callback. */
-        }
-    }
-
-    IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting "
-                     "ixNpeMhReceiveMessagesReceive\n");
-    
-    return IX_SUCCESS;
-}
-
-/*
- * Function definition: ixNpeMhReceiveShow
- */
-
-void ixNpeMhReceiveShow (
-    IxNpeMhNpeId npeId)
-{
-    /* show the ISR invocation counter */
-    IX_NPEMH_SHOW ("Receive ISR invocations",
-                   ixNpeMhReceiveStats[npeId].isrs);
-
-    /* show the receive message invocation counter */
-    IX_NPEMH_SHOW ("Receive messages invocations",
-                   ixNpeMhReceiveStats[npeId].receives);
-
-    /* show the message received counter */
-    IX_NPEMH_SHOW ("Messages received",
-                   ixNpeMhReceiveStats[npeId].messages);
-
-    /* show the solicited message counter */
-    IX_NPEMH_SHOW ("Solicited messages received",
-                   ixNpeMhReceiveStats[npeId].solicited);
-
-    /* show the unsolicited message counter */
-    IX_NPEMH_SHOW ("Unsolicited messages received",
-                   ixNpeMhReceiveStats[npeId].unsolicited);
-
-    /* show the callback invoked counter */
-    IX_NPEMH_SHOW ("Callbacks invoked",
-                   ixNpeMhReceiveStats[npeId].callbacks);
-
-    /* show the message discarded counter */
-    IX_NPEMH_SHOW ("Received messages discarded",
-                   (ixNpeMhReceiveStats[npeId].messages -
-                    ixNpeMhReceiveStats[npeId].callbacks));
-}
-
-/*
- * Function definition: ixNpeMhReceiveShowReset
- */
-
-void ixNpeMhReceiveShowReset (
-    IxNpeMhNpeId npeId)
-{
-    /* reset the ISR invocation counter */
-    ixNpeMhReceiveStats[npeId].isrs = 0;
-
-    /* reset the receive message invocation counter */
-    ixNpeMhReceiveStats[npeId].receives = 0;
-
-    /* reset the message received counter */
-    ixNpeMhReceiveStats[npeId].messages = 0;
-
-    /* reset the solicited message counter */
-    ixNpeMhReceiveStats[npeId].solicited = 0;
-
-    /* reset the unsolicited message counter */
-    ixNpeMhReceiveStats[npeId].unsolicited = 0;
-
-    /* reset the callback invoked counter */
-    ixNpeMhReceiveStats[npeId].callbacks = 0;
-}
diff --git a/arch/arm/cpu/ixp/npe/IxNpeMhSend.c b/arch/arm/cpu/ixp/npe/IxNpeMhSend.c
deleted file mode 100644
index 318913a..0000000
--- a/arch/arm/cpu/ixp/npe/IxNpeMhSend.c
+++ /dev/null
@@ -1,307 +0,0 @@
-/**
- * @file IxNpeMhSend.c
- *
- * @author Intel Corporation
- * @date 18 Jan 2002
- *
- * @brief This file contains the implementation of the private API for the
- * Send module.
- *
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
-*/
-
-/*
- * Put the system defined include files required.
- */
-
-
-/*
- * Put the user defined include files required.
- */
-
-#include "IxNpeMhMacros_p.h"
-
-#include "IxNpeMhConfig_p.h"
-#include "IxNpeMhSend_p.h"
-#include "IxNpeMhSolicitedCbMgr_p.h"
-
-/*
- * #defines and macros used in this file.
- */
-
-/**
- * @def IX_NPEMH_INFIFO_RETRY_DELAY_US
- *
- * @brief Amount of time (uSecs) to delay between retries
- * while inFIFO is Full when attempting to send a message
- */
-#define IX_NPEMH_INFIFO_RETRY_DELAY_US (1)
-
-
-/*
- * Typedefs whose scope is limited to this file.
- */
-
-/**
- * @struct IxNpeMhSendStats
- *
- * @brief This structure is used to maintain statistics for the Send
- * module.
- */
-
-typedef struct
-{
-    UINT32 sends;             /**< send invocations */
-    UINT32 sendWithResponses; /**< send with response invocations */
-    UINT32 queueFulls;        /**< fifo queue full occurrences */
-    UINT32 queueFullRetries;  /**< fifo queue full retry occurrences */
-    UINT32 maxQueueFullRetries; /**< max fifo queue full retries */
-    UINT32 callbackFulls;     /**< callback list full occurrences */
-} IxNpeMhSendStats;
-
-/*
- * Variable declarations global to this file only.  Externs are followed by
- * static variables.
- */
-
-PRIVATE IxNpeMhSendStats ixNpeMhSendStats[IX_NPEMH_NUM_NPES];
-
-/*
- * Extern function prototypes.
- */
-
-/*
- * Static function prototypes.
- */
-PRIVATE
-BOOL ixNpeMhSendInFifoIsFull(
-    IxNpeMhNpeId npeId,
-    UINT32 maxSendRetries);
-
-/*
- * Function definition: ixNpeMhSendInFifoIsFull
- */
-
-PRIVATE
-BOOL ixNpeMhSendInFifoIsFull(
-    IxNpeMhNpeId npeId,
-    UINT32 maxSendRetries)
-{
-    BOOL isFull = FALSE;
-    UINT32 numRetries = 0;
-
-    /* check the NPE's inFIFO */
-    isFull = ixNpeMhConfigInFifoIsFull (npeId);
-
-    /* we retry a few times, just to give the NPE a chance to read from */
-    /* the FIFO if the FIFO is currently full */
-    while (isFull && (numRetries++ < maxSendRetries))
-    {
-	if (numRetries >= IX_NPEMH_SEND_RETRIES_DEFAULT)
-	{
-	    /* Delay here for as short a time as possible (1 us). */
-	    /* Adding a delay here should ensure we are not hogging */
-	    /* the AHB bus while we are retrying                    */
-	    ixOsalBusySleep (IX_NPEMH_INFIFO_RETRY_DELAY_US);
-	}
-
-        /* re-check the NPE's inFIFO */
-        isFull = ixNpeMhConfigInFifoIsFull (npeId);
-
-        /* update statistical info */
-        ixNpeMhSendStats[npeId].queueFullRetries++;
-    }
-
-    /* record the highest number of retries that occurred */
-    if (ixNpeMhSendStats[npeId].maxQueueFullRetries < numRetries)
-    {
-	ixNpeMhSendStats[npeId].maxQueueFullRetries = numRetries;
-    }
-
-    if (isFull)
-    {
-        /* update statistical info */
-        ixNpeMhSendStats[npeId].queueFulls++;
-    }
-
-    return isFull;
-}
-
-/*
- * Function definition: ixNpeMhSendMessageSend
- */
-
-IX_STATUS ixNpeMhSendMessageSend (
-    IxNpeMhNpeId npeId,
-    IxNpeMhMessage message,
-    UINT32 maxSendRetries)
-{
-    IX_STATUS status;
-
-    IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering "
-                     "ixNpeMhSendMessageSend\n");
-
-    /* update statistical info */
-    ixNpeMhSendStats[npeId].sends++;
-
-    /* check if the NPE's inFIFO is full - if so return an error */
-    if (ixNpeMhSendInFifoIsFull (npeId, maxSendRetries))
-    {
-        IX_NPEMH_TRACE0 (IX_NPEMH_WARNING, "NPE's inFIFO is full\n");
-        return IX_FAIL;
-    }
-
-    /* write the message to the NPE's inFIFO */
-    status = ixNpeMhConfigInFifoWrite (npeId, message);
-
-    IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting "
-                     "ixNpeMhSendMessageSend\n");
-
-    return status;
-}
-
-/*
- * Function definition: ixNpeMhSendMessageWithResponseSend
- */
-
-IX_STATUS ixNpeMhSendMessageWithResponseSend (
-    IxNpeMhNpeId npeId,
-    IxNpeMhMessage message,
-    IxNpeMhMessageId solicitedMessageId,
-    IxNpeMhCallback solicitedCallback,
-    UINT32 maxSendRetries)
-{
-    IX_STATUS status = IX_SUCCESS;
-
-    IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering "
-                     "ixNpeMhSendMessageWithResponseSend\n");
-
-    /* update statistical info */
-    ixNpeMhSendStats[npeId].sendWithResponses++;
-
-    /* sr: this sleep will call the receive routine (no interrupts used!!!) */
-    ixOsalSleep (IX_NPEMH_INFIFO_RETRY_DELAY_US);
-
-    /* check if the NPE's inFIFO is full - if so return an error */
-    if (ixNpeMhSendInFifoIsFull (npeId, maxSendRetries))
-    {
-        IX_NPEMH_TRACE0 (IX_NPEMH_WARNING, "NPE's inFIFO is full\n");
-        return IX_FAIL;
-    }
-
-    /* save the solicited callback */
-    status = ixNpeMhSolicitedCbMgrCallbackSave (
-        npeId, solicitedMessageId, solicitedCallback);
-    if (status != IX_SUCCESS)
-    {
-        IX_NPEMH_ERROR_REPORT ("Failed to save solicited callback\n");
-
-        /* update statistical info */
-        ixNpeMhSendStats[npeId].callbackFulls++;
-
-        return status;
-    }
-
-    /* write the message to the NPE's inFIFO */
-    status = ixNpeMhConfigInFifoWrite (npeId, message);
-
-    IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting "
-                     "ixNpeMhSendMessageWithResponseSend\n");
-
-    return status;
-}
-
-/*
- * Function definition: ixNpeMhSendShow
- */
-
-void ixNpeMhSendShow (
-    IxNpeMhNpeId npeId)
-{
-    /* show the message send invocation counter */
-    IX_NPEMH_SHOW ("Send invocations",
-                   ixNpeMhSendStats[npeId].sends);
-
-    /* show the message send with response invocation counter */
-    IX_NPEMH_SHOW ("Send with response invocations",
-                   ixNpeMhSendStats[npeId].sendWithResponses);
-
-    /* show the fifo queue full occurrence counter */
-    IX_NPEMH_SHOW ("Fifo queue full occurrences",
-                   ixNpeMhSendStats[npeId].queueFulls);
-
-    /* show the fifo queue full retry occurrence counter */
-    IX_NPEMH_SHOW ("Fifo queue full retry occurrences",
-                   ixNpeMhSendStats[npeId].queueFullRetries);
-
-    /* show the fifo queue full maximum retries counter */
-    IX_NPEMH_SHOW ("Maximum fifo queue full retries",
-                   ixNpeMhSendStats[npeId].maxQueueFullRetries);
-
-    /* show the callback list full occurrence counter */
-    IX_NPEMH_SHOW ("Solicited callback list full occurrences",
-                   ixNpeMhSendStats[npeId].callbackFulls);
-}
-
-/*
- * Function definition: ixNpeMhSendShowReset
- */
-
-void ixNpeMhSendShowReset (
-    IxNpeMhNpeId npeId)
-{
-    /* reset the message send invocation counter */
-    ixNpeMhSendStats[npeId].sends = 0;
-
-    /* reset the message send with response invocation counter */
-    ixNpeMhSendStats[npeId].sendWithResponses = 0;
-
-    /* reset the fifo queue full occurrence counter */
-    ixNpeMhSendStats[npeId].queueFulls = 0;
-
-    /* reset the fifo queue full retry occurrence counter */
-    ixNpeMhSendStats[npeId].queueFullRetries = 0;
-
-    /* reset the max fifo queue full retries counter */
-    ixNpeMhSendStats[npeId].maxQueueFullRetries = 0;
-
-    /* reset the callback list full occurrence counter */
-    ixNpeMhSendStats[npeId].callbackFulls = 0;
-}
diff --git a/arch/arm/cpu/ixp/npe/IxNpeMhSolicitedCbMgr.c b/arch/arm/cpu/ixp/npe/IxNpeMhSolicitedCbMgr.c
deleted file mode 100644
index 8e083a6..0000000
--- a/arch/arm/cpu/ixp/npe/IxNpeMhSolicitedCbMgr.c
+++ /dev/null
@@ -1,358 +0,0 @@
-/**
- * @file IxNpeMhSolicitedCbMgr.c
- *
- * @author Intel Corporation
- * @date 18 Jan 2002
- *
- * @brief This file contains the implementation of the private API for the
- * Solicited Callback Manager module.
- *
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- * 
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- * 
- * @par
- * -- End of Copyright Notice --
-*/
-#ifndef IXNPEMHCONFIG_P_H
-#	define IXNPEMHSOLICITEDCBMGR_C
-#else
-#	error "Error, IxNpeMhConfig_p.h should not be included before this definition."
-#endif
-
-/*
- * Put the system defined include files required.
- */
-
-
-/*
- * Put the user defined include files required.
- */
-
-#include "IxOsal.h"
-
-#include "IxNpeMhMacros_p.h"
-#include "IxNpeMhSolicitedCbMgr_p.h"
-#include "IxNpeMhConfig_p.h"
-/*
- * #defines and macros used in this file.
- */
-
-/*
- * Typedefs whose scope is limited to this file.
- */
-
-/**
- * @struct IxNpeMhSolicitedCallbackListEntry
- *
- * @brief This structure is used to store the information associated with
- * an entry in the callback list.  This consists of the ID of the send
- * message (which indicates the ID of the corresponding response message)
- * and the callback function pointer itself.
- *
- */
-
-typedef struct IxNpeMhSolicitedCallbackListEntry
-{
-    /** message ID */
-    IxNpeMhMessageId messageId;
-
-    /** callback function pointer */
-    IxNpeMhCallback callback;
-
-    /** pointer to next entry in the list */
-    struct IxNpeMhSolicitedCallbackListEntry *next;
-} IxNpeMhSolicitedCallbackListEntry;
-
-/**
- * @struct IxNpeMhSolicitedCallbackList
- *
- * @brief This structure is used to maintain the list of response
- * callbacks.  The number of entries in this list will be variable, and
- * they will be stored in a linked list fashion for ease of addition and
- * removal.  The entries themselves are statically allocated, and are
- * organised into a "free" list and a "callback" list.  Adding an entry
- * means taking an entry from the "free" list and adding it to the
- * "callback" list.  Removing an entry means removing it from the
- * "callback" list and returning it to the "free" list.
- */
-
-typedef struct
-{
-    /** pointer to the head of the free list */
-    IxNpeMhSolicitedCallbackListEntry *freeHead;
-
-    /** pointer to the head of the callback list */
-    IxNpeMhSolicitedCallbackListEntry *callbackHead;
-
-    /** pointer to the tail of the callback list */
-    IxNpeMhSolicitedCallbackListEntry *callbackTail;
-
-    /** array of entries - the first entry is used as a dummy entry to */
-    /* avoid the scenario of having an empty list, hence '+ 1' */
-    IxNpeMhSolicitedCallbackListEntry entries[IX_NPEMH_MAX_CALLBACKS + 1];
-} IxNpeMhSolicitedCallbackList;
-
-/**
- * @struct IxNpeMhSolicitedCbMgrStats
- *
- * @brief This structure is used to maintain statistics for the Solicited
- * Callback Manager module.
- */
-
-typedef struct
-{
-    UINT32 saves;     /**< callback list saves */
-    UINT32 retrieves; /**< callback list retrieves */
-} IxNpeMhSolicitedCbMgrStats;
-
-/*
- * Variable declarations global to this file only.  Externs are followed by
- * static variables.
- */
-
-PRIVATE IxNpeMhSolicitedCallbackList
-ixNpeMhSolicitedCbMgrCallbackLists[IX_NPEMH_NUM_NPES];
-
-PRIVATE IxNpeMhSolicitedCbMgrStats
-ixNpeMhSolicitedCbMgrStats[IX_NPEMH_NUM_NPES];
-
-/*
- * Extern function prototypes.
- */
-
-/*
- * Static function prototypes.
- */
-
-/*
- * Function definition: ixNpeMhSolicitedCbMgrInitialize
- */
-
-void ixNpeMhSolicitedCbMgrInitialize (void)
-{
-    IxNpeMhNpeId npeId;
-    UINT32 localIndex;
-    IxNpeMhSolicitedCallbackList *list = NULL;
-
-    IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering "
-                     "ixNpeMhSolicitedCbMgrInitialize\n");
-
-    /* for each NPE ... */
-    for (npeId = 0; npeId < IX_NPEMH_NUM_NPES; npeId++)
-    {
-        /* initialise a pointer to the list for convenience */
-        list = &ixNpeMhSolicitedCbMgrCallbackLists[npeId];
-
-        /* for each entry in the list, after the dummy entry ... */
-        for (localIndex = 1; localIndex <= IX_NPEMH_MAX_CALLBACKS; localIndex++)
-        {
-            /* initialise the entry */
-            list->entries[localIndex].messageId = 0x00;
-            list->entries[localIndex].callback = NULL;
-
-            /* if this entry is before the last entry */
-            if (localIndex < IX_NPEMH_MAX_CALLBACKS)
-            {
-                /* chain this entry to the following entry */
-                list->entries[localIndex].next = &(list->entries[localIndex + 1]);
-            }
-            else /* this entry is the last entry */
-            {
-                /* the last entry isn't chained to anything */
-                list->entries[localIndex].next = NULL;
-            }
-        }
-
-        /* set the free list pointer to point to the first real entry */
-        /* (all real entries begin chained together on the free list) */
-        list->freeHead = &(list->entries[1]);
-
-        /* set the callback list pointers to point to the dummy entry */
-        /* (the callback list is initially empty) */
-        list->callbackHead = &(list->entries[0]);
-        list->callbackTail = &(list->entries[0]);
-    }
-
-    IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting "
-                     "ixNpeMhSolicitedCbMgrInitialize\n");
-}
-
-/*
- * Function definition: ixNpeMhSolicitedCbMgrCallbackSave
- */
-
-IX_STATUS ixNpeMhSolicitedCbMgrCallbackSave (
-    IxNpeMhNpeId npeId,
-    IxNpeMhMessageId solicitedMessageId,
-    IxNpeMhCallback solicitedCallback)
-{
-    IxNpeMhSolicitedCallbackList *list = NULL;
-    IxNpeMhSolicitedCallbackListEntry *callbackEntry = NULL;
-
-    IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering "
-                     "ixNpeMhSolicitedCbMgrCallbackSave\n");
-
-    /* initialise a pointer to the list for convenience */
-    list = &ixNpeMhSolicitedCbMgrCallbackLists[npeId];
-
-    /* check to see if there are any entries in the free list */
-    if (list->freeHead == NULL)
-    {
-        IX_NPEMH_ERROR_REPORT ("Solicited callback list is full\n");
-        return IX_FAIL;
-    }
-
-    /* there is an entry in the free list we can use */
-
-    /* update statistical info */
-    ixNpeMhSolicitedCbMgrStats[npeId].saves++;
-
-    /* remove a callback entry from the start of the free list */
-    callbackEntry = list->freeHead;
-    list->freeHead = callbackEntry->next;
-
-    /* fill in the callback entry with the new data */
-    callbackEntry->messageId = solicitedMessageId;
-    callbackEntry->callback = solicitedCallback;
-
-    /* the new callback entry will be added to the tail of the callback */
-    /* list, so it isn't chained to anything */
-    callbackEntry->next = NULL;
-
-    /* chain new callback entry to the last entry of the callback list */
-    list->callbackTail->next = callbackEntry;
-    list->callbackTail = callbackEntry;
-
-    IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting "
-                     "ixNpeMhSolicitedCbMgrCallbackSave\n");
-
-    return IX_SUCCESS;
-}
-
-/*
- * Function definition: ixNpeMhSolicitedCbMgrCallbackRetrieve
- */
-
-void ixNpeMhSolicitedCbMgrCallbackRetrieve (
-    IxNpeMhNpeId npeId,
-    IxNpeMhMessageId solicitedMessageId,
-    IxNpeMhCallback *solicitedCallback)
-{
-    IxNpeMhSolicitedCallbackList *list = NULL;
-    IxNpeMhSolicitedCallbackListEntry *callbackEntry = NULL;
-    IxNpeMhSolicitedCallbackListEntry *previousEntry = NULL;
-
-    /* initialise a pointer to the list for convenience */
-    list = &ixNpeMhSolicitedCbMgrCallbackLists[npeId];
-
-    /* initialise the callback entry to the first entry of the callback */
-    /* list - we must skip over the dummy entry, which is the previous */
-    callbackEntry = list->callbackHead->next;
-    previousEntry = list->callbackHead;
-
-    /* traverse the callback list looking for an entry with a matching */
-    /* message ID.  note we also save the previous entry's pointer to */
-    /* allow us to unchain the matching entry from the callback list */
-    while ((callbackEntry != NULL) &&
-           (callbackEntry->messageId != solicitedMessageId))
-    {
-        previousEntry = callbackEntry;
-        callbackEntry = callbackEntry->next;
-    }
-
-    /* if we didn't find a matching callback entry */
-    if (callbackEntry == NULL)
-    {
-        /* return a NULL callback in the outgoing parameter */
-        *solicitedCallback = NULL;
-    }
-    else /* we found a matching callback entry */
-    {
-        /* update statistical info */
-        ixNpeMhSolicitedCbMgrStats[npeId].retrieves++;
-
-        /* return the callback in the outgoing parameter */
-        *solicitedCallback = callbackEntry->callback;
-
-        /* unchain callback entry by chaining previous entry to next */
-        previousEntry->next = callbackEntry->next;
-
-        /* if the callback entry is at the tail of the list */
-        if (list->callbackTail == callbackEntry)
-        {
-            /* update the tail of the callback list */
-            list->callbackTail = previousEntry;
-        }
-
-        /* re-initialise the callback entry */
-        callbackEntry->messageId = 0x00;
-        callbackEntry->callback = NULL;
-
-        /* add the callback entry to the start of the free list */
-        callbackEntry->next = list->freeHead;
-        list->freeHead = callbackEntry;
-    }
-}
-
-/*
- * Function definition: ixNpeMhSolicitedCbMgrShow
- */
-
-void ixNpeMhSolicitedCbMgrShow (
-    IxNpeMhNpeId npeId)
-{
-    /* show the solicited callback list save counter */
-    IX_NPEMH_SHOW ("Solicited callback list saves",
-                   ixNpeMhSolicitedCbMgrStats[npeId].saves);
-
-    /* show the solicited callback list retrieve counter */
-    IX_NPEMH_SHOW ("Solicited callback list retrieves",
-                   ixNpeMhSolicitedCbMgrStats[npeId].retrieves);
-}
-
-/*
- * Function definition: ixNpeMhSolicitedCbMgrShowReset
- */
-
-void ixNpeMhSolicitedCbMgrShowReset (
-    IxNpeMhNpeId npeId)
-{
-    /* reset the solicited callback list save counter */
-    ixNpeMhSolicitedCbMgrStats[npeId].saves = 0;
-
-    /* reset the solicited callback list retrieve counter */
-    ixNpeMhSolicitedCbMgrStats[npeId].retrieves = 0;
-}
diff --git a/arch/arm/cpu/ixp/npe/IxNpeMhUnsolicitedCbMgr.c b/arch/arm/cpu/ixp/npe/IxNpeMhUnsolicitedCbMgr.c
deleted file mode 100644
index d37f9f9..0000000
--- a/arch/arm/cpu/ixp/npe/IxNpeMhUnsolicitedCbMgr.c
+++ /dev/null
@@ -1,246 +0,0 @@
-/**
- * @file IxNpeMhUnsolicitedCbMgr.c
- *
- * @author Intel Corporation
- * @date 18 Jan 2002
- *
- * @brief This file contains the implementation of the private API for
- * the Unsolicited Callback Manager module.
- *
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- * 
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- * 
- * @par
- * -- End of Copyright Notice --
-*/
-
-/*
- * Put the system defined include files required.
- */
-
-
-/*
- * Put the user defined include files required.
- */
-#include "IxOsal.h"
-
-#include "IxNpeMhMacros_p.h"
-
-#include "IxNpeMhUnsolicitedCbMgr_p.h"
-
-
-/*
- * #defines and macros used in this file.
- */
-
-/*
- * Typedefs whose scope is limited to this file.
- */
-
-/**
- * @struct IxNpeMhUnsolicitedCallbackTable
- *
- * @brief This structure is used to maintain the list of registered
- * callbacks.  One entry exists for each message ID, and a NULL entry will
- * signify that no callback has been registered for that ID.
- */
-
-typedef struct
-{
-    /** array of entries */
-    IxNpeMhCallback entries[IX_NPEMH_MAX_MESSAGE_ID + 1];
-} IxNpeMhUnsolicitedCallbackTable;
-
-/**
- * @struct IxNpeMhUnsolicitedCbMgrStats
- *
- * @brief This structure is used to maintain statistics for the Unsolicited
- * Callback Manager module.
- */
-
-typedef struct
-{
-    UINT32 saves;      /**< callback table saves */
-    UINT32 overwrites; /**< callback table overwrites */
-} IxNpeMhUnsolicitedCbMgrStats;
-
-/*
- * Variable declarations global to this file only.  Externs are followed by
- * static variables.
- */
-
-PRIVATE IxNpeMhUnsolicitedCallbackTable
-ixNpeMhUnsolicitedCallbackTables[IX_NPEMH_NUM_NPES];
-
-PRIVATE IxNpeMhUnsolicitedCbMgrStats
-ixNpeMhUnsolicitedCbMgrStats[IX_NPEMH_NUM_NPES];
-
-/*
- * Extern function prototypes.
- */
-
-/*
- * Static function prototypes.
- */
-
-/*
- * Function definition: ixNpeMhUnsolicitedCbMgrInitialize
- */
-
-void ixNpeMhUnsolicitedCbMgrInitialize (void)
-{
-    IxNpeMhNpeId npeId = 0;
-    IxNpeMhUnsolicitedCallbackTable *table = NULL;
-    IxNpeMhMessageId messageId = 0;
-
-    IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering "
-                     "ixNpeMhUnsolicitedCbMgrInitialize\n");
-
-    /* for each NPE ... */
-    for (npeId = 0; npeId < IX_NPEMH_NUM_NPES; npeId++)
-    {
-        /* initialise a pointer to the table for convenience */
-        table = &ixNpeMhUnsolicitedCallbackTables[npeId];
-
-        /* for each message ID ... */
-        for (messageId = IX_NPEMH_MIN_MESSAGE_ID;
-             messageId <= IX_NPEMH_MAX_MESSAGE_ID; messageId++)
-        {
-            /* initialise the callback for this message ID to NULL */
-            table->entries[messageId] = NULL;
-        }
-    }
-
-    IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting "
-                     "ixNpeMhUnsolicitedCbMgrInitialize\n");
-}
-
-/*
- * Function definition: ixNpeMhUnsolicitedCbMgrCallbackSave
- */
-
-void ixNpeMhUnsolicitedCbMgrCallbackSave (
-    IxNpeMhNpeId npeId,
-    IxNpeMhMessageId unsolicitedMessageId,
-    IxNpeMhCallback unsolicitedCallback)
-{
-    IxNpeMhUnsolicitedCallbackTable *table = NULL;
-
-    /* initialise a pointer to the table for convenience */
-    table = &ixNpeMhUnsolicitedCallbackTables[npeId];
-
-    IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering "
-                     "ixNpeMhUnsolicitedCbMgrCallbackSave\n");
-
-    /* update statistical info */
-    ixNpeMhUnsolicitedCbMgrStats[npeId].saves++;
-
-    /* check if there is a callback already registered for this NPE and */
-    /* message ID */
-    if (table->entries[unsolicitedMessageId] != NULL)
-    {
-	/* if we are overwriting an existing callback */
-	if (unsolicitedCallback != NULL)
-	{
-	    IX_NPEMH_TRACE2 (IX_NPEMH_DEBUG, "Unsolicited callback "
-			     "overwriting existing callback for NPE ID %d "
-			     "message ID 0x%02X\n", npeId, unsolicitedMessageId);
-	}
-	else /* if we are clearing an existing callback */
-	{
-	    IX_NPEMH_TRACE2 (IX_NPEMH_DEBUG, "NULL unsolicited callback "
-			     "clearing existing callback for NPE ID %d "
-			     "message ID 0x%02X\n", npeId, unsolicitedMessageId);
-	}
-
-        /* update statistical info */
-        ixNpeMhUnsolicitedCbMgrStats[npeId].overwrites++;
-    }
-
-    /* save the callback into the table */
-    table->entries[unsolicitedMessageId] = unsolicitedCallback;
-
-    IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting "
-                     "ixNpeMhUnsolicitedCbMgrCallbackSave\n");
-}
-
-/*
- * Function definition: ixNpeMhUnsolicitedCbMgrCallbackRetrieve
- */
-
-void ixNpeMhUnsolicitedCbMgrCallbackRetrieve (
-    IxNpeMhNpeId npeId,
-    IxNpeMhMessageId unsolicitedMessageId,
-    IxNpeMhCallback *unsolicitedCallback)
-{
-    IxNpeMhUnsolicitedCallbackTable *table = NULL;
-
-    /* initialise a pointer to the table for convenience */
-    table = &ixNpeMhUnsolicitedCallbackTables[npeId];
-
-    /* retrieve the callback from the table */
-    *unsolicitedCallback = table->entries[unsolicitedMessageId];
-}
-
-/*
- * Function definition: ixNpeMhUnsolicitedCbMgrShow
- */
-
-void ixNpeMhUnsolicitedCbMgrShow (
-    IxNpeMhNpeId npeId)
-{
-    /* show the unsolicited callback table save counter */
-    IX_NPEMH_SHOW ("Unsolicited callback table saves",
-                   ixNpeMhUnsolicitedCbMgrStats[npeId].saves);
-
-    /* show the unsolicited callback table overwrite counter */
-    IX_NPEMH_SHOW ("Unsolicited callback table overwrites",
-                   ixNpeMhUnsolicitedCbMgrStats[npeId].overwrites);
-}
-
-/*
- * Function definition: ixNpeMhUnsolicitedCbMgrShowReset
- */
-
-void ixNpeMhUnsolicitedCbMgrShowReset (
-    IxNpeMhNpeId npeId)
-{
-    /* reset the unsolicited callback table save counter */
-    ixNpeMhUnsolicitedCbMgrStats[npeId].saves = 0;
-
-    /* reset the unsolicited callback table overwrite counter */
-    ixNpeMhUnsolicitedCbMgrStats[npeId].overwrites = 0;
-}
diff --git a/arch/arm/cpu/ixp/npe/IxOsalBufferMgt.c b/arch/arm/cpu/ixp/npe/IxOsalBufferMgt.c
deleted file mode 100644
index fa8db47..0000000
--- a/arch/arm/cpu/ixp/npe/IxOsalBufferMgt.c
+++ /dev/null
@@ -1,800 +0,0 @@
-/**
- * @file IxOsalBufferMgt.c
- *
- * @brief Default buffer pool management and buffer management
- *        Implementation.
- *
- * Design Notes:
- *
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- * 
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- * 
- * @par
- * -- End of Copyright Notice --
- */
-
-/*
- * OS may choose to use default bufferMgt by defining
- * IX_OSAL_USE_DEFAULT_BUFFER_MGT in IxOsalOsBufferMgt.h  
- */
-
-#include "IxOsal.h"
-
-#define IX_OSAL_BUFFER_FREE_PROTECTION  /* Define this to enable Illegal MBuf Freed Protection*/
-
-/*
- * The implementation is only used when the following
- * is defined.
- */
-#ifdef IX_OSAL_USE_DEFAULT_BUFFER_MGT
-
-
-#define IX_OSAL_MBUF_SYS_SIGNATURE				(0x8BADF00D)
-#define IX_OSAL_MBUF_SYS_SIGNATURE_MASK				(0xEFFFFFFF)
-#define IX_OSAL_MBUF_USED_FLAG					(0x10000000)
-#define IX_OSAL_MBUF_SYS_SIGNATURE_INIT(bufPtr)        		IX_OSAL_MBUF_SIGNATURE (bufPtr) = (UINT32)IX_OSAL_MBUF_SYS_SIGNATURE
-
-/* 
-*  This implementation is protect, the buffer pool management's  ixOsalMBufFree 
-*  against an invalid MBUF pointer argument that already has been freed earlier 
-*  or in other words resides in the free pool of MBUFs. This added feature, 
-*  checks the MBUF "USED" FLAG. The Flag tells if the MBUF is still not freed 
-*  back to the Buffer Pool.
-*  Disable this feature for performance reasons by undef 
-*  IX_OSAL_BUFFER_FREE_PROTECTION macro.
-*/
-#ifdef IX_OSAL_BUFFER_FREE_PROTECTION  /*IX_OSAL_BUFFER_FREE_PROTECTION With Buffer Free protection*/
-
-#define IX_OSAL_MBUF_GET_SYS_SIGNATURE(bufPtr)		(IX_OSAL_MBUF_SIGNATURE (bufPtr)&(IX_OSAL_MBUF_SYS_SIGNATURE_MASK) )
-#define IX_OSAL_MBUF_SET_SYS_SIGNATURE(bufPtr)    do {																											\
-																									IX_OSAL_MBUF_SIGNATURE (bufPtr)&(~IX_OSAL_MBUF_SYS_SIGNATURE_MASK);\
-														    									IX_OSAL_MBUF_SIGNATURE (bufPtr)|=IX_OSAL_MBUF_SYS_SIGNATURE;			\
-																									}while(0)
-
-#define IX_OSAL_MBUF_SET_USED_FLAG(bufPtr)   IX_OSAL_MBUF_SIGNATURE (bufPtr)|=IX_OSAL_MBUF_USED_FLAG
-#define IX_OSAL_MBUF_CLEAR_USED_FLAG(bufPtr) IX_OSAL_MBUF_SIGNATURE (bufPtr)&=~IX_OSAL_MBUF_USED_FLAG
-#define IX_OSAL_MBUF_ISSET_USED_FLAG(bufPtr) (IX_OSAL_MBUF_SIGNATURE (bufPtr)&IX_OSAL_MBUF_USED_FLAG)
-
-#else
-
-#define IX_OSAL_MBUF_GET_SYS_SIGNATURE(bufPtr)	 IX_OSAL_MBUF_SIGNATURE (bufPtr)
-#define IX_OSAL_MBUF_SET_SYS_SIGNATURE(bufPtr)   IX_OSAL_MBUF_SIGNATURE (bufPtr) = IX_OSAL_MBUF_SYS_SIGNATURE
-
-#endif /*IX_OSAL_BUFFER_FREE_PROTECTION With Buffer Free protection*/
-/*
- * Variable declarations global to this file only.  Externs are followed by
- * static variables.
- */
-
-/* 
- * A unit of 32, used to provide bit-shift for pool
- * management. Needs some work if users want more than 32 pools.
- */
-#define IX_OSAL_BUFF_FREE_BITS 32
-
-PRIVATE UINT32 ixOsalBuffFreePools[IX_OSAL_MBUF_MAX_POOLS /
-    IX_OSAL_BUFF_FREE_BITS];
-
-PUBLIC IX_OSAL_MBUF_POOL ixOsalBuffPools[IX_OSAL_MBUF_MAX_POOLS];
-
-static int ixOsalBuffPoolsInUse = 0;
-
-#ifdef IX_OSAL_BUFFER_ALLOC_SEPARATELY
-PRIVATE IX_OSAL_MBUF *
-ixOsalBuffPoolMbufInit (UINT32 mbufSizeAligned,
-                      UINT32 dataSizeAligned,
-                      IX_OSAL_MBUF_POOL *poolPtr);
-#endif
-
-PRIVATE IX_OSAL_MBUF_POOL * ixOsalPoolAlloc (void);                      
-
-/*
- * Function definition: ixOsalPoolAlloc
- */
-
-/****************************/
-
-PRIVATE IX_OSAL_MBUF_POOL *
-ixOsalPoolAlloc (void)
-{
-    register unsigned int i = 0;
-
-    /*
-     * Scan for the first free buffer. Free buffers are indicated by 0
-     * on the corrsponding bit in ixOsalBuffFreePools. 
-     */
-    if (ixOsalBuffPoolsInUse >= IX_OSAL_MBUF_MAX_POOLS)
-    {
-        /*
-         * Fail to grab a ptr this time 
-         */
-        return NULL;
-    }
-
-    while (ixOsalBuffFreePools[i / IX_OSAL_BUFF_FREE_BITS] &
-        (1 << (i % IX_OSAL_BUFF_FREE_BITS)))
-        i++;
-    /*
-     * Free buffer found. Mark it as busy and initialize. 
-     */
-    ixOsalBuffFreePools[i / IX_OSAL_BUFF_FREE_BITS] |=
-        (1 << (i % IX_OSAL_BUFF_FREE_BITS));
-
-    memset (&ixOsalBuffPools[i], 0, sizeof (IX_OSAL_MBUF_POOL));
-
-    ixOsalBuffPools[i].poolIdx = i;
-    ixOsalBuffPoolsInUse++;
-
-    return &ixOsalBuffPools[i];
-}
-
-
-#ifdef IX_OSAL_BUFFER_ALLOC_SEPARATELY
-PRIVATE IX_OSAL_MBUF *
-ixOsalBuffPoolMbufInit (UINT32 mbufSizeAligned,
-                      UINT32 dataSizeAligned,
-                      IX_OSAL_MBUF_POOL *poolPtr)
-{
-    UINT8 *dataPtr;
-    IX_OSAL_MBUF *realMbufPtr;
-    /* Allocate cache-aligned memory for mbuf header */
-    realMbufPtr = (IX_OSAL_MBUF *) IX_OSAL_CACHE_DMA_MALLOC (mbufSizeAligned);
-    IX_OSAL_ASSERT (realMbufPtr != NULL);
-    memset (realMbufPtr, 0, mbufSizeAligned);
-
-    /* Allocate cache-aligned memory for mbuf data */
-    dataPtr = (UINT8 *) IX_OSAL_CACHE_DMA_MALLOC (dataSizeAligned);
-    IX_OSAL_ASSERT (dataPtr != NULL);
-    memset (dataPtr, 0, dataSizeAligned);
-
-    /* Fill in mbuf header fields */
-    IX_OSAL_MBUF_MDATA (realMbufPtr) = dataPtr;
-    IX_OSAL_MBUF_ALLOCATED_BUFF_DATA (realMbufPtr) = (UINT32)dataPtr;
-
-    IX_OSAL_MBUF_MLEN (realMbufPtr) = dataSizeAligned;
-    IX_OSAL_MBUF_ALLOCATED_BUFF_LEN (realMbufPtr) = dataSizeAligned;
-
-    IX_OSAL_MBUF_NET_POOL (realMbufPtr) = (IX_OSAL_MBUF_POOL *) poolPtr;
-
-    IX_OSAL_MBUF_SYS_SIGNATURE_INIT(realMbufPtr);
-
-    /* update some statistical information */
-    poolPtr->mbufMemSize += mbufSizeAligned;
-    poolPtr->dataMemSize += dataSizeAligned;
-
-    return realMbufPtr;
-}
-#endif /* #ifdef IX_OSAL_BUFFER_ALLOC_SEPARATELY */
-
-/*
- * Function definition: ixOsalBuffPoolInit
- */
-
-PUBLIC IX_OSAL_MBUF_POOL *
-ixOsalPoolInit (UINT32 count, UINT32 size, const char *name)
-{
-
-    /* These variables are only used if UX_OSAL_BUFFER_ALLOC_SEPERATELY
-     * is defined .
-     */
-#ifdef IX_OSAL_BUFFER_ALLOC_SEPARATELY
-    UINT32 i, mbufSizeAligned, dataSizeAligned;
-    IX_OSAL_MBUF *currentMbufPtr = NULL;
-#else
-    void *poolBufPtr;
-    void *poolDataPtr;
-    int mbufMemSize;
-    int dataMemSize;
-#endif
-
-    IX_OSAL_MBUF_POOL *poolPtr = NULL;
-    
-    if (count <= 0)
-    {
-        ixOsalLog (IX_OSAL_LOG_LVL_ERROR,
-            IX_OSAL_LOG_DEV_STDOUT,
-            "ixOsalPoolInit(): " "count = 0 \n", 0, 0, 0, 0, 0, 0);
-        return NULL;        
-    }
-
-    if (name == NULL)
-    {
-        ixOsalLog (IX_OSAL_LOG_LVL_ERROR,
-            IX_OSAL_LOG_DEV_STDOUT,
-            "ixOsalPoolInit(): " "NULL name \n", 0, 0, 0, 0, 0, 0);
-        return NULL;        
-    }
-    
-    if (strlen (name) > IX_OSAL_MBUF_POOL_NAME_LEN)
-    {
-        ixOsalLog (IX_OSAL_LOG_LVL_ERROR,
-            IX_OSAL_LOG_DEV_STDOUT,
-            "ixOsalPoolInit(): "
-            "ERROR - name length should be no greater than %d  \n",
-            IX_OSAL_MBUF_POOL_NAME_LEN, 0, 0, 0, 0, 0);
-        return NULL;
-    }
-
-/* OS can choose whether to allocate all buffers all together (if it 
- * can handle a huge single alloc request), or to allocate buffers 
- * separately by the defining IX_OSAL_BUFFER_ALLOC_SEPARATELY.
- */
-#ifdef IX_OSAL_BUFFER_ALLOC_SEPARATELY
-    /* Get a pool Ptr */
-    poolPtr = ixOsalPoolAlloc ();
-
-    if (poolPtr == NULL)
-    {
-        ixOsalLog (IX_OSAL_LOG_LVL_ERROR,
-            IX_OSAL_LOG_DEV_STDOUT,
-            "ixOsalPoolInit(): " "Fail to Get PoolPtr \n", 0, 0, 0, 0, 0, 0);    
-        return NULL;
-    }
-
-    mbufSizeAligned = IX_OSAL_MBUF_POOL_SIZE_ALIGN (sizeof (IX_OSAL_MBUF));
-    dataSizeAligned = IX_OSAL_MBUF_POOL_SIZE_ALIGN(size);
-
-    poolPtr->nextFreeBuf = NULL;    
-    poolPtr->mbufMemPtr = NULL;    
-    poolPtr->dataMemPtr = NULL;
-    poolPtr->bufDataSize = dataSizeAligned;
-    poolPtr->totalBufsInPool = count;
-    poolPtr->poolAllocType = IX_OSAL_MBUF_POOL_TYPE_SYS_ALLOC;
-    strcpy (poolPtr->name, name);
-
-
-    for (i = 0; i < count; i++)
-    {
-	    /* create an mbuf */
-	    currentMbufPtr = ixOsalBuffPoolMbufInit (mbufSizeAligned,
-					         dataSizeAligned,
-					         poolPtr);
-
-#ifdef IX_OSAL_BUFFER_FREE_PROTECTION 		
-/* Set the Buffer USED Flag. If not, ixOsalMBufFree will fail.
-   ixOsalMbufFree used here is in a special case whereby, it's 
-   used to add MBUF to the Pool. By specification, ixOsalMbufFree 
-   deallocates an allocated MBUF from Pool.
-*/ 			         
-      IX_OSAL_MBUF_SET_USED_FLAG(currentMbufPtr);
-#endif                             
-	    /* Add it to the pool */
-	    ixOsalMbufFree (currentMbufPtr);
-
-	    /* flush the pool information to RAM */
-	    IX_OSAL_CACHE_FLUSH (currentMbufPtr, mbufSizeAligned);
-    }
-    
-    /*
-     * update the number of free buffers in the pool 
-     */
-    poolPtr->freeBufsInPool = count;
-
-#else 
-/* Otherwise allocate buffers in a continuous block fashion */    
-    poolBufPtr = IX_OSAL_MBUF_POOL_MBUF_AREA_ALLOC (count, mbufMemSize);
-    IX_OSAL_ASSERT (poolBufPtr != NULL);
-    poolDataPtr =
-        IX_OSAL_MBUF_POOL_DATA_AREA_ALLOC (count, size, dataMemSize);
-    IX_OSAL_ASSERT (poolDataPtr != NULL);
-
-    poolPtr = ixOsalNoAllocPoolInit (poolBufPtr, poolDataPtr,
-        count, size, name);
-    if (poolPtr == NULL)
-    {
-        ixOsalLog (IX_OSAL_LOG_LVL_ERROR,
-            IX_OSAL_LOG_DEV_STDOUT,
-            "ixOsalPoolInit(): " "Fail to get pool ptr \n", 0, 0, 0, 0, 0, 0);
-        return NULL;
-    }
-
-    poolPtr->poolAllocType = IX_OSAL_MBUF_POOL_TYPE_SYS_ALLOC;
-
-#endif /* IX_OSAL_BUFFER_ALLOC_SEPARATELY */
-    return poolPtr;
-}
-
-PUBLIC IX_OSAL_MBUF_POOL *
-ixOsalNoAllocPoolInit (void *poolBufPtr,
-    void *poolDataPtr, UINT32 count, UINT32 size, const char *name)
-{
-    UINT32 i,  mbufSizeAligned, sizeAligned;
-    IX_OSAL_MBUF *currentMbufPtr = NULL;
-    IX_OSAL_MBUF *nextMbufPtr = NULL;
-    IX_OSAL_MBUF_POOL *poolPtr = NULL;
-
-    /*
-     * check parameters 
-     */
-    if (poolBufPtr == NULL)
-    {
-        ixOsalLog (IX_OSAL_LOG_LVL_ERROR,
-            IX_OSAL_LOG_DEV_STDOUT,
-            "ixOsalNoAllocPoolInit(): "
-            "ERROR - NULL poolBufPtr \n", 0, 0, 0, 0, 0, 0);
-        return NULL;
-    }
-
-    if (count <= 0)
-    {
-        ixOsalLog (IX_OSAL_LOG_LVL_ERROR,
-            IX_OSAL_LOG_DEV_STDOUT,
-            "ixOsalNoAllocPoolInit(): "
-            "ERROR - count must > 0   \n", 0, 0, 0, 0, 0, 0);
-        return NULL;
-    }
-
-    if (name == NULL)
-    {
-        ixOsalLog (IX_OSAL_LOG_LVL_ERROR,
-            IX_OSAL_LOG_DEV_STDOUT,
-            "ixOsalNoAllocPoolInit(): "
-            "ERROR - NULL name ptr  \n", 0, 0, 0, 0, 0, 0);
-        return NULL;
-    }
-
-    if (strlen (name) > IX_OSAL_MBUF_POOL_NAME_LEN)
-    {
-        ixOsalLog (IX_OSAL_LOG_LVL_ERROR,
-            IX_OSAL_LOG_DEV_STDOUT,
-            "ixOsalNoAllocPoolInit(): "
-            "ERROR - name length should be no greater than %d  \n",
-            IX_OSAL_MBUF_POOL_NAME_LEN, 0, 0, 0, 0, 0);
-        return NULL;
-    }
-
-    poolPtr = ixOsalPoolAlloc ();
-
-    if (poolPtr == NULL)
-    {
-        return NULL;
-    }
-
-    /*
-     * Adjust sizes to ensure alignment on cache line boundaries 
-     */
-    mbufSizeAligned =
-        IX_OSAL_MBUF_POOL_SIZE_ALIGN (sizeof (IX_OSAL_MBUF));
-    /*
-     * clear the mbuf memory area 
-     */
-    memset (poolBufPtr, 0, mbufSizeAligned * count);
-
-    if (poolDataPtr != NULL)
-    {
-        /*
-         * Adjust sizes to ensure alignment on cache line boundaries 
-         */
-        sizeAligned = IX_OSAL_MBUF_POOL_SIZE_ALIGN (size);
-        /*
-         * clear the data memory area 
-         */
-        memset (poolDataPtr, 0, sizeAligned * count);
-    }
-    else
-    {
-        sizeAligned = 0;
-    }
-
-    /*
-     * initialise pool fields 
-     */
-    strcpy ((poolPtr)->name, name);
-
-    poolPtr->dataMemPtr = poolDataPtr;
-    poolPtr->mbufMemPtr = poolBufPtr;
-    poolPtr->bufDataSize = sizeAligned;
-    poolPtr->totalBufsInPool = count;
-    poolPtr->mbufMemSize = mbufSizeAligned * count;
-    poolPtr->dataMemSize = sizeAligned * count;
-
-    currentMbufPtr = (IX_OSAL_MBUF *) poolBufPtr;
-
-    poolPtr->nextFreeBuf = currentMbufPtr;
-
-    for (i = 0; i < count; i++)
-    {
-        if (i < (count - 1))
-        {
-            nextMbufPtr =
-                (IX_OSAL_MBUF *) ((unsigned) currentMbufPtr +
-                mbufSizeAligned);
-        }
-        else
-        {                       /* last mbuf in chain */
-            nextMbufPtr = NULL;
-        }
-        IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR (currentMbufPtr) = nextMbufPtr;
-        IX_OSAL_MBUF_NET_POOL (currentMbufPtr) = poolPtr;
-
-        IX_OSAL_MBUF_SYS_SIGNATURE_INIT(currentMbufPtr);
-
-        if (poolDataPtr != NULL)
-        {
-            IX_OSAL_MBUF_MDATA (currentMbufPtr) = poolDataPtr;
-            IX_OSAL_MBUF_ALLOCATED_BUFF_DATA(currentMbufPtr) = (UINT32) poolDataPtr;
-
-            IX_OSAL_MBUF_MLEN (currentMbufPtr) = sizeAligned;
-            IX_OSAL_MBUF_ALLOCATED_BUFF_LEN(currentMbufPtr) = sizeAligned;
-
-            poolDataPtr = (void *) ((unsigned) poolDataPtr + sizeAligned);
-        }
-
-        currentMbufPtr = nextMbufPtr;
-    }
-
-    /*
-     * update the number of free buffers in the pool 
-     */
-    poolPtr->freeBufsInPool = count;
-
-    poolPtr->poolAllocType = IX_OSAL_MBUF_POOL_TYPE_USER_ALLOC;
-
-    return poolPtr;
-}
-
-/* 
- * Get a mbuf ptr from the pool
- */
-PUBLIC IX_OSAL_MBUF *
-ixOsalMbufAlloc (IX_OSAL_MBUF_POOL * poolPtr)
-{
-    int lock;
-    IX_OSAL_MBUF *newBufPtr = NULL;
-
-    /*
-     * check parameters 
-     */
-    if (poolPtr == NULL)
-    {
-        ixOsalLog (IX_OSAL_LOG_LVL_ERROR,
-            IX_OSAL_LOG_DEV_STDOUT,
-            "ixOsalMbufAlloc(): "
-            "ERROR - Invalid Parameter\n", 0, 0, 0, 0, 0, 0);
-        return NULL;
-    }
-
-    lock = ixOsalIrqLock ();
-
-    newBufPtr = poolPtr->nextFreeBuf;
-    if (newBufPtr)
-    {
-        poolPtr->nextFreeBuf =
-            IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR (newBufPtr);
-        IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR (newBufPtr) = NULL;
-
-        /*
-         * update the number of free buffers in the pool 
-         */
-        poolPtr->freeBufsInPool--;
-    }
-    else
-    {
-        /* Return NULL to indicate to caller that request is denied. */
-        ixOsalIrqUnlock (lock);
-
-        return NULL;
-    }
-
-#ifdef IX_OSAL_BUFFER_FREE_PROTECTION
-	/* Set Buffer Used Flag to indicate state.*/
-    IX_OSAL_MBUF_SET_USED_FLAG(newBufPtr);
-#endif
-
-    ixOsalIrqUnlock (lock);
-
-    return newBufPtr;
-}
-
-PUBLIC IX_OSAL_MBUF *
-ixOsalMbufFree (IX_OSAL_MBUF * bufPtr)
-{
-    int lock;
-    IX_OSAL_MBUF_POOL *poolPtr;
-
-    IX_OSAL_MBUF *nextBufPtr = NULL;
-
-    /*
-     * check parameters 
-     */
-    if (bufPtr == NULL)
-    {
-        ixOsalLog (IX_OSAL_LOG_LVL_ERROR,
-            IX_OSAL_LOG_DEV_STDOUT,
-            "ixOsalMbufFree(): "
-            "ERROR - Invalid Parameter\n", 0, 0, 0, 0, 0, 0);
-        return NULL;
-    }
-
-
-
-    lock = ixOsalIrqLock ();
-
-#ifdef IX_OSAL_BUFFER_FREE_PROTECTION
-	
-	/* Prevention for Buffer freed more than once*/
-    if(!IX_OSAL_MBUF_ISSET_USED_FLAG(bufPtr))
-    {
-   	return NULL;
-    }
-    IX_OSAL_MBUF_CLEAR_USED_FLAG(bufPtr);
-#endif
-	
-    poolPtr = IX_OSAL_MBUF_NET_POOL (bufPtr);
-
-    /*
-     * check the mbuf wrapper signature (if mbuf wrapper was used) 
-     */
-    if (poolPtr->poolAllocType == IX_OSAL_MBUF_POOL_TYPE_SYS_ALLOC)
-    {
-        IX_OSAL_ENSURE ( (IX_OSAL_MBUF_GET_SYS_SIGNATURE(bufPtr) == IX_OSAL_MBUF_SYS_SIGNATURE),
-            "ixOsalBuffPoolBufFree: ERROR - Invalid mbuf signature.");
-    }
-
-    nextBufPtr = IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR (bufPtr);
-
-    IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR (bufPtr) = poolPtr->nextFreeBuf;
-    poolPtr->nextFreeBuf = bufPtr;
-
-    /*
-     * update the number of free buffers in the pool 
-     */
-    poolPtr->freeBufsInPool++;
-
-    ixOsalIrqUnlock (lock);
-
-    return nextBufPtr;
-}
-
-PUBLIC void
-ixOsalMbufChainFree (IX_OSAL_MBUF * bufPtr)
-{
-    while ((bufPtr = ixOsalMbufFree (bufPtr)));
-}
-
-/*
- * Function definition: ixOsalBuffPoolShow
- */
-PUBLIC void
-ixOsalMbufPoolShow (IX_OSAL_MBUF_POOL * poolPtr)
-{
-    IX_OSAL_MBUF *nextBufPtr;
-    int count = 0;
-    int lock;
-
-    /*
-     * check parameters 
-     */
-    if (poolPtr == NULL)
-    {
-        ixOsalLog (IX_OSAL_LOG_LVL_ERROR,
-            IX_OSAL_LOG_DEV_STDOUT,
-            "ixOsalBuffPoolShow(): "
-            "ERROR - Invalid Parameter", 0, 0, 0, 0, 0, 0);
-        /*
-         * return IX_FAIL; 
-         */
-        return;
-    }
-
-    lock = ixOsalIrqLock ();
-    count = poolPtr->freeBufsInPool;
-    nextBufPtr = poolPtr->nextFreeBuf;
-    ixOsalIrqUnlock (lock);
-
-    ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE,
-        IX_OSAL_LOG_DEV_STDOUT, "=== POOL INFORMATION ===\n", 0, 0, 0,
-        0, 0, 0);
-    ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT,
-        "Pool Name:                   %s\n",
-        (unsigned int) poolPtr->name, 0, 0, 0, 0, 0);
-    ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT,
-        "Pool Allocation Type:        %d\n",
-        (unsigned int) poolPtr->poolAllocType, 0, 0, 0, 0, 0);
-    ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT,
-        "Pool Mbuf Mem Usage (bytes): %d\n",
-        (unsigned int) poolPtr->mbufMemSize, 0, 0, 0, 0, 0);
-    ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT,
-        "Pool Data Mem Usage (bytes): %d\n",
-        (unsigned int) poolPtr->dataMemSize, 0, 0, 0, 0, 0);
-    ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT,
-        "Mbuf Data Capacity  (bytes): %d\n",
-        (unsigned int) poolPtr->bufDataSize, 0, 0, 0, 0, 0);
-    ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT,
-        "Total Mbufs in Pool:         %d\n",
-        (unsigned int) poolPtr->totalBufsInPool, 0, 0, 0, 0, 0);
-    ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT,
-        "Available Mbufs:             %d\n", (unsigned int) count, 0,
-        0, 0, 0, 0);
-    ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT,
-        "Next Available Mbuf:         %p\n", (unsigned int) nextBufPtr,
-        0, 0, 0, 0, 0);
-
-    if (poolPtr->poolAllocType == IX_OSAL_MBUF_POOL_TYPE_USER_ALLOC)
-    {
-        ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE,
-            IX_OSAL_LOG_DEV_STDOUT,
-            "Mbuf Mem Area Start address: %p\n",
-            (unsigned int) poolPtr->mbufMemPtr, 0, 0, 0, 0, 0);
-        ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT,
-            "Data Mem Area Start address: %p\n",
-            (unsigned int) poolPtr->dataMemPtr, 0, 0, 0, 0, 0);
-    }
-}
-
-PUBLIC void
-ixOsalMbufDataPtrReset (IX_OSAL_MBUF * bufPtr)
-{
-    IX_OSAL_MBUF_POOL *poolPtr;
-    UINT8 *poolDataPtr;
-
-    if (bufPtr == NULL)
-    {
-        ixOsalLog (IX_OSAL_LOG_LVL_ERROR, IX_OSAL_LOG_DEV_STDOUT,
-            "ixOsalBuffPoolBufDataPtrReset"
-            ": ERROR - Invalid Parameter\n", 0, 0, 0, 0, 0, 0);
-        return;
-    }
-
-    poolPtr = (IX_OSAL_MBUF_POOL *) IX_OSAL_MBUF_NET_POOL (bufPtr);
-    poolDataPtr = poolPtr->dataMemPtr;
-
-    if (poolPtr->poolAllocType == IX_OSAL_MBUF_POOL_TYPE_SYS_ALLOC)
-    {
-        if (IX_OSAL_MBUF_GET_SYS_SIGNATURE(bufPtr) != IX_OSAL_MBUF_SYS_SIGNATURE)
-        {
-            ixOsalLog (IX_OSAL_LOG_LVL_ERROR, IX_OSAL_LOG_DEV_STDOUT,
-                "ixOsalBuffPoolBufDataPtrReset"
-                ": invalid mbuf, cannot reset mData pointer\n", 0, 0,
-                0, 0, 0, 0);
-            return;
-        }
-        IX_OSAL_MBUF_MDATA (bufPtr) = (UINT8*)IX_OSAL_MBUF_ALLOCATED_BUFF_DATA (bufPtr);
-    }
-    else
-    {
-        if (poolDataPtr)
-        {
-            unsigned int bufSize = poolPtr->bufDataSize;
-            unsigned int bufDataAddr =
-                (unsigned int) IX_OSAL_MBUF_MDATA (bufPtr);
-            unsigned int poolDataAddr = (unsigned int) poolDataPtr;
-
-            /*
-             * the pointer is still pointing somewhere in the mbuf payload.
-             * This operation moves the pointer to the beginning of the 
-             * mbuf payload
-             */
-            bufDataAddr = ((bufDataAddr - poolDataAddr) / bufSize) * bufSize;
-            IX_OSAL_MBUF_MDATA (bufPtr) = &poolDataPtr[bufDataAddr];
-        }
-        else
-        {
-            ixOsalLog (IX_OSAL_LOG_LVL_WARNING, IX_OSAL_LOG_DEV_STDOUT,
-                "ixOsalBuffPoolBufDataPtrReset"
-                ": cannot be used if user supplied NULL pointer for pool data area "
-                "when pool was created\n", 0, 0, 0, 0, 0, 0);
-            return;
-        }
-    }
-
-}
-
-/*
- * Function definition: ixOsalBuffPoolUninit
- */
-PUBLIC IX_STATUS
-ixOsalBuffPoolUninit (IX_OSAL_MBUF_POOL * pool)
-{
-    if (!pool)
-    {
-        ixOsalLog (IX_OSAL_LOG_LVL_ERROR, IX_OSAL_LOG_DEV_STDOUT,
-            "ixOsalBuffPoolUninit: NULL ptr \n", 0, 0, 0, 0, 0, 0);
-        return IX_FAIL;
-    }
-
-    if (pool->freeBufsInPool != pool->totalBufsInPool)
-    {
-        ixOsalLog (IX_OSAL_LOG_LVL_ERROR, IX_OSAL_LOG_DEV_STDOUT,
-            "ixOsalBuffPoolUninit: need to return all ptrs to the pool first! \n",
-            0, 0, 0, 0, 0, 0);
-        return IX_FAIL;
-    }
-
-    if (pool->poolAllocType == IX_OSAL_MBUF_POOL_TYPE_SYS_ALLOC)
-    {
-#ifdef IX_OSAL_BUFFER_ALLOC_SEPARATELY
-				UINT32 i;
-				IX_OSAL_MBUF* pBuf;
-				
-				pBuf = pool->nextFreeBuf;
-				/* Freed the Buffer one by one till all the Memory is freed*/
-				for (i= pool->freeBufsInPool; i >0 && pBuf!=NULL ;i--){
-						IX_OSAL_MBUF* pBufTemp;
-						pBufTemp = IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR(pBuf);
-						/* Freed MBUF Data Memory area*/
-						IX_OSAL_CACHE_DMA_FREE( (void *) (IX_OSAL_MBUF_ALLOCATED_BUFF_DATA(pBuf)) );
-						/* Freed MBUF Struct Memory area*/
-						IX_OSAL_CACHE_DMA_FREE(pBuf);
-						pBuf = pBufTemp;
-				}
-				
-#else    	
-        IX_OSAL_CACHE_DMA_FREE (pool->mbufMemPtr);
-        IX_OSAL_CACHE_DMA_FREE (pool->dataMemPtr);
-#endif        
-    }
-
-    ixOsalBuffFreePools[pool->poolIdx / IX_OSAL_BUFF_FREE_BITS] &=
-        ~(1 << (pool->poolIdx % IX_OSAL_BUFF_FREE_BITS));
-    ixOsalBuffPoolsInUse--;
-    return IX_SUCCESS;
-}
-
-/*
- * Function definition: ixOsalBuffPoolDataAreaSizeGet
- */
-PUBLIC UINT32
-ixOsalBuffPoolDataAreaSizeGet (int count, int size)
-{
-    UINT32 memorySize;
-    memorySize = count * IX_OSAL_MBUF_POOL_SIZE_ALIGN (size);
-    return memorySize;
-}
-
-/*
- * Function definition: ixOsalBuffPoolMbufAreaSizeGet
- */
-PUBLIC UINT32
-ixOsalBuffPoolMbufAreaSizeGet (int count)
-{
-    UINT32 memorySize;
-    memorySize =
-        count * IX_OSAL_MBUF_POOL_SIZE_ALIGN (sizeof (IX_OSAL_MBUF));
-    return memorySize;
-}
-
-/*
- * Function definition: ixOsalBuffPoolFreeCountGet
- */
-PUBLIC UINT32 ixOsalBuffPoolFreeCountGet(IX_OSAL_MBUF_POOL * poolPtr)
-
-{
-
-   return poolPtr->freeBufsInPool;
-
-}
-
-#endif /* IX_OSAL_USE_DEFAULT_BUFFER_MGT */
diff --git a/arch/arm/cpu/ixp/npe/IxOsalIoMem.c b/arch/arm/cpu/ixp/npe/IxOsalIoMem.c
deleted file mode 100644
index 34df92b..0000000
--- a/arch/arm/cpu/ixp/npe/IxOsalIoMem.c
+++ /dev/null
@@ -1,332 +0,0 @@
-/**
- * @file IxOsalIoMem.c 
- *
- * @brief OS-independent IO/Mem implementation 
- * 
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- * 
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- * 
- * @par
- * -- End of Copyright Notice --
- */
-
-/* Access to the global mem map is only allowed in this file */
-#define IxOsalIoMem_C
-
-#include "IxOsal.h"
-
-#define SEARCH_PHYSICAL_ADDRESS (1)
-#define SEARCH_VIRTUAL_ADDRESS  (2)
-
-/*
- * Searches for map using one of the following criteria:
- * 
- * - enough room to include a zone starting with the physical "requestedAddress" of size "size" (for mapping)
- * - includes the virtual "requestedAddress" in its virtual address space (already mapped, for unmapping)
- * - correct coherency
- *
- * Returns a pointer to the map or NULL if a suitable map is not found.
- */
-PRIVATE IxOsalMemoryMap *
-ixOsalMemMapFind (UINT32 requestedAddress,
-    UINT32 size, UINT32 searchCriteria, UINT32 requestedEndianType)
-{
-    UINT32 mapIndex;
-
-    UINT32 numMapElements =
-        sizeof (ixOsalGlobalMemoryMap) / sizeof (IxOsalMemoryMap);
-
-    for (mapIndex = 0; mapIndex < numMapElements; mapIndex++)
-    {
-        IxOsalMemoryMap *map = &ixOsalGlobalMemoryMap[mapIndex];
-
-        if (searchCriteria == SEARCH_PHYSICAL_ADDRESS
-            && requestedAddress >= map->physicalAddress
-            && (requestedAddress + size) <= (map->physicalAddress + map->size)
-            && (map->mapEndianType & requestedEndianType) != 0)
-        {
-            return map;
-        }
-        else if (searchCriteria == SEARCH_VIRTUAL_ADDRESS
-            && requestedAddress >= map->virtualAddress
-            && requestedAddress <= (map->virtualAddress + map->size)
-            && (map->mapEndianType & requestedEndianType) != 0)
-        {
-            return map;
-        }
-        else if (searchCriteria == SEARCH_PHYSICAL_ADDRESS)
-        {
-            ixOsalLog (IX_OSAL_LOG_LVL_DEBUG3,
-                IX_OSAL_LOG_DEV_STDOUT,
-                "Osal: Checking [phys addr 0x%x:size 0x%x:endianType %d]\n",
-                map->physicalAddress, map->size, map->mapEndianType, 0, 0, 0);
-        }
-    }
-
-    /*
-     * not found 
-     */
-    return NULL;
-}
-
-/*
- * This function maps an I/O mapped physical memory zone of the given size
- * into a virtual memory zone accessible by the caller and returns a cookie - 
- * the start address of the virtual memory zone. 
- * IX_OSAL_MMAP_PHYS_TO_VIRT should NOT therefore be used on the returned 
- * virtual address.
- * The memory zone is to be unmapped using ixOsalMemUnmap once the caller has
- * finished using this zone (e.g. on driver unload) using the cookie as 
- * parameter.
- * The IX_OSAL_READ/WRITE_LONG/SHORT macros should be used to read and write 
- * the mapped memory, adding the necessary offsets to the address cookie.
- *
- * Note: this function is not to be used directly. Use IX_OSAL_MEM_MAP 
- * instead.
- */
-PUBLIC void *
-ixOsalIoMemMap (UINT32 requestedAddress,
-    UINT32 size, IxOsalMapEndianessType requestedEndianType)
-{
-    IxOsalMemoryMap *map;
-
-    ixOsalLog (IX_OSAL_LOG_LVL_DEBUG3,
-        IX_OSAL_LOG_DEV_STDOUT,
-        "OSAL: Mapping [addr 0x%x:size 0x%x:endianType %d]\n",
-        requestedAddress, size, requestedEndianType, 0, 0, 0);
-
-    if (requestedEndianType == IX_OSAL_LE)
-    {
-        ixOsalLog (IX_OSAL_LOG_LVL_ERROR,
-            IX_OSAL_LOG_DEV_STDOUT,
-            "ixOsalIoMemMap: Please specify component coherency mode to use MEM functions \n",
-            0, 0, 0, 0, 0, 0);
-        return (NULL);
-    }
-    map = ixOsalMemMapFind (requestedAddress,
-        size, SEARCH_PHYSICAL_ADDRESS, requestedEndianType);
-    if (map != NULL)
-    {
-        UINT32 offset = requestedAddress - map->physicalAddress;
-
-        ixOsalLog (IX_OSAL_LOG_LVL_DEBUG3,
-            IX_OSAL_LOG_DEV_STDOUT, "OSAL: Found map [", 0, 0, 0, 0, 0, 0);
-        ixOsalLog (IX_OSAL_LOG_LVL_DEBUG3,
-            IX_OSAL_LOG_DEV_STDOUT, map->name, 0, 0, 0, 0, 0, 0);
-        ixOsalLog (IX_OSAL_LOG_LVL_DEBUG3,
-            IX_OSAL_LOG_DEV_STDOUT,
-            ":addr 0x%x: virt 0x%x:size 0x%x:ref %d:endianType %d]\n",
-            map->physicalAddress, map->virtualAddress,
-            map->size, map->refCount, map->mapEndianType, 0);
-
-        if (map->type == IX_OSAL_DYNAMIC_MAP && map->virtualAddress == 0)
-        {
-            if (map->mapFunction != NULL)
-            {
-                map->mapFunction (map);
-
-                if (map->virtualAddress == 0)
-                {
-                    /*
-                     * failed 
-                     */
-                    ixOsalLog (IX_OSAL_LOG_LVL_FATAL,
-                        IX_OSAL_LOG_DEV_STDERR,
-                        "OSAL: Remap failed - [addr 0x%x:size 0x%x:endianType %d]\n",
-                        requestedAddress, size, requestedEndianType, 0, 0, 0);
-                    return NULL;
-                }
-            }
-            else
-            {
-                /*
-                 * error, no map function for a dynamic map 
-                 */
-                ixOsalLog (IX_OSAL_LOG_LVL_FATAL,
-                    IX_OSAL_LOG_DEV_STDERR,
-                    "OSAL: No map function for a dynamic map - "
-                    "[addr 0x%x:size 0x%x:endianType %d]\n",
-                    requestedAddress, size, requestedEndianType, 0, 0, 0);
-
-                return NULL;
-            }
-        }
-
-        /*
-         * increment reference count 
-         */
-        map->refCount++;
-
-        return (void *) (map->virtualAddress + offset);
-    }
-
-    /*
-     * requested address is not described in the global memory map 
-     */
-    ixOsalLog (IX_OSAL_LOG_LVL_FATAL,
-        IX_OSAL_LOG_DEV_STDERR,
-        "OSAL: No mapping found - [addr 0x%x:size 0x%x:endianType %d]\n",
-        requestedAddress, size, requestedEndianType, 0, 0, 0);
-    return NULL;
-}
-
-/*
- * This function unmaps a previously mapped I/O memory zone using
- * the cookie obtained in the mapping operation. The memory zone in question
- * becomes unavailable to the caller once unmapped and the cookie should be
- * discarded.
- *
- * This function cannot fail if the given parameter is correct and does not
- * return a value.
- *
- * Note: this function is not to be used directly. Use IX_OSAL_MEM_UNMAP
- * instead.
- */
-PUBLIC void
-ixOsalIoMemUnmap (UINT32 requestedAddress, UINT32 endianType)
-{
-    IxOsalMemoryMap *map;
-
-    if (endianType == IX_OSAL_LE)
-    {
-        ixOsalLog (IX_OSAL_LOG_LVL_ERROR,
-            IX_OSAL_LOG_DEV_STDOUT,
-            "ixOsalIoMemUnmap: Please specify component coherency mode to use MEM functions \n",
-            0, 0, 0, 0, 0, 0);
-        return;
-    }
-
-    if (requestedAddress == 0)
-    {
-        /*
-         * invalid virtual address 
-         */
-        return;
-    }
-
-    map =
-        ixOsalMemMapFind (requestedAddress, 0, SEARCH_VIRTUAL_ADDRESS,
-        endianType);
-
-    if (map != NULL)
-    {
-        if (map->refCount > 0)
-        {
-            /*
-             * decrement reference count 
-             */
-            map->refCount--;
-
-            if (map->refCount == 0)
-            {
-                /*
-                 * no longer used, deallocate 
-                 */
-                if (map->type == IX_OSAL_DYNAMIC_MAP
-                    && map->unmapFunction != NULL)
-                {
-                    map->unmapFunction (map);
-                }
-            }
-        }
-    }
-    else
-    {
-        ixOsalLog (IX_OSAL_LOG_LVL_WARNING,
-            IX_OSAL_LOG_DEV_STDERR,
-            "OSAL: ixOsServMemUnmap didn't find the requested map "
-            "[virt addr 0x%x: endianType %d], ignoring call\n",
-            requestedAddress, endianType, 0, 0, 0, 0);
-    }
-}
-
-/* 
- * This function Converts a virtual address into a physical 
- * address, including the dynamically mapped memory.
- * 
- * Parameters	virtAddr - virtual address to convert
- * Return value: corresponding physical address, or NULL 
- *               if there is no physical address addressable 
- *               by the given virtual address
- * OS:	VxWorks, Linux, WinCE, QNX, eCos
- * Reentrant: Yes
- * IRQ safe: Yes
- */
-PUBLIC UINT32
-ixOsalIoMemVirtToPhys (UINT32 virtualAddress, UINT32 requestedCoherency)
-{
-    IxOsalMemoryMap *map =
-        ixOsalMemMapFind (virtualAddress, 0, SEARCH_VIRTUAL_ADDRESS,
-        requestedCoherency);
-
-    if (map != NULL)
-    {
-        return map->physicalAddress + virtualAddress - map->virtualAddress;
-    }
-    else
-    {
-        return (UINT32) IX_OSAL_MMU_VIRT_TO_PHYS (virtualAddress);
-    }
-}
-
-/* 
- * This function Converts a virtual address into a physical 
- * address, including the dynamically mapped memory.
- * 
- * Parameters	virtAddr - virtual address to convert
- * Return value: corresponding physical address, or NULL 
- *               if there is no physical address addressable 
- *               by the given virtual address
- * OS:	VxWorks, Linux, WinCE, QNX, eCos
- * Reentrant: Yes
- * IRQ safe: Yes
- */
-PUBLIC UINT32
-ixOsalIoMemPhysToVirt (UINT32 physicalAddress, UINT32 requestedCoherency)
-{
-    IxOsalMemoryMap *map =
-        ixOsalMemMapFind (physicalAddress, 0, SEARCH_PHYSICAL_ADDRESS,
-        requestedCoherency);
-
-    if (map != NULL)
-    {
-        return map->virtualAddress + physicalAddress - map->physicalAddress;
-    }
-    else
-    {
-        return (UINT32) IX_OSAL_MMU_PHYS_TO_VIRT (physicalAddress);
-    }
-}
diff --git a/arch/arm/cpu/ixp/npe/IxOsalOsCacheMMU.c b/arch/arm/cpu/ixp/npe/IxOsalOsCacheMMU.c
deleted file mode 100644
index 3db1a70..0000000
--- a/arch/arm/cpu/ixp/npe/IxOsalOsCacheMMU.c
+++ /dev/null
@@ -1,67 +0,0 @@
-/**
- * @file IxOsalOsCacheMMU.c (linux)
- *
- * @brief Cache MemAlloc and MemFree.
- *
- *
- * @par
- * IXP400 SW Release version 1.5
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
- */
-
-#include "IxOsal.h"
-
-#include <malloc.h>
-
-/*
- * Allocate on a cache line boundary (null pointers are
- * not affected by this operation). This operation is NOT cache safe.
- */
-void *
-ixOsalCacheDmaMalloc (UINT32 n)
-{
-	return malloc(n);
-}
-
-/*
- *
- */
-void
-ixOsalCacheDmaFree (void *ptr)
-{
-	free(ptr);
-}
diff --git a/arch/arm/cpu/ixp/npe/IxOsalOsMsgQ.c b/arch/arm/cpu/ixp/npe/IxOsalOsMsgQ.c
deleted file mode 100644
index 45a5c68..0000000
--- a/arch/arm/cpu/ixp/npe/IxOsalOsMsgQ.c
+++ /dev/null
@@ -1,79 +0,0 @@
-/**
- * @file IxOsalOsMsgQ.c (eCos)
- *
- * @brief OS-specific Message Queue implementation.
- *
- *
- * @par
- * IXP400 SW Release version 1.5
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
- */
-
-#include "IxOsal.h"
-
-/*******************************
- * Public functions
- *******************************/
-PUBLIC IX_STATUS
-ixOsalMessageQueueCreate (IxOsalMessageQueue * queue,
-    UINT32 msgCount, UINT32 msgLen)
-{
-    diag_printf("%s called\n", __FUNCTION__);
-    return IX_FAIL;
-}
-
-PUBLIC IX_STATUS
-ixOsalMessageQueueDelete (IxOsalMessageQueue * queue)
-{
-    diag_printf("%s called\n", __FUNCTION__);
-    return IX_FAIL;
-}
-
-PUBLIC IX_STATUS
-ixOsalMessageQueueSend (IxOsalMessageQueue * queue, UINT8 * message)
-{
-    diag_printf("%s called\n", __FUNCTION__);
-    return IX_FAIL;
-}
-
-PUBLIC IX_STATUS
-ixOsalMessageQueueReceive (IxOsalMessageQueue * queue, UINT8 * message)
-{
-    diag_printf("%s called\n", __FUNCTION__);
-    return IX_FAIL;
-}
-
diff --git a/arch/arm/cpu/ixp/npe/IxOsalOsSemaphore.c b/arch/arm/cpu/ixp/npe/IxOsalOsSemaphore.c
deleted file mode 100644
index 443aefd..0000000
--- a/arch/arm/cpu/ixp/npe/IxOsalOsSemaphore.c
+++ /dev/null
@@ -1,233 +0,0 @@
-/**
- * @file IxOsalOsSemaphore.c (eCos)
- *
- * @brief Implementation for semaphore and mutex.
- *
- *
- * @par
- * IXP400 SW Release version 1.5
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
- */
-
-#include "IxOsal.h"
-#include "IxNpeMhReceive_p.h"
-
-/* Define a large number */
-#define IX_OSAL_MAX_LONG (0x7FFFFFFF)
-
-/* Max timeout in MS, used to guard against possible overflow */
-#define IX_OSAL_MAX_TIMEOUT_MS (IX_OSAL_MAX_LONG/HZ)
-
-
-PUBLIC IX_STATUS
-ixOsalSemaphoreInit (IxOsalSemaphore * sid, UINT32 start_value)
-{
-    diag_printf("%s called\n", __FUNCTION__);
-    return IX_SUCCESS;
-}
-
-/**
- * DESCRIPTION: If the semaphore is 'empty', the calling thread is blocked.
- *              If the semaphore is 'full', it is taken and control is returned
- *              to the caller. If the time indicated in 'timeout' is reached,
- *              the thread will unblock and return an error indication. If the
- *              timeout is set to 'IX_OSAL_WAIT_NONE', the thread will never block;
- *              if it is set to 'IX_OSAL_WAIT_FOREVER', the thread will block until
- *              the semaphore is available.
- *
- *
- */
-
-
-PUBLIC IX_STATUS
-ixOsalSemaphoreWait (IxOsalOsSemaphore * sid, INT32 timeout)
-{
-    diag_printf("%s called\n", __FUNCTION__);
-    return IX_SUCCESS;
-}
-
-/*
- * Attempt to get semaphore, return immediately,
- * no error info because users expect some failures
- * when using this API.
- */
-PUBLIC IX_STATUS
-ixOsalSemaphoreTryWait (IxOsalSemaphore * sid)
-{
-    diag_printf("%s called\n", __FUNCTION__);
-    return IX_FAIL;
-}
-
-/**
- *
- * DESCRIPTION: This function causes the next available thread in the pend queue
- *              to be unblocked. If no thread is pending on this semaphore, the
- *              semaphore becomes 'full'.
- */
-PUBLIC IX_STATUS
-ixOsalSemaphorePost (IxOsalSemaphore * sid)
-{
-    diag_printf("%s called\n", __FUNCTION__);
-    return IX_SUCCESS;
-}
-
-PUBLIC IX_STATUS
-ixOsalSemaphoreGetValue (IxOsalSemaphore * sid, UINT32 * value)
-{
-    diag_printf("%s called\n", __FUNCTION__);
-    return IX_FAIL;
-}
-
-PUBLIC IX_STATUS
-ixOsalSemaphoreDestroy (IxOsalSemaphore * sid)
-{
-    diag_printf("%s called\n", __FUNCTION__);
-    return IX_FAIL;
-}
-
-/****************************
- *    Mutex
- ****************************/
-
-static void drv_mutex_init(IxOsalMutex *mutex)
-{
-	*mutex = 0;
-}
-
-static void drv_mutex_destroy(IxOsalMutex *mutex)
-{
-	*mutex = -1;
-}
-
-static int drv_mutex_trylock(IxOsalMutex *mutex)
-{
-	int result = TRUE;
-
-	if (*mutex == 1)
-		result = FALSE;
-
-	return result;
-}
-
-static void drv_mutex_unlock(IxOsalMutex *mutex)
-{
-	if (*mutex == 1)
-		printf("Trying to unlock unlocked mutex!");
-
-	*mutex = 0;
-}
-
-PUBLIC IX_STATUS
-ixOsalMutexInit (IxOsalMutex * mutex)
-{
-    drv_mutex_init(mutex);
-    return IX_SUCCESS;
-}
-
-PUBLIC IX_STATUS
-ixOsalMutexLock (IxOsalMutex * mutex, INT32 timeout)
-{
-    int tries;
-
-    if (timeout == IX_OSAL_WAIT_NONE) {
-	if (drv_mutex_trylock(mutex))
-	    return IX_SUCCESS;
-	else
-	    return IX_FAIL;
-    }
-
-    tries = (timeout * 1000) / 50;
-    while (1) {
-	if (drv_mutex_trylock(mutex))
-	    return IX_SUCCESS;
-	if (timeout != IX_OSAL_WAIT_FOREVER && tries-- <= 0)
-	    break;
-	udelay(50);
-    }
-    return IX_FAIL;
-}
-
-PUBLIC IX_STATUS
-ixOsalMutexUnlock (IxOsalMutex * mutex)
-{
-    drv_mutex_unlock(mutex);
-    return IX_SUCCESS;
-}
-
-/*
- * Attempt to get mutex, return immediately,
- * no error info because users expect some failures
- * when using this API.
- */
-PUBLIC IX_STATUS
-ixOsalMutexTryLock (IxOsalMutex * mutex)
-{
-    if (drv_mutex_trylock(mutex))
-	return IX_SUCCESS;
-    return IX_FAIL;
-}
-
-PUBLIC IX_STATUS
-ixOsalMutexDestroy (IxOsalMutex * mutex)
-{
-    drv_mutex_destroy(mutex);
-    return IX_SUCCESS;
-}
-
-PUBLIC IX_STATUS
-ixOsalFastMutexInit (IxOsalFastMutex * mutex)
-{
-    return ixOsalMutexInit(mutex);
-}
-
-PUBLIC IX_STATUS ixOsalFastMutexTryLock(IxOsalFastMutex *mutex)
-{
-    return ixOsalMutexTryLock(mutex);
-}
-
-
-PUBLIC IX_STATUS
-ixOsalFastMutexUnlock (IxOsalFastMutex * mutex)
-{
-    return ixOsalMutexUnlock(mutex);
-}
-
-PUBLIC IX_STATUS
-ixOsalFastMutexDestroy (IxOsalFastMutex * mutex)
-{
-    return ixOsalMutexDestroy(mutex);
-}
diff --git a/arch/arm/cpu/ixp/npe/IxOsalOsServices.c b/arch/arm/cpu/ixp/npe/IxOsalOsServices.c
deleted file mode 100644
index e18c6c4..0000000
--- a/arch/arm/cpu/ixp/npe/IxOsalOsServices.c
+++ /dev/null
@@ -1,251 +0,0 @@
-/**
- * @file IxOsalOsServices.c (linux)
- *
- * @brief Implementation for Irq, Mem, sleep.
- *
- *
- * @par
- * IXP400 SW Release version 1.5
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
- */
-
-#include <config.h>
-#include <common.h>
-#include "IxOsal.h"
-#include <IxEthAcc.h>
-#include <IxEthDB.h>
-#include <IxNpeDl.h>
-#include <IxQMgr.h>
-#include <IxNpeMh.h>
-
-static char *traceHeaders[] = {
-    "",
-    "[fatal] ",
-    "[error] ",
-    "[warning] ",
-    "[message] ",
-    "[debug1] ",
-    "[debug2] ",
-    "[debug3] ",
-    "[all]"
-};
-
-/* by default trace all but debug message */
-PRIVATE int ixOsalCurrLogLevel = IX_OSAL_LOG_LVL_MESSAGE;
-
-/**************************************
- * Irq services
- *************************************/
-
-PUBLIC IX_STATUS
-ixOsalIrqBind (UINT32 vector, IxOsalVoidFnVoidPtr routine, void *parameter)
-{
-    return IX_FAIL;
-}
-
-PUBLIC IX_STATUS
-ixOsalIrqUnbind (UINT32 vector)
-{
-    return IX_FAIL;
-}
-
-PUBLIC UINT32
-ixOsalIrqLock ()
-{
-    return 0;
-}
-
-/* Enable interrupts and task scheduling,
- * input parameter: irqEnable status returned
- * by ixOsalIrqLock().
- */
-PUBLIC void
-ixOsalIrqUnlock (UINT32 lockKey)
-{
-}
-
-PUBLIC UINT32
-ixOsalIrqLevelSet (UINT32 level)
-{
-    return IX_FAIL;
-}
-
-PUBLIC void
-ixOsalIrqEnable (UINT32 irqLevel)
-{
-}
-
-PUBLIC void
-ixOsalIrqDisable (UINT32 irqLevel)
-{
-}
-
-/*********************
- * Log function
- *********************/
-
-INT32
-ixOsalLog (IxOsalLogLevel level,
-    IxOsalLogDevice device,
-    char *format, int arg1, int arg2, int arg3, int arg4, int arg5, int arg6)
-{
-    /*
-     * Return -1 for custom display devices
-     */
-    if ((device != IX_OSAL_LOG_DEV_STDOUT)
-        && (device != IX_OSAL_LOG_DEV_STDERR))
-    {
-        debug("ixOsalLog: only IX_OSAL_LOG_DEV_STDOUT and IX_OSAL_LOG_DEV_STDERR are supported \n");
-        return (IX_OSAL_LOG_ERROR);
-    }
-
-    if (level <= ixOsalCurrLogLevel && level != IX_OSAL_LOG_LVL_NONE)
-    {
-#if 0 /* sr: U-Boots printf or debug doesn't return a length */
-        int headerByteCount = (level == IX_OSAL_LOG_LVL_USER) ? 0 : diag_printf(traceHeaders[level - 1]);
-
-        return headerByteCount + diag_printf (format, arg1, arg2, arg3, arg4, arg5, arg6);
-#else
-        int headerByteCount = (level == IX_OSAL_LOG_LVL_USER) ? 0 : strlen(traceHeaders[level - 1]);
-
-        return headerByteCount + strlen(format);
-#endif
-    }
-    else
-    {
-        /*
-         * Return error
-         */
-        return (IX_OSAL_LOG_ERROR);
-    }
-}
-
-PUBLIC UINT32
-ixOsalLogLevelSet (UINT32 level)
-{
-    UINT32 oldLevel;
-
-    /*
-     * Check value first
-     */
-    if ((level < IX_OSAL_LOG_LVL_NONE) || (level > IX_OSAL_LOG_LVL_ALL))
-    {
-        ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE,
-            IX_OSAL_LOG_DEV_STDOUT,
-            "ixOsalLogLevelSet: Log Level is between %d and%d \n",
-            IX_OSAL_LOG_LVL_NONE, IX_OSAL_LOG_LVL_ALL, 0, 0, 0, 0);
-        return IX_OSAL_LOG_LVL_NONE;
-    }
-    oldLevel = ixOsalCurrLogLevel;
-
-    ixOsalCurrLogLevel = level;
-
-    return oldLevel;
-}
-
-/**************************************
- * Task services
- *************************************/
-
-PUBLIC void
-ixOsalBusySleep (UINT32 microseconds)
-{
-	udelay(microseconds);
-}
-
-PUBLIC void
-ixOsalSleep (UINT32 milliseconds)
-{
-    if (milliseconds != 0) {
-#if 1
-	/*
-	 * sr: We poll while we wait because interrupts are off in U-Boot
-	 * and CSR expects messages, etc to be dispatched while sleeping.
-	 */
-	int i;
-	IxQMgrDispatcherFuncPtr qDispatcherFunc;
-
-	ixQMgrDispatcherLoopGet(&qDispatcherFunc);
-
-	while (milliseconds--) {
-		for (i = 1; i <= 2; i++)
-			ixNpeMhMessagesReceive(i);
-		(*qDispatcherFunc)(IX_QMGR_QUELOW_GROUP);
-
-		udelay(1000);
-	}
-#endif
-    }
-}
-
-/**************************************
- * Memory functions
- *************************************/
-
-void *
-ixOsalMemAlloc (UINT32 size)
-{
-    return (void *)0;
-}
-
-void
-ixOsalMemFree (void *ptr)
-{
-}
-
-/*
- * Copy count bytes from src to dest ,
- * returns pointer to the dest mem zone.
- */
-void *
-ixOsalMemCopy (void *dest, void *src, UINT32 count)
-{
-    IX_OSAL_ASSERT (dest != NULL);
-    IX_OSAL_ASSERT (src != NULL);
-    return (memcpy (dest, src, count));
-}
-
-/*
- * Fills a memory zone with a given constant byte,
- * returns pointer to the memory zone.
- */
-void *
-ixOsalMemSet (void *ptr, UINT8 filler, UINT32 count)
-{
-    IX_OSAL_ASSERT (ptr != NULL);
-    return (memset (ptr, filler, count));
-}
diff --git a/arch/arm/cpu/ixp/npe/IxOsalOsThread.c b/arch/arm/cpu/ixp/npe/IxOsalOsThread.c
deleted file mode 100644
index e6a4967..0000000
--- a/arch/arm/cpu/ixp/npe/IxOsalOsThread.c
+++ /dev/null
@@ -1,98 +0,0 @@
-/**
- * @file IxOsalOsThread.c (eCos)
- *
- * @brief OS-specific thread implementation.
- *
- *
- * @par
- * IXP400 SW Release version 1.5
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
- */
-
-#include "IxOsal.h"
-
-/* Thread attribute is ignored */
-PUBLIC IX_STATUS
-ixOsalThreadCreate (IxOsalThread * ptrTid,
-    IxOsalThreadAttr * threadAttr, IxOsalVoidFnVoidPtr entryPoint, void *arg)
-{
-    return IX_SUCCESS;
-}
-
-/*
- * Start thread after given its thread handle
- */
-PUBLIC IX_STATUS
-ixOsalThreadStart (IxOsalThread * tId)
-{
-    /* Thread already started upon creation */
-    return IX_SUCCESS;
-}
-
-/*
- * In Linux threadKill does not actually destroy the thread,
- * it will stop the signal handling.
- */
-PUBLIC IX_STATUS
-ixOsalThreadKill (IxOsalThread * tid)
-{
-    return IX_SUCCESS;
-}
-
-PUBLIC void
-ixOsalThreadExit (void)
-{
-}
-
-PUBLIC IX_STATUS
-ixOsalThreadPrioritySet (IxOsalOsThread * tid, UINT32 priority)
-{
-    return IX_SUCCESS;
-}
-
-PUBLIC IX_STATUS
-ixOsalThreadSuspend (IxOsalThread * tId)
-{
-    return IX_SUCCESS;
-
-}
-
-PUBLIC IX_STATUS
-ixOsalThreadResume (IxOsalThread * tId)
-{
-    return IX_SUCCESS;
-}
diff --git a/arch/arm/cpu/ixp/npe/IxQMgrAqmIf.c b/arch/arm/cpu/ixp/npe/IxQMgrAqmIf.c
deleted file mode 100644
index 7386513..0000000
--- a/arch/arm/cpu/ixp/npe/IxQMgrAqmIf.c
+++ /dev/null
@@ -1,963 +0,0 @@
-/* 
- * @file:    IxQMgrAqmIf.c
- *
- * @author Intel Corporation
- * @date     30-Oct-2001
- *
- * @brief    This component provides a set of functions for
- * perfoming I/O on the AQM hardware.
- * 
- * Design Notes: 
- *              These functions are intended to be as fast as possible
- * and as a result perform NO PARAMETER CHECKING.
- *
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- * 
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- * 
- * @par
- * -- End of Copyright Notice --
-*/
-
-/*
- * Inlines are compiled as function when this is defined.
- * N.B. Must be placed before #include of "IxQMgrAqmIf_p.h
- */
-#ifndef IXQMGRAQMIF_P_H
-#    define IXQMGRAQMIF_C
-#else
-#    error
-#endif
-
-/*
- * User defined include files.
- */
-#include "IxOsal.h"
-#include "IxQMgr.h"
-#include "IxQMgrAqmIf_p.h"
-#include "IxQMgrLog_p.h"
-
-
-/*
- * #defines and macros used in this file.
- */
-
-/* These defines are the bit offsets of the various fields of
- * the queue configuration register
- */
-#define IX_QMGR_Q_CONFIG_WRPTR_OFFSET       0x00
-#define IX_QMGR_Q_CONFIG_RDPTR_OFFSET       0x07
-#define IX_QMGR_Q_CONFIG_BADDR_OFFSET       0x0E
-#define IX_QMGR_Q_CONFIG_ESIZE_OFFSET       0x16
-#define IX_QMGR_Q_CONFIG_BSIZE_OFFSET       0x18
-#define IX_QMGR_Q_CONFIG_NE_OFFSET          0x1A
-#define IX_QMGR_Q_CONFIG_NF_OFFSET          0x1D
-
-#define IX_QMGR_BASE_ADDR_16_WORD_ALIGN     0x40
-#define IX_QMGR_BASE_ADDR_16_WORD_SHIFT     0x6
-
-#define IX_QMGR_NE_NF_CLEAR_MASK            0x03FFFFFF
-#define IX_QMGR_NE_MASK                     0x7
-#define IX_QMGR_NF_MASK                     0x7
-#define IX_QMGR_SIZE_MASK                   0x3
-#define IX_QMGR_ENTRY_SIZE_MASK             0x3
-#define IX_QMGR_BADDR_MASK                  0x003FC000
-#define IX_QMGR_RDPTR_MASK                  0x7F
-#define IX_QMGR_WRPTR_MASK                  0x7F
-#define IX_QMGR_RDWRPTR_MASK                0x00003FFF
-
-#define IX_QMGR_AQM_ADDRESS_SPACE_SIZE_IN_WORDS 0x1000
-
-/* Base address of AQM SRAM */
-#define IX_QMGR_AQM_SRAM_BASE_ADDRESS_OFFSET \
-((IX_QMGR_QUECONFIG_BASE_OFFSET) + (IX_QMGR_QUECONFIG_SIZE))
-
-/* Min buffer size used for generating buffer size in QUECONFIG */
-#define IX_QMGR_MIN_BUFFER_SIZE 16
-
-/* Reset values of QMgr hardware registers */
-#define IX_QMGR_QUELOWSTAT_RESET_VALUE    0x33333333
-#define IX_QMGR_QUEUOSTAT_RESET_VALUE     0x00000000
-#define IX_QMGR_QUEUPPSTAT0_RESET_VALUE   0xFFFFFFFF
-#define IX_QMGR_QUEUPPSTAT1_RESET_VALUE   0x00000000
-#define IX_QMGR_INT0SRCSELREG_RESET_VALUE 0x00000000
-#define IX_QMGR_QUEIEREG_RESET_VALUE      0x00000000
-#define IX_QMGR_QINTREG_RESET_VALUE       0xFFFFFFFF
-#define IX_QMGR_QUECONFIG_RESET_VALUE     0x00000000
-
-#define IX_QMGR_PHYSICAL_AQM_BASE_ADDRESS IX_OSAL_IXP400_QMGR_PHYS_BASE
-
-#define IX_QMGR_QUELOWSTAT_BITS_PER_Q (BITS_PER_WORD/IX_QMGR_QUELOWSTAT_NUM_QUE_PER_WORD)
-
-#define IX_QMGR_QUELOWSTAT_QID_MASK 0x7
-#define IX_QMGR_Q_CONFIG_ADDR_GET(qId)\
-        (((qId) * IX_QMGR_NUM_BYTES_PER_WORD) +\
-                  IX_QMGR_QUECONFIG_BASE_OFFSET)
-
-#define IX_QMGR_ENTRY1_OFFSET 0
-#define IX_QMGR_ENTRY2_OFFSET 1
-#define IX_QMGR_ENTRY4_OFFSET 3
-
-/*
- * Variable declarations global to this file. Externs are followed by
- * statics.
- */
-UINT32 aqmBaseAddress = 0;
-/* Store addresses and bit-masks for certain queue access and status registers.
- * This is to facilitate inlining of QRead, QWrite and QStatusGet functions
- * in IxQMgr,h
- */
-extern IxQMgrQInlinedReadWriteInfo ixQMgrQInlinedReadWriteInfo[];
-UINT32 * ixQMgrAqmIfQueAccRegAddr[IX_QMGR_MAX_NUM_QUEUES];
-UINT32 ixQMgrAqmIfQueLowStatRegAddr[IX_QMGR_MIN_QUEUPP_QID];
-UINT32 ixQMgrAqmIfQueLowStatBitsOffset[IX_QMGR_MIN_QUEUPP_QID];
-UINT32 ixQMgrAqmIfQueLowStatBitsMask;
-UINT32 ixQMgrAqmIfQueUppStat0RegAddr;
-UINT32 ixQMgrAqmIfQueUppStat1RegAddr;
-UINT32 ixQMgrAqmIfQueUppStat0BitMask[IX_QMGR_MIN_QUEUPP_QID];
-UINT32 ixQMgrAqmIfQueUppStat1BitMask[IX_QMGR_MIN_QUEUPP_QID];
-
-/* 
- * Fast mutexes, one for each queue, used to protect peek & poke functions
- */
-IxOsalFastMutex ixQMgrAqmIfPeekPokeFastMutex[IX_QMGR_MAX_NUM_QUEUES];
-
-/*
- * Function prototypes
- */
-PRIVATE unsigned
-watermarkToAqmWatermark (IxQMgrWMLevel watermark );
-
-PRIVATE unsigned
-entrySizeToAqmEntrySize (IxQMgrQEntrySizeInWords entrySize);
-
-PRIVATE unsigned
-bufferSizeToAqmBufferSize (unsigned bufferSizeInWords);
-
-PRIVATE void
-ixQMgrAqmIfRegistersReset (void);
-
-PRIVATE void
-ixQMgrAqmIfEntryAddressGet (unsigned int entryIndex,
-			    UINT32 configRegWord,
-			    unsigned int qEntrySizeInwords,
-			    unsigned int qSizeInWords,
-			    UINT32 **address);
-/*
- * Function definitions
- */
-void
-ixQMgrAqmIfInit (void)
-{
-    UINT32 aqmVirtualAddr;
-    int i;
-
-    /* The value of aqmBaseAddress depends on the logical address
-     * assigned by the MMU.
-     */
-    aqmVirtualAddr =
-	(UINT32) IX_OSAL_MEM_MAP(IX_QMGR_PHYSICAL_AQM_BASE_ADDRESS,
-				    IX_OSAL_IXP400_QMGR_MAP_SIZE);
-    IX_OSAL_ASSERT (aqmVirtualAddr);
-    
-    ixQMgrAqmIfBaseAddressSet (aqmVirtualAddr);
-
-    ixQMgrAqmIfRegistersReset ();
-
-    for (i = 0; i< IX_QMGR_MAX_NUM_QUEUES; i++)
-    {
-	ixOsalFastMutexInit(&ixQMgrAqmIfPeekPokeFastMutex[i]);
-
-	/********************************************************************
-	 * Register addresses and bit masks are calculated and stored here to
-	 * facilitate inlining of QRead, QWrite and QStatusGet functions in
-	 * IxQMgr.h.
-	 * These calculations are normally performed dynamically in inlined
-	 * functions in IxQMgrAqmIf_p.h, and their semantics are reused here.
-	 */
-
-	/* AQM Queue access reg addresses, per queue */
-	ixQMgrAqmIfQueAccRegAddr[i] = 
-	    (UINT32 *)(aqmBaseAddress + IX_QMGR_Q_ACCESS_ADDR_GET(i));
-	ixQMgrQInlinedReadWriteInfo[i].qAccRegAddr = 
-	    (volatile UINT32 *)(aqmBaseAddress + IX_QMGR_Q_ACCESS_ADDR_GET(i));
-
-
-	ixQMgrQInlinedReadWriteInfo[i].qConfigRegAddr = 
-	    (volatile UINT32 *)(aqmBaseAddress + IX_QMGR_Q_CONFIG_ADDR_GET(i));
-
-	/* AQM Queue lower-group (0-31), only */
-	if (i < IX_QMGR_MIN_QUEUPP_QID)
-	{
-	    /* AQM Q underflow/overflow status register addresses, per queue */
-	    ixQMgrQInlinedReadWriteInfo[i].qUOStatRegAddr = 
-		(volatile UINT32 *)(aqmBaseAddress +
-		IX_QMGR_QUEUOSTAT0_OFFSET +
-		((i / IX_QMGR_QUEUOSTAT_NUM_QUE_PER_WORD) *
-		 IX_QMGR_NUM_BYTES_PER_WORD));
-
-	    /* AQM Q underflow status bit masks for status register per queue */
-	    ixQMgrQInlinedReadWriteInfo[i].qUflowStatBitMask = 
-		(IX_QMGR_UNDERFLOW_BIT_OFFSET + 1) <<
-		((i & (IX_QMGR_QUEUOSTAT_NUM_QUE_PER_WORD - 1)) *
-		 (BITS_PER_WORD / IX_QMGR_QUEUOSTAT_NUM_QUE_PER_WORD));
-
-	    /* AQM Q overflow status bit masks for status register, per queue */
-	    ixQMgrQInlinedReadWriteInfo[i].qOflowStatBitMask = 
-		(IX_QMGR_OVERFLOW_BIT_OFFSET + 1) <<
-		((i & (IX_QMGR_QUEUOSTAT_NUM_QUE_PER_WORD - 1)) *
-		 (BITS_PER_WORD / IX_QMGR_QUEUOSTAT_NUM_QUE_PER_WORD));
-
-	    /* AQM Q lower-group (0-31) status register addresses, per queue */
-	    ixQMgrAqmIfQueLowStatRegAddr[i] = aqmBaseAddress +
-		IX_QMGR_QUELOWSTAT0_OFFSET +
-		((i / IX_QMGR_QUELOWSTAT_NUM_QUE_PER_WORD) *
-		 IX_QMGR_NUM_BYTES_PER_WORD);
-
-	    /* AQM Q lower-group (0-31) status register bit offset */
-	    ixQMgrAqmIfQueLowStatBitsOffset[i] =
-		(i & (IX_QMGR_QUELOWSTAT_NUM_QUE_PER_WORD - 1)) * 
-		(BITS_PER_WORD / IX_QMGR_QUELOWSTAT_NUM_QUE_PER_WORD);
-	}
-	else /* AQM Q upper-group (32-63), only */
-	{
-	    /* AQM Q upper-group (32-63) Nearly Empty status reg bit masks */
-	    ixQMgrAqmIfQueUppStat0BitMask[i - IX_QMGR_MIN_QUEUPP_QID] =
-		(1 << (i - IX_QMGR_MIN_QUEUPP_QID));
-
-	    /* AQM Q upper-group (32-63) Full status register bit masks */
-	    ixQMgrAqmIfQueUppStat1BitMask[i - IX_QMGR_MIN_QUEUPP_QID] =
-		(1 << (i - IX_QMGR_MIN_QUEUPP_QID));
-	}
-    }
-
-    /* AQM Q lower-group (0-31) status register bit mask */
-    ixQMgrAqmIfQueLowStatBitsMask = (1 <<
-				    (BITS_PER_WORD /
-				     IX_QMGR_QUELOWSTAT_NUM_QUE_PER_WORD)) - 1;
-
-    /* AQM Q upper-group (32-63) Nearly Empty status register address */
-    ixQMgrAqmIfQueUppStat0RegAddr = aqmBaseAddress + IX_QMGR_QUEUPPSTAT0_OFFSET;
-    
-    /* AQM Q upper-group (32-63) Full status register address */
-    ixQMgrAqmIfQueUppStat1RegAddr = aqmBaseAddress + IX_QMGR_QUEUPPSTAT1_OFFSET;
-}
-
-/*
- * Uninitialise the AqmIf module by unmapping memory, etc
- */
-void
-ixQMgrAqmIfUninit (void)
-{
-    UINT32 virtAddr;
-
-    ixQMgrAqmIfBaseAddressGet (&virtAddr);
-    IX_OSAL_MEM_UNMAP (virtAddr);
-    ixQMgrAqmIfBaseAddressSet (0);
-}
-
-/*
- * Set the the logical base address of AQM
- */
-void
-ixQMgrAqmIfBaseAddressSet (UINT32 address)
-{
-    aqmBaseAddress = address;
-}
-
-/*
- * Get the logical base address of AQM
- */
-void
-ixQMgrAqmIfBaseAddressGet (UINT32 *address)
-{
-    *address = aqmBaseAddress;
-}
-
-/*
- * Get the logical base address of AQM SRAM
- */
-void
-ixQMgrAqmIfSramBaseAddressGet (UINT32 *address)
-{
-    *address = aqmBaseAddress                +
-	IX_QMGR_AQM_SRAM_BASE_ADDRESS_OFFSET;
-}
-
-/*
- * This function will write the status bits of a queue
- * specified by qId.
- */
-void
-ixQMgrAqmIfQRegisterBitsWrite (IxQMgrQId qId, 
-			       UINT32 registerBaseAddrOffset,
-			       unsigned queuesPerRegWord,
-			       UINT32 value)
-{
-    volatile UINT32 *registerAddress;
-    UINT32 registerWord;
-    UINT32 statusBitsMask;
-    UINT32 bitsPerQueue;
-
-    bitsPerQueue = BITS_PER_WORD / queuesPerRegWord;
-
-    /*
-     * Calculate the registerAddress
-     * multiple queues split accross registers
-     */
-    registerAddress = (UINT32*)(aqmBaseAddress +
-				registerBaseAddrOffset +
-				((qId / queuesPerRegWord) *
-				 IX_QMGR_NUM_BYTES_PER_WORD));    
-
-    /* Read the current data */
-    ixQMgrAqmIfWordRead (registerAddress, &registerWord);
-
-
-    if( (registerBaseAddrOffset == IX_QMGR_INT0SRCSELREG0_OFFSET) &&
-        (qId == IX_QMGR_QUEUE_0) )
-    {
-      statusBitsMask = 0x7 ;   
-
-      /* Queue 0 at INT0SRCSELREG should not corrupt the value bit-3  */
-      value &=  0x7 ;        
-    }
-    else
-    {     
-      /* Calculate the mask for the status bits for this queue. */
-      statusBitsMask = ((1 << bitsPerQueue) - 1);
-      statusBitsMask <<= ((qId & (queuesPerRegWord - 1)) * bitsPerQueue);
-
-      /* Mask out bits in value that would overwrite other q data */
-      value <<= ((qId & (queuesPerRegWord - 1)) * bitsPerQueue);
-      value &= statusBitsMask;
-    }
-
-    /* Mask out bits to write to */
-    registerWord &= ~statusBitsMask;
-    
-
-    /* Set the write bits */
-    registerWord |= value;
-
-    /*
-     * Write the data
-     */
-    ixQMgrAqmIfWordWrite (registerAddress, registerWord);
-}
-
-/*
- * This function generates the parameters that can be used to
- * check if a Qs status matches the specified source select.
- * It calculates which status word to check (statusWordOffset),
- * the value to check the status against (checkValue) and the
- * mask (mask) to mask out all but the bits to check in the status word.
- */
-void
-ixQMgrAqmIfQStatusCheckValsCalc (IxQMgrQId qId,
-				 IxQMgrSourceId srcSel,
-				 unsigned int *statusWordOffset,
-				 UINT32 *checkValue,
-				 UINT32 *mask)
-{
-    UINT32 shiftVal;
-   
-    if (qId < IX_QMGR_MIN_QUEUPP_QID)
-    {
-	switch (srcSel)
-	{
-	    case IX_QMGR_Q_SOURCE_ID_E:
-		*checkValue = IX_QMGR_Q_STATUS_E_BIT_MASK;
-		*mask = IX_QMGR_Q_STATUS_E_BIT_MASK;
-		break;
-	    case IX_QMGR_Q_SOURCE_ID_NE:
-		*checkValue = IX_QMGR_Q_STATUS_NE_BIT_MASK;
-		*mask = IX_QMGR_Q_STATUS_NE_BIT_MASK;
-		break;
-	    case IX_QMGR_Q_SOURCE_ID_NF:
-		*checkValue = IX_QMGR_Q_STATUS_NF_BIT_MASK;
-		*mask = IX_QMGR_Q_STATUS_NF_BIT_MASK;
-		break;
-	    case IX_QMGR_Q_SOURCE_ID_F:
-		*checkValue = IX_QMGR_Q_STATUS_F_BIT_MASK;
-		*mask = IX_QMGR_Q_STATUS_F_BIT_MASK;
-		break;
-	    case IX_QMGR_Q_SOURCE_ID_NOT_E:
-		*checkValue = 0;
-		*mask = IX_QMGR_Q_STATUS_E_BIT_MASK;
-		break;
-	    case IX_QMGR_Q_SOURCE_ID_NOT_NE:
-		*checkValue = 0;
-		*mask = IX_QMGR_Q_STATUS_NE_BIT_MASK;
-		break;
-	    case IX_QMGR_Q_SOURCE_ID_NOT_NF:
-		*checkValue = 0;
-		*mask = IX_QMGR_Q_STATUS_NF_BIT_MASK;
-		break;
-	    case IX_QMGR_Q_SOURCE_ID_NOT_F:
-		*checkValue = 0;
-		*mask = IX_QMGR_Q_STATUS_F_BIT_MASK;
-		break;
-	    default:
-		/* Should never hit */
-		IX_OSAL_ASSERT(0);
-		break;
-	}
-
-	/* One nibble of status per queue so need to shift the
-	 * check value and mask out to the correct position.
-	 */
-	shiftVal = (qId % IX_QMGR_QUELOWSTAT_NUM_QUE_PER_WORD) * 
-	    IX_QMGR_QUELOWSTAT_BITS_PER_Q;
-
-	/* Calculate the which status word to check from the qId,
-	 * 8 Qs status per word
-	 */
-	*statusWordOffset = qId / IX_QMGR_QUELOWSTAT_NUM_QUE_PER_WORD;
-
-	*checkValue <<= shiftVal;
-	*mask <<= shiftVal;
-    }
-    else
-    {
-	/* One status word */
-	*statusWordOffset = 0;
-	/* Single bits per queue and int source bit hardwired  NE,
-	 * Qs start at 32.
-	 */
-	*mask = 1 << (qId - IX_QMGR_MIN_QUEUPP_QID);
-	*checkValue = *mask;
-    }
-}
-
-void
-ixQMgrAqmIfQInterruptEnable (IxQMgrQId qId)
-{
-    volatile UINT32 *registerAddress;
-    UINT32 registerWord;
-    UINT32 actualBitOffset;
-    
-    if (qId < IX_QMGR_MIN_QUEUPP_QID)
-    {    
-	registerAddress = (UINT32*)(aqmBaseAddress + IX_QMGR_QUEIEREG0_OFFSET);
-    }
-    else
-    {
-	registerAddress = (UINT32*)(aqmBaseAddress + IX_QMGR_QUEIEREG1_OFFSET);
-    }
-
-    actualBitOffset = 1 << (qId % IX_QMGR_MIN_QUEUPP_QID);
-
-    ixQMgrAqmIfWordRead (registerAddress, &registerWord);
-    ixQMgrAqmIfWordWrite (registerAddress, (registerWord | actualBitOffset));
-}
-
-void
-ixQMgrAqmIfQInterruptDisable (IxQMgrQId qId)
-{
-    volatile UINT32 *registerAddress;
-    UINT32 registerWord;
-    UINT32 actualBitOffset;
-
-    if (qId < IX_QMGR_MIN_QUEUPP_QID)
-    {    
-	registerAddress = (UINT32*)(aqmBaseAddress + IX_QMGR_QUEIEREG0_OFFSET);
-    }
-    else
-    {
-	registerAddress = (UINT32*)(aqmBaseAddress + IX_QMGR_QUEIEREG1_OFFSET);
-    }
-
-    actualBitOffset = 1 << (qId % IX_QMGR_MIN_QUEUPP_QID);
-
-    ixQMgrAqmIfWordRead (registerAddress, &registerWord);
-    ixQMgrAqmIfWordWrite (registerAddress, registerWord & (~actualBitOffset));
-}
-
-void
-ixQMgrAqmIfQueCfgWrite (IxQMgrQId qId,
-		       IxQMgrQSizeInWords qSizeInWords,
-		       IxQMgrQEntrySizeInWords entrySizeInWords,
-		       UINT32 freeSRAMAddress)
-{
-    volatile UINT32 *cfgAddress = NULL;
-    UINT32 qCfg = 0;
-    UINT32 baseAddress = 0;
-    unsigned aqmEntrySize = 0;
-    unsigned aqmBufferSize = 0;
-
-    /* Build config register */
-    aqmEntrySize = entrySizeToAqmEntrySize (entrySizeInWords);
-    qCfg |= (aqmEntrySize&IX_QMGR_ENTRY_SIZE_MASK) <<
-	IX_QMGR_Q_CONFIG_ESIZE_OFFSET;
-
-    aqmBufferSize = bufferSizeToAqmBufferSize (qSizeInWords);
-    qCfg |= (aqmBufferSize&IX_QMGR_SIZE_MASK) << IX_QMGR_Q_CONFIG_BSIZE_OFFSET;
-
-    /* baseAddress, calculated relative to aqmBaseAddress and start address  */
-    baseAddress = freeSRAMAddress -
-	(aqmBaseAddress + IX_QMGR_QUECONFIG_BASE_OFFSET);
-		   
-    /* Verify base address aligned to a 16 word boundary */
-    if ((baseAddress % IX_QMGR_BASE_ADDR_16_WORD_ALIGN) != 0)
-    {
-	IX_QMGR_LOG_ERROR0("ixQMgrAqmIfQueCfgWrite () address is not on 16 word boundary\n");
-    }
-    /* Now convert it to a 16 word pointer as required by QUECONFIG register */
-    baseAddress >>= IX_QMGR_BASE_ADDR_16_WORD_SHIFT;
-    
-    
-    qCfg |= (baseAddress << IX_QMGR_Q_CONFIG_BADDR_OFFSET);
-
-
-    cfgAddress = (UINT32*)(aqmBaseAddress +
-			IX_QMGR_Q_CONFIG_ADDR_GET(qId));
-
-
-    /* NOTE: High and Low watermarks are set to zero */
-    ixQMgrAqmIfWordWrite (cfgAddress, qCfg);
-}
-
-void
-ixQMgrAqmIfQueCfgRead (IxQMgrQId qId,
-		       unsigned int numEntries,
-		       UINT32 *baseAddress,
-		       unsigned int *ne,
-		       unsigned int *nf,
-		       UINT32 *readPtr,
-		       UINT32 *writePtr)
-{
-    UINT32 qcfg;
-    UINT32 *cfgAddress = (UINT32*)(aqmBaseAddress + IX_QMGR_Q_CONFIG_ADDR_GET(qId));
-    unsigned int qEntrySizeInwords;
-    unsigned int qSizeInWords;
-    UINT32 *readPtr_ = NULL;
-	
-    /* Read the queue configuration register */
-    ixQMgrAqmIfWordRead (cfgAddress, &qcfg);
-    
-    /* Extract the base address */
-    *baseAddress = (UINT32)((qcfg & IX_QMGR_BADDR_MASK) >>
-			    (IX_QMGR_Q_CONFIG_BADDR_OFFSET));
-
-    /* Base address is a 16 word pointer from the start of AQM SRAM.
-     * Convert to absolute word address.
-     */
-    *baseAddress <<= IX_QMGR_BASE_ADDR_16_WORD_SHIFT;
-    *baseAddress += (UINT32)IX_QMGR_QUECONFIG_BASE_OFFSET;
-
-    /*
-     * Extract the watermarks. 0->0 entries, 1->1 entries, 2->2 entries, 3->4 entries......
-     * If ne > 0 ==> neInEntries = 2^(ne - 1)
-     * If ne == 0 ==> neInEntries = 0
-     * The same applies.
-     */
-    *ne = ((qcfg) >> (IX_QMGR_Q_CONFIG_NE_OFFSET)) & IX_QMGR_NE_MASK;
-    *nf = ((qcfg) >> (IX_QMGR_Q_CONFIG_NF_OFFSET)) & IX_QMGR_NF_MASK;
-
-    if (0 != *ne)
-    {
-	*ne = 1 << (*ne - 1);	
-    }
-    if (0 != *nf)
-    {
-	*nf = 1 << (*nf - 1);
-    }
-
-    /* Get the queue entry size in words */
-    qEntrySizeInwords = ixQMgrQEntrySizeInWordsGet (qId);
-
-    /* Get the queue size in words */
-    qSizeInWords = ixQMgrQSizeInWordsGet (qId);
-
-    ixQMgrAqmIfEntryAddressGet (0/* Entry 0. i.e the readPtr*/,
-				qcfg,
-				qEntrySizeInwords,
-				qSizeInWords,
-				&readPtr_);
-    *readPtr = (UINT32)readPtr_;
-    *readPtr -= (UINT32)aqmBaseAddress;/* Offset, not absolute address */
-
-    *writePtr = (qcfg >> IX_QMGR_Q_CONFIG_WRPTR_OFFSET) & IX_QMGR_WRPTR_MASK;
-    *writePtr = *baseAddress + (*writePtr * (IX_QMGR_NUM_BYTES_PER_WORD));
-    return;
-}
-
-unsigned
-ixQMgrAqmIfLog2 (unsigned number)
-{
-    unsigned count = 0;
-
-    /*
-     * N.B. this function will return 0
-     * for ixQMgrAqmIfLog2 (0)
-     */
-    while (number/2)
-    {
-	number /=2;
-	count++;	
-    }
-
-    return count;
-}
-
-void ixQMgrAqmIfIntSrcSelReg0Bit3Set (void)
-{
-
-    volatile UINT32 *registerAddress;
-    UINT32 registerWord; 
-
-    /*
-     * Calculate the registerAddress
-     * multiple queues split accross registers
-     */
-    registerAddress = (UINT32*)(aqmBaseAddress +
-				IX_QMGR_INT0SRCSELREG0_OFFSET);    
-
-    /* Read the current data */
-    ixQMgrAqmIfWordRead (registerAddress, &registerWord);
-
-    /* Set the write bits */
-    registerWord |= (1<<IX_QMGR_INT0SRCSELREG0_BIT3) ;
-
-    /*
-     * Write the data
-     */
-    ixQMgrAqmIfWordWrite (registerAddress, registerWord);
-}  
-
-
-void
-ixQMgrAqmIfIntSrcSelWrite (IxQMgrQId qId,
-			  IxQMgrSourceId sourceId)
-{
-    ixQMgrAqmIfQRegisterBitsWrite (qId,
-				   IX_QMGR_INT0SRCSELREG0_OFFSET,
-				   IX_QMGR_INTSRC_NUM_QUE_PER_WORD,
-				   sourceId);
-}
-
-
-
-void
-ixQMgrAqmIfWatermarkSet (IxQMgrQId qId,
-			unsigned ne,
-			unsigned nf)
-{
-    volatile UINT32 *address = 0;
-    UINT32 value = 0;
-    unsigned aqmNeWatermark = 0;
-    unsigned aqmNfWatermark = 0;
-
-    address = (UINT32*)(aqmBaseAddress +
-		     IX_QMGR_Q_CONFIG_ADDR_GET(qId));
-
-    aqmNeWatermark = watermarkToAqmWatermark (ne);
-    aqmNfWatermark = watermarkToAqmWatermark (nf);
-
-    /* Read the current watermarks */
-    ixQMgrAqmIfWordRead (address, &value);
-
-    /* Clear out the old watermarks */
-    value &=  IX_QMGR_NE_NF_CLEAR_MASK;
-    
-    /* Generate the value to write */
-    value |= (aqmNeWatermark << IX_QMGR_Q_CONFIG_NE_OFFSET) |
-	(aqmNfWatermark << IX_QMGR_Q_CONFIG_NF_OFFSET); 
-
-    ixQMgrAqmIfWordWrite (address, value);
-
-}
-
-PRIVATE void
-ixQMgrAqmIfEntryAddressGet (unsigned int entryIndex,
-			    UINT32 configRegWord,
-			    unsigned int qEntrySizeInwords,
-			    unsigned int qSizeInWords,
-			    UINT32 **address)
-{
-    UINT32 readPtr;
-    UINT32 baseAddress;
-    UINT32 *topOfAqmSram;
-
-    topOfAqmSram = ((UINT32 *)aqmBaseAddress + IX_QMGR_AQM_ADDRESS_SPACE_SIZE_IN_WORDS);
-
-    /* Extract the base address */
-    baseAddress = (UINT32)((configRegWord & IX_QMGR_BADDR_MASK) >>
-			   (IX_QMGR_Q_CONFIG_BADDR_OFFSET));
-
-    /* Base address is a 16 word pointer from the start of AQM SRAM.
-     * Convert to absolute word address.
-     */
-    baseAddress <<= IX_QMGR_BASE_ADDR_16_WORD_SHIFT;
-    baseAddress += ((UINT32)aqmBaseAddress + (UINT32)IX_QMGR_QUECONFIG_BASE_OFFSET);
-
-    /* Extract the read pointer. Read pointer is a word pointer */
-    readPtr = (UINT32)((configRegWord >>
-			IX_QMGR_Q_CONFIG_RDPTR_OFFSET)&IX_QMGR_RDPTR_MASK);
-
-    /* Read/Write pointers(word pointers)  are offsets from the queue buffer space base address.
-     * Calculate the absolute read pointer address. NOTE: Queues are circular buffers.
-     */
-    readPtr  = (readPtr + (entryIndex * qEntrySizeInwords)) & (qSizeInWords - 1); /* Mask by queue size */
-    *address = (UINT32 *)(baseAddress + (readPtr * (IX_QMGR_NUM_BYTES_PER_WORD)));
-
-    switch (qEntrySizeInwords)
-    {
-	case IX_QMGR_Q_ENTRY_SIZE1:
-	    IX_OSAL_ASSERT((*address + IX_QMGR_ENTRY1_OFFSET) < topOfAqmSram);	    
-	    break;
-	case IX_QMGR_Q_ENTRY_SIZE2:
-	    IX_OSAL_ASSERT((*address + IX_QMGR_ENTRY2_OFFSET) < topOfAqmSram);
-	    break;
-	case IX_QMGR_Q_ENTRY_SIZE4:
-	    IX_OSAL_ASSERT((*address + IX_QMGR_ENTRY4_OFFSET) < topOfAqmSram);
-	    break;
-	default:
-	    IX_QMGR_LOG_ERROR0("Invalid Q Entry size passed to ixQMgrAqmIfEntryAddressGet");
-	    break;
-    }
-    
-}
-
-IX_STATUS
-ixQMgrAqmIfQPeek (IxQMgrQId qId,
-		  unsigned int entryIndex,
-		  unsigned int *entry)
-{
-    UINT32 *cfgRegAddress = (UINT32*)(aqmBaseAddress + IX_QMGR_Q_CONFIG_ADDR_GET(qId));
-    UINT32 *entryAddress = NULL;
-    UINT32 configRegWordOnEntry;
-    UINT32 configRegWordOnExit;
-    unsigned int qEntrySizeInwords;
-    unsigned int qSizeInWords;
-
-    /* Get the queue entry size in words */
-    qEntrySizeInwords = ixQMgrQEntrySizeInWordsGet (qId);
-
-    /* Get the queue size in words */
-    qSizeInWords = ixQMgrQSizeInWordsGet (qId);
-
-    /* Read the config register */
-    ixQMgrAqmIfWordRead (cfgRegAddress, &configRegWordOnEntry);
-
-    /* Get the entry address */
-    ixQMgrAqmIfEntryAddressGet (entryIndex,
-				configRegWordOnEntry,
-				qEntrySizeInwords,
-				qSizeInWords,
-				&entryAddress);
-
-    /* Get the lock or return busy */
-    if (IX_SUCCESS != ixOsalFastMutexTryLock(&ixQMgrAqmIfPeekPokeFastMutex[qId]))
-    {
-	return IX_FAIL;
-    }
-
-    while(qEntrySizeInwords--)
-    {
-	ixQMgrAqmIfWordRead (entryAddress++, entry++);
-    }
-
-    /* Release the lock */
-    ixOsalFastMutexUnlock(&ixQMgrAqmIfPeekPokeFastMutex[qId]);
-
-    /* Read the config register */
-    ixQMgrAqmIfWordRead (cfgRegAddress, &configRegWordOnExit);
-
-    /* Check that the read and write pointers have not changed */
-    if (configRegWordOnEntry != configRegWordOnExit)
-    {
-	return IX_FAIL;
-    }
-
-    return IX_SUCCESS;
-}
-
-IX_STATUS
-ixQMgrAqmIfQPoke (IxQMgrQId qId,
-		  unsigned entryIndex,
-		  unsigned int *entry)
-{
-    UINT32 *cfgRegAddress = (UINT32*)(aqmBaseAddress + IX_QMGR_Q_CONFIG_ADDR_GET(qId));
-    UINT32 *entryAddress = NULL;
-    UINT32 configRegWordOnEntry;
-    UINT32 configRegWordOnExit;
-    unsigned int qEntrySizeInwords;
-    unsigned int qSizeInWords;
-    
-    /* Get the queue entry size in words */
-    qEntrySizeInwords = ixQMgrQEntrySizeInWordsGet (qId);
-
-    /* Get the queue size in words */
-    qSizeInWords = ixQMgrQSizeInWordsGet (qId);
-
-    /* Read the config register */
-    ixQMgrAqmIfWordRead (cfgRegAddress, &configRegWordOnEntry);
-
-    /* Get the entry address */
-    ixQMgrAqmIfEntryAddressGet (entryIndex,
-				configRegWordOnEntry,
-				qEntrySizeInwords,
-				qSizeInWords,
-				&entryAddress);
-
-    /* Get the lock or return busy */
-    if (IX_SUCCESS != ixOsalFastMutexTryLock(&ixQMgrAqmIfPeekPokeFastMutex[qId]))
-    {
-	return IX_FAIL;
-    }
-
-    /* Else read the entry directly from SRAM. This will not move the read pointer */
-    while(qEntrySizeInwords--)
-    {
-	ixQMgrAqmIfWordWrite (entryAddress++, *entry++);
-    }
-
-    /* Release the lock */
-    ixOsalFastMutexUnlock(&ixQMgrAqmIfPeekPokeFastMutex[qId]);
-
-    /* Read the config register */
-    ixQMgrAqmIfWordRead (cfgRegAddress, &configRegWordOnExit);
-
-    /* Check that the read and write pointers have not changed */
-    if (configRegWordOnEntry != configRegWordOnExit)
-    {
-	return IX_FAIL;
-    }
-
-    return IX_SUCCESS;
-}
-
-PRIVATE unsigned
-watermarkToAqmWatermark (IxQMgrWMLevel watermark )
-{
-    unsigned aqmWatermark = 0;
-
-    /*
-     * Watermarks 0("000"),1("001"),2("010"),4("011"),
-     * 8("100"),16("101"),32("110"),64("111")
-     */
-    aqmWatermark = ixQMgrAqmIfLog2 (watermark * 2);
-    
-    return aqmWatermark;
-}
-
-PRIVATE unsigned
-entrySizeToAqmEntrySize (IxQMgrQEntrySizeInWords entrySize)
-{
-    /* entrySize  1("00"),2("01"),4("10") */
-    return (ixQMgrAqmIfLog2 (entrySize));
-}
-
-PRIVATE unsigned
-bufferSizeToAqmBufferSize (unsigned bufferSizeInWords)
-{
-    /* bufferSize 16("00"),32("01),64("10"),128("11") */
-    return (ixQMgrAqmIfLog2 (bufferSizeInWords / IX_QMGR_MIN_BUFFER_SIZE));
-}
-
-/*
- * Reset AQM registers to default values.
- */
-PRIVATE void
-ixQMgrAqmIfRegistersReset (void)
-{
-    volatile UINT32 *qConfigWordAddress = NULL;
-    unsigned int i;
-
-    /*
-     * Need to initialize AQM hardware registers to an initial
-     * value as init may have been called as a result of a soft
-     * reset. i.e. soft reset does not reset hardware registers.
-     */
-
-    /* Reset queues 0..31 status registers 0..3 */
-    ixQMgrAqmIfWordWrite((UINT32 *)(aqmBaseAddress + IX_QMGR_QUELOWSTAT0_OFFSET), 
-			 IX_QMGR_QUELOWSTAT_RESET_VALUE);
-    ixQMgrAqmIfWordWrite((UINT32 *)(aqmBaseAddress + IX_QMGR_QUELOWSTAT1_OFFSET), 
-			 IX_QMGR_QUELOWSTAT_RESET_VALUE);
-    ixQMgrAqmIfWordWrite((UINT32 *)(aqmBaseAddress + IX_QMGR_QUELOWSTAT2_OFFSET), 
-			 IX_QMGR_QUELOWSTAT_RESET_VALUE);
-    ixQMgrAqmIfWordWrite((UINT32 *)(aqmBaseAddress + IX_QMGR_QUELOWSTAT3_OFFSET), 
-			 IX_QMGR_QUELOWSTAT_RESET_VALUE);
-
-    /* Reset underflow/overflow status registers 0..1 */
-    ixQMgrAqmIfWordWrite((UINT32 *)(aqmBaseAddress + IX_QMGR_QUEUOSTAT0_OFFSET), 
-			 IX_QMGR_QUEUOSTAT_RESET_VALUE);
-    ixQMgrAqmIfWordWrite((UINT32 *)(aqmBaseAddress + IX_QMGR_QUEUOSTAT1_OFFSET), 
-			 IX_QMGR_QUEUOSTAT_RESET_VALUE);
-    
-    /* Reset queues 32..63 nearly empty status registers */
-    ixQMgrAqmIfWordWrite((UINT32 *)(aqmBaseAddress + IX_QMGR_QUEUPPSTAT0_OFFSET),
-			 IX_QMGR_QUEUPPSTAT0_RESET_VALUE);
-
-    /* Reset queues 32..63 full status registers */
-    ixQMgrAqmIfWordWrite((UINT32 *)(aqmBaseAddress + IX_QMGR_QUEUPPSTAT1_OFFSET),
-			 IX_QMGR_QUEUPPSTAT1_RESET_VALUE);
-
-    /* Reset int0 status flag source select registers 0..3 */
-    ixQMgrAqmIfWordWrite((UINT32 *)(aqmBaseAddress + IX_QMGR_INT0SRCSELREG0_OFFSET),
-			 IX_QMGR_INT0SRCSELREG_RESET_VALUE);
-    ixQMgrAqmIfWordWrite((UINT32 *)(aqmBaseAddress + IX_QMGR_INT0SRCSELREG1_OFFSET),
-			 IX_QMGR_INT0SRCSELREG_RESET_VALUE);
-    ixQMgrAqmIfWordWrite((UINT32 *)(aqmBaseAddress + IX_QMGR_INT0SRCSELREG2_OFFSET),
-			 IX_QMGR_INT0SRCSELREG_RESET_VALUE);
-    ixQMgrAqmIfWordWrite((UINT32 *)(aqmBaseAddress + IX_QMGR_INT0SRCSELREG3_OFFSET),
-			 IX_QMGR_INT0SRCSELREG_RESET_VALUE);
-	 
-    /* Reset queue interrupt enable register 0..1 */
-    ixQMgrAqmIfWordWrite((UINT32 *)(aqmBaseAddress + IX_QMGR_QUEIEREG0_OFFSET),
-			 IX_QMGR_QUEIEREG_RESET_VALUE);
-    ixQMgrAqmIfWordWrite((UINT32 *)(aqmBaseAddress + IX_QMGR_QUEIEREG1_OFFSET),
-			 IX_QMGR_QUEIEREG_RESET_VALUE);
-
-    /* Reset queue interrupt register 0..1 */
-    ixQMgrAqmIfWordWrite((UINT32 *)(aqmBaseAddress + IX_QMGR_QINTREG0_OFFSET),
-			 IX_QMGR_QINTREG_RESET_VALUE);
-    ixQMgrAqmIfWordWrite((UINT32 *)(aqmBaseAddress + IX_QMGR_QINTREG1_OFFSET),
-			 IX_QMGR_QINTREG_RESET_VALUE);
-
-    /* Reset queue configuration words 0..63 */
-    qConfigWordAddress = (UINT32 *)(aqmBaseAddress + IX_QMGR_QUECONFIG_BASE_OFFSET);
-    for (i = 0; i < (IX_QMGR_QUECONFIG_SIZE / sizeof(UINT32)); i++)
-    {
-	ixQMgrAqmIfWordWrite(qConfigWordAddress,
-			     IX_QMGR_QUECONFIG_RESET_VALUE);
-	/* Next word */
-	qConfigWordAddress++;
-    }
-}
-
diff --git a/arch/arm/cpu/ixp/npe/IxQMgrDispatcher.c b/arch/arm/cpu/ixp/npe/IxQMgrDispatcher.c
deleted file mode 100644
index 09f69ce..0000000
--- a/arch/arm/cpu/ixp/npe/IxQMgrDispatcher.c
+++ /dev/null
@@ -1,1347 +0,0 @@
-/**
- * @file    IxQMgrDispatcher.c
- *
- * @author Intel Corporation
- * @date    20-Dec-2001
- *    
- * @brief   This file contains the implementation of the Dispatcher sub component
- *
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- * 
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- * 
- * @par
- * -- End of Copyright Notice --
-*/
-
-/*
- * User defined include files.
- */
-#include "IxQMgr.h"
-#include "IxQMgrAqmIf_p.h"
-#include "IxQMgrQCfg_p.h"
-#include "IxQMgrDispatcher_p.h"
-#include "IxQMgrLog_p.h"
-#include "IxQMgrDefines_p.h"
-#include "IxFeatureCtrl.h"
-#include "IxOsal.h"
-
-
-
-/*
- * #defines and macros used in this file.
- */
-
-
-/*
- * This constant is used to indicate the number of priority levels supported
- */
-#define IX_QMGR_NUM_PRIORITY_LEVELS 3
-
-/* 
- * This constant is used to set the size of the array of status words
- */
-#define MAX_Q_STATUS_WORDS      4
-
-/*
- * This macro is used to check if a given priority is valid
- */
-#define IX_QMGR_DISPATCHER_PRIORITY_CHECK(priority) \
-(((priority) >= IX_QMGR_Q_PRIORITY_0) && ((priority) <= IX_QMGR_Q_PRIORITY_2))
-
-/*
- * This macto is used to check that a given interrupt source is valid
- */
-#define IX_QMGR_DISPATCHER_SOURCE_ID_CHECK(srcSel) \
-(((srcSel) >= IX_QMGR_Q_SOURCE_ID_E) && ((srcSel) <= IX_QMGR_Q_SOURCE_ID_NOT_F))
-
-/*
- * Number of times a dummy callback is called before logging a trace
- * message
- */
-#define LOG_THROTTLE_COUNT 1000000
-
-/* Priority tables limits */
-#define IX_QMGR_MIN_LOW_QUE_PRIORITY_TABLE_INDEX (0)
-#define IX_QMGR_MID_LOW_QUE_PRIORITY_TABLE_INDEX (16)
-#define IX_QMGR_MAX_LOW_QUE_PRIORITY_TABLE_INDEX (31)
-#define IX_QMGR_MIN_UPP_QUE_PRIORITY_TABLE_INDEX (32)
-#define IX_QMGR_MID_UPP_QUE_PRIORITY_TABLE_INDEX (48)
-#define IX_QMGR_MAX_UPP_QUE_PRIORITY_TABLE_INDEX (63)
- 
-/*
- * This macro is used to check if a given callback type is valid
- */
-#define IX_QMGR_DISPATCHER_CALLBACK_TYPE_CHECK(type) \
-            (((type) >= IX_QMGR_TYPE_REALTIME_OTHER) && \
-            ((type) <= IX_QMGR_TYPE_REALTIME_SPORADIC))
-
-/* 
- * define max index in lower queue to use in loops 
- */
-#define IX_QMGR_MAX_LOW_QUE_TABLE_INDEX (31)
-
-/*
- * Typedefs whose scope is limited to this file.
- */
-
-/*
- * Information on a queue needed by the Dispatcher
- */
-typedef struct 
-{
-    IxQMgrCallback callback;       /* Notification callback                  */
-    IxQMgrCallbackId callbackId;   /* Notification callback identifier       */
-    unsigned dummyCallbackCount;   /* Number of times runs of dummy callback */
-    IxQMgrPriority priority;       /* Dispatch priority                      */
-    unsigned int statusWordOffset; /* Offset to the status word to check     */
-    UINT32 statusMask;             /* Status mask                            */    
-    UINT32 statusCheckValue;       /* Status check value                     */
-    UINT32 intRegCheckMask;	   /* Interrupt register check mask          */
-} IxQMgrQInfo;
-
-/*
- * Variable declarations global to this file. Externs are followed by
- * statics.
- */
-
-/* 
- * Flag to keep record of what dispatcher set in featureCtrl when ixQMgrInit()
- * is called. This is needed because it is possible that a client might
- * change whether the live lock prevention dispatcher is used between
- * calls to ixQMgrInit() and ixQMgrDispatcherLoopGet(). 
- */
-PRIVATE IX_STATUS ixQMgrOrigB0Dispatcher = IX_FEATURE_CTRL_COMPONENT_ENABLED;
-
-/* 
- * keep record of Q types - not in IxQMgrQInfo for performance as
- * it is only used with ixQMgrDispatcherLoopRunB0LLP()
- */
-PRIVATE IxQMgrType ixQMgrQTypes[IX_QMGR_MAX_NUM_QUEUES];
-
-/*
- * This array contains a list of queue identifiers ordered by priority. The table
- * is split logically between queue identifiers 0-31 and 32-63.
- */
-static IxQMgrQId priorityTable[IX_QMGR_MAX_NUM_QUEUES];
-
-/*
- * This flag indicates to the dispatcher that the priority table needs to be rebuilt.
- */
-static BOOL rebuildTable = FALSE;
-
-/* Dispatcher statistics */
-static IxQMgrDispatcherStats dispatcherStats;
-
-/* Table of queue information */
-static IxQMgrQInfo dispatchQInfo[IX_QMGR_MAX_NUM_QUEUES];
-
-/* Masks use to identify the first queues in the priority tables 
-*  when comparing with the interrupt register
-*/
-static unsigned int lowPriorityTableFirstHalfMask;
-static unsigned int uppPriorityTableFirstHalfMask;
-
-/*
- * Static function prototypes
- */
-
-/*
- * This function is the default callback for all queues
- */
-PRIVATE void
-dummyCallback (IxQMgrQId qId,	      
-	       IxQMgrCallbackId cbId);
-
-PRIVATE void
-ixQMgrDispatcherReBuildPriorityTable (void);
-
-/*
- * Function definitions.
- */
-void
-ixQMgrDispatcherInit (void)
-{
-    int i;
-    IxFeatureCtrlProductId productId = 0;
-    IxFeatureCtrlDeviceId deviceId = 0;
-    BOOL stickyIntSilicon = TRUE; 
-
-    /* Set default priorities */
-    for (i=0; i< IX_QMGR_MAX_NUM_QUEUES; i++)
-    {
-	dispatchQInfo[i].callback = dummyCallback;
-	dispatchQInfo[i].callbackId = 0;
-	dispatchQInfo[i].dummyCallbackCount = 0;
-	dispatchQInfo[i].priority = IX_QMGR_Q_PRIORITY_2;
-	dispatchQInfo[i].statusWordOffset = 0;
-	dispatchQInfo[i].statusCheckValue = 0;
-	dispatchQInfo[i].statusMask = 0;  
-        /* 
-	 * There are two interrupt registers, 32 bits each. One for the lower
-	 * queues(0-31) and one for the upper queues(32-63). Therefore need to
-	 * mod by 32 i.e the min upper queue identifier.
-	 */
-	dispatchQInfo[i].intRegCheckMask = (1<<(i%(IX_QMGR_MIN_QUEUPP_QID)));
-
-        /* 
-         * Set the Q types - will only be used with livelock 
-         */
-        ixQMgrQTypes[i] = IX_QMGR_TYPE_REALTIME_OTHER;
-
-	/* Reset queue statistics */
-	dispatcherStats.queueStats[i].callbackCnt = 0;
-	dispatcherStats.queueStats[i].priorityChangeCnt = 0;
-	dispatcherStats.queueStats[i].intNoCallbackCnt = 0;
-	dispatcherStats.queueStats[i].intLostCallbackCnt = 0;
-        dispatcherStats.queueStats[i].notificationEnabled = FALSE;
-        dispatcherStats.queueStats[i].srcSel = 0;
-
-    }
-
-    /* Priority table. Order the table from queue 0 to 63 */
-    ixQMgrDispatcherReBuildPriorityTable();
-
-    /* Reset statistics */
-    dispatcherStats.loopRunCnt = 0;
-
-    /* Get the device ID for the underlying silicon */
-    deviceId = ixFeatureCtrlDeviceRead();
-    
-    /* Get the product ID for the underlying silicon */
-    productId = ixFeatureCtrlProductIdRead();
-
-    /* 
-     * Check featureCtrl to see if Livelock prevention is required 
-     */
-    ixQMgrOrigB0Dispatcher = ixFeatureCtrlSwConfigurationCheck( 
-                                 IX_FEATURECTRL_ORIGB0_DISPATCHER);
-
-    /*
-     * Check if the silicon supports the sticky interrupt feature.
-     * IF (IXP42X AND A0) -> No sticky interrupt feature supported 
-     */
-    if ((IX_FEATURE_CTRL_DEVICE_TYPE_IXP42X == 
-        (IX_FEATURE_CTRL_DEVICE_TYPE_MASK & deviceId)) &&
-        (IX_FEATURE_CTRL_SILICON_TYPE_A0 == 
-        (IX_FEATURE_CTRL_SILICON_STEPPING_MASK & productId))) 
-    {
-       stickyIntSilicon = FALSE;
-    }
-
-    /*
-     * IF user wants livelock prev option AND silicon supports sticky interrupt 
-     * feature -> enable the sticky interrupt bit
-     */
-    if ((IX_FEATURE_CTRL_SWCONFIG_DISABLED == ixQMgrOrigB0Dispatcher) &&
-         stickyIntSilicon)  
-    {
-        ixQMgrStickyInterruptRegEnable();
-    }
-}
-
-IX_STATUS
-ixQMgrDispatcherPrioritySet (IxQMgrQId qId,
-			     IxQMgrPriority priority)
-{   
-    int ixQMgrLockKey;
-
-    if (!ixQMgrQIsConfigured(qId))
-    {
-	return IX_QMGR_Q_NOT_CONFIGURED;
-    }
-    
-    if (!IX_QMGR_DISPATCHER_PRIORITY_CHECK(priority))
-    {
-	return IX_QMGR_Q_INVALID_PRIORITY;
-    }
-
-    ixQMgrLockKey = ixOsalIrqLock();
-    
-    /* Change priority */
-    dispatchQInfo[qId].priority = priority;
-    /* Set flag */
-    rebuildTable = TRUE;
-
-    ixOsalIrqUnlock(ixQMgrLockKey);
-
-#ifndef NDEBUG
-    /* Update statistics */
-    dispatcherStats.queueStats[qId].priorityChangeCnt++;
-#endif
-
-    return IX_SUCCESS;
-}
-
-IX_STATUS
-ixQMgrNotificationCallbackSet (IxQMgrQId qId,
-			       IxQMgrCallback callback,
-			       IxQMgrCallbackId callbackId)
-{
-    if (!ixQMgrQIsConfigured(qId))
-    {
-	return IX_QMGR_Q_NOT_CONFIGURED;
-    }
-
-    if (NULL == callback)
-    {
-	/* Reset to dummy callback */
-	dispatchQInfo[qId].callback = dummyCallback;
-	dispatchQInfo[qId].dummyCallbackCount = 0;
-	dispatchQInfo[qId].callbackId = 0;
-    }
-    else 
-    {
-	dispatchQInfo[qId].callback = callback;
-	dispatchQInfo[qId].callbackId = callbackId;
-    }
-
-    return IX_SUCCESS;
-}
-
-IX_STATUS
-ixQMgrNotificationEnable (IxQMgrQId qId, 
-			  IxQMgrSourceId srcSel)
-{
-    IxQMgrQStatus qStatusOnEntry;/* The queue status on entry/exit */
-    IxQMgrQStatus qStatusOnExit; /* to this function               */
-    int ixQMgrLockKey;
-
-#ifndef NDEBUG
-    if (!ixQMgrQIsConfigured (qId))
-    {
-	return IX_QMGR_Q_NOT_CONFIGURED;
-    }
-
-    if ((qId < IX_QMGR_MIN_QUEUPP_QID) &&
-       !IX_QMGR_DISPATCHER_SOURCE_ID_CHECK(srcSel))
-    {
-	/* QId 0-31 source id invalid */
-	return IX_QMGR_INVALID_INT_SOURCE_ID;
-    }
-
-    if ((IX_QMGR_Q_SOURCE_ID_NE != srcSel) &&
-	(qId >= IX_QMGR_MIN_QUEUPP_QID))
-    {
-	/*
-	 * For queues 32-63 the interrupt source is fixed to the Nearly
-	 * Empty status flag and therefore should have a srcSel of NE.
-	 */
-	return IX_QMGR_INVALID_INT_SOURCE_ID;
-    }
-#endif
-
-#ifndef NDEBUG
-    dispatcherStats.queueStats[qId].notificationEnabled = TRUE;
-    dispatcherStats.queueStats[qId].srcSel = srcSel;
-#endif
-
-    /* Get the current queue status */
-    ixQMgrAqmIfQueStatRead (qId, &qStatusOnEntry);
-  
-    /* 
-     * Enabling interrupts results in Read-Modify-Write
-     * so need critical section
-     */
-
-    ixQMgrLockKey = ixOsalIrqLock();
-
-    /* Calculate the checkMask and checkValue for this q */
-    ixQMgrAqmIfQStatusCheckValsCalc (qId,
-				     srcSel,
-				     &dispatchQInfo[qId].statusWordOffset,
-				     &dispatchQInfo[qId].statusCheckValue,
-				     &dispatchQInfo[qId].statusMask);
-
-
-    /* Set the interupt source is this queue is in the range 0-31 */
-    if (qId < IX_QMGR_MIN_QUEUPP_QID)
-    {
-	ixQMgrAqmIfIntSrcSelWrite (qId, srcSel);
-    }
-
-    /* Enable the interrupt */
-    ixQMgrAqmIfQInterruptEnable (qId);
-
-    ixOsalIrqUnlock(ixQMgrLockKey);
-    
-    /* Get the current queue status */
-    ixQMgrAqmIfQueStatRead (qId, &qStatusOnExit);
-  
-    /* If the status has changed return a warning */
-    if (qStatusOnEntry != qStatusOnExit)
-    {
-	return IX_QMGR_WARNING;
-    }
-    
-    return IX_SUCCESS;
-}
-
-
-IX_STATUS
-ixQMgrNotificationDisable (IxQMgrQId qId)
-{
-    int ixQMgrLockKey;
-
-#ifndef NDEBUG
-    /* Validate parameters */
-    if (!ixQMgrQIsConfigured (qId))
-    {
-	return IX_QMGR_Q_NOT_CONFIGURED;
-    }
-#endif
-  
-    /* 
-     * Enabling interrupts results in Read-Modify-Write
-     * so need critical section
-     */
-#ifndef NDEBUG
-    dispatcherStats.queueStats[qId].notificationEnabled = FALSE;
-#endif
-
-    ixQMgrLockKey = ixOsalIrqLock();
-
-    ixQMgrAqmIfQInterruptDisable (qId);
-    
-    ixOsalIrqUnlock(ixQMgrLockKey);
-
-    return IX_SUCCESS;    
-}
-
-void 
-ixQMgrStickyInterruptRegEnable(void)
-{
- /* Use Aqm If function to set Interrupt Register0 Bit-3 */ 
- ixQMgrAqmIfIntSrcSelReg0Bit3Set ();   
-}
-
-#if !defined __XSCALE__ || defined __linux
-
-/* Count the number of leading zero bits in a word,
- * and return the same value than the CLZ instruction.
- *
- * word (in)    return value (out)
- * 0x80000000   0
- * 0x40000000   1
- * ,,,          ,,,
- * 0x00000002   30
- * 0x00000001   31
- * 0x00000000   32
- *
- * The C version of this function is used as a replacement 
- * for system not providing the equivalent of the CLZ 
- * assembly language instruction.
- *
- * Note that this version is big-endian
- */
-unsigned int
-ixQMgrCountLeadingZeros(UINT32 word)
-{
-  unsigned int leadingZerosCount = 0;
-
-  if (word == 0)
-  {
-      return 32;
-  }
-  /* search the first bit set by testing the MSB and shifting the input word */
-  while ((word & 0x80000000) == 0)
-  {
-      word <<= 1;
-      leadingZerosCount++;
-  }
-  return leadingZerosCount;
-}
-#endif /* not  __XSCALE__ or __linux */
-
-void
-ixQMgrDispatcherLoopGet (IxQMgrDispatcherFuncPtr *qDispatcherFuncPtr)
-{
-  IxFeatureCtrlProductId productId = 0;
-  IxFeatureCtrlDeviceId deviceId = 0;
-  
-  /* Get the device ID for the underlying silicon */
-  deviceId = ixFeatureCtrlDeviceRead();
-
-  /* Get the product ID for the underlying silicon */
-  productId = ixFeatureCtrlProductIdRead ();
-
-  /* IF (IXP42X AND A0 silicon) -> use ixQMgrDispatcherLoopRunA0 */
-  if ((IX_FEATURE_CTRL_DEVICE_TYPE_IXP42X ==
-      (IX_FEATURE_CTRL_DEVICE_TYPE_MASK & deviceId)) &&
-      (IX_FEATURE_CTRL_SILICON_TYPE_A0 ==  
-      (IX_FEATURE_CTRL_SILICON_STEPPING_MASK & productId)))  
-  {
-    /*For IXP42X A0 silicon */
-    *qDispatcherFuncPtr = &ixQMgrDispatcherLoopRunA0 ;
-  } 
-  else /*For IXP42X B0 or IXP46X silicon*/ 
-  { 
-    if (IX_FEATURE_CTRL_SWCONFIG_ENABLED == ixQMgrOrigB0Dispatcher)
-    {
-        /* Default for IXP42X B0 and IXP46X silicon */
-        *qDispatcherFuncPtr = &ixQMgrDispatcherLoopRunB0;
-    }
-    else 
-    {
-        /* FeatureCtrl indicated that livelock dispatcher be used */
-        *qDispatcherFuncPtr = &ixQMgrDispatcherLoopRunB0LLP;
-    }
-  }
-}
-
-void
-ixQMgrDispatcherLoopRunA0 (IxQMgrDispatchGroup group)
-{
-    UINT32 intRegVal;                /* Interrupt reg val */
-    UINT32 intRegValAfterWrite;      /* Interrupt reg val after writing back */
-    UINT32 intRegCheckMask;          /* Mask for checking interrupt bits */
-    UINT32 qStatusWordsB4Write[MAX_Q_STATUS_WORDS];  /* Status b4 interrupt write */
-    UINT32 qStatusWordsAfterWrite[MAX_Q_STATUS_WORDS]; /* Status after interrupt write */
-    IxQMgrQInfo *currDispatchQInfo;
-    BOOL statusChangeFlag;
-
-    int priorityTableIndex;/* Priority table index */
-    int qIndex;            /* Current queue being processed */
-    int endIndex;          /* Index of last queue to process */
-
-#ifndef NDEBUG
-    IX_OSAL_ASSERT((group == IX_QMGR_QUEUPP_GROUP) || 
-	      (group == IX_QMGR_QUELOW_GROUP));
-#endif
-
-    /* Read Q status registers before interrupt status read/write */
-    ixQMgrAqmIfQStatusRegsRead (group, qStatusWordsB4Write);
-
-    /* Read the interrupt register */
-    ixQMgrAqmIfQInterruptRegRead (group, &intRegVal);
-
-    /* No bit set : nothing to process (the reaminder of the algorithm is
-    * based on the fact that the interrupt register value contains at
-    * least one bit set
-    */
-    if (intRegVal == 0) 
-    {
-#ifndef NDEBUG
-	/* Update statistics */
-	dispatcherStats.loopRunCnt++;
-#endif
-
-	/* Rebuild the priority table if needed */
-	if (rebuildTable)
-	{
-	    ixQMgrDispatcherReBuildPriorityTable ();
-	}
-
-	return;
-    }
-   
-    /* Write it back to clear the interrupt */
-    ixQMgrAqmIfQInterruptRegWrite (group, intRegVal);
-
-    /* Read Q status registers after interrupt status read/write */
-    ixQMgrAqmIfQStatusRegsRead (group, qStatusWordsAfterWrite);
- 
-    /* get the first queue Id from the interrupt register value */
-    qIndex = (BITS_PER_WORD - 1) - ixQMgrCountLeadingZeros(intRegVal);
-
-    /* check if any change occured during hw register modifications */ 
-    if (IX_QMGR_QUELOW_GROUP == group)
-    {
-	statusChangeFlag = 
-	    (qStatusWordsB4Write[0] != qStatusWordsAfterWrite[0]) ||
-	    (qStatusWordsB4Write[1] != qStatusWordsAfterWrite[1]) ||
-	    (qStatusWordsB4Write[2] != qStatusWordsAfterWrite[2]) ||
-	    (qStatusWordsB4Write[3] != qStatusWordsAfterWrite[3]);
-    }
-    else
-    {
-	statusChangeFlag = 
-	    (qStatusWordsB4Write[0] != qStatusWordsAfterWrite[0]);
-	/* Set the queue range based on the queue group to proccess */
-	qIndex += IX_QMGR_MIN_QUEUPP_QID;
-    }
-
-    if (statusChangeFlag == FALSE)
-    {
-	/* check if the interrupt register contains 
-	 * only 1 bit set (happy day scenario)
-	 */
-	currDispatchQInfo = &dispatchQInfo[qIndex];
-	if (intRegVal == currDispatchQInfo->intRegCheckMask)
-	{
-	    /* only 1 queue event triggered a notification *
-	     * Call the callback function for this queue 
-	     */
-	    currDispatchQInfo->callback (qIndex,
-					 currDispatchQInfo->callbackId);  
-#ifndef NDEBUG
-	    /* Update statistics */
-	    dispatcherStats.queueStats[qIndex].callbackCnt++;
-#endif
-	}
-	else 
-	{
-	    /* the event is triggered by more than 1 queue, 
-	     * the queue search will be starting from the beginning
-	     * or the middle of the priority table
-	     *
-	     * the serach will end when all the bits of the interrupt
-	     * register are cleared. There is no need to maintain
-	     * a seperate value and test it at each iteration.
-	     */
-	    if (IX_QMGR_QUELOW_GROUP == group)
-	    {
-		/* check if any bit related to queues in the first
-		 * half of the priority table is set
-		 */
-		if (intRegVal & lowPriorityTableFirstHalfMask)
-		{
-		    priorityTableIndex = IX_QMGR_MIN_LOW_QUE_PRIORITY_TABLE_INDEX;
-		}
-		else
-		{
-		    priorityTableIndex = IX_QMGR_MID_LOW_QUE_PRIORITY_TABLE_INDEX;
-		}
-	    }
-	    else 
-	    {
-		/* check if any bit related to queues in the first
-		 * half of the priority table is set
-		 */
-		if (intRegVal & uppPriorityTableFirstHalfMask)
-		{
-		    priorityTableIndex = IX_QMGR_MIN_UPP_QUE_PRIORITY_TABLE_INDEX;
-		}
-		else
-		{
-		    priorityTableIndex = IX_QMGR_MID_UPP_QUE_PRIORITY_TABLE_INDEX;
-		}
-	    }
-	    
-	    /* iterate following the priority table until all the bits 
-	     * of the interrupt register are cleared.
-	     */
-	    do
-	    {
-		qIndex = priorityTable[priorityTableIndex++];
-		currDispatchQInfo = &dispatchQInfo[qIndex];
-		intRegCheckMask = currDispatchQInfo->intRegCheckMask;
-		
-		/* If this queue caused this interrupt to be raised */
-		if (intRegVal & intRegCheckMask)
-		{
-		    /* Call the callback function for this queue */
-		    currDispatchQInfo->callback (qIndex,
-						 currDispatchQInfo->callbackId);
-#ifndef NDEBUG
-		    /* Update statistics */
-		    dispatcherStats.queueStats[qIndex].callbackCnt++;
-#endif
-		    
-		    /* Clear the interrupt register bit */
-		    intRegVal &= ~intRegCheckMask;
-		}
-	    }
-	    while(intRegVal);
-	}
-    }
-    else
-    {
-    /* A change in queue status occured during the hw interrupt
-     * register update. To maintain the interrupt consistency, it
-     * is necessary to iterate through all queues of the queue group.
-     */
-
-    /* Read interrupt status again */
-    ixQMgrAqmIfQInterruptRegRead (group, &intRegValAfterWrite);
-
-    if (IX_QMGR_QUELOW_GROUP == group)
-    {
-	priorityTableIndex = IX_QMGR_MIN_LOW_QUE_PRIORITY_TABLE_INDEX;
-	endIndex = IX_QMGR_MAX_LOW_QUE_PRIORITY_TABLE_INDEX;
-    }
-    else
-    {
-	priorityTableIndex = IX_QMGR_MIN_UPP_QUE_PRIORITY_TABLE_INDEX;
-	endIndex = IX_QMGR_MAX_UPP_QUE_PRIORITY_TABLE_INDEX;
-    }
-
-    for ( ; priorityTableIndex<=endIndex; priorityTableIndex++)
-    {
-	qIndex = priorityTable[priorityTableIndex];
-	currDispatchQInfo = &dispatchQInfo[qIndex];
-	intRegCheckMask = currDispatchQInfo->intRegCheckMask;
-
-	/* If this queue caused this interrupt to be raised */
-	if (intRegVal & intRegCheckMask)
-	{  
-	    /* Call the callback function for this queue */
-	    currDispatchQInfo->callback (qIndex,
-					 currDispatchQInfo->callbackId);
-#ifndef NDEBUG
-	    /* Update statistics */
-	    dispatcherStats.queueStats[qIndex].callbackCnt++;
-#endif
-	    
-	} /* if (intRegVal .. */
-
-	/* 
-	 * If interrupt bit is set in intRegValAfterWrite don't
-	 * proceed as this will be caught in next interrupt
-	 */
-	else if ((intRegValAfterWrite & intRegCheckMask) == 0)
-	{
-	    /* Check if an interrupt was lost for this Q */
-	    if (ixQMgrAqmIfQStatusCheck(qStatusWordsB4Write,
-					qStatusWordsAfterWrite,
-					currDispatchQInfo->statusWordOffset,
-					currDispatchQInfo->statusCheckValue,
-					currDispatchQInfo->statusMask))
-	    {
-		/* Call the callback function for this queue */
-		currDispatchQInfo->callback (qIndex, 
-					     dispatchQInfo[qIndex].callbackId);                 
-#ifndef NDEBUG
-		/* Update statistics */
-		dispatcherStats.queueStats[qIndex].callbackCnt++;
-		dispatcherStats.queueStats[qIndex].intLostCallbackCnt++;
-#endif
-	    } /* if ixQMgrAqmIfQStatusCheck(.. */
-	} /* else if ((intRegValAfterWrite ... */
-    } /* for (priorityTableIndex=0 ... */
-    }
-
-    /* Rebuild the priority table if needed */
-    if (rebuildTable)
-    {
-	ixQMgrDispatcherReBuildPriorityTable ();
-    }
-
-#ifndef NDEBUG
-    /* Update statistics */
-    dispatcherStats.loopRunCnt++;
-#endif
-}
-
-
-
-void
-ixQMgrDispatcherLoopRunB0 (IxQMgrDispatchGroup group)
-{
-    UINT32 intRegVal;                /* Interrupt reg val */
-    UINT32 intRegCheckMask;          /* Mask for checking interrupt bits */
-    IxQMgrQInfo *currDispatchQInfo;
-
-
-    int priorityTableIndex; /* Priority table index */
-    int qIndex;             /* Current queue being processed */
-
-#ifndef NDEBUG
-    IX_OSAL_ASSERT((group == IX_QMGR_QUEUPP_GROUP) ||
-              (group == IX_QMGR_QUELOW_GROUP));
-    IX_OSAL_ASSERT((group == IX_QMGR_QUEUPP_GROUP) || 
-	      (group == IX_QMGR_QUELOW_GROUP));
-#endif
-
-    /* Read the interrupt register */
-    ixQMgrAqmIfQInterruptRegRead (group, &intRegVal);
-
-
-    /* No queue has interrupt register set */
-    if (intRegVal != 0)
-    {
-
-            /* Write it back to clear the interrupt */
-            ixQMgrAqmIfQInterruptRegWrite (group, intRegVal);
-
-            /* get the first queue Id from the interrupt register value */
-            qIndex = (BITS_PER_WORD - 1) - ixQMgrCountLeadingZeros(intRegVal);
-
-            if (IX_QMGR_QUEUPP_GROUP == group)
-            {
-                /* Set the queue range based on the queue group to proccess */
-                qIndex += IX_QMGR_MIN_QUEUPP_QID;
-            }
-
-            /* check if the interrupt register contains
-             * only 1 bit set
-             * For example:
-             *                                        intRegVal = 0x0010
-             *               currDispatchQInfo->intRegCheckMask = 0x0010
-             *    intRegVal == currDispatchQInfo->intRegCheckMask is TRUE.
-             */
-             currDispatchQInfo = &dispatchQInfo[qIndex];
-             if (intRegVal == currDispatchQInfo->intRegCheckMask)
-             {
-                /* only 1 queue event triggered a notification *
-                 * Call the callback function for this queue
-                 */
-                currDispatchQInfo->callback (qIndex,
-                                     currDispatchQInfo->callbackId);
-#ifndef NDEBUG
-                /* Update statistics */
-                dispatcherStats.queueStats[qIndex].callbackCnt++;
-#endif
-             }
-             else
-             {
-                 /* the event is triggered by more than 1 queue,
-                  * the queue search will be starting from the beginning
-                  * or the middle of the priority table
-                  *
-                  * the serach will end when all the bits of the interrupt
-                  * register are cleared. There is no need to maintain
-                  * a seperate value and test it at each iteration.
-                  */
-                 if (IX_QMGR_QUELOW_GROUP == group)
-                 {
-                     /* check if any bit related to queues in the first
-                      * half of the priority table is set
-                      */
-                     if (intRegVal & lowPriorityTableFirstHalfMask)
-                     {
-                         priorityTableIndex = IX_QMGR_MIN_LOW_QUE_PRIORITY_TABLE_INDEX;
-                     }
-                     else
-                     {
-                         priorityTableIndex = IX_QMGR_MID_LOW_QUE_PRIORITY_TABLE_INDEX;
-                     }
-                 }
-                else
-                 {
-                     /* check if any bit related to queues in the first
-                      * half of the priority table is set
-                      */
-                     if (intRegVal & uppPriorityTableFirstHalfMask)
-                     {
-                         priorityTableIndex = IX_QMGR_MIN_UPP_QUE_PRIORITY_TABLE_INDEX;
-                     }
-                     else
-                     {
-                         priorityTableIndex = IX_QMGR_MID_UPP_QUE_PRIORITY_TABLE_INDEX;
-                     }
-                 }
-
-                 /* iterate following the priority table until all the bits
-                  * of the interrupt register are cleared.
-                  */
-                 do
-                 {
-                     qIndex = priorityTable[priorityTableIndex++];
-                     currDispatchQInfo = &dispatchQInfo[qIndex];
-                     intRegCheckMask = currDispatchQInfo->intRegCheckMask;
-
-                     /* If this queue caused this interrupt to be raised */
-                     if (intRegVal & intRegCheckMask)
-                     {
-                         /* Call the callback function for this queue */
-                         currDispatchQInfo->callback (qIndex,
-                                              currDispatchQInfo->callbackId);
-#ifndef NDEBUG
-                         /* Update statistics */
-                         dispatcherStats.queueStats[qIndex].callbackCnt++;
-#endif
-
-                         /* Clear the interrupt register bit */
-                         intRegVal &= ~intRegCheckMask;
-                     }
-                  }
-                  while(intRegVal);
-             } /*End of intRegVal == currDispatchQInfo->intRegCheckMask */
-     } /* End of intRegVal != 0 */
-
-#ifndef NDEBUG
-    /* Update statistics */
-    dispatcherStats.loopRunCnt++;
-#endif
-
-    /* Rebuild the priority table if needed */
-    if (rebuildTable)
-    {
-        ixQMgrDispatcherReBuildPriorityTable ();
-    }
-}
-
-void
-ixQMgrDispatcherLoopRunB0LLP (IxQMgrDispatchGroup group)
-{
-    UINT32 intRegVal =0;                /* Interrupt reg val */
-    UINT32 intRegCheckMask;          /* Mask for checking interrupt bits */
-    IxQMgrQInfo *currDispatchQInfo;
-
-    int priorityTableIndex; /* Priority table index */
-    int qIndex;             /* Current queue being processed */
-
-    UINT32 intRegValCopy = 0;
-    UINT32 intEnableRegVal = 0;
-    UINT8 i = 0;
-
-#ifndef NDEBUG
-    IX_OSAL_ASSERT((group == IX_QMGR_QUEUPP_GROUP) ||
-              (group == IX_QMGR_QUELOW_GROUP));
-#endif
-
-    /* Read the interrupt register */
-    ixQMgrAqmIfQInterruptRegRead (group, &intRegVal);
-
-    /* 
-     * mask any interrupts that are not enabled 
-     */
-    ixQMgrAqmIfQInterruptEnableRegRead (group, &intEnableRegVal);
-    intRegVal &= intEnableRegVal;
-
-    /* No queue has interrupt register set */
-    if (intRegVal != 0)
-    {
-        if (IX_QMGR_QUELOW_GROUP == group)
-        {
-            /*
-             * As the sticky bit is set, the interrupt register will 
-             * not clear if write back at this point because the condition
-             * has not been cleared. Take a copy and write back later after
-             * the condition has been cleared
-             */
-            intRegValCopy = intRegVal;
-        }
-        else
-        {
-            /* no sticky for upper Q's, so write back now */
-            ixQMgrAqmIfQInterruptRegWrite (group, intRegVal);
-        }
-
-        /* get the first queue Id from the interrupt register value */
-        qIndex = (BITS_PER_WORD - 1) - ixQMgrCountLeadingZeros(intRegVal);
-
-        if (IX_QMGR_QUEUPP_GROUP == group)
-        {
-            /* Set the queue range based on the queue group to proccess */
-            qIndex += IX_QMGR_MIN_QUEUPP_QID;
-        }
-
-        /* check if the interrupt register contains
-        * only 1 bit set
-        * For example:
-        *                                        intRegVal = 0x0010
-        *               currDispatchQInfo->intRegCheckMask = 0x0010
-        *    intRegVal == currDispatchQInfo->intRegCheckMask is TRUE.
-        */
-        currDispatchQInfo = &dispatchQInfo[qIndex];
-        if (intRegVal == currDispatchQInfo->intRegCheckMask)
-        {
-
-            /* 
-             * check if Q type periodic -  only lower queues can
-             * have there type set to periodic 
-             */
-            if (IX_QMGR_TYPE_REALTIME_PERIODIC == ixQMgrQTypes[qIndex])
-            {
-                /* 
-                 * Disable the notifications on any sporadics 
-                 */
-                for (i=0; i <= IX_QMGR_MAX_LOW_QUE_TABLE_INDEX; i++)
-                {
-                    if (IX_QMGR_TYPE_REALTIME_SPORADIC == ixQMgrQTypes[i])
-                    {
-                        ixQMgrNotificationDisable(i);
-#ifndef NDEBUG
-                        /* Update statistics */
-                        dispatcherStats.queueStats[i].disableCount++;
-#endif
-                    }
-                }
-            }
-
-            currDispatchQInfo->callback (qIndex,
-                                         currDispatchQInfo->callbackId);
-#ifndef NDEBUG
-            /* Update statistics */
-            dispatcherStats.queueStats[qIndex].callbackCnt++;
-#endif
-        }
-        else
-        {
-            /* the event is triggered by more than 1 queue,
-            * the queue search will be starting from the beginning
-            * or the middle of the priority table
-            *
-            * the serach will end when all the bits of the interrupt
-            * register are cleared. There is no need to maintain
-            * a seperate value and test it at each iteration.
-            */
-            if (IX_QMGR_QUELOW_GROUP == group)
-            {
-                /* check if any bit related to queues in the first
-                 * half of the priority table is set
-                 */
-                if (intRegVal & lowPriorityTableFirstHalfMask)
-                {
-                    priorityTableIndex =
-                                       IX_QMGR_MIN_LOW_QUE_PRIORITY_TABLE_INDEX;
-                }
-                else
-                {
-                    priorityTableIndex =
-                                       IX_QMGR_MID_LOW_QUE_PRIORITY_TABLE_INDEX;
-                }
-            }
-            else
-            {
-                /* check if any bit related to queues in the first
-                 * half of the priority table is set
-                 */
-                if (intRegVal & uppPriorityTableFirstHalfMask)
-                {
-                    priorityTableIndex =
-                                       IX_QMGR_MIN_UPP_QUE_PRIORITY_TABLE_INDEX;
-                }
-                else
-                {
-                    priorityTableIndex =
-                                       IX_QMGR_MID_UPP_QUE_PRIORITY_TABLE_INDEX;
-                }
-            }
-
-            /* iterate following the priority table until all the bits
-             * of the interrupt register are cleared.
-             */
-            do
-            {
-                qIndex = priorityTable[priorityTableIndex++];
-                currDispatchQInfo = &dispatchQInfo[qIndex];
-                intRegCheckMask = currDispatchQInfo->intRegCheckMask;
-
-                /* If this queue caused this interrupt to be raised */
-                if (intRegVal & intRegCheckMask)
-                {
-                    /* 
-                     * check if Q type periodic - only lower queues can
-                     * have there type set to periodic. There can only be one
-                     * periodic queue, so the sporadics are only disabled once.
-                     */
-                    if (IX_QMGR_TYPE_REALTIME_PERIODIC == ixQMgrQTypes[qIndex])
-                    {
-                        /* 
-                         * Disable the notifications on any sporadics 
-                         */
-                        for (i=0; i <= IX_QMGR_MAX_LOW_QUE_TABLE_INDEX; i++)
-                        {
-                            if (IX_QMGR_TYPE_REALTIME_SPORADIC == 
-                                    ixQMgrQTypes[i])
-                            {
-                                ixQMgrNotificationDisable(i);
-                                /* 
-                                 * remove from intRegVal as we don't want 
-                                 * to service any sporadics now
-                                 */
-                                intRegVal &= ~dispatchQInfo[i].intRegCheckMask;
-#ifndef NDEBUG
-                                /* Update statistics */
-                                dispatcherStats.queueStats[i].disableCount++;
-#endif
-                            }
-                        }
-                    }
-
-                    currDispatchQInfo->callback (qIndex,
-                                                 currDispatchQInfo->callbackId);
-#ifndef NDEBUG
-                    /* Update statistics */
-                    dispatcherStats.queueStats[qIndex].callbackCnt++;
-#endif
-                    /* Clear the interrupt register bit */
-                    intRegVal &= ~intRegCheckMask;
-                }
-            }
-            while(intRegVal);
-        } /*End of intRegVal == currDispatchQInfo->intRegCheckMask */
-    } /* End of intRegVal != 0 */
-
-#ifndef NDEBUG
-    /* Update statistics */
-    dispatcherStats.loopRunCnt++;
-#endif
-
-    if ((intRegValCopy != 0) && (IX_QMGR_QUELOW_GROUP == group))
-    {
-        /* 
-         * lower groups (therefore sticky) AND at least one enabled interrupt
-         * Write back to clear the interrupt 
-         */
-        ixQMgrAqmIfQInterruptRegWrite (IX_QMGR_QUELOW_GROUP, intRegValCopy);
-    }
-
-    /* Rebuild the priority table if needed */
-    if (rebuildTable)
-    {
-        ixQMgrDispatcherReBuildPriorityTable ();
-    }
-}
-
-PRIVATE void
-ixQMgrDispatcherReBuildPriorityTable (void)
-{
-    UINT32 qIndex;
-    UINT32 priority;
-    int lowQuePriorityTableIndex = IX_QMGR_MIN_LOW_QUE_PRIORITY_TABLE_INDEX;
-    int uppQuePriorityTableIndex = IX_QMGR_MIN_UPP_QUE_PRIORITY_TABLE_INDEX;
-
-    /* Reset the rebuild flag */
-    rebuildTable = FALSE;
-
-    /* initialize the mak used to identify the queues in the first half
-     * of the priority table
-     */
-    lowPriorityTableFirstHalfMask = 0;
-    uppPriorityTableFirstHalfMask = 0;
-    
-    /* For each priority level */
-    for(priority=0; priority<IX_QMGR_NUM_PRIORITY_LEVELS; priority++)
-    {
-	/* Foreach low queue in this priority */
-	for(qIndex=0; qIndex<IX_QMGR_MIN_QUEUPP_QID; qIndex++)
-	{
-	    if (dispatchQInfo[qIndex].priority == priority)
-	    { 
-		/* build the priority table bitmask which match the
-		 * queues of the first half of the priority table 
-		 */
-		if (lowQuePriorityTableIndex < IX_QMGR_MID_LOW_QUE_PRIORITY_TABLE_INDEX) 
-		{
-		    lowPriorityTableFirstHalfMask |= dispatchQInfo[qIndex].intRegCheckMask;
-		}
-		/* build the priority table */
-		priorityTable[lowQuePriorityTableIndex++] = qIndex;
-	    }
-	}
-	/* Foreach upp queue */
-	for(qIndex=IX_QMGR_MIN_QUEUPP_QID; qIndex<=IX_QMGR_MAX_QID; qIndex++)
-	{
-	    if (dispatchQInfo[qIndex].priority == priority)
-	    {
-		/* build the priority table bitmask which match the
-		 * queues of the first half of the priority table 
-		 */
-		if (uppQuePriorityTableIndex < IX_QMGR_MID_UPP_QUE_PRIORITY_TABLE_INDEX) 
-		{
-		    uppPriorityTableFirstHalfMask |= dispatchQInfo[qIndex].intRegCheckMask;
-		}
-		/* build the priority table */
-		priorityTable[uppQuePriorityTableIndex++] = qIndex;
-	    }
-	}
-    }
-}
-
-IxQMgrDispatcherStats*
-ixQMgrDispatcherStatsGet (void)
-{
-    return &dispatcherStats;
-}
-
-PRIVATE void
-dummyCallback (IxQMgrQId qId,
-	       IxQMgrCallbackId cbId)
-{
-    /* Throttle the trace message */
-    if ((dispatchQInfo[qId].dummyCallbackCount % LOG_THROTTLE_COUNT) == 0)
-    {
-	IX_QMGR_LOG_WARNING2("--> dummyCallback: qId (%d), callbackId (%d)\n",qId,cbId);
-    }
-    dispatchQInfo[qId].dummyCallbackCount++;
-
-#ifndef NDEBUG
-    /* Update statistcs */
-    dispatcherStats.queueStats[qId].intNoCallbackCnt++;
-#endif
-}
-void
-ixQMgrLLPShow (int resetStats)
-{
-#ifndef NDEBUG
-    UINT8 i = 0;
-    IxQMgrQInfo *q;
-    UINT32 intEnableRegVal = 0;
-
-    printf ("Livelock statistics are printed on the fly.\n");
-    printf ("qId Type     EnableCnt DisableCnt IntEnableState Callbacks\n");
-    printf ("=== ======== ========= ========== ============== =========\n");
-
-    for (i=0; i<= IX_QMGR_MAX_LOW_QUE_TABLE_INDEX; i++)
-    {
-        q = &dispatchQInfo[i];
-
-        if (ixQMgrQTypes[i] != IX_QMGR_TYPE_REALTIME_OTHER)
-        {
-            printf (" %2d ", i);
-
-            if (ixQMgrQTypes[i] == IX_QMGR_TYPE_REALTIME_SPORADIC)
-            {
-                printf ("Sporadic");
-            }
-            else
-            {
-                printf ("Periodic");
-            }
-
-           
-            ixQMgrAqmIfQInterruptEnableRegRead (IX_QMGR_QUELOW_GROUP, 
-                                                    &intEnableRegVal);
-            	
-
-	    intEnableRegVal &= dispatchQInfo[i].intRegCheckMask;
-            intEnableRegVal = intEnableRegVal >> i;
-
-            printf (" %10d %10d %10d %10d\n",
-                    dispatcherStats.queueStats[i].enableCount,
-                    dispatcherStats.queueStats[i].disableCount,
-                    intEnableRegVal,
-                    dispatcherStats.queueStats[i].callbackCnt);
-
-            if (resetStats)
-            {
-                dispatcherStats.queueStats[i].enableCount =
-                dispatcherStats.queueStats[i].disableCount = 
-                dispatcherStats.queueStats[i].callbackCnt = 0;
-            }
-        }
-    }
-#else
-    IX_QMGR_LOG0("Livelock Prevention statistics are only collected in debug mode\n");
-#endif
-}
-
-void
-ixQMgrPeriodicDone (void)
-{
-    UINT32 i = 0;
-    UINT32 ixQMgrLockKey = 0;
-
-    /* 
-     * for the lower queues
-     */
-    for (i=0; i <= IX_QMGR_MAX_LOW_QUE_TABLE_INDEX; i++)
-    {
-        /*
-         * check for sporadics 
-         */
-        if (IX_QMGR_TYPE_REALTIME_SPORADIC == ixQMgrQTypes[i])
-        {
-             /* 
-              * enable any sporadics 
-              */
-             ixQMgrLockKey = ixOsalIrqLock();
-             ixQMgrAqmIfQInterruptEnable(i);
-             ixOsalIrqUnlock(ixQMgrLockKey);
-#ifndef NDEBUG
-             /* 
-              * Update statistics 
-              */
-             dispatcherStats.queueStats[i].enableCount++;
-             dispatcherStats.queueStats[i].notificationEnabled = TRUE;
-#endif
-        }
-    }
-}
-IX_STATUS
-ixQMgrCallbackTypeSet (IxQMgrQId qId, 
-                       IxQMgrType type)
-{
-    UINT32 ixQMgrLockKey = 0;
-    IxQMgrType ixQMgrOldType =0;
-
-#ifndef NDEBUG
-    if (!ixQMgrQIsConfigured(qId))
-    {
-        return IX_QMGR_Q_NOT_CONFIGURED;
-    }
-    if (qId >= IX_QMGR_MIN_QUEUPP_QID)
-    {
-        return IX_QMGR_PARAMETER_ERROR;
-    }
-    if(!IX_QMGR_DISPATCHER_CALLBACK_TYPE_CHECK(type))
-    {
-        return IX_QMGR_PARAMETER_ERROR;
-    }
-#endif
-
-    ixQMgrOldType = ixQMgrQTypes[qId];
-    ixQMgrQTypes[qId] = type;
-
-    /*
-     * check if Q has been changed from type SPORADIC
-     */
-    if (IX_QMGR_TYPE_REALTIME_SPORADIC == ixQMgrOldType)
-    {
-       /* 
-        * previously Q was a SPORADIC, this means that LLP
-        * might have had it disabled. enable it now.
-        */
-       ixQMgrLockKey = ixOsalIrqLock();
-       ixQMgrAqmIfQInterruptEnable(qId);
-       ixOsalIrqUnlock(ixQMgrLockKey);
-
-#ifndef NDEBUG
-       /* 
-        * Update statistics 
-        */
-       dispatcherStats.queueStats[qId].enableCount++;
-#endif
-    }
-
-    return IX_SUCCESS;
-}
-
-IX_STATUS
-ixQMgrCallbackTypeGet (IxQMgrQId qId, 
-                       IxQMgrType *type)
-{
-#ifndef NDEBUG
-    if (!ixQMgrQIsConfigured(qId))
-    {
-        return IX_QMGR_Q_NOT_CONFIGURED;
-    }
-    if (qId >= IX_QMGR_MIN_QUEUPP_QID)
-    {
-        return IX_QMGR_PARAMETER_ERROR;
-    }
-    if(type == NULL)
-    {
-         return IX_QMGR_PARAMETER_ERROR;
-    }
-#endif
-
-    *type = ixQMgrQTypes[qId];
-    return IX_SUCCESS;
-}
diff --git a/arch/arm/cpu/ixp/npe/IxQMgrInit.c b/arch/arm/cpu/ixp/npe/IxQMgrInit.c
deleted file mode 100644
index b00c22d..0000000
--- a/arch/arm/cpu/ixp/npe/IxQMgrInit.c
+++ /dev/null
@@ -1,233 +0,0 @@
-/**
- * @file    IxQMgrInit.c
- *
- * @author Intel Corporation
- * @date    30-Oct-2001
- *
- * @brief:  Provided initialization of the QMgr component and its subcomponents.
- *
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- * 
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- * 
- * @par
- * -- End of Copyright Notice --
-*/
-
-/*
- * System defined include files.
- */
-
-/*
- * User defined include files.
- */
-#include "IxOsal.h"
-#include "IxQMgr.h"
-#include "IxQMgrQCfg_p.h"
-#include "IxQMgrDispatcher_p.h"
-#include "IxQMgrLog_p.h"
-#include "IxQMgrQAccess_p.h"
-#include "IxQMgrDefines_p.h"
-#include "IxQMgrAqmIf_p.h"
-
-/*
- * Set to true if initialized
- * N.B. global so integration/unit tests can reinitialize
- */
-BOOL qMgrIsInitialized = FALSE;
-
-/*
- * Function definitions.
- */
-IX_STATUS
-ixQMgrInit (void)
-{
-    if (qMgrIsInitialized)
-    {
-	IX_QMGR_LOG0("ixQMgrInit: IxQMgr already initialised\n");
-	return IX_FAIL;
-    }
-
-    /* Initialise the QCfg component */
-    ixQMgrQCfgInit ();
-
-    /* Initialise the Dispatcher component */
-    ixQMgrDispatcherInit ();
-
-    /* Initialise the Access component */
-    ixQMgrQAccessInit ();
-
-    /* Initialization complete */
-    qMgrIsInitialized = TRUE;
-
-    return IX_SUCCESS;
-}
-
-IX_STATUS
-ixQMgrUnload (void)
-{
-    if (!qMgrIsInitialized)
-    {
-	return IX_FAIL;
-    }
-
-    /* Uninitialise the QCfg component */
-    ixQMgrQCfgUninit ();
-
-    /* Uninitialization complete */
-    qMgrIsInitialized = FALSE;
-
-    return IX_SUCCESS;
-}
-
-void
-ixQMgrShow (void)
-{
-    IxQMgrQCfgStats *qCfgStats = NULL;
-    IxQMgrDispatcherStats *dispatcherStats = NULL;
-    int i;
-    UINT32 lowIntRegRead, upIntRegRead;
-
-    qCfgStats = ixQMgrQCfgStatsGet ();
-    dispatcherStats = ixQMgrDispatcherStatsGet ();
-    ixQMgrAqmIfQInterruptRegRead (IX_QMGR_QUELOW_GROUP, &lowIntRegRead);
-    ixQMgrAqmIfQInterruptRegRead (IX_QMGR_QUEUPP_GROUP, &upIntRegRead);
-    printf("Generic Stats........\n");
-    printf("=====================\n");
-    printf("Loop Run Count..........%u\n",dispatcherStats->loopRunCnt);
-    printf("Watermark set count.....%d\n", qCfgStats->wmSetCnt);
-    printf("===========================================\n");
-    printf("On the fly Interrupt Register Stats........\n");
-    printf("===========================================\n");
-    printf("Lower Interrupt Register............0x%08x\n",lowIntRegRead);
-    printf("Upper Interrupt Register............0x%08x\n",upIntRegRead);
-    printf("==============================================\n");
-    printf("Queue Specific Stats........\n");
-    printf("============================\n");
-
-    for (i=0; i<IX_QMGR_MAX_NUM_QUEUES; i++)
-    {
-	if (ixQMgrQIsConfigured(i))
-	{
-	    ixQMgrQShow(i);
-	}
-    }
-
-    printf("============================\n");
-}
-
-IX_STATUS
-ixQMgrQShow (IxQMgrQId qId)
-{
-    IxQMgrQCfgStats *qCfgStats = NULL;
-    IxQMgrDispatcherStats *dispatcherStats = NULL; 
-
-    if (!ixQMgrQIsConfigured(qId))
-    {
-	return IX_QMGR_Q_NOT_CONFIGURED;
-    }
-    
-    dispatcherStats = ixQMgrDispatcherStatsGet ();
-    qCfgStats = ixQMgrQCfgQStatsGet (qId);
-
-    printf("QId %d\n", qId);
-    printf("======\n");
-    printf("  IxQMgrQCfg Stats\n");
-    printf("    Name..................... \"%s\"\n", qCfgStats->qStats[qId].qName);
-    printf("    Size in words............ %u\n", qCfgStats->qStats[qId].qSizeInWords);
-    printf("    Entry size in words...... %u\n", qCfgStats->qStats[qId].qEntrySizeInWords);
-    printf("    Nearly empty watermark... %u\n", qCfgStats->qStats[qId].ne);
-    printf("    Nearly full watermark.... %u\n", qCfgStats->qStats[qId].nf);
-    printf("    Number of full entries... %u\n", qCfgStats->qStats[qId].numEntries);
-    printf("    Sram base address........ 0x%X\n", qCfgStats->qStats[qId].baseAddress);
-    printf("    Read pointer............. 0x%X\n", qCfgStats->qStats[qId].readPtr);
-    printf("    Write pointer............ 0x%X\n", qCfgStats->qStats[qId].writePtr);
-
-#ifndef NDEBUG
-    if (dispatcherStats->queueStats[qId].notificationEnabled)
-    {
-        char *localEvent = "none ????";
-        switch (dispatcherStats->queueStats[qId].srcSel)
-        {
-            case IX_QMGR_Q_SOURCE_ID_E:
-                localEvent = "Empty";
-                break;
-            case IX_QMGR_Q_SOURCE_ID_NE:
-                localEvent = "Nearly Empty";
-                break;
-            case IX_QMGR_Q_SOURCE_ID_NF:
-                localEvent = "Nearly Full";
-                break;
-            case IX_QMGR_Q_SOURCE_ID_F:
-                localEvent = "Full";
-                break;
-            case IX_QMGR_Q_SOURCE_ID_NOT_E:
-                localEvent = "Not Empty";
-                break;
-            case IX_QMGR_Q_SOURCE_ID_NOT_NE:
-                localEvent = "Not Nearly Empty";
-                break;
-            case IX_QMGR_Q_SOURCE_ID_NOT_NF:
-                localEvent = "Not Nearly Full";
-                break;
-            case IX_QMGR_Q_SOURCE_ID_NOT_F:
-                localEvent = "Not Full";
-                break;
-            default :
-                break;
-        }
-        printf("    Notifications localEvent...... %s\n", localEvent);
-    }
-    else
-    {
-        printf("    Notifications............ not enabled\n");
-    }
-    printf("  IxQMgrDispatcher Stats\n");
-    printf("    Callback count................%d\n",
-	  dispatcherStats->queueStats[qId].callbackCnt);
-    printf("    Priority change count.........%d\n",
-	  dispatcherStats->queueStats[qId].priorityChangeCnt);
-    printf("    Interrupt no callback count...%d\n",
-	  dispatcherStats->queueStats[qId].intNoCallbackCnt);
-    printf("    Interrupt lost callback count...%d\n",
-	  dispatcherStats->queueStats[qId].intLostCallbackCnt);
-#endif
-
-    return IX_SUCCESS;
-}
-
-
-
-
diff --git a/arch/arm/cpu/ixp/npe/IxQMgrQAccess.c b/arch/arm/cpu/ixp/npe/IxQMgrQAccess.c
deleted file mode 100644
index 8885736..0000000
--- a/arch/arm/cpu/ixp/npe/IxQMgrQAccess.c
+++ /dev/null
@@ -1,796 +0,0 @@
-/**
- * @file    IxQMgrQAccess.c
- *
- * @author Intel Corporation
- * @date    30-Oct-2001
- *
- * @brief   This file contains functions for putting entries on a queue and
- * removing entries from a queue.
- *
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- * 
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- * 
- * @par
- * -- End of Copyright Notice --
-*/
-
-/*
- * Inlines are compiled as function when this is defined.
- * N.B. Must be placed before #include of "IxQMgr.h"
- */
-#ifndef IXQMGR_H
-#    define IXQMGRQACCESS_C
-#else
-#    error
-#endif
-
-/*
- * System defined include files.
- */
-
-/*
- * User defined include files.
- */
-#include "IxQMgr.h"
-#include "IxQMgrAqmIf_p.h"
-#include "IxQMgrQAccess_p.h"
-#include "IxQMgrQCfg_p.h"
-#include "IxQMgrDefines_p.h"
-
-/*
- * Global variables and extern definitions
- */
-extern IxQMgrQInlinedReadWriteInfo ixQMgrQInlinedReadWriteInfo[];
-
-/*
- * Function definitions.
- */
-void
-ixQMgrQAccessInit (void)
-{   
-}
-
-IX_STATUS
-ixQMgrQReadWithChecks (IxQMgrQId qId,
-                       UINT32 *entry)
-{
-    IxQMgrQEntrySizeInWords entrySizeInWords;
-    IxQMgrQInlinedReadWriteInfo *infoPtr;
-
-    if (NULL == entry)
-    {
-	return IX_QMGR_PARAMETER_ERROR;
-    }
-
-    /* Check QId */
-    if (!ixQMgrQIsConfigured(qId))
-    {
-	return IX_QMGR_Q_NOT_CONFIGURED;
-    }
-
-    /* Get the q entry size in words */
-    entrySizeInWords = ixQMgrQEntrySizeInWordsGet (qId);
-
-    ixQMgrAqmIfQPop (qId, entrySizeInWords, entry);	    
-
-    /* reset the current read count if the counter wrapped around 
-    * (unsigned arithmetic)
-    */
-    infoPtr = &ixQMgrQInlinedReadWriteInfo[qId];
-    if (infoPtr->qReadCount-- > infoPtr->qSizeInEntries)
-    {
-	infoPtr->qReadCount = 0;
-    }
-
-    /* Check if underflow occurred on the read */
-    if (ixQMgrAqmIfUnderflowCheck (qId))
-    {
-	return IX_QMGR_Q_UNDERFLOW;
-    }
-    
-    return IX_SUCCESS;
-}
-
-/* this function reads the remaining of the q entry
- * for queues configured with many words.
- * (the first word of the entry is already read 
- * in the inlined function and the entry pointer already
- * incremented
- */
-IX_STATUS
-ixQMgrQReadMWordsMinus1 (IxQMgrQId qId,
-			 UINT32 *entry)
-{
-    IxQMgrQInlinedReadWriteInfo *infoPtr = &ixQMgrQInlinedReadWriteInfo[qId];
-    UINT32 entrySize = infoPtr->qEntrySizeInWords;
-    volatile UINT32 *qAccRegAddr = infoPtr->qAccRegAddr;
-    
-    while (--entrySize)
-    {
-	/* read the entry and accumulate the result */
-	*(++entry) = IX_OSAL_READ_LONG(++qAccRegAddr);
-    }
-    /* underflow is available for lower queues only */
-    if (qId < IX_QMGR_MIN_QUEUPP_QID)
-    {
-	/* get the queue status */
-	UINT32 status = IX_OSAL_READ_LONG(infoPtr->qUOStatRegAddr);
-	
-	/* check the underflow status */
-	if (status & infoPtr->qUflowStatBitMask)
-	{
-	    /* the queue is empty 
-	     *  clear the underflow status bit if it was set 
-	     */
-	    IX_OSAL_WRITE_LONG(infoPtr->qUOStatRegAddr,
-				 status & ~infoPtr->qUflowStatBitMask);
-	    return IX_QMGR_Q_UNDERFLOW;
-	}
-    }
-    return IX_SUCCESS;
-}
-
-IX_STATUS
-ixQMgrQWriteWithChecks (IxQMgrQId qId,
-                        UINT32 *entry)
-{
-    IxQMgrQEntrySizeInWords entrySizeInWords;
-    IxQMgrQInlinedReadWriteInfo *infoPtr;
-
-    if (NULL == entry)
-    {
-	return IX_QMGR_PARAMETER_ERROR;
-    }
-
-    /* Check QId */
-    if (!ixQMgrQIsConfigured(qId))
-    {
-	return IX_QMGR_Q_NOT_CONFIGURED;
-    }
-
-    /* Get the q entry size in words */
-    entrySizeInWords = ixQMgrQEntrySizeInWordsGet (qId);
-    
-    ixQMgrAqmIfQPush (qId, entrySizeInWords, entry);
-
-    /* reset the current read count if the counter wrapped around 
-    * (unsigned arithmetic)
-    */
-    infoPtr = &ixQMgrQInlinedReadWriteInfo[qId];
-    if (infoPtr->qWriteCount++ >= infoPtr->qSizeInEntries)
-    {
-	infoPtr->qWriteCount = infoPtr->qSizeInEntries;
-    }
-
-    /* Check if overflow occurred on the write*/
-    if (ixQMgrAqmIfOverflowCheck (qId))
-    {
-	return IX_QMGR_Q_OVERFLOW;
-    }
-         
-    return IX_SUCCESS;
-}
-
-IX_STATUS
-ixQMgrQPeek (IxQMgrQId qId,
-	     unsigned int entryIndex,
-	     UINT32 *entry)
-{
-    unsigned int numEntries;
-
-#ifndef NDEBUG
-    if ((NULL == entry) || (entryIndex >= IX_QMGR_Q_SIZE_INVALID))
-    {
-	return IX_QMGR_PARAMETER_ERROR;
-    }
-
-    if (!ixQMgrQIsConfigured(qId))
-    {
-	return IX_QMGR_Q_NOT_CONFIGURED;
-    }
-#endif
-    
-    if (IX_SUCCESS != ixQMgrQNumEntriesGet (qId, &numEntries))
-    {
-	return IX_FAIL;
-    }
-
-    if (entryIndex >= numEntries) /* entryIndex starts at 0 */
-    {
-	return IX_QMGR_ENTRY_INDEX_OUT_OF_BOUNDS;
-    }
-
-    return ixQMgrAqmIfQPeek (qId, entryIndex, entry);
-}
-
-IX_STATUS
-ixQMgrQPoke (IxQMgrQId qId,
-	     unsigned entryIndex,
-	     UINT32 *entry)
-{
-    unsigned int numEntries;
-
-#ifndef NDEBUG
-    if ((NULL == entry) || (entryIndex > 128))
-    {
-	return IX_QMGR_PARAMETER_ERROR;
-    }
-
-    if (!ixQMgrQIsConfigured(qId))
-    {
-	return IX_QMGR_Q_NOT_CONFIGURED;
-    }
-#endif
-        
-    if (IX_SUCCESS != ixQMgrQNumEntriesGet (qId, &numEntries))
-    {
-	return IX_FAIL;
-    }
-
-    if (numEntries < (entryIndex + 1)) /* entryIndex starts at 0 */
-    {
-	return IX_QMGR_ENTRY_INDEX_OUT_OF_BOUNDS;
-    }
-
-    return ixQMgrAqmIfQPoke (qId, entryIndex, entry);
-}
-
-IX_STATUS
-ixQMgrQStatusGetWithChecks (IxQMgrQId qId,
-                            IxQMgrQStatus *qStatus)
-{
-    if (NULL == qStatus)
-    {
-	return IX_QMGR_PARAMETER_ERROR;
-    }
-   
-    if (!ixQMgrQIsConfigured (qId)) 
-    {
-        return IX_QMGR_Q_NOT_CONFIGURED;
-    }
-
-    ixQMgrAqmIfQueStatRead (qId, qStatus);
-
-    return IX_SUCCESS;
-}
-
-IX_STATUS
-ixQMgrQNumEntriesGet (IxQMgrQId qId,
-		      unsigned *numEntriesPtr)
-{
-    UINT32 qPtrs;
-    UINT32 qStatus;
-    unsigned numEntries;
-    IxQMgrQInlinedReadWriteInfo *infoPtr;
-
-
-#ifndef NDEBUG
-    if (NULL == numEntriesPtr)
-    {
-	return IX_QMGR_PARAMETER_ERROR;
-    }
-
-    /* Check QId */
-    if (!ixQMgrQIsConfigured(qId))
-    {
-	return IX_QMGR_Q_NOT_CONFIGURED;
-    }
-#endif
-
-    /* get fast access data */
-    infoPtr = &ixQMgrQInlinedReadWriteInfo[qId];
-
-    /* get snapshot */
-    qPtrs = IX_OSAL_READ_LONG(infoPtr->qConfigRegAddr);
-
-    /* Mod subtraction of pointers to get number of words in Q. */
-    numEntries = (qPtrs - (qPtrs >> 7)) & 0x7f;
-  
-    if (numEntries == 0)
-    {
-	/* 
-	 * Could mean either full or empty queue
-	 * so look at status
-	 */
-	ixQMgrAqmIfQueStatRead (qId, &qStatus);
-
-	if (qId < IX_QMGR_MIN_QUEUPP_QID)
-	{
-	    if (qStatus & IX_QMGR_Q_STATUS_E_BIT_MASK)
-	    {
-		/* Empty */
-		*numEntriesPtr = 0;
-	    }
-	    else if (qStatus & IX_QMGR_Q_STATUS_F_BIT_MASK)
-	    {
-		/* Full */
-		*numEntriesPtr = infoPtr->qSizeInEntries;
-	    }
-	    else
-	    {	    
-		/* 
-		 * Queue status and read/write pointers are volatile.
-		 * The queue state has changed since we took the
-		 * snapshot of the read and write pointers.
-		 * Client can retry if they wish
-		 */
-		*numEntriesPtr = 0;
-		return IX_QMGR_WARNING;
-	    }
-	}
-	else /* It is an upper queue which does not have an empty status bit maintained */
-	{
-	    if (qStatus & IX_QMGR_Q_STATUS_F_BIT_MASK)
-	    {
-		/* The queue is Full at the time of snapshot. */
-		*numEntriesPtr = infoPtr->qSizeInEntries;
-	    }
-	    else
-	    {
-	       /* The queue is either empty, either moving,
-	        * Client can retry if they wish
-	        */
-		*numEntriesPtr = 0;
-	        return IX_QMGR_WARNING;
-	    }
-	}
-    }
-    else
-    {
-	*numEntriesPtr = (numEntries / infoPtr->qEntrySizeInWords) & (infoPtr->qSizeInEntries - 1);
-    }
-    
-    return IX_SUCCESS;
-}
-
-#if defined(__wince) && defined(NO_INLINE_APIS)
-
-PUBLIC IX_STATUS
-ixQMgrQRead (IxQMgrQId qId,
-      UINT32 *entryPtr)
-{
-    extern IxQMgrQInlinedReadWriteInfo ixQMgrQInlinedReadWriteInfo[];
-    IxQMgrQInlinedReadWriteInfo *infoPtr = &ixQMgrQInlinedReadWriteInfo[qId];
-    UINT32 entry, entrySize;
-
-    /* get a new entry */
-    entrySize = infoPtr->qEntrySizeInWords;
-    entry = IX_OSAL_READ_LONG(infoPtr->qAccRegAddr);
-
-    if (entrySize != IX_QMGR_Q_ENTRY_SIZE1)
-    { 
-    *entryPtr = entry;
-  /* process the remaining part of the entry */
-   return ixQMgrQReadMWordsMinus1(qId, entryPtr);
-    }
-
-    /* underflow is available for lower queues only */
-    if (qId < IX_QMGR_MIN_QUEUPP_QID)
-    {
- /* the counter of queue entries is decremented. In happy 
-    * day scenario there are many entries in the queue
-  * and the counter does not reach zero.
-  */
-     if (infoPtr->qReadCount-- == 0)
- {
-       /* There is maybe no entry in the queue
-      * qReadCount is now negative, but will be corrected before
-      * the function returns.
-         */
-     UINT32 qPtrs; /* queue internal pointers */
-
-     /* when a queue is empty, the hw guarantees to return 
-       * a null value. If the value is not null, the queue is
-      * not empty.
-        */
-     if (entry == 0)
-     {
-       /* get the queue status */
-      UINT32 status = IX_OSAL_READ_LONG(infoPtr->qUOStatRegAddr);
-   
-        /* check the underflow status */
-        if (status & infoPtr->qUflowStatBitMask)
-        {
-           /* the queue is empty 
-          *  clear the underflow status bit if it was set 
-            */
-          IX_OSAL_WRITE_LONG(infoPtr->qUOStatRegAddr,
-                    status & ~infoPtr->qUflowStatBitMask);
-         *entryPtr = 0;
-          infoPtr->qReadCount = 0;
-            return IX_QMGR_Q_UNDERFLOW;
-     }
-       }
-       /* store the result */
-      *entryPtr = entry;
-
-      /* No underflow occured : someone is filling the queue
-       * or the queue contains null entries.
-       * The current counter needs to be
-       * updated from the current number of entries in the queue
-       */
-
-     /* get snapshot of queue pointers */
-        qPtrs = IX_OSAL_READ_LONG(infoPtr->qConfigRegAddr);
-
-       /* Mod subtraction of pointers to get number of words in Q. */
-      qPtrs = (qPtrs - (qPtrs >> 7)) & 0x7f; 
-  
-       if (qPtrs == 0)
-     {
-       /* no entry in the queue */
-     infoPtr->qReadCount = 0;
-        }
-       else
-        {
-       /* convert the number of words inside the queue
-      * to a number of entries 
-       */
-     infoPtr->qReadCount = qPtrs & (infoPtr->qSizeInEntries - 1);
-        }
-       return IX_SUCCESS;
-  }
-    }
-    *entryPtr = entry;
-    return IX_SUCCESS;
-}
-
-PUBLIC IX_STATUS
-ixQMgrQBurstRead (IxQMgrQId qId,
-          UINT32 numEntries,
-          UINT32 *entries)
-{
-    extern IxQMgrQInlinedReadWriteInfo ixQMgrQInlinedReadWriteInfo[];
-    IxQMgrQInlinedReadWriteInfo *infoPtr = &ixQMgrQInlinedReadWriteInfo[qId];
-    UINT32 nullCheckEntry;
-
-    if (infoPtr->qEntrySizeInWords == IX_QMGR_Q_ENTRY_SIZE1)
-    {
-    volatile UINT32 *qAccRegAddr = infoPtr->qAccRegAddr;
-
-    /* the code is optimized to take care of data dependencies:
-  * Durig a read, there are a few cycles needed to get the 
-   * read complete. During these cycles, it is poossible to
-    * do some CPU, e.g. increment pointers and decrement 
-   * counters.
-     */
-
- /* fetch a queue entry */
-   nullCheckEntry = IX_OSAL_READ_LONG(infoPtr->qAccRegAddr);
-
- /* iterate the specified number of queue entries */ 
-    while (--numEntries)
-    {
-       /* check the result of the previous read */
-     if (nullCheckEntry == 0)
-        {
-       /* if we read a NULL entry, stop. We have underflowed */
-        break;
-      }
-       else
-        {
-       /* write the entry */
-       *entries = nullCheckEntry;
-      /* fetch next entry */
-      nullCheckEntry = IX_OSAL_READ_LONG(qAccRegAddr);
-      /* increment the write address */
-       entries++;
-      }
-   }
-   /* write the pre-fetched entry */
-   *entries = nullCheckEntry;
-    }
-    else
-    {
-    IxQMgrQEntrySizeInWords entrySizeInWords = infoPtr->qEntrySizeInWords;
-  /* read the specified number of queue entries */
-    nullCheckEntry = 0;
- while (numEntries--)
-    {
-       int i;
-
-      for (i = 0; i < entrySizeInWords; i++)
-      {
-       *entries = IX_OSAL_READ_LONG(infoPtr->qAccRegAddr + i);
-       nullCheckEntry |= *entries++;
-       }
-
-       /* if we read a NULL entry, stop. We have underflowed */
-        if (nullCheckEntry == 0)
-        {
-       break;
-      }
-       nullCheckEntry = 0;
- }
-    }
-
-    /* reset the current read count : next access to the read function 
-     * will force a underflow status check 
-     */
-    infoPtr->qWriteCount = 0;
-
-    /* Check if underflow occurred on the read */
-    if (nullCheckEntry == 0 && qId < IX_QMGR_MIN_QUEUPP_QID)
-    {
-  /* get the queue status */
-  UINT32 status = IX_OSAL_READ_LONG(infoPtr->qUOStatRegAddr);
-
-   if (status & infoPtr->qUflowStatBitMask)
-    {
-       /* clear the underflow status bit if it was set */
-      IX_OSAL_WRITE_LONG(infoPtr->qUOStatRegAddr,
-                status & ~infoPtr->qUflowStatBitMask);
-     return IX_QMGR_Q_UNDERFLOW;
- }
-    }
-
-    return IX_SUCCESS;
-}
-
-PUBLIC IX_STATUS
-ixQMgrQWrite (IxQMgrQId qId,
-         UINT32 *entry)
-{
-    extern IxQMgrQInlinedReadWriteInfo ixQMgrQInlinedReadWriteInfo[];
-    IxQMgrQInlinedReadWriteInfo *infoPtr = &ixQMgrQInlinedReadWriteInfo[qId];
-    UINT32 entrySize;
-
-    /* write the entry */
-    IX_OSAL_WRITE_LONG(infoPtr->qAccRegAddr, *entry);
-    entrySize = infoPtr->qEntrySizeInWords;
-
-    if (entrySize != IX_QMGR_Q_ENTRY_SIZE1)
-    {   
-    /* process the remaining part of the entry */
-   volatile UINT32 *qAccRegAddr = infoPtr->qAccRegAddr;
-    while (--entrySize)
- {
-       ++entry;
-        IX_OSAL_WRITE_LONG(++qAccRegAddr, *entry);
-    }
-   entrySize = infoPtr->qEntrySizeInWords;
-    }
-
-    /* overflow is available for lower queues only */
-    if (qId < IX_QMGR_MIN_QUEUPP_QID)
-    {   
-  UINT32 qSize = infoPtr->qSizeInEntries;
- /* increment the current number of entries in the queue
-  * and check for overflow 
-   */
- if (infoPtr->qWriteCount++ == qSize)
-    {
-       /* the queue may have overflow */
-       UINT32 qPtrs; /* queue internal pointers */
-  
-       /* get the queue status */
-      UINT32 status = IX_OSAL_READ_LONG(infoPtr->qUOStatRegAddr);
-
-       /* read the status twice because the status may 
-         * not be immediately ready after the write operation
-        */
-     if ((status & infoPtr->qOflowStatBitMask) ||
-        ((status = IX_OSAL_READ_LONG(infoPtr->qUOStatRegAddr))
-         & infoPtr->qOflowStatBitMask))
-     {
-       /* the queue is full, clear the overflow status
-      *  bit if it was set 
-       */
-     IX_OSAL_WRITE_LONG(infoPtr->qUOStatRegAddr,
-                    status & ~infoPtr->qOflowStatBitMask);
-     infoPtr->qWriteCount = infoPtr->qSizeInEntries;
-     return IX_QMGR_Q_OVERFLOW;
-      }
-       /* No overflow occured : someone is draining the queue
-       * and the current counter needs to be
-       * updated from the current number of entries in the queue
-       */
-
-     /* get q pointer snapshot */
-        qPtrs = IX_OSAL_READ_LONG(infoPtr->qConfigRegAddr);
-
-       /* Mod subtraction of pointers to get number of words in Q. */
-      qPtrs = (qPtrs - (qPtrs >> 7)) & 0x7f; 
-
-     if (qPtrs == 0)
-     {
-       /* the queue may be full at the time of the 
-         * snapshot. Next access will check 
-         * the overflow status again.
-        */
-     infoPtr->qWriteCount = qSize;
-       }
-       else 
-       {
-       /* convert the number of words to a number of entries */
-        if (entrySize == IX_QMGR_Q_ENTRY_SIZE1)
-     {
-           infoPtr->qWriteCount = qPtrs & (qSize - 1);
-     }
-       else
-        {
-           infoPtr->qWriteCount = (qPtrs / entrySize) & (qSize - 1);
-       }
-       }
-   }
-    }
-    return IX_SUCCESS;
-}
-
-PUBLIC IX_STATUS
-ixQMgrQBurstWrite (IxQMgrQId qId,
-          unsigned numEntries,
-        UINT32 *entries)
-{
-    extern IxQMgrQInlinedReadWriteInfo ixQMgrQInlinedReadWriteInfo[];
-    IxQMgrQInlinedReadWriteInfo *infoPtr = &ixQMgrQInlinedReadWriteInfo[qId];
-    UINT32 status;
-
-    /* update the current write count */
-    infoPtr->qWriteCount += numEntries;
-
-    if (infoPtr->qEntrySizeInWords == IX_QMGR_Q_ENTRY_SIZE1)
-    {
-    volatile UINT32 *qAccRegAddr = infoPtr->qAccRegAddr;
-    while (numEntries--)
-    {
-       IX_OSAL_WRITE_LONG(qAccRegAddr, *entries);
-        entries++;
-  }
-    }
-    else
-    {
- IxQMgrQEntrySizeInWords entrySizeInWords = infoPtr->qEntrySizeInWords;
-  int i;
-
-  /* write each queue entry */
-    while (numEntries--)
-    {
-       /* write the queueEntrySize number of words for each entry */
-       for (i = 0; i < entrySizeInWords; i++)
-      {
-       IX_OSAL_WRITE_LONG((infoPtr->qAccRegAddr + i), *entries);
-     entries++;
-      }
-   }
-    }
-
-    /* check if the write count overflows */
-    if (infoPtr->qWriteCount > infoPtr->qSizeInEntries)
-    {
-  /* reset the current write count */
- infoPtr->qWriteCount = infoPtr->qSizeInEntries;
-    }
-
-    /* Check if overflow occurred on the write operation */
-    if (qId < IX_QMGR_MIN_QUEUPP_QID)
-    {
-   /* get the queue status */
-  status = IX_OSAL_READ_LONG(infoPtr->qUOStatRegAddr);
-
-  /* read the status twice because the status may 
-     * not be ready at the time of the write
-     */
- if ((status & infoPtr->qOflowStatBitMask) ||
-        ((status = IX_OSAL_READ_LONG(infoPtr->qUOStatRegAddr))
-         & infoPtr->qOflowStatBitMask))
- {
-       /* clear the underflow status bit if it was set */
-      IX_OSAL_WRITE_LONG(infoPtr->qUOStatRegAddr,
-                status & ~infoPtr->qOflowStatBitMask);
-     return IX_QMGR_Q_OVERFLOW;
-  }
-    }
-
-    return IX_SUCCESS;
-}
-
-PUBLIC IX_STATUS
-ixQMgrQStatusGet (IxQMgrQId qId,
-          IxQMgrQStatus *qStatus)
-{
-    /* read the status of a queue in the range 0-31 */
-    if (qId < IX_QMGR_MIN_QUEUPP_QID)
-    {
-  extern UINT32 ixQMgrAqmIfQueLowStatRegAddr[];
-   extern UINT32 ixQMgrAqmIfQueLowStatBitsOffset[];
-    extern UINT32 ixQMgrAqmIfQueLowStatBitsMask;
-    extern IxQMgrQInlinedReadWriteInfo ixQMgrQInlinedReadWriteInfo[];
-    IxQMgrQInlinedReadWriteInfo *infoPtr = &ixQMgrQInlinedReadWriteInfo[qId];
-   volatile UINT32 *lowStatRegAddr = (UINT32*)ixQMgrAqmIfQueLowStatRegAddr[qId];
-   volatile UINT32 *qUOStatRegAddr = infoPtr->qUOStatRegAddr;
-
-  UINT32 lowStatBitsOffset = ixQMgrAqmIfQueLowStatBitsOffset[qId];
-    UINT32 lowStatBitsMask   = ixQMgrAqmIfQueLowStatBitsMask;
-   UINT32 underflowBitMask  = infoPtr->qUflowStatBitMask;
-  UINT32 overflowBitMask   = infoPtr->qOflowStatBitMask;
-
-  /* read the status register for this queue */
-   *qStatus = IX_OSAL_READ_LONG(lowStatRegAddr);
- /* mask out the status bits relevant only to this queue */
-  *qStatus = (*qStatus >> lowStatBitsOffset) & lowStatBitsMask;
-
-   /* Check if the queue has overflowed */
- if (IX_OSAL_READ_LONG(qUOStatRegAddr) & overflowBitMask)
-  {
-       /* clear the overflow status bit if it was set */
-       IX_OSAL_WRITE_LONG(qUOStatRegAddr,
-                 (IX_OSAL_READ_LONG(qUOStatRegAddr) &
-               ~overflowBitMask));
-       *qStatus |= IX_QMGR_Q_STATUS_OF_BIT_MASK;
-   }
-
-   /* Check if the queue has underflowed */
-        if (IX_OSAL_READ_LONG(qUOStatRegAddr) & underflowBitMask)
- {
-       /* clear the underflow status bit if it was set */
-      IX_OSAL_WRITE_LONG(qUOStatRegAddr,
-                 (IX_OSAL_READ_LONG(qUOStatRegAddr) &
-               ~underflowBitMask));
-      *qStatus |= IX_QMGR_Q_STATUS_UF_BIT_MASK;
-   }
-    }
-    else /* read status of a queue in the range 32-63 */
-    {
- extern UINT32 ixQMgrAqmIfQueUppStat0RegAddr;
-    extern UINT32 ixQMgrAqmIfQueUppStat1RegAddr;
-    extern UINT32 ixQMgrAqmIfQueUppStat0BitMask[];
-  extern UINT32 ixQMgrAqmIfQueUppStat1BitMask[];
-
-  volatile UINT32 *qNearEmptyStatRegAddr = (UINT32*)ixQMgrAqmIfQueUppStat0RegAddr;
-    volatile UINT32 *qFullStatRegAddr      = (UINT32*)ixQMgrAqmIfQueUppStat1RegAddr;
-    int maskIndex = qId - IX_QMGR_MIN_QUEUPP_QID;
-   UINT32 qNearEmptyStatBitMask = ixQMgrAqmIfQueUppStat0BitMask[maskIndex];
-    UINT32 qFullStatBitMask      = ixQMgrAqmIfQueUppStat1BitMask[maskIndex];
-
-    /* Reset the status bits */
- *qStatus = 0;
-
-   /* Check if the queue is nearly empty */
-    if (IX_OSAL_READ_LONG(qNearEmptyStatRegAddr) & qNearEmptyStatBitMask)
- {
-       *qStatus |= IX_QMGR_Q_STATUS_NE_BIT_MASK;
-   }
-
-   /* Check if the queue is full */
-    if (IX_OSAL_READ_LONG(qFullStatRegAddr) & qFullStatBitMask)
-   {
-       *qStatus |= IX_QMGR_Q_STATUS_F_BIT_MASK;
-    }
-    }
-    return IX_SUCCESS;
-}
-#endif /* def NO_INLINE_APIS */
diff --git a/arch/arm/cpu/ixp/npe/IxQMgrQCfg.c b/arch/arm/cpu/ixp/npe/IxQMgrQCfg.c
deleted file mode 100644
index ec7d837..0000000
--- a/arch/arm/cpu/ixp/npe/IxQMgrQCfg.c
+++ /dev/null
@@ -1,543 +0,0 @@
-/**
- * @file    QMgrQCfg.c
- *
- * @author Intel Corporation
- * @date    30-Oct-2001
- * 
- * @brief   This modules provides an interface for setting up the static
- * configuration of AQM queues.This file contains the following
- * functions:
- *
- * 
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- * 
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- * 
- * @par
- * -- End of Copyright Notice --
-*/
-
-/*
- * System defined include files.
- */
-
-/*
- * User defined include files.
- */
-#include "IxOsal.h"
-#include "IxQMgr.h"
-#include "IxQMgrAqmIf_p.h"
-#include "IxQMgrQCfg_p.h"
-#include "IxQMgrDefines_p.h"
-
-/*
- * #defines and macros used in this file.
- */
-
-#define IX_QMGR_MIN_ENTRY_SIZE_IN_WORDS 16
-
-/* Total size of SRAM */
-#define IX_QMGR_AQM_SRAM_SIZE_IN_BYTES 0x4000
-
-/*
- * Check that qId is a valid queue identifier. This is provided to
- * make the code easier to read.
- */
-#define IX_QMGR_QID_IS_VALID(qId) \
-(((qId) >= (IX_QMGR_MIN_QID)) && ((qId) <= (IX_QMGR_MAX_QID)))
-
-/*
- * Typedefs whose scope is limited to this file.
- */
-
-/*
- * This struct describes an AQM queue.
- * N.b. bufferSizeInWords and qEntrySizeInWords are stored in the queue
- * as these are requested by Access in the data path. sizeInEntries is
- * not required by the data path so it can be calculated dynamically.
- * 
- */
-typedef struct
-{
-    char qName[IX_QMGR_MAX_QNAME_LEN+1];       /* Textual description of a queue*/
-    IxQMgrQSizeInWords qSizeInWords;           /* The number of words in the queue */
-    IxQMgrQEntrySizeInWords qEntrySizeInWords; /* Number of words per queue entry*/
-    BOOL isConfigured;                         /* This flag is TRUE if the queue has
-                                                *   been configured
-                                                */
-} IxQMgrCfgQ;
-
-/*
- * Variable declarations global to this file. Externs are followed by
- * statics.
- */
-
-extern UINT32 * ixQMgrAqmIfQueAccRegAddr[]; 
-
-/* Store data required to inline read and write access
- */
-IxQMgrQInlinedReadWriteInfo ixQMgrQInlinedReadWriteInfo[IX_QMGR_MAX_NUM_QUEUES];
-
-static IxQMgrCfgQ cfgQueueInfo[IX_QMGR_MAX_NUM_QUEUES];
-
-/* This pointer holds the starting address of AQM SRAM not used by
- * the AQM queues.
- */
-static UINT32 freeSramAddress=0;
-
-/* 4 words of zeroed memory for inline access */
-static UINT32 zeroedPlaceHolder[4] = { 0, 0, 0, 0 };
-
-static BOOL cfgInitialized = FALSE;
-
-static IxOsalMutex ixQMgrQCfgMutex;
-
-/*
- * Statistics
- */
-static IxQMgrQCfgStats stats;
-
-/*
- * Function declarations
- */
-PRIVATE BOOL
-watermarkLevelIsOk (IxQMgrQId qId, IxQMgrWMLevel level);
-
-PRIVATE BOOL
-qSizeInWordsIsOk (IxQMgrQSizeInWords qSize);
-
-PRIVATE BOOL
-qEntrySizeInWordsIsOk (IxQMgrQEntrySizeInWords entrySize);
-
-/*
- * Function definitions.
- */
-void
-ixQMgrQCfgInit (void)
-{
-    int loopIndex;
-    
-    for (loopIndex=0; loopIndex < IX_QMGR_MAX_NUM_QUEUES;loopIndex++)
-    {
-	/* info for code inlining */
-	ixQMgrAqmIfQueAccRegAddr[loopIndex] = zeroedPlaceHolder;
-
-	/* info for code inlining */
-	ixQMgrQInlinedReadWriteInfo[loopIndex].qReadCount = 0;
-	ixQMgrQInlinedReadWriteInfo[loopIndex].qWriteCount = 0;
-	ixQMgrQInlinedReadWriteInfo[loopIndex].qAccRegAddr = zeroedPlaceHolder;
-	ixQMgrQInlinedReadWriteInfo[loopIndex].qUOStatRegAddr = zeroedPlaceHolder;
-	ixQMgrQInlinedReadWriteInfo[loopIndex].qUflowStatBitMask = 0;
-	ixQMgrQInlinedReadWriteInfo[loopIndex].qOflowStatBitMask = 0;
-	ixQMgrQInlinedReadWriteInfo[loopIndex].qEntrySizeInWords = 0;
-	ixQMgrQInlinedReadWriteInfo[loopIndex].qSizeInEntries = 0;
-	ixQMgrQInlinedReadWriteInfo[loopIndex].qConfigRegAddr = zeroedPlaceHolder;
-   }
-
-    /* Initialise the AqmIf component */
-    ixQMgrAqmIfInit ();
-   
-    /* Reset all queues to have queue name = NULL, entry size = 0 and
-     * isConfigured = false
-     */
-    for (loopIndex=0; loopIndex < IX_QMGR_MAX_NUM_QUEUES;loopIndex++)
-    {
-	strcpy (cfgQueueInfo[loopIndex].qName, "");
-	cfgQueueInfo[loopIndex].qSizeInWords = 0;
-	cfgQueueInfo[loopIndex].qEntrySizeInWords = 0;
-	cfgQueueInfo[loopIndex].isConfigured = FALSE;
-
-	/* Statistics */
-	stats.qStats[loopIndex].isConfigured = FALSE;
-	stats.qStats[loopIndex].qName = cfgQueueInfo[loopIndex].qName;
-    }
-
-    /* Statistics */
-    stats.wmSetCnt = 0;
-
-    ixQMgrAqmIfSramBaseAddressGet (&freeSramAddress);
-    
-    ixOsalMutexInit(&ixQMgrQCfgMutex);
-
-    cfgInitialized = TRUE;
-}
-
-void
-ixQMgrQCfgUninit (void)
-{
-    cfgInitialized = FALSE;
-
-    /* Uninitialise the AqmIf component */
-    ixQMgrAqmIfUninit ();
-}
-
-IX_STATUS
-ixQMgrQConfig (char *qName,
-	      IxQMgrQId qId,
-	      IxQMgrQSizeInWords qSizeInWords,
-	      IxQMgrQEntrySizeInWords qEntrySizeInWords)
-{
-    UINT32 aqmLocalBaseAddress;
-
-    if (!cfgInitialized)
-    {
-        return IX_FAIL;
-    }
-    
-    if (!IX_QMGR_QID_IS_VALID(qId))
-    {
-	return IX_QMGR_INVALID_Q_ID;
-    }
-    
-    else if (NULL == qName)
-    {
-	return IX_QMGR_PARAMETER_ERROR;
-    }
-    
-    else if (strlen (qName) > IX_QMGR_MAX_QNAME_LEN)
-    {
-	return IX_QMGR_PARAMETER_ERROR;
-    }
-
-    else if (!qSizeInWordsIsOk (qSizeInWords))
-    {
-	return IX_QMGR_INVALID_QSIZE;
-    }
-
-    else if (!qEntrySizeInWordsIsOk (qEntrySizeInWords))
-    {
-	return IX_QMGR_INVALID_Q_ENTRY_SIZE;
-    }
-    
-    else if (cfgQueueInfo[qId].isConfigured)
-    {
-	return IX_QMGR_Q_ALREADY_CONFIGURED;
-    }
-   
-    ixOsalMutexLock(&ixQMgrQCfgMutex, IX_OSAL_WAIT_FOREVER);
-
-    /* Write the config register */
-    ixQMgrAqmIfQueCfgWrite (qId,
-			   qSizeInWords,
-			   qEntrySizeInWords,
-			   freeSramAddress);
-
-
-    strcpy (cfgQueueInfo[qId].qName, qName);
-    cfgQueueInfo[qId].qSizeInWords = qSizeInWords;
-    cfgQueueInfo[qId].qEntrySizeInWords = qEntrySizeInWords;
-
-    /* store pre-computed information in the same cache line
-     * to facilitate inlining of QRead and QWrite functions 
-     * in IxQMgr.h
-     */
-    ixQMgrQInlinedReadWriteInfo[qId].qReadCount = 0;
-    ixQMgrQInlinedReadWriteInfo[qId].qWriteCount = 0;
-    ixQMgrQInlinedReadWriteInfo[qId].qEntrySizeInWords = qEntrySizeInWords;
-    ixQMgrQInlinedReadWriteInfo[qId].qSizeInEntries = 
-		(UINT32)qSizeInWords / (UINT32)qEntrySizeInWords;
-
-    /* Calculate the new freeSramAddress from the size of the queue
-     * currently being configured.
-     */
-    freeSramAddress += (qSizeInWords * IX_QMGR_NUM_BYTES_PER_WORD);
-
-    /* Get the virtual SRAM address */
-    ixQMgrAqmIfBaseAddressGet (&aqmLocalBaseAddress);
-
-    IX_OSAL_ASSERT((freeSramAddress - (aqmLocalBaseAddress + (IX_QMGR_QUEBUFFER_SPACE_OFFSET))) <=
-	      IX_QMGR_QUE_BUFFER_SPACE_SIZE);
-
-    /* The queue is now configured */
-    cfgQueueInfo[qId].isConfigured = TRUE;
-
-    ixOsalMutexUnlock(&ixQMgrQCfgMutex);
-
-#ifndef NDEBUG
-    /* Update statistics */
-    stats.qStats[qId].isConfigured = TRUE;
-    stats.qStats[qId].qName = cfgQueueInfo[qId].qName;
-#endif
-    return IX_SUCCESS;
-}
-
-IxQMgrQSizeInWords
-ixQMgrQSizeInWordsGet (IxQMgrQId qId)
-{
-    /* No parameter checking as this is used on the data path */
-    return (cfgQueueInfo[qId].qSizeInWords);
-}
-
-IX_STATUS
-ixQMgrQSizeInEntriesGet (IxQMgrQId qId,
-			 unsigned *qSizeInEntries)
-{
-    if (!ixQMgrQIsConfigured(qId))
-    {
-        return IX_QMGR_Q_NOT_CONFIGURED;
-    }
-
-    if(NULL == qSizeInEntries)
-    {
-        return IX_QMGR_PARAMETER_ERROR;
-    }
-
-    *qSizeInEntries = (UINT32)(cfgQueueInfo[qId].qSizeInWords) /
-        (UINT32)cfgQueueInfo[qId].qEntrySizeInWords;
-
-    return IX_SUCCESS;
-}
-
-IxQMgrQEntrySizeInWords
-ixQMgrQEntrySizeInWordsGet (IxQMgrQId qId)
-{
-    /* No parameter checking as this is used on the data path */
-    return (cfgQueueInfo[qId].qEntrySizeInWords);
-}
-
-IX_STATUS
-ixQMgrWatermarkSet (IxQMgrQId qId,
-		    IxQMgrWMLevel ne,
-		    IxQMgrWMLevel nf)
-{    
-    IxQMgrQStatus qStatusOnEntry;/* The queue status on entry/exit */
-    IxQMgrQStatus qStatusOnExit; /* to this function               */
-
-    if (!ixQMgrQIsConfigured(qId))
-    {
-        return IX_QMGR_Q_NOT_CONFIGURED;
-    }
-
-    if (!watermarkLevelIsOk (qId, ne))
-    {
-	return IX_QMGR_INVALID_Q_WM;
-    }
-
-    if (!watermarkLevelIsOk (qId, nf))
-    {
-	return IX_QMGR_INVALID_Q_WM;
-    }
-
-    /* Get the current queue status */
-    ixQMgrAqmIfQueStatRead (qId, &qStatusOnEntry);
-
-#ifndef NDEBUG
-    /* Update statistics */
-    stats.wmSetCnt++;
-#endif
-
-    ixQMgrAqmIfWatermarkSet (qId,
-			    ne,
-			    nf);
-
-    /* Get the current queue status */
-    ixQMgrAqmIfQueStatRead (qId, &qStatusOnExit);
-  
-    /* If the status has changed return a warning */
-    if (qStatusOnEntry != qStatusOnExit)
-    {
-	return IX_QMGR_WARNING;
-    }
-
-    return IX_SUCCESS;
-}
-
-IX_STATUS
-ixQMgrAvailableSramAddressGet (UINT32 *address,
-			      unsigned *sizeOfFreeRam)
-{
-    UINT32 aqmLocalBaseAddress;
-
-    if ((NULL == address)||(NULL == sizeOfFreeRam)) 
-    {
-	return IX_QMGR_PARAMETER_ERROR;
-    }
-    if (!cfgInitialized)
-    {
-	return IX_FAIL;
-    }
-
-    *address = freeSramAddress;
-
-    /* Get the virtual SRAM address */
-    ixQMgrAqmIfBaseAddressGet (&aqmLocalBaseAddress);
-
-    /* 
-     * Calculate the size in bytes of free sram 
-     * i.e. current free SRAM virtual pointer from
-     *      (base + total size)
-     */
-    *sizeOfFreeRam = 
-	(aqmLocalBaseAddress +
-	IX_QMGR_AQM_SRAM_SIZE_IN_BYTES) -
-	freeSramAddress;
-
-    if (0 == *sizeOfFreeRam)
-    {
-	return IX_QMGR_NO_AVAILABLE_SRAM;
-    }
-
-    return IX_SUCCESS;
-}
-
-BOOL
-ixQMgrQIsConfigured (IxQMgrQId qId)
-{
-    if (!IX_QMGR_QID_IS_VALID(qId))
-    {
-	return FALSE;
-    }
-
-    return cfgQueueInfo[qId].isConfigured;
-}
-
-IxQMgrQCfgStats*
-ixQMgrQCfgStatsGet (void)
-{
-    return &stats;
-}
-
-IxQMgrQCfgStats*
-ixQMgrQCfgQStatsGet (IxQMgrQId qId)
-{
-    unsigned int ne;
-    unsigned int nf;
-    UINT32 baseAddress;
-    UINT32 readPtr;
-    UINT32 writePtr;
-
-    stats.qStats[qId].qSizeInWords = cfgQueueInfo[qId].qSizeInWords;
-    stats.qStats[qId].qEntrySizeInWords = cfgQueueInfo[qId].qEntrySizeInWords;
-    
-    if (IX_SUCCESS != ixQMgrQNumEntriesGet (qId, &stats.qStats[qId].numEntries))
-    {
-        if (IX_QMGR_WARNING != ixQMgrQNumEntriesGet (qId, &stats.qStats[qId].numEntries))
-        {
-	   IX_QMGR_LOG_WARNING1("Failed to get the number of entries in queue.... %d\n", qId);
-        }
-    }
-
-    ixQMgrAqmIfQueCfgRead (qId,
-			   stats.qStats[qId].numEntries,
-			   &baseAddress,
-			   &ne,
-			   &nf,
-			   &readPtr,
-			   &writePtr);
-        
-    stats.qStats[qId].baseAddress = baseAddress;
-    stats.qStats[qId].ne = ne;
-    stats.qStats[qId].nf = nf;
-    stats.qStats[qId].readPtr = readPtr;
-    stats.qStats[qId].writePtr = writePtr;
-
-    return &stats;
-}
-
-/* 
- * Static function definitions
- */
-
-PRIVATE BOOL
-watermarkLevelIsOk (IxQMgrQId qId, IxQMgrWMLevel level)
-{
-    unsigned qSizeInEntries;
-
-    switch (level)
-    {
-	case IX_QMGR_Q_WM_LEVEL0: 
-	case IX_QMGR_Q_WM_LEVEL1: 
-	case IX_QMGR_Q_WM_LEVEL2: 
-	case IX_QMGR_Q_WM_LEVEL4: 
-	case IX_QMGR_Q_WM_LEVEL8: 
-	case IX_QMGR_Q_WM_LEVEL16:
-	case IX_QMGR_Q_WM_LEVEL32:
-	case IX_QMGR_Q_WM_LEVEL64:
-	    break;
-	default:
-	    return FALSE;
-    }
-
-    /* Check watermark is not bigger than the qSizeInEntries */
-    ixQMgrQSizeInEntriesGet(qId, &qSizeInEntries);
-
-    if ((unsigned)level > qSizeInEntries)
-    {
-	return FALSE;
-    }
-
-    return TRUE;
-}
-
-PRIVATE BOOL
-qSizeInWordsIsOk (IxQMgrQSizeInWords qSize)
-{
-    BOOL status;
-
-    switch (qSize)
-    {	
-	case IX_QMGR_Q_SIZE16:
-	case IX_QMGR_Q_SIZE32:
-	case IX_QMGR_Q_SIZE64:
-	case IX_QMGR_Q_SIZE128:
-	    status = TRUE;
-	    break;
-	default:
-	    status = FALSE;
-	    break;
-    }
-
-    return status;
-}
-
-PRIVATE BOOL
-qEntrySizeInWordsIsOk (IxQMgrQEntrySizeInWords entrySize)
-{
-    BOOL status;
-
-    switch (entrySize)
-    {
-	case IX_QMGR_Q_ENTRY_SIZE1:
-	case IX_QMGR_Q_ENTRY_SIZE2:
-	case IX_QMGR_Q_ENTRY_SIZE4:
-	    status = TRUE;
-	    break;
-	default:
-	    status = FALSE;
-	    break;
-    }
-
-    return status;
-}
diff --git a/arch/arm/cpu/ixp/npe/Makefile b/arch/arm/cpu/ixp/npe/Makefile
deleted file mode 100644
index c756a1d..0000000
--- a/arch/arm/cpu/ixp/npe/Makefile
+++ /dev/null
@@ -1,98 +0,0 @@
-#
-# (C) Copyright 2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB := $(obj)libnpe.o
-
-LOCAL_CFLAGS  += -I$(TOPDIR)/arch/arm/cpu/ixp/npe/include -DCONFIG_IXP425_COMPONENT_ETHDB -D__linux
-CFLAGS  += $(LOCAL_CFLAGS)
-HOSTCFLAGS  += $(LOCAL_CFLAGS)
-
-COBJS-$(CONFIG_IXP4XX_NPE) := npe.o \
-	miiphy.o \
-	IxOsalBufferMgt.o \
-	IxOsalIoMem.o \
-	IxOsalOsCacheMMU.o \
-	IxOsalOsMsgQ.o \
-	IxOsalOsSemaphore.o \
-	IxOsalOsServices.o \
-	IxOsalOsThread.o \
-	IxEthAcc.o \
-	IxEthAccCommon.o \
-	IxEthAccControlInterface.o \
-	IxEthAccDataPlane.o \
-	IxEthAccMac.o \
-	IxEthAccMii.o \
-	IxEthDBAPI.o \
-	IxEthDBAPISupport.o \
-	IxEthDBCore.o \
-	IxEthDBEvents.o \
-	IxEthDBFeatures.o \
-	IxEthDBFirewall.o \
-	IxEthDBHashtable.o \
-	IxEthDBLearning.o \
-	IxEthDBMem.o \
-	IxEthDBNPEAdaptor.o \
-	IxEthDBPortUpdate.o \
-	IxEthDBReports.o \
-	IxEthDBSearch.o \
-	IxEthDBSpanningTree.o \
-	IxEthDBUtil.o \
-	IxEthDBVlan.o \
-	IxEthDBWiFi.o \
-	IxEthMii.o \
-	IxQMgrAqmIf.o \
-	IxQMgrDispatcher.o \
-	IxQMgrInit.o \
-	IxQMgrQAccess.o \
-	IxQMgrQCfg.o \
-	IxFeatureCtrl.o \
-	IxNpeDl.o \
-	IxNpeDlImageMgr.o \
-	IxNpeDlNpeMgr.o \
-	IxNpeDlNpeMgrUtils.o \
-	IxNpeMh.o \
-	IxNpeMhConfig.o \
-	IxNpeMhReceive.o \
-	IxNpeMhSend.o \
-	IxNpeMhSolicitedCbMgr.o \
-	IxNpeMhUnsolicitedCbMgr.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS-y))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-all:	$(LIB)
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/arch/arm/cpu/ixp/npe/include/IxAssert.h b/arch/arm/cpu/ixp/npe/include/IxAssert.h
deleted file mode 100644
index eae8b3f..0000000
--- a/arch/arm/cpu/ixp/npe/include/IxAssert.h
+++ /dev/null
@@ -1,71 +0,0 @@
-/**
- * @file IxAssert.h
- *
- * @date 21-MAR-2002 (replaced by OSAL)
- *
- * @brief This file contains assert and ensure macros used by the IXP400 software
- *
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- * 
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- * 
- * @par
- * -- End of Copyright Notice --
- */
-
-/**
- * @defgroup IxAssert IXP400 Assertion Macros (IxAssert) API
- *
- * @brief Assertion support
- *
- * @{
- */
-
-#ifndef IXASSERT_H
-
-#ifndef __doxygen_HIDE
-#define IXASSERT_H
-#endif /* __doxygen_HIDE */
-
-#include "IxOsalBackward.h"
-
-#endif /* IXASSERT_H */
-
-/**
- * @} addtogroup IxAssert
- */
-
-
-
diff --git a/arch/arm/cpu/ixp/npe/include/IxAtmSch.h b/arch/arm/cpu/ixp/npe/include/IxAtmSch.h
deleted file mode 100644
index 73c3be2..0000000
--- a/arch/arm/cpu/ixp/npe/include/IxAtmSch.h
+++ /dev/null
@@ -1,504 +0,0 @@
-/**
- * @file    IxAtmSch.h
- *
- * @date    23-NOV-2001
- *
- * @brief   Header file for the IXP400 ATM Traffic Shaper
- *
- * This component demonstrates an ATM Traffic Shaper implementation. It
- * will perform shaping on upto 12 ports and total of 44 VCs accross all ports,
- * 32 are intended for AAL0/5 and 12 for OAM (1 per port).
- * The supported traffic types are;1 rt-VBR VC where PCR = SCR.
- * (Effectively CBR) and Up-to 44 VBR VCs.
- *
- * This component models the ATM ports and VCs and is capable of producing
- * a schedule of ATM cells per port which can be supplied to IxAtmdAcc
- * for execution on the data path.
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- * 
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- * 
- * @par
- * -- End of Copyright Notice --
- *
- * @sa IxAtmm.h
- *
- */
-
-/**
- * @defgroup IxAtmSch IXP400 ATM Transmit Scheduler (IxAtmSch) API
- *
- * @brief IXP400 ATM scheduler component Public API
- *
- * @{
- */
-
-#ifndef IXATMSCH_H
-#define IXATMSCH_H
-
-#include "IxOsalTypes.h"
-#include "IxAtmTypes.h"
-
-/*
- * #defines and macros used in this file.
- */
-
-/* Return codes */
-
-/** 
- * @ingroup IxAtmSch
- *
- * @def IX_ATMSCH_RET_NOT_ADMITTED
- * @brief Indicates that CAC function has rejected VC registration due
- *         to insufficient line capacity.
-*/
-#define IX_ATMSCH_RET_NOT_ADMITTED 2
-
-/**  
- * @ingroup IxAtmSch
- *
- * @def IX_ATMSCH_RET_QUEUE_FULL
- *  @brief Indicates that the VC queue is full, no more demand can be
- *         queued at this time.
- */
-#define IX_ATMSCH_RET_QUEUE_FULL 3
-
-/**  
- * @ingroup IxAtmSch
- *
- *  @def IX_ATMSCH_RET_QUEUE_EMPTY
- *  @brief Indicates that all VC queues on this port are empty and
- *         therefore there are no cells to be scheduled at this time.
- */
-#define IX_ATMSCH_RET_QUEUE_EMPTY 4
-
-/*
- * Function declarations
- */
-
-/**  
- * @ingroup IxAtmSch
- *
- * @fn ixAtmSchInit(void)
- *
- *  @brief This function is used to initialize the ixAtmSch component. It
- *         should be called before any other IxAtmSch API function.
- *
- * @param None
- *
- * @return
- * - <b>IX_SUCCESS :</b> indicates that
- *          -# The ATM scheduler component has been successfully initialized.
- *          -# The scheduler is ready to accept Port modelling requests.
- * - <b>IX_FAIL :</b> Some internal error has prevented the scheduler component
- *          from initialising.
- */
-PUBLIC IX_STATUS
-ixAtmSchInit(void);
-
-/**  
- * @ingroup IxAtmSch
- *
- * @fn ixAtmSchPortModelInitialize( IxAtmLogicalPort port,
-                                       unsigned int portRate,
-                                       unsigned int minCellsToSchedule)
- *
- * @brief This function shall be called first to initialize an ATM port before
- *         any other ixAtmSch API calls may be made for that port.
- *
- * @param port @ref IxAtmLogicalPort [in] - The specific port to initialize.  Valid
- *          values range from 0 to IX_UTOPIA_MAX_PORTS - 1, representing a 
- *          maximum of IX_UTOPIA_MAX_PORTS possible ports.
- *
- * @param portRate unsigned int [in] - Value indicating the upstream capacity
- *          of the indicated port.  The value should be supplied in
- *          units of ATM (53 bytes) cells per second.
- *          A port rate of 800Kbits/s is the equivalent 
- *          of 1886 cells per second
- *
- * @param minCellsToSchedule unsigned int [in] - This parameter specifies the minimum
- *          number of cells which the scheduler will put in a schedule
- *          table for this port. This value sets the worst case CDVT for VCs
- *          on this port i.e. CDVT = 1*minCellsToSchedule/portRate.
- * @return
- *    - <b>IX_SUCCESS :</b> indicates that
- *          -# The ATM scheduler has been successfully initialized.
- *          -# The requested port model has been established.
- *          -# The scheduler is ready to accept VC modelling requests
- *            on the ATM port.
- *    - <b>IX_FAIL :</b> indicates the requested port could not be
- * initialized.  */
-PUBLIC IX_STATUS
-ixAtmSchPortModelInitialize( IxAtmLogicalPort port,
-                                       unsigned int portRate,
-                                       unsigned int minCellsToSchedule);
-
-/**  
- * @ingroup IxAtmSch
- *
- * @fn ixAtmSchPortRateModify( IxAtmLogicalPort port,
-                        unsigned int portRate)
- *
- *  @brief This function is called to modify the portRate on a
- *         previously initialized port, typically in the event that
- *         the line condition of the port changes.
- *
- * @param port @ref IxAtmLogicalPort [in] - Specifies the ATM port which is to be
- *          modified.
- *
- * @param portRate unsigned int [in] - Value indicating the new upstream
- *          capacity for this port in cells/second.
- *          A port rate of 800Kbits/s is the equivalent 
- *          of 1886 cells per second
- *
- * @return
- * - <b>IX_SUCCESS :</b> The port rate has been successfully modified.<br>
- * - <b>IX_FAIL :</b> The port rate could not be modified, either
- *      because the input data was invalid, or the new port rate is
- *      insufficient to support established ATM VC contracts on this
- *      port.
- *
- * @warning The IxAtmSch component will validate the supplied port
- *          rate is sufficient to support all established VC
- *          contracts on the port.  If the new port rate is
- *          insufficient to support all established contracts then
- *          the request to modify the port rate will be rejected.
- *          In this event, the user is expected to remove
- *          established contracts using the ixAtmSchVcModelRemove
- *          interface and then retry this interface.
- *
- * @sa ixAtmSchVcModelRemove() */
-PUBLIC IX_STATUS
-ixAtmSchPortRateModify( IxAtmLogicalPort port,
-                        unsigned int portRate);
-
-
-/**  
- * @ingroup IxAtmSch
- *
- * @fn ixAtmSchVcModelSetup( IxAtmLogicalPort port,
-                      IxAtmTrafficDescriptor *trafficDesc,
-                      IxAtmSchedulerVcId *vcId)
- *
- *  @brief A client calls this interface to set up an upstream
- *         (transmitting) virtual connection model (VC) on the
- *         specified ATM port.  This function also provides the
- *         virtual * connection admission control (CAC) service to the
- *         client.
- *
- * @param port @ref IxAtmLogicalPort [in] - Specifies the ATM port on which the upstream
- *          VC is to be established.
- *
- * @param *trafficDesc @ref IxAtmTrafficDescriptor [in] - Pointer to a structure
- *          describing the requested traffic contract of the VC to be
- *          established.  This structure contains the typical ATM
- *          traffic descriptor values (e.g. PCR, SCR, MBS, CDVT, etc.)
- *          defined by the ATM standard.
- *
- * @param *vcId @ref IxAtmSchedulerVcId [out] - This value will be filled with the
- *              port-unique identifier for this virtual connection.  A
- *              valid identification is a non-negative number.
- *
- * @return
- * - <b>IX_SUCCESS :</b> The VC has been successfully established on
- *      this port.  The client may begin to submit demand on this VC.
- * - <b>IX_ATMSCH_RET_NOT_ADMITTED :</b> The VC cannot be established
- *      on this port because there is insufficient upstream capacity
- *      available to support the requested traffic contract descriptor
- * - <b>IX_FAIL :</b>Input data are invalid.  VC has not been
- *      established.
- */
-PUBLIC IX_STATUS
-ixAtmSchVcModelSetup( IxAtmLogicalPort port,
-                      IxAtmTrafficDescriptor *trafficDesc,
-                      IxAtmSchedulerVcId *vcId);
-
-/**  
- * @ingroup IxAtmSch
- *
- * @fn ixAtmSchVcConnIdSet( IxAtmLogicalPort port,
-                     IxAtmSchedulerVcId vcId,
-                     IxAtmConnId vcUserConnId)
- *
- *  @brief A client calls this interface to set the vcUserConnId for a VC on
- *         the specified ATM port. This vcUserConnId will default to
- *         IX_ATM_IDLE_CELLS_CONNID if this function is not called for a VC.
- *         Hence if the client does not call this function for a VC then only idle
- *         cells will be scheduled for this VC.
- *
- * @param port @ref IxAtmLogicalPort [in] - Specifies the ATM port on which the upstream
- *        VC is has been established.
- *
- * @param vcId @ref IxAtmSchedulerVcId [in] - This is the unique identifier for this virtual
- *        connection. A valid identification is a non-negative number and is
- *        all ports.
- *
- * @param vcUserConnId @ref IxAtmConnId [in] - The connId is used to refer to a VC in schedule
- *        table entries. It is treated as the Id by which the scheduler client
- *        knows the VC. It is used in any communicatations from the Scheduler
- *        to the scheduler user e.g. schedule table entries.
- *
- * @return
- * - <b>IX_SUCCESS :</b> The id has successfully been set.
- * - <b>IX_FAIL :</b>Input data are invalid. connId id is not established.
- */
-PUBLIC IX_STATUS
-ixAtmSchVcConnIdSet( IxAtmLogicalPort port,
-                     IxAtmSchedulerVcId vcId,
-                     IxAtmConnId vcUserConnId);
-
-/**  
- * @ingroup IxAtmSch
- *
- * @fn ixAtmSchVcModelRemove( IxAtmLogicalPort port,
-                       IxAtmSchedulerVcId vcId)
- *
- *  @brief Interface called by the client to remove a previously
- *         established VC on a particular port.
- *
- * @param port @ref IxAtmLogicalPort [in] - Specifies the ATM port on which the VC to be
- *          removed is established.
- *
- * @param vcId @ref IxAtmSchedulerVcId [in] - Identifies the VC to be removed.  This is the
- *          value returned by the @ref ixAtmSchVcModelSetup call which
- *          established the relevant VC.
- *
- * @return
- * - <b>IX_SUCCESS :</b> The VC has been successfully removed from
- *      this port. It is no longer modelled on this port.
- * - <b>IX_FAIL :</b>Input data are invalid. The VC is still being modeled
- *      by the traffic shaper.
- *
- * @sa ixAtmSchVcModelSetup() 
- */
-PUBLIC IX_STATUS
-ixAtmSchVcModelRemove( IxAtmLogicalPort port,
-                       IxAtmSchedulerVcId vcId);
-
-/**  
- * @ingroup IxAtmSch
- *
- * @fn ixAtmSchVcQueueUpdate( IxAtmLogicalPort port,
-                       IxAtmSchedulerVcId vcId,
-                       unsigned int numberOfCells)
- *
- *  @brief The client calls this function to notify IxAtmSch that the
- *         user of a VC has submitted cells for transmission.
- *
- *  This information is stored, aggregated from a number of calls to
- *  ixAtmSchVcQueueUpdate and eventually used in the call to
- *  ixAtmSchTableUpdate.
- *
- *  Normally IxAtmSch will update the VC queue by adding the number of
- *  cells to the current queue length.  However, if IxAtmSch
- *  determines that the user has over-submitted for the VC and
- *  exceeded its transmission quota the queue request can be rejected.
- *  The user should resubmit the request later when the queue has been
- *  depleted.
- *
- *  This implementation of ixAtmSchVcQueueUpdate uses no operating
- *  system or external facilities, either directly or indirectly.
- *  This allows clients to call this function form within an interrupt handler.
- *
- *  This interface is structurally compatible with the
- *  IxAtmdAccSchQueueUpdate callback type definition required for
- *  IXP400 ATM scheduler interoperability.
- *
- * @param port @ref IxAtmLogicalPort [in] - Specifies the ATM port on which the VC to be
- *          updated is established.
- *
- * @param vcId @ref IxAtmSchedulerVcId [in] - Identifies the VC to be updated.  This is the
- *          value returned by the @ref ixAtmSchVcModelSetup call which
- *          established the relevant VC.
- *
- * @param numberOfCells unsigned int [in] - Indicates how many ATM cells should
- *          be added to the queue for this VC.
- *
- * @return
- *  - <b>IX_SUCCESS :</b> The VC queue has been successfully updated.
- *  - <b>IX_ATMSCH_RET_QUEUE_FULL :</b> The VC queue has reached a
- *       preset limit.  This indicates the client has over-submitted
- *       and exceeded its transmission quota.  The request is
- *       rejected.  The VC queue is not updated.  The VC user is
- *       advised to resubmit the request later.
- *  - <b>IX_FAIL :</b> The input are invalid.  No VC queue is updated.
- *
- * @warning IxAtmSch assumes that the calling software ensures that
- *          calls to ixAtmSchVcQueueUpdate, ixAtmSchVcQueueClear and
- *          ixAtmSchTableUpdate are both self and mutually exclusive
- *          for the same port.
- *
- * @sa ixAtmSchVcQueueUpdate(), ixAtmSchVcQueueClear(), ixAtmSchTableUpdate().  */
-PUBLIC IX_STATUS
-ixAtmSchVcQueueUpdate( IxAtmLogicalPort port,
-                       IxAtmSchedulerVcId vcId,
-                       unsigned int numberOfCells);
-
-/**  
- * @ingroup IxAtmSch
- *
- * @fn ixAtmSchVcQueueClear( IxAtmLogicalPort port,
-                      IxAtmSchedulerVcId vcId)
- *
- *  @brief The client calls this function to remove all currently
- *         queued cells from a registered VC.  The pending cell count
- *         for the specified VC is reset to zero.
- *
- *  This interface is structurally compatible with the
- *  IxAtmdAccSchQueueClear callback type definition required for
- *  IXP400 ATM scheduler interoperability.
- *
- * @param port @ref IxAtmLogicalPort [in] - Specifies the ATM port on which the VC to be
- *          cleared is established.
- *
- * @param vcId @ref IxAtmSchedulerVcId [in] - Identifies the VC to be cleared.  This is the
- *          value returned by the @ref ixAtmSchVcModelSetup call which
- *          established the relevant VC.
- *
- * @return
- *  - <b>IX_SUCCESS :</b> The VC queue has been successfully cleared.
- *  - <b>IX_FAIL :</b> The input are invalid.  No VC queue is modified.
- *
- * @warning IxAtmSch assumes that the calling software ensures that
- *          calls to ixAtmSchVcQueueUpdate, ixAtmSchVcQueueClear and
- *          ixAtmSchTableUpdate are both self and mutually exclusive
- *          for the same port.
- *
- * @sa ixAtmSchVcQueueUpdate(), ixAtmSchVcQueueClear(), ixAtmSchTableUpdate().  */
-PUBLIC IX_STATUS
-ixAtmSchVcQueueClear( IxAtmLogicalPort port,
-                      IxAtmSchedulerVcId vcId);
-
-/**  
- * @ingroup IxAtmSch
- *
- * @fn ixAtmSchTableUpdate( IxAtmLogicalPort port,
-                     unsigned int maxCells,
-                     IxAtmScheduleTable **rettable)
- *
- *  @brief The client calls this function to request an update of the
- *         schedule table for a particular ATM port.
- *
- *  This is called when the client decides it needs a new sequence of
- *  cells to send (probably because the transmit queue is near to
- *  empty for this ATM port).  The scheduler will use its stored
- *  information on the cells submitted for transmit (i.e. data
- *  supplied via @ref ixAtmSchVcQueueUpdate function) with the traffic
- *  descriptor information of all established VCs on the ATM port to
- *  decide the sequence of cells to be sent and fill the schedule
- *  table for a period of time into the future.
- *
- *  IxAtmSch will guarantee a minimum of minCellsToSchedule if there
- *  is at least one cell ready to send. If there are no cells then
- *  IX_ATMSCH_RET_QUEUE_EMPTY is returned.
- *
- *  This implementation of ixAtmSchTableUpdate uses no operating
- *  system or external facilities, either directly or indirectly.
- *  This allows clients to call this function form within an FIQ
- *  interrupt handler.
- *
- * @param port @ref IxAtmLogicalPort [in] - Specifies the ATM port for which requested
- *          schedule table is to be generated.
- *
- * @param maxCells unsigned [in] - Specifies the maximum number of cells
- *          that must be scheduled in the supplied table during any
- *          call to the interface.
- *
- * @param **table @ref IxAtmScheduleTable [out] - A pointer to an area of
- *              storage is returned which contains the generated
- *              schedule table.  The client should not modify the
- *              contents of this table.
- *
- * @return
- *  - <b>IX_SUCCESS :</b> The schedule table has been published.
- *       Currently there is at least one VC queue that is nonempty.
- *  - <b>IX_ATMSCH_RET_QUEUE_EMPTY :</b> Currently all VC queues on
- *       this port are empty.  The schedule table returned is set to
- *       NULL.  The client is not expected to invoke this function
- *       again until more cells have been submitted on this port
- *       through the @ref ixAtmSchVcQueueUpdate function.
- *  - <b>IX_FAIL :</b> The input are invalid.  No action is taken.
- *
- * @warning IxAtmSch assumes that the calling software ensures that
- *          calls to ixAtmSchVcQueueUpdate, ixAtmSchVcQueueClear and
- *          ixAtmSchTableUpdate are both self and mutually exclusive
- *          for the same port.
- *
- * @warning Subsequent calls to this function for the same port will
- *          overwrite the contents of previously supplied schedule
- *          tables.  The client must be completely finished with the
- *          previously supplied schedule table before calling this
- *          function again for the same port.
- *
- * @sa ixAtmSchVcQueueUpdate(), ixAtmSchVcQueueClear(), ixAtmSchTableUpdate().  */
-PUBLIC IX_STATUS
-ixAtmSchTableUpdate( IxAtmLogicalPort port,
-                     unsigned int maxCells,
-                     IxAtmScheduleTable **rettable);
-
-/**  
- * @ingroup IxAtmSch
- *
- * @fn ixAtmSchShow(void)
- *
- *  @brief Utility function which will print statistics on the current
- *         and accumulated state of VCs and traffic in the ATM
- *         scheduler component.  Output is sent to the default output
- *         device.
- *
- * @param none
- * @return none
- */
-PUBLIC void
-ixAtmSchShow(void);
-
-/**  
- * @ingroup IxAtmSch
- *
- * @fn ixAtmSchStatsClear(void)
- *
- *  @brief Utility function which will reset all counter statistics in
- *         the ATM scheduler to zero.
- *
- * @param none
- * @return none
- */
-PUBLIC void
-ixAtmSchStatsClear(void);
-
-#endif
-/* IXATMSCH_H */
-
-/** @} */
diff --git a/arch/arm/cpu/ixp/npe/include/IxAtmTypes.h b/arch/arm/cpu/ixp/npe/include/IxAtmTypes.h
deleted file mode 100644
index 8624c33..0000000
--- a/arch/arm/cpu/ixp/npe/include/IxAtmTypes.h
+++ /dev/null
@@ -1,409 +0,0 @@
-/**
- * @file IxAtmTypes.h
- *
- * @date 24-MAR-2002
- *
- * @brief This file contains Atm types common to a number of Atm components.
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- * 
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- * 
- * @par
- * -- End of Copyright Notice --
- */
-
-/* ------------------------------------------------------
-   Doxygen group definitions
-   ------------------------------------------------------ */
-/**
- * @defgroup IxAtmTypes IXP400 ATM Types (IxAtmTypes)
- *
- * @brief The common set of types used in many Atm components
- *
- * @{ */
-
-#ifndef IXATMTYPES_H
-#define IXATMTYPES_H
-
-#include "IxNpeA.h"
-
-/**
- * @enum IxAtmLogicalPort
- *
- * @brief Logical Port Definitions  :
- *
- * Only 1 port is available in SPHY configuration
- * 12 ports are enabled in MPHY configuration
- *
- */
-typedef enum
-{
-    IX_UTOPIA_PORT_0 = 0,  /**< Port 0 */
-#ifdef IX_NPE_MPHYMULTIPORT
-    IX_UTOPIA_PORT_1,      /**< Port 1 */
-    IX_UTOPIA_PORT_2,      /**< Port 2 */
-    IX_UTOPIA_PORT_3,      /**< Port 3 */
-    IX_UTOPIA_PORT_4,      /**< Port 4 */
-    IX_UTOPIA_PORT_5,      /**< Port 5 */
-    IX_UTOPIA_PORT_6,      /**< Port 6 */
-    IX_UTOPIA_PORT_7,      /**< Port 7 */
-    IX_UTOPIA_PORT_8,      /**< Port 8 */
-    IX_UTOPIA_PORT_9,      /**< Port 9 */
-    IX_UTOPIA_PORT_10,     /**< Port 10 */
-    IX_UTOPIA_PORT_11,     /**< Port 11 */
-#endif /* IX_NPE_MPHY */
-    IX_UTOPIA_MAX_PORTS    /**< Not a port - just a definition for the
-                           * maximum possible ports
-                           */
-} IxAtmLogicalPort;
-
-/**
- * @def IX_ATM_CELL_PAYLOAD_SIZE
- * @brief Size of a ATM cell payload
- */
-#define IX_ATM_CELL_PAYLOAD_SIZE             (48)
-
-/**
- * @def IX_ATM_CELL_SIZE
- * @brief Size of a ATM cell, including header
- */
-#define IX_ATM_CELL_SIZE                     (53)
-
-/**
- * @def IX_ATM_CELL_SIZE_NO_HEC
- * @brief Size of a ATM cell, excluding HEC byte
- */
-#define IX_ATM_CELL_SIZE_NO_HEC              (IX_ATM_CELL_SIZE - 1)
-
-/**
- * @def IX_ATM_OAM_CELL_SIZE_NO_HEC
- * @brief Size of a OAM cell, excluding HEC byte
- */
-#define IX_ATM_OAM_CELL_SIZE_NO_HEC          IX_ATM_CELL_SIZE_NO_HEC
-
-/**
- * @def IX_ATM_AAL0_48_CELL_PAYLOAD_SIZE
- * @brief Size of a AAL0 48 Cell payload
- */
-#define IX_ATM_AAL0_48_CELL_PAYLOAD_SIZE     IX_ATM_CELL_PAYLOAD_SIZE
-
-/**
- * @def IX_ATM_AAL5_CELL_PAYLOAD_SIZE
- * @brief Size of a AAL5 Cell payload
- */
-#define IX_ATM_AAL5_CELL_PAYLOAD_SIZE        IX_ATM_CELL_PAYLOAD_SIZE
-
-/**
- * @def IX_ATM_AAL0_52_CELL_SIZE_NO_HEC
- * @brief Size of a AAL0 52 Cell, excluding HEC byte
- */
-#define IX_ATM_AAL0_52_CELL_SIZE_NO_HEC      IX_ATM_CELL_SIZE_NO_HEC
-
-
-/**
- * @def IX_ATM_MAX_VPI
- * @brief Maximum value of an ATM VPI
- */
-#define IX_ATM_MAX_VPI 255
-
-/**
- * @def IX_ATM_MAX_VCI
- * @brief Maximum value of an ATM VCI
- */
-#define IX_ATM_MAX_VCI 65535
-
- /**
- * @def IX_ATM_MAX_NUM_AAL_VCS
- * @brief Maximum number of active AAL5/AAL0 VCs in the system
- */
-#define IX_ATM_MAX_NUM_AAL_VCS 32
-
-/**
- * @def IX_ATM_MAX_NUM_VC
- * @brief Maximum number of active AAL5/AAL0 VCs in the system
- * The use of this macro is depreciated, it is retained for
- * backward compatiblity. For current software release
- * and beyond the define IX_ATM_MAX_NUM_AAL_VC should be used.
- */
-#define IX_ATM_MAX_NUM_VC IX_ATM_MAX_NUM_AAL_VCS
-
-
-
-/**
- * @def IX_ATM_MAX_NUM_OAM_TX_VCS
- * @brief Maximum number of active OAM Tx VCs in the system, 
- *        1 OAM VC per port
- */
-#define IX_ATM_MAX_NUM_OAM_TX_VCS IX_UTOPIA_MAX_PORTS
-
-/**
- * @def IX_ATM_MAX_NUM_OAM_RX_VCS
- * @brief Maximum number of active OAM Rx VCs in the system, 
- *        1 OAM VC shared accross all ports
- */
-#define IX_ATM_MAX_NUM_OAM_RX_VCS 1
-
-/**
- * @def IX_ATM_MAX_NUM_AAL_OAM_TX_VCS
- * @brief Maximum number of active AAL5/AAL0/OAM Tx VCs in the system
- */
-#define IX_ATM_MAX_NUM_AAL_OAM_TX_VCS (IX_ATM_MAX_NUM_AAL_VCS + IX_ATM_MAX_NUM_OAM_TX_VCS)
-
-/**
- * @def IX_ATM_MAX_NUM_AAL_OAM_RX_VCS
- * @brief Maximum number of active AAL5/AAL0/OAM Rx VCs in the system
- */
-#define IX_ATM_MAX_NUM_AAL_OAM_RX_VCS (IX_ATM_MAX_NUM_AAL_VCS + IX_ATM_MAX_NUM_OAM_RX_VCS)
-
-/**
- *  @def IX_ATM_IDLE_CELLS_CONNID
- *  @brief VC Id used to indicate idle cells in the returned schedule table.
- */
-#define IX_ATM_IDLE_CELLS_CONNID 0
-
-
-/**
- *  @def IX_ATM_CELL_HEADER_VCI_GET
- *  @brief get the VCI field from a cell header
- */
-#define IX_ATM_CELL_HEADER_VCI_GET(cellHeader) \
-    (((cellHeader) >> 4) & IX_OAM_VCI_BITS_MASK);
-
-/**
- *  @def IX_ATM_CELL_HEADER_VPI_GET
- *  @brief get the VPI field from a cell header
- */
-#define IX_ATM_CELL_HEADER_VPI_GET(cellHeader) \
-    (((cellHeader) >> 20) & IX_OAM_VPI_BITS_MASK);
-
-/**
- *  @def IX_ATM_CELL_HEADER_PTI_GET
- *  @brief get the PTI field from a cell header
- */
-#define IX_ATM_CELL_HEADER_PTI_GET(cellHeader) \
-    ((cellHeader) >> 1) & IX_OAM_PTI_BITS_MASK;
-
-/**
- * @typedef IxAtmCellHeader
- *
- * @brief ATM Cell Header, does not contain 4 byte HEC, added by NPE-A 
- */
-typedef unsigned int IxAtmCellHeader;
-
-
-/**
- * @enum IxAtmServiceCategory
- *
- * @brief Enumerated type representing available ATM service categories.
- *   For more informatoin on these categories, see "Traffic Management
- *   Specification" v4.1, published by the ATM Forum -
- *   http://www.atmforum.com
- */
-typedef enum
-{
-    IX_ATM_CBR,    /**< Constant Bit Rate */
-    IX_ATM_RTVBR,  /**< Real Time Variable Bit Rate */
-    IX_ATM_VBR,    /**< Variable Bit Rate */
-    IX_ATM_UBR,    /**< Unspecified Bit Rate */
-    IX_ATM_ABR     /**< Available Bit Rate (not supported) */
-
-} IxAtmServiceCategory;
-
-/**
- *
- * @enum IxAtmRxQueueId
- *
- * @brief Rx Queue Type for RX traffic
- *
- * IxAtmRxQueueId defines the queues involved for receiving data.
- *
- * There are two queues to facilitate prioritisation handling
- * and processing the 2 queues with different algorithms and
- * constraints
- *
- * e.g. : one queue can carry voice (or time-critical traffic), the
- * other queue can carry non-voice traffic
- *
- */
-typedef enum
-{
-    IX_ATM_RX_A = 0,      /**< RX queue A */
-    IX_ATM_RX_B,          /**< RX queue B */
-    IX_ATM_MAX_RX_STREAMS /**< Maximum number of RX streams */
-} IxAtmRxQueueId;
-
-/**
- * @brief Structure describing an ATM traffic contract for a Virtual
- *         Connection (VC).
- *
- * Structure is used to specify the requested traffic contract for a
- * VC to the IxAtmSch component using the @ref ixAtmSchVcModelSetup
- * interface.
- *
- * These parameters are defined by the ATM forum working group
- * (http://www.atmforum.com).
- *
- * @note Typical values for a voice channel 64 Kbit/s
- * - atmService @a IX_ATM_RTVBR
- * - pcr   400  (include IP overhead, and AAL5 trailer)
- * - cdvt  5000000 (5 ms)
- * - scr = pcr
- *
- * @note Typical values for a data channel 800 Kbit/s
- * - atmService @a IX_ATM_UBR
- * - pcr   1962  (include IP overhead, and AAL5 trailer)
- * - cdvt  5000000 (5 ms)
- *
- */
-typedef struct
-{
-    IxAtmServiceCategory atmService; /**< ATM service category */
-    unsigned pcr;   /**< Peak Cell Rate - cells per second */
-    unsigned cdvt;  /**< Cell Delay Variation Tolerance - in nanoseconds */
-    unsigned scr;   /**< Sustained Cell Rate - cells per second */
-    unsigned mbs;   /**< Max Burst Size - cells */
-    unsigned mcr;   /**< Minimum Cell Rate - cells per second */
-    unsigned mfs;   /**< Max Frame Size - cells */
-} IxAtmTrafficDescriptor;
-
-/**
- * @typedef IxAtmConnId
- *
- * @brief ATM VC data connection identifier.
- *
- * This is is generated by IxAtmdAcc when a successful connection is
- * made on a VC. The is the ID by which IxAtmdAcc knows an active
- * VC and should be used in IxAtmdAcc API calls to reference a
- * specific VC.
- */
-typedef unsigned int IxAtmConnId;
-
-/**
- * @typedef IxAtmSchedulerVcId
- *
- * @brief ATM VC scheduling connection identifier.
- *
- * This id is generated and used by ATM Tx controller, generally
- * the traffic shaper (e.g. IxAtmSch). The IxAtmdAcc component
- * will request one of these Ids whenever a data connection on
- * a Tx VC is requested. This ID will be used in callbacks to
- * the ATM Transmission Ctrl s/w (e.g. IxAtmm) to reference a
- * particular VC.
- */
-typedef int IxAtmSchedulerVcId;
-
-/**
- * @typedef IxAtmNpeRxVcId
- *
- * @brief ATM Rx VC identifier used by the ATM Npe.
- *
- * This Id is generated by IxAtmdAcc when a successful data connection
- * is made on a rx VC.
- */
-typedef unsigned int IxAtmNpeRxVcId;
-
-/**
- * @brief ATM Schedule Table entry
- *
- * This IxAtmScheduleTableEntry is used by an ATM scheduler to inform
- * IxAtmdAcc about the data to transmit (in term of cells per VC)
- *
- * This structure defines
- * @li the number of cells to be transmitted (numberOfCells)
- * @li the VC connection to be used for transmission (connId).
- *
- * @note - When the connection Id value is IX_ATM_IDLE_CELLS_CONNID, the
- * corresponding number of idle cells will be transmitted to the hardware.
- *
- */
-typedef struct
-{
-    IxAtmConnId connId; /**< connection Id
-                 *
-                 * Identifier of VC from which cells are to be transmitted.
-                 * When this valus is IX_ATM_IDLE_CELLS_CONNID, this indicates
-                 * that the system should transmit the specified number
-                 * of idle cells. Unknown connIds result in the transmission
-                 * idle cells.
-                 */
-    unsigned int numberOfCells; /**< number of cells to transmit
-                 *
-                 * The number of contiguous cells to schedule from this VC
-                 * at this point. The valid range is from 1 to
-                 * @a IX_ATM_SCHEDULETABLE_MAXCELLS_PER_ENTRY. This
-                 * number can swap over mbufs and pdus. OverSchduling results
-                 * in the transmission of idle cells.
-                 */
-} IxAtmScheduleTableEntry;
-
-/**
- * @brief This structure defines a schedule table which gives details
- *         on which data (from which VCs) should be transmitted for a
- *         forthcoming period of time for a particular port and the
- *         order in which that data should be transmitted.
- *
- *  The schedule table consists of a series of entries each of which
- *  will schedule one or more cells from a particular registered VC.
- *  The total number of cells scheduled and the total number of
- *  entries in the table are also indicated.
- *
- */
-typedef struct
-{
-    unsigned tableSize;      /**< Number of entries
-                              *
-                              * Indicates the total number of
-                              *   entries in the table.
-                              */
-    unsigned totalCellSlots; /**< Number of cells
-                              *
-                              * Indicates the total number of ATM
-                              *   cells which are scheduled by all the
-                              *   entries in the table.
-                              */
-    IxAtmScheduleTableEntry *table; /**< Pointer to schedule entries
-                                     *
-                                     * Pointer to an array
-                                     *   containing tableSize entries
-                                     */
-} IxAtmScheduleTable;
-
-#endif /* IXATMTYPES_H */
-
-/**
- * @} defgroup IxAtmTypes
- */
-
-
diff --git a/arch/arm/cpu/ixp/npe/include/IxAtmdAcc.h b/arch/arm/cpu/ixp/npe/include/IxAtmdAcc.h
deleted file mode 100644
index ae7b243..0000000
--- a/arch/arm/cpu/ixp/npe/include/IxAtmdAcc.h
+++ /dev/null
@@ -1,1194 +0,0 @@
-
-/**
- * @file    IxAtmdAcc.h
- *
- * @date    07-Nov-2001
- *
- * @brief IxAtmdAcc Public API
- *
- * This file contains the public API of IxAtmdAcc, related to the
- * data functions of the component
- *
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- * 
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- * 
- * @par
- * -- End of Copyright Notice --
- */
-
-/* ------------------------------------------------------
-   Doxygen group definitions
-   ------------------------------------------------------ */
-
-/**
- *
- * @defgroup IxAtmdAccAPI IXP400 ATM Driver Access (IxAtmdAcc) API
- *
- * @brief The public API for the IXP400 Atm Driver Data component
- *
- * IxAtmdAcc is the low level interface by which AAL0/AAL5 and
- * OAM data gets transmitted to,and received from the Utopia bus.
- *
- * For AAL0/AAL5 services transmit and receive connections may
- * be established independantly for unique combinations of
- * port,VPI,and VCI.
- *
- * Two AAL0 services supporting 48 or 52 byte cell data are provided.
- * Submitted AAL0 PDUs must be a multiple of the cell data size (48/52).
- * AAL0_52 is a raw cell service the client must format
- * the PDU with an ATM cell header (excluding HEC) at the start of
- * each cell, note that AtmdAcc does not validate the cell headers in
- * a submitted PDU.
- *
- * OAM cells cannot be received over the AAL0 service but instead
- * are received over a dedicated OAM service.
- *
- * For the OAM service an "OAM Tx channel" may be enabled for a port
- * by establishing a single dedicated OAM Tx connection on that port.
- * A single "OAM Rx channel" for all ports may be  enabled by
- * establishing a dedicated OAM Rx connection.
- *
- * The OAM service allows buffers containing 52 byte OAM F4/F5 cells
- * to be transmitted and received over the dedicated OAM channels.
- * HEC is appended/removed, and CRC-10 performed by the NPE. The OAM
- * service offered by AtmdAcc is a raw cell transport service.
- * It is assumed that ITU I.610 procedures that make use of this
- * service are implemented above AtmdAcc.
- *
- * Note that the dedicated OAM connections are established on
- * reserved VPI,VCI, and (in the case of Rx) port values defined below.
- * These values are used purely to descriminate the dedicated OAM channels
- * and do not identify a particular OAM F4/F5 flow. F4/F5 flows may be
- * realised for particluar VPI/VCIs by manipulating the VPI,VCI
- * fields of the ATM cell headers of cells in the buffers passed
- * to AtmdAcc. Note that AtmdAcc does not validate the cell headers
- * in a submitted OAM PDU.
- *
- *
- *
- * This part is related to the User datapath processing
- *
- * @{
- */
-
-#ifndef IXATMDACC_H
-#define IXATMDACC_H
-
-#include "IxAtmTypes.h"
-
-/* ------------------------------------------------------
-   AtmdAcc Data Types definition
-   ------------------------------------------------------ */
-
-/**
- *
- * @ingroup IxAtmdAccAPI
- *
- * @def IX_ATMDACC_WARNING
- *
- * @brief Warning return code
- *
- * This constant is used to tell IxAtmDAcc user about a special case.
- *
- */
-#define IX_ATMDACC_WARNING 2
-
-/**
- *
- * @ingroup IxAtmdAccAPI
- *
- * @def IX_ATMDACC_BUSY
- *
- * @brief Busy return code
- *
- * This constant is used to tell IxAtmDAcc user that the request
- * is correct, but cannot be processed because the IxAtmAcc resources
- * are already used. The user has to retry its request later
- *
- */
-#define IX_ATMDACC_BUSY 3
-
-/**
- *
- * @ingroup IxAtmdAccAPI
- *
- * @def IX_ATMDACC_RESOURCES_STILL_ALLOCATED
- *
- * @brief Disconnect return code
- *
- * This constant is used to tell IxAtmDAcc user that the disconnect
- * functions are not complete because the resources used by the driver
- * are not yet released. The user has to retry the disconnect call
- * later.
- *
- */
-#define IX_ATMDACC_RESOURCES_STILL_ALLOCATED 4
-
-/**
- *
- * @ingroup IxAtmdAccAPI
- *
- * @def IX_ATMDACC_DEFAULT_REPLENISH_COUNT
- *
- * @brief Default resources usage for RxVcFree replenish mechanism
- *
- * This constant is used to tell IxAtmDAcc to allocate and use
- * the minimum of resources for rx free replenish.
- *
- * @sa ixAtmdAccRxVcConnect
- */
-#define IX_ATMDACC_DEFAULT_REPLENISH_COUNT 0
-
-
-/**
- * @ingroup IxAtmdAccAPI
- *
- * @def IX_ATMDACC_OAM_TX_VPI
- *
- * @brief The reserved value used for the dedicated OAM
- * Tx connection. This "well known" value is used by atmdAcc and
- * its clients to dsicriminate the OAM channel, and should be chosen so
- * that it does not coencide with the VPI value used in an AAL0/AAL5 connection.
- * Any attempt to connect a service type other than OAM on this VPI will fail.
- *
- *
- */
-#define IX_ATMDACC_OAM_TX_VPI 0
-
-/**
- * @ingroup IxAtmdAccAPI
- *
- * @def IX_ATMDACC_OAM_TX_VCI
- *
- * @brief The reserved value used for the dedicated OAM
- * Tx connection. This "well known" value is used by atmdAcc and
- * its clients to dsicriminate the OAM channel, and should be chosen so
- * that it does not coencide with the VCI value used in an AAL0/AAL5 connection.
- * Any attempt to connect a service type other than OAM on this VCI will fail.
- */
-#define IX_ATMDACC_OAM_TX_VCI 0
-
-
- /**
- * @ingroup IxAtmdAccAPI
- *
- * @def IX_ATMDACC_OAM_RX_PORT
- *
- * @brief The reserved dummy PORT used for all dedicated OAM
- * Rx connections. Note that this is not a real port but must
- * have a value that lies within the valid range of port values.
- */
-#define IX_ATMDACC_OAM_RX_PORT IX_UTOPIA_PORT_0
-
- /**
- * @ingroup IxAtmdAccAPI
- *
- * @def IX_ATMDACC_OAM_RX_VPI
- *
- * @brief The reserved value value used for the dedicated OAM
- * Rx connection. This value should be chosen so that it does not
- * coencide with the VPI value used in an AAL0/AAL5 connection.
- * Any attempt to connect a service type other than OAM on this VPI will fail.
- */
-#define IX_ATMDACC_OAM_RX_VPI 0
-
-/**
- * @ingroup IxAtmdAccAPI
- *
- * @def IX_ATMDACC_OAM_RX_VCI
- *
- * @brief The reserved value value used for the dedicated OAM
- * Rx connection. This value should be chosen so that it does not
- * coencide with the VCI value used in an AAL0/AAL5 connection.
- * Any attempt to connect a service type other than OAM on this VCI will fail.
- */
-#define IX_ATMDACC_OAM_RX_VCI 0
-
-
-/**
- * @enum IxAtmdAccPduStatus
- *
- * @ingroup IxAtmdAccAPI
- *
- * @brief IxAtmdAcc Pdu status :
- *
- * IxAtmdAccPduStatus is used during a RX operation to indicate
- * the status of the received PDU
- *
- */
-
-typedef enum
-{
-    IX_ATMDACC_AAL0_VALID = 0,    /**< aal0 pdu */
-    IX_ATMDACC_OAM_VALID,         /**< OAM pdu */
-    IX_ATMDACC_AAL2_VALID,        /**< aal2 pdu @b reserved for future use */
-    IX_ATMDACC_AAL5_VALID,        /**< aal5 pdu complete and trailer is valid */
-    IX_ATMDACC_AAL5_PARTIAL,      /**< aal5 pdu not complete, trailer is missing */
-    IX_ATMDACC_AAL5_CRC_ERROR,    /**< aal5 pdu not complete, crc error/length error */
-    IX_ATMDACC_MBUF_RETURN        /**< empty buffer returned to the user */
-} IxAtmdAccPduStatus;
-
-
-/**
- *
- * @enum IxAtmdAccAalType
- *
- * @ingroup IxAtmdAccAPI
- *
- * @brief IxAtmdAcc AAL Service Type :
- *
- * IxAtmdAccAalType defines the type of traffic to run on this VC
- *
- */
-typedef enum
-{
-    IX_ATMDACC_AAL5,                /**< ITU-T AAL5 */
-    IX_ATMDACC_AAL2,                /**< ITU-T AAL2 @b reserved for future use */
-    IX_ATMDACC_AAL0_48,             /**< AAL0 48 byte payloads (cell header is added by NPE)*/
-    IX_ATMDACC_AAL0_52,             /**< AAL0 52 byte cell data (HEC is added by NPE) */
-    IX_ATMDACC_OAM,                 /**< OAM cell transport service (HEC is added by NPE)*/
-    IX_ATMDACC_MAX_SERVICE_TYPE     /**< not a service, used for parameter validation */
-} IxAtmdAccAalType;
-
-/**
- *
- * @enum IxAtmdAccClpStatus
- *
- * @ingroup IxAtmdAccAPI
- *
- * @brief IxAtmdAcc CLP indication
- *
- * IxAtmdAccClpStatus defines the CLP status of the current PDU
- *
- */
-typedef enum
-{
-    IX_ATMDACC_CLP_NOT_SET = 0,     /**< CLP indication is not set */
-    IX_ATMDACC_CLP_SET = 1     /**< CLP indication is set */
-} IxAtmdAccClpStatus;
-
-/**
- * @typedef IxAtmdAccUserId
- *
- * @ingroup IxAtmdAccAPI
- *
- * @brief User-supplied Id
- *
- * IxAtmdAccUserId is passed through callbacks and allows the
- * IxAtmdAcc user to identify the source of a call back. The range of
- * this user-owned Id is [0...2^32-1)].
- *
- * The user provides this own Ids on a per-channel basis as a parameter
- * in a call to @a ixAtmdAccRxVcConnect() or @a ixAtmdAccRxVcConnect()
- *
- * @sa ixAtmdAccRxVcConnect
- * @sa ixAtmdAccTxVcConnect
- *
- */
-typedef unsigned int IxAtmdAccUserId;
-
-/* ------------------------------------------------------
-   Part of the IxAtmdAcc interface related to RX traffic
-   ------------------------------------------------------ */
-
-/**
- *
- * @ingroup IxAtmdAccAPI
- *
- * @brief  Rx callback prototype
- *
- * IxAtmdAccRxVcRxCallback is the prototype of the Rx callback user
- * function called once per PDU to pass a receive Pdu to a user on a
- * partilcular connection. The callback is likely to push the mbufs
- * to a protocol layer, and recycle the mbufs for a further use.
- *
- * @note -This function is called ONLY in the context of
- *        the @a ixAtmdAccRxDispatch() function
- *
- * @sa ixAtmdAccRxDispatch
- * @sa ixAtmdAccRxVcConnect
- *
- * @param port @ref IxAtmLogicalPort [in] - the port on which this PDU was received
- *        a logical PHY port [@a IX_UTOPIA_PORT_0 .. @a IX_UTOPIA_MAX_PORTS - 1]
- * @param userId @ref IxAtmdAccUserId [in] - user Id provided in the call
- *        to @a ixAtmdAccRxVcConnect()
- * @param status @ref IxAtmdAccPduStatus [in] - an indication about the PDU validity.
- *        In the case of AAL0 the only possibile value is
- *        AAL0_VALID, in this case the client may optionally determine
- *        that an rx timeout occured by checking if the mbuf is
- *        compleletly or only partially filled, the later case
- *        indicating a timeout.
- *        In the case of OAM the only possible value is OAM valid.
- *        The status is set to @a IX_ATMDACC_MBUF_RETURN when
- *        the mbuf is released during a disconnect process.
- * @param clp @ref IxAtmdAccClpStatus [in] - clp indication for this PDU.
- *        For AAL5/AAL0_48 this information
- *        is set if the clp bit of any rx cell is set
- *        For AAL0-52/OAM the client may inspect the CLP in individual
- *        cell headers in the PDU, and this parameter is set to 0.
- * @param *mbufPtr @ref IX_OSAL_MBUF [in] - depending on the servive type a pointer to
- *        an mbuf (AAL5/AAL0/OAM) or mbuf chain (AAL5 only),
- *        that comprises the complete PDU data.
- *
- *        This parameter is guaranteed not to be a null pointer.
- *
- */
-typedef void (*IxAtmdAccRxVcRxCallback) (IxAtmLogicalPort port,
-                       IxAtmdAccUserId userId,
-                       IxAtmdAccPduStatus status,
-                       IxAtmdAccClpStatus clp,
-                       IX_OSAL_MBUF * mbufPtr);
-
-/**
- *
- * @ingroup IxAtmdAccAPI
- *
- * @brief Callback prototype for free buffer level is low.
- *
- * IxAtmdAccRxVcFreeLowCallback is the prototype of the user function
- * which get called on a per-VC basis, when more  mbufs are needed to
- * continue the ATM data reception. This function is likely to supply
- * more available mbufs by one or many calls to the replenish function
- * @a ixAtmdAccRxVcFreeReplenish()
- *
- * This function is called when the number of available buffers for
- * reception is going under the threshold level as defined
- * in @a ixAtmdAccRxVcFreeLowCallbackRegister()
- *
- * This function is called inside an Qmgr dispatch context. No system
- * resource or interrupt-unsafe feature should be used inside this
- * callback.
- *
- * @sa ixAtmdAccRxVcFreeLowCallbackRegister
- * @sa IxAtmdAccRxVcFreeLowCallback
- * @sa ixAtmdAccRxVcFreeReplenish
- * @sa ixAtmdAccRxVcFreeEntriesQuery
- * @sa ixAtmdAccRxVcConnect
- *
- * @param userId @ref IxAtmdAccUserId [in] - user Id provided in the call
- * to @a ixAtmdAccRxVcConnect()
- *
- * @return None
- *
- */
-typedef void (*IxAtmdAccRxVcFreeLowCallback) (IxAtmdAccUserId userId);
-
-/* ------------------------------------------------------
-   Part of the IxAtmdAcc interface related to TX traffic
-   ------------------------------------------------------ */
-
-/**
- *
- * @ingroup IxAtmdAccAPI
- *
- * @brief  Buffer callback prototype.
- *
- * This function is called to relinguish ownership of a transmitted
- * buffer chain to the user.
- *
- * @note -In the case of a chained mbuf the AmtdAcc component can
- * chain many user buffers together and pass ownership to the user in
- * one function call.
- *
- * @param userId @ref IxAtmdAccUserId [in] - user If provided at registration of this
- *        callback.
- * @param mbufPtr @ref IX_OSAL_MBUF [in] - a pointer to mbufs or chain of mbufs and is
- *        guaranteed not to be a null pointer.
- *
- */
-typedef void (*IxAtmdAccTxVcBufferReturnCallback) (IxAtmdAccUserId userId,
-                        IX_OSAL_MBUF * mbufPtr);
-
-/* ------------------------------------------------------
-   Part of the IxAtmdAcc interface related to Initialisation
-   ------------------------------------------------------ */
-
-/**
- *
- * @ingroup IxAtmdAccAPI
- *
- * @fn ixAtmdAccInit (void)
- *
- * @brief Initialise the IxAtmdAcc Component
- *
- * This function initialise the IxAtmdAcc component. This function shall
- * be called before any other function of the API. Its role is to
- * initialise all internal resources of the IxAtmdAcc component.
- *
- * The ixQmgr component needs to be initialized prior the use of
- * @a ixAtmdAccInit()
- *
- * @param none
- *
- * Failing to initilialize the IxAtmdAcc API before any use of it will
- * result in a failed status.
- * If the specified component is not present, a success status will still be 
- * returned, however, a warning indicating the NPE to download to is not
- * present will be issued.
- *
- * @return @li IX_SUCCESS initialisation is complete (in case of component not
- *             being present, a warning is clearly indicated)
- * @return @li IX_FAIL unable to process this request either
- *             because this IxAtmdAcc is already initialised
- *             or some unspecified error has occrred.
- */
-PUBLIC IX_STATUS ixAtmdAccInit (void);
-
-/**
- *
- * @ingroup IxAtmdAccAPI
- *
- * @fn ixAtmdAccShow (void)
- *
- * @brief Show IxAtmdAcc configuration on a per port basis
- *
- * @param none
- *
- * @return none
- *
- * @note - Display use printf() and are redirected to stdout
- */
-PUBLIC void
-ixAtmdAccShow (void);
-
-/**
- *
- * @ingroup IxAtmdAccAPI
- * 
- * @fn ixAtmdAccStatsShow (void)
- *
- * @brief Show all IxAtmdAcc stats
- *
- * @param none
- *
- * @return none
- *
- * @note - Stats display use printf() and are redirected to stdout
- */
-PUBLIC void
-ixAtmdAccStatsShow (void);
-
-/**
- *
- * @ingroup IxAtmdAccAPI
- *
- * @fn ixAtmdAccStatsReset (void)
- *
- * @brief Reset all IxAtmdAcc stats
- *
- * @param none
- *
- * @return none
- *
- */
-PUBLIC void
-ixAtmdAccStatsReset (void);
-
-/* ------------------------------------------------------
-   Part of the IxAtmdAcc interface related to RX traffic
-   ------------------------------------------------------ */
-
-/**
- *
- * @ingroup IxAtmdAccAPI
- *
- * @fn ixAtmdAccRxVcConnect (IxAtmLogicalPort port,
-                      unsigned int vpi,
-                      unsigned int vci,
-                      IxAtmdAccAalType aalServiceType,
-                      IxAtmRxQueueId rxQueueId,
-                      IxAtmdAccUserId userCallbackId,
-                      IxAtmdAccRxVcRxCallback rxCallback,
-                      unsigned int minimumReplenishCount,
-                      IxAtmConnId * connIdPtr,
-                      IxAtmNpeRxVcId * npeVcIdPtr )
- *
- * @brief Connect to a Aal Pdu receive service for a particular
- *        port/vpi/vci, and service type.
- *
- * This function allows a user to connect to an Aal5/Aal0/OAM Pdu receive service
- * for a particular port/vpi/vci. It registers the callback and allocates
- * internal resources and a Connection Id to be used in further API calls
- * related to this VCC.
- *
- * The function will setup VC receive service on the specified rx queue.
- *
- * This function is blocking and makes use internal locks, and hence
- * should not be called from an interrupt context.
- *
- * On return from @a ixAtmdAccRxVcConnect() with a failure status, the
- * connection Id parameter is unspecified. Its value cannot be used.
- * A connId is the reference by which IxAtmdAcc refers to a
- * connected VC. This identifier is the result of a succesful call
- * to a connect function. This identifier is invalid after a
- * sucessful call to a disconnect function.
- *
- * Calling this function for the same combination of Vpi, Vci and more
- * than once without calling @a ixAtmdAccRxVcTryDisconnect() will result in a
- * failure status.
- *
- * If this function returns success the user should supply receive
- * buffers by calling @a ixAtmdAccRxVcFreeReplenish() and then call
- * @a ixAtmdAccRxVcEnable() to begin receiving pdus.
- *
- * There is a choice of two receive Qs on which the VC pdus could be
- * receive. The user must associate the VC with one of these. Essentially
- * having two qs allows more flexible system configuration such as have
- * high prioriy traffic on one q (e.g. voice) and low priority traffic on
- * the other (e.g. data). The high priority Q could be serviced in
- * preference to the low priority Q. One queue may be configured to be
- * serviced as soon as there is traffic, the other queue may be configured
- * to be serviced by a polling mechanism running at idle time.
- *
- * Two AAL0 services supporting 48 or 52 byte cell data are provided.
- * Received AAL0 PDUs will be be a multiple of the cell data size (48/52).
- * AAL0_52 is a raw cell service and includes an ATM cell header
- * (excluding HEC) at the start of each cell.
- *
- * A single "OAM Rx channel" for all ports may be  enabled by
- * establishing a dedicated OAM Rx connection.
- *
- * The OAM service allows buffers containing 52 byte OAM F4/F5 cells
- * to be transmitted and received over the dedicated OAM channels.
- * HEC is appended/removed, and CRC-10 performed by the NPE. The OAM
- * service offered by AtmdAcc is a raw cell transport service.
- * It is assumed that ITU I.610 procedures that make use of this
- * service are implemented above AtmdAcc.
- *
- * Note that the dedicated OAM connections are established on
- * reserved VPI,VCI, and (in the case of Rx) port values.
- * These values are used purely to descriminate the dedicated OAM channels
- * and do not identify a particular OAM F4/F5 flow. F4/F5 flows may be
- * realised for particluar VPI/VCIs by manipulating the VPI,VCI
- * fields of the ATM cell headers of cells in the buffers passed
- * to AtmdAcc.
- *
- * Calling this function prior to enable the port will fail.
- *
- * @sa ixAtmdAccRxDispatch
- * @sa ixAtmdAccRxVcEnable
- * @sa ixAtmdAccRxVcDisable
- * @sa ixAtmdAccRxVcTryDisconnect
- * @sa ixAtmdAccPortEnable
- *
- * @param port @ref IxAtmLogicalPort [in] - VC identification : logical PHY port
- *                  [@a IX_UTOPIA_PORT_0 .. @a IX_UTOPIA_MAX_PORTS - 1]
- * @param vpi unsigned int [in] - VC identification : ATM Vpi [0..255] or IX_ATMDACC_OAM_VPI
- * @param vci unsigned int [in] - VC identification : ATM Vci [0..65535] or IX_ATMDACC_OAM_VCI
- * @param aalServiceType @ref IxAtmdAccAalType [in] - type of service: AAL5, AAL0_48, AAL0_52, or OAM
- * @param rxQueueId @ref IxAtmRxQueueId [in] - this identifieds which of two Qs the VC
- *     should use.when icoming traffic is processed
- * @param userCallbackId @ref IxAtmdAccUserId [in] - user Id used later as a parameter to
- *     the supplied rxCallback.
- * @param rxCallback [in] @ref IxAtmdAccRxVxRxCallback - function called when mbufs are received.
- *     This parameter cannot be a null pointer.
- * @param bufferFreeCallback [in] - function to be called to return
- *     ownership of buffers to IxAtmdAcc user.
- * @param minimumReplenishCount unsigned int [in] -  For AAL5/AAL0 the number of free mbufs
- *     to be used with this channel. Use a high number when the expected traffic
- *     rate on this channel is high, or when the user's mbufs are small, or when
- *     the RxVcFreeLow Notification has to be invoked less often. When this
- *     value is IX_ATMDACC_DEFAULT_REPLENISH_COUNT, the minimum of
- *     resources  will be used. Depending on traffic rate, pdu
- *     size and mbuf size, rxfree queue size, polling/interrupt rate, this value may
- *     require to be replaced by a different value in the range 1-128
- *     For OAM the rxFree queue size is fixed by atmdAcc and this parameter is ignored.
- * @param connIdPtr @ref IxAtmConnId [out] - pointer to a connection Id
- *     This parameter cannot be a null pointer.
- * @param npeVcIdPtr @ref IxAtmNpeRxVcId [out] - pointer to an npe Vc Id
- *     This parameter cannot be a null pointer.
- *
- * @return @li IX_SUCCESS successful call to IxAtmdAccRxVcConnect
- * @return @li IX_ATMDACC_BUSY cannot process this request :
- *         no VC is available
- * @return @li IX_FAIL
- *             parameter error,
- *             VC already in use,
- *             attempt to connect AAL service on reserved OAM VPI/VCI,
- *             attempt to connect OAM service on VPI/VCI other than the reserved OAM VPI/VCI,
- *             port is not initialised,
- *             or some other error occurs during processing.
- *
- */
-PUBLIC IX_STATUS ixAtmdAccRxVcConnect (IxAtmLogicalPort port,
-                      unsigned int vpi,
-                      unsigned int vci,
-                      IxAtmdAccAalType aalServiceType,
-                      IxAtmRxQueueId rxQueueId,
-                      IxAtmdAccUserId userCallbackId,
-                      IxAtmdAccRxVcRxCallback rxCallback,
-                      unsigned int minimumReplenishCount,
-                      IxAtmConnId * connIdPtr,
-                      IxAtmNpeRxVcId * npeVcIdPtr );
-
-/**
- *
- * @ingroup IxAtmdAccAPI
- * 
- * @fn ixAtmdAccRxVcFreeReplenish (IxAtmConnId connId,
-                        IX_OSAL_MBUF * mbufPtr)
- *
- * @brief Provide free mbufs for data reception on a connection.
- *
- * This function provides mbufs for data reception by the hardware. This
- * function needs to be called by the user on a regular basis to ensure
- * no packet loss. Providing free buffers is a connection-based feature;
- * each connection can have different requirements in terms of buffer size
- * number of buffers, recycling rate. This function could be invoked from
- * within the context of a @a IxAtmdAccRxVcFreeLowCallback() callback
- * for a particular VC
- *
- * Mbufs provided through this function call can be chained. They will be
- * unchained internally. A call to this function with chained mbufs or
- * multiple calls with unchained mbufs are equivalent, but calls with
- * unchained mbufs are more efficients.
- *
- * Mbufs provided to this interface need to be able to hold at least one
- * full cell payload (48/52 bytes, depending on service type).
- * Chained buffers with a size less than the size supported by the hardware
- * will be returned through the rx callback provided during the connect step.
- *
- * Failing to invoke this function prior to enabling the RX traffic
- * can result in packet loss.
- *
- * This function is not reentrant for the same connId.
- *
- * This function does not use system resources and can be
- * invoked from an interrupt context.
- *
- * @note - Over replenish is detected, and extra mbufs are returned through
- *         the rx callback provided during the connect step.
- *
- * @note - Mbuf provided to the replenish function should have a length greater or
- *         equal to 48/52 bytes according to service type.
- *
- * @note - The memory cache of mMbuf payload should be invalidated prior to Mbuf
- *         submission. Flushing the Mbuf headers is handled by IxAtmdAcc.
- *
- * @note - When a chained mbuf is provided, this function process the mbufs
- *         up to the hardware limit and invokes the user-supplied callback
- *         to release extra buffers.
- *
- * @sa ixAtmdAccRxVcFreeLowCallbackRegister
- * @sa IxAtmdAccRxVcFreeLowCallback
- * @sa ixAtmdAccRxVcConnect
- *
- * @param connId @ref IxAtmConnId [in] - connection Id as returned from a succesfull call to
- *        @a IxAtmdAccRxVcConnect()
- * @param mbufPtr @ref IX_OSAL_MBUF [in] - pointer to a mbuf structure to be used for data
- *        reception. The mbuf pointed to by this parameter can be chained
- *        to an other mbuf.
- *
- * @return @li IX_SUCCESS successful call to @a ixAtmdAccRxVcFreeReplenish()
- *          and the mbuf is now ready to use for incoming traffic.
- * @return @li IX_ATMDACC_BUSY cannot process this request because
- *         the max number of outstanding free buffers has been reached
- *         or the internal resources have exhausted for this VC.
- *         The user is responsible for retrying this request later.
- * @return @li IX_FAIL cannot process this request because of parameter
- *         errors or some unspecified internal error has occurred.
- *
- * @note - It is not always guaranteed the replenish step to be as fast as the
- *   hardware is consuming Rx Free mbufs. There is nothing in IxAtmdAcc to
- *   guarantee that replenish reaches the rxFree threshold level. If the
- *   threshold level is not reached, the next rxFree low notification for
- *   this channel will not be triggered.
- *   The preferred ways to replenish can be as follows (depending on
- *   applications and implementations) :
- *   @li Replenish in a rxFree low notification until the function
- *       ixAtmdAccRxVcFreeReplenish() returns IX_ATMDACC_BUSY
- *   @li Query the queue level using @sa ixAtmdAccRxVcFreeEntriesQuery, then
- *     , replenish using @a ixAtmdAccRxVcFreeReplenish(), then query the queue
- *       level again, and replenish if the threshold is still not reached.
- *   @li Trigger replenish from an other event source and use rxFree starvation
- *       to throttle the Rx traffic.
- *
- */
-PUBLIC IX_STATUS ixAtmdAccRxVcFreeReplenish (IxAtmConnId connId,
-                        IX_OSAL_MBUF * mbufPtr);
-
-/**
- *
- * @ingroup IxAtmdAccAPI
- * 
- * @fn ixAtmdAccRxVcFreeLowCallbackRegister (IxAtmConnId connId,
-                                    unsigned int numberOfMbufs,
-                                    IxAtmdAccRxVcFreeLowCallback callback)
- *
- * @brief Configure the RX Free threshold value and register a callback
- * to handle threshold notifications.
- *
- * The function ixAtmdAccRxVcFreeLowCallbackRegister sets the threshold value for
- * a particular RX VC. When the number of buffers reaches this threshold
- * the callback is invoked.
- *
- * This function should be called once per VC before RX traffic is
- * enabled.This function will fail if the curent level of the free buffers
- * is equal or less than the threshold value.
- *
- * @sa ixAtmdAccRxVcFreeLowCallbackRegister
- * @sa IxAtmdAccRxVcFreeLowCallback
- * @sa ixAtmdAccRxVcFreeReplenish
- * @sa ixAtmdAccRxVcFreeEntriesQuery
- * @sa ixAtmdAccRxVcConnect
- *
- * @param connId @ref IxAtmConnId [in] - connection Id as resulted from a succesfull call
- *        to @a IxAtmdAccRxVcConnect()
- * @param numberOfMbufs unsigned int [in] - threshold number of buffers. This number
- *        has to be a power of 2, one of the values 0,1,2,4,8,16,32....
- *        The maximum value cannot be more than half of the rxFree queue
- *        size (which can be retrieved using @a ixAtmdAccRxVcFreeEntriesQuery()
- *        before any use of the @a ixAtmdAccRxVcFreeReplenish() function)
- * @param callback @ref IxAtmdAccRxVcFreeLowCallback [in] - function telling the user that the number of
- *        free buffers has reduced to the threshold value.
- *
- * @return @li IX_SUCCESS Threshold set successfully.
- * @return @li IX_FAIL parameter error or the current number of free buffers
- *              is less than or equal to the threshold supplied or some
- *              unspecified error has occrred.
- *
- * @note - the callback will be called when the threshold level will drop from
- *        exactly (numberOfMbufs + 1) to (numberOfMbufs).
- *
- */
-PUBLIC IX_STATUS ixAtmdAccRxVcFreeLowCallbackRegister (IxAtmConnId connId,
-    unsigned int numberOfMbufs,
-    IxAtmdAccRxVcFreeLowCallback callback);
-
-/**
- *
- * @ingroup IxAtmdAccAPI
- *
- * @fn ixAtmdAccRxVcFreeEntriesQuery (IxAtmConnId connId,
-                         unsigned int *numberOfMbufsPtr)
- *
- * @brief Get the number of rx mbufs the system can accept to replenish the
- *       the rx reception mechanism on a particular channel
- *
- * The ixAtmdAccRxVcFreeEntriesQuery function is used to retrieve the current
- * number of available mbuf entries for reception, on a per-VC basis. This
- * function can be used to know the number of mbufs which can be provided
- * using @a ixAtmdAccRxVcFreeReplenish().
- *
- * This function can be used from a timer context, or can be associated
- * with a threshold event, or can be used inside an active polling
- * mechanism which is under user control.
- *
- * This function is reentrant and does not use system resources and can
- * be invoked from an interrupt context.
- *
- * @param connId @ref IxAtmConnId [in] - connection Id as resulted from a succesfull call
- *        to @a IxAtmdAccRxVcConnect()
- * @param numberOfMbufsPtr unsigned int [out] - Pointer to the number of available entries.
- *      . This parameter cannot be a null pointer.
- *
- * @return @li IX_SUCCESS the current number of mbufs not yet used for incoming traffic
- * @return @li IX_FAIL invalid parameter
- *
- * @sa ixAtmdAccRxVcFreeReplenish
- *
- */
-PUBLIC IX_STATUS ixAtmdAccRxVcFreeEntriesQuery (IxAtmConnId connId,
-                         unsigned int *numberOfMbufsPtr);
-
-/**
- *
- * @ingroup IxAtmdAccAPI
- *
- * @fn ixAtmdAccRxVcEnable (IxAtmConnId connId)
- *
- * @brief Start the RX service on a VC.
- *
- * This functions kicks-off the traffic reception for a particular VC.
- * Once invoked, incoming PDUs will be made available by the hardware
- * and are eventually directed to the @a IxAtmdAccRxVcRxCallback() callback
- * registered for the connection.
- *
- * If the traffic is already running, this function returns IX_SUCCESS.
- * This function can be invoked many times.
- *
- * IxAtmdAccRxVcFreeLowCallback event will occur only after
- * @a ixAtmdAccRxVcEnable() function is invoked.
- *
- * Before using this function, the @a ixAtmdAccRxVcFreeReplenish() function
- * has to be used to replenish the RX Free queue. If not, incoming traffic
- * may be discarded.and in the case of interrupt driven reception the
- * @a IxAtmdAccRxVcFreeLowCallback() callback may be invoked as a side effect
- * during a replenish action.
- *
- * This function is not reentrant and should not be used inside an
- * interrupt context.
- *
- * For an VC connection this function can be called after a call to
- * @a ixAtmdAccRxVcDisable() and should not be called after
- * @a ixAtmdAccRxVcTryDisconnect()
- *
- * @sa ixAtmdAccRxVcDisable
- * @sa ixAtmdAccRxVcConnect
- * @sa ixAtmdAccRxVcFreeReplenish
- *
- * @param connId @ref IxAtmConnId [in] - connection Id as resulted from a succesfull call
- * to @a IxAtmdAccRxVcConnect()
- *
- * @return @li IX_SUCCESS successful call to ixAtmdAccRxVcEnable
- * @return @li IX_ATMDACC_WARNING the channel is already enabled
- * @return @li IX_FAIL invalid parameters or some unspecified internal
- *         error occured.
- *
- */
-PUBLIC IX_STATUS ixAtmdAccRxVcEnable (IxAtmConnId connId);
-
-/**
- *
- * @ingroup IxAtmdAccAPI
- * 
- * @fn ixAtmdAccRxVcDisable (IxAtmConnId connId)
- *
- * @brief Stop the RX service on a VC.
- *
- * This functions stops the traffic reception for a particular VC connection.
- *
- * Once invoked, incoming Pdus are discarded by the hardware. Any Pdus
- * pending will be freed to the user
- *
- * Hence once this function returns no more receive callbacks will be
- * called for that VC. However, buffer free callbacks will be invoked
- * until such time as all buffers supplied by the user have been freed
- * back to the user
- *
- * Calling this function doe not invalidate the connId.
- * @a ixAtmdAccRxVcEnable() can be invoked to enable Pdu reception again.
- *
- * If the traffic is already stopped, this function returns IX_SUCCESS.
- *
- * This function is not reentrant and should not be used inside an
- * interrupt context.
- *
- * @sa ixAtmdAccRxVcConnect
- * @sa ixAtmdAccRxVcEnable
- * @sa ixAtmdAccRxVcDisable
- *
- * @param connId @ref IxAtmConnId [in] - connection Id as resulted from a succesfull call to @a
- *     IxAtmdAccRxVcConnect()
- *
- * @return @li IX_SUCCESS successful call to @a ixAtmdAccRxVcDisable().
- * @return @li IX_ATMDACC_WARNING the channel is already disabled
- * @return @li IX_FAIL invalid parameters or some unspecified internal error occured
- *
- */
-PUBLIC IX_STATUS ixAtmdAccRxVcDisable (IxAtmConnId connId);
-
-/**
- *
- * @ingroup IxAtmdAccAPI
- * 
- * @fn ixAtmdAccRxVcTryDisconnect (IxAtmConnId connId)
- *
- * @brief Disconnect a VC from the RX service.
- *
- * This function deregisters the VC and guarantees that all resources
- * associated with this VC are free. After its execution, the connection
- * Id is not available.
- *
- * This function will fail until such time as all resources allocated to
- * the VC connection have been freed. The user is responsible to delay and
- * call again this function many times until a success status is returned.
- *
- * This function needs internal locks and should not be called from an
- * interrupt context
- *
- * @param connId @ref IxAtmConnId [in] - connection Id as resulted from a succesfull call to
- * @a IxAtmdAccRxVcConnect()
- *
- * @return @li IX_SUCCESS successful call to ixAtmdAccRxVcDisable
- * @return @li IX_ATMDACC_RESOURCES_STILL_ALLOCATED not all resources
- *         associated with the connection have been freed.
- * @return @li IX_FAIL cannot process this request because of a parameter
- *         error
- *
- */
-PUBLIC IX_STATUS ixAtmdAccRxVcTryDisconnect (IxAtmConnId connId);
-
-/* ------------------------------------------------------
-   Part of the IxAtmdAcc interface related to TX traffic
-   ------------------------------------------------------ */
-
-/**
- *
- * @ingroup IxAtmdAccAPI
- * 
- * @fn ixAtmdAccTxVcConnect (IxAtmLogicalPort port,
-                      unsigned int vpi,
-                      unsigned int vci,
-                      IxAtmdAccAalType aalServiceType,
-                      IxAtmdAccUserId userId,
-                      IxAtmdAccTxVcBufferReturnCallback bufferFreeCallback,
-                      IxAtmConnId * connIdPtr)
- *
- * @brief Connect to a Aal Pdu transmit service for a particular
- *        port/vpi/vci and service type.
- *
- * This function allows a user to connect to an Aal5/Aal0/OAM Pdu transmit service
- * for a particular port/vpi/vci. It registers the callback and allocates
- * internal resources and a Connection Id to be used in further API calls
- * related to this VC.
- *
- * The function will setup VC transmit service on the specified on the
- * specified port. A connId is the reference by which IxAtmdAcc refers to a
- * connected VC. This identifier is the result of a succesful call
- * to a connect function. This identifier is invalid after a
- * sucessful call to a disconnect function.
- *
- * This function needs internal locks, and hence  should not be called
- * from an interrupt context.
- *
- * On return from @a ixAtmdAccTxVcConnect() with a failure status, the
- * connection Id parameter is unspecified. Its value cannot be used.
- *
- * Calling this function for the same combination of port, Vpi, Vci and
- * more than once without calling @a ixAtmdAccTxVcTryDisconnect() will result
- * in a failure status.
- *
- * Two AAL0 services supporting 48 or 52 byte cell data are provided.
- * Submitted AAL0 PDUs must be a multiple of the cell data size (48/52).
- * AAL0_52 is a raw cell service the client must format
- * the PDU with an ATM cell header (excluding HEC) at the start of
- * each cell, note that AtmdAcc does not validate the cell headers in
- * a submitted PDU.
- *
- * For the OAM service an "OAM Tx channel" may be enabled for a port
- * by establishing a single dedicated OAM Tx connection on that port.
- *
- * The OAM service allows buffers containing 52 byte OAM F4/F5 cells
- * to be transmitted and received over the dedicated OAM channels.
- * HEC is appended/removed, and CRC-10 performed by the NPE. The OAM
- * service offered by AtmdAcc is a raw cell transport service.
- * It is assumed that ITU I.610 procedures that make use of this
- * service are implemented above AtmdAcc.
- *
- * Note that the dedicated OAM connections are established on
- * reserved VPI,VCI, and (in the case of Rx) port values.
- * These values are used purely to descriminate the dedicated OAM channels
- * and do not identify a particular OAM F4/F5 flow. F4/F5 flows may be
- * realised for particluar VPI/VCIs by manipulating the VPI,VCI
- * fields of the ATM cell headers of cells in the buffers passed
- * to AtmdAcc.
- *
- * Calling this function before enabling the port will fail.
- *
- * @sa ixAtmdAccTxVcTryDisconnect
- * @sa ixAtmdAccPortTxScheduledModeEnable
- * @sa ixAtmdAccPortEnable
- *
- * @param port @ref IxAtmLogicalPort [in] - VC identification : logical PHY port
- *                  [@a IX_UTOPIA_PORT_0 .. @a IX_UTOPIA_MAX_PORTS - 1]
- * @param vpi unsigned int  [in] - VC identification : ATM Vpi [0..255] or IX_ATMDACC_OAM_VPI
- * @param vci unsigned int [in] - VC identification : ATM Vci [0..65535] or IX_ATMDACC_OAM_VCI
- * @param aalServiceType @ref IxAtmdAccAalType [in] - type of service AAL5, AAL0_48, AAL0_52, or OAM
- * @param userId @ref IxAtmdAccUserId [in] - user id to be used later during callbacks related
- *        to this channel
- * @param bufferFreeCallback @ref IxAtmdAccTxVcBufferReturnCallback [in] - function called when mbufs
- *        transmission is complete. This parameter cannot be a null
- *        pointer.
- * @param connIdPtr @ref IxAtmConnId [out] - Pointer to a connection Id.
- *        This parameter cannot be a null pointer.
- *
- * @return @li IX_SUCCESS successful call to @a IxAtmdAccRxVcConnect().
- * @return @li IX_ATMDACC_BUSY cannot process this request
- *         because no VC is available
- * @return @li IX_FAIL
- *             parameter error,
- *             VC already in use,
- *             attempt to connect AAL service on reserved OAM VPI/VCI,
- *             attempt to connect OAM service on VPI/VCI other than the reserved OAM VPI/VCI,
- *             port is not initialised,
- *             or some other error occurs during processing.
- *
- * @note - Unscheduled mode is not supported in ixp425 1.0. Therefore, the
- *       function @a ixAtmdAccPortTxScheduledModeEnable() need to be called
- *       for this port before any establishing a Tx Connection
- */
-PUBLIC IX_STATUS ixAtmdAccTxVcConnect (IxAtmLogicalPort port,
-                      unsigned int vpi,
-                      unsigned int vci,
-                      IxAtmdAccAalType aalServiceType,
-                      IxAtmdAccUserId userId,
-                      IxAtmdAccTxVcBufferReturnCallback bufferFreeCallback,
-                      IxAtmConnId * connIdPtr);
-
-/**
- *
- * @ingroup IxAtmdAccAPI
- *
- * @fn ixAtmdAccTxVcPduSubmit (IxAtmConnId connId,
-                    IX_OSAL_MBUF * mbufPtr,
-                    IxAtmdAccClpStatus clp,
-                    unsigned int numberOfCells)
- *
- * @brief Submit a Pdu for transmission on connection.
- *
- * A data user calls this function to submit an mbufs containing a Pdu
- * to be transmitted. The buffer supplied can be chained and the Pdu it
- * contains must be complete.
- *
- * The transmission behavior of this call depends on the operational mode
- * of the port on which the connection is made.
- *
- * In unscheduled mode the mbuf will be submitted to the hardware
- * immediately if sufficent resource is available. Otherwise the function
- * will return failure.
- *
- * In scheduled mode the buffer is queued internally in IxAtmdAcc. The cell
- * demand is made known to the traffic shaping entity. Cells from the
- * buffers are MUXed onto the port some time later as dictated by the
- * traffic shaping entity. The traffic shaping entity does this by sending
- * transmit schedules to IxAtmdAcc via @a ixAtmdAccPortTxProcess() function call.
- *
- * Note that the dedicated OAM channel is scheduled just like any
- * other channel. This means that any OAM traffic relating to an
- * active AAL0/AAL5 connection will be scheduled independantly of the
- * AAL0/AAL5 traffic for that connection.
- *
- * When transmission is complete, the TX Done mechanism will give the
- * owmnership of these buffers back to the customer. The tx done mechanism
- * must be in operation before transmission is attempted.
- *
- * For AAL0/OAM submitted AAL0 PDUs must be a multiple of the cell data
- * size (48/52). AAL0_52 and OAM are raw cell services, and the client
- * must format the PDU with an ATM cell header (excluding HEC) at the
- * start of each cell, note that AtmdAcc does not validate the cell headers in
- * a submitted PDU.
- *
- *
- * @sa IxAtmdAccTxVcBufferReturnCallback
- * @sa ixAtmdAccTxDoneDispatch
- *
- * @param connId @ref IxAtmConnId [in] - connection Id as resulted from a succesfull call to
- *        @a ixAtmdAccTxVcConnect()
- * @param mbufPtr @ref IX_OSAL_MBUF [in] - pointer to a chained structure of mbufs to transmit.
- *       This parameter cannot be a null pointer.
- * @param clp @ref IxAtmdAccClpStatus [in] - clp indication for this PDU. All cells of this pdu
- *       will be sent with the clp bit set
- * @param numberOfCells unsigned int [in] - number of cells in the PDU.
- *
- * @return @li IX_SUCCESS successful call to @a ixAtmdAccTxVcPduSubmit()
- *             The pdu pointed by the mbufPtr parameter will be
- *             transmitted
- * @return @li IX_ATMDACC_BUSY unable to process this request because
- *             internal resources are all used. The caller is responsible
- *             for retrying this request later.
- * @return @li IX_FAIL unable to process this request because of error
- *             in the parameters (wrong connId supplied,
- *             or wrong mbuf pointer supplied), the total length of all buffers
- *             in the chain should be a multiple of the cell size
- *             ( 48/52 depending on the service type ),
- *             or unspecified error during processing
- *
- * @note - This function in not re-entrant for the same VC (e.g. : two
- *         thread cannot send PDUs for the same VC). But two threads can
- *         safely call this function with a different connection Id
- *
- * @note - In unscheduled mode, this function is not re-entrant on a per
- *         port basis. The size of pdus is limited to 8Kb.
- *
- * @note - 0-length mbufs should be removed from the chain before submission.
- *         The total length of the pdu (sdu + padding +trailer) has to be
- *         updated in the header of the first mbuf of a chain of mbufs.
- *
- * @note - Aal5 trailer information (UUI, CPI, SDU length) has to be supplied
- *         before submission.
- *
- * @note - The payload memory cache should be flushed, if needed, prior to
- *         transmission. Mbuf headers are flushed by IxAtmdAcc
- *
- * @note - This function does not use system resources and can be used
- *         inside an interrupt context
- */
-PUBLIC IX_STATUS ixAtmdAccTxVcPduSubmit (IxAtmConnId connId,
-                    IX_OSAL_MBUF * mbufPtr,
-                    IxAtmdAccClpStatus clp,
-                    unsigned int numberOfCells);
-
-/**
- *
- * @ingroup IxAtmdAccAPI
- *
- * @fn ixAtmdAccTxVcTryDisconnect (IxAtmConnId connId)
- *
- * @brief Disconnect from a Aal Pdu transmit service for a particular
- *        port/vpi/vci.
- *
- * This function deregisters the VC and guarantees that all resources
- * associated with this VC are free. After its execution, the connection
- * Id is not available.
- *
- * This function will fail until such time as all resources allocated to
- * the VC connection have been freed. The user is responsible to delay
- * and call again this function many times until a success status is
- * returned.
- *
- * After its execution, the connection Id is not available.
- *
- * @param connId @ref IxAtmConnId [in] - connection Id as resulted from a succesfull call to
- *        @a ixAtmdAccTxVcConnect()
- *
- * @return @li IX_SUCCESS successful call to @a ixAtmdAccTxVcTryDisconnect()
- * @return @li IX_ATMDACC_RESOURCES_STILL_ALLOCATED not all resources
- *     associated with the connection have been freed. This condition will
- *     disappear after Tx and TxDone is complete for this channel.
- * @return @li IX_FAIL unable to process this request because of errors
- *                     in the parameters (wrong connId supplied)
- *
- * @note - This function needs internal locks and should not be called
- *         from an interrupt context
- *
- * @note - If the @a IX_ATMDACC_RESOURCES_STILL_ALLOCATED error does not
- *     clear after a while, this may be linked to a previous problem
- *     of cell overscheduling. Diabling the port and retry a disconnect
- *     will free the resources associated with this channel.
- *
- * @sa ixAtmdAccPortTxProcess
- *
- */
-PUBLIC IX_STATUS ixAtmdAccTxVcTryDisconnect (IxAtmConnId connId);
-
-#endif /* IXATMDACC_H */
-
-/**
- * @} defgroup IxAtmdAccAPI
- */
-
-
diff --git a/arch/arm/cpu/ixp/npe/include/IxAtmdAccCtrl.h b/arch/arm/cpu/ixp/npe/include/IxAtmdAccCtrl.h
deleted file mode 100644
index e223049..0000000
--- a/arch/arm/cpu/ixp/npe/include/IxAtmdAccCtrl.h
+++ /dev/null
@@ -1,1958 +0,0 @@
-
-/**
- * @file    IxAtmdAccCtrl.h
- *
- * @date    20-Mar-2002
- *
- * @brief IxAtmdAcc Public API
- *
- * This file contains the public API of IxAtmdAcc, related to the
- * control functions of the component.
- *
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- * 
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- * 
- * @par
- * -- End of Copyright Notice --
- */
-
-/* ------------------------------------------------------
-   Doxygen group definitions
-   ------------------------------------------------------ */
-
-/**
- *
- * @defgroup IxAtmdAccCtrlAPI IXP400 ATM Driver Access (IxAtmdAcc) Control API
- *
- * @brief The public API for the IXP400 Atm Driver Control component
- *
- * IxAtmdAcc is the low level interface by which AAL PDU get transmitted
- * to,and received from the Utopia bus
- *
- * This part is related to the Control configuration
- *
- * @{
- */
-
-#ifndef IXATMDACCCTRL_H
-#define IXATMDACCCTRL_H
-
-#include "IxAtmdAcc.h"
-
-/* ------------------------------------------------------
-   AtmdAccCtrl Data Types definition
-   ------------------------------------------------------ */
-
-/**
-*
-* @ingroup IxAtmdAccCtrlAPI
-*
-* @def IX_ATMDACC_PORT_DISABLE_IN_PROGRESS
-*
-* @brief Port enable return code
-*
-* This constant is used to tell IxAtmDAcc user that the port disable
-* functions are not complete. The user can call ixAtmdAccPortDisableComplete()
-* to find out when the disable has finished. The port enable can then proceed.
-*
-*/
-#define IX_ATMDACC_PORT_DISABLE_IN_PROGRESS 5
-
-/**
-*
-* @ingroup IxAtmdAccCtrlAPI
-*
-* @def IX_ATMDACC_ALLPDUS
-*
-* @brief All PDUs
-*
-* This constant is used to tell IxAtmDAcc to process all PDUs from
-* the RX queue or the TX Done
-*
-* @sa IxAtmdAccRxDispatcher
-* @sa IxAtmdAccTxDoneDispatcher
-*
-*/
-#define IX_ATMDACC_ALLPDUS 0xffffffff
-
-/* ------------------------------------------------------
-   Part of the IxAtmdAcc interface related to RX traffic
-   ------------------------------------------------------ */
-
-/**
- *
- * @ingroup IxAtmdAccCtrlAPI
- *
- * @brief Callback prototype for notification of available PDUs for
- * an Rx Q.
- *
- * This a protoype for a function which is called when there is at
- * least one Pdu available for processing on a particular Rx Q.
- *
- * This function should call @a ixAtmdAccRxDispatch() with
- * the aprropriate number of parameters to read and process the Rx Q.
- *
- * @sa ixAtmdAccRxDispatch
- * @sa ixAtmdAccRxVcConnect
- * @sa ixAtmdAccRxDispatcherRegister
- *
- * @param rxQueueId @ref IxAtmRxQueueId [in] indicates which RX queue to has Pdus to process.
- * @param numberOfPdusToProcess unsigned int [in] indicates the minimum number of
- *        PDUs available to process all PDUs from the queue.
- * @param reservedPtr unsigned int* [out] pointer to a int location which can
- *        be written to, but does not retain written values. This is
- *        provided to make this prototype compatible
- *        with @a ixAtmdAccRxDispatch()
- *
- * @return @li int - ignored.
- *
- */
-typedef IX_STATUS (*IxAtmdAccRxDispatcher) (IxAtmRxQueueId rxQueueId,
-                         unsigned int numberOfPdusToProcess,
-                         unsigned int *reservedPtr);
-
-/* ------------------------------------------------------
-   Part of the IxAtmdAcc interface related to TX traffic
-   ------------------------------------------------------ */
-
-/**
- *
- * @ingroup IxAtmdAccCtrlAPI
- *
- * @brief Callback prototype for transmitted mbuf when threshold level is
- *        crossed.
- *
- * IxAtmdAccTxDoneDispatcher is the prototype of the user function
- * which get called when pdus are completely transmitted. This function
- * is likely to call the @a ixAtmdAccTxDoneDispatch() function.
- *
- * This function is called when the number of available pdus for
- * reception is crossing the threshold level as defined
- * in @a ixAtmdAccTxDoneDispatcherRegister()
- *
- * This function is called inside an Qmgr dispatch context. No system
- * resource or interrupt-unsafe feature should be used inside this
- * callback.
- *
- * Transmitted buffers recycling implementation is a sytem-wide mechanism
- * and needs to be set before any traffic is started. If this threshold
- * mechanism is not used, the user is responsible for polling the
- * transmitted buffers with @a ixAtmdAccTxDoneDispatch()
- * and @a ixAtmdAccTxDoneLevelQuery() functions.
- *
- * @sa ixAtmdAccTxDoneDispatcherRegister
- * @sa ixAtmdAccTxDoneDispatch
- * @sa ixAtmdAccTxDoneLevelQuery
- *
- * @param numberOfPdusToProcess unsigned int [in] - The current number of pdus currently
- *        available for recycling
- * @param *reservedPtr unsigned int [out] - pointer to a int location which can be
- *        written to but does not retain written values. This is provided
- *        to make this prototype compatible
- *        with @a ixAtmdAccTxDoneDispatch()
- *
- * @return @li IX_SUCCESS This is provided to make
- *    this prototype compatible with @a ixAtmdAccTxDoneDispatch()
- * @return @li IX_FAIL invalid parameters or some unspecified internal
- *    error occured. This is provided to make
- *    this prototype compatible with @a ixAtmdAccTxDoneDispatch()
- *
- */
-typedef IX_STATUS (*IxAtmdAccTxDoneDispatcher) (unsigned int numberOfPdusToProcess,
-                                                unsigned int *reservedPtr);
-
-/**
-*
-* @ingroup IxAtmdAccCtrlAPI
-*
-* @brief Notification that the threshold number of scheduled cells
-* remains in a port's transmit Q.
-*
-* The is the prototype for of the user notification function which
-* gets called on a per-port basis, when the number of remaining
-* scheduled cells to be transmitted decreases to the threshold level.
-* The number of cells passed as a parameter can be used for scheduling
-* purposes as the maximum number of cells that can be passed in a
-* schedule table to the @a ixAtmdAccPortTxProcess() function.
-*
-* @sa ixAtmdAccPortTxCallbackRegister
-* @sa ixAtmdAccPortTxProcess
-* @sa ixAtmdAccPortTxFreeEntriesQuery
-*
-* @param port @ref IxAtmLogicalPort [in] - logical PHY port [@a IX_UTOPIA_PORT_0 .. @a IX_UTOPIA_MAX_PORTS - 1]
-* @param numberOfAvailableCells unsigned int [in] - number of available
-*        cell entries.for the port
-*
-* @note - This functions shall not use system resources when used
-*         inside an interrupt context.
-*
-*/
-typedef void (*IxAtmdAccPortTxLowCallback) (IxAtmLogicalPort port,
-                           unsigned int numberOfAvailableCells);
-
-/**
-*
-* @ingroup IxAtmdAccCtrlAPI
-*
-* @brief  Prototype to submit cells for transmission
-*
-* IxAtmdAccTxVcDemandUpdateCallback is the prototype of the callback
-* function used by AtmD to notify an ATM Scheduler that the user of
-* a VC has submitted cells for transmission.
-*
-* @sa IxAtmdAccTxVcDemandUpdateCallback
-* @sa IxAtmdAccTxVcDemandClearCallback
-* @sa IxAtmdAccTxSchVcIdGetCallback
-* @sa ixAtmdAccPortTxScheduledModeEnable
-*
-* @param port @ref IxAtmLogicalPort [in] - Specifies the ATM port on which the VC to be updated
-*        is established
-* @param vcId int [in] - Identifies the VC to be updated. This is the value
-*        returned by the @a IxAtmdAccTxSchVcIdGetCallback() call .
-* @param numberOfCells unsigned int [in] - Indicates how many ATM cells should be added
-*        to the queue for this VC.
-*
-* @return @li IX_SUCCESS the function is registering the cell demand for
-*        this VC.
-* @return @li IX_FAIL the function cannot register cell for this VC : the
-*         scheduler maybe overloaded or misconfigured
-*
-*/
-typedef IX_STATUS (*IxAtmdAccTxVcDemandUpdateCallback) (IxAtmLogicalPort port,
-                        int vcId,
-                        unsigned int numberOfCells);
-
-/**
-*
-* @ingroup IxAtmdAccCtrlAPI
-*
-* @brief  prototype to  remove all currently queued cells from a
-* registered VC
-*
-* IxAtmdAccTxVcDemandClearCallback is the prototype of the function
-* to remove all currently queued cells from a registered VC. The
-* pending cell count for the specified VC is reset to zero. After the
-* use of this callback, the scheduler shall not schedule more cells
-* for this VC.
-*
-* This callback function is called during a VC disconnection
-* @a ixAtmdAccTxVcTryDisconnect()
-*
-* @sa IxAtmdAccTxVcDemandUpdateCallback
-* @sa IxAtmdAccTxVcDemandClearCallback
-* @sa IxAtmdAccTxSchVcIdGetCallback
-* @sa ixAtmdAccPortTxScheduledModeEnable
-* @sa ixAtmdAccTxVcTryDisconnect
-*
-* @param port @ref IxAtmLogicalPort [in] - Specifies the ATM port on which the VC to be cleared
-*        is established
-* @param vcId int [in] - Identifies the VC to be cleared. This is the value
-*        returned by the @a IxAtmdAccTxSchVcIdGetCallback() call .
-*
-* @return none
-*
-*/
-typedef void (*IxAtmdAccTxVcDemandClearCallback) (IxAtmLogicalPort port,
-                             int vcId);
-
-/**
-*
-* @ingroup IxAtmdAccCtrlAPI
-*
-* @brief  prototype to get a scheduler vc id
-*
-* IxAtmdAccTxSchVcIdGetCallback is the prototype of the function to get
-* a scheduler vcId
-*
-* @sa IxAtmdAccTxVcDemandUpdateCallback
-* @sa IxAtmdAccTxVcDemandClearCallback
-* @sa IxAtmdAccTxSchVcIdGetCallback
-* @sa ixAtmdAccPortTxScheduledModeEnable
-*
-* @param port @ref IxAtmLogicalPort [in] - Specifies the ATM logical port on which the VC is
-*        established
-* @param vpi unsigned int [in] - For AAL0/AAL5 specifies the ATM vpi on which the 
-*                 VC is established.
-*                 For OAM specifies the dedicated "OAM Tx channel" VPI.
-* @param vci unsigned int [in] - For AAL0/AAL5 specifies the ATM vci on which the 
-*                 VC is established.
-*                 For OAM specifies the dedicated "OAM Tx channel" VCI.
-* @param connId @ref IxAtmConnId [in] - specifies the IxAtmdAcc connection Id already
-*        associated with this VC
-* @param vcId int* [out] - pointer to a vcId
-*
-* @return @li IX_SUCCESS the function is returning a Scheduler vcId for this
-*         VC
-* @return @li IX_FAIL the function cannot process scheduling for this VC.
-*                 the contents of vcId is unspecified
-*
-*/
-typedef IX_STATUS (*IxAtmdAccTxSchVcIdGetCallback) (IxAtmLogicalPort port,
-                               unsigned int vpi,
-                               unsigned int vci,
-                               IxAtmConnId connId,
-                               int *vcId);
-
-/* ------------------------------------------------------
-   Part of the IxAtmdAcc interface related to RX traffic
-   ------------------------------------------------------ */
-
-/**
- *
- * @ingroup IxAtmdAccCtrlAPI
- *
- * @fn ixAtmdAccRxDispatcherRegister (
-                          IxAtmRxQueueId queueId,
-                          IxAtmdAccRxDispatcher callback)
- *
- * @brief Register a notification callback to be invoked when there is
- * at least one entry on a particular Rx queue.
- *
- * This function registers a callback to be invoked when there is at
- * least one entry in a particular queue. The registered callback is
- * called every time when the hardware adds one or more pdus to the
- * specified Rx queue.
- *
- * This function cannot be used when a Rx Vc using this queue is
- * already existing.
- *
- * @note -The callback function can be the API function
- *       @a ixAtmdAccRxDispatch() : every time the threhold level
- *       of the queue is reached, the ixAtmdAccRxDispatch() is
- *       invoked to remove all entries from the queue.
- *
- * @sa ixAtmdAccRxDispatch
- * @sa IxAtmdAccRxDispatcher
- *
- * @param queueId @ref IxAtmRxQueueId [in] RX queue identification
- * @param callback @ref IxAtmdAccRxDispatcher [in] function triggering the delivery of incoming
- *        traffic. This parameter cannot be a null pointer.
- *
- * @return @li IX_SUCCESS Successful call to @a ixAtmdAccRxDispatcherRegister()
- * @return @li IX_FAIL error in the parameters, or there is an
- *             already active RX VC for this queue or some unspecified
- *             internal error occurred.
- *
- */
-PUBLIC IX_STATUS ixAtmdAccRxDispatcherRegister (
-                          IxAtmRxQueueId queueId,
-                          IxAtmdAccRxDispatcher callback);
-
-/**
- *
- * @ingroup IxAtmdAccCtrlAPI
- *
- * @fn ixAtmdAccRxDispatch (IxAtmRxQueueId rxQueueId,
-    unsigned int numberOfPdusToProcess,
-    unsigned int *numberOfPdusProcessedPtr)
- *
- *
- * @brief Control function which executes Rx processing for a particular
- * Rx stream.
- *
- * The @a IxAtmdAccRxDispatch() function is used to process received Pdus
- * available from one of the two incoming RX streams. When this function
- * is invoked, the incoming traffic (up to the number of PDUs passed as
- * a parameter) will be transferred to the IxAtmdAcc users through the
- * callback @a IxAtmdAccRxVcRxCallback(), as registered during the
- * @a ixAtmdAccRxVcConnect() call.
- *
- * The user receive callbacks will be executed in the context of this
- * function.
- *
- * Failing to use this function on a regular basis when there is traffic
- * will block incoming traffic and can result in Pdus being dropped by
- * the hardware.
- *
- * This should be used to control when received pdus are handed off from
- * the hardware to Aal users from a particluar stream. The function can
- * be used from a timer context, or can be registered as a callback in
- * response to an rx stream threshold event, or can be used inside an
- * active polling mechanism which is under user control.
- *
- * @note - The signature of this function is directly compatible with the
- * callback prototype which can be register with @a ixAtmdAccRxDispatcherRegister().
- *
- * @sa ixAtmdAccRxDispatcherRegister
- * @sa IxAtmdAccRxVcRxCallback
- * @sa ixAtmdAccRxVcFreeEntriesQuery
- *
- * @param rxQueueId @ref IxAtmRxQueueId [in] - indicates which RX queue to process.
- * @param numberOfPdusToProcess unsigned int [in] - indicates the maxiumum number of PDU to
- *     remove from the RX queue. A value of IX_ATMDACC_ALLPDUS indicates
- *     to process all PDUs from the queue. This includes at least the PDUs
- *     in the queue when the fuction is invoked. Because of real-time
- *     constraints, there is no guarantee thatthe queue will be empty
- *     when the function exits. If this parameter is greater than the
- *     number of entries of the queues, the function will succeed
- *     and the parameter numberOfPdusProcessedPtr will reflect the exact
- *     number of PDUs processed.
- * @param *numberOfPdusProcessedPtr unsigned int [out] - indicates the actual number of PDU
- *     processed during this call. This parameter cannot be a null
- *     pointer.
- *
- * @return @li IX_SUCCESS the number of PDUs as indicated in
- *     numberOfPdusProcessedPtr are removed from the RX queue and the VC callback
- *     are called.
- * @return @li IX_FAIL invalid parameters or some unspecified internal
- *     error occured.
- *
- */
-PUBLIC IX_STATUS ixAtmdAccRxDispatch (IxAtmRxQueueId rxQueueId,
-    unsigned int numberOfPdusToProcess,
-    unsigned int *numberOfPdusProcessedPtr);
-
-/**
- *
- * @ingroup IxAtmdAccCtrlAPI
- * 
- * @fn ixAtmdAccRxLevelQuery (IxAtmRxQueueId rxQueueId,
-                     unsigned int *numberOfPdusPtr)
- *
- * @brief Query the number of entries in a particular RX queue.
- *
- * This function is used to retrieve the number of pdus received by
- * the hardware and ready for distribution to users.
- *
- * @param rxQueueId @ref IxAtmRxQueueId [in] - indicates which of two RX queues to query.
- * @param numberOfPdusPtr unsigned int* [out] - Pointer to store the number of available
- *        PDUs in the RX queue. This parameter cannot be a null pointer.
- *
- * @return @li IX_SUCCESS the value in numberOfPdusPtr specifies the
- *         number of incoming pdus waiting in this queue
- * @return @li IX_FAIL an error occurs during processing.
- *         The value in numberOfPdusPtr is unspecified.
- *
- * @note - This function is reentrant, doesn't use system resources
- *         and can be used from an interrupt context.
- *
- */
-PUBLIC IX_STATUS ixAtmdAccRxLevelQuery (IxAtmRxQueueId rxQueueId,
-                     unsigned int *numberOfPdusPtr);
-
-/**
- *
- * @ingroup IxAtmdAccCtrlAPI
- *
- * @fn ixAtmdAccRxQueueSizeQuery (IxAtmRxQueueId rxQueueId,
-                     unsigned int *numberOfPdusPtr)
- *
- * @brief Query the size of a particular RX queue.
- *
- * This function is used to retrieve the number of pdus the system is
- * able to queue when reception is complete.
- *
- * @param rxQueueId @ref IxAtmRxQueueId [in] - indicates which of two RX queues to query.
- * @param numberOfPdusPtr unsigned int* [out] - Pointer to store the number of pdus
- *         the system is able to queue in the RX queue. This parameter
- *         cannot be a null pointer.
- *
- * @return @li IX_SUCCESS the value in numberOfPdusPtr specifies the
- *         number of pdus the system is able to queue.
- * @return @li IX_FAIL an error occurs during processing.
- *         The value in numberOfPdusPtr is unspecified.
- *
- * @note - This function is reentrant, doesn't use system resources
- *         and can be used from an interrupt context.
- *
- */
-PUBLIC IX_STATUS ixAtmdAccRxQueueSizeQuery (IxAtmRxQueueId rxQueueId,
-                     unsigned int *numberOfPdusPtr);
-
-/* ------------------------------------------------------
-   Part of the IxAtmdAcc interface related to TX traffic
-   ------------------------------------------------------ */
-
-/**
- *
- * @ingroup IxAtmdAccCtrlAPI
- *
- * @fn ixAtmdAccPortTxFreeEntriesQuery (IxAtmLogicalPort port,
-                         unsigned int *numberOfCellsPtr)
- *
- * @brief Get the number of available cells the system can accept for
- *       transmission.
- *
- * The function is used to retrieve the number of cells that can be
- * queued for transmission to the hardware.
- *
- * This number is based on the worst schedule table where one cell
- * is stored in one schedule table entry, depending on the pdus size
- * and mbuf size and fragmentation.
- *
- * This function doesn't use system resources and can be used from a
- * timer context, or can be associated with a threshold event, or can
- * be used inside an active polling mechanism
- *
- * @param port @ref IxAtmLogicalPort [in] - logical PHY port [@a IX_UTOPIA_PORT_0 .. @a IX_UTOPIA_MAX_PORTS - 1]
- * @param numberOfCellsPtr unsigned int* [out] - number of available cells.
- *                   This parameter cannot be a null pointer.
- *
- * @sa ixAtmdAccPortTxProcess
- *
- * @return @li IX_SUCCESS numberOfCellsPtr contains the number of cells that can be scheduled
- *         for this port.
- * @return @li IX_FAIL error in the parameters, or some processing error
- *         occured.
- *
- */
-PUBLIC IX_STATUS ixAtmdAccPortTxFreeEntriesQuery (IxAtmLogicalPort port,
-                         unsigned int *numberOfCellsPtr);
-
-/**
- *
- * @ingroup IxAtmdAccCtrlAPI
- * 
- * @fn ixAtmdAccPortTxCallbackRegister (IxAtmLogicalPort port,
-                       unsigned int numberOfCells,
-                       IxAtmdAccPortTxLowCallback callback)
- *
- * @brief Configure the Tx port threshold value and register a callback to handle
- * threshold notifications.
- *
- * This function sets the threshold in cells
- *
- * @sa ixAtmdAccPortTxCallbackRegister
- * @sa ixAtmdAccPortTxProcess
- * @sa ixAtmdAccPortTxFreeEntriesQuery
- *
- * @param port @ref IxAtmLogicalPort [in] - logical PHY port [@a IX_UTOPIA_PORT_0 .. @a IX_UTOPIA_MAX_PORTS - 1]
- * @param numberOfCells unsigned int [in] - threshold value which triggers the callback
- *        invocation, This number has to be one of the
- *        values 0,1,2,4,8,16,32 ....
- *        The maximum value cannot be more than half of the txVc queue
- *        size (which can be retrieved using @a ixAtmdAccPortTxFreeEntriesQuery()
- *        before any Tx traffic is sent for this port)
- * @param callback @ref IxAtmdAccPortTxLowCallback [in] - callback function to invoke when the threshold
- *                 level is reached.
- *                 This parameter cannot be a null pointer.
- *
- * @return @li IX_SUCCESS Successful call to @a ixAtmdAccPortTxCallbackRegister()
- * @return @li IX_FAIL error in the parameters, Tx channel already set for this port
- *             threshold level is not correct or within the range regarding the
- *             queue size:or unspecified error during processing:
- *
- * @note - This callback function get called when the threshold level drops from
- *         (numberOfCells+1) cells to (numberOfCells) cells
- *
- * @note - This function should be called during system initialisation,
- *         outside an interrupt context
- *
- */
-PUBLIC IX_STATUS ixAtmdAccPortTxCallbackRegister (IxAtmLogicalPort port,
-                       unsigned int numberOfCells,
-                       IxAtmdAccPortTxLowCallback callback);
-
-/**
- *
- * @ingroup IxAtmdAccCtrlAPI
- *
- * @fn ixAtmdAccPortTxScheduledModeEnable (IxAtmLogicalPort port,
-    IxAtmdAccTxVcDemandUpdateCallback vcDemandUpdateCallback,
-    IxAtmdAccTxVcDemandClearCallback vcDemandClearCallback,
-    IxAtmdAccTxSchVcIdGetCallback vcIdGetCallback)
- *
- * @brief Put the port into Scheduled Mode
- *
- * This function puts the specified port into scheduled mode of
- * transmission which means an external s/w entity controls the
- * transmission of cells on this port. This faciltates traffic shaping on
- * the port.
- *
- * Any buffers submitted on a VC for this port will be queued in IxAtmdAcc.
- * The transmission of these buffers to and by the hardware will be driven
- * by a transmit schedule submitted regulary in calls to
- * @a ixAtmdAccPortTxProcess() by traffic shaping entity.
- *
- * The transmit schedule is expected to be dynamic in nature based on
- * the demand in cells for each VC on the port. Hence the callback
- * parameters provided to this function allow IxAtmdAcc to inform the
- * shaping entity of demand changes for each VC on the port.
- *
- * By default a port is in Unscheduled Mode so if this function is not
- * called, transmission of data is done without sheduling rules, on a
- * first-come, first-out basis.
- *
- * Once a port is put in scheduled mode it cannot be reverted to
- * un-scheduled mode. Note that unscheduled mode is not supported
- * in ixp425 1.0
- *
- * @note - This function should be called before any VCs have be
- * connected on a port. Otherwise this function call will return failure.
- *
- * @note - This function uses internal locks and should not be called from
- * an interrupt context
- *
- * @sa IxAtmdAccTxVcDemandUpdateCallback
- * @sa IxAtmdAccTxVcDemandClearCallback
- * @sa IxAtmdAccTxSchVcIdGetCallback
- * @sa ixAtmdAccPortTxProcess
- *
- * @param port @ref IxAtmLogicalPort [in] - logical PHY port [@a IX_UTOPIA_PORT_0 .. @a IX_UTOPIA_MAX_PORTS - 1]
- * @param vcDemandUpdateCallback @ref IxAtmdAccTxVcDemandUpdateCallback [in] - callback function used to update
- *     the number of outstanding cells for transmission. This parameter
- *     cannot be a null pointer.
- * @param vcDemandClearCallback @ref IxAtmdAccTxVcDemandClearCallback [in] - callback function used to remove all
- *     clear the number of outstanding cells for a VC. This parameter
- *     cannot be a null pointer.
- * @param vcIdGetCallback @ref IxAtmdAccTxSchVcIdGetCallback [in] - callback function used to exchange vc
- *     Identifiers between IxAtmdAcc and the entity supplying the
- *     transmit schedule. This parameter cannot be a null pointer.
- *
- * @return @li IX_SUCCESS scheduler registration is complete and the port
- *         is now in scheduled mode.
- * @return @li IX_FAIL failed (wrong parameters, or traffic is already
- *         enabled on this port, possibly without ATM shaping)
- *
- */
-PUBLIC IX_STATUS ixAtmdAccPortTxScheduledModeEnable (IxAtmLogicalPort port,
-    IxAtmdAccTxVcDemandUpdateCallback vcDemandUpdateCallback,
-    IxAtmdAccTxVcDemandClearCallback vcDemandClearCallback,
-    IxAtmdAccTxSchVcIdGetCallback vcIdGetCallback);
-
-/**
- *
- * @ingroup IxAtmdAccCtrlAPI
- *
- * @fn ixAtmdAccPortTxProcess (IxAtmLogicalPort port,
-    IxAtmScheduleTable* scheduleTablePtr)
- *
- * @brief Transmit queue cells to the H/W based on the supplied schedule
- *        table.
- *
- * This function @a ixAtmdAccPortTxProcess() process the schedule
- * table provided as a parameter to the function. As a result cells are
- * sent to the underlaying hardware for transmission.
- *
- * The schedule table is executed in its entirety or not at all. So the
- * onus is on the caller not to submit a table containing more cells than
- * can be transmitted at that point. The maximum numbers that can be
- * transmitted is guaranteed to be the number of cells as returned by the
- * function @a ixAtmdAccPortTxFreeEntriesQuery().
- *
- * When the scheduler is invoked on a threshold level, IxAtmdAcc gives the
- * minimum number of cells (to ensure the callback will fire again later)
- * and the maximum number of cells that @a ixAtmdAccPortTxProcess()
- * will be able to process (assuming the ATM scheduler is able
- * to produce the worst-case schedule table, i.e. one entry per cell).
- *
- * When invoked ouside a threshold level, the overall number of cells of
- * the schedule table should be less than the number of cells returned
- * by the @a ixAtmdAccPortTxFreeEntriesQuery() function.
- *
- * After invoking the @a ixAtmdAccPortTxProcess() function, it is the
- * user choice to query again the queue level with the function
- * @a ixAtmdAccPortTxFreeEntriesQuery() and, depending on a new cell
- * number, submit an other schedule table.
- *
- * IxAtmdAcc will check that the number of cells in the schedule table
- * is compatible with the current transmit level. If the
- *
- * Obsolete or invalid connection Id will be silently discarded.
- *
- * This function is not reentrant for the same port.
- *
- * This functions doesn't use system resources and can be used inside an
- * interrupt context.
- *
- * This function is used as a response to the hardware requesting more
- * cells to transmit.
- *
- * @sa ixAtmdAccPortTxScheduledModeEnable
- * @sa ixAtmdAccPortTxFreeEntriesQuery
- * @sa ixAtmdAccPortTxCallbackRegister
- * @sa ixAtmdAccPortEnable
- *
- * @param port @ref IxAtmLogicalPort [in] - logical PHY port [@a IX_UTOPIA_PORT_0 .. @a IX_UTOPIA_MAX_PORTS - 1]
- * @param scheduleTablePtr @ref IxAtmScheduleTable* [in] - pointer to a scheduler update table. The
- *     content of this table is not modified by this function. This
- *     parameter cannot be a null pointer.
- *
- * @return @li IX_SUCCESS the schedule table process is complete
- *             and cells are transmitted to the hardware
- * @return @li IX_ATMDACC_WARNING : Traffic will be dropped: the schedule table exceed
- *     the hardware capacity  If this error is ignored, further traffic
- *     and schedule will work correctly.
- *     Overscheduling does not occur when the schedule table does
- *     not contain more entries that the number of free entries returned
- *     by @a ixAtmdAccPortTxFreeEntriesQuery().
- *     However, Disconnect attempts just after this error will fail permanently
- *     with the error code @a IX_ATMDACC_RESOURCES_STILL_ALLOCATED, and it is
- *     necessary to disable the port to make @a ixAtmdAccTxVcTryDisconnect()
- *     successful.
- * @return @li IX_FAIL a wrong parameter is supplied, or the format of
- *     the schedule table is invalid, or the port is not Enabled, or
- *     an internal severe error occured. No cells is transmitted to the hardware
- *
- * @note - If the failure is linked to an overschedule of data cells
- *     the result is an inconsistency in the output traffic (one or many
- *     cells may be missing and the traffic contract is not respected).
- *
- */
-PUBLIC IX_STATUS ixAtmdAccPortTxProcess (IxAtmLogicalPort port,
-    IxAtmScheduleTable* scheduleTablePtr);
-
-/**
- *
- * @ingroup IxAtmdAccCtrlAPI
- *
- * @fn ixAtmdAccTxDoneDispatch (unsigned int numberOfPdusToProcess,
-                unsigned int *numberOfPdusProcessedPtr)
- *
- * @brief Process a number of pending transmit done pdus from the hardware.
- *
- * As a by-product of Atm transmit operation buffers which transmission
- * is complete need to be recycled to users. This function is invoked
- * to service the oustanding list of transmitted buffers and pass them
- * to VC users.
- *
- * Users are handed back pdus by invoking the free callback registered
- * during the @a ixAtmdAccTxVcConnect() call.
- *
- * There is a single Tx done stream servicing all active Atm Tx ports
- * which can contain a maximum of 64 entries. If this stream fills port
- * transmission will stop so this function must be call sufficently
- * frequently to ensure no disruption to the transmit operation.
- *
- * This function can be used from a timer context, or can be associated
- * with a TxDone level threshold event (see @a ixAtmdAccTxDoneDispatcherRegister() ),
- * or can be used inside an active polling mechanism under user control.
- *
- * For ease of use the signature of this function is compatible with the
- * TxDone threshold event callback prototype.
- *
- * This functions can be used inside an interrupt context.
- *
- * @sa ixAtmdAccTxDoneDispatcherRegister
- * @sa IxAtmdAccTxVcBufferReturnCallback
- * @sa ixAtmdAccTxDoneLevelQuery
- *
- * @param numberOfPdusToProcess unsigned int [in] - maxiumum number of pdus to remove
- *     from the TX Done queue
- * @param *numberOfPdusProcessedPtr unsigned int [out] - number of pdus removed from
- *     the TX Done queue. This parameter cannot be a null pointer.
- *
- * @return @li IX_SUCCESS the number of pdus as indicated in
- *     numberOfPdusToProcess are removed from the TX Done hardware
- *     and passed to the user through the Tx Done callback registered
- *     during a call to @a ixAtmdAccTxVcConnect()
- * @return @li IX_FAIL invalid parameters or numberOfPdusProcessedPtr is
- *     a null pointer or some unspecified internal error occured.
- *
- */
-PUBLIC IX_STATUS
-ixAtmdAccTxDoneDispatch (unsigned int numberOfPdusToProcess,
-                unsigned int *numberOfPdusProcessedPtr);
-
-/**
- *
- * @ingroup IxAtmdAccCtrlAPI
- * 
- * @fn ixAtmdAccTxDoneLevelQuery (unsigned int *numberOfPdusPtr)
- *
- * @brief Query the current number of transmit pdus ready for
- *        recycling.
- *
- * This function is used to get the number of transmitted pdus which
- * the hardware is ready to hand back to user.
- *
- * This function can be used from a timer context, or can be associated
- * with a threshold event, on can be used inside an active polling
- * mechanism
- *
- * @sa ixAtmdAccTxDoneDispatch
- *
- * @param *numberOfPdusPtr unsigned int [out] - Pointer to the number of pdus transmitted
- *        at the time of this function call, and ready for recycling
- *        This parameter cannot be a null pointer.
- *
- * @return @li IX_SUCCESS numberOfPdusPtr contains the number of pdus
- *        ready for recycling at the time of this function call
- *
- * @return @li IX_FAIL wrong parameter (null pointer as parameter).or
- *         unspecified rocessing error occurs..The value in numberOfPdusPtr
- *         is unspecified.
- *
- */
-PUBLIC IX_STATUS
-ixAtmdAccTxDoneLevelQuery (unsigned int *numberOfPdusPtr);
-
-/**
- *
- * @ingroup IxAtmdAccCtrlAPI
- *
- * @fn ixAtmdAccTxDoneQueueSizeQuery (unsigned int *numberOfPdusPtr)
- *
- * @brief Query the TxDone queue size.
- *
- * This function is used to get the number of pdus which
- * the hardware is able to store after transmission is complete
- *
- * The returned value can be used to set a threshold and enable
- * a callback to be notified when the number of pdus is going over
- * the threshold.
- *
- * @sa ixAtmdAccTxDoneDispatcherRegister
- *
- * @param *numberOfPdusPtr unsigned int [out] - Pointer to the number of pdus the system
- *        is able to queue after transmission
- *
- * @return @li IX_SUCCESS numberOfPdusPtr contains the the number of
- *        pdus the system is able to queue after transmission
- * @return @li IX_FAIL wrong parameter (null pointer as parameter).or
- *         unspecified rocessing error occurs..The value in numberOfPdusPtr
- *         is unspecified.
- *
- * @note - This function is reentrant, doesn't use system resources
- *         and can be used from an interrupt context.
- */
-PUBLIC IX_STATUS
-ixAtmdAccTxDoneQueueSizeQuery (unsigned int *numberOfPdusPtr);
-
-/**
- *
- * @ingroup IxAtmdAccCtrlAPI
- * 
- * @fn ixAtmdAccTxDoneDispatcherRegister (unsigned int numberOfPdus,
-   IxAtmdAccTxDoneDispatcher notificationCallback)
- *
- * @brief Configure the Tx Done stream threshold value and register a
- * callback to handle threshold notifications.
- *
- * This function sets the threshold level in term of number of pdus at
- * which the supplied notification function should be called.
- *
- * The higher the threshold value is, the less events will be necessary
- * to process transmitted buffers.
- *
- * Transmitted buffers recycling implementation is a sytem-wide mechanism
- * and needs to be set prior any traffic is started. If this threshold
- * mechanism is not used, the user is responsible for polling the
- * transmitted buffers thanks to @a ixAtmdAccTxDoneDispatch() and
- * @a ixAtmdAccTxDoneLevelQuery() functions.
- *
- * This function should be called during system initialisation outside
- * an interrupt context
- *
- * @sa ixAtmdAccTxDoneDispatcherRegister
- * @sa ixAtmdAccTxDoneDispatch
- * @sa ixAtmdAccTxDoneLevelQuery
- *
- * @param numberOfPdus unsigned int [in] - The number of TxDone pdus which triggers the
- *        callback invocation This number has to be a power of 2, one of the
- *        values 0,1,2,4,8,16,32 ...
- *        The maximum value cannot be more than half of the txDone queue
- *        size (which can be retrieved using @a ixAtmdAccTxDoneQueueSizeQuery())
- * @param notificationCallback @ref IxAtmdAccTxDoneDispatcher [in] - The function to invoke. (This
- *        parameter can be @a ixAtmdAccTxDoneDispatch()).This
- *        parameter ust not be a null pointer.
- *
- * @return @li IX_SUCCESS Successful call to ixAtmdAccTxDoneDispatcherRegister
- * @return @li IX_FAIL error in the parameters:
- *
- * @note - The notificationCallback will be called exactly when the threshold level
- *         will increase from (numberOfPdus) to (numberOfPdus+1)
- *
- * @note - If there is no Tx traffic, there is no guarantee that TxDone Pdus will
- *       be released to the user (when txDone level is permanently under the threshold
- *       level. One of the preffered way to return resources to the user is to use
- *       a mix of txDone notifications, used together with a slow
- *       rate timer and an exclusion mechanism protecting from re-entrancy
- *
- * @note - The TxDone threshold will only hand back buffers when the threshold level is
- *      crossed. Setting this threshold to a great number reduce the interrupt rate
- *      and the cpu load, but also increase the number of outstanding mbufs and has
- *      a system wide impact when these mbufs are needed by other components.
- *
- */
-PUBLIC IX_STATUS ixAtmdAccTxDoneDispatcherRegister (unsigned int numberOfPdus,
-   IxAtmdAccTxDoneDispatcher notificationCallback);
-
-/* ------------------------------------------------------
-   Part of the IxAtmdAcc interface related to Utopia config
-   ------------------------------------------------------ */
-
-/**
- *
- * @ingroup IxAtmdAccCtrlAPI
- *
- * @defgroup IxAtmdAccUtopiaCtrlAPI IXP400 ATM Driver Access (IxAtmdAcc) Utopia Control API
- *
- * @brief The public API for the IXP400 Atm Driver Control component
- *
- * IxAtmdAcc is the low level interface by which AAL PDU get
- * transmitted to,and received from the Utopia bus
- *
- * This part is related to the UTOPIA configuration.
- *
- * @{
- */
-
-/**
- *
- * @brief Utopia configuration
- *
- * This structure is used to set the Utopia parameters
- * @li contains the values of Utopia registers, to be set during initialisation
- * @li contains debug commands for NPE, to be used during development steps
- *
- * @note - the exact description of all parameters is done in the Utopia reference
- *   documents.
- *
- */
-typedef struct
-{
-    /**
-    * @ingroup IxAtmdAccUtopiaCtrlAPI
-    * @struct UtTxConfig_
-    * @brief Utopia Tx Config Register
-    */
-    struct UtTxConfig_
-    {
-
-    unsigned int reserved_1:1;  /**< [31] These bits are always 0.*/
-    unsigned int txInterface:1;     /**< [30] Utopia Transmit Interface. The following encoding
-                                   * is used to set the Utopia Transmit interface as ATM master
-                                   * or PHY slave:
-                                   * @li 1 - PHY
-                                   * @li 0 - ATM
-                                   */
-    unsigned int txMode:1;      /**< [29] Utopia Transmit Mode. The following encoding is used
-    *  to set the Utopia Transmit mode to SPHY or MPHY:
-    *  @li 1 - SPHY
-    *  @li 0 - MPHY
-    */
-    unsigned int txOctet:1;  /**< [28] Utopia Transmit cell transfer protocol. Used to set
-    * the Utopia cell transfer protocol to Octet-level handshaking.
-    * Note this is only applicable in SPHY mode.
-    * @li 1 - Octet-handshaking enabled
-    * @li 0 - Cell-handshaking enabled
-    */
-    unsigned int txParity:1;    /**< [27] Utopia Transmit parity enabled when set. TxEvenParity
-    * defines the parity format odd/even.
-    * @li 1 - Enable Parity generation.
-    * @li 0 - ut_op_prty held low.
-    */
-    unsigned int txEvenParity:1; /**< [26] Utopia Transmit Parity Mode
-    * @li 1 - Even Parity Generated.
-    * @li 0 - Odd Parity Generated.
-    */
-    unsigned int txHEC:1; /**< [25] Header Error Check Insertion Mode. Specifies if the transmit
-    * cell header check byte is calculated and inserted when set.
-    * @li 1 - Generate HEC.
-    * @li 0 - Disable HEC generation.
-    */
-    unsigned int txCOSET:1;    /**< [24] If enabled the HEC is Exclusive-ORÆed with the value 0x55 before
-  * being presented on the Utopia bus.
-  * @li 1 - Enable HEC ExOR with value 0x55
-  * @li 0 - Use generated HEC value.
-  */
-
-    unsigned int reserved_2:1;    /**< [23] These bits are always 0
-    */
-    unsigned int txCellSize:7;    /**< [22:16] Transmit expected cell size. Configures the cell size
-    * for the transmit module: Values between 52-64 are valid.
-    */
-    unsigned int reserved_3:3;  /**< [15:13] These bits are always 0 */
-    unsigned int txAddrRange:5;       /**< [12:8] When configured as an ATM master in MPHY mode this
-    * register specifies the upper limit of the PHY polling logical
-    * range. The number of active PHYs are TxAddrRange + 1.
-    */
-    unsigned int reserved_4:3;      /**< [7:5] These bits are always 0 */
-    unsigned int txPHYAddr:5;     /**< [4:0] When configured as a slave in an MPHY system this register
-    * specifies the physical address of the PHY.
-    */
-    }
-
-    utTxConfig;       /**< Tx config Utopia register */
-
-   /**
-    * @ingroup IxAtmdAccUtopiaCtrlAPI
-   * @struct UtTxStatsConfig_
-   * @brief Utopia Tx stats Register
-    */
-    struct UtTxStatsConfig_
-    {
-
-    unsigned int vpi:12;  /**< [31:20] ATM VPI [11:0] OR GFC [3:0] and VPI [7:0]
-    @li Note: if VCStatsTxGFC is set to 0 the GFC field is ignored in test. */
-
-    unsigned int vci:16;  /**< [19:4] ATM VCI [15:0] or PHY Address[4] */
-
-    unsigned int pti:3;  /**< [3:1] ATM PTI [2:0] or PHY Address[3:1]
-  @li Note: if VCStatsTxPTI is set to 0 the PTI field is ignored in test.
-  @li Note: if VCStatsTxEnb is set to 0 only the transmit PHY port
-  address as defined by this register is used for ATM statistics [4:0]. */
-
-    unsigned int clp:1;  /**< [0] ATM CLP or PHY Address [0]
-  @li Note: if VCStatsTxCLP is set to 0 the CLP field is ignored in test.
-  @li Note: if VCStatsTxEnb is set to 0 only the transmit PHY port
-  address as defined by this register is used for ATM statistics [4:0]. */
-    }
-
-    utTxStatsConfig;       /**< Tx stats config Utopia register */
-
-       /**
-    * @ingroup IxAtmdAccUtopiaCtrlAPI
-       * @struct UtTxDefineIdle_
-       * @brief Utopia Tx idle cells Register
-    */
-    struct UtTxDefineIdle_
-    {
-
-    unsigned int vpi:12;  /**< [31:20] ATM VPI [11:0] OR GFC [3:0] and VPI [7:0]
-    @li Note: if VCIdleTxGFC is set to 0 the GFC field is ignored in test. */
-
-    unsigned int vci:16;  /**< [19:4] ATM VCI [15:0] */
-
-    unsigned int pti:3;  /**< [3:1] ATM PTI PTI [2:0]
-  @li Note: if VCIdleTxPTI is set to 0 the PTI field is ignored in test.*/
-
-    unsigned int clp:1;  /**< [0] ATM CLP [0]
-  @li Note: if VCIdleTxCLP is set to 0 the CLP field is ignored in test.*/
-    }
-
-    utTxDefineIdle;      /**< Tx idle cell config Utopia register */
-
-      /**
-    * @ingroup IxAtmdAccUtopiaCtrlAPI
-      * @struct UtTxEnableFields_
-      * @brief Utopia Tx ienable fields Register
-    */
-    struct UtTxEnableFields_
-    {
-
-    unsigned int defineTxIdleGFC:1;    /**< [31] This register is used to include or exclude the GFC
-    field of the ATM header when testing for Idle cells.
-    @li 1 - GFC field is valid.
-    @li 0 - GFC field ignored.*/
-
-    unsigned int defineTxIdlePTI:1;    /**< [30] This register is used to include or exclude the PTI
-    field of the ATM header when testing for Idle cells.
-    @li 1 - PTI field is valid
-    @li    0 - PTI field ignored.*/
-
-    unsigned int defineTxIdleCLP:1;    /**< [29] This register is used to include or
-    exclude the CLP field of the ATM header when testing for Idle cells.
-    @li 1 - CLP field is valid.
-    @li 0 - CLP field ignored. */
-
-    unsigned int phyStatsTxEnb:1;    /**< [28] This register is used to enable or disable ATM
-  statistics gathering based on the specified PHY address as defined
-  in TxStatsConfig register.
-  @li 1 - Enable statistics for specified transmit PHY address.
-    @li 0 - Disable statistics for specified transmit PHY address. */
-
-    unsigned int vcStatsTxEnb:1;  /**< [27] This register is used to change the ATM
-      statistics-gathering mode from the specified logical PHY address
-      to a specific VPI/VCI address.
-      @li 1 - Enable statistics for specified VPI/VCI address.
-      @li 0 - Disable statistics for specified VPI/VCI address */
-
-    unsigned int vcStatsTxGFC:1;  /**< [26] This register is used to include or exclude the GFC
-      field of the ATM header when ATM VPI/VCI statistics are enabled.
-      GFC is only available at the UNI and uses the first 4-bits of
-      the VPI field.
-      @li 1 - GFC field is valid
-      @li 0 - GFC field ignored.*/
-
-    unsigned int vcStatsTxPTI:1;  /**< [25] This register is used to include or exclude the PTI
-      field of the ATM header when ATM VPI/VCI statistics are enabled.
-      @li 1 - PTI field is valid
-      @li 0 - PTI field ignored.*/
-
-    unsigned int vcStatsTxCLP:1;  /**< [24] This register is used to include or exclude the CLP
-      field of the ATM header when ATM VPI/VCI statistics are enabled.
-      @li 1 - CLP field is valid
-      @li 0 - CLP field ignored. */
-
-    unsigned int reserved_1:3;  /**< [23-21] These bits are always 0 */
-
-    unsigned int txPollStsInt:1;    /**< [20] Enable the assertion of the ucp_tx_poll_sts condition
-  where there is a change in polling status.
-  @li 1 - ucp_tx_poll_sts asserted whenever there is a change in status
-  @li    0 - ucp_tx_poll_sts asserted if ANY transmit PHY is available
-  */
-    unsigned int txCellOvrInt:1;    /**< [19] Enable TxCellCount overflow CBI Transmit Status condition
-      assertion.
-      @li 1 - If TxCellCountOvr is set assert the Transmit Status Condition.
-      @li 0 - No CBI Transmit Status condition assertion */
-
-    unsigned int txIdleCellOvrInt:1;  /**< [18] Enable TxIdleCellCount overflow Transmit Status Condition
-    @li 1 - If TxIdleCellCountOvr is set assert the Transmit Status Condition
-      @li 0 - No CBI Transmit Status condition assertion..*/
-
-    unsigned int enbIdleCellCnt:1;    /**< [17] Enable Transmit Idle Cell Count.
-    @li 1 - Enable count of Idle cells transmitted.
-      @li 0 - No count is maintained. */
-
-    unsigned int enbTxCellCnt:1;    /**< [16] Enable Transmit Valid Cell Count of non-idle/non-error cells
-      @li 1 - Enable count of valid cells transmitted- non-idle/non-error
-      @li 0 - No count is maintained.*/
-
-    unsigned int reserved_2:16;   /**< [15:0] These bits are always 0 */
-    } utTxEnableFields;  /**< Tx enable Utopia register */
-
-    /**
-    * @ingroup IxAtmdAccUtopiaCtrlAPI
-    * @struct UtTxTransTable0_
-    * @brief Utopia Tx translation table Register
-    */
-    struct UtTxTransTable0_
-    {
-
-    unsigned int phy0:5;  /**< [31-27] Tx Mapping value of logical phy 0 */
-
-    unsigned int phy1:5;  /**< [26-22] Tx Mapping value of logical phy 1 */
-
-    unsigned int phy2:5;  /**< [21-17] Tx Mapping value of logical phy 2 */
-
-    unsigned int reserved_1:1;  /**< [16] These bits are always 0.*/
-
-    unsigned int phy3:5;  /**< [15-11] Tx Mapping value of logical phy 3 */
-
-    unsigned int phy4:5;  /**< [10-6] Tx Mapping value of logical phy 4 */
-
-    unsigned int phy5:5;  /**< [5-1] Tx Mapping value of logical phy 5 */
-
-    unsigned int reserved_2:1;  /**< [0] These bits are always 0 */
-    } utTxTransTable0;  /**< Tx translation table */
-
-  /**
-    * @ingroup IxAtmdAccUtopiaCtrlAPI
-  * @struct UtTxTransTable1_
-  * @brief Utopia Tx translation table Register
-    */
-    struct UtTxTransTable1_
-    {
-
-    unsigned int phy6:5;  /**< [31-27] Tx Mapping value of logical phy 6 */
-
-    unsigned int phy7:5;  /**< [26-22] Tx Mapping value of logical phy 7 */
-
-    unsigned int phy8:5;  /**< [21-17] Tx Mapping value of logical phy 8 */
-
-    unsigned int reserved_1:1; /**< [16-0] These bits are always 0 */
-
-    unsigned int phy9:5;  /**< [15-11] Tx Mapping value of logical phy 3 */
-
-    unsigned int phy10:5;   /**< [10-6] Tx Mapping value of logical phy 4 */
-
-    unsigned int phy11:5;   /**< [5-1] Tx Mapping value of logical phy 5 */
-
-    unsigned int reserved_2:1;  /**< [0] These bits are always 0 */
-    } utTxTransTable1;  /**< Tx translation table */
-
-    /**
-    * @ingroup IxAtmdAccUtopiaCtrlAPI
-    * @struct UtTxTransTable2_
-    * @brief Utopia Tx translation table Register
-    */
-    struct UtTxTransTable2_
-    {
-
-    unsigned int phy12:5;   /**< [31-27] Tx Mapping value of logical phy 6 */
-
-    unsigned int phy13:5;   /**< [26-22] Tx Mapping value of logical phy 7 */
-
-    unsigned int phy14:5;   /**< [21-17] Tx Mapping value of logical phy 8 */
-
-    unsigned int reserved_1:1; /**< [16-0] These bits are always 0 */
-
-    unsigned int phy15:5;   /**< [15-11] Tx Mapping value of logical phy 3 */
-
-    unsigned int phy16:5;   /**< [10-6] Tx Mapping value of logical phy 4 */
-
-    unsigned int phy17:5;   /**< [5-1] Tx Mapping value of logical phy 5 */
-
-    unsigned int reserved_2:1;  /**< [0] These bits are always 0 */
-    } utTxTransTable2;    /**< Tx translation table */
-
-    /**
-    * @ingroup IxAtmdAccUtopiaCtrlAPI
-    * @struct UtTxTransTable3_
-    * @brief Utopia Tx translation table Register
-    */
-    struct UtTxTransTable3_
-    {
-
-    unsigned int phy18:5;   /**< [31-27] Tx Mapping value of logical phy 6 */
-
-    unsigned int phy19:5;   /**< [26-22] Tx Mapping value of logical phy 7 */
-
-    unsigned int phy20:5;   /**< [21-17] Tx Mapping value of logical phy 8 */
-
-    unsigned int reserved_1:1; /**< [16-0] These bits are always 0 */
-
-    unsigned int phy21:5;   /**< [15-11] Tx Mapping value of logical phy 3 */
-
-    unsigned int phy22:5;   /**< [10-6] Tx Mapping value of logical phy 4 */
-
-    unsigned int phy23:5;   /**< [5-1] Tx Mapping value of logical phy 5 */
-
-    unsigned int reserved_2:1;  /**< [0] These bits are always 0 */
-    } utTxTransTable3;  /**< Tx translation table */
-
-    /**
-    * @ingroup IxAtmdAccUtopiaCtrlAPI
-    * @struct UtTxTransTable4_
-    * @brief Utopia Tx translation table Register
-    */
-    struct UtTxTransTable4_
-    {
-
-    unsigned int phy24:5;   /**< [31-27] Tx Mapping value of logical phy 6 */
-
-    unsigned int phy25:5;   /**< [26-22] Tx Mapping value of logical phy 7 */
-
-    unsigned int phy26:5;   /**< [21-17] Tx Mapping value of logical phy 8 */
-
-    unsigned int reserved_1:1; /**< [16-0] These bits are always 0 */
-
-    unsigned int phy27:5;   /**< [15-11] Tx Mapping value of logical phy 3 */
-
-    unsigned int phy28:5;   /**< [10-6] Tx Mapping value of logical phy 4 */
-
-    unsigned int phy29:5;   /**< [5-1] Tx Mapping value of logical phy 5 */
-
-    unsigned int reserved_2:1;  /**< [0] These bits are always 0 */
-    } utTxTransTable4;  /**< Tx translation table */
-
-    /**
-    * @ingroup IxAtmdAccUtopiaCtrlAPI
-    * @struct UtTxTransTable5_
-    * @brief Utopia Tx translation table Register
-    */
-    struct UtTxTransTable5_
-    {
-
-    unsigned int phy30:5;   /**< [31-27] Tx Mapping value of logical phy 6 */
-
-    unsigned int reserved_1:27;     /**< [26-0] These bits are always 0 */
-
-    } utTxTransTable5;  /**< Tx translation table */
-
-    /**
-    * @ingroup IxAtmdAccUtopiaCtrlAPI
-    * @struct UtRxConfig_
-    * @brief Utopia Rx config Register
-    */
-    struct UtRxConfig_
-    {
-
-    unsigned int rxInterface:1;    /**< [31] Utopia Receive Interface. The following encoding is used
- to set the Utopia Receive interface as ATM master or PHY slave:
- @li 1 - PHY
-    @li 0 - ATM */
-
-    unsigned int rxMode:1;      /**< [30] Utopia Receive Mode. The following encoding is used to set
-      the Utopia Receive mode to SPHY or MPHY:
-      @li 1 - SPHY
-    @li 0 - MPHY */
-
-    unsigned int rxOctet:1;  /**< [29] Utopia Receive cell transfer protocol. Used to set the Utopia
-  cell transfer protocol to Octet-level handshaking. Note this is only
-  applicable in SPHY mode.
-  @li 1 - Octet-handshaking enabled
-    @li 0 - Cell-handshaking enabled */
-
-    unsigned int rxParity:1;    /**< [28] Utopia Receive Parity Checking enable.
-    @li 1 - Parity checking enabled
-    @li 0 - Parity checking disabled */
-
-    unsigned int rxEvenParity:1;/**< [27] Utopia Receive Parity Mode
-    @li 1 - Check for Even Parity
-    @li 0 - Check for Odd Parity.*/
-
-    unsigned int rxHEC:1;    /**< [26] RxHEC    Header Error Check Mode. Enables/disables cell header
-    error checking on the received cell header.
-    @li 1 - HEC checking enabled
-    @li 0 - HEC checking disabled */
-
-    unsigned int rxCOSET:1;  /**< [25] If enabled the HEC is Exclusive-ORÆed with the value 0x55
-  before being tested with the received HEC.
-  @li 1 - Enable HEC ExOR with value 0x55.
-    @li 0 - Use generated HEC value.*/
-
-    unsigned int rxHECpass:1;    /**< [24] Specifies if the incoming cell HEC byte should be transferred
-     after optional processing to the NPE2 Coprocessor Bus Interface or
-     if it should be discarded.
-     @li 1 - HEC maintained 53-byte/UDC cell sent to NPE2.
-    @li 0 - HEC discarded 52-byte/UDC cell sent to NPE2 coprocessor.*/
-
-    unsigned int reserved_1:1;    /**< [23] These bits are always 0 */
-
-    unsigned int rxCellSize:7;    /**< [22:16] Receive cell size. Configures the receive cell size.
-      Values between 52-64 are valid */
-
-    unsigned int rxHashEnbGFC:1;      /**< [15] Specifies if the VPI field [11:8]/GFC field should be
-      included in the Hash data input or if the bits should be padded
-      with 1Æb0.
-      @li 1 - VPI [11:8]/GFC field valid and used in Hash residue calculation.
-      @li 0 - VPI [11:8]/GFC field padded with 1Æb0 */
-
-    unsigned int rxPreHash:1; /**< [14] Enable Pre-hash value generation. Specifies if the
- incoming cell data should be pre-hashed to allow VPI/VCI header look-up
- in a hash table.
- @li 1 - Pre-hashing enabled
-      @li 0 - Pre-hashing disabled */
-
-    unsigned int reserved_2:1;    /**< [13] These bits are always 0 */
-
-    unsigned int rxAddrRange:5;     /**< [12:8] In ATM master, MPHY mode,
-     * this register specifies the upper
-     * limit of the PHY polling logical range. The number of active PHYs are
-     * RxAddrRange + 1.
-     */
-    unsigned int reserved_3:3;    /**< [7-5] These bits are always 0 .*/
-    unsigned int rxPHYAddr:5;     /**< [4:0] When configured as a slave in an MPHY system this register
-      * specifies the physical address of the PHY.
-      */
-    } utRxConfig;  /**< Rx config Utopia register */
-
-      /**
-    * @ingroup IxAtmdAccUtopiaCtrlAPI
-      * @struct UtRxStatsConfig_
-      * @brief Utopia Rx stats config Register
-    */
-    struct UtRxStatsConfig_
-    {
-
-    unsigned int vpi:12;  /**< [31:20] ATM VPI    VPI [11:0] OR GFC [3:0] and VPI [7:0]
-    @li Note: if VCStatsRxGFC is set to 0 the GFC field is ignored in test. */
-
-    unsigned int vci:16;  /**< [19:4] VCI [15:0] or PHY Address [4] */
-
-    unsigned int pti:3;  /**< [3:1] PTI [2:0] or or PHY Address [3:1]
-  @li Note: if VCStatsRxPTI is set to 0 the PTI field is ignored in test.
-  @li Note: if VCStatsRxEnb is set to 0 only the PHY port address is used
-  for statistics gathering.. */
-
-    unsigned int clp:1;  /**< [0] CLP [0] or PHY Address [0]
-  @li Note: if VCStatsRxCLP is set to 0 the CLP field is ignored in test.
-  @li Note: if VCStatsRxEnb is set to 0 only the PHY port address is used
-  for statistics gathering.. */
-    } utRxStatsConfig;  /**< Rx stats config Utopia register */
-
-  /**
-    * @ingroup IxAtmdAccUtopiaCtrlAPI
-  * @struct UtRxDefineIdle_
-  * @brief Utopia Rx idle cells config Register
-    */
-    struct UtRxDefineIdle_
-    {
-
-    unsigned int vpi:12;  /**< [31:20] ATM VPI [11:0] OR GFC [3:0] and VPI [7:0]
-    @li Note: if VCIdleRxGFC is set to 0 the GFC field is ignored in test. */
-
-    unsigned int vci:16;  /**< [19:4] ATM VCI [15:0] */
-
-    unsigned int pti:3;  /**< [3:1] ATM PTI PTI [2:0]
-  @li Note: if VCIdleRxPTI is set to 0 the PTI field is ignored in test.*/
-
-    unsigned int clp:1;  /**< [0] ATM CLP [0]
-  @li Note: if VCIdleRxCLP is set to 0 the CLP field is ignored in test.*/
-    } utRxDefineIdle;      /**< Rx idle cell config Utopia register */
-
-      /**
-    * @ingroup IxAtmdAccUtopiaCtrlAPI
-      * @struct UtRxEnableFields_
-      * @brief Utopia Rx enable Register
-    */
-    struct UtRxEnableFields_
-    {
-
-    unsigned int defineRxIdleGFC:1;/**< [31] This register is used to include or exclude the GFC
- field of the ATM header when testing for Idle cells.
- @li 1 - GFC field is valid.
-    @li 0 - GFC field ignored.*/
-
-    unsigned int defineRxIdlePTI:1;/**< [30] This register is used to include or exclude the PTI
- field of the ATM header when testing for Idle cells.
- @li 1 - PTI field is valid.
-    @li 0 - PTI field ignored.*/
-
-    unsigned int defineRxIdleCLP:1;/**< [29] This register is used to include or exclude the CLP
- field of the ATM header when testing for Idle cells.
- @li 1 - CLP field is valid.
-    @li    0 - CLP field ignored.*/
-
-    unsigned int phyStatsRxEnb:1;/**< [28] This register is used to enable or disable ATM statistics
-     gathering based on the specified PHY address as defined in RxStatsConfig
-     register.
-     @li 1 - Enable statistics for specified receive PHY address.
-    @li 0 - Disable statistics for specified receive PHY address.*/
-
-    unsigned int vcStatsRxEnb:1;/**< [27] This register is used to enable or disable ATM statistics
-    gathering based on a specific VPI/VCI address.
-    @li 1 - Enable statistics for specified VPI/VCI address.
-    @li 0 - Disable statistics for specified VPI/VCI address.*/
-
-    unsigned int vcStatsRxGFC:1;/**< [26] This register is used to include or exclude the GFC field
-    of the ATM header when ATM VPI/VCI statistics are enabled. GFC is only
-    available at the UNI and uses the first 4-bits of the VPI field.
-    @li 1 - GFC field is valid.
-    @li 0 - GFC field ignored. */
-
-    unsigned int vcStatsRxPTI:1;/**< [25] This register is used to include or exclude the PTI field
-    of the ATM header when ATM VPI/VCI statistics are enabled.
-    @li 1 - PTI field is valid.
-    @li 0 - PTI field ignored.*/
-
-    unsigned int vcStatsRxCLP:1;/**< [24] This register is used to include or exclude the CLP field
-    of the ATM header when ATM VPI/VCI statistics are enabled.
-    @li 1 - CLP field is valid.
-    @li 0 - CLP field ignored. */
-
-    unsigned int discardHecErr:1;/**< [23] Discard cells with an invalid HEC.
-     @li 1 - Discard cells with HEC errors
-    @li 0 - Cells with HEC errors are passed */
-
-    unsigned int discardParErr:1;/**< [22] Discard cells containing parity errors.
-     @li 1 - Discard cells with parity errors
-    @li 0 - Cells with parity errors are passed */
-
-    unsigned int discardIdle:1;    /**< [21] Discard Idle Cells based on DefineIdle register values
- @li    1 - Discard IDLE cells
-    @li 0 - IDLE cells passed */
-
-    unsigned int enbHecErrCnt:1;/**< [20] Enable Receive HEC Error Count.
-    @li 1 - Enable count of received cells containing HEC errors
-    @li 0 - No count is maintained. */
-
-    unsigned int enbParErrCnt:1;/**< [19] Enable Parity Error Count
-    @li    1 - Enable count of received cells containing Parity errors
-    @li 0 - No count is maintained. */
-
-    unsigned int enbIdleCellCnt:1;/**< [18] Enable Receive Idle Cell Count.
-      @li 1 - Enable count of Idle cells received.
-    @li 0 - No count is maintained.*/
-
-    unsigned int enbSizeErrCnt:1;/**< [17] Enable Receive Size Error Count.
-     @li 1 - Enable count of received cells of incorrect size
-    @li    0 - No count is maintained. */
-
-    unsigned int enbRxCellCnt:1;/**< [16] Enable Receive Valid Cell Count of non-idle/non-error cells.
-    @li    1 - Enable count of valid cells received - non-idle/non-error
-    @li 0 - No count is maintained. */
-
-    unsigned int reserved_1:3;    /**< [15:13] These bits are always 0 */
-
-    unsigned int rxCellOvrInt:1;      /**< [12] Enable CBI Utopia Receive Status Condition if the RxCellCount
-      register overflows.
-      @li 1 - CBI Receive Status asserted.
-      @li    0 - No CBI Receive Status asserted.*/
-
-    unsigned int invalidHecOvrInt:1;  /**< [11] Enable CBI Receive Status Condition if the InvalidHecCount
-    register overflows.
-    @li    1 - CBI Receive Condition asserted.
-      @li 0 - No CBI Receive Condition asserted */
-
-    unsigned int invalidParOvrInt:1;  /**< [10] Enable CBI Receive Status Condition if the InvalidParCount
-    register overflows
-    @li    1 - CBI Receive Condition asserted.
-      @li 0 - No CBI Receive Condition asserted */
-
-    unsigned int invalidSizeOvrInt:1;   /**< [9] Enable CBI Receive Status Condition if the InvalidSizeCount
-     register overflows.
-     @li 1 - CBI Receive Status Condition asserted.
-      @li¸0 - No CBI Receive Status asserted */
-
-    unsigned int rxIdleOvrInt:1;      /**< [8] Enable CBI Receive Status Condition if the RxIdleCount overflows.
-      @li    1 - CBI Receive Condition asserted.
-      @li 0 - No CBI Receive Condition asserted */
-
-    unsigned int reserved_2:3;    /**< [7:5] These bits are always 0 */
-
-    unsigned int rxAddrMask:5;    /**< [4:0] This register is used as a mask to allow the user to increase
-    the PHY receive address range. The register should be programmed with
-    the address-range limit, i.e. if set to 0x3 the address range increases
-  to a maximum of 4 addresses. */
-    } utRxEnableFields;      /**< Rx enable Utopia register */
-
-      /**
-    * @ingroup IxAtmdAccUtopiaCtrlAPI
-      * @struct UtRxTransTable0_
-      * @brief Utopia Rx translation table Register
-    */
-    struct UtRxTransTable0_
-    {
-
-    unsigned int phy0:5;  /**< [31-27] Rx Mapping value of logical phy 0 */
-
-    unsigned int phy1:5;  /**< [26-22] Rx Mapping value of logical phy 1 */
-
-    unsigned int phy2:5;  /**< [21-17] Rx Mapping value of logical phy 2 */
-
-    unsigned int reserved_1:1;  /**< [16] These bits are always 0 */
-
-    unsigned int phy3:5;  /**< [15-11] Rx Mapping value of logical phy 3 */
-
-    unsigned int phy4:5;  /**< [10-6] Rx Mapping value of logical phy 4 */
-
-    unsigned int phy5:5;  /**< [5-1] Rx Mapping value of logical phy 5 */
-
-    unsigned int reserved_2:1;  /**< [0] These bits are always 0 */
-    }
-
-    utRxTransTable0;  /**< Rx translation table */
-
-  /**
-    * @ingroup IxAtmdAccUtopiaCtrlAPI
-  * @struct UtRxTransTable1_
-  * @brief Utopia Rx translation table Register
-    */
-    struct UtRxTransTable1_
-    {
-
-    unsigned int phy6:5;  /**< [31-27] Rx Mapping value of logical phy 6 */
-
-    unsigned int phy7:5;  /**< [26-22] Rx Mapping value of logical phy 7 */
-
-    unsigned int phy8:5;  /**< [21-17] Rx Mapping value of logical phy 8 */
-
-    unsigned int reserved_1:1; /**< [16-0] These bits are always 0 */
-
-    unsigned int phy9:5;  /**< [15-11] Rx Mapping value of logical phy 3 */
-
-    unsigned int phy10:5;   /**< [10-6] Rx Mapping value of logical phy 4 */
-
-    unsigned int phy11:5;   /**< [5-1] Rx Mapping value of logical phy 5 */
-
-    unsigned int reserved_2:1;  /**< [0] These bits are always 0 */
-    }
-
-    utRxTransTable1;  /**< Rx translation table */
-
-    /**
-    * @ingroup IxAtmdAccUtopiaCtrlAPI
-    * @struct UtRxTransTable2_
-    * @brief Utopia Rx translation table Register
-    */
-    struct UtRxTransTable2_
-    {
-
-    unsigned int phy12:5;   /**< [31-27] Rx Mapping value of logical phy 6 */
-
-    unsigned int phy13:5;   /**< [26-22] Rx Mapping value of logical phy 7 */
-
-    unsigned int phy14:5;   /**< [21-17] Rx Mapping value of logical phy 8 */
-
-    unsigned int reserved_1:1; /**< [16-0] These bits are always 0 */
-
-    unsigned int phy15:5;   /**< [15-11] Rx Mapping value of logical phy 3 */
-
-    unsigned int phy16:5;   /**< [10-6] Rx Mapping value of logical phy 4 */
-
-    unsigned int phy17:5;   /**< [5-1] Rx Mapping value of logical phy 5 */
-
-    unsigned int reserved_2:1;  /**< [0] These bits are always 0 */
-    } utRxTransTable2;    /**< Rx translation table */
-
-    /**
-    * @ingroup IxAtmdAccUtopiaCtrlAPI
-    * @struct UtRxTransTable3_
-    * @brief Utopia Rx translation table Register
-    */
-    struct UtRxTransTable3_
-    {
-
-    unsigned int phy18:5;   /**< [31-27] Rx Mapping value of logical phy 6 */
-
-    unsigned int phy19:5;   /**< [26-22] Rx Mapping value of logical phy 7 */
-
-    unsigned int phy20:5;   /**< [21-17] Rx Mapping value of logical phy 8 */
-
-    unsigned int reserved_1:1; /**< [16-0] These bits are always 0 */
-
-    unsigned int phy21:5;   /**< [15-11] Rx Mapping value of logical phy 3 */
-
-    unsigned int phy22:5;   /**< [10-6] Rx Mapping value of logical phy 4 */
-
-    unsigned int phy23:5;   /**< [5-1] Rx Mapping value of logical phy 5 */
-
-    unsigned int reserved_2:1;  /**< [0] These bits are always 0 */
-    } utRxTransTable3;  /**< Rx translation table */
-
-    /**
-    * @ingroup IxAtmdAccUtopiaCtrlAPI
-    * @struct UtRxTransTable4_
-    * @brief Utopia Rx translation table Register
-    */
-    struct UtRxTransTable4_
-    {
-
-    unsigned int phy24:5;   /**< [31-27] Rx Mapping value of logical phy 6 */
-
-    unsigned int phy25:5;   /**< [26-22] Rx Mapping value of logical phy 7 */
-
-    unsigned int phy26:5;   /**< [21-17] Rx Mapping value of logical phy 8 */
-
-    unsigned int reserved_1:1; /**< [16-0] These bits are always 0 */
-
-    unsigned int phy27:5;   /**< [15-11] Rx Mapping value of logical phy 3 */
-
-    unsigned int phy28:5;   /**< [10-6] Rx Mapping value of logical phy 4 */
-
-    unsigned int phy29:5;   /**< [5-1] Rx Mapping value of logical phy 5 */
-
-    unsigned int reserved_2:1;  /**< [0] These bits are always 0 */
-    } utRxTransTable4;  /**< Rx translation table */
-
-    /**
-    * @ingroup IxAtmdAccUtopiaCtrlAPI
-    * @struct UtRxTransTable5_
-    * @brief Utopia Rx translation table Register
-    */
-    struct UtRxTransTable5_
-    {
-
-    unsigned int phy30:5;   /**< [31-27] Rx Mapping value of logical phy 6 */
-
-    unsigned int reserved_1:27;     /**< [26-0] These bits are always 0 */
-
-    } utRxTransTable5;  /**< Rx translation table */
-
-    /**
-    * @ingroup IxAtmdAccUtopiaCtrlAPI
-    * @struct UtSysConfig_
-    * @brief NPE setup Register
-    */
-    struct UtSysConfig_
-    {
-
-    unsigned int reserved_1:2;     /**< [31-30] These bits are always 0 */
-    unsigned int txEnbFSM:1;    /**< [29] Enables the operation ofthe Utopia Transmit FSM
-   * @li 1 - FSM enabled
-   * @li 0 - FSM inactive
-   */
-    unsigned int rxEnbFSM:1;    /**< [28] Enables the operation ofthe Utopia Revieve FSM
-   * @li 1 - FSM enabled
-   * @li 0 - FSM inactive
-   */
-    unsigned int disablePins:1;    /**< [27] Disable Utopia interface I/O pins forcing the signals to an
-   * inactive state.  Note that this bit is set on reset and must be
-   * de-asserted
-   * @li 0 - Normal data transfer
-   * @li    1 - Utopia interface pins are forced inactive
-    */
-    unsigned int tstLoop:1;    /**< [26] Test Loop Back Enable.
-    * @li Note: For loop back to function RxMode and Tx Mode must both be set
-    * to single PHY mode.
-    * @li 0 - Loop back
-    * @li 1 - Normal operating mode
-    */
-
-    unsigned int txReset:1;   /**< [25] Resets the Utopia Coprocessor transmit module to a known state.
-    * @li Note: All transmit configuration and status registers will be reset
-    * to their reset values.
-    * @li 0 - Normal operating mode¸
-    * @li 1 - Reset transmit modules
-    */
-
-    unsigned int rxReset:1;   /**< [24] Resets the Utopia Coprocessor receive module to a known state.
-    * @li Note: All receive configuration and status registers will be reset
-    * to their reset values.
-    * @li    0 - Normal operating mode
-    * @li 1 - Reset receive modules
-    */
-
-    unsigned int reserved_2:24;     /**< [23-0] These bits are always 0 */
-    } utSysConfig;  /**< NPE debug config */
-
-}
-IxAtmdAccUtopiaConfig;
-
-/**
-*
-* @brief Utopia status
-*
-* This structure is used to set/get the Utopia status parameters
-* @li contains debug cell counters, to be accessed during a read operation
-*
-* @note - the exact description of all parameters is done in the Utopia reference
-*   documents.
-*
-*/
-typedef struct
-{
-
-    unsigned int utTxCellCount;  /**< count of cells transmitted */
-
-    unsigned int utTxIdleCellCount;    /**< count of idle cells transmitted */
-
-    /**
-    * @ingroup IxAtmdAccUtopiaCtrlAPI
-    * @struct UtTxCellConditionStatus_
-    * @brief Utopia Tx Status Register
-    */
-    struct UtTxCellConditionStatus_
-    {
-
-    unsigned int reserved_1:2;   /**< [31:30] These bits are always 0 */
-    unsigned int txFIFO2Underflow:1; /**< [29] This bit is set if 64-byte
-                                     * Transmit FIFO2 indicates a FIFO underflow
-                                     * error condition.
-                                     */
-    unsigned int txFIFO1Underflow:1; /**< [28] This bit is set if
-                                     * 64-byte Transmit FIFO1 indicates a FIFO
-                                     * underflow error condition.
-                                     */
-    unsigned int txFIFO2Overflow:1;  /**< [27] This bit is set if 64-byte
-                                     * Transmit FIFO2 indicates a FIFO overflow
-                                     * error condition.
-                                     */
-    unsigned int txFIFO1Overflow:1; /**< [26] This bit is set if 64-byte
-                                    * Transmit FIFO1 indicates a FIFO overflow
-                                    * error condition.
-                                    */
-    unsigned int txIdleCellCountOvr:1; /**< [25] This bit is set if the
-                                       * TxIdleCellCount register overflows.
-                                       */
-    unsigned int txCellCountOvr:1; /**< [24] This bit is set if the
-                                   * TxCellCount register overflows
-                                   */
-    unsigned int reserved_2:24;    /**< [23:0] These bits are always 0 */
-    } utTxCellConditionStatus;    /**< Tx cells condition status */
-
-    unsigned int utRxCellCount; /**< count of cell received */
-    unsigned int utRxIdleCellCount;    /**< count of idle cell received */
-    unsigned int utRxInvalidHECount;     /**< count of invalid cell
-                                        * received because of HEC errors
-                                        */
-    unsigned int utRxInvalidParCount;  /**< count of invalid cell received
-                                        * because of parity errors
-                                        */
-    unsigned int utRxInvalidSizeCount;  /**< count of invalid cell
-                                        * received because of cell
-                                        * size errors
-                                        */
-
-    /**
-    * @ingroup IxAtmdAccUtopiaCtrlAPI
-    * @struct UtRxCellConditionStatus_
-    * @brief Utopia Rx Status Register
-    */
-    struct UtRxCellConditionStatus_
-    {
-
-    unsigned int reserved_1:3;  /**< [31:29] These bits are always 0.*/
-    unsigned int rxCellCountOvr:1;      /**< [28] This bit is set if the RxCellCount register overflows. */
-    unsigned int invalidHecCountOvr:1;    /**< [27] This bit is set if the InvalidHecCount register overflows.*/
-    unsigned int invalidParCountOvr:1;    /**< [26] This bit is set if the InvalidParCount register overflows.*/
-    unsigned int invalidSizeCountOvr:1;    /**< [25] This bit is set if the InvalidSizeCount register overflows.*/
-    unsigned int rxIdleCountOvr:1;      /**< [24] This bit is set if the RxIdleCount register overflows.*/
-    unsigned int reserved_2:4;  /**< [23:20] These bits are always 0 */
-    unsigned int rxFIFO2Underflow:1;  /**< [19] This bit is set if 64-byte Receive FIFO2
-                                      * indicates a FIFO underflow error condition.
-                                      */
-    unsigned int rxFIFO1Underflow:1;  /**< [18] This bit is set if 64-byte Receive
-                                      * FIFO1 indicates a FIFO underflow error condition
-                                    . */
-    unsigned int rxFIFO2Overflow:1;    /**< [17] This bit is set if 64-byte Receive FIFO2
-                                       * indicates a FIFO overflow error condition.
-                                        */
-    unsigned int rxFIFO1Overflow:1;    /**< [16] This bit is set if 64-byte Receive FIFO1
-                                    * indicates a FIFO overflow error condition.
-                                    */
-    unsigned int reserved_3:16;      /**< [15:0] These bits are always 0. */
-    } utRxCellConditionStatus;    /**< Rx cells condition status */
-
-} IxAtmdAccUtopiaStatus;
-
-/**
- * @} defgroup IxAtmdAccUtopiaCtrlAPI
- */
-
- /**
- *
- * @ingroup IxAtmdAccCtrlAPI
- *
- * @fn ixAtmdAccUtopiaConfigSet (const IxAtmdAccUtopiaConfig *
-                        ixAtmdAccUtopiaConfigPtr)
- *
- * @brief Send the configuration structure to the Utopia interface
- *
- * This function downloads the @a IxAtmdAccUtopiaConfig structure to
- * the Utopia and has the following effects
- *  @li setup the Utopia interface
- *  @li initialise the NPE
- *  @li reset the Utopia cell counters and status registers to known values
- *
- * This action has to be done once at initialisation. A lock is preventing
- * the concurrent use of @a ixAtmdAccUtopiaStatusGet() and
- * @A ixAtmdAccUtopiaConfigSet()
- *
- * @param *ixAtmdAccNPEConfigPtr @ref IxAtmdAccUtopiaConfig [in] - pointer to a structure to download to
- *  Utopia. This parameter cannot be a null pointer.
- *
- * @return @li IX_SUCCESS successful download
- * @return @li IX_FAIL error in the parameters, or configuration is not
- *         complete or failed
- *
- * @sa ixAtmdAccUtopiaStatusGet
- *
- */
-PUBLIC IX_STATUS ixAtmdAccUtopiaConfigSet (const IxAtmdAccUtopiaConfig *
-                        ixAtmdAccUtopiaConfigPtr);
-
-/**
- *
- * @ingroup IxAtmdAccCtrlAPI
- *
- * @fn ixAtmdAccUtopiaStatusGet (IxAtmdAccUtopiaStatus *
-                        ixAtmdAccUtopiaStatus)
- *
- * @brief Get the Utopia interface configuration.
- *
- * This function reads the Utopia registers and the Cell counts
- * and fills the @a IxAtmdAccUtopiaStatus structure
- *
- * A lock is preventing the concurrent
- * use of @a ixAtmdAccUtopiaStatusGet() and @A ixAtmdAccUtopiaConfigSet()
- *
- * @param ixAtmdAccUtopiaStatus @ref IxAtmdAccUtopiaStatus [out] - pointer to structure to be updated from internal
- *        hardware counters. This parameter cannot be a NULL pointer.
- *
- * @return @li IX_SUCCESS successful read
- * @return @li IX_FAIL error in the parameters null pointer, or
- *          configuration read is not complete or failed
- *
- * @sa ixAtmdAccUtopiaConfigSet
- *
- */
-PUBLIC IX_STATUS ixAtmdAccUtopiaStatusGet (IxAtmdAccUtopiaStatus *
-                        ixAtmdAccUtopiaStatus);
-
-/**
- *
- * @ingroup IxAtmdAcc
- *
- * @fn ixAtmdAccPortEnable (IxAtmLogicalPort port)
- *
- * @brief enable a PHY logical port
- *
- * This function enables the transmission over one port. It should be
- * called before accessing any resource from this port and before the
- * establishment of a VC.
- *
- * When a port is enabled, the cell transmission to the Utopia interface
- * is started. If there is no traffic already running, idle cells are
- * sent over the interface.
- *
- * This function can be called multiple times.
- *
- * @param port @ref IxAtmLogicalPort [in] - logical PHY port [@a IX_UTOPIA_PORT_0 .. @a IX_UTOPIA_MAX_PORTS - 1]
- *
- * @return @li IX_SUCCESS enable is complete
- * @return @li IX_ATMDACC_WARNING port already enabled
- * @return @li IX_FAIL enable failed, wrong parameter, or cannot
- *         initialise this port (the port is maybe already in use,
- *         or there is a hardware issue)
- *
- * @note - This function needs internal locks and should not be
- *         called from an interrupt context
- *
- * @sa ixAtmdAccPortDisable
- *
- */
-PUBLIC IX_STATUS ixAtmdAccPortEnable (IxAtmLogicalPort port);
-
-/**
- *
- * @ingroup IxAtmdAccCtrlAPI
- *
- * @fn ixAtmdAccPortDisable (IxAtmLogicalPort port)
- *
- * @brief disable a PHY logical port
- *
- * This function disable the transmission over one port.
- *
- * When a port is disabled, the cell transmission to the Utopia interface
- * is stopped.
- *
- * @param port @ref IxAtmLogicalPort [in] - logical PHY port [@a IX_UTOPIA_PORT_0 .. @a IX_UTOPIA_MAX_PORTS - 1]
- *
- * @return @li IX_SUCCESS disable is complete
- * @return @li IX_ATMDACC_WARNING port already disabled
- * @return @li IX_FAIL disable failed, wrong parameter .
- *
- * @note - This function needs internal locks and should not be called
- *         from an interrupt context
- *
- * @note - The response from hardware is done through the txDone mechanism
- *         to ensure the synchrnisation with tx resources. Therefore, the
- *         txDone mechanism needs to be serviced to make a PortDisable complete.
- *
- * @sa ixAtmdAccPortEnable
- * @sa ixAtmdAccPortDisableComplete
- * @sa ixAtmdAccTxDoneDispatch
- *
- */
-PUBLIC IX_STATUS ixAtmdAccPortDisable (IxAtmLogicalPort port);
-
-/**
-*
-* @ingroup IxAtmdAccCtrlAPI
-*
-* @fn ixAtmdAccPortDisableComplete (IxAtmLogicalPort port)
-*
-* @brief disable a PHY logical port
-*
-* This function indicates if the port disable for a port has completed. This
-* function will return TRUE if the port has never been enabled.
-*
-* @param port @ref IxAtmLogicalPort [in] - logical PHY port [@a IX_UTOPIA_PORT_0 .. @a IX_UTOPIA_MAX_PORTS - 1]
-*
-* @return @li TRUE disable is complete
-* @return @li FALSE disable failed, wrong parameter .
-*
-* @note - This function needs internal locks and should not be called
-*         from an interrupt context
-*
-* @sa ixAtmdAccPortEnable
-* @sa ixAtmdAccPortDisable
-*
-*/
-PUBLIC BOOL ixAtmdAccPortDisableComplete (IxAtmLogicalPort port);
-
-#endif /* IXATMDACCCTRL_H */
-
-/**
- * @} defgroup IxAtmdAccCtrlAPI
- */
-
-
diff --git a/arch/arm/cpu/ixp/npe/include/IxAtmm.h b/arch/arm/cpu/ixp/npe/include/IxAtmm.h
deleted file mode 100644
index fcf523f..0000000
--- a/arch/arm/cpu/ixp/npe/include/IxAtmm.h
+++ /dev/null
@@ -1,795 +0,0 @@
-/**
- * @file    IxAtmm.h
- *
- * @date    3-DEC-2001
- *
- * @brief   Header file for the IXP400 ATM Manager component (IxAtmm)
- *
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- * 
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- * 
- * @par
- * -- End of Copyright Notice --
- */
-
-
-/**
- * @defgroup IxAtmm IXP400 ATM Manager (IxAtmm) API
- *
- * @brief IXP400 ATM Manager component Public API
- *
- * @{
- */
-
-#ifndef IXATMM_H
-#define IXATMM_H
-
-/*
- * Put the user defined include files required
- */
-#include "IxAtmSch.h"
-#include "IxOsalTypes.h"
-
-/*
- * #defines and macros used in this file.
- */
-
-/** 
- * @def IX_ATMM_RET_ALREADY_INITIALIZED
- * 
- * @brief Component has already been initialized 
- */
-#define IX_ATMM_RET_ALREADY_INITIALIZED 2
-
-/** 
- * @def IX_ATMM_RET_INVALID_PORT
- * 
- * @brief Specified port does not exist or is out of range */
-#define IX_ATMM_RET_INVALID_PORT 3
-
-/** 
- * @def IX_ATMM_RET_INVALID_VC_DESCRIPTOR
- * 
- * @brief The VC description does not adhere to ATM standards */
-#define IX_ATMM_RET_INVALID_VC_DESCRIPTOR 4
-
-/** 
- * @def IX_ATMM_RET_VC_CONFLICT
- * 
- * @brief The VPI/VCI values supplied are either reserved, or they
- *         conflict with a previously registered VC on this port */
-#define IX_ATMM_RET_VC_CONFLICT 5
-
-/** 
- * @def IX_ATMM_RET_PORT_CAPACITY_IS_FULL
- * 
- * @brief The virtual connection cannot be established on the port
- *         because the remaining port capacity is not sufficient to
- *         support it */
-#define IX_ATMM_RET_PORT_CAPACITY_IS_FULL 6
-
-/** 
- * @def IX_ATMM_RET_NO_SUCH_VC
- * 
- * @brief No registered VC, as described by the supplied VCI/VPI or
- *         VC identifier values, exists on this port */
-#define IX_ATMM_RET_NO_SUCH_VC 7
-
-/** 
- * @def IX_ATMM_RET_INVALID_VC_ID
- * 
- * @brief The specified VC identifier is out of range. */
-#define IX_ATMM_RET_INVALID_VC_ID 8
-
-/** 
- * @def IX_ATMM_RET_INVALID_PARAM_PTR
- * 
- * @brief A pointer parameter was NULL. */
-#define IX_ATMM_RET_INVALID_PARAM_PTR 9
-
-/** 
- * @def IX_ATMM_UTOPIA_SPHY_ADDR  
- * 
- * @brief The phy address when in SPHY mode */
-#define IX_ATMM_UTOPIA_SPHY_ADDR 31
-
-/**
- * @def IX_ATMM_THREAD_PRI_HIGH
- *
- * @brief The value of high priority thread */
-#define IX_ATMM_THREAD_PRI_HIGH 90
-
-/*
- * Typedefs whose scope is limited to this file.
- */
-
-/** @brief Definition for use in the @ref IxAtmmVc structure.
- *         Indicates the direction of a VC */
-typedef enum
-{
-    IX_ATMM_VC_DIRECTION_TX=0, /**< Atmm Vc direction transmit*/
-    IX_ATMM_VC_DIRECTION_RX, /**< Atmm Vc direction receive*/
-    IX_ATMM_VC_DIRECTION_INVALID /**< Atmm Vc direction invalid*/
-} IxAtmmVcDirection;
-
-/** @brief Definition for use with @ref IxAtmmVcChangeCallback
- *         callback.  Indicates that the event type represented by the
- *         callback for this VC. */
-typedef enum
-{
-    IX_ATMM_VC_CHANGE_EVENT_REGISTER=0, /**< Atmm Vc event register*/
-    IX_ATMM_VC_CHANGE_EVENT_DEREGISTER, /**< Atmm Vc event de-register*/
-    IX_ATMM_VC_CHANGE_EVENT_INVALID /**< Atmm Vc event invalid*/
-} IxAtmmVcChangeEvent;
-
-/** @brief Definitions for use with @ref ixAtmmUTOPIAInit interface to
- *         indicate that UTOPIA loopback should be enabled or disabled
- *         on initialisation. */
-typedef enum
-{
-    IX_ATMM_UTOPIA_LOOPBACK_DISABLED=0, /**< Atmm Utopia loopback mode disabled*/
-    IX_ATMM_UTOPIA_LOOPBACK_ENABLED, /**< Atmm Utopia loopback mode enabled*/
-    IX_ATMM_UTOPIA_LOOPBACK_INVALID /**< Atmm Utopia loopback mode invalid*/
-} IxAtmmUtopiaLoopbackMode;
-
-/** @brief This structure describes the required attributes of a
- *         virtual connection.
-*/
-typedef struct {
-    unsigned vpi;  /**< VPI value of this virtual connection */
-    unsigned vci;  /**< VCI value of this virtual connection. */
-    IxAtmmVcDirection direction; /**< VC direction */
-
-    /** Traffic descriptor of this virtual connection.  This structure
-     *  is defined by the @ref IxAtmSch component.  */
-    IxAtmTrafficDescriptor trafficDesc;
-} IxAtmmVc;
-
-
-/** @brief Definitions for use with @ref ixAtmmUtopiaInit interface to
- *         indicate that UTOPIA multi-phy/single-phy mode is used.
- */
-typedef enum
-{
-    IX_ATMM_MPHY_MODE = 0, /**< Atmm phy mode mphy*/
-    IX_ATMM_SPHY_MODE, /**< Atmm phy mode sphy*/
-    IX_ATMM_PHY_MODE_INVALID /**< Atmm phy mode invalid*/
-} IxAtmmPhyMode;
-
-
-/** @brief Structure contains port-specific information required to
- *         initialize IxAtmm, and specifically, the IXP400 UTOPIA
- *         Level-2 device. */
-typedef struct {
-    unsigned reserved_1:11;     /**< [31:21] Should be zero */
-    unsigned UtopiaTxPhyAddr:5; /**< [20:16] Address of the
-     *   transmit (Tx) PHY for this
-     *   port on the 5-bit UTOPIA
-     *   Level-2 address bus */
-    unsigned reserved_2:11;     /**< [15:5] Should be zero */
-    unsigned UtopiaRxPhyAddr:5; /**< [4:0] Address of the receive
-     *   (Rx) PHY for this port on the
-     *   5-bit UTOPIA  Level-2
-     *   address bus */
-} IxAtmmPortCfg;
-
-/** @brief Callback type used with @ref ixAtmmVcChangeCallbackRegister interface
- *         Defines a callback type  which will be used to notify registered
- *         users of registration/deregistration events on a particular port
- *
- * @param eventType @ref IxAtmmVcChangeEvent [in] - Event indicating
- *                        whether the VC supplied has been added or
- *                        removed
- *
- * @param port @ref IxAtmLogicalPort [in] - Specifies the port on which the event has
- *                        occurred
- *
- * @param vcChanged @ref IxAtmmVc* [in] - Pointer to a structure which gives
- *                              details of the VC which has been added
- *                              or removed on the port
- */
-typedef void (*IxAtmmVcChangeCallback) (IxAtmmVcChangeEvent eventType,
-					IxAtmLogicalPort port,
-					const IxAtmmVc* vcChanged);
-
-/*
- * Variable declarations global to this file only. Externs are followed by
- * static variables.
- */
-
-/*
- * Extern function prototypes
- */
-
-/*
- * Function declarations
- */
-
-
-/** 
- * @ingroup IxAtmm
- *
- * @fn ixAtmmInit (void)
- *
- * @brief Interface to initialize the IxAtmm software component.  Can
- *         be called once only.
- *
- *  Must be called before any other IxAtmm API is called.
- *
- * @param "none"
- *
- *  @return @li  IX_SUCCESS : IxAtmm has been successfully initialized.
- *      Calls to other IxAtmm interfaces may now be performed.
- *  @return @li  IX_FAIL : IxAtmm has already been initialized.
- */
-PUBLIC IX_STATUS
-ixAtmmInit (void);
-
-/**  
- * @ingroup IxAtmm
- * 
- * @fn ixAtmmUtopiaInit (unsigned numPorts,
-		  IxAtmmPhyMode phyMode,
-		  IxAtmmPortCfg portCfgs[],
-		  IxAtmmUtopiaLoopbackMode loopbackMode)
- *
- * @brief Interface to initialize the UTOPIA Level-2 ATM coprocessor
- *         for the specified number of physical ports.  The function
- *         must be called before the ixAtmmPortInitialize interface
- *         can operate successfully.
- *
- * @param numPorts unsigned [in] - Indicates the total number of logical
- *          ports that are active on the device.  Up to 12 ports are
- *          supported.
- *
- * @param phyMode @ref IxAtmmPhyMode [in] - Put the Utopia coprocessor in SPHY
- *        or MPHY mode.
- *
- * @param portCfgs[] @ref IxAtmmPortCfg [in] - Pointer to an array of elements
- *          detailing the UTOPIA specific port characteristics.  The
- *          length of the array must be equal to the number of ports
- *          activated.  ATM ports are referred to by the relevant
- *          offset in this array in all subsequent IxAtmm interface
- *          calls.
- *
- * @param loopbackMode @ref IxAtmmUtopiaLoopbackMode [in] - Value must be one of
- *          @ref IX_ATMM_UTOPIA_LOOPBACK_ENABLED or @ref
- *          IX_ATMM_UTOPIA_LOOPBACK_DISABLED indicating whether
- *          loopback should be enabled on the device.  Loopback can
- *          only be supported on a single PHY, therefore the numPorts
- *          parameter must be 1 if loopback is enabled.
- *
- * @return @li IX_SUCCESS : Indicates that the  UTOPIA device has been
- *      successfully initialized for the supplied ports.
- * @return @li IX_ATMM_RET_ALREADY_INITIALIZED : The UTOPIA device has
- *      already been initialized.
- * @return @li IX_FAIL : The supplied parameters are invalid or have been
- *     rejected by the UTOPIA-NPE device.
- *
- * @warning
- * This interface may only be called once.
- * Port identifiers are assumed to range from 0 to (numPorts - 1) in all 
- * instances.
- * In all subsequent calls to interfaces supplied by IxAtmm, the specified
- * port value is expected to represent the offset in the portCfgs array
- * specified in this interface.  i.e. The first port in this array will
- * subsequently be represented as port 0, the second port as port 1,
- * and so on.*/
-PUBLIC IX_STATUS
-ixAtmmUtopiaInit (unsigned numPorts,
-		  IxAtmmPhyMode phyMode,
-		  IxAtmmPortCfg portCfgs[],
-		  IxAtmmUtopiaLoopbackMode loopbackMode);
-
-
-/**   
- * @ingroup IxAtmm
- * 
- * @fn ixAtmmPortInitialize (IxAtmLogicalPort port,
-		      unsigned txPortRate,
-		      unsigned rxPortRate)
- *
- * @brief The interface is called following @ref ixAtmmUtopiaInit ()
- *         and before calls to any other IxAtmm interface.  It serves
- *         to activate the registered ATM port with IxAtmm.
- *
- *  The transmit and receive port rates are specified in bits per
- *  second.  This translates to ATM cells per second according to the
- *  following formula: CellsPerSecond = portRate / (53*8)  The
- *  IXP400 device supports only 53 byte cells. The client shall make
- *  sure that the off-chip physical layer device has already been
- *  initialized.
- *
- *  IxAtmm will configure IxAtmdAcc and IxAtmSch to enable scheduling
- *  on the port.
- *
- *  This interface must be called once for each active port in the
- *  system.  The first time the interface is invoked, it will configure
- *  the mechanism by which the handling of transmit, transmit-done and
- *  receive are driven with the IxAtmdAcc component.
- *
- *  This function is reentrant.
- *
- *  @note The minimum tx rate that will be accepted is 424 bit/s which equates
- *        to 1 cell (53 bytes) per second.
- *
- * @param port @ref IxAtmLogicalPort [in] - Identifies the port which is to be
- *          initialized.
- *
- * @param txPortRate unsigned [in] - Value specifies the
- *          transmit port rate for this port in
- *          bits/second.  This value is used by the ATM Scheduler
- *          component is evaluating VC access requests for the port.
- *
- * @param rxPortRate unsigned [in] - Value specifies the
- *          receive port rate for this port in bits/second.
- *
- * @return @li IX_SUCCESS : The specificed ATM port has been successfully
- *       initialized. IxAtmm is ready to accept VC registrations on
- *       this port.
- *
- * @return @li IX_ATMM_RET_ALREADY_INITIALIZED : ixAtmmPortInitialize has
- *       already been called successfully on this port.  The current
- *       call is rejected.
- *
- * @return @li IX_ATMM_RET_INVALID_PORT : The port value indicated in the
- *       input is not valid.  The request is rejected.
- *
- * @return @li IX_FAIL : IxAtmm could not initialize the port because the
- * inputs are not understood.
- *
- * @sa ixAtmmPortEnable, ixAtmmPortDisable
- *
- */
-PUBLIC IX_STATUS
-ixAtmmPortInitialize (IxAtmLogicalPort port,
-		      unsigned txPortRate,
-		      unsigned rxPortRate);
-
-/**    
- * @ingroup IxAtmm
- * 
- * @fn ixAtmmPortModify (IxAtmLogicalPort port,
-		  unsigned txPortRate,
-		  unsigned rxPortRate)
- *
- * @brief A client may call this interface to change the existing
- *         port rate (expressed in bits/second) on an established ATM
- *         port.
- *
- * @param port @ref IxAtmLogicalPort [in] - Identifies the port which is to be
- *          initialized.
- *
- * @param txPortRate unsigned [in] -  Value specifies the``
- *          transmit port rate for this port in
- *          bits/second.  This value is used by the ATM Scheduler
- *          component is evaluating VC access requests for the port.
- *
- * @param rxPortRate unsigned [in] - Value specifies the
- *          receive port rate for this port in
- *          bits/second.
- *
- * @return @li IX_SUCCESS : The indicated ATM port rates have been
- *      successfully modified.
- *
- * @return @li IX_ATMM_RET_INVALID_PORT : The port value indicated in the
- *       input is not valid.  The request is rejected.
- *
- * @return @li IX_FAIL : IxAtmm could not update the port because the
- *       inputs are not understood, or the interface was called before
- * the port was initialized.  */
-PUBLIC IX_STATUS
-ixAtmmPortModify (IxAtmLogicalPort port,
-		  unsigned txPortRate,
-		  unsigned rxPortRate);
-
-/**    
- * @ingroup IxAtmm
- * 
- * @fn ixAtmmPortQuery (IxAtmLogicalPort port,
-		 unsigned *txPortRate,
-		 unsigned *rxPortRate);
-
- *
- * @brief The client may call this interface to request details on
- *          currently registered transmit and receive rates for an ATM
- *          port.
- *
- * @param port @ref IxAtmLogicalPort [in] - Value identifies the port from which the
- *          rate details are requested.
- *
- * @param *txPortRate unsigned [out] - Pointer to a value
- *          which will be filled with the value of the transmit port
- *          rate specified in bits/second.
- *
- * @param *rxPortRate unsigned [out] - Pointer to a value
- *          which will be filled with the value of the receive port
- *          rate specified in bits/second.
- *
- * @return @li IX_SUCCESS : The information requested on the specified
- *       port has been successfully supplied in the output.
- *
- * @return @li IX_ATMM_RET_INVALID_PORT : The port value indicated in the
- *       input is not valid.  The request is rejected.
- *
- * @return @li IX_ATMM_RET_INVALID_PARAM_PTR : A pointer parameter was
- *       NULL.
- *
- * @return @li IX_FAIL : IxAtmm could not update the port because the
- *       inputs are not understood, or the interface was called before
- *       the port was initialized.  */
-PUBLIC IX_STATUS
-ixAtmmPortQuery (IxAtmLogicalPort port,
-		 unsigned *txPortRate,
-		 unsigned *rxPortRate);
-
-/**    
- * @ingroup IxAtmm
- * 
- * @fn ixAtmmPortEnable(IxAtmLogicalPort port)
- *
- * @brief The client call this interface to enable transmit for an ATM
- *          port. At initialisation, all the ports are disabled.
- *
- * @param port @ref IxAtmLogicalPort [in] - Value identifies the port
- *
- * @return @li IX_SUCCESS : Transmission over this port is started.
- *
- * @return @li IX_FAIL : The port parameter is not valid, or the
- *       port is already enabled
- *
- * @note - When a port is disabled, Rx and Tx VC Connect requests will fail
- *
- * @note - This function uses system resources and should not be used
- *        inside an interrupt context.
- *
- * @sa ixAtmmPortDisable  */
-PUBLIC IX_STATUS
-ixAtmmPortEnable(IxAtmLogicalPort port);
-
-/**    
- * @ingroup IxAtmm
- * 
- * @fn ixAtmmPortDisable(IxAtmLogicalPort port)
- *
- * @brief The client call this interface to disable transmit for an ATM
- *          port. At initialisation, all the ports are disabled.
- *
- * @param port @ref IxAtmLogicalPort [in] - Value identifies the port
- *
- * @return @li IX_SUCCESS : Transmission over this port is stopped.
- *
- * @return @li IX_FAIL : The port parameter is not valid, or the
- *       port is already disabled
- *
- * @note - When a port is disabled, Rx and Tx VC Connect requests will fail
- *
- * @note - This function call does not stop RX traffic. It is supposed
- *        that this function is invoked when a serious problem
- *        is detected (e.g. physical layer broken). Then, the RX traffic
- *        is not passing.
- *
- * @note - This function is blocking until the hw acknowledge that the
- *        transmission is stopped.
- *
- * @note - This function uses system resources and should not be used
- *        inside an interrupt context.
- *
- * @sa ixAtmmPortEnable  */
-PUBLIC IX_STATUS
-ixAtmmPortDisable(IxAtmLogicalPort port);
-
-/**    
- * @ingroup IxAtmm
- * 
- * @fn ixAtmmVcRegister (IxAtmLogicalPort port,
-		  IxAtmmVc *vcToAdd,
-		  IxAtmSchedulerVcId *vcId)
- *
- * @brief This interface is used to register an ATM Virtual
- *         Connection on the specified ATM port.
- *
- *  Each call to this interface registers a unidirectional virtual
- *  connection with the parameters specified.  If a bi-directional VC
- *  is needed, the function should be called twice (once for each
- *  direction, Tx & Rx) where the VPI and VCI and port parameters in
- *  each call are identical.
- *
- *  With the addition of each new VC to a port, a series of
- *  callback functions are invoked by the IxAtmm component to notify
- *  possible external components of the change.  The callback functions
- *  are registered using the @ref ixAtmmVcChangeCallbackRegister interface.
- *
- *  The IxAtmSch component is notified of the registration of transmit
- *  VCs.
- *
- * @param port @ref IxAtmLogicalPort [in] - Identifies port on which the specified VC is
- *          to be registered.
- *
- * @param *vcToAdd @ref IxAtmmVc [in] -  Pointer to an @ref IxAtmmVc structure
- *          containing a description of the VC to be registered. The
- *          client shall fill the vpi, vci and direction and relevant
- *          trafficDesc members of this structure before calling this
- *          function.
- *
- * @param *vcId @ref IxAtmSchedulerVcId [out] - Pointer to an integer value which is filled
- *              with the per-port unique identifier value for this VC.
- *              This identifier will be required when a request is
- *              made to deregister or change this VC.  VC identifiers
- *              for transmit VCs will have a value between 0-43,
- *              i.e. 32 data Tx VCs + 12 OAM Tx Port VCs.
- *              Receive VCs will have a value between 44-66,
- *              i.e. 32 data Rx VCs + 1 OAM Rx VC.
- *
- * @return @li IX_SUCCESS : The VC has been successfully registered on
- *       this port. The VC is ready for a client to configure IxAtmdAcc
- *       for receive and transmit operations on the VC.
- * @return @li IX_ATMM_RET_INVALID_PORT : The port value indicated in the
- *       input is not valid or has not been initialized.  The request
- *       is rejected.
- * @return @li IX_ATMM_RET_INVALID_VC_DESCRIPTOR : The descriptor
- *       pointed to by vcToAdd is invalid.  The registration request
- *       is rejected.
- * @return @li IX_ATMM_RET_VC_CONFLICT : The VC requested conflicts with
- *      reserved VPI and/or VCI values or with another VC already activated
- *      on this port.
- * @return @li IX_ATMM_RET_PORT_CAPACITY_IS_FULL : The VC cannot be
- *       registered in the port becuase the port capacity is
- *       insufficient to support the requested ATM traffic contract.
- *       The registration request is rejected.
- * @return @li IX_ATMM_RET_INVALID_PARAM_PTR : A pointer parameter was
- *       NULL.
- *
- * @warning IxAtmm has no capability of signaling or negotiating a virtual
- *          connection. Negotiation of the admission of the VC to the network
- *          is beyond the scope of this function.  This is assumed to be
- *          performed by the calling client, if appropriate,
- *          before or after this function is called.
- */
-PUBLIC IX_STATUS
-ixAtmmVcRegister (IxAtmLogicalPort port,
-		  IxAtmmVc *vcToAdd,
-		  IxAtmSchedulerVcId *vcId);
-
-/**    
- * @ingroup IxAtmm
- * 
- * @fn ixAtmmVcDeregister (IxAtmLogicalPort port, IxAtmSchedulerVcId vcId)
- *
- * @brief Function called by a client to deregister a VC from the
- *         system.
- *
- *  With the removal of each new VC from a port, a series of
- *  registered callback functions are invoked by the IxAtmm component
- *  to notify possible external components of the change.  The callback
- *  functions are registered using the @ref ixAtmmVcChangeCallbackRegister.
- *
- *  The IxAtmSch component is notified of the removal of transmit VCs.
- *
- * @param port @ref IxAtmLogicalPort [in] - Identifies port on which the VC to be
- *          removed is currently registered.
- *
- * @param vcId @ref IxAtmSchedulerVcId [in] - VC identifier value of the VC to
- *          be deregistered.  This value was supplied to the client when
-            the VC was originally registered.  This value can also be
-	    queried from the IxAtmm component through the @ref ixAtmmVcQuery
- *          interface.
- *
- * @return @li IX_SUCCESS : The specified VC has been successfully
- *       removed from this port.
- * @return @li IX_ATMM_RET_INVALID_PORT : The port value indicated in the
- *       input is not valid or has not been initialized.  The request
- *       is rejected.
- * @return @li IX_FAIL : There is no registered VC associated with the
- *       supplied identifier registered on this port. */
-PUBLIC IX_STATUS
-ixAtmmVcDeregister (IxAtmLogicalPort port, IxAtmSchedulerVcId vcId);
-
-/**    
- * @ingroup IxAtmm
- * 
- * @fn ixAtmmVcQuery (IxAtmLogicalPort port,
-	       unsigned vpi,
-	       unsigned vci,
-	       IxAtmmVcDirection direction,
-	       IxAtmSchedulerVcId *vcId,
-	       IxAtmmVc *vcDesc)
- *
- * @brief This interface supplies information about an active VC on a
- *         particular port when supplied with the VPI, VCI and
- *         direction of that VC.
- *
- * @param port @ref IxAtmLogicalPort [in] - Identifies port on which the VC to be
- *          queried is currently registered.
- *
- * @param vpi unsigned [in] - ATM VPI value of the requested VC.
- *
- * @param vci unsigned [in] - ATM VCI value of the requested VC.
- *
- * @param direction @ref IxAtmmVcDirection [in] - One of @ref
- *          IX_ATMM_VC_DIRECTION_TX or @ref IX_ATMM_VC_DIRECTION_RX
- *          indicating the direction (Tx or Rx) of the requested VC.
- *
- * @param *vcId @ref IxAtmSchedulerVcId [out] - Pointer to an integer value which will be
- *              filled with the VC identifier value for the requested
- *              VC (as returned by @ref ixAtmmVcRegister), if it
- *              exists on this port.
- *
- * @param *vcDesc @ref IxAtmmVc [out] - Pointer to an @ref IxAtmmVc structure
- *              which will be filled with the specific details of the
- *              requested VC, if it exists on this port.
- *
- * @return @li IX_SUCCESS : The specified VC has been found on this port
- *       and the requested details have been returned.
- * @return @li IX_ATMM_RET_INVALID_PORT : The port value indicated in the
- *       input is not valid or has not been initialized.  The request
- *       is rejected.
- * @return @li IX_ATMM_RET_NO_SUCH_VC : No VC exists on the specified
- *       port which matches the search criteria (VPI, VCI, direction)
- *       given.  No data is returned.
- * @return @li IX_ATMM_RET_INVALID_PARAM_PTR : A pointer parameter was
- *       NULL.
- *
- */
-PUBLIC IX_STATUS
-ixAtmmVcQuery (IxAtmLogicalPort port,
-	       unsigned vpi,
-	       unsigned vci,
-	       IxAtmmVcDirection direction,
-	       IxAtmSchedulerVcId *vcId,
-	       IxAtmmVc *vcDesc);
-
-
-/**    
- * @ingroup IxAtmm
- * 
- * @fn ixAtmmVcIdQuery (IxAtmLogicalPort port, IxAtmSchedulerVcId vcId, IxAtmmVc *vcDesc)
- *
- * @brief This interface supplies information about an active VC on a
- *         particular port when supplied with a vcId for that VC.
- *
- * @param port @ref IxAtmLogicalPort [in] - Identifies port on which the VC to be
- *          queried is currently registered.
- *
- * @param vcId @ref IxAtmSchedulerVcId [in] - Value returned by @ref ixAtmmVcRegister which
- *          uniquely identifies the requested VC on this port.
- *
- * @param *vcDesc @ref IxAtmmVc [out] - Pointer to an @ref IxAtmmVc structure
- *              which will be filled with the specific details of the
- *              requested VC, if it exists on this port.
- *
- * @return @li IX_SUCCESS : The specified VC has been found on this port
- *       and the requested details have been returned.
- * @return @li IX_ATMM_RET_INVALID_PORT : The port value indicated in the
- *       input is not valid or has not been initialized.  The request
- *       is rejected.
- * @return @li IX_ATMM_RET_NO_SUCH_VC : No VC exists on the specified
- *       port which matches the supplied identifier.  No data is
- *       returned.
- * @return @li IX_ATMM_RET_INVALID_PARAM_PTR : A pointer parameter was
- *       NULL.
- */
-PUBLIC IX_STATUS
-ixAtmmVcIdQuery (IxAtmLogicalPort port, IxAtmSchedulerVcId vcId, IxAtmmVc *vcDesc);
-
-/**    
- * @ingroup IxAtmm
- * 
- * @fn ixAtmmVcChangeCallbackRegister (IxAtmmVcChangeCallback callback)
- *
- * @brief This interface is invoked to supply a function to IxAtmm
- *         which will be called to notify the client if a new VC is
- *         registered with IxAtmm or an existing VC is removed.
- *
- * The callback, when invoked, will run within the context of the call
- * to @ref ixAtmmVcRegister or @ref ixAtmmVcDeregister which caused
- * the change of state.
- *
- * A maximum of 32 calbacks may be registered in with IxAtmm.
- *
- * @param callback @ref IxAtmmVcChangeCallback [in] - Callback which complies
- *          with the @ref IxAtmmVcChangeCallback definition.  This
- *          function will be invoked by IxAtmm with the appropiate
- *          parameters for the relevant VC when any VC has been
- *          registered or deregistered with IxAtmm.
- *
- * @return @li IX_SUCCESS : The specified callback has been registered
- *      successfully with IxAtmm and will be invoked when appropriate.
- * @return @li IX_FAIL : Either the supplied callback is invalid, or
- *      IxAtmm has already registered 32 and connot accommodate
- *      any further registrations of this type.  The request is
- *      rejected.
- *
- * @warning The client must not call either the @ref
- *          ixAtmmVcRegister or @ref ixAtmmVcDeregister interfaces
- *          from within the supplied callback function.  */
-PUBLIC IX_STATUS ixAtmmVcChangeCallbackRegister (IxAtmmVcChangeCallback callback);
-
-
-/**    
- * @ingroup IxAtmm
- * 
- * @fn ixAtmmVcChangeCallbackDeregister (IxAtmmVcChangeCallback callback)
- *
- * @brief This interface is invoked to deregister a previously supplied
- *         callback function.
- *
- * @param callback @ref IxAtmmVcChangeCallback [in] - Callback which complies
- *          with the @ref IxAtmmVcChangeCallback definition.  This
- *          function will removed from the table of callbacks.
- *
- * @return @li IX_SUCCESS : The specified callback has been deregistered
- *      successfully from IxAtmm.
- * @return @li IX_FAIL : Either the supplied callback is invalid, or
- *      is not currently registered with IxAtmm.
- */
-PUBLIC IX_STATUS
-ixAtmmVcChangeCallbackDeregister (IxAtmmVcChangeCallback callback);
-
-/**    
- * @ingroup IxAtmm
- * 
- * @fn ixAtmmUtopiaStatusShow (void)
- * 
- *  @brief Display utopia status counters
- *
- * @param "none"
- *
- * @return @li IX_SUCCESS : Show function was successful
- * @return @li IX_FAIL : Internal failure
- */
-PUBLIC IX_STATUS
-ixAtmmUtopiaStatusShow (void);
-
-/**     
- * @ingroup IxAtmm
- * 
- * @fn ixAtmmUtopiaCfgShow (void)
- *
- * @brief Display utopia information(config registers and status registers)
- *
- * @param "none"
- *
- * @return @li IX_SUCCESS : Show function was successful
- * @return @li IX_FAIL : Internal failure
- */
-PUBLIC IX_STATUS
-ixAtmmUtopiaCfgShow (void);
-
-#endif
-/* IXATMM_H */
-
-/** @} */
diff --git a/arch/arm/cpu/ixp/npe/include/IxDmaAcc.h b/arch/arm/cpu/ixp/npe/include/IxDmaAcc.h
deleted file mode 100644
index 45c7527..0000000
--- a/arch/arm/cpu/ixp/npe/include/IxDmaAcc.h
+++ /dev/null
@@ -1,260 +0,0 @@
-/**
- * @file IxDmaAcc.h
- *
- * @date	15 October 2002 
- *
- * @brief   API of the IXP400 DMA Access Driver Component (IxDma)
- *
- *
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- * 
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- * 
- * @par
- * -- End of Copyright Notice --
- */
-
-/*---------------------------------------------------------------------
-   Doxygen group definitions
-  ---------------------------------------------------------------------*/
-
-#ifndef IXDMAACC_H
-#define IXDMAACC_H
-
-#include "IxOsal.h"
-#include "IxNpeDl.h"
-/**
- * @defgroup IxDmaTypes IXP400 DMA Types (IxDmaTypes)
- * @brief The common set of types used in the DMA component
- * @{
- */
-
-/** 
- * @ingroup IxDmaTypes
- * @enum IxDmaReturnStatus
- * @brief Dma return status definitions
- */
-typedef enum
-{
-    IX_DMA_SUCCESS = IX_SUCCESS,  /**< DMA Transfer Success */
-    IX_DMA_FAIL = IX_FAIL,        /**< DMA Transfer Fail */
-    IX_DMA_INVALID_TRANSFER_WIDTH, /**< Invalid transfer width */
-    IX_DMA_INVALID_TRANSFER_LENGTH, /**< Invalid transfer length */
-    IX_DMA_INVALID_TRANSFER_MODE, /**< Invalid transfer mode */
-    IX_DMA_INVALID_ADDRESS_MODE, /**< Invalid address mode */
-    IX_DMA_REQUEST_FIFO_FULL  /**< DMA request queue is full */
-} IxDmaReturnStatus;
-
-/** 
- * @ingroup IxDmaTypes
- * @enum IxDmaTransferMode
- * @brief Dma transfer mode definitions
- * @note Copy and byte swap, and copy and reverse modes only support multiples of word data length.
- */
-typedef enum
-{
-    IX_DMA_COPY_CLEAR = 0,      /**< copy and clear source*/
-    IX_DMA_COPY,                /**< copy */
-    IX_DMA_COPY_BYTE_SWAP,      /**< copy and byte swap (endian) */
-    IX_DMA_COPY_REVERSE,        /**< copy and reverse */
-    IX_DMA_TRANSFER_MODE_INVALID /**< Invalid transfer mode */
-} IxDmaTransferMode;
-
-/** 
- * @ingroup IxDmaTypes
- * @enum IxDmaAddressingMode
- * @brief Dma addressing mode definitions
- * @note Fixed source address to fixed destination address addressing mode is not supported.
- */
-typedef enum
-{
-    IX_DMA_INC_SRC_INC_DST = 0, /**< Incremental source address to incremental destination address */
-    IX_DMA_INC_SRC_FIX_DST,     /**< Incremental source address to incremental destination address */
-    IX_DMA_FIX_SRC_INC_DST,     /**< Incremental source address to incremental destination address */
-    IX_DMA_FIX_SRC_FIX_DST,     /**< Incremental source address to incremental destination address */
-    IX_DMA_ADDRESSING_MODE_INVALID /**< Invalid Addressing Mode */
-} IxDmaAddressingMode;
-
-/** 
- * @ingroup IxDmaTypes
- * @enum IxDmaTransferWidth
- * @brief Dma transfer width definitions
- * @Note Fixed addresses (either source or destination) do not support burst transfer width.
- */
-typedef enum
-{
-    IX_DMA_32_SRC_32_DST = 0,  /**< 32-bit src to 32-bit dst */
-    IX_DMA_32_SRC_16_DST,      /**< 32-bit src to 16-bit dst */
-    IX_DMA_32_SRC_8_DST,       /**< 32-bit src to 8-bit dst */
-    IX_DMA_16_SRC_32_DST,      /**< 16-bit src to 32-bit dst */
-    IX_DMA_16_SRC_16_DST,      /**< 16-bit src to 16-bit dst */
-    IX_DMA_16_SRC_8_DST,       /**< 16-bit src to 8-bit dst */
-    IX_DMA_8_SRC_32_DST,       /**< 8-bit src to 32-bit dst */
-    IX_DMA_8_SRC_16_DST,       /**< 8-bit src to 16-bit dst */
-    IX_DMA_8_SRC_8_DST,        /**< 8-bit src to 8-bit dst */
-    IX_DMA_8_SRC_BURST_DST,    /**< 8-bit src to burst dst - Not supported for fixed destination address */
-    IX_DMA_16_SRC_BURST_DST,   /**< 16-bit src to burst dst - Not supported for fixed destination address */
-    IX_DMA_32_SRC_BURST_DST,   /**< 32-bit src to burst dst - Not supported for fixed destination address */
-    IX_DMA_BURST_SRC_8_DST,    /**< burst src to 8-bit dst  - Not supported for fixed source address */
-    IX_DMA_BURST_SRC_16_DST,   /**< burst src to 16-bit dst - Not supported for fixed source address */
-    IX_DMA_BURST_SRC_32_DST,   /**< burst src to 32-bit dst - Not supported for fixed source address*/
-    IX_DMA_BURST_SRC_BURST_DST, /**< burst src to burst dst  - Not supported for fixed source and destination address
-*/
-    IX_DMA_TRANSFER_WIDTH_INVALID /**< Invalid transfer width */
-} IxDmaTransferWidth;
-
-/** 
- * @ingroup IxDmaTypes
- * @enum IxDmaNpeId
- * @brief NpeId numbers to identify NPE A, B or C
- */
-typedef enum
-{
-    IX_DMA_NPEID_NPEA = 0, /**< Identifies NPE A */
-    IX_DMA_NPEID_NPEB,     /**< Identifies NPE B */
-    IX_DMA_NPEID_NPEC,     /**< Identifies NPE C */
-    IX_DMA_NPEID_MAX       /**< Total Number of NPEs */
-} IxDmaNpeId;
-/* @} */
-/**
- * @defgroup IxDmaAcc IXP400 DMA Access Driver (IxDmaAcc) API
- *
- * @brief The public API for the IXP400 IxDmaAcc component
- *
- * @{
- */
-
-/**
- * @ingroup IxDmaAcc
- * @brief DMA Request Id type
- */
-typedef UINT32 IxDmaAccRequestId;
-
-/**
- * @ingroup IxDmaAcc
- * @def IX_DMA_REQUEST_FULL
- * @brief DMA request queue is full
- * This constant is a return value used to tell the user that the IxDmaAcc
- * queue is full.
- *
- */
-#define IX_DMA_REQUEST_FULL 16
-
-/**
- * @ingroup	IxDmaAcc
- * @brief       DMA completion notification
- * This function is called to notify a client that the DMA has been completed
- * @param status @ref IxDmaReturnStatus [out] - reporting to client
- *
- */
-typedef void (*IxDmaAccDmaCompleteCallback) (IxDmaReturnStatus status);
-
-/**
- * @ingroup	IxDmaAcc
- * 
- * @fn ixDmaAccInit(IxNpeDlNpeId npeId)
- * 
- * @brief	Initialise the DMA Access component
- * This function will initialise the DMA Access component internals
- * @param npeId @ref IxNpeDlNpeId [in] - NPE to use for Dma Transfer
- * @return @li IX_SUCCESS succesfully initialised the component
- * @return @li IX_FAIL Initialisation failed for some unspecified
- * internal reason.
- */
-PUBLIC IX_STATUS
-ixDmaAccInit(IxNpeDlNpeId npeId);
-
-/**
- * @ingroup	IxDmaAcc
- * 
- * @fn ixDmaAccDmaTransfer(
-    IxDmaAccDmaCompleteCallback callback,
-    UINT32 SourceAddr,
-    UINT32 DestinationAddr,
-    UINT16 TransferLength,
-    IxDmaTransferMode TransferMode,
-    IxDmaAddressingMode AddressingMode,
-    IxDmaTransferWidth TransferWidth)
- *
- * @brief       Perform DMA transfer
- * This function will perform DMA transfer between devices within the
- * IXP400 memory map.
- * @note The following are restrictions for IxDmaAccDmaTransfer:
- *      @li The function is non re-entrant.
- *      @li The function assumes host devices are operating in big-endian mode.
- *      @li Fixed address does not suport burst transfer width
- *      @li Fixed source address to fixed destinatiom address mode is not suported
- *      @li The incrementing source address for expansion bus will not support a burst transfer width and copy and clear mode
- *
- * @param callback @ref IxDmaAccDmaCompleteCallback [in] - function pointer to be stored and called when the DMA transfer is completed. This cannot be NULL.
- * @param SourceAddr UINT32 [in] -	Starting address of DMA source. Must be a valid IXP400 memory map address.
- * @param DestinationAddr UINT32 [in] - Starting address of DMA destination. Must be a valid IXP400 memory map address.
- * @param TransferLength UINT16 [in] - The size of DMA data transfer. The range must be from 1-64Kbyte
- * @param TransferMode @ref IxDmaTransferMode [in] - The DMA transfer mode
- * @param AddressingMode @ref IxDmaAddressingMode [in] - The DMA addressing mode
- * @param TransferWidth	@ref IxDmaTransferWidth [in] - The DMA transfer width
- *
- * @return @li IX_DMA_SUCCESS	Notification that the DMA request is succesful
- * @return @li IX_DMA_FAIL	IxDmaAcc not yet initialised or some internal error has occured
- * @return @li IX_DMA_INVALID_TRANSFER_WIDTH Transfer width is nit valid
- * @return @li IX_DMA_INVALID_TRANSFER_LENGTH Transfer length outside of valid range
- * @return @li IX_DMA_INVALID_TRANSFER_MODE Transfer Mode not valid
- * @return @li IX_DMA_REQUEST_FIFO_FULL IxDmaAcc request queue is full
- */
-PUBLIC IxDmaReturnStatus
-ixDmaAccDmaTransfer(
-    IxDmaAccDmaCompleteCallback callback,
-    UINT32 SourceAddr,
-    UINT32 DestinationAddr,
-    UINT16 TransferLength,
-    IxDmaTransferMode TransferMode,
-    IxDmaAddressingMode AddressingMode,
-    IxDmaTransferWidth TransferWidth);
-/**
- * @ingroup IxDmaAcc
- *
- * @fn ixDmaAccShow(void)
- *
- * @brief Display some component information for debug purposes
- * Show some internal operation information relating to the DMA service.
- * At a minimum the following will show.
- * - the number of the DMA pend (in queue)
- * @param None
- * @return @li None
- */
-PUBLIC IX_STATUS
-ixDmaAccShow(void);
-
-#endif /* IXDMAACC_H */
-
diff --git a/arch/arm/cpu/ixp/npe/include/IxEthAcc.h b/arch/arm/cpu/ixp/npe/include/IxEthAcc.h
deleted file mode 100644
index ff706c4..0000000
--- a/arch/arm/cpu/ixp/npe/include/IxEthAcc.h
+++ /dev/null
@@ -1,2512 +0,0 @@
-/** @file    IxEthAcc.h
- *
- * @brief this file contains the public API of @ref IxEthAcc component
- *
- * Design notes:
- * The IX_OSAL_MBUF address is to be specified on bits [31-5] and must 
- * be cache aligned (bits[4-0] cleared)
- *
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- * 
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- * 
- * @par
- * -- End of Copyright Notice --
- *
- */
-
-#ifndef IxEthAcc_H
-#define IxEthAcc_H
-
-#include <IxOsBuffMgt.h>
-#include <IxTypes.h>
-
-/**
- * @defgroup IxEthAcc IXP400 Ethernet Access (IxEthAcc) API
- *
- * @brief ethAcc is a library that does provides access to the internal IXP400 10/100Bt Ethernet MACs.
- *
- *@{
- */
-
-/**
- * @ingroup IxEthAcc
- * @brief Definition of the Ethernet Access status
- */
-typedef enum /* IxEthAccStatus */
-{
-    IX_ETH_ACC_SUCCESS = IX_SUCCESS, /**< return success*/
-    IX_ETH_ACC_FAIL = IX_FAIL, /**< return fail*/
-    IX_ETH_ACC_INVALID_PORT, /**< return invalid port*/
-    IX_ETH_ACC_PORT_UNINITIALIZED, /**< return uninitialized*/
-    IX_ETH_ACC_MAC_UNINITIALIZED, /**< return MAC uninitialized*/
-    IX_ETH_ACC_INVALID_ARG, /**< return invalid arg*/
-    IX_ETH_TX_Q_FULL, /**< return tx queue is full*/
-    IX_ETH_ACC_NO_SUCH_ADDR /**< return no such address*/
-} IxEthAccStatus;
-
-/**
- * @ingroup IxEthAcc
- * @enum IxEthAccPortId
- * @brief Definition of the IXP400 Mac Ethernet device.
- */
-typedef enum  
-{
-	IX_ETH_PORT_1 = 0, /**< Ethernet Port 1 */
-	IX_ETH_PORT_2 = 1  /**< Ethernet port 2 */
-	,IX_ETH_PORT_3 = 2 /**< Ethernet port 3 */
-} IxEthAccPortId;
-
-/**
- * @ingroup IxEthAcc
- *
- * @def IX_ETH_ACC_NUMBER_OF_PORTS
- *
- * @brief  Definition of the number of ports
- *
- */
-#ifdef __ixp46X
-#define IX_ETH_ACC_NUMBER_OF_PORTS (3)
-#else
-#define IX_ETH_ACC_NUMBER_OF_PORTS (2)
-#endif
-
-/**
- * @ingroup IxEthAcc
- *
- * @def IX_IEEE803_MAC_ADDRESS_SIZE
- *
- * @brief  Definition of the size of the MAC address
- *
- */
-#define IX_IEEE803_MAC_ADDRESS_SIZE (6)
-
-
-/**
- *
- * @brief Definition of the IEEE 802.3 Ethernet MAC address structure.
- *
- * The data should be packed with bytes xx:xx:xx:xx:xx:xx 
- * @note
- * The data must be packed in network byte order.
- */
-typedef struct  
-{
-    UINT8 macAddress[IX_IEEE803_MAC_ADDRESS_SIZE]; /**< MAC address */
-} IxEthAccMacAddr;
-
-/**
- * @ingroup IxEthAcc
- * @def IX_ETH_ACC_NUM_TX_PRIORITIES
- * @brief Definition of the number of transmit priorities
- * 
- */
-#define IX_ETH_ACC_NUM_TX_PRIORITIES (8)
-
-/**
- * @ingroup IxEthAcc
- * @enum IxEthAccTxPriority
- * @brief Definition of the relative priority used to transmit a frame
- * 
- */
-typedef enum  
-{
-	IX_ETH_ACC_TX_PRIORITY_0 = 0, /**<Lowest Priority submission */
-	IX_ETH_ACC_TX_PRIORITY_1 = 1, /**<submission prority of 1 (0 is lowest)*/
-	IX_ETH_ACC_TX_PRIORITY_2 = 2, /**<submission prority of 2 (0 is lowest)*/
-	IX_ETH_ACC_TX_PRIORITY_3 = 3, /**<submission prority of 3 (0 is lowest)*/
-	IX_ETH_ACC_TX_PRIORITY_4 = 4, /**<submission prority of 4 (0 is lowest)*/
-	IX_ETH_ACC_TX_PRIORITY_5 = 5, /**<submission prority of 5 (0 is lowest)*/
-	IX_ETH_ACC_TX_PRIORITY_6 = 6, /**<submission prority of 6 (0 is lowest)*/
-	IX_ETH_ACC_TX_PRIORITY_7 = 7, /**<Highest priority submission */
-
-	IX_ETH_ACC_TX_DEFAULT_PRIORITY = IX_ETH_ACC_TX_PRIORITY_0 /**< By default send all 
-								 packets with lowest priority */
-} IxEthAccTxPriority;
-
-/**
- * @ingroup IxEthAcc
- * @enum IxEthAccRxFrameType
- * @brief Identify the type of a frame.
- * 
- * @sa IX_ETHACC_NE_FLAGS
- * @sa IX_ETHACC_NE_LINKMASK
- */
-typedef enum  
-{
-	IX_ETHACC_RX_LLCTYPE = 0x00, /**< 802.3 - 8802, with LLC/SNAP */
-	IX_ETHACC_RX_ETHTYPE = 0x10, /**< 802.3 (Ethernet) without LLC/SNAP */
-	IX_ETHACC_RX_STATYPE = 0x20, /**< 802.11, AP <=> STA */
-	IX_ETHACC_RX_APTYPE  = 0x30  /**< 802.11, AP <=> AP */
-} IxEthAccRxFrameType;
-
-/**
- * @ingroup IxEthAcc
- * @enum IxEthAccDuplexMode
- * @brief Definition to provision the duplex mode of the MAC. 
- * 
- */
-typedef enum
-{
-    IX_ETH_ACC_FULL_DUPLEX, /**< Full duplex operation of the MAC */
-    IX_ETH_ACC_HALF_DUPLEX  /**< Half duplex operation of the MAC */
-} IxEthAccDuplexMode;
-
-
-/**
- * @ingroup IxEthAcc
- * @struct IxEthAccNe
- * @brief Definition of service-specific informations.
- * 
- * This structure defines the Ethernet service-specific informations
- * and enable QoS and VLAN features.
- */
-typedef struct
-{
-    UINT32 ixReserved_next;    /**< reserved for chaining */
-    UINT32 ixReserved_lengths; /**< reserved for buffer lengths */
-    UINT32 ixReserved_data;    /**< reserved for buffer pointer */
-    UINT8  ixDestinationPortId; /**< Destination portId for this packet, if known by NPE */
-    UINT8  ixSourcePortId; /**< Source portId for this packet */
-    UINT16 ixFlags;        /**< BitField of option for this frame */
-    UINT8  ixQoS;          /**< QoS class of the frame */
-    UINT8  ixReserved;     /**< reserved */
-    UINT16 ixVlanTCI;      /**< Vlan TCI */
-    UINT8  ixDestMac[IX_IEEE803_MAC_ADDRESS_SIZE]; /**< Destination MAC address */
-    UINT8  ixSourceMac[IX_IEEE803_MAC_ADDRESS_SIZE]; /**< Source MAC address */
-} IxEthAccNe;
-
-/**
- * @ingroup IxEthAcc
- *
- * @def IX_ETHACC_NE_PORT_UNKNOWN
- *
- * @brief  Contents of the field @a IX_ETHACC_NE_DESTPORTID when no
- * destination port can be found by the NPE for this frame.
- *
- */
-#define IX_ETHACC_NE_PORT_UNKNOWN   (0xff)
-
-/**
- * @ingroup IxEthAcc
- *
- * @def IX_ETHACC_NE_DESTMAC
- *
- * @brief The location of the destination MAC address in the Mbuf header.
- *
- */
-#define IX_ETHACC_NE_DESTMAC(mBufPtr) ((IxEthAccNe *)&((mBufPtr)->ix_ne))->ixDestMac
-
-/**
- * @ingroup IxEthAcc
- *
- * @def IX_ETHACC_NE_SOURCEMAC
- *
- * @brief The location of the source MAC address in the Mbuf header.
- *
- */
-#define IX_ETHACC_NE_SOURCEMAC(mBufPtr) ((IxEthAccNe *)&((mBufPtr)->ix_ne))->ixSourceMac
-
-/**
- * @ingroup IxEthAcc
- *
- * @def IX_ETHACC_NE_VLANTCI
- *
- * @brief The VLAN Tag Control Information associated with this frame
- * 
- * The VLAN Tag Control Information associated with this frame. On Rx
- * path, this field is extracted from the packet header.
- * On Tx path, the value of this field is inserted in the frame when
- * the port is configured to insert or replace vlan tags in the 
- * egress frames.
- *
- * @sa IX_ETHACC_NE_FLAGS
- */
-#define IX_ETHACC_NE_VLANTCI(mBufPtr) ((IxEthAccNe *)&((mBufPtr)->ix_ne))->ixVlanTCI
-
-/**
- * @ingroup IxEthAcc
- *
- * @def IX_ETHACC_NE_SOURCEPORTID
- *
- * @brief The port where this frame came from.
- *
- * The port where this frame came from. This field is set on receive
- * with the port information. This field is ignored on Transmit path.
- */
-#define IX_ETHACC_NE_SOURCEPORTID(mBufPtr) ((IxEthAccNe *)&((mBufPtr)->ix_ne))->ixSourcePortId
-
-/**
- * @ingroup IxEthAcc
- *
- * @def IX_ETHACC_NE_DESTPORTID
- *
- * @brief The destination port where this frame should be sent.
- *
- * The destination port where this frame should be sent.
- *
- * @li In the transmit direction, this field contains the destination port
- * and is ignored unless @a IX_ETHACC_NE_FLAG_DST is set.
- * 
- * @li In the receive direction, this field contains the port where the
- * destination MAC addresses has been learned. If the destination
- * MAC address is unknown, then this value is set to the reserved value
- * @a IX_ETHACC_NE_PORT_UNKNOWN
- *
- */
-#define IX_ETHACC_NE_DESTPORTID(mBufPtr) ((IxEthAccNe *)&((mBufPtr)->ix_ne))->ixDestinationPortId
-
-/**
- * @ingroup IxEthAcc
- *
- * @def IX_ETHACC_NE_QOS
- *
- * @brief QualityOfService class (QoS) for this received frame.
- *
- */
-#define IX_ETHACC_NE_QOS(mBufPtr) ((IxEthAccNe *)&((mBufPtr)->ix_ne))->ixQoS
-
-/**
- * @ingroup IxEthAcc
- *
- * @def IX_ETHACC_NE_FLAGS
- *
- * @brief Bit Mask of the different flags associated with a frame
- * 
- * The flags are the bit-oring combination 
- * of the following different fields :
- *
- *      @li IP flag (Rx @a IX_ETHACC_NE_IPMASK)
- *      @li Spanning Tree flag (Rx @a IX_ETHACC_NE_STMASK)
- *      @li Link layer type (Rx and Tx @a IX_ETHACC_NE_LINKMASK)
- *      @li VLAN Tagged Frame (Rx @a IX_ETHACC_NE_VLANMASK)
- *      @li New source MAC address (Rx @a IX_ETHACC_NE_NEWSRCMASK)
- *      @li Multicast flag (Rx @a IX_ETHACC_NE_MCASTMASK)
- *      @li Broadcast flag (Rx @a IX_ETHACC_NE_BCASTMASK)
- *      @li Destination port flag (Tx @a IX_ETHACC_NE_PORTMASK)
- *      @li Tag/Untag Tx frame (Tx @a IX_ETHACC_NE_TAGMODEMASK)
- *      @li Overwrite destination port (Tx @a IX_ETHACC_NE_PORTOVERMASK)
- *      @li Filtered frame (Rx @a IX_ETHACC_NE_STMASK)
- *      @li VLAN Enabled (Rx and Tx @a IX_ETHACC_NE_VLANENABLEMASK)
- */
-#define IX_ETHACC_NE_FLAGS(mBufPtr) ((IxEthAccNe *)&((mBufPtr)->ix_ne))->ixFlags
-
-/**
- * @ingroup IxEthAcc
- *
- * @def IX_ETHACC_NE_BCASTMASK
- *
- * @brief This mask defines if a received frame is a broadcast frame.
- *
- * This mask defines if a received frame is a broadcast frame.
- * The BCAST flag is set when the destination MAC address of 
- * a frame is broadcast.
- *
- * @sa IX_ETHACC_NE_FLAGS 
- *
- */
-#define IX_ETHACC_NE_BCASTMASK      (0x1)
-
-/**
- * @ingroup IxEthAcc
- *
- * @def IX_ETHACC_NE_MCASTMASK
- *
- * @brief This mask defines if a received frame is a multicast frame.
- *
- * This mask defines if a received frame is a multicast frame.
- * The MCAST flag is set when the destination MAC address of 
- * a frame is multicast.
- *
- * @sa IX_ETHACC_NE_FLAGS 
- *
- */
-#define IX_ETHACC_NE_MCASTMASK      (0x1 << 1)
-
-/**
- * @ingroup IxEthAcc
- *
- * @def IX_ETHACC_NE_IPMASK
- *
- * @brief This mask defines if a received frame is a IP frame.
- *
- * This mask applies to @a IX_ETHACC_NE_FLAGS and defines if a received 
- * frame is a IP frame. The IP flag is set on Rx direction, depending on 
- * the frame contents. The flag is set when the length/type field of a 
- * received frame is 0x8000.
- *
- * @sa IX_ETHACC_NE_FLAGS
- *
- */
-#define IX_ETHACC_NE_IPMASK         (0x1 << 2)
-
-/**
- * @ingroup IxEthAcc
- *
- * @def IX_ETHACC_NE_VLANMASK
- *
- * @brief This mask defines if a received frame is VLAN tagged.
- *
- * This mask defines if a received frame is VLAN tagged.
- * When set, the Rx frame is VLAN-tagged and the tag value 
- * is available thru @a IX_ETHACC_NE_VLANID.
- * Note that when sending frames which are already tagged
- * this flag should be set, to avoid inserting another VLAN tag.
- *
- * @sa IX_ETHACC_NE_FLAGS 
- * @sa IX_ETHACC_NE_VLANID
- *
- */
-#define IX_ETHACC_NE_VLANMASK       (0x1 << 3)
-
-/**
- * @ingroup IxEthAcc
- *
- * @def IX_ETHACC_NE_LINKMASK
- *
- * @brief This mask is the link layer protocol indicator
- *
- * This mask applies to @a IX_ETHACC_NE_FLAGS.
- * It reflects the state of a frame as it exits an NPE on the Rx path
- * or enters an NPE on the Tx path. Its values are as follows:
- *      @li 0x00 - IEEE802.3 - 8802 (Rx) / IEEE802.3 - 8802 (Tx)
- *      @li 0x01 - IEEE802.3 - Ethernet (Rx) / IEEE802.3 - Ethernet (Tx)
- *      @li 0x02 - IEEE802.11 AP -> STA (Rx) / IEEE802.11 STA -> AP (Tx)
- *      @li 0x03 - IEEE802.11 AP -> AP (Rx) / IEEE802.11 AP->AP (Tx)
- *
- * @sa IX_ETHACC_NE_FLAGS
- *
- */
-#define IX_ETHACC_NE_LINKMASK       (0x3 << 4)
-
-/**
- * @ingroup IxEthAcc
- *
- * @def IX_ETHACC_NE_STMASK
- *
- * @brief This mask defines if a received frame is a Spanning Tree frame.
- *
- * This mask applies to @a IX_ETHACC_NE_FLAGS.
- * On rx direction, it defines if a received if frame is a Spanning Tree frame.
- * Setting this fkag on transmit direction overrides the port settings 
- * regarding the VLAN options and 
- *
- * @sa IX_ETHACC_NE_FLAGS
- *
- */
-#define IX_ETHACC_NE_STMASK         (0x1 << 6)
-
-/**
- * @ingroup IxEthAcc
- *
- * @def IX_ETHACC_NE_FILTERMASK
- *
- * @brief This bit indicates whether a frame has been filtered by the Rx service.
- *
- * This mask applies to @a IX_ETHACC_NE_FLAGS.
- * Certain frames, which should normally be fully filtered by the NPE to due
- * the destination MAC address being on the same segment as the Rx port are
- * still forwarded to the XScale (although the payload is invalid) in order
- * to learn the MAC address of the transmitting station, if this is unknown.
- * Normally EthAcc will filter and recycle these framess internally and no
- * frames with the FILTER bit set will be received by the client.
- *
- * @sa IX_ETHACC_NE_FLAGS
- *
- */
-#define IX_ETHACC_NE_FILTERMASK     (0x1 << 7)
-
-/**
- * @ingroup IxEthAcc
- *
- * @def IX_ETHACC_NE_PORTMASK
- *
- * @brief This mask defines the rule to transmit a frame
- *
- * This mask defines the rule to transmit a frame. When set, a frame
- * is transmitted to the destination port as set by the macro
- * @a IX_ETHACC_NE_DESTPORTID. If not set, the destination port 
- * is searched using the destination MAC address.
- *
- * @note This flag is meaningful only for multiport Network Engines.
- * 
- * @sa IX_ETHACC_NE_FLAGS 
- * @sa IX_ETHACC_NE_DESTPORTID
- *
- */
-#define IX_ETHACC_NE_PORTOVERMASK   (0x1 << 8)
-
-/**
- * @ingroup IxEthAcc
- *
- * @def IX_ETHACC_NE_TAGMODEMASK
- *
- * @brief This mask defines the tagging rules to apply to a transmit frame.
- *
- * This mask defines the tagging rules to apply to a transmit frame
- * regardless of the default setting for a port. When used together 
- * with @a IX_ETHACC_NE_TAGOVERMASK and when set, the 
- * frame will be tagged prior to transmission. When not set,
- * the frame will be untagged prior to transmission. This is accomplished
- * irrespective of the Egress tagging rules, constituting a per-frame override.
- *
- * @sa IX_ETHACC_NE_FLAGS
- * @sa IX_ETHACC_NE_TAGOVERMASK 
- *
- */
-#define IX_ETHACC_NE_TAGMODEMASK    (0x1 << 9)
-
-/**
- * @ingroup IxEthAcc
- *
- * @def IX_ETHACC_NE_TAGOVERMASK
- *
- * @brief This mask defines the rule to transmit a frame
- *
- * This mask defines the rule to transmit a frame. When set, the
- * default transmit rules of a port are overriden.
- * When not set, the default rules as set by @ref IxEthDB should apply.
- *
- * @sa IX_ETHACC_NE_FLAGS
- * @sa IX_ETHACC_NE_TAGMODEMASK
- *
- */
-#define IX_ETHACC_NE_TAGOVERMASK    (0x1 << 10)
-
-/**
- * @ingroup IxEthAcc
- *
- * @def IX_ETHACC_NE_VLANENABLEMASK
- *
- * @brief This mask defines if a frame is a VLAN frame or not
- *
- * When set, frames undergo normal VLAN processing on the Tx path
- * (membership filtering, tagging, tag removal etc). If this flag is
- * not set, the frame is considered to be a regular non-VLAN frame
- * and no VLAN processing will be performed.
- *
- * Note that VLAN-enabled NPE images will always set this flag in all
- * Rx frames, and images which are not VLAN enabled will clear this
- * flag for all received frames.
- *
- * @sa IX_ETHACC_NE_FLAGS
- *
- */
-#define IX_ETHACC_NE_VLANENABLEMASK (0x1 << 14)
-
-/**
- * @ingroup IxEthAcc
- *
- * @def IX_ETHACC_NE_NEWSRCMASK
- *
- * @brief This mask defines if a received frame has been learned.
- *
- * This mask defines if the source MAC address of a frame is 
- * already known. If the bit is set, the source MAC address was
- * unknown to the NPE at the time the frame was received.
- *
- * @sa IX_ETHACC_NE_FLAGS 
- *
- */
-#define IX_ETHACC_NE_NEWSRCMASK     (0x1 << 15)
-
-/**
- * @ingroup IxEthAcc
- *
- * @brief This defines the recommanded minimum size of MBUF's submitted
- * to the frame receive service.
- *
- */
-#define IX_ETHACC_RX_MBUF_MIN_SIZE (2048)
-
-/**
- * @ingroup IxEthAcc
- *
- * @brief This defines the highest MII address of any attached PHYs 
- * 
- * The maximum number for PHY address is 31, add on for range checking.
- *
- */
-#define IXP425_ETH_ACC_MII_MAX_ADDR   32
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn ixEthAccInit(void)
- * 
- * @brief Initializes the IXP400 Ethernet Access Service.
- * 
- * @li Reentrant    - no
- * @li ISR Callable - no
- * 
- * This should be called once per module initialization.
- * @pre
- *   The NPE must first be downloaded with the required microcode which supports all
- *   required features.
- *
- * @return IxEthAccStatus
- * @li @a IX_ETH_ACC_SUCCESS
- * @li @a IX_ETH_ACC_FAIL	:  Service has failed to initialize.
- *
- * <hr>
- */
-PUBLIC IxEthAccStatus ixEthAccInit(void);
-
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn ixEthAccUnload(void)
- * 
- * @brief Unload the Ethernet Access Service.
- * 
- * @li Reentrant    - no
- * @li ISR Callable - no
- *
- * @return void 
- *
- * <hr>
- */
-PUBLIC void ixEthAccUnload(void);
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn ixEthAccPortInit( IxEthAccPortId portId)
- *
- * @brief Initializes an NPE/Ethernet MAC Port.
- *
- * The NPE/Ethernet port initialisation includes the following steps
- * @li Initialize the NPE/Ethernet MAC hardware.
- * @li Verify NPE downloaded and operational.
- * @li The NPE shall be available for usage once this API returns.
- * @li Verify that the Ethernet port is present before initializing
- *
- * @li Reentrant    - no
- * @li ISR Callable - no
- *
- * This should be called once per mac device.
- * The NPE/MAC shall be in disabled state after init.
- *
- * @pre
- *   The component must be initialized via @a ixEthAccInit
- *   The NPE must first be downloaded with the required microcode which supports all
- *   required features.
- *
- * Dependant on Services: (Must be initialized before using this service may be initialized)
- *	ixNPEmh - NPE Message handling service.
- *	ixQmgr	- Queue Manager component.
- *
- * @param portId  @ref IxEthAccPortId [in]
- *
- * @return IxEthAccStatus
- * @li @a IX_ETH_ACC_SUCCESS: if the ethernet port is not present, a warning is issued.
- * @li @a IX_ETH_ACC_FAIL : The NPE processor has failed to initialize.
- * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid.
- *
- * <hr>
- */
-PUBLIC IxEthAccStatus ixEthAccPortInit(IxEthAccPortId portId);
-
-
-/*************************************************************************
-
- #####     ##     #####    ##            #####     ##     #####  #    #
- #    #   #  #      #     #  #           #    #   #  #      #    #    #
- #    #  #    #     #    #    #          #    #  #    #     #    ######
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- #    #  #    #     #    #    #          #       #    #     #    #    #
- #####   #    #     #    #    #          #       #    #     #    #    #
-
-*************************************************************************/
-
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn ixEthAccPortTxFrameSubmit( 
-    IxEthAccPortId portId,
-    IX_OSAL_MBUF *buffer, 
-    IxEthAccTxPriority priority)
- * 
- * @brief This function shall be used to submit MBUFs buffers for transmission on a particular MAC device. 
- *
- * When the frame is transmitted, the buffer shall be returned thru the 
- * callback @a IxEthAccPortTxDoneCallback.
- *
- * In case of over-submitting, the order of the frames on the 
- * network may be modified.
- *
- * Buffers shall be not queued for transmission if the port is disabled.
- * The port can be enabled using @a ixEthAccPortEnable
- *
- * 
- * @li Reentrant    - yes
- * @li ISR Callable - yes
- *
- *
- * @pre 
- *  @a ixEthAccPortTxDoneCallbackRegister must be called to register a function to allow this service to
- *   return the buffer to the calling service. 
- * 
- * @note 
- *  If the buffer submit fails for any reason the user has retained ownership of the buffer.
- *
- * @param portId @ref IxEthAccPortId [in] - MAC port ID to transmit Ethernet frame on.
- * @param buffer @ref IX_OSAL_MBUF [in] - pointer to an MBUF formatted buffer. Chained buffers are supported for transmission.
- *             Chained packets are not supported and the field IX_OSAL_MBUF_NEXT_PKT_IN_CHAIN_PTR is ignored. 
- * @param priority @ref IxEthAccTxPriority [in]
- *
- * @return IxEthAccStatus
- * @li @a IX_ETH_ACC_SUCCESS
- * @li @a IX_ETH_ACC_FAIL  : Failed to queue frame for transmission. 
- * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid.
- * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized
- *
- * <hr>
- */
-
-PUBLIC IxEthAccStatus ixEthAccPortTxFrameSubmit( 
-    IxEthAccPortId portId,
-    IX_OSAL_MBUF *buffer, 
-    IxEthAccTxPriority priority);
-
-/**
- * @ingroup IxEthAcc
- *
- * @brief Function prototype for Ethernet Tx Buffer Done callback. Registered 
- *  via @a ixEthAccTxBufferDoneCallbackRegister 
- * 
- * This function is called once the previously submitted buffer is no longer required by this service.
- * It may be returned upon successful transmission of the frame or during the shutdown of 
- * the port prior to the transmission of a queued frame.
- * The calling of this registered function is not a guarantee of successful transmission of the buffer.
- *
- *  
- * @li Reentrant    - yes , The user provided function should be reentrant.
- * @li ISR Callable - yes , The user provided function must be callable from an ISR.
- *
- *
- * <b>Calling Context </b>: 
- * @par
- *   This callback is called in the context of the queue manager dispatch loop @a ixQmgrgrDispatcherLoopRun
- *   within the @ref IxQMgrAPI component. The calling context may be from interrupt or high priority thread. 
- *   The decision is system specific.
- *
- * @param callbackTag UINT32 [in] - This tag is that provided when the callback was registered for a particular MAC 
- * via @a ixEthAccPortTxDoneCallbackRegister. It allows the same callback to be used for multiple MACs.
- * @param mbuf @ref IX_OSAL_MBUF [in] - Pointer to the Tx mbuf descriptor. 
- * 
- * @return void
- *
- * @note
- * The field IX_OSAL_MBUF_NEXT_PKT_IN_CHAIN_PTR is modified by the access layer and reset to NULL.
- *
- * <hr>
- */
-typedef void (*IxEthAccPortTxDoneCallback) ( UINT32 callbackTag, IX_OSAL_MBUF *buffer );
-
-
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn ixEthAccPortTxDoneCallbackRegister( IxEthAccPortId portId, 
-					   IxEthAccPortTxDoneCallback txCallbackFn, 
-					   UINT32 callbackTag)
- *
- * @brief Register a callback function to allow 
- * the transmitted buffers to return to the user.
- * 
- * This function registers the transmit buffer done function callback for a particular port.
- *
- * The registered callback function is called once the previously submitted buffer is no longer required by this service.
- * It may be returned upon successful transmission of the frame or  shutdown of port prior to submission.
- * The calling of this registered function is not a guarantee of successful transmission of the buffer.
- *
- * If called several times the latest callback shall be registered for a particular port.
- *
- * @li Reentrant    - yes
- * @li ISR Callable - yes
- *
- * @pre
- *	The port must be initialized via @a ixEthAccPortInit
- *
- *
- * @param portId @ref IxEthAccPortId [in] - Register callback for a particular MAC device.
- * @param txCallbackFn @ref IxEthAccPortTxDoneCallback [in] - Function to be called to return transmit buffers to the user.
- * @param callbackTag UINT32 [in] -  This tag shall be provided to the callback function.
- *
- * @return IxEthAccStatus
- * @li @a IX_ETH_ACC_SUCCESS 
- * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid.
- * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized
- * @li @a IX_ETH_ACC_INVALID_ARG : An argument other than portId is invalid.
- *
- * <hr>
- */
-PUBLIC IxEthAccStatus
-ixEthAccPortTxDoneCallbackRegister(IxEthAccPortId portId,
-								   IxEthAccPortTxDoneCallback txCallbackFn,
-								   UINT32 callbackTag);
-
-
-
-/**
- * @ingroup IxEthAcc
- *
- * @brief Function prototype for Ethernet Frame Rx callback. Registered via @a ixEthAccPortRxCallbackRegister 
- * 
- * It is the responsibility of the user function to free any MBUF's which it receives.
- *  
- * @li Reentrant    - yes , The user provided function should be reentrant.
- * @li ISR Callable - yes , The user provided function must be callable from an ISR.
- * @par
- *
- * This function dispatches frames to the user level
- * via the provided function. The invocation shall be made for each
- * frame dequeued from the Ethernet QM queue. The user is required to free any MBUF's 
- * supplied via this callback. In addition the registered callback must free up MBUF's
- * from the receive free queue when the port is disabled 
- * 
- * If called several times the latest callback shall be registered for a particular port.
- *
- * <b>Calling Context </b>: 
- * @par
- *   This callback is called in the context of the queue manager dispatch loop @a ixQmgrgrDispatcherLoopRun
- *   within the @ref IxQMgrAPI component. The calling context may be from interrupt or high priority thread. 
- *   The decision is system specific.
- *
- *
- * @param callbackTag UINT32 [in] - This tag is that provided when the callback was registered for a particular MAC 
- * via @a ixEthAccPortRxCallbackRegister. It allows the same callback to be used for multiple MACs.
- * @param mbuf @ref IX_OSAL_MBUF [in] - Pointer to the Rx mbuf header. Mbufs may be chained if 
- *               the frame length is greater than the supplied mbuf length.
- * @param reserved [in] - deprecated parameter The information is passed 
- *      thru the IxEthAccNe header destination port ID field 
- *      (@sa IX_ETHACC_NE_DESTPORTID). For backward 
- *      compatibility,the value is equal to IX_ETH_DB_UNKNOWN_PORT (0xff). 
- * 
- * @return void
- *
- * @note
- * Buffers may not be filled up to the length supplied in 
- * @a ixEthAccPortRxFreeReplenish(). The firmware fills
- * them to the previous 64 bytes boundary. The user has to be aware 
- * that the length of the received mbufs may be smaller than the length
- * of the supplied mbufs. 
- * The mbuf header contains the following modified field
- * @li @a IX_OSAL_MBUF_PKT_LEN is set in the header of the first mbuf and indicates
- *  the total frame size
- * @li @a IX_OSAL_MBUF_MLEN is set each mbuf header and indicates the payload length
- * @li @a IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR contains a pointer to the next 
- *     mbuf, or NULL at the end of a chain.
- * @li @a IX_OSAL_MBUF_NEXT_PKT_IN_CHAIN_PTR is modified. Its value is reset to NULL
- * @li @a IX_OSAL_MBUF_FLAGS contains the bit 4 set for a broadcast packet and the bit 5
- *     set for a multicast packet. Other bits are unmodified.
- *
- * <hr>
- */
-typedef void (*IxEthAccPortRxCallback) (UINT32 callbackTag, IX_OSAL_MBUF *buffer, UINT32 reserved);
-
-/**
- * @ingroup IxEthAcc
- *
- * @brief Function prototype for Ethernet Frame Rx callback. Registered via @a ixEthAccPortMultiBufferRxCallbackRegister 
- * 
- * It is the responsibility of the user function to free any MBUF's which it receives.
- *  
- * @li Reentrant    - yes , The user provided function should be reentrant.
- * @li ISR Callable - yes , The user provided function must be callable from an ISR.
- * @par
- *
- * This function dispatches many frames to the user level
- * via the provided function. The invocation shall be made for multiple frames
- * dequeued from the Ethernet QM queue. The user is required to free any MBUF's 
- * supplied via this callback. In addition the registered callback must free up MBUF's
- * from the receive free queue when the port is disabled 
- * 
- * If called several times the latest callback shall be registered for a particular port.
- *
- * <b>Calling Context </b>: 
- * @par
- *   This callback is called in the context of the queue manager dispatch loop @a ixQmgrDispatcherLoopRun
- *   within the @ref IxQMgrAPI component. The calling context may be from interrupt or high priority thread. 
- *   The decision is system specific.
- *
- *
- * @param callbackTag - This tag is that provided when the callback was registered for a particular MAC 
- * via @a ixEthAccPortMultiBufferRxCallbackRegister. It allows the same callback to be used for multiple MACs.
- * @param mbuf - Pointer to an array of Rx mbuf headers. Mbufs 
- *               may be chained if 
- *               the frame length is greater than the supplied mbuf length.
- *               The end of the array contains a zeroed entry (NULL pointer).
- *
- * @return void
- *
- * @note The mbufs passed to this callback have the same structure than the
- *  buffers passed to @a IxEthAccPortRxCallback interfac. 
- *
- * @note The usage of this callback is exclusive with the usage of
- *  @a ixEthAccPortRxCallbackRegister and @a IxEthAccPortRxCallback 
- *
- * @sa ixEthAccPortMultiBufferRxCallbackRegister
- * @sa IxEthAccPortMultiBufferRxCallback
- * @sa ixEthAccPortRxCallbackRegister
- * @sa IxEthAccPortRxCallback
- * <hr>
- */
-
-typedef void (*IxEthAccPortMultiBufferRxCallback) (UINT32 callbackTag, IX_OSAL_MBUF **buffer);
-
-
-
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn ixEthAccPortRxCallbackRegister( IxEthAccPortId portId, IxEthAccPortRxCallback rxCallbackFn, UINT32 callbackTag)
- *
- * @brief Register a callback function to allow 
- * the reception of frames.
- *
- * The registered callback function is called once a frame is received  by this service.
- *
- * If called several times the latest callback shall be registered for a particular port.
- *
- *
- * @li Reentrant    - yes
- * @li ISR Callable - yes
- *
- *
- * @param portId @ref IxEthAccPortId [in] - Register callback for a particular MAC device.
- * @param rxCallbackFn @ref IxEthAccPortRxCallback [in] - Function to be called when Ethernet frames are availble.
- * @param callbackTag UINT32 [in] -  This tag shall be provided to the callback function.
- *
- * @return IxEthAccStatus
- * @li @a IX_ETH_ACC_SUCCESS 
- * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid.
- * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized
- * @li @a IX_ETH_ACC_INVALID_ARG : An argument other than portId is invalid.
- *
- * <hr>
- */
-PUBLIC IxEthAccStatus
-ixEthAccPortRxCallbackRegister(IxEthAccPortId portId,
-							   IxEthAccPortRxCallback rxCallbackFn,
-							   UINT32 callbackTag);
-
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn ixEthAccPortMultiBufferRxCallbackRegister( IxEthAccPortId portId, IxEthAccPortMultiBufferRxCallback rxCallbackFn, UINT32 callbackTag)
- *
- * @brief Register a callback function to allow 
- * the reception of frames.
- * 
- * The registered callback function is called once a frame is 
- * received  by this service. If many frames are already received, 
- * the function is called once.
- *
- * If called several times the latest callback shall be registered for a particular port.
- *
- * @li Reentrant    - yes
- * @li ISR Callable - yes
- *
- *
- * @param portId - Register callback for a particular MAC device.
- * @param rxCallbackFn - @a IxEthAccMultiBufferRxCallbackFn - Function to be called when Ethernet frames are availble.
- * @param callbackTag -  This tag shall be provided to the callback function.
- *
- * @return IxEthAccStatus
- * @li @a IX_ETH_ACC_SUCCESS 
- * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid.
- * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized
- * @li @a IX_ETH_ACC_INVALID_ARG : An argument other than portId is invalid.
- *
- * @sa ixEthAccPortMultiBufferRxCallbackRegister
- * @sa IxEthAccPortMultiBufferRxCallback
- * @sa ixEthAccPortRxCallbackRegister
- * @sa IxEthAccPortRxCallback
- * <hr>
- */
-PUBLIC IxEthAccStatus
-ixEthAccPortMultiBufferRxCallbackRegister(IxEthAccPortId portId,
-										  IxEthAccPortMultiBufferRxCallback rxCallbackFn,
-										  UINT32 callbackTag);
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn ixEthAccPortRxFreeReplenish( IxEthAccPortId portId, IX_OSAL_MBUF *buffer)
- *
- * @brief This function provides buffers for the Ethernet receive path. 
- *
- * This component does not have a buffer management mechanisms built in. All Rx buffers must be supplied to it
- * via this interface. 
- *
- * @li Reentrant    - yes
- * @li ISR Callable - yes
- *
- * @param portId @ref IxEthAccPortId [in] - Provide buffers only to specific Rx MAC. 
- * @param buffer @ref IX_OSAL_MBUF [in] - Provide an MBUF to the Ethernet receive mechanism. 
- *                 Buffers size smaller than IX_ETHACC_RX_MBUF_MIN_SIZE may result in poor
- *                 performances and excessive buffer chaining. Buffers
- *                 larger than this size may be suitable for jumbo frames.
- *                 Chained packets are not supported and the field IX_OSAL_MBUF_NEXT_PKT_IN_CHAIN_PTR must be NULL. 
- *
- * @return IxEthAccStatus
- * @li @a IX_ETH_ACC_SUCCESS
- * @li @a IX_ETH_ACC_FAIL : Buffer has was not able to queue the 
- *                     buffer in the receive service.
- * @li @a IX_ETH_ACC_FAIL : Buffer size is less than IX_ETHACC_RX_MBUF_MIN_SIZE
- * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid.
- * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized
- *
- * @note
- * If the buffer replenish operation fails it is the responsibility 
- * of the user to free the buffer.
- *
- * @note
- * Sufficient buffers must be supplied to the component to maintain
- * receive throughput and avoid rx buffer underflow conditions.
- * To meet this goal, It is expected that the user preload the 
- * component with a sufficent number of buffers prior to enabling the
- * NPE Ethernet receive path. The recommended minimum number of 
- * buffers is 8.
- *
- * @note
- * For maximum performances, the mbuf size should be greater 
- * than the maximum frame size (Ethernet header, payload and FCS) + 64. 
- * Supplying smaller mbufs to the service results in mbuf
- * chaining and degraded performances. The recommended size
- * is @a IX_ETHACC_RX_MBUF_MIN_SIZE, which is
- * enough to take care of 802.3 frames and "baby jumbo" frames without
- * chaining, and "jumbo" frame within chaining.
- *
- * @note
- * Buffers may not be filled up to their length. The firware fills
- * them up to the previous 64 bytes boundary. The user has to be aware 
- * that the length of the received mbufs may be smaller than the length
- * of the supplied mbufs.
- *
- * @warning This function checks the parameters if the NDEBUG 
- * flag is not defined. Turning on the argument checking (disabled by 
- * default) results in a lower EthAcc performance as this function
- * is part of the data path.
- *
- * <hr>
- */
-PUBLIC IxEthAccStatus
-ixEthAccPortRxFreeReplenish( IxEthAccPortId portId, IX_OSAL_MBUF *buffer);
-
-
-
-/***************************************************************
-
-  ####    ####   #    #   #####  #####    ####   #
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-         #####   #         ##    #    #  ######
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-***************************************************************/
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn ixEthAccPortEnable(IxEthAccPortId portId)
- *
- * @brief This enables an Ethernet port for both Tx and Rx. 
- *
- * @li Reentrant    - yes
- * @li ISR Callable - no
- *
- * @pre The port must first be initialized via @a ixEthAccPortInit and the MAC address 
- * must be set using @a ixEthAccUnicastMacAddressSet before enabling it
- * The rx and Tx Done callbacks registration via @a
- * ixEthAccPortTxDoneCallbackRegister amd @a  ixEthAccPortRxCallbackRegister
- * has to be done before enabling the traffic.
- * 
- * @param  portId @ref IxEthAccPortId [in] - Port id to act upon.
- * 
- * @return IxEthAccStatus
- * @li @a IX_ETH_ACC_SUCCESS 
- * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid.
- * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is not initialized
- * @li @a IX_ETH_ACC_MAC_UNINITIALIZED : port MAC address is not initialized
- *
- * <hr>
- */
-PUBLIC IxEthAccStatus ixEthAccPortEnable(IxEthAccPortId portId);
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn ixEthAccPortDisable(IxEthAccPortId portId)
- *
- * @brief This disables an Ethernet port for both Tx and Rx. 
- *
- * Free MBufs are returned to the user via the registered callback when the port is disabled 
- *
- * @li Reentrant    - yes
- * @li ISR Callable - no
- *
- * @pre The port must be enabled with @a ixEthAccPortEnable, otherwise this
- * function has no effect
- *
- * @param  portId @ref IxEthAccPortId [in] - Port id to act upon.
- * 
- * @return IxEthAccStatus
- * @li @a IX_ETH_ACC_SUCCESS 
- * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid.
- * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is not initialized
- * @li @a IX_ETH_ACC_MAC_UNINITIALIZED : port MAC address is not initialized
- *
- * <hr>
- */
-PUBLIC IxEthAccStatus ixEthAccPortDisable(IxEthAccPortId portId);
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn ixEthAccPortEnabledQuery(IxEthAccPortId portId, BOOL *enabled)
- *
- * @brief Get the enabled state of a port.
- *
- * @li Reentrant    - yes
- * @li ISR Callable - yes
- *
- * @pre The port must first be initialized via @a ixEthAccPortInit
- *
- * @param  portId @ref IxEthAccPortId [in] - Port id to act upon.
- * @param  enabled BOOL [out] - location to store the state of the port
- *
- * @return IxEthAccStatus
- * @li @a IX_ETH_ACC_SUCCESS
- * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid
- *
- * <hr>
- */
-PUBLIC IxEthAccStatus
-ixEthAccPortEnabledQuery(IxEthAccPortId portId, BOOL *enabled);
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn ixEthAccPortPromiscuousModeClear(IxEthAccPortId portId)
- *
- * @brief Put the Ethernet MAC device in non-promiscuous mode.
- * 
- * In non-promiscuous mode the MAC filters all frames other than 
- * destination MAC address which matches the following criteria:
- * @li Unicast address provisioned via @a ixEthAccUnicastMacAddressSet
- * @li All broadcast frames.
- * @li Multicast addresses provisioned via @a ixEthAccMulticastAddressJoin
- *
- * Other functions modify the MAC filtering
- *
- * @li @a ixEthAccPortMulticastAddressJoinAll() - all multicast
- *     frames are forwarded to the application
- * @li @a ixEthAccPortMulticastAddressLeaveAll() - rollback the
- *     effects of @a ixEthAccPortMulticastAddressJoinAll()
- * @li @a ixEthAccPortMulticastAddressLeave() - unprovision a new 
- *     filtering address
- * @li @a ixEthAccPortMulticastAddressJoin() - provision a new 
- *     filtering address
- * @li @a ixEthAccPortPromiscuousModeSet() - all frames are 
- *     forwarded to the application regardless of the multicast 
- *     address provisioned
- * @li @a ixEthAccPortPromiscuousModeClear() - frames are forwarded 
- *     to the application following the multicast address provisioned
- *
- * In all cases, unicast and broadcast addresses are forwarded to 
- * the application.
- *
- * @li Reentrant    - yes
- * @li ISR Callable - no
- * 
- * @sa ixEthAccPortPromiscuousModeSet
- * 
- * @param portId @ref IxEthAccPortId [in] - Ethernet port id.
- * 
- * @return IxEthAccStatus 
- * @li @a IX_ETH_ACC_SUCCESS
- * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid.
- * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized
- *
- * <hr>
- */
-PUBLIC IxEthAccStatus ixEthAccPortPromiscuousModeClear(IxEthAccPortId portId);
-
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn  ixEthAccPortPromiscuousModeSet(IxEthAccPortId portId)
- *
- * @brief Put the MAC device in promiscuous mode.
- * 
- * If the device is in promiscuous mode then all all received frames shall be forwared
- * to the NPE for processing.
- *
- * Other functions modify the MAC filtering
- *
- * @li @a ixEthAccPortMulticastAddressJoinAll() - all multicast
- *     frames are forwarded to the application
- * @li @a ixEthAccPortMulticastAddressLeaveAll() - rollback the
- *     effects of @a ixEthAccPortMulticastAddressJoinAll()
- * @li @a ixEthAccPortMulticastAddressLeave() - unprovision a new 
- *     filtering address
- * @li @a ixEthAccPortMulticastAddressJoin() - provision a new 
- *     filtering address
- * @li @a ixEthAccPortPromiscuousModeSet() - all frames are 
- *     forwarded to the application regardless of the multicast 
- *     address provisioned
- * @li @a ixEthAccPortPromiscuousModeClear() - frames are forwarded 
- *     to the application following the multicast address provisioned
- *
- * In all cases, unicast and broadcast addresses are forwarded to 
- * the application.
- *
- * @li Reentrant    - yes
- * @li ISR Callable - no
- * 
- * @sa ixEthAccPortPromiscuousModeClear
- *
- * @param portId @ref IxEthAccPortId [in] - Ethernet port id.
- * 
- * @return IxEthAccStatus 
- * @li @a IX_ETH_ACC_SUCCESS
- * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid.
- * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized
- *
- * <hr>
- */
-PUBLIC IxEthAccStatus ixEthAccPortPromiscuousModeSet(IxEthAccPortId portId);
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn ixEthAccPortUnicastMacAddressSet(      IxEthAccPortId portId,
-                                                  IxEthAccMacAddr *macAddr)
- *
- * @brief Configure unicast MAC address for a particular port
- *
- *
- * @li Reentrant    - yes
- * @li ISR Callable - no
- *
- * @param portId @ref IxEthAccPortId [in] - Ethernet port id.
- * @param *macAddr @ref IxEthAccMacAddr [in] - Ethernet Mac address.
- *
- * @return IxEthAccStatus 
- * @li @a IX_ETH_ACC_SUCCESS
- * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid.
- * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized
- *
- * <hr>
- */
-PUBLIC IxEthAccStatus ixEthAccPortUnicastMacAddressSet(IxEthAccPortId portId,
-													   IxEthAccMacAddr *macAddr);
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn ixEthAccPortUnicastMacAddressGet(	IxEthAccPortId portId, 
-					IxEthAccMacAddr *macAddr)
- *
- * @brief Get unicast MAC address for a particular MAC port 
- *
- * @pre
- * The MAC address must first be set via @a ixEthAccMacPromiscuousModeSet
- * If the MAC address has not been set, the function returns a 
- * IX_ETH_ACC_MAC_UNINITIALIZED status
- *
- * @li Reentrant    - yes
- * @li ISR Callable - no
- *
- * @param portId @ref IxEthAccPortId [in] - Ethernet port id.
- * @param *macAddr @ref IxEthAccMacAddr [out] - Ethernet MAC address.
- *
- * @return  IxEthAccStatus
- * @li @a IX_ETH_ACC_SUCCESS
- * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid.
- * @li @a IX_ETH_ACC_MAC_UNINITIALIZED : port MAC address is not initialized.
- * @li @a IX_ETH_ACC_FAIL : macAddr is invalid.
- *
- * <hr>
- */
-PUBLIC IxEthAccStatus
-ixEthAccPortUnicastMacAddressGet(IxEthAccPortId portId,
-								 IxEthAccMacAddr *macAddr);
-
-
-
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn ixEthAccPortMulticastAddressJoin(      IxEthAccPortId portId,
-                                             IxEthAccMacAddr *macAddr)
- *
- * @brief Add a multicast address to the MAC address table.
- *
- *  @note
- *  Due to the operation of the Ethernet MAC multicast filtering mechanism, frames which do not 
- *  have a multicast destination address which were provisioned via this API may be forwarded 
- *  to the NPE's. This is a result of the hardware comparison  algorithm used in the destination mac address logic
- *  within the Ethernet MAC. 
- *
- *  See Also: IXP425 hardware development manual.
- * 
- * Other functions modify the MAC filtering
- *
- * @li @a ixEthAccPortMulticastAddressJoinAll() - all multicast
- *     frames are forwarded to the application
- * @li @a ixEthAccPortMulticastAddressLeaveAll() - rollback the
- *     effects of @a ixEthAccPortMulticastAddressJoinAll()
- * @li @a ixEthAccPortMulticastAddressLeave() - unprovision a new 
- *     filtering address
- * @li @a ixEthAccPortMulticastAddressJoin() - provision a new 
- *     filtering address
- * @li @a ixEthAccPortPromiscuousModeSet() - all frames are 
- *     forwarded to the application regardless of the multicast 
- *     address provisioned
- * @li @a ixEthAccPortPromiscuousModeClear() - frames are forwarded 
- *     to the application following the multicast address provisioned
- *
- * In all cases, unicast and broadcast addresses are forwarded to 
- * the application.
- *
- * @li Reentrant    - yes
- * @li ISR Callable - no
- *
- * @param portId @ref IxEthAccPortId [in] - Ethernet port id.
- * @param *macAddr @ref IxEthAccMacAddr [in] - Ethernet Mac address.
- *
- * @return IxEthAccStatus 
- * @li @a IX_ETH_ACC_SUCCESS
- * @li @a IX_ETH_ACC_FAIL : Error writing to the MAC registers
- * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid.
- * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized
- *
- * <hr>
- */
-PUBLIC IxEthAccStatus
-ixEthAccPortMulticastAddressJoin(IxEthAccPortId portId,
-								 IxEthAccMacAddr *macAddr);
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn ixEthAccPortMulticastAddressJoinAll(  IxEthAccPortId portId)
- *
- * @brief Filter all frames with multicast dest.
- *
- * This function clears the MAC address table, and then sets
- * the MAC to forward ALL multicast frames to the NPE.
- * Specifically, it forwards all frames whose destination address
- * has the LSB of the highest byte set  (01:00:00:00:00:00).  This
- * bit is commonly referred to as the "multicast bit".
- * Broadcast frames will still be forwarded. 
- *
- * Other functions modify the MAC filtering
- *
- * @li @a ixEthAccPortMulticastAddressJoinAll() - all multicast
- *     frames are forwarded to the application
- * @li @a ixEthAccPortMulticastAddressLeaveAll() - rollback the
- *     effects of @a ixEthAccPortMulticastAddressJoinAll()
- * @li @a ixEthAccPortMulticastAddressLeave() - unprovision a new 
- *     filtering address
- * @li @a ixEthAccPortMulticastAddressJoin() - provision a new 
- *     filtering address
- * @li @a ixEthAccPortPromiscuousModeSet() - all frames are 
- *     forwarded to the application regardless of the multicast 
- *     address provisioned
- * @li @a ixEthAccPortPromiscuousModeClear() - frames are forwarded 
- *     to the application following the multicast address provisioned
- *
- * In all cases, unicast and broadcast addresses are forwarded to 
- * the application.
- *
- * @li Reentrant    - yes
- * @li ISR Callable - no
- *
- * @param portId @ref IxEthAccPortId [in] - Ethernet port id.
- *
- * @return IxEthAccStatus 
- * @li @a IX_ETH_ACC_SUCCESS
- * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid.
- * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized
- *
- * <hr>
- */
-PUBLIC IxEthAccStatus
-ixEthAccPortMulticastAddressJoinAll(IxEthAccPortId portId);
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn ixEthAccPortMulticastAddressLeave( IxEthAccPortId portId,
-                                         IxEthAccMacAddr *macAddr)
- *
- * @brief Remove a multicast address from the MAC address table.
- *
- * Other functions modify the MAC filtering
- *
- * @li @a ixEthAccPortMulticastAddressJoinAll() - all multicast
- *     frames are forwarded to the application
- * @li @a ixEthAccPortMulticastAddressLeaveAll() - rollback the
- *     effects of @a ixEthAccPortMulticastAddressJoinAll()
- * @li @a ixEthAccPortMulticastAddressLeave() - unprovision a new 
- *     filtering address
- * @li @a ixEthAccPortMulticastAddressJoin() - provision a new 
- *     filtering address
- * @li @a ixEthAccPortPromiscuousModeSet() - all frames are 
- *     forwarded to the application regardless of the multicast 
- *     address provisioned
- * @li @a ixEthAccPortPromiscuousModeClear() - frames are forwarded 
- *     to the application following the multicast address provisioned
- *
- * In all cases, unicast and broadcast addresses are forwarded to 
- * the application.
- *
- * @li Reentrant    - yes
- * @li ISR Callable - no
- *
- * @param portId @ref IxEthAccPortId [in] - Ethernet port id.
- * @param *macAddr @ref IxEthAccMacAddr [in] - Ethernet Mac address.
- *
- * @return IxEthAccStatus
- * @li @a IX_ETH_ACC_SUCCESS
- * @li @a IX_ETH_ACC_NO_SUCH_ADDR :  Failed if MAC address was not in the table.
- * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid.
- * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized
- *
- * <hr>
- */
-PUBLIC IxEthAccStatus
-ixEthAccPortMulticastAddressLeave(IxEthAccPortId portId,
-								  IxEthAccMacAddr *macAddr);
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn ixEthAccPortMulticastAddressLeaveAll( IxEthAccPortId portId)
- *
- * @brief This function unconfigures the multicast filtering settings
- *
- * This function first clears the MAC address table, and then sets
- * the MAC as configured by the promiscuous mode current settings.
- *
- * Other functions modify the MAC filtering
- *
- * @li @a ixEthAccPortMulticastAddressJoinAll() - all multicast
- *     frames are forwarded to the application
- * @li @a ixEthAccPortMulticastAddressLeaveAll() - rollback the
- *     effects of @a ixEthAccPortMulticastAddressJoinAll()
- * @li @a ixEthAccPortMulticastAddressLeave() - unprovision a new 
- *     filtering address
- * @li @a ixEthAccPortMulticastAddressJoin() - provision a new 
- *     filtering address
- * @li @a ixEthAccPortPromiscuousModeSet() - all frames are 
- *     forwarded to the application regardless of the multicast 
- *     address provisioned
- * @li @a ixEthAccPortPromiscuousModeClear() - frames are forwarded 
- *     to the application following the multicast address provisioned
- *
- * In all cases, unicast and broadcast addresses are forwarded to 
- * the application.
- *
- * @li Reentrant    - yes
- * @li ISR Callable - no
- *
- * @param portId @ref IxEthAccPortId [in] - Ethernet port id.
- *
- * @return IxEthAccStatus
- * @li @a IX_ETH_ACC_SUCCESS
- * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid.
- * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized
- *
- * <hr>
- */
-PUBLIC IxEthAccStatus
-ixEthAccPortMulticastAddressLeaveAll(IxEthAccPortId portId);
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn ixEthAccPortUnicastAddressShow(IxEthAccPortId portId)
- *
- * @brief Displays unicast MAC address
- *
- * Displays unicast address which is configured using 
- * @a ixEthAccUnicastMacAddressSet. This function also displays the MAC filter used
- * to filter multicast frames.
- *
- * Other functions modify the MAC filtering
- *
- * @li @a ixEthAccPortMulticastAddressJoinAll() - all multicast
- *     frames are forwarded to the application
- * @li @a ixEthAccPortMulticastAddressLeaveAll() - rollback the
- *     effects of @a ixEthAccPortMulticastAddressJoinAll()
- * @li @a ixEthAccPortMulticastAddressLeave() - unprovision a new 
- *     filtering address
- * @li @a ixEthAccPortMulticastAddressJoin() - provision a new 
- *     filtering address
- * @li @a ixEthAccPortPromiscuousModeSet() - all frames are 
- *     forwarded to the application regardless of the multicast 
- *     address provisioned
- * @li @a ixEthAccPortPromiscuousModeClear() - frames are forwarded 
- *     to the application following the multicast address provisioned
- *
- * In all cases, unicast and broadcast addresses are forwarded to 
- * the application.
- *
- * @li Reentrant    - yes
- * @li ISR Callable - no
- *
- * @param portId @ref IxEthAccPortId [in] - Ethernet port id.
- *
- * @return void
- *
- * <hr>
- */
-PUBLIC IxEthAccStatus ixEthAccPortUnicastAddressShow(IxEthAccPortId portId);
-
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn ixEthAccPortMulticastAddressShow( IxEthAccPortId portId)
- *
- * @brief Displays multicast MAC address
- *
- * Displays multicast address which have been configured using @a ixEthAccMulticastAddressJoin
- * 
- * @li Reentrant    - yes
- * @li ISR Callable - no
- * 
- * @param portId @ref IxEthAccPortId [in] - Ethernet port id.
- *
- * @return void
- *
- * <hr>
- */
-PUBLIC void ixEthAccPortMulticastAddressShow( IxEthAccPortId portId);
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn ixEthAccPortDuplexModeSet( IxEthAccPortId portId, IxEthAccDuplexMode mode )
- *
- * @brief  Set the duplex mode for the MAC.
- *
- * Configure the IXP400 MAC to either full or half duplex. 
- *
- * @note 
- * The configuration should match that provisioned on the PHY.
- *
- * @li Reentrant    - yes
- * @li ISR Callable - no
- *
- * @param portId @ref IxEthAccPortId [in]
- * @param mode @ref IxEthAccDuplexMode [in]
- *
- * @return IxEthAccStatus 
- * @li @a IX_ETH_ACC_SUCCESS 
- * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid.
- * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized
- *
- * <hr>
- */
-PUBLIC IxEthAccStatus 
-ixEthAccPortDuplexModeSet(IxEthAccPortId portId,IxEthAccDuplexMode mode);
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn ixEthAccPortDuplexModeGet( IxEthAccPortId portId, IxEthAccDuplexMode *mode )
- *
- * @brief  Get the duplex mode for the MAC.
- *
- * return the duplex configuration of the IXP400 MAC.
- *
- * @note
- * The configuration should match that provisioned on the PHY.
- * See @a ixEthAccDuplexModeSet
- *
- * @li Reentrant    - yes
- * @li ISR Callable - no
- *
- * @param portId @ref IxEthAccPortId [in]
- * @param *mode @ref IxEthAccDuplexMode [out]
- *
- * @return IxEthAccStatus
- * @li @a IX_ETH_ACC_SUCCESS 
- * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid.
- * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized
- *
- * <hr>
- *
- */
-PUBLIC IxEthAccStatus 
-ixEthAccPortDuplexModeGet(IxEthAccPortId portId,IxEthAccDuplexMode *mode );
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn ixEthAccPortTxFrameAppendPaddingEnable( IxEthAccPortId portId)
- *
- * @brief  Enable padding bytes to be appended to runt frames submitted to
- * this port
- * 
- * Enable up to 60 null-bytes padding bytes to be appended to runt frames 
- * submitted to this port. This is the default behavior of the access 
- * component.
- *
- * @warning Do not change this behaviour while the port is enabled.
- *
- * @note When Tx padding is enabled, Tx FCS generation is turned on
- *
- * @li Reentrant    - yes
- * @li ISR Callable - no
- *
- * @sa ixEthAccPortTxFrameAppendFCSDusable
- *
- * @param portId @ref IxEthAccPortId [in]
- *
- * @return IxEthAccStatus
- * @li @a IX_ETH_ACC_SUCCESS 
- * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid.
- * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized
- *
- * <hr>
- */
-PUBLIC IxEthAccStatus
-ixEthAccPortTxFrameAppendPaddingEnable(IxEthAccPortId portId);
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn ixEthAccPortTxFrameAppendPaddingDisable( IxEthAccPortId portId)
- *
- * @brief  Disable padding bytes to be appended to runt frames submitted to
- * this port
- * 
- * Disable padding bytes to be appended to runt frames 
- * submitted to this port. This is not the default behavior of the access 
- * component.
- *
- * @warning Do not change this behaviour while the port is enabled.
- *
- * @li Reentrant    - yes
- * @li ISR Callable - no
- *
- * @param portId @ref IxEthAccPortId [in] 
- *
- * @return IxEthAccStatus
- * @li @a IX_ETH_ACC_SUCCESS 
- * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid.
- * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized
- *
- * <hr>
- */
-PUBLIC IxEthAccStatus
-ixEthAccPortTxFrameAppendPaddingDisable(IxEthAccPortId portId);
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn ixEthAccPortTxFrameAppendFCSEnable( IxEthAccPortId portId)
- *
- * @brief  Enable the appending of Ethernet FCS to all frames submitted to this port
- * 
- * When enabled, the FCS is added to the submitted frames. This is the default 
- * behavior of the access component.
- * Do not change this behaviour while the port is enabled.
- *
- * @li Reentrant    - yes
- * @li ISR Callable - no
- *
- * @param portId @ref IxEthAccPortId [in] 
- *
- * @return IxEthAccStatus
- * @li @a IX_ETH_ACC_SUCCESS 
- * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid.
- * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized
- *
- * <hr>
- */
-PUBLIC IxEthAccStatus
-ixEthAccPortTxFrameAppendFCSEnable(IxEthAccPortId portId);
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn ixEthAccPortTxFrameAppendFCSDisable( IxEthAccPortId portId)
- *
- * @brief  Disable the appending of Ethernet FCS to all frames submitted to this port.
- * 
- * When disabled, the Ethernet FCS is not added to the submitted frames. 
- * This is not the default
- * behavior of the access component.
- *
- * @note Since the FCS is not appended to the frame it is expected that the frame submitted to the 
- * component includes a valid FCS at the end of the data, although this will not be validated.
- *
- * The component shall forward the frame to the Ethernet MAC WITHOUT modification.
- *
- * Do not change this behaviour while the port is enabled.
- *
- * @note Tx FCS append is not disabled while Tx padding is enabled.
- *
- * @li Reentrant    - yes
- * @li ISR Callable - no
- *
- * @sa ixEthAccPortTxFrameAppendPaddingEnable
- *
- * @param portId @ref IxEthAccPortId [in] 
- *
- * @return IxEthAccStatus
- * @li @a IX_ETH_ACC_SUCCESS 
- * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid.
- * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized
- *
- * <hr>
- */
-PUBLIC IxEthAccStatus
-ixEthAccPortTxFrameAppendFCSDisable(IxEthAccPortId portId);
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn ixEthAccPortRxFrameAppendFCSEnable( IxEthAccPortId portId)
- *
- * @brief Forward frames with FCS included in the receive buffer.
- *
- * The FCS is not striped from the receive buffer. 
- * The received frame length includes the FCS size (4 bytes). ie. 
- * A minimum sized ethernet frame shall have a length of 64bytes.
- *
- * Frame FCS validity checks are still carried out on all received frames.
- *
- * This is not the default
- * behavior of the access component.
- *
- * @li Reentrant    - yes
- * @li ISR Callable - no
- *
- * @param portId @ref IxEthAccPortId [in]
- *
- * @return IxEthAccStatus
- * @li @a IX_ETH_ACC_SUCCESS 
- * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid.
- * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized
- *
- * <hr>
- */
-PUBLIC IxEthAccStatus
-ixEthAccPortRxFrameAppendFCSEnable(IxEthAccPortId portId);
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn ixEthAccPortRxFrameAppendFCSDisable( IxEthAccPortId portId)
- *
- * @brief  Do not forward the FCS portion of the received Ethernet frame to the user. 
- * The FCS is striped from the receive buffer. 
- * The received frame length does not include the FCS size (4 bytes).
- * Frame FCS validity checks are still carried out on all received frames.
- *
- * This is the default behavior of the component.
- * Do not change this behaviour while the port is enabled.
- *
- * @li Reentrant    - yes
- * @li ISR Callable - no
- *
- * @param portId @ref IxEthAccPortId [in]
- *
- * @return IxEthAccStatus
- * @li @a IX_ETH_ACC_SUCCESS 
- * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid.
- * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized
- *
- * <hr>
- */
-PUBLIC IxEthAccStatus
-ixEthAccPortRxFrameAppendFCSDisable(IxEthAccPortId portId);
-
-
-
-
-/**
- * @ingroup IxEthAcc
- *
- * @enum IxEthAccSchedulerDiscipline
- *
- * @brief  Definition for the port scheduling discipline
- *
- * Select the port scheduling discipline on receive and transmit path
- * @li FIFO : No Priority : In this configuration all frames are processed
- *                       in the access component in the strict order in which 
- *                        the component received them.
- * @li FIFO : Priority : This shall be a very simple priority mechanism. 
- *                     Higher prior-ity frames shall be forwarded 
- *                     before lower priority frames. There shall be no 
- *                     fairness mechanisms applied across different 
- *                     priorities. Higher priority frames could starve 
- *                     lower priority frames indefinitely.
- */
-typedef  enum 
-{
-    FIFO_NO_PRIORITY, /**<frames submitted with no priority*/
-    FIFO_PRIORITY /**<higher prority frames submitted before lower priority*/
-}IxEthAccSchedulerDiscipline;
-
-/**
- * @ingroup IxEthAcc
- *
- * @def IxEthAccTxSchedulerDiscipline
- *
- * @brief  Deprecated definition for the port transmit scheduling discipline
- */ 
-#define IxEthAccTxSchedulerDiscipline IxEthAccSchedulerDiscipline
-
-
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn ixEthAccTxSchedulingDisciplineSet( IxEthAccPortId portId, IxEthAccSchedulerDiscipline sched)
- *
- * @brief Set the port scheduling to one of @a IxEthAccSchedulerDiscipline
- *
- * The default behavior of the component is @a FIFO_NO_PRIORITY.
- *
- * @li Reentrant    - yes
- * @li ISR Callable - no
- *
- * @pre
- *
- *
- * @param portId @ref IxEthAccPortId [in] 
- * @param sched @ref IxEthAccSchedulerDiscipline [in] 
- *
- * @return IxEthAccStatus
- * @li @a IX_ETH_ACC_SUCCESS : Set appropriate discipline.
- * @li @a IX_ETH_ACC_FAIL :  Invalid/unsupported discipline.
- * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid.
- * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized
- *
- * <hr>
- */
-PUBLIC IxEthAccStatus
-ixEthAccTxSchedulingDisciplineSet(IxEthAccPortId portId, 
-								  IxEthAccSchedulerDiscipline sched);
-
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn ixEthAccRxSchedulingDisciplineSet(IxEthAccSchedulerDiscipline sched)
- *
- * @brief Set the Rx scheduling to one of @a IxEthAccSchedulerDiscipline
- *
- * The default behavior of the component is @a FIFO_NO_PRIORITY.
- *
- * @li Reentrant    - yes
- * @li ISR Callable - no
- *
- * @pre
- *
- * @param sched : @a IxEthAccSchedulerDiscipline 
- *
- * @return IxEthAccStatus
- * @li @a IX_ETH_ACC_SUCCESS : Set appropriate discipline.
- * @li @a IX_ETH_ACC_FAIL :  Invalid/unsupported discipline.
- *
- * <hr>
- */
-PUBLIC IxEthAccStatus
-ixEthAccRxSchedulingDisciplineSet(IxEthAccSchedulerDiscipline sched);
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn IxEthAccStatus ixEthAccNpeLoopbackEnable(IxEthAccPortId portId)
- *
- * @brief Enable NPE loopback
- *
- * When this loopback mode is enabled all the transmitted frames are
- * received on the same port, without payload.
- *
- * This function is recommended for power-up diagnostic checks and
- * should never be used under normal Ethernet traffic operations.
- *
- * @li Reentrant    - yes
- * @li ISR Callable - no
- *
- * @pre
- *
- * @param portId : ID of the port 
- *
- * @note Calling ixEthAccPortDisable followed by ixEthAccPortEnable is
- * guaranteed to restore correct Ethernet Tx/Rx operation.
- *
- * @return IxEthAccStatus
- * @li @a IX_ETH_ACC_SUCCESS : NPE loopback mode enabled
- * @li @a IX_ETH_ACC_FAIL : Invalid port or Ethernet service not initialized
- *
- * <hr>
- */
-PUBLIC IxEthAccStatus 
-ixEthAccPortNpeLoopbackEnable(IxEthAccPortId portId);
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn IxEthAccStatus ixEthAccPortNpeLoopbackDisable(IxEthAccPortId portId)
- *
- * @brief Disable NPE loopback
- *
- * This function is used to disable the NPE loopback if previously
- * enabled using ixEthAccNpeLoopbackEnable.
- *
- * This function is recommended for power-up diagnostic checks and
- * should never be used under normal Ethernet traffic operations.
- *
- * @li Reentrant    - yes
- * @li ISR Callable - no
- *
- * @pre
- *
- * @note Calling ixEthAccPortDisable followed by ixEthAccPortEnable is
- * guaranteed to restore correct Ethernet Tx/Rx operation.
- *
- * @param portId : ID of the port 
- *
- * @return IxEthAccStatus
- * @li @a IX_ETH_ACC_SUCCESS : NPE loopback successfully disabled
- * @li @a IX_ETH_ACC_FAIL : Invalid port or Ethernet service not initialized
- *
- * <hr>
- */
-PUBLIC IxEthAccStatus 
-ixEthAccPortNpeLoopbackDisable(IxEthAccPortId portId);
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn IxEthAccStatus ixEthAccPortTxEnable(IxEthAccPortId portId)
- *
- * @brief Enable Tx on the port
- *
- * This function is the complement of ixEthAccPortTxDisable and should
- * be used only after Tx was disabled. A MAC core reset is required before
- * this function is called (see @a ixEthAccPortMacReset).
- *
- * This function is the recommended usage scenario for emergency security
- * shutdown and hardware failure recovery and should never be used for throttling 
- * traffic.
- *
- * @li Reentrant    - yes
- * @li ISR Callable - no
- *
- * @pre
- *
- * @note Calling ixEthAccPortDisable followed by ixEthAccPortEnable is
- * guaranteed to restore correct Ethernet Tx/Rx operation.
- *
- * @param portId : ID of the port 
- *
- * @return IxEthAccStatus
- * @li @a IX_ETH_ACC_SUCCESS : Tx successfully enabled
- * @li @a IX_ETH_ACC_FAIL : Invalid port or Ethernet service not initialized
- *
- * <hr>
- */
-PUBLIC IxEthAccStatus 
-ixEthAccPortTxEnable(IxEthAccPortId portId);
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn IxEthAccStatus ixEthAccPortTxDisable(IxEthAccPortId portId)
- *
- * @brief Disable Tx on the port
- *
- * This function can be used to disable Tx in the MAC core.
- * Tx can be re-enabled, although this is not guaranteed, by performing
- * a MAC core reset (@a ixEthAccPortMacReset) and calling ixEthAccPortTxEnable.
- * Note that using this function is not recommended, except for shutting
- * down Tx for emergency reasons. For proper port shutdown and re-enabling
- * see ixEthAccPortEnable and ixEthAccPortDisable.
- *
- * This function is the recommended usage scenario for emergency security
- * shutdown and hardware failure recovery and should never be used for throttling 
- * traffic.
- *
- * @li Reentrant    - yes
- * @li ISR Callable - no
- *
- * @note Calling ixEthAccPortDisable followed by ixEthAccPortEnable is
- * guaranteed to restore correct Ethernet Tx/Rx operation.
- *
- * @pre
- *
- * @param portId : ID of the port 
- *
- * @return IxEthAccStatus
- * @li @a IX_ETH_ACC_SUCCESS : Tx successfully disabled
- * @li @a IX_ETH_ACC_FAIL : Invalid port or Ethernet service not initialized
- *
- * <hr>
- */
-PUBLIC IxEthAccStatus 
-ixEthAccPortTxDisable(IxEthAccPortId portId);
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn IxEthAccStatus ixEthAccPortRxEnable(IxEthAccPortId portId)
- *
- * @brief Enable Rx on the port
- *
- * This function is the complement of ixEthAccPortRxDisable and should
- * be used only after Rx was disabled.
- *
- * This function is the recommended usage scenario for emergency security
- * shutdown and hardware failure recovery and should never be used for throttling 
- * traffic.
- *
- * @li Reentrant    - yes
- * @li ISR Callable - no
- *
- * @note Calling ixEthAccPortDisable followed by ixEthAccPortEnable is
- * guaranteed to restore correct Ethernet Tx/Rx operation.
- *
- * @pre
- *
- * @param portId : ID of the port 
- *
- * @return IxEthAccStatus
- * @li @a IX_ETH_ACC_SUCCESS : Rx successfully enabled
- * @li @a IX_ETH_ACC_FAIL : Invalid port or Ethernet service not initialized
- *
- * <hr>
- */
-PUBLIC IxEthAccStatus 
-ixEthAccPortRxEnable(IxEthAccPortId portId);
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn IxEthAccStatus ixEthAccPortRxDisable(IxEthAccPortId portId)
- *
- * @brief Disable Rx on the port
- *
- * This function can be used to disable Rx in the MAC core.
- * Rx can be re-enabled, although this is not guaranteed, by performing
- * a MAC core reset (@a ixEthAccPortMacReset) and calling ixEthAccPortRxEnable.
- * Note that using this function is not recommended, except for shutting
- * down Rx for emergency reasons. For proper port shutdown and re-enabling
- * see ixEthAccPortEnable and ixEthAccPortDisable.
- *
- * This function is the recommended usage scenario for emergency security
- * shutdown and hardware failure recovery and should never be used for throttling 
- * traffic.
- *
- * @li Reentrant    - yes
- * @li ISR Callable - no
- *
- * @pre
- *
- * @note Calling ixEthAccPortDisable followed by ixEthAccPortEnable is
- * guaranteed to restore correct Ethernet Tx/Rx operation.
- *
- * @param portId : ID of the port 
- *
- * @return IxEthAccStatus
- * @li @a IX_ETH_ACC_SUCCESS : Rx successfully disabled
- * @li @a IX_ETH_ACC_FAIL : Invalid port or Ethernet service not initialized
- *
- * <hr>
- */
-PUBLIC IxEthAccStatus 
-ixEthAccPortRxDisable(IxEthAccPortId portId);
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn IxEthAccStatus ixEthAccPortMacReset(IxEthAccPortId portId)
- *
- * @brief Reset MAC core on the port
- *
- * This function will perform a MAC core reset (NPE Ethernet coprocessor).
- * This function is inherently unsafe and the NPE recovery is not guaranteed
- * after this function is called. The proper manner of performing port disable
- * and enable (which will reset the MAC as well) is ixEthAccPortEnable/ixEthAccPortDisable.
- *
- * This function is the recommended usage scenario for hardware failure recovery
- * and should never be used for throttling traffic.
- *
- * @li Reentrant    - yes
- * @li ISR Callable - no
- *
- * @pre
- *
- * @note Calling ixEthAccPortDisable followed by ixEthAccPortEnable is
- * guaranteed to restore correct Ethernet Tx/Rx operation.
- *
- * @param portId : ID of the port 
- *
- * @return IxEthAccStatus
- * @li @a IX_ETH_ACC_SUCCESS : MAC core reset
- * @li @a IX_ETH_ACC_FAIL : Invalid port or Ethernet service not initialized
- *
- * <hr>
- */
-PUBLIC IxEthAccStatus 
-ixEthAccPortMacReset(IxEthAccPortId portId);
-
-/*********************************************************************************
-  ####    #####    ##     #####     #     ####    #####     #     ####    ####
- #          #     #  #      #       #    #          #       #    #    #  #
-  ####      #    #    #     #       #     ####      #       #    #        ####
-      #     #    ######     #       #         #     #       #    #            #
- #    #     #    #    #     #       #    #    #     #       #    #    #  #    #
-  ####      #    #    #     #       #     ####      #       #     ####    ####
-**********************************************************************************/
-
-
-/**
- *
- * @brief This struct defines the statistics returned by this component.
- *
- * The component returns MIB2 EthObj variables which are obtained from the 
- * hardware or maintained by this component. 
- *
- *
- */
-typedef struct   
-{
-    UINT32 dot3StatsAlignmentErrors;            /**< link error count (rx) */
-    UINT32 dot3StatsFCSErrors;                  /**< link error count (rx) */
-    UINT32 dot3StatsInternalMacReceiveErrors;   /**< link error count (rx) */
-    UINT32 RxOverrunDiscards;                   /**< NPE: discarded frames count (rx) */
-    UINT32 RxLearnedEntryDiscards;                /**< NPE: discarded frames count(rx)  */
-    UINT32 RxLargeFramesDiscards;                 /**< NPE: discarded frames count(rx)  */
-    UINT32 RxSTPBlockedDiscards;                  /**< NPE: discarded frames count(rx)  */
-    UINT32 RxVLANTypeFilterDiscards;              /**< NPE: discarded frames count (rx) */
-    UINT32 RxVLANIdFilterDiscards;                /**< NPE: discarded frames count (rx) */
-    UINT32 RxInvalidSourceDiscards;               /**< NPE: discarded frames count (rx) */
-    UINT32 RxBlackListDiscards;                   /**< NPE: discarded frames count (rx) */
-    UINT32 RxWhiteListDiscards;                   /**< NPE: discarded frames count (rx) */
-    UINT32 RxUnderflowEntryDiscards;              /**< NPE: discarded frames count (rx) */
-    UINT32 dot3StatsSingleCollisionFrames;      /**< link error count (tx) */
-    UINT32 dot3StatsMultipleCollisionFrames;    /**< link error count (tx) */
-    UINT32 dot3StatsDeferredTransmissions;      /**< link error count (tx) */
-    UINT32 dot3StatsLateCollisions;             /**< link error count (tx) */
-    UINT32 dot3StatsExcessiveCollsions;         /**< link error count (tx) */
-    UINT32 dot3StatsInternalMacTransmitErrors;  /**< link error count (tx) */
-    UINT32 dot3StatsCarrierSenseErrors;         /**< link error count (tx) */
-    UINT32 TxLargeFrameDiscards;                /**< NPE: discarded frames count (tx) */
-    UINT32 TxVLANIdFilterDiscards;              /**< NPE: discarded frames count (tx) */
-
-}IxEthEthObjStats;
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn ixEthAccMibIIStatsGet(IxEthAccPortId portId ,IxEthEthObjStats *retStats )
- *
- * @brief  Returns the statistics maintained for a port.
- *
- * @li Reentrant    - yes
- * @li ISR Callable - no
- *
- * @pre
- *
- *
- * @param portId @ref IxEthAccPortId [in] 
- * @param retStats @ref IxEthEthObjStats [out]
- * @note Please note the user is responsible for cache coheriency of the retStat
- * buffer. The data is actually populated via the NPE's. As such cache safe
- * memory should be used in the retStats argument.
- *
- * @return IxEthAccStatus
- * @li @a IX_ETH_ACC_SUCCESS
- * @li @a IX_ETH_ACC_FAIL : Invalid arguments.
- * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid.
- * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized
- *
- * <hr>
- */
-PUBLIC IxEthAccStatus
-ixEthAccMibIIStatsGet(IxEthAccPortId portId, IxEthEthObjStats *retStats );
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn ixEthAccMibIIStatsGetClear(IxEthAccPortId portId, IxEthEthObjStats *retStats)
- * 
- * @brief  Returns and clears the statistics maintained for a port. 
- *
- * @li Reentrant    - yes
- * @li ISR Callable - yes
- *
- * @pre
- *
- * @param portId @ref IxEthAccPortId [in] 
- * @param retStats @ref IxEthEthObjStats [out]
- * @note Please note the user is responsible for cache coheriency of the retStats
- * buffer. The data is actually populated via the NPE's. As such cache safe
- * memory should be used in the retStats argument.
- *
- * @return IxEthAccStatus
- * @li @a IX_ETH_ACC_SUCCESS
- * @li @a IX_ETH_ACC_FAIL : invalid arguments.
- * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid.
- * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized
- *
- * <hr>
- */
-PUBLIC IxEthAccStatus
-ixEthAccMibIIStatsGetClear(IxEthAccPortId portId, IxEthEthObjStats *retStats);
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn ixEthAccMibIIStatsClear(IxEthAccPortId portId)
- *
- * @brief   Clears the statistics maintained for a port.
- *
- * @li Reentrant    - yes
- * @li ISR Callable - no
- *
- * @pre
- *
- * @param portId @ref IxEthAccPortId [in]
- *
- * @return IxEthAccStatus
- * @li @a IX_ETH_ACC_SUCCESS
- * @li @a IX_ETH_ACC_FAIL : Invalid arguments.
- * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid.
- * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized
- *
- * <hr>
- */
-PUBLIC IxEthAccStatus ixEthAccMibIIStatsClear(IxEthAccPortId portId);
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn ixEthAccMacInit(IxEthAccPortId portId)
- * 
- * @brief Initializes the ethernet MAC settings 
- * 
- * @li Reentrant    - no
- * @li ISR Callable - no
- *
- * @param portId @ref IxEthAccPortId [in]
- *
- * @return IxEthAccStatus
- * @li @a IX_ETH_ACC_SUCCESS
- * @li @a IX_ETH_ACC_INVALID_PORT	:  portId is invalid.
- *
- * <hr>
- */
-PUBLIC IxEthAccStatus ixEthAccMacInit(IxEthAccPortId portId);
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn ixEthAccStatsShow(IxEthAccPortId portId)
- *
- *
- * @brief Displays a ports statistics on the standard io console using printf.
- *
- * @li Reentrant    - no
- * @li ISR Callable - no
- *
- * @pre
- *
- * @param portId @ref IxEthAccPortId [in]
- *
- * @return void
- *
- * <hr>
- */
-PUBLIC void ixEthAccStatsShow(IxEthAccPortId portId);
-
-/*************************************************************************
-
- #    #     #       #            #    #  #####      #     ####
- ##  ##     #       #            ##  ##  #    #     #    #    #
- # ## #     #       #            # ## #  #    #     #    #    #
- #    #     #       #            #    #  #    #     #    #    #
- #    #     #       #            #    #  #    #     #    #    #
- #    #     #       #            #    #  #####      #     ####
-
-*************************************************************************/
-
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn ixEthAccMiiReadRtn (UINT8 phyAddr, 
-                           UINT8 phyReg, 
-	                   UINT16 *value)
- *
- *
- * @brief Reads a 16 bit value from a PHY
- *
- * Reads a 16-bit word from a register of a MII-compliant PHY. Reading
- * is performed through the MII management interface.  This function returns
- * when the read operation has successfully completed, or when a timeout has elapsed.
- *
- * @li Reentrant    - no
- * @li ISR Callable - no
- *
- * @pre The MAC on Ethernet Port 2 (NPE C) must be initialised, and generating the MDIO clock.
- *   
- * @param phyAddr UINT8 [in] - the address of the Ethernet PHY (0-31)
- * @param phyReg UINT8 [in] -  the number of the MII register to read (0-31)
- * @param value UINT16 [in] -  the value read from the register
- *
- * @return IxEthAccStatus
- * @li @a IX_ETH_ACC_SUCCESS
- * @li @a IX_ETH_ACC_FAIL : failed to read the register.
- *
- * <hr>
- */
-PUBLIC IxEthAccStatus
-ixEthAccMiiReadRtn (UINT8 phyAddr, UINT8 phyReg, UINT16 *value);
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn ixEthAccMiiWriteRtn (UINT8 phyAddr, 
-                            UINT8 phyReg, 
-	                    UINT16 value)
- *
- *
- * @brief Writes a 16 bit value to a PHY
- *
- * Writes a 16-bit word from a register of a MII-compliant PHY. Writing
- * is performed through the MII management interface.  This function returns
- * when the write operation has successfully completed, or when a timeout has elapsed.
- *
- * @li Reentrant    - no
- * @li ISR Callable - no
- *
- * @pre The MAC on Ethernet Port 2 (NPE C) must be initialised, and generating the MDIO clock.
- *   
- * @param phyAddr UINT8 [in] - the address of the Ethernet PHY (0-31)
- * @param phyReg UINT8 [in] -  the number of the MII register to write (0-31)
- * @param value UINT16 [out] -  the value to write to the register
- *
- * @return IxEthAccStatus
- * @li @a IX_ETH_ACC_SUCCESS
- * @li @a IX_ETH_ACC_FAIL : failed to write register.
- *
- * <hr>
- */
-PUBLIC IxEthAccStatus
-ixEthAccMiiWriteRtn (UINT8 phyAddr, UINT8 phyReg, UINT16 value);
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn ixEthAccMiiAccessTimeoutSet(UINT32 timeout)
- *
- * @brief Overrides the default timeout value and retry count when reading or 
- * writing MII registers using ixEthAccMiiWriteRtn or ixEthAccMiiReadRtn
- *
- * The default behavior of the component is to use a IX_ETH_ACC_MII_10TH_SEC_IN_MILLIS ms
- * timeout (declared as 100 in IxEthAccMii_p.h) and a retry count of IX_ETH_ACC_MII_TIMEOUT_10TH_SECS
- * (declared as 5 in IxEthAccMii_p.h).
- *
- * The MII read and write functions will attempt to read the status of the register up
- * to the retry count times, delaying between each attempt with the timeout value.
- *
- * @li Reentrant    - no
- * @li ISR Callable - no
- *
- * @pre
- *
- * @param timeout UINT32 [in] - new timeout value, in milliseconds
- * @param timeout UINT32 [in] - new retry count (a minimum value of 1 must be used)
- *
- * @return IxEthAccStatus
- * @li @a IX_ETH_ACC_SUCCESS
- * @li @a IX_ETH_ACC_FAIL : invalid parameter(s)
- *
- * <hr>
- */
-PUBLIC IxEthAccStatus
-ixEthAccMiiAccessTimeoutSet(UINT32 timeout, UINT32 retryCount);
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn ixEthAccMiiStatsShow (UINT32 phyAddr)
- *
- *
- * @brief Displays detailed information on a specified PHY
- *
- * Displays the current values of the first eigth MII registers for a PHY, 
- *
- * @li Reentrant    - no
- * @li ISR Callable - no
- *
- * @pre The MAC on Ethernet Port 2 (NPE C) must be initialised, and 
- *      generating the MDIO clock.
- *   
- * @param phyAddr UINT32 [in] - the address of the Ethernet PHY (0-31)
- *
- * @return IxEthAccStatus
- * @li @a IX_ETH_ACC_SUCCESS
- * @li @a IX_ETH_ACC_FAIL : invalid arguments.
- *
- * <hr>
- */
-PUBLIC IxEthAccStatus ixEthAccMiiStatsShow (UINT32 phyAddr);
-
-
-
-/******* BOARD SPECIFIC DEPRECATED API *********/
-
-/* The following functions are high level functions which rely
- * on the properties and interface of some Ethernet PHYs. The
- * implementation is hardware specific and has been moved to 
- * the hardware-specific component IxEthMii.
- */
-
- #include "IxEthMii.h"
-
-/**
- * @ingroup IxEthAcc
- *
- * @def  ixEthAccMiiPhyScan
- *
- * @brief : deprecated API entry point. This definition 
- * ensures backward compatibility
- *
- * See @ref ixEthMiiPhyScan
- *
- * @note this feature is board specific
- *
- */
-#define ixEthAccMiiPhyScan(phyPresent) ixEthMiiPhyScan(phyPresent,IXP425_ETH_ACC_MII_MAX_ADDR)
-
-/**
- * @ingroup IxEthAcc
- *
- * @def ixEthAccMiiPhyConfig
- *
- * @brief : deprecated API entry point. This definition 
- * ensures backward compatibility
- *
- * See @ref ixEthMiiPhyConfig
- *
- * @note this feature is board specific
- */
-#define ixEthAccMiiPhyConfig(phyAddr,speed100,fullDuplex,autonegotiate) \
-           ixEthMiiPhyConfig(phyAddr,speed100,fullDuplex,autonegotiate)
-
-/**
- * @ingroup IxEthAcc
- *
- * @def ixEthAccMiiPhyReset
- *
- * @brief : deprecated API entry point. This definition 
- * ensures backward compatibility
- *
- * See @ref ixEthMiiPhyReset
- *
- * @note this feature is board specific
- */
-#define ixEthAccMiiPhyReset(phyAddr) \
-           ixEthMiiPhyReset(phyAddr)
-
-/**
- * @ingroup IxEthAcc
- *
- * @def ixEthAccMiiLinkStatus
- *
- * @brief : deprecated API entry point. This definition 
- * ensures backward compatibility
- *
- * See @ref ixEthMiiLinkStatus
- *
- * @note this feature is board specific
- */
-#define ixEthAccMiiLinkStatus(phyAddr,linkUp,speed100,fullDuplex,autoneg) \
-           ixEthMiiLinkStatus(phyAddr,linkUp,speed100,fullDuplex,autoneg)
-
-
-
-/**
- * @ingroup IxEthAcc
- *
- * @def ixEthAccMiiShow  
- *
- * @brief : deprecated API entry point. This definition 
- * ensures backward compatibility
- *
- * See @ref ixEthMiiPhyShow
- *
- * @note this feature is board specific
- */
-#define ixEthAccMiiShow(phyAddr) \
-        ixEthMiiPhyShow(phyAddr)
-
-#endif /* ndef IxEthAcc_H */
-/**
- *@}
- */
diff --git a/arch/arm/cpu/ixp/npe/include/IxEthAccDataPlane_p.h b/arch/arm/cpu/ixp/npe/include/IxEthAccDataPlane_p.h
deleted file mode 100644
index 8b8e6b2..0000000
--- a/arch/arm/cpu/ixp/npe/include/IxEthAccDataPlane_p.h
+++ /dev/null
@@ -1,245 +0,0 @@
-/**
- * @file IxEthAccDataPlane_p.h
- *
- * @author Intel Corporation
- * @date 12-Feb-2002
- *
- * @brief  Internal Header file for IXP425 Ethernet Access component.
- *
- * Design Notes:
- *
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- * 
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- * 
- * @par
- * -- End of Copyright Notice --
- */
-
-
-
-#ifndef IxEthAccDataPlane_p_H
-#define IxEthAccDataPlane_p_H
-
-#include <IxOsal.h>
-#include <IxQMgr.h>
-
-/**
- * @addtogroup IxEthAccPri
- *@{
- */
-
-/* typedefs global to this file*/
-
-typedef struct
-{
-    IX_OSAL_MBUF *pHead;
-    IX_OSAL_MBUF *pTail;
-}IxEthAccDataPlaneQList;
-
-
-/**
- * @struct  IxEthAccDataPlaneStats
- * @brief   Statistics data structure associated with the data plane
- *
- */
-typedef struct
-{
-    UINT32 addToSwQ;
-    UINT32 removeFromSwQ;
-    UINT32 unchainedTxMBufs;
-    UINT32 chainedTxMBufs;
-    UINT32 unchainedTxDoneMBufs;
-    UINT32 chainedTxDoneMBufs;
-    UINT32 unchainedRxMBufs;
-    UINT32 chainedRxMBufs;
-    UINT32 unchainedRxFreeMBufs;
-    UINT32 chainedRxFreeMBufs;
-    UINT32 rxCallbackCounter;
-    UINT32 rxCallbackBurstRead;
-    UINT32 txDoneCallbackCounter;
-    UINT32 unexpectedError;
-} IxEthAccDataPlaneStats;
-
-/**
- * @fn ixEthAccMbufFromSwQ
- * @brief  used during disable steps to convert mbufs from 
- *  swq format, ready to be pushed into hw queues for NPE, 
- *  back into XScale format 
- */
-IX_OSAL_MBUF *ixEthAccMbufFromSwQ(IX_OSAL_MBUF *mbuf);
-
-/**
- * @fn ixEthAccDataPlaneShow
- * @brief  Show function (for data plane statistics
- */
-void ixEthAccDataPlaneShow(void);
-
-/*
- * lock dataplane when atomic operation is required
- */
-#define IX_ETH_ACC_DATA_PLANE_LOCK(arg) arg = ixOsalIrqLock();
-#define IX_ETH_ACC_DATA_PLANE_UNLOCK(arg) ixOsalIrqUnlock(arg);
-
-/*
- * Use MBUF fields
- */
-#define IX_ETHACC_NE_SHARED(mBufPtr) \
- ((IxEthAccNe *)&((mBufPtr)->ix_ne))
-
-#if 1
-
-#define IX_ETHACC_NE_NEXT(mBufPtr) (mBufPtr)->ix_ne.reserved[0]
-
-/* tm - wrong!! len and pkt_len are in the second word - #define IX_ETHACC_NE_LEN(mBufPtr) (mBufPtr)->ix_ne.reserved[3] */
-#define IX_ETHACC_NE_LEN(mBufPtr) (mBufPtr)->ix_ne.reserved[1]
-
-#define IX_ETHACC_NE_DATA(mBufPtr)(mBufPtr)->ix_ne.reserved[2]
-
-#else
-
-#define IX_ETHACC_NE_NEXT(mBufPtr) \
-  IX_ETHACC_NE_SHARED(mBufPtr)->ixReserved_next
-
-#define IX_ETHACC_NE_LEN(mBufPtr) \
-  IX_ETHACC_NE_SHARED(mBufPtr)->ixReserved_lengths
-
-#define IX_ETHACC_NE_DATA(mBufPtr) \
-  IX_ETHACC_NE_SHARED(mBufPtr)->ixReserved_data
-#endif
-
-/*
- * Use MBUF  next pointer field to chain data.
- */
-#define IX_ETH_ACC_MBUF_NEXT_PKT_CHAIN_MEMBER(mbuf) (mbuf)->ix_ctrl.ix_chain
-
-
-
-#define IX_ETH_ACC_DATAPLANE_IS_Q_EMPTY(mbuf_list) ((mbuf_list.pHead) == NULL)
-    
-
-#define IX_ETH_ACC_DATAPLANE_ADD_MBUF_TO_Q_HEAD(mbuf_list,mbuf_to_add) 		\
-  do {										\
-    int lockVal;								\
-    IX_ETH_ACC_DATA_PLANE_LOCK(lockVal);                                    	\
-    IX_ETH_ACC_STATS_INC(ixEthAccDataStats.addToSwQ);                           \
-    if ( (mbuf_list.pHead) != NULL ) 						\
-    {										\
-      (IX_ETH_ACC_MBUF_NEXT_PKT_CHAIN_MEMBER((mbuf_to_add))) = (mbuf_list.pHead);\
-      (mbuf_list.pHead) = (mbuf_to_add);					\
-    } 										\
-    else {									\
-      (mbuf_list.pTail) = (mbuf_list.pHead) = (mbuf_to_add);			\
-      IX_ETH_ACC_MBUF_NEXT_PKT_CHAIN_MEMBER((mbuf_to_add)) = NULL;		\
-    } 										\
-    IX_ETH_ACC_DATA_PLANE_UNLOCK(lockVal);					\
-  } while(0)
-
-
-#define IX_ETH_ACC_DATAPLANE_ADD_MBUF_TO_Q_TAIL(mbuf_list,mbuf_to_add)   	\
-  do {										\
-    int lockVal;								\
-    IX_ETH_ACC_DATA_PLANE_LOCK(lockVal);                                    	\
-    IX_ETH_ACC_STATS_INC(ixEthAccDataStats.addToSwQ);                           \
-    if ( (mbuf_list.pHead) == NULL ) 						\
-    {										\
-      (mbuf_list.pHead) = mbuf_to_add;						\
-      IX_ETH_ACC_MBUF_NEXT_PKT_CHAIN_MEMBER((mbuf_to_add)) = NULL;		\
-    } 										\
-    else {									\
-      IX_ETH_ACC_MBUF_NEXT_PKT_CHAIN_MEMBER((mbuf_list.pTail)) = (mbuf_to_add);	\
-      IX_ETH_ACC_MBUF_NEXT_PKT_CHAIN_MEMBER((mbuf_to_add)) = NULL;		\
-    } 										\
-    (mbuf_list.pTail) = mbuf_to_add;						\
-    IX_ETH_ACC_DATA_PLANE_UNLOCK(lockVal);					\
-  } while (0)
-
-
-#define IX_ETH_ACC_DATAPLANE_REMOVE_MBUF_FROM_Q_HEAD(mbuf_list,mbuf_to_rem)   	\
-  do {										\
-    int lockVal;								\
-    IX_ETH_ACC_DATA_PLANE_LOCK(lockVal);                                    	\
-    if ( (mbuf_list.pHead) != NULL ) 						\
-    {										\
-      IX_ETH_ACC_STATS_INC(ixEthAccDataStats.removeFromSwQ);                    \
-      (mbuf_to_rem) = (mbuf_list.pHead) ;					\
-      (mbuf_list.pHead) = (IX_ETH_ACC_MBUF_NEXT_PKT_CHAIN_MEMBER((mbuf_to_rem)));\
-    } 										\
-    else {									\
-      (mbuf_to_rem) = NULL;							\
-    } 										\
-    IX_ETH_ACC_DATA_PLANE_UNLOCK(lockVal);					\
-  } while (0)
-
-
-/**
- * @brief message handler QManager entries for NPE id => port ID conversion (NPE_B => 0, NPE_C => 1)
- */
-#define IX_ETH_ACC_PORT_TO_NPE_ID(port) \
-   ixEthAccPortData[(port)].npeId
-
-#define IX_ETH_ACC_NPE_TO_PORT_ID(npe) ((npe == 0 ? 2 : (npe == 1 ? 0 : ( npe == 2 ? 1 : -1 ))))
-
-#define IX_ETH_ACC_PORT_TO_TX_Q_ID(port)  \
-   ixEthAccPortData[(port)].ixEthAccTxData.txQueue
-
-#define IX_ETH_ACC_PORT_TO_RX_FREE_Q_ID(port) \
-   ixEthAccPortData[(port)].ixEthAccRxData.rxFreeQueue
-
-#define IX_ETH_ACC_PORT_TO_TX_Q_SOURCE(port)    (port == IX_ETH_PORT_1 ? IX_ETH_ACC_TX_FRAME_ENET0_Q_SOURCE : (port == IX_ETH_PORT_2 ? IX_ETH_ACC_TX_FRAME_ENET1_Q_SOURCE : IX_ETH_ACC_TX_FRAME_ENET2_Q_SOURCE))
-
-#define IX_ETH_ACC_PORT_TO_RX_FREE_Q_SOURCE(port) (port == IX_ETH_PORT_1 ? IX_ETH_ACC_RX_FREE_BUFF_ENET0_Q_SOURCE : (port == IX_ETH_PORT_2 ? IX_ETH_ACC_RX_FREE_BUFF_ENET1_Q_SOURCE : IX_ETH_ACC_RX_FREE_BUFF_ENET2_Q_SOURCE ))
-
-/* Flush the mbufs chain and all data pointed to by the mbuf */
-
-#ifndef NDEBUG
-#define IX_ETH_ACC_STATS_INC(x) (x++)
-#else
-#define IX_ETH_ACC_STATS_INC(x)
-#endif
-
-#define IX_ETH_ACC_MAX_TX_FRAMES_TO_SUBMIT 128
-
-void ixEthRxFrameQMCallback(IxQMgrQId qId, IxQMgrCallbackId callbackId);
-void ixEthRxMultiBufferQMCallback(IxQMgrQId qId, IxQMgrCallbackId callbackId);
-void ixEthTxFrameDoneQMCallback(IxQMgrQId qId, IxQMgrCallbackId callbackId);
-
-#endif /* IxEthAccDataPlane_p_H */
-
-
-/**
- *@}
- */
-
diff --git a/arch/arm/cpu/ixp/npe/include/IxEthAccMac_p.h b/arch/arm/cpu/ixp/npe/include/IxEthAccMac_p.h
deleted file mode 100644
index 93e9d98..0000000
--- a/arch/arm/cpu/ixp/npe/include/IxEthAccMac_p.h
+++ /dev/null
@@ -1,248 +0,0 @@
-/*
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- * 
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- * 
- * @par
- * -- End of Copyright Notice --
-*/
-
-
-#ifndef IxEthAccMac_p_H
-#define IxEthAccMac_p_H
-
-#include "IxOsal.h"
-
-#define IX_ETH_ACC_MAX_MULTICAST_ADDRESSES 256
-#define IX_ETH_ACC_NUM_PORTS 3
-#define IX_ETH_ACC_MAX_FRAME_SIZE_DEFAULT 1536
-#define IX_ETH_ACC_MAX_FRAME_SIZE_UPPER_RANGE (65536-64)
-#define IX_ETH_ACC_MAX_FRAME_SIZE_LOWER_RANGE 64
-
-/*
- * 
- * MAC register definitions
- *
- */
-#define IX_ETH_ACC_MAC_0_BASE IX_OSAL_IXP400_ETHA_PHYS_BASE
-#define IX_ETH_ACC_MAC_1_BASE IX_OSAL_IXP400_ETHB_PHYS_BASE
-#define IX_ETH_ACC_MAC_2_BASE IX_OSAL_IXP400_ETH_NPEA_PHYS_BASE
-
-#define IX_ETH_ACC_MAC_TX_CNTRL1       0x000
-#define IX_ETH_ACC_MAC_TX_CNTRL2       0x004
-#define IX_ETH_ACC_MAC_RX_CNTRL1       0x010
-#define IX_ETH_ACC_MAC_RX_CNTRL2       0x014
-#define IX_ETH_ACC_MAC_RANDOM_SEED     0x020
-#define IX_ETH_ACC_MAC_THRESH_P_EMPTY  0x030
-#define IX_ETH_ACC_MAC_THRESH_P_FULL   0x038
-#define IX_ETH_ACC_MAC_BUF_SIZE_TX     0x040
-#define IX_ETH_ACC_MAC_TX_DEFER        0x050
-#define IX_ETH_ACC_MAC_RX_DEFER        0x054
-#define IX_ETH_ACC_MAC_TX_TWO_DEFER_1  0x060
-#define IX_ETH_ACC_MAC_TX_TWO_DEFER_2  0x064
-#define IX_ETH_ACC_MAC_SLOT_TIME       0x070
-#define IX_ETH_ACC_MAC_MDIO_CMD_1      0x080
-#define IX_ETH_ACC_MAC_MDIO_CMD_2      0x084
-#define IX_ETH_ACC_MAC_MDIO_CMD_3      0x088
-#define IX_ETH_ACC_MAC_MDIO_CMD_4      0x08c
-#define IX_ETH_ACC_MAC_MDIO_STS_1      0x090
-#define IX_ETH_ACC_MAC_MDIO_STS_2      0x094
-#define IX_ETH_ACC_MAC_MDIO_STS_3      0x098
-#define IX_ETH_ACC_MAC_MDIO_STS_4      0x09c
-#define IX_ETH_ACC_MAC_ADDR_MASK_1     0x0A0
-#define IX_ETH_ACC_MAC_ADDR_MASK_2     0x0A4
-#define IX_ETH_ACC_MAC_ADDR_MASK_3     0x0A8
-#define IX_ETH_ACC_MAC_ADDR_MASK_4     0x0AC
-#define IX_ETH_ACC_MAC_ADDR_MASK_5     0x0B0
-#define IX_ETH_ACC_MAC_ADDR_MASK_6     0x0B4
-#define IX_ETH_ACC_MAC_ADDR_1          0x0C0
-#define IX_ETH_ACC_MAC_ADDR_2          0x0C4
-#define IX_ETH_ACC_MAC_ADDR_3          0x0C8
-#define IX_ETH_ACC_MAC_ADDR_4          0x0CC
-#define IX_ETH_ACC_MAC_ADDR_5          0x0D0
-#define IX_ETH_ACC_MAC_ADDR_6          0x0D4
-#define IX_ETH_ACC_MAC_INT_CLK_THRESH  0x0E0
-#define IX_ETH_ACC_MAC_UNI_ADDR_1      0x0F0
-#define IX_ETH_ACC_MAC_UNI_ADDR_2      0x0F4
-#define IX_ETH_ACC_MAC_UNI_ADDR_3      0x0F8
-#define IX_ETH_ACC_MAC_UNI_ADDR_4      0x0FC
-#define IX_ETH_ACC_MAC_UNI_ADDR_5      0x100
-#define IX_ETH_ACC_MAC_UNI_ADDR_6      0x104
-#define IX_ETH_ACC_MAC_CORE_CNTRL      0x1FC
-
-
-/*
- *
- *Bit definitions
- *
- */
-
-/* TX Control Register 1*/
-
-#define IX_ETH_ACC_TX_CNTRL1_TX_EN         BIT(0)
-#define IX_ETH_ACC_TX_CNTRL1_DUPLEX        BIT(1)
-#define IX_ETH_ACC_TX_CNTRL1_RETRY         BIT(2)
-#define IX_ETH_ACC_TX_CNTRL1_PAD_EN        BIT(3)
-#define IX_ETH_ACC_TX_CNTRL1_FCS_EN        BIT(4)
-#define IX_ETH_ACC_TX_CNTRL1_2DEFER        BIT(5)
-#define IX_ETH_ACC_TX_CNTRL1_RMII          BIT(6)
-
-/* TX Control Register 2 */
-#define IX_ETH_ACC_TX_CNTRL2_RETRIES_MASK  0xf
-
-/* RX Control Register 1 */
-#define IX_ETH_ACC_RX_CNTRL1_RX_EN         BIT(0)
-#define IX_ETH_ACC_RX_CNTRL1_PADSTRIP_EN   BIT(1)
-#define IX_ETH_ACC_RX_CNTRL1_CRC_EN        BIT(2)
-#define IX_ETH_ACC_RX_CNTRL1_PAUSE_EN      BIT(3)
-#define IX_ETH_ACC_RX_CNTRL1_LOOP_EN       BIT(4)
-#define IX_ETH_ACC_RX_CNTRL1_ADDR_FLTR_EN  BIT(5)
-#define IX_ETH_ACC_RX_CNTRL1_RX_RUNT_EN    BIT(6)
-#define IX_ETH_ACC_RX_CNTRL1_BCAST_DIS     BIT(7)
-
-/* RX Control Register 2 */
-#define IX_ETH_ACC_RX_CNTRL2_DEFER_EN      BIT(0)
-
-
-
-/* Core Control Register */
-#define IX_ETH_ACC_CORE_RESET              BIT(0)
-#define IX_ETH_ACC_CORE_RX_FIFO_FLUSH      BIT(1)
-#define IX_ETH_ACC_CORE_TX_FIFO_FLUSH      BIT(2)
-#define IX_ETH_ACC_CORE_SEND_JAM           BIT(3)
-#define IX_ETH_ACC_CORE_MDC_EN             BIT(4)
-
-/* 1st bit of 1st MAC octet */
-#define IX_ETH_ACC_ETH_MAC_BCAST_MCAST_BIT ( 1) 
-
-
-/*
- *
- * Default values
- *
- */
-
-
-#define IX_ETH_ACC_TX_CNTRL1_DEFAULT  (IX_ETH_ACC_TX_CNTRL1_TX_EN | \
- IX_ETH_ACC_TX_CNTRL1_RETRY  | \
- IX_ETH_ACC_TX_CNTRL1_FCS_EN | \
- IX_ETH_ACC_TX_CNTRL1_2DEFER | \
- IX_ETH_ACC_TX_CNTRL1_PAD_EN)
-
-#define IX_ETH_ACC_TX_MAX_RETRIES_DEFAULT      0x0f 
-
-#define IX_ETH_ACC_RX_CNTRL1_DEFAULT    (IX_ETH_ACC_RX_CNTRL1_CRC_EN    \
-					 | IX_ETH_ACC_RX_CNTRL1_RX_EN)
-
-#define IX_ETH_ACC_RX_CNTRL2_DEFAULT           0x0
-
-/* Thresholds determined by NPE firmware FS */
-#define IX_ETH_ACC_MAC_THRESH_P_EMPTY_DEFAULT  0x12
-#define IX_ETH_ACC_MAC_THRESH_P_FULL_DEFAULT   0x30
-
-/* Number of bytes that must be in the tx fifo before
-   transmission commences*/
-#define IX_ETH_ACC_MAC_BUF_SIZE_TX_DEFAULT     0x8
-
-/* One-part deferral values */
-#define IX_ETH_ACC_MAC_TX_DEFER_DEFAULT        0x15
-#define IX_ETH_ACC_MAC_RX_DEFER_DEFAULT        0x16
-
-/* Two-part deferral values... */
-#define IX_ETH_ACC_MAC_TX_TWO_DEFER_1_DEFAULT  0x08
-#define IX_ETH_ACC_MAC_TX_TWO_DEFER_2_DEFAULT  0x07
-
-/* This value applies to MII */
-#define IX_ETH_ACC_MAC_SLOT_TIME_DEFAULT       0x80
-
-/* This value applies to RMII */
-#define IX_ETH_ACC_MAC_SLOT_TIME_RMII_DEFAULT  0xFF
-
-#define IX_ETH_ACC_MAC_ADDR_MASK_DEFAULT       0xFF
-
-#define IX_ETH_ACC_MAC_INT_CLK_THRESH_DEFAULT  0x1
-/*The following is a value chosen at random*/
-#define IX_ETH_ACC_RANDOM_SEED_DEFAULT         0x8
-
-/*By default we must configure the MAC to generate the 
-  MDC clock*/
-#define IX_ETH_ACC_CORE_DEFAULT                (IX_ETH_ACC_CORE_MDC_EN)
-
-#define IXP425_ETH_ACC_MAX_PHY 2
-#define IXP425_ETH_ACC_MAX_AN_ENTRIES 20
-#define IX_ETH_ACC_MAC_RESET_DELAY    1
-
-#define IX_ETH_ACC_MAC_ALL_BITS_SET   0xFF
-
-#define IX_ETH_ACC_MAC_MSGID_SHL      24
-
-#define IX_ETH_ACC_PORT_DISABLE_DELAY_MSECS 20
-#define IX_ETH_ACC_PORT_DISABLE_DELAY_COUNT 200  /* 4 seconds timeout */
-#define IX_ETH_ACC_PORT_DISABLE_RETRY_COUNT 3
-#define IX_ETH_ACC_MIB_STATS_DELAY_MSECS 2000 /* 2 seconds delay for ethernet stats */ 
-
-/*Register access macros*/
-#if  (CPU == SIMSPARCSOLARIS)
-extern void registerWriteStub (UINT32 base, UINT32 offset, UINT32 val);
-extern UINT32 registerReadStub (UINT32 base, UINT32 offset);
-
-#define REG_WRITE(b,o,v) registerWriteStub(b, o, v)
-#define REG_READ(b,o,v)  do { v = registerReadStub(b, o); } while (0)
-#else
-#define REG_WRITE(b,o,v) IX_OSAL_WRITE_LONG((volatile UINT32 *)(b + o), v)
-#define REG_READ(b,o,v)  (v = IX_OSAL_READ_LONG((volatile UINT32 *)(b + o)))
-
-#endif
-
-void ixEthAccMacUnload(void);
-IxEthAccStatus ixEthAccMacMemInit(void);
-
-/* MAC core loopback */
-IxEthAccStatus ixEthAccPortLoopbackEnable(IxEthAccPortId portId);
-IxEthAccStatus ixEthAccPortLoopbackDisable(IxEthAccPortId portId);
-
-/* MAC core traffic control */
-IxEthAccStatus ixEthAccPortTxEnablePriv(IxEthAccPortId portId);
-IxEthAccStatus ixEthAccPortTxDisablePriv(IxEthAccPortId portId);
-IxEthAccStatus ixEthAccPortRxEnablePriv(IxEthAccPortId portId);
-IxEthAccStatus ixEthAccPortRxDisablePriv(IxEthAccPortId portId);
-IxEthAccStatus ixEthAccPortMacResetPriv(IxEthAccPortId portId);
-
-/* NPE software loopback */
-IxEthAccStatus ixEthAccNpeLoopbackDisablePriv(IxEthAccPortId portId);
-IxEthAccStatus ixEthAccNpeLoopbackEnablePriv(IxEthAccPortId portId);
-
-#endif /*IxEthAccMac_p_H*/
-
diff --git a/arch/arm/cpu/ixp/npe/include/IxEthAccMii_p.h b/arch/arm/cpu/ixp/npe/include/IxEthAccMii_p.h
deleted file mode 100644
index 568d4a0..0000000
--- a/arch/arm/cpu/ixp/npe/include/IxEthAccMii_p.h
+++ /dev/null
@@ -1,97 +0,0 @@
-/**
- * @file IxEthAccMii_p.h
- *
- * @author Intel Corporation
- * @date 
- *
- * @brief  MII Header file
- *
- * Design Notes:
- *
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- * 
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- * 
- * @par
- * -- End of Copyright Notice --
- */
-
-#ifndef IxEthAccMii_p_H
-#define IxEthAccMii_p_H
-
-/* MII definitions - these have been verified against the LXT971 and LXT972 PHYs*/
-
-#define IXP425_ETH_ACC_MII_MAX_REG      32      /* max register per phy */
-
-#define IX_ETH_ACC_MII_REG_SHL    16
-#define IX_ETH_ACC_MII_ADDR_SHL   21
-
-/* Definitions for MII access routines*/
- 
-#define IX_ETH_ACC_MII_GO                  BIT(31)
-#define IX_ETH_ACC_MII_WRITE               BIT(26)
-#define IX_ETH_ACC_MII_TIMEOUT_10TH_SECS        5    
-#define IX_ETH_ACC_MII_10TH_SEC_IN_MILLIS     100
-#define IX_ETH_ACC_MII_READ_FAIL           BIT(31)
- 
-#define IX_ETH_ACC_MII_PHY_DEF_DELAY   300  /* max delay before link up, etc. */
-#define IX_ETH_ACC_MII_PHY_NO_DELAY    0x0  /* do not delay */
-#define IX_ETH_ACC_MII_PHY_NULL        0xff /* PHY is not present */
-#define IX_ETH_ACC_MII_PHY_DEF_ADDR    0x0  /* default PHY's logical address */
-
-#ifndef IX_ETH_ACC_MII_MONITOR_DELAY
-#   define IX_ETH_ACC_MII_MONITOR_DELAY   0x5    /* in seconds */
-#endif
-
-/* Register definition */  
-
-#define IX_ETH_ACC_MII_CTRL_REG	    0x0	/* Control Register */
-#define IX_ETH_ACC_MII_STAT_REG	    0x1	/* Status Register */
-#define IX_ETH_ACC_MII_PHY_ID1_REG  0x2	/* PHY identifier 1 Register */
-#define IX_ETH_ACC_MII_PHY_ID2_REG  0x3	/* PHY identifier 2 Register */
-#define IX_ETH_ACC_MII_AN_ADS_REG   0x4	/* Auto-Negotiation	  */
-					/* Advertisement Register */
-#define IX_ETH_ACC_MII_AN_PRTN_REG  0x5	/* Auto-Negotiation	    */
-					/* partner ability Register */
-#define IX_ETH_ACC_MII_AN_EXP_REG   0x6	/* Auto-Negotiation   */
-					/* Expansion Register */
-#define IX_ETH_ACC_MII_AN_NEXT_REG  0x7	/* Auto-Negotiation	       */
-					/* next-page transmit Register */
-
-IxEthAccStatus ixEthAccMdioShow (void);
-IxEthAccStatus ixEthAccMiiInit(void);
-void ixEthAccMiiUnload(void);
-
-#endif  /*IxEthAccMii_p_H*/
diff --git a/arch/arm/cpu/ixp/npe/include/IxEthAccQueueAssign_p.h b/arch/arm/cpu/ixp/npe/include/IxEthAccQueueAssign_p.h
deleted file mode 100644
index e5fd16e..0000000
--- a/arch/arm/cpu/ixp/npe/include/IxEthAccQueueAssign_p.h
+++ /dev/null
@@ -1,137 +0,0 @@
-/**
- * @file IxEthAccQueueAssign_p.h
- *
- * @author Intel Corporation
- * @date 06-Mar-2002
- *
- * @brief   Mapping from QMgr Q's to internal assignment
- *
- * Design Notes:
- *
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- * 
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- * 
- * @par
- * -- End of Copyright Notice --
- */
-
-/**
- * @addtogroup IxEthAccPri
- *@{
- */
-
-/*
- * Os/System dependancies.
- */
-#include "IxOsal.h"
-
-/*
- * Intermodule dependancies
- */
-#include "IxQMgr.h"
-#include "IxQueueAssignments.h"
-
-/* Check range of Q's assigned to this component. */
-#if IX_ETH_ACC_RX_FRAME_ETH_Q >= (IX_QMGR_MIN_QUEUPP_QID ) |    	\
- IX_ETH_ACC_RX_FREE_BUFF_ENET0_Q  >=  (IX_QMGR_MIN_QUEUPP_QID) | 	\
- IX_ETH_ACC_RX_FREE_BUFF_ENET1_Q  >=  (IX_QMGR_MIN_QUEUPP_QID) | 	\
- IX_ETH_ACC_TX_FRAME_ENET0_Q >=   (IX_QMGR_MIN_QUEUPP_QID) |  		\
- IX_ETH_ACC_TX_FRAME_ENET1_Q >=   (IX_QMGR_MIN_QUEUPP_QID) | 		\
- IX_ETH_ACC_TX_FRAME_DONE_ETH_Q  >=  (IX_QMGR_MIN_QUEUPP_QID)  
-#error "Not all Ethernet Access Queues are betweem 1-31, requires full functionalty Q's unless otherwise validated "
-#endif
-
-/**
-*
-* @typedef  IxEthAccQregInfo
-*
-* @brief 
-*
-*/
-typedef struct 
-{
-   IxQMgrQId qId;
-   char *qName;
-   IxQMgrCallback qCallback;
-   IxQMgrCallbackId callbackTag;
-   IxQMgrQSizeInWords qSize;
-   IxQMgrQEntrySizeInWords qWords; 
-   BOOL           qNotificationEnableAtStartup;
-   IxQMgrSourceId qConditionSource; 
-   IxQMgrWMLevel  AlmostEmptyThreshold;
-   IxQMgrWMLevel  AlmostFullThreshold;
-
-} IxEthAccQregInfo;
-
-/*
- * Prototypes for all QM callbacks.
- */
-
-/* 
- * Rx Callbacks 
- */
-IX_ETH_ACC_PUBLIC
-void  ixEthRxFrameQMCallback(IxQMgrQId, IxQMgrCallbackId);
-
-IX_ETH_ACC_PUBLIC
-void  ixEthRxMultiBufferQMCallback(IxQMgrQId, IxQMgrCallbackId);
-
-IX_ETH_ACC_PUBLIC
-void  ixEthRxFreeQMCallback(IxQMgrQId, IxQMgrCallbackId);
-
-/* 
- * Tx Callback.
- */
-IX_ETH_ACC_PUBLIC
-void  ixEthTxFrameQMCallback(IxQMgrQId, IxQMgrCallbackId);
-
-IX_ETH_ACC_PUBLIC
-void  ixEthTxFrameDoneQMCallback(IxQMgrQId, IxQMgrCallbackId );
-
-
-#define IX_ETH_ACC_QM_QUEUE_DISPATCH_PRIORITY (IX_QMGR_Q_PRIORITY_0) /* Highest priority */
-
-/*
- * Queue watermarks
- */
-#define IX_ETH_ACC_RX_FRAME_ETH_Q_SOURCE 		(IX_QMGR_Q_SOURCE_ID_NOT_E   )
-#define IX_ETH_ACC_RX_FREE_BUFF_ENET0_Q_SOURCE 		(IX_QMGR_Q_SOURCE_ID_E   )   
-#define IX_ETH_ACC_RX_FREE_BUFF_ENET1_Q_SOURCE 		(IX_QMGR_Q_SOURCE_ID_E   )
-#define IX_ETH_ACC_RX_FREE_BUFF_ENET2_Q_SOURCE 		(IX_QMGR_Q_SOURCE_ID_E   )
-#define IX_ETH_ACC_TX_FRAME_ENET0_Q_SOURCE 		(IX_QMGR_Q_SOURCE_ID_E   ) 
-#define IX_ETH_ACC_TX_FRAME_ENET1_Q_SOURCE 		(IX_QMGR_Q_SOURCE_ID_E   )
-#define IX_ETH_ACC_TX_FRAME_ENET2_Q_SOURCE 		(IX_QMGR_Q_SOURCE_ID_E   )
-#define IX_ETH_ACC_TX_FRAME_DONE_ETH_Q_SOURCE 		(IX_QMGR_Q_SOURCE_ID_NOT_E   )
diff --git a/arch/arm/cpu/ixp/npe/include/IxEthAcc_p.h b/arch/arm/cpu/ixp/npe/include/IxEthAcc_p.h
deleted file mode 100644
index 0ee4123..0000000
--- a/arch/arm/cpu/ixp/npe/include/IxEthAcc_p.h
+++ /dev/null
@@ -1,325 +0,0 @@
-/**
- * @file IxEthAcc_p.h
- *
- * @author Intel Corporation
- * @date 12-Feb-2002
- *
- * @brief  Internal Header file for IXP425 Ethernet Access component.
- *
- * Design Notes:
- *
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- * 
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- * 
- * @par
- * -- End of Copyright Notice --
- */
-
-/**
- * @addtogroup IxEthAccPri
- *@{
- */
-
-#ifndef IxEthAcc_p_H
-#define IxEthAcc_p_H
-
-/*
- * Os/System dependancies.
- */
-#include "IxOsal.h"
-
-/*
- * Intermodule dependancies
- */
-#include "IxNpeDl.h"
-#include "IxQMgr.h"
-
-#include "IxEthNpe.h"
-
-/* 
- * Intra module dependancies
- */
-
-#include "IxEthAccDataPlane_p.h"
-#include "IxEthAccMac_p.h"
-
-
-#define INLINE __inline__
-
-#ifdef NDEBUG
-
-#define IX_ETH_ACC_PRIVATE static
-
-#else
-
-#define IX_ETH_ACC_PRIVATE
-
-#endif /* ndef NDEBUG */
-
-#define IX_ETH_ACC_PUBLIC
-
-
-#define IX_ETH_ACC_IS_PORT_VALID(port) ((port) <  IX_ETH_ACC_NUMBER_OF_PORTS  ? TRUE : FALSE )
-
-
-
-#ifndef NDEBUG
-#define IX_ETH_ACC_FATAL_LOG(a,b,c,d,e,f,g)   { ixOsalLog ( IX_OSAL_LOG_LVL_FATAL,IX_OSAL_LOG_DEV_STDOUT,a,b,c,d,e,f,g);}
-#define IX_ETH_ACC_WARNING_LOG(a,b,c,d,e,f,g) { ixOsalLog ( IX_OSAL_LOG_LVL_WARNING,IX_OSAL_LOG_DEV_STDOUT,a,b,c,d,e,f,g);}
-#define IX_ETH_ACC_DEBUG_LOG(a,b,c,d,e,f,g)   { ixOsalLog ( IX_OSAL_LOG_LVL_FATAL,IX_OSAL_LOG_DEV_STDOUT,a,b,c,d,e,f,g);}
-#else
-#define IX_ETH_ACC_FATAL_LOG(a,b,c,d,e,f,g)   { ixOsalLog ( IX_OSAL_LOG_LVL_FATAL,IX_OSAL_LOG_DEV_STDOUT,a,b,c,d,e,f,g);}
-#define IX_ETH_ACC_WARNING_LOG(a,b,c,d,e,f,g) { ixOsalLog ( IX_OSAL_LOG_LVL_WARNING,IX_OSAL_LOG_DEV_STDOUT,a,b,c,d,e,f,g);}
-#define IX_ETH_ACC_DEBUG_LOG(a,b,c,d,e,f,g)   {}
-#endif
-
-IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccInitDataPlane(void);
-IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccQMgrQueuesConfig(void);
-IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccQMgrRxCallbacksRegister(IxQMgrCallback ixQMgrCallback);
-IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccSingleEthNpeCheck(IxEthAccPortId portId);
-IX_ETH_ACC_PUBLIC void ixEthAccQMgrRxQEntryGet(UINT32 *numRxQueueEntries);
-
-/* prototypes for the private control plane functions (used by the control interface wrapper) */
-IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortEnablePriv(IxEthAccPortId portId);
-IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortDisablePriv(IxEthAccPortId portId);
-IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortEnabledQueryPriv(IxEthAccPortId portId, BOOL *enabled);
-IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortPromiscuousModeClearPriv(IxEthAccPortId portId);
-IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortPromiscuousModeSetPriv(IxEthAccPortId portId);
-IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortUnicastMacAddressSetPriv(IxEthAccPortId portId, IxEthAccMacAddr *macAddr);
-IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortUnicastMacAddressGetPriv(IxEthAccPortId portId, IxEthAccMacAddr *macAddr);
-IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortMulticastAddressJoinPriv(IxEthAccPortId portId, IxEthAccMacAddr *macAddr);
-IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortMulticastAddressJoinAllPriv(IxEthAccPortId portId);
-IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortMulticastAddressLeavePriv(IxEthAccPortId portId, IxEthAccMacAddr *macAddr);
-IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortMulticastAddressLeaveAllPriv(IxEthAccPortId portId);
-IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortUnicastAddressShowPriv(IxEthAccPortId portId);
-IX_ETH_ACC_PUBLIC void ixEthAccPortMulticastAddressShowPriv(IxEthAccPortId portId);
-IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortDuplexModeSetPriv(IxEthAccPortId portId, IxEthAccDuplexMode mode);
-IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortDuplexModeGetPriv(IxEthAccPortId portId, IxEthAccDuplexMode *mode);
-IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortTxFrameAppendPaddingEnablePriv(IxEthAccPortId portId);
-IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortTxFrameAppendPaddingDisablePriv(IxEthAccPortId portId);
-IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortTxFrameAppendFCSEnablePriv(IxEthAccPortId portId);
-IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortTxFrameAppendFCSDisablePriv(IxEthAccPortId portId);
-IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortRxFrameAppendFCSEnablePriv(IxEthAccPortId portId);
-IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortRxFrameAppendFCSDisablePriv(IxEthAccPortId portId);
-IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccTxSchedulingDisciplineSetPriv(IxEthAccPortId portId, IxEthAccSchedulerDiscipline sched);
-IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccRxSchedulingDisciplineSetPriv(IxEthAccSchedulerDiscipline sched);
-
-/**
- * @struct  ixEthAccRxDataStats
- * @brief   Stats data structures for data path. - Not obtained from h/w
- *
- */
-typedef struct
-{ 
-    UINT32 rxFrameClientCallback;
-    UINT32 rxFreeRepOK;
-    UINT32 rxFreeRepDelayed;
-    UINT32 rxFreeRepFromSwQOK;
-    UINT32 rxFreeRepFromSwQDelayed;
-    UINT32 rxFreeLateNotificationEnabled;
-    UINT32 rxFreeLowCallback;
-    UINT32 rxFreeOverflow;
-    UINT32 rxFreeLock;
-    UINT32 rxDuringDisable;
-    UINT32 rxSwQDuringDisable;
-    UINT32 rxUnlearnedMacAddress;
-    UINT32 rxPriority[IX_ETH_ACC_TX_PRIORITY_7 + 1];
-    UINT32 rxUnexpectedError;
-    UINT32 rxFiltered;
-} IxEthAccRxDataStats;
-
-/**
- * @struct  IxEthAccTxDataStats
- * @brief   Stats data structures for data path. - Not obtained from h/w
- *
- */
-typedef struct
-{   
-    UINT32 txQOK;
-    UINT32 txQDelayed;
-    UINT32 txFromSwQOK;
-    UINT32 txFromSwQDelayed;
-    UINT32 txLowThreshCallback;
-    UINT32 txDoneClientCallback;
-    UINT32 txDoneClientCallbackDisable;
-    UINT32 txOverflow;
-    UINT32 txLock;
-    UINT32 txPriority[IX_ETH_ACC_TX_PRIORITY_7 + 1];
-    UINT32 txLateNotificationEnabled;
-    UINT32 txDoneDuringDisable;
-    UINT32 txDoneSwQDuringDisable;
-    UINT32 txUnexpectedError;
-} IxEthAccTxDataStats;
-
-/* port Disable state machine : list of states */
-typedef enum
-{
-    /* general port states */
-    DISABLED = 0,
-    ACTIVE,
-
-    /* particular Tx/Rx states */
-    REPLENISH,
-    RECEIVE,
-    TRANSMIT,
-    TRANSMIT_DONE
-} IxEthAccPortDisableState;
-
-typedef struct
-{
-    BOOL fullDuplex;
-    BOOL rxFCSAppend;
-    BOOL txFCSAppend;
-    BOOL txPADAppend;
-    BOOL enabled;
-    BOOL promiscuous;
-    BOOL joinAll;
-    IxOsalMutex ackMIBStatsLock;
-    IxOsalMutex ackMIBStatsResetLock;
-    IxOsalMutex MIBStatsGetAccessLock;
-    IxOsalMutex MIBStatsGetResetAccessLock;
-    IxOsalMutex npeLoopbackMessageLock;
-    IxEthAccMacAddr mcastAddrsTable[IX_ETH_ACC_MAX_MULTICAST_ADDRESSES];
-    UINT32 mcastAddrIndex;
-    IX_OSAL_MBUF *portDisableTxMbufPtr;
-    IX_OSAL_MBUF *portDisableRxMbufPtr;
-
-    volatile IxEthAccPortDisableState portDisableState;
-    volatile IxEthAccPortDisableState rxState;
-    volatile IxEthAccPortDisableState txState;
-
-    BOOL initDone;
-    BOOL macInitialised;
-} IxEthAccMacState;
-
-/**
- * @struct  IxEthAccRxInfo
- * @brief   System-wide data structures associated with the data plane.
- *
- */
-typedef struct
-{
-  IxQMgrQId higherPriorityQueue[IX_QMGR_MAX_NUM_QUEUES]; /**< higher priority queue list */
-  IxEthAccSchedulerDiscipline schDiscipline; /**< Receive Xscale QoS type */
-} IxEthAccInfo; 
-
-/**
- * @struct  IxEthAccRxDataInfo
- * @brief   Per Port data structures associated with the receive data plane.
- *
- */
-typedef struct
-{
-  IxQMgrQId rxFreeQueue; /**< rxFree Queue for this port */
-  IxEthAccPortRxCallback rxCallbackFn;
-  UINT32  rxCallbackTag;
-  IxEthAccDataPlaneQList freeBufferList;
-  IxEthAccPortMultiBufferRxCallback rxMultiBufferCallbackFn;
-  UINT32  rxMultiBufferCallbackTag;
-  BOOL rxMultiBufferCallbackInUse;
-  IxEthAccRxDataStats stats; /**< Receive s/w stats */
-} IxEthAccRxDataInfo; 
-
-/**
- * @struct  IxEthAccTxDataInfo
- * @brief   Per Port data structures associated with the transmit data plane.
- *
- */
-typedef struct
-{
-  IxEthAccPortTxDoneCallback  txBufferDoneCallbackFn;
-  UINT32  txCallbackTag;
-  IxEthAccDataPlaneQList	txQ[IX_ETH_ACC_NUM_TX_PRIORITIES]; /**< Transmit Q */
-  IxEthAccSchedulerDiscipline schDiscipline; /**< Transmit Xscale QoS */
-  IxQMgrQId txQueue; /**< txQueue for this port */
-  IxEthAccTxDataStats stats; /**< Transmit s/w stats */
-} IxEthAccTxDataInfo; 
-
-
-/**
- * @struct  IxEthAccPortDataInfo
- * @brief   Per Port data structures associated with the port data plane.
- *
- */
-typedef struct
-{
-    BOOL               portInitialized;
-    UINT32 npeId; /**< NpeId for this port */
-    IxEthAccTxDataInfo ixEthAccTxData; /**< Transmit data control structures */
-    IxEthAccRxDataInfo ixEthAccRxData; /**< Recieve data control structures */
-} IxEthAccPortDataInfo; 
-
-extern IxEthAccPortDataInfo  ixEthAccPortData[];
-#define IX_ETH_IS_PORT_INITIALIZED(port) (ixEthAccPortData[port].portInitialized)
-
-extern BOOL ixEthAccServiceInit;
-#define IX_ETH_ACC_IS_SERVICE_INITIALIZED() (ixEthAccServiceInit == TRUE )
-
-/* 
- * Maximum number of frames to consume from the Rx Frame Q.
- */
-
-#define IX_ETH_ACC_MAX_RX_FRAME_CONSUME_PER_CALLBACK (128)
-
-/*
- * Max number of times to load the Rx Free Q from callback.  
- */
-#define IX_ETH_ACC_MAX_RX_FREE_BUFFERS_LOAD (256)  /* Set greater than depth of h/w Q + drain time at line rate */
-
-/*
- *  Max number of times to read from the Tx Done Q in one sitting.
- */
-
-#define IX_ETH_ACC_MAX_TX_FRAME_DONE_CONSUME_PER_CALLBACK (256)
-
-/*
- *  Max number of times to take buffers from S/w queues and write them to the H/w Tx
- *  queues on receipt of a Tx low threshold callback 
- */
-
-#define IX_ETH_ACC_MAX_TX_FRAME_TX_CONSUME_PER_CALLBACK (16)
-
-
-#define IX_ETH_ACC_FLUSH_CACHE(addr,size)  IX_OSAL_CACHE_FLUSH((addr),(size))
-#define IX_ETH_ACC_INVALIDATE_CACHE(addr,size)  IX_OSAL_CACHE_INVALIDATE((addr),(size))
-
-
-#define IX_ETH_ACC_MEMSET(start,value,size) memset(start,value,size)
-
-#endif /* ndef IxEthAcc_p_H */
-
-
-
diff --git a/arch/arm/cpu/ixp/npe/include/IxEthDB.h b/arch/arm/cpu/ixp/npe/include/IxEthDB.h
deleted file mode 100644
index 1189c9a..0000000
--- a/arch/arm/cpu/ixp/npe/include/IxEthDB.h
+++ /dev/null
@@ -1,2373 +0,0 @@
-/** @file IxEthDB.h
- *
- * @brief this file contains the public API of @ref IxEthDB component
- *
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- * 
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- * 
- * @par
- * -- End of Copyright Notice --
- *
- */
- 
-#ifndef IxEthDB_H
-#define IxEthDB_H
-
-#include <IxOsBuffMgt.h>
-#include <IxTypes.h>
-
-/**
- * @defgroup IxEthDB IXP400 Ethernet Database (IxEthDB) API
- *
- * @brief ethDB is a library that does provides a MAC address database learning/filtering capability
- *
- *@{
- */
-
-#define INLINE __inline__
-
-#define IX_ETH_DB_PRIVATE PRIVATE /* imported from IxTypes.h */
-
-#define IX_ETH_DB_PUBLIC PUBLIC
-
-/**
- * @brief port ID => message handler NPE id conversion (0 => NPE_B, 1 => NPE_C)
- */
-#define IX_ETH_DB_PORT_ID_TO_NPE(id) (id == 0 ? 1 : (id == 1 ? 2 : (id == 2 ? 0 : -1)))
-
-/**
- * @def IX_ETH_DB_NPE_TO_PORT_ID(npe)
- * @brief message handler NPE id => port ID conversion (NPE_B => 0, NPE_C => 1)
- */
-#define IX_ETH_DB_NPE_TO_PORT_ID(npe) (npe == 0 ? 2 : (npe == 1 ? 0 : (npe == 2 ? 1 : -1)))
-
-/* temporary define - won't work for Azusa */
-#define IX_ETH_DB_PORT_ID_TO_NPE_LOGICAL_ID(id) (IX_ETH_DB_PORT_ID_TO_NPE(id) << 4)
-#define IX_ETH_DB_NPE_LOGICAL_ID_TO_PORT_ID(id) (IX_ETH_DB_NPE_TO_PORT_ID(id >> 4))
-
-/**
- * @def IX_IEEE803_MAC_ADDRESS_SIZE
- * @brief The size of the MAC address
- */
-#define IX_IEEE803_MAC_ADDRESS_SIZE (6)
-
-/**
- * @def IX_IEEE802_1Q_QOS_PRIORITY_COUNT
- * @brief Number of QoS priorities defined by IEEE802.1Q
- */
-#define IX_IEEE802_1Q_QOS_PRIORITY_COUNT (8)
-
-/**
- * @enum IxEthDBStatus
- * @brief Ethernet Database API return values
- */
-typedef enum /* IxEthDBStatus */
-{
-  IX_ETH_DB_SUCCESS = IX_SUCCESS,   /**< Success */
-  IX_ETH_DB_FAIL = IX_FAIL,         /**< Failure */
-  IX_ETH_DB_INVALID_PORT,           /**< Invalid port */
-  IX_ETH_DB_PORT_UNINITIALIZED,     /**< Port not initialized */
-  IX_ETH_DB_MAC_UNINITIALIZED,      /**< MAC not initialized */
-  IX_ETH_DB_INVALID_ARG,            /**< Invalid argument */
-  IX_ETH_DB_NO_SUCH_ADDR,           /**< Address not found for search or delete operations */
-  IX_ETH_DB_NOMEM,                  /**< Learning database memory full */
-  IX_ETH_DB_BUSY,                   /**< Learning database cannot complete operation, access temporarily blocked */
-  IX_ETH_DB_END,                    /**< Database browser passed the end of the record set */
-  IX_ETH_DB_INVALID_VLAN,           /**< Invalid VLAN ID (valid range is 0..4094, 0 signifies no VLAN membership, used for priority tagged frames) */
-  IX_ETH_DB_INVALID_PRIORITY,       /**< Invalid QoS priority/traffic class (valid range for QoS priority is 0..7, valid range for traffic class depends on run-time configuration) */
-  IX_ETH_DB_NO_PERMISSION,          /**< No permission for attempted operation */
-  IX_ETH_DB_FEATURE_UNAVAILABLE,    /**< Feature not available (or not enabled) */
-  IX_ETH_DB_INVALID_KEY,            /**< Invalid search key */
-  IX_ETH_DB_INVALID_RECORD_TYPE     /**< Invalid record type */
-} IxEthDBStatus;
-    
-/** @brief VLAN ID type, valid range is 0..4094, 0 signifying no VLAN membership */
-typedef UINT32 IxEthDBVlanId;
-
-/** @brief 802.1Q VLAN tag, contains 3 bits user priority, 1 bit CFI, 12 bits VLAN ID */
-typedef UINT32 IxEthDBVlanTag;
-
-/** @brief QoS priority/traffic class type, valid range is 0..7, 0 being the lowest */
-typedef UINT32 IxEthDBPriority;
-
-/** @brief Priority mapping table; 0..7 QoS priorities used to index, table contains traffic classes */
-typedef UINT8 IxEthDBPriorityTable[8];
-
-/** @brief A 4096 bit array used to map the complete VLAN ID range */
-typedef UINT8 IxEthDBVlanSet[512];
-
-#define IX_ETH_DB_802_1Q_VLAN_MASK (0xFFF)
-#define IX_ETH_DB_802_1Q_QOS_MASK  (0x7)
-
-#define IX_ETH_DB_802_1Q_MAX_VLAN_ID (0xFFE)
-
-/**
- * @def IX_ETH_DB_SET_VLAN_ID
- * @brief returns the given 802.1Q tag with the VLAN ID field substituted with the given VLAN ID
- *
- * This macro is used to change the VLAN ID in a 802.1Q tag.
- *
- * Example: 
- * 
- *  tag = IX_ETH_DB_SET_VLAN_ID(tag, 32)
- *
- * inserts the VLAN ID "32" in the given tag.
- */
-#define IX_ETH_DB_SET_VLAN_ID(vlanTag, vlanID) (((vlanTag) & 0xF000) | ((vlanID) & IX_ETH_DB_802_1Q_VLAN_MASK))
-
-/**
-* @def IX_ETH_DB_GET_VLAN_ID
-* @brief returns the VLAN ID from the given 802.1Q tag
-*/
-#define IX_ETH_DB_GET_VLAN_ID(vlanTag) ((vlanTag) & IX_ETH_DB_802_1Q_VLAN_MASK)
-
-#define IX_ETH_DB_GET_QOS_PRIORITY(vlanTag) (((vlanTag) >> 13) & IX_ETH_DB_802_1Q_QOS_MASK)
-
-#define IX_ETH_DB_SET_QOS_PRIORITY(vlanTag, priority) (((vlanTag) & 0x1FFF) | (((priority) & IX_ETH_DB_802_1Q_QOS_MASK) << 13))
-
-#define IX_ETH_DB_CHECK_VLAN_TAG(vlanTag) { if(((vlanTag & 0xFFFF0000) != 0) || (IX_ETH_DB_GET_VLAN_ID(vlanTag) > 4094)) return IX_ETH_DB_INVALID_VLAN; }
-
-#define IX_ETH_DB_CHECK_VLAN_ID(vlanId) { if (vlanId > IX_ETH_DB_802_1Q_MAX_VLAN_ID) return IX_ETH_DB_INVALID_VLAN; }
-
-#define IX_IEEE802_1Q_VLAN_TPID (0x8100)
-    
-typedef enum
-{
-  IX_ETH_DB_UNTAGGED_FRAMES        = 0x1, /**< Accepts untagged frames */
-  IX_ETH_DB_VLAN_TAGGED_FRAMES     = 0x2, /**< Accepts tagged frames */
-  IX_ETH_DB_PRIORITY_TAGGED_FRAMES = 0x4, /**< Accepts tagged frames with VLAN ID set to 0 (no VLAN membership) */
-  IX_ETH_DB_ACCEPT_ALL_FRAMES      = 
-      IX_ETH_DB_UNTAGGED_FRAMES | IX_ETH_DB_VLAN_TAGGED_FRAMES /**< Accepts all the frames */
-} IxEthDBFrameFilter;
-
-typedef enum
-{
-  IX_ETH_DB_PASS_THROUGH = 0x1, /**< Leave frame as-is */
-  IX_ETH_DB_ADD_TAG      = 0x2, /**< Add default port VLAN tag */
-  IX_ETH_DB_REMOVE_TAG   = 0x3  /**< Remove VLAN tag from frame */
-} IxEthDBTaggingAction;
-
-typedef enum
-{
-  IX_ETH_DB_FIREWALL_WHITE_LIST = 0x1,  /**< Firewall operates in white-list mode (MAC address based admission) */
-  IX_ETH_DB_FIREWALL_BLACK_LIST = 0x2   /**< Firewall operates in black-list mode (MAC address based blocking) */
-} IxEthDBFirewallMode;
-  
-typedef enum
-{
-  IX_ETH_DB_FILTERING_RECORD        = 0x01, /**< <table><caption> Filtering record </caption> 
-                                             *      <tr><td> MAC address <td> static/dynamic type <td> age 
-                                             *   </table> 
-                                             */
-  IX_ETH_DB_FILTERING_VLAN_RECORD   = 0x02, /**< <table><caption> VLAN-enabled filtering record </caption>
-                                             *      <tr><td> MAC address <td> static/dynamic type <td> age <td> 802.1Q tag 
-                                             *   </table> 
-                                             */
-  IX_ETH_DB_WIFI_RECORD             = 0x04, /**< <table><caption> WiFi header conversion record </caption>
-                                             *      <tr><td> MAC address <td> optional gateway MAC address <td> 
-                                             *   </table>
-                                             */
-  IX_ETH_DB_FIREWALL_RECORD         = 0x08, /**< <table><caption> Firewall record </caption>
-                                             *      <tr><td> MAC address 
-                                             *   </table>
-                                             */
-  IX_ETH_DB_GATEWAY_RECORD          = 0x10, /**< <i>For internal use only</i> */
-  IX_ETH_DB_MAX_RECORD_TYPE_INDEX   = 0x10, /**< <i>For internal use only</i> */
-  IX_ETH_DB_NO_RECORD_TYPE          = 0,    /**< None of the registered record types */
-  IX_ETH_DB_ALL_FILTERING_RECORDS   = IX_ETH_DB_FILTERING_RECORD | IX_ETH_DB_FILTERING_VLAN_RECORD, /**< All the filtering records */
-  IX_ETH_DB_ALL_RECORD_TYPES        = IX_ETH_DB_FILTERING_RECORD | IX_ETH_DB_FILTERING_VLAN_RECORD |
-      IX_ETH_DB_WIFI_RECORD | IX_ETH_DB_FIREWALL_RECORD /**< All the record types registered within EthDB */    
-} IxEthDBRecordType;
-  
-typedef enum
-{
-  IX_ETH_DB_LEARNING                = 0x01, /**< Learning feature; enables EthDB to learn MAC address (filtering) records, including 802.1Q enabled records */
-  IX_ETH_DB_FILTERING               = 0x02, /**< Filtering feature; enables EthDB to communicate with the NPEs for downloading filtering information in the NPEs; depends on the learning feature */
-  IX_ETH_DB_VLAN_QOS                = 0x04, /**< VLAN/QoS feature; enables EthDB to configure NPEs to operate in VLAN/QoS aware modes */
-  IX_ETH_DB_FIREWALL                = 0x08, /**< Firewall feature; enables EthDB to configure NPEs to operate in firewall mode, using white/black address lists */
-  IX_ETH_DB_SPANNING_TREE_PROTOCOL  = 0x10, /**< Spanning tree protocol feature; enables EthDB to configure the NPEs as STP nodes */
-  IX_ETH_DB_WIFI_HEADER_CONVERSION  = 0x20  /**< WiFi 802.3 to 802.11 header conversion feature; enables EthDB to handle WiFi conversion data */
-} IxEthDBFeature;
-  
-typedef UINT32 IxEthDBProperty;  /**< Property ID type */
-
-typedef enum
-{
-  IX_ETH_DB_INTEGER_PROPERTY  = 0x1, /**< 4 byte unsigned integer type */
-  IX_ETH_DB_STRING_PROPERTY   = 0x2, /**< NULL-terminated string type of maximum 255 characters (including the terminator) */
-  IX_ETH_DB_MAC_ADDR_PROPERTY = 0x3, /**< 6 byte MAC address type */
-  IX_ETH_DB_BOOL_PROPERTY     = 0x4  /**< 4 byte boolean type; can contain only TRUE and FALSE values */
-} IxEthDBPropertyType;
-
-/* list of supported properties for the IX_ETH_DB_VLAN_QOS feature */
-#define IX_ETH_DB_QOS_TRAFFIC_CLASS_COUNT_PROPERTY   (0x01)     /**< Property identifying number the supported number of traffic classes */
-#define IX_ETH_DB_QOS_TRAFFIC_CLASS_0_RX_QUEUE_PROPERTY (0x10)  /**< Rx queue assigned to traffic class 0 */
-#define IX_ETH_DB_QOS_TRAFFIC_CLASS_1_RX_QUEUE_PROPERTY (0x11)  /**< Rx queue assigned to traffic class 1 */
-#define IX_ETH_DB_QOS_TRAFFIC_CLASS_2_RX_QUEUE_PROPERTY (0x12)  /**< Rx queue assigned to traffic class 2 */
-#define IX_ETH_DB_QOS_TRAFFIC_CLASS_3_RX_QUEUE_PROPERTY (0x13)  /**< Rx queue assigned to traffic class 3 */
-#define IX_ETH_DB_QOS_TRAFFIC_CLASS_4_RX_QUEUE_PROPERTY (0x14)  /**< Rx queue assigned to traffic class 4 */
-#define IX_ETH_DB_QOS_TRAFFIC_CLASS_5_RX_QUEUE_PROPERTY (0x15)  /**< Rx queue assigned to traffic class 5 */
-#define IX_ETH_DB_QOS_TRAFFIC_CLASS_6_RX_QUEUE_PROPERTY (0x16)  /**< Rx queue assigned to traffic class 6 */
-#define IX_ETH_DB_QOS_TRAFFIC_CLASS_7_RX_QUEUE_PROPERTY (0x17)  /**< Rx queue assigned to traffic class 7 */
-
-/* private property used by EthAcc to indicate queue configuration complete */
-#define IX_ETH_DB_QOS_QUEUE_CONFIGURATION_COMPLETE (0x18)
-      
-/**
- *
- * @brief The IEEE 802.3 Ethernet MAC address structure.
- * 
- * The data should be packed with bytes xx:xx:xx:xx:xx:xx 
- *
- * @note The data must be packed in network byte order.
- */
-typedef struct  
-{
-   UINT8 macAddress[IX_IEEE803_MAC_ADDRESS_SIZE];
-} IxEthDBMacAddr;
-
-/**
- * @ingroup IxEthDB
- *
- * @brief Definition of an IXP400 port.
- */
-typedef UINT32 IxEthDBPortId;
-
-/**
- * @ingroup IxEthDB
- *
- * @brief Port dependency map definition
- */
-typedef UINT8 IxEthDBPortMap[32];
-    
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBInit(void)
- *
- * @brief Initializes the Ethernet learning/filtering database
- *
- * @note calling this function multiple times does not constitute an error;
- * redundant calls will be ignored, returning IX_ETH_DB_SUCCESS
- *
- * @retval IX_ETH_DB_SUCCESS initialization was successful
- * @retval IX_ETH_DB_FAIL initialization failed (OS error)
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBInit(void);
- 
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBUnload(void)
- *
- * @brief Stops and prepares the EthDB component for unloading.
- *
- * @retval IX_ETH_DB_SUCCESS de-initialization was successful
- * @retval IX_ETH_DB_BUSY de-initialization failed, ports must be disabled first
- * @retval IX_ETH_DB_FAIL de-initialization failed (OS error)
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBUnload(void);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn void ixEthDBPortInit(IxEthDBPortId portID)
- *
- * @brief Initializes a port
- *
- * This function is called automatically by the Ethernet Access
- * ixEthAccPortInit() routine for Ethernet NPE ports and should be manually
- * called for any user-defined port (any port that is not one of
- * the two Ethernet NPEs). 
- *
- * @param portID @ref IxEthDBPortId [in] - ID of the port to be initialized
- *
- * @see IxEthDBPortDefs.h for port definitions
- *
- * @note calling this function multiple times does not constitute an error;
- * redundant calls will be ignored
- */
-IX_ETH_DB_PUBLIC 
-void ixEthDBPortInit(IxEthDBPortId portID);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBPortEnable(IxEthDBPortId portID)
- *
- * @brief Enables a port
- *
- * This function is called automatically from the Ethernet Access component
- * ixEthAccPortEnable() routine for Ethernet NPE ports and should be manually
- * called for any user-defined port (any port that is not one of
- * the Ethernet NPEs). 
- *
- * @param portID @ref IxEthDBPortId [in] - ID of the port to enable processing on
- *
- * @retval IX_ETH_DB_SUCCESS if enabling is successful
- * @retval IX_ETH_DB_FAIL if the enabling was not successful due to
- * a message handler error
- * @retval IX_ETH_DB_MAC_UNINITIALIZED the MAC address of this port was
- * not initialized (only for Ethernet NPEs)
- * @retval IX_ETH_DB_INVALID_PORT if portID is invalid
- *
- * @pre ixEthDBPortAddressSet needs to be called prior to enabling the port events
- * for Ethernet NPEs
- *
- * @see ixEthDBPortAddressSet
- *
- * @see IxEthDBPortDefs.h for port definitions
- *
- * @note calling this function multiple times does not constitute an error;
- * redundant calls will be ignored
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBPortEnable(IxEthDBPortId portID);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBPortDisable(IxEthDBPortId portID)
- *
- * @brief Disables processing on a port
- *
- * This function is called automatically from the Ethernet Access component
- * ixEthAccPortDisable() routine for Ethernet NPE ports and should be manually
- * called for any user-defined port (any port that is not one of
- * the Ethernet NPEs).
- *
- * @note Calling ixEthAccPortDisable() will disable the respective Ethernet NPE.
- * After Ethernet NPEs are disabled they are stopped therefore
- * when re-enabled they need to be reset, downloaded with microcode and started.
- * For learning to restart working the user needs to call again 
- * ixEthAccPortUnicastMacAddressSet or ixEthDBUnicastAddressSet
- * with the respective port MAC address.
- * Residual MAC addresses learnt before the port was disabled are deleted as soon
- * as the port is disabled. This only applies to dynamic (learnt) entries, static
- * entries do not dissapear when the port is disabled.
- *
- * @param portID @ref IxEthDBPortId [in] - ID of the port to disable processing on
- *
- * @retval IX_ETH_DB_SUCCESS if disabling is successful
- * @retval IX_ETH_DB_FAIL if the disabling was not successful due to
- * a message handler error
- * @retval IX_ETH_DB_INVALID_PORT if portID is invalid
- *
- * @note calling this function multiple times after the first time completed successfully
- * does not constitute an error; redundant calls will be ignored and return IX_ETH_DB_SUCCESS
-*/
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBPortDisable(IxEthDBPortId portID);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBPortAddressSet(IxEthDBPortId portID, IxEthDBMacAddr *macAddr)
- *
- * @brief Sets the port MAC address
- *
- * This function is to be called from the Ethernet Access component top-level
- * ixEthDBUnicastAddressSet(). Event processing cannot be enabled for a port
- * until its MAC address has been set.
- *
- * @param portID @ref IxEthDBPortId [in] - ID of the port whose MAC address is set
- * @param macAddr @ref IxEthDBMacAddr [in] - port MAC address
- *
- * @retval IX_ETH_DB_SUCCESS MAC address was set successfully
- * @retval IX_ETH_DB_FAIL MAC address was not set due to a message handler failure
- * @retval IX_ETH_DB_INVALID_PORT if the port is not an Ethernet NPE
- *
- * @see IxEthDBPortDefs.h for port definitions
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBPortAddressSet(IxEthDBPortId portID, IxEthDBMacAddr *macAddr);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBFilteringPortMaximumFrameSizeSet(IxEthDBPortId portID, UINT32 maximumFrameSize)
- *
- * @brief Set the maximum frame size supported on the given port ID
- *
- * This functions set the maximum frame size supported on a specific port ID 
- * 
- * - Reentrant    - yes
- * - ISR Callable - no
- *
- * @param portID @ref IxEthDBPortId [in] - port ID to configure
- * @param maximumFrameSize UINT32 [in] - maximum frame size to configure
- *
- * @retval IX_ETH_DB_SUCCESS the port is configured
- * @retval IX_ETH_DB_PORT_UNINITIALIZED the port has not been initialized
- * @retval IX_ETH_DB_INVALID_PORT portID is invalid
- * @retval IX_ETH_DB_INVALID_ARG size parameter is out of range
- * @retval IX_ETH_DB_NO_PERMISSION selected port is not an Ethernet NPE
- * @retval IX_FAIL unknown OS or NPE communication error
- *
- * @note
- * This maximum frame size is used to filter the frames based on their
- * destination addresses and the capabilities of the destination port.
- * The mximum value that can be set for a NPE port is 16320.
- * (IX_ETHNPE_ACC_FRAME_LENGTH_MAX)
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBFilteringPortMaximumFrameSizeSet(IxEthDBPortId portID, UINT32 maximumFrameSize);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBFilteringStaticEntryProvision(IxEthDBPortId portID, IxEthDBMacAddr *macAddr)
- *
- * @brief Populate the Ethernet learning/filtering database with a static MAC address
- *
- * Populates the Ethernet learning/filtering database with a static MAC address. The entry will not be subject to aging.
- * If there is an entry (static or dynamic) with the corresponding MAC address on any port this entry will take precedence.
- * Any other entry with the same MAC address will be removed.
- *
- * - Reentrant    - yes
- * - ISR Callable - yes
- * 
- * @param portID @ref IxEthDBPortId [in] - port ID to add the static address to
- * @param macAddr @ref IxEthDBMacAddr [in] - static MAC address to add
- * 
- * @retval IX_ETH_DB_SUCCESS the add was successful
- * @retval IX_ETH_DB_FAIL failed to populate the database entry
- * @retval IX_ETH_DB_BUSY failed due to a temporary busy condition (i.e. lack of CPU cycles), try again later
- * @retval IX_ETH_DB_INVALID_PORT portID is invalid
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized
- * @retval IX_ETH_DB_INVALID_ARG invalid <i>macAddr</i> pointer argument
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE learning feature is disabled
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBFilteringStaticEntryProvision(IxEthDBPortId portID, IxEthDBMacAddr *macAddr);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBFilteringDynamicEntryProvision(IxEthDBPortId portID, IxEthDBMacAddr *macAddr)
- *
- * @brief Populate the Ethernet learning/filtering database with a dynamic MAC address
- *
- * Populates the Ethernet learning/filtering database with a dynamic MAC address. This entry will be subject to normal 
- * aging function, if aging is enabled on its port.
- * If there is an entry (static or dynamic) with the same MAC address on any port this entry will take precedence.
- * Any other entry with the same MAC address will be removed.
- *
- * - Reentrant    - yes
- * - ISR Callable - yes
- *
- * @param portID @ref IxEthDBPortId [in] - port ID to add the dynamic address to
- * @param macAddr @ref IxEthDBMacAddr [in] - static MAC address to add
- *
- * @retval IX_ETH_DB_SUCCESS the add was successful
- * @retval IX_ETH_DB_FAIL failed to populate the database entry
- * @retval IX_ETH_DB_BUSY failed due to a temporary busy condition (i.e. lack of CPU cycles), try again later
- * @retval IX_ETH_DB_INVALID_PORT portID is invalid
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized
- * @retval IX_ETH_DB_INVALID_ARG invalid <i>macAddr</i> pointer argument
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE learning feature is disabled
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBFilteringDynamicEntryProvision(IxEthDBPortId portID, IxEthDBMacAddr *macAddr);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBFilteringEntryDelete(IxEthDBMacAddr *macAddr)
- *
- * @brief Removes a MAC address entry from the Ethernet learning/filtering database
- *
- * @param macAddr IxEthDBMacAddr [in] - MAC address to remove
- *
- * - Reentrant    - yes
- * - ISR Callable - no
- *
- * @retval IX_ETH_DB_SUCCESS the removal was successful
- * @retval IX_ETH_DB_NO_SUCH_ADDR failed to remove the address (not in the database)
- * @retval IX_ETH_DB_INVALID_ARG invalid <i>macAddr</i> pointer argument
- * @retval IX_ETH_DB_BUSY failed due to a temporary busy condition (i.e. lack of CPU cycles), try again later
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBFilteringEntryDelete(IxEthDBMacAddr *macAddr);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBFilteringPortSearch(IxEthDBPortId portID, IxEthDBMacAddr *macAddr)
- *
- * @brief Search the Ethernet learning/filtering database for the given MAC address and port ID
- *
- * This functions searches the database for a specific port ID and MAC address. Both the port ID
- * and the MAC address have to match in order for the record to be reported as found.
- *
- * - Reentrant    - yes
- * - ISR Callable - no
- *
- * @param portID @ref IxEthDBPortId [in] - port ID to search for
- * @param macAddr @ref IxEthDBMacAddr [in] - MAC address to search for
- *
- * @retval IX_ETH_DB_SUCCESS the record exists in the database
- * @retval IX_ETH_DB_INVALID_ARG invalid macAddr pointer argument
- * @retval IX_ETH_DB_NO_SUCH_ADDR the record was not found in the database
- * @retval IX_ETH_DB_INVALID_PORT portID is invalid
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port ID is not initialized
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE learning feature is disabled
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBFilteringPortSearch(IxEthDBPortId portID, IxEthDBMacAddr *macAddr);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBFilteringDatabaseSearch(IxEthDBPortId *portID, IxEthDBMacAddr *macAddr)
- *
- * @brief Search the Ethernet learning/filtering database for a MAC address and return the port ID
- *
- * Searches the database for a MAC address. The function returns the portID for the 
- * MAC address record, if found. If no match is found the function returns IX_ETH_DB_NO_SUCH_ADDR. 
- * The portID is only valid if the function finds a match.
- *
- * - Reentrant    - yes
- * - ISR Callable - no
- *
- * @param portID @ref IxEthDBPortId [in] - port ID the address belongs to (populated only on a successful search)
- * @param macAddr @ref IxEthDBMacAddr [in] - MAC address to search for
- *
- * @retval IX_ETH_DB_SUCCESS the record exists in the database
- * @retval IX_ETH_DB_NO_SUCH_ADDR the record was not found in the database
- * @retval IX_ETH_DB_INVALID_ARG invalid macAddr or portID pointer argument(s)
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBFilteringDatabaseSearch(IxEthDBPortId *portID, IxEthDBMacAddr *macAddr);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBFilteringPortUpdatingSearch(IxEthDBPortId *portID, IxEthDBMacAddr *macAddr)
- *
- * @brief Search the filtering database for a MAC address, return the port ID and reset the record age
- *
- * Searches the database for a MAC address. The function returns the portID for the 
- * MAC address record and resets the entry age to 0, if found. 
- * If no match is found the function returns IX_ETH_DB_NO_SUCH_ADDR. 
- * The portID is only valid if the function finds a match.
- *
- * - Reentrant      - yes
- * - ISR Callable   - no
- *
- * @retval IX_ETH_DB_SUCCESS the MAC address was found
- * @retval IX_ETH_DB_NO_SUCH_ADDR the MAC address was not found
- * @retval IX_ETH_DB_INVALID_ARG invalid macAddr or portID pointer argument(s)
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBFilteringPortUpdatingSearch(IxEthDBPortId *portID, IxEthDBMacAddr *macAddr);
-
-/**
- * @ingroup IxEthDB
- *
- * @def IX_ETH_DB_MAINTENANCE_TIME
- *
- * @brief The @ref ixEthDBDatabaseMaintenance must be called by the user at a frequency of 
- * IX_ETH_DB_MAINTENANCE_TIME
- *
- */
-#define IX_ETH_DB_MAINTENANCE_TIME (1 * 60) /* 1 Minute */
-
-/**
- * @ingroup IxEthDB
- *
- * @def IX_ETH_DB_LEARNING_ENTRY_AGE_TIME
- *
- * @brief The define specifies the filtering database age entry time. Static entries older than
- * IX_ETH_DB_LEARNING_ENTRY_AGE_TIME +/- IX_ETH_DB_MAINTENANCE_TIME shall be removed.
- *
- */
-#define IX_ETH_DB_LEARNING_ENTRY_AGE_TIME (15 * 60 ) /* 15 Mins */
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBPortAgingDisable(IxEthDBPortId portID)
- *
- * @brief Disable the aging function for a specific port
- *
- * @param portID @ref IxEthDBPortId [in] - port ID to disable aging on
- *
- * - Reentrant    - yes
- * - ISR Callable - no
- *
- * @retval IX_ETH_DB_SUCCESS aging disabled successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is invalid
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port ID is not initialized
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE learning feature is disabled
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBPortAgingDisable(IxEthDBPortId portID);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBPortAgingEnable(IxEthDBPortId portID)
- *
- * @brief Enable the aging function for a specific port
- * 
- * Enables the aging of dynamic MAC address entries stored in the learning/filtering database
- * 
- * @note The aging function relies on the @ref ixEthDBDatabaseMaintenance being called with a period of 
- * @ref IX_ETH_DB_MAINTENANCE_TIME seconds.
- *
- * - Reentrant    - yes
- * - ISR Callable - no
- *
- * @param portID @ref IxEthDBPortId [in] - port ID to enable aging on
- *
- * @retval IX_ETH_DB_SUCCESS aging enabled successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is invalid
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port ID is not initialized
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE learning feature is disabled
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBPortAgingEnable(IxEthDBPortId portID);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn void ixEthDBDatabaseMaintenance(void)
- *
- * @brief Performs a maintenance operation on the Ethernet learning/filtering database
- * 
- * In order to perform a database maintenance this function must be called every
- * @ref IX_ETH_DB_MAINTENANCE_TIME seconds. It should be called regardless of whether learning is
- * enabled or not.
- *
- * - Reentrant    - no
- * - ISR Callable - no
- * 
- * @note this function call will be ignored if the learning feature is disabled
- */
-IX_ETH_DB_PUBLIC 
-void ixEthDBDatabaseMaintenance(void);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBFilteringDatabaseShow(IxEthDBPortId  portID)
- *
- * @brief This function displays the Mac Ethernet MAC address filtering tables.
- *
- * It displays the MAC address, port ID, entry type (dynamic/static),and age for 
- * the given port ID.
- *
- * - Reentrant    - no
- * - ISR Callable - no
- *
- * @param portID @ref IxEthDBPortId [in] - port ID to display the MAC address entries
- *
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is invalid
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port ID is not initialized
- * @retval IX_ETH_DB_FAIL record browser failed due to an internal busy or lock condition
- *
- * @note this function is deprecated and kept for compatibility reasons; use @ref ixEthDBFilteringDatabaseShowRecords instead
- * 
- * @see ixEthDBFilteringDatabaseShowRecords
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBFilteringDatabaseShow(IxEthDBPortId portID);
-
-/** 
- * @ingroup IxEthDB
- *
- * @fn void ixEthDBFilteringDatabaseShowAll(void)
- *
- * @brief Displays the MAC address recorded in the filtering database for all registered
- * ports (see IxEthDBPortDefs.h), grouped by port ID.
- *
- * - Reentrant    - no
- * - ISR Callable - no
- *
- * @retval void
- *
- * @note this function is deprecated and kept for compatibility reasons; use @ref ixEthDBFilteringDatabaseShowRecords instead
- * 
- * @see ixEthDBFilteringDatabaseShowRecords
- */
-IX_ETH_DB_PUBLIC 
-void ixEthDBFilteringDatabaseShowAll(void);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBFilteringDatabaseShowRecords(IxEthDBPortId portID, IxEthDBRecordType recordFilter)
- *
- * @brief This function displays per port database records, given a record type filter
- *
- * The supported record type filters are:
- * 
- * - IX_ETH_DB_FILTERING_RECORD - displays the non-VLAN filtering records (MAC address, age, static/dynamic)
- * - IX_ETH_DB_FILTERING_VLAN_RECORD - displays the VLAN filtering records (MAC address, age, static/dynamic, VLAN ID, CFI, QoS class)
- * - IX_ETH_DB_FILTERING_RECORD | IX_ETH_DB_FILTERING_VLAN_RECORD - displays the previous two types of records
- * - IX_ETH_DB_WIFI_RECORD - displays the WiFi header conversion records (MAC address, optional gateway MAC address) and WiFi header conversion parameters (BBSID, Duration/ID)
- * - IX_ETH_DB_FIREWALL_RECORD - displays the firewall MAC address table and firewall operating mode (white list/black list)
- * - IX_ETH_DB_ALL_RECORD_TYPES - displays all the record types
- * - IX_ETH_DB_NO_RECORD_TYPE - displays only the port status (no records are displayed)
- * 
- * Additionally, the status of each port will be displayed, containg the following information: type, capabilities, enabled status, 
- * aging enabled status, group membership and maximum frame size.
- *
- * The port ID can either be an actual port or IX_ETH_DB_ALL_PORTS, in which case the requested information
- * will be displayed for all the ports (grouped by port)
- *
- * - Reentrant    - no
- * - ISR Callable - no
- *
- * @param portID ID of the port to display information on (use IX_ETH_DB_ALL_PORTS for all the ports)
- * @param recordFilter record type filter
- *
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is invalid
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port ID is not initialized
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBFilteringDatabaseShowRecords(IxEthDBPortId portID, IxEthDBRecordType recordFilter);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBPortDependencyMapSet(IxEthDBPortId portID, IxEthDBPortMap dependencyPortMap)
- *
- * @brief Sets the dependency port map for a port
- *
- * @param portID ID of the port to set the dependency map to
- * @param dependencyPortMap new dependency map (as bitmap, each bit set indicates a port being included)
- *
- * This function is used to share filtering information between ports.
- * By adding a port into another port's dependency map the target port
- * filtering data will import the filtering data from the port it depends on.
- * Any changes to filtering data for a port - such as adding, updating or removing records -
- * will trigger updates in the filtering information for all the ports depending on
- * on the updated port.
- *
- * For example, if ports 2 and 3 are set in the port 0 dependency map the filtering
- * information for port 0 will also include the filtering information from ports 2 and 3.
- * Adding a record to port 2 will also trigger an update not only on port 2 but also on
- * port 0.
- *
- * The dependency map is a 256 bit array where each bit corresponds to a port corresponding to the
- * bit offset (bit 0 - port 0, bit 1 - port 1 etc). Setting a bit to 1 indicates that the corresponding
- * port is the port map. For example, a dependency port map of 0x14 consists in the ports with IDs 2 and 4.
- * Note that the last bit (offset 255) is reserved and should never be set (it will be automatically
- * cleared by the function).
- *
- * By default, each port has a dependency port map consisting only of itself, i.e. 
- *
- * @verbatim
-    IxEthDBPortMap portMap;
-    
-    // clear all ports from port map
-    memset(portMap, 0, sizeof (portMap)); 
-    
-    // include portID in port map 
-    portMap[portID / 8] = 1 << (portID % 8);
-   @endverbatim
- *
- * - Reentrant    - no
- * - ISR Callable - no
- *
- * @note Setting dependency maps is useful for NPE ports, which benefit from automatic updates
- * of filtering information. Setting dependency maps for user-defined ports is not an error
- * but will have no actual effect.
- * 
- * @note Including a port in its own dependency map is not compulsory, however note that
- * in this case updating the port will not trigger an update on the port itself, which 
- * might not be the intended behavior
- *
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized
- * @retval IX_ETH_DB_INVALID_ARG invalid <i>dependencyPortMap</i> pointer
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE Filtering is not available or not enabled for the port
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBPortDependencyMapSet(IxEthDBPortId portID, IxEthDBPortMap dependencyPortMap);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBPortDependencyMapGet(IxEthDBPortId portID, IxEthDBPortMap dependencyPortMap)
- *
- * @brief Retrieves the dependency port map for a port
- *
- * @param portID ID of the port to set the dependency map to
- * @param dependencyPortMap location where the port dependency map is to be copied
- *
- * This function will copy the port dependency map to a user specified location.
- *
- * - Reentrant    - no
- * - ISR Callable - no
- *
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized
- * @retval IX_ETH_DB_INVALID_ARG invalid <i>dependencyPortMap</i> pointer
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE Filtering is not available or not enabled for the port
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBPortDependencyMapGet(IxEthDBPortId portID, IxEthDBPortMap dependencyPortMap);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBPortVlanTagSet(IxEthDBPortId portID, IxEthDBVlanTag vlanTag)
- *
- * @brief Sets the default 802.1Q VLAN tag for a given port
- *
- * @param portID @ref IxEthDBPortId [in] - ID of the port to set the default VLAN tag to
- * @param vlanTag @ref IxEthDBVlanTag [in] - default 802.1Q VLAN tag
- *
- * The tag format has 16 bits and it is defined in the IEEE802.1Q specification.
- * This tag will be used for tagging untagged frames (if enabled) and classifying
- * unexpedited traffic into an internal traffic class (using the user priority field).
- *
- * <table border="1"> <caption> 802.1Q tag format </caption>
- *    <tr> <td>  <b> 3 bits   <td> <b> 1 bit <td> <b> 12 bits </b>
- *    <tr> <td> user priority <td>  CFI  <td>   VID
- * </table>
- *
- * User Priority : Defines user priority, giving eight (2^3) priority levels. IEEE 802.1P defines 
- * the operation for these 3 user priority bits
- * 
- * CFI : Canonical Format Indicator is always set to zero for Ethernet switches. CFI is used for 
- * compatibility reason between Ethernet type network and Token Ring type network. If a frame received 
- * at an Ethernet port has a CFI set to 1, then that frame should not be forwarded as it is to an untagged port. 
- *
- * VID : VLAN ID is the identification of the VLAN, which is basically used by the standard 802.1Q. 
- * It has 12 bits and allow the id entification of 4096 (2^12) VLANs. Of the 4096 possible VIDs, a VID of 0 
- * is used to identify priority frames and value 4095 (FFF) is reserved, so the maximum possible VLAN 
- * configurations are 4,094.
- * 
- * - Reentrant    - no
- * - ISR Callable - no
- *
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE VLAN/QoS feature is not available or not enabled for the port
- * @retval IX_ETH_DB_INVALID_VLAN <i>vlanTag</i> argument does not parse to a valid 802.1Q VLAN tag
- *
- * @note a VLAN ID value of 0 indicates that the port is not part of any VLAN
- * @note the value of the cannonical frame indicator (CFI) field is ignored, the 
- * field being used only in frame tagging operations
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBPortVlanTagSet(IxEthDBPortId portID, IxEthDBVlanTag vlanTag);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBPortVlanTagGet(IxEthDBPortId portID, IxEthDBVlanTag *vlanTag)
- *
- * @brief Retrieves the default 802.1Q port VLAN tag for a given port (see also @ref ixEthDBPortVlanTagSet)
- *
- * @param portID @ref IxEthDBPortId [in] - ID of the port to retrieve the default VLAN tag from
- * @param vlanTag @ref IxEthDBVlanTag [out] - location to write the default port 802.1Q VLAN tag to
- *
- * - Reentrant    - no
- * - ISR Callable - no
- *
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized
- * @retval IX_ETH_DB_INVALID_ARG invalid vlanTag pointer
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE VLAN/QoS feature is not available or not enabled for the port
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBPortVlanTagGet(IxEthDBPortId portID, IxEthDBVlanTag *vlanTag);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBVlanTagSet(IxEthDBMacAddr *macAddr, IxEthDBVlanTag vlanTag)
- *
- * @brief Sets the 802.1Q VLAN tag for a database record
- *
- * @param macAddr MAC address
- * @param vlanTag 802.1Q VLAN tag
- *
- * This function is used together with @ref ixEthDBVlanTagGet to provide MAC-based VLAN classification support.
- * Please note that the bridging application must contain specific code to make use of this feature (see below).
- * 
- * VLAN tags can be set only in IX_ETH_DB_FILTERING_RECORD or IX_ETH_DB_FILTERING_VLAN_RECORD type records.
- * If to an IX_ETH_DB_FILTERING_RECORD type record is added a VLAN tag the record type is automatically
- * changed to IX_ETH_DB_FILTERING_VLAN_RECORD. Once this has occurred the record type will never
- * revert to a non-VLAN type (unless deleted and re-added).
- *
- * Record types used for different purposes (such as IX_ETH_DB_WIFI_RECORD) will be ignored by
- * this function.
- *
- * After using this function to associate a VLAN ID with a MAC address the VLAN ID can be extracted knowing the
- * MAC address using @ref ixEthDBVlanTagGet. This mechanism can be used to implement MAC-based VLAN classification
- * if a bridging application searches for the VLAN tag when receiving a frame based on the source MAC address 
- * (contained in the <i>ixp_ne_src_mac</i> field of the buffer header).
- * If found in the database, the application can instruct the NPE to tag the frame by writing the VLAN tag
- * in the <i>ixp_ne_vlan_tci</i> field of the buffer header. This way the NPE will inspect the Egress tagging
- * rule associated with the given VLAN ID on the Tx port and tag the frame if Egress tagging on the VLAN is
- * allowed. Additionally, Egress tagging can be forced by setting the <i>ixp_ne_tx_flags.tag_over</i> and 
- * <i>ixp_ne_tx_flags.tag_mode</i> flags in the buffer header.
- *
- * - Reentrant    - no
- * - ISR Callable - no
- *
- * @note this function will <b>not</b> add a filtering record, it can only be used to update an existing one
- * 
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_ARG invalid <i>macAddr</i> pointer
- * @retval IX_ETH_DB_NO_SUCH_ADDR a filtering record with the specified MAC address was not found
- * @retval IX_ETH_DB_INVALID_VLAN <i>vlanTag</i> argument does not parse to a valid 802.1Q VLAN tag
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBVlanTagSet(IxEthDBMacAddr *macAddr, IxEthDBVlanTag vlanTag);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn ixEthDBVlanTagGet(IxEthDBMacAddr *macAddr, IxEthDBVlanTag *vlanTag)
- *
- * @brief Retrieves the 802.1Q VLAN tag from a database record given the record MAC address
- *
- * @param macAddr MAC address
- * @param vlanTag location to write the record 802.1Q VLAN tag to
- *
- * @note VLAN tags can be retrieved only from IX_ETH_DB_FILTERING_VLAN_RECORD type records
- * 
- * This function is used together with ixEthDBVlanTagSet to provide MAC-based VLAN classification support.
- * Please note that the bridging application must contain specific code to make use of this feature (see @ref ixEthDBVlanTagSet).
- *
- * - Reentrant    - no
- * - ISR Callable - no
- *
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_ARG invalid <i>macAddr</i> or <i>vlanTag</i> pointer
- * @retval IX_ETH_DB_NO_SUCH_ADDR a filtering record with the specified MAC address was not found
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBVlanTagGet(IxEthDBMacAddr *macAddr, IxEthDBVlanTag *vlanTag);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBPortVlanMembershipAdd(IxEthDBPortId portID, IxEthDBVlanId vlanID)
- *
- * @brief Adds a VLAN ID to a port's VLAN membership table
- *
- * Adding a VLAN ID to a port's VLAN membership table will cause frames tagged with the specified 
- * VLAN ID to be accepted by the frame filter, if Ingress VLAN membership filtering is enabled.
- * 
- * - Reentrant    - no
- * - ISR Callable - no
- *
- * @param portID @ref IxEthDBPortId [in] - ID of the port to add the VLAN ID membership to
- * @param vlanID @ref IxEthDBVlanId [in] - VLAN ID to be added to the port membership table
- *
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized
- * @retval IX_ETH_DB_INVALID_VLAN vlanID is not a valid VLAN ID
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE VLAN/QoS feature is not available or not enabled for the port
- * @retval IX_FAIL unknown OS or NPE communication error
- *
- * @note A port's default VLAN ID is always in its own membership table, hence there
- * is no need to explicitly add it using this function (although it is not an error
- * to do so)
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBPortVlanMembershipAdd(IxEthDBPortId portID, IxEthDBVlanId vlanID);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBPortVlanMembershipRangeAdd(IxEthDBPortId portID, IxEthDBVlanId vlanIDMin, IxEthDBVlanId vlanIDMax)
- *
- * @brief Adds a VLAN ID range to a port's VLAN membership table
- *
- * All the VLAN IDs in the specified range will be added to the port VLAN
- * membership table, including the range start and end VLAN IDs. Tagged frames with
- * VLAN IDs in the specified range will be accepted by the frame filter, if Ingress VLAN
- * membership filtering is enabled.
- *
- * - Reentrant    - no
- * - ISR Callable - no
- *
- * @param portID @ref IxEthDBPortId [in] - port ID to add the VLAN membership range into
- * @param vlanIDMin @ref IxEthDBVlanId [in] - start of the VLAN ID range
- * @param vlanIDMax @ref IxEthDBVlanId [in] - end of the VLAN ID range
- *
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized
- * @retval IX_ETH_DB_INVALID_VLAN the specified VLAN IDs are invalid or do not constitute a range
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE VLAN/QoS feature is not available or not enabled for the port
- * @retval IX_FAIL unknown OS or NPE communication error
- *
- * @note Is is valid to use the same VLAN ID for both vlanIDMin and vlanIDMax, in which case this
- * function will behave as @ref ixEthDBPortVlanMembershipAdd
- *
- * @note A port's default VLAN ID is always in its own membership table, hence there is no need
- * to explicitly add it using this function (although it is not an error to do so)
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBPortVlanMembershipRangeAdd(IxEthDBPortId portID, IxEthDBVlanId vlanIDMin, IxEthDBVlanId vlanIDMax);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBPortVlanMembershipRemove(IxEthDBPortId portID, IxEthDBVlanId vlanID)
- *
- * @brief Removes a VLAN ID from a port's VLAN membership table
- *
- * Frames tagged with a VLAN ID which is not in a port's VLAN membership table
- * will be discarded by the frame filter, if Ingress membership filtering is enabled.
- *
- * - Reentrant    - no
- * - ISR Callable - no
- *
- * @param portID @ref IxEthDBPortId [in] - ID of the port to remove the VLAN ID membership from
- * @param vlanID @ref IxEthDBVlanId [in] - VLAN ID to be removed from the port membership table
- *
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_INVALID_VLAN vlanID is not a valid VLAN ID
- * @retval IX_ETH_DB_NO_PERMISSION attempted to remove the default VLAN ID
- * from the port membership table (vlanID was set to the default port VLAN ID)
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE VLAN/QoS feature is not available or not enabled for the port
- * @retval IX_FAIL unknown OS or NPE communication error
- *
- * @note A port's default VLAN ID cannot be removed from the port's membership
- * table; attempting it will return IX_ETH_DB_NO_PERMISSION
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBPortVlanMembershipRemove(IxEthDBPortId portID, IxEthDBVlanId vlanID);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBPortVlanMembershipRangeRemove(IxEthDBPortId portID, IxEthDBVlanId vlanIDMin, IxEthDBVlanId vlanIDMax)
- *
- * @brief Removes a VLAN ID range from a port's VLAN membership table
- *
- * All the VLAN IDs in the specified range will be removed from the port VLAN
- * membership table, including the range start and end VLAN IDs. Tagged frames
- * with VLAN IDs in the range will be discarded by the frame filter, if Ingress
- * membership filtering is enabled.
- *
- * - Reentrant    - no
- * - ISR Callable - no
- *
- * @param portID @ref IxEthDBPortId [in] - ID of the port to remove the VLAN membership range from
- * @param vlanIDMin @ref IxEthDBVlanId [in] - start of the VLAN ID range
- * @param vlanIDMax @ref IxEthDBVlanId [in] - end of the VLAN ID range
- *
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized
- * @retval IX_ETH_DB_INVALID_VLAN the specified VLAN IDs are invalid or do not constitute a range
- * @retval IX_ETH_DB_NO_PERMISSION attempted to remove the default VLAN ID
- * from the port membership table (both vlanIDMin and vlanIDMax were set to the default port VLAN ID)
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE VLAN/QoS feature is not available or not enabled for the port
- * @retval IX_FAIL unknown OS or NPE communication error
- *
- * @note Is is valid to use the same VLAN ID for both vlanIDMin and vlanIDMax, in which case
- * function will behave as @ref ixEthDBPortVlanMembershipRemove
- *
- * @note If the given range overlaps the default port VLAN ID this function
- * will remove all the VLAN IDs in the range except for the port VLAN ID from its 
- * own membership table. This situation will be silently dealt with (no error message
- * will be returned) as long as the range contains more than one value (i.e. at least 
- * one other value, apart from the default port VLAN ID). If the function is called 
- * with the vlanIDMin and vlanIDMax parameters both set to the port default VLAN ID, the 
- * function will infer that an attempt was specifically made to remove the default port 
- * VLAN ID from the port membership table, in which case the return value will be 
- * IX_ETH_DB_NO_PERMISSION.
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBPortVlanMembershipRangeRemove(IxEthDBPortId portID, IxEthDBVlanId vlanIDMin, IxEthDBVlanId vlanIDMax);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBPortVlanMembershipSet(IxEthDBPortId portID, IxEthDBVlanSet vlanSet)
- *
- * @brief Sets a port's VLAN membership table
- *
- * Sets a port's VLAN membership table from a complete VLAN table containing all the possible
- * 4096 VLAN IDs. The table format is an array containing 4096 bits (512 bytes), where each bit
- * indicates whether the VLAN at that bit index is in the port's membership list (if set) or
- * not (unset).
- *
- * The bit at index 0, indicating VLAN ID 0, indicates no VLAN membership and therefore no
- * other bit must be set if bit 0 is set.
- *
- * The bit at index 4095 is reserved and should never be set (it will be ignored if set).
- *
- * The bit referencing the same VLAN ID as the default port VLAN ID should always be set, as 
- * the membership list must contain at least the default port VLAN ID.
- *
- * - Reentrant    - no
- * - ISR Callable - no
- *
- * @param portID @ref IxEthDBPortId [in] - port ID to set the VLAN membership table to
- * @param vlanSet @ref IxEthDBVlanSet [in] - pointer to the VLAN membership table
- * 
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized
- * @retval IX_ETH_DB_INVALID_ARG invalid <i>vlanSet</i> pointer
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE VLAN/QoS feature is not available or not enabled for the port
- * @retval IX_FAIL unknown OS or NPE communication error
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBPortVlanMembershipSet(IxEthDBPortId portID, IxEthDBVlanSet vlanSet);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBPortVlanMembershipGet(IxEthDBPortId portID, IxEthDBVlanSet vlanSet)
- *
- * @brief Retrieves a port's VLAN membership table
- *
- * Retrieves the complete VLAN membership table from a port, containing all the possible
- * 4096 VLAN IDs. The table format is an array containing 4096 bits (512 bytes), where each bit
- * indicates whether the VLAN at that bit index is in the port's membership list (if set) or
- * not (unset).
- *
- * The bit at index 0, indicating VLAN ID 0, indicates no VLAN membership and therefore no
- * other bit will be set if bit 0 is set.
- *
- * The bit at index 4095 is reserved and will not be set (it will be ignored if set).
- *
- * The bit referencing the same VLAN ID as the default port VLAN ID will always be set, as 
- * the membership list must contain at least the default port VLAN ID.
- *
- * - Reentrant    - no
- * - ISR Callable - no
- *
- * @param portID @ref IxEthDBPortId [in] - port ID to retrieve the VLAN membership table from
- * @param vlanSet @ref IxEthDBVlanSet [out] - pointer a location where the VLAN membership table will be
- *                written to 
- * 
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized
- * @retval IX_ETH_DB_INVALID_ARG invalid <i>vlanSet</i> pointer
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE VLAN/QoS feature is not available or not enabled for the port
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBPortVlanMembershipGet(IxEthDBPortId portID, IxEthDBVlanSet vlanSet);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBAcceptableFrameTypeSet(IxEthDBPortId portID, IxEthDBFrameFilter frameFilter)
- *
- * @brief Sets a port's acceptable frame type filter
- *
- * The acceptable frame type is one (or a combination) of the following values:
- *    - IX_ETH_DB_ACCEPT_ALL_FRAMES       - accepts all the frames
- *    - IX_ETH_DB_UNTAGGED_FRAMES         - accepts untagged frames
- *    - IX_ETH_DB_VLAN_TAGGED_FRAMES      - accepts tagged frames
- *    - IX_ETH_DB_PRIORITY_TAGGED_FRAMES  - accepts tagged frames with VLAN ID set to 0 (no VLAN membership)
- *
- * Except for using the exact values given above only the following combinations are valid:
- *    - IX_ETH_DB_UNTAGGED_FRAMES | IX_ETH_DB_VLAN_TAGGED_FRAMES
- *    - IX_ETH_DB_UNTAGGED_FRAMES | IX_ETH_DB_PRIORITY_TAGGED_FRAMES
- *
- * Please note that IX_ETH_DB_UNTAGGED_FRAMES | IX_ETH_DB_VLAN_TAGGED_FRAMES is equivalent
- * to IX_ETH_DB_ACCEPT_ALL_FRAMES.
- *
- * - Reentrant    - no
- * - ISR Callable - no
- *
- * @note by default the acceptable frame type filter is set to IX_ETH_DB_ACCEPT_ALL_FRAMES
- *
- * @note setting the acceptable frame type to PRIORITY_TAGGED_FRAMES is internally
- * accomplished by changing the frame filter to VLAN_TAGGED_FRAMES and setting the
- * VLAN membership list to include only VLAN ID 0; the membership list will need
- * to be restored manually to an appropriate value if the acceptable frame type
- * filter is changed back to ACCEPT_ALL_FRAMES or VLAN_TAGGED_FRAMES; failure to do so
- * will filter all VLAN traffic bar frames tagged with VLAN ID 0
- *
- * @param portID @ref IxEthDBPortId [in] - port ID to set the acceptable frame type filter to
- * @param frameFilter @ref IxEthDBFrameFilter [in] - acceptable frame type filter
- * 
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized
- * @retval IX_ETH_DB_INVALID_ARG invalid frame type filter
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE VLAN/QoS feature is not available or not enabled for the port
- * @retval IX_FAIL unknown OS or NPE communication error
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBAcceptableFrameTypeSet(IxEthDBPortId portID, IxEthDBFrameFilter frameFilter);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBAcceptableFrameTypeGet(IxEthDBPortId portID, IxEthDBFrameFilter *frameFilter)
- *
- * @brief Retrieves a port's acceptable frame type filter 
- *
- * For a description of the acceptable frame types see @ref ixEthDBAcceptableFrameTypeSet
- *
- * - Reentrant    - no
- * - ISR Callable - no
- *
- * @param portID @ref IxEthDBPortId [in] - port ID to retrieve the acceptable frame type filter from
- * @param frameFilter @ref IxEthDBFrameFilter [out] - location to store the acceptable frame type filter
- * 
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized
- * @retval IX_ETH_DB_INVALID_ARG invalid <i>frameFilter</i> pointer argument
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE VLAN/QoS feature is not available or not enabled for the port
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBAcceptableFrameTypeGet(IxEthDBPortId portID, IxEthDBFrameFilter *frameFilter);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBPriorityMappingTableSet(IxEthDBPortId portID, IxEthDBPriorityTable priorityTable)
- *
- * @brief Sets a port's priority mapping table
- *
- * The priority mapping table is an 8x2 table mapping a QoS (user) priority into an internal
- * traffic class. There are 8 valid QoS priorities (0..7, 0 being the lowest) which can be
- * mapped into one of the 4 available traffic classes (0..3, 0 being the lowest).
- * If a custom priority mapping table is not specified using this function the following
- * default priority table will be used (as per IEEE 802.1Q and IEEE 802.1D):
- * 
- * <table border="1"> <caption> QoS traffic classes  </caption>
- *    <tr> <td> <b> QoS priority <td> <b> Default traffic class <td> <b> Traffic type </b>
- *    <tr> <td>      0       <td>           1           <td> Best effort, default class for unexpedited traffic
- *    <tr> <td>      1       <td>           0           <td> Background traffic
- *    <tr> <td>      2       <td>           0           <td> Spare bandwidth
- *    <tr> <td>      3       <td>           1           <td> Excellent effort
- *    <tr> <td>      4       <td>           2           <td> Controlled load
- *    <tr> <td>      5       <td>           2           <td> Video traffic
- *    <tr> <td>      6       <td>           3           <td> Voice traffic
- *    <tr> <td>      7       <td>           3           <td> Network control
- * </table>
- *
- * - Reentrant    - no
- * - ISR Callable - no
- *
- * @param portID @ref IxEthDBPortId [in] - port ID of the port to set the priority mapping table to
- * @param priorityTable @ref IxEthDBPriorityTable [in] - location of the user priority table
- *
- * @note The provided table will be copied into internal data structures in EthDB and 
- * can be deallocated by the called after this function has completed its execution, if
- * so desired
- *
- * @warning The number of available traffic classes differs depending on the NPE images
- * and queue configuration. Check IxEthDBQoS.h for up-to-date information on the availability of
- * traffic classes. Note that specifiying a traffic class in the priority map which exceeds
- * the system availability will produce an IX_ETH_DB_INVALID_PRIORITY return error code and no
- * priority will be remapped.
- * 
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized
- * @retval IX_ETH_DB_INVALID_ARG invalid <i>priorityTable</i> pointer
- * @retval IX_ETH_DB_INVALID_PRIORITY at least one priority value exceeds
- * the current number of available traffic classes
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE VLAN/QoS feature is not available or not enabled for the port
- * @retval IX_FAIL unknown OS or NPE communication error
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBPriorityMappingTableSet(IxEthDBPortId portID, IxEthDBPriorityTable priorityTable);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBPriorityMappingTableGet(IxEthDBPortId portID, IxEthDBPriorityTable priorityTable)
- *
- * @brief Retrieves a port's priority mapping table
- *
- * The priority mapping table for the given port will be copied in the location
- * specified by the caller using "priorityTable"
- *
- * - Reentrant    - no
- * - ISR Callable - no
- *
- * @param portID ID @ref IxEthDBPortId [in] - of the port to retrieve the priority mapping table from
- * @param priorityTable @ref IxEthDBPriorityTable [out] - pointer to a user specified location where the table will be copied to
- *
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized
- * @retval IX_ETH_DB_INVALID_ARG invalid priorityTable pointer
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE VLAN/QoS feature is not available or not enabled for the port
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBPriorityMappingTableGet(IxEthDBPortId portID, IxEthDBPriorityTable priorityTable);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBPriorityMappingClassSet(IxEthDBPortId portID, IxEthDBPriority userPriority, IxEthDBPriority trafficClass)
- *
- * @brief Sets one QoS/user priority => traffic class mapping in a port's priority mapping table
- *
- * This function establishes a mapping between a user (QoS) priority and an internal traffic class.
- * The mapping will be saved in the port's priority mapping table. Use this function when not all
- * the QoS priorities need remapping (see also @ref ixEthDBPriorityMappingTableSet)
- *
- * - Reentrant    - no
- * - ISR Callable - no
- *
- * @param portID @ref IxEthDBPortId [in] - ID of the port to set the mapping to
- * @param userPriority @ref IxEthDBPriority [in] - user (QoS) priority, between 0 and 7 (0 being the lowest)
- * @param trafficClass @ref IxEthDBPriority [in] - internal traffic class, between 0 and 3 (0 being the lowest)
- *
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized
- * @retval IX_ETH_DB_INVALID_PRIORITY <i>userPriority</i> out of range or
- * <i>trafficClass</i> is beyond the number of currently available traffic classes
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE VLAN/QoS feature is not available or not enabled for the port
- * @retval IX_FAIL unknown OS or NPE communication error
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBPriorityMappingClassSet(IxEthDBPortId portID, IxEthDBPriority userPriority, IxEthDBPriority trafficClass);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBPriorityMappingClassGet(IxEthDBPortId portID, IxEthDBPriority userPriority, IxEthDBPriority *trafficClass)
- *
- * @brief Retrieves one QoS/user priority => traffic class mapping in a port's priority mapping table
- *
- * This function retrieves the internal traffic class associated with a QoS (user) priority from a given
- * port's priority mapping table. Use this function when not all the QoS priority mappings are 
- * required (see also @ref ixEthDBPriorityMappingTableGet)
- *
- * - Reentrant    - no
- * - ISR Callable - no
- *
- * @param portID @ref IxEthDBPortId [in] - ID of the port to set the mapping to
- * @param userPriority @ref IxEthDBPriority [in] - user (QoS) priority, between 0 and 7 (0 being the lowest)
- * @param trafficClass @ref IxEthDBPriority [out] - location to write the corresponding internal traffic class to
- *
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized
- * @retval IX_ETH_DB_INVALID_PRIORITY invalid userPriority value (out of range)
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE VLAN/QoS feature is not available or not enabled for the port
- * @retval IX_ETH_DB_INVALID_ARG invalid <i>trafficClass</i> pointer argument
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBPriorityMappingClassGet(IxEthDBPortId portID, IxEthDBPriority userPriority, IxEthDBPriority *trafficClass);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBEgressVlanEntryTaggingEnabledSet(IxEthDBPortId portID, IxEthDBVlanId vlanID, BOOL enabled)
- *
- * @brief Enables or disables Egress VLAN tagging for a port and a given VLAN
- *
- * This function enables or disables Egress VLAN tagging for the given port and VLAN ID.
- * If the VLAN tagging for a certain VLAN ID is enabled then all the frames to be
- * transmitted on the given port tagged with the same VLAN ID will be transmitted in a tagged format.
- * If tagging is not enabled for the given VLAN ID, the VLAN tag from the frames matching
- * this VLAN ID will be removed (the frames will be untagged).
- *
- * VLAN ID 4095 is reserved and should never be used with this function.
- * VLAN ID 0 has the special meaning of "No VLAN membership" and it is used in this
- * context to allow the port to send priority-tagged frames or not.
- *
- * By default, no Egress VLAN tagging is enabled on any port.
- *
- * - Reentrant    - no
- * - ISR Callable - no
- *
- * @param portID @ref IxEthDBPortId [in] - ID of the port to enable or disable the VLAN ID Egress tagging on
- * @param vlanID @ref IxEthDBVlanId [in] - VLAN ID to be matched against outgoing frames
- * @param enabled BOOL [in] - TRUE to enable Egress VLAN tagging on the port and given VLAN, and
- *                FALSE to disable Egress VLAN tagging
- *
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized
- * @retval IX_ETH_DB_INVALID_VLAN invalid VLAN ID (out of range)
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE VLAN/QoS feature is not available or not enabled for the port
- * @retval IX_FAIL unknown OS or NPE communication error
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBEgressVlanEntryTaggingEnabledSet(IxEthDBPortId portID, IxEthDBVlanId vlanID, BOOL enabled);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBEgressVlanEntryTaggingEnabledGet(IxEthDBPortId portID, IxEthDBVlanId vlanID, BOOL *enabled)
- *
- * @brief Retrieves the Egress VLAN tagging enabling status for a port and VLAN ID
- *
- * @param portID [in] - ID of the port to extract the Egress VLAN ID tagging status from
- * @param vlanID VLAN [in] - ID whose tagging status is to be extracted
- * @param enabled [in] - user-specifed location where the status is copied to; following
- * the successfull execution of this function the value will be TRUE if Egress VLAN 
- * tagging is enabled for the given port and VLAN ID, and FALSE otherwise                                                 
- *
- * - Reentrant    - no
- * - ISR Callable - no
- *
- * @see ixEthDBEgressVlanEntryTaggingEnabledGet
- *
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized
- * @retval IX_ETH_DB_INVALID_VLAN invalid VLAN ID (out of range)
- * @retval IX_ETH_DB_INVALID_ARG invalid <i>enabled</i> argument pointer
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE VLAN/QoS feature is not available or not enabled for the port
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBEgressVlanEntryTaggingEnabledGet(IxEthDBPortId portID, IxEthDBVlanId vlanID, BOOL *enabled);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBEgressVlanRangeTaggingEnabledSet(IxEthDBPortId portID, IxEthDBVlanId vlanIDMin, IxEthDBVlanId vlanIDMax, BOOL enabled)
- *
- * @brief Enables or disables Egress VLAN tagging for a port and given VLAN range
- *
- * This function is very similar to @ref ixEthDBEgressVlanEntryTaggingEnabledSet with the
- * difference that it can manipulate the Egress tagging status on multiple VLAN IDs,
- * defined by a contiguous range. Note that both limits in the range are explicitly 
- * included in the execution of this function.
- *
- * - Reentrant    - no
- * - ISR Callable - no
- *
- * @param portID @ref IxEthDBPortId [in] - ID of the port to enable or disable the VLAN ID Egress tagging on
- * @param vlanIDMin @ref IxEthDBVlanId [in] - start of the VLAN range to be matched against outgoing frames
- * @param vlanIDMax @ref IxEthDBVlanId [in] - end of the VLAN range to be matched against outgoing frames
- * @param enabled BOOL [in] - TRUE to enable Egress VLAN tagging on the port and given VLAN range,
- *                and FALSE to disable Egress VLAN tagging
- * 
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized
- * @retval IX_ETH_DB_INVALID_VLAN invalid VLAN ID (out of range), or do not constitute a range
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE VLAN/QoS feature is not available or not enabled for the port
- * @retval IX_ETH_DB_NO_PERMISSION attempted to explicitly remove the default port VLAN ID from the tagging table
- * @retval IX_FAIL unknown OS or NPE communication error
- *
- * @note Specifically removing the default port VLAN ID from the Egress tagging table by setting both vlanIDMin and vlanIDMax
- * to the VLAN ID portion of the PVID is not allowed by this function and will return IX_ETH_DB_NO_PERMISSION.
- * However, this can be circumvented, should the user specifically desire this, by either using a 
- * larger range (vlanIDMin < vlanIDMax) or by using ixEthDBEgressVlanEntryTaggingEnabledSet.
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBEgressVlanRangeTaggingEnabledSet(IxEthDBPortId portID, IxEthDBVlanId vlanIDMin, IxEthDBVlanId vlanIDMax, BOOL enabled);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBEgressVlanTaggingEnabledSet(IxEthDBPortId portID, IxEthDBVlanSet vlanSet)
- *
- * @brief Sets the complete Egress VLAN tagging table for a port
- *
- * This function is used to set the VLAN tagging/untagging per VLAN ID for a given port
- * covering the entire VLAN ID range (0..4094). The <i>vlanSet</i> parameter is a 4096
- * bit array, each bit indicating the Egress behavior for the corresponding VLAN ID.
- * If a bit is set then outgoing frames with the corresponding VLAN ID will be transmitted
- * with the VLAN tag, otherwise the frame will be transmitted without the VLAN tag.
- *
- * Bit 0 has a special significance, indicating tagging or tag removal for priority-tagged
- * frames.
- *
- * Bit 4095 is reserved and should never be set (it will be ignored if set).
- *
- * - Reentrant    - no
- * - ISR Callable - no
- *
- * @param portID @ref IxEthDBPortId [in] - ID of the port whose Egress VLAN tagging behavior is set
- * @param vlanSet @ref IxEthDBVlanSet [in] - 4096 bit array controlling per-VLAN tagging and untagging 
- *
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized
- * @retval IX_ETH_DB_INVALID_ARG invalid <i>vlanSet</i> pointer
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE VLAN/QoS feature is not available or not enabled for the port
- * @retval IX_FAIL unknown OS or NPE communication error
- *
- * @warning This function will automatically add the default port VLAN ID to the Egress tagging table
- * every time it is called. The user should manually call ixEthDBEgressVlanEntryTaggingEnabledSet to
- * prevent tagging on the default port VLAN ID if the default behavior is not intended.
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBEgressVlanTaggingEnabledSet(IxEthDBPortId portID, IxEthDBVlanSet vlanSet);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBEgressVlanTaggingEnabledGet(IxEthDBPortId portID, IxEthDBVlanSet vlanSet)
- *
- * @brief Retrieves the complete Egress VLAN tagging table from a port
- *
- * This function copies the 4096 bit table controlling the Egress VLAN tagging into a user specified
- * area. Each bit in the array indicates whether tagging for the corresponding VLAN (the bit position
- * in the array) is enabled (the bit is set) or not (the bit is unset). 
- *
- * Bit 4095 is reserved and should not be set (it will be ignored if set).
- *
- * @see ixEthDBEgressVlanTaggingEnabledSet
- *
- * @param portID @ref IxEthDBPortId [in] - ID of the port whose Egress VLAN tagging behavior is retrieved
- * @param vlanSet @ref IxEthDBVlanSet [out] - user location to copy the Egress tagging table into; should have
- * room to store 4096 bits (512 bytes)
- * 
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized
- * @retval IX_ETH_DB_INVALID_ARG invalid <i>vlanSet</i> pointer
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE VLAN/QoS feature is not available or not enabled for the port
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBEgressVlanTaggingEnabledGet(IxEthDBPortId portID, IxEthDBVlanSet vlanSet);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBIngressVlanTaggingEnabledSet(IxEthDBPortId portID, IxEthDBTaggingAction taggingAction)
- *
- * @brief Sets the Ingress VLAN tagging behavior for a port
- *
- * A port's Ingress tagging behavior is controlled by the taggingAction parameter,
- * which can take one of the following values:
- * 
- * - IX_ETH_DB_PASS_THROUGH - leaves the frame unchanged (does not add or remove the VLAN tag)
- * - IX_ETH_DB_ADD_TAG - adds the VLAN tag if not present, using the default port VID
- * - IX_ETH_DB_REMOVE_TAG - removes the VLAN tag if present
- * 
- * @param portID @ref IxEthDBPortId [in] - ID of the port whose Ingress VLAN tagging behavior is set
- * @param taggingAction @ref IxEthDBTaggingAction [in] - tagging behavior for the port
- * 
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized
- * @retval IX_ETH_DB_INVALID_ARG invalid <i>taggingAction</i> argument
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE VLAN/QoS feature is not available or not enabled for the port
- * @retval IX_FAIL unknown OS or NPE communication error
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBIngressVlanTaggingEnabledSet(IxEthDBPortId portID, IxEthDBTaggingAction taggingAction);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBIngressVlanTaggingEnabledGet(IxEthDBPortId portID, IxEthDBTaggingAction *taggingAction)
- *
- * @brief Retrieves the Ingress VLAN tagging behavior from a port (see @ref ixEthDBIngressVlanTaggingEnabledSet)
- *
- * @param portID @ref IxEthDBPortId [in] - ID of the port whose Ingress VLAN tagging behavior is set
- * @param taggingAction @ref IxEthDBTaggingAction [out] - location where the tagging behavior for the port is written to
- * 
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized
- * @retval IX_ETH_DB_INVALID_ARG invalid <i>taggingAction</i> pointer argument
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE VLAN/QoS feature is not available or not enabled for the port
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBIngressVlanTaggingEnabledGet(IxEthDBPortId portID, IxEthDBTaggingAction *taggingAction);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBVlanPortExtractionEnable(IxEthDBPortId portID, BOOL enable)
- *
- * @brief Enables or disables port ID extraction
- *
- * This feature can be used in the situation when a multi-port device (e.g. a switch) 
- * is connected to an IXP4xx port and the device can provide incoming frame port 
- * identification by tagging the TPID field in the Ethernet frame. Enabling
- * port extraction will instruct the NPE to copy the TPID field from the frame and 
- * place it in the <i>ixp_ne_src_port</i> of the <i>ixp_buf</i> header. In addition,
- * the NPE restores the TPID field to 0.
- *
- * If the frame is not tagged the NPE will fill the <i>ixp_ne_src_port</i> with the 
- * port ID of the MII interface the frame was received from.
- *
- * The TPID field is the least significant byte of the type/length field, which is 
- * normally set to 0x8100 for 802.1Q-tagged frames.
- *
- * This feature is disabled by default.
- *
- * @param portID ID of the port to configure port ID extraction on
- * @param enable TRUE to enable port ID extraction and FALSE to disable it
- * 
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE VLAN/QoS feature is not available or not enabled for the port
- * @retval IX_FAIL unknown OS or NPE communication error
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBVlanPortExtractionEnable(IxEthDBPortId portID, BOOL enable);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBFeatureCapabilityGet(IxEthDBPortId portID, IxEthDBFeature *featureSet)
- *
- * @brief Retrieves the feature capability set for a port
- *
- * This function retrieves the feature capability set for a port or the common capabilities shared between all 
- * the ports, writing the feature capability set in a user specified location.
- *
- * The feature capability set will consist of a set formed by OR-ing one or more of the following values:
- * - IX_ETH_DB_LEARNING - Learning feature; enables EthDB to learn MAC address (filtering) records, including 802.1Q enabled records
- * - IX_ETH_DB_FILTERING - Filtering feature; enables EthDB to communicate with the NPEs for downloading filtering information in the NPEs; depends on the learning feature
- * - IX_ETH_DB_VLAN_QOS - VLAN/QoS feature; enables EthDB to configure NPEs to operate in VLAN/QoS aware modes
- * - IX_ETH_DB_FIREWALL - Firewall feature; enables EthDB to configure NPEs to operate in firewall mode, using white/black address lists
- * - IX_ETH_DB_SPANNING_TREE_PROTOCOL - Spanning tree protocol feature; enables EthDB to configure the NPEs as STP nodes
- * - IX_ETH_DB_WIFI_HEADER_CONVERSION - WiFi 802.3 to 802.11 header conversion feature; enables EthDB to handle WiFi conversion data
- *
- * Note that EthDB provides only the LEARNING feature for non-NPE ports.
- * 
- * @param portID @ref IxEthDBPortId [in] - ID of the port to retrieve the capability set for 
- * (use IX_ETH_DB_ALL_PORTS to retrieve the common capabilities shared between all the ports)
- * @param featureSet @ref IxEthDBFeature [out] - location where the capability set will be written to
- * 
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized
- * @retval IX_ETH_DB_INVALID_ARG invalid <i>featureSet</i> pointer
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBFeatureCapabilityGet(IxEthDBPortId portID, IxEthDBFeature *featureSet);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBFeatureEnable(IxEthDBPortId portID, IxEthDBFeature feature, BOOL enabled)
- *
- * @brief Enables or disables one or more EthDB features
- *
- * Selects one or more features (see @ref ixEthDBFeatureCapabilityGet for a description of the supported
- * features) to be enabled or disabled on the selected port (or all the ports).
- *
- * Note that some features are mutually incompatible:
- * - IX_ETH_DB_FILTERING is incompatible with IX_ETH_DB_WIFI_HEADER_CONVERSION
- *
- * Also note that some features require other features to be enabled: 
- * - IX_ETH_DB_FILTERING requires IX_ETH_DB_LEARNING
- *
- * This function will either enable the entire selected feature set for the selected port (or all the ports),
- * in which case it will return IX_ETH_DB_SUCCESS, or in case of error it will not enable any feature at all
- * and return an appropriate error message.
- *
- * The following features are enabled by default (for ports with the respective capability), 
- * for compatibility reasons with previous versions of CSR:
- * - IX_ETH_DB_LEARNING
- * - IX_ETH_DB_FILTERING
- *
- * All other features are disabled by default and require manual enabling using ixEthDBFeatureEnable.
- *
- * <b>Default settings for VLAN, QoS, Firewall and WiFi header conversion features:</b>
- *
- * <i>VLAN</i>
- *
- * When the VLAN/QoS feature is enabled for a port for the first time the default VLAN behavior 
- * of the port is set to be as <b>permissive</b> (it will accept all the frames) and 
- * <b>non-interferential</b> (it will not change any frames) as possible:
- * - the port VLAN ID (VID) is set to 0
- * - the Ingress acceptable frame filter is set to accept all frames
- * - the VLAN port membership is set to the complete VLAN range (0 - 4094)
- * - the Ingress tagging mode is set to pass-through (will not change frames)
- * - the Egress tagging mode is to send tagged frames in the entire VLAN range (0 - 4094)
- *
- * Note that further disabling and re-enabling the VLAN feature for a given port will not reset the port VLAN behavior
- * to the settings listed above. Any VLAN settings made by the user are kept.
- *
- * <i>QoS</i>
- *
- * The following default priority mapping table will be used (as per IEEE 802.1Q and IEEE 802.1D):
- * 
- * <table border="1"> <caption> QoS traffic classes  </caption>
- *    <tr> <td> <b> QoS priority <td> <b> Default traffic class <td> <b> Traffic type </b>
- *    <tr> <td>      0       <td>           1           <td> Best effort, default class for unexpedited traffic
- *    <tr> <td>      1       <td>           0           <td> Background traffic
- *    <tr> <td>      2       <td>           0           <td> Spare bandwidth
- *    <tr> <td>      3       <td>           1           <td> Excellent effort
- *    <tr> <td>      4       <td>           2           <td> Controlled load
- *    <tr> <td>      5       <td>           2           <td> Video traffic
- *    <tr> <td>      6       <td>           3           <td> Voice traffic
- *    <tr> <td>      7       <td>           3           <td> Network control
- * </table>
- *
- * <i> Firewall </i>
- *  
- * The port firewall is configured by default in <b>black-list mode</b>, and the firewall address table is empty.
- * This means the firewall will not filter any frames until the feature is configured and the firewall table is
- * downloaded to the NPE.
- *
- * <i> Spanning Tree </i>
- *
- * The port is set to <b>STP unblocked mode</b>, therefore it will accept all frames until re-configured.
- *
- * <i> WiFi header conversion </i>
- *
- * The WiFi header conversion database is empty, therefore no actual header conversion will take place until this
- * feature is configured and the conversion table downloaded to the NPE.
- *
- * @param portID @ref IxEthDBPortId [in] - ID of the port to enable or disable the features on (use IX_ETH_DB_ALL_PORTS for all the ports)
- * @param feature @ref IxEthDBFeature [in] - feature or feature set to enable or disable
- * @param enabled BOOL [in] - TRUE to enable the feature and FALSE to disable it
- * 
- * @note Certain features, from a functional point of view, cannot be disabled as such at NPE level;
- * when such features are set to <i>disabled</i> using the EthDB API they will be configured in such
- * a way to determine a behavior equivalent to the feature being disabled. As well as this, disabled
- * features cannot be configured or accessed via the EthDB API (except for getting their status).
- *
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized
- * @retval IX_ETH_DB_NO_PERMISSION attempted to enable mutually exclusive features, 
- * or a feature that depends on another feature which is not present or enabled
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE at least one of the features selected is unavailable
- * @retval IX_FAIL unknown OS or NPE communication error
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBFeatureEnable(IxEthDBPortId portID, IxEthDBFeature feature, BOOL enabled);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBFeatureStatusGet(IxEthDBPortId portID, IxEthDBFeature feature, BOOL *present, BOOL *enabled)
- *
- * @brief Retrieves the availability and status of a feature set
- *
- * This function returns the availability and status for a feature set.
- * Note that if more than one feature is selected (e.g. IX_ETH_DB_LEARNING | IX_ETH_DB_FILTERING)
- * the "present" and "enabled" return values will be set to TRUE only if all the features in the 
- * feature set are present and enabled (not only some). 
- * 
- * @param portID @ref IxEthDBPortId [in] - ID of the port 
- * @param feature @ref IxEthDBFeature [in] - identifier of the feature to retrieve the status for
- * @param present BOOL [out] - location where a boolean flag indicating whether this feature is present will be written to
- * @param enabled BOOL [out] - location where a boolean flag indicating whether this feature is enabled will be written to
- * 
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized
- * @retval IX_ETH_DB_INVALID_ARG either <i>present</i> or <i>enabled</i> pointer argument is invalid
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBFeatureStatusGet(IxEthDBPortId portID, IxEthDBFeature feature, BOOL *present, BOOL *enabled);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBFeaturePropertyGet(IxEthDBPortId portID, IxEthDBFeature feature, IxEthDBProperty property, IxEthDBPropertyType *type, void *value)
- *
- * @brief Retrieves the value of a feature property
- *
- * The EthDB features usually contain feature-specific properties describing or
- * controlling how the feature operates. While essential properties (e.g. the
- * firewall operating mode) have their own API, secondary properties can be 
- * retrieved using this function.
- *
- * Properties can be read-only or read-write. ixEthDBFeaturePropertyGet operates with
- * both types of features.
- *
- * Properties have types associated with them. A descriptor indicating the property
- * type is returned in the <i>type</i> argument for convenience.
- *
- * The currently supported properties and their corresponding features are as follows:
- *
- * <table border="1"> <caption> Properties for IX_ETH_DB_VLAN_QOS </caption>
- *    <tr> <td> <b>        Property identifier                  <td> <b> Property type          <td> <b> Property value                   <td> <b> Read-Only </b>
- *    <tr> <td> IX_ETH_DB_QOS_TRAFFIC_CLASS_COUNT_PROPERTY      <td> IX_ETH_DB_INTEGER_PROPERTY <td> number of internal traffic classes   <td> Yes
- *    <tr> <td> IX_ETH_DB_QOS_TRAFFIC_CLASS_0_RX_QUEUE_PROPERTY <td> IX_ETH_DB_INTEGER_PROPERTY <td> queue assignment for traffic class 0 <td> Yes
- *    <tr> <td> IX_ETH_DB_QOS_TRAFFIC_CLASS_1_RX_QUEUE_PROPERTY <td> IX_ETH_DB_INTEGER_PROPERTY <td> queue assignment for traffic class 1 <td> Yes
- *    <tr> <td> IX_ETH_DB_QOS_TRAFFIC_CLASS_2_RX_QUEUE_PROPERTY <td> IX_ETH_DB_INTEGER_PROPERTY <td> queue assignment for traffic class 2 <td> Yes
- *    <tr> <td> IX_ETH_DB_QOS_TRAFFIC_CLASS_3_RX_QUEUE_PROPERTY <td> IX_ETH_DB_INTEGER_PROPERTY <td> queue assignment for traffic class 3 <td> Yes
- *    <tr> <td> IX_ETH_DB_QOS_TRAFFIC_CLASS_4_RX_QUEUE_PROPERTY <td> IX_ETH_DB_INTEGER_PROPERTY <td> queue assignment for traffic class 4 <td> Yes
- *    <tr> <td> IX_ETH_DB_QOS_TRAFFIC_CLASS_5_RX_QUEUE_PROPERTY <td> IX_ETH_DB_INTEGER_PROPERTY <td> queue assignment for traffic class 5 <td> Yes
- *    <tr> <td> IX_ETH_DB_QOS_TRAFFIC_CLASS_6_RX_QUEUE_PROPERTY <td> IX_ETH_DB_INTEGER_PROPERTY <td> queue assignment for traffic class 6 <td> Yes
- *    <tr> <td> IX_ETH_DB_QOS_TRAFFIC_CLASS_7_RX_QUEUE_PROPERTY <td> IX_ETH_DB_INTEGER_PROPERTY <td> queue assignment for traffic class 7 <td> Yes
- * </table>
- * 
- * @see ixEthDBFeaturePropertySet
- *
- * @param portID @ref IxEthDBPortId [in] - ID of the port 
- * @param feature @ref IxEthDBFeature [in] - EthDB feature for which the property is retrieved
- * @param property @ref IxEthDBProperty [in] - property identifier
- * @param type @ref IxEthDBPropertyType [out] - location where the property type will be stored
- * @param value void [out] - location where the property value will be stored
- * 
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_INVALID_ARG invalid property identifier, <i>type</i> or <i>value</i> pointer arguments
- * @retval IX_ETH_DB_FAIL incorrect property value or unknown error
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBFeaturePropertyGet(IxEthDBPortId portID, IxEthDBFeature feature, IxEthDBProperty property, IxEthDBPropertyType *type, void *value);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBFeaturePropertySet(IxEthDBPortId portID, IxEthDBFeature feature, IxEthDBProperty property, void *value)
- *
- * @brief Sets the value of a feature property
- *
- * Unlike @ref ixEthDBFeaturePropertyGet, this function operates only with read-write properties
- *
- * The currently supported properties and their corresponding features are as follows:
- *
- *   - IX_ETH_DB_QOS_QUEUE_CONFIGURATION_COMPLETE (for IX_ETH_DB_VLAN_QOS): freezes the availability of traffic classes
- *     to the number of traffic classes currently in use
- *
- * Note that this function creates deep copies of the property values; once the function is invoked the client 
- * can free or reuse the memory area containing the original property value.
- *
- * Copy behavior for different property types is defined as follows:
- *
- *   - IX_ETH_DB_INTEGER_PROPERTY   - 4 bytes are copied from the source location
- *   - IX_ETH_DB_STRING_PROPERTY    - the source string will be copied up to the NULL '\0' string terminator, maximum of 255 characters
- *   - IX_ETH_DB_MAC_ADDR_PROPERTY  - 6 bytes are copied from the source location
- *   - IX_ETH_DB_BOOL_PROPERTY      - 4 bytes are copied from the source location; the only allowed values are TRUE (1L) and false (0L)
- *
- * @see ixEthDBFeaturePropertySet
- *
- * @warning IX_ETH_DB_QOS_QUEUE_CONFIGURATION_COMPLETE is provided for EthAcc internal use; 
- * do not attempt to set this property directly
- *
- * @param portID @ref IxEthDBPortId [in] - ID of the port 
- * @param feature @ref IxEthDBFeature [in] - EthDB feature for which the property is set
- * @param property @ref IxEthDBProperty [in] - property identifier
- * @param value void [in] - location where the property value is to be copied from
- * 
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_INVALID_ARG invalid property identifier, <i>value</i> pointer, or invalid property value
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBFeaturePropertySet(IxEthDBPortId portID, IxEthDBFeature feature, IxEthDBProperty property, void *value);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBDatabaseClear(IxEthDBPortId portID, IxEthDBRecordType recordType)
- *
- * @brief Deletes a set of record types from the Ethernet Database
- *
- * This function deletes all the records of certain types (specified in the recordType filter)
- * associated with a port. Additionally, the IX_ETH_DB_ALL_PORTS value can be used as port ID
- * to indicate that the specified record types should be deleted for all the ports.
- *
- * The record type filter can be an ORed combination of the following types:
- *
- * <caption> Record types </caption>
- *    - IX_ETH_DB_FILTERING_RECORD      <table><caption> Filtering record </caption>
- *                                               <tr><td> MAC address <td> static/dynamic type <td> age </tr>
- *                                             </table> 
- *
- *    - IX_ETH_DB_FILTERING_VLAN_RECORD <table><caption> VLAN-enabled filtering record </caption>
- *                                               <tr><td> MAC address <td> static/dynamic type <td> age <td> 802.1Q tag </tr>
- *                                             </table> 
- *
- *    - IX_ETH_DB_WIFI_RECORD           <table><caption> WiFi header conversion record </caption>
- *                                                <tr><td> MAC address <td> optional gateway MAC address <td> </tr>
- *                                             </table>
- *
- *    - IX_ETH_DB_FIREWALL_RECORD       <table><caption> Firewall record </caption>
- *                                                <tr><td> MAC address </tr>
- *                                             </table>
- *    - IX_ETH_DB_ALL_RECORD_TYPES
- * 
- * Any combination of the above types is valid e.g. 
- *
- *    (IX_ETH_DB_FILTERING_RECORD | IX_ETH_DB_FILTERING_VLAN_RECORD | IX_ETH_DB_FIREWALL_RECORD), 
- *
- * although some might be redundant (it is not an error to do so) e.g.
- *
- *    (IX_ETH_DB_FILTERING_RECORD | IX_ETH_DB_ALL_RECORD_TYPES)
- *
- * @param portID @ref IxEthDBPortId [in] - ID of the port
- * @param recordType @ref IxEthDBRecordType [in] - record type filter
- * 
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_INVALID_ARG invalid <i>recordType</i> filter
- *
- * @note If the record type filter contains any unrecognized value (hence the 
- * IX_ETH_DB_INVALID_ARG error value is returned) no actual records will be deleted.
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBDatabaseClear(IxEthDBPortId portID, IxEthDBRecordType recordType);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBWiFiStationEntryAdd(IxEthDBPortId portID, IxEthDBMacAddr *macAddr)
- *
- * @brief Adds an "Access Point to Station" record to the database, for 802.3 => 802.11 frame 
- * header conversion
- *
- * Frame header conversion is controlled by the set of MAC addresses
- * added using @ref ixEthDBWiFiStationEntryAdd and @ref ixEthDBWiFiAccessPointEntryAdd.
- * Conversion arguments are added using @ref ixEthDBWiFiFrameControlSet, 
- * @ref ixEthDBWiFiDurationIDSet and @ref ixEthDBWiFiBBSIDSet.
- *
- * Note that adding the same MAC address twice will not return an error
- * (but will not accomplish anything either), while re-adding a record previously added
- * as an "Access Point to Access Point" will migrate the record to the "Access Point
- * to Station" type.
- *
- * @param portID @ref IxEthDBPortId [in] - ID of the port 
- * @param macAddr @ref IxEthDBMacAddr [in] - MAC address to add
- * 
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_INVALID_ARG macAddr is an invalid pointer
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE WiFi feature not enabled 
- * @retval IX_ETH_DB_INVALID_ARG invalid <i>macAddr</i> pointer argument
- * @retval IX_ETH_DB_NOMEM maximum number of records reached
- * @retval IX_ETH_DB_BUSY lock condition or transaction in progress, try again later
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBWiFiStationEntryAdd(IxEthDBPortId portID, IxEthDBMacAddr *macAddr);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBWiFiAccessPointEntryAdd(IxEthDBPortId portID, IxEthDBMacAddr *macAddr, IxEthDBMacAddr *gatewayMacAddr)
- *
- * @brief Adds an "Access Point to Access Point" record to the database
- *
- * @see ixEthDBWiFiStationEntryAdd
- *
- * Note that adding the same MAC address twice will simply overwrite the previously
- * defined gateway MAC address value in the same record, if the record was previously of the
- * "Access Point to Access Point" type.
- *
- * Re-adding a MAC address as "Access Point to Access Point", which was previously added as 
- * "Access Point to Station" will migrate the record type to "Access Point to Access Point" and
- * record the gateway MAC address.
- *
- * @param portID @ref IxEthDBPortId [in] - ID of the port 
- * @param macAddr @ref IxEthDBMacAddr [in] - MAC address to add
- * @param gatewayMacAddr @ref IxEthDBMacAddr [in] - MAC address of the gateway Access Point
- * 
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized
- * @retval IX_ETH_DB_INVALID_ARG macAddr is an invalid pointer
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE WiFi feature not enabled 
- * @retval IX_ETH_DB_INVALID_ARG invalid <i>macAddr</i> or <i>gatewayMacAddr</i> pointer argument
- * @retval IX_ETH_DB_NOMEM maximum number of records reached
- * @retval IX_ETH_DB_BUSY lock condition or transaction in progress, try again later
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBWiFiAccessPointEntryAdd(IxEthDBPortId portID, IxEthDBMacAddr *macAddr, IxEthDBMacAddr *gatewayMacAddr);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBWiFiEntryRemove(IxEthDBPortId portID, IxEthDBMacAddr *macAddr)
- *
- * @brief Removes a WiFi station record
- *
- * This function removes both types of WiFi records ("Access Point to Station" and
- * "Access Point to Access Point").
- * 
- * @param portID @ref IxEthDBPortId [in] - ID of the port 
- * @param macAddr @ref IxEthDBMacAddr [in] - MAC address to remove
- * 
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized
- * @retval IX_ETH_DB_INVALID_ARG invalid <i>macAddr</i> pointer argument
- * @retval IX_ETH_DB_NO_SUCH_ADDR specified address was not found in the database
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE WiFi feature not enabled 
- * @retval IX_ETH_DB_BUSY lock condition or transaction in progress, try again later
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBWiFiEntryRemove(IxEthDBPortId portID, IxEthDBMacAddr *macAddr);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBWiFiConversionTableDownload(IxEthDBPortId portID)
- *
- * @brief Downloads the MAC address table for 802.3 => 802.11 frame header
- * conversion to the NPE
- *
- * Note that the frame conversion MAC address table must be individually downloaded
- * to each NPE for which the frame header conversion feature is enabled (i.e. it
- * is not possible to specify IX_ETH_DB_ALL_PORTS).
- *
- * @param portID @ref IxEthDBPortId [in] - ID of the port 
- * 
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port not initialized
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE WiFi feature not enabled
- * @retval IX_ETH_DB_FAIL unknown OS or NPE communication error
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBWiFiConversionTableDownload(IxEthDBPortId portID);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBWiFiFrameControlSet(IxEthDBPortId portID, UINT16 frameControl)
- *
- * @brief Sets the GlobalFrameControl field
- *
- * The GlobalFrameControl field is a 2-byte value inserted in the <i>Frame Control</i>
- * field for all 802.3 to 802.11 frame header conversions
- * 
- * @param portID @ref IxEthDBPortId [in] - ID of the port
- * @param frameControl UINT16 [in] - GlobalFrameControl value
- * 
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port not initialized
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE WiFi feature not enabled
- * @retval IX_ETH_DB_FAIL unknown OS or NPE communication error
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBWiFiFrameControlSet(IxEthDBPortId portID, UINT16 frameControl);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBWiFiDurationIDSet(IxEthDBPortId portID, UINT16 durationID)
- *
- * @brief Sets the GlobalDurationID field
- *
- * The GlobalDurationID field is a 2-byte value inserted in the <i>Duration/ID</i>
- * field for all 802.3 to 802.11 frame header conversions
- *
- * @param portID @ref IxEthDBPortId [in] - ID of the port 
- * @param durationID UINT16 [in] - GlobalDurationID field
- * 
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port not initialized
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE WiFi feature not enabled
- * @retval IX_ETH_DB_FAIL unknown OS or NPE communication error
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBWiFiDurationIDSet(IxEthDBPortId portID, UINT16 durationID);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBWiFiBBSIDSet(IxEthDBPortId portID, IxEthDBMacAddr *bbsid)
- *
- * @brief Sets the BBSID field
- *
- * The BBSID field is a 6-byte value which
- * identifies the infrastructure of the service set managed 
- * by the Access Point having the IXP400 as its processor. The value
- * is written in the <i>BBSID</i> field of the 802.11 frame header.
- * The BBSID value is the MAC address of the Access Point.
- *
- * @param portID @ref IxEthDBPortId [in] - ID of the port 
- * @param bbsid @ref IxEthDBMacAddr [in] - pointer to 6 bytes containing the BSSID
- * 
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port not initialized
- * @retval IX_ETH_DB_INVALID_ARG invalid <i>bbsid</i> pointer argument
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE WiFi feature not enabled
- * @retval IX_ETH_DB_FAIL unknown OS or NPE communication error
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBWiFiBBSIDSet(IxEthDBPortId portID, IxEthDBMacAddr *bbsid);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBSpanningTreeBlockingStateSet(IxEthDBPortId portID, BOOL blocked)
- *
- * @brief Sets the STP blocked/unblocked state for a port
- *
- * @param portID @ref IxEthDBPortId [in] - ID of the port 
- * @param blocked BOOL [in] - TRUE to set the port as STP blocked, FALSE to set it as unblocked
- * 
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port not initialized
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE Spanning Tree Protocol feature not enabled
- * @retval IX_ETH_DB_FAIL unknown OS or NPE communication error
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBSpanningTreeBlockingStateSet(IxEthDBPortId portID, BOOL blocked);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBSpanningTreeBlockingStateGet(IxEthDBPortId portID, BOOL *blocked)
- *
- * @brief Retrieves the STP blocked/unblocked state for a port
- *
- * @param portID @ref IxEthDBPortId [in] - ID of the port 
- * @param blocked BOOL * [in] - set to TRUE if the port is STP blocked, FALSE otherwise
- * 
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port not initialized
- * @retval IX_ETH_DB_INVALID_ARG invalid <i>blocked</i> pointer argument
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE Spanning Tree Protocol feature not enabled
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBSpanningTreeBlockingStateGet(IxEthDBPortId portID, BOOL *blocked);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBFirewallModeSet(IxEthDBPortId portID, IxEthDBFirewallMode mode)
- *
- * @brief Sets the firewall mode to use white or black listing
- *
- * When enabled, the NPE MAC address based firewall support operates in two modes:
- *
- * - white-list mode (MAC address based admission) 
- *    - <i>mode</i> set to IX_ETH_DB_FIREWALL_WHITE_LIST
- *    - only packets originating from MAC addresses contained in the firewall address list
- *      are allowed on the Rx path
- * - black-list mode (MAC address based blocking)  
- *    - <i>mode</i> set to IX_ETH_DB_FIREWALL_BLACK_LIST
- *    - packets originating from MAC addresses contained in the firewall address list
- *      are discarded
- *
- * @param portID @ref IxEthDBPortId [in] - ID of the port 
- * @param mode @ref IxEthDBFirewallMode [in] - firewall mode (IX_ETH_DB_FIREWALL_WHITE_LIST or IX_ETH_DB_FIREWALL_BLACK_LIST)
- *
- * @note by default the firewall operates in black-list mode with an empty address
- * list, hence it doesn't filter any packets
- * 
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port not initialized
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE Firewall feature not enabled 
- * @retval IX_ETH_DB_INVALID_ARGUMENT <i>mode</i> argument is not a valid firewall configuration mode
- * @retval IX_ETH_DB_FAIL unknown OS or NPE communication error
-*/
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBFirewallModeSet(IxEthDBPortId portID, IxEthDBFirewallMode mode);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn ixEthDBFirewallInvalidAddressFilterEnable(IxEthDBPortId portID, BOOL enable)
- *
- * @brief Enables or disables invalid MAC address filtering
- *
- * According to IEEE802 it is illegal for a source address to be a multicast
- * or broadcast address. If this feature is enabled the NPE inspects the source
- * MAC addresses of incoming frames and discards them if invalid addresses are
- * detected.
- *
- * By default this service is enabled, if the firewall feature is supported by the
- * NPE image.
- *
- * @param portID ID of the port 
- * @param enable TRUE to enable invalid MAC address filtering and FALSE to disable it
- * 
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port not initialized
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE Firewall feature not enabled 
- * @retval IX_ETH_DB_FAIL unknown OS or NPE communication error
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBFirewallInvalidAddressFilterEnable(IxEthDBPortId portID, BOOL enable);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBFirewallEntryAdd(IxEthDBPortId portID, IxEthDBMacAddr *macAddr)
- *
- * @brief Adds a MAC address to the firewall address list
- *
- * Note that adding the same MAC address twice will not return an error
- * but will not actually accomplish anything.
- *
- * The firewall MAC address list has a limited number of entries; once
- * the maximum number of entries has been reached this function will failed
- * to add more addresses, returning IX_ETH_DB_NOMEM.
- *
- * @param portID @ref IxEthDBPortId [in] - ID of the port 
- * @param macAddr @ref IxEthDBMacAddr [in] - MAC address to be added
- * 
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port not initialized
- * @retval IX_ETH_DB_INVALID_ARG invalid <i>macAddr</i> pointer argument
- * @retval IX_ETH_DB_NOMEM maximum number of records reached
- * @retval IX_ETH_DB_BUSY lock condition or transaction in progress, try again later
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE Firewall feature not enabled 
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBFirewallEntryAdd(IxEthDBPortId portID, IxEthDBMacAddr *macAddr);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBFirewallEntryRemove(IxEthDBPortId portID, IxEthDBMacAddr *macAddr)
- *
- * @brief Removes a MAC address from the firewall address list
- *
- * @param portID @ref IxEthDBPortId [in] - ID of the port 
- * @param macAddr @ref IxEthDBMacAddr [in] - MAC address to be removed
- * 
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port not initialized
- * @retval IX_ETH_DB_INVALID_ARG invalid <i>macAddr</i> pointer argument
- * @retval IX_ETH_DB_NO_SUCH_ADDR address not found
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE Firewall feature not enabled 
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBFirewallEntryRemove(IxEthDBPortId portID, IxEthDBMacAddr *macAddr);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBFirewallTableDownload(IxEthDBPortId portID)
- *
- * @brief Downloads the MAC firewall table to a port
- *
- * @param portID ID of the port 
- * 
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port not initialized
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE Firewall feature not enabled 
- * @retval IX_ETH_DB_FAIL unknown OS or NPE communication error
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBFirewallTableDownload(IxEthDBPortId portID);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBUserFieldSet(IxEthDBRecordType recordType, IxEthDBMacAddr *macAddr, IxEthDBPortId portID, IxEthDBVlanId vlanID, void *field)
- *
- * @brief Adds a user-defined field to a database record
- *
- * This function associates a user-defined field to a database record.
- * The user-defined field is passed as a <i>(void *)</i> parameter, hence it can be used
- * for any purpose (such as identifying a structure). Retrieving the user-defined field from
- * a record is done using @ref ixEthDBUserFieldGet. Note that EthDB never uses the user-defined
- * field for any internal operation and it is not aware of the significance of its contents. The
- * field is only stored as a pointer.
- *
- * The database record is identified using a combination of the given parameters, depending on the record type.
- * All the record types require the record MAC address.
- *
- * - IX_ETH_DB_FILTERING_RECORD requires only the MAC address
- * - IX_ETH_DB_VLAN_FILTERING_RECORD requires the MAC address and the VLAN ID
- * - IX_ETH_DB_WIFI_RECORD requires the MAC address and the portID
- * - IX_ETH_DB_FIREWALL_RECORD requires the MAC address and the portID
- *
- * Please note that if a parameter is not required it is completely ignored (it does not undergo parameter checking).
- * The user-defined field can be cleared using a <b>NULL</b> <i>field</i> parameter.
- *
- * @param recordType @ref IxEthDBRecordType [in] - type of record (can be IX_ETH_DB_FILTERING_RECORD, 
- * IX_ETH_DB_FILTERING_VLAN_RECORD, IX_ETH_DB_WIFI_RECORD or IX_ETH_DB_FIREWALL_RECORD)
- * @param portID @ref IxEthDBPortId [in] - ID of the port (required only for WIFI and FIREWALL records) 
- * @param macAddr @ref IxEthDBMacAddr * [in] - MAC address of the record
- * @param vlanID @ref IxEthDBVlanId [in] - VLAN ID of the record (required only for FILTERING_VLAN records)
- * @param field void * [in] - user defined field
- * 
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID was required but it is not a valid port identifier
- * @retval IX_ETH_DB_INVALID_ARG invalid <i>macAddr</i> pointer argument
- * @retval IX_ETH_DB_NO_SUCH_ADDR record not found
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBUserFieldSet(IxEthDBRecordType recordType, IxEthDBMacAddr *macAddr, IxEthDBPortId portID, IxEthDBVlanId vlanID, void *field);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBUserFieldGet(IxEthDBRecordType recordType, IxEthDBMacAddr *macAddr, IxEthDBPortId portID, IxEthDBVlanId vlanID, void **field)
- *
- * @brief Retrieves a user-defined field from a database record
- *
- * The database record is identified using a combination of the given parameters, depending on the record type.
- * All the record types require the record MAC address.
- *
- * - IX_ETH_DB_FILTERING_RECORD requires only the MAC address
- * - IX_ETH_DB_VLAN_FILTERING_RECORD requires the MAC address and the VLAN ID
- * - IX_ETH_DB_WIFI_RECORD requires the MAC address and the portID
- * - IX_ETH_DB_FIREWALL_RECORD requires the MAC address and the portID
- *
- * Please note that if a parameter is not required it is completely ignored (it does not undergo parameter checking).
- *
- * If no user-defined field was registered with the specified record then <b>NULL</b> will be written
- * at the location specified by <i>field</i>.
- *
- * @param recordType type of record (can be IX_ETH_DB_FILTERING_RECORD, IX_ETH_DB_FILTERING_VLAN_RECORD, IX_ETH_DB_WIFI_RECORD 
- * or IX_ETH_DB_FIREWALL_RECORD)
- * @param portID ID of the port (required only for WIFI and FIREWALL records) 
- * @param macAddr MAC address of the record
- * @param vlanID VLAN ID of the record (required only for FILTERING_VLAN records)
- * @param field location to write the user defined field into
- * 
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID was required but it is not a valid port identifier
- * @retval IX_ETH_DB_INVALID_ARG invalid <i>macAddr</i> or <i>field</i> pointer arguments
- * @retval IX_ETH_DB_NO_SUCH_ADDR record not found
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBUserFieldGet(IxEthDBRecordType recordType, IxEthDBMacAddr *macAddr, IxEthDBPortId portId, IxEthDBVlanId vlanID, void **field);
-
-/**
- * @}
- */
-
-#endif /* IxEthDB_H */
diff --git a/arch/arm/cpu/ixp/npe/include/IxEthDBLocks_p.h b/arch/arm/cpu/ixp/npe/include/IxEthDBLocks_p.h
deleted file mode 100644
index 1d8b24f..0000000
--- a/arch/arm/cpu/ixp/npe/include/IxEthDBLocks_p.h
+++ /dev/null
@@ -1,122 +0,0 @@
-/**
- * @file IxEthAccDBLocks_p.h
- *
- * @brief Definition of transaction lock stacks and lock utility macros
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- * 
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- * 
- * @par
- * -- End of Copyright Notice --
- */
-
-#ifndef IxEthAccDBLocks_p_H
-#define IxEthAccDBLocks_p_H
-
-#include "IxOsPrintf.h"
-
-/* Lock and lock stacks */
-typedef struct
-{
-    IxOsalFastMutex* locks[MAX_LOCKS];
-    UINT32 stackPointer, basePointer;
-} LockStack;
-
-#define TRY_LOCK(mutex) \
-    { \
-        if (ixOsalFastMutexTryLock(mutex) != IX_SUCCESS) \
-        { \
-            return IX_ETH_DB_BUSY; \
-        } \
-    }
-
-
-#define UNLOCK(mutex) { ixOsalFastMutexUnlock(mutex); }
-
-#define INIT_STACK(stack) \
-    { \
-        (stack)->basePointer  = 0; \
-        (stack)->stackPointer = 0; \
-    }
-
-#define PUSH_LOCK(stack, lock) \
-    { \
-        if ((stack)->stackPointer == MAX_LOCKS) \
-        { \
-            ERROR_LOG("Ethernet DB: maximum number of elements in a lock stack has been exceeded on push, heavy chaining?\n"); \
-            UNROLL_STACK(stack); \
-            \
-            return IX_ETH_DB_NOMEM; \
-        } \
-        \
-        if (ixOsalFastMutexTryLock(lock) == IX_SUCCESS) \
-        { \
-            (stack)->locks[(stack)->stackPointer++] = (lock); \
-        } \
-        else \
-        { \
-            UNROLL_STACK(stack); \
-            \
-            return IX_ETH_DB_BUSY; \
-        } \
-    }
-
-#define POP_LOCK(stack) \
-    { \
-        ixOsalFastMutexUnlock((stack)->locks[--(stack)->stackPointer]); \
-    }
-
-#define UNROLL_STACK(stack) \
-    { \
-        while ((stack)->stackPointer > (stack)->basePointer) \
-        { \
-            POP_LOCK(stack); \
-        } \
-    }
-
-#define SHIFT_STACK(stack) \
-    { \
-        if ((stack)->basePointer == MAX_LOCKS - 1) \
-        { \
-            ERROR_LOG("Ethernet DB: maximum number of elements in a lock stack has been exceeded on shift, heavy chaining?\n"); \
-            UNROLL_STACK(stack); \
-            \
-            return IX_ETH_DB_BUSY; \
-        } \
-        \
-        ixOsalFastMutexUnlock((stack)->locks[(stack)->basePointer++]); \
-    }
-
-#endif /* IxEthAccDBLocks_p_H */
diff --git a/arch/arm/cpu/ixp/npe/include/IxEthDBLog_p.h b/arch/arm/cpu/ixp/npe/include/IxEthDBLog_p.h
deleted file mode 100644
index 1d6b0bb..0000000
--- a/arch/arm/cpu/ixp/npe/include/IxEthDBLog_p.h
+++ /dev/null
@@ -1,227 +0,0 @@
-/**
- * @file IxEthDBLog_p.h
- *
- * @brief definitions of log macros and log configuration
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- * 
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- * 
- * @par
- * -- End of Copyright Notice --
- */
-
-#include <IxOsal.h>
-
-#ifdef IX_UNIT_TEST
-#define NULL_PRINT_ROUTINE(format, arg...) /* nothing */
-#else
-#define NULL_PRINT_ROUTINE if(0) printf
-#endif
-
-/***************************************************
- *                 Globals                         *
- ***************************************************/
-/* safe to permanently leave these on */
-#define HAS_ERROR_LOG
-#define HAS_ERROR_IRQ_LOG
-#define HAS_WARNING_LOG
-
-/***************************************************
- *              Log Configuration                  *
- ***************************************************/
-
-/* debug output can be turned on unless specifically
-   declared as a non-debug build */
-#ifndef NDEBUG
-
-#undef HAS_EVENTS_TRACE
-#undef HAS_EVENTS_VERBOSE_TRACE
-
-#undef HAS_SUPPORT_TRACE
-#undef HAS_SUPPORT_VERBOSE_TRACE
-
-#undef HAS_NPE_TRACE
-#undef HAS_NPE_VERBOSE_TRACE
-#undef HAS_DUMP_NPE_TREE
-
-#undef HAS_UPDATE_TRACE
-#undef HAS_UPDATE_VERBOSE_TRACE
-
-#endif /* NDEBUG */
-
-
-/***************************************************
- *              Log Macros                         *
- ***************************************************/
-
-/************** Globals ******************/
-
-#ifdef HAS_ERROR_LOG
-
-    #define ERROR_LOG printf
-
-#else
-
-    #define ERROR_LOG NULL_PRINT_ROUTINE
-
-#endif
-
-#ifdef HAS_ERROR_IRQ_LOG
-
-    #define ERROR_IRQ_LOG(format, arg1, arg2, arg3, arg4, arg5, arg6) ixOsalLog(IX_OSAL_LOG_LVL_ERROR, IX_OSAL_LOG_DEV_STDOUT, format, arg1, arg2, arg3, arg4, arg5, arg6)
-
-#else
-
-    #define ERROR_IRQ_LOG(format, arg1, arg2, arg3, arg4, arg5, arg6) /* nothing */
-
-#endif
-
-#ifdef HAS_WARNING_LOG
-
-    #define WARNING_LOG printf
-
-#else
-
-    #define WARNING_LOG NULL_PRINT_ROUTINE
-
-#endif
-
-/************** Events *******************/
-
-#ifdef HAS_EVENTS_TRACE
-
-    #define IX_ETH_DB_EVENTS_TRACE     printf
-    #define IX_ETH_DB_IRQ_EVENTS_TRACE(format, arg1, arg2, arg3, arg4, arg5, arg6) ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, format, arg1, arg2, arg3, arg4, arg5, arg6)
-
-    #ifdef HAS_EVENTS_VERBOSE_TRACE
-
-        #define IX_ETH_DB_EVENTS_VERBOSE_TRACE printf
-    
-    #else
-
-        #define IX_ETH_DB_EVENTS_VERBOSE_TRACE NULL_PRINT_ROUTINE
-
-    #endif /* HAS_EVENTS_VERBOSE_TRACE */
-
-#else
-
-    #define IX_ETH_DB_EVENTS_TRACE         NULL_PRINT_ROUTINE
-    #define IX_ETH_DB_EVENTS_VERBOSE_TRACE NULL_PRINT_ROUTINE
-    #define IX_ETH_DB_IRQ_EVENTS_TRACE(format, arg1, arg2, arg3, arg4, arg5, arg6) /* nothing */
-
-#endif /* HAS_EVENTS_TRACE */
-
-/************** Support *******************/
-
-#ifdef HAS_SUPPORT_TRACE
-
-    #define IX_ETH_DB_SUPPORT_TRACE     printf
-    #define IX_ETH_DB_SUPPORT_IRQ_TRACE(format, arg1, arg2, arg3, arg4, arg5, arg6) ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, format, arg1, arg2, arg3, arg4, arg5, arg6)
-
-    #ifdef HAS_SUPPORT_VERBOSE_TRACE
-
-        #define IX_ETH_DB_SUPPORT_VERBOSE_TRACE printf
-
-    #else
-
-        #define IX_ETH_DB_SUPPORT_VERBOSE_TRACE NULL_PRINT_ROUTINE
-
-    #endif /* HAS_SUPPORT_VERBOSE_TRACE */
-
-#else
-
-    #define IX_ETH_DB_SUPPORT_TRACE         NULL_PRINT_ROUTINE
-    #define IX_ETH_DB_SUPPORT_VERBOSE_TRACE NULL_PRINT_ROUTINE
-    #define IX_ETH_DB_SUPPORT_IRQ_TRACE(format, arg1, arg2, arg3, arg4, arg5, arg6) /* nothing */
-
-#endif /* HAS_SUPPORT_TRACE */
-
-/************** NPE Adaptor *******************/
-
-#ifdef HAS_NPE_TRACE
-
-    #define IX_ETH_DB_NPE_TRACE     printf
-    #define IX_ETH_DB_NPE_IRQ_TRACE(format, arg1, arg2, arg3, arg4, arg5, arg6) ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, format, arg1, arg2, arg3, arg4, arg5, arg6)
-
-    #ifdef HAS_NPE_VERBOSE_TRACE
-
-        #define IX_ETH_DB_NPE_VERBOSE_TRACE printf
-
-    #else
-
-        #define IX_ETH_DB_NPE_VERBOSE_TRACE NULL_PRINT_ROUTINE
-
-    #endif /* HAS_NPE_VERBOSE_TRACE */
-
-#else
-
-    #define IX_ETH_DB_NPE_TRACE         NULL_PRINT_ROUTINE
-    #define IX_ETH_DB_NPE_VERBOSE_TRACE NULL_PRINT_ROUTINE
-    #define IX_ETH_DB_NPE_IRQ_TRACE(format, arg1, arg2, arg3, arg4, arg5, arg6) /* nothing */
-
-#endif /* HAS_NPE_TRACE */
-
-#ifdef HAS_DUMP_NPE_TREE
-
-#define IX_ETH_DB_NPE_DUMP_ELT(eltBaseAddress, eltSize) ixEthELTDumpTree(eltBaseAddress, eltSize)
-
-#else
-
-#define IX_ETH_DB_NPE_DUMP_ELT(eltBaseAddress, eltSize) /* nothing */
-
-#endif /* HAS_DUMP_NPE_TREE */
-
-/************** Port Update *******************/
-
-#ifdef HAS_UPDATE_TRACE
-
-    #define IX_ETH_DB_UPDATE_TRACE printf
-
-    #ifdef HAS_UPDATE_VERBOSE_TRACE
-
-        #define IX_ETH_DB_UPDATE_VERBOSE_TRACE printf
-
-    #else
-
-        #define IX_ETH_DB_UPDATE_VERBOSE_TRACE NULL_PRINT_ROUTINE
-
-    #endif
-
-#else /* HAS_UPDATE_VERBOSE_TRACE */
-
-    #define IX_ETH_DB_UPDATE_TRACE         NULL_PRINT_ROUTINE
-    #define IX_ETH_DB_UPDATE_VERBOSE_TRACE NULL_PRINT_ROUTINE
-
-#endif /* HAS_UPDATE_TRACE */
diff --git a/arch/arm/cpu/ixp/npe/include/IxEthDBMessages_p.h b/arch/arm/cpu/ixp/npe/include/IxEthDBMessages_p.h
deleted file mode 100644
index ff18160..0000000
--- a/arch/arm/cpu/ixp/npe/include/IxEthDBMessages_p.h
+++ /dev/null
@@ -1,258 +0,0 @@
-/**
- * @file IxEthDBMessages_p.h
- *
- * @brief Definitions of NPE messages
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
- */
-
-#ifndef IxEthDBMessages_p_H
-#define IxEthDBMessages_p_H
-
-#include <IxEthNpe.h>
-#include <IxOsCacheMMU.h>
-#include "IxEthDB_p.h"
-
-/* events watched by the Eth event processor */
-#define IX_ETH_DB_MIN_EVENT_ID        (IX_ETHNPE_EDB_GETMACADDRESSDATABASE)
-#define IX_ETH_DB_MAX_EVENT_ID        (IX_ETHNPE_PC_SETAPMACTABLE)
-
-/* macros to fill and extract data from NPE messages - place any endian conversions here */
-#define RESET_ELT_MESSAGE(message) { memset((void *) &(message), 0, sizeof((message))); }
-#define NPE_MSG_ID(msg) ((msg).data[0] >> 24)
-
-#define FILL_SETPORTVLANTABLEENTRY_MSG(message, portID, setOffset, vlanMembershipSet, ttiSet) \
-    do { \
-        message.data[0] = (IX_ETHNPE_VLAN_SETPORTVLANTABLEENTRY << 24) | (portID << 16) | (setOffset * 2); \
-        message.data[1] = (vlanMembershipSet << 8) | ttiSet; \
-    } while (0);
-
-#define FILL_SETPORTVLANTABLERANGE_MSG(message, portID, offset, length, zone) \
-    do { \
-        message.data[0] = IX_ETHNPE_VLAN_SETPORTVLANTABLERANGE << 24 | portID << 16 | offset << 9 | length << 1; \
-        message.data[1] = (UINT32) zone; \
-    } while (0);
-
-#define FILL_SETDEFAULTRXVID_MSG(message, portID, tpid, vlanTag) \
-    do { \
-        message.data[0] = (IX_ETHNPE_VLAN_SETDEFAULTRXVID << 24) \
-            | (portID << 16); \
-        \
-        message.data[1] = (tpid << 16) | vlanTag; \
-    } while (0);
-
-#define FILL_SETRXTAGMODE_MSG(message, portID, filterMode, tagMode) \
-    do { \
-        message.data[0] = IX_ETHNPE_VLAN_SETRXTAGMODE << 24 \
-            | portID << 16 \
-            | filterMode << 2 \
-            | tagMode; \
-        \
-        message.data[1] = 0; \
-    } while (0);
-
-#define FILL_SETRXQOSENTRY(message, portID, classIndex, trafficClass, aqmQueue) \
-    do { \
-        message.data[0] = IX_ETHNPE_VLAN_SETRXQOSENTRY << 24 \
-            | portID << 16 \
-            | classIndex; \
-        \
-        message.data[1] = trafficClass << 24 \
-            | 0x1 << 23 \
-            | aqmQueue << 16 \
-            | aqmQueue << 4; \
-    } while (0);
-
-#define FILL_SETPORTIDEXTRACTIONMODE(message, portID, enable) \
-    do { \
-        message.data[0] = IX_ETHNPE_VLAN_SETPORTIDEXTRACTIONMODE << 24 \
-            | portID << 16 \
-            | (enable ? 0x1 : 0x0); \
-        \
-        message.data[1] = 0; \
-    } while (0);
-
-
-#define FILL_SETBLOCKINGSTATE_MSG(message, portID, blocked) \
-    do { \
-        message.data[0] = IX_ETHNPE_STP_SETBLOCKINGSTATE << 24 \
-            | portID << 16 \
-            | (blocked ? 0x1 : 0x0); \
-        \
-        message.data[1] = 0; \
-    } while (0);
-
-#define FILL_SETBBSID_MSG(message, portID, bbsid) \
-    do { \
-        message.data[0] = IX_ETHNPE_PC_SETBBSID << 24 \
-            | portID << 16 \
-            | bbsid->macAddress[0] << 8 \
-            | bbsid->macAddress[1]; \
-        \
-        message.data[1] = bbsid->macAddress[2] << 24 \
-            | bbsid->macAddress[3] << 16 \
-            | bbsid->macAddress[4] << 8 \
-            | bbsid->macAddress[5]; \
-    } while (0);
-
-#define FILL_SETFRAMECONTROLDURATIONID(message, portID, frameControlDurationID) \
-    do { \
-        message.data[0] = (IX_ETHNPE_PC_SETFRAMECONTROLDURATIONID << 24) | (portID << 16); \
-        message.data[1] = frameControlDurationID; \
-    } while (0);
-
-#define FILL_SETAPMACTABLE_MSG(message, zone) \
-    do { \
-        message.data[0] = IX_ETHNPE_PC_SETAPMACTABLE << 24 \
-            | 0 << 8      /* always use index 0 */ \
-            | 64;         /* 32 entries, 8 bytes each, 4 bytes in a word */ \
-        message.data[1] = (UINT32) zone; \
-    } while (0);
-
-#define FILL_SETFIREWALLMODE_MSG(message, portID, epDelta, mode, address) \
-    do { \
-        message.data[0] = IX_ETHNPE_FW_SETFIREWALLMODE << 24 \
-            | portID << 16 \
-            | (epDelta & 0xFF) << 8 \
-            | mode; \
-        \
-        message.data[1] = (UINT32) address; \
-    } while (0);
-
-#define FILL_SETMACADDRESSDATABASE_MSG(message, portID, epDelta, blockCount, address) \
-    do { \
-        message.data[0] = IX_ETHNPE_EDB_SETMACADDRESSSDATABASE << 24 \
-                | (epDelta & 0xFF) << 8 \
-                | (blockCount & 0xFF); \
-        \
-        message.data[1] = (UINT32) address; \
-    } while (0);
-
-#define FILL_GETMACADDRESSDATABASE(message, npeId, zone) \
-    do { \
-        message.data[0] = IX_ETHNPE_EDB_GETMACADDRESSDATABASE << 24; \
-        message.data[1] = (UINT32) zone; \
-    } while (0);
-
-#define FILL_SETMAXFRAMELENGTHS_MSG(message, portID, maxRxFrameSize, maxTxFrameSize) \
-    do { \
-        message.data[0] = IX_ETHNPE_SETMAXFRAMELENGTHS << 24 \
-            | portID << 16 \
-            | ((maxRxFrameSize + 63) / 64) << 8  /* max Rx 64-byte blocks */ \
-            | (maxTxFrameSize + 63) / 64; /* max Tx 64-byte blocks */ \
-        \
-        message.data[1] = maxRxFrameSize << 16 | maxTxFrameSize; \
-    } while (0);
-
-#define FILL_SETPORTADDRESS_MSG(message, portID, macAddress) \
-    do { \
-        message.data[0] = IX_ETHNPE_EDB_SETPORTADDRESS << 24 \
-            | portID << 16 \
-            | macAddress[0] << 8 \
-            | macAddress[1]; \
-        \
-        message.data[1] = macAddress[2] << 24 \
-            | macAddress[3] << 16 \
-            | macAddress[4] << 8 \
-            | macAddress[5]; \
-    } while (0);
-
-/* access to a MAC node in the NPE tree */
-#define NPE_NODE_BYTE(eltNodeAddr, offset)      (((UINT8 *) (eltNodeAddr))[offset])
-
-/* browsing of the implicit linear binary tree structure of the NPE tree */
-#define LEFT_CHILD_OFFSET(offset)   ((offset) << 1)
-#define RIGHT_CHILD_OFFSET(offset)  (((offset) << 1) + 1)
-
-#define IX_EDB_FLAGS_ACTIVE         (0x2)
-#define IX_EDB_FLAGS_VALID          (0x1)
-#define IX_EDB_FLAGS_RESERVED       (0xfc)
-#define IX_EDB_FLAGS_INACTIVE_VALID (0x1)
-
-#define IX_EDB_NPE_NODE_ELT_PORT_ID_OFFSET (6)
-#define IX_EDB_NPE_NODE_ELT_FLAGS_OFFSET   (7)
-#define IX_EDB_NPE_NODE_WIFI_INDEX_OFFSET  (6)
-#define IX_EDB_NPE_NODE_WIFI_FLAGS_OFFSET  (7)
-#define IX_EDB_NPE_NODE_FW_FLAGS_OFFSET    (1)
-#define IX_EDB_NPE_NODE_FW_RESERVED_OFFSET (6)
-#define IX_EDB_NPE_NODE_FW_ADDR_OFFSET     (2)
-
-#define IX_EDB_NPE_NODE_VALID(address)     ((NPE_NODE_BYTE(address, IX_EDB_NPE_NODE_ELT_FLAGS_OFFSET) & IX_EDB_FLAGS_VALID) != 0)
-#define IX_EDB_NPE_NODE_ACTIVE(address)    ((NPE_NODE_BYTE(address, IX_EDB_NPE_NODE_ELT_FLAGS_OFFSET) & IX_EDB_FLAGS_ACTIVE) != 0)
-#define IX_EDB_NPE_NODE_PORT_ID(address)   (NPE_NODE_BYTE(address, IX_EDB_NPE_NODE_ELT_PORT_ID_OFFSET))
-
-/* macros to send messages to the NPEs */
-#define IX_ETHDB_ASYNC_SEND_NPE_MSG(npeId, msg, result) \
-    do { \
-        result = ixNpeMhMessageSend(npeId, msg, IX_NPEMH_SEND_RETRIES_DEFAULT); \
-        \
-        if (result != IX_SUCCESS) \
-        { \
-            ERROR_LOG("DB: Failed to send NPE message\n"); \
-        } \
-    } while (0);
-
-#define IX_ETHDB_SYNC_SEND_NPE_MSG(npeId, msg, result) \
-    do { \
-        result = ixNpeMhMessageWithResponseSend(npeId, msg, msg.data[0] >> 24, ixEthDBNpeMsgAck, IX_NPEMH_SEND_RETRIES_DEFAULT); \
-        \
-        if (result == IX_SUCCESS) \
-        { \
-            result = ixOsalMutexLock(&ixEthDBPortInfo[IX_ETH_DB_NPE_TO_PORT_ID(npeId)].npeAckLock, IX_ETH_DB_NPE_TIMEOUT); \
-            \
-            if (result != IX_SUCCESS) \
-            { \
-                ERROR_LOG("DB: NPE failed to respond within %dms\n", IX_ETH_DB_NPE_TIMEOUT); \
-            } \
-        } \
-        else \
-        { \
-            ERROR_LOG("DB: Failed to send NPE message\n"); \
-        } \
-    } while (0);
-
-#ifndef IX_NDEBUG
-#define IX_ETH_DB_NPE_MSG_HISTORY_DEPTH (100)
-extern IX_ETH_DB_PUBLIC UINT32 npeMsgHistory[IX_ETH_DB_NPE_MSG_HISTORY_DEPTH][2];
-extern IX_ETH_DB_PUBLIC UINT32 npeMsgHistoryLen;
-#endif
-
-#define IX_ETHDB_SEND_NPE_MSG(npeId, msg, result) { LOG_NPE_MSG(msg); IX_ETHDB_SYNC_SEND_NPE_MSG(npeId, msg, result); }
-
-#endif /* IxEthDBMessages_p_H */
diff --git a/arch/arm/cpu/ixp/npe/include/IxEthDBPortDefs.h b/arch/arm/cpu/ixp/npe/include/IxEthDBPortDefs.h
deleted file mode 100644
index c3acbdd..0000000
--- a/arch/arm/cpu/ixp/npe/include/IxEthDBPortDefs.h
+++ /dev/null
@@ -1,163 +0,0 @@
-/**
- * @file IxEthDBPortDefs.h
- *
- * @brief Public definition of the ports and port capabilities
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- * 
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- * 
- * @par
- * -- End of Copyright Notice --
- */
-
-/**
- * @defgroup IxEthDBPortDefs IXP400 Ethernet Database Port Definitions (IxEthDBPortDefs)
- *
- * @brief IXP400 Public definition of the ports and port capabilities
- *
- * @{
- */
-
-#ifndef IxEthDBPortDefs_H
-#define IxEthDBPortDefs_H
-
-/** 
- * @brief Port types - currently only Ethernet NPEs are recognized as specific types 
- * All other (user-defined) ports must be specified as IX_ETH_GENERIC
- */
-typedef enum
-{
-    IX_ETH_GENERIC = 0, /**< generic ethernet port */
-    IX_ETH_NPE          /**< specific Ethernet NPE */
-} IxEthDBPortType;
-
-/** 
- * @brief Port capabilities - used by ixEthAccDatabaseMaintenance to decide whether it
- * should manually age entries or not depending on the port capabilities.
- *
- * Ethernet NPEs have aging capabilities, meaning that they will age the entries
- * automatically (by themselves).*/
-typedef enum
-{
-    IX_ETH_NO_CAPABILITIES = 0,   /**< no aging capabilities */
-    IX_ETH_ENTRY_AGING     = 0x1  /**< aging capabilities present */
-} IxEthDBPortCapability;
-
-/** 
- * @brief Port Definition - a structure contains the Port type and capabilities 
- */
-typedef struct
-{
-    IxEthDBPortType type;
-    IxEthDBPortCapability capabilities;
-} IxEthDBPortDefinition;
-
-/** 
- * @brief Port definitions structure, indexed on the port ID
- * @warning Ports 0 and 1 are used by the Ethernet access component therefore
- * it is essential to be left untouched. Port 2 here (WAN) is given as 
- * an example port. The NPE firmware also assumes the NPE B to be
- * the port 0 and NPE C to be the port 1.
- *
- * @note that only 32 ports (0..31) are supported by EthDB
- */
-static const IxEthDBPortDefinition ixEthDBPortDefinitions[] = 
-{
-    /*    id       type              capabilities */
-    {   /* 0 */    IX_ETH_NPE,       IX_ETH_NO_CAPABILITIES },    /* Ethernet NPE B */
-    {   /* 1 */    IX_ETH_NPE,       IX_ETH_NO_CAPABILITIES },    /* Ethernet NPE C */
-    {   /* 2 */    IX_ETH_NPE,       IX_ETH_NO_CAPABILITIES },    /* Ethernet NPE A */
-    {   /* 3 */    IX_ETH_GENERIC,   IX_ETH_NO_CAPABILITIES },    /* WAN port */
-};
-
-/** 
- * @def IX_ETH_DB_NUMBER_OF_PORTS
- * @brief number of supported ports 
- */
-#define IX_ETH_DB_NUMBER_OF_PORTS (sizeof (ixEthDBPortDefinitions) / sizeof (ixEthDBPortDefinitions[0]))
-
-/**
- * @def IX_ETH_DB_UNKNOWN_PORT
- * @brief definition of an unknown port
- */
-#define IX_ETH_DB_UNKNOWN_PORT (0xff)
-
-/** 
- * @def IX_ETH_DB_ALL_PORTS
- * @brief Special port ID indicating all the ports
- * @note This port ID can be used only by a subset of the EthDB API; each
- * function specifically mentions whether this is a valid parameter as the port ID
- */
-#define IX_ETH_DB_ALL_PORTS (IX_ETH_DB_NUMBER_OF_PORTS + 1)
-
-/**
- * @def IX_ETH_DB_PORTS_ASSERTION
- * @brief catch invalid port definitions (<2) with a 
- * compile-time assertion resulting in a duplicate case error. 
- */
-#define IX_ETH_DB_PORTS_ASSERTION { switch(0) { case 0 : ; case 1 : ; case IX_ETH_DB_NUMBER_OF_PORTS : ; }}
-
-/** 
- * @def IX_ETH_DB_CHECK_PORT(portID)
- * @brief safety checks to verify whether the port is invalid or uninitialized
- */
-#define IX_ETH_DB_CHECK_PORT(portID) \
-{ \
-  if ((portID) >= IX_ETH_DB_NUMBER_OF_PORTS) \
-  { \
-      return IX_ETH_DB_INVALID_PORT; \
-  } \
-  \
-  if (!ixEthDBPortInfo[(portID)].enabled) \
-  { \
-      return IX_ETH_DB_PORT_UNINITIALIZED; \
-  } \
-}
-
-/**
- * @def IX_ETH_DB_CHECK_PORT_ALL(portID)
- * @brief safety checks to verify whether the port is invalid or uninitialized; 
- * tolerates the use of IX_ETH_DB_ALL_PORTS
- */
-#define IX_ETH_DB_CHECK_PORT_ALL(portID) \
-{ \
-  if ((portID) != IX_ETH_DB_ALL_PORTS) \
-    IX_ETH_DB_CHECK_PORT(portID) \
-}
-
-#endif /* IxEthDBPortDefs_H */
-/**
- *@}
- */
diff --git a/arch/arm/cpu/ixp/npe/include/IxEthDBQoS.h b/arch/arm/cpu/ixp/npe/include/IxEthDBQoS.h
deleted file mode 100644
index 6d34889..0000000
--- a/arch/arm/cpu/ixp/npe/include/IxEthDBQoS.h
+++ /dev/null
@@ -1,154 +0,0 @@
-/**
- * @file IxEthDBQoS.h
- *
- * @brief Public definitions for QoS traffic classes
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- * 
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- * 
- * @par
- * -- End of Copyright Notice --
- */
-
-/**
- * @defgroup IxEthDBPortDefs IXP400 Ethernet QoS definitions
- *
- * @brief IXP00 Public definitions for QoS traffic classes
- *
- * @{
- */
-
-#ifndef IxEthDBQoS_H
-#define IxEthDBQoS_H
-
-/**
- * @def IX_ETH_DB_QUEUE_UNAVAILABLE
- * @brief alias to indicate a queue (traffic class) is not available
- */
-#define IX_ETH_DB_QUEUE_UNAVAILABLE  (0)
-
-#ifndef IX_IEEE802_1Q_QOS_PRIORITY_COUNT
-/**
- * @def IX_IEEE802_1Q_QOS_PRIORITY_COUNT
- * @brief number of QoS priorities, according to IEEE 802.1Q
- */
-#define IX_IEEE802_1Q_QOS_PRIORITY_COUNT (8)
-#endif
-
-/**
- * @brief array containing all the supported traffic class configurations
- */
-static const
-UINT8 ixEthDBQueueAssignments[][IX_IEEE802_1Q_QOS_PRIORITY_COUNT] = 
-{
-    { 4, 5, 6, 7, IX_ETH_DB_QUEUE_UNAVAILABLE, IX_ETH_DB_QUEUE_UNAVAILABLE, IX_ETH_DB_QUEUE_UNAVAILABLE, IX_ETH_DB_QUEUE_UNAVAILABLE },
-    { 15, 16, 17, 18, IX_ETH_DB_QUEUE_UNAVAILABLE, IX_ETH_DB_QUEUE_UNAVAILABLE, IX_ETH_DB_QUEUE_UNAVAILABLE, IX_ETH_DB_QUEUE_UNAVAILABLE },
-    { 11, 23, 26, IX_ETH_DB_QUEUE_UNAVAILABLE, IX_ETH_DB_QUEUE_UNAVAILABLE, IX_ETH_DB_QUEUE_UNAVAILABLE, IX_ETH_DB_QUEUE_UNAVAILABLE,  IX_ETH_DB_QUEUE_UNAVAILABLE },
-    { 4, 5, 6, 7, 8, 9, 10, 11 }
-    /* add here all other cases of queue configuration structures and update ixEthDBTrafficClassDefinitions to use them */
-};
-
-/**
- * @brief value used to index the NPE A functionality ID in the traffic class definition table
- */
-#define IX_ETH_DB_NPE_A_FUNCTIONALITY_ID_INDEX    (0)
-
-/**
- * @brief value used to index the traffic class count in the traffic class definition table
- */
-#define IX_ETH_DB_TRAFFIC_CLASS_COUNT_INDEX       (1)
-
-/**
- * @brief value used to index the queue assignment index in the traffic class definition table
- */
-#define IX_ETH_DB_QUEUE_ASSIGNMENT_INDEX          (2)
-
-/**
- * @brief traffic class definitions
- *
- * This array contains the default traffic class definition configuration,
- * as well as any special cases dictated by the functionality ID of NPE A.
- *
- * The default case should not be removed (otherwise the Ethernet
- * components will assert a fatal failure on initialization).
- */
-static const
-UINT8 ixEthDBTrafficClassDefinitions[][3] = 
-{
-    /* NPE A functionality ID | traffic class count | queue assignment index (points to the queue enumeration in ixEthDBQueueAssignments) */
-    {            0x00,                      4,                    0 }, /* default case - DO NOT REMOVE */
-    {            0x04,                      4,                    1 }, /* NPE A image ID 0.4.0.0 */
-    {            0x09,                      3,                    2 }, /* NPE A image ID 0.9.0.0 */
-    {            0x80,                      8,                    3 }, /* NPE A image ID 10.80.02.0 */
-    {            0x81,                      8,                    3 }, /* NPE A image ID 10.81.02.0 */
-    {            0x82,                      8,                    3 }  /* NPE A image ID 10.82.02.0 */
-};
-
-/**
- * @brief IEEE 802.1Q recommended QoS Priority => traffic class maps
- *
- * @verbatim
-                    Number of available traffic classes
-                    1 2 3 4 5 6 7 8
-    QoS Priority
-        0           0 0 0 1 1 1 1 2
-        1           0 0 0 0 0 0 0 0
-        2           0 0 0 0 0 0 0 1
-        3           0 0 0 1 1 2 2 3
-        4           0 1 1 2 2 3 3 4
-        5           0 1 1 2 3 4 4 5
-        6           0 1 2 3 4 5 5 6
-        7           0 1 2 3 4 5 6 7
-
-    @endverbatim
- */
-static const
-UINT8 ixEthIEEE802_1QUserPriorityToTrafficClassMapping[IX_IEEE802_1Q_QOS_PRIORITY_COUNT][IX_IEEE802_1Q_QOS_PRIORITY_COUNT] = 
- {
-     { 0, 0, 0, 0, 0, 0, 0, 0 }, /* 1 traffic class available */
-     { 0, 0, 0, 0, 1, 1, 1, 1 }, /* 2 traffic classes available */
-     { 0, 0, 0, 0, 1, 1, 2, 2 }, /* 3 traffic classes available */
-     { 1, 0, 0, 1, 2, 2, 3, 3 }, /* 4 traffic classes available */
-     { 1, 0, 0, 1, 2, 3, 4, 4 }, /* 5 traffic classes available */
-     { 1, 0, 0, 2, 3, 4, 5, 5 }, /* 6 traffic classes available */
-     { 1, 0, 0, 2, 3, 4, 5, 6 }, /* 7 traffic classes available */
-     { 2, 0, 1, 3, 4, 5, 6, 7 }  /* 8 traffic classes available */
- };
-
-#endif /* IxEthDBQoS_H */
-
-/**
- *@}
- */
diff --git a/arch/arm/cpu/ixp/npe/include/IxEthDB_p.h b/arch/arm/cpu/ixp/npe/include/IxEthDB_p.h
deleted file mode 100644
index ccec7ea..0000000
--- a/arch/arm/cpu/ixp/npe/include/IxEthDB_p.h
+++ /dev/null
@@ -1,710 +0,0 @@
-/**
- * @file IxEthDB_p.h
- *
- * @brief Private MAC learning API
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
- */
-
-#ifndef IxEthDB_p_H
-#define IxEthDB_p_H
-
-#include <IxTypes.h>
-#include <IxOsal.h>
-#include <IxEthDB.h>
-#include <IxNpeMh.h>
-#include <IxEthDBPortDefs.h>
-
-#include "IxEthDBMessages_p.h"
-#include "IxEthDBLog_p.h"
-
-#if (CPU==SIMSPARCSOLARIS)
-
-/* when running unit tests intLock() won't protect the event queue so we lock it manually */
-#define TEST_FIXTURE_LOCK_EVENT_QUEUE   { ixOsalMutexLock(&eventQueueLock, IX_OSAL_WAIT_FOREVER); }
-#define TEST_FIXTURE_UNLOCK_EVENT_QUEUE { ixOsalMutexUnlock(&eventQueueLock); }
-
-#else
-
-#define TEST_FIXTURE_LOCK_EVENT_QUEUE   /* nothing */
-#define TEST_FIXTURE_UNLOCK_EVENT_QUEUE /* nothing */
-
-#endif /* #if(CPU==SIMSPARCSOLARIS) */
-
-#ifndef IX_UNIT_TEST
-
-#define TEST_FIXTURE_INCREMENT_DB_CORE_ACCESS_COUNTER /* nothing */
-#define TEST_FIXTURE_MARK_OVERFLOW_EVENT              /* nothing */
-
-#else
-
-extern int dbAccessCounter;
-extern int overflowEvent;
-
-#define TEST_FIXTURE_INCREMENT_DB_CORE_ACCESS_COUNTER { dbAccessCounter++; }
-#define TEST_FIXTURE_MARK_OVERFLOW_EVENT              { overflowEvent = 1; }
-
-#endif
-
-/* code readability markers */
-#define __mempool__      /* memory pool marker */
-#define __lock__         /* hash write locking marker */
-#define __smartpointer__ /* smart pointer marker - warning: use only clone() when duplicating! */
-#define __alignment__    /* marker for data used only as alignment zones */
-
-/* constants */
-#define IX_ETH_DB_NPE_TIMEOUT (100) /* NPE response timeout, in ms */
-
-/**
- * number of hash table buckets
- * it should be at least 8x the predicted number of entries for performance
- * each bucket needs 8 bytes
- */
-#define NUM_BUCKETS (8192)
-
-/**
- * number of hash table buckets to preload when incrementing bucket iterator
- * = two cache lines
- */
-#define IX_ETHDB_CACHE_LINE_AHEAD (2)
-
-#define IX_ETHDB_BUCKETPTR_AHEAD  ((IX_ETHDB_CACHE_LINE_AHEAD * IX_OSAL_CACHE_LINE_SIZE)/sizeof(void *))
-
-#define IX_ETHDB_BUCKET_INDEX_MASK   (((IX_OSAL_CACHE_LINE_SIZE)/sizeof(void *)) - 1)
-
-/* locks */
-#define MAX_LOCKS (20) /**< maximum number of locks used simultaneously, do not tamper with */
-
-/* learning tree constants */
-#define INITIAL_ELT_SIZE    (8)                              /**< initial byte size of tree (empty unused root size) */
-#define MAX_ELT_SIZE        (512)                            /**< maximum number of entries (includes unused root) */
-#define MAX_GW_SIZE         (32)                             /**< maximum number of gateway entries (including unused root) */
-#define MAX_FW_SIZE         (32)                             /**< maximum number of firewall entries (including unused root) */
-#define ELT_ENTRY_SIZE      (8)                              /**< entry size, in bytes */
-#define ELT_ROOT_OFFSET     (ELT_ENTRY_SIZE)                 /**< tree root offset, in bytes - node preceeding root is unused */
-#define FULL_ELT_BYTE_SIZE  (MAX_ELT_SIZE * ELT_ENTRY_SIZE)  /**< full size of tree, in bytes, including unused root */
-#define FULL_GW_BYTE_SIZE   (MAX_GW_SIZE * ELT_ENTRY_SIZE)   /**< full size of gateway list, in bytes, including unused root */
-#define FULL_FW_BYTE_SIZE   (MAX_FW_SIZE * ELT_ENTRY_SIZE)   /**< full size of firewall table, in bytes, including unused root */
-
-/* maximum size of the VLAN table:
- * 4096 bits (one per VLAN)
- * 8 bits in one byte
- * interleaved VLAN membership and VLAN TTI (*2) */
-#define FULL_VLAN_BYTE_SIZE (4096 / 8 * 2)
-
-/* upper 9 bits used as set index, lower 3 bits as byte index */
-#define VLAN_SET_OFFSET(vlanID) ((vlanID) >> 3)
-#define VLAN_SET_MASK(vlanID)   (0x7 - ((vlanID) & 0x7))
-
-/* Update zone definitions */
-#define NPE_TREE_MEM_SIZE (4096) /* ((511 entries + 1 unused root) * 8 bytes/entry) */
-
-/* check the above value, we rely on 4k */
-#if NPE_TREE_MEM_SIZE != 4096
-    #error NPE_TREE_MEM_SIZE is not defined to 4096 bytes!
-#endif
-
-/* Size Filtering limits (Jumbo frame filtering) */
-#define IX_ETHDB_MAX_FRAME_SIZE     65535 /* other ports than NPE ports */
-#define IX_ETHDB_MIN_FRAME_SIZE         1 /* other ports than NPE ports */
-#define IX_ETHDB_MAX_NPE_FRAME_SIZE 16320 /* NPE ports firmware limit */
-#define IX_ETHDB_MIN_NPE_FRAME_SIZE     1 /* NPE ports firmware limit */
-#define IX_ETHDB_DEFAULT_FRAME_SIZE  1522
-
-/* memory management pool sizes  */
-
-/*
- * Note:
- *
- * NODE_POOL_SIZE controls the maximum number of elements in the database at any one time.
- * It should be large enough to cover all the search trees of all the ports simultaneously.
- *
- * MAC_POOL_SIZE should be higher than NODE_POOL_SIZE by at least the total number of MAC addresses
- * possible to be held at any time in all the ports.
- *
- * TREE_POOL_SIZE should follow the same guideline as for MAC_POOL_SIZE.
- *
- * The database structure described here (2000/4000/4000) is enough for two NPEs holding at most 511
- * entries each plus one PCI NIC holding at most 900 entries.
- */
-
-#define NODE_POOL_SIZE (2000) /**< number of HashNode objects - also master number of elements in the database; each entry has 16 bytes */
-#define MAC_POOL_SIZE  (4000) /**< number of MacDescriptor objects; each entry has 28 bytes */
-#define TREE_POOL_SIZE (4000) /**< number of MacTreeNode objects; each entry has 16 bytes */
-
-/* retry policies */
-#define BUSY_RETRY_ENABLED (TRUE)  /**< if set to TRUE the API will retry automatically calls returning BUSY */
-#define FOREVER_RETRY      (TRUE)  /**< if set to TRUE the API will retry forever BUSY calls */
-#define MAX_RETRIES        (400)   /**< upper retry limit - used only when FOREVER_RETRY is FALSE */
-#define BUSY_RETRY_YIELD   (5)     /**< ticks to yield for every failed retry */
-
-/* event management */
-#define EVENT_QUEUE_SIZE       (500) /**< size of the sink collecting events from the Message Handler FIFO */
-#define EVENT_PROCESSING_LIMIT (100)  /**< batch processing control size (how many events are extracted from the queue at once) */
-
-/* MAC descriptors */
-#define STATIC_ENTRY  (TRUE)
-#define DYNAMIC_ENTRY (FALSE)
-
-/* age reset on next maintenance - incrementing by 1 will reset to 0 */
-#define AGE_RESET (0xFFFFFFFF)
-
-/* dependency maps */
-#define EMPTY_DEPENDENCY_MAP (0)
-
-/* trees */
-#define RIGHT (1)
-#define LEFT  (-1)
-
-/* macros */
-#define IX_ETH_DB_CHECK_PORT_EXISTS(portID) \
-{ \
-    if ((portID) >= IX_ETH_DB_NUMBER_OF_PORTS) \
-    { \
-        return IX_ETH_DB_INVALID_PORT; \
-    } \
-}
-
-#define IX_ETH_DB_CHECK_PORT_INITIALIZED(portID) \
-{ \
-    if ((portID) >= IX_ETH_DB_NUMBER_OF_PORTS) \
-    { \
-        return IX_ETH_DB_INVALID_PORT; \
-    } \
-    else \
-    { \
-        if (!ixEthDBPortInfo[portID].initialized) \
-        { \
-            return IX_ETH_DB_PORT_UNINITIALIZED; \
-        } \
-    } \
-}
-
-/* single NPE check */
-#define IX_ETH_DB_CHECK_SINGLE_NPE(portID) \
-    if (ixEthDBSingleEthNpeCheck(portID) != IX_ETH_DB_SUCCESS) \
-    { \
-        WARNING_LOG("EthDB: port ID %d is unavailable\n",(UINT32) portID); \
-        \
-        return IX_ETH_DB_INVALID_PORT; \
-    }
-
-/* feature check */
-#define IX_ETH_DB_CHECK_FEATURE(portID, feature) \
-    if ((ixEthDBPortInfo[portID].featureStatus & feature) == 0) \
-    { \
-        return IX_ETH_DB_FEATURE_UNAVAILABLE; \
-    }
-
-/* busy retrying */
-#define BUSY_RETRY(functionCall) \
-    { \
-        UINT32 retries = 0; \
-        IxEthDBStatus br_result; \
-        \
-        while ((br_result = functionCall) == IX_ETH_DB_BUSY \
-            && BUSY_RETRY_ENABLED && (FOREVER_RETRY || ++retries < MAX_RETRIES)) { ixOsalSleep(BUSY_RETRY_YIELD); }; \
-        \
-        if ((!FOREVER_RETRY && retries == MAX_RETRIES) || (br_result == IX_ETH_DB_FAIL)) \
-        {\
-            ERROR_LOG("Ethernet Learning Database Error: BUSY_RETRY failed at %s:%d\n", __FILE__, __LINE__); \
-        }\
-    }
-
-#define BUSY_RETRY_WITH_RESULT(functionCall, brwr_result) \
-    { \
-        UINT32 retries = 0; \
-        \
-        while ((brwr_result = functionCall) == IX_ETH_DB_BUSY \
-            && BUSY_RETRY_ENABLED && (FOREVER_RETRY || ++retries < MAX_RETRIES)) { ixOsalSleep(BUSY_RETRY_YIELD); }; \
-        \
-        if ((!FOREVER_RETRY && retries == MAX_RETRIES) || (brwr_result == IX_ETH_DB_FAIL)) \
-        {\
-            ERROR_LOG("Ethernet Learning Database Error: BUSY_RETRY_WITH_RESULT failed at %s:%d\n", __FILE__, __LINE__); \
-        }\
-    }
-
-/* iterators */
-#define IS_ITERATOR_VALID(iteratorPtr) ((iteratorPtr)->node != NULL)
-
-/* dependency port maps */
-
-/* Warning: if port indexing starts from 1 replace (portID) with (portID - 1) in DEPENDENCY_MAP (and make sure IX_ETH_DB_NUMBER_OF_PORTS is big enough) */
-
-/* gives an empty dependency map */
-#define SET_EMPTY_DEPENDENCY_MAP(map)      { int i = 0; for (; i < 32 ; i++) map[i] = 0; }
-
-#define IS_EMPTY_DEPENDENCY_MAP(result, map)       { int i = 0 ; result = TRUE; for (; i < 32 ; i++) if (map[i] != 0) { result = FALSE; break; }}
-
-/**
- * gives a map consisting only of 'portID'
- */
-#define SET_DEPENDENCY_MAP(map, portID)    {SET_EMPTY_DEPENDENCY_MAP(map); map[portID >> 3] = 1 << (portID & 0x7);}
-
-/**
- * gives a map resulting from joining map1 and map2
- */
-#define JOIN_MAPS(map, map1, map2)         { int i = 0; for (; i < 32 ; i++) map[i] = map1[i] | map2[i]; }
-
-/**
- * gives the map resulting from joining portID and map
- */
-#define JOIN_PORT_TO_MAP(map, portID)      { map[portID >> 3] |= 1 << (portID & 0x7); }
-
-/**
- * gives the map resulting from excluding portID from map
- */
-#define EXCLUDE_PORT_FROM_MAP(map, portID) { map[portID >> 3] &= ~(1 << (portID & 0x7); }
-
-/**
- * returns TRUE if map1 is a subset of map2 and FALSE otherwise
- */
-#define IS_MAP_SUBSET(result, map1, map2)  { int i = 0; result = TRUE; for (; i < 32 ; i++) if ((map1[i] | map2[i]) != map2[i]) result = FALSE; }
-
-/**
- * returns TRUE is portID is part of map and FALSE otherwise
- */
-#define IS_PORT_INCLUDED(portID, map)      ((map[portID >> 3] & (1 << (portID & 0x7))) != 0)
-
-/**
- * returns the difference between map1 and map2 (ports included in map1 and not included in map2)
- */
-#define DIFF_MAPS(map, map1, map2)         { int i = 0; for (; i < 32 ; i++) map[i] = map1[i] ^ (map1[i] & map2[i]); }
-
-/**
- * returns TRUE if the maps collide (have at least one port in common) and FALSE otherwise
- */
-#define MAPS_COLLIDE(result, map1, map2)   { int i = 0; result = FALSE; for (; i < 32 ; i++) if ((map1[i] & map2[i]) != 0) result = TRUE; }
-
-/* size (number of ports) of a dependency map */
-#define GET_MAP_SIZE(map, size)            { int i = 0, b = 0; size = 0; for (; i < 32 ; i++) { char y = map[i]; for (; b < 8 && (y >>= 1); b++) size += (y & 1); }}
-
-/* copy map2 into map1 */
-#define COPY_DEPENDENCY_MAP(map1, map2)    { memcpy (map1, map2, sizeof (map1)); }
-
-/* definition of a port map size/port number which cannot be reached (we support at most 32 ports) */
-#define MAX_PORT_SIZE   (0xFF)
-#define MAX_PORT_NUMBER (0xFF)
-
-#define IX_ETH_DB_CHECK_REFERENCE(ptr)   { if ((ptr) == NULL) { return IX_ETH_DB_INVALID_ARG; } }
-#define IX_ETH_DB_CHECK_MAP(portID, map) { if (!IS_PORT_INCLUDED(portID, map)) { return IX_ETH_DB_INVALID_ARG; } }
-
-/* event queue macros */
-#define EVENT_QUEUE_WRAP(offset)            ((offset) >= EVENT_QUEUE_SIZE ? (offset) - EVENT_QUEUE_SIZE : (offset))
-
-#define CAN_ENQUEUE(eventQueuePtr)          ((eventQueuePtr)->length < EVENT_QUEUE_SIZE)
-
-#define QUEUE_HEAD(eventQueuePtr)           (&(eventQueuePtr)->queue[EVENT_QUEUE_WRAP((eventQueuePtr)->base + (eventQueuePtr)->length)])
-
-#define QUEUE_TAIL(eventQueuePtr)           (&(eventQueuePtr)->queue[(eventQueuePtr)->base])
-
-#define PUSH_UPDATE_QUEUE(eventQueuePtr)    { (eventQueuePtr)->length++; }
-
-#define SHIFT_UPDATE_QUEUE(eventQueuePtr) \
-        { \
-            (eventQueuePtr)->base = EVENT_QUEUE_WRAP((eventQueuePtr)->base + 1); \
-            (eventQueuePtr)->length--; \
-        }
-
-#define RESET_QUEUE(eventQueuePtr) \
-    { \
-        (eventQueuePtr)->base   = 0; \
-        (eventQueuePtr)->length = 0; \
-    }
-
-/* node stack macros - used to browse a tree without using a recursive function */
-#define NODE_STACK_INIT(stack)               { (stack)->nodeCount = 0; }
-#define NODE_STACK_PUSH(stack, node, offset) { (stack)->nodes[(stack)->nodeCount] = (node); (stack)->offsets[(stack)->nodeCount++] = (offset); }
-#define NODE_STACK_POP(stack, node, offset)  { (node) = (stack)->nodes[--(stack)->nodeCount]; offset = (stack)->offsets[(stack)->nodeCount]; }
-#define NODE_STACK_NONEMPTY(stack)           ((stack)->nodeCount != 0)
-
-#ifndef IX_NDEBUG
-#define IX_ETH_DB_NPE_MSG_HISTORY_DEPTH (100)
-#define LOG_NPE_MSG(msg) \
-    do { \
-        UINT32 npeMsgHistoryIndex = (npeMsgHistoryLen++) % IX_ETH_DB_NPE_MSG_HISTORY_DEPTH; \
-        npeMsgHistory[npeMsgHistoryIndex][0] = msg.data[0]; \
-        npeMsgHistory[npeMsgHistoryIndex][1] = msg.data[1]; \
-    } while (0);
-#else
-#define LOG_NPE_MSG() /* nothing */
-#endif
-
-/* ----------- Data -------------- */
-
-/* typedefs */
-
-typedef UINT32 (*HashFunction)(void *entity);
-typedef BOOL (*MatchFunction)(void *reference, void *entry);
-typedef void (*FreeFunction)(void *entry);
-
-/**
- * basic component of a hash table
- */
-typedef struct HashNode_t
-{
-    void *data;                                 /**< specific data */
-    struct HashNode_t *next;                    /**< used for bucket chaining */
-
-    __mempool__ struct HashNode_t *nextFree;    /**< memory pool management */
-
-    __lock__ IxOsalFastMutex lock;              /**< node lock */
-} HashNode;
-
-/**
- * @brief hash table iterator definition
- *
- * an iterator is an object which can be used
- * to browse a hash table
- */
-typedef struct
-{
-    UINT32 bucketIndex;     /**< index of the currently iterated bucket */
-    HashNode *previousNode; /**< reference to the previously iterated node within the current bucket */
-    HashNode *node;         /**< reference to the currently iterated node */
-} HashIterator;
-
-/**
- * definition of a MAC descriptor (a database record)
- */
-
-typedef enum
-{
-    IX_ETH_DB_WIFI_AP_TO_STA = 0x0,
-    IX_ETH_DB_WIFI_AP_TO_AP  = 0x1
-} IxEthDBWiFiRecordType;
-
-typedef union
-{
-    struct
-    {
-        UINT32 age;
-        BOOL staticEntry; /**< TRUE if this address is static (doesn't age) */
-    } filteringData;
-
-    struct
-    {
-        UINT32 age;
-        BOOL staticEntry;
-        UINT32 ieee802_1qTag;
-      } filteringVlanData;
-
-    struct
-    {
-        IxEthDBWiFiRecordType type;  /**< AP_TO_AP (0x1) or AP_TO_STA (0x0) */
-        UINT32 gwAddressIndex; /**< used only when linearizing the entries for NPE usage */
-        UINT8 gwMacAddress[IX_IEEE803_MAC_ADDRESS_SIZE];
-
-        __alignment__ UINT8 reserved2[2];
-    } wifiData;
-} IxEthDBRecordData;
-
-typedef struct MacDescriptor_t
-{
-    UINT8 macAddress[IX_IEEE803_MAC_ADDRESS_SIZE];
-
-    __alignment__ UINT8 reserved1[2];
-
-    UINT32 portID;
-    IxEthDBRecordType type;
-    IxEthDBRecordData recordData;
-
-    /* used for internal operations, such as NPE linearization */
-    void *internal;
-
-    /* custom user data */
-    void *user;
-
-    __mempool__ struct MacDescriptor_t *nextFree;   /**< memory pool management */
-    __smartpointer__ UINT32 refCount;               /**< smart pointer reference counter */
-} MacDescriptor;
-
-/**
- * hash table definition
- */
-typedef struct
-{
-    HashNode *hashBuckets[NUM_BUCKETS];
-    UINT32 numBuckets;
-
-    __lock__ IxOsalFastMutex bucketLocks[NUM_BUCKETS];
-
-    HashFunction entryHashFunction;
-    MatchFunction *matchFunctions;
-    FreeFunction freeFunction;
-} HashTable;
-
-typedef enum
-{
-    IX_ETH_DB_MAC_KEY       = 1,
-    IX_ETH_DB_MAC_PORT_KEY  = 2,
-    IX_ETH_DB_MAC_VLAN_KEY  = 3,
-    IX_ETH_DB_MAX_KEY_INDEX = 3
-} IxEthDBSearchKeyType;
-
-typedef struct MacTreeNode_t
-{
-    __smartpointer__  MacDescriptor *descriptor;
-    struct MacTreeNode_t *left, *right;
-
-    __mempool__ struct MacTreeNode_t *nextFree;
-} MacTreeNode;
-
-typedef IxEthDBStatus (*IxEthDBPortUpdateHandler)(IxEthDBPortId portID, IxEthDBRecordType type);
-
-typedef void (*IxEthDBNoteWriteFn)(void *address, MacTreeNode *node);
-
-typedef struct
-{
-    BOOL updateEnabled;                         /**< TRUE if updates are enabled for port */
-    BOOL userControlled;                        /**< TRUE if the user has manually used ixEthDBPortUpdateEnableSet */
-    BOOL treeInitialized;                       /**< TRUE if the NPE has received an initial tree */
-    IxEthDBPortUpdateHandler updateHandler;     /**< port update handler routine */
-    void *npeUpdateZone;                        /**< port update memory zone */
-    void *npeGwUpdateZone;                      /**< port update memory zone for gateways */
-    void *vlanUpdateZone;                       /**< port update memory zone for VLAN tables */
-    MacTreeNode *searchTree;                    /**< internal search tree, in MacTreeNode representation */
-    BOOL searchTreePendingWrite;                /**< TRUE if searchTree holds a tree pending write to the port */
-} PortUpdateMethod;
-
-typedef struct
-{
-    IxEthDBPortId portID;                   /**< port ID */
-    BOOL enabled;                           /**< TRUE if the port is enabled */
-    BOOL agingEnabled;                      /**< TRUE if aging on this port is enabled */
-    BOOL initialized;
-    IxEthDBPortMap dependencyPortMap;       /**< dependency port map for this port */
-    PortUpdateMethod updateMethod;          /**< update method structure */
-    BOOL macAddressUploaded;                /**< TRUE if the MAC address was uploaded into the port */
-    UINT32 maxRxFrameSize;                  /**< maximum Rx frame size for this port */
-    UINT32 maxTxFrameSize;                  /**< maximum Rx frame size for this port */
-
-    UINT8 bbsid[6];
-    __alignment__ UINT8 reserved[2];
-    UINT32 frameControlDurationID;          /**< Frame Control - Duration/ID WiFi control */
-
-    IxEthDBVlanTag vlanTag;                  /**< default VLAN tag for port */
-    IxEthDBPriorityTable priorityTable;     /**< QoS <=> internal priority mapping */
-    IxEthDBVlanSet vlanMembership;
-    IxEthDBVlanSet transmitTaggingInfo;
-    IxEthDBFrameFilter frameFilter;
-    IxEthDBTaggingAction taggingAction;
-
-    UINT32 npeFrameFilter;
-    UINT32 npeTaggingAction;
-
-    IxEthDBFirewallMode firewallMode;
-    BOOL srcAddressFilterEnabled;
-
-    BOOL stpBlocked;
-
-    IxEthDBFeature featureCapability;
-    IxEthDBFeature featureStatus;
-
-    UINT32 ixEthDBTrafficClassAQMAssignments[IX_IEEE802_1Q_QOS_PRIORITY_COUNT];
-
-    UINT32 ixEthDBTrafficClassCount;
-
-    UINT32 ixEthDBTrafficClassAvailable;
-
-
-
-    __lock__ IxOsalMutex npeAckLock;
-} PortInfo;
-
-/* list of port information structures indexed on port Ids */
-extern IX_ETH_DB_PUBLIC PortInfo ixEthDBPortInfo[IX_ETH_DB_NUMBER_OF_PORTS];
-
-typedef enum
-{
-    IX_ETH_DB_ADD_FILTERING_RECORD    = 0xFF0001,
-    IX_ETH_DB_REMOVE_FILTERING_RECORD = 0xFF0002
-} PortEventType;
-
-typedef struct
-{
-    UINT32 eventType;
-    IxEthDBPortId portID;
-    IxEthDBMacAddr macAddr;
-    BOOL staticEntry;
-} PortEvent;
-
-typedef struct
-{
-    PortEvent queue[EVENT_QUEUE_SIZE];
-    UINT32 base;
-    UINT32 length;
-} PortEventQueue;
-
-typedef struct
-{
-    IxEthDBPortId portID; /**< originating port */
-    MacDescriptor *macDescriptors[MAX_ELT_SIZE]; /**< addresses to be synced into db */
-    UINT32 addressCount; /**< number of addresses */
-} TreeSyncInfo;
-
-typedef struct
-{
-    MacTreeNode *nodes[MAX_ELT_SIZE];
-    UINT32 offsets[MAX_ELT_SIZE];
-    UINT32 nodeCount;
-} MacTreeNodeStack;
-
-/* Prototypes */
-
-/* ----------- Memory management -------------- */
-
-IX_ETH_DB_PUBLIC void ixEthDBInitMemoryPools(void);
-
-IX_ETH_DB_PUBLIC HashNode* ixEthDBAllocHashNode(void);
-IX_ETH_DB_PUBLIC void ixEthDBFreeHashNode(HashNode *);
-
-IX_ETH_DB_PUBLIC __smartpointer__ MacDescriptor* ixEthDBAllocMacDescriptor(void);
-IX_ETH_DB_PUBLIC __smartpointer__ MacDescriptor* ixEthDBCloneMacDescriptor(MacDescriptor *macDescriptor);
-IX_ETH_DB_PUBLIC __smartpointer__ void ixEthDBFreeMacDescriptor(MacDescriptor *);
-
-IX_ETH_DB_PUBLIC __smartpointer__ MacTreeNode* ixEthDBAllocMacTreeNode(void);
-IX_ETH_DB_PUBLIC __smartpointer__ MacTreeNode* ixEthDBCloneMacTreeNode(MacTreeNode *);
-IX_ETH_DB_PUBLIC __smartpointer__ void ixEthDBFreeMacTreeNode(MacTreeNode *);
-
-IX_ETH_DB_PUBLIC void ixEthDBPoolFreeMacTreeNode(MacTreeNode *);
-IX_ETH_DB_PUBLIC UINT32 ixEthDBSearchTreeUsageGet(MacTreeNode *tree);
-IX_ETH_DB_PUBLIC int ixEthDBShowMemoryStatus(void);
-
-/* Hash Table */
-IX_ETH_DB_PUBLIC void ixEthDBInitHash(HashTable *hashTable, UINT32 numBuckets, HashFunction entryHashFunction, MatchFunction *matchFunctions, FreeFunction freeFunction);
-
-IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBAddHashEntry(HashTable *hashTable, void *entry);
-IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBRemoveHashEntry(HashTable *hashTable, int keyType, void *reference);
-IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBSearchHashEntry(HashTable *hashTable, int keyType, void *reference, HashNode **searchResult);
-IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBPeekHashEntry(HashTable *hashTable, int keyType, void *reference);
-IX_ETH_DB_PUBLIC void ixEthDBReleaseHashNode(HashNode *node);
-
-IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBInitHashIterator(HashTable *hashTable, HashIterator *iterator);
-IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBIncrementHashIterator(HashTable *hashTable, HashIterator *iterator);
-IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBRemoveEntryAtHashIterator(HashTable *hashTable, HashIterator *iterator);
-IX_ETH_DB_PUBLIC void ixEthDBReleaseHashIterator(HashIterator *iterator);
-
-/* API Support */
-IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBPortAddressSet(IxEthDBPortId portID, IxEthDBMacAddr *macAddr);
-IX_ETH_DB_PUBLIC void ixEthDBMaximumFrameSizeAckCallback(IxNpeMhNpeId npeID, IxNpeMhMessage msg);
-
-/* DB Core functions */
-IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBInit(void);
-IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBAdd(MacDescriptor *newRecordTemplate, IxEthDBPortMap updateTrigger);
-IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBRemove(MacDescriptor *templateRecord, IxEthDBPortMap updateTrigger);
-IX_ETH_DB_PUBLIC HashNode* ixEthDBSearch(IxEthDBMacAddr *macAddress, IxEthDBRecordType typeFilter);
-IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBPeek(IxEthDBMacAddr *macAddress, IxEthDBRecordType typeFilter);
-
-/* Learning support */
-IX_ETH_DB_PUBLIC UINT32 ixEthDBAddressCompare(UINT8 *mac1, UINT8 *mac2);
-IX_ETH_DB_PUBLIC BOOL ixEthDBAddressMatch(void *reference, void *entry);
-IX_ETH_DB_PUBLIC UINT32 ixEthDBEntryXORHash(void *macDescriptor);
-IX_ETH_DB_PUBLIC UINT32 ixEthDBKeyXORHash(void *macAddress);
-
-/* Port updates */
-IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBNPEUpdateHandler(IxEthDBPortId portID, IxEthDBRecordType type);
-IX_ETH_DB_PUBLIC void ixEthDBUpdatePortLearningTrees(IxEthDBPortMap triggerPorts);
-IX_ETH_DB_PUBLIC void ixEthDBNPEAccessRequest(IxEthDBPortId portID);
-IX_ETH_DB_PUBLIC void ixEthDBUpdateLock(void);
-IX_ETH_DB_PUBLIC void ixEthDBUpdateUnlock(void);
-IX_ETH_DB_PUBLIC MacTreeNode* ixEthDBQuery(MacTreeNode *searchTree, IxEthDBPortMap query, IxEthDBRecordType recordFilter, UINT32 maximumEntries);
-IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBFirewallUpdate(IxEthDBPortId portID, void *address, UINT32 epDelta);
-
-/* Init/unload */
-IX_ETH_DB_PUBLIC void ixEthDBPortSetAckCallback(IxNpeMhNpeId npeID, IxNpeMhMessage msg);
-IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBEventProcessorInit(void);
-IX_ETH_DB_PUBLIC void ixEthDBPortInit(IxEthDBPortId portID);
-IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBPortEnable(IxEthDBPortId portID);
-IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBPortDisable(IxEthDBPortId portID);
-IX_ETH_DB_PUBLIC void ixEthDBNPEUpdateAreasInit(void);
-IX_ETH_DB_PUBLIC UINT32 ixEthDBMatchMethodsRegister(MatchFunction *matchFunctions);
-IX_ETH_DB_PUBLIC UINT32 ixEthDBRecordSerializeMethodsRegister(void);
-IX_ETH_DB_PUBLIC UINT32 ixEthDBUpdateTypeRegister(BOOL *typeArray);
-IX_ETH_DB_PUBLIC void ixEthDBNPEUpdateAreasUnload(void);
-IX_ETH_DB_PUBLIC void ixEthDBFeatureCapabilityScan(void);
-IX_ETH_DB_PUBLIC UINT32 ixEthDBKeyTypeRegister(UINT32 *keyType);
-
-/* Event processing */
-IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBDefaultEventCallbackEnable(IxEthDBPortId portID, BOOL enable);
-IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBTriggerAddPortUpdate(IxEthDBMacAddr *macAddr, IxEthDBPortId portID, BOOL staticEntry);
-IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBTriggerRemovePortUpdate(IxEthDBMacAddr *macAddr, IxEthDBPortId portID);
-IX_ETH_DB_PUBLIC void ixEthDBNPEEventCallback(IxNpeMhNpeId npeID, IxNpeMhMessage msg);
-
-/* NPE adaptor */
-IX_ETH_DB_PUBLIC void ixEthDBGetMacDatabaseCbk(IxNpeMhNpeId npeID, IxNpeMhMessage msg);
-IX_ETH_DB_PUBLIC void ixEthDBNpeMsgAck(IxNpeMhNpeId npeID, IxNpeMhMessage msg);
-IX_ETH_DB_PUBLIC void ixEthDBNPESyncScan(IxEthDBPortId portID, void *eltBaseAddress, UINT32 eltSize);
-IX_ETH_DB_PUBLIC void ixEthDBNPETreeWrite(IxEthDBRecordType type, UINT32 totalSize, void *baseAddress, MacTreeNode *tree, UINT32 *blocks, UINT32 *startIndex);
-IX_ETH_DB_PUBLIC void ixEthDBNPEGatewayNodeWrite(void *address, MacTreeNode *node);
-
-/* Other public API functions */
-IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBStartLearningFunction(void);
-IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBStopLearningFunction(void);
-IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBPortUpdateEnableSet(IxEthDBPortId portID, BOOL enableUpdate);
-
-/* Maximum Tx/Rx public functions */
-IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBFilteringPortMaximumRxFrameSizeSet(IxEthDBPortId portID, UINT32 maximumRxFrameSize);
-IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBFilteringPortMaximumTxFrameSizeSet(IxEthDBPortId portID, UINT32 maximumTxFrameSize);
-
-/* VLAN-related */
-IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBPortVlanTableSet(IxEthDBPortId portID, IxEthDBVlanSet portVlanTable, IxEthDBVlanSet vlanSet);
-
-/* Record search */
-IX_ETH_DB_PUBLIC BOOL ixEthDBAddressRecordMatch(void *untypedReference, void *untypedEntry);
-IX_ETH_DB_PUBLIC BOOL ixEthDBVlanRecordMatch(void *untypedReference, void *untypedEntry);
-IX_ETH_DB_PUBLIC BOOL ixEthDBPortRecordMatch(void *untypedReference, void *untypedEntry);
-IX_ETH_DB_PUBLIC BOOL ixEthDBNullMatch(void *reference, void *entry);
-IX_ETH_DB_PUBLIC HashNode* ixEthDBPortSearch(IxEthDBMacAddr *macAddress, IxEthDBPortId portID, IxEthDBRecordType typeFilter);
-IX_ETH_DB_PUBLIC HashNode* ixEthDBVlanSearch(IxEthDBMacAddr *macAddress, IxEthDBVlanId vlanID, IxEthDBRecordType typeFilter);
-
-/* Utilities */
-IX_ETH_DB_PUBLIC const char* mac2string(const unsigned char *mac);
-IX_ETH_DB_PUBLIC void showHashInfo(void);
-IX_ETH_DB_PUBLIC int ixEthDBAnalyzeHash(void);
-IX_ETH_DB_PUBLIC const char* errorString(IxEthDBStatus error);
-IX_ETH_DB_PUBLIC int numHashElements(void);
-IX_ETH_DB_PUBLIC void zapHashtable(void);
-IX_ETH_DB_PUBLIC BOOL ixEthDBCheckSingleBitValue(UINT32 value);
-
-/* Single Eth NPE Check */
-IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBSingleEthNpeCheck(IxEthDBPortId portId);
-
-#endif /* IxEthDB_p_H */
-
diff --git a/arch/arm/cpu/ixp/npe/include/IxEthMii.h b/arch/arm/cpu/ixp/npe/include/IxEthMii.h
deleted file mode 100644
index 397253a..0000000
--- a/arch/arm/cpu/ixp/npe/include/IxEthMii.h
+++ /dev/null
@@ -1,270 +0,0 @@
-/**
- * @file    IxEthMii.h
- *
- * @brief this file contains the public API of @ref IxEthMii component
- *
- * Design notes :  
- * The main intent of this API is to inplement MII high level fonctionalitoes
- * to support the codelets provided with the IXP400 software releases. It 
- * superceedes previous interfaces provided with @ref IxEThAcc component.
- * 
- * This API has been tested with the PHYs provided with the
- * IXP400 development platforms. It may not work for specific Ethernet PHYs
- * used on specific boards.
- *
- * This source code detects and interface the LXT972, LXT973 and KS6995
- * Ethernet PHYs.
- *
- * This source code should be considered as an example which may need
- * to be adapted for different hardware implementations.
- *
- * It is strongly recommended to use public domain and GPL utilities
- * like libmii, mii-diag for MII interface support.
- * 
- *
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- * 
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- * 
- * @par
- * -- End of Copyright Notice --
- */
-
-#ifndef IxEthMii_H
-#define IxEthMii_H
-
-#include <IxTypes.h>
-
-/**
- * @defgroup IxEthMii IXP400 Ethernet Phy Access (IxEthMii) API
- *
- * @brief ethMii is a library that does provides access to the 
- * Ethernet PHYs
- *
- *@{
- */
-
-/**
- * @ingroup IxEthMii
- *
- * @fn  ixEthMiiPhyScan(BOOL phyPresent[], UINT32 maxPhyCount)
- *
- * @brief Scan the MDIO bus for PHYs
- *  This function scans PHY addresses 0 through 31, and sets phyPresent[n] to 
- *  TRUE if a phy is discovered at address n. 
- *
- * - Reentrant    - no
- * - ISR Callable - no
- *
- * @pre The MAC on Ethernet Port 2 (NPE C) must be initialised, and generating the MDIO clock.
- *
- * @param phyPresent BOOL [in] - boolean array of IXP425_ETH_ACC_MII_MAX_ADDR entries
- * @param maxPhyCount UINT32 [in] - number of PHYs to search for (the scan will stop when
- *         the indicated number of PHYs is found).
- *
- * @return IX_STATUS
- * - IX_ETH_ACC_SUCCESS
- * - IX_ETH_ACC_FAIL : invalid arguments.
- *
- * <hr>
- */
-PUBLIC IX_STATUS ixEthMiiPhyScan(BOOL phyPresent[], UINT32 maxPhyCount);
-
-/**
- * @ingroup IxEthMii
- *
- * @fn ixEthMiiPhyConfig(UINT32 phyAddr,
-		         BOOL speed100, 
-			 BOOL fullDuplex, 
-			 BOOL autonegotiate)
- *
- *
- * @brief Configure a PHY
- *   Configure a PHY's speed, duplex and autonegotiation status
- *
- * - Reentrant    - no
- * - ISR Callable - no
- *
- * @pre The MAC on Ethernet Port 2 (NPE C) must be initialised, and generating the MDIO clock.
- *   
- * @param phyAddr UINT32 [in] 
- * @param speed100 BOOL [in] - set to TRUE for 100Mbit/s operation, FALSE for 10Mbit/s
- * @param fullDuplex BOOL [in] - set to TRUE for Full Duplex, FALSE for Half Duplex
- * @param autonegotiate BOOL [in] - set to TRUE to enable autonegotiation
- *
- * @return IX_STATUS
- * - IX_SUCCESS
- * - IX_FAIL : invalid arguments.
- *
- * <hr>
- */
-PUBLIC IX_STATUS ixEthMiiPhyConfig(UINT32 phyAddr,
-				    BOOL speed100, 
-				    BOOL fullDuplex, 
-				    BOOL autonegotiate);
-
-/**
- * @ingroup IxEthMii
- *
- * @fn ixEthMiiPhyLoopbackEnable(UINT32 phyAddr)
- *
- *
- * @brief Enable PHY Loopback in a specific Eth MII port
- *
- * @note When PHY Loopback is enabled, frames sent out to the PHY from the
- * IXP400 will be looped back to the IXP400. They will not be transmitted out
- * on the wire.
- *
- * - Reentrant    - no
- * - ISR Callable - no
- *
- * @param phyAddr UINT32 [in] - the address of the Ethernet PHY (0-31)
- *
- * @return IX_STATUS
- * - IX_SUCCESS
- * - IX_FAIL : invalid arguments.
- * <hr>
- */
-PUBLIC IX_STATUS
-ixEthMiiPhyLoopbackEnable (UINT32 phyAddr);
-
-/**
- * @ingroup IxEthMii
- *
- * @fn ixEthMiiPhyLoopbackDisable(UINT32 phyAddr)
- *
- *
- * @brief Disable PHY Loopback in a specific Eth MII port
- *
- * - Reentrant    - no
- * - ISR Callable - no
- *   
- * @param phyAddr UINT32 [in] - the address of the Ethernet PHY (0-31)
- *
- * @return IX_STATUS
- * - IX_SUCCESS
- * - IX_FAIL : invalid arguments.
- * <hr>
- */
-PUBLIC IX_STATUS
-ixEthMiiPhyLoopbackDisable (UINT32 phyAddr);
-
-/**
- * @ingroup IxEthMii
- *
- * @fn ixEthMiiPhyReset(UINT32 phyAddr)
- *
- * @brief Reset a PHY
- *   Reset a PHY
- *
- * - Reentrant    - no
- * - ISR Callable - no
- *
- * @pre The MAC on Ethernet Port 2 (NPE C) must be initialised, and generating the MDIO clock.
- *   
- * @param phyAddr UINT32 [in] - the address of the Ethernet PHY (0-31)
- *
- * @return IX_STATUS
- * - IX_SUCCESS
- * - IX_FAIL : invalid arguments.
- *
- * <hr>
- */
-PUBLIC IX_STATUS ixEthMiiPhyReset(UINT32 phyAddr);
-
-
-/**
- * @ingroup IxEthMii
- *
- * @fn ixEthMiiLinkStatus(UINT32 phyAddr, 
-			  BOOL *linkUp,
-			  BOOL *speed100, 
-			  BOOL *fullDuplex,
-		          BOOL *autoneg)
- *
- * @brief Retrieve the current status of a PHY
- *   Retrieve the link, speed, duplex and autonegotiation status of a PHY
- *
- * - Reentrant    - no
- * - ISR Callable - no
- *
- * @pre The MAC on Ethernet Port 2 (NPE C) must be initialised, and generating the MDIO clock.
- *   
- * @param phyAddr UINT32 [in] - the address of the Ethernet PHY (0-31)
- * @param linkUp BOOL [out] - set to TRUE if the link is up
- * @param speed100 BOOL [out] - set to TRUE indicates 100Mbit/s, FALSE indicates 10Mbit/s
- * @param fullDuplex BOOL [out] - set to TRUE indicates Full Duplex, FALSE indicates Half Duplex
- * @param autoneg BOOL [out] - set to TRUE indicates autonegotiation is enabled, FALSE indicates autonegotiation is disabled
- *
- * @return IX_STATUS
- * - IX_SUCCESS
- * - IX_FAIL : invalid arguments.
- *
- * <hr>
- */
-PUBLIC IX_STATUS ixEthMiiLinkStatus(UINT32 phyAddr, 
-				     BOOL *linkUp,
-				     BOOL *speed100, 
-				     BOOL *fullDuplex,
-				     BOOL *autoneg);
-
-/**
- * @ingroup IxEthMii
- *
- * @fn ixEthMiiPhyShow (UINT32 phyAddr)
- *
- *
- * @brief Display information on a specified PHY
- *   Display link status, speed, duplex and Auto Negotiation status
- *
- * - Reentrant    - no
- * - ISR Callable - no
- *
- * @pre The MAC on Ethernet Port 2 (NPE C) must be initialised, and generating the MDIO clock.
- *   
- * @param phyAddr UINT32 [in] - the address of the Ethernet PHY (0-31)
- *
- * @return IX_STATUS
- * - IX_SUCCESS
- * - IX_FAIL : invalid arguments.
- *
- * <hr>
- */
-PUBLIC IX_STATUS ixEthMiiPhyShow (UINT32 phyAddr);
-
-#endif /* ndef IxEthMii_H */
-/**
- *@}
- */
diff --git a/arch/arm/cpu/ixp/npe/include/IxEthMii_p.h b/arch/arm/cpu/ixp/npe/include/IxEthMii_p.h
deleted file mode 100644
index 104b65c..0000000
--- a/arch/arm/cpu/ixp/npe/include/IxEthMii_p.h
+++ /dev/null
@@ -1,185 +0,0 @@
-/**
- * @file IxEthMii_p.h
- *
- * @author Intel Corporation
- * @date 
- *
- * @brief  MII Header file
- *
- * Design Notes:
- *
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- * 
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- * 
- * @par
- * -- End of Copyright Notice --
- */
-
-#ifndef IxEthMii_p_H
-#define IxEthMii_p_H
-
-
-/* MII definitions - these have been verified against the LXT971 and
- LXT972 PHYs*/
-
-#define IX_ETH_MII_MAX_REG_NUM  0x20  /* max number of registers */
-
-#define IX_ETH_MII_CTRL_REG     0x0	/* Control Register */
-#define IX_ETH_MII_STAT_REG	0x1	/* Status Register */
-#define IX_ETH_MII_PHY_ID1_REG  0x2	/* PHY identifier 1 Register */
-#define IX_ETH_MII_PHY_ID2_REG  0x3	/* PHY identifier 2 Register */
-#define IX_ETH_MII_AN_ADS_REG   0x4	/* Auto-Negotiation 	  */
-					/* Advertisement Register */
-#define IX_ETH_MII_AN_PRTN_REG  0x5	/* Auto-Negotiation 	    */
-					/* partner ability Register */
-#define IX_ETH_MII_AN_EXP_REG   0x6	/* Auto-Negotiation   */
-					/* Expansion Register */
-#define IX_ETH_MII_AN_NEXT_REG  0x7	/* Auto-Negotiation 	       */
-					/* next-page transmit Register */
-
-#define IX_ETH_MII_STAT2_REG    0x11    /* Status Register 2*/
-
-
-/* MII control register bit  */
-
-#define IX_ETH_MII_CR_COLL_TEST  0x0080  /* collision test */
-#define IX_ETH_MII_CR_FDX	 0x0100  /* FDX =1, half duplex =0 */
-#define IX_ETH_MII_CR_RESTART    0x0200  /* restart auto negotiation */
-#define IX_ETH_MII_CR_ISOLATE    0x0400  /* isolate PHY from MII */
-#define IX_ETH_MII_CR_POWER_DOWN 0x0800  /* power down */
-#define IX_ETH_MII_CR_AUTO_EN    0x1000  /* auto-negotiation enable */
-#define IX_ETH_MII_CR_100	 0x2000  /* 0 = 10mb, 1 = 100mb */
-#define IX_ETH_MII_CR_LOOPBACK   0x4000  /* 0 = normal, 1 = loopback */
-#define IX_ETH_MII_CR_RESET	 0x8000  /* 0 = normal, 1 = PHY reset */
-#define IX_ETH_MII_CR_NORM_EN    0x0000  /* just enable the PHY */
-#define IX_ETH_MII_CR_DEF_0_MASK 0xca7f  /* they must return zero */
-#define IX_ETH_MII_CR_RES_MASK   0x007f  /* reserved bits, return zero */
-
-/* MII Status register bit definitions */
-
-#define IX_ETH_MII_SR_LINK_STATUS   0x0004 /* link Status -- 1 = link */
-#define IX_ETH_MII_SR_AUTO_SEL      0x0008 /* auto speed select capable */
-#define IX_ETH_MII_SR_REMOTE_FAULT  0x0010 /* Remote fault detect */
-#define IX_ETH_MII_SR_AUTO_NEG      0x0020 /* auto negotiation complete */
-#define IX_ETH_MII_SR_10T_HALF_DPX  0x0800 /* 10BaseT HD capable */
-#define IX_ETH_MII_SR_10T_FULL_DPX  0x1000 /* 10BaseT FD capable */
-#define IX_ETH_MII_SR_TX_HALF_DPX   0x2000 /* TX HD capable */
-#define IX_ETH_MII_SR_TX_FULL_DPX   0x4000 /* TX FD capable */
-#define IX_ETH_MII_SR_T4            0x8000 /* T4 capable */
-#define IX_ETH_MII_SR_ABIL_MASK     0xff80 /* abilities mask */
-#define IX_ETH_MII_SR_EXT_CAP       0x0001 /* extended capabilities */
-
-
-/* LXT971/2 Status 2 register bit definitions */
-#define IX_ETH_MII_SR2_100          0x4000
-#define IX_ETH_MII_SR2_TX           0x2000
-#define IX_ETH_MII_SR2_RX           0x1000
-#define IX_ETH_MII_SR2_COL          0x0800
-#define IX_ETH_MII_SR2_LINK         0x0400
-#define IX_ETH_MII_SR2_FD           0x0200
-#define IX_ETH_MII_SR2_AUTO         0x0100
-#define IX_ETH_MII_SR2_AUTO_CMPLT   0x0080
-#define IX_ETH_MII_SR2_POLARITY     0x0020
-#define IX_ETH_MII_SR2_PAUSE        0x0010
-#define IX_ETH_MII_SR2_ERROR        0x0008
-
-/* MII Link Code word  bit definitions */
-
-#define IX_ETH_MII_BP_FAULT	0x2000       	/* remote fault */
-#define IX_ETH_MII_BP_ACK	0x4000       	/* acknowledge */
-#define IX_ETH_MII_BP_NP	0x8000       	/* nexp page is supported */
-
-/* MII Next Page bit definitions */
-
-#define IX_ETH_MII_NP_TOGGLE 0x0800       	/* toggle bit */
-#define IX_ETH_MII_NP_ACK2	 0x1000       	/* acknowledge two */
-#define IX_ETH_MII_NP_MSG	 0x2000       	/* message page */
-#define IX_ETH_MII_NP_ACK1	 0x4000       	/* acknowledge one */
-#define IX_ETH_MII_NP_NP	 0x8000       	/* nexp page will follow */
-
-/* MII Expansion Register bit definitions */
-
-#define IX_ETH_MII_EXP_FAULT    0x0010  /* parallel detection fault */
-#define IX_ETH_MII_EXP_PRTN_NP  0x0008  /* link partner next-page able */
-#define IX_ETH_MII_EXP_LOC_NP   0x0004  /* local PHY next-page able */
-#define IX_ETH_MII_EXP_PR	    0x0002  /* full page received */
-#define IX_ETH_MII_EXP_PRT_AN   0x0001  /* link partner auto neg able */
-
-/* technology ability field bit definitions */
-
-#define IX_ETH_MII_TECH_10BASE_T	  0x0020  /* 10Base-T */
-#define IX_ETH_MII_TECH_10BASE_FD	  0x0040  /* 10Base-T Full Duplex */
-#define IX_ETH_MII_TECH_100BASE_TX	  0x0080  /* 100Base-TX */
-#define IX_ETH_MII_TECH_100BASE_TX_FD 0x0100  /* 100Base-TX Full Duplex */
-
-#define IX_ETH_MII_TECH_100BASE_T4	0x0200	/* 100Base-T4 */
-#define IX_ETH_MII_ADS_TECH_MASK	0x1fe0	/* technology abilities mask */
-#define IX_ETH_MII_TECH_MASK	IX_ETH_MII_ADS_TECH_MASK
-#define IX_ETH_MII_ADS_SEL_MASK	0x001f	/* selector field mask */
-
-#define IX_ETH_MII_AN_FAIL     0x10    /* auto-negotiation fail */
-#define IX_ETH_MII_STAT_FAIL   0x20    /* errors in the status register */
-#define IX_ETH_MII_PHY_NO_ABLE 0x40    /* the PHY lacks some abilities */
-
-/* Definitions for MII access routines*/
-
-#define IX_ETH_MII_GO                  BIT(31)
-#define IX_ETH_MII_WRITE               BIT(26)
-#define IX_ETH_MII_TIMEOUT_10TH_SECS       (5)    
-#define IX_ETH_MII_10TH_SEC_IN_MILLIS    (100)              
-#define IX_ETH_MII_READ_FAIL           BIT(31)
-
-/* When we reset the PHY we delay for 2 seconds to allow the reset to 
-   complete*/
-#define IX_ETH_MII_RESET_DELAY_MS  (2000)     
-#define IX_ETH_MII_RESET_POLL_MS     (50)
-
-#define IX_ETH_MII_REG_SHL    16
-#define IX_ETH_MII_ADDR_SHL   21
-
-/* supported PHYs */
-#define IX_ETH_MII_LXT971_PHY_ID	0x001378E0
-#define IX_ETH_MII_LXT972_PHY_ID	0x001378E2
-#define IX_ETH_MII_LXT973_PHY_ID	0x00137A10
-#define IX_ETH_MII_LXT973A3_PHY_ID	0x00137A11
-#define IX_ETH_MII_KS8995_PHY_ID	0x00221450
-#define IX_ETH_MII_LXT9785_PHY_ID	0x001378FF	
-
-
-#define IX_ETH_MII_INVALID_PHY_ID 0x00000000
-#define IX_ETH_MII_UNKNOWN_PHY_ID 0xffffffff
-
-#endif  /*IxEthAccMii_p_H*/
diff --git a/arch/arm/cpu/ixp/npe/include/IxEthNpe.h b/arch/arm/cpu/ixp/npe/include/IxEthNpe.h
deleted file mode 100644
index 21bdedc..0000000
--- a/arch/arm/cpu/ixp/npe/include/IxEthNpe.h
+++ /dev/null
@@ -1,695 +0,0 @@
-#ifndef __doxygen_HIDE  /* This file is not part of the API */
-
-/**
- * @file IxEthNpe.h
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- * 
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- * 
- * @par
- * -- End of Copyright Notice --
-*/
-
-/**
- * @defgroup IxEthNpe IXP400 Ethernet NPE (IxEthNpe) API
- *
- * @brief Contains the API for Ethernet NPE.
- * 
- * All messages given to NPE, get back an acknowledgment. The acknowledgment 
- * is identical to the message sent to the NPE (except for NPE_GETSTATUS message).
- *
- * @{
- */
-
-
-/*--------------------------------------------------------------------------
- * APB Message IDs - XScale->NPE
- *------------------------------------------------------------------------*/
-
-/**
- * @def IX_ETHNPE_NPE_GETSTATUS
- *
- * @brief Request from the XScale client for the NPE to return the firmware
- * version of the currently executing image.
- *
- * Acknowledgment message id is same as the request message id. 
- * NPE returns the firmware version ID to XScale.
- */
-#define IX_ETHNPE_NPE_GETSTATUS                 0x00
-
-/**
- * @def IX_ETHNPE_EDB_SETPORTADDRESS
- *
- * @brief Request from the XScale client for the NPE to set the Ethernet 
- * port's port ID and MAC address. 
- */
-#define IX_ETHNPE_EDB_SETPORTADDRESS            0x01
-
-/**
- * @def IX_ETHNPE_EDB_GETMACADDRESSDATABASE
- *
- * @brief Request from XScale client to the NPE requesting upload of 
- * Ethernet Filtering Database or Header Conversion Database from NPE's 
- * data memory to XScale accessible SDRAM.
- */
-#define IX_ETHNPE_EDB_GETMACADDRESSDATABASE     0x02
-
-/**
- * @def IX_ETHNPE_EDB_SETMACADDRESSSDATABASE
- *
- * @brief Request from XScale client to the NPE requesting download of 
- * Ethernet Filtering Database or Header Conversion Database from SDRAM
- * to the NPE's datamemory.
- */
-#define IX_ETHNPE_EDB_SETMACADDRESSSDATABASE    0x03
-
-/**
- * @def IX_ETHNPE_GETSTATS
- *
- * @brief Request from the XScale client for the current MAC port statistics 
- * data to be written to the (empty) statistics structure and the specified
- * location in externa memory.
- */
-#define IX_ETHNPE_GETSTATS                      0x04
-
-/**
- * @def IX_ETHNPE_RESETSTATS
- *
- * @brief Request from the XScale client to the NPE to reset all of its internal 
- * MAC port statistics state variables. 
- *
- * As a side effect, this message entails an implicit request that the NPE
- *  write the current MAC port statistics into the MAC statistics structure 
- * at the specified location in external memory.
- */
-#define IX_ETHNPE_RESETSTATS                    0x05
-
-/**
- * @def IX_ETHNPE_SETMAXFRAMELENGTHS
- *
- * @brief Request from the XScale client to the NPE to configure maximum framelengths
- * and block sizes in receive and transmit direction.
- */
-#define IX_ETHNPE_SETMAXFRAMELENGTHS            0x06
-
-/**
- * @def IX_ETHNPE_VLAN_SETRXTAGMODE
- *
- * @brief Request from the XScale client to the NPE to configure VLAN frame type
- * filtering and VLAN the tagging mode for the receiver.
- */
-#define IX_ETHNPE_VLAN_SETRXTAGMODE             0x07
-
-/**
- * @def IX_ETHNPE_VLAN_SETDEFAULTRXVID
- *
- * @brief Request from the XScale client to the NPE to set receiver's default 
- * VLAN tag (PVID)and internal traffic class.
- */
-#define IX_ETHNPE_VLAN_SETDEFAULTRXVID          0x08
-
-/**
- * @def IX_ETHNPE_VLAN_SETPORTVLANTABLEENTRY
- *
- * @brief Request from the XScale client to the NPE to configure VLAN Port 
- * membership and Tx tagging for 8 consecutive VLANID's.
- */
-#define IX_ETHNPE_VLAN_SETPORTVLANTABLEENTRY    0x09
-
-/**
- * @def IX_ETHNPE_VLAN_SETPORTVLANTABLERANGE
- *
- * @brief Request from the XScale client to the NPE to configure VLAN Port
- * membership and Tx tagging for a range of VLANID's.
- */
-#define IX_ETHNPE_VLAN_SETPORTVLANTABLERANGE    0x0A
-
-/**
- * @def IX_ETHNPE_VLAN_SETRXQOSENTRY
- *
- * @brief Request from the XScale client to the NPE to map a user priority
- * to QoS class and an AQM queue number.
- */
-#define IX_ETHNPE_VLAN_SETRXQOSENTRY            0x0B
-
-/**
- * @def IX_ETHNPE_VLAN_SETPORTIDEXTRACTIONMODE
- *
- * @brief Request from the XScale client to the NPE to enable or disable
- * portID extraction from VLAN-tagged frames for the specified port.
- */
-#define IX_ETHNPE_VLAN_SETPORTIDEXTRACTIONMODE  0x0C
-
-/**
- * @def IX_ETHNPE_STP_SETBLOCKINGSTATE
- *
- * @brief Request from the XScale client to the NPE to block or unblock
- * forwarding for spanning tree BPDUs.
- */
-#define IX_ETHNPE_STP_SETBLOCKINGSTATE          0x0D
-
-/**
- * @def IX_ETHNPE_FW_SETFIREWALLMODE
- *
- * @brief Request from the XScale client to the NPE to configure firewall
- * services modes of operation and/or download Ethernet Firewall Database from
- * SDRAM to NPE.
- */
-#define IX_ETHNPE_FW_SETFIREWALLMODE            0x0E
-
-/**
- * @def IX_ETHNPE_PC_SETFRAMECONTROLDURATIONID 
- *
- * @brief Request from the XScale client to the NPE to set global frame control
- * and duration/ID field for the 802.3 to 802.11 protocol header conversion
- * service.
- */
-#define IX_ETHNPE_PC_SETFRAMECONTROLDURATIONID  0x0F
-
-/**
- * @def IX_ETHNPE_PC_SETBBSID
- *
- * @brief Request from the XScale client to the NPE to set global BBSID field
- * value for the 802.3 to 802.11 protocol header conversion service. 
- */
-#define IX_ETHNPE_PC_SETBBSID                   0x10
-
-/**
- * @def IX_ETHNPE_PC_SETAPMACTABLE
- *
- * @brief Request from the XScale client to the NPE to update a block/section/
- * range of the AP MAC Address Table.
- */
-#define IX_ETHNPE_PC_SETAPMACTABLE              0x11
-
-/**
- * @def IX_ETHNPE_SETLOOPBACK_MODE
- *
- * @brief Turn on or off the NPE frame loopback.
- */
-#define IX_ETHNPE_SETLOOPBACK_MODE              (0x12)
-
-/*--------------------------------------------------------------------------
- * APB Message IDs - NPE->XScale
- *------------------------------------------------------------------------*/
-
-/**
- * @def IX_ETHNPE_NPE_GETSTATUS_ACK
- *
- * @brief Acknowledgment to IX_ETHNPE_NPE_GETSTATUS message. NPE firmware version 
- * id is returned in the message.
- */
-#define IX_ETHNPE_NPE_GETSTATUS_ACK                 0x00
-
-/**
- * @def IX_ETHNPE_EDB_SETPORTADDRESS_ACK
- *
- * @brief Acknowledgment to IX_ETHNPE_EDB_SETPORTADDRESS message.
- */
-#define IX_ETHNPE_EDB_SETPORTADDRESS_ACK            0x01
-
-/**
- * @def IX_ETHNPE_EDB_GETMACADDRESSDATABASE_ACK
- *
- * @brief Acknowledgment to IX_ETHNPE_EDB_GETMACADDRESSDATABASE message
- */
-#define IX_ETHNPE_EDB_GETMACADDRESSDATABASE_ACK     0x02
-
-/**
- * @def IX_ETHNPE_EDB_SETMACADDRESSSDATABASE_ACK
- *
- * @brief Acknowledgment to IX_ETHNPE_EDB_SETMACADDRESSSDATABASE message.
- */
-#define IX_ETHNPE_EDB_SETMACADDRESSSDATABASE_ACK    0x03
-
-/**
- * @def IX_ETHNPE_GETSTATS_ACK
- *
- * @brief Acknowledgment to IX_ETHNPE_GETSTATS message.
- */
-#define IX_ETHNPE_GETSTATS_ACK                      0x04
-
-/**
- * @def IX_ETHNPE_RESETSTATS_ACK
- *
- * @brief Acknowledgment to IX_ETHNPE_RESETSTATS message.
- */
-#define IX_ETHNPE_RESETSTATS_ACK                    0x05
-
-/**
- * @def IX_ETHNPE_SETMAXFRAMELENGTHS_ACK
- *
- * @brief Acknowledgment to IX_ETHNPE_SETMAXFRAMELENGTHS message.
- */
-#define IX_ETHNPE_SETMAXFRAMELENGTHS_ACK            0x06
-
-/**
- * @def IX_ETHNPE_VLAN_SETRXTAGMODE_ACK
- *
- * @brief Acknowledgment to IX_ETHNPE_VLAN_SETRXTAGMODE message.
- */
-#define IX_ETHNPE_VLAN_SETRXTAGMODE_ACK             0x07
-
-/**
- * @def IX_ETHNPE_VLAN_SETDEFAULTRXVID_ACK
- *
- * @brief Acknowledgment to IX_ETHNPE_VLAN_SETDEFAULTRXVID  message.
- */
-#define IX_ETHNPE_VLAN_SETDEFAULTRXVID_ACK          0x08
-
-/**
- * @def IX_ETHNPE_VLAN_SETPORTVLANTABLEENTRY_ACK
- *
- * @brief Acknowledgment to IX_ETHNPE_VLAN_SETPORTVLANTABLEENTRY message.
- */
-#define IX_ETHNPE_VLAN_SETPORTVLANTABLEENTRY_ACK    0x09
-
-/**
- * @def IX_ETHNPE_VLAN_SETPORTVLANTABLERANGE_ACK
- *
- * @brief Acknowledgment to IX_ETHNPE_VLAN_SETPORTVLANTABLERANGE message.
- */
-#define IX_ETHNPE_VLAN_SETPORTVLANTABLERANGE_ACK    0x0A
-
-/**
- * @def IX_ETHNPE_VLAN_SETRXQOSENTRY_ACK
- *
- * @brief Acknowledgment to IX_ETHNPE_VLAN_SETRXQOSENTRY message.
- */
-#define IX_ETHNPE_VLAN_SETRXQOSENTRY_ACK            0x0B
-
-/**
- * @def IX_ETHNPE_VLAN_SETPORTIDEXTRACTIONMODE_ACK
- *
- * @brief Acknowledgment to IX_ETHNPE_VLAN_SETPORTIDEXTRACTIONMODE message.
- */
-#define IX_ETHNPE_VLAN_SETPORTIDEXTRACTIONMODE_ACK  0x0C
-
-/**
- * @def IX_ETHNPE_STP_SETBLOCKINGSTATE_ACK
- *
- * @brief Acknowledgment to IX_ETHNPE_STP_SETBLOCKINGSTATE message.
- */
-#define IX_ETHNPE_STP_SETBLOCKINGSTATE_ACK          0x0D
-
-/**
- * @def IX_ETHNPE_FW_SETFIREWALLMODE_ACK
- *
- * @brief Acknowledgment to IX_ETHNPE_FW_SETFIREWALLMODE message. 
- */
-#define IX_ETHNPE_FW_SETFIREWALLMODE_ACK            0x0E
-
-/**
- * @def IX_ETHNPE_PC_SETFRAMECONTROLDURATIONID_ACK
- *
- * @brief Acknowledgment to IX_ETHNPE_PC_SETFRAMECONTROLDURATIONID message.
- */
-#define IX_ETHNPE_PC_SETFRAMECONTROLDURATIONID_ACK  0x0F
-
-/**
- * @def IX_ETHNPE_PC_SETBBSID_ACK
- *
- * @brief Acknowledgment to IX_ETHNPE_PC_SETBBSID message.
- */
-#define IX_ETHNPE_PC_SETBBSID_ACK                   0x10
-
-/**
- * @def IX_ETHNPE_PC_SETAPMACTABLE_ACK
- *
- * @brief Acknowledgment to IX_ETHNPE_PC_SETAPMACTABLE message.
- */
-#define IX_ETHNPE_PC_SETAPMACTABLE_ACK              0x11
-
-/**
- * @def IX_ETHNPE_SETLOOPBACK_MODE_ACK
- *
- * @brief Acknowledgment to IX_ETHNPE_SETLOOPBACK_MODE message.
- */
-#define IX_ETHNPE_SETLOOPBACK_MODE_ACK              (0x12)
-
-/*--------------------------------------------------------------------------
- * Queue Manager Queue entry bit field boundary definitions
- *------------------------------------------------------------------------*/
-
-/**
- * @def MASK(hi,lo)
- *
- * @brief Macro for mask
- */
-#define MASK(hi,lo)                    (((1 << (1 + ((hi) - (lo)))) - 1) << (lo))
-
-/**
- * @def BITS(x,hi,lo)
- *
- * @brief Macro for bits
- */
-#define BITS(x,hi,lo)                  (((x) & MASK(hi,lo)) >> (lo))
-
-/**
- * @def IX_ETHNPE_QM_Q_RXENET_LENGTH_MASK
- *
- * @brief QMgr Queue LENGTH field mask
- */
-#define IX_ETHNPE_QM_Q_RXENET_LENGTH_MASK   0x3fff
-
-/**
- * @def IX_ETHNPE_QM_Q_FIELD_FLAG_R
- *
- * @brief QMgr Queue FLAG field right boundary
- */
-#define IX_ETHNPE_QM_Q_FIELD_FLAG_R             20
-
-/**
- * @def IX_ETHNPE_QM_Q_FIELD_FLAG_MASK
- *
- * @brief QMgr Queue FLAG field mask
- *
- * Multicast bit : BIT(4)
- * Broadcast bit : BIT(5)
- * IP bit        : BIT(6) (linux only)
- *
- */
-#ifdef __vxworks
-#define IX_ETHNPE_QM_Q_FIELD_FLAG_MASK           0x30
-#else
-#define IX_ETHNPE_QM_Q_FIELD_FLAG_MASK           0x70
-#endif
-
-
-/**
- * @def IX_ETHNPE_QM_Q_FIELD_NPEID_L
- *
- * @brief QMgr Queue NPE ID field left boundary
- */
-#define IX_ETHNPE_QM_Q_FIELD_NPEID_L            1
-
-/**
- * @def IX_ETHNPE_QM_Q_FIELD_NPEID_R
- *
- * @brief QMgr Queue NPE ID field right boundary
- */
-#define IX_ETHNPE_QM_Q_FIELD_NPEID_R            0
-
-/**
- * @def IX_ETHNPE_QM_Q_FIELD_PRIOR_L
- *
- * @brief QMgr Queue Priority field left boundary
- */
-#define IX_ETHNPE_QM_Q_FIELD_PRIOR_L            2
-
-/**
- * @def IX_ETHNPE_QM_Q_FIELD_PRIOR_R
- *
- * @brief QMgr Queue Priority field right boundary
- */
-#define IX_ETHNPE_QM_Q_FIELD_PRIOR_R            0
-
-/**
- * @def IX_ETHNPE_QM_Q_FIELD_ADDR_L 
- *
- * @brief QMgr Queue Address field left boundary
- */
-#define IX_ETHNPE_QM_Q_FIELD_ADDR_L             31
-
-/**
- * @def IX_ETHNPE_QM_Q_FIELD_ADDR_R
- *
- * @brief QMgr Queue Address field right boundary
- */
-#define IX_ETHNPE_QM_Q_FIELD_ADDR_R              5
-
-/*--------------------------------------------------------------------------
- * Queue Manager Queue entry bit field masks
- *------------------------------------------------------------------------*/
-
-/**
- * @def IX_ETHNPE_QM_Q_FREEENET_ADDR_MASK 
- *
- * @brief Macro to mask the Address field of the FreeEnet Queue Manager Entry
- */
-#define IX_ETHNPE_QM_Q_FREEENET_ADDR_MASK \
-            MASK (IX_ETHNPE_QM_Q_FIELD_ADDR_L, \
-                  IX_ETHNPE_QM_Q_FIELD_ADDR_R)
-
-/**
- * @def IX_ETHNPE_QM_Q_RXENET_NPEID_MASK  
- *
- * @brief Macro to mask the NPE ID field of the RxEnet Queue Manager Entry
- */
-#define IX_ETHNPE_QM_Q_RXENET_NPEID_MASK \
-            MASK (IX_ETHNPE_QM_Q_FIELD_NPEID_L, \
-                  IX_ETHNPE_QM_Q_FIELD_NPEID_R)
-
-/**
- * @def IX_ETHNPE_QM_Q_RXENET_ADDR_MASK 
- *
- * @brief Macro to mask the Mbuf Address field of the RxEnet Queue Manager Entry
- */
-#define IX_ETHNPE_QM_Q_RXENET_ADDR_MASK \
-            MASK (IX_ETHNPE_QM_Q_FIELD_ADDR_L, \
-                  IX_ETHNPE_QM_Q_FIELD_ADDR_R)
-
-/**
- * @def IX_ETHNPE_QM_Q_TXENET_PRIOR_MASK
- *
- * @brief Macro to mask the Priority field of the TxEnet Queue Manager Entry
- */
-#define IX_ETHNPE_QM_Q_TXENET_PRIOR_MASK \
-            MASK (IX_ETHNPE_QM_Q_FIELD_PRIOR_L, \
-                  IX_ETHNPE_QM_Q_FIELD_PRIOR_R)
-
-/**
- * @def IX_ETHNPE_QM_Q_TXENET_ADDR_MASK 
- *
- * @brief Macro to mask the Mbuf Address field of the TxEnet Queue Manager Entry
- */
-#define IX_ETHNPE_QM_Q_TXENET_ADDR_MASK \
-            MASK (IX_ETHNPE_QM_Q_FIELD_ADDR_L, \
-                  IX_ETHNPE_QM_Q_FIELD_ADDR_R)
-
-/**
- * @def IX_ETHNPE_QM_Q_TXENETDONE_NPEID_MASK 
- *
- * @brief Macro to mask the NPE ID field of the TxEnetDone Queue Manager Entry
- */
-#define IX_ETHNPE_QM_Q_TXENETDONE_NPEID_MASK \
-            MASK (IX_ETHNPE_QM_Q_FIELD_NPEID_L, \
-                  IX_ETHNPE_QM_Q_FIELD_NPEID_R)
-
-/**
- * @def IX_ETHNPE_QM_Q_TXENETDONE_ADDR_MASK 
- * 
- * @brief Macro to mask the Mbuf Address field of the TxEnetDone Queue Manager 
- * Entry
- */
-#define IX_ETHNPE_QM_Q_TXENETDONE_ADDR_MASK \
-            MASK (IX_ETHNPE_QM_Q_FIELD_ADDR_L, \
-                  IX_ETHNPE_QM_Q_FIELD_ADDR_R)
-
-/*--------------------------------------------------------------------------
- * Queue Manager Queue entry bit field value extraction macros
- *------------------------------------------------------------------------*/
-
-/**
- * @def IX_ETHNPE_QM_Q_FREEENET_ADDR_VAL(x)
- *
- * @brief Extraction macro for Address field of FreeNet Queue Manager Entry 
- *
- * Pointer to an mbuf buffer descriptor
- */
-#define IX_ETHNPE_QM_Q_FREEENET_ADDR_VAL(x) \
-            ((x) & IX_ETHNPE_QM_Q_FREEENET_ADDR_MASK)
-
-/**
- * @def IX_ETHNPE_QM_Q_RXENET_NPEID_VAL(x)
- *
- * @brief Extraction macro for NPE ID field of RxEnet Queue Manager Entry 
- *
- * Set to 0 for entries originating from the Eth0 NPE; 
- * Set to 1 for entries originating from the Eth1 NPE.
- */
-#define IX_ETHNPE_QM_Q_RXENET_NPEID_VAL(x) \
-            BITS (x, IX_ETHNPE_QM_Q_FIELD_NPEID_L, \
-                     IX_ETHNPE_QM_Q_FIELD_NPEID_R)
-
-/**
- * @def IX_ETHNPE_QM_Q_RXENET_PORTID_VAL(x)
- *
- * @brief Extraction macro for Port ID field of RxEnet Queue Manager Entry 
- *
- * 0-5: Assignable (by the XScale client) to any of the physical ports.
- * 6: It is reserved
- * 7: Indication that the NPE did not find the associated frame's destination MAC address within 
- * its internal filtering database.
- */
-#define IX_ETHNPE_QM_Q_RXENET_PORTID_VAL(x) \
-            BITS (x, IX_ETHNPE_QM_Q_FIELD_PORTID_L, \
-                     IX_ETHNPE_QM_Q_Field_PortID_R)
-
-/**
- * @def IX_ETHNPE_QM_Q_RXENET_ADDR_VAL(x)
- *
- * @brief Extraction macro for Address field of RxEnet Queue Manager Entry
- *
- * Pointer to an mbuf buffer descriptor
- */
-#define IX_ETHNPE_QM_Q_RXENET_ADDR_VAL(x) \
-            ((x) & IX_ETHNPE_QM_Q_RXENET_ADDR_MASK)
-
-/**
- * @def IX_ETHNPE_QM_Q_TXENET_PRIOR_VAL(x)
- *
- * @brief Extraction macro for Priority field of TxEnet Queue Manager Entry
- *
- * Priority of the packet (as described in IEEE 802.1D). This field is
- * cleared upon return from the Ethernet NPE to the TxEnetDone queue.
- */
-#define IX_ETHNPE_QM_Q_TXENET_PRIOR_VAL(x) \
-            BITS (x, IX_ETHNPE_QM_Q_FIELD_PRIOR_L, \
-                     IX_ETHNPE_QM_Q_FIELD_PRIOR_R)
-
-/**
- * @def IX_ETHNPE_QM_Q_TXENET_ADDR_VAL(x)
- *
- * @brief Extraction macro for Address field of Queue Manager TxEnet Queue 
- * Manager Entry
- *
- * Pointer to an mbuf buffer descriptor
- */
-#define IX_ETHNPE_QM_Q_TXENET_ADDR_VAL(x) \
-            ((x) & IX_ETHNPE_QM_Q_TXENET_ADDR_MASK)
-
-/**
- * @def IX_ETHNPE_QM_Q_TXENETDONE_NPEID_VAL(x)
- *
- * @brief Extraction macro for NPE ID field of TxEnetDone Queue Manager Entry
- *
- * Set to 0 for entries originating from the Eth0 NPE; set to 1 for en-tries 
- * originating from the Eth1 NPE.
- */
-#define IX_ETHNPE_QM_Q_TXENETDONE_NPEID_VAL(x) \
-            BITS (x, IX_ETHNPE_QM_Q_FIELD_NPEID_L, \
-                     IX_ETHNPE_QM_Q_FIELD_NPEID_R)
-
-/**
- * @def IX_ETHNPE_QM_Q_TXENETDONE_ADDR_VAL(x)
- *
- * @brief Extraction macro for Address field of TxEnetDone Queue Manager Entry
- *
- * Pointer to an mbuf buffer descriptor
- */
-#define IX_ETHNPE_QM_Q_TXENETDONE_ADDR_VAL(x) \
-            ((x) & IX_ETHNPE_QM_Q_TXENETDONE_ADDR_MASK)
-
-
-/*--------------------------------------------------------------------------
- * NPE limits
- *------------------------------------------------------------------------*/
-
-/**
- * @def IX_ETHNPE_ACC_RXFREE_BUFFER_LENGTH_MIN
- * 
- * @brief Macro to check the minimum length of a rx free buffer
- */
-#define IX_ETHNPE_ACC_RXFREE_BUFFER_LENGTH_MIN (64)
-
-/**
- * @def IX_ETHNPE_ACC_RXFREE_BUFFER_LENGTH_MASK
- * 
- * @brief Mask to apply to the mbuf length before submitting it to the NPE
- * (the NPE handles only rx free mbufs which are multiple of 64)
- * 
- * @sa IX_ETHNPE_ACC_RXFREE_BUFFER_LENGTH_MASK
- */
-#define IX_ETHNPE_ACC_RXFREE_BUFFER_LENGTH_MASK (~63)
-
-/**
- * @def IX_ETHNPE_ACC_RXFREE_BUFFER_ROUND_UP(size)
- * 
- * @brief  Round up to get the size necessary to receive without chaining
- * the frames which are (size) bytes (the NPE operates by multiple of 64)
- * e.g. To receive 1514 bytes frames, the size of the buffers in replenish
- * has to be at least (1514+63)&(~63) = 1536 bytes.
- *
- */
-#define IX_ETHNPE_ACC_RXFREE_BUFFER_ROUND_UP(size) (((size) + 63) & ~63)
-
-/**
- * @def IX_ETHNPE_ACC_RXFREE_BUFFER_ROUND_DOWN(size)
- *
- * @brief Round down to apply to the mbuf length before submitting
- * it to the NPE. (the NPE operates by multiple of 64)
- *
- */
-#define IX_ETHNPE_ACC_RXFREE_BUFFER_ROUND_DOWN(size) ((size) & ~63)
-
-/**
- * @def IX_ETHNPE_ACC_FRAME_LENGTH_MAX
- * 
- * @brief maximum mbuf length supported by the NPE
- * 
- * @sa IX_ETHNPE_ACC_FRAME_LENGTH_MAX
- */
-#define IX_ETHNPE_ACC_FRAME_LENGTH_MAX (16320)
-
-/**
- * @def IX_ETHNPE_ACC_FRAME_LENGTH_DEFAULT
- * 
- * @brief default mbuf length supported by the NPE
- * 
- * @sa IX_ETHNPE_ACC_FRAME_LENGTH_DEFAULT
- */
-#define IX_ETHNPE_ACC_FRAME_LENGTH_DEFAULT (1522)
-
-/**
- * @def IX_ETHNPE_ACC_LENGTH_OFFSET
- *
- * @brief Offset of the cluster length field in the word shared with the NPEs
- */
-#define IX_ETHNPE_ACC_LENGTH_OFFSET 16
-
-/**
- * @def IX_ETHNPE_ACC_PKTLENGTH_MASK
- *
- * @brief Mask of the cluster length field in the word shared with the NPEs
- */
-#define IX_ETHNPE_ACC_PKTLENGTH_MASK 0x3fff
-
-
-/**
- *@}
- */
-
-#endif /* __doxygen_HIDE */
diff --git a/arch/arm/cpu/ixp/npe/include/IxFeatureCtrl.h b/arch/arm/cpu/ixp/npe/include/IxFeatureCtrl.h
deleted file mode 100644
index dabc38e..0000000
--- a/arch/arm/cpu/ixp/npe/include/IxFeatureCtrl.h
+++ /dev/null
@@ -1,742 +0,0 @@
-/**
- * @file IxFeatureCtrl.h
- *
- * @date 30-Jan-2003
-
- * @brief This file contains the public API of the IXP400 Feature Control
- *        component.
- *
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- * 
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- * 
- * @par
- * -- End of Copyright Notice --
-*/
-/* ------------------------------------------------------
-   Doxygen group definitions
-   ------------------------------------------------------ */
-/**
- * @defgroup IxFeatureCtrlAPI IXP400 Feature Control (IxFeatureCtrl) API
- *
- * @brief The Public API for the IXP400 Feature Control.
- * 
- * @{
- */
-
-#ifndef IXFEATURECTRL_H
-#define IXFEATURECTRL_H
-
-/*
- * User defined include files
- */
-#include "IxOsal.h"
-
-/*
- * #defines and macros
- */
-
-/*************************************************************
- * The following are IxFeatureCtrlComponentCheck return values.
- ************************************************************/
-
-/**
- * @ingroup IxFeatureCtrlAPI 
- *
- * @def  IX_FEATURE_CTRL_COMPONENT_DISABLED
- *
- * @brief Hardware Component is disabled/unavailable.
- *        Return status by ixFeatureCtrlComponentCheck()  
- */
-#define  IX_FEATURE_CTRL_COMPONENT_DISABLED 0
-
-/**
- * @ingroup IxFeatureCtrlAPI 
- *
- * @def  IX_FEATURE_CTRL_COMPONENT_ENABLED
- *
- * @brief Hardware Component is available. 
- *        Return status by ixFeatureCtrlComponentCheck()  
- */
-#define  IX_FEATURE_CTRL_COMPONENT_ENABLED  1
-
-/***********************************************************************************
- * Product ID in XScale CP15 - Register 0
- *  - It contains information on the maximum XScale Core Frequency and
- *    Silicon Stepping.  
- *  - XScale Core Frequency Id indicates only the maximum XScale frequency
- *    achievable and not the running XScale frequency (maybe stepped down).    
- *  - The register is read by using ixFeatureCtrlProductIdRead.
- *  - Usage example: 
- *          productId = ixFeatureCtrlProductIdRead();
- *          if( (productId & IX_FEATURE_CTRL_SILICON_STEPPING_MASK) == 
- *              IX_FEATURE_CTRL_SILICON_TYPE_A0 )
- *          if( (productId & IX_FEATURE_CTRL_XSCALE_FREQ_MASK) == 
- *              IX_FEATURE_CTRL_XSCALE_FREQ_533 )    
- * 
- *  31 28 27 24 23 20 19 16 15 12 11        9 8                   4 3              0  
- *  -------------------------------------------------------------------------------- 
- * | 0x6 | 0x9 | 0x0 | 0x5 | 0x4 | Device ID | XScale Core Freq Id | Si Stepping Id |    
- *  --------------------------------------------------------------------------------
- *
- *   Maximum Achievable XScale Core Frequency Id :  533MHz  - 0x1C 
- *                                                  400MHz  - 0x1D 
- *                                                  266MHz  - 0x1F
- *
- *   <b>THE CORE FREQUENCY ID IS NOT APPLICABLE TO IXP46X <\b>
- *  
- *   The above is applicable to IXP42X only. CP15 in IXP46X does not contain any
- *   Frequency ID. 
- * 
- *  Si Stepping Id            :  A       - 0x0    
- *                               B       - 0x1 
- *  
- *  XScale Core freq Id - Device ID [11:9] : IXP42X - 0x0
- *                                           IXP46X - 0x1
- *************************************************************************************/
-
-/**
- * @ingroup IxFeatureCtrlAPI 
- *
- * @def IX_FEATURE_CTRL_SILICON_TYPE_A0
- *
- * @brief This is the value of A0 Silicon in product ID. 
- */
-#define IX_FEATURE_CTRL_SILICON_TYPE_A0   0
-
-/**
- * @ingroup IxFeatureCtrlAPI 
- *
- * @def IX_FEATURE_CTRL_SILICON_TYPE_B0
- *
- * @brief This is the value of B0 Silicon in product ID.
- */
-#define IX_FEATURE_CTRL_SILICON_TYPE_B0   1
-
-/**
- * @ingroup IxFeatureCtrlAPI 
- *
- * @def IX_FEATURE_CTRL_SILICON_STEPPING_MASK
- *
- * @brief This is the mask of silicon stepping in product ID. 
- */
-#define IX_FEATURE_CTRL_SILICON_STEPPING_MASK  0xF 
-
-/**
- * @ingroup IxFeatureCtrlAPI
- *
- * @def IX_FEATURE_CTRL_DEVICE_TYPE_MASK
- *
- * @brief This is the mask of silicon stepping in product ID.
- */
-#define IX_FEATURE_CTRL_DEVICE_TYPE_MASK  (0x7) 
-
-/**
- * @ingroup IxFeatureCtrlAPI
- *
- * @def IX_FEATURE_CTRL_DEVICE_TYPE_OFFSET
- *
- * @brief This is the mask of silicon stepping in product ID.
- */
-#define IX_FEATURE_CTRL_DEVICE_TYPE_OFFSET  9
-
-
-/**
- * @ingroup IxFeatureCtrlAPI 
- *
- * @def IX_FEATURE_CTRL_XSCALE_FREQ_533
- *
- * @brief This is the value of 533MHz XScale Core in product ID.
- */
-#define IX_FEATURE_CTRL_XSCALE_FREQ_533  ((0x1C)<<4)
-
-/**
- * @ingroup IxFeatureCtrlAPI 
- *
- * @def IX_FEATURE_CTRL_XSCALE_FREQ_400
- *
- * @brief This is the value of 400MHz XScale Core in product ID.
- */
-#define IX_FEATURE_CTRL_XSCALE_FREQ_400  ((0x1D)<<4)
-
-/**
- * @ingroup IxFeatureCtrlAPI 
- *
- * @def IX_FEATURE_CTRL_XSCALE_FREQ_266
- *
- * @brief This is the value of 266MHz XScale Core in product ID.
- */
-#define IX_FEATURE_CTRL_XSCALE_FREQ_266 ((0x1F)<<4)   
-
-/**
- * @ingroup IxFeatureCtrlAPI 
- *
- * @def IX_FEATURE_CTRL_XSCALE_FREQ_MASK
- *
- * @brief This is the mask of XScale Core in product ID.
- */
-#define IX_FEATURE_CTRL_XSCALE_FREQ_MASK ((0xFF)<<4)  
-
-/**
- * @ingroup IxFeatureCtrlAPI 
- *
- * @def IX_FEATURECTRL_REG_UTOPIA_32PHY
- *
- * @brief Maximum  UTOPIA PHY available is 32.  
- * 
- */
-#define IX_FEATURECTRL_REG_UTOPIA_32PHY  0x0
-
-/**
- * @ingroup IxFeatureCtrlAPI 
- *
- * @def IX_FEATURECTRL_REG_UTOPIA_16PHY
- *
- * @brief Maximum  UTOPIA PHY available is 16.  
- * 
- */
-#define IX_FEATURECTRL_REG_UTOPIA_16PHY  0x1
-
-/**
- * @ingroup IxFeatureCtrlAPI 
- *
- * @def IX_FEATURECTRL_REG_UTOPIA_8PHY
- *
- * @brief Maximum  UTOPIA PHY available to is 8.  
- * 
- */
-#define IX_FEATURECTRL_REG_UTOPIA_8PHY   0x2
-
-/**
- * @ingroup IxFeatureCtrlAPI 
- *
- * @def IX_FEATURECTRL_REG_UTOPIA_4PHY
- *
- * @brief Maximum  UTOPIA PHY available to is 4.  
- * 
- */
-#define IX_FEATURECTRL_REG_UTOPIA_4PHY   0x3
-
-#ifdef __ixp46X
-
-/**
- * @ingroup IxFeatureCtrlAPI
- *
- * @def IX_FEATURECTRL_REG_XSCALE_533FREQ
- *
- * @brief Maximum  frequency available to IXP46x is 533 MHz.
- *
- */
-#define IX_FEATURECTRL_REG_XSCALE_533FREQ   0x0
-
-/**
- * @ingroup IxFeatureCtrlAPI
- *
- * @def IX_FEATURECTRL_REG_XSCALE_667FREQ
- *
- * @brief Maximum  frequency available to IXP46x is 667 MHz.
- *
- */
-#define IX_FEATURECTRL_REG_XSCALE_667FREQ   0x1
-
-/**
- * @ingroup IxFeatureCtrlAPI
- *
- * @def IX_FEATURECTRL_REG_XSCALE_400FREQ
- *
- * @brief Maximum  frequency available to IXP46x is 400 MHz.
- *
- */
-#define IX_FEATURECTRL_REG_XSCALE_400FREQ   0x2
-
-/**
- * @ingroup IxFeatureCtrlAPI
- *
- * @def IX_FEATURECTRL_REG_XSCALE_266FREQ
- *
- * @brief Maximum  frequency available to IXP46x is 266 MHz.
- *
- */
-#define IX_FEATURECTRL_REG_XSCALE_266FREQ   0x3
-
-#endif /* __ixp46X */
-
-/**
- * @ingroup IxFeatureCtrlAPI
- *
- * @def IX_FEATURECTRL_COMPONENT_NOT_AVAILABLE
- *
- * @brief Component selected is not available for device
- *
- */
-#define IX_FEATURECTRL_COMPONENT_NOT_AVAILABLE  0x0000
-
-/**
- * @ingroup IxFeatureCtrlAPI
- *
- * @def IX_FEATURECTRL_COMPONENT_ALWAYS_AVAILABLE
- *
- * @brief Component selected is not available for device
- *
- */
-#define IX_FEATURECTRL_COMPONENT_ALWAYS_AVAILABLE  0xffff
-
-/**
- * @defgroup IxFeatureCtrlSwConfig Software Configuration for Access Component
- *
- * @ingroup IxFeatureCtrlAPI 
- *
- * @brief This section describes software configuration in access component. The
- *        configuration can be changed at run-time. ixFeatureCtrlSwConfigurationCheck( )
- *        will be used across applicable access component to check the configuration.
- *        ixFeatureCtrlSwConfigurationWrite( ) is used to write the software configuration.
- *
- * @note <b>All software configurations are default to be enabled.</b> 
- *
- * @{
- */
-/**
- * @ingroup IxFeatureCtrlSwConfig
- *
- * @def IX_FEATURE_CTRL_SWCONFIG_DISABLED
- *
- * @brief Software configuration is disabled. 
- * 
- */
-#define IX_FEATURE_CTRL_SWCONFIG_DISABLED 0  
-
-/**
- * @ingroup IxFeatureCtrlSwConfig
- *
- * @def IX_FEATURE_CTRL_SWCONFIG_ENABLED
- *
- * @brief Software configuration is enabled. 
- * 
- */
-#define IX_FEATURE_CTRL_SWCONFIG_ENABLED 1  
-
-/**
- * Section for enums
- **/
-
-/**
- * @ingroup IxFeatureCtrlBuildDevice
- *
- * @enum IxFeatureCtrlBuildDevice
- *
- * @brief Indicates software build type.
- *
- * Default build type is IXP42X
- *
- */
-typedef enum
-{
-    IX_FEATURE_CTRL_SW_BUILD_IXP42X = 0, /**<Build type is IXP42X */
-    IX_FEATURE_CTRL_SW_BUILD_IXP46X      /**<Build type is IXP46X */
-} IxFeatureCtrlBuildDevice;
-
-/**
- * @ingroup IxFeatureCtrlSwConfig
- *
- * @enum IxFeatureCtrlSwConfig
- *
- * @brief Enumeration for software configuration in access components.
- *
- * Entry for new run-time software configuration should be added here.
- */
-typedef enum
-{
-    IX_FEATURECTRL_ETH_LEARNING = 0,       /**< EthDB Learning Feature */
-    IX_FEATURECTRL_ORIGB0_DISPATCHER,  /**< IXP42X B0 and IXP46X dispatcher without 
-                                            livelock prevention functionality Feature */
-    IX_FEATURECTRL_SWCONFIG_MAX        /**< Maximum boudary for IxFeatureCtrlSwConfig  */
-} IxFeatureCtrlSwConfig;
-
-
-/************************************************************************
- * IXP400 Feature Control Register
- * - It contains the information (available/unavailable) of IXP425&IXP46X
- *   hardware components in their corresponding bit location.
- * - Bit value of 0 means the hardware component is available
- *   or not software disabled. Hardware component that is available
- *   can be software disabled.
- * - Bit value of 1 means the hardware is unavailable or software
- *   disabled.Hardware component that is unavailable cannot be software
- *   enabled.
- * - Use ixFeatureCtrlHwCapabilityRead() to read the hardware component's
- *   availability.
- * - Use ixFeatureCtrlRead() to get the current IXP425/IXP46X feature control
- *   register value.
- *
- *   Bit            Field Description (Hardware Component Availability)
- *   ---            ---------------------------------------------------
- *    0             RComp Circuitry
- *    1             USB Controller
- *    2             Hashing Coprocessor
- *    3             AES Coprocessor
- *    4             DES Coprocessor
- *    5             HDLC Coprocessor
- *    6             AAL Coprocessor         - Always available in IXP46X
- *    7             HSS Coprocesspr
- *    8             Utopia Coprocessor
- *    9             Ethernet 0 Coprocessor
- *   10             Ethernet 1 Coprocessor
- *   11             NPE A
- *   12             NPE B
- *   13             NPE C
- *   14             PCI Controller
- *   15             ECC/TimeSync Coprocessor -  Only applicable to IXP46X
- *  16-17           Utopia PHY Limit Status : 0x0 - 32 PHY
- *                                            0x1 - 16 PHY
- *                                            0x2 -  8 PHY
- *                                            0x3 -  4 PHY
- *
- *  Portions below are only applicable to IXP46X
- *   18             USB Host Coprocessor
- *   19             NPE A Ethernet - 0 for Enable if Utopia = 1
- *   20             NPE B Ethernet coprocessor 1-3.
- *   21             RSA Crypto Block coprocessor.
- *  22-23           Processor frequency : 0x0 - 533 MHz
- *                                        0x1 - 667 MHz
- *                                        0x2 - 400 MHz
- *                                        0x3 - 266 MHz
- *  24-31           Reserved
- *
- ************************************************************************/
-/*Section generic to both IXP42X and IXP46X*/
-
-/**
- * @ingroup IxFeatureCtrlAPI
- *
- * @enum IxFeatureCtrlComponentType
- *
- * @brief Enumeration for components availavble
- *
- */
-typedef enum
-{
-    IX_FEATURECTRL_RCOMP = 0, /**<bit location for RComp Circuitry*/
-    IX_FEATURECTRL_USB,       /**<bit location for USB Controller*/
-    IX_FEATURECTRL_HASH,      /**<bit location for Hashing Coprocessor*/
-    IX_FEATURECTRL_AES,       /**<bit location for AES Coprocessor*/
-    IX_FEATURECTRL_DES,       /**<bit location for DES Coprocessor*/
-    IX_FEATURECTRL_HDLC,      /**<bit location for HDLC Coprocessor*/
-    IX_FEATURECTRL_AAL,       /**<bit location for AAL Coprocessor*/
-    IX_FEATURECTRL_HSS,       /**<bit location for HSS Coprocessor*/
-    IX_FEATURECTRL_UTOPIA,    /**<bit location for UTOPIA Coprocessor*/
-    IX_FEATURECTRL_ETH0,      /**<bit location for Ethernet 0 Coprocessor*/
-    IX_FEATURECTRL_ETH1,      /**<bit location for Ethernet 1 Coprocessor*/
-    IX_FEATURECTRL_NPEA,      /**<bit location for NPE A*/
-    IX_FEATURECTRL_NPEB,      /**<bit location for NPE B*/
-    IX_FEATURECTRL_NPEC,      /**<bit location for NPE C*/
-    IX_FEATURECTRL_PCI,       /**<bit location for PCI Controller*/
-    IX_FEATURECTRL_ECC_TIMESYNC,     /**<bit location for TimeSync Coprocessor*/
-    IX_FEATURECTRL_UTOPIA_PHY_LIMIT, /**<bit location for Utopia PHY Limit Status*/
-    IX_FEATURECTRL_UTOPIA_PHY_LIMIT_BIT2, /**<2nd bit of PHY limit status*/
-    IX_FEATURECTRL_USB_HOST_CONTROLLER, /**<bit location for USB host controller*/
-    IX_FEATURECTRL_NPEA_ETH,  /**<bit location for NPE-A Ethernet Disable*/
-    IX_FEATURECTRL_NPEB_ETH,  /**<bit location for NPE-B Ethernet 1-3 Coprocessors Disable*/
-    IX_FEATURECTRL_RSA,       /**<bit location for RSA Crypto block Coprocessors Disable*/
-    IX_FEATURECTRL_XSCALE_MAX_FREQ, /**<bit location for XScale max frequency*/
-    IX_FEATURECTRL_XSCALE_MAX_FREQ_BIT2, /**<2nd xscale max freq bit NOT TO BE USED */
-    IX_FEATURECTRL_MAX_COMPONENTS
-} IxFeatureCtrlComponentType;
-
-/**
- * @ingroup IxFeatureCtrlDeviceId
- *
- * @enum IxFeatureCtrlDeviceId
- *
- * @brief Enumeration for device type.
- *
- * @warning This enum is closely related to the npe image. Its format should comply
- *          with formats used in the npe image ImageID. This is indicated by the  
- *          first nibble of the image ID. This should also be in sync with the
- *          with what is defined in CP15.  Current available formats are
- *          - IXP42X - 0000
- *          - IXP46X - 0001
- *
- */
-typedef enum
-{
-    IX_FEATURE_CTRL_DEVICE_TYPE_IXP42X = 0, /**<Device type is IXP42X */
-    IX_FEATURE_CTRL_DEVICE_TYPE_IXP46X, /**<Device type is IXP46X */
-    IX_FEATURE_CTRL_DEVICE_TYPE_MAX /**<Max devices */
-} IxFeatureCtrlDeviceId;
-
-
-/**
- * @} addtogroup IxFeatureCtrlSwConfig
- */
-
-/*
- * Typedefs
- */
-
-/**
- * @ingroup IxFeatureCtrlAPI 
- * 
- * @typedef IxFeatureCtrlReg
- *
- * @brief Feature Control Register that contains hardware components'
- *        availability information.
- */
-typedef UINT32 IxFeatureCtrlReg;
-
-/**
- * @ingroup IxFeatureCtrlAPI 
- * 
- * @typedef IxFeatureCtrlProductId
- *
- * @brief Product ID of Silicon that contains Silicon Stepping and 
- *        Maximum XScale Core Frequency information.  
- */
-typedef UINT32 IxFeatureCtrlProductId;
-
-/*
- * Prototypes for interface functions
- */
-
-/**
- * @ingroup IxFeatureCtrlAPI 
- *
- * @fn IxFeatureCtrlReg ixFeatureCtrlRead (void)
- * 
- * @brief This function reads out the CURRENT value of Feature Control Register.
- *        The current value may not be the same as that of the hardware component 
- *        availability.    
- * 
- * The bit location of each hardware component is defined above. 
- * A value of '1' in bit means the hardware component is not available.  A value of '0'   
- * means the hardware component is available.
- *
- * @return 
- *      - IxFeatureCtrlReg - the current value of IXP400 Feature Control Register
- */ 
-PUBLIC IxFeatureCtrlReg
-ixFeatureCtrlRead (void);
-
-/**
- * @ingroup IxFeatureCtrlAPI
- *
- * @fn IxFeatureDeviceId ixFeatureCtrlDeviceRead (void)
- *
- * @brief This function gets the type of device that the software is currently running
- *        on
- *
- * This function reads the feature Ctrl register specifically to obtain the device id.
- * The definitions of the avilable IDs are as above.
- *
- * @return
- *      - IxFeatureCtrlDeviceId - the type of device currently running
- */
-IxFeatureCtrlDeviceId
-ixFeatureCtrlDeviceRead (void);
-
-/**
- * @ingroup IxFeatureCtrlAPI
- *
- * @fn IxFeatureCtrlBuildDevice ixFeatureCtrlSoftwareBuildGet (void)
- *
- * @brief This function refers to  the value set by the compiler flag to determine
- *        the type of device the software is built for.
- *
- * The function reads the compiler flag to determine the device the software is
- * built for. When the user executes build in the command line, 
- * a compile time flag (__ixp42X/__ixp46X is set. This API reads this 
- * flag and returns the software build type to the calling client.
- *
- * @return
- *      - IxFeatureCtrlBuildDevice - the type of device software is built for.
- */
-IxFeatureCtrlBuildDevice
-ixFeatureCtrlSoftwareBuildGet (void);
-
-/**
- * @ingroup IxFeatureCtrlAPI 
- *
- * @fn IxFeatureCtrlReg ixFeatureCtrlHwCapabilityRead (void)
- * 
- * @brief This function reads out the hardware capability of a silicon type as defined in 
- * feature control register.This value is different from that returned by 
- * ixFeatureCtrlRead() because this function returns the actual hardware component
- * availability.     
- *
- * The bit location of each hardware component is defined above. 
- * A value of '1' in bit means the hardware component is not available.  A value of '0'   
- * means the hardware component is available.
- *
- * @return 
- *      - IxFeatureCtrlReg - the hardware capability of IXP400. 
- *
- * @warning
- *      - This function must not be called when IXP400 is running as the result
- *        is undefined.    
- */ 
-PUBLIC IxFeatureCtrlReg
-ixFeatureCtrlHwCapabilityRead (void);
-
-/**
- * @ingroup IxFeatureCtrlAPI 
- *
- * @fn void ixFeatureCtrlWrite (IxFeatureCtrlReg expUnitReg)
- * 
- * @brief This function write the value stored in IxFeatureCtrlReg expUnitReg  
- *        to the Feature Control Register. 
- * 
- * The bit location of each hardware component is defined above.
- * The write is only effective on available hardware components. Writing '1' in a  
- * bit will software disable the respective hardware component. A '0' will mean that  
- * the hardware component will remain to be operable. 
- *
- * @param expUnitReg @ref IxFeatureCtrlReg [in] - The value to be written to feature control 
- *                                          register.
- *
- * @return none
- *
- */ 
-PUBLIC void
-ixFeatureCtrlWrite (IxFeatureCtrlReg expUnitReg);
-
-/**
- * @ingroup IxFeatureCtrlAPI 
- *
- * @fn IX_STATUS ixFeatureCtrlComponentCheck (IxFeatureCtrlComponentType componentType)
- * 
- * @brief This function will check the availability of hardware component specified
- *        as componentType value. 
- *
- *        Usage Example:<br> 
- *         -  if(IX_FEATURE_CTRL_COMPONENT_DISABLED != 
- *              ixFeatureCtrlComponentCheck(IX_FEATURECTRL_ETH0)) <br>
- *         -  if(IX_FEATURE_CTRL_COMPONENT_ENABLED == 
- *              ixFeatureCtrlComponentCheck(IX_FEATURECTRL_PCI)) <br>
- *
- * This function is typically called during component initialization time. 
- *
- * @param componentType @ref IxFeatureCtrlComponentType [in] - the type of a component as
- *        defined above as IX_FEATURECTRL_XXX (Exp: IX_FEATURECTRL_PCI, IX_FEATURECTRL_ETH0)           
-
- *        
- * @return 
- *      - IX_FEATURE_CTRL_COMPONENT_ENABLED if component is available 
- *      - IX_FEATURE_CTRL_COMPONENT_DISABLED if component is unavailable            
- */ 
-PUBLIC IX_STATUS
-ixFeatureCtrlComponentCheck (IxFeatureCtrlComponentType componentType);
-
-/**
- * @ingroup IxFeatureCtrlAPI 
- * 
- * @fn IxFeatureCtrlProductId ixFeatureCtrlProductIdRead (void)
- * 
- * @brief This function will return IXP400 product ID i.e. CP15,
- *        Register 0.
- *                                                
- * @return 
- *      - IxFeatureCtrlProductId - the value of product ID.
- *
- */ 
-PUBLIC IxFeatureCtrlProductId
-ixFeatureCtrlProductIdRead (void) ;
-
-/**
- * @ingroup IxFeatureCtrlAPI 
- *
- * @fn IX_STATUS ixFeatureCtrlSwConfigurationCheck (IxFeatureCtrlSwConfig swConfigType)
- * 
- * @brief This function checks whether the specified software configuration is
- *        enabled or disabled. 
- *
- *        Usage Example:<br> 
- *        - if(IX_FEATURE_CTRL_SWCONFIG_DISABLED != 
- *            ixFeatureCtrlSwConfigurationCheck(IX_FEATURECTRL_ETH_LEARNING)) <br>
- *        - if(IX_FEATURE_CTRL_SWCONFIG_ENABLED == 
- *            ixFeatureCtrlSwConfigurationCheck(IX_FEATURECTRL_ETH_LEARNING)) <br>
- *
- * This function is typically called during access component initialization time. 
- *
- * @param swConfigType @ref IxFeatureCtrlSwConfig [in] - the type of a software configuration
- *        defined in IxFeatureCtrlSwConfig enumeration.          
- *        
- * @return 
- *      - IX_FEATURE_CTRL_SWCONFIG_ENABLED if software configuration is enabled. 
- *      - IX_FEATURE_CTRL_SWCONFIG_DISABLED if software configuration is disabled.            
- */ 
-PUBLIC IX_STATUS
-ixFeatureCtrlSwConfigurationCheck (IxFeatureCtrlSwConfig swConfigType);
-
-/**
- * @ingroup IxFeatureCtrlAPI 
- *
- * @fn void ixFeatureCtrlSwConfigurationWrite (IxFeatureCtrlSwConfig swConfigType, BOOL enabled)
- * 
- * @brief This function enable/disable the specified software configuration.  
- *
- *        Usage Example:<br> 
- *        - ixFeatureCtrlSwConfigurationWrite(IX_FEATURECTRL_ETH_LEARNING, TRUE) is used
- *          to enable Ethernet Learning Feature <br>
- *        - ixFeatureCtrlSwConfigurationWrite(IX_FEATURECTRL_ETH_LEARNING, FALSE) is used
- *          to disable Ethernet Learning Feature <br> 
- *
- * @param swConfigType IxFeatureCtrlSwConfig [in] - the type of a software configuration
- *        defined in IxFeatureCtrlSwConfig enumeration. 
- * @param enabled BOOL [in] - To enable(TRUE) / disable (FALSE) the specified software
- *                           configuration.            
- *
- * @return none
- *          
- */ 
-PUBLIC void
-ixFeatureCtrlSwConfigurationWrite (IxFeatureCtrlSwConfig swConfigType, BOOL enabled);
-
-/**
- * @ingroup IxFeatureCtrlAPI 
- *
- * @fn void ixFeatureCtrlIxp400SwVersionShow (void)
- * 
- * @brief This function shows the current software release information for IXP400 
- *          
- * @return none
- *          
- */ 
-PUBLIC void
-ixFeatureCtrlIxp400SwVersionShow (void);
-
-#endif /* IXFEATURECTRL_H */
-
-/**
- * @} defgroup IxFeatureCtrlAPI
- */
diff --git a/arch/arm/cpu/ixp/npe/include/IxHssAcc.h b/arch/arm/cpu/ixp/npe/include/IxHssAcc.h
deleted file mode 100644
index 07bb119..0000000
--- a/arch/arm/cpu/ixp/npe/include/IxHssAcc.h
+++ /dev/null
@@ -1,1316 +0,0 @@
-/**
- * @file IxHssAcc.h
- * 
- * @date 07-DEC-2001
- *
- * @brief This file contains the public API of the IXP400 HSS Access
- * component
- *
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- * 
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- * 
- * @par
- * -- End of Copyright Notice --
-*/
- 
-/* ------------------------------------------------------
-   Doxygen group definitions
-   ------------------------------------------------------ */
-/**
- * @defgroup IxHssAccAPI IXP400 HSS Access (IxHssAcc) API
- *
- * @brief The public API for the IXP400 HssAccess component
- *
- * IxHssAcc is the access layer to the HSS packetised and channelised
- * services
- * 
- * <b> Design Notes </b><br>
- * <UL>
- * <LI>When a packet-pipe is configured for 56Kbps RAW mode, byte alignment of 
- *     the transmitted data is not preserved. All raw data that is transmitted 
- *     will be received in proper order by the receiver, but the first bit of 
- *     the packet may be seen at any offset within a byte; all subsequent bytes 
- *     will have the same offset for the duration of the packet. The same offset 
- *     also applies to all subsequent packets received on the packet-pipe too. 
- *     (Similar results will occur for data received from remote end.) While 
- *     this behavior will also occur for 56Kbps HDLC mode, the HDLC 
- *     encoding/decoding will preserve the original byte alignment at the 
- *     receiver end.
- * </UL>
- *
- * <b> 56Kbps Packetised Service Bandwidth Limitation </b><br>
- * <UL>
- * <LI>IxHssAcc supports 56Kbps packetised service at a maximum aggregate rate
- *     for all HSS ports/HDLC channels of 12.288Mbps[1] in each direction, i.e.
- *     it supports 56Kbps packetised service on up to 8 T1 trunks. It does
- *     not support 56Kbps packetised service on 8 E1 trunks (i.e. 4 trunks per 
- *     HSS port) unless those trunks are running 'fractional E1' with maximum 
- *     aggregate rate of 12.288 Mbps in each direction.<br>
- *     [1] 12.288Mbps = 1.536Mbp * 8 T1
- * </UL>
- * @{ */
-
-#ifndef IXHSSACC_H
-#define IXHSSACC_H
-
-#include "IxOsal.h"
-
-/*
- * #defines for function return types, etc.
- */
-
-/**
- * @def IX_HSSACC_TSLOTS_PER_HSS_PORT
- *
- * @brief The max number of TDM timeslots supported per HSS port - 4E1's =
- *  32x4 = 128 
- */
-#define IX_HSSACC_TSLOTS_PER_HSS_PORT 128
-
-/* -----------------------------------------------------------
-   The following are HssAccess return values returned through 
-   service interfaces. The globally defined IX_SUCCESS (0) and
-   IX_FAIL (1) in IxOsalTypes.h are also used.
-   ----------------------------------------------------------- */
-/**
- * @def IX_HSSACC_PARAM_ERR
- *
- * @brief HssAccess function return value for a parameter error
- */
-#define IX_HSSACC_PARAM_ERR 2
-
-/**
- * @def IX_HSSACC_RESOURCE_ERR
- *
- * @brief HssAccess function return value for a resource error
- */
-#define IX_HSSACC_RESOURCE_ERR 3
-
-/**
- * @def IX_HSSACC_PKT_DISCONNECTING
- *
- * @brief Indicates that a disconnect call is progressing and will 
- * disconnect soon
- */
-#define IX_HSSACC_PKT_DISCONNECTING 4
-
-/**
- * @def IX_HSSACC_Q_WRITE_OVERFLOW
- *
- * @brief Indicates that an attempt to Tx or to replenish an 
- * RxFree Q failed due to Q overflow.  
- */
-#define IX_HSSACC_Q_WRITE_OVERFLOW 5
-
-/* -------------------------------------------------------------------
-   The following errors are HSS/NPE errors returned on error retrieval
-   ------------------------------------------------------------------- */
-/**
- * @def IX_HSSACC_NO_ERROR
- *
- * @brief HSS port no error present
- */
-#define IX_HSSACC_NO_ERROR 0
-
-/**
- * @def IX_HSSACC_TX_FRM_SYNC_ERR
- *
- * @brief HSS port TX Frame Sync error
- */
-#define IX_HSSACC_TX_FRM_SYNC_ERR 1
-
-/**
- * @def IX_HSSACC_TX_OVER_RUN_ERR
- *
- * @brief HSS port TX over-run error
- */
-#define IX_HSSACC_TX_OVER_RUN_ERR 2
-
-/**
- * @def IX_HSSACC_CHANNELISED_SW_TX_ERR
- *
- * @brief NPE software error in channelised TX
- */
-#define IX_HSSACC_CHANNELISED_SW_TX_ERR 3
-
-/**
- * @def IX_HSSACC_PACKETISED_SW_TX_ERR
- *
- * @brief NPE software error in packetised TX
- */
-#define IX_HSSACC_PACKETISED_SW_TX_ERR 4
-
-/**
- * @def IX_HSSACC_RX_FRM_SYNC_ERR
- *
- * @brief HSS port RX Frame Sync error
- */
-#define IX_HSSACC_RX_FRM_SYNC_ERR 5
-
-/**
- * @def IX_HSSACC_RX_OVER_RUN_ERR
- *
- * @brief HSS port RX over-run error
- */
-#define IX_HSSACC_RX_OVER_RUN_ERR 6
-
-/**
- * @def IX_HSSACC_CHANNELISED_SW_RX_ERR
- *
- * @brief NPE software error in channelised RX
- */
-#define IX_HSSACC_CHANNELISED_SW_RX_ERR 7
-
-/**
- * @def IX_HSSACC_PACKETISED_SW_RX_ERR
- *
- * @brief NPE software error in packetised TX
- */
-#define IX_HSSACC_PACKETISED_SW_RX_ERR 8
-
-/* -----------------------------------
-   Packetised service specific defines
-   ----------------------------------- */
-
-/**
- * @def IX_HSSACC_PKT_MIN_RX_MBUF_SIZE
- *
- * @brief Minimum size of the Rx mbuf in bytes which the client must supply 
- * to the component. 
- */
-#define IX_HSSACC_PKT_MIN_RX_MBUF_SIZE 64
-
-/* --------------------------------------------------------------------
-   Enumerated Types - these enumerated values may be used in setting up
-   the contents of hardware registers
-   -------------------------------------------------------------------- */
-/**
- * @enum IxHssAccHssPort
- * @brief The HSS port ID - There are two identical ports (0-1). 
- * 
- */
-typedef enum
-{
-    IX_HSSACC_HSS_PORT_0,   /**< HSS Port 0 */
-    IX_HSSACC_HSS_PORT_1,   /**< HSS Port 1 */
-    IX_HSSACC_HSS_PORT_MAX  /**< Delimiter for error checks */
-} IxHssAccHssPort;
-
-/**
- * @enum IxHssAccHdlcPort
- * @brief The HDLC port ID - There are four identical HDLC ports (0-3) per 
- * HSS port and they correspond to the 4 E1/T1 trunks.
- * 
- */
-typedef enum
-{
-   IX_HSSACC_HDLC_PORT_0,   /**< HDLC Port 0 */
-   IX_HSSACC_HDLC_PORT_1,   /**< HDLC Port 1 */
-   IX_HSSACC_HDLC_PORT_2,   /**< HDLC Port 2 */
-   IX_HSSACC_HDLC_PORT_3,   /**< HDLC Port 3 */
-   IX_HSSACC_HDLC_PORT_MAX  /**< Delimiter for error checks */
-} IxHssAccHdlcPort;
-
-/**
- * @enum IxHssAccTdmSlotUsage
- * @brief The HSS TDM stream timeslot assignment types
- *
- */
-typedef enum
-{
-    IX_HSSACC_TDMMAP_UNASSIGNED,    /**< Unassigned */
-    IX_HSSACC_TDMMAP_HDLC,          /**< HDLC - packetised */
-    IX_HSSACC_TDMMAP_VOICE56K,      /**< Voice56K - channelised */
-    IX_HSSACC_TDMMAP_VOICE64K,      /**< Voice64K - channelised */
-    IX_HSSACC_TDMMAP_MAX            /**< Delimiter for error checks */
-} IxHssAccTdmSlotUsage;
-
-/**
- * @enum IxHssAccFrmSyncType
- * @brief The HSS frame sync pulse type
- *
- */
-typedef enum
-{
-    IX_HSSACC_FRM_SYNC_ACTIVE_LOW,   /**< Frame sync is sampled low */
-    IX_HSSACC_FRM_SYNC_ACTIVE_HIGH,  /**< sampled high */
-    IX_HSSACC_FRM_SYNC_FALLINGEDGE,  /**< sampled on a falling edge */
-    IX_HSSACC_FRM_SYNC_RISINGEDGE,   /**< sampled on a rising edge */
-    IX_HSSACC_FRM_SYNC_TYPE_MAX      /**< Delimiter for error checks */
-} IxHssAccFrmSyncType;
-
-/**
- * @enum IxHssAccFrmSyncEnable
- * @brief The IxHssAccFrmSyncEnable determines how the frame sync pulse is
- * used
- * */
-typedef enum
-{
-    IX_HSSACC_FRM_SYNC_INPUT,          /**< Frame sync is sampled as an input */
-    IX_HSSACC_FRM_SYNC_INVALID_VALUE,  /**< 1 is not used */
-    IX_HSSACC_FRM_SYNC_OUTPUT_FALLING, /**< Frame sync is an output generated 
-					  off a falling clock edge */
-    IX_HSSACC_FRM_SYNC_OUTPUT_RISING,  /**< Frame sync is an output generated 
-					  off a rising clock edge */
-    IX_HSSACC_FRM_SYNC_ENABLE_MAX      /**< Delimiter for error checks */
-} IxHssAccFrmSyncEnable;
-
-/**
- * @enum IxHssAccClkEdge
- * @brief IxHssAccClkEdge is used to determine the clk edge to use for 
- * framing and data
- *
- */
-typedef enum
-{
-    IX_HSSACC_CLK_EDGE_FALLING,  /**< Clock sampled off a falling edge */
-    IX_HSSACC_CLK_EDGE_RISING,   /**< Clock sampled off a rising edge */
-    IX_HSSACC_CLK_EDGE_MAX       /**< Delimiter for error checks */
-} IxHssAccClkEdge;
-
-/**
- * @enum IxHssAccClkDir
- * @brief The HSS clock direction
- *
- */
-typedef enum
-{
-    IX_HSSACC_SYNC_CLK_DIR_INPUT,    /**< Clock is an input */
-    IX_HSSACC_SYNC_CLK_DIR_OUTPUT,   /**< Clock is an output */
-    IX_HSSACC_SYNC_CLK_DIR_MAX       /**< Delimiter for error checks */
-} IxHssAccClkDir;
-
-/**
- * @enum IxHssAccFrmPulseUsage
- * @brief The HSS frame pulse usage
- *
- */
-typedef enum
-{
-    IX_HSSACC_FRM_PULSE_ENABLED,     /**< Generate/Receive frame pulses */
-    IX_HSSACC_FRM_PULSE_DISABLED,    /**< Disregard frame pulses */
-    IX_HSSACC_FRM_PULSE_MAX          /**< Delimiter for error checks */
-} IxHssAccFrmPulseUsage;
-
-/**
- * @enum IxHssAccDataRate
- * @brief The HSS Data rate in relation to the clock
- *
- */
-typedef enum
-{
-    IX_HSSACC_CLK_RATE,      /**< Data rate is at the configured clk speed */
-    IX_HSSACC_HALF_CLK_RATE, /**< Data rate is half the configured clk speed */
-    IX_HSSACC_DATA_RATE_MAX  /**< Delimiter for error checks */
-} IxHssAccDataRate;
-
-/**
- * @enum IxHssAccDataPolarity
- * @brief The HSS data polarity type
- *
- */
-typedef enum
-{
-    IX_HSSACC_DATA_POLARITY_SAME,   /**< Don't invert data between NPE and 
-				       HSS FIFOs */
-    IX_HSSACC_DATA_POLARITY_INVERT, /**< Invert data between NPE and HSS 
-				       FIFOs */
-    IX_HSSACC_DATA_POLARITY_MAX     /**< Delimiter for error checks */
-} IxHssAccDataPolarity;
-
-/**
- * @enum IxHssAccBitEndian
- * @brief HSS Data endianness
- *
- */
-typedef enum
-{
-    IX_HSSACC_LSB_ENDIAN,    /**< TX/RX Least Significant Bit first */
-    IX_HSSACC_MSB_ENDIAN,    /**< TX/RX Most Significant Bit first */
-    IX_HSSACC_ENDIAN_MAX     /**< Delimiter for the purposes of error checks */
-} IxHssAccBitEndian;
-
-
-/**
- * @enum IxHssAccDrainMode
- * @brief Tx pin open drain mode
- *
- */
-typedef enum
-{
-    IX_HSSACC_TX_PINS_NORMAL,       /**< Normal mode */
-    IX_HSSACC_TX_PINS_OPEN_DRAIN,   /**< Open Drain mode */
-    IX_HSSACC_TX_PINS_MAX           /**< Delimiter for error checks */
-} IxHssAccDrainMode;
-
-/**
- * @enum IxHssAccSOFType
- * @brief HSS start of frame types
- *
- */
-typedef enum
-{
-    IX_HSSACC_SOF_FBIT,  /**< Framing bit transmitted and expected on rx */
-    IX_HSSACC_SOF_DATA,  /**< Framing bit not transmitted nor expected on rx */
-    IX_HSSACC_SOF_MAX    /**< Delimiter for error checks */
-} IxHssAccSOFType;
-
-/**
- * @enum IxHssAccDataEnable
- * @brief IxHssAccDataEnable is used to determine whether or not to drive 
- * the data pins
- *
- */
-typedef enum
-{
-    IX_HSSACC_DE_TRI_STATE,   /**< TRI-State the data pins */
-    IX_HSSACC_DE_DATA,        /**< Push data out the data pins */
-    IX_HSSACC_DE_MAX          /**< Delimiter for error checks */
-} IxHssAccDataEnable;
-
-/**
- * @enum IxHssAccTxSigType
- * @brief IxHssAccTxSigType is used to determine how to drive the data pins
- *
- */
-typedef enum
-{
-    IX_HSSACC_TXSIG_LOW,        /**< Drive the data pins low */
-    IX_HSSACC_TXSIG_HIGH,       /**< Drive the data pins high */
-    IX_HSSACC_TXSIG_HIGH_IMP,   /**< Drive the data pins with high impedance */
-    IX_HSSACC_TXSIG_MAX         /**< Delimiter for error checks */
-} IxHssAccTxSigType;
-
-/**
- * @enum IxHssAccFbType
- * @brief IxHssAccFbType determines how to drive the Fbit
- *
- * @warning This will only be used for T1 @ 1.544MHz
- *
- */
-typedef enum
-{
-    IX_HSSACC_FB_FIFO,        /**< Fbit is dictated in FIFO */
-    IX_HSSACC_FB_HIGH_IMP,    /**< Fbit is high impedance */
-    IX_HSSACC_FB_MAX          /**< Delimiter for error checks */
-} IxHssAccFbType;
-
-/**
- * @enum IxHssAcc56kEndianness
- * @brief 56k data endianness when using the 56k type
- *
- */
-typedef enum
-{
-    IX_HSSACC_56KE_BIT_7_UNUSED,  /**< High bit is unused */
-    IX_HSSACC_56KE_BIT_0_UNUSED,  /**< Low bit is unused */
-    IX_HSSACC_56KE_MAX            /**< Delimiter for error checks */
-} IxHssAcc56kEndianness;
-
-/**
- * @enum IxHssAcc56kSel
- * @brief 56k data transmission type when using the 56k type
- *
- */
-typedef enum
-{
-    IX_HSSACC_56KS_32_8_DATA,  /**< 32/8 bit data */
-    IX_HSSACC_56KS_56K_DATA,   /**< 56K data */
-    IX_HSSACC_56KS_MAX         /**< Delimiter for error checks */
-} IxHssAcc56kSel;
-
-
-/**
- * @enum IxHssAccClkSpeed
- * @brief IxHssAccClkSpeed represents the HSS clock speeds available
- *
- */
-typedef enum
-{
-    IX_HSSACC_CLK_SPEED_512KHZ,     /**< 512KHz */
-    IX_HSSACC_CLK_SPEED_1536KHZ,    /**< 1.536MHz */
-    IX_HSSACC_CLK_SPEED_1544KHZ,    /**< 1.544MHz */
-    IX_HSSACC_CLK_SPEED_2048KHZ,    /**< 2.048MHz */
-    IX_HSSACC_CLK_SPEED_4096KHZ,    /**< 4.096MHz */
-    IX_HSSACC_CLK_SPEED_8192KHZ,    /**< 8.192MHz */
-    IX_HSSACC_CLK_SPEED_MAX      /**< Delimiter for error checking */
-} IxHssAccClkSpeed;
-
-/**
- * @enum IxHssAccPktStatus
- * @brief Indicates the status of packets passed to the client
- *
- */
-typedef enum
-{
-    IX_HSSACC_PKT_OK,              /**< Error free.*/
-    IX_HSSACC_STOP_SHUTDOWN_ERROR, /**< Errored due to stop or shutdown 
-				      occurrance.*/
-    IX_HSSACC_HDLC_ALN_ERROR,      /**< HDLC alignment error */
-    IX_HSSACC_HDLC_FCS_ERROR,       /**< HDLC Frame Check Sum error.*/
-    IX_HSSACC_RXFREE_Q_EMPTY_ERROR,       /**< RxFree Q became empty 
-					     while receiving this packet.*/
-    IX_HSSACC_HDLC_MAX_FRAME_SIZE_EXCEEDED,      /**< HDLC frame size 
-						   received is greater than
-						   max specified at connect.*/
-    IX_HSSACC_HDLC_ABORT_ERROR,   /**< HDLC frame received is invalid due to an 
-				   abort sequence received.*/
-    IX_HSSACC_DISCONNECT_IN_PROGRESS     /**< Packet returned
-					    because a disconnect is in progress */
-} IxHssAccPktStatus;
-
-
-/**
- * @enum IxHssAccPktCrcType
- * @brief HDLC CRC type
- *
- */
-typedef enum
-{
-    IX_HSSACC_PKT_16_BIT_CRC = 16,  /**< 16 bit CRC is being used */
-    IX_HSSACC_PKT_32_BIT_CRC = 32   /**< 32 bit CRC is being used */
-} IxHssAccPktCrcType;
-
-/**
- * @enum IxHssAccPktHdlcIdleType
- * @brief HDLC idle transmission type
- *
- */
-typedef enum
-{
-    IX_HSSACC_HDLC_IDLE_ONES,    /**< idle tx/rx will be a succession of ones */
-    IX_HSSACC_HDLC_IDLE_FLAGS    /**< idle tx/rx will be repeated flags */
-} IxHssAccPktHdlcIdleType;
-
-/**
- * @brief Structure containing HSS port configuration parameters
- *
- * Note: All of these are used for TX. Only some are specific to RX.
- *
- */
-typedef struct
-{
-    IxHssAccFrmSyncType frmSyncType;     /**< frame sync pulse type (tx/rx) */
-    IxHssAccFrmSyncEnable frmSyncIO;     /**< how the frame sync pulse is 
-					    used (tx/rx) */
-    IxHssAccClkEdge frmSyncClkEdge;      /**< frame sync clock edge type 
-					    (tx/rx) */
-    IxHssAccClkEdge dataClkEdge;         /**< data clock edge type (tx/rx) */
-    IxHssAccClkDir clkDirection;         /**< clock direction (tx/rx) */
-    IxHssAccFrmPulseUsage frmPulseUsage; /**< whether to use the frame sync 
-					    pulse or not (tx/rx) */
-    IxHssAccDataRate dataRate;           /**< data rate in relation to the 
-					    clock (tx/rx) */
-    IxHssAccDataPolarity dataPolarity;   /**< data polarity type (tx/rx) */
-    IxHssAccBitEndian dataEndianness;    /**< data endianness (tx/rx) */
-    IxHssAccDrainMode drainMode;         /**< tx pin open drain mode (tx) */
-    IxHssAccSOFType fBitUsage;           /**< start of frame types (tx/rx) */
-    IxHssAccDataEnable dataEnable;       /**< whether or not to drive the data 
-					    pins (tx) */
-    IxHssAccTxSigType voice56kType;      /**< how to drive the data pins for 
-					    voice56k type (tx) */
-    IxHssAccTxSigType unassignedType;    /**< how to drive the data pins for 
-					    unassigned type (tx) */
-    IxHssAccFbType fBitType;             /**< how to drive the Fbit (tx) */
-    IxHssAcc56kEndianness voice56kEndian;/**< 56k data endianness when using 
-					    the 56k type (tx) */
-    IxHssAcc56kSel voice56kSel;          /**< 56k data transmission type when 
-					    using the 56k type (tx) */
-    unsigned frmOffset;                  /**< frame pulse offset in bits wrt 
-					    the first timeslot (0-1023) (tx/rx) */
-    unsigned maxFrmSize;                 /**< frame size in bits (1-1024) 
-					    (tx/rx) */
-} IxHssAccPortConfig;
-
-/**
- * @brief Structure containing HSS configuration parameters
- *
- */
-typedef struct
-{
-    IxHssAccPortConfig txPortConfig; /**< HSS tx port configuration */
-    IxHssAccPortConfig rxPortConfig; /**< HSS rx port configuration */
-    unsigned numChannelised;         /**< The number of channelised 
-					timeslots (0-32) */
-    unsigned hssPktChannelCount;     /**< The number of packetised 
-					clients (0 - 4) */
-    UINT8 channelisedIdlePattern;    /**< The byte to be transmitted on 
-					channelised service when there 
-					is no client data to tx */
-    BOOL loopback;                   /**< The HSS loopback state */
-    unsigned packetizedIdlePattern;  /**< The data to be transmitted on 
-					packetised service when there is 
-					no client data to tx */
-    IxHssAccClkSpeed clkSpeed;       /**< The HSS clock speed */
-} IxHssAccConfigParams;
-
-/**
- * @brief This structure contains 56Kbps, HDLC-mode configuration parameters
- *
- */
-typedef struct
-{
-    BOOL hdlc56kMode;                    /**< 56kbps(TRUE)/64kbps(FALSE) HDLC */
-    IxHssAcc56kEndianness hdlc56kEndian; /**< 56kbps data endianness 
-					    - ignored if hdlc56kMode is FALSE*/
-    BOOL hdlc56kUnusedBitPolarity0;      /**< The polarity '0'(TRUE)/'1'(FALSE) of the unused
-					   bit while in 56kbps mode
-					   - ignored if hdlc56kMode is FALSE*/
-} IxHssAccHdlcMode;
-
-/**
- * @brief This structure contains information required by the NPE to 
- * configure the HDLC co-processor
- *
- */
-typedef struct
-{
-    IxHssAccPktHdlcIdleType hdlcIdleType;   /**< What to transmit when a HDLC port is idle */
-    IxHssAccBitEndian dataEndian;           /**< The HDLC data endianness */
-    IxHssAccPktCrcType crcType;             /**< The CRC type to be used for this HDLC port */
-} IxHssAccPktHdlcFraming;
-
-/**
- * @typedef UINT32 IxHssAccPktUserId
- *
- * @brief The client supplied value which will be supplied as a parameter
- * with a given callback.
- *
- * This value will be passed into the ixHssAccPktPortConnect function once each
- * with given callbacks.  This value will then be passed back to the client
- * as one of the parameters to each of these callbacks, 
- * when these callbacks are called.
- */
-typedef UINT32 IxHssAccPktUserId;
-
-
-/**
- * @typedef IxHssAccLastErrorCallback
- * @brief Prototype of the clients function to accept notification of the 
- * last error
- *
- * This function is registered through the config. The client will initiate
- * the last error retrieval. The HssAccess component will send a message to
- * the NPE through the NPE Message Handler. When a response to the read is
- * received, the NPE Message Handler will callback the HssAccess component
- * which will execute this function in the same IxNpeMh context. The client
- * will be passed the last error and the related service port (packetised
- * 0-3, channelised 0)
- *
- * @param lastHssError unsigned [in] - The last Hss error registered that
- *                                      has been registered.
- * @param servicePort unsigned [in] - This is the service port number.  
- *                                     (packetised 0-3, channelised 0) 
- * 
- * @return void
- */
-typedef void (*IxHssAccLastErrorCallback) (unsigned lastHssError, 
-					   unsigned servicePort);
-
-/**
- * @typedef IxHssAccPktRxCallback
- * @brief  Prototype of the clients function to accept notification of 
- * packetised rx
- *
- * This function is registered through the ixHssAccPktPortConnect. hssPktAcc will pass
- * received data in the form of mbufs to the client.  The mbuf passed back
- * to the client could contain a chain of buffers, depending on the packet
- * size received. 
- * 
- * @param *buffer @ref IX_OSAL_MBUF [in] - This is the mbuf which contains the 
- * payload received.
- * @param numHssErrs unsigned [in] - This is the number of hssErrors 
- * the Npe has received
- * @param pktStatus @ref IxHssAccPktStatus [in] - This is the status of the 
- * mbuf that has been received.
- * @param rxUserId @ref IxHssAccPktUserId [in] - This is the client supplied value 
- * passed in at ixHssAccPktPortConnect time which is now returned to the client.			       
- * 
- * @return void
- */
-typedef void (*IxHssAccPktRxCallback) (IX_OSAL_MBUF *buffer, 
-				       unsigned numHssErrs, 
-				       IxHssAccPktStatus pktStatus, 
-				       IxHssAccPktUserId rxUserId);
-
-/**
- * @typedef IxHssAccPktRxFreeLowCallback
- * @brief Prototype of the clients function to accept notification of 
- * requirement of more Rx Free buffers
- *
- * The client can choose to register a callback of this type when
- * calling a connecting. This function is registered through the ixHssAccPktPortConnect. 
- * If defined, the access layer will provide the trigger for
- * this callback. The callback will be responsible for supplying mbufs to
- * the access layer for use on the receive path from the HSS using
- * ixHssPktAccFreeBufReplenish. 
- *
- * @return void
- */
-typedef void (*IxHssAccPktRxFreeLowCallback) (IxHssAccPktUserId rxFreeLowUserId);
-
-/**
- * @typedef IxHssAccPktTxDoneCallback
- * @brief  Prototype of the clients function to accept notification of 
- * completion with Tx buffers
- *
- * This function is registered through the ixHssAccPktPortConnect.  It enables
- * the hssPktAcc to pass buffers back to the client
- * when transmission is complete.
- *
- * @param *buffer @ref IX_OSAL_MBUF [in] - This is the mbuf which contained 
- * the payload that was for Tx.
- * @param numHssErrs unsigned [in] - This is the number of hssErrors 
- * the Npe has received
- * @param pktStatus @ref IxHssAccPktStatus [in] - This is the status of the 
- * mbuf that has been transmitted.
- * @param txDoneUserId @ref IxHssAccPktUserId [in] - This is the client supplied value 
- * passed in at ixHssAccPktPortConnect time which is now returned to the client.	 
- *
- * @return void
- */
-typedef void (*IxHssAccPktTxDoneCallback) (IX_OSAL_MBUF *buffer, 
-					   unsigned numHssErrs,
-					   IxHssAccPktStatus pktStatus, 
-					   IxHssAccPktUserId txDoneUserId);
-
-/**
- * @typedef IxHssAccChanRxCallback
- * @brief Prototype of the clients function to accept notification of 
- * channelised rx
- *
- * This callback, if defined by the client in the connect, will get called
- * in the context of an IRQ. The IRQ will be triggered when the hssSyncQMQ
- * is not empty. The queued entry will be dequeued and this function will
- * be executed.
- *
- * @param hssPortId @ref IxHssAccHssPort - The HSS port Id. There are two
- * identical ports (0-1).
- * @param txOffset unsigned [in] - an offset indicating from where within
- * the txPtrList the NPE is currently transmitting from.
- * @param rxOffset unsigned [in] - an offset indicating where within the
- * receive buffers the NPE has just written the received data to.
- * @param numHssErrs unsigned [in] - This is the number of hssErrors 
- * the Npe has received
- *
- * @return void
- */
-typedef void (*IxHssAccChanRxCallback) (IxHssAccHssPort hssPortId,
-					unsigned rxOffset, 
-					unsigned txOffset, 
-					unsigned numHssErrs);
-
-/*
- * Prototypes for interface functions.
- */
-
-/**
- *
- * @ingroup IxHssAccAPI
- *
- * @fn IX_STATUS ixHssAccPortInit (IxHssAccHssPort hssPortId, 
-               IxHssAccConfigParams *configParams, 
-               IxHssAccTdmSlotUsage *tdmMap, 
-               IxHssAccLastErrorCallback lastHssErrorCallback)
- *
- * @brief Initialise a HSS port. No channelised or packetised connections
- * should exist in the HssAccess layer while this interface is being called.
- *
- * @param hssPortId @ref IxHssAccHssPort [in] - The HSS port Id. There are two
- * identical ports (0-1). 
- * @param *configParams @ref IxHssAccConfigParams [in] - A pointer to the HSS 
- * configuration structure
- * @param *tdmMap @ref IxHssAccTdmSlotUsage [in] - A pointer to an array of size
- * IX_HSSACC_TSLOTS_PER_HSS_PORT, defining the slot usage over the HSS port
- * @param lastHssErrorCallback @ref IxHssAccLastErrorCallback [in] - Client 
- * callback to report last error
- *
- * @return 
- *         - IX_SUCCESS The function executed successfully
- *         - IX_FAIL The function did not execute successfully
- *         - IX_HSSACC_PARAM_ERR The function did not execute successfully due to a
- *                          parameter error
- */
-PUBLIC IX_STATUS 
-ixHssAccPortInit (IxHssAccHssPort hssPortId, 
-		  IxHssAccConfigParams *configParams, 
-		  IxHssAccTdmSlotUsage *tdmMap, 
-		  IxHssAccLastErrorCallback lastHssErrorCallback);
-
-/**
- *
- * @ingroup IxHssAccAPI
- *
- * @fn IX_STATUS ixHssAccLastErrorRetrievalInitiate (
-               IxHssAccHssPort hssPortId)
- *
- * @brief Initiate the retrieval of the last HSS error. The HSS port
- * should be configured before attempting to call this interface.
- *
- * @param hssPortId @ref IxHssAccHssPort [in] - the HSS port ID
- *
- * @return 
- *         - IX_SUCCESS The function executed successfully
- *         - IX_FAIL The function did not execute successfully
- *         - IX_HSSACC_PARAM_ERR The function did not execute successfully due to a
- *                          parameter error
- */
-PUBLIC IX_STATUS 
-ixHssAccLastErrorRetrievalInitiate (IxHssAccHssPort hssPortId);
-
-
-/**
- *
- * @ingroup IxHssAccAPI
- *
- * @fn IX_STATUS ixHssAccInit ()
- *
- * @brief This function is responsible for initialising resources for use
- * by the packetised and channelised clients. It should be called after 
- * HSS NPE image has been downloaded into NPE-A and before any other
- * HssAccess interface is called. 
- * No other HssAccPacketised interface should be called while this interface
- * is being processed.
- *
- * @return 
- *         - IX_SUCCESS The function executed successfully
- *         - IX_FAIL The function did not execute successfully
- *         - IX_HSSACC_RESOURCE_ERR The function did not execute successfully due
- *                          to a resource error 
- */
-PUBLIC IX_STATUS 
-ixHssAccInit (void);
-
-
-/**
- *
- * @ingroup IxHssAccAPI
- *
- * @fn ixHssAccPktPortConnect (IxHssAccHssPort hssPortId, 
-			IxHssAccHdlcPort hdlcPortId, 
-			BOOL hdlcFraming, 
-			IxHssAccHdlcMode hdlcMode,
-			BOOL hdlcBitInvert,
-			unsigned blockSizeInWords,
-			UINT32 rawIdleBlockPattern,
-			IxHssAccPktHdlcFraming hdlcTxFraming, 
-			IxHssAccPktHdlcFraming hdlcRxFraming, 
-			unsigned frmFlagStart, 
-			IxHssAccPktRxCallback rxCallback,
-			IxHssAccPktUserId rxUserId, 
-			IxHssAccPktRxFreeLowCallback rxFreeLowCallback, 
-			IxHssAccPktUserId rxFreeLowUserId,
-			IxHssAccPktTxDoneCallback txDoneCallback,
-			IxHssAccPktUserId txDoneUserId) 
- *
- * @brief This function is responsible for connecting a client to one of 
- * the 4 available HDLC ports. The HSS port should be configured before 
- * attempting a connect. No other HssAccPacketised interface should be
- * called while this connect is being processed.
- *
- * @param hssPortId @ref IxHssAccHssPort [in] - The HSS port Id. There are two
- * identical ports (0-1). 
- * @param hdlcPortId @ref IxHssAccHdlcPort [in] - This is the number of the HDLC port and 
- * it corresponds to the physical E1/T1 trunk i.e. 0, 1, 2, 3 
- * @param hdlcFraming BOOL [in] - This value determines whether the service 
- * will use HDLC data or the debug, raw data type i.e. no HDLC processing
- * @param hdlcMode @ref IxHssAccHdlcMode [in] - This structure contains 56Kbps, HDLC-mode
- * configuration parameters
- * @param hdlcBitInvert BOOL [in] - This value determines whether bit inversion
- * will occur between HDLC and HSS co-processors i.e. post-HDLC processing for
- * transmit and pre-HDLC processing for receive, for the specified HDLC Termination
- * Point
- * @param blockSizeInWords unsigned [in] -  The max tx/rx block size 
- * @param rawIdleBlockPattern UINT32 [in] -  Tx idle pattern in raw mode 
- * @param hdlcTxFraming @ref IxHssAccPktHdlcFraming [in] - This structure contains 
- * the following information required by the NPE to configure the HDLC 
- * co-processor for TX
- * @param hdlcRxFraming @ref IxHssAccPktHdlcFraming [in] -  This structure contains 
- * the following information required by the NPE to configure the HDLC 
- * co-processor for RX
- * @param frmFlagStart unsigned - Number of flags to precede to 
- * transmitted flags (0-2).
- * @param rxCallback @ref IxHssAccPktRxCallback [in] - Pointer to 
- * the clients packet receive function.
- * @param rxUserId @ref IxHssAccPktUserId [in] - The client supplied rx value
- * to be passed back as an argument to the supplied rxCallback
- * @param rxFreeLowCallback @ref IxHssAccPktRxFreeLowCallback [in] - Pointer to 
- * the clients Rx free buffer request function.  If NULL, assume client will 
- * trigger independently.
- * @param rxFreeLowUserId @ref IxHssAccPktUserId [in] - The client supplied RxFreeLow value
- * to be passed back as an argument to the supplied rxFreeLowCallback
- * @param txDoneCallback @ref IxHssAccPktTxDoneCallback [in] - Pointer to the 
- * clients Tx done callback function
- * @param txDoneUserId @ref IxHssAccPktUserId [in] - The client supplied txDone value
- * to be passed back as an argument to the supplied txDoneCallback
- *
- * @return 
- *         - IX_SUCCESS The function executed successfully
- *         - IX_FAIL The function did not execute successfully
- *         - IX_HSSACC_PARAM_ERR The function did not execute successfully due to a
- *                          parameter error
- *         - IX_HSSACC_RESOURCE_ERR The function did not execute successfully due
- *                          to a resource error
- */
-PUBLIC IX_STATUS 
-ixHssAccPktPortConnect (IxHssAccHssPort hssPortId, 
-			IxHssAccHdlcPort hdlcPortId, 
-			BOOL hdlcFraming, 
-			IxHssAccHdlcMode hdlcMode,
-			BOOL hdlcBitInvert,
-			unsigned blockSizeInWords,
-			UINT32 rawIdleBlockPattern,
-			IxHssAccPktHdlcFraming hdlcTxFraming, 
-			IxHssAccPktHdlcFraming hdlcRxFraming, 
-			unsigned frmFlagStart, 
-			IxHssAccPktRxCallback rxCallback,
-			IxHssAccPktUserId rxUserId, 
-			IxHssAccPktRxFreeLowCallback rxFreeLowCallback, 
-			IxHssAccPktUserId rxFreeLowUserId,
-			IxHssAccPktTxDoneCallback txDoneCallback,
-			IxHssAccPktUserId txDoneUserId);
-
-/**
- *
- * @ingroup IxHssAccAPI
- *
- * @fn IX_STATUS ixHssAccPktPortEnable (IxHssAccHssPort hssPortId, 
-           IxHssAccHdlcPort hdlcPortId)
- *
- * @brief This function is responsible for enabling a packetised service
- * for the specified HSS/HDLC port combination. It enables the RX flow. The
- * client must have already connected to a packetised service and is responsible 
- * for ensuring an adequate amount of RX mbufs have been supplied to the access
- * component before enabling the packetised service. This function must be called
- * on a given port before any call to ixHssAccPktPortTx on the same port. 
- * No other HssAccPacketised interface should be called while this interface is 
- * being processed.
- *
- * @param hssPortId @ref IxHssAccHssPort [in] - The HSS port Id. There are two
- * identical ports (0-1).   
- * @param hdlcPortId @ref IxHssAccHdlcPort [in] - The port id (0,1,2,3) to enable the service
- * on.
- *
- * @return 
- *         - IX_SUCCESS The function executed successfully
- *         - IX_FAIL The function did not execute successfully
- *         - IX_HSSACC_PARAM_ERR The function did not execute successfully due to a
- *                          parameter error
- */
-PUBLIC IX_STATUS 
-ixHssAccPktPortEnable (IxHssAccHssPort hssPortId, 
-		       IxHssAccHdlcPort hdlcPortId);
-
-/**
- * @fn IX_STATUS ixHssAccPktPortDisable (IxHssAccHssPort hssPortId, 
-           IxHssAccHdlcPort hdlcPortId)
- *
- * @brief This function is responsible for disabling a packetised service
- * for the specified HSS/HDLC port combination. It disables the RX flow. 
- * The client must have already connected to and enabled a packetised service 
- * for the specified HDLC port. This disable interface can be called before a
- * disconnect, but is not required to.
- *
- * @param hssPortId @ref IxHssAccHssPort [in] - The HSS port Id. There are two
- * identical ports (0-1). 
- * @param hdlcPortId @ref IxHssAccHdlcPort [in] - The port id (0,1,2,3) to disable 
- * the service on.
- *
- * @return 
- *         - IX_SUCCESS The function executed successfully
- *         - IX_FAIL The function did not execute successfully
- *         - IX_HSSACC_PARAM_ERR The function did not execute successfully due to a
- *                          parameter error
- */
-PUBLIC IX_STATUS 
-ixHssAccPktPortDisable (IxHssAccHssPort hssPortId, 
-			IxHssAccHdlcPort hdlcPortId);
-
-/**
- *
- * @ingroup IxHssAccAPI
- *
- * @fn IX_STATUS ixHssAccPktPortDisconnect (IxHssAccHssPort hssPortId, 
-           IxHssAccHdlcPort hdlcPortId)
- *
- * @brief This function is responsible for disconnecting a client from one
- * of the 4 available HDLC ports. It is not required that the Rx Flow 
- * has been disabled before calling this function.  If the RX Flow has not been
- * disabled, the disconnect will disable it before proceeding with the
- * disconnect.  No other HssAccPacketised 
- * interface should be called while this interface is being processed.
- *
- * @param hssPortId @ref IxHssAccHssPort [in] - The HSS port Id. There are two
- * identical ports (0-1). 
- * @param hdlcPortId @ref IxHssAccHdlcPort [in] - This is the number of the HDLC port
- * to disconnect and it corresponds to the physical E1/T1 trunk i.e. 0, 1, 2, 3
- *
- * @return 
- *         - IX_SUCCESS The function executed successfully
- *         - IX_FAIL The function did not execute successfully 
- *         - IX_HSSACC_PKT_DISCONNECTING The function has initiated the disconnecting
- *                             procedure but it has not completed yet.
- */
-PUBLIC IX_STATUS 
-ixHssAccPktPortDisconnect (IxHssAccHssPort hssPortId, 
-			   IxHssAccHdlcPort hdlcPortId);
-
-/**
- *
- * @ingroup IxHssAccAPI
- *
- * @fn BOOL ixHssAccPktPortIsDisconnectComplete (IxHssAccHssPort hssPortId, 
-           IxHssAccHdlcPort hdlcPortId)
- *
- * @brief This function is called to check if a given HSS/HDLC port 
- * combination is in a connected state or not. This function may be called 
- * at any time to determine a ports state.  No other HssAccPacketised 
- * interface should be called while this interface is being processed.
- *
- * @param hssPortId @ref IxHssAccHssPort [in] - The HSS port Id. There are two
- * identical ports (0-1). 
- * @param hdlcPortId @ref IxHssAccHdlcPort [in] - This is the number of the HDLC port
- * to disconnect and it corresponds to the physical E1/T1 trunk i.e. 0, 1, 2, 3
- *
- * @return 
- *         - TRUE The state of this HSS/HDLC port combination is disconnected,
- *                so if a disconnect was called, it is now completed.
- *         - FALSE The state of this HSS/HDLC port combination is connected,
- *                so if a disconnect was called, it is not yet completed.
- */
-PUBLIC BOOL 
-ixHssAccPktPortIsDisconnectComplete (IxHssAccHssPort hssPortId, 
-				     IxHssAccHdlcPort hdlcPortId);
-
-
-/**
- *
- * @ingroup IxHssAccAPI
- *
- * @fn IX_STATUS ixHssAccPktPortRxFreeReplenish (IxHssAccHssPort hssPortId, 
-              IxHssAccHdlcPort hdlcPortId, 
-	      IX_OSAL_MBUF *buffer)
- *
- * @brief Function which the client calls at regular intervals to provide
- * mbufs to the access component for RX. A connection should exist for
- * the specified hssPortId/hdlcPortId combination before attempting to call this 
- * interface. Also, the connection should not be in a disconnecting state.
- *
- * @param hssPortId @ref IxHssAccHssPort [in] - The HSS port Id. There are two
- * identical ports (0-1). 
- * @param hdlcPortId @ref IxHssAccHdlcPort [in] - This is the number of the HDLC port
- * and it corresponds to the physical E1/T1 trunk i.e. 0, 1, 2, 3
- * @param *buffer @ref IX_OSAL_MBUF [in] - A pointer to a free mbuf to filled with payload.
- *
- * @return 
- *         - IX_SUCCESS The function executed successfully
- *         - IX_FAIL The function did not execute successfully
- *         - IX_HSSACC_PARAM_ERR The function did not execute successfully due to a
- *                          parameter error
- *         - IX_HSSACC_RESOURCE_ERR The function did not execute successfully due
- *                          to a resource error
- *         - IX_HSSACC_Q_WRITE_OVERFLOW The function did not succeed due to a Q
- *                                      overflow
- */
-PUBLIC IX_STATUS 
-ixHssAccPktPortRxFreeReplenish (IxHssAccHssPort hssPortId, 
-				IxHssAccHdlcPort hdlcPortId, 
-				IX_OSAL_MBUF *buffer);
-
-/**
- *
- * @ingroup IxHssAccAPI
- *
- * @fn IX_STATUS ixHssAccPktPortTx (IxHssAccHssPort hssPortId, 
-    IxHssAccHdlcPort hdlcPortId, 
-    IX_OSAL_MBUF *buffer)
- *
- * @brief Function which the client calls when it wants to transmit
- * packetised data. An enabled connection should exist on the specified
- * hssPortId/hdlcPortId combination before attempting to call this interface.
- * No other HssAccPacketised 
- * interface should be called while this interface is being processed.
- *
- * @param hssPortId @ref IxHssAccHssPort [in] - The HSS port Id. There are two
- * identical ports (0-1). 
- * @param hdlcPortId @ref IxHssAccHdlcPort [in] - This is the number of the HDLC port
- * and it corresponds to the physical E1/T1 trunk i.e. 0, 1, 2, 3
- * @param *buffer @ref IX_OSAL_MBUF [in] - A pointer to a chain of mbufs which the
- * client has filled with the payload
- *
- * @return 
- *         - IX_SUCCESS The function executed successfully
- *         - IX_FAIL The function did not execute successfully
- *         - IX_HSSACC_PARAM_ERR The function did not execute successfully due to a
- *                          parameter error
- *         - IX_HSSACC_RESOURCE_ERR The function did not execute successfully due
- *                          to a resource error. See note.
- *         - IX_HSSACC_Q_WRITE_OVERFLOW The function did not succeed due to a Q
- *                                      overflow
- *
- * @note IX_HSSACC_RESOURCE_ERR is returned when a free descriptor cannot be
- * obtained to send the chain of mbufs to the NPE.  This is a normal scenario.
- * HssAcc has a pool of descriptors and this error means that they are currently
- * all in use.
- * The recommended approach to this is to retry until a descriptor becomes free
- * and the packet is successfully transmitted.
- * Alternatively, the user could wait until the next IxHssAccPktTxDoneCallback
- * callback is triggered, and then retry, as it is this event that causes a
- * transmit descriptor to be freed. 
- */
-PUBLIC IX_STATUS 
-ixHssAccPktPortTx (IxHssAccHssPort hssPortId, 
-		   IxHssAccHdlcPort hdlcPortId, 
-		   IX_OSAL_MBUF *buffer);
-
-/**
- *
- * @ingroup IxHssAccAPI
- *
- * @fn IX_STATUS ixHssAccChanConnect (IxHssAccHssPort hssPortId, 
-           unsigned bytesPerTSTrigger, 
-	   UINT8 *rxCircular, 
-	   unsigned numRxBytesPerTS, 
-	   UINT32 *txPtrList, 
-	   unsigned numTxPtrLists, 
-	   unsigned numTxBytesPerBlk, 
-	   IxHssAccChanRxCallback rxCallback)
- *
- * @brief This function allows the client to connect to the Tx/Rx NPE
- * Channelised Service. There can only be one client per HSS port. The
- * client is responsible for ensuring that the HSS port is configured
- * appropriately before its connect request. No other HssAccChannelised 
- * interface should be called while this interface is being processed.
- *
- * @param hssPortId @ref IxHssAccHssPort [in] - The HSS port Id. There are two
- * identical ports (0-1). 
- * @param bytesPerTSTrigger unsigned [in] - The NPE will trigger the access
- * component after bytesPerTSTrigger have been received for all trunk
- * timeslots. This figure is a multiple of 8 e.g. 8 for 1ms trigger, 16 for
- * 2ms trigger.
- * @param *rxCircular UINT8 [in] - A pointer to memory allocated by the
- * client to be filled by data received. The buffer at this address is part
- * of a pool of buffers to be accessed in a circular fashion. This address
- * will be written to by the NPE. Therefore, it needs to be a physical address.
- * @param numRxBytesPerTS unsigned [in] - The number of bytes allocated per
- * timeslot within the receive memory. This figure will depend on the
- * latency of the system. It needs to be deep enough for data to be read by
- * the client before the NPE re-writes over that memory e.g. if the client
- * samples at a rate of 40bytes per timeslot, numRxBytesPerTS may need to
- * be 40bytes * 3. This would give the client 3 * 5ms of time before
- * received data is over-written.
- * @param *txPtrList UINT32 [in] - The address of an area of contiguous
- * memory allocated by the client to be populated with pointers to data for
- * transmission. Each pointer list contains a pointer per active channel.
- * The txPtrs will point to data to be transmitted by the NPE. Therefore,
- * they must point to physical addresses.
- * @param numTxPtrLists unsigned [in] - The number of pointer lists in
- * txPtrList. This figure is dependent on jitter.
- * @param numTxBytesPerBlk unsigned [in] - The size of the Tx data, in
- * bytes, that each pointer within the PtrList points to.
- * @param rxCallback @ref IxHssAccChanRxCallback [in] - A client function
- * pointer to be called back to handle the actual tx/rx of channelised
- * data. If this is not NULL, an ISR will call this function. If this
- * pointer is NULL, it implies that the client will use a polling mechanism
- * to detect when the tx and rx of channelised data is to occur. The client
- * will use hssChanAccStatus for this.
- *
- * @return
- *         - IX_SUCCESS The function executed successfully
- *         - IX_FAIL The function did not execute successfully
- *         - IX_HSSACC_PARAM_ERR The function did not execute successfully due to a
- *                          parameter error
- */
- 
-PUBLIC IX_STATUS 
-ixHssAccChanConnect (IxHssAccHssPort hssPortId, 
-		     unsigned bytesPerTSTrigger, 
-		     UINT8 *rxCircular, 
-		     unsigned numRxBytesPerTS, 
-		     UINT32 *txPtrList, 
-		     unsigned numTxPtrLists, 
-		     unsigned numTxBytesPerBlk, 
-		     IxHssAccChanRxCallback rxCallback);
-
-/**
- *
- * @ingroup IxHssAccAPI
- *
- * @fn IX_STATUS ixHssAccChanPortEnable (IxHssAccHssPort hssPortId)
- *
- * @brief This function is responsible for enabling a channelised service
- * for the specified HSS port. It enables the NPE RX flow. The client must
- * have already connected to a channelised service before enabling the
- * channelised service. No other HssAccChannelised 
- * interface should be called while this interface is being processed.
- *
- * @param hssPortId @ref IxHssAccHssPort [in] - The HSS port Id. There are two
- * identical ports (0-1). 
- *
- * @return
- *         - IX_SUCCESS The function executed successfully
- *         - IX_FAIL The function did not execute successfully
- *         - IX_HSSACC_PARAM_ERR The function did not execute successfully due to a
- *                          parameter error
- */
-PUBLIC IX_STATUS 
-ixHssAccChanPortEnable (IxHssAccHssPort hssPortId);
-
-/**
- *
- * @ingroup IxHssAccAPI
- *
- * @fn IX_STATUS ixHssAccChanPortDisable (IxHssAccHssPort hssPortId)
- *
- * @brief This function is responsible for disabling a channelised service
- * for the specified HSS port. It disables the NPE RX flow. The client must
- * have already connected to and enabled a channelised service for the
- * specified HSS port. This disable interface can be called before a
- * disconnect, but is not required to. No other HssAccChannelised 
- * interface should be called while this interface is being processed.
- *
- * @param hssPortId @ref IxHssAccHssPort [in] - The HSS port Id. There are two
- * identical ports (0-1). 
- *
- * @return 
- *         - IX_SUCCESS The function executed successfully
- *         - IX_FAIL The function did not execute successfully
- *         - IX_HSSACC_PARAM_ERR The function did not execute successfully due to a
- *                          parameter error
- */
-PUBLIC IX_STATUS 
-ixHssAccChanPortDisable (IxHssAccHssPort hssPortId);
-
-/**
- *
- * @ingroup IxHssAccAPI
- *
- * @fn IX_STATUS ixHssAccChanDisconnect (IxHssAccHssPort hssPortId)
- *
- * @brief This function allows the client to Disconnect from a channelised
- * service. If the NPE RX Flow has not been disabled, the disconnect will
- * disable it before proceeding with other disconnect functionality.
- * No other HssAccChannelised interface should be called while this 
- * interface is being processed.
- *
- * @param hssPortId @ref IxHssAccHssPort [in] - The HSS port Id. There are two
- * identical ports (0-1). 
- *
- * @return 
- *         - IX_SUCCESS The function executed successfully
- *         - IX_FAIL The function did not execute successfully
- *         - IX_HSSACC_PARAM_ERR The function did not execute successfully due to a
- *                          parameter error
- */
-PUBLIC IX_STATUS 
-ixHssAccChanDisconnect (IxHssAccHssPort hssPortId);
-
-/**
- *
- * @ingroup IxHssAccAPI
- *
- * @fn IX_STATUS ixHssAccChanStatusQuery (IxHssAccHssPort hssPortId, 
-           BOOL *dataRecvd, 
-	   unsigned *rxOffset, 
-	   unsigned *txOffset, 
-	   unsigned *numHssErrs)
- *
- * @brief This function is called by the client to query whether or not
- * channelised data has been received. If there is, hssChanAcc will return
- * the details in the output parameters. An enabled connection should
- * exist on the specified hssPortId before attempting to call this interface.  
- * No other HssAccChannelised interface should be called while this 
- * interface is being processed.
- *
- * @param hssPortId @ref IxHssAccHssPort [in] - The HSS port Id. There are two
- * identical ports (0-1). 
- * @param *dataRecvd BOOL [out] - This BOOL indicates to the client whether
- * or not the access component has read any data for the client. If
- * FALSE, the other output parameters will not have been written to.
- * @param *rxOffset unsigned [out] - An offset to indicate to the client
- * where within the receive buffers the NPE has just written the received
- * data to.
- * @param *txOffset unsigned [out] - An offset to indicate to the client
- * from where within the txPtrList the NPE is currently transmitting from
- * @param *numHssErrs unsigned [out] - The total number of HSS port errors
- * since initial port configuration
- *
- *
- * @return 
- *         - IX_SUCCESS The function executed successfully
- *         - IX_FAIL The function did not execute successfully
- *         - IX_HSSACC_PARAM_ERR The function did not execute successfully due to a
- *                          parameter error
- */
-PUBLIC IX_STATUS 
-ixHssAccChanStatusQuery (IxHssAccHssPort hssPortId, 
-			 BOOL *dataRecvd, 
-			 unsigned *rxOffset, 
-			 unsigned *txOffset, 
-			 unsigned *numHssErrs);
-
-/**
- *
- * @ingroup IxHssAccAPI
- *
- * @fn void ixHssAccShow (void)
- *
- * @brief This function will display the current state of the IxHssAcc
- * component. The output is sent to stdout.
- *
- * @return void
- */
-PUBLIC void 
-ixHssAccShow (void);
-
-/**
- *
- * @ingroup IxHssAccAPI
- *
- * @fn void ixHssAccStatsInit (void)
- *
- * @brief This function will reset the IxHssAcc statistics.
- *
- * @return void
- */
-PUBLIC void 
-ixHssAccStatsInit (void);
-
-#endif /* IXHSSACC_H */
-
-/**
- * @} defgroup IxHssAcc
- */
diff --git a/arch/arm/cpu/ixp/npe/include/IxI2cDrv.h b/arch/arm/cpu/ixp/npe/include/IxI2cDrv.h
deleted file mode 100644
index 92c6b24..0000000
--- a/arch/arm/cpu/ixp/npe/include/IxI2cDrv.h
+++ /dev/null
@@ -1,867 +0,0 @@
-/**
- * @file IxI2cDrv.h
- *
- * @brief  Header file for the IXP400 I2C Driver (IxI2cDrv)
- *
- * @version $Revision: 0.1 $
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- * 
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- * 
- * @par
- * -- End of Copyright Notice --
- */
-
-/**
- * @defgroup IxI2cDrv IXP400 I2C Driver(IxI2cDrv) API 
- *
- * @brief IXP400 I2C Driver Public API
- *
- * @{
- */
-#ifndef IXI2CDRV_H
-#define IXI2CDRV_H
-
-#ifdef __ixp46X
-#include "IxOsal.h"
-
-/*
- * Section for #define
- */
-
-/**
- * @ingroup IxI2cDrv
- * @brief The interval of micro/mili seconds the IXP will wait before it polls for
- *			status from the ixI2cIntrXferStatus; Every 20us is 1 byte @
- *			400Kbps and 4 bytes	@ 100Kbps. This is dependent on delay type selected
- *          through the API ixI2cDrvDelayTypeSelect.
- */
-#define IX_I2C_US_POLL_FOR_XFER_STATUS	20
-
-/**
- * @ingroup IxI2cDrv
- * @brief The number of tries that will be attempted to call a callback
- *          function if the callback does not or is unable to resolve the
- *          issue it is called to resolve
- */
-#define IX_I2C_NUM_OF_TRIES_TO_CALL_CALLBACK_FUNC	10
-
-
-/**
- * @ingroup IxI2cDrv
- * @brief Number of tries slave will poll the IDBR Rx full bit before it
- *			gives up
- */
-#define IX_I2C_NUM_TO_POLL_IDBR_RX_FULL 0x100
-
-/**
- * @ingroup IxI2cDrv
- * @brief Number of tries slave will poll the IDBR Tx empty bit before it
- *			gives up
- */
-#define IX_I2C_NUM_TO_POLL_IDBR_TX_EMPTY 0x100
-
-/*
- * Section for enum
- */
-
-/**
- * @ingroup IxI2cDrv
- * 
- * @enum IxI2cMasterStatus
- *
- * @brief The master status - transfer complete, bus error or arbitration loss
- */
-typedef enum
-{
-    IX_I2C_MASTER_XFER_COMPLETE = IX_SUCCESS,
-	IX_I2C_MASTER_XFER_BUS_ERROR,
-	IX_I2C_MASTER_XFER_ARB_LOSS
-} IxI2cMasterStatus;
-
-
-/**
- * @ingroup IxI2cDrv
- * 
- * @enum IX_I2C_STATUS
- *
- * @brief The status that can be returned in a I2C driver initialization
- */
-typedef enum
-{
-	IX_I2C_SUCCESS = IX_SUCCESS, /**< Success status */
-	IX_I2C_FAIL, /**< Fail status */
-	IX_I2C_NOT_SUPPORTED, /**< hardware does not have dedicated I2C hardware */
-	IX_I2C_NULL_POINTER, /**< parameter passed in is NULL */
-	IX_I2C_INVALID_SPEED_MODE_ENUM_VALUE, /**< speed mode selected is invalid */
-	IX_I2C_INVALID_FLOW_MODE_ENUM_VALUE, /**< flow mode selected is invalid */
-	IX_I2C_SLAVE_ADDR_CB_MISSING, /**< slave callback is NULL */
-	IX_I2C_GEN_CALL_CB_MISSING, /**< general callback is NULL */
-	IX_I2C_INVALID_SLAVE_ADDR, /**< invalid slave address specified */
-	IX_I2C_INT_BIND_FAIL, /**< interrupt bind fail */
-	IX_I2C_INT_UNBIND_FAIL, /**< interrupt unbind fail */
-	IX_I2C_NOT_INIT, /**< I2C is not initialized yet */
-	IX_I2C_MASTER_BUS_BUSY, /**< master detected a I2C bus busy */
-	IX_I2C_MASTER_ARB_LOSS, /**< master experienced arbitration loss */
-	IX_I2C_MASTER_XFER_ERROR, /**< master experienced a transfer error */
-	IX_I2C_MASTER_BUS_ERROR, /**< master detected a I2C bus error */
-	IX_I2C_MASTER_NO_BUFFER, /**< no buffer provided for master transfer */
-	IX_I2C_MASTER_INVALID_XFER_MODE, /**< xfer mode selected is invalid */
-	IX_I2C_SLAVE_ADDR_NOT_DETECTED, /**< polled slave addr not detected */
-	IX_I2C_GEN_CALL_ADDR_DETECTED, /**< polling detected general call */
-	IX_I2C_SLAVE_READ_DETECTED, /**< polling detected slave read request */
-	IX_I2C_SLAVE_WRITE_DETECTED, /**< polling detected slave write request */
-	IX_I2C_SLAVE_NO_BUFFER, /**< no buffer provided for slave transfers */
-	IX_I2C_DATA_SIZE_ZERO, /**< data size transfer is zero - invalid */
-	IX_I2C_SLAVE_WRITE_BUFFER_EMPTY, /**< slave buffer is used till empty */
-	IX_I2C_SLAVE_WRITE_ERROR, /**< slave write experienced an error */
-	IX_I2C_SLAVE_OR_GEN_READ_BUFFER_FULL, /**< slave buffer is filled up */
-	IX_I2C_SLAVE_OR_GEN_READ_ERROR /**< slave read experienced an error */
-} IX_I2C_STATUS;
-
-/**
- * @ingroup IxI2cDrv
- * 
- * @enum IxI2cSpeedMode
- *
- * @brief Type of speed modes supported by the I2C hardware.
- */
-typedef enum
-{
-    IX_I2C_NORMAL_MODE = 0x0,
-    IX_I2C_FAST_MODE
-} IxI2cSpeedMode;
-
-/**
- * @ingroup IxI2cDrv
- * 
- * @enum IxI2cXferMode
- *
- * @brief Used for indicating it is a repeated start or normal transfer
- */
-typedef enum
-{
-    IX_I2C_NORMAL = 0x0,
-    IX_I2C_REPEATED_START
-} IxI2cXferMode;
-
-/**
- * @ingroup IxI2cDrv
- * 
- * @enum IxI2cFlowMode
- *
- * @brief Used for indicating it is a poll or interrupt mode
- */
-typedef enum
-{
-    IX_I2C_POLL_MODE = 0x0,
-    IX_I2C_INTERRUPT_MODE
-} IxI2cFlowMode;
-
-/**
- * @ingroup IxI2cDrv
- * 
- * @enum IxI2cDelayMode
- *
- * @brief Used for selecting looping delay or OS scheduler delay
- */
-typedef enum
-{
-    IX_I2C_LOOP_DELAY = 1,  /**< delay in microseconds */
-    IX_I2C_SCHED_DELAY      /**< delay in miliseconds */
-} IxI2cDelayMode;
-
-/**
- * @ingroup IxI2cDrv
- * 
- * @brief The pointer to the function that will be called when the master
- *			has completed its receive. The parameter that is passed will
- *			provide the status of the read (success, arb loss, or bus
- *			error), the transfer mode (normal or repeated start, the
- *			buffer pointer and number of bytes transferred.
- */
-typedef void (*IxI2cMasterReadCallbackP)(IxI2cMasterStatus, IxI2cXferMode, char*, UINT32);
-
-/**
- * @ingroup IxI2cDrv
- * 
- * @brief The pointer to the function that will	be called when the master
- *			has completed its transmit. The parameter that is passed will
- *			provide the status of the write (success, arb loss, or buss
- *			error), the transfer mode (normal or repeated start), the
- *			buffer pointer and number of bytes transferred.
- */
-typedef void (*IxI2cMasterWriteCallbackP)(IxI2cMasterStatus, IxI2cXferMode, char*, UINT32);
-
-/**
- * @ingroup IxI2cDrv
- * 
- * @brief The pointer to the function that will be called when a slave
- *			address detected in interrupt mode for a read. The parameters
- *			that is passed will provide the read status, buffer pointer,
- *			buffer size, and the bytes received. When a start of a read
- *			is initiated there will be no buffer allocated and this callback
- *			will be called to request for a buffer. While receiving, if the
- *			buffer gets filled, this callback will be called to request for
- *			a new buffer while sending the filled buffer's pointer and size,
- *			and data size received. When the receive is complete, this
- *			callback will be called to process the data and free the memory
- *			by passing the buffer's pointer and size, and data size received.
- */
-typedef void (*IxI2cSlaveReadCallbackP)(IX_I2C_STATUS, char*, UINT32, UINT32);
-
-/**
- * @ingroup IxI2cDrv
- * 
- * @brief The pointer to the function that will be called when a slave
- *			address detected in interrupt mode for a write. The parameters
- *			that is passed will provide the write status, buffer pointer,
- *			buffer size, and the bytes received. When a start of a write is
- *			initiated there will be no buffer allocated and this callback
- *			will be called to request for a buffer and to fill it with data.
- *			While transmitting, if the data in the buffer empties, this
- *			callback will be called to request for more data to be filled in
- *			the same or new buffer. When the transmit is complete, this
- *			callback will be called to free the memory or other actions to
- *			be taken.
- */
-typedef void (*IxI2cSlaveWriteCallbackP)(IX_I2C_STATUS, char*, UINT32, UINT32);
-
-/**
- * @ingroup IxI2cDrv
- * 
- * @brief The pointer to the function that will be called when a general
- *			call detected in interrupt mode for a read. The parameters that
- *			is passed will provide the read status, buffer pointer, buffer
- *			size, and the bytes received. When a start of a read is
- *			initiated there will be no buffer allocated and this callback
- *			will be called to request for a buffer. While receiving, if the
- *			buffer gets filled, this callback will be called to request for
- *			a new buffer while sending the filled buffer's pointer and size,
- *			and data size received. When the receive is complete, this
- *			callback will be called to process the data and free the memory
- *			by passing the buffer's pointer and size, and data size received.
- */
-typedef void (*IxI2cGenCallCallbackP)(IX_I2C_STATUS, char*, UINT32, UINT32);
-
-/*
- * Section for struct
- */
-
-/**
- * @brief contains all the variables required to initialize the I2C unit
- * 
- * Structure to be filled and used for calling initialization
- */
-typedef struct
-{
-	IxI2cSpeedMode I2cSpeedSelect;	/**<Select either normal (100kbps)
-									or fast mode (400kbps)*/
-	IxI2cFlowMode I2cFlowSelect;	/**<Select interrupt or poll mode*/	
-	IxI2cMasterReadCallbackP MasterReadCBP;
-									/**<The master read callback pointer */
-	IxI2cMasterWriteCallbackP MasterWriteCBP;
-									/**<The master write callback pointer */
-	IxI2cSlaveReadCallbackP SlaveReadCBP;
-									/**<The slave read callback pointer */
-	IxI2cSlaveWriteCallbackP SlaveWriteCBP;
-									/**<The slave write callback pointer */
-	IxI2cGenCallCallbackP GenCallCBP;
-									/**<The general call callback pointer */
-	BOOL I2cGenCallResponseEnable;	/**<Enable/disable the unit to
-									respond to generall calls.*/
-	BOOL I2cSlaveAddrResponseEnable;/**<Enable/disable the unit to
-									respond to the slave address set in
-									ISAR*/
-	BOOL SCLEnable;					/**<Enable/disable the unit from
-									driving the SCL line during master
-									mode operation*/
-	UINT8 I2cHWAddr;				/**<The address the unit will
-									response to as a slave device*/
-} IxI2cInitVars;
-
-/**
- * @brief contains results of counters and their overflow
- * 
- * Structure contains all values of counters and associated overflows.
- */
-typedef struct
-{
-	UINT32 ixI2cMasterXmitCounter;			/**<Total bytes transmitted as
-											master.*/
-	UINT32 ixI2cMasterFailedXmitCounter;	/**<Total bytes failed for
-											transmission as master.*/
-	UINT32 ixI2cMasterRcvCounter;			/**<Total bytes received as
-											master.*/
-	UINT32 ixI2cMasterFailedRcvCounter;		/**<Total bytes failed for
-											receival as master.*/
-	UINT32 ixI2cSlaveXmitCounter;			/**<Total bytes transmitted as
-											slave.*/
-	UINT32 ixI2cSlaveFailedXmitCounter;		/**<Total bytes failed for
-											transmission as slave.*/
-	UINT32 ixI2cSlaveRcvCounter;			/**<Total bytes received as
-											slave.*/
-	UINT32 ixI2cSlaveFailedRcvCounter;		/**<Total bytes failed for
-											receival as slave.*/
-	UINT32 ixI2cGenAddrCallSucceedCounter;	/**<Total bytes successfully
-											transmitted for general address.*/
-	UINT32 ixI2cGenAddrCallFailedCounter;	/**<Total bytes failed transmission
-											for general address.*/
-	UINT32 ixI2cArbLossCounter;				/**<Total instances of arbitration
-											loss has occured.*/
-} IxI2cStatsCounters;
-
-
-/*
- * Section for prototypes interface functions
- */
-
-/**
- * @ingroup IxI2cDrv
- * 
- * @fn ixI2cDrvInit(
-	IxI2cInitVars *InitVarsSelected)
- *
- * @brief Initializes the I2C Driver.
- *
- * @param "IxI2cInitVars [in] *InitVarsSelected" - struct containing required
- *			variables for initialization 
- *
- * Global Data	:
- *		- None.
- *
- * This API will check if the hardware supports this I2C driver and the validity
- * of the parameters passed in. It will continue to process the parameters
- * passed in by setting the speed of the I2C unit (100kbps or 400kbps), setting
- * the flow to either interrupt or poll mode, setting the address of the I2C unit,
- * enabling/disabling the respond to General Calls, enabling/disabling the respond
- * to Slave Address and SCL line driving. If it is interrupt mode, then it will
- * register the callback routines for master, slavetransfer and general call receive.
- *
- * @return 
- *      - IX_I2C_SUCCESS - Successfully initialize and enable the I2C
- *							hardware.
- *		- IX_I2C_NOT_SUPPORTED - The hardware does not support or have a
- *                              dedicated I2C unit to support this driver
- *		- IX_I2C_NULL_POINTER - The parameter passed in is a NULL pointed
- *		- IX_I2C_INVALID_SPEED_MODE_ENUM_VALUE - The speed mode selected in the
- *												InitVarsSelected is invalid
- *		- IX_I2C_INVALID_FLOW_MODE_ENUM_VALUE - The flow mode selected in the
- *												InitVarsSelected is invalid
- *		- IX_I2C_INVALID_SLAVE_ADDR - The address 0x0 is reserved for
- *										general call.
- *		- IX_I2C_SLAVE_ADDR_CB_MISSING - interrupt mode is selected but
- *										slave address callback pointer is NULL
- *		- IX_I2C_GEN_CALL_CB_MISSING - interrupt mode is selected but
- *										general call callback pointer is NULL
- *		- IX_I2C_INT_BIND_FAIL - The ISR for the I2C failed to bind
- *		- IX_I2C_INT_UNBIND_FAIL - The ISR for the I2C failed to unbind
- *
- * @li   Reentrant    : yes
- * @li   ISR Callable : yes
- *
- */
-PUBLIC IX_I2C_STATUS
-ixI2cDrvInit(IxI2cInitVars *InitVarsSelected);
-
-/**
- * @ingroup IxI2cDrv
- * 
- * @fn ixI2cDrvUninit(
-	void)
- *
- * @brief Disables the I2C hardware
- *
- * @param - None
- *
- * Global Data	:
- *		- None.
- *                        
- * This API will disable the I2C hardware, unbind interrupt, and unmap memory.
- *
- * @return 
- *      - IX_I2C_SUCCESS - successfully un-initialized I2C
- *		- IX_I2C_INT_UNBIND_FAIL - failed to unbind the I2C interrupt
- *		- IX_I2C_NOT_INIT - I2C not init yet.
- *              
- * @li   Reentrant    : yes
- * @li   ISR Callable : yes
- *
- */
-PUBLIC IX_I2C_STATUS
-ixI2cDrvUninit(void);
-
-/**
- * @ingroup IxI2cDrv
- * 
- * @fn ixI2cDrvSlaveAddrSet(
-	UINT8 SlaveAddrSet)
- *
- * @brief Sets the I2C Slave Address
- *
- * @param "UINT8 [in] SlaveAddrSet" - Slave Address to be inserted into ISAR
- *
- * Global Data	:
- *		- None.
- *                        
- * This API will insert the SlaveAddrSet into the ISAR.
- *
- * @return 
- *      - IX_I2C_SUCCESS - successfuly set the slave addr
- *		- IX_I2C_INVALID_SLAVE_ADDR - invalid slave address (zero) specified
- *		- IX_I2C_NOT_INIT - I2C not init yet.
- *              
- * @li   Reentrant    : yes
- * @li   ISR Callable : yes
- *
- */
-PUBLIC IX_I2C_STATUS
-ixI2cDrvSlaveAddrSet(UINT8 SlaveAddrSet);
-
-/**
- * @ingroup IxI2cDrv
- * 
- * @fn ixI2cDrvBusScan(
-	void)
- *
- * @brief scans the I2C bus for slave devices
- *
- * @param - None
- *
- * Global Data	:
- *		- None.
- *                        
- * This API will prompt all slave addresses for a reply except its own
- *
- * @return 
- *      - IX_I2C_SUCCESS - found at least one slave device
- *		- IX_I2C_FAIL - Fail to find even one slave device
- *		- IX_I2C_BUS_BUSY - The I2C bus is busy (held by another I2C master)
- *		- IX_I2C_ARB_LOSS - The I2C bus was loss to another I2C master
- *		- IX_I2C_NOT_INIT - I2C not init yet.
- *              
- * @li   Reentrant    : yes
- * @li   ISR Callable : yes
- *
- */
-PUBLIC IX_I2C_STATUS
-ixI2cDrvBusScan(void);
-
-/**
- * @ingroup IxI2cDrv
- * 
- * @fn ixI2cDrvWriteTransfer(
-	UINT8 SlaveAddr,
-	char *bufP,
-	UINT32 dataSize,
-	IxI2cXferMode XferModeSelect)
- *
- * @param "UINT8 [in] SlaveAddr" - The slave address to request data from.
- * @param "char [in] *bufP" - The pointer to the data to be transmitted.
- * @param "UINT32 [in] dataSize" - The number of bytes requested.
- * @param "IxI2cXferMode [in] XferModeSelect" - the transfer mode selected,
- *			either repeated start (ends w/o stop) or normal (start and stop)
- *
- * Global Data	:
- *		- None.
- *                        
- * This API will try to obtain master control of the I2C bus and transmit the
- * number of bytes, specified by dataSize, to the user specified slave
- * address from the buffer pointer. It will use either interrupt or poll mode
- * depending on the method selected. 
- *
- * If in interrupt mode and IxI2cMasterWriteCallbackP is not NULL, the driver
- * will initiate the transfer and return immediately. The function pointed to
- * by IxI2cMasterWriteCallbackP will be called in the interrupt service
- * handlers when the operation is complete.
- *
- * If in interrupt mode and IxI2cMasterWriteCallbackP is NULL, then the driver
- * will wait for the operation to complete, and then return.
- *
- * And if the repeated start transfer mode is selected, then it will not send a
- * stop signal at the end of all the transfers.
- * *NOTE*: If repeated start transfer mode is selected, it has to end with a
- *			normal mode transfer mode else the bus will continue to be held
- *			by the IXP.
- *
- * @return 
- *      - IX_I2C_SUCCESS - Successfuuly wrote data to slave.
- *		- IX_I2C_MASTER_BUS_BUSY - The I2C bus is busy (held by another I2C master)
- *		- IX_I2C_MASTER_ARB_LOSS - The I2C bus was loss to another I2C master
- *		- IX_I2C_MASTER_XFER_ERROR - There was a transfer error
- *      - IX_I2C_MASTER_BUS_ERROR - There was a bus error during transfer
- *		- IX_I2C_MASTER_NO_BUFFER - buffer pointer is NULL
- *      - IX_I2C_MASTER_INVALID_XFER_MODE - Xfer mode selected is invalid
- *      - IX_I2C_DATA_SIZE_ZERO - dataSize passed in is zero, which is invalid
- *		- IX_I2C_NOT_INIT - I2C not init yet.
- *              
- * @li   Reentrant    : no
- * @li   ISR Callable : no
- *
- */
-PUBLIC IX_I2C_STATUS
-ixI2cDrvWriteTransfer(
-	UINT8 SlaveAddr,
-	char *bufP,
-	UINT32 dataSize,
-	IxI2cXferMode XferModeSelect);
-
-/**
- * @ingroup IxI2cDrv
- * 
- * @fn ixI2cDrvReadTransfer(
-	UINT8 SlaveAddr,
-	char *bufP,
-	UINT32 dataSize,
-	IxI2cXferMode XferModeSelect)
- *
- * @brief Initiates a transfer to receive bytes of data from a slave
- *			device through the I2C bus.
- *
- * @param "UINT8 [in] SlaveAddr" - The slave address to request data from.
- * @param "char [out] *bufP" - The pointer to the buffer to store the
- *			requested data.
- * @param "UINT32 [in] dataSize" - The number of bytes requested.
- * @param "IxI2cXferMode [in] XferModeSelect" - the transfer mode selected,
- *			either repeated start (ends w/o stop) or normal (start and stop)
- *
- * Global Data	:
- *		- None.
- *                        
- * This API will try to obtain master control of the I2C bus and receive the
- * number of bytes, specified by dataSize, from the user specified address
- * into the receive buffer. It will use either interrupt or poll mode depending
- * on the mode selected.
- *
- * If in interrupt mode and IxI2cMasterReadCallbackP is not NULL, the driver
- * will initiate the transfer and return immediately. The function pointed to
- * by IxI2cMasterReadCallbackP will be called in the interrupt service
- * handlers when the operation is complete.
- *
- * If in interrupt mode and IxI2cMasterReadCallbackP is NULL, then the driver will
- * wait for the operation to complete, and then return.
- *
- * And if the repeated start transfer mode is selected, then it will not send a
- * stop signal at the end of all the transfers.
- * *NOTE*: If repeated start transfer mode is selected, it has to end with a
- *			normal mode transfer mode else the bus will continue to be held
- *			by the IXP.
- *
- * @return 
- *      - IX_I2C_SUCCESS - Successfuuly read slave data
- *		- IX_I2C_MASTER_BUS_BUSY - The I2C bus is busy (held by another I2C master)
- *		- IX_I2C_MASTER_ARB_LOSS - The I2C bus was loss to another I2C master
- *		- IX_I2C_MASTER_XFER_ERROR - There was a bus error during transfer
- *      - IX_I2C_MASTER_BUS_ERROR - There was a bus error during transfer
- *		- IX_I2C_MASTER_NO_BUFFER - buffer pointer is NULL
- *      - IX_I2C_MASTER_INVALID_XFER_MODE - Xfer mode selected is invalid
- *      - IX_I2C_INVALID_SLAVE_ADDR - invalid slave address (zero) specified
- *      - IX_I2C_DATA_SIZE_ZERO - dataSize passed in is zero, which is invalid
- *		- IX_I2C_NOT_INIT - I2C not init yet.
- *              
- * @li   Reentrant    : no
- * @li   ISR Callable : no
- *
- */
-PUBLIC IX_I2C_STATUS
-ixI2cDrvReadTransfer(
-	UINT8 SlaveAddr,
-	char *bufP,
-	UINT32 dataSize,
-	IxI2cXferMode XferModeSelect);
-
-/**
- * @ingroup IxI2cDrv
- * 
- * @fn ixI2cDrvSlaveAddrAndGenCallDetectedCheck(
-	void)
- *
- * @brief Checks the I2C Status Register to determine if a slave address is
- *			detected
- *
- * @param - None
- *
- * Global Data	:
- *		- None.
- *                        
- * This API is used in polled mode to determine if the I2C unit is requested
- * for a slave or general call transfer. If it is requested for a slave
- * transfer then it will determine if it is a general call (read only), read,
- * or write transfer requested.
- *
- * @return 
- *      - IX_I2C_SLAVE_ADDR_NOT_DETECTED - The I2C unit is not requested for slave
- *										transfer
- *		- IX_I2C_GEN_CALL_ADDR_DETECTED - The I2C unit is not requested for slave
- *									transfer but for general call
- *      - IX_I2C_SLAVE_READ_DETECTED - The I2C unit is requested for a read
- *      - IX_I2C_SLAVE_WRITE_DETECTED - The I2C unit is requested for a write
- *		- IX_I2C_NOT_INIT - I2C not init yet.
- *              
- * @li   Reentrant    : no
- * @li   ISR Callable : no
- *
- */
-PUBLIC IX_I2C_STATUS
-ixI2cDrvSlaveAddrAndGenCallDetectedCheck(void);
-
-/**
- * @ingroup IxI2cDrv
- * 
- * @fn ixI2cDrvSlaveOrGenDataReceive(
-	char *bufP,
-	UINT32 bufSize,
-	UINT32 *dataSizeRcvd)
- *
- * @brief Performs the slave receive or general call receive data transfer
- *
- * @param	"char [in] *bufP" - the pointer to the buffer to store data
- *			"UINT32 [in] bufSize" - the buffer size allocated
- *			"UINT32 [in] *dataSizeRcvd" - the length of data received in bytes
- *
- * Global Data	:
- *		- None.
- *                        
- * This API is only used in polled mode to perform the slave read or general call
- * receive data. It will continuously store the data received into bufP until
- * complete or until bufP is full in which it will return
- * IX_I2C_SLAVE_OR_GEN_READ_BUFFER_FULL. If in interrupt mode, the callback will be
- * used.
- *
- * @return 
- *      - IX_I2C_SUCCESS - The I2C driver transferred the data successfully.
- *		- IX_I2C_SLAVE_OR_GEN_READ_BUFFER_FULL - The I2C driver has ran out of
- *			space to store the received data.
- *		- IX_I2C_SLAVE_OR_GEN_READ_ERROR - The I2C driver didn't manage to
- *			detect the IDBR Rx Full bit
- *      - IX_I2C_DATA_SIZE_ZERO - bufSize passed in is zero, which is invalid
- *		- IX_I2C_SLAVE_NO_BUFFER - buffer pointer is NULL
- *      - IX_I2C_NULL_POINTER - dataSizeRcvd is NULL
- *		- IX_I2C_NOT_INIT - I2C not init yet.
- *              
- * @li   Reentrant    : no
- * @li   ISR Callable : no
- *
- */
-PUBLIC IX_I2C_STATUS
-ixI2cDrvSlaveOrGenDataReceive(
-	char *bufP,
-	UINT32 bufSize,
-	UINT32 *dataSizeRcvd);
-
-/**
- * @ingroup IxI2cDrv
- * 
- * @fn ixI2cDrvSlaveDataTransmit(
-	char *bufP,
-	UINT32 dataSize,
-	UINT32 *dataSizeXmtd)
- *
- * @brief Performs the slave write data transfer
- *
- * @param	"char [in] *bufP" - the pointer to the buffer for data to be
- *				transmitted
- *			"UINT32 [in] bufSize" - the buffer size allocated
- *			"UINT32 [in] *dataSizeRcvd" - the length of data trasnmitted in
- *				bytes
- *
- * Global Data	:
- *		- None.
- *                        
- * This API is only used in polled mode to perform the slave transmit data. It
- * will continuously transmit the data from bufP until complete or until bufP
- * is empty in which it will return IX_I2C_SLAVE_WRITE_BUFFER_EMPTY. If in
- * interrupt mode, the callback will be used.
- *
- * @return 
- *      - IX_I2C_SUCCESS - The I2C driver transferred the data successfully.
- *      - IX_I2C_SLAVE_WRITE_BUFFER_EMPTY - The I2C driver needs more data to
- *			transmit.
- *      - IX_I2C_SLAVE_WRITE_ERROR -The I2C driver didn't manage to detect the
- *          IDBR Tx empty bit or the slave stop bit.
- *      - IX_I2C_DATA_SIZE_ZERO - dataSize passed in is zero, which is invalid
- *		- IX_I2C_SLAVE_NO_BUFFER - buffer pointer is NULL
- *      - IX_I2C_NULL_POINTER - dataSizeXmtd is NULL
- *		- IX_I2C_NOT_INIT - I2C not init yet.
- *              
- * @li   Reentrant    : no
- * @li   ISR Callable : no
- *
- */
-PUBLIC IX_I2C_STATUS
-ixI2cDrvSlaveDataTransmit(
-	char *bufP,
-	UINT32 dataSize,
-	UINT32 *dataSizeXmtd);
-
-/**
- * @ingroup IxI2cDrv
- * 
- * @fn ixI2cDrvSlaveOrGenCallBufReplenish(
-	char *bufP,
-	UINT32 bufSize)
- *
- * @brief Replenishes the buffer which stores buffer info for both slave and
- *			general call
- *
- * @param	"char [in] *bufP" - pointer to the buffer allocated
- *			"UINT32 [in] bufSize" - size of the buffer
- *
- * Global Data	:
- *		- None.
- *                        
- * This API is only used in interrupt mode for replenishing the same buffer
- * that is used by both slave and generall call by updating the buffer info
- * with new info and clearing previous offsets set by previous transfers.
- *
- * @return 
- *      - None
- *              
- * @li   Reentrant    : no
- * @li   ISR Callable : no
- *
- */
-PUBLIC void
-ixI2cDrvSlaveOrGenCallBufReplenish(
-	char *bufP,
-	UINT32 bufSize);
-
-/**
- * @ingroup IxI2cDrv
- * 
- * @fn ixI2cDrvStatsGet(IxI2cStatsCounters *I2cStats)
- *
- * @brief Returns the I2C Statistics through the pointer passed in
- *
- * @param - "IxI2cStatsCounters [out] *I2cStats" - I2C statistics counter will
- *			be read and written to the location pointed by this pointer.
- *
- * Global Data	:
- *		- None.
- *                        
- * This API will return the statistics counters of the I2C driver.
- *
- * @return 
- *      - IX_I2C_NULL_POINTER - pointer passed in is NULL
- *		- IX_I2C_SUCCESS - successfully obtained I2C statistics
- *              
- * @li   Reentrant    : yes
- * @li   ISR Callable : no
- *
- */
-PUBLIC IX_I2C_STATUS
-ixI2cDrvStatsGet(IxI2cStatsCounters *I2cStats);
-
-/**
- * @ingroup IxI2cDrv
- * 
- * @fn ixI2cDrvStatsReset(void)
- *
- * @brief Reset I2C statistics counters.
- *
- * @param - None
- *
- * Global Data	:
- *		- None.
- *                        
- * This API will reset the statistics counters of the I2C driver.
- *
- * @return 
- *      - None
- *              
- * @li   Reentrant    : yes
- * @li   ISR Callable : no
- *
- */
-PUBLIC void
-ixI2cDrvStatsReset(void);
-
-/**
- * @ingroup IxI2cDrv
- * 
- * @fn ixI2cDrvShow(void)
- *
- * @brief Displays the I2C status register and the statistics counter.
- *
- * @param - None
- *
- * Global Data	:
- *		- None.
- *                        
- * This API will display the I2C Status register and is useful if any error
- * occurs. It displays the detection of bus error, slave address, general call,
- * address, IDBR receive full, IDBR transmit empty, arbitration loss, slave
- * STOP signal, I2C bus busy, unit busy, ack/nack, and read/write mode. It will
- * also call the ixI2cDrvGetStats and then display the statistics counter.
- *
- * @return 
- *		- IX_I2C_SUCCESS - successfully displayed statistics and status register
- *		- IX_I2C_NOT_INIT - I2C not init yet.
- *              
- * @li   Reentrant    : yes
- * @li   ISR Callable : no
- *
- */
-PUBLIC IX_I2C_STATUS
-ixI2cDrvShow(void);
-
-/**
- * @ingroup IxI2cDrv
- * 
- * @fn ixI2cDrvDelayTypeSelect (IxI2cDelayMode delayMechanismSelect)
- *
- * @brief Sets the delay type of either looping delay or OS scheduler delay
- *          according to the argument provided.
- *
- * @param - "IxI2cDelayMode [in] delayTypeSelect" - the I2C delay type selected
- *
- * Global Data	:
- *		- None.
- *                        
- * This API will set the delay type used by the I2C Driver to either looping
- * delay or OS scheduler delay.
- *
- * @return 
- *		- None
- *              
- * @li   Reentrant    : yes
- * @li   ISR Callable : no
- *
- */
-PUBLIC void
-ixI2cDrvDelayTypeSelect (IxI2cDelayMode delayTypeSelect);
-
-#endif /* __ixp46X */
-#endif /* IXI2CDRV_H */
diff --git a/arch/arm/cpu/ixp/npe/include/IxNpeA.h b/arch/arm/cpu/ixp/npe/include/IxNpeA.h
deleted file mode 100644
index 7427cc4..0000000
--- a/arch/arm/cpu/ixp/npe/include/IxNpeA.h
+++ /dev/null
@@ -1,782 +0,0 @@
-#ifndef __doxygen_HIDE  /* This file is not part of the API */
-
-/**
- * @file    IxNpeA.h
- *
- * @date    22-Mar-2002
- *
- * @brief   Header file for the IXP400 ATM NPE API
- *
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- * 
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- * 
- * @par
- * -- End of Copyright Notice --
- */
-
-/**
- * @defgroup IxNpeA IXP400 NPE-A (IxNpeA) API
- *
- * @brief The Public API for the IXP400 NPE-A
- *
- * @{
- */
-
-#ifndef IX_NPE_A_H
-#define IX_NPE_A_H
-
-#include "IxQMgr.h"
-#include "IxOsal.h"
-#include "IxQueueAssignments.h"
-
-/* General Message Ids */
-
-/* ATM Message Ids */
-
-/**
- * @def IX_NPE_A_MSSG_ATM_UTOPIA_CONFIG_WRITE
- *
- * @brief ATM Message ID command to write the data to the offset in the
- * Utopia Configuration Table
- */
-#define IX_NPE_A_MSSG_ATM_UTOPIA_CONFIG_WRITE       0x20
-
-/**
- * @def IX_NPE_A_MSSG_ATM_UTOPIA_CONFIG_LOAD
- *
- * @brief ATM Message ID command triggers the NPE to copy the Utopia
- * Configuration Table to the Utopia coprocessor
- */
-#define IX_NPE_A_MSSG_ATM_UTOPIA_CONFIG_LOAD        0x21
-
-/**
- * @def IX_NPE_A_MSSG_ATM_UTOPIA_STATUS_UPLOAD
- *
- * @brief ATM Message ID command triggers the NPE to read-back the Utopia
- * status registers and update the Utopia Status Table.
- */
-#define IX_NPE_A_MSSG_ATM_UTOPIA_STATUS_UPLOAD      0x22
-
-/**
- * @def IX_NPE_A_MSSG_ATM_UTOPIA_STATUS_READ
- *
- * @brief ATM Message ID command to read the Utopia Status Table at the
- * specified offset.
- */
-#define IX_NPE_A_MSSG_ATM_UTOPIA_STATUS_READ        0x23
-
-/**
- * @def IX_NPE_A_MSSG_ATM_TX_ENABLE
- *
- * @brief ATM Message ID command triggers the NPE to re-enable processing
- * of any entries on the TxVcQ for this port.
- *
- * This command will be ignored for a port already enabled
- */
-#define IX_NPE_A_MSSG_ATM_TX_ENABLE                 0x25
-
- /**
- * @def IX_NPE_A_MSSG_ATM_TX_DISABLE
- *
- * @brief ATM Message ID command triggers the NPE to disable processing on
- * this port
- *
- * This command will be ignored for a port already disabled
- */
-#define IX_NPE_A_MSSG_ATM_TX_DISABLE                0x26
-
-/**
- * @def IX_NPE_A_MSSG_ATM_RX_ENABLE
- *
- * @brief ATM Message ID command triggers the NPE to process any received
- * cells for this VC according to the VC Lookup Table.
- *
- * Re-issuing this command with different contents for a VC that is not
- * disabled will cause unpredictable behavior.
- */
-#define IX_NPE_A_MSSG_ATM_RX_ENABLE                 0x27
-
-/**
- * @def IX_NPE_A_MSSG_ATM_RX_DISABLE
- *
- * @brief ATM Message ID command triggers the NPE to disable processing for
- * this VC.
- *
- * This command will be ignored for a VC already disabled
- */
-#define IX_NPE_A_MSSG_ATM_RX_DISABLE                0x28
-
-/**
- * @def IX_NPE_A_MSSG_ATM_STATUS_READ
- *
- * @brief ATM Message ID command to read the ATM status. The data is returned via
- * a response message
- */
-#define IX_NPE_A_MSSG_ATM_STATUS_READ               0x29
-
-/*--------------------------------------------------------------------------
- * HSS Message IDs
- *--------------------------------------------------------------------------*/
-
-/**
- * @def IX_NPE_A_MSSG_HSS_PORT_CONFIG_WRITE
- *
- * @brief HSS Message ID command writes the ConfigWord value to the location
- * in the HSS_CONFIG_TABLE specified by offset for HSS port hPort.
- */
-#define IX_NPE_A_MSSG_HSS_PORT_CONFIG_WRITE         0x40
-
-/**
- * @def IX_NPE_A_MSSG_HSS_PORT_CONFIG_LOAD
- *
- * @brief HSS Message ID command triggers the NPE to copy the contents of the
- * HSS Configuration Table to the appropriate configuration registers in the
- * HSS coprocessor for the port specified by hPort.
- */
-#define IX_NPE_A_MSSG_HSS_PORT_CONFIG_LOAD          0x41
-
-/**
- * @def IX_NPE_A_MSSG_HSS_PORT_ERROR_READ
- *
- * @brief HSS Message ID command triggers the NPE to return an HssErrorReadResponse
- * message for HSS port hPort.
- */
-#define IX_NPE_A_MSSG_HSS_PORT_ERROR_READ           0x42
-
-/**
- * @def IX_NPE_A_MSSG_HSS_CHAN_FLOW_ENABLE
- *
- * @brief HSS Message ID command triggers the NPE to reset internal status and
- * enable the HssChannelized operation on the HSS port specified by hPort.
- */
-#define IX_NPE_A_MSSG_HSS_CHAN_FLOW_ENABLE          0x43
-
-/**
- * @def IX_NPE_A_MSSG_HSS_CHAN_FLOW_DISABLE
- *
- * @brief HSS Message ID command triggers the NPE to disable the HssChannelized
- * operation on the HSS port specified by hPort.
- */
-#define IX_NPE_A_MSSG_HSS_CHAN_FLOW_DISABLE         0x44
-
-/**
- * @def  IX_NPE_A_MSSG_HSS_CHAN_IDLE_PATTERN_WRITE
- *
- * @brief HSS Message ID command writes the HSSnC_IDLE_PATTERN value for HSS
- * port hPort. (n=hPort)
- */
-#define IX_NPE_A_MSSG_HSS_CHAN_IDLE_PATTERN_WRITE   0x45
-
-/**
- * @def IX_NPE_A_MSSG_HSS_CHAN_NUM_CHANS_WRITE
- *
- * @brief HSS Message ID command writes the HSSnC_NUM_CHANNELS value for HSS
- * port hPort. (n=hPort)
- */
-#define IX_NPE_A_MSSG_HSS_CHAN_NUM_CHANS_WRITE      0x46
-
-/**
- * @def IX_NPE_A_MSSG_HSS_CHAN_RX_BUF_ADDR_WRITE
- *
- * @brief HSS Message ID command writes the HSSnC_RX_BUF_ADDR value for HSS
- * port hPort. (n=hPort)
- */
-#define IX_NPE_A_MSSG_HSS_CHAN_RX_BUF_ADDR_WRITE    0x47
-
-/**
- * @def IX_NPE_A_MSSG_HSS_CHAN_RX_BUF_CFG_WRITE
- *
- * @brief HSS Message ID command  writes the HSSnC_RX_BUF_SIZEB and
- * HSSnC_RX_TRIG_PERIOD values for HSS port hPort.  (n=hPort)
- */
-#define IX_NPE_A_MSSG_HSS_CHAN_RX_BUF_CFG_WRITE     0x48
-
-/**
- * @def IX_NPE_A_MSSG_HSS_CHAN_TX_BLK_CFG_WRITE
- *
- * @brief HSS Message ID command writes the HSSnC_TX_BLK1_SIZEB,
- * HSSnC_TX_BLK1_SIZEW, HSSnC_TX_BLK2_SIZEB, and HSSnC_TX_BLK2_SIZEW  values
- * for HSS port hPort. (n=hPort)
- */
-#define IX_NPE_A_MSSG_HSS_CHAN_TX_BLK_CFG_WRITE     0x49
-
-/**
- * @def IX_NPE_A_MSSG_HSS_CHAN_TX_BUF_ADDR_WRITE
- * @brief HSS Message ID command writes the HSSnC_TX_BUF_ADDR value for HSS
- * port hPort. (n=hPort)
- */
-#define IX_NPE_A_MSSG_HSS_CHAN_TX_BUF_ADDR_WRITE    0x4A
-
-/**
- * @def IX_NPE_A_MSSG_HSS_CHAN_TX_BUF_SIZE_WRITE
- *
- * @brief HSS Message ID command writes the HSSnC_TX_BUF_SIZEN value for HSS
- * port hPort. (n=hPort)
- */
-#define IX_NPE_A_MSSG_HSS_CHAN_TX_BUF_SIZE_WRITE    0x4B
-
-/**
- * @def IX_NPE_A_MSSG_HSS_PKT_PIPE_FLOW_ENABLE
- *
- * @brief HSS Message ID command triggers the NPE to reset internal status and
- * enable the HssPacketized operation for the flow specified by pPipe on
- * the HSS port specified by hPort.
- */
-#define IX_NPE_A_MSSG_HSS_PKT_PIPE_FLOW_ENABLE      0x50
-
-/**
- * @def IX_NPE_A_MSSG_HSS_PKT_PIPE_FLOW_DISABLE
- * @brief HSS Message ID command triggers the NPE to disable the HssPacketized
- * operation for the flow specified by pPipe on the HSS port specified by hPort.
- */
-#define IX_NPE_A_MSSG_HSS_PKT_PIPE_FLOW_DISABLE     0x51
-
-/**
- * @def IX_NPE_A_MSSG_HSS_PKT_NUM_PIPES_WRITE
- * @brief HSS Message ID command writes the HSSnP_NUM_PIPES value for HSS
- * port hPort.(n=hPort)
- */
-#define IX_NPE_A_MSSG_HSS_PKT_NUM_PIPES_WRITE       0x52
-
-/**
- * @def IX_NPE_A_MSSG_HSS_PKT_PIPE_FIFO_SIZEW_WRITE
- *
- * @brief HSS Message ID command writes the HSSnP_PIPEp_FIFOSIZEW value for
- * packet-pipe pPipe on HSS port hPort.  (n=hPort, p=pPipe)
- */
-#define IX_NPE_A_MSSG_HSS_PKT_PIPE_FIFO_SIZEW_WRITE 0x53
-
-/**
- * @def IX_NPE_A_MSSG_HSS_PKT_PIPE_HDLC_CFG_WRITE
- *
- * @brief HSS Message ID command writes the HSSnP_PIPEp_HDLC_RXCFG and
- * HSSnP_PIPEp_HDLC_TXCFG values for packet-pipe pPipe on HSS port hPort.
- * (n=hPort, p=pPipe)
- */
-#define IX_NPE_A_MSSG_HSS_PKT_PIPE_HDLC_CFG_WRITE   0x54
-
-/**
- * @def IX_NPE_A_MSSG_HSS_PKT_PIPE_IDLE_PATTERN_WRITE
- *
- * @brief HSS Message ID command writes the HSSnP_PIPEp_IDLE_PATTERN value
- * for packet-pipe pPipe on HSS port hPort.  (n=hPort, p=pPipe)
- */
-#define IX_NPE_A_MSSG_HSS_PKT_PIPE_IDLE_PATTERN_WRITE 0x55
-
-/**
- * @def IX_NPE_A_MSSG_HSS_PKT_PIPE_RX_SIZE_WRITE
- *
- * @brief HSS Message ID command writes the HSSnP_PIPEp_RXSIZEB value for
- * packet-pipe pPipe on HSS port hPort.  (n=hPort, p=pPipe)
- */
-#define IX_NPE_A_MSSG_HSS_PKT_PIPE_RX_SIZE_WRITE    0x56
-
-/**
- * @def IX_NPE_A_MSSG_HSS_PKT_PIPE_MODE_WRITE
- *
- * @brief HSS Message ID command writes the HSSnP_PIPEp_MODE value for
- * packet-pipe pPipe on HSS port hPort.  (n=hPort, p=pPipe)
- */
-#define IX_NPE_A_MSSG_HSS_PKT_PIPE_MODE_WRITE       0x57
-
-
-
-/* Queue Entry Masks */
-
-/*--------------------------------------------------------------------------
- *  ATM Descriptor Structure offsets
- *--------------------------------------------------------------------------*/
-
-/**
- * @def IX_NPE_A_RXDESCRIPTOR_STATUS_OFFSET
- *
- * @brief ATM Descriptor structure offset for Receive Descriptor Status field
- *
- * It is used for descriptor error reporting.
- */
-#define IX_NPE_A_RXDESCRIPTOR_STATUS_OFFSET          0
-
-/**
- * @def IX_NPE_A_RXDESCRIPTOR_VCID_OFFSET
- *
- * @brief ATM Descriptor structure offset for Receive Descriptor VC ID field
- *
- * It is used to hold an identifier number for this VC
- */
-#define IX_NPE_A_RXDESCRIPTOR_VCID_OFFSET            1
-
-/**
- * @def IX_NPE_A_RXDESCRIPTOR_CURRMBUFSIZE_OFFSET
- *
- * @brief ATM Descriptor structure offset for Receive Descriptor Current Mbuf
- * Size field
- *
- * Number of bytes the current mbuf data buffer can hold
- */
-#define IX_NPE_A_RXDESCRIPTOR_CURRMBUFSIZE_OFFSET    2
-
-/**
- * @def IX_NPE_A_RXDESCRIPTOR_ATMHEADER_OFFSET
- *
- * @brief ATM Descriptor structure offset for Receive Descriptor ATM Header
- */
-#define IX_NPE_A_RXDESCRIPTOR_ATMHEADER_OFFSET       4
-
-/**
- * @def IX_NPE_A_RXDESCRIPTOR_CURRMBUFLEN_OFFSET
- *
- * @brief ATM Descriptor structure offset for Receive Descriptor Current MBuf length
- *
- *
- * RX - Initialized to zero.  The NPE updates this field as each cell is received and
- * zeroes it with every new mbuf for chaining. Will not be bigger than currBbufSize.
- */
-#define IX_NPE_A_RXDESCRIPTOR_CURRMBUFLEN_OFFSET    12
-
-/**
- * @def IX_NPE_A_RXDESCRIPTOR_TIMELIMIT__OFFSET
- *
- * @brief ATM Descriptor structure offset for Receive Descriptor Time Limit field
- *
- * Contains the Payload Reassembly Time Limit (used for aal0_xx only)
- */
-#define IX_NPE_A_RXDESCRIPTOR_TIMELIMIT_OFFSET        14
-
-/**
- * @def IX_NPE_A_RXDESCRIPTOR_PCURRMBUFF_OFFSET
- *
- * @brief ATM Descriptor structure offset for Receive Descriptor Current MBuf Pointer
- *
- * The current mbuf pointer of a chain of mbufs.
- */
-#define IX_NPE_A_RXDESCRIPTOR_PCURRMBUFF_OFFSET     20
-
-/**
- * @def IX_NPE_A_RXDESCRIPTOR_PCURRMBUFDATA_OFFSET
- *
- * @brief ATM Descriptor structure offset for Receive Descriptor Current MBuf Pointer
- *
- * Pointer to the next byte to be read or next free location to be written.
- */
-#define IX_NPE_A_RXDESCRIPTOR_PCURRMBUFDATA_OFFSET  24
-
-/**
- * @def IX_NPE_A_RXDESCRIPTOR_PNEXTMBUF_OFFSET
- *
- * @brief ATM Descriptor structure offset for Receive Descriptor Next MBuf Pointer
- *
- * Pointer to the next MBuf in a chain of MBufs.
- */
-#define IX_NPE_A_RXDESCRIPTOR_PNEXTMBUF_OFFSET      28
-
-/**
- * @def IX_NPE_A_RXDESCRIPTOR_TOTALLENGTH_OFFSET
- *
- * @brief ATM Descriptor structure offset for Receive Descriptor Total Length
- *
- * Total number of bytes written to the chain of MBufs by the NPE
- */
-#define IX_NPE_A_RXDESCRIPTOR_TOTALLENGTH_OFFSET    32
-
-/**
- * @def IX_NPE_A_RXDESCRIPTOR_AAL5CRCRESIDUE_OFFSET
- *
- * @brief ATM Descriptor structure offset for Receive Descriptor AAL5 CRC Residue
- *
- * Current CRC value for a PDU
- */
-#define IX_NPE_A_RXDESCRIPTOR_AAL5CRCRESIDUE_OFFSET 36
-
-/**
- * @def IX_NPE_A_RXDESCRIPTOR_SIZE
- *
- * @brief ATM Descriptor structure offset for Receive Descriptor Size
- *
- * The size of the Receive descriptor
- */
-#define IX_NPE_A_RXDESCRIPTOR_SIZE                  40
-
-/**
- * @def IX_NPE_A_TXDESCRIPTOR_PORT_OFFSET
- *
- * @brief ATM Descriptor structure offset for Transmit Descriptor Port
- *
- * Port identifier.
- */
-#define IX_NPE_A_TXDESCRIPTOR_PORT_OFFSET            0
-
-/**
- * @def IX_NPE_A_TXDESCRIPTOR_RSVD_OFFSET
- *
- * @brief ATM Descriptor structure offset for Transmit Descriptor RSVD
- */
-#define IX_NPE_A_TXDESCRIPTOR_RSVD_OFFSET            1
-
-/**
- * @def IX_NPE_A_TXDESCRIPTOR_CURRMBUFLEN_OFFSET
- *
- * @brief ATM Descriptor structure offset for Transmit Descriptor Current MBuf Length
- *
- * TX - Initialized by the XScale to the number of bytes in the current MBuf data buffer.
- * The NPE decrements this field for every transmitted cell.  Thus, when the NPE writes a
- * descriptor the TxDone queue, this field will equal zero.
- */
-#define IX_NPE_A_TXDESCRIPTOR_CURRMBUFLEN_OFFSET     2
-
-/**
- * @def IX_NPE_A_TXDESCRIPTOR_ATMHEADER_OFFSET
- * @brief ATM Descriptor structure offset for Transmit Descriptor ATM Header
- */
-#define IX_NPE_A_TXDESCRIPTOR_ATMHEADER_OFFSET       4
-
-/**
- * @def IX_NPE_A_TXDESCRIPTOR_PCURRMBUFF_OFFSET
- *
- * @brief ATM Descriptor structure offset for Transmit Descriptor Pointer to the current MBuf chain
- */
-#define IX_NPE_A_TXDESCRIPTOR_PCURRMBUFF_OFFSET      8
-
-/**
- * @def IX_NPE_A_TXDESCRIPTOR_PCURRMBUFDATA_OFFSET
- *
- * @brief ATM Descriptor structure offset for Transmit Descriptor Pointer to the current MBuf Data
- *
- * Pointer to the next byte to be read or next free location to be written.
- */
-#define IX_NPE_A_TXDESCRIPTOR_PCURRMBUFDATA_OFFSET  12
-
-/**
- * @def IX_NPE_A_TXDESCRIPTOR_PNEXTMBUF_OFFSET
- *
- * @brief ATM Descriptor structure offset for Transmit Descriptor Pointer to the Next MBuf chain
- */
-#define IX_NPE_A_TXDESCRIPTOR_PNEXTMBUF_OFFSET      16
-
-/**
- * @def IX_NPE_A_TXDESCRIPTOR_TOTALLENGTH_OFFSET
- *
- * @brief ATM Descriptor structure offset for Transmit Descriptor Total Length
- *
- * Total number of bytes written to the chain of MBufs by the NPE
- */
-#define IX_NPE_A_TXDESCRIPTOR_TOTALLENGTH_OFFSET    20
-
-/**
- * @def IX_NPE_A_TXDESCRIPTOR_AAL5CRCRESIDUE_OFFSET
- *
- * @brief ATM Descriptor structure offset for Transmit Descriptor AAL5 CRC Residue
- *
- * Current CRC value for a PDU
- */
-#define IX_NPE_A_TXDESCRIPTOR_AAL5CRCRESIDUE_OFFSET 24
-
-/**
- * @def IX_NPE_A_TXDESCRIPTOR_SIZE
- *
- * @brief ATM Descriptor structure offset for Transmit Descriptor Size
- */
-#define IX_NPE_A_TXDESCRIPTOR_SIZE                  28
-
-/**
- * @def IX_NPE_A_CHAIN_DESC_COUNT_MAX
- *
- * @brief Maximum number of chained MBufs that can be chained together
- */
-#define IX_NPE_A_CHAIN_DESC_COUNT_MAX            256
-
-/*
- *  Definition of the ATM cell header
- *
- * This would most conviently be defined as the bit field shown below.
- * Endian portability prevents this, therefore a set of macros
- * are defined to access the fields within the cell header assumed to
- * be passed as a UINT32.
- *
- * Changes to field sizes or orders must be reflected in the offset
- * definitions above.
- *
- *    typedef struct
- *    {
- *       unsigned int gfc:4;
- *       unsigned int vpi:8;
- *       unsigned int vci:16;
- *       unsigned int pti:3;
- *       unsigned int clp:1;
- *    } IxNpeA_AtmCellHeader;
- *
- */
-
-/** Mask to acess GFC */
-#define GFC_MASK        0xf0000000
-
-/** return GFC from ATM cell header */
-#define IX_NPE_A_ATMCELLHEADER_GFC_GET( header ) \
-(((header) & GFC_MASK) >> 28)
-
-/** set GFC into ATM cell header */
-#define IX_NPE_A_ATMCELLHEADER_GFC_SET( header,gfc ) \
-do { \
-    (header) &= ~GFC_MASK; \
-    (header) |= (((gfc) << 28) & GFC_MASK); \
-} while(0)
-
-/** Mask to acess VPI */
-#define VPI_MASK        0x0ff00000
-
-/** return VPI from ATM cell header */
-#define IX_NPE_A_ATMCELLHEADER_VPI_GET( header ) \
-(((header) & VPI_MASK) >> 20)
-
-/** set VPI into ATM cell header */
-#define IX_NPE_A_ATMCELLHEADER_VPI_SET( header, vpi ) \
-do { \
-    (header) &= ~VPI_MASK; \
-    (header) |= (((vpi) << 20) & VPI_MASK); \
-} while(0)
-
-/** Mask to acess VCI */
-#define VCI_MASK        0x000ffff0
-
-/** return VCI from ATM cell header */
-#define IX_NPE_A_ATMCELLHEADER_VCI_GET( header ) \
-(((header) & VCI_MASK) >> 4)
-
-/** set VCI into ATM cell header */
-#define IX_NPE_A_ATMCELLHEADER_VCI_SET( header, vci ) \
-do { \
-    (header) &= ~VCI_MASK; \
-    (header) |= (((vci) << 4) & VCI_MASK); \
-} while(0)
-
-/** Mask to acess PTI */
-#define PTI_MASK        0x0000000e
-
-/** return PTI from ATM cell header */
-#define IX_NPE_A_ATMCELLHEADER_PTI_GET( header ) \
-(((header) & PTI_MASK) >> 1)
-
-/** set PTI into ATM cell header */
-#define IX_NPE_A_ATMCELLHEADER_PTI_SET( header, pti ) \
-do { \
-    (header) &= ~PTI_MASK; \
-    (header) |= (((pti) << 1) & PTI_MASK); \
-} while(0)
-
-/** Mask to acess CLP */
-#define CLP_MASK        0x00000001
-
-/** return CLP from ATM cell header */
-#define IX_NPE_A_ATMCELLHEADER_CLP_GET( header ) \
-((header) & CLP_MASK)
-
-/** set CLP into ATM cell header */
-#define IX_NPE_A_ATMCELLHEADER_CLP_SET( header, clp ) \
-do { \
-    (header) &= ~CLP_MASK; \
-    (header) |= ((clp) & CLP_MASK); \
-} while(0)
-
-
-/*
-* Definition of the Rx bitfield
-*
-* This would most conviently be defined as the bit field shown below.
-* Endian portability prevents this, therefore a set of macros
-* are defined to access the fields within the rxBitfield assumed to
-* be passed as a UINT32.
-*
-* Changes to field sizes or orders must be reflected in the offset
-* definitions above.
-*
-* Rx bitfield
-*    struct
-*    {   IX_NPEA_RXBITFIELD(
-*        unsigned int status:1,
-*        unsigned int port:7,
-*        unsigned int vcId:8,
-*        unsigned int currMbufSize:16);
-*    } rxBitField;
-*
-*/
-
-/** Mask to acess the rxBitField status */
-#define STATUS_MASK     0x80000000
-
-/** return the rxBitField status */
-#define IX_NPE_A_RXBITFIELD_STATUS_GET( rxbitfield ) \
-(((rxbitfield) & STATUS_MASK) >> 31)
-
-/** set the rxBitField status */
-#define IX_NPE_A_RXBITFIELD_STATUS_SET( rxbitfield, status ) \
-do { \
-    (rxbitfield) &= ~STATUS_MASK; \
-    (rxbitfield) |= (((status) << 31) & STATUS_MASK); \
-} while(0)
-
-/** Mask to acess the rxBitField port */
-#define PORT_MASK       0x7f000000
-
-/** return the rxBitField port */
-#define IX_NPE_A_RXBITFIELD_PORT_GET( rxbitfield ) \
-(((rxbitfield) & PORT_MASK) >> 24)
-
-/** set the rxBitField port */
-#define IX_NPE_A_RXBITFIELD_PORT_SET( rxbitfield, port ) \
-do { \
-    (rxbitfield) &= ~PORT_MASK; \
-    (rxbitfield) |= (((port) << 24) & PORT_MASK); \
-} while(0)
-
-/** Mask to acess the rxBitField vcId */
-#define VCID_MASK       0x00ff0000
-
-/** return the rxBitField vcId */
-#define IX_NPE_A_RXBITFIELD_VCID_GET( rxbitfield ) \
-(((rxbitfield) & VCID_MASK) >> 16)
-
-/** set the rxBitField vcId */
-#define IX_NPE_A_RXBITFIELD_VCID_SET( rxbitfield, vcid ) \
-do { \
-    (rxbitfield) &= ~VCID_MASK; \
-    (rxbitfield) |= (((vcid) << 16) & VCID_MASK); \
-} while(0)
-
-/** Mask to acess the rxBitField mbuf size */
-#define CURRMBUFSIZE_MASK       0x0000ffff
-
-/** return the rxBitField mbuf size */
-#define IX_NPE_A_RXBITFIELD_CURRMBUFSIZE_GET( rxbitfield ) \
-((rxbitfield) & CURRMBUFSIZE_MASK)
-
-/** set the rxBitField mbuf size */
-#define IX_NPE_A_RXBITFIELD_CURRMBUFSIZE_SET( rxbitfield, currmbufsize ) \
-do { \
-    (rxbitfield) &= ~CURRMBUFSIZE_MASK; \
-    (rxbitfield) |= ((currmbufsize) & CURRMBUFSIZE_MASK); \
-} while(0)
-
-
-
-/**
- * @brief Tx Descriptor definition
- */
-typedef struct
-{
-    UINT8 port;				/**< Tx Port number */
-    UINT8 aalType; 			/**< AAL Type */
-    UINT16 currMbufLen;			/**< mbuf length */
-    UINT32 atmCellHeader;		/**< ATM cell header */
-    IX_OSAL_MBUF *pCurrMbuf;	        /**< pointer to mbuf */
-    unsigned char *pCurrMbufData;	/**< Pointer to mbuf->dat */
-    IX_OSAL_MBUF *pNextMbuf;		/**< Pointer to next mbuf */
-    UINT32  totalLen;			/**< Total Length */
-    UINT32  aal5CrcResidue;		/**< AAL5 CRC Residue */
-} IxNpeA_TxAtmVc;
-
-/* Changes to field sizes or orders must be reflected in the offset
- * definitions above. */
-
-
-
-
-/**
- * @brief Rx Descriptor definition
- */
-typedef struct
-{
-    UINT32  rxBitField;			/**< Recieved bit field */
-    UINT32  atmCellHeader;		/**< ATM Cell Header */
-    UINT32  rsvdWord0;                  /**< Reserved field */
-    UINT16  currMbufLen;		/**< Mbuf Length */
-    UINT8   timeLimit; 			/**< Payload Reassembly timeLimit (used for aal0_xx only) */
-    UINT8   rsvdByte0;                  /**< Reserved field */ 
-    UINT32  rsvdWord1;   		/**< Reserved field */
-    IX_OSAL_MBUF *pCurrMbuf;		/**< Pointer to current mbuf */
-    unsigned char *pCurrMbufData;	/**< Pointer to current mbuf->data */
-    IX_OSAL_MBUF *pNextMbuf;		/**< Pointer to next mbuf */
-    UINT32  totalLen;			/**< Total Length */
-    UINT32  aal5CrcResidue;		/**< AAL5 CRC Residue */
-} IxNpeA_RxAtmVc;
-
-
-/**
- * @brief NPE-A AAL Type
- */
-typedef enum
-{
-    IX_NPE_A_AAL_TYPE_INVALID = 0,	/**< Invalid AAL type */
-    IX_NPE_A_AAL_TYPE_0_48    = 0x1,	/**< AAL0 - 48 byte */
-    IX_NPE_A_AAL_TYPE_0_52    = 0x2,	/**< AAL0 - 52 byte */
-    IX_NPE_A_AAL_TYPE_5       = 0x5,	/**< AAL5 */
-    IX_NPE_A_AAL_TYPE_OAM     = 0xF	/**< OAM */
-} IxNpeA_AalType;
-
-/**
- * @brief NPE-A Payload format 52-bytes & 48-bytes
- */
-typedef enum
-{
-    IX_NPE_A_52_BYTE_PAYLOAD = 0,	/**< 52 byte payload */
-    IX_NPE_A_48_BYTE_PAYLOAD		/**< 48 byte payload */
-} IxNpeA_PayloadFormat;
-
-/**
- * @brief  HSS Packetized NpePacket Descriptor Structure
- */
-typedef struct
-{
-    UINT8   status;		/**< Status of the packet passed to the client */
-    UINT8   errorCount;		/**< Number of errors */
-    UINT8   chainCount;		/**< Mbuf chain count e.g. 0 - No mbuf chain */
-    UINT8   rsvdByte0;		/**< Reserved byte to make the descriptor word align */
-
-    UINT16  packetLength;	/**< Packet Length */
-    UINT16  rsvdShort0;		/**< Reserved short to make the descriptor a word align */
-
-    IX_OSAL_MBUF *pRootMbuf;	/**< Pointer to Root mbuf */
-    IX_OSAL_MBUF *pNextMbuf;	/**< Pointer to next mbuf */
-    UINT8   *pMbufData;		/**< Pointer to the current mbuf->data */
-    UINT32  mbufLength;		/**< Current mbuf length */
-
-} IxNpeA_NpePacketDescriptor;
-
-
-#endif
-/**
- *@}
- */
-
-#endif /* __doxygen_HIDE */
diff --git a/arch/arm/cpu/ixp/npe/include/IxNpeDl.h b/arch/arm/cpu/ixp/npe/include/IxNpeDl.h
deleted file mode 100644
index 86f69f4..0000000
--- a/arch/arm/cpu/ixp/npe/include/IxNpeDl.h
+++ /dev/null
@@ -1,980 +0,0 @@
-/**
- * @file IxNpeDl.h
- *
- * @date 14 December 2001
-
- * @brief This file contains the public API of the IXP400 NPE Downloader
- *        component.
- *
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- * 
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- * 
- * @par
- * -- End of Copyright Notice --
-*/
-
-/**
- * @defgroup IxNpeDl IXP400 NPE-Downloader (IxNpeDl) API
- *
- * @brief The Public API for the IXP400 NPE Downloader
- *
- * @{
- */
-
-#ifndef IXNPEDL_H
-#define IXNPEDL_H
-
-/*
- * Put the user defined include files required
- */
-#include "IxOsalTypes.h"
-#include "IxNpeMicrocode.h"
-
-/*
- * #defines for function return types, etc.
- */
-
-/**
- * @def IX_NPEDL_PARAM_ERR
- *
- * @brief NpeDl function return value for a parameter error
- */
-#define IX_NPEDL_PARAM_ERR               2
-
-/**
- * @def IX_NPEDL_RESOURCE_ERR
- *
- * @brief NpeDl function return value for a resource error
- */
-#define IX_NPEDL_RESOURCE_ERR            3
-
-/**
- * @def IX_NPEDL_CRITICAL_NPE_ERR
- *
- * @brief NpeDl function return value for a Critical NPE error occuring during
-          download. Assume NPE is left in unstable condition if this value is
-          returned or NPE is hang / halt.
- */
-#define IX_NPEDL_CRITICAL_NPE_ERR        4
-
-/**
- * @def IX_NPEDL_CRITICAL_MICROCODE_ERR
- *
- * @brief NpeDl function return value for a Critical Microcode error
- *        discovered during download. Assume NPE is left in unstable condition
- *        if this value is returned.
- */
-#define IX_NPEDL_CRITICAL_MICROCODE_ERR  5
-
-/**
- * @def IX_NPEDL_DEVICE_ERR
- *
- * @brief NpeDl function return value when image being downloaded
- *        is not meant for the device in use
- */
-#define IX_NPEDL_DEVICE_ERR 6 
-
-/**
- * @defgroup NPEImageID IXP400 NPE Image ID Definition
- *
- * @ingroup IxNpeDl
- *
- * @brief Definition of NPE Image ID to be passed to ixNpeDlNpeInitAndStart()
- *        as input of type UINT32 which has the following fields format:
- *
- *               Field [Bit Location] <BR>
- *               -------------------- <BR>
- *               Device ID [31 - 28] <BR>
- *               NPE ID [27 - 24] <BR>
- *               NPE Functionality ID [23 - 16] <BR>
- *               Major Release Number [15 -  8] <BR>
- *               Minor Release Number [7 - 0] <BR>
- *
- *
- * @{
- */
-
-/**
- * @def IX_NPEDL_NPEIMAGE_FIELD_MASK
- *
- * @brief Mask for NPE Image ID's Field
- *
- * @warning <b>THIS #define HAS BEEN DEPRECATED AND SHOULD NOT BE USED.</b>
- *       It will be removed in a future release.
- *       See @ref ixNpeDlNpeInitAndStart for more information.
- */
-#define IX_NPEDL_NPEIMAGE_FIELD_MASK  0xff
-
-/**
- * @def IX_NPEDL_NPEIMAGE_NPEID_MASK
- *
- * @brief Mask for NPE Image NPE ID's Field
- *
- */
-#define IX_NPEDL_NPEIMAGE_NPEID_MASK  0xf
-
-/**
- * @def IX_NPEDL_NPEIMAGE_DEVICEID_MASK
- *
- * @brief Mask for NPE Image Device ID's Field
- *
- */
-#define IX_NPEDL_NPEIMAGE_DEVICEID_MASK  0xf
-
-/**
- * @def IX_NPEDL_NPEIMAGE_BIT_LOC_NPEID
- *
- * @brief Location of NPE ID field in term of bit.
- *
- * @warning <b>THIS #define HAS BEEN DEPRECATED AND SHOULD NOT BE USED.</b>
- *       It will be removed in a future release.
- *       See @ref ixNpeDlNpeInitAndStart for more information.
- */
-#define IX_NPEDL_NPEIMAGE_BIT_LOC_NPEID  24
-
-/**
- * @def IX_NPEDL_NPEIMAGE_BIT_LOC_FUNCTIONALITYID
- *
- * @brief Location of Functionality ID field in term of bit.
- *
- * @warning <b>THIS #define HAS BEEN DEPRECATED AND SHOULD NOT BE USED.</b>
- *       It will be removed in a future release.
- *       See @ref ixNpeDlNpeInitAndStart for more information.
- */
-#define IX_NPEDL_NPEIMAGE_BIT_LOC_FUNCTIONALITYID  16
-
-/**
- * @def IX_NPEDL_NPEIMAGE_BIT_LOC_MAJOR
- *
- * @brief Location of Major Release Number field in term of bit.
- *
- * @warning <b>THIS #define HAS BEEN DEPRECATED AND SHOULD NOT BE USED.</b>
- *       It will be removed in a future release.
- *       See @ref ixNpeDlNpeInitAndStart for more information.
- */
-#define IX_NPEDL_NPEIMAGE_BIT_LOC_MAJOR  8
-
-/**
- * @def IX_NPEDL_NPEIMAGE_BIT_LOC_MINOR
- *
- * @brief Location of Minor Release Number field in term of bit.
- *
- * @warning <b>THIS #define HAS BEEN DEPRECATED AND SHOULD NOT BE USED.</b>
- *       It will be removed in a future release.
- *       See @ref ixNpeDlNpeInitAndStart for more information.
- */
-#define IX_NPEDL_NPEIMAGE_BIT_LOC_MINOR  0
-
-/**
- * @} addtogroup NPEImageID
- */
-
-/**
- * @def ixNpeDlMicrocodeImageOverride(x)
- *
- * @brief  Map old terminology that uses term "image" to new term
- *        "image library"
- *
- * @warning <b>THIS #define HAS BEEN DEPRECATED AND SHOULD NOT BE USED.</b>
- *       It will be removed in a future release.
- *       See @ref ixNpeDlNpeInitAndStart for more information.
- */
-#define ixNpeDlMicrocodeImageOverride(x) ixNpeDlMicrocodeImageLibraryOverride(x)
-
-/**
- * @def IxNpeDlVersionId
- *
- * @brief  Map old terminology that uses term "version" to new term
- *        "image"
- *
- * @warning <b>THIS #define HAS BEEN DEPRECATED AND SHOULD NOT BE USED.</b>
- *       It will be removed in a future release.
- *       See @ref ixNpeDlNpeInitAndStart for more information.
- */
-#define IxNpeDlVersionId IxNpeDlImageId
-
-/**
- * @def ixNpeDlVersionDownload
- *
- * @brief  Map old terminology that uses term "version" to new term
- *        "image"
- *
- * @warning <b>THIS #define HAS BEEN DEPRECATED AND SHOULD NOT BE USED.</b>
- *       It will be removed in a future release.
- *       See @ref ixNpeDlNpeInitAndStart for more information.
- */
-#define ixNpeDlVersionDownload(x,y) ixNpeDlImageDownload(x,y)
-
-/**
- * @def ixNpeDlAvailableVersionsCountGet
- *
- * @brief  Map old terminology that uses term "version" to new term
- *        "image"
- *
- * @warning <b>THIS #define HAS BEEN DEPRECATED AND SHOULD NOT BE USED.</b>
- *       It will be removed in a future release.
- *       See @ref ixNpeDlNpeInitAndStart for more information.
- */
-#define ixNpeDlAvailableVersionsCountGet(x) ixNpeDlAvailableImagesCountGet(x)
-
-/**
- * @def ixNpeDlAvailableVersionsListGet
- *
- * @brief  Map old terminology that uses term "version" to new term
- *        "image"
- *
- * @warning <b>THIS #define HAS BEEN DEPRECATED AND SHOULD NOT BE USED.</b>
- *       It will be removed in a future release.
- *       See @ref ixNpeDlNpeInitAndStart for more information.
- */
-#define ixNpeDlAvailableVersionsListGet(x,y) ixNpeDlAvailableImagesListGet(x,y)
-
- /**
- * @def ixNpeDlLoadedVersionGet
- *
- * @brief  Map old terminology that uses term "version" to new term
- *        "image"
- *
- * @warning <b>THIS #define HAS BEEN DEPRECATED AND SHOULD NOT BE USED.</b>
- *       It will be removed in a future release.
- *       See @ref ixNpeDlNpeInitAndStart for more information.
- */
-#define ixNpeDlLoadedVersionGet(x,y) ixNpeDlLoadedImageGet(x,y)
-
- /**
- * @def clientImage
- *
- * @brief  Map old terminology that uses term "image" to new term
- *        "image library"
- *
- * @warning <b>THIS #define HAS BEEN DEPRECATED AND SHOULD NOT BE USED.</b>
- *       It will be removed in a future release.
- *       See @ref ixNpeDlNpeInitAndStart for more information.
- */
-#define clientImage clientImageLibrary
-
- /**
- * @def versionIdPtr
- *
- * @brief  Map old terminology that uses term "version" to new term
- *        "image"
- *
- * @warning <b>THIS #define HAS BEEN DEPRECATED AND SHOULD NOT BE USED.</b>
- *       It will be removed in a future release.
- *       See @ref ixNpeDlNpeInitAndStart for more information.
- */
-#define versionIdPtr imageIdPtr
-
- /**
- * @def numVersionsPtr
- *
- * @brief  Map old terminology that uses term "version" to new term
- *        "image"
- *
- * @warning <b>THIS #define HAS BEEN DEPRECATED AND SHOULD NOT BE USED.</b>
- *       It will be removed in a future release.
- *       See @ref ixNpeDlNpeInitAndStart for more information.
- */
-#define numVersionsPtr numImagesPtr
-
-/**
- * @def versionIdListPtr
- *
- * @brief  Map old terminology that uses term "version" to new term
- *        "image"
- *
- * @warning <b>THIS #define HAS BEEN DEPRECATED AND SHOULD NOT BE USED.</b>
- *       It will be removed in a future release.
- *       See @ref ixNpeDlNpeInitAndStart for more information.
- */
-#define versionIdListPtr imageIdListPtr
-
-/**
- * @def IxNpeDlBuildId
- *
- * @brief  Map old terminology that uses term "buildId" to new term
- *        "functionalityId"
- *
- * @warning <b>THIS #define HAS BEEN DEPRECATED AND SHOULD NOT BE USED.</b>
- *       It will be removed in a future release.
- *       See @ref ixNpeDlNpeInitAndStart for more information.
- */
-#define IxNpeDlBuildId IxNpeDlFunctionalityId
-
-/**
- * @def buildId
- *
- * @brief  Map old terminology that uses term "buildId" to new term
- *        "functionalityId"
- *
- * @warning <b>THIS #define HAS BEEN DEPRECATED AND SHOULD NOT BE USED.</b>
- *       It will be removed in a future release.
- *       See @ref ixNpeDlNpeInitAndStart for more information.
- */
-#define buildId functionalityId
-
-/**
- * @def IX_NPEDL_MicrocodeImage
- *
- * @brief  Map old terminology that uses term "image" to new term
- *        "image library"
- *
- * @warning <b>THIS #define HAS BEEN DEPRECATED AND SHOULD NOT BE USED.</b>
- *       It will be removed in a future release.
- *       See @ref ixNpeDlNpeInitAndStart for more information.
- */
-#define IX_NPEDL_MicrocodeImage IX_NPEDL_MicrocodeImageLibrary
-
-/*
- * Typedefs
- */
-
-/**
- * @typedef IxNpeDlFunctionalityId
- * @brief Used to make up Functionality ID field of Image Id
- *
- * @warning <b>THIS typedef HAS BEEN DEPRECATED AND SHOULD NOT BE USED.</b>
- *       It will be removed in a future release.
- *       See @ref ixNpeDlNpeInitAndStart for more information.
- */
-typedef UINT8 IxNpeDlFunctionalityId;
-
-/**
- * @typedef IxNpeDlMajor
- * @brief Used to make up Major Release field of Image Id
- *
- * @warning <b>THIS typedef HAS BEEN DEPRECATED AND SHOULD NOT BE USED.</b>
- *       It will be removed in a future release.
- *       See @ref ixNpeDlNpeInitAndStart for more information.
- */
-typedef UINT8 IxNpeDlMajor;
-
-/**
- * @typedef IxNpeDlMinor
- * @brief Used to make up Minor Revision field of Image Id
- *
- * @warning <b>THIS typedef HAS BEEN DEPRECATED AND SHOULD NOT BE USED.</b>
- *       It will be removed in a future release.
- *       See @ref ixNpeDlNpeInitAndStart for more information.
- */
-typedef UINT8 IxNpeDlMinor;
-
-/*
- * Enums
- */
-
-/**
- * @brief NpeId numbers to identify NPE A, B or C
- * @note In this context, for IXP425 Silicon (B0):<br>
- *      - NPE-A has HDLC, HSS, AAL and UTOPIA Coprocessors.<br>
- *      - NPE-B has Ethernet Coprocessor.<br>
- *      - NPE-C has Ethernet, AES, DES and HASH Coprocessors.<br>
- *      - IXP400 Product Line have different combinations of coprocessors.
- */
-typedef enum
-{
-  IX_NPEDL_NPEID_NPEA = 0,    /**< Identifies NPE A */
-  IX_NPEDL_NPEID_NPEB,        /**< Identifies NPE B */
-  IX_NPEDL_NPEID_NPEC,        /**< Identifies NPE C */
-  IX_NPEDL_NPEID_MAX          /**< Total Number of NPEs */
-} IxNpeDlNpeId;
-
-/*
- * Structs
- */
-
-/**
- * @brief Image Id to identify each image contained in an image library
- *
- * @warning <b>THIS struct HAS BEEN DEPRECATED AND SHOULD NOT BE USED.</b>
- *       It will be removed in a future release.
- *       See @ref ixNpeDlNpeInitAndStart for more information.
- */
-typedef struct
-{
-    IxNpeDlNpeId   npeId;   /**< NPE ID */
-    IxNpeDlFunctionalityId functionalityId; /**< Build ID indicates functionality of image */
-    IxNpeDlMajor   major;   /**< Major Release Number */
-    IxNpeDlMinor   minor;   /**< Minor Revision Number */
-} IxNpeDlImageId;
-
-/*
- * Prototypes for interface functions
- */
-
-/**
- * @ingroup IxNpeDl
- *
- * @fn PUBLIC IX_STATUS ixNpeDlNpeInitAndStart (UINT32 imageId)
- *
- * @brief Stop, reset, download microcode (firmware) and finally start NPE.
- *
- * @param imageId UINT32 [in] - Id of the microcode image to download.
- *
- * This function locates the image specified by the <i>imageId</i> parameter
- * from the default microcode image library which is included internally by
- * this component.
- * It then stops and resets the NPE, loads the firmware image onto the NPE,
- * and then restarts the NPE.
- *
- * @note A list of valid image IDs is included in this header file.
- *       See #defines with prefix IX_NPEDL_NPEIMAGE_...
- *
- * @note This function, along with @ref ixNpeDlCustomImageNpeInitAndStart
- *       and @ref ixNpeDlLoadedImageFunctionalityGet, supercedes the following
- *       functions which are deprecated and will be removed completely in a
- *       future release:
- *       - @ref ixNpeDlImageDownload
- *       - @ref ixNpeDlAvailableImagesCountGet
- *       - @ref ixNpeDlAvailableImagesListGet
- *       - @ref ixNpeDlLatestImageGet
- *       - @ref ixNpeDlLoadedImageGet
- *       - @ref ixNpeDlMicrocodeImageLibraryOverride
- *       - @ref ixNpeDlNpeExecutionStop
- *       - @ref ixNpeDlNpeStopAndReset
- *       - @ref ixNpeDlNpeExecutionStart
- *
- * @pre
- *         - The Client is responsible for ensuring mutual access to the NPE.
- * @post
- *         - The NPE Instruction Pipeline will be cleared if State Information
- *           has been downloaded.
- *         - If the download fails with a critical error, the NPE may
- *           be left in an ususable state.
- * @return
- *         - IX_SUCCESS if the download was successful;
- *         - IX_NPEDL_PARAM_ERR if a parameter error occured
- *         - IX_NPEDL_CRITICAL_NPE_ERR if a critical NPE error occured during
- *           download
- *         - IX_NPEDL_CRITICAL_MICROCODE_ERR if a critical microcode error
- *           occured during download
- *         - IX_NPEDL_DEVICE_ERR if the image being loaded is not meant for 
- *           the device currently running.
- *         - IX_FAIL if NPE is not available or image is failed to be located.
- *           A warning is issued if the NPE is not present.
- */
-PUBLIC IX_STATUS
-ixNpeDlNpeInitAndStart (UINT32 npeImageId);
-
-/**
- * @ingroup IxNpeDl
- *
- * @fn PUBLIC IX_STATUS ixNpeDlCustomImageNpeInitAndStart (UINT32 *imageLibrary,
-                                                           UINT32 imageId)
- *
- * @brief Stop, reset, download microcode (firmware) and finally start NPE
- *
- * @param imageId UINT32 [in] - Id of the microcode image to download.
- *
- * This function locates the image specified by the <i>imageId</i> parameter
- * from the specified microcode image library which is pointed to by the
- * <i>imageLibrary</i> parameter.
- * It then stops and resets the NPE, loads the firmware image onto the NPE,
- * and then restarts the NPE.
- *
- * This is a facility for users who wish to use an image from an external
- * library of NPE firmware images.  To use a standard image from the
- * built-in library, see @ref ixNpeDlNpeInitAndStart instead.
- *
- * @note A list of valid image IDs is included in this header file.
- *       See #defines with prefix IX_NPEDL_NPEIMAGE_...
- *
- * @note This function, along with @ref ixNpeDlNpeInitAndStart
- *       and @ref ixNpeDlLoadedImageFunctionalityGet, supercedes the following
- *       functions which are deprecated and will be removed completely in a
- *       future release:
- *       - @ref ixNpeDlImageDownload
- *       - @ref ixNpeDlAvailableImagesCountGet
- *       - @ref ixNpeDlAvailableImagesListGet
- *       - @ref ixNpeDlLatestImageGet
- *       - @ref ixNpeDlLoadedImageGet
- *       - @ref ixNpeDlMicrocodeImageLibraryOverride
- *       - @ref ixNpeDlNpeExecutionStop
- *       - @ref ixNpeDlNpeStopAndReset
- *       - @ref ixNpeDlNpeExecutionStart
- *
- * @pre
- *         - The Client is responsible for ensuring mutual access to the NPE.
- *         - The image library supplied must be in the correct format for use
- *           by the NPE Downloader (IxNpeDl) component.  Details of the library
- *           format are contained in the Functional Specification document for
- *           IxNpeDl.
- * @post
- *         - The NPE Instruction Pipeline will be cleared if State Information
- *           has been downloaded.
- *         - If the download fails with a critical error, the NPE may
- *           be left in an ususable state.
- * @return
- *         - IX_SUCCESS if the download was successful;
- *         - IX_NPEDL_PARAM_ERR if a parameter error occured
- *         - IX_NPEDL_CRITICAL_NPE_ERR if a critical NPE error occured during
- *           download
- *         - IX_NPEDL_CRITICAL_MICROCODE_ERR if a critical microcode error
- *           occured during download
- *         - IX_NPEDL_DEVICE_ERR if the image being loaded is not meant for 
- *           the device currently running.
- *         - IX_FAIL if NPE is not available or image is failed to be located.
- *           A warning is issued if the NPE is not present.
- */
-PUBLIC IX_STATUS
-ixNpeDlCustomImageNpeInitAndStart (UINT32 *imageLibrary,
-                    UINT32 npeImageId);
-
-
-/**
- * @ingroup IxNpeDl
- *
- * @fn PUBLIC IX_STATUS ixNpeDlLoadedImageFunctionalityGet (IxNpeDlNpeId npeId,
-                                                        UINT8 *functionalityId)
- *
- * @brief Gets the functionality of the image last loaded on a particular NPE
- *
- * @param npeId  @ref IxNpeDlNpeId [in]      - Id of the target NPE.
- * @param functionalityId UINT8* [out] - the functionality ID of the image
- *                                       last loaded on the NPE.
- *
- * This function retrieves the functionality ID of the image most recently
- * downloaded successfully to the specified NPE.  If the NPE does not contain
- * a valid image, this function returns a FAIL status.
- *
- * @warning This function is not intended for general use, as a knowledge of
- * how to interpret the functionality ID is required.  As such, this function
- * should only be used by other Access Layer components of the IXP400 Software
- * Release.
- *
- * @pre
- *
- * @post
- *
- * @return
- *     -  IX_SUCCESS if the operation was successful
- *     -  IX_NPEDL_PARAM_ERR if a parameter error occured
- *     -  IX_FAIL if the NPE does not have a valid image loaded
- */
-PUBLIC IX_STATUS
-ixNpeDlLoadedImageFunctionalityGet (IxNpeDlNpeId npeId,
-                                    UINT8 *functionalityId);
-
-
-/**
- * @ingroup IxNpeDl
- *
- * @fn IX_STATUS ixNpeDlMicrocodeImageLibraryOverride (UINT32 *clientImageLibrary)
- *
- * @brief This instructs NPE Downloader to use client-supplied microcode image library.
- *
- * @param clientImageLibrary UINT32* [in]  - Pointer to the client-supplied
- *                                   NPE microcode image library
- *
- * This function sets NPE Downloader to use a client-supplied microcode image library
- * instead of the standard image library which is included by the NPE Downloader.
- * <b>This function is provided mainly for increased testability and should not
- * be used in normal circumstances.</b> When not used, NPE Downloader will use
- * a "built-in" image library, local to this component, which should always contain the
- * latest microcode for the NPEs.
- *
- * @warning <b>THIS FUNCTION HAS BEEN DEPRECATED AND SHOULD NOT BE USED.</b>
- *       It will be removed in a future release.
- *       See @ref ixNpeDlCustomImageNpeInitAndStart.
- *
- * @pre
- *      - <i>clientImageLibrary</i> should point to a microcode image library valid for use
- *        by the NPE Downloader component.
- *
- * @post
- *      - the client-supplied image library will be used for all subsequent operations
- *        performed by the NPE Downloader
- *
- * @return
- *      - IX_SUCCESS if the operation was successful
- *      - IX_NPEDL_PARAM_ERR if a parameter error occured
- *      - IX_FAIL if the client-supplied image library did not contain a valid signature
- */
-PUBLIC IX_STATUS
-ixNpeDlMicrocodeImageLibraryOverride (UINT32 *clientImageLibrary);
-
-/**
- * @ingroup IxNpeDl
- *
- * @fn PUBLIC IX_STATUS ixNpeDlImageDownload (IxNpeDlImageId *imageIdPtr,
-                                                BOOL verify)
- *
- * @brief Stop, reset, download microcode and finally start NPE.
- *
- * @param imageIdPtr @ref IxNpeDlImageId* [in] - Pointer to Id of the microcode
- *                                              image to download.
- * @param verify BOOL [in]     - ON/OFF option to verify the download. If ON
- *                               (verify == TRUE), the Downloader will read back
- *                               each word written to the NPE registers to
- *                               ensure the download operation was successful.
- *
- * Using the <i>imageIdPtr</i>, this function locates a particular image of
- * microcode in the microcode image library in memory, and downloads the microcode
- * to a particular NPE.
- *
- * @warning <b>THIS FUNCTION HAS BEEN DEPRECATED AND SHOULD NOT BE USED.</b>
- *       It will be removed in a future release.
- *       See @ref ixNpeDlNpeInitAndStart and @ref ixNpeDlCustomImageNpeInitAndStart.
- *
- * @pre
- *         - The Client is responsible for ensuring mutual access to the NPE.
- *       - The Client should use ixNpeDlLatestImageGet() to obtain the latest
- *         version of the image before attempting download.
- * @post
- *         - The NPE Instruction Pipeline will be cleared if State Information
- *           has been downloaded.
- *         - If the download fails with a critical error, the NPE may
- *           be left in an ususable state.
- * @return
- *         - IX_SUCCESS if the download was successful;
- *         - IX_NPEDL_PARAM_ERR if a parameter error occured
- *         - IX_NPEDL_CRITICAL_NPE_ERR if a critical NPE error occured during
- *           download
- *         - IX_PARAM_CRITICAL_MICROCODE_ERR if a critical microcode error
- *           occured during download
- *         - IX_FAIL if NPE is not available or image is failed to be located.
- *           A warning is issued if the NPE is not present.
- */
-PUBLIC IX_STATUS
-ixNpeDlImageDownload (IxNpeDlImageId *imageIdPtr,
-            BOOL verify);
-
-/**
- * @ingroup IxNpeDl
- *
- * @fn PUBLIC IX_STATUS ixNpeDlAvailableImagesCountGet (UINT32 *numImagesPtr)
- *
- * @brief Get the number of Images available in a microcode image library
- *
- * @param numImagesPtr UINT32* [out] - A pointer to the number of images in
- *                                       the image library.
- *
- * Gets the number of images available in the microcode image library.
- * Then returns this in a variable pointed to by <i>numImagesPtr</i>.
- *
- * @warning <b>THIS FUNCTION HAS BEEN DEPRECATED AND SHOULD NOT BE USED.</b>
- *       It will be removed in a future release.
- *       See @ref ixNpeDlNpeInitAndStart and @ref ixNpeDlCustomImageNpeInitAndStart.
- *
- * @pre
- *     - The Client should declare the variable to which numImagesPtr points
- *
- * @post
- *
- * @return
- *     - IX_SUCCESS if the operation was successful
- *     - IX_NPEDL_PARAM_ERR if a parameter error occured
- *     - IX_FAIL otherwise
- */
-PUBLIC IX_STATUS
-ixNpeDlAvailableImagesCountGet (UINT32 *numImagesPtr);
-
-/**
- * @ingroup IxNpeDl
- *
- * @fn PUBLIC IX_STATUS ixNpeDlAvailableImagesListGet (IxNpeDlImageId *imageIdListPtr,
-                                                         UINT32 *listSizePtr)
- *
- * @brief Get a list of the images available in a microcode image library
- *
- * @param imageIdListPtr @ref IxNpeDlImageId* [out] - Array to contain list of
- *                                                   image Ids (memory
- *                                                   allocated by Client).
- * @param listSizePtr UINT32* [inout]  - As an input, this param should point
- *                                       to the max number of Ids the
- *                                       <i>imageIdListPtr</i> array can
- *                                       hold. NpeDl will replace the input
- *                                       value of this parameter with the
- *                                       number of image Ids actually filled
- *                                       into the array before returning.
- *
- * Finds list of images available in the microcode image library.
- * Fills these into the array pointed to by <i>imageIdListPtr</i>
- *
- * @warning <b>THIS FUNCTION HAS BEEN DEPRECATED AND SHOULD NOT BE USED.</b>
- *       It will be removed in a future release.
- *       See @ref ixNpeDlNpeInitAndStart and @ref ixNpeDlCustomImageNpeInitAndStart.
- *
- * @pre
- *     - The Client should declare the variable to which numImagesPtr points
- *     - The Client should create an array (<i>imageIdListPtr</i>) large
- *       enough to contain all the image Ids in the image library
- *
- * @post
- *
- * @return
- *     - IX_SUCCESS if the operation was successful
- *     - IX_NPEDL_PARAM_ERR if a parameter error occured
- *     - IX_FAIL otherwise
- */
-PUBLIC IX_STATUS
-ixNpeDlAvailableImagesListGet (IxNpeDlImageId *imageIdListPtr,
-                 UINT32 *listSizePtr);
-
-/**
- * @ingroup IxNpeDl
- *
- * @fn PUBLIC IX_STATUS ixNpeDlLoadedImageGet (IxNpeDlNpeId npeId,
-                                                IxNpeDlImageId *imageIdPtr)
- *
- * @brief Gets the Id of the image currently loaded on a particular NPE
- *
- * @param npeId @ref IxNpeDlNpeId [in]              - Id of the target NPE.
- * @param imageIdPtr @ref IxNpeDlImageId* [out]     - Pointer to the where the
- *                                               image id should be stored.
- *
- * If an image of microcode was previously downloaded successfully to the NPE
- * by NPE Downloader, this function returns in <i>imageIdPtr</i> the image
- * Id of that image loaded on the NPE.
- *
- * @pre
- *     - The Client has allocated memory to the <i>imageIdPtr</i> pointer.
- *
- * @post
- *
- * @return
- *     -  IX_SUCCESS if the operation was successful
- *     -  IX_NPEDL_PARAM_ERR if a parameter error occured
- *     -  IX_FAIL if the NPE doesn't currently have a image loaded
- */
-PUBLIC IX_STATUS
-ixNpeDlLoadedImageGet (IxNpeDlNpeId npeId,
-             IxNpeDlImageId *imageIdPtr);
-
-/**
- * @fn PUBLIC IX_STATUS ixNpeDlLatestImageGet (IxNpeDlNpeId npeId, IxNpeDlFunctionalityId
-                                        functionalityId, IxNpeDlImageId *imageIdPtr)
- *
- * @brief This instructs NPE Downloader to get Id of the latest version for an
- * image that is specified by the client.
- *
- * @param npeId @ref IxNpeDlNpeId [in]                    - Id of the target NPE.
- * @param functionalityId @ref IxNpeDlFunctionalityId [in]    - functionality of the image
- * @param imageIdPtr @ref IxNpeDlImageId* [out]               - Pointer to the where the
- *                                                         image id should be stored.
- *
- * This function sets NPE Downloader to return the id of the latest version for
- * image.  The user will select the image by providing a particular NPE
- * (specifying <i>npeId</i>) with particular functionality (specifying
- * <i>FunctionalityId</i>). The most recent version available as determined by the
- * highest Major and Minor revision numbers is returned in <i>imageIdPtr</i>.
- *
- * @warning <b>THIS FUNCTION HAS BEEN DEPRECATED AND SHOULD NOT BE USED.</b>
- *       It will be removed in a future release.
- *       See @ref ixNpeDlNpeInitAndStart and @ref ixNpeDlCustomImageNpeInitAndStart.
- *
- * @return
- *      - IX_SUCCESS if the operation was successful
- *      - IX_NPEDL_PARAM_ERR if a parameter error occured
- *      - IX_FAIL otherwise
- */
-PUBLIC IX_STATUS
-ixNpeDlLatestImageGet (IxNpeDlNpeId npeId,
-             IxNpeDlFunctionalityId functionalityId,
-                    IxNpeDlImageId *imageIdPtr);
-
-/**
- * @ingroup IxNpeDl
- *
- * @fn PUBLIC IX_STATUS ixNpeDlNpeStopAndReset (IxNpeDlNpeId npeId)
- *
- * @brief Stops and Resets an NPE
- *
- * @param npeId @ref IxNpeDlNpeId [in] - Id of the target NPE.
- *
- * This function performs a soft NPE reset by writing reset values to
- * particular NPE registers. Note that this does not reset NPE co-processors.
- * This implicitly stops NPE code execution before resetting the NPE.
- *
- * @note It is no longer necessary to call this function before downloading
- * a new image to the NPE.  It is left on the API only to allow greater control
- * of NPE execution if required.  Where appropriate, use @ref ixNpeDlNpeInitAndStart
- * or @ref ixNpeDlCustomImageNpeInitAndStart instead.
- *
- * @warning <b>THIS FUNCTION HAS BEEN DEPRECATED AND SHOULD NOT BE USED.</b>
- *       It will be removed in a future release.
- *       See @ref ixNpeDlNpeInitAndStart and @ref ixNpeDlCustomImageNpeInitAndStart.
- *
- * @pre
- *     - The Client is responsible for ensuring mutual access to the NPE.
- *
- * @post
- *
- * @return
- *      - IX_SUCCESS if the operation was successful
- *      - IX_NPEDL_PARAM_ERR if a parameter error occured
- *      - IX_FAIL otherwise
- *      - IX_NPEDL_CRITICAL_NPE_ERR failed to reset NPE due to timeout error. 
- *        Timeout error could happen if NPE hang
- */
-PUBLIC IX_STATUS
-ixNpeDlNpeStopAndReset (IxNpeDlNpeId npeId);
-
-/**
- * @ingroup IxNpeDl
- *
- * @fn PUBLIC IX_STATUS ixNpeDlNpeExecutionStart (IxNpeDlNpeId npeId)
- *
- * @brief Starts code execution on a NPE
- *
- * @param npeId @ref IxNpeDlNpeId [in] - Id of the target NPE
- *
- * Starts execution of code on a particular NPE.  A client would typically use
- * this after a download to NPE is performed, to start/restart code execution
- * on the NPE.
- *
- * @note It is no longer necessary to call this function after downloading
- * a new image to the NPE.  It is left on the API only to allow greater control
- * of NPE execution if required.  Where appropriate, use @ref ixNpeDlNpeInitAndStart
- * or @ref ixNpeDlCustomImageNpeInitAndStart instead.
- *
- * @warning <b>THIS FUNCTION HAS BEEN DEPRECATED AND SHOULD NOT BE USED.</b>
- *       It will be removed in a future release.
- *       See @ref ixNpeDlNpeInitAndStart and @ref ixNpeDlCustomImageNpeInitAndStart.
- *
- * @pre
- *     - The Client is responsible for ensuring mutual access to the NPE.
- *     - Note that this function does not set the NPE Next Program Counter
- *       (NextPC), so it should be set beforehand if required by downloading
- *       appropriate State Information (using ixNpeDlVersionDownload()).
- *
- * @post
- *
- * @return
- *      - IX_SUCCESS if the operation was successful
- *      - IX_NPEDL_PARAM_ERR if a parameter error occured
- *      - IX_FAIL otherwise
- */
-PUBLIC IX_STATUS
-ixNpeDlNpeExecutionStart (IxNpeDlNpeId npeId);
-
-/**
- * @ingroup IxNpeDl
- *
- * @fn PUBLIC IX_STATUS ixNpeDlNpeExecutionStop (IxNpeDlNpeId npeId)
- *
- * @brief Stops code execution on a NPE
- *
- * @param npeId @ref IxNpeDlNpeId [in] - Id of the target NPE
- *
- * Stops execution of code on a particular NPE.  This would typically be used
- * by a client before a download to NPE is performed, to stop code execution on
- * an NPE, unless ixNpeDlNpeStopAndReset() is used instead.  Unlike
- * ixNpeDlNpeStopAndReset(), this function only halts the NPE and leaves
- * all registers and settings intact. This is useful, for example, between
- * stages of a multi-stage download, to stop the NPE prior to downloading the
- * next image while leaving the current state of the NPE intact..
- *
- * @warning <b>THIS FUNCTION HAS BEEN DEPRECATED AND SHOULD NOT BE USED.</b>
- *       It will be removed in a future release.
- *       See @ref ixNpeDlNpeInitAndStart and @ref ixNpeDlCustomImageNpeInitAndStart.
- *
- * @pre
- *     - The Client is responsible for ensuring mutual access to the NPE.
- *
- * @post
- *
- * @return
- *      - IX_SUCCESS if the operation was successful
- *      - IX_NPEDL_PARAM_ERR if a parameter error occured
- *      - IX_FAIL otherwise
- */
-PUBLIC IX_STATUS
-ixNpeDlNpeExecutionStop (IxNpeDlNpeId npeId);
-
-/**
- * @ingroup IxNpeDl
- *
- * @fn PUBLIC IX_STATUS ixNpeDlUnload (void)
- *
- * @brief This function will uninitialise the IxNpeDl component.
- *
- * This function will uninitialise the IxNpeDl component.  It should only be
- * called once, and only if the IxNpeDl component has already been initialised by
- * calling any of the following functions:
- * - @ref ixNpeDlNpeInitAndStart
- * - @ref ixNpeDlCustomImageNpeInitAndStart
- * - @ref ixNpeDlImageDownload     (deprecated)
- * - @ref ixNpeDlNpeStopAndReset   (deprecated)
- * - @ref ixNpeDlNpeExecutionStop  (deprecated)
- * - @ref ixNpeDlNpeExecutionStart (deprecated)
- *
- * If possible, this function should be called before a soft reboot or unloading
- * a kernel module to perform any clean up operations required for IxNpeDl.
- *
- * The following actions will be performed by this function:
- * - Unmapping of any kernel memory mapped by IxNpeDl
- *
- * @return
- *      - IX_SUCCESS if the operation was successful
- *      - IX_FAIL otherwise
- */
-
-PUBLIC IX_STATUS 
-ixNpeDlUnload (void);
-
-/**
- * @ingroup IxNpeDl
- *
- * @fn PUBLIC void ixNpeDlStatsShow (void)
- *
- * @brief This function will display run-time statistics from the IxNpeDl
- *        component
- *
- * @return none
- */
-PUBLIC void
-ixNpeDlStatsShow (void);
-
-/**
- * @ingroup IxNpeDl
- *
- * @fn PUBLIC void ixNpeDlStatsReset (void)
- *
- * @brief This function will reset the statistics of the IxNpeDl component
- *
- * @return none
- */
-PUBLIC void
-ixNpeDlStatsReset (void);
-
-#endif /* IXNPEDL_H */
-
-/**
- * @} defgroup IxNpeDl
- */
-
-
diff --git a/arch/arm/cpu/ixp/npe/include/IxNpeDlImageMgr_p.h b/arch/arm/cpu/ixp/npe/include/IxNpeDlImageMgr_p.h
deleted file mode 100644
index 622f879..0000000
--- a/arch/arm/cpu/ixp/npe/include/IxNpeDlImageMgr_p.h
+++ /dev/null
@@ -1,363 +0,0 @@
-/**
- * @file IxNpeDlImageMgr_p.h
- *
- * @author Intel Corporation
- * @date 14 December 2001
-
- * @brief This file contains the private API for the ImageMgr module
- *
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- * 
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- * 
- * @par
- * -- End of Copyright Notice --
-*/
-
-/**
- * @defgroup IxNpeDlImageMgr_p IxNpeDlImageMgr_p
- *
- * @brief The private API for the IxNpeDl ImageMgr module
- * 
- * @{
- */
-
-#ifndef IXNPEDLIMAGEMGR_P_H
-#define IXNPEDLIMAGEMGR_P_H
-
-
-/*
- * Put the user defined include files required.
- */
-#include "IxNpeDl.h"
-#include "IxOsalTypes.h"
-
-
-/*
- * #defines and macros
- */
-
-/**
- * @def IX_NPEDL_IMAGEMGR_SIGNATURE
- *
- * @brief Signature found as 1st word in a microcode image library
- */
-#define IX_NPEDL_IMAGEMGR_SIGNATURE      0xDEADBEEF
-
-/**
- * @def IX_NPEDL_IMAGEMGR_END_OF_HEADER
- *
- * @brief Marks end of header in a microcode image library
- */
-#define IX_NPEDL_IMAGEMGR_END_OF_HEADER  0xFFFFFFFF
-
-/**
- * @def IX_NPEDL_IMAGEID_NPEID_OFFSET
- *
- * @brief Offset from LSB of NPE ID field in Image ID
- */
-#define IX_NPEDL_IMAGEID_NPEID_OFFSET      24
-
-/**
- * @def IX_NPEDL_IMAGEID_DEVICEID_OFFSET
- *
- * @brief Offset from LSB of Device ID field in Image ID
- */
-#define IX_NPEDL_IMAGEID_DEVICEID_OFFSET   28
-
-/**
- * @def IX_NPEDL_IMAGEID_FUNCTIONID_OFFSET
- *
- * @brief Offset from LSB of Functionality ID field in Image ID
- */
-#define IX_NPEDL_IMAGEID_FUNCTIONID_OFFSET 16
-
-/**
- * @def IX_NPEDL_IMAGEID_MAJOR_OFFSET
- *
- * @brief Offset from LSB of Major revision field in Image ID
- */
-#define IX_NPEDL_IMAGEID_MAJOR_OFFSET      8
-
-/**
- * @def IX_NPEDL_IMAGEID_MINOR_OFFSET
- *
- * @brief Offset from LSB of Minor revision field in Image ID
- */
-#define IX_NPEDL_IMAGEID_MINOR_OFFSET      0
-
-
-/**
- * @def IX_NPEDL_NPEID_FROM_IMAGEID_GET
- *
- * @brief Macro to extract NPE ID field from Image ID
- */
-#define IX_NPEDL_NPEID_FROM_IMAGEID_GET(imageId) \
-    (((imageId) >> IX_NPEDL_IMAGEID_NPEID_OFFSET) & \
-     IX_NPEDL_NPEIMAGE_NPEID_MASK)
-
-/**
- * @def IX_NPEDL_DEVICEID_FROM_IMAGEID_GET
- *
- * @brief Macro to extract NPE ID field from Image ID
- */
-#define IX_NPEDL_DEVICEID_FROM_IMAGEID_GET(imageId) \
-    (((imageId) >> IX_NPEDL_IMAGEID_DEVICEID_OFFSET) & \
-     IX_NPEDL_NPEIMAGE_DEVICEID_MASK)
-
-/**
- * @def IX_NPEDL_FUNCTIONID_FROM_IMAGEID_GET
- *
- * @brief Macro to extract Functionality ID field from Image ID
- */
-#define IX_NPEDL_FUNCTIONID_FROM_IMAGEID_GET(imageId) \
-    (((imageId) >> IX_NPEDL_IMAGEID_FUNCTIONID_OFFSET) & \
-     IX_NPEDL_NPEIMAGE_FIELD_MASK)
-
-/**
- * @def IX_NPEDL_MAJOR_FROM_IMAGEID_GET
- *
- * @brief Macro to extract Major revision field from Image ID
- */
-#define IX_NPEDL_MAJOR_FROM_IMAGEID_GET(imageId) \
-    (((imageId) >> IX_NPEDL_IMAGEID_MAJOR_OFFSET) & \
-     IX_NPEDL_NPEIMAGE_FIELD_MASK)
-
-/**
- * @def IX_NPEDL_MINOR_FROM_IMAGEID_GET
- *
- * @brief Macro to extract Minor revision field from Image ID
- */
-#define IX_NPEDL_MINOR_FROM_IMAGEID_GET(imageId) \
-    (((imageId) >> IX_NPEDL_IMAGEID_MINOR_OFFSET) & \
-     IX_NPEDL_NPEIMAGE_FIELD_MASK)
-
-
-/*
- * Prototypes for interface functions
- */
-
-/**
- * @fn IX_STATUS ixNpeDlImageMgrMicrocodeImageLibraryOverride (UINT32 *clientImageLibrary)
- * 
- * @brief This instructs NPE Downloader to use client-supplied microcode image library.
- *
- * This function sets NPE Downloader to use a client-supplied microcode image library
- * instead of the standard image library which is included by the NPE Downloader.
- * 
- * @note THIS FUNCTION HAS BEEN DEPRECATED AND SHOULD NOT BE USED.
- *       It will be removed in a future release.
- *       See API header file IxNpeDl.h for more information.             
- *
- * @pre
- *    - <i>clientImageLibrary</i> should point to a microcode image library valid for use
- *      by the NPE Downloader component.
- *
- * @post
- *    - the client-supplied image uibrary will be used for all subsequent operations
- *      performed by the NPE Downloader
- *
- * @return
- *      - IX_SUCCESS if the operation was successful
- *      - IX_FAIL if the client-supplied image library did not contain a valid signature
- */ 
-IX_STATUS
-ixNpeDlImageMgrMicrocodeImageLibraryOverride (UINT32 *clientImageLibrary);
-
-
-/**
- * @fn IX_STATUS ixNpeDlImageMgrImageListExtract (IxNpeDlImageId *imageListPtr,
-                                                    UINT32 *numImages)
- * 
- * @brief Extracts a list of images available in the NPE microcode image library.
- *
- * @param IxNpeDlImageId* [out] imageListPtr - pointer to array to contain
- *                                                 a list of images. If NULL,
- *                                                 only the number of images 
- *                                                 is returned (in
- *                                                 <i>numImages</i>)
- * @param UINT32* [inout] numImages - As input, it points to a variable
- *                                      containing the number of images which
- *                                      can be stored in the
- *                                      <i>imageListPtr</i> array. Its value
- *                                      is ignored as input if
- *                                      <i>imageListPtr</i> is NULL. As an
- *                                      output, it will contain number of
- *                                      images in the image library.
- * 
- * This function reads the header of the microcode image library and extracts a list of the
- * images available in the image library.  It can also be used to find the number of
- * images in the image library.
- * 
- * @note THIS FUNCTION HAS BEEN DEPRECATED AND SHOULD NOT BE USED.
- *       It will be removed in a future release.
- *       See API header file IxNpeDl.h for more information.             
- *
- * @pre
- *    - if <i>imageListPtr</i> != NULL, <i>numImages</i> should reflect the
- *      number of image Id elements the <i>imageListPtr</i> can contain.
- *
- * @post
- *    - <i>numImages</i> will reflect the number of image Id's found in the
- *      microcode image library.
- *
- * @return
- *      - IX_SUCCESS if the operation was successful
- *      - IX_FAIL otherwise
- */ 
-IX_STATUS
-ixNpeDlImageMgrImageListExtract (IxNpeDlImageId *imageListPtr,
-				   UINT32 *numImages);
-
-
-/**
- * @fn IX_STATUS ixNpeDlImageMgrImageLocate (IxNpeDlImageId *imageId,
-                                               UINT32 **imagePtr,
-                                               UINT32 *imageSize)
- * 
- * @brief Finds a image block in the NPE microcode image library. 
- *
- * @param IxNpeDlImageId* [in] imageId - the id of the image to locate
- * @param UINT32** [out] imagePtr        - pointer to the image in memory
- * @param UINT32* [out] imageSize        - size (in 32-bit words) of image
- * 
- * This function examines the header of the microcode image library for the location
- * and size of the specified image.
- * 
- * @note THIS FUNCTION HAS BEEN DEPRECATED AND SHOULD NOT BE USED.
- *       It will be removed in a future release.
- *       See API header file IxNpeDl.h for more information.             
- *
- * @pre
- *
- * @post
- *
- * @return 
- *      - IX_SUCCESS if the operation was successful
- *      - IX_FAIL otherwise
- */ 
-IX_STATUS
-ixNpeDlImageMgrImageLocate (IxNpeDlImageId *imageId,
-			      UINT32 **imagePtr,
-			      UINT32 *imageSize);
-
-/**
- * @fn IX_STATUS ixNpeDlImageMgrLatestImageExtract (IxNpeDlImageId *imageId)
- * 
- * @brief Finds the most recent version of an image in the NPE image library. 
- *
- * @param IxNpeDlImageId* [inout] imageId - the id of the image 
- * 
- * This function determines the most recent version of a specified image by its 
- * higest major release and minor revision numbers
- * 
- * @note THIS FUNCTION HAS BEEN DEPRECATED AND SHOULD NOT BE USED.
- *       It will be removed in a future release.
- *       See API header file IxNpeDl.h for more information.             
- *
- * @pre
- *
- * @post
- *
- * @return 
- *      - IX_SUCCESS if the operation was successful
- *      - IX_FAIL otherwise
- */ 
-IX_STATUS
-ixNpeDlImageMgrLatestImageExtract (IxNpeDlImageId *imageId);
-
-/**
- * @fn void ixNpeDlImageMgrStatsShow (void)
- *
- * @brief This function will display the statistics of the IxNpeDl ImageMgr
- *        module
- *
- * @return none
- */
-void
-ixNpeDlImageMgrStatsShow (void);
-
-
-/**
- * @fn void ixNpeDlImageMgrStatsReset (void)
- *
- * @brief This function will reset the statistics of the IxNpeDl ImageMgr
- *        module
- *
- * @return none
- */
-void
-ixNpeDlImageMgrStatsReset (void);
-
-
-/**
- * @fn IX_STATUS ixNpeDlImageMgrImageGet (UINT32 *imageLibrary,
-                                          UINT32 imageId,
-                                          UINT32 **imagePtr,
-                                          UINT32 *imageSize)
- * 
- * @brief Finds a image block in the NPE microcode image library. 
- *
- * @param UINT32*  [in]  imageLibrary - the image library to use
- * @param UINT32   [in]  imageId      - the id of the image to locate
- * @param UINT32** [out] imagePtr     - pointer to the image in memory
- * @param UINT32*  [out] imageSize    - size (in 32-bit words) of image
- * 
- * This function examines the header of the specified microcode image library
- * for the location and size of the specified image.  It returns a pointer to
- * the image in the <i>imagePtr</i> parameter.
- * If no image library is specified (imageLibrary == NULL), then the default
- * built-in image library will be used.
- * 
- * @pre
- *
- * @post
- *
- * @return 
- *      - IX_SUCCESS if the operation was successful
- *      - IX_FAIL otherwise
- */ 
-IX_STATUS
-ixNpeDlImageMgrImageFind (UINT32 *imageLibrary,
-                          UINT32 imageId,
-			  UINT32 **imagePtr,
-			  UINT32 *imageSize);
-
-
-#endif /* IXNPEDLIMAGEMGR_P_H */
-
-/**
- * @} defgroup IxNpeDlImageMgr_p
- */
diff --git a/arch/arm/cpu/ixp/npe/include/IxNpeDlMacros_p.h b/arch/arm/cpu/ixp/npe/include/IxNpeDlMacros_p.h
deleted file mode 100644
index e32906a..0000000
--- a/arch/arm/cpu/ixp/npe/include/IxNpeDlMacros_p.h
+++ /dev/null
@@ -1,414 +0,0 @@
-/**
- * @file IxNpeDlMacros_p.h
- *
- * @author Intel Corporation
- * @date 21 January 2002
- *
- * @brief This file contains the macros for the IxNpeDl component.
- *
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- * 
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- * 
- * @par
- * -- End of Copyright Notice --
-*/
-
-/**
- * @defgroup IxNpeDlMacros_p IxNpeDlMacros_p
- *
- * @brief Macros for the IxNpeDl component.
- * 
- * @{
- */
-
-#ifndef IXNPEDLMACROS_P_H
-#define IXNPEDLMACROS_P_H
-
-
-/*
- * Put the user defined include files required.
- */
-#if (CPU != XSCALE)
-/* To support IxNpeDl unit tests... */
-#include <stdio.h>
-#include "test/IxNpeDlTestReg.h"
-
-#else   
-#include "IxOsal.h"
-
-#endif
-
-
-/*
- * Typedefs
- */
-
-/**
- * @typedef IxNpeDlTraceTypes
- * @brief Enumeration defining IxNpeDl trace levels
- */
-typedef enum
-{
-    IX_NPEDL_TRACE_OFF,     /**< no trace */
-    IX_NPEDL_DEBUG,         /**< debug */
-    IX_NPEDL_FN_ENTRY_EXIT  /**< function entry/exit */
-} IxNpeDlTraceTypes;
-
-
-/*
- * #defines and macros.
- */
-
-/* Implementation of the following macros for use with IxNpeDl unit test code */
-#if (CPU != XSCALE)
-
-
-/**
- * @def IX_NPEDL_TRACE_LEVEL
- *
- * @brief IxNpeDl debug trace level
- */
-#define IX_NPEDL_TRACE_LEVEL IX_NPEDL_FN_ENTRY_EXIT
-
-/**
- * @def IX_NPEDL_ERROR_REPORT
- *
- * @brief Mechanism for reporting IxNpeDl software errors
- *
- * @param char* [in] STR - Error string to report
- *
- * This macro simply prints the error string passed.
- * Intended for use with IxNpeDl unit test code.
- *
- * @return none
- */
-#define IX_NPEDL_ERROR_REPORT(STR) printf ("IxNpeDl ERROR: %s\n", (STR));
-
-/**
- * @def IX_NPEDL_WARNING_REPORT
- *
- * @brief Mechanism for reporting IxNpeDl software errors
- *
- * @param char* [in] STR - Error string to report
- *
- * This macro simply prints the error string passed.
- * Intended for use with IxNpeDl unit test code.
- *
- * @return none
- */
-#define IX_NPEDL_WARNING_REPORT(STR) printf ("IxNpeDl WARNING: %s\n", (STR));
-
-/**
- * @def IX_NPEDL_TRACE0
- *
- * @brief Mechanism for tracing debug for the IxNpeDl component, for no arguments
- *
- * @param unsigned [in] LEVEL - one of IxNpeDlTraceTypes enumerated values
- * @param char* [in] STR - Trace string
- *
- * This macro simply prints the trace string passed, if the level is supported. 
- * Intended for use with IxNpeDl unit test code.
- *
- * @return none
- */
-#define IX_NPEDL_TRACE0(LEVEL, STR) \
-{ \
-    if (LEVEL <= IX_NPEDL_TRACE_LEVEL) \
-    { \
-        printf ("IxNpeDl TRACE: "); \
-        printf ((STR)); \
-        printf ("\n"); \
-    } \
-}
-
- /**
- * @def IX_NPEDL_TRACE1
- *
- * @brief Mechanism for tracing debug for the IxNpeDl component, with 1 argument
- *
- * @param unsigned [in] LEVEL - one of IxNpeDlTraceTypes enumerated values
- * @param char* [in] STR - Trace string
- * @param argType [in] ARG1 - Argument to trace
- *
- * This macro simply prints the trace string passed, if the level is supported.
- * Intended for use with IxNpeDl unit test code.
- *
- * @return none
- */
-#define IX_NPEDL_TRACE1(LEVEL, STR, ARG1) \
-{ \
-    if (LEVEL <= IX_NPEDL_TRACE_LEVEL) \
-    { \
-        printf ("IxNpeDl TRACE: "); \
-        printf (STR, ARG1); \
-        printf ("\n"); \
-    } \
-}
-
-/**
- * @def IX_NPEDL_TRACE2
- *
- * @brief Mechanism for tracing debug for the IxNpeDl component, with 2 arguments
- *
- * @param unsigned [in] LEVEL - one of IxNpeDlTraceTypes enumerated values
- * @param char* [in] STR - Trace string
- * @param argType [in] ARG1 - Argument to trace
- * @param argType [in] ARG2 - Argument to trace
- *
- * This macro simply prints the trace string passed, if the level is supported. 
- * Intended for use with IxNpeDl unit test code.
- *
- * @return none
- */
-#define IX_NPEDL_TRACE2(LEVEL, STR, ARG1, ARG2) \
-{ \
-    if (LEVEL <= IX_NPEDL_TRACE_LEVEL) \
-    { \
-        printf ("IxNpeDl TRACE: "); \
-        printf (STR, ARG1, ARG2); \
-        printf ("\n"); \
-    } \
-}
-
-
-/**
- * @def IX_NPEDL_REG_WRITE
- *
- * @brief Mechanism for writing to a memory-mapped register
- *
- * @param UINT32 [in] base   - Base memory address for this NPE's registers
- * @param UINT32 [in] offset - Offset from base memory address
- * @param UINT32 [in] value  - Value to write to register
- *
- * This macro calls a function from Unit Test code to write a register.  This
- * allows extra flexibility for unit testing of the IxNpeDl component.
- *
- * @return none
- */
-#define IX_NPEDL_REG_WRITE(base, offset, value) \
-{ \
-    ixNpeDlTestRegWrite (base, offset, value); \
-}
-
-
-/**
- * @def IX_NPEDL_REG_READ
- *
- * @brief Mechanism for reading from a memory-mapped register
- *
- * @param UINT32 [in] base     - Base memory address for this NPE's registers
- * @param UINT32 [in] offset   - Offset from base memory address
- * @param UINT32 *[out] value  - Value read from register
- *
- * This macro calls a function from Unit Test code to read a register.  This
- * allows extra flexibility for unit testing of the IxNpeDl component.
- *
- * @return none
- */
-#define IX_NPEDL_REG_READ(base, offset, value) \
-{ \
-    ixNpeDlTestRegRead (base, offset, value); \
-}
-
-
-/* Implementation of the following macros when integrated with IxOsal */
-#else  /* #if (CPU != XSCALE) */
-
-
-/**
- * @def IX_NPEDL_TRACE_LEVEL
- *
- * @brief IxNpeDl debug trace level
- */
-#define IX_NPEDL_TRACE_LEVEL IX_NPEDL_DEBUG
-
-
-/**
- * @def IX_NPEDL_ERROR_REPORT
- *
- * @brief Mechanism for reporting IxNpeDl software errors
- *
- * @param char* [in] STR - Error string to report
- *
- * This macro is used to report IxNpeDl software errors.
- *
- * @return none
- */
-#define IX_NPEDL_ERROR_REPORT(STR) \
-    ixOsalLog (IX_OSAL_LOG_LVL_ERROR, IX_OSAL_LOG_DEV_STDERR, STR, 0, 0, 0, 0, 0, 0);
-
-/**
- * @def IX_NPEDL_WARNING_REPORT
- *
- * @brief Mechanism for reporting IxNpeDl software warnings
- *
- * @param char* [in] STR - Warning string to report
- *
- * This macro is used to report IxNpeDl software warnings.
- *
- * @return none
- */
-#define IX_NPEDL_WARNING_REPORT(STR) \
-    ixOsalLog (IX_OSAL_LOG_LVL_WARNING, IX_OSAL_LOG_DEV_STDOUT, STR, 0, 0, 0, 0, 0, 0);
-
-
-/**
- * @def IX_NPEDL_TRACE0
- *
- * @brief Mechanism for tracing debug for the IxNpeDl component, for no arguments
- *
- * @param unsigned [in] LEVEL - one of IxNpeDlTraceTypes enumerated values
- * @param char* [in] STR - Trace string
- *
- * This macro simply prints the trace string passed, if the level is supported.
- *
- * @return none
- */
-#define IX_NPEDL_TRACE0(LEVEL, STR) \
-{ \
-    if (LEVEL <= IX_NPEDL_TRACE_LEVEL) \
-    { \
-        if (LEVEL == IX_NPEDL_FN_ENTRY_EXIT) \
-        { \
-            ixOsalLog (IX_OSAL_LOG_LVL_DEBUG3, IX_OSAL_LOG_DEV_STDOUT, STR, 0, 0, 0, 0, 0, 0); \
-        } \
-        else if (LEVEL == IX_NPEDL_DEBUG) \
-        { \
-            ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, STR, 0, 0, 0, 0, 0, 0); \
-        } \
-    } \
-}
-
-/**
- * @def IX_NPEDL_TRACE1
- *
- * @brief Mechanism for tracing debug for the IxNpeDl component, with 1 argument
- *
- * @param unsigned [in] LEVEL - one of IxNpeDlTraceTypes enumerated values
- * @param char* [in] STR - Trace string
- * @param argType [in] ARG1 - Argument to trace
- *
- * This macro simply prints the trace string passed, if the level is supported. 
- *
- * @return none
- */
-#define IX_NPEDL_TRACE1(LEVEL, STR, ARG1) \
-{ \
-    if (LEVEL <= IX_NPEDL_TRACE_LEVEL) \
-    { \
-        if (LEVEL == IX_NPEDL_FN_ENTRY_EXIT) \
-        { \
-            ixOsalLog (IX_OSAL_LOG_LVL_DEBUG3, IX_OSAL_LOG_DEV_STDOUT, STR, ARG1, 0, 0, 0, 0, 0); \
-        } \
-        else if (LEVEL == IX_NPEDL_DEBUG) \
-        { \
-            ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, STR, ARG1, 0, 0, 0, 0, 0); \
-        } \
-    } \
-}
-
-/**
- * @def IX_NPEDL_TRACE2
- *
- * @brief Mechanism for tracing debug for the IxNpeDl component, with 2 arguments
- *
- * @param unsigned [in] LEVEL - one of IxNpeDlTraceTypes enumerated values
- * @param char* [in] STR - Trace string
- * @param argType [in] ARG1 - Argument to trace
- * @param argType [in] ARG2 - Argument to trace
- *
- * This macro simply prints the trace string passed, if the level is supported. 
- *
- * @return none
- */
-#define IX_NPEDL_TRACE2(LEVEL, STR, ARG1, ARG2) \
-{ \
-    if (LEVEL <= IX_NPEDL_TRACE_LEVEL) \
-    { \
-        if (LEVEL == IX_NPEDL_FN_ENTRY_EXIT) \
-        { \
-            ixOsalLog (IX_OSAL_LOG_LVL_DEBUG3, IX_OSAL_LOG_DEV_STDOUT, STR, ARG1, ARG2, 0, 0, 0, 0); \
-        } \
-        else if (LEVEL == IX_NPEDL_DEBUG) \
-        { \
-            ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, STR, ARG1, ARG2, 0, 0, 0, 0); \
-        } \
-    } \
-}
-
-/**
- * @def IX_NPEDL_REG_WRITE
- *
- * @brief Mechanism for writing to a memory-mapped register
- *
- * @param UINT32 [in] base   - Base memory address for this NPE's registers
- * @param UINT32 [in] offset - Offset from base memory address
- * @param UINT32 [in] value  - Value to write to register
- *
- * This macro forms the address of the register from base address + offset, and 
- * dereferences that address to write the contents of the register.
- *
- * @return none
- */
-#define IX_NPEDL_REG_WRITE(base, offset, value) \
-    IX_OSAL_WRITE_LONG(((base) + (offset)), (value))
-
-
-
-/**
- * @def IX_NPEDL_REG_READ
- *
- * @brief Mechanism for reading from a memory-mapped register
- *
- * @param UINT32 [in] base    - Base memory address for this NPE's registers
- * @param UINT32 [in] offset  - Offset from base memory address
- * @param UINT32 *[out] value  - Value read from register
- *
- * This macro forms the address of the register from base address + offset, and 
- * dereferences that address to read the register contents.
- *
- * @return none
- */
-#define IX_NPEDL_REG_READ(base, offset, value) \
-    *(value) = IX_OSAL_READ_LONG(((base) + (offset)))
-
-#endif  /* #if (CPU != XSCALE) */
-
-#endif /* IXNPEDLMACROS_P_H */
-
-/**
- * @} defgroup IxNpeDlMacros_p
- */
diff --git a/arch/arm/cpu/ixp/npe/include/IxNpeDlNpeMgrEcRegisters_p.h b/arch/arm/cpu/ixp/npe/include/IxNpeDlNpeMgrEcRegisters_p.h
deleted file mode 100644
index f682126..0000000
--- a/arch/arm/cpu/ixp/npe/include/IxNpeDlNpeMgrEcRegisters_p.h
+++ /dev/null
@@ -1,893 +0,0 @@
-/**
- * @file IxNpeDlNpeMgrEcRegisters_p.h
- *
- * @author Intel Corporation
- * @date 14 December 2001
-
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- * 
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- * 
- * @par
- * -- End of Copyright Notice --
-*/
-
-
-#ifndef IXNPEDLNPEMGRECREGISTERS_P_H
-#define IXNPEDLNPEMGRECREGISTERS_P_H
-
-#include "IxOsal.h"
-
-/*
- * Base Memory Addresses for accessing NPE registers
- */
-
-#define IX_NPEDL_NPE_BASE (IX_OSAL_IXP400_PERIPHERAL_PHYS_BASE)
-
-#define IX_NPEDL_NPEA_OFFSET (0x6000) /**< NPE-A register base offset */
-#define IX_NPEDL_NPEB_OFFSET (0x7000) /**< NPE-B register base offset */
-#define IX_NPEDL_NPEC_OFFSET (0x8000) /**< NPE-C register base offset */
-
-/**
- * @def IX_NPEDL_NPEBASEADDRESS_NPEA
- * @brief Base Memory Address of NPE-A Configuration Bus registers
- */
-#define IX_NPEDL_NPEBASEADDRESS_NPEA (IX_NPEDL_NPE_BASE + IX_NPEDL_NPEA_OFFSET)
-
-/**
- * @def IX_NPEDL_NPEBASEADDRESS_NPEB
- * @brief Base Memory Address of NPE-B Configuration Bus registers
- */
-#define IX_NPEDL_NPEBASEADDRESS_NPEB (IX_NPEDL_NPE_BASE + IX_NPEDL_NPEB_OFFSET)
-
-/**
- * @def IX_NPEDL_NPEBASEADDRESS_NPEC
- * @brief Base Memory Address of NPE-C Configuration Bus registers
- */
-#define IX_NPEDL_NPEBASEADDRESS_NPEC (IX_NPEDL_NPE_BASE + IX_NPEDL_NPEC_OFFSET)
-
-
-/*
- * Instruction Memory Size (in words) for each NPE 
- */
-
-/**
- * @def IX_NPEDL_INS_MEMSIZE_WORDS_NPEA
- * @brief Size (in words) of NPE-A Instruction Memory
- */
-#define IX_NPEDL_INS_MEMSIZE_WORDS_NPEA     4096
-
-/**
- * @def IX_NPEDL_INS_MEMSIZE_WORDS_NPEB
- * @brief Size (in words) of NPE-B Instruction Memory
- */
-#define IX_NPEDL_INS_MEMSIZE_WORDS_NPEB     2048
-
-/**
- * @def IX_NPEDL_INS_MEMSIZE_WORDS_NPEC
- * @brief Size (in words) of NPE-B Instruction Memory
- */
-#define IX_NPEDL_INS_MEMSIZE_WORDS_NPEC     2048
-
-
-/*
- * Data Memory Size (in words) for each NPE 
- */
-
-/**
- * @def IX_NPEDL_DATA_MEMSIZE_WORDS_NPEA
- * @brief Size (in words) of NPE-A Data Memory
- */
-#define IX_NPEDL_DATA_MEMSIZE_WORDS_NPEA    2048
-
-/**
- * @def IX_NPEDL_DATA_MEMSIZE_WORDS_NPEB
- * @brief Size (in words) of NPE-B Data Memory
- */
-#define IX_NPEDL_DATA_MEMSIZE_WORDS_NPEB    2048
-
-/**
- * @def IX_NPEDL_DATA_MEMSIZE_WORDS_NPEC
- * @brief Size (in words) of NPE-C Data Memory
- */
-#define IX_NPEDL_DATA_MEMSIZE_WORDS_NPEC    2048
-
-
-/*
- * Configuration Bus Register offsets (in bytes) from NPE Base Address
- */
-
-/**
- * @def IX_NPEDL_REG_OFFSET_EXAD
- * @brief Offset (in bytes) of EXAD (Execution Address) register from NPE Base
- *        Address
- */
-#define IX_NPEDL_REG_OFFSET_EXAD             0x00000000		
-
-/**
- * @def IX_NPEDL_REG_OFFSET_EXDATA
- * @brief Offset (in bytes) of EXDATA (Execution Data) register from NPE Base
- *        Address
- */
-#define IX_NPEDL_REG_OFFSET_EXDATA           0x00000004
-
-/**
- * @def IX_NPEDL_REG_OFFSET_EXCTL
- * @brief Offset (in bytes) of EXCTL (Execution Control) register from NPE Base
- *        Address
- */
-#define IX_NPEDL_REG_OFFSET_EXCTL            0x00000008		
-
-/**
- * @def IX_NPEDL_REG_OFFSET_EXCT
- * @brief Offset (in bytes) of EXCT (Execution Count) register from NPE Base
- *        Address
- */
-#define IX_NPEDL_REG_OFFSET_EXCT 	     0x0000000C		
-
-/**
- * @def IX_NPEDL_REG_OFFSET_AP0
- * @brief Offset (in bytes) of AP0 (Action Point 0) register from NPE Base
- *        Address
- */
-#define IX_NPEDL_REG_OFFSET_AP0	             0x00000010		
-
-/**
- * @def IX_NPEDL_REG_OFFSET_AP1
- * @brief Offset (in bytes) of AP1 (Action Point 1) register from NPE Base
- *        Address
- */
-#define IX_NPEDL_REG_OFFSET_AP1	             0x00000014		
-
-/**
- * @def IX_NPEDL_REG_OFFSET_AP2
- * @brief Offset (in bytes) of AP2 (Action Point 2) register from NPE Base
- *        Address
- */
-#define IX_NPEDL_REG_OFFSET_AP2	             0x00000018		
-
-/**
- * @def IX_NPEDL_REG_OFFSET_AP3
- * @brief Offset (in bytes) of AP3 (Action Point 3) register from NPE Base
- *        Address
- */
-#define IX_NPEDL_REG_OFFSET_AP3	             0x0000001C		
-
-/**
- * @def IX_NPEDL_REG_OFFSET_WFIFO
- * @brief Offset (in bytes) of WFIFO (Watchpoint FIFO) register from NPE Base
- *        Address
- */
-#define IX_NPEDL_REG_OFFSET_WFIFO            0x00000020
-
-/**
- * @def IX_NPEDL_REG_OFFSET_WC
- * @brief Offset (in bytes) of WC (Watch Count) register from NPE Base
- *        Address
- */
-#define IX_NPEDL_REG_OFFSET_WC	             0x00000024 		
-
-/**
- * @def IX_NPEDL_REG_OFFSET_PROFCT
- * @brief Offset (in bytes) of PROFCT (Profile Count) register from NPE Base
- *        Address
- */
-#define IX_NPEDL_REG_OFFSET_PROFCT           0x00000028		
-
-/**
- * @def IX_NPEDL_REG_OFFSET_STAT
- * @brief Offset (in bytes) of STAT (Messaging Status) register from NPE Base
- *        Address
- */
-#define IX_NPEDL_REG_OFFSET_STAT	     0x0000002C		
-
-/**
- * @def IX_NPEDL_REG_OFFSET_CTL
- * @brief Offset (in bytes) of CTL (Messaging Control) register from NPE Base
- *        Address
- */
-#define IX_NPEDL_REG_OFFSET_CTL	             0x00000030		
-
-/**
- * @def IX_NPEDL_REG_OFFSET_MBST
- * @brief Offset (in bytes) of MBST (Mailbox Status) register from NPE Base
- *        Address
- */
-#define IX_NPEDL_REG_OFFSET_MBST	     0x00000034		
-
-/**
- * @def IX_NPEDL_REG_OFFSET_FIFO
- * @brief Offset (in bytes) of FIFO (messaging in/out FIFO) register from NPE
- *        Base Address
- */
-#define IX_NPEDL_REG_OFFSET_FIFO	     0x00000038		
-
-
-/*
- * Non-zero reset values for the Configuration Bus registers
- */
-
-/**
- * @def IX_NPEDL_REG_RESET_FIFO
- * @brief Reset value for Mailbox (MBST) register
- *        NOTE that if used, it should be complemented with an NPE intruction
- *        to clear the Mailbox at the NPE side as well
- */
-#define IX_NPEDL_REG_RESET_MBST              0x0000F0F0
-
-
-/*
- * Bit-masks used to read/write particular bits in Configuration Bus registers
- */
-
-/**
- * @def IX_NPEDL_MASK_WFIFO_VALID
- * @brief Masks the VALID bit in the WFIFO register
- */
-#define IX_NPEDL_MASK_WFIFO_VALID            0x80000000
-
-/**
- * @def IX_NPEDL_MASK_STAT_OFNE
- * @brief Masks the OFNE bit in the STAT register
- */
-#define IX_NPEDL_MASK_STAT_OFNE              0x00010000
-
-/**
- * @def IX_NPEDL_MASK_STAT_IFNE
- * @brief Masks the IFNE bit in the STAT register
- */
-#define IX_NPEDL_MASK_STAT_IFNE              0x00080000
-
-
-/*
- * EXCTL (Execution Control) Register commands 
-*/
-
-/**
- * @def IX_NPEDL_EXCTL_CMD_NPE_STEP
- * @brief EXCTL Command to Step execution of an NPE Instruction
- */
-
-#define IX_NPEDL_EXCTL_CMD_NPE_STEP          0x01
-
-/**
- * @def IX_NPEDL_EXCTL_CMD_NPE_START
- * @brief EXCTL Command to Start NPE execution
- */
-#define IX_NPEDL_EXCTL_CMD_NPE_START         0x02
-
-/**
- * @def IX_NPEDL_EXCTL_CMD_NPE_STOP
- * @brief EXCTL Command to Stop NPE execution
- */
-#define IX_NPEDL_EXCTL_CMD_NPE_STOP          0x03
-
-/**
- * @def IX_NPEDL_EXCTL_CMD_NPE_CLR_PIPE
- * @brief EXCTL Command to Clear NPE instruction pipeline
- */
-#define IX_NPEDL_EXCTL_CMD_NPE_CLR_PIPE      0x04
-
-/**
- * @def IX_NPEDL_EXCTL_CMD_RD_INS_MEM
- * @brief EXCTL Command to read NPE instruction memory at address in EXAD
- *        register and return value in EXDATA register
- */
-#define IX_NPEDL_EXCTL_CMD_RD_INS_MEM        0x10
-
-/**
- * @def IX_NPEDL_EXCTL_CMD_WR_INS_MEM
- * @brief EXCTL Command to write NPE instruction memory at address in EXAD
- *        register with data in EXDATA register
- */
-#define IX_NPEDL_EXCTL_CMD_WR_INS_MEM        0x11
-
-/**
- * @def IX_NPEDL_EXCTL_CMD_RD_DATA_MEM
- * @brief EXCTL Command to read NPE data memory at address in EXAD
- *        register and return value in EXDATA register
- */
-#define IX_NPEDL_EXCTL_CMD_RD_DATA_MEM       0x12
-
-/**
- * @def IX_NPEDL_EXCTL_CMD_WR_DATA_MEM
- * @brief EXCTL Command to write NPE data memory at address in EXAD
- *        register with data in EXDATA register
- */
-#define IX_NPEDL_EXCTL_CMD_WR_DATA_MEM       0x13
-
-/**
- * @def IX_NPEDL_EXCTL_CMD_RD_ECS_REG
- * @brief EXCTL Command to read Execution Access register at address in EXAD
- *        register and return value in EXDATA register
- */
-#define IX_NPEDL_EXCTL_CMD_RD_ECS_REG        0x14
-
-/**
- * @def IX_NPEDL_EXCTL_CMD_WR_ECS_REG
- * @brief EXCTL Command to write Execution Access register at address in EXAD
- *        register with data in EXDATA register
- */
-#define IX_NPEDL_EXCTL_CMD_WR_ECS_REG        0x15
-
-/**
- * @def IX_NPEDL_EXCTL_CMD_CLR_PROFILE_CNT
- * @brief EXCTL Command to clear Profile Count register
- */
-#define IX_NPEDL_EXCTL_CMD_CLR_PROFILE_CNT   0x0C
-
-
-/*
- * EXCTL (Execution Control) Register status bit masks
- */
-
-/**
- * @def IX_NPEDL_EXCTL_STATUS_RUN
- * @brief Masks the RUN status bit in the EXCTL register
- */
-#define IX_NPEDL_EXCTL_STATUS_RUN            0x80000000
-
-/**
- * @def IX_NPEDL_EXCTL_STATUS_STOP
- * @brief Masks the STOP status bit in the EXCTL register
- */
-#define IX_NPEDL_EXCTL_STATUS_STOP           0x40000000
-
-/**
- * @def IX_NPEDL_EXCTL_STATUS_CLEAR
- * @brief Masks the CLEAR status bit in the EXCTL register
- */
-#define IX_NPEDL_EXCTL_STATUS_CLEAR          0x20000000
-
-/**
- * @def IX_NPEDL_EXCTL_STATUS_ECS_K
- * @brief Masks the K (pipeline Klean) status bit in the EXCTL register
- */
-#define IX_NPEDL_EXCTL_STATUS_ECS_K          0x00800000
-
-
-/*
- * Executing Context Stack (ECS) level registers 
- */
-
-/**
- * @def IX_NPEDL_ECS_BG_CTXT_REG_0
- * @brief Execution Access register address for register 0 at Backgound 
- *        Executing Context Stack level
- */
-#define IX_NPEDL_ECS_BG_CTXT_REG_0           0x00
-
-/**
- * @def IX_NPEDL_ECS_BG_CTXT_REG_1
- * @brief Execution Access register address for register 1 at Backgound 
- *        Executing Context Stack level
- */
-#define IX_NPEDL_ECS_BG_CTXT_REG_1           0x01
-
-/**
- * @def IX_NPEDL_ECS_BG_CTXT_REG_2
- * @brief Execution Access register address for register 2 at Backgound 
- *        Executing Context Stack level
- */
-#define IX_NPEDL_ECS_BG_CTXT_REG_2           0x02
-
-/**
- * @def IX_NPEDL_ECS_PRI_1_CTXT_REG_0
- * @brief Execution Access register address for register 0 at Priority 1
- *        Executing Context Stack level
- */
-#define IX_NPEDL_ECS_PRI_1_CTXT_REG_0        0x04
-
-/**
- * @def IX_NPEDL_ECS_PRI_1_CTXT_REG_1
- * @brief Execution Access register address for register 1 at Priority 1
- *        Executing Context Stack level
- */
-#define IX_NPEDL_ECS_PRI_1_CTXT_REG_1        0x05
-
-/**
- * @def IX_NPEDL_ECS_PRI_1_CTXT_REG_2
- * @brief Execution Access register address for register 2 at Priority 1
- *        Executing Context Stack level
- */
-#define IX_NPEDL_ECS_PRI_1_CTXT_REG_2        0x06
-
-/**
- * @def IX_NPEDL_ECS_PRI_2_CTXT_REG_0
- * @brief Execution Access register address for register 0 at Priority 2
- *        Executing Context Stack level
- */
-#define IX_NPEDL_ECS_PRI_2_CTXT_REG_0        0x08
-
-/**
- * @def IX_NPEDL_ECS_PRI_2_CTXT_REG_1
- * @brief Execution Access register address for register 1 at Priority 2
- *        Executing Context Stack level
- */
-#define IX_NPEDL_ECS_PRI_2_CTXT_REG_1        0x09
-
-/**
- * @def IX_NPEDL_ECS_PRI_2_CTXT_REG_2
- * @brief Execution Access register address for register 2 at Priority 2
- *        Executing Context Stack level
- */
-#define IX_NPEDL_ECS_PRI_2_CTXT_REG_2        0x0A
-
-/**
- * @def IX_NPEDL_ECS_DBG_CTXT_REG_0
- * @brief Execution Access register address for register 0 at Debug
- *        Executing Context Stack level
- */
-#define IX_NPEDL_ECS_DBG_CTXT_REG_0          0x0C
-
-/**
- * @def IX_NPEDL_ECS_DBG_CTXT_REG_1
- * @brief Execution Access register address for register 1 at Debug 
- *        Executing Context Stack level
- */
-#define IX_NPEDL_ECS_DBG_CTXT_REG_1          0x0D
-
-/**
- * @def IX_NPEDL_ECS_DBG_CTXT_REG_2
- * @brief Execution Access register address for register 2 at Debug 
- *        Executing Context Stack level
- */
-#define IX_NPEDL_ECS_DBG_CTXT_REG_2          0x0E
-
-/**
- * @def IX_NPEDL_ECS_INSTRUCT_REG
- * @brief Execution Access register address for NPE Instruction Register 
- */
-#define IX_NPEDL_ECS_INSTRUCT_REG            0x11
-
-
-/*
- * Execution Access register reset values
- */
-
-/**
- * @def IX_NPEDL_ECS_BG_CTXT_REG_0_RESET
- * @brief Reset value for Execution Access Background ECS level register 0
- */
-#define IX_NPEDL_ECS_BG_CTXT_REG_0_RESET     0xA0000000
-
-/**
- * @def IX_NPEDL_ECS_BG_CTXT_REG_1_RESET
- * @brief Reset value for Execution Access Background ECS level register 1
- */
-#define IX_NPEDL_ECS_BG_CTXT_REG_1_RESET     0x01000000
-
-/**
- * @def IX_NPEDL_ECS_BG_CTXT_REG_2_RESET
- * @brief Reset value for Execution Access Background ECS level register 2
- */
-#define IX_NPEDL_ECS_BG_CTXT_REG_2_RESET     0x00008000
-
-/**
- * @def IX_NPEDL_ECS_PRI_1_CTXT_REG_0_RESET
- * @brief Reset value for Execution Access Priority 1 ECS level register 0
- */
-#define IX_NPEDL_ECS_PRI_1_CTXT_REG_0_RESET  0x20000080
-
-/**
- * @def IX_NPEDL_ECS_PRI_1_CTXT_REG_1_RESET
- * @brief Reset value for Execution Access Priority 1 ECS level register 1
- */
-#define IX_NPEDL_ECS_PRI_1_CTXT_REG_1_RESET  0x01000000
-
-/**
- * @def IX_NPEDL_ECS_PRI_1_CTXT_REG_2_RESET
- * @brief Reset value for Execution Access Priority 1 ECS level register 2
- */
-#define IX_NPEDL_ECS_PRI_1_CTXT_REG_2_RESET  0x00008000
-
-/**
- * @def IX_NPEDL_ECS_PRI_2_CTXT_REG_0_RESET
- * @brief Reset value for Execution Access Priority 2 ECS level register 0
- */
-#define IX_NPEDL_ECS_PRI_2_CTXT_REG_0_RESET  0x20000080
-
-/**
- * @def IX_NPEDL_ECS_PRI_2_CTXT_REG_1_RESET
- * @brief Reset value for Execution Access Priority 2 ECS level register 1
- */
-#define IX_NPEDL_ECS_PRI_2_CTXT_REG_1_RESET  0x01000000
-
-/**
- * @def IX_NPEDL_ECS_PRI_2_CTXT_REG_2_RESET
- * @brief Reset value for Execution Access Priority 2 ECS level register 2
- */
-#define IX_NPEDL_ECS_PRI_2_CTXT_REG_2_RESET  0x00008000
-
-/**
- * @def IX_NPEDL_ECS_DBG_CTXT_REG_0_RESET
- * @brief Reset value for Execution Access Debug ECS level register 0
- */
-#define IX_NPEDL_ECS_DBG_CTXT_REG_0_RESET    0x20000000
-
-/**
- * @def IX_NPEDL_ECS_DBG_CTXT_REG_1_RESET
- * @brief Reset value for Execution Access Debug ECS level register 1
- */
-#define IX_NPEDL_ECS_DBG_CTXT_REG_1_RESET    0x00000000
-
-/**
- * @def IX_NPEDL_ECS_DBG_CTXT_REG_2_RESET
- * @brief Reset value for Execution Access Debug ECS level register 2
- */
-#define IX_NPEDL_ECS_DBG_CTXT_REG_2_RESET    0x001E0000
-
-/**
- * @def IX_NPEDL_ECS_INSTRUCT_REG_RESET
- * @brief Reset value for Execution Access NPE Instruction Register
- */
-#define IX_NPEDL_ECS_INSTRUCT_REG_RESET      0x1003C00F
-
-
-/*
- * masks used to read/write particular bits in Execution Access registers
- */
-
-/**
- * @def IX_NPEDL_MASK_ECS_REG_0_ACTIVE
- * @brief Mask the A (Active) bit in Execution Access Register 0 of all ECS
- *        levels
- */
-#define IX_NPEDL_MASK_ECS_REG_0_ACTIVE       0x80000000
-
-/**
- * @def IX_NPEDL_MASK_ECS_REG_0_NEXTPC
- * @brief Mask the NextPC bits in Execution Access Register 0 of all ECS
- *        levels (except Debug ECS level)
- */
-#define IX_NPEDL_MASK_ECS_REG_0_NEXTPC       0x1FFF0000
-
-/**
- * @def IX_NPEDL_MASK_ECS_REG_0_LDUR
- * @brief Mask the LDUR bits in Execution Access Register 0 of all ECS levels
- */
-#define IX_NPEDL_MASK_ECS_REG_0_LDUR         0x00000700
-
-/**
- * @def IX_NPEDL_MASK_ECS_REG_1_CCTXT
- * @brief Mask the NextPC bits in Execution Access Register 1 of all ECS levels
- */
-#define IX_NPEDL_MASK_ECS_REG_1_CCTXT        0x000F0000
-
-/**
- * @def IX_NPEDL_MASK_ECS_REG_1_SELCTXT
- * @brief Mask the NextPC bits in Execution Access Register 1 of all ECS levels
- */
-#define IX_NPEDL_MASK_ECS_REG_1_SELCTXT      0x0000000F
-
-/**
- * @def IX_NPEDL_MASK_ECS_DBG_REG_2_IF
- * @brief Mask the IF bit in Execution Access Register 2 of Debug ECS level
- */
-#define IX_NPEDL_MASK_ECS_DBG_REG_2_IF       0x00100000
-
-/**
- * @def IX_NPEDL_MASK_ECS_DBG_REG_2_IE
- * @brief Mask the IE bit in Execution Access Register 2 of Debug ECS level
- */
-#define IX_NPEDL_MASK_ECS_DBG_REG_2_IE       0x00080000
-
-
-/*
- * Bit-Offsets from LSB of particular bit-fields in Execution Access registers
- */
-
-/**
- * @def IX_NPEDL_OFFSET_ECS_REG_0_NEXTPC
- * @brief LSB-offset of NextPC field in Execution Access Register 0 of all ECS
- *        levels (except Debug ECS level)
- */
-#define IX_NPEDL_OFFSET_ECS_REG_0_NEXTPC     16 
-
-/**
- * @def IX_NPEDL_OFFSET_ECS_REG_0_LDUR
- * @brief LSB-offset of LDUR field in Execution Access Register 0 of all ECS
- *        levels
- */
-#define IX_NPEDL_OFFSET_ECS_REG_0_LDUR        8
-
-/**
- * @def IX_NPEDL_OFFSET_ECS_REG_1_CCTXT
- * @brief LSB-offset of CCTXT field in Execution Access Register 1 of all ECS
- *        levels
- */
-#define IX_NPEDL_OFFSET_ECS_REG_1_CCTXT      16
-
-/**
- * @def IX_NPEDL_OFFSET_ECS_REG_1_SELCTXT
- * @brief LSB-offset of SELCTXT field in Execution Access Register 1 of all ECS
- *        levels
- */
-#define IX_NPEDL_OFFSET_ECS_REG_1_SELCTXT     0
-
-
-/*
- * NPE core & co-processor instruction templates to load into NPE Instruction 
- * Register, for read/write of NPE register file registers
- */
-
-/**
- * @def IX_NPEDL_INSTR_RD_REG_BYTE
- * @brief NPE Instruction, used to read an 8-bit NPE internal logical register
- *        and return the value in the EXDATA register (aligned to MSB).
- *        NPE Assembler instruction:  "mov8 d0, d0  &&& DBG_WrExec"
- */
-#define IX_NPEDL_INSTR_RD_REG_BYTE    0x0FC00000
-
-/**
- * @def IX_NPEDL_INSTR_RD_REG_SHORT
- * @brief NPE Instruction, used to read a 16-bit NPE internal logical register
- *        and return the value in the EXDATA register (aligned to MSB).
- *        NPE Assembler instruction:  "mov16 d0, d0  &&& DBG_WrExec"
- */
-#define IX_NPEDL_INSTR_RD_REG_SHORT   0x0FC08010
-
-/**
- * @def IX_NPEDL_INSTR_RD_REG_WORD
- * @brief NPE Instruction, used to read a 16-bit NPE internal logical register
- *        and return the value in the EXDATA register.
- *        NPE Assembler instruction:  "mov32 d0, d0  &&& DBG_WrExec"
- */
-#define IX_NPEDL_INSTR_RD_REG_WORD    0x0FC08210
-
-/**
- * @def IX_NPEDL_INSTR_WR_REG_BYTE
- * @brief NPE Immediate-Mode Instruction, used to write an 8-bit NPE internal
- *        logical register.
- *        NPE Assembler instruction:  "mov8 d0, #0"
- */
-#define IX_NPEDL_INSTR_WR_REG_BYTE    0x00004000
-
-/**
- * @def IX_NPEDL_INSTR_WR_REG_SHORT
- * @brief NPE Immediate-Mode Instruction, used to write a 16-bit NPE internal
- *        logical register.
- *        NPE Assembler instruction:  "mov16 d0, #0"
- */
-#define IX_NPEDL_INSTR_WR_REG_SHORT   0x0000C000
-
-/**
- * @def IX_NPEDL_INSTR_RD_FIFO
- * @brief NPE Immediate-Mode Instruction, used to write a 16-bit NPE internal
- *        logical register.
- *        NPE Assembler instruction:  "cprd32 d0    &&& DBG_RdInFIFO"
- */
-#define IX_NPEDL_INSTR_RD_FIFO        0x0F888220    
-
-/**
- * @def IX_NPEDL_INSTR_RESET_MBOX
- * @brief NPE Instruction, used to reset Mailbox (MBST) register
- *        NPE Assembler instruction:  "mov32 d0, d0  &&& DBG_ClearM"
- */
-#define IX_NPEDL_INSTR_RESET_MBOX     0x0FAC8210
-
-
-/*
- * Bit-offsets from LSB, of particular bit-fields in an NPE instruction
- */
-
-/**
- * @def IX_NPEDL_OFFSET_INSTR_SRC
- * @brief LSB-offset to SRC (source operand) field of an NPE Instruction
- */
-#define IX_NPEDL_OFFSET_INSTR_SRC              4
-
-/**
- * @def IX_NPEDL_OFFSET_INSTR_DEST
- * @brief LSB-offset to DEST (destination operand) field of an NPE Instruction
- */
-#define IX_NPEDL_OFFSET_INSTR_DEST             9
-
-/**
- * @def IX_NPEDL_OFFSET_INSTR_COPROC
- * @brief LSB-offset to COPROC (coprocessor instruction) field of an NPE
- *        Instruction
- */
-#define IX_NPEDL_OFFSET_INSTR_COPROC          18
-
-
-/*
- * masks used to read/write particular bits of an NPE Instruction
- */
-
-/**
- * @def IX_NPEDL_MASK_IMMED_INSTR_SRC_DATA
- * @brief Mask the bits of 16-bit data value (least-sig 5 bits) to be used in
- *        SRC field of immediate-mode NPE instruction
- */
-#define IX_NPEDL_MASK_IMMED_INSTR_SRC_DATA         0x1F 
-
-/**
- * @def IX_NPEDL_MASK_IMMED_INSTR_COPROC_DATA
- * @brief Mask the bits of 16-bit data value (most-sig 11 bits) to be used in
- *        COPROC field of immediate-mode NPE instruction
- */
-#define IX_NPEDL_MASK_IMMED_INSTR_COPROC_DATA      0xFFE0
-
-/**
- * @def IX_NPEDL_OFFSET_IMMED_INSTR_COPROC_DATA
- * @brief LSB offset of the bit-field of 16-bit data value (most-sig 11 bits)
- *        to be used in COPROC field of immediate-mode NPE instruction
- */
-#define IX_NPEDL_OFFSET_IMMED_INSTR_COPROC_DATA    5
-
-/**
- * @def IX_NPEDL_DISPLACE_IMMED_INSTR_COPROC_DATA
- * @brief Number of left-shifts required to align most-sig 11 bits of 16-bit
- *        data value into COPROC field of immediate-mode NPE instruction
- */
-#define IX_NPEDL_DISPLACE_IMMED_INSTR_COPROC_DATA \
-     (IX_NPEDL_OFFSET_INSTR_COPROC - IX_NPEDL_OFFSET_IMMED_INSTR_COPROC_DATA)
-
-/**
- * @def IX_NPEDL_WR_INSTR_LDUR
- * @brief LDUR value used with immediate-mode NPE Instructions by the NpeDl
- *        for writing to NPE internal logical registers
- */
-#define IX_NPEDL_WR_INSTR_LDUR                     1
-
-/**
- * @def IX_NPEDL_RD_INSTR_LDUR
- * @brief LDUR value used with NON-immediate-mode NPE Instructions by the NpeDl
- *        for reading from NPE internal logical registers
- */
-#define IX_NPEDL_RD_INSTR_LDUR                     0
-
-
-/**
- * @enum IxNpeDlCtxtRegNum
- * @brief Numeric values to identify the NPE internal Context Store registers
- */
-typedef enum
-{
-    IX_NPEDL_CTXT_REG_STEVT = 0,  /**< identifies STEVT   */
-    IX_NPEDL_CTXT_REG_STARTPC,    /**< identifies STARTPC */
-    IX_NPEDL_CTXT_REG_REGMAP,     /**< identifies REGMAP  */
-    IX_NPEDL_CTXT_REG_CINDEX,     /**< identifies CINDEX  */
-    IX_NPEDL_CTXT_REG_MAX         /**< Total number of Context Store registers */
-} IxNpeDlCtxtRegNum;
-
-
-/*
- * NPE Context Store register logical addresses
- */
-
-/**
- * @def IX_NPEDL_CTXT_REG_ADDR_STEVT
- * @brief Logical address of STEVT NPE internal Context Store register
- */
-#define IX_NPEDL_CTXT_REG_ADDR_STEVT      0x0000001B
-
-/**
- * @def IX_NPEDL_CTXT_REG_ADDR_STARTPC
- * @brief Logical address of STARTPC NPE internal Context Store register
- */
-#define IX_NPEDL_CTXT_REG_ADDR_STARTPC    0x0000001C
-
-/**
- * @def IX_NPEDL_CTXT_REG_ADDR_REGMAP
- * @brief Logical address of REGMAP NPE internal Context Store register
- */
-#define IX_NPEDL_CTXT_REG_ADDR_REGMAP     0x0000001E
-
-/**
- * @def IX_NPEDL_CTXT_REG_ADDR_CINDEX
- * @brief Logical address of CINDEX NPE internal Context Store register
- */
-#define IX_NPEDL_CTXT_REG_ADDR_CINDEX     0x0000001F
-
-
-/*
- * NPE Context Store register reset values
- */
-
-/**
- * @def IX_NPEDL_CTXT_REG_RESET_STEVT
- * @brief Reset value of STEVT NPE internal Context Store register
- *        (STEVT = off, 0x80)
- */
-#define IX_NPEDL_CTXT_REG_RESET_STEVT     0x80
-
-/**
- * @def IX_NPEDL_CTXT_REG_RESET_STARTPC
- * @brief Reset value of STARTPC NPE internal Context Store register
- *        (STARTPC = 0x0000)
- */
-#define IX_NPEDL_CTXT_REG_RESET_STARTPC   0x0000
-
-/**
- * @def IX_NPEDL_CTXT_REG_RESET_REGMAP
- * @brief Reset value of REGMAP NPE internal Context Store register
- *        (REGMAP = d0->p0, d8->p2, d16->p4)
- */
-#define IX_NPEDL_CTXT_REG_RESET_REGMAP    0x0820
-
-/**
- * @def IX_NPEDL_CTXT_REG_RESET_CINDEX
- * @brief Reset value of CINDEX NPE internal Context Store register
- *        (CINDEX = 0)
- */
-#define IX_NPEDL_CTXT_REG_RESET_CINDEX    0x00
-
-
-/*
- * numeric range of context levels available on an NPE
- */
-
-/**
- * @def IX_NPEDL_CTXT_NUM_MIN
- * @brief Lowest NPE Context number in range
- */
-#define IX_NPEDL_CTXT_NUM_MIN             0
-
-/**
- * @def IX_NPEDL_CTXT_NUM_MAX
- * @brief Highest NPE Context number in range
- */
-#define IX_NPEDL_CTXT_NUM_MAX             15
-
-
-/*
- * Physical NPE internal registers
- */
-
-/**
- * @def IX_NPEDL_TOTAL_NUM_PHYS_REG
- * @brief Number of Physical registers currently supported
- *        Initial NPE implementations will have a 32-word register file.
- *        Later implementations may have a 64-word register file.
- */
-#define IX_NPEDL_TOTAL_NUM_PHYS_REG               32
-
-/**
- * @def IX_NPEDL_OFFSET_PHYS_REG_ADDR_REGMAP
- * @brief LSB-offset of Regmap number in Physical NPE register address, used
- *        for Physical To Logical register address mapping in the NPE
- */
-#define IX_NPEDL_OFFSET_PHYS_REG_ADDR_REGMAP      1
-
-/**
- * @def IX_NPEDL_MASK_PHYS_REG_ADDR_LOGICAL_ADDR
- * @brief Mask to extract a logical NPE register address from a physical
- *        register address, used for Physical To Logical address mapping
- */
-#define IX_NPEDL_MASK_PHYS_REG_ADDR_LOGICAL_ADDR   0x1
-
-#endif /* IXNPEDLNPEMGRECREGISTERS_P_H */
diff --git a/arch/arm/cpu/ixp/npe/include/IxNpeDlNpeMgrUtils_p.h b/arch/arm/cpu/ixp/npe/include/IxNpeDlNpeMgrUtils_p.h
deleted file mode 100644
index a752f26..0000000
--- a/arch/arm/cpu/ixp/npe/include/IxNpeDlNpeMgrUtils_p.h
+++ /dev/null
@@ -1,405 +0,0 @@
-/**
- * @file IxNpeDlNpeMgrUtils_p.h
- *
- * @author Intel Corporation
- * @date 18 February 2002
- * @brief This file contains the private API for the NpeMgr module.
- *
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- * 
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- * 
- * @par
- * -- End of Copyright Notice --
-*/
-
-
-/**
- * @defgroup IxNpeDlNpeMgrUtils_p IxNpeDlNpeMgrUtils_p
- *
- * @brief The private API for the IxNpeDl NpeMgr Utils module
- * 
- * @{
- */
-
-#ifndef IXNPEDLNPEMGRUTILS_P_H
-#define IXNPEDLNPEMGRUTILS_P_H
-
-
-/*
- * Put the user defined include files required.
- */
-#include "IxNpeDl.h"
-#include "IxOsalTypes.h"
-#include "IxNpeDlNpeMgrEcRegisters_p.h"
-
-
-/*
- * Function Prototypes
- */
-
-/**
- * @fn IX_STATUS ixNpeDlNpeMgrInsMemWrite (UINT32 npeBaseAddress,
-                                           UINT32 insMemAddress,
-			                   UINT32 insMemData,
-                                           BOOL verify)
- * 
- * @brief Writes a word to NPE Instruction memory
- *
- * @param UINT32 [in] npeBaseAddress - Base Address of NPE
- * @param UINT32 [in] insMemAddress  - NPE instruction memory address to write
- * @param UINT32 [in] insMemData     - data to write to instruction memory
- * @param BOOL   [in] verify         - if TRUE, verify the memory location is
- *                                     written successfully.
- * 
- * This function is used to write a single word of data to a location in NPE 
- * instruction memory.  If the <i>verify</i> option is ON, NpeDl will read back
- * from the memory location to verify that it was written successfully
- * 
- * @pre
- *
- * @post
- *
- * @return
- *    - IX_FAIL if verify is TRUE and the memory location was not written
- *      successfully
- *    - IX_SUCCESS otherwise
- */ 
-IX_STATUS
-ixNpeDlNpeMgrInsMemWrite (UINT32 npeBaseAddress, UINT32 insMemAddress,
-			  UINT32 insMemData, BOOL verify);
-
-
-/**
- * @fn IX_STATUS ixNpeDlNpeMgrDataMemWrite (UINT32 npeBaseAddress,
-                                            UINT32 dataMemAddress,
-	                                    UINT32 dataMemData,
-                                            BOOL verify)
- * 
- * @brief Writes a word to NPE Data memory
- *
- * @param UINT32 [in] npeBaseAddress - Base Address of NPE
- * @param UINT32 [in] dataMemAddress - NPE data memory address to write
- * @param UINT32 [in] dataMemData    - data to write to NPE data memory
- * @param BOOL   [in] verify         - if TRUE, verify the memory location is
- *                                     written successfully.
- * 
- * This function is used to write a single word of data to a location in NPE 
- * data memory.  If the <i>verify</i> option is ON, NpeDl will read back from
- * the memory location to verify that it was written successfully
- * 
- * @pre
- *
- * @post
- *
- * @return
- *    - IX_FAIL if verify is TRUE and the memory location was not written
- *      successfully
- *    - IX_SUCCESS otherwise
- */ 
-IX_STATUS
-ixNpeDlNpeMgrDataMemWrite (UINT32 npeBaseAddress, UINT32 dataMemAddress,
-			   UINT32 dataMemData, BOOL verify);
-
-
-/**
- * @fn void ixNpeDlNpeMgrExecAccRegWrite (UINT32 npeBaseAddress,
-                                          UINT32 regAddress,
-                                          UINT32 regData)
- * 
- * @brief Writes a word to an NPE Execution Access register
- *
- * @param UINT32 [in] npeBaseAddress - Base Address of NPE
- * @param UINT32 [in] regAddress     - NPE Execution Access register address
- * @param UINT32 [in] regData        - data to write to register
- * 
- * This function is used to write a single word of data to an NPE Execution
- * Access register.
- * 
- * @pre
- *
- * @post
- *
- * @return none
- */ 
-void
-ixNpeDlNpeMgrExecAccRegWrite (UINT32 npeBaseAddress, UINT32 regAddress,
-			      UINT32 regData);
-
-
-/**
- * @fn UINT32 ixNpeDlNpeMgrExecAccRegRead (UINT32 npeBaseAddress,
-                                           UINT32 regAddress)
- * 
- * @brief Reads the contents of an NPE Execution Access register
- *
- * @param UINT32 [in] npeBaseAddress - Base Address of NPE
- * @param UINT32 [in] regAddress     - NPE Execution Access register address
- * 
- * This function is used to read the contents of an NPE Execution
- * Access register.
- * 
- * @pre
- *
- * @post
- *
- * @return The value read from the Execution Access register
- */ 
-UINT32
-ixNpeDlNpeMgrExecAccRegRead (UINT32 npeBaseAddress, UINT32 regAddress);
-
-
-/**
- * @fn void ixNpeDlNpeMgrCommandIssue (UINT32 npeBaseAddress,
-                                       UINT32 command)
- * 
- * @brief Issues an NPE Execution Control command
- *
- * @param UINT32 [in] npeBaseAddress - Base Address of NPE
- * @param UINT32 [in] command        - Command to issue
- * 
- * This function is used to issue a stand-alone NPE Execution Control command
- * (e.g. command to Stop NPE execution)
- * 
- * @pre
- *
- * @post
- *
- * @return none
- */ 
-void
-ixNpeDlNpeMgrCommandIssue (UINT32 npeBaseAddress, UINT32 command);
-
-
-/**
- * @fn void ixNpeDlNpeMgrDebugInstructionPreExec (UINT32 npeBaseAddress)
- * 
- * @brief Prepare to executes one or more NPE instructions in the Debug
- *        Execution Stack level.
- *
- * @param UINT32 [in] npeBaseAddress - Base Address of NPE
- * 
- * This function should be called once before a sequence of calls to 
- * ixNpeDlNpeMgrDebugInstructionExec().
- * 
- * @pre
- *
- * @post
- *     - ixNpeDlNpeMgrDebugInstructionPostExec() should be called to restore
- *       registers values altered by this function
- *
- * @return none
- */ 
-void
-ixNpeDlNpeMgrDebugInstructionPreExec (UINT32 npeBaseAddress);
-
-
-/**
- * @fn IX_STATUS ixNpeDlNpeMgrDebugInstructionExec (UINT32 npeBaseAddress,
-                                               UINT32 npeInstruction,
-                                               UINT32 ctxtNum,
-                                               UINT32 ldur)
- * 
- * @brief Executes a single instruction on the NPE at the Debug Execution Stack
- *        level
- *
- * @param UINT32 [in] npeBaseAddress - Base Address of NPE
- * @param UINT32 [in] npeInstruction - Value to write to INSTR (Instruction)
- *                                     register
- * @param UINT32 [in] ctxtNum        - context the instruction will be executed
- *                                     in and which context store it may access
- * @param UINT32 [in] ldur           - Long Immediate Duration, set to non-zero
- *                                     to use long-immediate mode instruction
- * 
- * This function is used to execute a single instruction in the NPE pipeline at
- * the debug Execution Context Stack level. It won't disturb the state of other
- * executing contexts.  Its useful for performing NPE operations, such as
- * writing to NPE Context Store registers and physical registers, that cannot
- * be carried out directly using the Configuration Bus registers. This function
- * will return TIMEOUT status if NPE not responding due to NPS is hang / halt.
- * 
- * @pre 
- *     - The NPE should be stopped and in a clean state
- *     - ixNpeDlNpeMgrDebugInstructionPreExec() should be called once before
- *       a sequential of 1 or more calls to this function
- *
- * @post
- *     - ixNpeDlNpeMgrDebugInstructionPostExec() should be called after 
- *       a sequence of calls to this function
- *
- * @return 
- *    - IX_NPEDL_CRITICAL_NPE_ERR if execution of instruction failed / timeout
- *    - IX_SUCCESS otherwise 
- */ 
-IX_STATUS
-ixNpeDlNpeMgrDebugInstructionExec (UINT32 npeBaseAddress,
-				   UINT32 npeInstruction,
-				   UINT32 ctxtNum, UINT32 ldur);
-
-
-/**
- * @fn void ixNpeDlNpeMgrDebugInstructionPostExec (UINT32 npeBaseAddress)
- * 
- * @brief Clean up after executing one or more NPE instructions in the
- *        Debug Stack Level
- *
- * @param UINT32 [in] npeBaseAddress - Base Address of NPE
- * 
- * This function should be called once following a sequence of calls to 
- * ixNpeDlNpeMgrDebugInstructionExec().
- *
- * @pre 
- *    -  ixNpeDlNpeMgrDebugInstructionPreExec() was called earlier
- *
- * @post
- *    -  The Instruction Pipeline will cleared
- *
- * @return none
- */ 
-void
-ixNpeDlNpeMgrDebugInstructionPostExec (UINT32 npeBaseAddress);
-
-
-/**
- * @fn IX_STATUS ixNpeDlNpeMgrPhysicalRegWrite (UINT32 npeBaseAddress,
-                                                UINT32 regAddr,
-                                                UINT32 regValue,
-					        BOOL verify)
- * 
- * @brief Write one of the 32* 32-bit physical registers in the NPE data 
- *        register file
- *
- * @param UINT32 [in] npeBaseAddress - Base Address of NPE
- * @param UINT32 [in] regAddr        - number of the physical register (0-31)*
- * @param UINT32 [in] regValue       - value to write to the physical register
- * @param BOOL   [in] verify         - if TRUE, verify the register is written
- *                                     successfully.
- * 
- * This function writes a physical register in the NPE data register file.
- * If the <i>verify</i> option is ON, NpeDl will read back the register to 
- * verify that it was written successfully
- * *Note that release 1.0 of this software supports 32 physical
- * registers, but 64 may be supported in future versions.
- * 
- * @pre
- *    - The NPE should be stopped and in a clean state
- *    - ixNpeDlNpeMgrDebugInstructionPreExec() should be called once before
- *      a sequential of 1 or more calls to this function
- *
- * @post
- *    - Contents of REGMAP Context Store register for Context 0 will be altered
- *    - ixNpeDlNpeMgrDebugInstructionPostExec() should be called after 
- *      a sequence of calls to this function
- *
- * @return
- *    - IX_FAIL if verify is TRUE and the Context Register was not written
- *      successfully
- *    - IX_SUCCESS if Context Register was written successfully
- *    - IX_NPEDL_CRITICAL_NPE_ERR if Context Register was not written 
- *      successfully due to timeout error where NPE is not responding
- */
-IX_STATUS
-ixNpeDlNpeMgrPhysicalRegWrite (UINT32 npeBaseAddress, UINT32 regAddr,
-			       UINT32 regValue, BOOL verify);
-
-
-/**
- * @fn IX_STATUS ixNpeDlNpeMgrCtxtRegWrite (UINT32 npeBaseAddress,
-                                            UINT32 ctxtNum,
-                                            IxNpeDlCtxtRegNum ctxtReg,
-                                            UINT32 ctxtRegVal,
-                                            BOOL verify)
- * 
- * @brief Writes a value to a Context Store register on an NPE
- *
- * @param UINT32 [in] npeBaseAddress     - Base Address of NPE
- * @param UINT32 [in] ctxtNum            - context store to access
- * @param IxNpeDlCtxtRegNum [in] ctxtReg - which Context Store reg to write
- * @param UINT32 [in] ctxtRegVal         - value to write to the Context Store
- *                                         register
- * @param BOOL   [in] verify             - if TRUE, verify the register is
- *                                         written successfully.
- * 
- * This function writes the contents of a Context Store register in the NPE 
- * register file. If the <i>verify</i> option is ON, NpeDl will read back the
- * register to verify that it was written successfully
- * 
- * @pre
- *    - The NPE should be stopped and in a clean state
- *    - ixNpeDlNpeMgrDebugInstructionPreExec() should be called once before
- *      a sequential of 1 or more calls to this function
- *
- * @post
- *    - ixNpeDlNpeMgrDebugInstructionPostExec() should be called after 
- *      a sequence of calls to this function
- *
- * @return
- *    - IX_FAIL if verify is TRUE and the Context Register was not written
- *      successfully
- *    - IX_SUCCESS if Context Register was written successfully
- *    - IX_NPEDL_CRITICAL_NPE_ERR if Context Register was not written 
- *      successfully due to timeout error where NPE is not responding
- */
-IX_STATUS
-ixNpeDlNpeMgrCtxtRegWrite (UINT32 npeBaseAddress, UINT32 ctxtNum,
-			   IxNpeDlCtxtRegNum ctxtReg, UINT32 ctxtRegVal,
-			   BOOL verify);
-
-
-/**
- * @fn void ixNpeDlNpeMgrUtilsStatsShow (void)
- *
- * @brief This function will display the statistics of the IxNpeDl NpeMgrUtils
- *        module
- *
- * @return none
- */
-void
-ixNpeDlNpeMgrUtilsStatsShow (void);
-
-
-/**
- * @fn void ixNpeDlNpeMgrUtilsStatsReset (void)
- *
- * @brief This function will reset the statistics of the IxNpeDl NpeMgrUtils
- *        module
- *
- * @return none
- */
-void
-ixNpeDlNpeMgrUtilsStatsReset (void);
-
-
-#endif  /* IXNPEDLNPEMGRUTILS_P_H */
diff --git a/arch/arm/cpu/ixp/npe/include/IxNpeDlNpeMgr_p.h b/arch/arm/cpu/ixp/npe/include/IxNpeDlNpeMgr_p.h
deleted file mode 100644
index b7fb0f0..0000000
--- a/arch/arm/cpu/ixp/npe/include/IxNpeDlNpeMgr_p.h
+++ /dev/null
@@ -1,260 +0,0 @@
-/**
- * @file IxNpeDlNpeMgr_p.h
- *
- * @author Intel Corporation
- * @date 14 December 2001
- * @brief This file contains the private API for the NpeMgr module.
- *
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- * 
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- * 
- * @par
- * -- End of Copyright Notice --
-*/
-
-
-/**
- * @defgroup IxNpeDlNpeMgr_p IxNpeDlNpeMgr_p
- *
- * @brief The private API for the IxNpeDl NpeMgr module
- * 
- * @{
- */
-
-#ifndef IXNPEDLNPEMGR_P_H
-#define IXNPEDLNPEMGR_P_H
-
-
-/*
- * Put the user defined include files required.
- */
-#include "IxNpeDl.h"
-#include "IxOsalTypes.h"
-
-
-/*
- * Function Prototypes
- */
-
-
-/**
- * @fn void ixNpeDlNpeMgrInit (void)
- * 
- * @brief Initialises the NpeMgr module
- *
- * @param none
- * 
- * This function initialises the NpeMgr module.
- * It should be called before any other function in this module is called.
- * It only needs to be called once, but can be called multiple times safely.
- * The code will ASSERT on failure.
- * 
- * @pre
- *     - It must be called before any other function in this module
- *
- * @post
- *     - NPE Configuration Register memory space will be mapped using
- *       IxOsal. This memory will not be unmapped by this module.
- *
- * @return none
- */ 
-void
-ixNpeDlNpeMgrInit (void);
-
-
-/**
- * @fn IX_STATUS ixNpeMhNpeMgrUninit (void)
- *
- * @brief This function will uninitialise the IxNpeDlNpeMgr sub-component.
- *
- * This function will uninitialise the IxNpeDlNpeMgr sub-component.
- * It should only be called once, and only if the IxNpeDlNpeMgr sub-component
- * has already been initialised by calling @ref ixNpeDlNpeMgrInit().
- * No other IxNpeDlNpeMgr sub-component API functions should be called
- * until @ref ixNpeDlNpeMgrInit() is called again.
- * If possible, this function should be called before a soft reboot or unloading
- * a kernel module to perform any clean up operations required for IxNpeMh.
- *
- * @return
- *      - IX_SUCCESS if the operation was successful
- *      - IX_FAIL otherwise
- */
-
-IX_STATUS ixNpeDlNpeMgrUninit (void);
-
-
-/**
- * @fn IX_STATUS ixNpeDlNpeMgrImageLoad (IxNpeDlNpeId npeId,
-                                           UINT32 *imageCodePtr,
-                                           BOOL verify)
- * 
- * @brief Loads a image of microcode onto an NPE
- *
- * @param IxNpeDlNpeId [in] npeId     - Id of target NPE
- * @param UINT32* [in] imageCodePtr - pointer to image code in image to be
- *                                      downloaded
- * @param BOOL [in] verify            - if TRUE, verify each word written to
- *                                      NPE memory.
- * 
- * This function loads a image containing blocks of microcode onto a
- * particular NPE. If the <i>verify</i> option is ON, NpeDl will read back each
- * word written and verify that it was written successfully
- * 
- * @pre
- *     - The NPE should be stopped beforehand
- *
- * @post
- *     - The NPE Instruction Pipeline may be flushed clean
- *
- * @return
- *     - IX_SUCCESS if the download was successful
- *     - IX_FAIL if the download failed
- *     - IX_NPEDL_CRITICAL_NPE_ERR if the download failed due to timeout error 
- *       where NPE is not responding
- */ 
-IX_STATUS
-ixNpeDlNpeMgrImageLoad (IxNpeDlNpeId npeId, UINT32 *imageCodePtr,
-			  BOOL verify);
-
-
-/**
- * @fn IX_STATUS ixNpeDlNpeMgrNpeReset (IxNpeDlNpeId npeId)
- * 
- * @brief sets a NPE to RESET state
- *
- * @param IxNpeDlNpeId [in] npeId - id of target NPE
- * 
- * This function performs a soft NPE reset by writing reset values to the
- * Configuration Bus Execution Control registers, the Execution Context Stack
- * registers, the Physical Register file, and the Context Store registers for 
- * each context number. It also clears inFIFO, outFIFO and Watchpoint FIFO.
- * It does not reset NPE Co-processors.
- * 
- * @pre
- *     - The NPE should be stopped beforehand
- *
- * @post
- *     - NPE NextProgram Counter (NextPC) will be set to a fixed initial value,
- *       such as 0.  This should be explicitly set by downloading State
- *       Information before starting NPE Execution.
- *     - The NPE Instruction Pipeline will be in a clean state.
- *
- * @return
- *     - IX_SUCCESS if the operation was successful
- *     - IX_FAIL if the operation failed
- *     - IX_NPEDL_CRITICAL_NPE_ERR if the operation failed due to NPE hang
- */ 
-IX_STATUS
-ixNpeDlNpeMgrNpeReset (IxNpeDlNpeId npeId);
-
-
-/**
- * @fn IX_STATUS ixNpeDlNpeMgrNpeStart (IxNpeDlNpeId npeId)
- * 
- * @brief Starts NPE Execution
- *
- * @param IxNpeDlNpeId [in] npeId - Id of target NPE
- * 
- * Ensures only background Execution Stack Level is Active, clears instruction
- * pipeline, and starts Execution on a NPE by sending a Start NPE command to
- * the NPE. Checks the execution status of the NPE to verify that it is
- * running.
- * 
- * @pre
- *     - The NPE should be stopped beforehand.
- *     - Note that this function does not set the NPE Next Program Counter 
- *       (NextPC), so it should be set beforehand if required by downloading 
- *       appropriate State Information.
- *
- * @post
- *
- * @return
- *     - IX_SUCCESS if the operation was successful
- *     - IX_FAIL otherwise
- */ 
-IX_STATUS
-ixNpeDlNpeMgrNpeStart (IxNpeDlNpeId npeId);
-
-
-/**
- * @fn IX_STATUS ixNpeDlNpeMgrNpeStop (IxNpeDlNpeId npeId)
- * 
- * @brief Halts NPE Execution
- *
- * @param IxNpeDlNpeId [in] npeId - id of target NPE
- * 
- * Stops execution on an NPE by sending a Stop NPE command to the NPE.
- * Checks the execution status of the NPE to verify that it has stopped.
- *
- * @pre
- *
- * @post
- *
- * @return 
- *     - IX_SUCCESS if the operation was successful
- *     - IX_FAIL otherwise
- */ 
-IX_STATUS
-ixNpeDlNpeMgrNpeStop (IxNpeDlNpeId npeId);
-
-
-/**
- * @fn void ixNpeDlNpeMgrStatsShow (void)
- *
- * @brief This function will display statistics of the IxNpeDl NpeMgr module
- *
- * @return none
- */
-void
-ixNpeDlNpeMgrStatsShow (void);
-
-
-/**
- * @fn void ixNpeDlNpeMgrStatsReset (void)
- *
- * @brief This function will reset the statistics of the IxNpeDl NpeMgr module
- *
- * @return none
- */
-void
-ixNpeDlNpeMgrStatsReset (void);
-
-
-#endif /* IXNPEDLIMAGEMGR_P_H */
-
-/**
- * @} defgroup IxNpeDlNpeMgr_p
- */
diff --git a/arch/arm/cpu/ixp/npe/include/IxNpeMh.h b/arch/arm/cpu/ixp/npe/include/IxNpeMh.h
deleted file mode 100644
index 20ee38b..0000000
--- a/arch/arm/cpu/ixp/npe/include/IxNpeMh.h
+++ /dev/null
@@ -1,497 +0,0 @@
-/**
- * @file IxNpeMh.h
- *
- * @date 14 Dec 2001
- *
- * @brief This file contains the public API for the IXP400 NPE Message
- * Handler component.
- *
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- * 
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- * 
- * @par
- * -- End of Copyright Notice --
-*/
-
-/**
- * @defgroup IxNpeMh IXP400 NPE Message Handler (IxNpeMh) API
- *
- * @brief The public API for the IXP400 NPE Message Handler component.
- * 
- * @{
- */
-
-#ifndef IXNPEMH_H
-#define IXNPEMH_H
-
-#include "IxOsalTypes.h"
-
-/*
- * #defines for function return types, etc.
- */
-
-#define IX_NPEMH_MIN_MESSAGE_ID (0x00) /**< minimum valid message ID */
-#define IX_NPEMH_MAX_MESSAGE_ID (0xFF) /**< maximum valid message ID */
-
-#define IX_NPEMH_SEND_RETRIES_DEFAULT (3) /**< default msg send retries */
-
-
-/**
- * @def IX_NPEMH_CRITICAL_NPE_ERR
- *
- * @brief NpeMH function return value for a Critical NPE error occuring during
-          sending/receiving message. Assume NPE hang / halt if this value is
-          returned.
- */
-#define IX_NPEMH_CRITICAL_NPE_ERR        2
-
-/**
- * @enum IxNpeMhNpeId
- *
- * @brief The ID of a particular NPE.
- * @note In this context, for IXP425 Silicon (B0):<br> 
- *      - NPE-A has HDLC, HSS, AAL and UTOPIA Coprocessors.<br> 
- *      - NPE-B has Ethernet Coprocessor.<br>
- *      - NPE-C has Ethernet, AES, DES and HASH Coprocessors.<br>
- *      - IXP400 Product Line have different combinations of coprocessors. 
- */
-
-typedef enum
-{
-    IX_NPEMH_NPEID_NPEA = 0, /**< ID for NPE-A */
-    IX_NPEMH_NPEID_NPEB,     /**< ID for NPE-B */
-    IX_NPEMH_NPEID_NPEC,     /**< ID for NPE-C */
-    IX_NPEMH_NUM_NPES        /**< Number of NPEs */
-} IxNpeMhNpeId;
-
-/**
- * @enum IxNpeMhNpeInterrupts
- *
- * @brief Indicator specifying whether or not NPE interrupts should drive
- * receiving of messages from the NPEs.
- */
-
-typedef enum
-{
-    IX_NPEMH_NPEINTERRUPTS_NO = 0, /**< Don't use NPE interrupts */
-    IX_NPEMH_NPEINTERRUPTS_YES     /**< Do use NPE interrupts */
-} IxNpeMhNpeInterrupts;
-
-/**
- * @brief The 2-word message structure to send to and receive from the
- * NPEs.
- */
-
-typedef struct
-{
-    UINT32 data[2]; /**< the actual data of the message */
-} IxNpeMhMessage;
-
-/** message ID */
-typedef UINT32 IxNpeMhMessageId;
-
-/**
- * @typedef IxNpeMhCallback
- *
- * @brief This prototype shows the format of a message callback function.
- *
- * This prototype shows the format of a message callback function.  The
- * message callback will be passed the message to be handled and will also
- * be told from which NPE the message was received.  The message callback
- * will either be registered by ixNpeMhUnsolicitedCallbackRegister() or
- * passed as a parameter to ixNpeMhMessageWithResponseSend().  It will be
- * called from within an ISR triggered by the NPE's "outFIFO not empty"
- * interrupt (see ixNpeMhInitialize()).  The parameters passed are the ID
- * of the NPE that the message was received from, and the message to be
- * handled.<P><B>Re-entrancy:</B> This function is only a prototype, and
- * will be implemented by the client.  It does not need to be re-entrant.
- */
-
-typedef void (*IxNpeMhCallback) (IxNpeMhNpeId, IxNpeMhMessage);
-
-/*
- * Prototypes for interface functions.
- */
-
-/**
- * @ingroup IxNpeMh
- *
- * @fn IX_STATUS ixNpeMhInitialize (
-           IxNpeMhNpeInterrupts npeInterrupts)
- *
- * @brief This function will initialise the IxNpeMh component.
- *
- * @param npeInterrupts @ref IxNpeMhNpeInterrupts [in] - This parameter
- * dictates whether or not the IxNpeMh component will service NPE "outFIFO
- * not empty" interrupts to trigger receiving and processing of messages
- * from the NPEs.  If not then the client must use ixNpeMhMessagesReceive()
- * to control message receiving and processing.
- *
- * This function will initialise the IxNpeMh component.  It should only be
- * called once, prior to using the IxNpeMh component.  The following
- * actions will be performed by this function:<OL><LI>Initialization of
- * internal data structures (e.g. solicited and unsolicited callback
- * tables).</LI><LI>Configuration of the interface with the NPEs (e.g.
- * enabling of NPE "outFIFO not empty" interrupts).</LI><LI>Registration of
- * ISRs that will receive and handle messages when the NPEs' "outFIFO not
- * empty" interrupts fire (if npeInterrupts equals
- * IX_NPEMH_NPEINTERRUPTS_YES).</LI></OL>
- *
- * @return The function returns a status indicating success or failure.
- */
-
-PUBLIC IX_STATUS ixNpeMhInitialize (
-    IxNpeMhNpeInterrupts npeInterrupts);
-
-/**
- * @ingroup IxNpeMh
- *
- * @fn IX_STATUS ixNpeMhUnload (void)
- *
- * @brief This function will uninitialise the IxNpeMh component.
- *
- * This function will uninitialise the IxNpeMh component.  It should only be
- * called once, and only if the IxNpeMh component has already been initialised.
- * No other IxNpeMh API functions should be called until @ref ixNpeMhInitialize
- * is called again.
- * If possible, this function should be called before a soft reboot or unloading
- * a kernel module to perform any clean up operations required for IxNpeMh.
- *
- * The following actions will be performed by this function:
- * <OL><LI>Unmapping of kernel memory mapped by the function
- * @ref ixNpeMhInitialize.</LI></OL>
- *
- * @return The function returns a status indicating success or failure.
- */
-
-PUBLIC IX_STATUS ixNpeMhUnload (void);
-
-/**
- * @ingroup IxNpeMh
- *
- * @fn IX_STATUS ixNpeMhUnsolicitedCallbackRegister (
-           IxNpeMhNpeId npeId,
-           IxNpeMhMessageId messageId,
-           IxNpeMhCallback unsolicitedCallback)
- *
- * @brief This function will register an unsolicited callback for a
- * particular NPE and message ID.
- *
- * @param npeId @ref IxNpeMhNpeId [in] - The ID of the NPE whose messages
- * the unsolicited callback will handle.
- * @param messageId @ref IxNpeMhMessageId [in] - The ID of the messages the
- * unsolicited callback will handle.
- * @param unsolicitedCallback @ref IxNpeMhCallback [in] - The unsolicited
- * callback function.  A value of NULL will deregister any previously
- * registered callback for this NPE and message ID.
- *
- * This function will register an unsolicited message callback for a
- * particular NPE and message ID.<P>If an unsolicited callback is already
- * registered for the specified NPE and message ID then the callback will
- * be overwritten.  Only one client will be responsible for handling a
- * particular message ID associated with a NPE.  Registering a NULL
- * unsolicited callback will deregister any previously registered
- * callback.<P>The callback function will be called from an ISR that will
- * be triggered by the NPE's "outFIFO not empty" interrupt (see
- * ixNpeMhInitialize()) to handle any unsolicited messages of the specific
- * message ID received from the NPE.  Unsolicited messages will be handled
- * in the order they are received.<P>If no unsolicited callback can be
- * found for a received message then it is assumed that the message is
- * solicited.<P>If more than one client may be interested in a particular
- * unsolicited message then the suggested strategy is to register a
- * callback for the message that can itself distribute the message to
- * multiple clients as necessary.<P>See also
- * ixNpeMhUnsolicitedCallbackForRangeRegister().<P><B>Re-entrancy:</B> This
- * function will be callable from any thread at any time.  IxOsal
- * will be used for any necessary resource protection.
- *
- * @return The function returns a status indicating success or failure.
- */
-
-PUBLIC IX_STATUS ixNpeMhUnsolicitedCallbackRegister (
-    IxNpeMhNpeId npeId,
-    IxNpeMhMessageId messageId,
-    IxNpeMhCallback unsolicitedCallback);
-
-/**
- * @ingroup IxNpeMh
- *
- * @fn IX_STATUS ixNpeMhUnsolicitedCallbackForRangeRegister (
-           IxNpeMhNpeId npeId,
-           IxNpeMhMessageId minMessageId,
-           IxNpeMhMessageId maxMessageId,
-           IxNpeMhCallback unsolicitedCallback)
- *
- * @brief This function will register an unsolicited callback for a
- * particular NPE and range of message IDs.
- *
- * @param npeId @ref IxNpeMhNpeId [in] - The ID of the NPE whose messages the
- * unsolicited callback will handle.
- * @param minMessageId @ref IxNpeMhMessageId [in] - The minimum message ID in
- * the range of message IDs the unsolicited callback will handle.
- * @param maxMessageId @ref IxNpeMhMessageId [in] - The maximum message ID in
- * the range of message IDs the unsolicited callback will handle.
- * @param unsolicitedCallback @ref IxNpeMhCallback [in] - The unsolicited
- * callback function.  A value of NULL will deregister any previously
- * registered callback(s) for this NPE and range of message IDs.
- *
- * This function will register an unsolicited callback for a particular NPE
- * and range of message IDs.  It is a convenience function that is
- * effectively the same as calling ixNpeMhUnsolicitedCallbackRegister() for
- * each ID in the specified range.  See
- * ixNpeMhUnsolicitedCallbackRegister() for more
- * information.<P><B>Re-entrancy:</B> This function will be callable from
- * any thread at any time.  IxOsal will be used for any necessary
- * resource protection.
- *
- * @return The function returns a status indicating success or failure.
- */
-
-PUBLIC IX_STATUS ixNpeMhUnsolicitedCallbackForRangeRegister (
-    IxNpeMhNpeId npeId,
-    IxNpeMhMessageId minMessageId,
-    IxNpeMhMessageId maxMessageId,
-    IxNpeMhCallback unsolicitedCallback);
-
-/**
- * @ingroup IxNpeMh
- *
- * @fn IX_STATUS ixNpeMhMessageSend (
-           IxNpeMhNpeId npeId,
-           IxNpeMhMessage message,
-           UINT32 maxSendRetries)
- *
- * @brief This function will send a message to a particular NPE.
- *
- * @param npeId @ref IxNpeMhNpeId [in] - The ID of the NPE to send the message
- * to.
- * @param message @ref IxNpeMhMessage [in] - The message to send.
- * @param maxSendRetries UINT32 [in] - Max num. of retries to perform
- * if the NPE's inFIFO is full.
- *
- * This function will send a message to a particular NPE.  It will be the
- * client's responsibility to ensure that the message is properly formed.
- * The return status will signify to the client if the message was
- * successfully sent or not.<P>If the message is sent to the NPE then this
- * function will return a status of success.  Note that this will only mean
- * the message has been placed in the NPE's inFIFO.  There will be no way
- * of knowing that the NPE has actually read the message, but once in the
- * incoming message queue it will be safe to assume that the NPE will
- * process it.
- * <P>The inFIFO may fill up sometimes if the Xscale is sending messages
- * faster than the NPE can handle them. This forces us to retry attempts 
- * to send the message until the NPE services the inFIFO. The client should
- * specify a ceiling value for the number of retries suitable to their
- * needs. IX_NPEMH_SEND_RETRIES_DEFAULT can be used as a default value for
- * the <i>maxSendRetries</i> parameter for this function. Each retry
- * exceeding this default number will incur a blocking delay of 1 microsecond,
- * to avoid consuming too much AHB bus bandwidth while performing retries.
- * <P>Note this function <B>must</B> only be used for messages.
- * that do not solicit responses. If the message being sent will solicit a
- * response then the ixNpeMhMessageWithResponseSend() function <B>must</B>
- * be used to ensure that the response is correctly
- * handled. <P> This function will return timeout status if NPE hang / halt 
- * while sending message. The timeout error is not related to the 
- * <i>maxSendRetries</i> as mentioned above. The timeout error will only occur 
- * if the first word of the message has been sent to NPE (not exceeding 
- * <i>maxSendRetries</i> when sending 1st message word), but the second word of
- * the message can't be written to NPE's inFIFO due to NPE hang / halt after 
- * maximum waiting time (IX_NPE_MH_MAX_NUM_OF_RETRIES). 
- * <P><B>Re-entrancy:</B> This function will be callable from any
- * thread at any time.  IxOsal will be used for any necessary
- * resource protection.
- *
- * @return The function returns a status indicating success, failure or timeout.
- */
-
-PUBLIC IX_STATUS ixNpeMhMessageSend (
-    IxNpeMhNpeId npeId,
-    IxNpeMhMessage message,
-    UINT32 maxSendRetries);
-
-/**
- * @ingroup IxNpeMh
- *
- * @fn IX_STATUS ixNpeMhMessageWithResponseSend (
-           IxNpeMhNpeId npeId,
-           IxNpeMhMessage message,
-           IxNpeMhMessageId solicitedMessageId,
-           IxNpeMhCallback solicitedCallback,
-           UINT32 maxSendRetries)
- *
- * @brief This function is equivalent to the ixNpeMhMessageSend() function,
- * but must be used when the message being sent will solicited a response.
- *
- * @param npeId @ref IxNpeMhNpeId [in] - The ID of the NPE to send the message
- * to.
- * @param message @ref IxNpeMhMessage [in] - The message to send.
- * @param solicitedMessageId @ref IxNpeMhMessageId [in] - The ID of the
- * solicited response message.
- * @param solicitedCallback @ref IxNpeMhCallback [in] - The function to use to
- * pass the response message back to the client.  A value of NULL will
- * cause the response message to be discarded.
- * @param maxSendRetries UINT32 [in] - Max num. of retries to perform
- * if the NPE's inFIFO is full.
- *
- * This function is equivalent to the ixNpeMhMessageSend() function, but
- * must be used when the message being sent will solicited a
- * response.<P>The client must specify the ID of the solicited response
- * message to allow the response to be recognised when it is received.  The
- * client must also specify a callback function to handle the received
- * response.  The IxNpeMh component will not offer the facility to send a
- * message to a NPE and receive a response within the same context.<P>Note
- * if the client is not interested in the response, specifying a NULL
- * callback will cause the response message to be discarded.<P>The
- * solicited callback will be stored and called some time later from an ISR
- * that will be triggered by the NPE's "outFIFO not empty" interrupt (see
- * ixNpeMhInitialize()) to handle the response message corresponding to the
- * message sent.  Response messages will be handled in the order they are
- * received.<P>
- * <P>The inFIFO may fill up sometimes if the Xscale is sending messages
- * faster than the NPE can handle them. This forces us to retry attempts 
- * to send the message until the NPE services the inFIFO. The client should
- * specify a ceiling value for the number of retries suitable to their
- * needs. IX_NPEMH_SEND_RETRIES_DEFAULT can be used as a default value for
- * the <i>maxSendRetries</i> parameter for this function. Each retry
- * exceeding this default number will incur a blocking delay of 1 microsecond,
- * to avoid consuming too much AHB bus bandwidth while performing retries.
- * <P> This function will return timeout status if NPE hang / halt 
- * while sending message. The timeout error is not related to the 
- * <i>maxSendRetries</i> as mentioned above. The timeout error will only occur 
- * if the first word of the message has been sent to NPE (not exceeding 
- * <i>maxSendRetries</i> when sending 1st message word), but the second word of
- * the message can't be written to NPE's inFIFO due to NPE hang / halt after 
- * maximum waiting time (IX_NPE_MH_MAX_NUM_OF_RETRIES). 
- * <P><B>Re-entrancy:</B> This function will be callable from any
- * thread at any time.  IxOsal will be used for any necessary
- * resource protection.
- *
- * @return The function returns a status indicating success or failure.
- */
-
-PUBLIC IX_STATUS ixNpeMhMessageWithResponseSend (
-    IxNpeMhNpeId npeId,
-    IxNpeMhMessage message,
-    IxNpeMhMessageId solicitedMessageId,
-    IxNpeMhCallback solicitedCallback,
-    UINT32 maxSendRetries);
-
-/**
- * @ingroup IxNpeMh
- *
- * @fn IX_STATUS ixNpeMhMessagesReceive (
-           IxNpeMhNpeId npeId)
- *
- * @brief This function will receive messages from a particular NPE and
- * pass each message to the client via a solicited callback (for solicited
- * messages) or an unsolicited callback (for unsolicited messages).
- *
- * @param npeId @ref IxNpeMhNpeId [in] - The ID of the NPE to receive and
- * process messages from.
- *
- * This function will receive messages from a particular NPE and pass each
- * message to the client via a solicited callback (for solicited messages)
- * or an unsolicited callback (for unsolicited messages).<P>If the IxNpeMh
- * component is initialised to service NPE "outFIFO not empty" interrupts
- * (see ixNpeMhInitialize()) then there is no need to call this function.
- * This function is only provided as an alternative mechanism to control
- * the receiving and processing of messages from the NPEs.<P> This function
- * will return timeout status if NPE hang / halt while receiving message. The
- * timeout error will only occur if this function has read the first word of
- * the message and can't read second word of the message from NPE's outFIFO
- * after maximum retries (IX_NPE_MH_MAX_NUM_OF_RETRIES). 
- * <P>Note this function cannot be called from within 
- * an ISR as it will use resource protection mechanisms.<P><B>Re-entrancy:</B> 
- * This function will be callable from any thread at any time.  IxOsal will be 
- * used for any necessary resource protection.
- *
- * @return The function returns a status indicating success, failure or timeout.
- */
-
-PUBLIC IX_STATUS ixNpeMhMessagesReceive (
-    IxNpeMhNpeId npeId);
-
-/**
- * @ingroup IxNpeMh
- *
- * @fn IX_STATUS ixNpeMhShow (
-           IxNpeMhNpeId npeId)
- *
- * @brief This function will display the current state of the IxNpeMh
- * component.
- *
- * <B>Re-entrancy:</B> This function will be callable from
- * any thread at any time.  However, no resource protection will be used
- * so as not to impact system performance.  As this function is only
- * reading statistical information then this is acceptable.
- *
- * @param npeId @ref IxNpeMhNpeId [in] - The ID of the NPE to display state
- * information for.
- *
- * @return The function returns a status indicating success or failure.
- */
-
-PUBLIC IX_STATUS ixNpeMhShow (
-    IxNpeMhNpeId npeId);
-
-/**
- * @ingroup IxNpeMh
- *
- * @fn IX_STATUS ixNpeMhShowReset (
-           IxNpeMhNpeId npeId)
- *
- * @brief This function will reset the current state of the IxNpeMh
- * component.
- *
- * <B>Re-entrancy:</B> This function will be callable from
- * any thread at any time.  However, no resource protection will be used
- * so as not to impact system performance.  As this function is only
- * writing statistical information then this is acceptable.
- *
- * @param npeId @ref IxNpeMhNpeId [in] - The ID of the NPE to reset state
- * information for.
- *
- * @return The function returns a status indicating success or failure.
- */
-
-PUBLIC IX_STATUS ixNpeMhShowReset (
-    IxNpeMhNpeId npeId);
-
-#endif /* IXNPEMH_H */
-
-/**
- * @} defgroup IxNpeMh
- */
diff --git a/arch/arm/cpu/ixp/npe/include/IxNpeMhConfig_p.h b/arch/arm/cpu/ixp/npe/include/IxNpeMhConfig_p.h
deleted file mode 100644
index 375b346..0000000
--- a/arch/arm/cpu/ixp/npe/include/IxNpeMhConfig_p.h
+++ /dev/null
@@ -1,555 +0,0 @@
-/**
- * @file IxNpeMhConfig_p.h
- *
- * @author Intel Corporation
- * @date 18 Jan 2002
- *
- * @brief This file contains the private API for the Configuration module.
- *
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- * 
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- * 
- * @par
- * -- End of Copyright Notice --
-*/
-
-/**
- * @defgroup IxNpeMhConfig_p IxNpeMhConfig_p
- *
- * @brief The private API for the Configuration module.
- * 
- * @{
- */
-
-#ifndef IXNPEMHCONFIG_P_H
-#define IXNPEMHCONFIG_P_H
-
-#include "IxOsal.h"
-
-#include "IxNpeMh.h"
-#include "IxNpeMhMacros_p.h"
-
-/*
- * inline definition
- */
-/* enable function inlining for performances */
-#ifdef IXNPEMHSOLICITEDCBMGR_C
-/* Non-inline functions will be defined in this translation unit. 
-	 Reason is that in GNU Compiler, if the Optimization is turn off, all extern inline
-	 functions will not be compiled.
-*/
-#		ifndef __wince
-#			ifndef IXNPEMHCONFIG_INLINE
-#				define IXNPEMHCONFIG_INLINE 
-#			endif
-#		else
-#			ifndef IXNPEMHCONFIG_INLINE
-#				define IXNPEMHCONFIG_INLINE IX_OSAL_INLINE_EXTERN
-#			endif
-#		endif /* __wince*/
-
-#else
-
-#		ifndef IXNPEMHCONFIG_INLINE
-#			define IXNPEMHCONFIG_INLINE IX_OSAL_INLINE_EXTERN
-#		endif /* IXNPEMHCONFIG_INLINE */
-#endif /* IXNPEMHSOLICITEDCBMGR_C */
-/*
- * Typedefs and #defines, etc.
- */
- 
-typedef void (*IxNpeMhConfigIsr) (int); /**< ISR function pointer */
-
-/**
- * @struct IxNpeMhConfigNpeInfo
- *
- * @brief This structure is used to maintain the configuration information
- * associated with an NPE.
- */
-
-typedef struct
-{
-    IxOsalMutex mutex;          /**< mutex */
-    UINT32 interruptId;     /**< interrupt ID */
-    UINT32 virtualRegisterBase; /**< register virtual base address */
-    UINT32 statusRegister;      /**< status register virtual address */
-    UINT32 controlRegister;     /**< control register virtual address */
-    UINT32 inFifoRegister;      /**< inFIFO register virutal address */
-    UINT32 outFifoRegister;     /**< outFIFO register virtual address */
-    IxNpeMhConfigIsr isr;   /**< isr routine for handling interrupt */
-    BOOL oldInterruptState; /**< old interrupt state (TRUE => enabled) */
-} IxNpeMhConfigNpeInfo;
-
-
-/*
- * #defines for function return types, etc.
- */
-
-/**< NPE register base address */
-#define IX_NPEMH_NPE_BASE (IX_OSAL_IXP400_PERIPHERAL_PHYS_BASE)
-
-#define IX_NPEMH_NPEA_OFFSET (0x6000) /**< NPE-A register base offset */
-#define IX_NPEMH_NPEB_OFFSET (0x7000) /**< NPE-B register base offset */
-#define IX_NPEMH_NPEC_OFFSET (0x8000) /**< NPE-C register base offset */
-
-#define IX_NPEMH_NPESTAT_OFFSET (0x002C) /**< NPE status register offset */
-#define IX_NPEMH_NPECTL_OFFSET  (0x0030) /**< NPE control register offset */
-#define IX_NPEMH_NPEFIFO_OFFSET (0x0038) /**< NPE FIFO register offset */
-
-/** NPE-A register base address */
-#define IX_NPEMH_NPEA_BASE (IX_NPEMH_NPE_BASE + IX_NPEMH_NPEA_OFFSET)
-/** NPE-B register base address */
-#define IX_NPEMH_NPEB_BASE (IX_NPEMH_NPE_BASE + IX_NPEMH_NPEB_OFFSET)
-/** NPE-C register base address */
-#define IX_NPEMH_NPEC_BASE (IX_NPEMH_NPE_BASE + IX_NPEMH_NPEC_OFFSET)
-
-/* NPE-A configuration */
-
-/** NPE-A interrupt */
-#define IX_NPEMH_NPEA_INT  (IX_OSAL_IXP400_NPEA_IRQ_LVL)
-/** NPE-A FIFO register */
-#define IX_NPEMH_NPEA_FIFO (IX_NPEMH_NPEA_BASE + IX_NPEMH_NPEFIFO_OFFSET)
-/** NPE-A control register */
-#define IX_NPEMH_NPEA_CTL  (IX_NPEMH_NPEA_BASE + IX_NPEMH_NPECTL_OFFSET)
-/** NPE-A status register */
-#define IX_NPEMH_NPEA_STAT (IX_NPEMH_NPEA_BASE + IX_NPEMH_NPESTAT_OFFSET)
-
-/* NPE-B configuration */
-
-/** NPE-B interrupt */
-#define IX_NPEMH_NPEB_INT  (IX_OSAL_IXP400_NPEB_IRQ_LVL)
-/** NPE-B FIFO register */
-#define IX_NPEMH_NPEB_FIFO (IX_NPEMH_NPEB_BASE + IX_NPEMH_NPEFIFO_OFFSET)
-/** NPE-B control register */
-#define IX_NPEMH_NPEB_CTL  (IX_NPEMH_NPEB_BASE + IX_NPEMH_NPECTL_OFFSET)
-/** NPE-B status register */
-#define IX_NPEMH_NPEB_STAT (IX_NPEMH_NPEB_BASE + IX_NPEMH_NPESTAT_OFFSET)
-
-/* NPE-C configuration */
-
-/** NPE-C interrupt */
-#define IX_NPEMH_NPEC_INT  (IX_OSAL_IXP400_NPEC_IRQ_LVL)
-/** NPE-C FIFO register */
-#define IX_NPEMH_NPEC_FIFO (IX_NPEMH_NPEC_BASE + IX_NPEMH_NPEFIFO_OFFSET)
-/** NPE-C control register */
-#define IX_NPEMH_NPEC_CTL  (IX_NPEMH_NPEC_BASE + IX_NPEMH_NPECTL_OFFSET)
-/** NPE-C status register */
-#define IX_NPEMH_NPEC_STAT (IX_NPEMH_NPEC_BASE + IX_NPEMH_NPESTAT_OFFSET)
-
-/* NPE control register bit definitions */
-#define IX_NPEMH_NPE_CTL_OFE   (1 << 16) /**< OutFifoEnable */
-#define IX_NPEMH_NPE_CTL_IFE   (1 << 17) /**< InFifoEnable */
-#define IX_NPEMH_NPE_CTL_OFEWE (1 << 24) /**< OutFifoEnableWriteEnable */
-#define IX_NPEMH_NPE_CTL_IFEWE (1 << 25) /**< InFifoEnableWriteEnable */
-
-/* NPE status register bit definitions */
-#define IX_NPEMH_NPE_STAT_OFNE  (1 << 16) /**< OutFifoNotEmpty */
-#define IX_NPEMH_NPE_STAT_IFNF  (1 << 17) /**< InFifoNotFull */
-#define IX_NPEMH_NPE_STAT_OFNF  (1 << 18) /**< OutFifoNotFull */
-#define IX_NPEMH_NPE_STAT_IFNE  (1 << 19) /**< InFifoNotEmpty */
-#define IX_NPEMH_NPE_STAT_MBINT (1 << 20) /**< Mailbox interrupt */
-#define IX_NPEMH_NPE_STAT_IFINT (1 << 21) /**< InFifo interrupt */
-#define IX_NPEMH_NPE_STAT_OFINT (1 << 22) /**< OutFifo interrupt */
-#define IX_NPEMH_NPE_STAT_WFINT (1 << 23) /**< WatchFifo interrupt */
-
-
-/**
- * Variable declarations.  Externs are followed by static variables.
- */
-extern IxNpeMhConfigNpeInfo ixNpeMhConfigNpeInfo[IX_NPEMH_NUM_NPES];
-
-
-/*
- * Prototypes for interface functions.
- */
-
-/**
- * @fn void ixNpeMhConfigInitialize (
-           IxNpeMhNpeInterrupts npeInterrupts)
- *
- * @brief This function initialises the Configuration module.
- *
- * @param IxNpeMhNpeInterrupts npeInterrupts (in) - whether or not to
- * service the NPE "outFIFO not empty" interrupts.
- *
- * @return No return value.
- */
-
-void ixNpeMhConfigInitialize (
-    IxNpeMhNpeInterrupts npeInterrupts);
-
-/**
- * @fn void ixNpeMhConfigUninit (void)
- *
- * @brief This function uninitialises the Configuration module.
- *
- * @return No return value.
- */
-
-void ixNpeMhConfigUninit (void);
-
-/**
- * @fn void ixNpeMhConfigIsrRegister (
-           IxNpeMhNpeId npeId,
-           IxNpeMhConfigIsr isr)
- *
- * @brief This function registers an ISR to handle NPE "outFIFO not
- * empty" interrupts.
- *
- * @param IxNpeMhNpeId npeId (in) - the ID of the NPE whose interrupt will
- * be handled.
- * @param IxNpeMhConfigIsr isr (in) - the ISR function pointer that the
- * interrupt will trigger.
- *
- * @return No return value.
- */
-
-void ixNpeMhConfigIsrRegister (
-    IxNpeMhNpeId npeId,
-    IxNpeMhConfigIsr isr);
-
-/**
- * @fn BOOL ixNpeMhConfigNpeInterruptEnable (
-           IxNpeMhNpeId npeId)
- *
- * @brief This function enables a NPE's "outFIFO not empty" interrupt.
- *
- * @param IxNpeMhNpeId npeId (in) - the ID of the NPE whose interrupt will
- * be enabled.
- *
- * @return Returns the previous state of the interrupt (TRUE => enabled).
- */
-
-BOOL ixNpeMhConfigNpeInterruptEnable (
-    IxNpeMhNpeId npeId);
-
-/**
- * @fn BOOL ixNpeMhConfigNpeInterruptDisable (
-           IxNpeMhNpeId npeId)
- *
- * @brief This function disables a NPE's "outFIFO not empty" interrupt
- *
- * @param IxNpeMhNpeId npeId (in) - the ID of the NPE whose interrupt will
- * be disabled.
- *
- * @return Returns the previous state of the interrupt (TRUE => enabled).
- */
-
-BOOL ixNpeMhConfigNpeInterruptDisable (
-    IxNpeMhNpeId npeId);
-
-/**
- * @fn IxNpeMhMessageId ixNpeMhConfigMessageIdGet (
-           IxNpeMhMessage message)
- *
- * @brief This function gets the ID of a message.
- *
- * @param IxNpeMhMessage message (in) - the message to get the ID of.
- *
- * @return the ID of the message
- */
-
-IxNpeMhMessageId ixNpeMhConfigMessageIdGet (
-    IxNpeMhMessage message);
-
-/**
- * @fn BOOL ixNpeMhConfigNpeIdIsValid (
-           IxNpeMhNpeId npeId)
- *
- * @brief This function checks to see if a NPE ID is valid.
- *
- * @param IxNpeMhNpeId npeId (in) - the NPE ID to validate.
- *
- * @return True if the NPE ID is valid, otherwise False.
- */
-
-BOOL ixNpeMhConfigNpeIdIsValid (
-    IxNpeMhNpeId npeId);
-
-/**
- * @fn void ixNpeMhConfigLockGet (
-           IxNpeMhNpeId npeId)
- *
- * @brief This function gets a lock for exclusive NPE interaction, and
- * disables the NPE's "outFIFO not empty" interrupt.
- *
- * @param IxNpeMhNpeId npeId (in) - The ID of the NPE for which to get the
- * lock and disable its interrupt.
- *
- * @return No return value.
- */
-
-void ixNpeMhConfigLockGet (
-    IxNpeMhNpeId npeId);
-
-/**
- * @fn void ixNpeMhConfigLockRelease (
-           IxNpeMhNpeId npeId)
- *
- * @brief This function releases a lock for exclusive NPE interaction, and
- * enables the NPE's "outFIFO not empty" interrupt.
- *
- * @param IxNpeMhNpeId npeId (in) - The ID of the NPE for which to release
- * the lock and enable its interrupt.
- *
- * @return No return value.
- */
-
-void ixNpeMhConfigLockRelease (
-    IxNpeMhNpeId npeId);
-
-/**
- * @fn BOOL ixNpeMhConfigInFifoIsEmpty (
-           IxNpeMhNpeId npeId)
- *
- * @brief This inline function checks if a NPE's inFIFO is empty.
- *
- * @param IxNpeMhNpeId npeId (in) - The ID of the NPE for which the inFIFO
- * will be checked.
- *
- * @return True if the inFIFO is empty, otherwise False.
- */
-
-IXNPEMHCONFIG_INLINE BOOL ixNpeMhConfigInFifoIsEmpty (
-    IxNpeMhNpeId npeId);
-
-/**
- * @fn BOOL ixNpeMhConfigInFifoIsFull (
-           IxNpeMhNpeId npeId)
- *
- * @brief This inline function checks if a NPE's inFIFO is full.
- *
- * @param IxNpeMhNpeId npeId (in) - The ID of the NPE for which the inFIFO
- * will be checked.
- *
- * @return True if the inFIFO is full, otherwise False.
- */
-
-IXNPEMHCONFIG_INLINE BOOL ixNpeMhConfigInFifoIsFull (
-    IxNpeMhNpeId npeId);
-
-/**
- * @fn BOOL ixNpeMhConfigOutFifoIsEmpty (
-           IxNpeMhNpeId npeId)
- *
- * @brief This inline function checks if a NPE's outFIFO is empty.
- *
- * @param IxNpeMhNpeId npeId (in) - The ID of the NPE for which the outFIFO
- * will be checked.
- *
- * @return True if the outFIFO is empty, otherwise False.
- */
-
-IXNPEMHCONFIG_INLINE BOOL ixNpeMhConfigOutFifoIsEmpty (
-    IxNpeMhNpeId npeId);
-
-/**
- * @fn BOOL ixNpeMhConfigOutFifoIsFull (
-           IxNpeMhNpeId npeId)
- *
- * @brief This inline function checks if a NPE's outFIFO is full.
- *
- * @param IxNpeMhNpeId npeId (in) - The ID of the NPE for which the outFIFO
- * will be checked.
- *
- * @return True if the outFIFO is full, otherwise False.
- */
-
-IXNPEMHCONFIG_INLINE BOOL ixNpeMhConfigOutFifoIsFull (
-    IxNpeMhNpeId npeId);
-
-/**
- * @fn IX_STATUS ixNpeMhConfigInFifoWrite (
-           IxNpeMhNpeId npeId,
-           IxNpeMhMessage message)
- *
- * @brief This function writes a message to a NPE's inFIFO.  The caller
- * must first check that the NPE's inFifo is not full. After writing the first 
- * word of the message, this function will keep polling NPE's inFIFO is not
- * full to write the second word. If inFIFO is not available after maximum 
- * retries (IX_NPE_MH_MAX_NUM_OF_RETRIES), this function will return TIMEOUT 
- * status to indicate NPE hang / halt.
- *
- * @param IxNpeMhNpeId npeId (in) - The ID of the NPE for which the inFIFO
- * will be written to.
- * @param IxNpeMhMessage message (in) - The message to write.
- *
- * @return The function returns a status indicating success, failure or timeout.
- */
-
-IX_STATUS ixNpeMhConfigInFifoWrite (
-    IxNpeMhNpeId npeId,
-    IxNpeMhMessage message);
-
-/**
- * @fn IX_STATUS ixNpeMhConfigOutFifoRead (
-           IxNpeMhNpeId npeId,
-           IxNpeMhMessage *message)
- *
- * @brief This function reads a message from a NPE's outFIFO.  The caller
- * must first check that the NPE's outFifo is not empty. After reading the first 
- * word of the message, this function will keep polling NPE's outFIFO is not
- * empty to read the second word. If outFIFO is empty after maximum 
- * retries (IX_NPE_MH_MAX_NUM_OF_RETRIES), this function will return TIMEOUT 
- * status to indicate NPE hang / halt.
- *
- * @param IxNpeMhNpeId npeId (in) - The ID of the NPE for which the outFIFO
- * will be read from.
- * @param IxNpeMhMessage message (out) - The message read.
- *
- * @return The function returns a status indicating success, failure or timeout.
- */
-
-IX_STATUS ixNpeMhConfigOutFifoRead (
-    IxNpeMhNpeId npeId,
-    IxNpeMhMessage *message);
-
-/**
- * @fn void ixNpeMhConfigShow (
-           IxNpeMhNpeId npeId)
- *
- * @brief This function will display the current state of the Configuration
- * module.
- *
- * @param IxNpeMhNpeId npeId (in) - The ID of the NPE to display state
- * information for.
- *
- * @return No return value.
- */
-
-void ixNpeMhConfigShow (
-    IxNpeMhNpeId npeId);
-
-/**
- * @fn void ixNpeMhConfigShowReset (
-           IxNpeMhNpeId npeId)
- *
- * @brief This function will reset the current state of the Configuration
- * module.
- *
- * @param IxNpeMhNpeId npeId (in) - The ID of the NPE to reset state
- * information for.
- *
- * @return No return value.
- */
-
-void ixNpeMhConfigShowReset (
-    IxNpeMhNpeId npeId);
-
-/*
- * Inline functions
- */
- 
-/*
- * This inline function checks if a NPE's inFIFO is empty.
- */
-
-IXNPEMHCONFIG_INLINE
-BOOL ixNpeMhConfigInFifoIsEmpty (
-    IxNpeMhNpeId npeId)
-{
-    UINT32 ifne;
-    volatile UINT32 *statusReg =
-        (UINT32 *)ixNpeMhConfigNpeInfo[npeId].statusRegister;
-
-    /* get the IFNE (InFifoNotEmpty) bit of the status register */
-    IX_NPEMH_REGISTER_READ_BITS (statusReg, &ifne, IX_NPEMH_NPE_STAT_IFNE);
-
-    /* if the IFNE status bit is unset then the inFIFO is empty */
-    return (ifne == 0);
-}
-
-
-/*
- * This inline function checks if a NPE's inFIFO is full.
- */
-IXNPEMHCONFIG_INLINE
-BOOL ixNpeMhConfigInFifoIsFull (
-    IxNpeMhNpeId npeId)
-{
-    UINT32 ifnf;
-    volatile UINT32 *statusReg =
-        (UINT32 *)ixNpeMhConfigNpeInfo[npeId].statusRegister;
-
-    /* get the IFNF (InFifoNotFull) bit of the status register */
-    IX_NPEMH_REGISTER_READ_BITS (statusReg, &ifnf, IX_NPEMH_NPE_STAT_IFNF);
-
-    /* if the IFNF status bit is unset then the inFIFO is full */
-    return (ifnf == 0);
-}
-
-
-/*
- * This inline function checks if a NPE's outFIFO is empty.
- */
-IXNPEMHCONFIG_INLINE
-BOOL ixNpeMhConfigOutFifoIsEmpty (
-    IxNpeMhNpeId npeId)
-{
-    UINT32 ofne;
-    volatile UINT32 *statusReg =
-        (UINT32 *)ixNpeMhConfigNpeInfo[npeId].statusRegister;
-
-    /* get the OFNE (OutFifoNotEmpty) bit of the status register */
-    IX_NPEMH_REGISTER_READ_BITS (statusReg, &ofne, IX_NPEMH_NPE_STAT_OFNE);
-
-    /* if the OFNE status bit is unset then the outFIFO is empty */
-    return (ofne == 0);
-}
-
-/*
- * This inline function checks if a NPE's outFIFO is full.
- */
-IXNPEMHCONFIG_INLINE
-BOOL ixNpeMhConfigOutFifoIsFull (
-    IxNpeMhNpeId npeId)
-{
-    UINT32 ofnf;
-    volatile UINT32 *statusReg =
-        (UINT32 *)ixNpeMhConfigNpeInfo[npeId].statusRegister;
-
-    /* get the OFNF (OutFifoNotFull) bit of the status register */
-    IX_NPEMH_REGISTER_READ_BITS (statusReg, &ofnf, IX_NPEMH_NPE_STAT_OFNF);
-
-    /* if the OFNF status bit is unset then the outFIFO is full */
-    return (ofnf == 0);
-}
-
-#endif /* IXNPEMHCONFIG_P_H */
-
-/**
- * @} defgroup IxNpeMhConfig_p
- */
diff --git a/arch/arm/cpu/ixp/npe/include/IxNpeMhMacros_p.h b/arch/arm/cpu/ixp/npe/include/IxNpeMhMacros_p.h
deleted file mode 100644
index 68f34ef..0000000
--- a/arch/arm/cpu/ixp/npe/include/IxNpeMhMacros_p.h
+++ /dev/null
@@ -1,296 +0,0 @@
-/**
- * @file IxNpeMhMacros_p.h
- *
- * @author Intel Corporation
- * @date 21 Jan 2002
- *
- * @brief This file contains the macros for the IxNpeMh component.
- *
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- * 
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- * 
- * @par
- * -- End of Copyright Notice --
-*/
-
-/**
- * @defgroup IxNpeMhMacros_p IxNpeMhMacros_p
- *
- * @brief Macros for the IxNpeMh component.
- * 
- * @{
- */
-
-#ifndef IXNPEMHMACROS_P_H
-#define IXNPEMHMACROS_P_H
-
-/* if we are running as a unit test */
-#ifdef IX_UNIT_TEST
-#undef NDEBUG
-#endif /* #ifdef IX_UNIT_TEST */
-
-#include "IxOsal.h"
-
-/*
- * #defines for function return types, etc.
- */
-
-#define IX_NPEMH_SHOW_TEXT_WIDTH (40) /**< text width for stats display */
-#define IX_NPEMH_SHOW_STAT_WIDTH (10) /**< stat width for stats display */
-
-/**
- * @def IX_NPEMH_SHOW
- *
- * @brief Macro for displaying a stat preceded by a textual description.
- */
-
-#define IX_NPEMH_SHOW(TEXT, STAT) \
-    ixOsalLog (IX_OSAL_LOG_LVL_USER, IX_OSAL_LOG_DEV_STDOUT, \
-               "%-40s: %10d\n", (int) TEXT, (int) STAT, 0, 0, 0, 0)
-
-/*
- * Prototypes for interface functions.
- */
-
-/**
- * @typedef IxNpeMhTraceTypes
- *
- * @brief Enumeration defining IxNpeMh trace levels
- */
-
-typedef enum
-{
-    IX_NPEMH_TRACE_OFF     = IX_OSAL_LOG_LVL_NONE,    /**< no trace */
-    IX_NPEMH_WARNING       = IX_OSAL_LOG_LVL_WARNING, /**< warning */
-    IX_NPEMH_DEBUG         = IX_OSAL_LOG_LVL_MESSAGE, /**< debug */
-    IX_NPEMH_FN_ENTRY_EXIT = IX_OSAL_LOG_LVL_DEBUG3   /**< function entry/exit */
-} IxNpeMhTraceTypes;
-
-#ifdef IX_UNIT_TEST
-#define IX_NPEMH_TRACE_LEVEL (IX_NPEMH_FN_ENTRY_EXIT) /**< trace level */
-#else
-#define IX_NPEMH_TRACE_LEVEL (IX_NPEMH_TRACE_OFF) /**< trace level */
-#endif
-
-/**
- * @def IX_NPEMH_TRACE0
- *
- * @brief Trace macro taking 0 arguments.
- */
-
-#define IX_NPEMH_TRACE0(LEVEL, STR) \
-    IX_NPEMH_TRACE6(LEVEL, STR, 0, 0, 0, 0, 0, 0)
-
-/**
- * @def IX_NPEMH_TRACE1
- *
- * @brief Trace macro taking 1 argument.
- */
-
-#define IX_NPEMH_TRACE1(LEVEL, STR, ARG1) \
-    IX_NPEMH_TRACE6(LEVEL, STR, ARG1, 0, 0, 0, 0, 0)
-
-/**
- * @def IX_NPEMH_TRACE2
- *
- * @brief Trace macro taking 2 arguments.
- */
-
-#define IX_NPEMH_TRACE2(LEVEL, STR, ARG1, ARG2) \
-    IX_NPEMH_TRACE6(LEVEL, STR, ARG1, ARG2, 0, 0, 0, 0)
-
-/**
- * @def IX_NPEMH_TRACE3
- *
- * @brief Trace macro taking 3 arguments.
- */
-
-#define IX_NPEMH_TRACE3(LEVEL, STR, ARG1, ARG2, ARG3) \
-    IX_NPEMH_TRACE6(LEVEL, STR, ARG1, ARG2, ARG3, 0, 0, 0)
-
-/**
- * @def IX_NPEMH_TRACE4
- *
- * @brief Trace macro taking 4 arguments.
- */
-
-#define IX_NPEMH_TRACE4(LEVEL, STR, ARG1, ARG2, ARG3, ARG4) \
-    IX_NPEMH_TRACE6(LEVEL, STR, ARG1, ARG2, ARG3, ARG4, 0, 0)
-
-/**
- * @def IX_NPEMH_TRACE5
- *
- * @brief Trace macro taking 5 arguments.
- */
-
-#define IX_NPEMH_TRACE5(LEVEL, STR, ARG1, ARG2, ARG3, ARG4, ARG5) \
-    IX_NPEMH_TRACE6(LEVEL, STR, ARG1, ARG2, ARG3, ARG4, ARG5, 0)
-
-/**
- * @def IX_NPEMH_TRACE6
- *
- * @brief Trace macro taking 6 arguments.
- */
-
-#define IX_NPEMH_TRACE6(LEVEL, STR, ARG1, ARG2, ARG3, ARG4, ARG5, ARG6) \
-{ \
-    if (LEVEL <= IX_NPEMH_TRACE_LEVEL) \
-    { \
-        (void) ixOsalLog (LEVEL, IX_OSAL_LOG_DEV_STDOUT, (STR), \
-                          (int)(ARG1), (int)(ARG2), (int)(ARG3), \
-                          (int)(ARG4), (int)(ARG5), (int)(ARG6)); \
-    } \
-}
-
-/**
- * @def IX_NPEMH_ERROR_REPORT
- *
- * @brief Error reporting facility.
- */
-
-#define IX_NPEMH_ERROR_REPORT(STR) \
-{ \
-    (void) ixOsalLog (IX_OSAL_LOG_LVL_ERROR, IX_OSAL_LOG_DEV_STDERR, \
-		      (STR), 0, 0, 0, 0, 0, 0); \
-}
-
-/* if we are running on XScale, i.e. real environment */
-#if CPU==XSCALE
-
-/**
- * @def IX_NPEMH_REGISTER_READ
- *
- * @brief This macro reads a memory-mapped register.
- */
-
-#define IX_NPEMH_REGISTER_READ(registerAddress, value) \
-{ \
-    *value = IX_OSAL_READ_LONG(registerAddress); \
-}
-
-/**
- * @def IX_NPEMH_REGISTER_READ_BITS
- *
- * @brief This macro partially reads a memory-mapped register.
- */
-
-#define IX_NPEMH_REGISTER_READ_BITS(registerAddress, value, mask) \
-{ \
-    *value = (IX_OSAL_READ_LONG(registerAddress) & mask); \
-}
-
-/**
- * @def IX_NPEMH_REGISTER_WRITE
- *
- * @brief This macro writes a memory-mapped register.
- */
-
-#define IX_NPEMH_REGISTER_WRITE(registerAddress, value) \
-{ \
-    IX_OSAL_WRITE_LONG(registerAddress, value); \
-}
-
-/**
- * @def IX_NPEMH_REGISTER_WRITE_BITS
- *
- * @brief This macro partially writes a memory-mapped register.
- */
-
-#define IX_NPEMH_REGISTER_WRITE_BITS(registerAddress, value, mask) \
-{ \
-    UINT32 orig = IX_OSAL_READ_LONG(registerAddress); \
-    orig &= (~mask); \
-    orig |= (value & mask); \
-    IX_OSAL_WRITE_LONG(registerAddress, orig); \
-}
-
-
-/* if we are running as a unit test */
-#else /* #if CPU==XSCALE */
-
-#include "IxNpeMhTestRegister.h"
-
-/**
- * @def IX_NPEMH_REGISTER_READ
- *
- * @brief This macro reads a memory-mapped register.
- */
-
-#define IX_NPEMH_REGISTER_READ(registerAddress, value) \
-{ \
-    ixNpeMhTestRegisterRead (registerAddress, value); \
-}
-
-/**
- * @def IX_NPEMH_REGISTER_READ_BITS
- *
- * @brief This macro partially reads a memory-mapped register.
- */
-
-#define IX_NPEMH_REGISTER_READ_BITS(registerAddress, value, mask) \
-{ \
-    ixNpeMhTestRegisterReadBits (registerAddress, value, mask); \
-}
-
-/**
- * @def IX_NPEMH_REGISTER_WRITE
- *
- * @brief This macro writes a memory-mapped register.
- */
-
-#define IX_NPEMH_REGISTER_WRITE(registerAddress, value) \
-{ \
-    ixNpeMhTestRegisterWrite (registerAddress, value); \
-}
-
-/**
- * @def IX_NPEMH_REGISTER_WRITE_BITS
- *
- * @brief This macro partially writes a memory-mapped register.
- */
-
-#define IX_NPEMH_REGISTER_WRITE_BITS(registerAddress, value, mask) \
-{ \
-    ixNpeMhTestRegisterWriteBits (registerAddress, value, mask); \
-}
-
-#endif /* #if CPU==XSCALE */
-
-#endif /* IXNPEMHMACROS_P_H */
-
-/**
- * @} defgroup IxNpeMhMacros_p
- */
diff --git a/arch/arm/cpu/ixp/npe/include/IxNpeMhReceive_p.h b/arch/arm/cpu/ixp/npe/include/IxNpeMhReceive_p.h
deleted file mode 100644
index 6416bed..0000000
--- a/arch/arm/cpu/ixp/npe/include/IxNpeMhReceive_p.h
+++ /dev/null
@@ -1,139 +0,0 @@
-/**
- * @file IxNpeMhReceive_p.h
- *
- * @author Intel Corporation
- * @date 18 Jan 2002
- *
- * @brief This file contains the private API for the Receive module.
- *
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- * 
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- * 
- * @par
- * -- End of Copyright Notice --
-*/
-
-/**
- * @defgroup IxNpeMhReceive_p IxNpeMhReceive_p
- *
- * @brief The private API for the Receive module.
- * 
- * @{
- */
-
-#ifndef IXNPEMHRECEIVE_P_H
-#define IXNPEMHRECEIVE_P_H
-
-#include "IxNpeMh.h"
-#include "IxOsalTypes.h"
-
-/*
- * #defines for function return types, etc.
- */
-
-/*
- * Prototypes for interface functions.
- */
-
-/**
- * @fn void ixNpeMhReceiveInitialize (void)
- *
- * @brief This function registers an internal ISR to handle the NPEs'
- * "outFIFO not empty" interrupts and receive messages from the NPEs when
- * they become available.
- *
- * @return No return value.
- */
-
-void ixNpeMhReceiveInitialize (void);
-
-/**
- * @fn IX_STATUS ixNpeMhReceiveMessagesReceive (
-           IxNpeMhNpeId npeId)
- *
- * @brief This function reads messages from a particular NPE's outFIFO
- * until the outFIFO is empty, and for each message looks first for an
- * unsolicited callback, then a solicited callback, to pass the message
- * back to the client.  If no callback can be found the message is
- * discarded and an error reported. This function will return TIMEOUT 
- * status if NPE hang / halt.
- *
- * @param IxNpeMhNpeId npeId (in) - The ID of the NPE to receive
- * messages from.
- *
- * @return The function returns a status indicating success, failure or timeout.
- */
-
-IX_STATUS ixNpeMhReceiveMessagesReceive (
-    IxNpeMhNpeId npeId);
-
-/**
- * @fn void ixNpeMhReceiveShow (
-           IxNpeMhNpeId npeId)
- *
- * @brief This function will display the current state of the Receive
- * module.
- *
- * @param IxNpeMhNpeId npeId (in) - The ID of the NPE to display state
- * information for.
- *
- * @return No return status.
- */
-
-void ixNpeMhReceiveShow (
-    IxNpeMhNpeId npeId);
-
-/**
- * @fn void ixNpeMhReceiveShowReset (
-           IxNpeMhNpeId npeId)
- *
- * @brief This function will reset the current state of the Receive
- * module.
- *
- * @param IxNpeMhNpeId npeId (in) - The ID of the NPE to reset state
- * information for.
- *
- * @return No return status.
- */
-
-void ixNpeMhReceiveShowReset (
-    IxNpeMhNpeId npeId);
-
-#endif /* IXNPEMHRECEIVE_P_H */
-
-/**
- * @} defgroup IxNpeMhReceive_p
- */
diff --git a/arch/arm/cpu/ixp/npe/include/IxNpeMhSend_p.h b/arch/arm/cpu/ixp/npe/include/IxNpeMhSend_p.h
deleted file mode 100644
index 977cc94..0000000
--- a/arch/arm/cpu/ixp/npe/include/IxNpeMhSend_p.h
+++ /dev/null
@@ -1,163 +0,0 @@
-/**
- * @file IxNpeMhSend_p.h
- *
- * @author Intel Corporation
- * @date 18 Jan 2002
- *
- * @brief This file contains the private API for the Send module.
- *
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- * 
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- * 
- * @par
- * -- End of Copyright Notice --
-*/
-
-/**
- * @defgroup IxNpeMhSend_p IxNpeMhSend_p
- *
- * @brief The private API for the Send module.
- * 
- * @{
- */
-
-#ifndef IXNPEMHSEND_P_H
-#define IXNPEMHSEND_P_H
-
-#include "IxNpeMh.h"
-#include "IxOsalTypes.h"
-
-/*
- * #defines for function return types, etc.
- */
-
-/*
- * Prototypes for interface functions.
- */
-
-/**
- * @fn IX_STATUS ixNpeMhSendMessageSend (
-           IxNpeMhNpeId npeId,
-           IxNpeMhMessage message,
-           UINT32 maxSendRetries)
- *
- * @brief This function writes a message to the specified NPE's inFIFO,
- * and must be used when the message being sent does not solicit a response
- * from the NPE. This function will return TIMEOUT status if NPE hang / halt.
- *
- * @param IxNpeMhNpeId npeId (in) - The ID of the NPE to send the message
- * to.
- * @param IxNpeMhMessage message (in) - The message to send.
- * @param UINT32 maxSendRetries (in) - Max num. of retries to perform
- * if the NPE's inFIFO is full.
- *
- * @return The function returns a status indicating success, failure or timeout.
- */
-
-IX_STATUS ixNpeMhSendMessageSend (
-    IxNpeMhNpeId npeId,
-    IxNpeMhMessage message,
-    UINT32 maxSendRetries);
-
-/**
- * @fn IX_STATUS ixNpeMhSendMessageWithResponseSend (
-           IxNpeMhNpeId npeId,
-           IxNpeMhMessage message,
-           IxNpeMhMessageId solicitedMessageId,
-           IxNpeMhCallback solicitedCallback,
-           UINT32 maxSendRetries)
- *
- * @brief This function writes a message to the specified NPE's inFIFO,
- * and must be used when the message being sent solicits a response from
- * the NPE.  The ID of the solicited response must be specified so that it
- * can be recognised, and a callback provided to pass the response back to
- * the client. This function will return TIMEOUT status if NPE hang / halt.
- *
- * @param IxNpeMhNpeId npeId (in) - The ID of the NPE to send the message
- * to.
- * @param IxNpeMhMessage message (in) - The message to send.
- * @param IxNpeMhMessageId solicitedMessageId (in) - The ID of the
- * solicited response.
- * @param IxNpeMhCallback solicitedCallback (in) - The callback to pass the
- * solicited response back to the client.
- * @param UINT32 maxSendRetries (in) - Max num. of retries to perform
- * if the NPE's inFIFO is full.
- *
- * @return The function returns a status indicating success, failure or timeout.
- */
-
-IX_STATUS ixNpeMhSendMessageWithResponseSend (
-    IxNpeMhNpeId npeId,
-    IxNpeMhMessage message,
-    IxNpeMhMessageId solicitedMessageId,
-    IxNpeMhCallback solicitedCallback,
-    UINT32 maxSendRetries);
-
-/**
- * @fn void ixNpeMhSendShow (
-           IxNpeMhNpeId npeId)
- *
- * @brief This function will display the current state of the Send module.
- *
- * @param IxNpeMhNpeId npeId (in) - The ID of the NPE to display state
- * information for.
- *
- * @return No return value.
- */
-
-void ixNpeMhSendShow (
-    IxNpeMhNpeId npeId);
-
-/**
- * @fn void ixNpeMhSendShowReset (
-           IxNpeMhNpeId npeId)
- *
- * @brief This function will reset the current state of the Send module.
- *
- * @param IxNpeMhNpeId npeId (in) - The ID of the NPE to reset state
- * information for.
- *
- * @return No return value.
- */
-
-void ixNpeMhSendShowReset (
-    IxNpeMhNpeId npeId);
-
-#endif /* IXNPEMHSEND_P_H */
-
-/**
- * @} defgroup IxNpeMhSend_p
- */
diff --git a/arch/arm/cpu/ixp/npe/include/IxNpeMhSolicitedCbMgr_p.h b/arch/arm/cpu/ixp/npe/include/IxNpeMhSolicitedCbMgr_p.h
deleted file mode 100644
index 40cd496..0000000
--- a/arch/arm/cpu/ixp/npe/include/IxNpeMhSolicitedCbMgr_p.h
+++ /dev/null
@@ -1,171 +0,0 @@
-/**
- * @file IxNpeMhSolicitedCbMgr_p.h
- *
- * @author Intel Corporation
- * @date 18 Jan 2002
- *
- * @brief This file contains the private API for the Solicited Callback
- * Manager module.
- *
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- * 
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- * 
- * @par
- * -- End of Copyright Notice --
-*/
-
-/**
- * @defgroup IxNpeMhSolicitedCbMgr_p IxNpeMhSolicitedCbMgr_p
- *
- * @brief The private API for the Solicited Callback Manager module.
- * 
- * @{
- */
-
-#ifndef IXNPEMHSOLICITEDCBMGR_P_H
-#define IXNPEMHSOLICITEDCBMGR_P_H
-
-#include "IxNpeMh.h"
-#include "IxOsalTypes.h"
-
-/*
- * #defines for function return types, etc.
- */
-
-/** Maximum number of solicited callbacks that can be stored in the list */
-#define IX_NPEMH_MAX_CALLBACKS (16)
-
-/*
- * Prototypes for interface functions.
- */
-
-/**
- * @fn void ixNpeMhSolicitedCbMgrInitialize (void)
- *
- * @brief This function initializes the Solicited Callback Manager module,
- * setting up a callback data structure for each NPE.
- *
- * @return No return value.
- */
-
-void ixNpeMhSolicitedCbMgrInitialize (void);
-
-/**
- * @fn IX_STATUS ixNpeMhSolicitedCbMgrCallbackSave (
-           IxNpeMhNpeId npeId,
-           IxNpeMhMessageId solicitedMessageId,
-           IxNpeMhCallback solicitedCallback)
- *
- * @brief This function saves a callback in the specified NPE's callback
- * list.  If the callback list is full the function will fail.
- *
- * @param IxNpeMhNpeId npeId (in) - The ID of the NPE in whose callback
- * list the callback will be saved.
- * @param IxNpeMhMessageId solicitedMessageId (in) - The ID of the message
- * that this callback is for.
- * @param IxNpeMhCallback solicitedCallback (in) - The callback function
- * pointer to save.
- *
- * @return The function returns a status indicating success or failure.
- */
-
-IX_STATUS ixNpeMhSolicitedCbMgrCallbackSave (
-    IxNpeMhNpeId npeId,
-    IxNpeMhMessageId solicitedMessageId,
-    IxNpeMhCallback solicitedCallback);
-
-/**
- * @fn void ixNpeMhSolicitedCbMgrCallbackRetrieve (
-           IxNpeMhNpeId npeId,
-           IxNpeMhMessageId solicitedMessageId,
-           IxNpeMhCallback *solicitedCallback)
- *
- * @brief This function retrieves the first ID-matching callback from the
- * specified NPE's callback list.  If no matching callback can be found the
- * function will fail.
- *
- * @param IxNpeMhNpeId npeId (in) - The ID of the NPE from whose callback
- * list the callback will be retrieved.
- * @param IxNpeMhMessageId solicitedMessageId (in) - The ID of the message
- * that the callback is for.
- * @param IxNpeMhCallback solicitedCallback (out) - The callback function
- * pointer retrieved.
- *
- * @return No return value.
- */
-
-void ixNpeMhSolicitedCbMgrCallbackRetrieve (
-    IxNpeMhNpeId npeId,
-    IxNpeMhMessageId solicitedMessageId,
-    IxNpeMhCallback *solicitedCallback);
-
-/**
- * @fn void ixNpeMhSolicitedCbMgrShow (
-           IxNpeMhNpeId npeId)
- *
- * @brief This function will display the current state of the Solicited
- * Callback Manager module.
- *
- * @param IxNpeMhNpeId npeId (in) - The ID of the NPE to display state
- * information for.
- *
- * @return No return value.
- */
-
-void ixNpeMhSolicitedCbMgrShow (
-    IxNpeMhNpeId npeId);
-
-/**
- * @fn void ixNpeMhSolicitedCbMgrShowReset (
-           IxNpeMhNpeId npeId)
- *
- * @brief This function will reset the current state of the Solicited
- * Callback Manager module.
- *
- * @param IxNpeMhNpeId npeId (in) - The ID of the NPE to reset state
- * information for.
- *
- * @return No return value.
- */
-
-void ixNpeMhSolicitedCbMgrShowReset (
-    IxNpeMhNpeId npeId);
-
-#endif /* IXNPEMHSOLICITEDCBMGR_P_H */
-
-/**
- * @} defgroup IxNpeMhSolicitedCbMgr_p
- */
diff --git a/arch/arm/cpu/ixp/npe/include/IxNpeMhUnsolicitedCbMgr_p.h b/arch/arm/cpu/ixp/npe/include/IxNpeMhUnsolicitedCbMgr_p.h
deleted file mode 100644
index dea8caf..0000000
--- a/arch/arm/cpu/ixp/npe/include/IxNpeMhUnsolicitedCbMgr_p.h
+++ /dev/null
@@ -1,169 +0,0 @@
-/**
- * @file IxNpeMhUnsolicitedCbMgr_p.h
- *
- * @author Intel Corporation
- * @date 18 Jan 2002
- *
- * @brief This file contains the private API for the Unsolicited Callback
- * Manager module.
- *
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- * 
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- * 
- * @par
- * -- End of Copyright Notice --
- */
-
-/**
- * @defgroup IxNpeMhUnsolicitedCbMgr_p IxNpeMhUnsolicitedCbMgr_p
- *
- * @brief The private API for the Unsolicited Callback Manager module.
- * 
- * @{
- */
-
-#ifndef IXNPEMHUNSOLICITEDCBMGR_P_H
-#define IXNPEMHUNSOLICITEDCBMGR_P_H
-
-#include "IxNpeMh.h"
-#include "IxOsalTypes.h"
-
-/*
- * #defines for function return types, etc.
- */
-
-/*
- * Prototypes for interface functions.
- */
-
-/**
- * @fn void ixNpeMhUnsolicitedCbMgrInitialize (void)
- *
- * @brief This function initializes the Unsolicited Callback Manager
- * module, setting up a callback data structure for each NPE.
- *
- * @return No return value.
- */
-
-void ixNpeMhUnsolicitedCbMgrInitialize (void);
-
-/**
- * @fn void ixNpeMhUnsolicitedCbMgrCallbackSave (
-           IxNpeMhNpeId npeId,
-           IxNpeMhMessageId unsolicitedMessageId,
-           IxNpeMhCallback unsolicitedCallback)
- *
- * @brief This function saves a callback in the specified NPE's callback
- * table.  If a callback already exists for the specified ID then it will
- * be overwritten.
- *
- * @param IxNpeMhNpeId npeId (in) - The ID of the NPE in whose callback
- * table the callback will be saved.
- * @param IxNpeMhMessageId unsolicitedMessageId (in) - The ID of the
- * messages that this callback is for.
- * @param IxNpeMhCallback unsolicitedCallback (in) - The callback function
- * pointer to save.
- *
- * @return No return value.
- */
-
-void ixNpeMhUnsolicitedCbMgrCallbackSave (
-    IxNpeMhNpeId npeId,
-    IxNpeMhMessageId unsolicitedMessageId,
-    IxNpeMhCallback unsolicitedCallback);
-
-/**
- * @fn void ixNpeMhUnsolicitedCbMgrCallbackRetrieve (
-           IxNpeMhNpeId npeId,
-           IxNpeMhMessageId unsolicitedMessageId,
-           IxNpeMhCallback *unsolicitedCallback)
- *
- * @brief This function retrieves the callback for the specified ID from
- * the specified NPE's callback table.  If no callback is registered for
- * the specified ID and NPE then a callback value of NULL will be returned.
- *
- * @param IxNpeMhNpeId npeId (in) - The ID of the NPE from whose callback
- * table the callback will be retrieved.
- * @param IxNpeMhMessageId unsolicitedMessageId (in) - The ID of the
- * messages that the callback is for.
- * @param IxNpeMhCallback unsolicitedCallback (out) - The callback function
- * pointer retrieved.
- *
- * @return No return value.
- */
-
-void ixNpeMhUnsolicitedCbMgrCallbackRetrieve (
-    IxNpeMhNpeId npeId,
-    IxNpeMhMessageId unsolicitedMessageId,
-    IxNpeMhCallback *unsolicitedCallback);
-
-/**
- * @fn void ixNpeMhUnsolicitedCbMgrShow (
-           IxNpeMhNpeId npeId)
- *
- * @brief This function will display the current state of the Unsolicited
- * Callback Manager module.
- *
- * @param IxNpeMhNpeId npeId (in) - The ID of the NPE to display state
- * information for.
- *
- * @return No return value.
- */
-
-void ixNpeMhUnsolicitedCbMgrShow (
-    IxNpeMhNpeId npeId);
-
-/**
- * @fn void ixNpeMhUnsolicitedCbMgrShowReset (
-           IxNpeMhNpeId npeId)
- *
- * @brief This function will reset the current state of the Unsolicited
- * Callback Manager module.
- *
- * @param IxNpeMhNpeId npeId (in) - The ID of the NPE to reset state
- * information for.
- *
- * @return No return value.
- */
-
-void ixNpeMhUnsolicitedCbMgrShowReset (
-    IxNpeMhNpeId npeId);
-
-#endif /* IXNPEMHUNSOLICITEDCBMGR_P_H */
-
-/**
- * @} defgroup IxNpeMhUnsolicitedCbMgr_p
- */
diff --git a/arch/arm/cpu/ixp/npe/include/IxNpeMicrocode.h b/arch/arm/cpu/ixp/npe/include/IxNpeMicrocode.h
deleted file mode 100644
index 893d803..0000000
--- a/arch/arm/cpu/ixp/npe/include/IxNpeMicrocode.h
+++ /dev/null
@@ -1,296 +0,0 @@
-/**
- * @date   April 18, 2005
- *
- * @brief  IXP400 NPE Microcode Image file
- *
- * This file was generated by the IxNpeDlImageGen tool.
- * It contains a NPE microcode image suitable for use
- * with the NPE Downloader (IxNpeDl) component in the
- * IXP400 Access Driver software library.
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
-*/
-
-/**
- * @defgroup IxNpeMicrocode IXP400 NPE Microcode Image Library
- *
- * @brief Library containing a set of NPE firmware images, for use
- * with NPE Downloader s/w component
- *
- * @{
- */
-
-/**
- * @def IX_NPE_IMAGE_INCLUDE
- *
- * @brief Wrap the following Image identifiers with "#if IX_NPE_IMAGE_INCLUDE ... #endif" to include the image in the library
- */
-#define IX_NPE_IMAGE_INCLUDE 1
-
-/**
- * @def IX_NPE_IMAGE_OMIT
- *
- * @brief Wrap the following Image identifiers with "#if IX_NPE_IMAGE_OMIT ... #endif" to OMIT the image from the library
- */
-#define IX_NPE_IMAGE_OMIT    0
-
-
-#if IX_NPE_IMAGE_INCLUDE
-/**
- * @def IX_NPEDL_NPEIMAGE_NPEA_HSS0
- *
- * @brief NPE Image Id for NPE-A with HSS-0 Only feature.  It supports 32 channelized and 4 packetized.
- */
-#define IX_NPEDL_NPEIMAGE_NPEA_HSS0 0x00010000
-#endif
-
-#if IX_NPE_IMAGE_INCLUDE
-/**
- * @def IX_NPEDL_NPEIMAGE_NPEA_HSS0_ATM_SPHY_1_PORT
- *
- * @brief NPE Image Id for NPE-A with HSS-0 and ATM feature. For HSS, it supports 16/32 channelized and 4/0 packetized. For ATM, it supports AAL5, AAL0 and OAM for UTOPIA SPHY, 1 logical port, 32 VCs. It also has Fast Path support.
- */
-#define IX_NPEDL_NPEIMAGE_NPEA_HSS0_ATM_SPHY_1_PORT 0x00020000
-#endif
-
-#if IX_NPE_IMAGE_INCLUDE
-/**
- * @def IX_NPEDL_NPEIMAGE_NPEA_HSS0_ATM_MPHY_1_PORT
- *
- * @brief NPE Image Id for NPE-A with HSS-0 and ATM feature. For HSS, it supports 16/32 channelized and 4/0 packetized. For ATM, it supports AAL5, AAL0 and OAM for UTOPIA MPHY, 1 logical port, 32 VCs. It also has Fast Path support.
- */
-#define IX_NPEDL_NPEIMAGE_NPEA_HSS0_ATM_MPHY_1_PORT 0x00030000
-#endif
-
-#if IX_NPE_IMAGE_INCLUDE
-/**
- * @def IX_NPEDL_NPEIMAGE_NPEA_ATM_MPHY_12_PORT
- *
- * @brief NPE Image Id for NPE-A with ATM-Only feature. It supports AAL5, AAL0 and OAM for UTOPIA MPHY, 12 logical ports, 32 VCs. It also has Fast Path support.
- */
-#define IX_NPEDL_NPEIMAGE_NPEA_ATM_MPHY_12_PORT 0x00040000
-#endif
-
-#if IX_NPE_IMAGE_INCLUDE
-/**
- * @def IX_NPEDL_NPEIMAGE_NPEA_DMA
- *
- * @brief NPE Image Id for NPE-A with DMA-Only feature.
- */
-#define IX_NPEDL_NPEIMAGE_NPEA_DMA 0x00150100
-#endif
-
-#if IX_NPE_IMAGE_INCLUDE
-/**
- * @def IX_NPEDL_NPEIMAGE_NPEA_HSS_2_PORT
- *
- * @brief NPE Image Id for NPE-A with HSS-0 and HSS-1 feature. Each HSS port supports 32 channelized and 4 packetized.
- */
-#define IX_NPEDL_NPEIMAGE_NPEA_HSS_2_PORT 0x00090000
-#endif
-
-#if IX_NPE_IMAGE_INCLUDE
-/**
- * @def IX_NPEDL_NPEIMAGE_NPEA_ETH
- *
- * @brief NPE Image Id for NPE-A with Basic Ethernet Rx/Tx which includes: MAC_FILTERING, MAC_LEARNING, SPANNING_TREE, FIREWALL
- */
-#define IX_NPEDL_NPEIMAGE_NPEA_ETH 0x10800200
-#endif
-
-#if IX_NPE_IMAGE_INCLUDE
-/**
- * @def IX_NPEDL_NPEIMAGE_NPEA_ETH_LEARN_FILTER_SPAN_FIREWALL
- *
- * @brief NPE Image Id for NPE-A with Basic Ethernet Rx/Tx which includes: MAC_FILTERING, MAC_LEARNING, SPANNING_TREE, FIREWALL
- */
-#define IX_NPEDL_NPEIMAGE_NPEA_ETH_LEARN_FILTER_SPAN_FIREWALL 0x10800200
-#endif
-
-#if IX_NPE_IMAGE_INCLUDE
-/**
- * @def IX_NPEDL_NPEIMAGE_NPEA_ETH_LEARN_FILTER_SPAN_FIREWALL_VLAN_QOS
- *
- * @brief NPE Image Id for NPE-A with Ethernet Rx/Tx which includes: MAC_FILTERING, MAC_LEARNING, SPANNING_TREE, FIREWALL, VLAN_QOS
- */
-#define IX_NPEDL_NPEIMAGE_NPEA_ETH_LEARN_FILTER_SPAN_FIREWALL_VLAN_QOS 0x10810200
-#endif
-
-#if IX_NPE_IMAGE_INCLUDE
-/**
- * @def IX_NPEDL_NPEIMAGE_NPEA_ETH_SPAN_FIREWALL_VLAN_QOS_HDR_CONV
- *
- * @brief NPE Image Id for NPE-A with Ethernet Rx/Tx which includes: SPANNING_TREE, FIREWALL, VLAN_QOS, HEADER_CONVERSION
- */
-#define IX_NPEDL_NPEIMAGE_NPEA_ETH_SPAN_FIREWALL_VLAN_QOS_HDR_CONV 0x10820200
-#endif
-
-#if IX_NPE_IMAGE_INCLUDE
-/**
- * @def IX_NPEDL_NPEIMAGE_NPEB_ETH
- *
- * @brief NPE Image Id for NPE-B with Basic Ethernet Rx/Tx which includes: MAC_FILTERING, MAC_LEARNING, SPANNING_TREE, FIREWALL
- */
-#define IX_NPEDL_NPEIMAGE_NPEB_ETH 0x01000200
-#endif
-
-#if IX_NPE_IMAGE_INCLUDE
-/**
- * @def IX_NPEDL_NPEIMAGE_NPEB_ETH_LEARN_FILTER_SPAN_FIREWALL
- *
- * @brief NPE Image Id for NPE-B with Basic Ethernet Rx/Tx which includes: MAC_FILTERING, MAC_LEARNING, SPANNING_TREE, FIREWALL
- */
-#define IX_NPEDL_NPEIMAGE_NPEB_ETH_LEARN_FILTER_SPAN_FIREWALL 0x01000200
-#endif
-
-#if IX_NPE_IMAGE_INCLUDE
-/**
- * @def IX_NPEDL_NPEIMAGE_NPEB_ETH_LEARN_FILTER_SPAN_FIREWALL_VLAN_QOS
- *
- * @brief NPE Image Id for NPE-B with Ethernet Rx/Tx which includes: MAC_FILTERING, MAC_LEARNING, SPANNING_TREE, FIREWALL, VLAN_QOS
- */
-#define IX_NPEDL_NPEIMAGE_NPEB_ETH_LEARN_FILTER_SPAN_FIREWALL_VLAN_QOS 0x01010200
-#endif
-
-#if IX_NPE_IMAGE_INCLUDE
-/**
- * @def IX_NPEDL_NPEIMAGE_NPEB_ETH_SPAN_FIREWALL_VLAN_QOS_HDR_CONV
- *
- * @brief NPE Image Id for NPE-B with Ethernet Rx/Tx which includes: SPANNING_TREE, FIREWALL, VLAN_QOS, HEADER_CONVERSION
- */
-#define IX_NPEDL_NPEIMAGE_NPEB_ETH_SPAN_FIREWALL_VLAN_QOS_HDR_CONV 0x01020200
-#endif
-
-#if IX_NPE_IMAGE_INCLUDE
-/**
- * @def IX_NPEDL_NPEIMAGE_NPEB_DMA
- *
- * @brief NPE Image Id for NPE-B with DMA-Only feature.
- */
-#define IX_NPEDL_NPEIMAGE_NPEB_DMA 0x01020100
-#endif
-
-#if IX_NPE_IMAGE_INCLUDE
-/**
- * @def IX_NPEDL_NPEIMAGE_NPEC_ETH
- *
- * @brief NPE Image Id for NPE-C with Basic Ethernet Rx/Tx which includes: MAC_FILTERING, MAC_LEARNING, SPANNING_TREE, FIREWALL
- */
-#define IX_NPEDL_NPEIMAGE_NPEC_ETH 0x02000200
-#endif
-
-#if IX_NPE_IMAGE_INCLUDE
-/**
- * @def IX_NPEDL_NPEIMAGE_NPEC_ETH_LEARN_FILTER_SPAN_FIREWALL
- *
- * @brief NPE Image Id for NPE-C with Basic Ethernet Rx/Tx which includes: MAC_FILTERING, MAC_LEARNING, SPANNING_TREE, FIREWALL
- */
-#define IX_NPEDL_NPEIMAGE_NPEC_ETH_LEARN_FILTER_SPAN_FIREWALL 0x02000200
-#endif
-
-#if IX_NPE_IMAGE_INCLUDE
-/**
- * @def IX_NPEDL_NPEIMAGE_NPEC_ETH_LEARN_FILTER_SPAN_FIREWALL_VLAN_QOS
- *
- * @brief NPE Image Id for NPE-C with Ethernet Rx/Tx which includes: MAC_FILTERING, MAC_LEARNING, SPANNING_TREE, FIREWALL, VLAN_QOS
- */
-#define IX_NPEDL_NPEIMAGE_NPEC_ETH_LEARN_FILTER_SPAN_FIREWALL_VLAN_QOS 0x02010200
-#endif
-
-#if IX_NPE_IMAGE_INCLUDE
-/**
- * @def IX_NPEDL_NPEIMAGE_NPEC_ETH_SPAN_FIREWALL_VLAN_QOS_HDR_CONV
- *
- * @brief NPE Image Id for NPE-C with Ethernet Rx/Tx which includes: SPANNING_TREE, FIREWALL, VLAN_QOS, HEADER_CONVERSION
- */
-#define IX_NPEDL_NPEIMAGE_NPEC_ETH_SPAN_FIREWALL_VLAN_QOS_HDR_CONV 0x02020200
-#endif
-
-#if IX_NPE_IMAGE_INCLUDE
-/**
- * @def IX_NPEDL_NPEIMAGE_NPEC_DMA
- *
- * @brief NPE Image Id for NPE-C with DMA-Only feature.
- */
-#define IX_NPEDL_NPEIMAGE_NPEC_DMA 0x02080100
-#endif
-
-/* Number of NPE firmware images in this library */
-#define IX_NPE_MICROCODE_AVAILABLE_VERSIONS_COUNT 17
-
-/* Location of Microcode Images */
-#ifdef IX_NPE_MICROCODE_FIRMWARE_INCLUDED
-#ifdef IX_NPEDL_READ_MICROCODE_FROM_FILE
-
-extern UINT32* ixNpeMicrocode_binaryArray;
-
-#else
-
-extern unsigned IxNpeMicrocode_array[];
-
-#endif
-#endif
-
-/*
- * sr: undef all but the bare minimum to reduce flash usage for U-Boot
- */
-#undef IX_NPEDL_NPEIMAGE_NPEA_HSS0
-#undef IX_NPEDL_NPEIMAGE_NPEA_HSS0_ATM_SPHY_1_PORT
-#undef IX_NPEDL_NPEIMAGE_NPEA_HSS0_ATM_MPHY_1_PORT
-#undef IX_NPEDL_NPEIMAGE_NPEA_ATM_MPHY_12_PORT
-#undef IX_NPEDL_NPEIMAGE_NPEA_DMA
-#undef IX_NPEDL_NPEIMAGE_NPEA_HSS_2_PORT
-#undef IX_NPEDL_NPEIMAGE_NPEA_ETH
-#undef IX_NPEDL_NPEIMAGE_NPEA_ETH_LEARN_FILTER_SPAN_FIREWALL
-#undef IX_NPEDL_NPEIMAGE_NPEA_ETH_LEARN_FILTER_SPAN_FIREWALL_VLAN_QOS
-#undef IX_NPEDL_NPEIMAGE_NPEA_ETH_SPAN_FIREWALL_VLAN_QOS_HDR_CONV
-#undef IX_NPEDL_NPEIMAGE_NPEB_ETH
-#undef IX_NPEDL_NPEIMAGE_NPEB_ETH_LEARN_FILTER_SPAN_FIREWALL
-/* #undef IX_NPEDL_NPEIMAGE_NPEB_ETH_LEARN_FILTER_SPAN_FIREWALL_VLAN_QOS */
-#undef IX_NPEDL_NPEIMAGE_NPEB_ETH_SPAN_FIREWALL_VLAN_QOS_HDR_CONV
-#undef IX_NPEDL_NPEIMAGE_NPEB_DMA
-#undef IX_NPEDL_NPEIMAGE_NPEC_ETH
-#undef IX_NPEDL_NPEIMAGE_NPEC_ETH_LEARN_FILTER_SPAN_FIREWALL
-/* #undef IX_NPEDL_NPEIMAGE_NPEC_ETH_LEARN_FILTER_SPAN_FIREWALL_VLAN_QOS */
-#undef IX_NPEDL_NPEIMAGE_NPEC_ETH_SPAN_FIREWALL_VLAN_QOS_HDR_CONV
-#undef IX_NPEDL_NPEIMAGE_NPEC_DMA
-
-/**
- * @} defgroup IxNpeMicrocode
- */
diff --git a/arch/arm/cpu/ixp/npe/include/IxOsBufLib.h b/arch/arm/cpu/ixp/npe/include/IxOsBufLib.h
deleted file mode 100644
index a297a97..0000000
--- a/arch/arm/cpu/ixp/npe/include/IxOsBufLib.h
+++ /dev/null
@@ -1,55 +0,0 @@
-/**
- * @file IxOsBufLib.h  (Replaced by OSAL)
- *
- * @date 9 Oct 2002
- *
- * @brief This file contains the mbuf pool initialisation entry point
- *
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- * 
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- * 
- * @par
- * -- End of Copyright Notice --
- *
- */
-
-#ifndef IXOSBUFLIB_H
-#define IXOSBUFLIB_H
-
-#include "IxOsalBackward.h"
-
-#endif /* IXOSBUFLIB_H */
-
diff --git a/arch/arm/cpu/ixp/npe/include/IxOsBuffMgt.h b/arch/arm/cpu/ixp/npe/include/IxOsBuffMgt.h
deleted file mode 100644
index b7de712..0000000
--- a/arch/arm/cpu/ixp/npe/include/IxOsBuffMgt.h
+++ /dev/null
@@ -1,52 +0,0 @@
-/**
- * @file (Replaced by OSAL)
- *
- * @brief This file includes the OS dependant MBUF header files.
- *
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- * 
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- * 
- * @par
- * -- End of Copyright Notice --
- */
-
-
-#ifndef IxOsBuffMgt_inc
-#define IxOsBuffMgt_inc
-
-#include "IxOsalBackward.h"
-
-#endif /* ndef IxOsBuffMgt_inc */
diff --git a/arch/arm/cpu/ixp/npe/include/IxOsBuffPoolMgt.h b/arch/arm/cpu/ixp/npe/include/IxOsBuffPoolMgt.h
deleted file mode 100644
index 4a983c7..0000000
--- a/arch/arm/cpu/ixp/npe/include/IxOsBuffPoolMgt.h
+++ /dev/null
@@ -1,74 +0,0 @@
-/**
- * @file IxOsBuffPoolMgt.h (Replaced by OSAL)
- *
- * @date 9 Oct 2002
- *
- * @brief This file contains the mbuf pool implementation API
- *
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- * 
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- * 
- * @par
- * -- End of Copyright Notice --
- * This module contains the implementation of the OS Services buffer pool
- * management service.  This module provides routines for creating pools
- * of buffers for exchange of network data, getting and returning buffers
- * from and to the pool, and some other utility functions. 
- * <P>
- * Currently, the pool has 2 underlying implementations - one for the vxWorks
- * OS, and another which attempts to be OS-agnostic so that it can be used on
- * other OS's such as Linux.  The API is largely the same for all OS's,
- * but there are some differences to be aware of.  These are documented
- * in the API descriptions below.
- * <P>
- * The most significant difference is this: when this module is used with
- * the WindRiver VxWorks OS, it will create a pool of vxWorks "MBufs".
- * These can be used directly with the vxWorks "netBufLib" OS Library.
- * For other OS's, it will create a pool of generic buffers.  These may need
- * to be converted into other buffer types (sk_buff's in Linux, for example)
- * before being used with any built-in OS routines available for
- * manipulating network data buffers.
- *
- * @sa IxOsBuffMgt.h
- */
-
-#ifndef IXOSBUFFPOOLMGT_H
-#define IXOSBUFFPOOLMGT_H
-
-#include "IxOsalBackward.h"
-
-#endif  /* IXOSBUFFPOOLMGT_H */
-
diff --git a/arch/arm/cpu/ixp/npe/include/IxOsCacheMMU.h b/arch/arm/cpu/ixp/npe/include/IxOsCacheMMU.h
deleted file mode 100644
index 2c8592f..0000000
--- a/arch/arm/cpu/ixp/npe/include/IxOsCacheMMU.h
+++ /dev/null
@@ -1,60 +0,0 @@
-/**
- * @file IxOsCacheMMU.h
- *
- * @brief this file contains the API of the @ref IxCacheMMU component
- * 
- * <hr>
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- * 
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- * 
- * @par
- * -- End of Copyright Notice --
- */
-
-#ifndef IxOsCacheMMU_H
-
-#ifndef __doxygen_hide
-#define IxOsCacheMMU_H
-#endif /* __doxygen_hide */
-
-#ifdef __doxygen_HIDE
-#define IX_OS_CACHE_DOXYGEN
-#endif /* __doxygen_HIDE */
-
-#include "IxOsalBackward.h"
-
-#endif /* IxOsCacheMMU_H */
-
diff --git a/arch/arm/cpu/ixp/npe/include/IxOsPrintf.h b/arch/arm/cpu/ixp/npe/include/IxOsPrintf.h
deleted file mode 100644
index 218e140..0000000
--- a/arch/arm/cpu/ixp/npe/include/IxOsPrintf.h
+++ /dev/null
@@ -1,102 +0,0 @@
-/**
- * @file IxOsPrintf.h
- *
- * @brief this file contains the API of the @ref IxOsServices component
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- * 
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- * 
- * @par
- * -- End of Copyright Notice --
- */
-
-#include "IxTypes.h"
-
-#ifndef IxOsPrintf_H
-
-#ifndef __doxygen_hide
-#define IxOsPrintf_H
-#endif /* __doxygen_hide */
-
-#ifdef __wince
-
-#ifndef IX_USE_SERCONSOLE
-
-static int
-ixLogMsg(
-    char *pFormat, 
-    ...
-    )
-{    
-#ifndef IN_KERNEL
-    static WCHAR    pOutputString[256]; 
-	static char     pNarrowStr[256];
-    int             returnCnt = 0; 
-    va_list ap;
-    
-    pOutputString[0] = 0; 
-	pNarrowStr[0] = 0;	
-    
-    va_start(ap, pFormat);
-
-	returnCnt = _vsnprintf(pNarrowStr, 256, pFormat, ap);
-
-    MultiByteToWideChar(
-            CP_ACP, 
-            MB_PRECOMPOSED, 
-            pNarrowStr, 
-            -1, 
-            pOutputString, 
-            256
-            ); 
-
-    OutputDebugString(pOutputString);
-
-    return returnCnt; 
-#else
-    return 0; 
-#endif
-}
-#define printf ixLogMsg
-
-#endif /* IX_USE_SERCONSOLE */
-
-#endif /* __wince */
-
-/**
- * @} IxOsPrintf
- */
-
-#endif /* IxOsPrintf_H */
diff --git a/arch/arm/cpu/ixp/npe/include/IxOsServices.h b/arch/arm/cpu/ixp/npe/include/IxOsServices.h
deleted file mode 100644
index 62e8a79..0000000
--- a/arch/arm/cpu/ixp/npe/include/IxOsServices.h
+++ /dev/null
@@ -1,55 +0,0 @@
-/**
- * @file (Replaced by OSAL)
- *
- * @brief this file contains the API of the @ref IxOsServices component
- * 
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- * 
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- * 
- * @par
- * -- End of Copyright Notice --
- */
-#ifndef IxOsServices_H
-
-#ifndef __doxygen_hide
-#define IxOsServices_H
-#endif /* __doxygen_hide */
-
-#include "IxOsalBackward.h"
-
-#endif /* IxOsServices_H */
-
-
diff --git a/arch/arm/cpu/ixp/npe/include/IxOsServicesComponents.h b/arch/arm/cpu/ixp/npe/include/IxOsServicesComponents.h
deleted file mode 100644
index d662cd3..0000000
--- a/arch/arm/cpu/ixp/npe/include/IxOsServicesComponents.h
+++ /dev/null
@@ -1,134 +0,0 @@
-/**
- * @file IxOsServicesComponents.h (Replaced by OSAL)
- *
- * @brief Header file for memory access
- *
- * @par
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- * 
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- * 
- * @par
- * -- End of Copyright Notice --
- */
-
-#ifndef IxOsServicesComponents_H
-#define IxOsServicesComponents_H
-
-#include "IxOsalBackward.h"
- * codelets_parityENAcc
- * timeSyncAcc
- * parityENAcc
- * sspAcc
- * i2c
- * integration_sspAcc
- * integration_i2c
-#define ix_timeSyncAcc         36
-#define ix_parityENAcc         37
-#define ix_codelets_parityENAcc     38
-#define ix_sspAcc              39
-#define ix_i2c                 40
-#define ix_integration_sspAcc  41
-#define ix_integration_i2c     42
-#define ix_osal		       43
-#define ix_integration_parityENAcc  44
-#define ix_integration_timeSyncAcc  45
-
-/***************************
- * timeSyncAcc
- ***************************/
-#if (IX_COMPONENT_NAME == ix_timeSyncAcc)
-
-#if defined (IX_OSSERV_VXWORKS_LE)
-
-#define CSR_LE_DATA_COHERENT_MAPPING
-
-#endif /* IX_OSSERV_VXWORKS_LE */
-
-#endif /* timeSyncAcc */
-
-/***************************
- * parityENAcc
- ***************************/
-#if (IX_COMPONENT_NAME == ix_parityENAcc)
-
-#if defined (IX_OSSERV_VXWORKS_LE)
-
-#define CSR_LE_DATA_COHERENT_MAPPING
-
-#endif /* IX_OSSERV_VXWORKS_LE */
-
-#endif /* parityENAcc */
-
-/***************************
- * codelets_parityENAcc
- ***************************/
-#if (IX_COMPONENT_NAME == ix_codelets_parityENAcc)
-
-#if defined (IX_OSSERV_VXWORKS_LE)
-
-#define CSR_LE_DATA_COHERENT_MAPPING
-
-#endif /* IX_OSSERV_VXWORKS_LE */
-
-#endif /* codelets_parityENAcc */
-
-#endif /* IxOsServicesComponents_H */
-
-/***************************
- * integration_timeSyncAcc
- ***************************/
-#if (IX_COMPONENT_NAME == ix_integration_timeSyncAcc)
-
-#if defined (IX_OSSERV_VXWORKS_LE)
-
-#define CSR_LE_DATA_COHERENT_MAPPING
-
-#endif /* IX_OSSERV_VXWORKS_LE */
-
-#endif /* integration_timeSyncAcc */
-
-/***************************
- * integration_parityENAcc
- ***************************/
-#if (IX_COMPONENT_NAME == ix_integration_parityENAcc)
-
-#if defined (IX_OSSERV_VXWORKS_LE)
-
-#define CSR_LE_DATA_COHERENT_MAPPING
-
-#endif /* IX_OSSERV_VXWORKS_LE */
-
-#endif /* integration_parityENAcc */
diff --git a/arch/arm/cpu/ixp/npe/include/IxOsServicesEndianess.h b/arch/arm/cpu/ixp/npe/include/IxOsServicesEndianess.h
deleted file mode 100644
index 0d6cd8c..0000000
--- a/arch/arm/cpu/ixp/npe/include/IxOsServicesEndianess.h
+++ /dev/null
@@ -1,52 +0,0 @@
-/** 
- * @file IxOsServicesEndianess.h (Replaced by OSAL)
- * 
- * @brief Header file for determining system endianess and OS
- * 
- * @par
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- * 
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- * 
- * @par
- * -- End of Copyright Notice --
- */
- 
-#ifndef IxOsServicesEndianess_H
-#define IxOsServicesEndianess_H
-
-#include "IxOsalBackward.h"
-
-#endif /* IxOsServicesEndianess_H */
diff --git a/arch/arm/cpu/ixp/npe/include/IxOsServicesMemAccess.h b/arch/arm/cpu/ixp/npe/include/IxOsServicesMemAccess.h
deleted file mode 100644
index 58e9941..0000000
--- a/arch/arm/cpu/ixp/npe/include/IxOsServicesMemAccess.h
+++ /dev/null
@@ -1,52 +0,0 @@
-/** 
- * @file IxOsServicesMemAccess.h (Replaced by OSAL)
- * 
- * @brief Header file for memory access
- * 
- * @par
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- * 
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- * 
- * @par
- * -- End of Copyright Notice --
- */
-
-#ifndef IxOsServicesMemAccess_H
-#define IxOsServicesMemAccess_H
-
-#include "IxOsalBackward.h"
-
-#endif /* IxOsServicesMemAccess_H */
diff --git a/arch/arm/cpu/ixp/npe/include/IxOsServicesMemMap.h b/arch/arm/cpu/ixp/npe/include/IxOsServicesMemMap.h
deleted file mode 100644
index 4ce37c3..0000000
--- a/arch/arm/cpu/ixp/npe/include/IxOsServicesMemMap.h
+++ /dev/null
@@ -1,54 +0,0 @@
-/**
- * @file IxOsServicesMemMap.h (Replaced by OSAL)
- * 
- * @brief Header file for memory access maps
- * 
- * @par
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- * 
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- * 
- * @par
- * -- End of Copyright Notice --
- */
-
-#ifndef IxOsServicesMemMap_H
-#define IxOsServicesMemMap_H
-
-#include "IxOsalBackward.h"
-#define IX_OSSERV_ETH_NPEA_MAP_SIZE           (0x1000)     /**< Eth for NPEA map size */
-#define IX_OSSERV_ETH_NPEA_PHYS_BASE           IXP425_Eth_NPEA_BASE_PHYS
-
-#endif /* IxOsServicesMemMap_H */
diff --git a/arch/arm/cpu/ixp/npe/include/IxOsal.h b/arch/arm/cpu/ixp/npe/include/IxOsal.h
deleted file mode 100644
index b2a93a5..0000000
--- a/arch/arm/cpu/ixp/npe/include/IxOsal.h
+++ /dev/null
@@ -1,1517 +0,0 @@
-/**
- * @file IxOsal.h
- *
- * @brief Top include file for OSAL 
- * 
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- * 
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- * 
- * @par
- * -- End of Copyright Notice --
- */
-
-#ifndef IxOsal_H
-#define IxOsal_H
-
-/* Basic types */
-#include "IxOsalTypes.h"
-
-/* Include assert */
-#include "IxOsalAssert.h"
-
-/* 
- * Config header gives users option to choose IO MEM 
- * and buffer management modules 
- */
-
-#include "IxOsalConfig.h"
-
-/*
- * Symbol file needed by some OS.
- */
-#include "IxOsalUtilitySymbols.h"
-
-/* OS-specific header */
-#include "IxOsalOs.h"
-
-
-/**
- * @defgroup IxOsal Operating System Abstraction Layer (IxOsal) API
- *
- * @brief This service provides a thin layer of OS dependency services. 
- *
- * This file contains the API to the functions which are some what OS dependant and would
- * require porting to a particular OS. 
- * A primary focus of the component development is to make them as OS independent as possible.
- * All other components should abstract their OS dependency to this module.
- * Services overview
- *	-# Data types, constants, defines
- *	-# Interrupts
- *              - bind interrupts to handlers
- *              - unbind interrupts from handlers
- *             	- disables all interrupts 
- *              - enables all interrupts 
- *              - selectively disables interrupts 
- *              - enables an interrupt level 
- *              - disables an interrupt level 
- *      -# Memory
- *              - allocates memory
- *              - frees memory 
- *              - copies memory zones 
- *              - fills a memory zone 
- *              - allocates cache-safe memory 
- *              - frees cache-safe memory 
- *              - physical to virtual address translation 
- *              - virtual to physical address translation 
- *              - cache to memory flush 
- *              - cache line invalidate 
- *      -# Threads
- *              - creates a new thread 
- *              - starts a newly created thread 
- *              - kills an existing thread 
- *              - exits a running thread 
- *              - sets the priority of an existing thread 
- *              - suspends thread execution 
- *              - resumes thread execution 
- *      -# IPC
- *              - creates a message queue 
- *              - deletes a message queue 
- *              - sends a message to a message queue 
- *              - receives a message from a message queue
- *      -# Thread Synchronisation
- *              - initializes a mutex 
- *              - locks a mutex 
- *              - unlocks a mutex 
- *              - non-blocking attempt to lock a mutex 
- *              - destroys a mutex object 
- *              - initializes a fast mutex 
- *              - non-blocking attempt to lock a fast mutex 
- *              - unlocks a fast mutex 
- *              - destroys a fast mutex object 
- *              - initializes a semaphore 
- *              - posts to (increments) a semaphore 
- *              - waits on (decrements) a semaphore 
- *              - non-blocking wait on semaphore 
- *              - gets semaphore value 
- *              - destroys a semaphore object 
- *              - yields execution of current thread 
- *      -# Time functions
- *              - yielding sleep for a number of milliseconds 
- *              - busy sleep for a number of microseconds 
- *              - value of the timestamp counter 
- *              - resolution of the timestamp counter 
- *              - system clock rate, in ticks 
- *              - current system time 
- *              - converts ixOsalTimeVal into ticks 
- *              - converts ticks into ixOsalTimeVal 
- *              - converts ixOsalTimeVal to milliseconds 
- *              - converts milliseconds to IxOsalTimeval 
- *              - "equal" comparison for IxOsalTimeval 
- *              - "less than" comparison for IxOsalTimeval 
- *              - "greater than" comparison for IxOsalTimeval 
- *              - "add" operator for IxOsalTimeval 
- *              - "subtract" operator for IxOsalTimeval 
- *      -# Logging
- *              - sets the current logging verbosity level 
- *              - interrupt-safe logging function 
- *      -# Timer services
- *              - schedules a repeating timer 
- *              - schedules a single-shot timer 
- *              - cancels a running timer 
- *              - displays all the running timers 
- *      -# Optional Modules
- *              - Buffer management module
- *              - I/O memory and endianess support module
- *
- * @{
- */
-
-
-/*
- * Prototypes
- */
-
-/* ==========================  Interrupts  ================================
- * 
- */
-
-/** 
- * @ingroup IxOsal
- *
- * @brief Binds an interrupt handler to an interrupt level
- *
- * @param irqLevel (in)   - interrupt level
- * @param irqHandler (in) - interrupt handler
- * @param parameter (in)  - custom parameter to be passed to the
- *                          interrupt handler
- *
- * Binds an interrupt handler to an interrupt level. The operation will
- * fail if the wrong level is selected, if the handler is NULL, or if the
- * interrupt is already bound. This functions binds the specified C
- * routine to an interrupt level. When called, the "parameter" value will
- * be passed to the routine.
- *
- * Reentrant: no
- * IRQ safe:  no
- *
- * @return IX_SUCCESS if the operation succeeded or IX_FAIL otherwise
- */
-PUBLIC IX_STATUS ixOsalIrqBind (UINT32 irqLevel,
-				IxOsalVoidFnVoidPtr irqHandler,
-				void *parameter);
-
-/** 
- * @ingroup IxOsal
- *
- * @brief Unbinds an interrupt handler from an interrupt level
- *
- * @param irqLevel (in)   - interrupt level
- *
- * Unbinds the selected interrupt level from any previously registered
- * handler 
- *
- * @li Reentrant: no
- * @li IRQ safe:  no
- *
- * @return IX_SUCCESS if the operation succeeded or IX_FAIL otherwise
- */
-PUBLIC IX_STATUS ixOsalIrqUnbind (UINT32 irqLevel);
-
-
-/** 
- * @ingroup IxOsal
- *
- * @brief Disables all interrupts
- *
- * @param - none
- *
- * Disables all the interrupts and prevents tasks scheduling 
- *
- * @li Reentrant: no
- * @li IRQ safe:  yes
- *
- * @return interrupt enable status prior to locking
- */
-PUBLIC UINT32 ixOsalIrqLock (void);
-
-/** 
- * @ingroup IxOsal
- *
- * @brief Enables all interrupts
- *
- * @param irqEnable (in) - interrupt enable status, prior to interrupt
- *                         locking 
- *
- * Enables the interrupts and task scheduling, cancelling the effect
- * of ixOsalIrqLock() 
- *
- * @li Reentrant: no
- * @li IRQ safe:  yes
- *
- * @return IX_SUCCESS if the operation succeeded or IX_FAIL otherwise
- */
-PUBLIC void ixOsalIrqUnlock (UINT32 irqEnable);
-
-/** 
- * @ingroup IxOsal
- *
- * @brief Selectively disables interrupts
- *
- * @param irqLevel ­ new interrupt level
- *
- * Disables the interrupts below the specified interrupt level 
- * 
- * @li Reentrant: no
- * @li IRQ safe:  yes
- *
- * @note Depending on the implementation this function can disable all
- *       the interrupts 
- *
- * @return previous interrupt level
- */
-PUBLIC UINT32 ixOsalIrqLevelSet (UINT32 irqLevel);
-
-/** 
- * @ingroup IxOsal
- *
- * @brief Enables an interrupt level
- *
- * @param irqLevel ­ interrupt level to enable
- *
- * Enables the specified interrupt level
- *
- * @li Reentrant: no
- * @li IRQ safe:  yes
- *
- * @return - none
- */
-PUBLIC void ixOsalIrqEnable (UINT32 irqLevel);
-
-/** 
- * @ingroup IxOsal
- *
- * @brief Disables an interrupt level
- *
- * @param irqLevel ­ interrupt level to disable
- *
- * Disables the specified interrupt level
- *
- * @li Reentrant: no
- * @li IRQ safe:  yes
- *
- * @return - none
- */
-PUBLIC void ixOsalIrqDisable (UINT32 irqLevel);
-
-
-/* =============================  Memory  =================================
- * 
- */
-
-/** 
- * @ingroup IxOsal
- *
- * @brief Allocates memory
- *
- * @param size - memory size to allocate, in bytes
- *
- * Allocates a memory zone of a given size
- *
- * @li Reentrant: no
- * @li IRQ safe:  no
- *
- * @return Pointer to the allocated zone or NULL if the allocation failed
- */
-PUBLIC void *ixOsalMemAlloc (UINT32 size);
-
-/** 
- * @ingroup IxOsal
- *
- * @brief Frees memory
- *
- * @param ptr - pointer to the memory zone
- *
- * Frees a previously allocated memory zone
- *
- * @li Reentrant: no
- * @li IRQ safe:  no
- *
- * @return - none
- */
-PUBLIC void ixOsalMemFree (void *ptr);
-
-/** 
- * @ingroup IxOsal
- *
- * @brief Copies memory zones
- *
- * @param dest  - destination memory zone
- * @param src   - source memory zone
- * @param count - number of bytes to copy
- *
- * Copies count bytes from the source memory zone pointed by src into the
- * memory zone pointed by dest.
- *
- * @li Reentrant: no
- * @li IRQ safe:  yes
- *
- * @return Pointer to the destination memory zone
- */
-PUBLIC void *ixOsalMemCopy (void *dest, void *src, UINT32 count);
-
-/** 
- * @ingroup IxOsal
- *
- * @brief Fills a memory zone
- *
- * @param ptr - pointer to the memory zone
- * @param filler - byte to fill the memory zone with
- * @param count - number of bytes to fill
- *
- * Fills a memory zone with a given constant byte
- *
- * @li Reentrant: no
- * @li IRQ safe:  yes
- *
- * @return Pointer to the memory zone
- */
-PUBLIC void *ixOsalMemSet (void *ptr, UINT8 filler, UINT32 count);
-
-/** 
- * @ingroup IxOsal
- *
- * @brief Allocates cache-safe memory
- *
- * @param size - size, in bytes, of the allocated zone
- *
- * Allocates a cache-safe memory zone of at least "size" bytes and returns
- * the pointer to the memory zone. This memory zone, depending on the
- * platform, is either uncached or aligned on a cache line boundary to make
- * the CACHE_FLUSH and CACHE_INVALIDATE macros safe to use. The memory
- * allocated with this function MUST be freed with ixOsalCacheDmaFree(),
- * otherwise memory corruption can occur.
- *
- * @li Reentrant: no
- * @li IRQ safe:  no
- *
- * @return Pointer to the memory zone or NULL if allocation failed
- *
- * @note It is important to note that cache coherence is maintained in
- * software by using the IX_OSAL_CACHE_FLUSH and IX_OSAL_CACHE_INVALIDATE
- * macros to maintain consistency between cache and external memory.
- */
-PUBLIC void *ixOsalCacheDmaMalloc (UINT32 size);
-
-/* Macros for ixOsalCacheDmaMalloc*/
-#define IX_OSAL_CACHE_DMA_MALLOC(size) ixOsalCacheDmaMalloc(size)
-
-/** 
- * @ingroup IxOsal
- *
- * @brief Frees cache-safe memory
- *
- * @param ptr   - pointer to the memory zone
- *
- * Frees a memory zone previously allocated with ixOsalCacheDmaMalloc()
- *
- * @li Reentrant: no
- * @li IRQ safe:  no
- *
- * @return - none
- */
-PUBLIC void ixOsalCacheDmaFree (void *ptr);
-
-#define IX_OSAL_CACHE_DMA_FREE(ptr)		ixOsalCacheDmaFree(ptr)
-
-/** 
- * @ingroup IxOsal
- *
- * @brief physical to virtual address translation
- *
- * @param physAddr - physical address
- *
- * Converts a physical address into its equivalent MMU-mapped virtual address
- *
- * @li Reentrant: no
- * @li IRQ safe:  yes
- *
- * @return Corresponding virtual address, as UINT32
- */
-#define IX_OSAL_MMU_PHYS_TO_VIRT(physAddr) \
-    IX_OSAL_OS_MMU_PHYS_TO_VIRT(physAddr)
-
-
-/** 
- * @ingroup IxOsal
- *
- * @brief virtual to physical address translation
- *
- * @param virtAddr - virtual address
- *
- * Converts a virtual address into its equivalent MMU-mapped physical address
- *
- * @li Reentrant: no
- * @li IRQ safe:  yes
- *
- * @return Corresponding physical address, as UINT32
- */
-#define IX_OSAL_MMU_VIRT_TO_PHYS(virtAddr)  \
-    IX_OSAL_OS_MMU_VIRT_TO_PHYS(virtAddr)
-
-
-
-/** 
- * @ingroup IxOsal
- *
- * @brief cache to memory flush
- *
- * @param addr - memory address to flush from cache
- * @param size - number of bytes to flush (rounded up to a cache line)
- *
- * Flushes the cached value of the memory zone pointed by "addr" into memory,
- * rounding up to a cache line. Use before the zone is to be read by a
- * processing unit which is not cache coherent with the main CPU.
- *
- * @li Reentrant: no
- * @li IRQ safe:  yes
- *
- * @return - none
- */
-#define IX_OSAL_CACHE_FLUSH(addr, size)  IX_OSAL_OS_CACHE_FLUSH(addr, size)
-
-
-
-/** 
- * @ingroup IxOsal
- *
- * @brief cache line invalidate
- *
- * @param addr - memory address to invalidate in cache
- * @param size - number of bytes to invalidate (rounded up to a cache line)
- *
- * Invalidates the cached value of the memory zone pointed by "addr",
- * rounding up to a cache line. Use before reading the zone from the main
- * CPU, if the zone has been updated by a processing unit which is not cache
- * coherent with the main CPU.
- *
- * @li Reentrant: no
- * @li IRQ safe:  yes
- *
- * @return - none
- */
-#define IX_OSAL_CACHE_INVALIDATE(addr, size)  IX_OSAL_OS_CACHE_INVALIDATE(addr, size)
-
-
-/* =============================  Threads  =================================
- * 
- */
-
-/** 
- * @ingroup IxOsal
- *
- * @brief Creates a new thread
- *
- * @param thread - handle of the thread to be created
- * @param threadAttr - pointer to a thread attribute object
- * @param startRoutine - thread entry point
- * @param arg - argument given to the thread
- *
- * Creates a thread given a thread handle and a thread attribute object. The
- * same thread attribute object can be used to create separate threads. "NULL"
- * can be specified as the attribute, in which case the default values will
- * be used. The thread needs to be explicitly started using ixOsalThreadStart().
- *
- * @li Reentrant: no
- * @li IRQ safe:  no
- *
- * @return - IX_SUCCESS/IX_FAIL
- */
-PUBLIC IX_STATUS ixOsalThreadCreate (IxOsalThread * thread,
-				     IxOsalThreadAttr * threadAttr,
-				     IxOsalVoidFnVoidPtr startRoutine,
-				     void *arg);
-
-/** 
- * @ingroup IxOsal
- *
- * @brief Starts a newly created thread
- *
- * @param thread - handle of the thread to be started
- *
- * Starts a thread given its thread handle. This function is to be called
- * only once, following the thread initialization.
- *
- * @li Reentrant: no
- * @li IRQ safe:  no
- *
- * @return - IX_SUCCESS/IX_FAIL
- */
-PUBLIC IX_STATUS ixOsalThreadStart (IxOsalThread * thread);
-
-/** 
- * @ingroup IxOsal
- *
- * @brief Kills an existing thread
- *
- * @param thread - handle of the thread to be killed
- *
- * Kills a thread given its thread handle.
- *
- * @li Reentrant: no
- * @li IRQ safe:  no
- *
- * @note It is not possible to kill threads in Linux kernel mode. This 
- * function will only send a SIGTERM signal, and it is the responsibility
- * of the thread to check for the presence of this signal with
- * signal_pending().
- *
- * @return -  IX_SUCCESS/IX_FAIL
- */
-PUBLIC IX_STATUS ixOsalThreadKill (IxOsalThread * thread);
-
-/** 
- * @ingroup IxOsal
- *
- * @brief Exits a running thread
- *
- * Terminates the calling thread
- *
- * @li Reentrant: no
- * @li IRQ safe:  no
- *
- * @return - This function never returns
- */
-PUBLIC void ixOsalThreadExit (void);
-
-/** 
- * @ingroup IxOsal
- *
- * @brief Sets the priority of an existing thread
- *
- * @param thread - handle of the thread
- * @param priority - new priority, between 0 and 255 (0 being the highest)
- *
- * Sets the thread priority
- *
- * @li Reentrant: no
- * @li IRQ safe:  no
- *
- * @return - IX_SUCCESS/IX_FAIL
- */
-PUBLIC IX_STATUS ixOsalThreadPrioritySet (IxOsalThread * thread,
-					  UINT32 priority);
-
-/** 
- * @ingroup IxOsal
- *
- * @brief Suspends thread execution
- *
- * @param thread - handle of the thread
- *
- * Suspends the thread execution
- *
- * @li Reentrant: no
- * @li IRQ safe:  no
- *
- * @return - IX_SUCCESS/IX_FAIL
- */
-PUBLIC IX_STATUS ixOsalThreadSuspend (IxOsalThread * thread);
-
-/** 
- * @ingroup IxOsal
- *
- * @brief Resumes thread execution
- *
- * @param thread - handle of the thread
- *
- * Resumes the thread execution
- *
- * @li Reentrant: no
- * @li IRQ safe:  no
- *
- * @return - IX_SUCCESS/IX_FAIL
- */
-PUBLIC IX_STATUS ixOsalThreadResume (IxOsalThread * thread);
-
-
-/* =======================  Message Queues (IPC) ==========================
- * 
- */
-
-/** 
- * @ingroup IxOsal
- *
- * @brief Creates a message queue
- *
- * @param queue - queue handle
- * @param msgCount - maximum number of messages to hold in the queue
- * @param msgLen - maximum length of each message, in bytes
- *
- * Creates a message queue of msgCount messages, each containing msgLen bytes
- *
- * @li Reentrant: no
- * @li IRQ safe:  no
- *
- * @return - IX_SUCCESS/IX_FAIL
- */
-PUBLIC IX_STATUS ixOsalMessageQueueCreate (IxOsalMessageQueue * queue,
-					   UINT32 msgCount, UINT32 msgLen);
-
-/** 
- * @ingroup IxOsal
- *
- * @brief Deletes a message queue
- *
- * @param queue - queue handle
- *
- * Deletes a message queue
- *
- * @li Reentrant: no
- * @li IRQ safe:  no
- *
- * @return - IX_SUCCESS/IX_FAIL
- */
-PUBLIC IX_STATUS ixOsalMessageQueueDelete (IxOsalMessageQueue * queue);
-
-/** 
- * @ingroup IxOsal
- *
- * @brief Sends a message to a message queue
- *
- * @param queue - queue handle
- * @param message - message to send
- *
- * Sends a message to the message queue. The message will be copied (at the
- * configured size of the message) into the queue.
- *
- * @li Reentrant: yes
- * @li IRQ safe:  yes
- *
- * @return - IX_SUCCESS/IX_FAIL
- */
-PUBLIC IX_STATUS ixOsalMessageQueueSend (IxOsalMessageQueue * queue,
-					 UINT8 * message);
-
-/** 
- * @ingroup IxOsal
- *
- * @brief Receives a message from a message queue
- *
- * @param queue - queue handle
- * @param message - pointer to where the message should be copied to
- *
- * Retrieves the first message from the message queue
- *
- * @li Reentrant: yes
- * @li IRQ safe:  yes
- *
- * @return - IX_SUCCESS/IX_FAIL
- */
-PUBLIC IX_STATUS ixOsalMessageQueueReceive (IxOsalMessageQueue * queue,
-					    UINT8 * message);
-
-
-/* =======================  Thread Synchronisation ========================
- * 
- */
-
-/** 
- * @ingroup IxOsal
- *
- * @brief initializes a mutex
- *
- * @param mutex - mutex handle
- *
- * Initializes a mutex object
- *
- * @li Reentrant: no
- * @li IRQ safe:  no
- *
- * @return - IX_SUCCESS/IX_FAIL
- */
-PUBLIC IX_STATUS ixOsalMutexInit (IxOsalMutex * mutex);
-
-/** 
- * @ingroup IxOsal
- *
- * @brief locks a mutex
- *
- * @param mutex - mutex handle
- * @param timeout - timeout in ms; IX_OSAL_WAIT_FOREVER (-1) to wait forever
- *                  or IX_OSAL_WAIT_NONE to return immediately
- *
- * Locks a mutex object
- *
- * @li Reentrant: yes
- * @li IRQ safe:  no
- *
- * @return - IX_SUCCESS/IX_FAIL
- */
-PUBLIC IX_STATUS ixOsalMutexLock (IxOsalMutex * mutex, INT32 timeout);
-
-/** 
- * @ingroup IxOsal
- *
- * @brief Unlocks a mutex
- *
- * @param mutex - mutex handle
- *
- * Unlocks a mutex object
- *
- * @li Reentrant: yes
- * @li IRQ safe:  yes
- *
- * @return - IX_SUCCESS/IX_FAIL
- */
-PUBLIC IX_STATUS ixOsalMutexUnlock (IxOsalMutex * mutex);
-
-/** 
- * @ingroup IxOsal
- *
- * @brief Non-blocking attempt to lock a mutex
- *
- * @param mutex - mutex handle
- *
- * Attempts to lock a mutex object, returning immediately with IX_SUCCESS if
- * the lock was successful or IX_FAIL if the lock failed
- *
- * @li Reentrant: yes
- * @li IRQ safe:  no
- *
- * @return - IX_SUCCESS/IX_FAIL
- */
-PUBLIC IX_STATUS ixOsalMutexTryLock (IxOsalMutex * mutex);
-
-/** 
- * @ingroup IxOsal
- *
- * @brief Destroys a mutex object
- *
- * @param mutex - mutex handle
- * @param
- *
- * Destroys a mutex object; the caller should ensure that no thread is
- * blocked on this mutex
- *
- * @li Reentrant: no
- * @li IRQ safe:  no
- *
- * @return - IX_SUCCESS/IX_FAIL
- */
-PUBLIC IX_STATUS ixOsalMutexDestroy (IxOsalMutex * mutex);
-
-/** 
- * @ingroup IxOsal
- *
- * @brief Initializes a fast mutex
- *
- * @param mutex - fast mutex handle
- *
- * Initializes a fast mutex object
- *
- * @li Reentrant: yes
- * @li IRQ safe:  yes
- *
- * @return - IX_SUCCESS/IX_FAIL
- */
-PUBLIC IX_STATUS ixOsalFastMutexInit (IxOsalFastMutex * mutex);
-
-/** 
- * @ingroup IxOsal
- *
- * @brief Non-blocking attempt to lock a fast mutex
- *
- * @param mutex - fast mutex handle
- *
- * Attempts to lock a fast mutex object, returning immediately with
- * IX_SUCCESS if the lock was successful or IX_FAIL if the lock failed
- *
- * @li Reentrant: yes
- * @li IRQ safe:  yes
- *
- * @return - IX_SUCCESS/IX_FAIL
- */
-PUBLIC IX_STATUS ixOsalFastMutexTryLock (IxOsalFastMutex * mutex);
-
-/** 
- * @ingroup IxOsal
- *
- * @brief Unlocks a fast mutex
- *
- * @param mutex - fast mutex handle
- *
- * Unlocks a fast mutex object
- *
- * @li Reentrant: yes
- * @li IRQ safe:  yes
- *
- * @return - IX_SUCCESS/IX_FAIL
- */
-PUBLIC IX_STATUS ixOsalFastMutexUnlock (IxOsalFastMutex * mutex);
-
-/** 
- * @ingroup IxOsal
- *
- * @brief Destroys a fast mutex object
- *
- * @param mutex - fast mutex handle
- *
- * Destroys a fast mutex object
- *
- * @li Reentrant: yes
- * @li IRQ safe:  yes
- *
- * @return - IX_SUCCESS/IX_FAIL
- */
-PUBLIC IX_STATUS ixOsalFastMutexDestroy (IxOsalFastMutex * mutex);
-
-/** 
- * @ingroup IxOsal
- *
- * @brief Initializes a semaphore
- *
- * @param semaphore - semaphore handle
- * @param value - initial semaphore value
- *
- * Initializes a semaphore object
- *
- * @li Reentrant: no
- * @li IRQ safe:  no
- *
- * @return - IX_SUCCESS/IX_FAIL
- */
-PUBLIC IX_STATUS ixOsalSemaphoreInit (IxOsalSemaphore * semaphore,
-				      UINT32 value);
-
-/** 
- * @ingroup IxOsal
- *
- * @brief Posts to (increments) a semaphore
- *
- * @param semaphore - semaphore handle
- *
- * Increments a semaphore object
- *
- * @li Reentrant: no
- * @li IRQ safe:  yes
- *
- * @return - IX_SUCCESS/IX_FAIL
- */
-PUBLIC IX_STATUS ixOsalSemaphorePost (IxOsalSemaphore * semaphore);
-
-/** 
- * @ingroup IxOsal
- *
- * @brief Waits on (decrements) a semaphore
- *
- * @param semaphore - semaphore handle
- * @param timeout - timeout, in ms; IX_OSAL_WAIT_FOREVER (-1) if the thread
- * is to block indefinitely or IX_OSAL_WAIT_NONE (0) if the thread is to
- * return immediately even if the call fails
- *
- * Decrements a semaphore, blocking if the semaphore is
- * unavailable (value is 0).
- *
- * @li Reentrant: no
- * @li IRQ safe:  no
- *
- * @return - IX_SUCCESS/IX_FAIL
- */
-PUBLIC IX_STATUS ixOsalSemaphoreWait (IxOsalSemaphore * semaphore,
-				      INT32 timeout);
-
-/** 
- * @ingroup IxOsal
- *
- * @brief Non-blocking wait on semaphore
- *
- * @param semaphore - semaphore handle
- *
- * Decrements a semaphore, not blocking the calling thread if the semaphore
- * is unavailable
- *
- * @li Reentrant: no
- * @li IRQ safe:  no
- *
- * @return - IX_SUCCESS/IX_FAIL
- */
-PUBLIC IX_STATUS ixOsalSemaphoreTryWait (IxOsalSemaphore * semaphore);
-
-/** 
- * @ingroup IxOsal
- *
- * @brief Gets semaphore value
- *
- * @param semaphore - semaphore handle
- * @param value - location to store the semaphore value
- *
- * Retrieves the current value of a semaphore object
- *
- * @li Reentrant: no
- * @li IRQ safe:  no
- *
- * @return - IX_SUCCESS/IX_FAIL
- */
-PUBLIC IX_STATUS ixOsalSemaphoreGetValue (IxOsalSemaphore * semaphore,
-					  UINT32 * value);
-
-/** 
- * @ingroup IxOsal
- *
- * @brief Destroys a semaphore object
- *
- * @param semaphore - semaphore handle
- *
- * Destroys a semaphore object; the caller should ensure that no thread is
- * blocked on this semaphore
- *
- * @li Reentrant: no
- * @li IRQ safe:  no
- *
- * @return - IX_SUCCESS/IX_FAIL
- */
-PUBLIC IX_STATUS ixOsalSemaphoreDestroy (IxOsalSemaphore * semaphore);
-
-/** 
- * @ingroup IxOsal
- *
- * @brief Yields execution of current thread
- *
- * Yields the execution of the current thread
- *
- * @li Reentrant: no
- * @li IRQ safe:  no
- *
- * @return - none
- */
-PUBLIC void ixOsalYield (void);
-
-
-/* ========================== Time functions  ===========================
- * 
- */
-
-/** 
- * @ingroup IxOsal
- *
- * @brief Yielding sleep for a number of milliseconds
- *
- * @param milliseconds - number of milliseconds to sleep
- *
- * The calling thread will sleep for the specified number of milliseconds.
- * This sleep is yielding, hence other tasks will be scheduled by the
- * operating system during the sleep period. Calling this function with an
- * argument of 0 will place the thread at the end of the current scheduling
- * loop.
- *
- * @li Reentrant: no
- * @li IRQ safe:  no
- *
- * @return - none
- */
-PUBLIC void ixOsalSleep (UINT32 milliseconds);
-
-/** 
- * @ingroup IxOsal
- *
- * @brief Busy sleep for a number of microseconds
- *
- * @param microseconds - number of microseconds to sleep
- *
- * Sleeps for the specified number of microseconds, without explicitly
- * yielding thread execution to the OS scheduler
- *
- * @li Reentrant: yes
- * @li IRQ safe:  yes
- *
- * @return - none
- */
-PUBLIC void ixOsalBusySleep (UINT32 microseconds);
-
-/** 
- * @ingroup IxOsal
- *
- * @brief XXX
- *
- * Retrieves the current timestamp
- *
- * @li Reentrant: yes
- * @li IRQ safe:  yes
- *
- * @return - The current timestamp
- *
- * @note The implementation of this function is platform-specific. Not
- * all the platforms provide a high-resolution timestamp counter.
- */
-PUBLIC UINT32 ixOsalTimestampGet (void);
-
-/** 
- * @ingroup IxOsal
- *
- * @brief Resolution of the timestamp counter
- *
- * Retrieves the resolution (frequency) of the timestamp counter.
- *
- * @li Reentrant: yes
- * @li IRQ safe:  yes
- *
- * @return - The resolution of the timestamp counter
- *
- * @note The implementation of this function is platform-specific. Not all
- * the platforms provide a high-resolution timestamp counter.
- */
-PUBLIC UINT32 ixOsalTimestampResolutionGet (void);
-
-/** 
- * @ingroup IxOsal
- *
- * @brief System clock rate, in ticks
- *
- * Retrieves the resolution (number of ticks per second) of the system clock
- *
- * @li Reentrant: no
- * @li IRQ safe:  no
- *
- * @return - The system clock rate
- *
- * @note The implementation of this function is platform and OS-specific.
- * The system clock rate is not always available - e.g. Linux does not
- * provide this information in user mode
- */
-PUBLIC UINT32 ixOsalSysClockRateGet (void);
-
-/** 
- * @ingroup IxOsal
- *
- * @brief Current system time
- *
- * @param tv - pointer to an IxOsalTimeval structure to store the current
- *             time in
- *
- * Retrieves the current system time (real-time)
- *
- * @li Reentrant: no
- * @li IRQ safe:  no
- *
- * @return - none
- *
- * @note The implementation of this function is platform-specific. Not all
- * platforms have a real-time clock.
- */
-PUBLIC void ixOsalTimeGet (IxOsalTimeval * tv);
-
-
-
-/* Internal function to convert timer val to ticks.
- * NOTE - This should not be called by the user.
- * Use the macro IX_OSAL_TIMEVAL_TO_TICKS 
- * OS-independent, implemented in framework.
- */
-PUBLIC UINT32 ixOsalTimevalToTicks (IxOsalTimeval tv);
-
-
-/** 
- * @ingroup IxOsal
- *
- * @brief Converts ixOsalTimeVal into ticks
- *
- * @param tv - an IxOsalTimeval structure
- *
- * Converts an IxOsalTimeval structure into OS ticks
- *
- * @li Reentrant: yes
- * @li IRQ safe:  yes
- *
- * @return - Corresponding number of ticks
- * 
- * Note: This function is OS-independent. Implemented by core.
- */
-#define IX_OSAL_TIMEVAL_TO_TICKS(tv)  ixOsalTimevalToTicks(tv)
-
-
-
-/* Internal function to convert ticks to timer val
- * NOTE - This should not be called by the user.
- * Use the macro IX_OSAL_TICKS_TO_TIMEVAL 
- */
-
-PUBLIC void ixOsalTicksToTimeval (UINT32 ticks, IxOsalTimeval * pTv);
-
-
-/** 
- * @ingroup IxOsal
- *
- * @brief Converts ticks into ixOsalTimeVal 
- *
- * @param ticks - number of ticks
- * @param pTv - pointer to the destination structure
- *
- * Converts the specified number of ticks into an IxOsalTimeval structure
- *
- * @li Reentrant: yes
- * @li IRQ safe:  yes
- *
- * @return - Corresponding IxOsalTimeval structure
- * Note: This function is OS-independent. Implemented by core.
- */
-#define IX_OSAL_TICKS_TO_TIMEVAL(ticks, pTv)  \
-    ixOsalTicksToTimeval(ticks, pTv)
-
-
-
-
-/** 
- * @ingroup IxOsal
- *
- * @brief Converts ixOsalTimeVal to milliseconds
- *
- * @param tv - IxOsalTimeval structure to convert
- *
- * Converts an IxOsalTimeval structure into milliseconds
- *
- * @li Reentrant: yes
- * @li IRQ safe:  yes
- *
- * @return - Corresponding number of milliseconds
- * Note: This function is OS-independent. Implemented by core.
- */
-#define IX_OSAL_TIMEVAL_TO_MS(tv)     ((tv.secs * 1000) + (tv.nsecs / 1000000))
-
-
-/** 
- * @ingroup IxOsal
- *
- * @brief Converts milliseconds to IxOsalTimeval
- *
- * @param milliseconds - number of milliseconds to convert
- * @param pTv - pointer to the destination structure
- *
- * Converts a millisecond value into an IxOsalTimeval structure
- *
- * @li Reentrant: yes
- * @li IRQ safe:  yes
- *
- * @return - Corresponding IxOsalTimeval structure
- * Note: This function is OS-independent. Implemented by core.
- */
-#define IX_OSAL_MS_TO_TIMEVAL(milliseconds, pTv)  \
-   	    ((IxOsalTimeval *) pTv)->secs = milliseconds / 1000;			  \
-        ((IxOsalTimeval *) pTv)->nsecs = (milliseconds % 1000) * 1000000
-
-
-/** 
- * @ingroup IxOsal
- *
- * @brief "equal" comparison for IxOsalTimeval
- *
- * @param tvA, tvB - IxOsalTimeval structures to compare
- *
- * Compares two IxOsalTimeval structures for equality
- *
- * @li Reentrant: yes
- * @li IRQ safe:  yes
- *
- * @return - TRUE if the structures are equal
- *         - FALSE otherwise
- * Note: This function is OS-independant
- */
-#define IX_OSAL_TIME_EQ(tvA, tvB)        \
-        ((tvA).secs == (tvB).secs && (tvA).nsecs == (tvB).nsecs)
-
-
-/** 
- * @ingroup IxOsal
- *
- * @brief "less than" comparison for IxOsalTimeval
- *
- * @param tvA, tvB - IxOsalTimeval structures to compare
- *
- * Compares two IxOsalTimeval structures to determine if the first one is
- * less than the second one
- *
- * @li Reentrant: yes
- * @li IRQ safe:  yes
- *
- * @return - TRUE if tvA < tvB
- *         - FALSE otherwise
- * Note: This function is OS-independent. Implemented by core.
- */
-#define IX_OSAL_TIME_LT(tvA,tvB) \
-        ((tvA).secs  < (tvB).secs ||	\
-        ((tvA).secs == (tvB).secs && (tvA).nsecs < (tvB).nsecs))
-
-
-/** 
- * @ingroup IxOsal
- *
- * @brief "greater than" comparison for IxOsalTimeval
- *
- * @param tvA, tvB - IxOsalTimeval structures to compare
- *
- * Compares two IxOsalTimeval structures to determine if the first one is
- * greater than the second one
- *
- * @li Reentrant: yes
- * @li IRQ safe:  yes
- *
- * @return - TRUE if tvA > tvB
- *         - FALSE  otherwise
- * Note: This function is OS-independent.
- */
-#define IX_OSAL_TIME_GT(tvA, tvB)  \
-        ((tvA).secs  > (tvB).secs ||	\
-        ((tvA).secs == (tvB).secs && (tvA).nsecs > (tvB).nsecs))
-
-
-/** 
- * @ingroup IxOsal
- *
- * @brief "add" operator for IxOsalTimeval
- *
- * @param tvA, tvB - IxOsalTimeval structures to add
- *
- * Adds the second IxOsalTimevalStruct to the first one (equivalent to
- * tvA += tvB)
- *
- * @li Reentrant: yes
- * @li IRQ safe:  yes
- *
- * @return - none
- * Note: This function is OS-independent.
- */
-#define IX_OSAL_TIME_ADD(tvA, tvB)  \
-        (tvA).secs += (tvB).secs;   \
-        (tvA).nsecs += (tvB).nsecs; \
-        if ((tvA).nsecs >= IX_OSAL_BILLION) \
-    	{ \
-        (tvA).secs++; \
-        (tvA).nsecs -= IX_OSAL_BILLION; }
-
-
-/** 
- * @ingroup IxOsal
- *
- * @brief "subtract" operator for IxOsalTimeval
- *
- * @param tvA, tvB - IxOsalTimeval structures to subtract
- *
- * Subtracts the second IxOsalTimevalStruct from the first one (equivalent
- * to tvA -= tvB)
- *
- * @li Reentrant: yes
- * @li IRQ safe:  yes
- *
- * @return - none
- * Note: This function is OS-independent. Implemented by core.
- */
-#define IX_OSAL_TIME_SUB(tvA, tvB)   \
-        if ((tvA).nsecs >= (tvB).nsecs) \
-        { \
-          (tvA).secs -= (tvB).secs; \
-          (tvA).nsecs -= (tvB).nsecs; \
-        } \
-        else \
-        { \
-          (tvA).secs -= ((tvB).secs + 1); \
-          (tvA).nsecs += IX_OSAL_BILLION - (tvB).nsecs; \
-        }
-
-
-/* ============================= Logging  ==============================
- * 
- */
-
-/** 
- * @ingroup IxOsal
- *
- * @brief Interrupt-safe logging function
- *
- * @param level - identifier prefix for the message
- * @param device - output device
- * @param format - message format, in a printf format
- * @param ... - up to 6 arguments to be printed
- *
- * IRQ-safe logging function, similar to printf. Accepts up to 6 arguments
- * to print (excluding the level, device and the format). This function will
- * actually display the message only if the level is lower than the current
- * verbosity level or if the IX_OSAL_LOG_USER level is used. An output device
- * must be specified (see IxOsalTypes.h).
- *
- * @li Reentrant: yes
- * @li IRQ safe:  yes
- *
- * @return - Beside the exceptions documented in the note below, the returned
- * value is the number of printed characters, or -1 if the parameters are
- * incorrect (NULL format, unknown output device)
- *
- * @note The exceptions to the return value are:
- * VxWorks: The return value is 32 if the specified level is 1 and 64
- * if the specified level is greater than 1 and less or equal than 9.
- * WinCE: If compiled for EBOOT then the return value is always 0.
- *
- * @note The given print format should take into account the specified 
- * output device. IX_OSAL_STDOUT supports all the usual print formats,
- * however a custom hex display specified by IX_OSAL_HEX would support
- * only a fixed number of hexadecimal digits.
- */
-PUBLIC INT32 ixOsalLog (IxOsalLogLevel level,
-			IxOsalLogDevice device,
-			char *format,
-			int arg1,
-			int arg2, int arg3, int arg4, int arg5, int arg6);
-
-/** 
- * @ingroup IxOsal
- *
- * @brief sets the current logging verbosity level
- *
- * @param level - new log verbosity level
- *
- * Sets the log verbosity level. The default value is IX_OSAL_LOG_ERROR.
- *
- * @li Reentrant: yes
- * @li IRQ safe:  yes
- *
- * @return - Old log verbosity level
- */
-PUBLIC UINT32 ixOsalLogLevelSet (UINT32 level);
-
-
-/* ============================= Logging  ==============================
- * 
- */
-
-/** 
- * @ingroup IxOsal
- *
- * @brief Schedules a repeating timer
- *
- * @param timer - handle of the timer object
- * @param period - timer trigger period, in milliseconds
- * @param priority - timer priority (0 being the highest)
- * @param callback - user callback to invoke when the timer triggers
- * @param param - custom parameter passed to the callback
- *
- * Schedules a timer to be called every period milliseconds. The timer
- * will invoke the specified callback function possibly in interrupt
- * context, passing the given parameter. If several timers trigger at the
- * same time contention issues are dealt according to the specified timer
- * priorities.
- *
- * @li Reentrant: no
- * @li IRQ safe:  no
- *
- * @return - IX_SUCCESS/IX_FAIL
- */
-PUBLIC IX_STATUS ixOsalRepeatingTimerSchedule (IxOsalTimer * timer,
-					       UINT32 period,
-					       UINT32 priority,
-					       IxOsalVoidFnVoidPtr callback,
-					       void *param);
-
-/** 
- * @ingroup IxOsal
- *
- * @brief Schedules a single-shot timer
- *
- * @param timer - handle of the timer object
- * @param period - timer trigger period, in milliseconds
- * @param priority - timer priority (0 being the highest)
- * @param callback - user callback to invoke when the timer triggers
- * @param param - custom parameter passed to the callback
- *
- * Schedules a timer to be called after period milliseconds. The timer
- * will cease to function past its first trigger. The timer will invoke
- * the specified callback function, possibly in interrupt context, passing
- * the given parameter. If several timers trigger at the same time contention
- * issues are dealt according to the specified timer priorities.
- *
- * @li Reentrant: no
- * @li IRQ safe:  no
- *
- * @return - IX_SUCCESS/IX_FAIL
- */
-PUBLIC IX_STATUS
-ixOsalSingleShotTimerSchedule (IxOsalTimer * timer,
-			       UINT32 period,
-			       UINT32 priority,
-			       IxOsalVoidFnVoidPtr callback, void *param);
-
-/** 
- * @ingroup IxOsal
- *
- * @brief Cancels a running timer
- *
- * @param timer - handle of the timer object
- *
- * Cancels a single-shot or repeating timer.
- *
- * @li Reentrant: no
- * @li IRQ safe:  yes
- *
- * @return - IX_SUCCESS/IX_FAIL
- */
-PUBLIC IX_STATUS ixOsalTimerCancel (IxOsalTimer * timer);
-
-/** 
- * @ingroup IxOsal
- *
- * @brief displays all the running timers
- *
- * Displays a list with all the running timers and their parameters (handle,
- * period, type, priority, callback and user parameter)
- *
- * @li Reentrant: no
- * @li IRQ safe:  no
- *
- * @return - none
- */
-PUBLIC void ixOsalTimersShow (void);
-
-
-/* ============================= Version  ==============================
- * 
- */
-
-/**
- * @ingroup IxOsal
- *
- * @brief provides the name of the Operating System running
- *
- * @param osName - Pointer to a NULL-terminated string of characters
- * that holds the name of the OS running.
- * This is both an input and an ouput parameter
- * @param maxSize - Input parameter that defines the maximum number of
- * bytes that can be stored in osName
- *
- * Returns a string of characters that describe the Operating System name
- *
- * @li Reentrant: yes
- * @li IRQ safe:  yes
- *
- * return - IX_SUCCESS for successful retrieval
- *        - IX_FAIL if (osType == NULL | maxSize =< 0)
- */
-PUBLIC IX_STATUS ixOsalOsNameGet (INT8* osName, INT32 maxSize);
-
-/**
- * @ingroup IxOsal
- *
- * @brief provides the version of the Operating System running
- *
- * @param osVersion - Pointer to a NULL terminated string of characters
- * that holds the version of the OS running.
- * This is both an input and an ouput parameter
- * @param maxSize - Input parameter that defines the maximum number of
- * bytes that can be stored in osVersion
- *
- * Returns a string of characters that describe the Operating System's version
- *
- * @li Reentrant: yes
- * @li IRQ safe:  yes
- *
- * return - IX_SUCCESS for successful retrieval
- *        - IX_FAIL if (osVersion == NULL | maxSize =< 0)
- */
-PUBLIC IX_STATUS ixOsalOsVersionGet(INT8* osVersion, INT32 maxSize);
-
-
-
-/**
- * @} IxOsal
- */
-
-#endif /* IxOsal_H */
diff --git a/arch/arm/cpu/ixp/npe/include/IxOsalAssert.h b/arch/arm/cpu/ixp/npe/include/IxOsalAssert.h
deleted file mode 100644
index 04a4f51..0000000
--- a/arch/arm/cpu/ixp/npe/include/IxOsalAssert.h
+++ /dev/null
@@ -1,81 +0,0 @@
-/*
- * @file        IxOsalAssert.h 
- * @author	Intel Corporation
- * @date        25-08-2004
- *
- * @brief       description goes here
- *
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- * 
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- * 
- * @par
- * -- End of Copyright Notice --
- */
-
-#ifndef IX_OSAL_ASSERT_H
-#define IX_OSAL_ASSERT_H
-
-/*
- * Put the system defined include files required
- * @par
- * <TAGGED>
- */
-
-#include "IxOsalOsAssert.h"
-
-/**
- * @brief Assert macro, assert the condition is true. This
- *        will not be compiled out.
- *        N.B. will result in a system crash if it is false.
- */
-#define IX_OSAL_ASSERT(c) IX_OSAL_OS_ASSERT(c)
-
-
-/**
- * @brief Ensure macro, ensure the condition is true.
- *        This will be conditionally compiled out and
- *        may be used for test purposes.
- */
-#ifdef IX_OSAL_ENSURE_ON
-#define IX_OSAL_ENSURE(c, str) do { \
-if (!(c)) ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, str, \
-0, 0, 0, 0, 0, 0); } while (0)
-
-#else
-#define IX_OSAL_ENSURE(c, str)
-#endif
-
-
-#endif /* IX_OSAL_ASSERT_H */
diff --git a/arch/arm/cpu/ixp/npe/include/IxOsalBackward.h b/arch/arm/cpu/ixp/npe/include/IxOsalBackward.h
deleted file mode 100644
index ea9f307..0000000
--- a/arch/arm/cpu/ixp/npe/include/IxOsalBackward.h
+++ /dev/null
@@ -1,65 +0,0 @@
-/** 
- * This file is intended to provide backward 
- * compatibility for main osService/OSSL 
- * APIs. 
- *
- * It shall be phased out gradually and users
- * are strongly recommended to use IX_OSAL API.
- *
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- * 
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- * 
- * @par
- * -- End of Copyright Notice --
- */
-
-#ifndef IX_OSAL_BACKWARD_H
-#define IX_OSAL_BACKWARD_H
-
-#include "IxOsal.h"
-
-#include "IxOsalBackwardCacheMMU.h"
-
-#include "IxOsalBackwardOsServices.h"
-
-#include "IxOsalBackwardMemMap.h"
-
-#include "IxOsalBackwardBufferMgt.h"
-
-#include "IxOsalBackwardOssl.h"
-
-#include "IxOsalBackwardAssert.h"
-
-#endif /* IX_OSAL_BACKWARD_H */
diff --git a/arch/arm/cpu/ixp/npe/include/IxOsalBackwardAssert.h b/arch/arm/cpu/ixp/npe/include/IxOsalBackwardAssert.h
deleted file mode 100644
index be1e272..0000000
--- a/arch/arm/cpu/ixp/npe/include/IxOsalBackwardAssert.h
+++ /dev/null
@@ -1,54 +0,0 @@
-/** 
- * This file is intended to provide backward 
- * compatibility for main osService/OSSL 
- * APIs. 
- *
- * It shall be phased out gradually and users
- * are strongly recommended to use IX_OSAL API.
- *
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- * 
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- * 
- * @par
- * -- End of Copyright Notice --
- */
-
-#ifndef IX_OSAL_BACKWARD_ASSERT_H
-#define IX_OSAL_BACKWARD_ASSERT_H
-
-#define IX_ENSURE(c, str)	IX_OSAL_ENSURE(c, str)
-#define IX_ASSERT(c)		IX_OSAL_ASSERT(c)
-
-#endif /* IX_OSAL_BACKWARD_ASSERT_H */
diff --git a/arch/arm/cpu/ixp/npe/include/IxOsalBackwardBufferMgt.h b/arch/arm/cpu/ixp/npe/include/IxOsalBackwardBufferMgt.h
deleted file mode 100644
index 4cf80d3..0000000
--- a/arch/arm/cpu/ixp/npe/include/IxOsalBackwardBufferMgt.h
+++ /dev/null
@@ -1,159 +0,0 @@
-/** 
- * This file is intended to provide backward 
- * compatibility for main osService/OSSL 
- * APIs. 
- *
- * It shall be phased out gradually and users
- * are strongly recommended to use IX_OSAL API.
- *
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- * 
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- * 
- * @par
- * -- End of Copyright Notice --
- */
-
-#ifndef IX_OSAL_BACKWARD_BUFFER_MGT_H
-#define IX_OSAL_BACKWARD_BUFFER_MGT_H
-
-typedef IX_OSAL_MBUF IX_MBUF;
-
-typedef IX_OSAL_MBUF_POOL IX_MBUF_POOL;
-
-
-#define IX_MBUF_NEXT_BUFFER_IN_PKT_PTR(m_blk_ptr)  \
-		IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR(m_blk_ptr)
-
-
-#define IX_MBUF_NEXT_PKT_IN_CHAIN_PTR(m_blk_ptr)  \
-		IX_OSAL_MBUF_NEXT_PKT_IN_CHAIN_PTR(m_blk_ptr)
-
-
-#define IX_MBUF_MDATA(m_blk_ptr)  \
-		IX_OSAL_MBUF_MDATA(m_blk_ptr)
-
-
-#define IX_MBUF_MLEN(m_blk_ptr) \
-		IX_OSAL_MBUF_MLEN(m_blk_ptr)
-
-
-#define IX_MBUF_TYPE(m_blk_ptr) \
-		IX_OSAL_MBUF_MTYPE(m_blk_ptr)
-
-/* Same as IX_MBUF_TYPE */
-#define IX_MBUF_MTYPE(m_blk_ptr) \
-                IX_OSAL_MBUF_MTYPE(m_blk_ptr)
-
-#define IX_MBUF_FLAGS(m_blk_ptr)	\
-		IX_OSAL_MBUF_FLAGS(m_blk_ptr)
-
-
-#define IX_MBUF_NET_POOL(m_blk_ptr)	\
-		IX_OSAL_MBUF_NET_POOL(m_blk_ptr)
-
-
-#define IX_MBUF_PKT_LEN(m_blk_ptr)	\
-		IX_OSAL_MBUF_PKT_LEN(m_blk_ptr)
-
-
-#define IX_MBUF_PRIV(m_blk_ptr)		\
-		IX_OSAL_MBUF_PRIV(m_blk_ptr)
-
-
-#define IX_MBUF_ALLOCATED_BUFF_LEN(m_blk_ptr)  \
-		IX_OSAL_MBUF_ALLOCATED_BUFF_LEN(m_blk_ptr)
-
-
-#define IX_MBUF_ALLOCATED_BUFF_DATA(m_blk_ptr)  \
-		IX_OSAL_MBUF_ALLOCATED_BUFF_DATA(m_blk_ptr)
-
-
-#define IX_MBUF_POOL_SIZE_ALIGN(size)   \
-		IX_OSAL_MBUF_POOL_SIZE_ALIGN(size)
-
-
-#define IX_MBUF_POOL_MBUF_AREA_SIZE_ALIGNED(count)	\
-		IX_OSAL_MBUF_POOL_MBUF_AREA_SIZE_ALIGNED(count)
-
-
-#define IX_MBUF_POOL_DATA_AREA_SIZE_ALIGNED(count, size) \
-		IX_OSAL_MBUF_POOL_DATA_AREA_SIZE_ALIGNED(count, size)
-
-
-#define IX_MBUF_POOL_MBUF_AREA_ALLOC(count, memAreaSize) \
-		IX_OSAL_MBUF_POOL_MBUF_AREA_ALLOC(count, memAreaSize)
-
-
-#define IX_MBUF_POOL_DATA_AREA_ALLOC(count, size, memAreaSize) \
-		IX_OSAL_MBUF_POOL_DATA_AREA_ALLOC(count, size, memAreaSize)
-
-IX_STATUS
-ixOsalOsIxp400BackwardPoolInit (IX_OSAL_MBUF_POOL ** poolPtrPtr,
-				UINT32 count, UINT32 size, const char *name);
-
-
-/* This one needs extra steps*/
-#define IX_MBUF_POOL_INIT(poolPtr, count, size, name) \
-		ixOsalOsIxp400BackwardPoolInit( poolPtr, count,  size, name)
-
-
-#define IX_MBUF_POOL_INIT_NO_ALLOC(poolPtrPtr, bufPtr, dataPtr, count, size, name) \
-		(*poolPtrPtr = IX_OSAL_MBUF_NO_ALLOC_POOL_INIT(bufPtr, dataPtr, count, size, name))
-
-
-IX_STATUS
-ixOsalOsIxp400BackwardMbufPoolGet (IX_OSAL_MBUF_POOL * poolPtr,
-				   IX_OSAL_MBUF ** newBufPtrPtr);
-
-#define IX_MBUF_POOL_GET(poolPtr, bufPtrPtr) \
-		ixOsalOsIxp400BackwardMbufPoolGet(poolPtr, bufPtrPtr)
-
-
-#define IX_MBUF_POOL_PUT(bufPtr) \
-		IX_OSAL_MBUF_POOL_PUT(bufPtr)
-
-
-#define IX_MBUF_POOL_PUT_CHAIN(bufPtr) \
-		IX_OSAL_MBUF_POOL_PUT_CHAIN(bufPtr)
-
-
-#define IX_MBUF_POOL_SHOW(poolPtr) \
-		IX_OSAL_MBUF_POOL_SHOW(poolPtr)
-
-
-#define IX_MBUF_POOL_MDATA_RESET(bufPtr) \
-		IX_OSAL_MBUF_POOL_MDATA_RESET(bufPtr)
-
-#endif /* IX_OSAL_BACKWARD_BUFFER_MGT_H */
diff --git a/arch/arm/cpu/ixp/npe/include/IxOsalBackwardCacheMMU.h b/arch/arm/cpu/ixp/npe/include/IxOsalBackwardCacheMMU.h
deleted file mode 100644
index fe570e6..0000000
--- a/arch/arm/cpu/ixp/npe/include/IxOsalBackwardCacheMMU.h
+++ /dev/null
@@ -1,69 +0,0 @@
-/** 
- * This file is intended to provide backward 
- * compatibility for main osService/OSSL 
- * APIs. 
- *
- * It shall be phased out gradually and users
- * are strongly recommended to use IX_OSAL API.
- *
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- * 
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- * 
- * @par
- * -- End of Copyright Notice --
- */
-
-#ifndef IX_OSAL_BACKWARD_CACHE_MMU_H
-#define IX_OSAL_BACKWARD_CACHE_MMU_H
-
-#ifdef IX_OSAL_CACHED
-#define IX_ACC_CACHE_ENABLED
-#endif
-
-#define IX_XSCALE_CACHE_LINE_SIZE IX_OSAL_CACHE_LINE_SIZE
-
-#define IX_ACC_DRV_DMA_MALLOC(size) IX_OSAL_CACHE_DMA_MALLOC(size)
-
-#define IX_ACC_DRV_DMA_FREE(ptr,size) IX_OSAL_CACHE_DMA_FREE(ptr)
-
-#define IX_MMU_VIRTUAL_TO_PHYSICAL_TRANSLATION(addr) IX_OSAL_MMU_VIRT_TO_PHYS(addr)
-
-#define IX_MMU_PHYSICAL_TO_VIRTUAL_TRANSLATION(addr) IX_OSAL_MMU_PHYS_TO_VIRT(addr)
-
-#define IX_ACC_DATA_CACHE_INVALIDATE(addr,size) IX_OSAL_CACHE_INVALIDATE(addr, size)
-
-#define IX_ACC_DATA_CACHE_FLUSH(addr,size) IX_OSAL_CACHE_FLUSH(addr,size)
-
-#endif /* IX_OSAL_BACKWARD_CACHE_MMU_H */
diff --git a/arch/arm/cpu/ixp/npe/include/IxOsalBackwardMemMap.h b/arch/arm/cpu/ixp/npe/include/IxOsalBackwardMemMap.h
deleted file mode 100644
index 3881a3b..0000000
--- a/arch/arm/cpu/ixp/npe/include/IxOsalBackwardMemMap.h
+++ /dev/null
@@ -1,141 +0,0 @@
-/** 
- * This file is intended to provide backward 
- * compatibility for main osService/OSSL 
- * APIs. 
- *
- * It shall be phased out gradually and users
- * are strongly recommended to use IX_OSAL API.
- *
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- * 
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- * 
- * @par
- * -- End of Copyright Notice --
- */
-
-
-#ifndef IX_OSAL_BACKWARD_MEM_MAP_H
-#define IX_OSAL_BACKWARD_MEM_MAP_H
-
-#include "IxOsal.h"
-
-#define IX_OSSERV_SWAP_LONG(wData) IX_OSAL_SWAP_LONG(wData)
-#define IX_OSSERV_SWAP_SHORT(sData) IX_OSAL_SWAP_SHORT(sData)
-
-#define IX_OSSERV_SWAP_SHORT_ADDRESS(sAddr) IX_OSAL_SWAP_SHORT_ADDRESS(sAddr)
-#define IX_OSSERV_SWAP_BYTE_ADDRESS(bAddr) IX_OSAL_SWAP_BYTE_ADDRESS(bAddr)
-
-#define IX_OSSERV_BE_XSTOBUSL(wData)  IX_OSAL_BE_XSTOBUSL(wData)
-#define IX_OSSERV_BE_XSTOBUSS(sData)  IX_OSAL_BE_XSTOBUSS(sData)
-#define IX_OSSERV_BE_XSTOBUSB(bData)  IX_OSAL_BE_XSTOBUSB(bData)
-#define IX_OSSERV_BE_BUSTOXSL(wData)  IX_OSAL_BE_BUSTOXSL(wData)
-#define IX_OSSERV_BE_BUSTOXSS(sData)  IX_OSAL_BE_BUSTOXSS(sData)
-#define IX_OSSERV_BE_BUSTOXSB(bData)  IX_OSAL_BE_BUSTOXSB(bData)
-
-#define IX_OSSERV_LE_AC_XSTOBUSL(wAddr) IX_OSAL_LE_AC_XSTOBUSL(wAddr)
-#define IX_OSSERV_LE_AC_XSTOBUSS(sAddr) IX_OSAL_LE_AC_XSTOBUSS(sAddr)
-#define IX_OSSERV_LE_AC_XSTOBUSB(bAddr) IX_OSAL_LE_AC_XSTOBUSB(bAddr)
-#define IX_OSSERV_LE_AC_BUSTOXSL(wAddr) IX_OSAL_LE_AC_BUSTOXSL(wAddr)
-#define IX_OSSERV_LE_AC_BUSTOXSS(sAddr) IX_OSAL_LE_AC_BUSTOXSS(sAddr)
-#define IX_OSSERV_LE_AC_BUSTOXSB(bAddr) IX_OSAL_LE_AC_BUSTOXSB(bAddr)
-
-#define IX_OSSERV_LE_DC_XSTOBUSL(wData) IX_OSAL_LE_DC_XSTOBUSL(wData)
-#define IX_OSSERV_LE_DC_XSTOBUSS(sData) IX_OSAL_LE_DC_XSTOBUSS(sData)
-#define IX_OSSERV_LE_DC_XSTOBUSB(bData) IX_OSAL_LE_DC_XSTOBUSB(bData)
-#define IX_OSSERV_LE_DC_BUSTOXSL(wData) IX_OSAL_LE_DC_BUSTOXSL(wData)
-#define IX_OSSERV_LE_DC_BUSTOXSS(sData) IX_OSAL_LE_DC_BUSTOXSS(sData)
-#define IX_OSSERV_LE_DC_BUSTOXSB(bData) IX_OSAL_LE_DC_BUSTOXSB(bData)
-
-#define IX_OSSERV_READ_LONG(wAddr)          IX_OSAL_READ_LONG(wAddr)
-#define IX_OSSERV_READ_SHORT(sAddr)         IX_OSAL_READ_SHORT(sAddr)
-#define IX_OSSERV_READ_BYTE(bAddr)          IX_OSAL_READ_BYTE(bAddr)
-#define IX_OSSERV_WRITE_LONG(wAddr, wData)  IX_OSAL_WRITE_LONG(wAddr, wData)
-#define IX_OSSERV_WRITE_SHORT(sAddr, sData) IX_OSAL_WRITE_SHORT(sAddr, sData)
-#define IX_OSSERV_WRITE_BYTE(bAddr, bData)  IX_OSAL_WRITE_BYTE(bAddr, bData)
-
-
-#define IX_OSSERV_READ_NPE_SHARED_LONG(wAddr)            IX_OSAL_READ_BE_SHARED_LONG(wAddr)
-#define IX_OSSERV_READ_NPE_SHARED_SHORT(sAddr)           IX_OSAL_READ_BE_SHARED_SHORT(sAddr)
-#define IX_OSSERV_WRITE_NPE_SHARED_LONG(wAddr, wData)    IX_OSAL_WRITE_BE_SHARED_LONG(wAddr, wData)
-#define IX_OSSERV_WRITE_NPE_SHARED_SHORT(sAddr, sData)   IX_OSAL_WRITE_BE_SHARED_SHORT(sAddr, sData)
-
-#define IX_OSSERV_SWAP_NPE_SHARED_LONG(wData)            IX_OSAL_SWAP_BE_SHARED_LONG(wData)
-#define IX_OSSERV_SWAP_NPE_SHARED_SHORT(sData)           IX_OSAL_SWAP_BE_SHARED_SHORT(sData)
-
-
-/* Map osServ address/size */
-#define IX_OSSERV_QMGR_MAP_SIZE			IX_OSAL_IXP400_QMGR_MAP_SIZE
-#define IX_OSSERV_EXP_REG_MAP_SIZE		IX_OSAL_IXP400_EXP_REG_MAP_SIZE
-#define IX_OSSERV_UART1_MAP_SIZE		IX_OSAL_IXP400_UART1_MAP_SIZE
-#define IX_OSSERV_UART2_MAP_SIZE		IX_OSAL_IXP400_UART2_MAP_SIZE
-#define IX_OSSERV_PMU_MAP_SIZE			IX_OSAL_IXP400_PMU_MAP_SIZE
-#define IX_OSSERV_OSTS_MAP_SIZE			IX_OSAL_IXP400_OSTS_MAP_SIZE
-#define IX_OSSERV_NPEA_MAP_SIZE			IX_OSAL_IXP400_NPEA_MAP_SIZE
-#define IX_OSSERV_NPEB_MAP_SIZE			IX_OSAL_IXP400_NPEB_MAP_SIZE
-#define IX_OSSERV_NPEC_MAP_SIZE			IX_OSAL_IXP400_NPEC_MAP_SIZE
-#define IX_OSSERV_ETHA_MAP_SIZE			IX_OSAL_IXP400_ETHA_MAP_SIZE
-#define IX_OSSERV_ETHB_MAP_SIZE			IX_OSAL_IXP400_ETHB_MAP_SIZE
-#define IX_OSSERV_USB_MAP_SIZE			IX_OSAL_IXP400_USB_MAP_SIZE
-#define IX_OSSERV_GPIO_MAP_SIZE			IX_OSAL_IXP400_GPIO_MAP_SIZE
-#define IX_OSSERV_EXP_BUS_MAP_SIZE		IX_OSAL_IXP400_EXP_BUS_MAP_SIZE
-#define IX_OSSERV_EXP_BUS_CS0_MAP_SIZE	IX_OSAL_IXP400_EXP_BUS_CS0_MAP_SIZE
-#define IX_OSSERV_EXP_BUS_CS1_MAP_SIZE	IX_OSAL_IXP400_EXP_BUS_CS1_MAP_SIZE
-#define IX_OSSERV_EXP_BUS_CS4_MAP_SIZE	IX_OSAL_IXP400_EXP_BUS_CS4_MAP_SIZE
-
-
-#define IX_OSSERV_GPIO_PHYS_BASE			IX_OSAL_IXP400_GPIO_PHYS_BASE
-#define IX_OSSERV_UART1_PHYS_BASE			IX_OSAL_IXP400_UART1_PHYS_BASE
-#define IX_OSSERV_UART2_PHYS_BASE			IX_OSAL_IXP400_UART2_PHYS_BASE
-#define IX_OSSERV_ETHA_PHYS_BASE			IX_OSAL_IXP400_ETHA_PHYS_BASE
-#define IX_OSSERV_ETHB_PHYS_BASE			IX_OSAL_IXP400_ETHB_PHYS_BASE
-#define IX_OSSERV_NPEA_PHYS_BASE			IX_OSAL_IXP400_NPEA_PHYS_BASE
-#define IX_OSSERV_NPEB_PHYS_BASE			IX_OSAL_IXP400_NPEB_PHYS_BASE
-#define IX_OSSERV_NPEC_PHYS_BASE			IX_OSAL_IXP400_NPEC_PHYS_BASE
-#define IX_OSSERV_PERIPHERAL_PHYS_BASE		IX_OSAL_IXP400_PERIPHERAL_PHYS_BASE
-#define IX_OSSERV_QMGR_PHYS_BASE			IX_OSAL_IXP400_QMGR_PHYS_BASE
-#define IX_OSSERV_OSTS_PHYS_BASE			IX_OSAL_IXP400_OSTS_PHYS_BASE
-#define IX_OSSERV_USB_PHYS_BASE				IX_OSAL_IXP400_USB_PHYS_BASE
-#define IX_OSSERV_EXP_BUS_PHYS_BASE			IX_OSAL_IXP400_EXP_BUS_PHYS_BASE
-#define IX_OSSERV_EXP_BUS_BOOT_PHYS_BASE	IX_OSAL_IXP400_EXP_BUS_BOOT_PHYS_BASE
-#define IX_OSSERV_EXP_BUS_CS0_PHYS_BASE		IX_OSAL_IXP400_EXP_BUS_CS0_PHYS_BASE
-#define IX_OSSERV_EXP_BUS_CS1_PHYS_BASE		IX_OSAL_IXP400_EXP_BUS_CS1_PHYS_BASE
-#define IX_OSSERV_EXP_BUS_CS4_PHYS_BASE		IX_OSAL_IXP400_EXP_BUS_CS4_PHYS_BASE
-#define IX_OSSERV_EXP_BUS_REGS_PHYS_BASE	IX_OSAL_IXP400_EXP_BUS_REGS_PHYS_BASE
-
-#define IX_OSSERV_MEM_MAP(physAddr, size)		IX_OSAL_MEM_MAP(physAddr, size)
-
-#define IX_OSSERV_MEM_UNMAP(virtAddr)			IX_OSAL_MEM_UNMAP(virtAddr)
-
-#endif /* IX_OSAL_BACKWARD_MEM_MAP_H */
diff --git a/arch/arm/cpu/ixp/npe/include/IxOsalBackwardOsServices.h b/arch/arm/cpu/ixp/npe/include/IxOsalBackwardOsServices.h
deleted file mode 100644
index 0ccff84..0000000
--- a/arch/arm/cpu/ixp/npe/include/IxOsalBackwardOsServices.h
+++ /dev/null
@@ -1,125 +0,0 @@
-/** 
- * This file is intended to provide backward 
- * compatibility for main osService/OSSL 
- * APIs. 
- *
- * It shall be phased out gradually and users
- * are strongly recommended to use IX_OSAL API.
- *
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- * 
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- * 
- * @par
- * -- End of Copyright Notice --
- */
-
-#ifndef IX_OSAL_BACKWARD_OSSERVICES_H
-#define IX_OSAL_BACKWARD_OSSERVICES_H
-
-#ifndef __vxworks
-typedef UINT32 IX_IRQ_STATUS;
-#else
-typedef int IX_IRQ_STATUS;
-#endif
-
-typedef IxOsalMutex IxMutex;
-
-typedef IxOsalFastMutex IxFastMutex;
-
-typedef IxOsalVoidFnVoidPtr IxVoidFnVoidPtr;
-
-typedef IxOsalVoidFnPtr IxVoidFnPtr;
-
-
-#define LOG_NONE 	IX_OSAL_LOG_LVL_NONE
-#define LOG_USER 	IX_OSAL_LOG_LVL_USER
-#define LOG_FATAL 	IX_OSAL_LOG_LVL_FATAL
-#define LOG_ERROR  	IX_OSAL_LOG_LVL_ERROR
-#define LOG_WARNING	IX_OSAL_LOG_LVL_WARNING
-#define LOG_MESSAGE	IX_OSAL_LOG_LVL_MESSAGE
-#define LOG_DEBUG1  IX_OSAL_LOG_LVL_DEBUG1
-#define LOG_DEBUG2	IX_OSAL_LOG_LVL_DEBUG2
-#define LOG_DEBUG3 	IX_OSAL_LOG_LVL_DEBUG3
-#ifndef __vxworks
-#define LOG_ALL 	IX_OSAL_LOG_LVL_ALL
-#endif
-
-PUBLIC IX_STATUS
-ixOsServIntBind (int level, void (*routine) (void *), void *parameter);
-
-PUBLIC IX_STATUS ixOsServIntUnbind (int level);
-
-
-PUBLIC int ixOsServIntLock (void);
-
-PUBLIC void ixOsServIntUnlock (int lockKey);
-
-
-PUBLIC int ixOsServIntLevelSet (int level);
-
-PUBLIC IX_STATUS ixOsServMutexInit (IxMutex * mutex);
-
-PUBLIC IX_STATUS ixOsServMutexLock (IxMutex * mutex);
-
-PUBLIC IX_STATUS ixOsServMutexUnlock (IxMutex * mutex);
-
-PUBLIC IX_STATUS ixOsServMutexDestroy (IxMutex * mutex);
-
-PUBLIC IX_STATUS ixOsServFastMutexInit (IxFastMutex * mutex);
-
-PUBLIC IX_STATUS ixOsServFastMutexTryLock (IxFastMutex * mutex);
-
-PUBLIC IX_STATUS ixOsServFastMutexUnlock (IxFastMutex * mutex);
-
-PUBLIC int
-ixOsServLog (int level, char *format, int arg1, int arg2, int arg3, int arg4,
-	     int arg5, int arg6);
-
-
-PUBLIC int ixOsServLogLevelSet (int level);
-
-PUBLIC void ixOsServSleep (int microseconds);
-
-PUBLIC void ixOsServTaskSleep (int milliseconds);
-
-PUBLIC unsigned int ixOsServTimestampGet (void);
-
-
-PUBLIC void ixOsServUnload (void);
-
-PUBLIC void ixOsServYield (void);
-
-#endif
-/* IX_OSAL_BACKWARD_OSSERVICES_H */
diff --git a/arch/arm/cpu/ixp/npe/include/IxOsalBackwardOssl.h b/arch/arm/cpu/ixp/npe/include/IxOsalBackwardOssl.h
deleted file mode 100644
index 634b494..0000000
--- a/arch/arm/cpu/ixp/npe/include/IxOsalBackwardOssl.h
+++ /dev/null
@@ -1,272 +0,0 @@
-/** 
- * This file is intended to provide backward 
- * compatibility for main osService/OSSL 
- * APIs. 
- *
- * It shall be phased out gradually and users
- * are strongly recommended to use IX_OSAL API.
- *
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- * 
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- * 
- * @par
- * -- End of Copyright Notice --
- */
-
-#ifndef IX_OSAL_BACKWARD_OSSL_H
-#define IX_OSAL_BACKWARD_OSSL_H
-
-
-typedef IxOsalThread ix_ossl_thread_t;
-
-typedef IxOsalSemaphore ix_ossl_sem_t;
-
-typedef IxOsalMutex ix_ossl_mutex_t;
-
-typedef IxOsalTimeval ix_ossl_time_t;
-
-
-/* Map sub-fields for ix_ossl_time_t */
-#define tv_sec secs
-#define tv_nec nsecs
-
-
-typedef IX_STATUS ix_error;
-
-typedef UINT32 ix_ossl_thread_priority;
-
-typedef UINT32 ix_uint32;
-
-
-#define IX_OSSL_ERROR_SUCCESS IX_SUCCESS
-
-#define IX_ERROR_SUCCESS IX_SUCCESS
-
-
-typedef enum
-{
-    IX_OSSL_SEM_UNAVAILABLE = 0,
-    IX_OSSL_SEM_AVAILABLE
-} ix_ossl_sem_state;
-
-
-typedef enum
-{
-    IX_OSSL_MUTEX_UNLOCK = 0,
-    IX_OSSL_MUTEX_LOCK
-} ix_ossl_mutex_state;
-
-
-typedef IxOsalVoidFnVoidPtr ix_ossl_thread_entry_point_t;
-
-
-#define	IX_OSSL_THREAD_PRI_HIGH 	90
-#define IX_OSSL_THREAD_PRI_MEDIUM 	160
-#define IX_OSSL_THREAD_PRI_LOW 		240
-
-
-#define IX_OSSL_WAIT_FOREVER    IX_OSAL_WAIT_FOREVER
-
-#define IX_OSSL_WAIT_NONE       IX_OSAL_WAIT_NONE
-
-#define BILLION  IX_OSAL_BILLION
-
-#define IX_OSSL_TIME_EQ(a,b)  IX_OSAL_TIME_EQ(a,b)
-
-#define IX_OSSL_TIME_GT(a,b)  IX_OSAL_TIME_GT(a,b)
-
-#define IX_OSSL_TIME_LT(a,b)  IX_OSAL_TIME_LT(a,b)
-
-#define IX_OSSL_TIME_ADD(a,b)  IX_OSAL_TIME_ADD(a,b)
-
-#define IX_OSSL_TIME_SUB(a,b)  IX_OSAL_TIME_SUB(a,b)
-
-
-/* a is tick, b is timeval */
-#define IX_OSSL_TIME_CONVERT_TO_TICK(a,b)  \
-		 (a) = IX_OSAL_TIMEVAL_TO_TICKS(b)
-
-
-
-
-PUBLIC IX_STATUS
-ixOsalOsIxp400BackwardOsslThreadCreate (IxOsalVoidFnVoidPtr entryPoint,
-					void *arg, IxOsalThread * ptrThread);
-
-#define ix_ossl_thread_create(entryPoint, arg, ptrTid) \
-		ixOsalOsIxp400BackwardOsslThreadCreate(entryPoint, arg, ptrTid)
-
-
-/* void ix_ossl_thread_exit(ix_error retError, void* retObj) */
-#define ix_ossl_thread_exit(retError, retObj)   \
-		ixOsalThreadExit()
-
-
-PUBLIC IX_STATUS ixOsalOsIxp400BackwardOsslThreadKill (IxOsalThread tid);
-
-/* ix_error ix_ossl_thread_kill(tid) */
-#define ix_ossl_thread_kill(tid) \
-		ixOsalOsIxp400BackwardOsslThreadKill(tid)
-
-
-PUBLIC IX_STATUS
-ixOsalOsIxp400BackwardOsslThreadSetPriority (IxOsalThread tid,
-					     UINT32 priority);
-
-
-/* 
- * ix_error ix_ossl_thread_set_priority(ix_ossl_thread_t tid,
- *                             ix_ossl_thread_priority priority
- *                             ); 
- */
-
-#define ix_ossl_thread_set_priority(tid, priority) \
-		ixOsalOsIxp400BackwardOsslThreadSetPriority(tid, priority)
-
-
-PUBLIC IX_STATUS ixOsalOsIxp400BackwardOsslTickGet (int *pticks);
-
-#define ix_ossl_tick_get(pticks) \
-		ixOsalOsIxp400BackwardOsslTickGet(pticks)
-
-PUBLIC IX_STATUS ixOsalOsIxp400BackwardOsslThreadDelay (int ticks);
-
-#define ix_ossl_thread_delay(ticks) ixOsalOsIxp400BackwardOsslThreadDelay(ticks)
-
-
-
-/* ix_error ix_ossl_sem_init(int start_value, ix_ossl_sem_t* sid); */
-/* Note sid is a pointer to semaphore */
-#define ix_ossl_sem_init(value, sid) \
-		ixOsalSemaphoreInit(sid, value)
-
-
-PUBLIC IX_STATUS
-ixOsalOsIxp400BackwardOsslSemaphoreWait (IxOsalSemaphore semaphore,
-					 INT32 timeout);
-
-
-/*
-ix_error ix_ossl_sem_take(
-                          ix_ossl_sem_t sid,
-                          ix_uint32 timeout
-                         );
-*/
-
-#define ix_ossl_sem_take( sid, timeout) \
-		ixOsalOsIxp400BackwardOsslSemaphoreWait(sid, timeout)
-
-
-
-PUBLIC IX_STATUS
-ixOsalOsIxp400BackwardOsslSemaphorePost (IxOsalSemaphore sid);
-
-/*ix_error ix_ossl_sem_give(ix_ossl_sem_t sid); */
-#define ix_ossl_sem_give(sid) \
-		ixOsalOsIxp400BackwardOsslSemaphorePost(sid);
-
-
-PUBLIC IX_STATUS ixOsalOsIxp400BackwardSemaphoreDestroy (IxOsalSemaphore sid);
-
-#define ix_ossl_sem_fini(sid) \
-		ixOsalOsIxp400BackwardSemaphoreDestroy(sid)
-
-
-PUBLIC IX_STATUS
-ixOsalOsIxp400BackwardOsslMutexInit (ix_ossl_mutex_state start_state,
-				     IxOsalMutex * pMutex);
-
-
-/* ix_error ix_ossl_mutex_init(ix_ossl_mutex_state start_state, ix_ossl_mutex_t* mid); */
-#define ix_ossl_mutex_init(start_state, pMutex) \
-		ixOsalOsIxp400BackwardOsslMutexInit(start_state, pMutex)
-
-
-PUBLIC IX_STATUS
-ixOsalOsIxp400BackwardOsslMutexLock (IxOsalMutex mid, INT32 timeout);
-
-/*
-ix_error ix_ossl_mutex_lock(
-                            ix_ossl_mutex_t mid, 
-                            ix_uint32 timeout
-                           );
-*/
-#define ix_ossl_mutex_lock(mid, timeout) \
-		ixOsalOsIxp400BackwardOsslMutexLock(mid, timout)
-
-
-PUBLIC IX_STATUS ixOsalOsIxp400BackwardOsslMutexUnlock (IxOsalMutex mid);
-
-/* ix_error ix_ossl_mutex_unlock(ix_ossl_mutex_t mid); */
-#define ix_ossl_mutex_unlock(mid) \
-		ixOsalOsIxp400BackwardOsslMutexUnlock(mid)
-
-PUBLIC IX_STATUS ixOsalOsIxp400BackwardOsslMutexDestroy (IxOsalMutex mid);
-
-#define ix_ossl_mutex_fini(mid) \
-		ixOsalOsIxp400BackwardOsslMutexDestroy(mid);
-
-#define ix_ossl_sleep(sleeptime_ms) \
-		ixOsalSleep(sleeptime_ms)
-
-PUBLIC IX_STATUS ixOsalOsIxp400BackwardOsslSleepTick (UINT32 ticks);
-
-#define ix_ossl_sleep_tick(sleeptime_ticks) \
-		ixOsalOsIxp400BackwardOsslSleepTick(sleeptime_ticks)
-
-
-PUBLIC IX_STATUS ixOsalOsIxp400BackwardOsslTimeGet (IxOsalTimeval * pTv);
-
-#define ix_ossl_time_get(pTv)    \
-		ixOsalOsIxp400BackwardOsslTimeGet(pTv)
-
-
-typedef UINT32 ix_ossl_size_t;
-
-#define ix_ossl_malloc(arg_size) \
-		ixOsalMemAlloc(arg_size)
-
-#define ix_ossl_free(arg_pMemory) \
-		ixOsalMemFree(arg_pMemory)
-
-
-#define ix_ossl_memcpy(arg_pDest, arg_pSrc,arg_Count) \
-		ixOsalMemCopy(arg_pDest, arg_pSrc,arg_Count)
-
-#define ix_ossl_memset(arg_pDest, arg_pChar, arg_Count) \
-		ixOsalMemSet(arg_pDest, arg_pChar, arg_Count)
-
-
-#endif /* IX_OSAL_BACKWARD_OSSL_H */
diff --git a/arch/arm/cpu/ixp/npe/include/IxOsalBufferMgt.h b/arch/arm/cpu/ixp/npe/include/IxOsalBufferMgt.h
deleted file mode 100644
index 497ed04..0000000
--- a/arch/arm/cpu/ixp/npe/include/IxOsalBufferMgt.h
+++ /dev/null
@@ -1,621 +0,0 @@
-/**
- * @file IxOsalBufferMgt.h
- *
- * @brief OSAL Buffer pool management and buffer management definitions.
- *
- * Design Notes:
- *
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- * 
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- * 
- * @par
- * -- End of Copyright Notice --
- */
-/* @par
- * -- Copyright Notice --
- *
- * @par
- * Copyright 1979, 1980, 1983, 1986, 1988, 1989, 1991, 1992, 1993, 1994 
- *      The Regents of the University of California. All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the University nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
- */
-
-#ifndef IxOsalBufferMgt_H
-#define IxOsalBufferMgt_H
-
-#include "IxOsal.h"
-/**
- * @defgroup IxOsalBufferMgt OSAL Buffer Management Module.
- *
- * @brief Buffer management module for IxOsal
- *
- * @{ 
- */
-
-/**
- * @ingroup IxOsalBufferMgt
- *
- * @def IX_OSAL_MBUF_MAX_POOLS
- *
- * @brief The maximum number of pools that can be allocated, must be 
- *        a multiple of 32 as required by implementation logic.
- * @note  This can safely be increased if more pools are required.
- */
-#define IX_OSAL_MBUF_MAX_POOLS      32
-
-/**
- * @ingroup IxOsalBufferMgt
- *
- * @def IX_OSAL_MBUF_POOL_NAME_LEN
- *
- * @brief The maximum string length of the pool name
- */
-#define IX_OSAL_MBUF_POOL_NAME_LEN  64
-
-
-
-/**
- *  Define IX_OSAL_MBUF
- */
-
-
-/* forward declaration of internal structure */
-struct __IXP_BUF;
-
-/* 
- * OS can define it in IxOsalOs.h to skip the following
- * definition.
- */
-#ifndef IX_OSAL_ATTRIBUTE_ALIGN32
-#define IX_OSAL_ATTRIBUTE_ALIGN32 __attribute__ ((aligned(32)))
-#endif
-
-/* release v1.4 backward compatible definitions */
-struct __IX_MBUF
-{
-    struct __IXP_BUF *ix_next IX_OSAL_ATTRIBUTE_ALIGN32;
-    struct __IXP_BUF *ix_nextPacket;
-    UINT8 *ix_data;
-    UINT32 ix_len;  
-    unsigned char ix_type;
-    unsigned char ix_flags;
-    unsigned short ix_reserved;
-    UINT32 ix_rsvd;
-    UINT32 ix_PktLen; 
-    void *ix_priv;     
-};
-
-struct __IX_CTRL
-{
-    UINT32 ix_reserved[2];        /**< Reserved field */
-    UINT32 ix_signature;          /**< Field to indicate if buffers are allocated by the system */    
-    UINT32 ix_allocated_len;      /**< Allocated buffer length */  
-    UINT32 ix_allocated_data;     /**< Allocated buffer data pointer */  
-    void *ix_pool;                /**< pointer to the buffer pool */
-    struct __IXP_BUF *ix_chain;   /**< chaining */ 
-    void *ix_osbuf_ptr;           /**< Storage for OS-specific buffer pointer */
-};
-
-struct __IX_NE_SHARED
-{
-    UINT32 reserved[8] IX_OSAL_ATTRIBUTE_ALIGN32;   /**< Reserved area for NPE Service-specific usage */
-};
-
-
-/* 
- * IXP buffer structure 
- */
-typedef struct __IXP_BUF
-{
-    struct __IX_MBUF ix_mbuf IX_OSAL_ATTRIBUTE_ALIGN32; /**< buffer header */
-    struct __IX_CTRL ix_ctrl;                           /**< buffer management */
-    struct __IX_NE_SHARED ix_ne;                        /**< Reserved area for NPE Service-specific usage*/
-} IXP_BUF;
-
-
-
-/**
- * @ingroup IxOsalBufferMgt
- *
- * @def typedef IX_OSAL_MBUF
- *
- * @brief Generic IXP mbuf format.
- */
-typedef IXP_BUF IX_OSAL_MBUF;
-
-
-/**
- * @ingroup IxOsalBufferMgt
- *
- * @def IX_OSAL_IXP_NEXT_BUFFER_IN_PKT_PTR(m_blk_ptr)
- *
- * @brief Return pointer to the next mbuf in a single packet
- */
-#define IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR(m_blk_ptr)  \
-        (m_blk_ptr)->ix_mbuf.ix_next
-
-
-/**
- * @ingroup IxOsalBufferMgt
- *
- * @def IX_OSAL_MBUF_NEXT_PKT_IN_CHAIN_PTR(m_blk_ptr)
- *
- * @brief Return pointer to the next packet in the chain
- */
-#define IX_OSAL_MBUF_NEXT_PKT_IN_CHAIN_PTR(m_blk_ptr)  \
-        (m_blk_ptr)->ix_mbuf.ix_nextPacket
-
-
-/**
- * @ingroup IxOsalBufferMgt
- *
- * @def IX_OSAL_MBUF_MDATA(m_blk_ptr)
- *
- * @brief Return pointer to the data in the mbuf
- */
-#define IX_OSAL_MBUF_MDATA(m_blk_ptr)       (m_blk_ptr)->ix_mbuf.ix_data
-
-/**
- * @ingroup IxOsalBufferMgt
- *
- * @def IX_OSAL_MBUF_MLEN(m_blk_ptr)
- *
- * @brief Return the data length
- */
-#define IX_OSAL_MBUF_MLEN(m_blk_ptr) \
-    (m_blk_ptr)->ix_mbuf.ix_len
-
-/**
- * @ingroup IxOsalBufferMgt
- *
- * @def IX_OSAL_MBUF_MTYPE(m_blk_ptr)
- *
- * @brief Return the data type in the mbuf
- */
-#define IX_OSAL_MBUF_MTYPE(m_blk_ptr) \
-    (m_blk_ptr)->ix_mbuf.ix_type
-
-
-/**
- * @ingroup IxOsalBufferMgt
- *
- * @def IX_OSAL_MBUF_FLAGS(m_blk_ptr)
- *
- * @brief Return the buffer flags
- */
-#define IX_OSAL_MBUF_FLAGS(m_blk_ptr)       \
-        (m_blk_ptr)->ix_mbuf.ix_flags
-
-
-/**
- * @ingroup IxOsalBufferMgt
- *
- * @def IX_OSAL_MBUF_NET_POOL(m_blk_ptr)
- *
- * @brief Return pointer to a network pool
- */
-#define IX_OSAL_MBUF_NET_POOL(m_blk_ptr)	\
-        (m_blk_ptr)->ix_ctrl.ix_pool
-
-
-
-/**
- * @ingroup IxOsalBufferMgt
- *
- * @def IX_OSAL_MBUF_PKT_LEN(m_blk_ptr)
- *
- * @brief Return the total length of all the data in
- * the mbuf chain for this packet
- */
-#define IX_OSAL_MBUF_PKT_LEN(m_blk_ptr) \
-        (m_blk_ptr)->ix_mbuf.ix_PktLen
-
-
-
-
-/**
- * @ingroup IxOsalBufferMgt
- *
- * @def IX_OSAL_MBUF_PRIV(m_blk_ptr)
- *
- * @brief Return the private field
- */
-#define IX_OSAL_MBUF_PRIV(m_blk_ptr)        \
-        (m_blk_ptr)->ix_mbuf.ix_priv
-
-
-
-/**
- * @ingroup IxOsalBufferMgt
- *
- * @def IX_OSAL_MBUF_SIGNATURE(m_blk_ptr)
- *
- * @brief Return the signature field of IX_OSAL_MBUF
- */
-#define IX_OSAL_MBUF_SIGNATURE(m_blk_ptr)  \
-        (m_blk_ptr)->ix_ctrl.ix_signature
-
-
-/**
- * @ingroup IxOsalBufferMgt
- *
- * @def IX_OSAL_MBUF_OSBUF_PTR(m_blk_ptr)
- *
- * @brief Return ix_osbuf_ptr field of IX_OSAL_MBUF, which is used to store OS-specific buffer pointer during a buffer conversion.
- */
-#define IX_OSAL_MBUF_OSBUF_PTR(m_blk_ptr)  \
-        (m_blk_ptr)->ix_ctrl.ix_osbuf_ptr
-
-
-/**
- * @ingroup IxOsalBufferMgt
- *
- * @def IX_OSAL_MBUF_ALLOCATED_BUFF_LEN(m_blk_ptr)
- *
- * @brief Return the allocated buffer size
- */
-#define IX_OSAL_MBUF_ALLOCATED_BUFF_LEN(m_blk_ptr)  \
-        (m_blk_ptr)->ix_ctrl.ix_allocated_len
-
-/**
- * @ingroup IxOsalBufferMgt
- *
- * @def IX_OSAL_MBUF_ALLOCATED_BUFF_DATA(m_blk_ptr)
- *
- * @brief Return the allocated buffer pointer
- */
-#define IX_OSAL_MBUF_ALLOCATED_BUFF_DATA(m_blk_ptr)  \
-        (m_blk_ptr)->ix_ctrl.ix_allocated_data
-
-
-
-/* Name length */
-#define IX_OSAL_MBUF_POOL_NAME_LEN  64
-
-
-/****************************************************
- * Macros for buffer pool management
- ****************************************************/
-
-/**
- * @ingroup IxOsalBufferMgt
- *
- * @def IX_OSAL_MBUF_POOL_FREE_COUNT(m_pool_ptr
- *
- * @brief Return the total number of freed buffers left in the pool.
- */
-#define IX_OSAL_MBUF_POOL_FREE_COUNT(m_pool_ptr) \
-                    ixOsalBuffPoolFreeCountGet(m_pool_ptr)
-
-/**
- * @ingroup IxOsalBufferMgt
- *
- * @def IX_OSAL_MBUF_POOL_SIZE_ALIGN
- *
- * @brief This macro takes an integer as an argument and
- * rounds it up to be a multiple of the memory cache-line 
- * size.
- *
- * @param int [in] size - the size integer to be rounded up
- *
- * @return int - the size, rounded up to a multiple of
- *               the cache-line size
- */
-#define IX_OSAL_MBUF_POOL_SIZE_ALIGN(size)                 \
-    ((((size) + (IX_OSAL_CACHE_LINE_SIZE - 1)) /      \
-        IX_OSAL_CACHE_LINE_SIZE) *                  \
-            IX_OSAL_CACHE_LINE_SIZE)
-
-/* Don't use this directly, use macro */
-PUBLIC UINT32 ixOsalBuffPoolMbufAreaSizeGet (int count);
-
-
-/**
- * @ingroup IxOsalBufferMgt
- *
- * @def IX_OSAL_MBUF_POOL_MBUF_AREA_SIZE_ALIGNED
- *
- * @brief This macro calculates, from the number of mbufs required, the 
- * size of the memory area required to contain the mbuf headers for the
- * buffers in the pool.  The size to be used for each mbuf header is 
- * rounded up to a multiple of the cache-line size, to ensure
- * each mbuf header aligns on a cache-line boundary.
- * This macro is used by IX_OSAL_MBUF_POOL_MBUF_AREA_ALLOC()
- *
- * @param int [in] count - the number of buffers the pool will contain
- *
- * @return int - the total size required for the pool mbuf area (aligned)
- */
-#define IX_OSAL_MBUF_POOL_MBUF_AREA_SIZE_ALIGNED(count) \
-        ixOsalBuffPoolMbufAreaSizeGet(count)
-
-
-/* Don't use this directly, use macro */
-PUBLIC UINT32 ixOsalBuffPoolDataAreaSizeGet (int count, int size);
-
-
-/**
- * @ingroup IxOsalBufferMgt
- *
- * @def IX_OSAL_MBUF_POOL_DATA_AREA_SIZE_ALIGNED
- *
- * @brief This macro calculates, from the number of mbufs required and the
- * size of the data portion for each mbuf, the size of the data memory area
- * required. The size is adjusted to ensure alignment on cache line boundaries.
- * This macro is used by IX_OSAL_MBUF_POOL_DATA_AREA_ALLOC()
- *
- *
- * @param int [in] count - The number of mbufs in the pool.
- * @param int [in] size  - The desired size for each mbuf data portion.
- *                         This size will be rounded up to a multiple of the
- *                         cache-line size to ensure alignment on cache-line
- *                         boundaries for each data block.
- *
- * @return int - the total size required for the pool data area (aligned)
- */
-#define IX_OSAL_MBUF_POOL_DATA_AREA_SIZE_ALIGNED(count, size) \
-        ixOsalBuffPoolDataAreaSizeGet((count), (size))
-
-
-/**
- * @ingroup IxOsalBufferMgt
- *
- * @def IX_OSAL_MBUF_POOL_MBUF_AREA_ALLOC
- *
- * @brief Allocates the memory area needed for the number of mbuf headers
- * specified by <i>count</i>.
- * This macro ensures the mbuf headers align on cache line boundaries.
- * This macro evaluates to a pointer to the memory allocated.
- *
- * @param int [in] count - the number of mbufs the pool will contain
- * @param int [out] memAreaSize - the total amount of memory allocated
- *
- * @return void * - a pointer to the allocated memory area
- */
-#define IX_OSAL_MBUF_POOL_MBUF_AREA_ALLOC(count, memAreaSize) \
-    IX_OSAL_CACHE_DMA_MALLOC((memAreaSize =                 \
-        IX_OSAL_MBUF_POOL_MBUF_AREA_SIZE_ALIGNED(count)))
-
-/**
- * @ingroup IxOsalBufferMgt
- *
- * @def IX_OSAL_MBUF_POOL_DATA_AREA_ALLOC
- *
- * @brief Allocates the memory pool for the data portion of the pool mbufs.
- * The number of mbufs is specified by <i>count</i>.  The size of the data
- * portion of each mbuf is specified by <i>size</i>.
- * This macro ensures the mbufs are aligned on cache line boundaries
- * This macro evaluates to a pointer to the memory allocated.
- *
- * @param int [in] count - the number of mbufs the pool will contain
- * @param int [in] size - the desired size (in bytes) required for the data
- *                        portion of each mbuf.  Note that this size may be
- *                        rounded up to ensure alignment on cache-line
- *                        boundaries.
- * @param int [out] memAreaSize - the total amount of memory allocated
- *
- * @return void * - a pointer to the allocated memory area
- */
-#define IX_OSAL_MBUF_POOL_DATA_AREA_ALLOC(count, size, memAreaSize) \
-    IX_OSAL_CACHE_DMA_MALLOC((memAreaSize =                     \
-        IX_OSAL_MBUF_POOL_DATA_AREA_SIZE_ALIGNED(count,size)))
-
-
-
-/**
- * @ingroup IxOsalBufferMgt
- *
- * @def IX_OSAL_MBUF_POOL_INIT
- *
- * @brief Wrapper macro for ixOsalPoolInit() 
- * See function description below for details.
- */
-#define IX_OSAL_MBUF_POOL_INIT(count, size, name) \
-    ixOsalPoolInit((count), (size), (name))
-
-/**
- * @ingroup IxOsalBufferMgt
- *
- * @def IX_OSAL_MBUF_NO_ALLOC_POOL_INIT
- *
- * @return Pointer to the new pool or NULL if the initialization failed.
- *
- * @brief Wrapper macro for ixOsalNoAllocPoolInit() 
- * See function description below for details.
- * 
- */
-#define IX_OSAL_MBUF_NO_ALLOC_POOL_INIT(bufPtr, dataPtr, count, size, name) \
-    ixOsalNoAllocPoolInit( (bufPtr), (dataPtr), (count), (size), (name))
-
-/**
- * @ingroup IxOsalBufferMgt
- *
- * @def IX_OSAL_MBUF_POOL_GET
- *
- * @brief Wrapper macro for ixOsalMbufAlloc() 
- * See function description below for details.
- */
-#define IX_OSAL_MBUF_POOL_GET(poolPtr) \
-        ixOsalMbufAlloc(poolPtr)
-
-/**
- * @ingroup IxOsalBufferMgt
- *
- * @def IX_OSAL_MBUF_POOL_PUT
- *
- * @brief Wrapper macro for ixOsalMbufFree() 
- * See function description below for details.
- */
-#define IX_OSAL_MBUF_POOL_PUT(bufPtr) \
-    ixOsalMbufFree(bufPtr)
-
-/**
- * @ingroup IxOsalBufferMgt
- *
- * @def IX_OSAL_MBUF_POOL_PUT_CHAIN
- *
- * @brief Wrapper macro for ixOsalMbufChainFree() 
- * See function description below for details.
- */
-#define IX_OSAL_MBUF_POOL_PUT_CHAIN(bufPtr) \
-    ixOsalMbufChainFree(bufPtr)
-
-/**
- * @ingroup IxOsalBufferMgt
- *
- * @def IX_OSAL_MBUF_POOL_SHOW
- *
- * @brief Wrapper macro for ixOsalMbufPoolShow() 
- * See function description below for details.
- */
-#define IX_OSAL_MBUF_POOL_SHOW(poolPtr) \
-    ixOsalMbufPoolShow(poolPtr)
-
-/**
- * @ingroup IxOsalBufferMgt
- *
- * @def IX_OSAL_MBUF_POOL_MDATA_RESET
- *
- * @brief Wrapper macro for ixOsalMbufDataPtrReset() 
- * See function description below for details.
- */
-#define IX_OSAL_MBUF_POOL_MDATA_RESET(bufPtr) \
-    ixOsalMbufDataPtrReset(bufPtr)
-
-/**
- * @ingroup IxOsalBufferMgt
- *
- * @def IX_OSAL_MBUF_POOL_UNINIT
- *
- * @brief Wrapper macro for ixOsalBuffPoolUninit() 
- * See function description below for details.
- */
-#define IX_OSAL_MBUF_POOL_UNINIT(m_pool_ptr)  \
-        ixOsalBuffPoolUninit(m_pool_ptr)
-
-/* 
- * Include OS-specific bufferMgt definitions 
- */
-#include "IxOsalOsBufferMgt.h"
-
-
-/**
- * @ingroup IxOsalBufferMgt
- *
- * @def IX_OSAL_CONVERT_OSBUF_TO_IXPBUF( osBufPtr, ixpBufPtr)
- *
- * @brief Convert pre-allocated os-specific buffer format to OSAL IXP_BUF (IX_OSAL_MBUF) format. 
- * It is users' responsibility to provide pre-allocated and valid buffer pointers.
- * @param osBufPtr (in) - a pre-allocated os-specific buffer pointer.
- * @param ixpBufPtr (in)- a pre-allocated OSAL IXP_BUF pointer
- * @return None
- */
-#define IX_OSAL_CONVERT_OSBUF_TO_IXPBUF( osBufPtr, ixpBufPtr) \
-        IX_OSAL_OS_CONVERT_OSBUF_TO_IXPBUF( osBufPtr, ixpBufPtr)        
-
-
-/**
- * @ingroup IxOsalBufferMgt
- *
- * @def IX_OSAL_CONVERT_IXPBUF_TO_OSBUF( ixpBufPtr, osBufPtr)
- *
- * @brief Convert pre-allocated OSAL IXP_BUF (IX_OSAL_MBUF) format to os-specific buffer pointers.
- * @param ixpBufPtr (in) - OSAL IXP_BUF pointer
- * @param osBufPtr (out) - os-specific buffer pointer.
- * @return None
- */
-
-#define IX_OSAL_CONVERT_IXPBUF_TO_OSBUF( ixpBufPtr, osBufPtr)  \
-        IX_OSAL_OS_CONVERT_IXPBUF_TO_OSBUF( ixpBufPtr, osBufPtr)
-
-
-PUBLIC IX_OSAL_MBUF_POOL *ixOsalPoolInit (UINT32 count,
-                      UINT32 size, const char *name);
-
-PUBLIC IX_OSAL_MBUF_POOL *ixOsalNoAllocPoolInit (void *poolBufPtr,
-                         void *poolDataPtr,
-						 UINT32 count,
-						 UINT32 size,
-						 const char *name);
-
-PUBLIC IX_OSAL_MBUF *ixOsalMbufAlloc (IX_OSAL_MBUF_POOL * pool);
-
-PUBLIC IX_OSAL_MBUF *ixOsalMbufFree (IX_OSAL_MBUF * mbuf);
-
-PUBLIC void ixOsalMbufChainFree (IX_OSAL_MBUF * mbuf);
-
-PUBLIC void ixOsalMbufDataPtrReset (IX_OSAL_MBUF * mbuf);
-
-PUBLIC void ixOsalMbufPoolShow (IX_OSAL_MBUF_POOL * pool);
-
-PUBLIC IX_STATUS ixOsalBuffPoolUninit (IX_OSAL_MBUF_POOL * pool);
-
-PUBLIC UINT32 ixOsalBuffPoolFreeCountGet(IX_OSAL_MBUF_POOL * pool);
-
-
-/**
- * @} IxOsalBufferMgt
- */
-
-
-#endif /* IxOsalBufferMgt_H */
diff --git a/arch/arm/cpu/ixp/npe/include/IxOsalBufferMgtDefault.h b/arch/arm/cpu/ixp/npe/include/IxOsalBufferMgtDefault.h
deleted file mode 100644
index 684b52e..0000000
--- a/arch/arm/cpu/ixp/npe/include/IxOsalBufferMgtDefault.h
+++ /dev/null
@@ -1,88 +0,0 @@
-/**
- * @file IxOsalBufferMgtDefault.h
- *
- * @brief Default buffer pool management and buffer management
- *        definitions.
- *
- * Design Notes:
- *
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- * 
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- * 
- * @par
- * -- End of Copyright Notice --
- */
-
-#ifndef IX_OSAL_BUFFER_MGT_DEFAULT_H
-#define IX_OSAL_BUFFER_MGT_DEFAULT_H
-
-/**
- * @enum IxMbufPoolAllocationType
- * @brief Used to indicate how the pool memory was allocated
- */
-
-typedef enum
-{
-    IX_OSAL_MBUF_POOL_TYPE_SYS_ALLOC = 0, /**< mbuf pool allocated by the system */
-    IX_OSAL_MBUF_POOL_TYPE_USER_ALLOC	 /**< mbuf pool allocated by the user */
-} IxOsalMbufPoolAllocationType;
-
-
-/**
- * @brief Implementation of buffer pool structure for use with non-VxWorks OS
- */
-
-typedef struct
-{
-    IX_OSAL_MBUF *nextFreeBuf;	/**< Pointer to the next free mbuf              */
-    void *mbufMemPtr;	   /**< Pointer to the mbuf memory area            */
-    void *dataMemPtr;	   /**< Pointer to the data memory area            */
-    int bufDataSize;	   /**< The size of the data portion of each mbuf  */
-    int totalBufsInPool;   /**< Total number of mbufs in the pool          */
-    int freeBufsInPool;	   /**< Number of free mbufs currently in the pool */
-    int mbufMemSize;	   /**< The size of the pool mbuf memory area      */
-    int dataMemSize;	   /**< The size of the pool data memory area      */
-    char name[IX_OSAL_MBUF_POOL_NAME_LEN + 1];	 /**< Descriptive name for pool */
-    IxOsalMbufPoolAllocationType poolAllocType;
-    unsigned int poolIdx;  /**< Pool Index */ 
-} IxOsalMbufPool;
-
-typedef IxOsalMbufPool IX_OSAL_MBUF_POOL;
-
-
-PUBLIC IX_STATUS ixOsalBuffPoolUninit (IX_OSAL_MBUF_POOL * pool);
-
-
-#endif /* IX_OSAL_BUFFER_MGT_DEFAULT_H */
diff --git a/arch/arm/cpu/ixp/npe/include/IxOsalConfig.h b/arch/arm/cpu/ixp/npe/include/IxOsalConfig.h
deleted file mode 100644
index d56e796..0000000
--- a/arch/arm/cpu/ixp/npe/include/IxOsalConfig.h
+++ /dev/null
@@ -1,76 +0,0 @@
-/**
- * @file  IxOsalConfig.h
- *
- * @brief OSAL Configuration header file
- * 
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- * 
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- * 
- * @par
- * -- End of Copyright Notice --
- */
-
-/* 
- * This file contains user-editable fields for modules inclusion.
- */
-#ifndef IxOsalConfig_H
-#define IxOsalConfig_H
-
-
-/*
- * Note: in the future these config options may
- * become build time decision. 
- */
-
-/* Choose cache */
-#define IX_OSAL_CACHED
-/* #define IX_OSAL_UNCACHED */
-
-
-/*
- * Select the module headers to include
- */
-#include "IxOsalIoMem.h"	/* I/O Memory Management module API */
-#include "IxOsalBufferMgt.h"	/* Buffer Management module API */
-
-/*
- * Select main platform header file to use
- */
-#include "IxOsalOem.h"
-
-
-
-#endif /* IxOsalConfig_H */
diff --git a/arch/arm/cpu/ixp/npe/include/IxOsalEndianess.h b/arch/arm/cpu/ixp/npe/include/IxOsalEndianess.h
deleted file mode 100644
index 3b1c739..0000000
--- a/arch/arm/cpu/ixp/npe/include/IxOsalEndianess.h
+++ /dev/null
@@ -1,134 +0,0 @@
-/** 
- * @file IxOsalEndianess.h (Obsolete file) 
- * 
- * @brief Header file for determining system endianess and OS
- * 
- * @par
- * @version $Revision: 1.1
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- * 
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- * 
- * @par
- * -- End of Copyright Notice --
- */
-
-
-#ifndef IxOsalEndianess_H
-#define IxOsalEndianess_H
-
-#if defined (__vxworks) || defined (__linux)
-
-/* get ntohl/ntohs/htohl/htons macros and CPU definitions for VxWorks */
-/* #include <netinet/in.h>  */
-
-#elif defined (__wince)
-
-/* get ntohl/ntohs/htohl/htons macros definitions for WinCE */
-#include <Winsock2.h>
-
-#else
-
-#error Unknown OS, please add a section with the include file for htonl/htons/ntohl/ntohs
-
-#endif /* vxworks or linux or wince */
-
-/* Compiler specific endianness selector - WARNING this works only with arm gcc, use appropriate defines with diab */
-
-#ifndef __wince
-
-#if defined (__ARMEL__)
-
-#ifndef __LITTLE_ENDIAN
-
-#define __LITTLE_ENDIAN
-
-#endif /* _LITTLE_ENDIAN */
-
-#elif defined (__ARMEB__) || CPU == SIMSPARCSOLARIS
-
-#ifndef __BIG_ENDIAN
-
-#define __BIG_ENDIAN
-
-#endif /* __BIG_ENDIAN */
-
-#else
-
-#error Error, could not identify target endianness
-
-#endif /* endianness selector no WinCE OSes */
-
-#else /* ndef __wince */
-
-#define __LITTLE_ENDIAN
-
-#endif /* def __wince */
-
-
-/* OS mode selector */
-#if defined (__vxworks) && defined (__LITTLE_ENDIAN)
-
-#define IX_OSAL_VXWORKS_LE
-
-#elif defined (__vxworks) && defined (__BIG_ENDIAN)
-
-#define IX_OSAL_VXWORKS_BE
-
-#elif defined (__linux) && defined (__BIG_ENDIAN)
-
-#define IX_OSAL_LINUX_BE
-
-#elif defined (__linux) && defined (__LITTLE_ENDIAN)
-
-#define IX_OSAL_LINUX_LE
-
-#elif defined (BOOTLOADER_BLD) && defined (__LITTLE_ENDIAN)
-
-#define IX_OSAL_EBOOT_LE
-
-#elif defined (__wince) && defined (__LITTLE_ENDIAN)
-
-#define IX_OSAL_WINCE_LE
-
-#else
-
-#error Unknown OS/Endianess combination - only vxWorks BE LE, Linux BE LE, WinCE BE LE are supported
-
-#endif /* mode selector */
-
-
-
-#endif /* IxOsalEndianess_H */
diff --git a/arch/arm/cpu/ixp/npe/include/IxOsalIoMem.h b/arch/arm/cpu/ixp/npe/include/IxOsalIoMem.h
deleted file mode 100644
index ea6d64d..0000000
--- a/arch/arm/cpu/ixp/npe/include/IxOsalIoMem.h
+++ /dev/null
@@ -1,322 +0,0 @@
-/*
- * @file        IxOsalIoMem.h
- * @author	Intel Corporation
- * @date        25-08-2004
- *
- * @brief       description goes here
- */
-
-/**
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- * 
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- * 
- * @par
- * -- End of Copyright Notice --
- */
-
-#ifndef IxOsalIoMem_H
-#define IxOsalIoMem_H
-
-
-/*
- * Decide OS and Endianess, such as IX_OSAL_VXWORKS_LE.
- */
-#include "IxOsalEndianess.h"
-
-/**
- * @defgroup IxOsalIoMem Osal IoMem module
- *
- * @brief I/O memory and endianess support.
- *
- * @{ 
- */
-
-/* Low-level conversion macros - DO NOT USE UNLESS ABSOLUTELY NEEDED */
-#ifndef __wince
-
-
-/* 
- * Private function to swap word
- */
-#ifdef __XSCALE__
-static __inline__ UINT32
-ixOsalCoreWordSwap (UINT32 wordIn)
-{
-    /*
-     * Storage for the swapped word 
-     */
-    UINT32 wordOut;
-
-    /*
-     * wordIn = A, B, C, D 
-     */
-    __asm__ (" eor r1, %1, %1, ror #16;"	/* R1 =      A^C, B^D, C^A, D^B */
-	     " bic r1, r1, #0x00ff0000;"	/* R1 =      A^C, 0  , C^A, D^B */
-	     " mov %0, %1, ror #8;"	/* wordOut = D,   A,   B,   C   */
-	     " eor %0, %0, r1, lsr #8;"	/* wordOut = D,   C,   B,   A   */
-  : "=r" (wordOut): "r" (wordIn):"r1");
-
-    return wordOut;
-}
-
-#define IX_OSAL_SWAP_LONG(wData)          (ixOsalCoreWordSwap(wData))
-#else
-#define IX_OSAL_SWAP_LONG(wData)          ((wData >> 24) | (((wData >> 16) & 0xFF) << 8) | (((wData >> 8) & 0xFF) << 16) | ((wData & 0xFF) << 24))
-#endif
-
-#else /* ndef __wince */
-#define IX_OSAL_SWAP_LONG(wData)        ((((UINT32)wData << 24) | ((UINT32)wData >> 24)) | (((wData << 8) & 0xff0000) | ((wData >> 8) & 0xff00)))
-#endif /* ndef __wince */
-
-#define IX_OSAL_SWAP_SHORT(sData)         ((sData >> 8) | ((sData & 0xFF) << 8))
-#define IX_OSAL_SWAP_SHORT_ADDRESS(sAddr) ((sAddr) ^ 0x2)
-#define IX_OSAL_SWAP_BYTE_ADDRESS(bAddr)  ((bAddr) ^ 0x3)
-
-#define IX_OSAL_BE_XSTOBUSL(wData)  (wData)
-#define IX_OSAL_BE_XSTOBUSS(sData)  (sData)
-#define IX_OSAL_BE_XSTOBUSB(bData)  (bData)
-#define IX_OSAL_BE_BUSTOXSL(wData)  (wData)
-#define IX_OSAL_BE_BUSTOXSS(sData)  (sData)
-#define IX_OSAL_BE_BUSTOXSB(bData)  (bData)
-
-#define IX_OSAL_LE_AC_XSTOBUSL(wAddr) (wAddr)
-#define IX_OSAL_LE_AC_XSTOBUSS(sAddr) IX_OSAL_SWAP_SHORT_ADDRESS(sAddr)
-#define IX_OSAL_LE_AC_XSTOBUSB(bAddr) IX_OSAL_SWAP_BYTE_ADDRESS(bAddr)
-#define IX_OSAL_LE_AC_BUSTOXSL(wAddr) (wAddr)
-#define IX_OSAL_LE_AC_BUSTOXSS(sAddr) IX_OSAL_SWAP_SHORT_ADDRESS(sAddr)
-#define IX_OSAL_LE_AC_BUSTOXSB(bAddr) IX_OSAL_SWAP_BYTE_ADDRESS(bAddr)
-
-#define IX_OSAL_LE_DC_XSTOBUSL(wData) IX_OSAL_SWAP_LONG(wData)
-#define IX_OSAL_LE_DC_XSTOBUSS(sData) IX_OSAL_SWAP_SHORT(sData)
-#define IX_OSAL_LE_DC_XSTOBUSB(bData) (bData)
-#define IX_OSAL_LE_DC_BUSTOXSL(wData) IX_OSAL_SWAP_LONG(wData)
-#define IX_OSAL_LE_DC_BUSTOXSS(sData) IX_OSAL_SWAP_SHORT(sData)
-#define IX_OSAL_LE_DC_BUSTOXSB(bData) (bData)
-
-
-/*
- * Decide SDRAM mapping, then implement read/write
- */
-#include "IxOsalMemAccess.h"
-
-
-/**
- * @ingroup IxOsalIoMem
- * @enum IxOsalMapEntryType
- * @brief This is an emum for OSAL I/O mem map type. 
- */
-typedef enum
-{
-    IX_OSAL_STATIC_MAP = 0,	 /**<Set map entry type to static map */
-    IX_OSAL_DYNAMIC_MAP	     /**<Set map entry type to dynamic map */
-} IxOsalMapEntryType;
-
-
-/**
- * @ingroup IxOsalIoMem
- * @enum IxOsalMapEndianessType
- * @brief This is an emum for OSAL I/O mem Endianess and Coherency mode.
- */
-typedef enum
-{
-    IX_OSAL_BE = 0x1,      /**<Set map endian mode to Big Endian */
-    IX_OSAL_LE_AC = 0x2,   /**<Set map endian mode to Little Endian, Address Coherent */
-    IX_OSAL_LE_DC = 0x4,   /**<Set map endian mode to Little Endian, Data Coherent */
-    IX_OSAL_LE = 0x8       /**<Set map endian mode to Little Endian without specifying coherency mode */
-} IxOsalMapEndianessType;
-
-
-/**
- * @struct IxOsalMemoryMap 
- * @brief IxOsalMemoryMap structure
- */
-typedef struct _IxOsalMemoryMap
-{
-    IxOsalMapEntryType type;   /**< map type - IX_OSAL_STATIC_MAP or IX_OSAL_DYNAMIC_MAP */
-
-    UINT32 physicalAddress;    /**< physical address of the memory mapped I/O zone */
-
-    UINT32 size;               /**< size of the map */
-
-    UINT32 virtualAddress;     /**< virtual address of the zone; must be predefined
-                                    in the global memory map for static maps and has
-                                    to be NULL for dynamic maps (populated on allocation)
-								*/
-    /*
-     * pointer to a map function called to map a dynamic map; 
-     * will populate the virtualAddress field 
-     */
-    void (*mapFunction) (struct _IxOsalMemoryMap * map);   /**< pointer to a map function called to map a dynamic map */
-
-    /*
-     * pointer to a map function called to unmap a dynamic map; 
-     * will reset the virtualAddress field to NULL 
-     */
-    void (*unmapFunction) (struct _IxOsalMemoryMap * map); /**< pointer to a map function called to unmap a dynamic map */
-
-    /*
-     * reference count describing how many components share this map; 
-     * actual allocation/deallocation for dynamic maps is done only 
-     * between 0 <=> 1 transitions of the counter 
-     */
-    UINT32 refCount;   /**< reference count describing how many components share this map */
-
-    /*
-     * memory endian type for the map; can be a combination of IX_OSAL_BE (Big 
-     * Endian) and IX_OSAL_LE or IX_OSAL_LE_AC or IX_OSAL_LE_DC
-     * (Little Endian, Address Coherent or Data Coherent). Any combination is
-     * allowed provided it contains at most one LE flag - e.g.
-     * (IX_OSAL_BE), (IX_OSAL_LE_AC), (IX_OSAL_BE | IX_OSAL_LE_DC) are valid
-     * combinations while (IX_OSAL_BE | IX_OSAL_LE_DC | IX_OSAL_LE_AC) is not. 
-     */
-    IxOsalMapEndianessType mapEndianType; /**< memory endian type for the map */
-
-    char *name;      /**< user-friendly name */
-} IxOsalMemoryMap;
-
-
-
-
-/* Internal function to map a memory zone
- * NOTE - This should not be called by the user.
- * Use the macro IX_OSAL_MEM_MAP instead
- */
-PUBLIC void *ixOsalIoMemMap (UINT32 requestedAddress,
-			     UINT32 size,
-			     IxOsalMapEndianessType requestedCoherency);
-
-
-/* Internal function to unmap a memory zone mapped with ixOsalIoMemMap
- * NOTE - This should not be called by the user.
- * Use the macro IX_OSAL_MEM_UNMAP instead
- */
-PUBLIC void ixOsalIoMemUnmap (UINT32 requestedAddress, UINT32 coherency);
-
-
-/* Internal function to convert virtual address to physical address 
- * NOTE - This should not be called by the user.
- * Use the macro IX_OSAL_MMAP_VIRT_TO_PHYS */
-PUBLIC UINT32 ixOsalIoMemVirtToPhys (UINT32 virtualAddress, UINT32 coherency);
-
-
-/* Internal function to convert physical address to virtual address 
- * NOTE - This should not be called by the user.
- * Use the macro IX_OSAL_MMAP_PHYS_TO_VIRT */
-PUBLIC UINT32
-ixOsalIoMemPhysToVirt (UINT32 physicalAddress, UINT32 coherency);
-
-/**
- * @ingroup IxOsalIoMem
- *
- * @def IX_OSAL_MEM_MAP(physAddr, size)
- *
- * @brief Map an I/O mapped physical memory zone to virtual zone and return virtual
- *        pointer.
- * @param  physAddr - the physical address
- * @param  size     - the size
- * @return start address of the virtual memory zone.
- *
- * @note  This function maps an I/O mapped physical memory zone of the given size
- * into a virtual memory zone accessible by the caller and returns a cookie - 
- * the start address of the virtual memory zone. 
- * IX_OSAL_MMAP_PHYS_TO_VIRT should NOT therefore be used on the returned 
- * virtual address.
- * The memory zone is to be unmapped using IX_OSAL_MEM_UNMAP once the caller has
- * finished using this zone (e.g. on driver unload) using the cookie as 
- * parameter.
- * The IX_OSAL_READ/WRITE_LONG/SHORT macros should be used to read and write 
- * the mapped memory, adding the necessary offsets to the address cookie.
- */
-#define IX_OSAL_MEM_MAP(physAddr, size) \
-    ixOsalIoMemMap((physAddr), (size), IX_OSAL_COMPONENT_MAPPING)
-
-
-/**
- * @ingroup IxOsalIoMem
- *
- * @def IX_OSAL_MEM_UNMAP(virtAddr)
- *
- * @brief Unmap a previously mapped I/O memory zone using virtual pointer obtained
- *        during the mapping operation.
- *        pointer.
- * @param  virtAddr - the virtual pointer to the zone to be unmapped.
- * @return none
- *
- * @note  This function unmaps a previously mapped I/O memory zone using
- * the cookie obtained in the mapping operation. The memory zone in question
- * becomes unavailable to the caller once unmapped and the cookie should be
- * discarded.
- *
- * This function cannot fail if the given parameter is correct and does not
- * return a value.
- */
-#define IX_OSAL_MEM_UNMAP(virtAddr) \
-    ixOsalIoMemUnmap ((virtAddr), IX_OSAL_COMPONENT_MAPPING)
-
-/**
- * @ingroup IxOsalIoMem
- *
- * @def IX_OSAL_MMAP_VIRT_TO_PHYS(virtAddr)
- *
- * @brief This function Converts a virtual address into a physical 
- * address, including the dynamically mapped memory.
- *
- * @param  virtAddr - virtual address to convert
- * Return value: corresponding physical address, or NULL
- */
-#define IX_OSAL_MMAP_VIRT_TO_PHYS(virtAddr) \
-    ixOsalIoMemVirtToPhys(virtAddr, IX_OSAL_COMPONENT_MAPPING)
-
-
-/**
- * @ingroup IxOsalIoMem
- *
- * @def IX_OSAL_MMAP_PHYS_TO_VIRT(physAddr)
- *
- * @brief  This function Converts a virtual address into a physical 
- * address, including the dynamically mapped memory.
- *
- * @param  physAddr - physical address to convert
- * Return value: corresponding virtual address, or NULL
- *
- */
-#define IX_OSAL_MMAP_PHYS_TO_VIRT(physAddr) \
-    ixOsalIoMemPhysToVirt(physAddr, IX_OSAL_COMPONENT_MAPPING)
-
-/**
- * @} IxOsalIoMem
- */
-
-#endif /* IxOsalIoMem_H */
diff --git a/arch/arm/cpu/ixp/npe/include/IxOsalMemAccess.h b/arch/arm/cpu/ixp/npe/include/IxOsalMemAccess.h
deleted file mode 100644
index 9e7fb87..0000000
--- a/arch/arm/cpu/ixp/npe/include/IxOsalMemAccess.h
+++ /dev/null
@@ -1,494 +0,0 @@
-/** 
- * @file IxOsalMemAccess.h
- * 
- * @brief Header file for memory access
- * 
- * @par
- * @version $Revision: 1.0 $
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- * 
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- * 
- * @par
- * -- End of Copyright Notice --
- */
-
-#ifndef IxOsalMemAccess_H
-#define IxOsalMemAccess_H
-
-
-/* Global BE switch
- * 
- *  Should be set only in BE mode and only if the component uses I/O memory.
- */
-
-#if defined (__BIG_ENDIAN)
-
-#define IX_OSAL_BE_MAPPING
-
-#endif /* Global switch */
-
-
-/* By default only static memory maps in use;
-   define IX_OSAL_DYNAMIC_MEMORY_MAP per component if dynamic maps are
-   used instead in that component */
-#define IX_OSAL_STATIC_MEMORY_MAP
-
-
-/* 
- * SDRAM coherency mode
- * Must be defined to BE, LE_DATA_COHERENT or LE_ADDRESS_COHERENT.
- * The mode changes depending on OS 
- */
-#if defined (IX_OSAL_LINUX_BE) || defined (IX_OSAL_VXWORKS_BE)
-
-#define IX_SDRAM_BE
-
-#elif defined (IX_OSAL_VXWORKS_LE)
-
-#define IX_SDRAM_LE_DATA_COHERENT
-
-#elif defined (IX_OSAL_LINUX_LE)
-
-#define IX_SDRAM_LE_DATA_COHERENT
-
-#elif defined (IX_OSAL_WINCE_LE)
-
-#define IX_SDRAM_LE_DATA_COHERENT
-
-#elif defined (IX_OSAL_EBOOT_LE)
-
-#define IX_SDRAM_LE_ADDRESS_COHERENT
-
-#endif
-
-
-
-
-/**************************************
- * Retrieve current component mapping *
- **************************************/
-
-/*
- * Only use customized mapping for LE. 
- * 
- */
-#if defined (IX_OSAL_VXWORKS_LE) || defined (IX_OSAL_LINUX_LE) || defined (IX_OSAL_WINCE_LE) || defined (IX_OSAL_EBOOT_LE)
-
-#include "IxOsalOsIxp400CustomizedMapping.h"
-
-#endif
-
-
-/*******************************************************************
- * Turn off IX_STATIC_MEMORY map for components using dynamic maps *
- *******************************************************************/
-#ifdef IX_OSAL_DYNAMIC_MEMORY_MAP
-
-#undef IX_OSAL_STATIC_MEMORY_MAP
-
-#endif
-
-
-/************************************************************
- * Turn off BE access for components using LE or no mapping *
- ************************************************************/
-
-#if ( defined (IX_OSAL_LE_AC_MAPPING) || defined (IX_OSAL_LE_DC_MAPPING) || defined (IX_OSAL_NO_MAPPING) )
-
-#undef IX_OSAL_BE_MAPPING
-
-#endif
-
-
-/*****************
- * Safety checks *
- *****************/
-
-/* Default to no_mapping */
-#if !defined (IX_OSAL_BE_MAPPING) && !defined (IX_OSAL_LE_AC_MAPPING) && !defined (IX_OSAL_LE_DC_MAPPING) && !defined (IX_OSAL_NO_MAPPING)
-
-#define IX_OSAL_NO_MAPPING
-
-#endif /* check at least one mapping */
-
-/* No more than one mapping can be defined for a component */
-#if   (defined (IX_OSAL_BE_MAPPING)    && defined (IX_OSAL_LE_AC_MAPPING))  \
-    ||(defined (IX_OSAL_BE_MAPPING)    && defined (IX_OSAL_LE_DC_MAPPING))  \
-    ||(defined (IX_OSAL_BE_MAPPING)    && defined (IX_OSAL_NO_MAPPING))     \
-    ||(defined (IX_OSAL_LE_DC_MAPPING) && defined (IX_OSAL_NO_MAPPING))     \
-    ||(defined (IX_OSAL_LE_DC_MAPPING) && defined (IX_OSAL_LE_AC_MAPPING))	\
-    ||(defined (IX_OSAL_LE_AC_MAPPING) && defined (IX_OSAL_NO_MAPPING))
-
-
-#ifdef IX_OSAL_BE_MAPPING
-#warning IX_OSAL_BE_MAPPING is defined
-#endif
-
-#ifdef IX_OSAL_LE_AC_MAPPING
-#warning IX_OSAL_LE_AC_MAPPING is defined
-#endif
-
-#ifdef IX_OSAL_LE_DC_MAPPING
-#warning IX_OSAL_LE_DC_MAPPING is defined
-#endif
-
-#ifdef IX_OSAL_NO_MAPPING
-#warning IX_OSAL_NO_MAPPING is defined
-#endif
-
-#error More than one I/O mapping is defined, please check your component mapping
-
-#endif /* check at most one mapping */
-
-
-/* Now set IX_OSAL_COMPONENT_MAPPING */
-
-#ifdef IX_OSAL_BE_MAPPING
-#define IX_OSAL_COMPONENT_MAPPING IX_OSAL_BE
-#endif
-
-#ifdef IX_OSAL_LE_AC_MAPPING
-#define IX_OSAL_COMPONENT_MAPPING IX_OSAL_LE_AC
-#endif
-
-#ifdef IX_OSAL_LE_DC_MAPPING
-#define IX_OSAL_COMPONENT_MAPPING IX_OSAL_LE_DC
-#endif
-
-#ifdef IX_OSAL_NO_MAPPING
-#define IX_OSAL_COMPONENT_MAPPING IX_OSAL_LE
-#endif
-
-
-/* SDRAM coherency should be defined */
-#if !defined (IX_SDRAM_BE) && !defined (IX_SDRAM_LE_DATA_COHERENT) && !defined (IX_SDRAM_LE_ADDRESS_COHERENT)
-
-#error SDRAM coherency must be defined
-
-#endif /* SDRAM coherency must be defined */
-
-/* SDRAM coherency cannot be defined in several ways */
-#if (defined (IX_SDRAM_BE) && (defined (IX_SDRAM_LE_DATA_COHERENT) || defined (IX_SDRAM_LE_ADDRESS_COHERENT))) \
-    || (defined (IX_SDRAM_LE_DATA_COHERENT) && (defined (IX_SDRAM_BE) || defined (IX_SDRAM_LE_ADDRESS_COHERENT))) \
-    || (defined (IX_SDRAM_LE_ADDRESS_COHERENT) && (defined (IX_SDRAM_BE) || defined (IX_SDRAM_LE_DATA_COHERENT)))
-
-#error SDRAM coherency cannot be defined in more than one way
-
-#endif /* SDRAM coherency must be defined exactly once */
-
-
-/*********************
- * Read/write macros *
- *********************/
-
-/* WARNING - except for addition of special cookie read/write macros (see below)
-             these macros are NOT user serviceable. Please do not modify */
-
-#define IX_OSAL_READ_LONG_RAW(wAddr)          (*(wAddr))
-#define IX_OSAL_READ_SHORT_RAW(sAddr)         (*(sAddr))
-#define IX_OSAL_READ_BYTE_RAW(bAddr)          (*(bAddr))
-#define IX_OSAL_WRITE_LONG_RAW(wAddr, wData)  (*(wAddr) = (wData))
-#define IX_OSAL_WRITE_SHORT_RAW(sAddr,sData)  (*(sAddr) = (sData))
-#define IX_OSAL_WRITE_BYTE_RAW(bAddr, bData)  (*(bAddr) = (bData))
-
-#ifdef __linux
-
-/* Linux - specific cookie reads/writes. 
-  Redefine per OS if dynamic memory maps are used
-  and I/O memory is accessed via functions instead of raw pointer access. */
-
-#define IX_OSAL_READ_LONG_COOKIE(wCookie)           (readl((UINT32) (wCookie) ))
-#define IX_OSAL_READ_SHORT_COOKIE(sCookie)          (readw((UINT32) (sCookie) ))
-#define IX_OSAL_READ_BYTE_COOKIE(bCookie)           (readb((UINT32) (bCookie) ))
-#define IX_OSAL_WRITE_LONG_COOKIE(wCookie, wData)   (writel(wData, (UINT32) (wCookie) ))
-#define IX_OSAL_WRITE_SHORT_COOKIE(sCookie, sData)  (writew(sData, (UINT32) (sCookie) ))
-#define IX_OSAL_WRITE_BYTE_COOKIE(bCookie, bData)   (writeb(bData, (UINT32) (bCookie) ))
-
-#endif /* linux */
-
-#ifdef __wince
-
-/* WinCE - specific cookie reads/writes. */
-
-static __inline__ UINT32
-ixOsalWinCEReadLCookie (volatile UINT32 * lCookie)
-{
-    return *lCookie;
-}
-
-static __inline__ UINT16
-ixOsalWinCEReadWCookie (volatile UINT16 * wCookie)
-{
-#if 0
-    UINT32 auxVal = *((volatile UINT32 *) wCookie);
-    if ((unsigned) wCookie & 3)
-	return (UINT16) (auxVal >> 16);
-    else
-	return (UINT16) (auxVal & 0xffff);
-#else
-    return *wCookie;
-#endif
-}
-
-static __inline__ UINT8
-ixOsalWinCEReadBCookie (volatile UINT8 * bCookie)
-{
-#if 0
-    UINT32 auxVal = *((volatile UINT32 *) bCookie);
-    return (UINT8) ((auxVal >> (3 - (((unsigned) bCookie & 3) << 3)) & 0xff));
-#else
-    return *bCookie;
-#endif
-}
-
-static __inline__ void
-ixOsalWinCEWriteLCookie (volatile UINT32 * lCookie, UINT32 lVal)
-{
-    *lCookie = lVal;
-}
-
-static __inline__ void
-ixOsalWinCEWriteWCookie (volatile UINT16 * wCookie, UINT16 wVal)
-{
-#if 0
-    volatile UINT32 *auxCookie =
-	(volatile UINT32 *) ((unsigned) wCookie & ~3);
-    if ((unsigned) wCookie & 3)
-    {
-	*auxCookie &= 0xffff;
-	*auxCookie |= (UINT32) wVal << 16;
-    }
-    else
-    {
-	*auxCookie &= ~0xffff;
-	*auxCookie |= (UINT32) wVal & 0xffff;
-    }
-#else
-    *wCookie = wVal;
-#endif
-}
-
-static __inline__ void
-ixOsalWinCEWriteBCookie (volatile UINT8 * bCookie, UINT8 bVal)
-{
-#if 0
-    volatile UINT32 *auxCookie =
-	(volatile UINT32 *) ((unsigned) bCookie & ~3);
-    *auxCookie &= 0xff << (3 - (((unsigned) bCookie & 3) << 3));
-    *auxCookie |= (UINT32) bVal << (3 - (((unsigned) bCookie & 3) << 3));
-#else
-    *bCookie = bVal;
-#endif
-}
-
-
-#define IX_OSAL_READ_LONG_COOKIE(wCookie)           (ixOsalWinCEReadLCookie(wCookie))
-#define IX_OSAL_READ_SHORT_COOKIE(sCookie)          (ixOsalWinCEReadWCookie(sCookie))
-#define IX_OSAL_READ_BYTE_COOKIE(bCookie)           (ixOsalWinCEReadBCookie(bCookie))
-#define IX_OSAL_WRITE_LONG_COOKIE(wCookie, wData)   (ixOsalWinCEWriteLCookie(wCookie, wData))
-#define IX_OSAL_WRITE_SHORT_COOKIE(sCookie, sData)  (ixOsalWinCEWriteWCookie(sCookie, sData))
-#define IX_OSAL_WRITE_BYTE_COOKIE(bCookie, bData)   (ixOsalWinCEWriteBCookie(bCookie, bData))
-
-#endif /* wince */
-
-#if defined (__vxworks) || (defined (__linux) && defined (IX_OSAL_STATIC_MEMORY_MAP)) || \
-                           (defined (__wince) && defined (IX_OSAL_STATIC_MEMORY_MAP))
-
-#define IX_OSAL_READ_LONG_IO(wAddr)            IX_OSAL_READ_LONG_RAW(wAddr)
-#define IX_OSAL_READ_SHORT_IO(sAddr)           IX_OSAL_READ_SHORT_RAW(sAddr)
-#define IX_OSAL_READ_BYTE_IO(bAddr)            IX_OSAL_READ_BYTE_RAW(bAddr)
-#define IX_OSAL_WRITE_LONG_IO(wAddr, wData)    IX_OSAL_WRITE_LONG_RAW(wAddr, wData)
-#define IX_OSAL_WRITE_SHORT_IO(sAddr, sData)   IX_OSAL_WRITE_SHORT_RAW(sAddr, sData)
-#define IX_OSAL_WRITE_BYTE_IO(bAddr, bData)    IX_OSAL_WRITE_BYTE_RAW(bAddr, bData)
-
-#elif (defined (__linux) && !defined (IX_OSAL_STATIC_MEMORY_MAP)) || \
-      (defined (__wince) && !defined (IX_OSAL_STATIC_MEMORY_MAP))
-
-#ifndef __wince
-#include <asm/io.h>
-#endif /* ndef __wince */
-
-#define IX_OSAL_READ_LONG_IO(wAddr)            IX_OSAL_READ_LONG_COOKIE(wAddr)
-#define IX_OSAL_READ_SHORT_IO(sAddr)           IX_OSAL_READ_SHORT_COOKIE(sAddr)
-#define IX_OSAL_READ_BYTE_IO(bAddr)            IX_OSAL_READ_BYTE_COOKIE(bAddr)
-#define IX_OSAL_WRITE_LONG_IO(wAddr, wData)    IX_OSAL_WRITE_LONG_COOKIE(wAddr, wData)
-#define IX_OSAL_WRITE_SHORT_IO(sAddr, sData)   IX_OSAL_WRITE_SHORT_COOKIE(sAddr, sData)
-#define IX_OSAL_WRITE_BYTE_IO(bAddr, bData)    IX_OSAL_WRITE_BYTE_COOKIE(bAddr, bData)
-
-#endif
-
-/* Define BE macros */
-#define IX_OSAL_READ_LONG_BE(wAddr)          IX_OSAL_BE_BUSTOXSL(IX_OSAL_READ_LONG_IO((volatile UINT32 *) (wAddr) ))
-#define IX_OSAL_READ_SHORT_BE(sAddr)         IX_OSAL_BE_BUSTOXSS(IX_OSAL_READ_SHORT_IO((volatile UINT16 *) (sAddr) ))
-#define IX_OSAL_READ_BYTE_BE(bAddr)          IX_OSAL_BE_BUSTOXSB(IX_OSAL_READ_BYTE_IO((volatile UINT8 *) (bAddr) ))
-#define IX_OSAL_WRITE_LONG_BE(wAddr, wData)  IX_OSAL_WRITE_LONG_IO((volatile UINT32 *) (wAddr), IX_OSAL_BE_XSTOBUSL((UINT32) (wData) ))
-#define IX_OSAL_WRITE_SHORT_BE(sAddr, sData) IX_OSAL_WRITE_SHORT_IO((volatile UINT16 *) (sAddr), IX_OSAL_BE_XSTOBUSS((UINT16) (sData) ))
-#define IX_OSAL_WRITE_BYTE_BE(bAddr, bData)  IX_OSAL_WRITE_BYTE_IO((volatile UINT8 *) (bAddr), IX_OSAL_BE_XSTOBUSB((UINT8) (bData) ))
-
-/* Define LE AC macros */
-#define IX_OSAL_READ_LONG_LE_AC(wAddr)          IX_OSAL_READ_LONG_IO((volatile UINT32 *) IX_OSAL_LE_AC_BUSTOXSL((UINT32) (wAddr) ))
-#define IX_OSAL_READ_SHORT_LE_AC(sAddr)         IX_OSAL_READ_SHORT_IO((volatile UINT16 *) IX_OSAL_LE_AC_BUSTOXSS((UINT32) (sAddr) ))
-#define IX_OSAL_READ_BYTE_LE_AC(bAddr)          IX_OSAL_READ_BYTE_IO((volatile UINT8 *) IX_OSAL_LE_AC_BUSTOXSB((UINT32) (bAddr) ))
-#define IX_OSAL_WRITE_LONG_LE_AC(wAddr, wData)  IX_OSAL_WRITE_LONG_IO((volatile UINT32 *) IX_OSAL_LE_AC_XSTOBUSL((UINT32) (wAddr) ), (UINT32) (wData))
-#define IX_OSAL_WRITE_SHORT_LE_AC(sAddr, sData) IX_OSAL_WRITE_SHORT_IO((volatile UINT16 *) IX_OSAL_LE_AC_XSTOBUSS((UINT32) (sAddr) ), (UINT16) (sData))
-#define IX_OSAL_WRITE_BYTE_LE_AC(bAddr, bData)  IX_OSAL_WRITE_BYTE_IO((volatile UINT8 *) IX_OSAL_LE_AC_XSTOBUSB((UINT32) (bAddr) ), (UINT8) (bData))
-
-
-/* Inline functions are required here to avoid reading the same I/O location 2 or 4 times for the byte swap */
-static __inline__ UINT32
-ixOsalDataCoherentLongReadSwap (volatile UINT32 * wAddr)
-{
-    UINT32 wData = IX_OSAL_READ_LONG_IO (wAddr);
-    return IX_OSAL_LE_DC_BUSTOXSL (wData);
-}
-
-static __inline__ UINT16
-ixOsalDataCoherentShortReadSwap (volatile UINT16 * sAddr)
-{
-    UINT16 sData = IX_OSAL_READ_SHORT_IO (sAddr);
-    return IX_OSAL_LE_DC_BUSTOXSS (sData);
-}
-
-static __inline__ void
-ixOsalDataCoherentLongWriteSwap (volatile UINT32 * wAddr, UINT32 wData)
-{
-    wData = IX_OSAL_LE_DC_XSTOBUSL (wData);
-    IX_OSAL_WRITE_LONG_IO (wAddr, wData);
-}
-
-static __inline__ void
-ixOsalDataCoherentShortWriteSwap (volatile UINT16 * sAddr, UINT16 sData)
-{
-    sData = IX_OSAL_LE_DC_XSTOBUSS (sData);
-    IX_OSAL_WRITE_SHORT_IO (sAddr, sData);
-}
-
-/* Define LE DC macros */
-
-#define IX_OSAL_READ_LONG_LE_DC(wAddr)          ixOsalDataCoherentLongReadSwap((volatile UINT32 *) (wAddr) )
-#define IX_OSAL_READ_SHORT_LE_DC(sAddr)         ixOsalDataCoherentShortReadSwap((volatile UINT16 *) (sAddr) )
-#define IX_OSAL_READ_BYTE_LE_DC(bAddr)          IX_OSAL_LE_DC_BUSTOXSB(IX_OSAL_READ_BYTE_IO((volatile UINT8 *) (bAddr) ))
-#define IX_OSAL_WRITE_LONG_LE_DC(wAddr, wData)  ixOsalDataCoherentLongWriteSwap((volatile UINT32 *) (wAddr), (UINT32) (wData))
-#define IX_OSAL_WRITE_SHORT_LE_DC(sAddr, sData) ixOsalDataCoherentShortWriteSwap((volatile UINT16 *) (sAddr), (UINT16) (sData))
-#define IX_OSAL_WRITE_BYTE_LE_DC(bAddr, bData)  IX_OSAL_WRITE_BYTE_IO((volatile UINT8 *) (bAddr), IX_OSAL_LE_DC_XSTOBUSB((UINT8) (bData)))
-
-#if defined (IX_OSAL_BE_MAPPING)
-
-#define IX_OSAL_READ_LONG(wAddr)            IX_OSAL_READ_LONG_BE(wAddr) 
-#define IX_OSAL_READ_SHORT(sAddr)	        IX_OSAL_READ_SHORT_BE(sAddr) 
-#define IX_OSAL_READ_BYTE(bAddr)	        IX_OSAL_READ_BYTE_BE(bAddr) 
-#define IX_OSAL_WRITE_LONG(wAddr, wData)	IX_OSAL_WRITE_LONG_BE(wAddr, wData)
-#define IX_OSAL_WRITE_SHORT(sAddr, sData)	IX_OSAL_WRITE_SHORT_BE(sAddr, sData)
-#define IX_OSAL_WRITE_BYTE(bAddr, bData)	IX_OSAL_WRITE_BYTE_BE(bAddr, bData)
-
-#elif defined (IX_OSAL_LE_AC_MAPPING)
-
-#define IX_OSAL_READ_LONG(wAddr)            IX_OSAL_READ_LONG_LE_AC(wAddr) 
-#define IX_OSAL_READ_SHORT(sAddr)	        IX_OSAL_READ_SHORT_LE_AC(sAddr) 
-#define IX_OSAL_READ_BYTE(bAddr)	        IX_OSAL_READ_BYTE_LE_AC(bAddr) 
-#define IX_OSAL_WRITE_LONG(wAddr, wData)	IX_OSAL_WRITE_LONG_LE_AC(wAddr, wData)
-#define IX_OSAL_WRITE_SHORT(sAddr, sData)	IX_OSAL_WRITE_SHORT_LE_AC(sAddr, sData)
-#define IX_OSAL_WRITE_BYTE(bAddr, bData)	IX_OSAL_WRITE_BYTE_LE_AC(bAddr, bData)
-
-#elif defined (IX_OSAL_LE_DC_MAPPING)
-
-#define IX_OSAL_READ_LONG(wAddr)            IX_OSAL_READ_LONG_LE_DC(wAddr) 
-#define IX_OSAL_READ_SHORT(sAddr)	        IX_OSAL_READ_SHORT_LE_DC(sAddr) 
-#define IX_OSAL_READ_BYTE(bAddr)	        IX_OSAL_READ_BYTE_LE_DC(bAddr) 
-#define IX_OSAL_WRITE_LONG(wAddr, wData)	IX_OSAL_WRITE_LONG_LE_DC(wAddr, wData)
-#define IX_OSAL_WRITE_SHORT(sAddr, sData)	IX_OSAL_WRITE_SHORT_LE_DC(sAddr, sData)
-#define IX_OSAL_WRITE_BYTE(bAddr, bData)	IX_OSAL_WRITE_BYTE_LE_DC(bAddr, bData)
-
-#endif   /* End of BE and LE coherency mode switch */
-
-
-/* Reads/writes to and from memory shared with NPEs - depends on the SDRAM coherency */
-
-#if defined (IX_SDRAM_BE)
-
-#define IX_OSAL_READ_BE_SHARED_LONG(wAddr)            IX_OSAL_READ_LONG_RAW(wAddr)
-#define IX_OSAL_READ_BE_SHARED_SHORT(sAddr)           IX_OSAL_READ_SHORT_RAW(sAddr)
-#define IX_OSAL_READ_BE_SHARED_BYTE(bAddr)            IX_OSAL_READ_BYTE_RAW(bAddr)
-
-#define IX_OSAL_WRITE_BE_SHARED_LONG(wAddr, wData)    IX_OSAL_WRITE_LONG_RAW(wAddr, wData)
-#define IX_OSAL_WRITE_BE_SHARED_SHORT(sAddr, sData)   IX_OSAL_WRITE_SHORT_RAW(sAddr, sData)
-#define IX_OSAL_WRITE_BE_SHARED_BYTE(bAddr, bData)    IX_OSAL_WRITE_BYTE_RAW(bAddr, bData)
-
-#define IX_OSAL_SWAP_BE_SHARED_LONG(wData)            (wData)
-#define IX_OSAL_SWAP_BE_SHARED_SHORT(sData)           (sData)
-#define IX_OSAL_SWAP_BE_SHARED_BYTE(bData)            (bData)
-
-#elif defined (IX_SDRAM_LE_ADDRESS_COHERENT)
-
-#define IX_OSAL_READ_BE_SHARED_LONG(wAddr)            IX_OSAL_READ_LONG_RAW(wAddr)
-#define IX_OSAL_READ_BE_SHARED_SHORT(sAddr)           IX_OSAL_READ_SHORT_RAW(IX_OSAL_SWAP_SHORT_ADDRESS(sAddr))
-#define IX_OSAL_READ_BE_SHARED_BYTE(bAddr)            IX_OSAL_READ_BYTE_RAW(IX_OSAL_SWAP_BYTE_ADDRESS(bAddr))
-
-#define IX_OSAL_WRITE_BE_SHARED_LONG(wAddr, wData)    IX_OSAL_WRITE_LONG_RAW(wAddr, wData)
-#define IX_OSAL_WRITE_BE_SHARED_SHORT(sAddr, sData)   IX_OSAL_WRITE_SHORT_RAW(IX_OSAL_SWAP_SHORT_ADDRESS(sAddr), sData)
-#define IX_OSAL_WRITE_BE_SHARED_BYTE(bAddr, bData)    IX_OSAL_WRITE_BYTE_RAW(IX_OSAL_SWAP_BYTE_ADDRESS(bAddr), bData)
-
-#define IX_OSAL_SWAP_BE_SHARED_LONG(wData)            (wData)
-#define IX_OSAL_SWAP_BE_SHARED_SHORT(sData)           (sData)
-#define IX_OSAL_SWAP_BE_SHARED_BYTE(bData)            (bData)
-
-#elif defined (IX_SDRAM_LE_DATA_COHERENT)
-
-#define IX_OSAL_READ_BE_SHARED_LONG(wAddr)            IX_OSAL_SWAP_LONG(IX_OSAL_READ_LONG_RAW(wAddr))
-#define IX_OSAL_READ_BE_SHARED_SHORT(sAddr)           IX_OSAL_SWAP_SHORT(IX_OSAL_READ_SHORT_RAW(sAddr))
-#define IX_OSAL_READ_BE_SHARED_BYTE(bAddr)            IX_OSAL_READ_BYTE_RAW(bAddr)
-
-#define IX_OSAL_WRITE_BE_SHARED_LONG(wAddr, wData)    IX_OSAL_WRITE_LONG_RAW(wAddr, IX_OSAL_SWAP_LONG(wData))
-#define IX_OSAL_WRITE_BE_SHARED_SHORT(sAddr, sData)   IX_OSAL_WRITE_SHORT_RAW(sAddr, IX_OSAL_SWAP_SHORT(sData))
-#define IX_OSAL_WRITE_BE_SHARED_BYTE(bAddr, bData)    IX_OSAL_WRITE_BYTE_RAW(bAddr, bData)
-
-#define IX_OSAL_SWAP_BE_SHARED_LONG(wData)            IX_OSAL_SWAP_LONG(wData)
-#define IX_OSAL_SWAP_BE_SHARED_SHORT(sData)           IX_OSAL_SWAP_SHORT(sData)
-
-#endif
-
-
-#define IX_OSAL_COPY_BE_SHARED_LONG_ARRAY(wDestAddr, wSrcAddr, wCount) \
-  { \
-    UINT32 i; \
-    \
-    for ( i = 0 ; i < wCount ; i++ ) \
-    { \
-      * (((UINT32 *) wDestAddr) + i) = IX_OSAL_READ_BE_SHARED_LONG(((UINT32 *) wSrcAddr) + i); \
-    }; \
-  };
-
-#endif /* IxOsalMemAccess_H */
diff --git a/arch/arm/cpu/ixp/npe/include/IxOsalOem.h b/arch/arm/cpu/ixp/npe/include/IxOsalOem.h
deleted file mode 100644
index f894026..0000000
--- a/arch/arm/cpu/ixp/npe/include/IxOsalOem.h
+++ /dev/null
@@ -1,97 +0,0 @@
-/**
- * @file IxOsalIxpOem.h
- *
- * @brief this file contains platform-specific defines.
- * 
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- * 
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- * 
- * @par
- * -- End of Copyright Notice --
- */
-
-#ifndef IxOsalOem_H
-#define IxOsalOem_H
-
-#include "IxOsalTypes.h"
-
-/* OS-specific header for Platform package */
-#include "IxOsalOsIxp400.h"
-
-/*
- * Platform Name
- */
-#define IX_OSAL_PLATFORM_NAME ixp400
-
-/*
- * Cache line size
- */
-#define IX_OSAL_CACHE_LINE_SIZE (32)
-
-
-/* Platform-specific fastmutex implementation */
-PUBLIC IX_STATUS ixOsalOemFastMutexTryLock (IxOsalFastMutex * mutex);
-
-/* Platform-specific init (MemMap) */
-PUBLIC IX_STATUS
-ixOsalOemInit (void);
-
-/* Platform-specific unload (MemMap) */
-PUBLIC void
-ixOsalOemUnload (void);
-
-/* Default implementations */
-
-PUBLIC UINT32
-ixOsalIxp400SharedTimestampGet (void);
-
-
-UINT32
-ixOsalIxp400SharedTimestampRateGet (void);
-
-UINT32
-ixOsalIxp400SharedSysClockRateGet (void);
-
-void
-ixOsalIxp400SharedTimeGet (IxOsalTimeval * tv);
-
-
-INT32
-ixOsalIxp400SharedLog (UINT32 level, UINT32 device, char *format, 
-                       int arg1, int arg2, int arg3, int arg4, 
-                       int arg5, int arg6);
-
-#endif /* IxOsal_Oem_H */
diff --git a/arch/arm/cpu/ixp/npe/include/IxOsalOs.h b/arch/arm/cpu/ixp/npe/include/IxOsalOs.h
deleted file mode 100644
index 6c66613..0000000
--- a/arch/arm/cpu/ixp/npe/include/IxOsalOs.h
+++ /dev/null
@@ -1,30 +0,0 @@
-#ifndef IxOsalOs_H
-#define IxOsalOs_H
-
-#ifndef IX_OSAL_CACHED
-#error "Uncached memory not supported in linux environment"
-#endif
-
-static inline unsigned long __v2p(unsigned long v)
-{
-	if (v < 0x40000000)
-		return (v & 0xfffffff);
-	else
-		return v;
-}
-
-#define IX_OSAL_OS_MMU_VIRT_TO_PHYS(addr)        __v2p((u32)addr)
-#define IX_OSAL_OS_MMU_PHYS_TO_VIRT(addr)        (addr)
-
-/*
- * Data cache not enabled (hopefully)
- */
-#define IX_OSAL_OS_CACHE_INVALIDATE(addr, size)
-#define IX_OSAL_OS_CACHE_FLUSH(addr, size)
-#define HAL_DCACHE_INVALIDATE(addr, size)
-#define HAL_DCACHE_FLUSH(addr, size)
-
-#define __ixp42X			/* sr: U-Boot needs this define */
-
-#endif /* IxOsalOs_H */
-
diff --git a/arch/arm/cpu/ixp/npe/include/IxOsalOsAssert.h b/arch/arm/cpu/ixp/npe/include/IxOsalOsAssert.h
deleted file mode 100644
index e4c3e1f..0000000
--- a/arch/arm/cpu/ixp/npe/include/IxOsalOsAssert.h
+++ /dev/null
@@ -1,10 +0,0 @@
-#ifndef IxOsalOsAssert_H
-#define IxOsalOsAssert_H
-
-#define IX_OSAL_OS_ASSERT(c)    if(!(c)) \
-                                { \
-                                    ixOsalLog (IX_OSAL_LOG_LVL_ERROR, IX_OSAL_LOG_DEV_STDOUT, "Assertion failure \n", 0, 0, 0, 0, 0, 0);\
-                                    while(1); \
-                                }
-
-#endif /* IxOsalOsAssert_H */
diff --git a/arch/arm/cpu/ixp/npe/include/IxOsalOsBufferMgt.h b/arch/arm/cpu/ixp/npe/include/IxOsalOsBufferMgt.h
deleted file mode 100644
index 8e46586..0000000
--- a/arch/arm/cpu/ixp/npe/include/IxOsalOsBufferMgt.h
+++ /dev/null
@@ -1,96 +0,0 @@
-/**
- * @file IxOsalOsBufferMgt.h
- *
- * @brief vxworks-specific buffer management module definitions.
- *
- * Design Notes:
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
- */
-
-
-#ifndef IX_OSAL_OS_BUFFER_MGT_H
-#define IX_OSAL_OS_BUFFER_MGT_H
-
-/*
- * use the defaul bufferMgt provided by OSAL framework.
- */
-#define IX_OSAL_USE_DEFAULT_BUFFER_MGT
-
-#include "IxOsalBufferMgtDefault.h"
-
-#if 0  /* FIXME */
-/* Define os-specific buffer macros for subfields */
-#define IX_OSAL_OSBUF_MDATA(osBufPtr) IX_OSAL_MBUF_MDATA(osBufPtr)
-             ( ((M_BLK *) osBufPtr)->m_data )
-
-#define IX_OSAL_OSBUF_MLEN(osBufPtr) \
-             ( ((M_BLK *) osBufPtr)->m_len )
-
-#define IX_OSAL_OSBUF_PKT_LEN(osBufPtr) \
-             ( ((M_BLK *) osBufPtr)->m_pkthdr.len )
-
-#define IX_OSAL_OS_CONVERT_OSBUF_TO_IXPBUF( osBufPtr, ixpBufPtr) \
-        { \
-            IX_OSAL_MBUF_OSBUF_PTR( (IX_OSAL_MBUF *) ixpBufPtr) = (void *) osBufPtr; \
-            IX_OSAL_MBUF_MDATA((IX_OSAL_MBUF *) ixpBufPtr) =  IX_OSAL_OSBUF_MDATA(osBufPtr); \
-            IX_OSAL_MBUF_PKT_LEN((IX_OSAL_MBUF *) ixpBufPtr) = IX_OSAL_OSBUF_PKT_LEN(osBufPtr); \
-            IX_OSAL_MBUF_MLEN((IX_OSAL_MBUF *) ixpBufPtr) = IX_OSAL_OSBUF_MLEN(osBufPtr); \
-        }
-
-#define IX_OSAL_OS_CONVERT_IXPBUF_TO_OSBUF( ixpBufPtr, osBufPtr) \
-        { \
-            if (ixpBufPtr == NULL) \
-            { /* Do nothing */ } \
-            else \
-            { \
-                (M_BLK *) osBufPtr = (M_BLK *) IX_OSAL_MBUF_OSBUF_PTR((IX_OSAL_MBUF *) ixpBufPtr); \
-                if (osBufPtr == NULL) \
-                { /* Do nothing */ } \
-                else \
-                { \
-                    IX_OSAL_OSBUF_MLEN(osBufPtr) =IX_OSAL_MBUF_MLEN((IX_OSAL_MBUF *) ixpBufPtr); \
-                    IX_OSAL_OSBUF_PKT_LEN(osBufPtr) =IX_OSAL_MBUF_PKT_LEN((IX_OSAL_MBUF *) ixpBufPtr); \
-                } \
-            } \
-        }
-
-#endif /* FIXME */
-
-#endif /* #define IX_OSAL_OS_BUFFER_MGT_H */
diff --git a/arch/arm/cpu/ixp/npe/include/IxOsalOsIxp400.h b/arch/arm/cpu/ixp/npe/include/IxOsalOsIxp400.h
deleted file mode 100644
index 44a94fb..0000000
--- a/arch/arm/cpu/ixp/npe/include/IxOsalOsIxp400.h
+++ /dev/null
@@ -1,316 +0,0 @@
-/**
- * @file IxOsalOsIxp400.h
- *
- * @brief OS and platform specific definitions
- *
- * Design Notes:
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
- */
-
-#ifndef IxOsalOsIxp400_H
-#define IxOsalOsIxp400_H
-
-#define BIT(x) (1<<(x))
-
-#define IXP425_EthA_BASE	0xc8009000
-#define IXP425_EthB_BASE	0xc800a000
-
-#define IXP425_PSMA_BASE	0xc8006000
-#define IXP425_PSMB_BASE	0xc8007000
-#define IXP425_PSMC_BASE	0xc8008000
-
-#define IXP425_PERIPHERAL_BASE	0xc8000000
-
-#define IXP425_QMGR_BASE	0x60000000
-#define IXP425_OSTS		0xC8005000
-
-#define IXP425_INT_LVL_NPEA	0
-#define IXP425_INT_LVL_NPEB	1
-#define IXP425_INT_LVL_NPEC	2
-
-#define IXP425_INT_LVL_QM1	3
-#define IXP425_INT_LVL_QM2	4
-
-#define IXP425_EXPANSION_BUS_BASE1	0x50000000
-#define IXP425_EXPANSION_BUS_BASE2	0x50000000
-#define IXP425_EXPANSION_BUS_CS1_BASE	0x51000000
-
-#define IXP425_EXP_CONFIG_BASE		0xC4000000
-
-/* physical addresses to be used when requesting memory with IX_OSAL_MEM_MAP */
-#define IX_OSAL_IXP400_INTC_PHYS_BASE          IXP425_INTC_BASE
-#define IX_OSAL_IXP400_GPIO_PHYS_BASE          IXP425_GPIO_BASE
-#define IX_OSAL_IXP400_UART1_PHYS_BASE         IXP425_UART1_BASE
-#define IX_OSAL_IXP400_UART2_PHYS_BASE         IXP425_UART2_BASE
-#define IX_OSAL_IXP400_ETHA_PHYS_BASE          IXP425_EthA_BASE
-#define IX_OSAL_IXP400_ETHB_PHYS_BASE          IXP425_EthB_BASE
-#define IX_OSAL_IXP400_NPEA_PHYS_BASE          IXP425_NPEA_BASE
-#define IX_OSAL_IXP400_NPEB_PHYS_BASE          IXP425_NPEB_BASE
-#define IX_OSAL_IXP400_NPEC_PHYS_BASE          IXP425_NPEC_BASE
-#define IX_OSAL_IXP400_PERIPHERAL_PHYS_BASE    IXP425_PERIPHERAL_BASE
-#define IX_OSAL_IXP400_QMGR_PHYS_BASE          IXP425_QMGR_BASE
-#define IX_OSAL_IXP400_OSTS_PHYS_BASE          IXP425_TIMER_BASE
-#define IX_OSAL_IXP400_USB_PHYS_BASE           IXP425_USB_BASE
-#define IX_OSAL_IXP400_EXP_CFG_PHYS_BASE       IXP425_EXP_CFG_BASE
-#define IX_OSAL_IXP400_EXP_BUS_PHYS_BASE       IXP425_EXP_BUS_BASE2
-#define IX_OSAL_IXP400_EXP_BUS_BOOT_PHYS_BASE  IXP425_EXP_BUS_BASE1
-#define IX_OSAL_IXP400_EXP_BUS_CS0_PHYS_BASE   IXP425_EXP_BUS_CS0_BASE
-#define IX_OSAL_IXP400_EXP_BUS_CS1_PHYS_BASE   IXP425_EXP_BUS_CS1_BASE
-#define IX_OSAL_IXP400_EXP_BUS_CS4_PHYS_BASE   IXP425_EXP_BUS_CS4_BASE
-#define IX_OSAL_IXP400_EXP_BUS_REGS_PHYS_BASE  IXP425_EXP_CFG_BASE
-#define IX_OSAL_IXP400_PCI_CFG_PHYS_BASE       IXP425_PCI_CFG_BASE
-
-/* map sizes to be used when requesting memory with IX_OSAL_MEM_MAP */
-#define IX_OSAL_IXP400_QMGR_MAP_SIZE        (0x4000)	 /**< Queue Manager map size */
-#define IX_OSAL_IXP400_PERIPHERAL_MAP_SIZE  (0xC000)	 /**< Peripheral space map size */
-#define IX_OSAL_IXP400_UART1_MAP_SIZE       (0x1000)	 /**< UART1 map size */
-#define IX_OSAL_IXP400_UART2_MAP_SIZE       (0x1000)	 /**< UART2 map size */
-#define IX_OSAL_IXP400_PMU_MAP_SIZE         (0x1000)	 /**< PMU map size */
-#define IX_OSAL_IXP400_OSTS_MAP_SIZE        (0x1000)	 /**< OS Timers map size */
-#define IX_OSAL_IXP400_NPEA_MAP_SIZE        (0x1000)	 /**< NPE A map size */
-#define IX_OSAL_IXP400_NPEB_MAP_SIZE        (0x1000)	 /**< NPE B map size */
-#define IX_OSAL_IXP400_NPEC_MAP_SIZE        (0x1000)	 /**< NPE C map size */
-#define IX_OSAL_IXP400_ETHA_MAP_SIZE        (0x1000)	 /**< Eth A map size */
-#define IX_OSAL_IXP400_ETHB_MAP_SIZE        (0x1000)	 /**< Eth B map size */
-#define IX_OSAL_IXP400_USB_MAP_SIZE         (0x1000)	 /**< USB map size */
-#define IX_OSAL_IXP400_GPIO_MAP_SIZE        (0x1000)	 /**< GPIO map size */
-#define IX_OSAL_IXP400_EXP_REG_MAP_SIZE     (0x1000)	 /**< Exp Bus Config Registers map size */
-#define IX_OSAL_IXP400_EXP_BUS_MAP_SIZE     (0x08000000) /**< Expansion bus map size */
-#define IX_OSAL_IXP400_EXP_BUS_CS0_MAP_SIZE (0x01000000) /**< CS0 map size */
-#define IX_OSAL_IXP400_EXP_BUS_CS1_MAP_SIZE (0x01000000) /**< CS1 map size */
-#define IX_OSAL_IXP400_EXP_BUS_CS4_MAP_SIZE (0x01000000) /**< CS4 map size */
-#define IX_OSAL_IXP400_PCI_CFG_MAP_SIZE     (0x1000)	 /**< PCI Bus Config Registers map size */
-
-#define IX_OSAL_IXP400_EXP_FUSE             (IXP425_EXP_CONFIG_BASE + 0x28)
-#define IX_OSAL_IXP400_ETH_NPEA_PHYS_BASE   0xC800C000
-#define IX_OSAL_IXP400_ETH_NPEA_MAP_SIZE    0x1000
-
-/*
- * Interrupt Levels
- */
-#define IX_OSAL_IXP400_NPEA_IRQ_LVL		(0)
-#define IX_OSAL_IXP400_NPEB_IRQ_LVL		(1)
-#define IX_OSAL_IXP400_NPEC_IRQ_LVL		(2)
-#define IX_OSAL_IXP400_QM1_IRQ_LVL		(3)
-#define IX_OSAL_IXP400_QM2_IRQ_LVL		(4)
-#define IX_OSAL_IXP400_TIMER1_IRQ_LVL		(5)
-#define IX_OSAL_IXP400_GPIO0_IRQ_LVL		(6)
-#define IX_OSAL_IXP400_GPIO1_IRQ_LVL		(7)
-#define IX_OSAL_IXP400_PCI_INT_IRQ_LVL		(8)
-#define IX_OSAL_IXP400_PCI_DMA1_IRQ_LVL		(9)
-#define IX_OSAL_IXP400_PCI_DMA2_IRQ_LVL		(10)
-#define IX_OSAL_IXP400_TIMER2_IRQ_LVL		(11)
-#define IX_OSAL_IXP400_USB_IRQ_LVL		(12)
-#define IX_OSAL_IXP400_UART2_IRQ_LVL		(13)
-#define IX_OSAL_IXP400_TIMESTAMP_IRQ_LVL	(14)
-#define IX_OSAL_IXP400_UART1_IRQ_LVL		(15)
-#define IX_OSAL_IXP400_WDOG_IRQ_LVL		(16)
-#define IX_OSAL_IXP400_AHB_PMU_IRQ_LVL		(17)
-#define IX_OSAL_IXP400_XSCALE_PMU_IRQ_LVL	(18)
-#define IX_OSAL_IXP400_GPIO2_IRQ_LVL		(19)
-#define IX_OSAL_IXP400_GPIO3_IRQ_LVL		(20)
-#define IX_OSAL_IXP400_GPIO4_IRQ_LVL		(21)
-#define IX_OSAL_IXP400_GPIO5_IRQ_LVL		(22)
-#define IX_OSAL_IXP400_GPIO6_IRQ_LVL		(23)
-#define IX_OSAL_IXP400_GPIO7_IRQ_LVL		(24)
-#define IX_OSAL_IXP400_GPIO8_IRQ_LVL		(25)
-#define IX_OSAL_IXP400_GPIO9_IRQ_LVL		(26)
-#define IX_OSAL_IXP400_GPIO10_IRQ_LVL		(27)
-#define IX_OSAL_IXP400_GPIO11_IRQ_LVL		(28)
-#define IX_OSAL_IXP400_GPIO12_IRQ_LVL		(29)
-#define IX_OSAL_IXP400_SW_INT1_IRQ_LVL		(30)
-#define IX_OSAL_IXP400_SW_INT2_IRQ_LVL		(31)
-
-/* USB interrupt level mask */
-#define IX_OSAL_IXP400_INT_LVL_USB             IRQ_IXP425_USB
-
-/* USB IRQ */
-#define IX_OSAL_IXP400_USB_IRQ                 IRQ_IXP425_USB
-
-/*
- * OS name retrieval
- */
-#define IX_OSAL_OEM_OS_NAME_GET(name, limit) \
-ixOsalOsIxp400NameGet((INT8*)(name), (INT32) (limit))
-
-/*
- * OS version retrieval
- */
-#define IX_OSAL_OEM_OS_VERSION_GET(version, limit) \
-ixOsalOsIxp400VersionGet((INT8*)(version), (INT32) (limit))
-
-/*
- * Function to retrieve the OS name
- */
-PUBLIC IX_STATUS ixOsalOsIxp400NameGet(INT8* osName, INT32 maxSize);
-
-/*
- * Function to retrieve the OS version
- */
-PUBLIC IX_STATUS ixOsalOsIxp400VersionGet(INT8* osVersion, INT32 maxSize);
-
-/*
- * TimestampGet
- */
-PUBLIC UINT32 ixOsalOsIxp400TimestampGet (void);
-
-/*
- * Timestamp
- */
-#define IX_OSAL_OEM_TIMESTAMP_GET ixOsalOsIxp400TimestampGet
-
-
-/*
- * Timestamp resolution
- */
-PUBLIC UINT32 ixOsalOsIxp400TimestampResolutionGet (void);
-
-#define IX_OSAL_OEM_TIMESTAMP_RESOLUTION_GET ixOsalOsIxp400TimestampResolutionGet
-
-/*
- * Retrieves the system clock rate
- */
-PUBLIC UINT32 ixOsalOsIxp400SysClockRateGet (void);
-
-#define IX_OSAL_OEM_SYS_CLOCK_RATE_GET ixOsalOsIxp400SysClockRateGet
-
-/*
- * required by FS but is not really platform-specific.
- */
-#define IX_OSAL_OEM_TIME_GET(pTv) ixOsalTimeGet(pTv)
-
-
-
-/* linux map/unmap functions */
-PUBLIC void ixOsalLinuxMemMap (IxOsalMemoryMap * map);
-
-PUBLIC void ixOsalLinuxMemUnmap (IxOsalMemoryMap * map);
-
-
-/*********************
- *	Memory map
- ********************/
-
-/* Global memmap only visible to IO MEM module */
-
-#ifdef IxOsalIoMem_C
-
-IxOsalMemoryMap ixOsalGlobalMemoryMap[] = {
-     {
-     /* Global BE and LE_AC map */
-     IX_OSAL_STATIC_MAP,	/* type            */
-     0x00000000,		/* physicalAddress */
-     0x30000000,		/* size            */
-     0x00000000,		/* virtualAddress  */
-     NULL,			/* mapFunction     */
-     NULL,			/* unmapFunction   */
-     0,				/* refCount        */
-     IX_OSAL_BE | IX_OSAL_LE_AC,/* endianType      */
-     "global_low"		/* name            */
-     },
-
-    /* SDRAM LE_DC alias */
-    {
-     IX_OSAL_STATIC_MAP,	/* type            */
-     0x00000000,		/* physicalAddress */
-     0x10000000,		/* size            */
-     0x30000000,		/* virtualAddress  */
-     NULL,			/* mapFunction     */
-     NULL,			/* unmapFunction   */
-     0,				/* refCount        */
-     IX_OSAL_LE_DC,		/* endianType      */
-     "sdram_dc"			/* name            */
-     },
-
-    /* QMGR LE_DC alias */
-    {
-     IX_OSAL_STATIC_MAP,	/* type            */
-     0x60000000,		/* physicalAddress */
-     0x00100000,		/* size            */
-     0x60000000,		/* virtualAddress  */
-     NULL,			/* mapFunction     */
-     NULL,			/* unmapFunction   */
-     0,				/* refCount        */
-     IX_OSAL_LE_DC,		/* endianType      */
-     "qmgr_dc"			/* name            */
-     },
-
-    /* QMGR BE alias */
-    {
-     IX_OSAL_STATIC_MAP,	/* type            */
-     0x60000000,		/* physicalAddress */
-     0x00100000,		/* size            */
-     0x60000000,		/* virtualAddress  */
-     NULL,			/* mapFunction     */
-     NULL,			/* unmapFunction   */
-     0,				/* refCount        */
-     IX_OSAL_BE | IX_OSAL_LE_AC,/* endianType      */
-     "qmgr_be"			/* name            */
-     },
-
-    /* Global BE and LE_AC map */
-    {
-     IX_OSAL_STATIC_MAP,	/* type            */
-     0x40000000,		/* physicalAddress */
-     0x20000000,		/* size            */
-     0x40000000,		/* virtualAddress  */
-     NULL,			/* mapFunction     */
-     NULL,			/* unmapFunction   */
-     0,				/* refCount        */
-     IX_OSAL_BE | IX_OSAL_LE_AC,/* endianType      */
-     "Misc Cfg"			/* name            */
-     },
-
-    /* Global BE and LE_AC map */
-    {
-     IX_OSAL_STATIC_MAP,	/* type            */
-     0x70000000,		/* physicalAddress */
-     0x8FFFFFFF,		/* size            */
-     0x70000000,		/* virtualAddress  */
-     NULL,			/* mapFunction     */
-     NULL,			/* unmapFunction   */
-     0,				/* refCount        */
-     IX_OSAL_BE | IX_OSAL_LE_AC,/* endianType      */
-     "Exp Cfg"			/* name            */
-     },
-};
-
-#endif /* IxOsalIoMem_C */
-#endif /* #define IxOsalOsIxp400_H */
diff --git a/arch/arm/cpu/ixp/npe/include/IxOsalOsIxp400CustomizedMapping.h b/arch/arm/cpu/ixp/npe/include/IxOsalOsIxp400CustomizedMapping.h
deleted file mode 100644
index 47ce3a2..0000000
--- a/arch/arm/cpu/ixp/npe/include/IxOsalOsIxp400CustomizedMapping.h
+++ /dev/null
@@ -1,404 +0,0 @@
-/**
- * @file IxOsalOsIxp400CustomizedMapping.h 
- *
- * @brief Set LE coherency modes for components. 
- *        The default setting is IX_OSAL_NO_MAPPING for LE.
- * 
- *
- *		  By default IX_OSAL_STATIC_MEMORY_MAP is defined for all the components.
- *		  If any component uses a dynamic memory map it must define
- *		  IX_OSAL_DYNAMIC_MEMORY_MAP in its corresponding section.
- *        
- *
- * @par
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- * 
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- * 
- * @par
- * -- End of Copyright Notice --
- */
-
-#ifndef IxOsalOsIxp400CustomizedMapping_H
-#define IxOsalOsIxp400CustomizedMapping_H
-
-/*
- * only include this file in Little Endian
- */
-
-#if defined (IX_OSAL_LINUX_BE)
-#error Only include IxOsalOsIxp400CustomizedMapping.h in Little Endian
-#endif
-
- /*
-  * Components don't have to be in this list if
-  * the default mapping is OK.
-  */
-#define ix_osal                1
-#define ix_dmaAcc              2
-#define ix_atmdAcc             3
-
-#define ix_atmsch              5
-#define ix_ethAcc              6
-#define ix_npeMh               7
-#define ix_qmgr                8
-#define ix_npeDl               9
-#define ix_atmm                10
-#define ix_hssAcc              11
-#define ix_ethDB               12
-#define ix_ethMii              13
-#define ix_timerCtrl           14
-#define ix_adsl                15
-#define ix_usb                 16
-#define ix_uartAcc             17
-#define ix_featureCtrl         18
-#define ix_cryptoAcc           19
-#define ix_unloadAcc           33
-#define ix_perfProfAcc         34
-#define ix_parityENAcc                 49
-#define ix_sspAcc                      51
-#define ix_timeSyncAcc                 52
-#define ix_i2c                         53
-
-#define ix_codelets_uartAcc    21
-#define ix_codelets_timers     22
-#define ix_codelets_atm        23
-#define ix_codelets_ethAal5App 24
-#define ix_codelets_demoUtils  26
-#define ix_codelets_usb        27
-#define ix_codelets_hssAcc     28
-#define ix_codelets_dmaAcc         40
-#define ix_codelets_cryptoAcc	   41
-#define ix_codelets_perfProfAcc    42
-#define ix_codelets_ethAcc         43
-#define ix_codelets_parityENAcc        54
-#define ix_codelets_timeSyncAcc        55
-
-
-#endif /* IxOsalOsIxp400CustomizedMapping_H */
-
-
-/***************************
- * osal
- ***************************/
-#if (IX_COMPONENT_NAME == ix_osal)
-
-#define IX_OSAL_LE_AC_MAPPING
-
-#endif /* osal */
-
-/***************************
- * dmaAcc
- ***************************/
-#if (IX_COMPONENT_NAME == ix_dmaAcc)
-
-#define IX_OSAL_LE_AC_MAPPING
-
-#endif /* dmaAcc */
-
-/***************************
- * atmdAcc
- ***************************/
-#if (IX_COMPONENT_NAME == ix_atmdAcc)
-
-#define IX_OSAL_LE_AC_MAPPING
-
-#endif /* atmdAcc */
-
-/***************************
- * atmsch
- ***************************/
-#if (IX_COMPONENT_NAME == ix_atmsch)
-
-#define IX_OSAL_LE_AC_MAPPING
-
-#endif /* atmsch */
-
-/***************************
- * ethAcc
- ***************************/
-#if (IX_COMPONENT_NAME == ix_ethAcc)
-
-#define IX_OSAL_LE_AC_MAPPING
-
-#endif /* ethAcc */
-
-/***************************
- * npeMh
- ***************************/
-#if (IX_COMPONENT_NAME == ix_npeMh)
-
-#define IX_OSAL_LE_AC_MAPPING
-
-#endif /* npeMh */
-
-/***************************
- * qmgr
- ***************************/
-#if (IX_COMPONENT_NAME == ix_qmgr)
-
-#define IX_OSAL_LE_DC_MAPPING
-
-#endif /* qmgr */
-
-/***************************
- * npeDl
- ***************************/
-#if (IX_COMPONENT_NAME == ix_npeDl)
-
-#define IX_OSAL_LE_AC_MAPPING
-
-#endif /* npeDl */
-
-/***************************
- * atmm
- ***************************/
-#if (IX_COMPONENT_NAME == ix_atmm)
-
-#define IX_OSAL_LE_AC_MAPPING
-
-#endif /* atmm */
-
-/***************************
- * ethMii
- ***************************/
-#if (IX_COMPONENT_NAME == ix_ethMii)
-
-#define IX_OSAL_LE_AC_MAPPING
-
-#endif /* ethMii */
-
-
-/***************************
- * adsl
- ***************************/
-#if (IX_COMPONENT_NAME == ix_adsl)
-
-#define IX_OSAL_LE_AC_MAPPING
-
-#endif /* adsl */
-
-/***************************
- * usb
- ***************************/
-#if (IX_COMPONENT_NAME == ix_usb)
-
-#define IX_OSAL_LE_AC_MAPPING
-
-#endif /* usb */
-
-/***************************
- * uartAcc
- ***************************/
-#if (IX_COMPONENT_NAME == ix_uartAcc)
-
-#define IX_OSAL_LE_AC_MAPPING
-
-#endif /* uartAcc */
-
-/***************************
- * featureCtrl
- ***************************/
-#if (IX_COMPONENT_NAME == ix_featureCtrl)
-
-#define IX_OSAL_LE_AC_MAPPING
-
-#endif /* featureCtrl */
-
-/***************************
- * cryptoAcc
- ***************************/
-#if (IX_COMPONENT_NAME == ix_cryptoAcc)
-
-#define IX_OSAL_LE_AC_MAPPING
-
-#endif /* cryptoAcc */
-
-/***************************
- * codelets_usb
- ***************************/
-#if (IX_COMPONENT_NAME == ix_codelets_usb)
-
-#define IX_OSAL_LE_AC_MAPPING
-
-#endif /* codelets_usb */
-
-
-/***************************
- * codelets_uartAcc
- ***************************/
-#if (IX_COMPONENT_NAME == ix_codelets_uartAcc)
-
-#define IX_OSAL_LE_AC_MAPPING
-
-#endif /* codelets_uartAcc */
-
-
-
-/***************************
- * codelets_timers
- ***************************/
-#if (IX_COMPONENT_NAME == ix_codelets_timers)
-
-#define IX_OSAL_LE_AC_MAPPING
-
-#endif /* codelets_timers */
-
-/***************************
- * codelets_atm
- ***************************/
-#if (IX_COMPONENT_NAME == ix_codelets_atm)
-
-#define IX_OSAL_LE_AC_MAPPING
-
-#endif /* codelets_atm */
-
-/***************************
- * codelets_ethAal5App
- ***************************/
-#if (IX_COMPONENT_NAME == ix_codelets_ethAal5App)
-
-#define IX_OSAL_LE_AC_MAPPING
-
-#endif /* codelets_ethAal5App */
-
-/***************************
- * codelets_ethAcc
- ***************************/
-#if (IX_COMPONENT_NAME == ix_codelets_ethAcc)
-
-#define IX_OSAL_LE_AC_MAPPING
-
-#endif /* codelets_ethAcc */
-
-
-/***************************
- * codelets_demoUtils
- ***************************/
-#if (IX_COMPONENT_NAME == ix_codelets_demoUtils)
-
-#define IX_OSAL_LE_AC_MAPPING
-
-#endif /* codelets_demoUtils */
-
-
-
-/***************************
- * perfProfAcc
- ***************************/
-#if (IX_COMPONENT_NAME == ix_perfProfAcc)
-
-#define IX_OSAL_LE_AC_MAPPING
-
-#endif /* perfProfAcc */
-
-
-/***************************
- * unloadAcc
- ***************************/
-#if (IX_COMPONENT_NAME == ix_unloadAcc)
-
-#define IX_OSAL_LE_AC_MAPPING
-
-#endif /* unloadAcc */
-
-
-
-
-
-/***************************
- * parityENAcc
- ***************************/
-#if (IX_COMPONENT_NAME == ix_parityENAcc)
-
-#define IX_OSAL_LE_AC_MAPPING
-
-#endif /* parityENAcc */
-
-/***************************
- * codelets_parityENAcc
- ***************************/
-#if (IX_COMPONENT_NAME == ix_codelets_parityENAcc)
-
-#define IX_OSAL_LE_AC_MAPPING
-
-#endif /* codelets_parityENAcc */
-
-
-
-
-/***************************
- * timeSyncAcc
- ***************************/
-#if (IX_COMPONENT_NAME == ix_timeSyncAcc)
-
-#define IX_OSAL_LE_AC_MAPPING
-
-#endif /* timeSyncAcc */
-
-
-/***************************
- * codelets_timeSyncAcc
- ***************************/
-#if (IX_COMPONENT_NAME == ix_codelets_timeSyncAcc)
-
-#define IX_OSAL_LE_AC_MAPPING
-
-#endif /* codelets_timeSyncAcc */
-
-
-
-
-/***************************
- * i2c
- ***************************/
-#if (IX_COMPONENT_NAME == ix_i2c)
-
-#define IX_OSAL_LE_AC_MAPPING
-
-#endif /* i2c */
-
-
-
-/***************************
- * sspAcc
- ***************************/
-#if (IX_COMPONENT_NAME == ix_sspAcc)
-
-#define IX_OSAL_LE_AC_MAPPING
-
-#endif /* sspAcc */
-
-
diff --git a/arch/arm/cpu/ixp/npe/include/IxOsalOsTypes.h b/arch/arm/cpu/ixp/npe/include/IxOsalOsTypes.h
deleted file mode 100644
index 272eef1..0000000
--- a/arch/arm/cpu/ixp/npe/include/IxOsalOsTypes.h
+++ /dev/null
@@ -1,60 +0,0 @@
-#ifndef IxOsalOsTypes_H
-#define IxOsalOsTypes_H
-
-#include <asm/types.h>
-
-typedef s64 INT64;
-typedef u64 UINT64;
-typedef s32 INT32;
-typedef u32 UINT32;
-typedef s16 INT16;
-typedef u16 UINT16;
-typedef s8 INT8;
-typedef u8 UINT8;
-
-typedef u32 ULONG;
-typedef u16 USHORT;
-typedef u8 UCHAR;
-typedef u32 BOOL;
-
-#if 0 /* FIXME */
-
-/* Default stack limit is 10 KB */
-#define IX_OSAL_OS_THREAD_DEFAULT_STACK_SIZE  (10240)
-
-/* Maximum stack limit is 32 MB */
-#define IX_OSAL_OS_THREAD_MAX_STACK_SIZE      (33554432)  /* 32 MBytes */
-
-/* Default thread priority */
-#define IX_OSAL_OS_DEFAULT_THREAD_PRIORITY    (90)
-
-/* Thread maximum priority (0 - 255). 0 - highest priority */
-#define IX_OSAL_OS_MAX_THREAD_PRIORITY	      (255)
-
-#endif /* FIXME */
-
-#define IX_OSAL_OS_WAIT_FOREVER (-1L)
-#define IX_OSAL_OS_WAIT_NONE	0
-
-
-/* Thread handle is eventually an int type */
-typedef int IxOsalOsThread;
-
-/* Semaphore handle FIXME */
-typedef int IxOsalOsSemaphore;
-
-/* Mutex handle */
-typedef int IxOsalOsMutex;
-
-/*
- * Fast mutex handle - fast mutex operations are implemented in
- * native assembler code using atomic test-and-set instructions
- */
-typedef int IxOsalOsFastMutex;
-
-typedef struct
-{
-} IxOsalOsMessageQueue;
-
-
-#endif /* IxOsalOsTypes_H */
diff --git a/arch/arm/cpu/ixp/npe/include/IxOsalOsUtilitySymbols.h b/arch/arm/cpu/ixp/npe/include/IxOsalOsUtilitySymbols.h
deleted file mode 100644
index beb45a0..0000000
--- a/arch/arm/cpu/ixp/npe/include/IxOsalOsUtilitySymbols.h
+++ /dev/null
@@ -1,4 +0,0 @@
-#ifndef IxOsalOsUtilitySymbols_H
-#define IxOsalOsUtilitySymbols_H
-
-#endif /* IxOsalOsUtilitySymbols_H */
diff --git a/arch/arm/cpu/ixp/npe/include/IxOsalTypes.h b/arch/arm/cpu/ixp/npe/include/IxOsalTypes.h
deleted file mode 100644
index a190a70..0000000
--- a/arch/arm/cpu/ixp/npe/include/IxOsalTypes.h
+++ /dev/null
@@ -1,401 +0,0 @@
-/**
- * @file IxOsalTypes.h
- *
- * @brief Define OSAL basic data types.
- *
- * This file contains fundamental data types used by OSAL.
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
- */
-
-
-#ifndef IxOsalTypes_H
-#define IxOsalTypes_H
-
-#include <config.h>
-#include <common.h>
-
-#define __ixp42X			/* sr: U-Boot needs this define */
-#define IXP425_EXP_CFG_BASE	0xC4000000
-#define diag_printf		debug
-
-#undef SIMSPARCSOLARIS
-#define SIMSPARCSOLARIS		0xaffe	/* sr: U-Boot gets confused with this solaris define */
-
-/*
- * Include the OS-specific type definitions
- */
-#include "IxOsalOsTypes.h"
-/**
- * @defgroup IxOsalTypes Osal basic data types.
- *
- * @brief Basic data types for Osal
- *
- * @{
- */
-
-/**
- * @brief OSAL status
- *
- * @note Possible OSAL return status include IX_SUCCESS and IX_FAIL.
- */
-typedef UINT32 IX_STATUS;
-
-/**
- * @brief VUINT32
- *
- * @note volatile UINT32
- */
-typedef volatile UINT32 VUINT32;
-
-/**
- * @brief VINT32
- *
- * @note volatile INT32
- */
-typedef volatile INT32 VINT32;
-
-
-#ifndef NUMELEMS
-#define NUMELEMS(x) (sizeof(x) / sizeof((x)[0]))
-#endif
-
-
-/**
- * @ingroup IxOsalTypes
- *
- * @def IX_OSAL_BILLION
- *
- * @brief  Alias for 1,000,000,000
- *
- */
-#define IX_OSAL_BILLION (1000000000)
-
-#ifndef TRUE
-#define TRUE       1L
-#endif
-
-#if TRUE != 1
-#error TRUE is not defined to 1
-#endif
-
-#ifndef FALSE
-#define FALSE      0L
-#endif
-
-#if FALSE != 0
-#error FALSE is not defined to 0
-#endif
-
-#ifndef NULL
-#define NULL       0L
-#endif
-
-/**
- * @ingroup IxOsalTypes
- *
- * @def IX_SUCCESS
- *
- * @brief Success status
- *
- */
-#ifndef IX_SUCCESS
-#define IX_SUCCESS 0L /**< #defined as 0L */
-#endif
-
-/**
- * @ingroup IxOsalTypes
- *
- * @def IX_FAIL
- *
- * @brief Failure status
- *
- */
-#ifndef IX_FAIL
-#define IX_FAIL    1L /**< #defined as 1L */
-#endif
-
-
-#ifndef PRIVATE
-#ifdef IX_PRIVATE_OFF
-#define PRIVATE			/* nothing */
-#else
-#define PRIVATE static	/**< #defined as static, except for debug builds */
-#endif /* IX_PRIVATE_OFF */
-#endif /* PRIVATE */
-
-
-/**
- * @ingroup IxOsalTypes
- *
- * @def IX_OSAL_INLINE
- *
- * @brief Alias for __inline
- *
- */
-#ifndef IX_OSAL_INLINE
-#define IX_OSAL_INLINE __inline
-#endif /* IX_OSAL_INLINE */
-
-
-#ifndef __inline__
-#define __inline__	IX_OSAL_INLINE
-#endif
-
-
-/* Each OS can define its own PUBLIC, otherwise it will be empty. */
-#ifndef PUBLIC
-#define PUBLIC
-#endif /* PUBLIC */
-
-
-/**
- * @ingroup IxOsalTypes
- *
- * @def IX_OSAL_INLINE_EXTERN
- *
- * @brief Alias for __inline extern
- *
- */
-#ifndef IX_OSAL_INLINE_EXTERN
-#define IX_OSAL_INLINE_EXTERN IX_OSAL_INLINE extern
-#endif
-
-/**
- * @ingroup IxOsalTypes
- * @enum IxOsalLogDevice
- * @brief This is an emum for OSAL log devices.
- */
-typedef enum
-{
-    IX_OSAL_LOG_DEV_STDOUT = 0,	       /**< standard output (implemented by default) */
-    IX_OSAL_LOG_DEV_STDERR = 1,	       /**< standard error (implemented */
-    IX_OSAL_LOG_DEV_HEX_DISPLAY = 2,   /**< hexadecimal display (not implemented) */
-    IX_OSAL_LOG_DEV_ASCII_DISPLAY = 3  /**< ASCII-capable display (not implemented) */
-} IxOsalLogDevice;
-
-
-/**
- * @ingroup IxOsalTypes
- *
- * @def IX_OSAL_LOG_ERROR
- *
- * @brief Alias for -1, used as log function error status
- *
- */
-#define IX_OSAL_LOG_ERROR (-1)
-
-/**
- * @ingroup IxOsalTypes
- * @enum IxOsalLogLevel
- * @brief This is an emum for OSAL log trace level.
- */
-typedef enum
-{
-    IX_OSAL_LOG_LVL_NONE = 0,	 /**<No trace level */
-    IX_OSAL_LOG_LVL_USER = 1,	 /**<Set trace level to user */
-    IX_OSAL_LOG_LVL_FATAL = 2,	 /**<Set trace level to fatal */
-    IX_OSAL_LOG_LVL_ERROR = 3,	 /**<Set trace level to error */
-    IX_OSAL_LOG_LVL_WARNING = 4, /**<Set trace level to warning */
-    IX_OSAL_LOG_LVL_MESSAGE = 5, /**<Set trace level to message */
-    IX_OSAL_LOG_LVL_DEBUG1 = 6,	 /**<Set trace level to debug1 */
-    IX_OSAL_LOG_LVL_DEBUG2 = 7,	 /**<Set trace level to debug2 */
-    IX_OSAL_LOG_LVL_DEBUG3 = 8,	 /**<Set trace level to debug3 */
-    IX_OSAL_LOG_LVL_ALL	/**<Set trace level to all */
-} IxOsalLogLevel;
-
-
-/**
- * @ingroup IxOsalTypes
- * @brief Void function pointer prototype
- *
- * @note accepts a void pointer parameter
- * and does not return a value.
- */
-typedef void (*IxOsalVoidFnVoidPtr) (void *);
-
-typedef void (*IxOsalVoidFnPtr) (void);
-
-
-/**
- * @brief Timeval structure
- *
- * @note Contain subfields of seconds and nanoseconds..
- */
-typedef struct
-{
-    UINT32 secs;		/**< seconds */
-    UINT32 nsecs;		/**< nanoseconds */
-} IxOsalTimeval;
-
-
-/**
- * @ingroup IxOsalTypes
- * @brief IxOsalTimer
- *
- * @note OSAL timer handle
- *
- */
-typedef UINT32 IxOsalTimer;
-
-
-/**
- * @ingroup IxOsalTypes
- *
- * @def IX_OSAL_WAIT_FOREVER
- *
- * @brief Definition for timeout forever, OS-specific.
- *
- */
-#define IX_OSAL_WAIT_FOREVER IX_OSAL_OS_WAIT_FOREVER
-
-/**
- * @ingroup IxOsalTypes
- *
- * @def IX_OSAL_WAIT_NONE
- *
- * @brief Definition for timeout 0, OS-specific.
- *
- */
-#define IX_OSAL_WAIT_NONE    IX_OSAL_OS_WAIT_NONE
-
-
-/**
- * @ingroup IxOsalTypes
- * @brief IxOsalMutex
- *
- * @note Mutex handle, OS-specific
- *
- */
-typedef IxOsalOsMutex IxOsalMutex;
-
-/**
- * @ingroup IxOsalTypes
- * @brief IxOsalFastMutex
- *
- * @note FastMutex handle, OS-specific
- *
- */
-typedef IxOsalOsFastMutex IxOsalFastMutex;
-
-/**
- * @ingroup IxOsalTypes
- * @brief IxOsalThread
- *
- * @note Thread handle, OS-specific
- *
- */
-typedef IxOsalOsThread IxOsalThread;
-
-/**
- * @ingroup IxOsalTypes
- * @brief IxOsalSemaphore
- *
- * @note Semaphore handle, OS-specific
- *
- */
-typedef IxOsalOsSemaphore IxOsalSemaphore;
-
-/**
- * @ingroup IxOsalTypes
- * @brief IxOsalMessageQueue
- *
- * @note Message Queue handle, OS-specific
- *
- */
-typedef IxOsalOsMessageQueue IxOsalMessageQueue;
-
-
-/**
- * @brief Thread Attribute
- * @note Default thread attribute
- */
-typedef struct
-{
-    char *name;        /**< name */
-    UINT32 stackSize;  /**< stack size */
-    UINT32 priority;   /**< priority */
-} IxOsalThreadAttr;
-
-/**
- * @ingroup IxOsalTypes
- *
- * @def IX_OSAL_THREAD_DEFAULT_STACK_SIZE
- *
- * @brief Default thread stack size, OS-specific.
- *
- */
-#define IX_OSAL_THREAD_DEFAULT_STACK_SIZE (IX_OSAL_OS_THREAD_DEFAULT_STACK_SIZE)
-
-/**
- * @ingroup IxOsalTypes
- *
- * @def IX_OSAL_THREAD_MAX_STACK_SIZE
- *
- * @brief Max stack size, OS-specific.
- *
- */
-#define IX_OSAL_THREAD_MAX_STACK_SIZE (IX_OSAL_OS_THREAD_MAX_STACK_SIZE)
-
-/**
- * @ingroup IxOsalTypes
- *
- * @def IX_OSAL_DEFAULT_THREAD_PRIORITY
- *
- * @brief Default thread priority, OS-specific.
- *
- */
-#define IX_OSAL_DEFAULT_THREAD_PRIORITY (IX_OSAL_OS_DEFAULT_THREAD_PRIORITY)
-
-/**
- * @ingroup IxOsalTypes
- *
- * @def IX_OSAL_MAX_THREAD_PRIORITY
- *
- * @brief Max thread priority, OS-specific.
- *
- */
-#define IX_OSAL_MAX_THREAD_PRIORITY (IX_OSAL_OS_MAX_THREAD_PRIORITY)
-
-/**
- * @} IxOsalTypes
- */
-
-
-#endif /* IxOsalTypes_H */
diff --git a/arch/arm/cpu/ixp/npe/include/IxOsalUtilitySymbols.h b/arch/arm/cpu/ixp/npe/include/IxOsalUtilitySymbols.h
deleted file mode 100644
index f2a73db..0000000
--- a/arch/arm/cpu/ixp/npe/include/IxOsalUtilitySymbols.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/**
- * @file
- *
- * @brief OSAL Configuration header file
- * 
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- * 
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- * 
- * @par
- * -- End of Copyright Notice --
- */
-
-#ifndef IxOsalUtilitySymbols_H
-#define IxOsalUtilitySymbols_H
-
-#include "IxOsalOsUtilitySymbols.h"	/* OS-specific utility symbol definitions */
-
-#endif /* IxOsalUtilitySymbols_H */
diff --git a/arch/arm/cpu/ixp/npe/include/IxParityENAcc.h b/arch/arm/cpu/ixp/npe/include/IxParityENAcc.h
deleted file mode 100644
index 62fe171..0000000
--- a/arch/arm/cpu/ixp/npe/include/IxParityENAcc.h
+++ /dev/null
@@ -1,785 +0,0 @@
-/**
- * @file IxParityENAcc.h
- *
- * @author Intel Corporation
- * @date 24 Mar 2004
- *
- * @brief This file contains the public API for the IXP400 Parity Error 
- * Notifier access component.
- *
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- * 
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- * 
- * @par
- * -- End of Copyright Notice --
- */
-
-/**
- * @defgroup IxParityENAcc IXP400 Parity Error Notifier (IxParityENAcc) API
- *
- * @brief The public API for the Parity Error Notifier 
- * 
- * @{
- */
-
-#ifndef IXPARITYENACC_H
-#define IXPARITYENACC_H
-
-#ifdef __ixp46X
-
-#include "IxOsal.h"
-
-/*
- * #defines for function return types, etc.
- */
-
-/**
- * @ingroup IxParityENAcc
- *
- * @enum IxParityENAccStatus
- *
- * @brief The status as returend from the API
- */
-typedef enum /**< IxParityENAccStatus */
-{
-  IX_PARITYENACC_SUCCESS = IX_SUCCESS, /**< The request is successful */
-  IX_PARITYENACC_INVALID_PARAMETERS,   /**< Invalid or NULL parameters passed */
-  IX_PARITYENACC_NOT_INITIALISED,      /**< Access layer has not been initialised before accessing the APIs */
-  IX_PARITYENACC_ALREADY_INITIALISED,  /**< Access layer has already been initialised */ 
-  IX_PARITYENACC_OPERATION_FAILED,     /**< Operation did not succeed due to hardware failure */
-  IX_PARITYENACC_NO_PARITY             /**< No parity condition exits or has already been cleared */
-} IxParityENAccStatus;
-
-/**
- * @ingroup IxParityENAcc
- *
- * @enum IxParityENAccParityType
- * 
- * @brief Odd or Even Parity Type
- */
-typedef enum  /**< IxParityENAccParityType */
-{
-  IX_PARITYENACC_EVEN_PARITY,    /**< Even Parity */
-  IX_PARITYENACC_ODD_PARITY      /**< Odd Parity */
-} IxParityENAccParityType;
-
-/**
- * @ingroup IxParityENAcc
- *
- * @enum IxParityENAccConfigOption
- *
- * @brief The parity error enable/disable configuration option
- */
-typedef enum /**< IxParityENAccConfigOption */
-{
-  IX_PARITYENACC_DISABLE,       /**< Disable parity error detection */
-  IX_PARITYENACC_ENABLE         /**< Enable parity error detection */
-} IxParityENAccConfigOption;
-
-/**
- * @ingroup IxParityENAcc
- *
- * @struct IxParityENAccNpeConfig
- *
- * @brief NPE parity detection is to be enabled/disabled
- */
-typedef struct /**< IxParityENAccNpeConfig */
-{
-  IxParityENAccConfigOption ideEnabled; /**< NPE IMem, DMem and External */
-  IxParityENAccParityType parityOddEven; /**< Parity - Odd or Even */
-} IxParityENAccNpeConfig ;
-
-
-/**
- * @ingroup IxParityENAcc
- *
- * @struct IxParityENAccMcuConfig
- *
- * @brief MCU pairty detection is to be enabled/disabled
- */
-typedef struct /**< IxParityENAccMcuConfig */ 
-{
-  IxParityENAccConfigOption singlebitDetectEnabled;      /**< Single-bit parity error detection */
-  IxParityENAccConfigOption singlebitCorrectionEnabled;  /**< Single-bit parity error correction */
-  IxParityENAccConfigOption multibitDetectionEnabled;    /**< Multi-bit  parity error detection */
-} IxParityENAccMcuConfig ;
-
-
-/**
- * @ingroup IxParityENAcc
- *
- * @struct IxParityENAccEbcConfig
- *
- * @brief Expansion Bus Controller parity detection is to be enabled or disabled 
- *
- * Note: All the Chip Select(s) and External Masters will have the same parity
- */
-typedef struct /**< IxParityENAccEbcConfig */
-{
-  IxParityENAccConfigOption ebcCs0Enabled;    /**< Expansion Bus Controller - Chip Select 0 */
-  IxParityENAccConfigOption ebcCs1Enabled;    /**< Expansion Bus Controller - Chip Select 1 */
-  IxParityENAccConfigOption ebcCs2Enabled;    /**< Expansion Bus Controller - Chip Select 2 */
-  IxParityENAccConfigOption ebcCs3Enabled;    /**< Expansion Bus Controller - Chip Select 3 */
-  IxParityENAccConfigOption ebcCs4Enabled;    /**< Expansion Bus Controller - Chip Select 4 */
-  IxParityENAccConfigOption ebcCs5Enabled;    /**< Expansion Bus Controller - Chip Select 5 */
-  IxParityENAccConfigOption ebcCs6Enabled;    /**< Expansion Bus Controller - Chip Select 6 */
-  IxParityENAccConfigOption ebcCs7Enabled;    /**< Expansion Bus Controller - Chip Select 7 */
-  IxParityENAccConfigOption ebcExtMstEnabled; /**< External Master on Expansion bus */
-  IxParityENAccParityType parityOddEven;      /**< Parity - Odd or Even */
-} IxParityENAccEbcConfig ;
-
-/**
- * @ingroup IxParityENAcc
- *
- * @struct IxParityENAccHWParityConfig
- *
- * @brief Parity error configuration of the Hardware Blocks
- */
-typedef struct /**< IxParityENAccHWParityConfig */
-{ 
-  IxParityENAccNpeConfig npeAConfig;     /**< NPE A parity detection is to be enabled/disabled */
-  IxParityENAccNpeConfig npeBConfig;     /**< NPE B parity detection is to be enabled/disabled */
-  IxParityENAccNpeConfig npeCConfig;     /**< NPE C parity detection is to be enabled/disabled */
-  IxParityENAccMcuConfig mcuConfig;      /**< MCU pairty detection is to be enabled/disabled */
-  IxParityENAccConfigOption swcpEnabled; /**< SWCP parity detection is to be enabled */
-  IxParityENAccConfigOption aqmEnabled;  /**< AQM parity detection is to be enabled */
-  IxParityENAccEbcConfig ebcConfig;      /**< Expansion Bus Controller parity detection is to be enabled/disabled */
-} IxParityENAccHWParityConfig;
-
-
-/**
- * @ingroup IxParityENAcc
- *
- * @struct IxParityENAccNpeParityErrorStats
- *
- * @brief NPE parity error statistics
- */
-typedef struct  /* IxParityENAccNpeParityErrorStats */
-{
-  UINT32 parityErrorsIMem;         /**< Parity errors in Instruction Memory */
-  UINT32 parityErrorsDMem;         /**< Parity errors in Data Memory */
-  UINT32 parityErrorsExternal;     /**< Parity errors in NPE External Entities */
-} IxParityENAccNpeParityErrorStats;
-
-/**
- * @ingroup IxParityENAcc
- *
- * @struct IxParityENAccMcuParityErrorStats
- *
- * @brief DDR Memory Control Unit parity error statistics
- * 
- * Note: There could be two outstanding parity errors at any given time whose address
- * details captured. If there is no room for the new interrupt then it would be treated
- * as overflow parity condition.
- */
-typedef struct  /* IxParityENAccMcuParityErrorStats */
-{
-  UINT32 parityErrorsSingleBit;    /**< Parity errors of the type Single-Bit */
-  UINT32 parityErrorsMultiBit;     /**< Parity errors of the type Multi-Bit */
-  UINT32 parityErrorsOverflow;     /**< Parity errors when more than two parity errors occured */
-} IxParityENAccMcuParityErrorStats;
-
-/**
- * @ingroup IxParityENAcc
- *
- * @struct IxParityENAccEbcParityErrorStats
- *
- * @brief Expansion Bus Controller parity error statistics
- */
-typedef struct  /* IxParityENAccEbcParityErrorStats */
-{
-  UINT32 parityErrorsInbound;      /**< Odd bit parity errors on inbound transfers */
-  UINT32 parityErrorsOutbound;     /**< Odd bit parity errors on outbound transfers */
-} IxParityENAccEbcParityErrorStats;
-
-
-/**
- * @ingroup IxParityENAcc
- *
- * @struct IxParityENAccParityErrorStats
- *
- * @brief Parity Error Statistics for the all the hardware blocks
- */
-typedef struct  /**< IxParityENAccParityErrorStats */
-{
-  IxParityENAccNpeParityErrorStats  npeStats;  /**< NPE parity error statistics */
-  IxParityENAccMcuParityErrorStats  mcuStats;  /**< MCU parity error statistics */
-  IxParityENAccEbcParityErrorStats  ebcStats;  /**< EBC parity error statistics */
-  UINT32                            swcpStats; /**< SWCP parity error statistics */
-  UINT32                            aqmStats;  /**< AQM parity error statistics */
-} IxParityENAccParityErrorStats;
-
-
-/**
- * @ingroup IxParityENAcc
- *
- * @enum IxParityENAccParityErrorSource
- *
- * @brief The source of the parity error notification 
- */
-typedef enum  /**< IxParityENAccParityErrorSource  */
-{
-  IX_PARITYENACC_NPE_A_IMEM,     /**< NPE A - Instruction memory */
-  IX_PARITYENACC_NPE_A_DMEM,     /**< NPE A - Data memory */
-  IX_PARITYENACC_NPE_A_EXT,      /**< NPE A - External Entity*/
-  IX_PARITYENACC_NPE_B_IMEM,     /**< NPE B - Instruction memory */
-  IX_PARITYENACC_NPE_B_DMEM,     /**< NPE B - Data memory */
-  IX_PARITYENACC_NPE_B_EXT,      /**< NPE B - External Entity*/
-  IX_PARITYENACC_NPE_C_IMEM,     /**< NPE C - Instruction memory */
-  IX_PARITYENACC_NPE_C_DMEM,     /**< NPE C - Data memory */
-  IX_PARITYENACC_NPE_C_EXT,      /**< NPE C - External Entity*/
-  IX_PARITYENACC_SWCP,           /**< SWCP */
-  IX_PARITYENACC_AQM,            /**< AQM */
-  IX_PARITYENACC_MCU_SBIT,       /**< DDR Memory Controller Unit - Single bit parity */
-  IX_PARITYENACC_MCU_MBIT,       /**< DDR Memory Controller Unit - Multi bit parity */
-  IX_PARITYENACC_MCU_OVERFLOW,   /**< DDR Memory Controller Unit - Parity errors in excess of two */
-  IX_PARITYENACC_EBC_CS,         /**< Expansion Bus Controller - Chip Select */
-  IX_PARITYENACC_EBC_EXTMST      /**< Expansion Bus Controller - External Master */
-} IxParityENAccParityErrorSource;
-
-/**
- * @ingroup IxParityENAcc
- *
- * @enum IxParityENAccParityErrorAccess
- *
- * @brief The type of access resulting in parity error
- */
-typedef enum  /**< IxParityENAccParityErrorAccess  */
-{
-  IX_PARITYENACC_READ,   /**< Read Access  */
-  IX_PARITYENACC_WRITE   /**< Write Access */
-} IxParityENAccParityErrorAccess;
-
-/**
- * @ingroup IxParityENAcc
- *
- * @typedef IxParityENAccParityErrorAddress
- *
- * @brief The memory location which has parity error
- */
-typedef UINT32 IxParityENAccParityErrorAddress;
-
-/**
- * @ingroup IxParityENAcc
- *
- * @typedef IxParityENAccParityErrorData
- *
- * @brief The data read from the memory location which has parity error
- */
-typedef UINT32 IxParityENAccParityErrorData;
-
-/**
- * @ingroup IxParityENAcc
- *
- * @enum IxParityENAccParityErrorRequester
- *
- * @brief The requester interface through which the SDRAM memory access 
- * resulted in the parity error.
- */
-typedef enum  /**< IxParityENAccParityErrorRequester  */
-{
-  IX_PARITYENACC_MPI,     /**< Direct Memory Port Interface  */
-  IX_PARITYENACC_AHB_BUS  /**< South or North AHB Bus */
-} IxParityENAccParityErrorRequester;
-
-/**
- * @ingroup IxParityENAcc
- *
- * @enum IxParityENAccAHBErrorMaster
- *
- * @brief The Master on the AHB bus interface whose transaction might have 
- * resulted in the parity error notification to XScale.
- */
-typedef enum  /**< IxParityENAccAHBErrorMaster */
-{
-  IX_PARITYENACC_AHBN_MST_NPE_A,       /**< NPE - A */
-  IX_PARITYENACC_AHBN_MST_NPE_B,       /**< NPE - B */
-  IX_PARITYENACC_AHBN_MST_NPE_C,       /**< NPE - C */
-  IX_PARITYENACC_AHBS_MST_XSCALE,      /**< XScale Bus Interface Unit */
-  IX_PARITYENACC_AHBS_MST_PBC,         /**< PCI Bus Controller */
-  IX_PARITYENACC_AHBS_MST_EBC,         /**< Expansion Bus Controller */
-  IX_PARITYENACC_AHBS_MST_AHB_BRIDGE,  /**< AHB Bridge */
-  IX_PARITYENACC_AHBS_MST_USBH         /**< USB Host Controller */
-} IxParityENAccAHBErrorMaster;
-
-/**
- * @ingroup IxParityENAcc
- *
- * @enum IxParityENAccAHBErrorSlave
- *
- * @brief The Slave on the AHB bus interface whose transaction might have 
- * resulted in the parity error notification to XScale.
- */
-typedef enum  /**< IxParityENAccAHBErrorSlave */
-{
-  IX_PARITYENACC_AHBN_SLV_MCU,         /**< Memory Control Unit */
-  IX_PARITYENACC_AHBN_SLV_AHB_BRIDGE,  /**< AHB Bridge */
-  IX_PARITYENACC_AHBS_SLV_MCU,         /**< XScale Bus Interface Unit */
-  IX_PARITYENACC_AHBS_SLV_APB_BRIDGE,  /**< APB Bridge */
-  IX_PARITYENACC_AHBS_SLV_AQM,         /**< AQM */
-  IX_PARITYENACC_AHBS_SLV_RSA,         /**< RSA (Crypto Bus) */
-  IX_PARITYENACC_AHBS_SLV_PBC,         /**< PCI Bus Controller */
-  IX_PARITYENACC_AHBS_SLV_EBC,         /**< Expansion Bus Controller */
-  IX_PARITYENACC_AHBS_SLV_USBH         /**< USB Host Controller */
-} IxParityENAccAHBErrorSlave;
-
-/**
- * @ingroup IxParityENAcc
- *
- * @struct IxParityENAccAHBErrorTransaction
- *
- * @brief The Master and Slave on the AHB bus interface whose transaction might
- * have resulted in the parity error notification to XScale.
- *
- * NOTE: This information may be used in the data abort exception handler
- * to differentiate between the XScale and non-XScale access to the SDRAM
- * memory.
- */
-typedef struct  /**< IxParityENAccAHBErrorTransaction  */
-{
-  IxParityENAccAHBErrorMaster  ahbErrorMaster; /**< Master on AHB bus */
-  IxParityENAccAHBErrorSlave   ahbErrorSlave;  /**< Slave  on AHB bus */
-} IxParityENAccAHBErrorTransaction;
-
-/**
- * @ingroup IxParityENAcc
- *
- * @struct IxParityENAccParityErrorContextMessage
- *
- * @brief Parity Error Context Message
- */
-typedef struct /**< IxParityENAccParityErrorContextMessage */
-{
-  IxParityENAccParityErrorSource     pecParitySource; /**< Source info of parity error */
-  IxParityENAccParityErrorAccess     pecAccessType;   /**< Read or Write Access
-                                                           Read  - NPE, SWCP, AQM, DDR MCU,
-                                                                   Exp Bus Ctrlr (Outbound)
-                                                           Write - DDR MCU,
-                                                                   Exp Bus Ctrlr (Inbound 
-                                                                   i.e., External Master) */
-  IxParityENAccParityErrorAddress    pecAddress;      /**< Address faulty location
-                                                           Valid only for AQM, DDR MCU, 
-                                                           Exp Bus Ctrlr */
-  IxParityENAccParityErrorData       pecData;         /**< Data read from the faulty location
-                                                           Valid only for AQM and DDR MCU
-                                                           For DDR MCU it is the bit location
-                                                           of the Single-bit parity */
-  IxParityENAccParityErrorRequester  pecRequester;    /**< Requester of SDRAM memory access
-                                                           Valid only for the DDR MCU */
-  IxParityENAccAHBErrorTransaction   ahbErrorTran;    /**< Master and Slave information on the
-                                                           last AHB Error Transaction */
-} IxParityENAccParityErrorContextMessage;
-
-/**
- * @ingroup IxParityENAcc
- *
- * @typedef IxParityENAccCallback
- *
- * @brief This prototype shows the format of a callback function.
- *
- * The callback will be used to notify the parity error to the client application.
- * The callback will be registered  by @ref ixParityENAccCallbackRegister.
- *
- * It will be called from an ISR when a parity error is detected and thus
- * needs to follow the interrupt callable function conventions.
- *
- */
-typedef void (*IxParityENAccCallback) (void);
-
-
-/*
- * Prototypes for interface functions.
- */
-
-/**
- * @ingroup IxParityENAcc
- *
- * @fn IxParityENAccStatus ixParityENAccInit(void)
- *
- * @brief This function will initialise the IxParityENAcc component.
- *
- * This function will initialise the IxParityENAcc component. It should only be
- * called once, prior to using the IxParityENAcc component.
- *
- * <OL><LI>It initialises the internal data structures, registers the ISR that 
- * will be triggered when a parity error occurs in IXP4xx silicon.</LI></OL>
- *
- * @li Re-entrant   : No
- * @li ISR Callable : No
- * 
- * @return @li IX_PARITYENACC_SUCCESS - Initialization is successful
- *         @li IX_PARITYENACC_ALREADY_INITIALISED - The access layer has already 
- *             been initialized
- *         @li IX_PARITYENACC_OPERATION_FAILED - The request failed because the 
- *             operation didn't succeed on the hardware. Refer to error trace/log
- *             for details.
- */
-
-PUBLIC IxParityENAccStatus ixParityENAccInit(void);
-
-/**
- * @ingroup IxParityENAcc
- *
- * @fn IxParityENAccStatus ixParityENAccCallbackRegister (
-           IxParityENAccCallback parityErrNfyCallBack)
- *
- * @brief This function will register a new callback with IxParityENAcc component. 
- * It can also reregister a new callback replacing the old callback.
- *
- * @param parityErrNfyCallBack [in] - This parameter will specify the call-back
- * function supplied by the client application.
- *
- * This interface registers the user application supplied call-back handler with
- * the parity error handling access component after the init.
- *
- * The callback function will be called from an ISR that will be triggered by the 
- * parity error in the IXP400 silicon.
- *
- * The following actions will be performed by this function:
- * <OL><LI>Check for the prior initialisation of the module before registering or
- * re-registering of the callback.
- * Check for parity error detection disabled before re-registration of the callback.
- * </LI></OL>
- *
- * @li   Re-entrant   : No
- * @li   ISR Callable : No
- *
- * @return @li IX_PARITYENACC_SUCCESS - The parameters check passed and the 
- *             registration is successful.
- *         @li IX_PARITYENACC_INVALID_PARAMETERS - Request failed due to NULL 
- *             parameter passed.
- *         @li IX_PARITYENACC_OPERATION_FAILED - The request failed because the 
- *             parity error detection not yet disabled.
- *         @li IX_PARITYENACC_NOT_INITIALISED - The operation requested prior to
- *             the initialisation of the access layer.
- */
-
-PUBLIC IxParityENAccStatus ixParityENAccCallbackRegister (
-           IxParityENAccCallback parityErrNfyCallBack);
-
-/**
- * @ingroup IxParityENAcc
- *
- * @fn IxParityENAccStatus ixParityENAccParityDetectionConfigure (
-           const IxParityENAccHWParityConfig *hwParityConfig)
- *
- * @brief This interface allows the client application to enable the parity 
- * error detection on the underlying hardware block.
- *
- * @param hwParityConfig [in] - Hardware blocks for which the parity error 
- * detection is to be enabled or disabled.
- *
- * The client application allocates and provides the reference to the buffer.
- *
- * It will also verify whether the specific hardware block is functional or not.
- *
- * NOTE: Failure in enabling or disabling of one or more components result in
- * trace message but still returns IX_PARITYENACC_SUCCESS. Refer to the function 
- * @ref ixParityENAccParityDetectionQuery on how to verify the failures while 
- * enabling/disabling paritys error detection.
- *
- * It shall be invoked after the Init and CallbackRegister functions but before
- * any other function of the IxParityENAcc layer.
- *
- * @li   Re-entrant   : No
- * @li   ISR Callable : No
- *
- * @return @li IX_PARITYENACC_SUCCESS - The parameters check passed and the 
- *             request to enable/disable is successful.
- *         @li IX_PARITYENACC_INVALID_PARAMETERS-The request failed due to  
- *             NULL parameter supplied.
- *         @li IX_PARITYENACC_OPERATION_FAILED - The request failed because the 
- *             operation didn't succeed on the hardware.
- *         @li IX_PARITYENACC_NOT_INITIALISED - The operation requested prior to
- *             the initialisation of the access layer.
- */
-
-PUBLIC IxParityENAccStatus ixParityENAccParityDetectionConfigure (
-           const IxParityENAccHWParityConfig *hwParityConfig);
-
-/**
- * @ingroup IxParityENAcc
- *
- * @fn IxParityENAccStatus ixParityENAccParityDetectionQuery (
-           IxParityENAccHWParityConfig * const hwParityConfig)
- *
- * @brief This interface allows the client application to determine the 
- * status of the parity error detection on the specified hardware blocks
- *
- * @param hwParityConfig [out] - Hardware blocks whose parity error detection 
- * has been enabled or disabled.
- *
- * The client application allocates and provides the reference to the buffer.
- *
- * This interface can be used immediately after the interface @ref
- * ixParityENAccParityDetectionConfigure to see on which of the hardware blocks
- * the parity error detection has either been enabled or disabled based on the
- * client application request.
- *
- * @li   Re-entrant   : No
- * @li   ISR Callable : No
- *
- * @return @li IX_PARITYENACC_SUCCESS - The parameters check passed and the 
- *             request to query on whether the hardware parity error detection
- *             is enabled or disabled is successful.
- *         @li IX_PARITYENACC_INVALID_PARAMETERS-The request failed due to  
- *             NULL parameter or invalid values supplied.
- *         @li IX_PARITYENACC_NOT_INITIALISED - The operation requested prior 
- *             to the initialisation of the access layer.
- */
-
-PUBLIC IxParityENAccStatus ixParityENAccParityDetectionQuery(
-           IxParityENAccHWParityConfig * const hwParityConfig);
-
-/**
- * @ingroup IxParityENAcc
- *
- * @fn IxParityENAccStatus ixParityENAccParityErrorContextGet( 
-           IxParityENAccParityErrorContextMessage * const pecMessage)
- *
- * @brief This interface allows the client application to determine the 
- * status of the parity error context on hardware block for which the
- * current parity error interrupt triggered.
- *
- * @param pecMessage [out] - The parity error context information of the
- * parity interrupt currently being process.
- *
- * The client application allocates and provides the reference to the buffer.
- *
- * Refer to the data structure @ref IxParityENAccParityErrorContextMessage
- * for details.
- *
- * The routine will will fetch the parity error context in the following
- * priority, if multiple parity errors observed.
- * 
- * <pre>
- * 0 - MCU (Multi-bit and single-bit in that order)
- * 1 - NPE-A
- * 2 - NPE-B
- * 3 - NPE-C
- * 4 - SWCP
- * 5 - QM
- * 6 - EXP
- *
- * NOTE: The information provided in the @ref IxParityENAccAHBErrorTransaction
- * may be of help for the client application to decide on the course of action 
- * to take. This info is taken from the Performance Monitoring Unit register
- * which records most recent error observed on the AHB bus. This information
- * might have been overwritten by some other error by the time it is retrieved.
- * </pre>
- *
- * @li   Re-entrant   : No
- * @li   ISR Callable : Yes
- *
- * @return @li IX_PARITYENACC_SUCCESS-The parameters check passed and the 
- *             request to get the parity error context information is successful.
- *         @li IX_PARITYENACC_INVALID_PARAMETERS-The request failed due to  
- *             NULL parameter is passed
- *         @li IX_PARITYENACC_OPERATION_FAILED - The request failed because 
- *             the operation didn't succeed on the hardware.
- *         @li IX_PARITYENACC_NOT_INITIALISED - The operation requested prior
- *             to the initialisation of the access layer.
- *         @li IX_PARITYENACC_NO_PARITY - No parity condition exits or has 
- *             already been cleared
- */
-
-PUBLIC IxParityENAccStatus ixParityENAccParityErrorContextGet( 
-           IxParityENAccParityErrorContextMessage * const pecMessage);
-
-/**
- * @ingroup IxParityENAcc
- *
- * @fn IxParityENAccStatus ixParityENAccParityErrorInterruptClear (
-          const IxParityENAccParityErrorContextMessage *pecMessage)
- *
- * @brief This interface helps the client application to clear off the
- * interrupt condition on the hardware block identified in the parity
- * error context message.  Please refer to the table below as the operation
- * varies depending on the interrupt source.
- * 
- * @param pecMessage [in] - The parity error context information of the
- * hardware block whose parity error interrupt condition is to disabled.
- *
- * The client application allocates and provides the reference to the buffer.
- *
- * <pre>
- * ****************************************************************************
- * Following actions will be taken during the interrupt clear for respective
- * hardware blocks.
- * 
- *  Parity Source     Actions taken during Interrupt clear 
- *  -------------     -------------------------------------------------------
- *  NPE-A             Interrupt will be masked off at the interrupt controller 
- *                    so that it will not trigger continuously.
- *                      Client application has to take appropriate action and 
- *                      re-configure the parity error detection subsequently. 
- *                      The client application will not be notified of further 
- *                      interrupts, until the re-configuration is done using
- *                      @ref ixParityENAccParityDetectionConfigure.
- *
- *  NPE-B             Interrupt will be masked off at the interrupt controller 
- *                    so that it will not trigger continuously.
- *                      Client application has to take appropriate action and 
- *                      re-configure the parity error detection subsequently. 
- *                      The client application will not be notified of further
- *                      interrupts, until the re-configuration is done using
- *                      @ref ixParityENAccParityDetectionConfigure.
- *
- *  NPE-C             Interrupt will be masked off at the interrupt controller 
- *                      Client application has to take appropriate action and 
- *                      re-configure the parity error detection subsequently. 
- *                      The client application will not be notified of further
- *                      interrupts, until the re-configuration is done using
- *                      @ref ixParityENAccParityDetectionConfigure.
- *
- *  SWCP              Interrupt will be masked off at the interrupt controller.
- *                      Client application has to take appropriate action and 
- *                      re-configure the parity error detection subsequently. 
- *                      The client application will not be notified of further
- *                      interrupts, until the re-configuration is done using
- *                      @ref ixParityENAccParityDetectionConfigure.
- *
- *  AQM               Interrupt will be masked off at the interrupt controller.
- *                         Client application has to take appropriate action and 
- *                         re-configure the parity error detection subsequently. 
- *                         The client application will not be notified of further
- *                         interrupts, until the re-configuration is done using
- *                         @ref ixParityENAccParityDetectionConfigure.
- *
- *  MCU               Parity interrupt condition is cleared at the SDRAM MCU for 
- *                    the following:
- *                    1. Single-bit
- *                    2. Multi-bit
- *                    3. Overflow condition i.e., more than two parity conditions 
- *                       occurred
- *                    Note that single-parity errors do not result in data abort
- *                    and not all data aborts caused by multi-bit parity error.
- *
- *  EXP               Parity interrupt condition is cleared at the expansion bus 
- *                    controller for the following:
- *                    1. External master initiated Inbound write
- *                    2. Internal master (IXP400) initiated Outbound read
- * ****************************************************************************
- * </pre>
- * @li   Re-entrant   : No
- * @li   ISR Callable : No
- *
- * @return @li IX_PARITYENACC_SUCCESS-The parameters check passed and the request
- *             to clear the parity error interrupt condition is successful.
- *         @li IX_PARITYENACC_INVALID_PARAMETERS-The request failed due to 
- *             NULL parameters have been passed or contents have been
- *             supplied with invalid values.
- *         @li IX_PARITYENACC_OPERATION_FAILED - The request failed because 
- *             the operation didn't succeed on the hardware.
- *         @li IX_PARITYENACC_NOT_INITIALISED - The operation requested prior
- *             to the initialisation of the access layer.
- */
-
-PUBLIC IxParityENAccStatus ixParityENAccParityErrorInterruptClear (
-          const IxParityENAccParityErrorContextMessage *pecMessage);
-
-/**
- * @ingroup IxParityENAcc
- *
- * @fn IxParityENAccStatus ixParityENAccStatsGet (
-            IxParityENAccParityErrorStats * const ixParityErrorStats)
- *
- * @brief This interface allows the client application to retrieve parity 
- * error statistics for all the hardware blocks 
- *
- * @param ixParityErrorStats - [out] The statistics for all the hardware blocks.
- *
- * The client application allocates and provides the reference to the buffer.
- *
- * @li   Re-entrant   : No
- * @li   ISR Callable : Yes
- *
- * @return @li IX_PARITYENACC_SUCCESS-The parameters check passed and the 
- *             request to retrieve parity error statistics for the hardware
- *             block is successful.
- *         @li IX_PARITYENACC_INVALID_PARAMETERS-The request failed due to a
- *             NULL parameter passed.
- *         @li IX_PARITYENACC_NOT_INITIALISED - The operation requested prior
- *             to the initialisation of the access layer.
- */
-
-PUBLIC IxParityENAccStatus ixParityENAccStatsGet (
-            IxParityENAccParityErrorStats * const ixParityErrorStats);
-
-/**
- * @ingroup IxParityENAcc
- *
- * @fn IxParityENAccStatus ixParityENAccStatsShow (void)
- *
- * @brief This interface allows the client application to print all the
- * parity error statistics.
- *
- * @li   Re-entrant   : No
- * @li   ISR Callable : No
- *
- * @return @li IX_PARITYENACC_SUCCESS - The request to show the pairty 
- *             error statistics is successful.
- *         @li IX_PARITYENACC_NOT_INITIALISED - The operation requested
- *             prior to the initialisation of the access layer.
- */
-
-PUBLIC IxParityENAccStatus ixParityENAccStatsShow (void);
-
-/**
- * @ingroup IxParityENAcc
- *
- * @fn IxParityENAccStatus ixParityENAccStatsReset (void)
- *
- * @brief This interface allows the client application to reset all the 
- * parity error statistics.
- *
- * @li   Re-entrant   : No
- * @li   ISR Callable : No
- *
- * @return @li IX_PARITYENACC_SUCCESS - The request to reset the parity 
- *             error statistics is successful.
- *         @li IX_PARITYENACC_NOT_INITIALISED - The operation requested 
- *             prior to the initialisation of the access layer.
- */
-
-PUBLIC IxParityENAccStatus ixParityENAccStatsReset (void);
-
-#endif /* IXPARITYENACC_H */
-#endif /* __ixp46X */
-
-/**
- * @} defgroup IxParityENAcc
- */
-
diff --git a/arch/arm/cpu/ixp/npe/include/IxPerfProfAcc.h b/arch/arm/cpu/ixp/npe/include/IxPerfProfAcc.h
deleted file mode 100644
index 65c0ba9..0000000
--- a/arch/arm/cpu/ixp/npe/include/IxPerfProfAcc.h
+++ /dev/null
@@ -1,1358 +0,0 @@
-/**
- * @file IxPerfProfAcc.h
- *
- * @brief  Header file for the IXP400 Perf Prof component (IxPerfProfAcc)
- *
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- * 
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- * 
- * @par
- * -- End of Copyright Notice --
- */
-
-/**
- * @defgroup IxPerfProfAcc IXP400 Performance Profiling (IxPerfProfAcc) API 
- *
- * @brief IXP400 Performance Profiling Utility component Public API. 
- * @li NOTE: Xcycle measurement is not supported in Linux.
- *
- *
- * @{
- */
-#ifndef IXPERFPROFACC_H
-#define IXPERFPROFACC_H
-
-#include "IxOsal.h"
-
-#ifdef __linux
-#include <linux/proc_fs.h>
-#endif
-
-/*
- * Section for #define
- */
-/**
- * @ingroup IxPerfProfAcc
- *
- * @def IX_PERFPROF_ACC_XSCALE_PMU_MAX_PROFILE_SAMPLES
- *
- * @brief This is the maximum number of profiling samples allowed, which can be
- * modified according to the user's discretion
- */
-#define IX_PERFPROF_ACC_XSCALE_PMU_MAX_PROFILE_SAMPLES	0xFFFF
-
-/**
- * @ingroup IxPerfProfAcc
- *
- * @def IX_PERFPROF_ACC_BUS_PMU_MAX_PECS      
- *
- * @brief This is the maximum number of Programmable Event Counters available. 
- *        This is a hardware specific and fixed value. Do not change.
- *        
- */
-#define IX_PERFPROF_ACC_BUS_PMU_MAX_PECS        7
-
-/**  
- * @ingroup IxPerfProfAcc
- *
- * @def IX_PERFPROF_ACC_XCYCLE_MAX_NUM_OF_MEASUREMENTS
- *
- * @brief Max number of measurement allowed. This constant is used when 
- *        creating storage array for Xcycle. When run in continuous mode,  
- *        Xcycle will wrap around and re-use buffer. 
- */
-#define IX_PERFPROF_ACC_XCYCLE_MAX_NUM_OF_MEASUREMENTS 600
-
-#ifdef __linux
-/**
- * @ingroup IxPerfProfAcc
- *
- * @def IX_PERFPROF_ACC_XSCALE_PMU_SYMBOL_ACCURACY
- *
- * @brief Level of accuracy required for matching the PC Address to
- *        symbol address. This is used when the XScale PMU time/event
- *        sampling functions get the PC address and search for the 
- *        corresponding symbol address.
- */
-#define IX_PERFPROF_ACC_XSCALE_PMU_SYMBOL_ACCURACY 0xffff
-
-#endif /*__linux*/
-
-/**  
- * @ingroup IxPerfProfAcc
- *
- * @def IX_PERFPROF_ACC_LOG
- *
- * @brief Mechanism for logging a formatted message for the PerfProfAcc component
- *
- * @param level UINT32 [in] - trace level
- * @param device UINT32 [in] - output device
- * @param str char* [in] - format string, similar to printf().
- * @param a UINT32 [in] - first argument to display
- * @param b UINT32 [in] - second argument to display
- * @param c UINT32 [in] - third argument to display
- * @param d UINT32 [in] - fourth argument to display
- * @param e UINT32 [in] - fifth argument to display
- * @param f UINT32 [in] - sixth argument to display
- *
- * @return none
- */
-#ifndef NDEBUG
-#define IX_PERFPROF_ACC_LOG(level, device, str, a, b, c, d, e, f)\
-             (ixOsalLog (level, device, str, a, b, c, d, e, f))
-#else /*do nothing*/
-#define IX_PERFPROF_ACC_LOG(level, device, str, a, b, c, d, e, f) 
-#endif /*ifdef NDEBUG */
-
-/*
- * Section for struct
- */
-
-/**
- * @brief contains summary of samples taken 
- * 
- * Structure contains all details of each program counter value - frequency 
- * that PC occurs 
- */
-typedef struct
-{
-	UINT32 programCounter;  /**<the program counter value of the sample*/
-	UINT32 freq;		/**<the frequency of the occurence of the sample*/
-} IxPerfProfAccXscalePmuSamplePcProfile;
-
-/**
- * @brief contains results of a counter
- *
- * Structure contains the results of a counter, which are split into the lower 
- * and upper 32 bits of the final count
- */
-typedef struct
-{
-    UINT32 lower32BitsEventCount; /**<lower 32bits value of the event counter*/        
-    UINT32 upper32BitsEventCount; /**<upper 32bits value of the event counter*/
-}   IxPerfProfAccXscalePmuEvtCnt;
-
-/**
- * @brief contains results of counters and their overflow 
- * 
- * Structure contains all values of counters and associated overflows.  The 
- * specific event and clock counters are determined by the user
- */
-typedef struct
-{
-    UINT32 clk_value;           /**<current value of clock counter*/                 
-    UINT32 clk_samples;        /**<number of clock counter overflows*/
-    UINT32 event1_value;        /**<current value of event 1 counter*/    
-    UINT32 event1_samples;     /**<number of event 1 counter overflows*/
-    UINT32 event2_value;        /**<current value of event 2 counter*/
-    UINT32 event2_samples;     /**<number of event 2 counter overflows*/
-    UINT32 event3_value;        /**<current value of event 3 counter*/
-    UINT32 event3_samples;     /**<number of event 3 counter overflows*/
-    UINT32 event4_value;        /**<current value of event 4 counter*/
-    UINT32 event4_samples;     /**<number of event 4 counter overflows*/
-} IxPerfProfAccXscalePmuResults;
-
-/** 
- * 
- * @brief Results obtained from Xcycle run 
- */ 
-typedef struct 
-{
-    float maxIdlePercentage; 		/**<maximum percentage of Idle cycles*/
-    float minIdlePercentage; 		/**<minimum percentage of Idle cycles*/
-    float aveIdlePercentage;		/**<average percentage of Idle cycles*/
-    UINT32 totalMeasurements;		/**<total number of measurement made */
-} IxPerfProfAccXcycleResults; 
-
-/**
- *
- * @brief Results obtained from running the Bus Pmu component. The results
- *        are obtained when the get functions is called.
- *        
- */
-typedef struct
-{
-    UINT32 statsToGetLower27Bit[IX_PERFPROF_ACC_BUS_PMU_MAX_PECS]; /**<Lower 27 Bit of counter value */
-    UINT32 statsToGetUpper32Bit[IX_PERFPROF_ACC_BUS_PMU_MAX_PECS]; /**<Upper 32 Bit of counter value */
-} IxPerfProfAccBusPmuResults;
-
-/*
- * Section for enum
- */
-
-/**
- * @ingroup IxPerfProfAcc
- * 
- * @enum IxPerfProfAccBusPmuEventCounters1
- *
- * @brief Type of bus pmu events supported on PEC 1.
- *
- * Lists all bus pmu events.  
- */
-typedef enum
-{
-	IX_PERFPROF_ACC_BUS_PMU_PEC1_NORTH_NPEA_GRANT_SELECT = 1, /**< Select North NPEA grant on PEC1*/
-	IX_PERFPROF_ACC_BUS_PMU_PEC1_NORTH_NPEB_GRANT_SELECT, /**< Select North NPEB grant on PEC1*/
-	IX_PERFPROF_ACC_BUS_PMU_PEC1_NORTH_NPEC_GRANT_SELECT, /**< Select North NPEC grant on PEC1*/
-	IX_PERFPROF_ACC_BUS_PMU_PEC1_NORTH_BUS_IDLE_SELECT, /**< Select North bus idle on PEC1*/
-	IX_PERFPROF_ACC_BUS_PMU_PEC1_NORTH_NPEA_REQ_SELECT, /**< Select North NPEA req on PEC1*/
-	IX_PERFPROF_ACC_BUS_PMU_PEC1_NORTH_NPEB_REQ_SELECT, /**< Select North NPEB req on PEC1*/
-	IX_PERFPROF_ACC_BUS_PMU_PEC1_NORTH_NPEC_REQ_SELECT, /**< Select North NPEC req on PEC1*/
-
-	IX_PERFPROF_ACC_BUS_PMU_PEC1_SOUTH_GSKT_GRANT_SELECT, /**< Select south gasket grant on PEC1*/
-	IX_PERFPROF_ACC_BUS_PMU_PEC1_SOUTH_ABB_GRANT_SELECT, /**< Select south abb grant on PEC1*/
-	IX_PERFPROF_ACC_BUS_PMU_PEC1_SOUTH_PCI_GRANT_SELECT, /**< Select south pci grant on PEC1*/
-	IX_PERFPROF_ACC_BUS_PMU_PEC1_SOUTH_APB_GRANT_SELECT, /**< Select south apb grant on PEC1*/
-	IX_PERFPROF_ACC_BUS_PMU_PEC1_SOUTH_GSKT_REQ_SELECT, /**< Select south gasket request on PEC1*/
-	IX_PERFPROF_ACC_BUS_PMU_PEC1_SOUTH_ABB_REQ_SELECT, /**< Select south abb request on PEC1*/
-	IX_PERFPROF_ACC_BUS_PMU_PEC1_SOUTH_PCI_REQ_SELECT, /**< Select south pci request on PEC1*/
-	IX_PERFPROF_ACC_BUS_PMU_PEC1_SOUTH_APB_REQ_SELECT, /**< Select south apb request on PEC1*/
-
-	IX_PERFPROF_ACC_BUS_PMU_PEC1_SDR_0_HIT_SELECT, /**< Select sdram0 hit on PEC1*/
-	IX_PERFPROF_ACC_BUS_PMU_PEC1_SDR_1_HIT_SELECT, /**< Select sdram1 hit on PEC1*/
-	IX_PERFPROF_ACC_BUS_PMU_PEC1_SDR_2_HIT_SELECT, /**< Select sdram2 hit on PEC1*/
-	IX_PERFPROF_ACC_BUS_PMU_PEC1_SDR_3_HIT_SELECT, /**< Select sdram3 hit on PEC1*/
-	IX_PERFPROF_ACC_BUS_PMU_PEC1_SDR_4_MISS_SELECT, /**< Select sdram4 miss on PEC1*/
-	IX_PERFPROF_ACC_BUS_PMU_PEC1_SDR_5_MISS_SELECT, /**< Select sdram5 miss on PEC1*/
-	IX_PERFPROF_ACC_BUS_PMU_PEC1_SDR_6_MISS_SELECT, /**< Select sdram6 miss on PEC1*/
-	IX_PERFPROF_ACC_BUS_PMU_PEC1_SDR_7_MISS_SELECT /**< Select sdram7 miss on PEC1*/
-} IxPerfProfAccBusPmuEventCounters1;
-
-/**
- * @ingroup IxPerfProfAcc
- *
- * @enum IxPerfProfAccBusPmuEventCounters2
- *
- * @brief Type of bus pmu events supported on PEC 2.
- *
- * Lists all bus pmu events.
- */
-typedef enum
-{
-	IX_PERFPROF_ACC_BUS_PMU_PEC2_NORTH_NPEA_XFER_SELECT = 24, /**< Select North NPEA transfer on PEC2*/
-	IX_PERFPROF_ACC_BUS_PMU_PEC2_NORTH_NPEB_XFER_SELECT, /**< Select North NPEB transfer on PEC2*/
-	IX_PERFPROF_ACC_BUS_PMU_PEC2_NORTH_NPEC_XFER_SELECT, /**< Select North NPEC transfer on PEC2*/
-	IX_PERFPROF_ACC_BUS_PMU_PEC2_NORTH_BUS_WRITE_SELECT, /**< Select North bus write on PEC2*/
-	IX_PERFPROF_ACC_BUS_PMU_PEC2_NORTH_NPEA_OWN_SELECT, /**< Select North NPEA own on PEC2*/
-	IX_PERFPROF_ACC_BUS_PMU_PEC2_NORTH_NPEB_OWN_SELECT, /**< Select North NPEB own on PEC2*/
-	IX_PERFPROF_ACC_BUS_PMU_PEC2_NORTH_NPEC_OWN_SELECT, /**< Select North NPEC own on PEC2*/
-
-	IX_PERFPROF_ACC_BUS_PMU_PEC2_SOUTH_GSKT_XFER_SELECT, /**< Select South gasket transfer on PEC2*/
-	IX_PERFPROF_ACC_BUS_PMU_PEC2_SOUTH_ABB_XFER_SELECT, /**< Select South abb transfer on PEC2*/
-	IX_PERFPROF_ACC_BUS_PMU_PEC2_SOUTH_PCI_XFER_SELECT, /**< Select South pci transfer on PEC2*/
-	IX_PERFPROF_ACC_BUS_PMU_PEC2_SOUTH_APB_XFER_SELECT, /**< Select South apb transfer on PEC2*/
-	IX_PERFPROF_ACC_BUS_PMU_PEC2_SOUTH_GSKT_OWN_SELECT, /**< Select South gasket own on PEC2*/
-	IX_PERFPROF_ACC_BUS_PMU_PEC2_SOUTH_ABB_OWN_SELECT, /**< Select South abb own on PEC2*/
-	IX_PERFPROF_ACC_BUS_PMU_PEC2_SOUTH_PCI_OWN_SELECT, /**< Select South pci own on PEC2*/
-	IX_PERFPROF_ACC_BUS_PMU_PEC2_SOUTH_APB_OWN_SELECT, /**< Select South apb own transfer on PEC2*/
-
-	IX_PERFPROF_ACC_BUS_PMU_PEC2_SDR_1_HIT_SELECT, /**< Select sdram1 hit on PEC2*/
-	IX_PERFPROF_ACC_BUS_PMU_PEC2_SDR_2_HIT_SELECT, /**< Select sdram2 hit on PEC2*/
-	IX_PERFPROF_ACC_BUS_PMU_PEC2_SDR_3_HIT_SELECT, /**< Select sdram3 hit on PEC2*/
-	IX_PERFPROF_ACC_BUS_PMU_PEC2_SDR_4_HIT_SELECT, /**< Select sdram4 hit on PEC2*/
-	IX_PERFPROF_ACC_BUS_PMU_PEC2_SDR_5_MISS_SELECT, /**< Select sdram5 miss on PEC2*/
-	IX_PERFPROF_ACC_BUS_PMU_PEC2_SDR_6_MISS_SELECT, /**< Select sdram6 miss on PEC2*/
-	IX_PERFPROF_ACC_BUS_PMU_PEC2_SDR_7_MISS_SELECT, /**< Select sdram7 miss on PEC2*/
-	IX_PERFPROF_ACC_BUS_PMU_PEC2_SDR_0_MISS_SELECT /**< Select sdram0 miss on PEC2*/
-} IxPerfProfAccBusPmuEventCounters2;
-
-/**
- * @ingroup IxPerfProfAcc
- *
- * @enum IxPerfProfAccBusPmuEventCounters3
- *
- * @brief Type of bus pmu events supported on PEC 3.
- *
- * Lists all bus pmu events.
- */
-typedef enum
-{
-	IX_PERFPROF_ACC_BUS_PMU_PEC3_NORTH_NPEA_RETRY_SELECT = 47, /**< Select north NPEA retry on PEC3*/
-	IX_PERFPROF_ACC_BUS_PMU_PEC3_NORTH_NPEB_RETRY_SELECT, /**< Select north NPEB retry on PEC3*/
-	IX_PERFPROF_ACC_BUS_PMU_PEC3_NORTH_NPEC_RETRY_SELECT, /**< Select north NPEC retry on PEC3*/
-	IX_PERFPROF_ACC_BUS_PMU_PEC3_NORTH_BUS_READ_SELECT, /**< Select north bus read on PEC3*/
-	IX_PERFPROF_ACC_BUS_PMU_PEC3_NORTH_NPEA_WRITE_SELECT, /**< Select north NPEA write on PEC3*/
-	IX_PERFPROF_ACC_BUS_PMU_PEC3_NORTH_NPEB_WRITE_SELECT, /**< Select north NPEB write on PEC3*/
-	IX_PERFPROF_ACC_BUS_PMU_PEC3_NORTH_NPEC_WRITE_SELECT, /**< Select north NPEC wirte on PEC3*/
-
-	IX_PERFPROF_ACC_BUS_PMU_PEC3_SOUTH_GSKT_RETRY_SELECT, /**< Select south gasket retry on PEC3*/
-	IX_PERFPROF_ACC_BUS_PMU_PEC3_SOUTH_ABB_RETRY_SELECT, /**< Select south abb retry on PEC3*/
-	IX_PERFPROF_ACC_BUS_PMU_PEC3_SOUTH_PCI_RETRY_SELECT, /**< Select south pci retry on PEC3*/
-	IX_PERFPROF_ACC_BUS_PMU_PEC3_SOUTH_APB_RETRY_SELECT, /**< Select south apb retry on PEC3*/
- 	IX_PERFPROF_ACC_BUS_PMU_PEC3_SOUTH_GSKT_WRITE_SELECT, /**< Select south gasket write on PEC3*/
- 	IX_PERFPROF_ACC_BUS_PMU_PEC3_SOUTH_ABB_WRITE_SELECT, /**< Select south abb write on PEC3*/
- 	IX_PERFPROF_ACC_BUS_PMU_PEC3_SOUTH_PCI_WRITE_SELECT, /**< Select south pci write on PEC3*/
- 	IX_PERFPROF_ACC_BUS_PMU_PEC3_SOUTH_APB_WRITE_SELECT, /**< Select south apb write on PEC3*/
-
- 	IX_PERFPROF_ACC_BUS_PMU_PEC3_SDR_2_HIT_SELECT, /**< Select sdram2 hit on PEC3*/
- 	IX_PERFPROF_ACC_BUS_PMU_PEC3_SDR_3_HIT_SELECT, /**< Select sdram3 hit on PEC3*/
- 	IX_PERFPROF_ACC_BUS_PMU_PEC3_SDR_4_HIT_SELECT, /**< Select sdram4 hit on PEC3*/
- 	IX_PERFPROF_ACC_BUS_PMU_PEC3_SDR_5_HIT_SELECT, /**< Select sdram5 hit on PEC3*/
- 	IX_PERFPROF_ACC_BUS_PMU_PEC3_SDR_6_MISS_SELECT, /**< Select sdram6 miss on PEC3*/
- 	IX_PERFPROF_ACC_BUS_PMU_PEC3_SDR_7_MISS_SELECT, /**< Select sdram7 miss on PEC3*/
- 	IX_PERFPROF_ACC_BUS_PMU_PEC3_SDR_0_MISS_SELECT, /**< Select sdram0 miss on PEC3*/
- 	IX_PERFPROF_ACC_BUS_PMU_PEC3_SDR_1_MISS_SELECT /**< Select sdram1 miss on PEC3*/
-} IxPerfProfAccBusPmuEventCounters3;
-
-/**
- * @ingroup IxPerfProfAcc
- *
- * @enum IxPerfProfAccBusPmuEventCounters4
- *
- * @brief Type of bus pmu events supported on PEC 4.
- *
- * Lists all bus pmu events.
- */
-typedef enum
-{
- 	IX_PERFPROF_ACC_BUS_PMU_PEC4_SOUTH_PCI_SPLIT_SELECT = 70, /**< Select south pci split on PEC4*/
- 	IX_PERFPROF_ACC_BUS_PMU_PEC4_SOUTH_EXP_SPLIT_SELECT, /**< Select south expansion split on PEC4*/
- 	IX_PERFPROF_ACC_BUS_PMU_PEC4_SOUTH_APB_GRANT_SELECT, /**< Select south apb grant on PEC4*/
- 	IX_PERFPROF_ACC_BUS_PMU_PEC4_SOUTH_APB_XFER_SELECT, /**< Select south apb transfer on PEC4*/
- 	IX_PERFPROF_ACC_BUS_PMU_PEC4_SOUTH_GSKT_READ_SELECT, /**< Select south gasket read on PEC4*/
- 	IX_PERFPROF_ACC_BUS_PMU_PEC4_SOUTH_ABB_READ_SELECT, /**< Select south abb read on PEC4*/
- 	IX_PERFPROF_ACC_BUS_PMU_PEC4_SOUTH_PCI_READ_SELECT, /**< Select south pci read on PEC4*/
- 	IX_PERFPROF_ACC_BUS_PMU_PEC4_SOUTH_APB_READ_SELECT, /**< Select south apb read on PEC4*/
-
- 	IX_PERFPROF_ACC_BUS_PMU_PEC4_NORTH_ABB_SPLIT_SELECT, /**< Select north abb split on PEC4*/
- 	IX_PERFPROF_ACC_BUS_PMU_PEC4_NORTH_NPEA_REQ_SELECT, /**< Select north NPEA req on PEC4*/
- 	IX_PERFPROF_ACC_BUS_PMU_PEC4_NORTH_NPEA_READ_SELECT, /**< Select north NPEA read on PEC4*/
- 	IX_PERFPROF_ACC_BUS_PMU_PEC4_NORTH_NPEB_READ_SELECT, /**< Select north NPEB read on PEC4*/
- 	IX_PERFPROF_ACC_BUS_PMU_PEC4_NORTH_NPEC_READ_SELECT, /**< Select north NPEC read on PEC4*/
-
- 	IX_PERFPROF_ACC_BUS_PMU_PEC4_SDR_3_HIT_SELECT, /**< Select sdram3 hit on PEC4*/
- 	IX_PERFPROF_ACC_BUS_PMU_PEC4_SDR_4_HIT_SELECT, /**< Select sdram4 hit on PEC4*/
- 	IX_PERFPROF_ACC_BUS_PMU_PEC4_SDR_5_HIT_SELECT, /**< Select sdram5 hit on PEC4*/
- 	IX_PERFPROF_ACC_BUS_PMU_PEC4_SDR_6_HIT_SELECT, /**< Select sdram6 hit on PEC4*/
- 	IX_PERFPROF_ACC_BUS_PMU_PEC4_SDR_7_MISS_SELECT, /**< Select sdram7 miss on PEC4*/
- 	IX_PERFPROF_ACC_BUS_PMU_PEC4_SDR_0_MISS_SELECT, /**< Select sdram0 miss on PEC4*/
- 	IX_PERFPROF_ACC_BUS_PMU_PEC4_SDR_1_MISS_SELECT, /**< Select sdram1 miss on PEC4*/
- 	IX_PERFPROF_ACC_BUS_PMU_PEC4_SDR_2_MISS_SELECT /**< Select sdram2 miss on PEC4*/
-} IxPerfProfAccBusPmuEventCounters4;
-
-/**
- * @ingroup IxPerfProfAcc
- *
- * @enum IxPerfProfAccBusPmuEventCounters5
- *
- * @brief Type of bus pmu events supported on PEC 5.
- *
- * Lists all bus pmu events.
- */
-typedef enum
-{
- 	IX_PERFPROF_ACC_BUS_PMU_PEC5_SOUTH_ABB_GRANT_SELECT = 91, /**< Select south abb grant on PEC5*/
- 	IX_PERFPROF_ACC_BUS_PMU_PEC5_SOUTH_ABB_XFER_SELECT, /**< Select south abb transfer on PEC5*/
- 	IX_PERFPROF_ACC_BUS_PMU_PEC5_SOUTH_ABB_RETRY_SELECT, /**< Select south abb retry on PEC5*/
- 	IX_PERFPROF_ACC_BUS_PMU_PEC5_SOUTH_EXP_SPLIT_SELECT, /**< Select south expansion split on PEC5*/
- 	IX_PERFPROF_ACC_BUS_PMU_PEC5_SOUTH_ABB_REQ_SELECT, /**< Select south abb request on PEC5*/
- 	IX_PERFPROF_ACC_BUS_PMU_PEC5_SOUTH_ABB_OWN_SELECT, /**< Select south abb own on PEC5*/
- 	IX_PERFPROF_ACC_BUS_PMU_PEC5_SOUTH_BUS_IDLE_SELECT, /**< Select south bus idle on PEC5*/
-
- 	IX_PERFPROF_ACC_BUS_PMU_PEC5_NORTH_NPEB_GRANT_SELECT, /**< Select north NPEB grant on PEC5*/
- 	IX_PERFPROF_ACC_BUS_PMU_PEC5_NORTH_NPEB_XFER_SELECT, /**< Select north NPEB transfer on PEC5*/
- 	IX_PERFPROF_ACC_BUS_PMU_PEC5_NORTH_NPEB_RETRY_SELECT, /**< Select north NPEB retry on PEC5*/
- 	IX_PERFPROF_ACC_BUS_PMU_PEC5_NORTH_NPEB_REQ_SELECT, /**< Select north NPEB request on PEC5*/
- 	IX_PERFPROF_ACC_BUS_PMU_PEC5_NORTH_NPEB_OWN_SELECT, /**< Select north NPEB own on PEC5*/
- 	IX_PERFPROF_ACC_BUS_PMU_PEC5_NORTH_NPEB_WRITE_SELECT, /**< Select north NPEB write on PEC5*/
- 	IX_PERFPROF_ACC_BUS_PMU_PEC5_NORTH_NPEB_READ_SELECT, /**< Select north NPEB read on PEC5*/
-
- 	IX_PERFPROF_ACC_BUS_PMU_PEC5_SDR_4_HIT_SELECT, /**< Select north sdram4 hit on PEC5*/
- 	IX_PERFPROF_ACC_BUS_PMU_PEC5_SDR_5_HIT_SELECT, /**< Select north sdram5 hit on PEC5*/
- 	IX_PERFPROF_ACC_BUS_PMU_PEC5_SDR_6_HIT_SELECT, /**< Select north sdram6 hit on PEC5*/
- 	IX_PERFPROF_ACC_BUS_PMU_PEC5_SDR_7_HIT_SELECT, /**< Select north sdram7 hit on PEC5*/
- 	IX_PERFPROF_ACC_BUS_PMU_PEC5_SDR_0_MISS_SELECT, /**< Select north sdram0 miss on PEC5*/
- 	IX_PERFPROF_ACC_BUS_PMU_PEC5_SDR_1_MISS_SELECT, /**< Select north sdram1 miss on PEC5*/
- 	IX_PERFPROF_ACC_BUS_PMU_PEC5_SDR_2_MISS_SELECT, /**< Select north sdram2 miss on PEC5*/
- 	IX_PERFPROF_ACC_BUS_PMU_PEC5_SDR_3_MISS_SELECT /**< Select north sdram3 miss on PEC5*/
-} IxPerfProfAccBusPmuEventCounters5;
-
-/**
- * @ingroup IxPerfProfAcc
- *
- * @enum IxPerfProfAccBusPmuEventCounters6
- *
- * @brief Type of bus pmu events supported on PEC 6.
- *
- * Lists all bus pmu events.
- */
-typedef enum
-{
-	IX_PERFPROF_ACC_BUS_PMU_PEC6_SOUTH_PCI_GRANT_SELECT = 113, /**< Select south pci grant on PEC6*/
- 	IX_PERFPROF_ACC_BUS_PMU_PEC6_SOUTH_PCI_XFER_SELECT, /**< Select south pci transfer on PEC6*/
- 	IX_PERFPROF_ACC_BUS_PMU_PEC6_SOUTH_PCI_RETRY_SELECT, /**< Select south pci retry on PEC6*/
- 	IX_PERFPROF_ACC_BUS_PMU_PEC6_SOUTH_PCI_SPLIT_SELECT, /**< Select south pci split on PEC6*/
- 	IX_PERFPROF_ACC_BUS_PMU_PEC6_SOUTH_PCI_REQ_SELECT, /**< Select south pci request on PEC6*/
- 	IX_PERFPROF_ACC_BUS_PMU_PEC6_SOUTH_PCI_OWN_SELECT, /**< Select south pci own on PEC6*/
- 	IX_PERFPROF_ACC_BUS_PMU_PEC6_SOUTH_BUS_WRITE_SELECT, /**< Select south pci write on PEC6*/
-
- 	IX_PERFPROF_ACC_BUS_PMU_PEC6_NORTH_NPEC_GRANT_SELECT, /**< Select north NPEC grant on PEC6*/
- 	IX_PERFPROF_ACC_BUS_PMU_PEC6_NORTH_NPEC_XFER_SELECT, /**< Select north NPEC transfer on PEC6*/
- 	IX_PERFPROF_ACC_BUS_PMU_PEC6_NORTH_NPEC_RETRY_SELECT, /**< Select north NPEC retry on PEC6*/
- 	IX_PERFPROF_ACC_BUS_PMU_PEC6_NORTH_NPEC_REQ_SELECT, /**< Select north NPEC request on PEC6*/
- 	IX_PERFPROF_ACC_BUS_PMU_PEC6_NORTH_NPEC_OWN_SELECT, /**< Select north NPEC own on PEC6*/
- 	IX_PERFPROF_ACC_BUS_PMU_PEC6_NORTH_NPEB_WRITE_SELECT, /**< Select north NPEB write on PEC6*/
- 	IX_PERFPROF_ACC_BUS_PMU_PEC6_NORTH_NPEC_READ_SELECT, /**< Select north NPEC read on PEC6*/
-
- 	IX_PERFPROF_ACC_BUS_PMU_PEC6_SDR_5_HIT_SELECT, /**< Select sdram5 hit on PEC6*/
- 	IX_PERFPROF_ACC_BUS_PMU_PEC6_SDR_6_HIT_SELECT, /**< Select sdram6 hit on PEC6*/
- 	IX_PERFPROF_ACC_BUS_PMU_PEC6_SDR_7_HIT_SELECT, /**< Select sdram7 hit on PEC6*/
- 	IX_PERFPROF_ACC_BUS_PMU_PEC6_SDR_0_HIT_SELECT, /**< Select sdram0 hit on PEC6*/
- 	IX_PERFPROF_ACC_BUS_PMU_PEC6_SDR_1_MISS_SELECT, /**< Select sdram1 miss on PEC6*/
- 	IX_PERFPROF_ACC_BUS_PMU_PEC6_SDR_2_MISS_SELECT, /**< Select sdram2 miss on PEC6*/
- 	IX_PERFPROF_ACC_BUS_PMU_PEC6_SDR_3_MISS_SELECT, /**< Select sdram3 miss on PEC6*/
- 	IX_PERFPROF_ACC_BUS_PMU_PEC6_SDR_4_MISS_SELECT /**< Select sdram4 miss on PEC6*/
-} IxPerfProfAccBusPmuEventCounters6;
-
-/**
- * @ingroup IxPerfProfAcc
- *
- * @enum IxPerfProfAccBusPmuEventCounters7
- *
- * @brief Type of bus pmu events supported on PEC 7.
- *
- * Lists all bus pmu events.
- */
-typedef enum
-{
- 	IX_PERFPROF_ACC_BUS_PMU_PEC7_SOUTH_APB_RETRY_SELECT = 135, /**< Select south apb retry on PEC7*/
- 	IX_PERFPROF_ACC_BUS_PMU_PEC7_SOUTH_APB_REQ_SELECT, /**< Select south apb request on PEC7*/
- 	IX_PERFPROF_ACC_BUS_PMU_PEC7_SOUTH_APB_OWN_SELECT, /**< Select south apb own on PEC7*/
- 	IX_PERFPROF_ACC_BUS_PMU_PEC7_SOUTH_BUS_READ_SELECT, /**< Select south bus read on PEC7*/
- 	IX_PERFPROF_ACC_BUS_PMU_PEC7_CYCLE_COUNT_SELECT /**< Select cycle count on PEC7*/
-} IxPerfProfAccBusPmuEventCounters7;
-
-/** 
- * @ingroup IxPerfProfAcc 
- * 
- * @enum IxPerfProfAccXscalePmuEvent 
- * 
- * @brief Type of xscale pmu events supported 
- * 
- * Lists all xscale pmu events.  The maximum is a default value that the user 
- * should not exceed. 
- */ 
-typedef enum 
-{
-    IX_PERFPROF_ACC_XSCALE_PMU_EVENT_CACHE_MISS=0,      /**< cache miss*/ 
-    IX_PERFPROF_ACC_XSCALE_PMU_EVENT_CACHE_INSTRUCTION,/**< cache instruction*/ 
-    IX_PERFPROF_ACC_XSCALE_PMU_EVENT_STALL,     /**< event stall*/ 
-    IX_PERFPROF_ACC_XSCALE_PMU_EVENT_INST_TLB_MISS, /**< instruction tlb miss*/ 
-    IX_PERFPROF_ACC_XSCALE_PMU_EVENT_DATA_TLB_MISS, /**< data tlb miss*/ 
-    IX_PERFPROF_ACC_XSCALE_PMU_EVENT_BRANCH_EXEC,   /**< branch executed*/ 
-    IX_PERFPROF_ACC_XSCALE_PMU_EVENT_BRANCH_MISPREDICT, /**<branch mispredict*/ 
-    IX_PERFPROF_ACC_XSCALE_PMU_EVENT_INST_EXEC, /**< instruction executed*/ 
-    IX_PERFPROF_ACC_XSCALE_PMU_EVENT_FULL_EVERYCYCLE,   /**< 
-                                                         *Stall - data cache 
-                                                         *buffers are full. 
-							 							 *This event occurs 
-							 							 *every cycle where 
-							 							 *condition present 
-							 							 */ 
-    IX_PERFPROF_ACC_XSCALE_PMU_EVENT_ONCE,    /**< 
-                                               *Stall - data cache buffers are 
-					       					   *full.This event occurs once 
-					       					   *for each contiguous sequence 
-					       					   */ 
-    IX_PERFPROF_ACC_XSCALE_PMU_EVENT_DATA_CACHE_ACCESS, /**< data cache access*/ 
-    IX_PERFPROF_ACC_XSCALE_PMU_EVENT_DATA_CACHE_MISS,   /**< data cache miss*/ 
-    IX_PERFPROF_ACC_XSCALE_PMU_EVENT_DATA_CACHE_WRITEBACK,  /**<data cache 
-                                                             *writeback 
-						             						 */ 
-    IX_PERFPROF_ACC_XSCALE_PMU_EVENT_SW_CHANGE_PC,  /**< sw change pc*/ 
-    IX_PERFPROF_ACC_XSCALE_PMU_EVENT_MAX    /**< max value*/ 
-} IxPerfProfAccXscalePmuEvent;
-
-/**
- * @ingroup IxPerfProfAcc
- *
- * @enum IxPerfProfAccStatus
- *
- * @brief Invalid Status Definitions  
- *
- * These status will be used by the APIs to return to the user.
- */
-typedef enum
-{
-	IX_PERFPROF_ACC_STATUS_SUCCESS = IX_SUCCESS,    /**< success*/
-	IX_PERFPROF_ACC_STATUS_FAIL = IX_FAIL,          /**< fail*/
-	IX_PERFPROF_ACC_STATUS_ANOTHER_UTIL_IN_PROGRESS,/**<another utility in 
-													 *progress
-													 */ 
-	IX_PERFPROF_ACC_STATUS_XCYCLE_MEASUREMENT_IN_PROGRESS, /**<measurement in
-															*progress
-															*/
-	IX_PERFPROF_ACC_STATUS_XCYCLE_NO_BASELINE, /**<no baseline yet*/	 
-	IX_PERFPROF_ACC_STATUS_XCYCLE_MEASUREMENT_REQUEST_OUT_OF_RANGE, /**< 
-															* Measurement chosen 
-															* is out of range
-															*/
-	IX_PERFPROF_ACC_STATUS_XCYCLE_PRIORITY_SET_FAIL,  /**<
-	                                                     * Cannot set 
-														 * task priority
-	                                                     */
-	IX_PERFPROF_ACC_STATUS_XCYCLE_THREAD_CREATE_FAIL, /**< 
-	                                                     * Fail create thread
-	                                                     */
-	IX_PERFPROF_ACC_STATUS_XCYCLE_PRIORITY_RESTORE_FAIL,  /**<
-	                                                         *cannot restore
-	                                                         *priority
-	                                                         */
-	IX_PERFPROF_ACC_STATUS_XCYCLE_MEASUREMENT_NOT_RUNNING, /**< xcycle not running*/
-   	IX_PERFPROF_ACC_STATUS_XSCALE_PMU_NUM_INVALID, /**< invalid number 
-   	                                                *entered
-   	                                                */
-	IX_PERFPROF_ACC_STATUS_XSCALE_PMU_EVENT_INVALID, /**< invalid pmu event*/
-	IX_PERFPROF_ACC_STATUS_XSCALE_PMU_START_NOT_CALLED, /**<a start process
-							     						 *was not called 
-							     						 *before attempting
-							     						 *a stop or results
-							     						 *get
-							     						 */
-	IX_PERFPROF_ACC_STATUS_BUS_PMU_MODE_ERROR,  /**< invalid mode*/
-	IX_PERFPROF_ACC_STATUS_BUS_PMU_PEC1_ERROR,	/**< invalid pec1 entered*/
-	IX_PERFPROF_ACC_STATUS_BUS_PMU_PEC2_ERROR,	/**< invalid pec2 entered*/
-	IX_PERFPROF_ACC_STATUS_BUS_PMU_PEC3_ERROR,	/**< invalid pec3 entered*/
-	IX_PERFPROF_ACC_STATUS_BUS_PMU_PEC4_ERROR,	/**< invalid pec4 entered*/
-	IX_PERFPROF_ACC_STATUS_BUS_PMU_PEC5_ERROR,	/**< invalid pec5 entered*/
-	IX_PERFPROF_ACC_STATUS_BUS_PMU_PEC6_ERROR,	/**< invalid pec6 entered*/
-	IX_PERFPROF_ACC_STATUS_BUS_PMU_PEC7_ERROR,	/**< invalid pec7 entered*/
-	IX_PERFPROF_ACC_STATUS_BUS_PMU_START_NOT_CALLED, /**<a start process
-							     					 *was not called 
-							     					 *before attempting
-							     					 *a stop 
-													 */
-        IX_PERFPROF_ACC_STATUS_COMPONENT_NOT_SUPPORTED /**<Device or OS does not support component*/
-} IxPerfProfAccStatus;
-
-/**
- * @ingroup IxPerfProfAcc 
- * 
- * @enum IxPerfProfAccBusPmuMode
- *
- * @brief State selection of counters.
- *
- * These states will be used to determine the counters whose values are to be
- * read.
- */
-typedef enum
-{
-        IX_PERFPROF_ACC_BUS_PMU_MODE_HALT=0,   /**< halt state*/
-        IX_PERFPROF_ACC_BUS_PMU_MODE_SOUTH,    /**< south state*/
-        IX_PERFPROF_ACC_BUS_PMU_MODE_NORTH,    /**< north state*/
-        IX_PERFPROF_ACC_BUS_PMU_MODE_SDRAM    /**< SDRAM state*/
-} IxPerfProfAccBusPmuMode;
-
-/*
- * Section for prototypes interface functions
- */
-
-/**
- * @ingroup IxPerfProfAcc
- *
- * @fn ixPerfProfAccXscalePmuEventCountStart(
-   		BOOL clkCntDiv,
-   		UINT32 numEvents,
-  	 	IxPerfProfAccXscalePmuEvent pmuEvent1,
-   		IxPerfProfAccXscalePmuEvent pmuEvent2,
-   		IxPerfProfAccXscalePmuEvent pmuEvent3,
-   		IxPerfProfAccXscalePmuEvent pmuEvent4 )
- *
- * @brief This API will start the clock and event counting
- *
- * @param	clkCntDiv BOOL [in] - enables/disables the clock divider. When 
- *			true, the divider is enabled and the clock count will be incremented
- *          by one at each 64th processor clock cycle.  When false, the divider
- *			is disabled and the clock count will be incremented at every 
- *			processor clock cycle.
- * @param 	numEvents UINT32 [in] - the number of PMU events that are to be 
- *	  		monitored as specified by the user. For clock counting only, this
- *	  	 	is set to zero.
- * @param 	pmuEvent1 @ref IxPerfProfAccXscalePmuEvent [in] - the specific PMU 
- *    		event to be monitored by counter 1
- * @param 	pmuEvent2 @ref IxPerfProfAccXscalePmuEvent [in] - the specific PMU 
- *    		event to be monitored by counter 2 
- * @param	pmuEvent3 @ref IxPerfProfAccXscalePmuEvent [in] - the specific PMU 
- *    		event to be monitored by counter 3
- * @param 	pmuEvent4 @ref IxPerfProfAccXscalePmuEvent [in] - the specific PMU 
- *    		event to be monitored by counter 4
- *
- * This API will start the clock and xscale PMU event counting.  Up to 
- * 4 events can be monitored simultaneously. This API has to be called before
- * ixPerfProfAccXscalePmuEventCountStop can be called.
- *
- * @return 
- *	- IX_PERFPROF_ACC_STATUS_SUCCESS if clock and events counting are 
- *        started successfully
- *	- IX_PERFPROF_ACC_STATUS_FAIL if unable to start the counting
- *	- IX_PERFPROF_ACC_STATUS_XSCALE_PMU_NUM_INVALID if the number of events 
- *        specified is out of the valid range
- *	- IX_PERFPROF_ACC_STATUS_XSCALE_PMU_EVENT_INVALID if the value of the PMU 
- * 	  event specified does not exist
- * 	- IX_PERFPROF_ACC_STATUS_ANOTHER_UTIL_IN_PROGRESS - another utility is 
- * 	  running 
- *              
- * @li   Reentrant    : no
- * @li   ISR Callable : no
- *
- */
-PUBLIC IxPerfProfAccStatus
-ixPerfProfAccXscalePmuEventCountStart(
-	BOOL clkCntDiv,
-	UINT32 numEvents,
-	IxPerfProfAccXscalePmuEvent pmuEvent1,
-	IxPerfProfAccXscalePmuEvent pmuEvent2,
-	IxPerfProfAccXscalePmuEvent pmuEvent3,
-	IxPerfProfAccXscalePmuEvent pmuEvent4 );
-
-/**
- * @ingroup IxPerfProfAcc
- *
- * @fn ixPerfProfAccXscalePmuEventCountStop (
-   IxPerfProfAccXscalePmuResults *eventCountStopResults) 
- *
- * @brief This API will stop the clock and event counting
- *
- * @param *eventCountStopResults @ref IxPerfProfAccXscalePmuResults [out] - pointer 
- *		  to struct containing results of counters and their overflow. It is the 
- * 		  users's responsibility to allocate the memory for this pointer. 
- *
- * This API will stop the clock and xscale PMU events that are being counted.
- * The results of the clock and events count will be stored in the pointer 
- * allocated by the user. It can only be called once 
- * IxPerfProfAccEventCountStart has been called. 
- *
- * @return 
- *      - IX_PERFPROF_ACC_STATUS_SUCCESS if clock and events counting are 
- *        stopped successfully
- *      - IX_PERFPROF_ACC_STATUS_XSCALE_PMU_START_NOT_CALLED if
- *        ixPerfProfAccXscalePmuEventCountStart is not called first.
- *              
- * @li   Reentrant    : no
- * @li   ISR Callable : no
- *
- */
-
-PUBLIC IxPerfProfAccStatus 
-ixPerfProfAccXscalePmuEventCountStop(
-   IxPerfProfAccXscalePmuResults *eventCountStopResults); 
-
-/**
- * @ingroup IxPerfProfAcc
- *
- * @fn ixPerfProfAccXscalePmuTimeSampStart(
-   UINT32 samplingRate,
-   BOOL clkCntDiv) 
- *
- * @brief Starts the time based sampling
- *
- * @param	samplingRate UINT32 [in] - sampling rate is the number of
- *       	clock counts before a counter overflow interrupt is generated,
- *        	at which, a sample is taken; the rate specified cannot be greater
- *          than the counter size of 32bits or set to zero.
- * @param 	clkCntDiv BOOL [in] - enables/disables the clock divider. When 
- *		true, the divider is enabled and the clock count will be incremented
- *          by one at each 64th processor clock cycle.  When false, the divider
- *			is disabled and the clock count will be incremented at every 
- *			processor clock cycle. 
- *
- * This API starts the time based sampling to determine the frequency with 
- * which lines of code are being executed.  Sampling is done at the rate 
- * specified by the user.  At each sample,the value of the program counter
- * is determined.  Each of these occurrences are recorded to determine the 
- * frequency with which the Xscale code is being executed. This API has to be 
- * called before ixPerfProfAccXscalePmuTimeSampStop can be called.
- *
- * @return
- *	- IX_PERFPROF_ACC_STATUS_SUCCESS if time based sampling is started 
- *        successfully
- *	- IX_PERFPROF_ACC_STATUS_FAIL if unable to start the sampling
- * 	- IX_PERFPROF_ACC_STATUS_ANOTHER_UTIL_IN_PROGRESS - another utility is 
- *	  running 
- *              
- * @li   Reentrant    : no
- * @li   ISR Callable : no
- *
- */
-PUBLIC IxPerfProfAccStatus 
-ixPerfProfAccXscalePmuTimeSampStart(
-	UINT32 samplingRate, 
-	BOOL clkCntDiv);
-
-/**
- * @ingroup IxPerfProfAcc
- *
- * @fn ixPerfProfAccXscalePmuTimeSampStop(
-   IxPerfProfAccXscalePmuEvtCnt *clkCount,
-   IxPerfProfAccXscalePmuSamplePcProfile *timeProfile)
- *
- * @brief Stops the time based sampling
- *
- * @param	*clkCount @ref IxPerfProfAccXscalePmuEvtCnt [out]  - pointer to the 
- *			struct containing the final clock count and its overflow.  It is the
- *			user's responsibility to allocate the memory for this pointer.
- * @param 	*timeProfile @ref IxPerfProfAccXscalePmuSamplePcProfile [out] -
- *          pointer to the array of profiles for each program counter value;
- *          the user should set the size of the array to 
- *			IX_PERFPROF_ACC_XSCALE_PMU_MAX_PROFILE_SAMPLES.  It is the user's 
- * 			responsibility to allocate the memory for this pointer.
- *
- * This API stops the time based sampling.  The results are stored in the 
- * pointers allocated by the user.  It can only be called once
- * ixPerfProfAccXscalePmuTimeSampStart has been called.
- *
- * @return
- *	- IX_PERFPROF_ACC_STATUS_SUCCESS if time based sampling is stopped 
- *        successfully
- *	- IX_PERFPROF_ACC_STATUS_XSCALE_PMU_START_NOT_CALLED if
- *	  ixPerfProfAccXscalePmuTimeSampStart not called first
- *              
- * @li   Reentrant    : no
- * @li   ISR Callable : no
- *
- */
-PUBLIC IxPerfProfAccStatus
-ixPerfProfAccXscalePmuTimeSampStop(
-	IxPerfProfAccXscalePmuEvtCnt *clkCount,
-	IxPerfProfAccXscalePmuSamplePcProfile *timeProfile);
-
-/**
- * @ingroup IxPerfProfAcc
- *
- * @fn ixPerfProfAccXscalePmuEventSampStart(
-   UINT32 numEvents,
-   IxPerfProfAccXscalePmuEvent pmuEvent1,
-   UINT32 eventRate1,
-   IxPerfProfAccXscalePmuEvent pmuEvent2,
-   UINT32 eventRate2,
-   IxPerfProfAccXscalePmuEvent pmuEvent3,
-   UINT32 eventRate3,
-   IxPerfProfAccXscalePmuEvent pmuEvent4,
-   UINT32 eventRate4)
- *
- * @brief Starts the event based sampling
- *
- * @param	numEvents UINT32 [in] - the number of PMU events that are 
- *	  		to be monitored as specified by the user. The value should be
- *          between 1-4 events at a time.
- * @param 	pmuEvent1 @ref IxPerfProfAccXscalePmuEvent [in] - the specific PMU 
- *    		event to be monitored by counter 1
- * @param 	eventRate1 UINT32 [in] - sampling rate of counter 1. The rate is 
- *			the number of events before a sample taken.  If 0 is specified, the
- *			the full counter value (0xFFFFFFFF) is used. The rate must not be 
- *			greater than the full counter value.
- * @param 	pmuEvent2 @ref IxPerfProfAccXscalePmuEvent [in] - the specific PMU 
- *    		event to be monitored by counter 2 
- * @param 	eventRate2 UINT32 [in] -  sampling rate of counter 2. The rate is 
- *			the number of events before a sample taken. If 0 is specified, the 
- *			full counter value (0xFFFFFFFF) is used. The rate must not be 
- *          greater than the full counter value.
- * @param 	pmuEvent3 @ref IxPerfProfAccXscalePmuEvent [in] - the specific PMU 
- *    		event to be monitored by counter 3
- * @param 	eventRate3 UINT32 [in] -  sampling rate of counter 3. The rate is 
- *			the number of events before a sample taken.  If 0 is specified, the 
- *			full counter value (0xFFFFFFFF) is used.  The rate must not be 
- *          greater than the full counter value.
- * @param 	pmuEvent4 @ref IxPerfProfAccXscalePmuEvent [in] - the specific PMU 
- *    		event to be monitored by counter 4
- * @param 	eventRate4 UINT32 [in] -  sampling rate of counter 4. The rate is 
- *			the number of events before a sample taken.  If 0 is specified, the 
- *			full counter value (0xFFFFFFFF) is used. The rate must not be 
- *          greater than the full counter value.
- *
- * Starts the event based sampling to determine the frequency with 
- * which events are being executed.  The sampling rate is the number of events,
- * as specified by the user,  before a counter overflow interrupt is 
- * generated.  A sample is taken at each counter overflow interrupt.  At each
- * sample,the value of the program counter determines the corresponding 
- * location in the code.  Each of these occurrences are recorded to determine 
- * the frequency with which the Xscale code in each event is executed. This API
- * has to be called before ixPerfProfAccXscalePmuEventSampStop can be called.
- *
- * @return
- *	- IX_PERFPROF_ACC_STATUS_SUCCESS if event based sampling is started 
- *	  successfully
- *	- IX_PERFPROF_ACC_STATUS_FAIL if unable to start the sampling
- *	- IX_PERFPROF_ACC_STATUS_XSCALE_PMU_NUM_INVALID if the number of events 
- *        specified is out of the valid range
- *	- IX_PERFPROF_ACC_STATUS_XSCALE_PMU_EVENT_INVALID if the value of the
- *        PMU event specified does not exist
- *      - IX_PERFPROF_ACC_STATUS_ANOTHER_UTIL_IN_PROGRESS - another utility is
- *        running 
- *              
- * @li   Reentrant    : no
- * @li   ISR Callable : no
- *
- */
-PUBLIC IxPerfProfAccStatus
-ixPerfProfAccXscalePmuEventSampStart(
-	UINT32 numEvents,
-	IxPerfProfAccXscalePmuEvent pmuEvent1,
-	UINT32 eventRate1,
-    IxPerfProfAccXscalePmuEvent pmuEvent2,
-    UINT32 eventRate2,
-    IxPerfProfAccXscalePmuEvent pmuEvent3,
-    UINT32 eventRate3,
-    IxPerfProfAccXscalePmuEvent pmuEvent4,
-    UINT32 eventRate4);
-
-/**
- * @ingroup IxPerfProfAcc
- *
- * @fn ixPerfProfAccXscalePmuEventSampStop(
-   IxPerfProfAccXscalePmuSamplePcProfile *eventProfile1,
-   IxPerfProfAccXscalePmuSamplePcProfile *eventProfile2,
-   IxPerfProfAccXscalePmuSamplePcProfile *eventProfile3,
-   IxPerfProfAccXscalePmuSamplePcProfile *eventProfile4)
- *
- * @brief Stops the event based sampling
- *
- * @param       *eventProfile1 @ref IxPerfProfAccXscalePmuSamplePcProfile [out] - 
- *              pointer to the array of profiles for each program counter value;
- *              the user should set the size of the array to 
- *				IX_PERFPROF_ACC_XSCALE_PMU_MAX_PROFILE_SAMPLES. It is the 
- *				users's responsibility to allocate memory for this pointer.
- * @param       *eventProfile2 @ref IxPerfProfAccXscalePmuSamplePcProfile [out] - 
- *              pointer to the array of profiles for each program counter value;
- *              the user should set the size of the array to 
- *				IX_PERFPROF_ACC_XSCALE_PMU_MAX_PROFILE_SAMPLES.  It is the 
- *				users's responsibility to allocate memory for this pointer.
- * @param       *eventProfile3 @ref IxPerfProfAccXscalePmuSamplePcProfile [out] - 
- *              pointer to the array of profiles for each program counter value;
- *              the user should set the size of the array to 
- *				IX_PERFPROF_ACC_XSCALE_PMU_MAX_PROFILE_SAMPLES.  It is the 
- *				users's responsibility to allocate memory for this pointer.
- * @param       *eventProfile4 @ref IxPerfProfAccXscalePmuSamplePcProfile [out] - 
- *              pointer to the array of profiles for each program counter value;
- *              the user should set the size of the array to 
- *				IX_PERFPROF_ACC_XSCALE_PMU_MAX_PROFILE_SAMPLES.  It is the 
- *				users's responsibility to allocate memory for this pointer.
- *
- * This API stops the event based sampling.  The results are stored in the 
- * pointers allocated by the user.  It can only be called once 
- * ixPerfProfAccEventSampStart has been called.
- *
- * @return 
- *      - IX_PERFPROF_ACC_STATUS_SUCCESS if event based sampling is stopped 
- *         successfully
- *      - IX_PERFPROF_ACC_STATUS_XSCALE_PMU_START_NOT_CALLED if
- *          ixPerfProfAccEventSampStart not called first.
- *              
- * @li   Reentrant    : no
- * @li   ISR Callable : no
- *
- */
-PUBLIC IxPerfProfAccStatus 
-ixPerfProfAccXscalePmuEventSampStop(
-    IxPerfProfAccXscalePmuSamplePcProfile *eventProfile1,
-    IxPerfProfAccXscalePmuSamplePcProfile *eventProfile2,
-    IxPerfProfAccXscalePmuSamplePcProfile *eventProfile3,
-    IxPerfProfAccXscalePmuSamplePcProfile *eventProfile4);
-
-/**                                                                             
- * @ingroup IxPerfProfAcc                                                      
- *                                                                              
- * @fn ixPerfProfAccXscalePmuResultsGet(IxPerfProfAccXscalePmuResults *results)     
- *                                                                              
- * @brief Reads the current value of the counters and their overflow                                        
- *                                                                              
- * @param *results @ref IxPerfProfAccXscalePmuResults [out] - pointer to the 
-          results struct.  It is the user's responsibility to allocate memory
-          for this pointer
- *                                                                              
- * This API reads the value of all four event counters and the clock counter, 
- * and the associated overflows.  It does not give results associated with 
- * sampling, i.e. PC and their frequencies.  This API can be called at any time
- * once a process has been started. If it is called before a process has started
- * the user should be aware that the values it contains are default values and 
- * might be meaningless.  The values of the counters are stored in the pointer 
- * allocated by the client.
- *                                                                    
- * @return - none
- *              
- * @li   Reentrant    : no
- * @li   ISR Callable : no
- *
- */                                                                             
-PUBLIC void                                                     
-ixPerfProfAccXscalePmuResultsGet(IxPerfProfAccXscalePmuResults *results);    
-
-/**
- * @ingroup IxPerfProfAcc
- * 
- * @fn ixPerfProfAccBusPmuStart(
-        IxPerfProfAccBusPmuMode mode, 
-        IxPerfProfAccBusPmuEventCounters1 pecEvent1,
-        IxPerfProfAccBusPmuEventCounters2 pecEvent2, 
-        IxPerfProfAccBusPmuEventCounters3 pecEvent3, 
-        IxPerfProfAccBusPmuEventCounters4 pecEvent4,
-        IxPerfProfAccBusPmuEventCounters5 pecEvent5, 
-        IxPerfProfAccBusPmuEventCounters6 pecEvent6, 
-        IxPerfProfAccBusPmuEventCounters7 pecEvent7)
- * @brief Initializes all the counters and selects events to be monitored.
- *
- * Function initializes all the counters and assigns the events associated 
- * with the counters. Users send in the mode and events they want to count.
- * This API verifies if the combination chosen is appropriate 
- * and sets all the registers accordingly. Selecting HALT mode will result
- * in an error. User should use ixPerfProfAccBusPmuStop() to HALT. 
- * 
- * 
- * @param mode @ref IxPerfProfAccStateBusPmuMode [in] - Mode selection.
- * @param pecEvent1 @ref IxPerfProfAccBusPmuEventCounters1 [in] - Event for PEC1.
- * @param pecEvent2 @ref IxPerfProfAccBusPmuEventCounters2 [in] - Event for PEC2.
- * @param pecEvent3 @ref IxPerfProfAccBusPmuEventCounters3 [in] - Event for PEC3.
- * @param pecEvent4 @ref IxPerfProfAccBusPmuEventCounters4 [in] - Event for PEC4.
- * @param pecEvent5 @ref IxPerfProfAccBusPmuEventCounters5 [in] - Event for PEC5.
- * @param pecEvent6 @ref IxPerfProfAccBusPmuEventCounters6 [in] - Event for PEC6.
- * @param pecEvent7 @ref IxPerfProfAccBusPmuEventCounters7 [in] - Event for PEC7.
- *
- * @return 
- *      - IX_PERFPROF_ACC_STATUS_SUCCESS - Initialization executed 
- *        successfully.  
- *      - IX_PERFPROF_ACC_STATUS_BUS_PMU_MODE_ERROR - Error in selection of 
- * 		  mode. Only NORTH, SOUTH and SDRAM modes are allowed. 
- *      - IX_PERFPROF_ACC_STATUS_BUS_PMU_PEC1_ERROR - Error in selection of 
- *        event for PEC1
- *      - IX_PERFPROF_ACC_STATUS_BUS_PMU_PEC2_ERROR - Error in selection of 
- *        event for PEC2 
- *      - IX_PERFPROF_ACC_STATUS_BUS_PMU_PEC3_ERROR - Error in selection of 
- *        event for PEC3
- *      - IX_PERFPROF_ACC_STATUS_BUS_PMU_PEC4_ERROR - Error in selection of 
- *        event for PEC4
- *      - IX_PERFPROF_ACC_STATUS_BUS_PMU_PEC5_ERROR - Error in selection of 
- *        event for PEC5
- *      - IX_PERFPROF_ACC_STATUS_BUS_PMU_PEC6_ERROR - Error in selection of 
- *        event for PEC6
- *      - IX_PERFPROF_ACC_STATUS_BUS_PMU_PEC7_ERROR - Error in selection of 
- *        event for PEC7
- * 		- IX_PERFPROF_ACC_STATUS_ANOTHER_UTIL_IN_PROGRESS - another utility 
- * 		  is running
- * 		- IX_PERFPROF_ACC_STATUS_FAIL - Failed to start because interrupt 
- * 		  service routine fails to bind.  
- *              
- * @li   Reentrant    : no
- * @li   ISR Callable : no
- *
- **/
-PUBLIC 
-IxPerfProfAccStatus ixPerfProfAccBusPmuStart (
-        IxPerfProfAccBusPmuMode mode, 
-        IxPerfProfAccBusPmuEventCounters1 pecEvent1,
-        IxPerfProfAccBusPmuEventCounters2 pecEvent2, 
-        IxPerfProfAccBusPmuEventCounters3 pecEvent3, 
-        IxPerfProfAccBusPmuEventCounters4 pecEvent4,
-        IxPerfProfAccBusPmuEventCounters5 pecEvent5, 
-        IxPerfProfAccBusPmuEventCounters6 pecEvent6, 
-        IxPerfProfAccBusPmuEventCounters7 pecEvent7);
-
-/**
- * @ingroup IxPerfProfAcc
- * 
- * @fn ixPerfProfAccBusPmuStop(void)
- * @brief Stops all counters. 
- * 
- * This function stops all the PECs by setting the halt bit in the ESR.
- *
- *
- * @return 
- *      - IX_PERFPROF_ACC_STATUS_SUCCESS - Counters successfully halted.
- *      - IX_PERFPROF_ACC_STATUS_FAIL - Counters could'nt be halted. 
- *		- IX_PERFPROF_ACC_STATUS_BUS_PMU_START_NOT_CALLED - the 
- * 		  ixPerfProfAccBusPmuStart() function is not called.
- *              
- * @li   Reentrant    : no
- * @li   ISR Callable : no
- *
- **/
-PUBLIC IxPerfProfAccStatus 
-ixPerfProfAccBusPmuStop (void);
-
-/**
- * @ingroup IxPerfProfAcc
- * 
- * @fn ixPerfProfAccBusPmuResultsGet (
-		IxPerfProfAccBusPmuResults *busPmuResults)
- * @brief Gets values of all counters 
- * 
- * This function is responsible for getting all the counter values from the 
- * lower API and putting it into an array for the user.
- *
- * @param *busPmuResults @ref IxPerfProfAccBusPmuResults [out]
- *           - Pointer to a structure of arrays to store all counter values.
- *
- * @return  none
- *              
- * @li   Reentrant    : no
- * @li   ISR Callable : no
- *
- **/
-PUBLIC void
-ixPerfProfAccBusPmuResultsGet (IxPerfProfAccBusPmuResults *BusPmuResults);
-
-/**
- * @ingroup IxPerfProfAcc
- * 
- * @fn ixPerfProfAccBusPmuPMSRGet (
-	UINT32 *pmsrValue)
- * @brief Get values of PMSR  
- *
- * This API gets the Previous Master Slave Register
- * value and returns it to the calling function. This value indicates
- * which master or slave accessed the north, south bus or sdram last.
- * The value returned by this function is a 32 bit value and is read
- * from location of an offset 0x0024 of the base value.
- *
- * The PMSR value returned indicate the following:
- * <pre>
- *
- * *************************************************************************************
- * *  Bit    *  Name  *       Description                                              *
- * *                                                                                   * 
- * *************************************************************************************
- * * [31:18]  *Reserved*                                                               *
- * *************************************************************************************
- * * [17:12] *  PSS   * Indicates which of the slaves on                               *
- * *         *        *  ARBS was previously                                           *
- * *         *        * accessed by the AHBS.                                          * 
- * *         *        * [000001] Expansion Bus                                         *
- * *         *        * [000010] SDRAM Controller                                      *
- * *         *        * [000100] PCI                                                   *
- * *         *        * [001000] Queue Manager                                         * 
- * *         *        * [010000] AHB-APB Bridge                                        * 
- * *         *        * [100000] Reserved                                              *
- * *************************************************************************************
- * * [11:8]  *  PSN   * Indicates which of the Slaves on                               *
- * *         *        * ARBN was previously                                            *
- * *         *        * accessed the AHBN.                                             *
- * *         *        * [0001] SDRAM Controller                                        *
- * *         *        * [0010] AHB-AHB Bridge                                          *
- * *         *        * [0100] Reserved                                                *
- * *         *        * [1000] Reserved                                                *
- * *************************************************************************************
- * *  [7:4]  *  PMS   * Indicates which of the Masters on                              *
- * *         *        * ARBS was previously                                            *
- * *         *        * accessing the AHBS.                                            *
- * *         *        * [0001] Gasket                                                  *
- * *         *        * [0010] AHB-AHB Bridge                                          *
- * *         *        * [0100] PCI                                                     *
- * *         *        * [1000] APB                                                     *
- * *************************************************************************************
- * *  [3:0]  *  PMN   * Indicates which of the Masters on                              *
- * *         *        * ARBN was previously                                            *
- * *         *        * accessing the AHBN.                                            *
- * *         *        * [0001] NPEA                                                    *
- * *         *        * [0010] NPEB                                                    *
- * *         *        * [0100] NPEC                                                    *
- * *         *        * [1000] Reserved                                                *
- * *************************************************************************************
- * </pre>
- *
- * @param *pmsrValue UINT32 [out] - Pointer to return PMSR value. Users need to
- * 							  allocate storage for psmrValue.   
- *
- * @return none 
- *
- * @li   Reentrant    : no
- * @li   ISR Callable : no
- *
- **/
-PUBLIC void
-ixPerfProfAccBusPmuPMSRGet (
-UINT32 *pmsrValue);
-
-
-/** 
- * The APIs below are specifically used for Xcycle module. 
- **/
-
-/**
- * @ingroup IxPerfProfAcc
- * 
- * @fn ixPerfProfAccXcycleBaselineRun (
-		UINT32 *numBaselineCycle) 
- *
- * @brief Perform baseline for Xcycle 
- *
- * @param *numBaselineCycle UINT32 [out] - pointer to baseline value after
- * 					calibration. Calling function are responsible for 
- *					allocating memory space for this pointer. 
- *
- * Global Data  : 
- *                        - None.
- *                        
- * This function MUST be run before the Xcycle tool can be used. This 
- * function must be run immediately when the OS boots up with no other 
- * addition programs running. 
- * Addition note :     This API will measure the time needed to perform
- * a fix amount of CPU instructions (~ 1 second worth of loops) as a 
- * highest priority task and with interrupt disabled. The time measured
- * is known as the baseline - interpreted as the shortest time 
- * needed to complete the amount of CPU instructions. The baseline is 
- * returned as unit of time in 66Mhz clock tick.  
- *
- * @return 
- *      - IX_PERFPROF_ACC_STATUS_SUCCESS - successful run, result is returned
- *      - IX_PERFPROF_ACC_STATUS_XCYCLE_PRIORITY_SET_FAIL - failed to change
- *         task priority
- *      - IX_PERFPROF_ACC_STATUS_XCYCLE_PRIORITY_RESTORE_FAIL - failed to
- *         restore task priority
- *      - IX_PERFPROF_ACC_STATUS_ANOTHER_UTIL_IN_PROGRESS - another utility 
- *         is running 
- *      - IX_PERFPROF_ACC_STATUS_XCYCLE_MEASUREMENT_IN_PROGRESS  - Xcycle 
- *	  tool has already started
- *              
- * @li   Reentrant    : no
- * @li   ISR Callable : no
- *
- */
-PUBLIC IxPerfProfAccStatus
-ixPerfProfAccXcycleBaselineRun(
-	UINT32 *numBaselineCycle); 
-
-/**
- * @ingroup IxPerfProfAcc
- * 
- * @fn ixPerfProfAccXcycleStart(
-		UINT32 numMeasurementsRequested);
- *
- * @brief Start the measurement
- *
- * @param  numMeasurementsRequested UINT32 [in] - number of measurements 
- *							to perform. Value can be 0 to  
- *							IX_PERFPROF_ACC_XCYCLE_MAX_NUM_OF_MEASUREMENTS. 
- *							0 indicate continuous measurement. 
- *
- * Global Data  : 
- *                        - None.
- *                        
- * 
- * Start the measurements immediately. 
- * numMeasurementsRequested specifies number of measurements to run. 
- * If numMeasurementsRequested is set to 0, the measurement will
- * be performed continuously until IxPerfProfAccXcycleStop()
- * is called.  
- * It is estimated that 1 measurement takes approximately 1 second during 
- * low CPU utilization, therefore 128 measurement takes approximately 128 sec.
- * When CPU utilization is high, the measurement will take longer.
- * This function spawn a task the perform the measurement and returns. 
- * The measurement may continue even if this function returns. 
- *
- * IMPORTANT: Under heavy CPU utilization, the task spawn by this 
- * function may starve and fail to respond to stop command. User 
- * may need to kill the task manually in this case.  
- *
- * There are only IX_PERFPROF_ACC_XCYCLE_MAX_NUM_OF_MEASUREMENTS 
- * storage available so storing is wrapped around if measurements are  
- * more than IX_PERFPROF_ACC_XCYCLE_MAX_NUM_OF_MEASUREMENTS.
- *
- *
- * @return 
- *      - IX_PERFPROF_ACC_STATUS_SUCCESS - successful start, a thread is created 
- *	   in the background to perform measurement. 
- *      - IX_PERFPROF_ACC_STATUS_XCYCLE_PRIORITY_SET_FAIL - failed to set
- *         task priority
- *      - IX_PERFPROF_ACC_STATUS_XCYCLE_THREAD_CREATE_FAIL - failed to create
- *	   thread to perform measurement.
- *      - IX_PERFPROF_ACC_STATUS_XCYCLE_NO_BASELINE - baseline is not available 
- *      - IX_PERFPROF_ACC_STATUS_XCYCLE_MEASUREMENT_REQUEST_OUT_OF_RANGE -
- *	   value is larger than IX_PERFPROF_ACC_XCYCLE_MAX_NUM_OF_MEASUREMENTS
- *      - IX_PERFPROF_ACC_STATUS_XCYCLE_MEASUREMENT_IN_PROGRESS	- Xcycle tool 
- *	   has already started
- *      - IX_PERFPROF_ACC_STATUS_ANOTHER_UTIL_IN_PROGRESS - another utility is 
- *         running
- *              
- * @li   Reentrant    : no
- * @li   ISR Callable : no
- *
- */
-PUBLIC IxPerfProfAccStatus
-ixPerfProfAccXcycleStart (
-	UINT32 numMeasurementsRequested);  
-
-/**
- * @ingroup IxPerfProfAcc
- * 
- * @fn ixPerfProfAccXcycleStop(void); 
- *
- * @brief Stop the Xcycle measurement
- *
- * @param None
- *
- * Global Data  : 
- *                        - None.
- *                        
- * Stop Xcycle measurements immediately. If the measurements have stopped 
- * or not started, return IX_PERFPROF_STATUS_XCYCLE_MEASUREMENT_NOT_RUNNING. 
- * Note: This function does not stop measurement cold. The measurement thread 
- * may need a few seconds to complete the last measurement. User needs to use
- * ixPerfProfAccXcycleInProgress() to determine if measurement is indeed
- * completed. 
- *
- * @return 
- *      - IX_PERFPROF_ACC_STATUS_SUCCESS - successful measurement is stopped
- *      - IX_PERFPROF_STATUS_XCYCLE_MEASUREMENT_NOT_RUNNING - no measurement running
- *              
- * @li   Reentrant    : no
- * @li   ISR Callable : no
- *
- */
-PUBLIC IxPerfProfAccStatus
-ixPerfProfAccXcycleStop(void); 
-
-/**
- * @ingroup IxPerfProfAcc
- * 
- * @fn ixPerfProfAccXcycleResultsGet(
-	IxPerfProfAccXcycleResults *xcycleResult ) 
- *
- * @brief Get the results of Xcycle measurement
- *
- * @param *xcycleResult @ref IxPerfProfAccXcycleResults [out] - Pointer to 
- * 				results of last measurements. Calling function are 
- *				responsible for allocating memory space for this pointer.
- *
- * Global Data  : 
- *                        - None.
- *                        
- * Retrieve the results of last measurement. User should use 
- * ixPerfProfAccXcycleInProgress() to check if measurement is completed 
- * before getting the results.
- *
- * @return 
- *      - IX_PERFPROF_ACC_STATUS_SUCCESS - successful 
- *      - IX_PERFPROF_ACC_STATUS_FAIL - result is not complete. 
- *      - IX_PERFPROF_ACC_STATUS_XCYCLE_NO_BASELINE - baseline is performed
- *      - IX_PERFPROF_ACC_STATUS_XCYCLE_MEASUREMENT_IN_PROGRESS  - Xcycle 
- *         tool is still running
- *              
- * @li   Reentrant    : no
- * @li   ISR Callable : no
- *
- */
-PUBLIC IxPerfProfAccStatus
-ixPerfProfAccXcycleResultsGet (
-    IxPerfProfAccXcycleResults *xcycleResult);  
-
-/**
- * @ingroup IxPerfProfAcc
- * 
- * @fn ixPerfProfAccXcycleInProgress (void)
- *
- * @brief Check if Xcycle is running
- *
- * @param None
- * Global Data  : 
- *                        - None.
- *                        
- * Check if Xcycle measuring task is running. 
- *
- * @return 
- *      - TRUE - Xcycle is running  
- *      - FALSE - Xcycle is not running  
- *              
- * @li   Reentrant    : no
- * @li   ISR Callable : no
- *
- */
-PUBLIC BOOL
-ixPerfProfAccXcycleInProgress(void); 
-
-#ifdef __linux
-/**
- * @ingroup IxPerfProfAcc
- *
- * @fn ixPerfProfAccXscalePmuTimeSampCreateProcFile 
- *
- * @brief Enables proc file to call module function
- *
- * @param None
- *
- * Global Data  :
- *                        - None.
- *
- * This function is declared globally to enable /proc directory system to call
- * and execute the function when the registered file is called. This function is not meant to 
- * be called by the user.
- *
- * @return
- *      - Length of data written to file.
- *
- * @li   Reentrant    : no
- * @li   ISR Callable : no
- *
- */
-int
-ixPerfProfAccXscalePmuTimeSampCreateProcFile (char *buf, char **start, off_t offset,
-                                      int count, int *eof, void *data);
-
-/**
- * @ingroup IxPerfProfAcc
- *
- * @fn ixPerfProfAccXscalePmuEventSampCreateProcFile 
- *
- * @brief Enables proc file to call module function 
- *
- * @param None
- *
- * Global Data  :
- *                        - None.
- *
- * This function is declared globally to enable /proc directory system to call
- * and execute the function when the registered file is called. This function is not meant to 
- * be called by the user.
- *
- * @return
- *      - Length of data written to file.
- *
- * @li   Reentrant    : no
- * @li   ISR Callable : no
- *
- */
-int
-ixPerfProfAccXscalePmuEventSampCreateProcFile (char *buf, char **start, off_t offset,
-                                      int count, int *eof, void *data);
-
-
-#endif /* ifdef __linux */
-
-#endif /* ndef IXPERFPROFACC_H */
-
-/**
- *@} defgroup IxPerfProfAcc 
- */
-
-
diff --git a/arch/arm/cpu/ixp/npe/include/IxQMgr.h b/arch/arm/cpu/ixp/npe/include/IxQMgr.h
deleted file mode 100644
index 165ed96..0000000
--- a/arch/arm/cpu/ixp/npe/include/IxQMgr.h
+++ /dev/null
@@ -1,2210 +0,0 @@
-/**
- * @file    IxQMgr.h
- *
- * @date    30-Oct-2001
- *
- * @brief This file contains the public API of IxQMgr component.
- *
- * Some functions contained in this module are inline to achieve better
- * data-path performance. For this to work, the function definitions are
- * contained in this header file. The "normal" use of inline functions
- * is to use the inline functions in the module in which they are
- * defined. In this case these inline functions are used in external
- * modules and therefore the use of "inline extern". What this means
- * is as follows: if a function foo is declared as "inline extern" this
- * definition is only used for inlining, in no case is the function
- * compiled on its own. If the compiler cannot inline the function it
- * becomes an external reference. Therefore in IxQMgrQAccess.c all
- * inline functions are defined without the "inline extern" specifier
- * and so define the external references. In all other source files
- * including this header file, these funtions are defined as "inline
- * extern".
- *
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- * 
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- * 
- * @par
- * -- End of Copyright Notice --
-*/
-
-/* ------------------------------------------------------
-   Doxygen group definitions
-   ------------------------------------------------------ */
-/**
- * @defgroup IxQMgrAPI IXP400 Queue Manager (IxQMgr) API
- *
- * @brief The public API for the IXP400 QMgr component.
- *
- * IxQMgr is a low level interface to the AHB Queue Manager
- *
- * @{
- */
-
-#ifndef IXQMGR_H
-#define IXQMGR_H
-
-/*
- * User defined include files
- */
-
-#include "IxOsal.h"
-
-/* 
- * Define QMgr's IoMem macros, in DC mode if in LE 
- * regular if in BE. (Note: For Linux LSP gold release
- * may need to adjust mode.
- */
-#if defined (__BIG_ENDIAN)
-
-#define IX_QMGR_INLINE_READ_LONG IX_OSAL_READ_LONG_BE
-#define IX_QMGR_INLINE_WRITE_LONG IX_OSAL_WRITE_LONG_BE
-
-#else
-
-#define IX_QMGR_INLINE_READ_LONG IX_OSAL_READ_LONG_LE_DC
-#define IX_QMGR_INLINE_WRITE_LONG IX_OSAL_WRITE_LONG_LE_DC
-
-#endif
-
-/*
- * #defines and macros
- */
-
-/**
-*
-* @ingroup IxQMgrAPI
-*
-* @def IX_QMGR_INLINE
-*
-* @brief Inline definition, for inlining of Queue Access functions on API
-*
-* Please read the header information in this file for more details on the
-* use of function inlining in this component.
-*
-*/
-
-#ifndef __wince
-
-#ifdef IXQMGRQACCESS_C
-/* If IXQMGRQACCESS_C is set then the IxQmgrQAccess.c is including this file
-   and must instantiate a concrete definition for each inlineable API function
-   whether or not that function actually gets inlined. */
-#    ifdef NO_INLINE_APIS
-#        undef NO_INLINE_APIS
-#    endif
-#    define IX_QMGR_INLINE  /* Empty Define */
-#else
-#    ifndef NO_INLINE_APIS
-#       define IX_QMGR_INLINE IX_OSAL_INLINE_EXTERN
-#    else
-#       define IX_QMGR_INLINE /* Empty Define */
-#    endif
-#endif
-
-#else /* ndef __wince */
-
-#    ifndef NO_INLINE_APIS
-#       define NO_INLINE_APIS
-#    endif
-#    define IX_QMGR_INLINE
-
-#endif
-
-
-/**
-*
-* @ingroup IxQMgrAPI
-*
-* @def IX_QMGR_MAX_NUM_QUEUES
-*
-* @brief Number of queues supported by the AQM.
-*
-* This constant is used to indicate the number of AQM queues
-*
-*/
-#define IX_QMGR_MAX_NUM_QUEUES  64
-
-/**
-*
-* @ingroup IxQMgrAPI
-*
-* @def IX_QMGR_MIN_QID
-*
-* @brief Minimum queue identifier.
-*
-* This constant is used to indicate the smallest queue identifier
-*
-*/
-#define IX_QMGR_MIN_QID IX_QMGR_QUEUE_0
-
-/**
-*
-* @ingroup IxQMgrAPI
-*
-* @def IX_QMGR_MAX_QID
-*
-* @brief Maximum queue identifier.
-*
-* This constant is used to indicate the largest queue identifier
-*
-*/
-#define IX_QMGR_MAX_QID IX_QMGR_QUEUE_63
-
-/**
-*
-* @ingroup IxQMgrAPI
-*
-* @def IX_QMGR_MIN_QUEUPP_QID
-*
-* @brief Minimum queue identifier for reduced functionality queues.
-*
-* This constant is used to indicate Minimum queue identifier for reduced
-* functionality queues
-*
-*/
-#define IX_QMGR_MIN_QUEUPP_QID 32
-
-/**
-*
-* @ingroup IxQMgrAPI
-*
-* @def IX_QMGR_MAX_QNAME_LEN
-*
-* @brief Maximum queue name length.
-*
-* This constant is used to indicate the maximum null terminated string length
-* (excluding '\0') for a queue name
-*
-*/
-#define IX_QMGR_MAX_QNAME_LEN 16
-
-/**
- *
- * @ingroup IxQMgrAPI
- *
- * @def IX_QMGR_WARNING
- *
- * @brief Warning return code.
- *
- * Execution complete, but there is a special case to handle
- *
- */
-#define IX_QMGR_WARNING 2
-
-/**
- *
- * @ingroup IxQMgrAPI
- *
- * @def IX_QMGR_PARAMETER_ERROR
- *
- * @brief Parameter error return code (NULL pointer etc..).
- *
- * parameter error out of range/invalid
- *
- */
-#define IX_QMGR_PARAMETER_ERROR 3
-
-/**
- *
- * @ingroup IxQMgrAPI
- *
- * @def IX_QMGR_INVALID_Q_ENTRY_SIZE
- *
- * @brief Invalid entry size return code.
- *
- * Invalid queue entry size for a queue read/write
- *
- */
-#define IX_QMGR_INVALID_Q_ENTRY_SIZE 4
-
-/**
- *
- * @ingroup IxQMgrAPI
- *
- * @def IX_QMGR_INVALID_Q_ID
- *
- * @brief Invalid queue identifier return code.
- *
- * Invalid queue id, not in range 0-63
- *
- */
-#define IX_QMGR_INVALID_Q_ID 5
-
-/**
- *
- * @ingroup IxQMgrAPI
- *
- * @def IX_QMGR_INVALID_CB_ID
- *
- * @brief Invalid callback identifier return code.
- *
- * Invalid callback id
- */
-#define IX_QMGR_INVALID_CB_ID 6
-
-/**
- *
- * @ingroup IxQMgrAPI
- *
- * @def IX_QMGR_CB_ALREADY_SET
- *
- * @brief Callback set error return code.
- *
- * The specified callback has already been for this queue
- *
- */
-#define IX_QMGR_CB_ALREADY_SET 7
-
-/**
- *
- * @ingroup IxQMgrAPI
- *
- * @def IX_QMGR_NO_AVAILABLE_SRAM
- *
- * @brief Sram consumed return code.
- *
- * All AQM Sram is consumed by queue configuration
- *
- */
-#define IX_QMGR_NO_AVAILABLE_SRAM 8
-
-/**
- *
- * @ingroup IxQMgrAPI
- *
- * @def IX_QMGR_INVALID_INT_SOURCE_ID
- *
- * @brief Invalid queue interrupt source identifier return code.
- *
- * Invalid queue interrupt source given for notification enable
- */
-#define IX_QMGR_INVALID_INT_SOURCE_ID 9
-
-/**
- *
- * @ingroup IxQMgrAPI
- *
- * @def IX_QMGR_INVALID_QSIZE
- *
- * @brief Invalid queue size error code.
- *
- * Invalid queue size not one of 16,32, 64, 128
- *
- *
- */
-#define IX_QMGR_INVALID_QSIZE 10
-
-/**
- *
- * @ingroup IxQMgrAPI
- *
- * @def IX_QMGR_INVALID_Q_WM
- *
- * @brief Invalid queue watermark return code.
- *
- * Invalid queue watermark given for watermark set
- */
-#define IX_QMGR_INVALID_Q_WM 11
-
-/**
- *
- * @ingroup IxQMgrAPI
- *
- * @def IX_QMGR_Q_NOT_CONFIGURED
- *
- * @brief Queue not configured return code.
- *
- * Returned to the client when a function has been called on an unconfigured
- * queue
- *
- */
-#define IX_QMGR_Q_NOT_CONFIGURED 12
-
-/**
- *
- * @ingroup IxQMgrAPI
- *
- * @def IX_QMGR_Q_ALREADY_CONFIGURED
- *
- * @brief Queue already configured return code.
- *
- * Returned to client to indicate that a queue has already been configured
- */
-#define IX_QMGR_Q_ALREADY_CONFIGURED 13
-
-/**
- *
- * @ingroup IxQMgrAPI
- *
- * @def IX_QMGR_Q_UNDERFLOW
- *
- * @brief Underflow return code.
- *
- * Underflow on a queue read has occurred
- *
- */
-#define IX_QMGR_Q_UNDERFLOW 14
-
-/**
- *
- * @ingroup IxQMgrAPI
- *
- * @def IX_QMGR_Q_OVERFLOW
- *
- * @brief Overflow return code.
- *
- * Overflow on a queue write has occurred
- *
- */
-#define IX_QMGR_Q_OVERFLOW 15
-
-/**
- *
- * @ingroup IxQMgrAPI
- *
- * @def IX_QMGR_Q_INVALID_PRIORITY
- *
- * @brief Invalid priority return code.
- *
- * Invalid priority, not one of 0,1,2
- */
-#define IX_QMGR_Q_INVALID_PRIORITY 16
-
-/**
- *
- * @ingroup IxQMgrAPI
- *
- * @def IX_QMGR_ENTRY_INDEX_OUT_OF_BOUNDS
- *
- * @brief  Entry index out of bounds return code.
- *
- * Entry index is greater than number of entries in queue.
- */
-#define IX_QMGR_ENTRY_INDEX_OUT_OF_BOUNDS 17
-
-/**
- *
- * @ingroup IxQMgrAPI
- *
- * @def ixQMgrDispatcherLoopRun
- *
- * @brief  Map old function name ixQMgrDispatcherLoopRun () 
- *         to @ref ixQMgrDispatcherLoopRunA0 ().
- *
- */
-#define ixQMgrDispatcherLoopRun ixQMgrDispatcherLoopRunA0
-
-
-/**
- *
- * @ingroup IxQMgrAPI
- *
- * @def IX_QMGR_QUEUE
- *
- * @brief  Definition of AQM queue numbers
- *
- */
-#define IX_QMGR_QUEUE_0 (0)      /**< Queue Number 0 */
-#define IX_QMGR_QUEUE_1 (1)      /**< Queue Number 1 */
-#define IX_QMGR_QUEUE_2 (2)      /**< Queue Number 2 */
-#define IX_QMGR_QUEUE_3 (3)      /**< Queue Number 3 */
-#define IX_QMGR_QUEUE_4 (4)      /**< Queue Number 4 */
-#define IX_QMGR_QUEUE_5 (5)      /**< Queue Number 5 */
-#define IX_QMGR_QUEUE_6 (6)      /**< Queue Number 6 */
-#define IX_QMGR_QUEUE_7 (7)      /**< Queue Number 7 */
-#define IX_QMGR_QUEUE_8 (8)      /**< Queue Number 8 */
-#define IX_QMGR_QUEUE_9 (9)      /**< Queue Number 9 */
-#define IX_QMGR_QUEUE_10 (10)    /**< Queue Number 10 */
-#define IX_QMGR_QUEUE_11 (11)    /**< Queue Number 11 */
-#define IX_QMGR_QUEUE_12 (12)    /**< Queue Number 12 */
-#define IX_QMGR_QUEUE_13 (13)    /**< Queue Number 13 */
-#define IX_QMGR_QUEUE_14 (14)    /**< Queue Number 14 */
-#define IX_QMGR_QUEUE_15 (15)    /**< Queue Number 15 */
-#define IX_QMGR_QUEUE_16 (16)    /**< Queue Number 16 */
-#define IX_QMGR_QUEUE_17 (17)    /**< Queue Number 17 */
-#define IX_QMGR_QUEUE_18 (18)    /**< Queue Number 18 */
-#define IX_QMGR_QUEUE_19 (19)    /**< Queue Number 19 */
-#define IX_QMGR_QUEUE_20 (20)    /**< Queue Number 20 */
-#define IX_QMGR_QUEUE_21 (21)    /**< Queue Number 21 */
-#define IX_QMGR_QUEUE_22 (22)    /**< Queue Number 22 */
-#define IX_QMGR_QUEUE_23 (23)    /**< Queue Number 23 */
-#define IX_QMGR_QUEUE_24 (24)    /**< Queue Number 24 */
-#define IX_QMGR_QUEUE_25 (25)    /**< Queue Number 25 */
-#define IX_QMGR_QUEUE_26 (26)    /**< Queue Number 26 */
-#define IX_QMGR_QUEUE_27 (27)    /**< Queue Number 27 */
-#define IX_QMGR_QUEUE_28 (28)    /**< Queue Number 28 */
-#define IX_QMGR_QUEUE_29 (29)    /**< Queue Number 29 */
-#define IX_QMGR_QUEUE_30 (30)    /**< Queue Number 30 */
-#define IX_QMGR_QUEUE_31 (31)    /**< Queue Number 31 */
-#define IX_QMGR_QUEUE_32 (32)    /**< Queue Number 32 */
-#define IX_QMGR_QUEUE_33 (33)    /**< Queue Number 33 */
-#define IX_QMGR_QUEUE_34 (34)    /**< Queue Number 34 */
-#define IX_QMGR_QUEUE_35 (35)    /**< Queue Number 35 */
-#define IX_QMGR_QUEUE_36 (36)    /**< Queue Number 36 */
-#define IX_QMGR_QUEUE_37 (37)    /**< Queue Number 37 */
-#define IX_QMGR_QUEUE_38 (38)    /**< Queue Number 38 */
-#define IX_QMGR_QUEUE_39 (39)    /**< Queue Number 39 */
-#define IX_QMGR_QUEUE_40 (40)    /**< Queue Number 40 */
-#define IX_QMGR_QUEUE_41 (41)    /**< Queue Number 41 */
-#define IX_QMGR_QUEUE_42 (42)    /**< Queue Number 42 */
-#define IX_QMGR_QUEUE_43 (43)    /**< Queue Number 43 */
-#define IX_QMGR_QUEUE_44 (44)    /**< Queue Number 44 */
-#define IX_QMGR_QUEUE_45 (45)    /**< Queue Number 45 */
-#define IX_QMGR_QUEUE_46 (46)    /**< Queue Number 46 */
-#define IX_QMGR_QUEUE_47 (47)    /**< Queue Number 47 */
-#define IX_QMGR_QUEUE_48 (48)    /**< Queue Number 48 */
-#define IX_QMGR_QUEUE_49 (49)    /**< Queue Number 49 */
-#define IX_QMGR_QUEUE_50 (50)    /**< Queue Number 50 */
-#define IX_QMGR_QUEUE_51 (51)    /**< Queue Number 51 */
-#define IX_QMGR_QUEUE_52 (52)    /**< Queue Number 52 */
-#define IX_QMGR_QUEUE_53 (53)    /**< Queue Number 53 */
-#define IX_QMGR_QUEUE_54 (54)    /**< Queue Number 54 */
-#define IX_QMGR_QUEUE_55 (55)    /**< Queue Number 55 */
-#define IX_QMGR_QUEUE_56 (56)    /**< Queue Number 56 */
-#define IX_QMGR_QUEUE_57 (57)    /**< Queue Number 57 */
-#define IX_QMGR_QUEUE_58 (58)    /**< Queue Number 58 */
-#define IX_QMGR_QUEUE_59 (59)    /**< Queue Number 59 */
-#define IX_QMGR_QUEUE_60 (60)    /**< Queue Number 60 */
-#define IX_QMGR_QUEUE_61 (61)    /**< Queue Number 61 */
-#define IX_QMGR_QUEUE_62 (62)    /**< Queue Number 62 */
-#define IX_QMGR_QUEUE_63 (63)    /**< Queue Number 63 */
-#define IX_QMGR_QUEUE_INVALID (64)     /**< AQM Queue Number Delimiter */
-
-
-/*
- * Typedefs
- */
-
-/**
- * @typedef IxQMgrQId
- *
- * @ingroup IxQMgrAPI
- *
- * @brief Used in the API to identify the AQM queues.
- *
- */
-typedef int IxQMgrQId;
-
-/**
- * @typedef IxQMgrQStatus
- *
- * @ingroup IxQMgrAPI
- *
- * @brief Queue status.
- *
- * A queues status is defined by its relative fullness or relative emptiness.
- * Each of the queues 0-31 have Nearly Empty, Nearly Full, Empty, Full,
- * Underflow and Overflow status flags. Queues 32-63 have just Nearly Empty and
- * Full status flags.
- * The flags bit positions are outlined below:
- *        
- *        OF - bit-5<br> 
- *        UF - bit-4<br> 
- *         F - bit-3<br> 
- *        NF - bit-2<br> 
- *        NE - bit-1<br>
- *         E - bit-0<br> 
- *
- */
-typedef UINT32 IxQMgrQStatus;
-
-/**
- * @enum IxQMgrQStatusMask
- *
- * @ingroup IxQMgrAPI
- *
- * @brief Queue status mask.
- *
- * Masks for extracting the individual status flags from the IxQMgrStatus
- * word.
- *
- */
-typedef enum
-{
-    IX_QMGR_Q_STATUS_E_BIT_MASK  = 0x1,
-    IX_QMGR_Q_STATUS_NE_BIT_MASK = 0x2,
-    IX_QMGR_Q_STATUS_NF_BIT_MASK = 0x4,
-    IX_QMGR_Q_STATUS_F_BIT_MASK  = 0x8,
-    IX_QMGR_Q_STATUS_UF_BIT_MASK = 0x10,
-    IX_QMGR_Q_STATUS_OF_BIT_MASK = 0x20
-} IxQMgrQStatusMask;
-
-/**
- * @enum IxQMgrSourceId
- *
- * @ingroup IxQMgrAPI
- *
- * @brief Queue interrupt source select.
- *
- * This enum defines the different source conditions on a queue that result in
- * an interupt being fired by the AQM. Interrupt source is configurable for
- * queues 0-31 only. The interrupt source for queues 32-63 is hardwired to the
- * NE(Nearly Empty) status flag.
- *
- */
-typedef enum
-{
-    IX_QMGR_Q_SOURCE_ID_E = 0,  /**< Queue Empty due to last read             */
-    IX_QMGR_Q_SOURCE_ID_NE,     /**< Queue Nearly Empty due to last read      */
-    IX_QMGR_Q_SOURCE_ID_NF,     /**< Queue Nearly Full due to last write      */
-    IX_QMGR_Q_SOURCE_ID_F,      /**< Queue Full due to last write             */
-    IX_QMGR_Q_SOURCE_ID_NOT_E,  /**< Queue Not Empty due to last write        */
-    IX_QMGR_Q_SOURCE_ID_NOT_NE, /**< Queue Not Nearly Empty due to last write */
-    IX_QMGR_Q_SOURCE_ID_NOT_NF, /**< Queue Not Nearly Full due to last read   */
-    IX_QMGR_Q_SOURCE_ID_NOT_F   /**< Queue Not Full due to last read          */
-} IxQMgrSourceId;
-
-/**
- * @enum IxQMgrQEntrySizeInWords
- *
- * @ingroup IxQMgrAPI
- *
- * @brief QMgr queue entry sizes.
- *
- * The entry size of a queue specifies the size of a queues entry in words.
- *
- */
-typedef enum
-{
-    IX_QMGR_Q_ENTRY_SIZE1 = 1,   /**< 1 word entry       */
-    IX_QMGR_Q_ENTRY_SIZE2 = 2,   /**< 2 word entry       */
-    IX_QMGR_Q_ENTRY_SIZE4 = 4    /**< 4 word entry       */
-} IxQMgrQEntrySizeInWords;
-
-/**
- * @enum IxQMgrQSizeInWords
- *
- * @ingroup IxQMgrAPI
- *
- * @brief QMgr queue sizes.
- *
- * These values define the allowed queue sizes for AQM queue. The sizes are
- * specified in words.
- *
- */
-typedef enum
-{
-    IX_QMGR_Q_SIZE16 = 16,   /**< 16 word buffer     */
-    IX_QMGR_Q_SIZE32 = 32,   /**< 32 word buffer     */
-    IX_QMGR_Q_SIZE64 = 64,   /**< 64 word buffer     */
-    IX_QMGR_Q_SIZE128 = 128, /**< 128 word buffer    */
-    IX_QMGR_Q_SIZE_INVALID = 129  /**< Insure that this is greater than largest
-				    * queue size supported by the hardware
-				    */
-} IxQMgrQSizeInWords;
-
-/**
- * @enum IxQMgrWMLevel
- *
- * @ingroup IxQMgrAPI
- *
- * @brief QMgr watermark levels.
- *
- * These values define the valid watermark levels(in ENTRIES) for queues. Each
- * queue 0-63 have configurable Nearly full and Nearly empty watermarks. For
- * queues 32-63 the Nearly full watermark has NO EFFECT.
- * If the Nearly full watermark is set to IX_QMGR_Q_WM_LEVEL16 this means that
- * the nearly full flag will be set by the hardware when there are >= 16 empty
- * entries in the specified queue.
- * If the Nearly empty watermark is set to IX_QMGR_Q_WM_LEVEL16 this means that
- * the Nearly empty flag will be set by the hardware when there are <= 16 full
- * entries in the specified queue.
- */
-typedef enum
-{
-    IX_QMGR_Q_WM_LEVEL0 = 0,    /**< 0 entry watermark  */
-    IX_QMGR_Q_WM_LEVEL1 = 1,    /**< 1 entry watermark  */
-    IX_QMGR_Q_WM_LEVEL2 = 2,    /**< 2 entry watermark  */
-    IX_QMGR_Q_WM_LEVEL4 = 4,    /**< 4 entry watermark  */
-    IX_QMGR_Q_WM_LEVEL8 = 8,    /**< 8 entry watermark  */
-    IX_QMGR_Q_WM_LEVEL16 = 16,  /**< 16 entry watermark */
-    IX_QMGR_Q_WM_LEVEL32 = 32,  /**< 32 entry watermark */
-    IX_QMGR_Q_WM_LEVEL64 = 64   /**< 64 entry watermark */
-} IxQMgrWMLevel;
-
-/**
- * @ingroup IxQMgrAPI
- * 
- * @enum IxQMgrDispatchGroup
- *
- * @brief QMgr dispatch group select identifiers.
- *
- * This enum defines the groups over which the  dispatcher will process when
- * called. One of the enum values must be used as a input to
- * @a ixQMgrDispatcherLoopRunA0, @a ixQMgrDispatcherLoopRunB0 
- * or @a ixQMgrDispatcherLoopRunB0LLP.
- *
- */
-typedef enum
-{
-    IX_QMGR_QUELOW_GROUP = 0, /**< Queues 0-31  */
-    IX_QMGR_QUEUPP_GROUP      /**< Queues 32-63 */
-} IxQMgrDispatchGroup;
-
-/**
- * @ingroup IxQMgrAPI
- * 
- * @enum IxQMgrPriority
- *
- * @brief Dispatcher priority levels.
- *
- * This enum defines the different queue dispatch priority levels.
- * The lowest priority number (0) is the highest priority level.
- *
- */
-typedef enum
-{
-  IX_QMGR_Q_PRIORITY_0 = 0,  /**< Priority level 0 */
-  IX_QMGR_Q_PRIORITY_1,      /**< Priority level 1 */
-  IX_QMGR_Q_PRIORITY_2,      /**< Priority level 2 */
-  IX_QMGR_Q_PRIORITY_INVALID /**< Invalid Priority level */
-} IxQMgrPriority;
-
-/**
- * @ingroup IxQMgrAPI
- *
- * @enum IxQMgrType
- *
- * @brief Callback types as used with livelock prevention
- *
- * This enum defines the different callback types. 
- * These types are only used when Livelock prevention is enabled.
- * The default is IX_QMGR_TYPE_REALTIME_OTHER. 
- *
- */
-
-typedef enum
-{
-  IX_QMGR_TYPE_REALTIME_OTHER = 0, /**< Real time callbacks-always allowed run*/
-  IX_QMGR_TYPE_REALTIME_PERIODIC,  /**< Periodic callbacks-always allowed run */
-  IX_QMGR_TYPE_REALTIME_SPORADIC   /**< Sporadic callbacks-only run if no
-                                        periodic callbacks are in progress    */
-} IxQMgrType;
-
-
-/**
- * @ingroup IxQMgrAPI
- * 
- * @typedef IxQMgrCallbackId
- *
- * @brief Uniquely identifies a callback function.
- *
- * A unique callback identifier associated with each callback
- * registered by clients.
- *
- */
-typedef unsigned IxQMgrCallbackId;
-
-/**
- * @typedef IxQMgrCallback
- *
- * @brief QMgr notification callback type.
- *
- * This defines the interface to all client callback functions.
- *
- * @param qId @ref IxQMgrQId [in] - the queue identifier
- * @param cbId @ref IxQMgrCallbackId [in] - the callback identifier
- */
-typedef void (*IxQMgrCallback)(IxQMgrQId qId,
-                               IxQMgrCallbackId cbId);
-
-/**
- * @ingroup IxQMgrAPI
- *
- * @typedef IxQMgrDispatcherFuncPtr
- *
- * @brief QMgr Dispatcher Loop function pointer.
- *
- * This defines the interface for QMgr Dispather functions.
- *
- * @param group @ref IxQMgrDispatchGroup [in] - the group of the 
- *                  queue of which the dispatcher will run   
- */
-typedef void (*IxQMgrDispatcherFuncPtr)(IxQMgrDispatchGroup group);
-
-/*
- * Function Prototypes
- */
-
-/* ------------------------------------------------------------
-   Initialisation related functions
-   ---------------------------------------------------------- */
-
-/**
- *
- * @ingroup IxQMgrAPI
- *
- * @fn ixQMgrInit (void)
- *
- * @brief Initialise the QMgr.
- *
- * This function must be called before and other QMgr function. It
- * sets up internal data structures.
- *
- * @return @li IX_SUCCESS, the IxQMgr successfully initialised
- * @return @li IX_FAIL, failed to initialize the Qmgr
- *
- */
-PUBLIC IX_STATUS
-ixQMgrInit (void);
-
-/**
- *
- * @ingroup IxQMgrAPI
- *
- * @fn ixQMgrUnload (void)
- *
- * @brief Uninitialise the QMgr.
- *
- * This function will perform the tasks required to unload the QMgr component
- * cleanly.  This includes unmapping kernel memory.
- * This should be called before a soft reboot or unloading of a kernel module.
- *
- * @pre It should only be called if @ref ixQMgrInit has already been called.
- *
- * @post No QMgr functions should be called until ixQMgrInit is called again.
- *
- * @return @li IX_SUCCESS, the IxQMgr successfully uninitialised
- * @return @li IX_FAIL, failed to uninitialize the Qmgr
- *
- */
-PUBLIC IX_STATUS
-ixQMgrUnload (void);
-
-/**
- *
- * @ingroup IxQMgrAPI
- *
- * @fn ixQMgrShow (void)
- *
- * @brief Describe queue configuration and statistics for active queues.
- *
- * This function shows active queues, their configurations and statistics.
- *
- * @return @li void
- *
- */
-PUBLIC void
-ixQMgrShow (void);
-
-/**
- *
- * @ingroup IxQMgrAPI
- *
- * @fn ixQMgrQShow (IxQMgrQId qId)
- *
- * @brief Display aqueue configuration and statistics for a queue.
- *
- * This function shows queue configuration and statistics for a queue.
- *
- * @param qId @ref IxQMgrQId [in] - the queue identifier.
- *
- * @return @li IX_SUCCESS, success
- * @return @li IX_QMGR_Q_NOT_CONFIGURED, queue not configured for this QId
- *
- */
-PUBLIC IX_STATUS
-ixQMgrQShow (IxQMgrQId qId);
-
-
-/* ------------------------------------------------------------
-   Configuration related functions
-   ---------------------------------------------------------- */
-
-/**
- *
- * @ingroup IxQMgrAPI
- * 
- * @fn ixQMgrQConfig (char *qName,
-	       IxQMgrQId qId,
-	       IxQMgrQSizeInWords qSizeInWords,
-	       IxQMgrQEntrySizeInWords qEntrySizeInWords)
- *
- * @brief Configure an AQM queue.
- *
- * This function is called by a client to setup a queue. The size and entrySize
- * qId and qName(NULL pointer) are checked for valid values. This function must
- * be called for each queue, before any queue accesses are made and after
- * ixQMgrInit() has been called. qName is assumed to be a '\0' terminated array
- * of 16 charachters or less.
- *
- * @param *qName char [in] - is the name provided by the client and is associated
- *                          with a QId by the QMgr.
- * @param qId @ref IxQMgrQId [in]  - the qId of this queue
- * @param qSizeInWords @ref IxQMgrQSize [in] - the size of the queue can be one of 16,32
- *                                       64, 128 words.
- * @param qEntrySizeInWords @ref IxQMgrQEntrySizeInWords [in] - the size of a queue entry
- *                                                        can be one of 1,2,4 words.
- *
- * @return @li IX_SUCCESS, a specified queue has been successfully configured.
- * @return @li IX_FAIL, IxQMgr has not been initialised.
- * @return @li IX_QMGR_PARAMETER_ERROR, invalid parameter(s).
- * @return @li IX_QMGR_INVALID_QSIZE, invalid queue size
- * @return @li IX_QMGR_INVALID_Q_ID, invalid queue id
- * @return @li IX_QMGR_INVALID_Q_ENTRY_SIZE, invalid queue entry size
- * @return @li IX_QMGR_Q_ALREADY_CONFIGURED, queue already configured
- *
- */
-PUBLIC IX_STATUS
-ixQMgrQConfig (char *qName,
-	       IxQMgrQId qId,
-	       IxQMgrQSizeInWords qSizeInWords,
-	       IxQMgrQEntrySizeInWords qEntrySizeInWords);
-
-/**
- * @ingroup IxQMgrAPI
- * 
- * @fn ixQMgrQSizeInEntriesGet (IxQMgrQId qId,
-			 unsigned *qSizeInEntries)
- *
- * @brief Return the size of a queue in entries.
- *
- * This function returns the the size of the queue in entriese.
- *
- * @param qId @ref IxQMgrQId [in] - the queue identifier
- * @param *qSizeInEntries @ref IxQMgrQSize [out] - queue size in entries
- *
- * @return @li IX_SUCCESS, successfully retrieved the number of full entrie
- * @return @li IX_QMGR_Q_NOT_CONFIGURED, queue not configured for this QId
- * @return @li IX_QMGR_PARAMETER_ERROR, invalid parameter(s).
- *
- */
-PUBLIC IX_STATUS
-ixQMgrQSizeInEntriesGet (IxQMgrQId qId,
-			 unsigned *qSizeInEntries);
-
-/**
- *
- * @ingroup IxQMgrAPI
- * 
- * @fn ixQMgrWatermarkSet (IxQMgrQId qId,
-		    IxQMgrWMLevel ne,
-		    IxQMgrWMLevel nf)
- *
- * @brief Set the Nearly Empty and Nearly Full Watermarks fo a queue.
- *
- * This function is called by a client to set the watermarks NE and NF for the
- * queue specified by qId.
- * The queue must be empty at the time this function is called, it is the clients
- * responsibility to ensure that the queue is empty.
- * This function will read the status of the queue before the watermarks are set
- * and again after the watermarks are set. If the status register has changed,
- * due to a queue access by an NPE for example, a warning is returned.
- * Queues 32-63 only support the NE flag, therefore the value of nf will be ignored
- * for these queues.
- *
- * @param qId @ref IxQMgrQId [in] -  the QId of the queue.
- * @param ne @ref IxQMgrWMLevel [in]  - the NE(Nearly Empty) watermark for this
- *                                 queue. Valid values are 0,1,2,4,8,16,32 and
- *                                 64 entries.
- * @param nf @ref IxQMgrWMLevel [in] - the NF(Nearly Full) watermark for this queue.
- *                                 Valid values are 0,1,2,4,8,16,32 and 64
- *                                 entries.
- *
- * @return @li IX_SUCCESS, watermarks have been set for the queu
- * @return @li IX_QMGR_Q_NOT_CONFIGURED, queue not configured for this QId
- * @return @li IX_QMGR_INVALID_Q_WM, invalid watermark
- * @return @li IX_QMGR_WARNING, the status register may not be constistent
- *
- */
-PUBLIC IX_STATUS
-ixQMgrWatermarkSet (IxQMgrQId qId,
-		    IxQMgrWMLevel ne,
-		    IxQMgrWMLevel nf);
-
-/**
- * @ingroup IxQMgrAPI
- * 
- * @fn ixQMgrAvailableSramAddressGet (UINT32 *address,
-			       unsigned *sizeOfFreeSram)
- *
- * @brief Return the address of available AQM SRAM.
- *
- * This function returns the starting address in AQM SRAM not used by the
- * current queue configuration and should only be called after all queues
- * have been configured.
- * Calling this function before all queues have been configured will will return
- * the currently available SRAM. A call to configure another queue will use some
- * of the available SRAM.
- * The amount of SRAM available is specified in sizeOfFreeSram. The address is the
- * address of the bottom of available SRAM. Available SRAM extends from address
- * from address to address + sizeOfFreeSram.
- *
- * @param **address UINT32 [out] - the address of the available SRAM, NULL if
- *                                none available.
- * @param *sizeOfFreeSram unsigned [out]- the size in words of available SRAM
- *
- * @return @li IX_SUCCESS, there is available SRAM and is pointed to by address
- * @return @li IX_QMGR_PARAMETER_ERROR, invalid parameter(s)
- * @return @li IX_QMGR_NO_AVAILABLE_SRAM, all AQM SRAM is consumed by the queue
- *             configuration.
- *
- */
-PUBLIC IX_STATUS
-ixQMgrAvailableSramAddressGet (UINT32 *address,
-			       unsigned *sizeOfFreeSram);
-
-
-/* ------------------------------------------------------------
-   Queue access related functions
-   ---------------------------------------------------------- */
-
-/**
- *
- * @ingroup IxQMgrAPI
- * 
- * @fn ixQMgrQReadWithChecks (IxQMgrQId qId,
-                       UINT32 *entry)
- *
- * @brief Read an entry from a queue.
- *
- * This function reads an entire entry from a queue returning it in entry. The
- * queue configuration word is read to determine what entry size this queue is
- * configured for and then the number of words specified by the entry size is
- * read.  entry must be a pointer to a previously allocated array of sufficient
- * size to hold an entry.
- *
- * @note - IX_QMGR_Q_UNDERFLOW is only returned for queues 0-31 as queues 32-63
- * do not have an underflow status maintained.
- *
- * @param  qId @ref IxQMgrQId [in]   - the queue identifier.
- * @param  *entry UINT32 [out]  - pointer to the entry word(s).
- *
- * @return @li IX_SUCCESS, entry was successfully read.
- * @return @li IX_QMGR_PARAMETER_ERROR, invalid paramter(s).
- * @return @li IX_QMGR_Q_NOT_CONFIGURED, queue not configured for this QId
- * @return @li IX_QMGR_Q_UNDERFLOW, attempt to read from an empty queue
- *
- */
-PUBLIC IX_STATUS
-ixQMgrQReadWithChecks (IxQMgrQId qId,
-                       UINT32 *entry);
-
-
-
-/** 
- * @brief Internal structure to facilitate inlining functions in IxQMgr.h
- */
-typedef struct
-{
-    /* fields related to write functions */
-    UINT32 qOflowStatBitMask;         /**< overflow status mask */
-    UINT32 qWriteCount;               /**< queue write count */
-
-    /* fields related to read and write functions */
-    volatile UINT32 *qAccRegAddr;     /**< access register */
-    volatile UINT32 *qUOStatRegAddr;  /**< status register */
-    volatile UINT32 *qConfigRegAddr;  /**< config register */
-    UINT32 qEntrySizeInWords;         /**< queue entry size in words */
-    UINT32 qSizeInEntries;            /**< queue size in entries */
-
-    /* fields related to read functions */
-    UINT32 qUflowStatBitMask;         /**< underflow status mask */
-    UINT32 qReadCount;                /**< queue read count */
-} IxQMgrQInlinedReadWriteInfo;
-
-
-/**
- *
- * @ingroup IxQMgrAPI
- *
- * @fn ixQMgrQReadMWordsMinus1 (IxQMgrQId qId,
-			        UINT32 *entry)
- *
- * @brief This function reads the remaining of the q entry
- *        for queues configured with many words.
- *        (the first word of the entry is already read 
- *        in the inlined function and the entry pointer already
- *        incremented
- *
- * @param  qId @ref IxQMgrQId [in]  - the queue identifier.
- * @param  *entry UINT32 [out] - pointer to the entry word(s).
- *
- * @return @li IX_SUCCESS, entry was successfully read.
- * @return @li IX_QMGR_Q_UNDERFLOW, attempt to read from an empty queue
- *
- */
-PUBLIC IX_STATUS
-ixQMgrQReadMWordsMinus1 (IxQMgrQId qId,
-			 UINT32 *entry);
-
-
-
-/**
- *
- * @ingroup IxQMgrAPI
- * 
- * @fn ixQMgrQRead (IxQMgrQId qId,
-	     UINT32 *entry)
- *
- * @brief Fast read of an entry from a queue.
- *
- * This function is a heavily streamlined version of ixQMgrQReadWithChecks(),
- * but performs essentially the same task.  It reads an entire entry from a
- * queue, returning it in entry which must be a pointer to a previously
- * allocated array of sufficient size to hold an entry.
- *
- * @note - This function is inlined, to reduce unnecessary function call
- * overhead.  It does not perform any parameter checks, or update any statistics.
- * Also, it does not check that the queue specified by qId has been configured.
- * or is in range. It simply reads an entry from the queue, and checks for
- * underflow.
- *
- * @note - IX_QMGR_Q_UNDERFLOW is only returned for queues 0-31 as queues 32-63
- * do not have an underflow status maintained.
- *
- * @param  qId @ref IxQMgrQId [in] - the queue identifier.
- * @param  *entry UINT32 [out] - pointer to the entry word(s).
- *
- * @return @li IX_SUCCESS, entry was successfully read.
- * @return @li IX_QMGR_Q_UNDERFLOW, attempt to read from an empty queue
- *
- */
-#ifdef NO_INLINE_APIS
-PUBLIC IX_STATUS
-ixQMgrQRead (IxQMgrQId qId,
-             UINT32 *entryPtr);
-#else 
-extern IxQMgrQInlinedReadWriteInfo ixQMgrQInlinedReadWriteInfo[];
-extern IX_STATUS ixQMgrQReadMWordsMinus1 (IxQMgrQId qId, UINT32 *entryPtr);
-
-IX_QMGR_INLINE PUBLIC IX_STATUS
-ixQMgrQRead (IxQMgrQId qId,
-             UINT32 *entryPtr);
-#endif
-
-IX_QMGR_INLINE PUBLIC IX_STATUS
-ixQMgrQRead (IxQMgrQId qId,
-	     UINT32 *entryPtr)
-#ifdef NO_INLINE_APIS
-    ;
-#else
-{
-    IxQMgrQInlinedReadWriteInfo *infoPtr = &ixQMgrQInlinedReadWriteInfo[qId];
-    UINT32 entry, entrySize;
-
-    /* get a new entry */
-    entrySize = infoPtr->qEntrySizeInWords;
-    entry = IX_QMGR_INLINE_READ_LONG(infoPtr->qAccRegAddr);
-
-    if (entrySize != IX_QMGR_Q_ENTRY_SIZE1)
-    {	
-	*entryPtr = entry;
-	/* process the remaining part of the entry */
-	return ixQMgrQReadMWordsMinus1(qId, entryPtr);
-    }
-
-    /* underflow is available for lower queues only */
-    if (qId < IX_QMGR_MIN_QUEUPP_QID)
-    {
-	/* the counter of queue entries is decremented. In happy 
-	 * day scenario there are many entries in the queue
-	 * and the counter does not reach zero.
-	 */
-	if (infoPtr->qReadCount-- == 0)
-	{
-	    /* There is maybe no entry in the queue
-	     * qReadCount is now negative, but will be corrected before
-	     * the function returns.
-	     */
-	    UINT32 qPtrs; /* queue internal pointers */
-
-	    /* when a queue is empty, the hw guarantees to return 
-	     * a null value. If the value is not null, the queue is
-	     * not empty.
-	     */
-	    if (entry == 0)
-	    {
-		/* get the queue status */
-		UINT32 status = IX_QMGR_INLINE_READ_LONG(infoPtr->qUOStatRegAddr);
-	
-		/* check the underflow status */
-		if (status & infoPtr->qUflowStatBitMask)
-		{
-		    /* the queue is empty 
-		    *  clear the underflow status bit if it was set 
-		    */
-		    IX_QMGR_INLINE_WRITE_LONG(infoPtr->qUOStatRegAddr,
-					 status & ~infoPtr->qUflowStatBitMask);
-		    *entryPtr = 0;
-		    infoPtr->qReadCount = 0;
-		    return IX_QMGR_Q_UNDERFLOW;
-		}
-	    }
-	    /* store the result */
-	    *entryPtr = entry;
-
-	    /* No underflow occured : someone is filling the queue
-	     * or the queue contains null entries.
-	     * The current counter needs to be
-	     * updated from the current number of entries in the queue
-	     */
-
-	    /* get snapshot of queue pointers */
-	    qPtrs = IX_QMGR_INLINE_READ_LONG(infoPtr->qConfigRegAddr);
-
-	    /* Mod subtraction of pointers to get number of words in Q. */
-	    qPtrs = (qPtrs - (qPtrs >> 7)) & 0x7f; 
-  
-	    if (qPtrs == 0)
-	    {
-		/* no entry in the queue */
-		infoPtr->qReadCount = 0;
-	    }
-	    else
-	    {
-		/* convert the number of words inside the queue
-		 * to a number of entries 
-		 */
-		infoPtr->qReadCount = qPtrs & (infoPtr->qSizeInEntries - 1);
-	    }
-	    return IX_SUCCESS;
-	}
-    }
-    *entryPtr = entry;
-    return IX_SUCCESS;
-}
-#endif
-
-/**
- *
- * @ingroup IxQMgrAPI
- * 
- * @fn ixQMgrQBurstRead (IxQMgrQId qId,
-		  UINT32 numEntries,
-		  UINT32 *entries)
- *
- * @brief Read a number of entries from an AQM queue.
- *
- * This function will burst read a number of entries from the specified queue.
- * The entry size of queue is auto-detected. The function will attempt to
- * read as many entries as specified by the numEntries parameter and will
- * return an UNDERFLOW if any one of the individual entry reads fail.
- *
- * @warning
- * IX_QMGR_Q_UNDERFLOW is only returned for queues 0-31 as queues 32-63
- * do not have an underflow status maintained, hence there is a potential for
- * silent failure here. This function must be used with caution.
- *
- * @note
- * This function is intended for fast draining of queues, so to make it
- * as efficient as possible, it has the following features:
- * - This function is inlined, to reduce unnecessary function call overhead.
- * - It does not perform any parameter checks, or update any statistics.
- * - It does not check that the queue specified by qId has been configured.
- * - It does not check that the queue has the number of full entries that
- * have been specified to be read. It will read until it finds a NULL entry or
- * until the number of specified entries have been read.  It always checks for
- * underflow after all the reads have been performed.
- * Therefore, the client should ensure before calling this function that there
- * are enough entries in the queue to read.  ixQMgrQNumEntriesGet() will
- * provide the number of full entries in a queue.
- * ixQMgrQRead() or ixQMgrQReadWithChecks(), which only reads
- * a single queue entry per call, should be used instead if the user requires
- * checks for UNDERFLOW after each entry read.
- *
- * @param qId @ref IxQMgrQId [in]   - the queue identifier.
- * @param numEntries unsigned [in] - the number of entries to read. 
- *                     This number should be greater than 0
- * @param *entries UINT32 [out] - the word(s) read.
- *
- * @return @li IX_SUCCESS, entries were successfully read.
- * @return @li IX_QMGR_Q_UNDERFLOW, attempt to read from an empty queue 
- *
- */
-#ifdef NO_INLINE_APIS  
-PUBLIC IX_STATUS
-ixQMgrQBurstRead (IxQMgrQId qId,
-                  UINT32 numEntries,
-                  UINT32 *entries);
-#else
-IX_QMGR_INLINE PUBLIC IX_STATUS
-ixQMgrQBurstRead (IxQMgrQId qId,
-                  UINT32 numEntries,
-                  UINT32 *entries);
-#endif  /* endif NO_INLINE_APIS */
-
-IX_QMGR_INLINE PUBLIC IX_STATUS
-ixQMgrQBurstRead (IxQMgrQId qId,
-		  UINT32 numEntries,
-		  UINT32 *entries)
-#ifdef NO_INLINE_APIS
-;
-#else
-{
-    IxQMgrQInlinedReadWriteInfo *infoPtr = &ixQMgrQInlinedReadWriteInfo[qId];
-    UINT32 nullCheckEntry;
-
-    if (infoPtr->qEntrySizeInWords == IX_QMGR_Q_ENTRY_SIZE1)
-    {
-	volatile UINT32 *qAccRegAddr = infoPtr->qAccRegAddr;
-
-	/* the code is optimized to take care of data dependencies:
-	 * Durig a read, there are a few cycles needed to get the 
-	 * read complete. During these cycles, it is poossible to
-	 * do some CPU, e.g. increment pointers and decrement 
-	 * counters.
-	 */
-
-	/* fetch a queue entry */
-	nullCheckEntry = IX_QMGR_INLINE_READ_LONG(infoPtr->qAccRegAddr);
-
-	/* iterate the specified number of queue entries */ 
-	while (--numEntries)
-	{
-	    /* check the result of the previous read */
-	    if (nullCheckEntry == 0)
-	    {
-		/* if we read a NULL entry, stop. We have underflowed */
-		break;
-	    }
-	    else
-	    {
-		/* write the entry */
-		*entries = nullCheckEntry;
-		/* fetch next entry */
-		nullCheckEntry = IX_QMGR_INLINE_READ_LONG(qAccRegAddr);
-		/* increment the write address */
-		entries++;
-	    }
-	}
-	/* write the pre-fetched entry */
-	*entries = nullCheckEntry;
-    }
-    else
-    {
-	IxQMgrQEntrySizeInWords entrySizeInWords = infoPtr->qEntrySizeInWords;
-	/* read the specified number of queue entries */
-	nullCheckEntry = 0;
-	while (numEntries--)
-	{
-	    UINT32 i;
-
-	    for (i = 0; i < (UINT32)entrySizeInWords; i++)
-	    {
-		*entries = IX_QMGR_INLINE_READ_LONG(infoPtr->qAccRegAddr + i);
-		nullCheckEntry |= *entries++;
-	    }
-
-	    /* if we read a NULL entry, stop. We have underflowed */
-	    if (nullCheckEntry == 0)
-	    {
-		break;
-	    }
-	    nullCheckEntry = 0;
-	}
-    }
-
-    /* reset the current read count : next access to the read function 
-     * will force a underflow status check 
-     */
-    infoPtr->qReadCount = 0;
-
-    /* Check if underflow occurred on the read */
-    if (nullCheckEntry == 0 && qId < IX_QMGR_MIN_QUEUPP_QID)
-    {
-	/* get the queue status */
-	UINT32 status = IX_QMGR_INLINE_READ_LONG(infoPtr->qUOStatRegAddr);
-
-	if (status & infoPtr->qUflowStatBitMask)
-	{
-	    /* clear the underflow status bit if it was set */
-	    IX_QMGR_INLINE_WRITE_LONG(infoPtr->qUOStatRegAddr,
-				 status & ~infoPtr->qUflowStatBitMask);
-	    return IX_QMGR_Q_UNDERFLOW;
-	}
-    }
-
-    return IX_SUCCESS;
-}
-#endif
-
-/**
- * @ingroup IxQMgrAPI
- * 
- * @fn ixQMgrQPeek (IxQMgrQId qId,
-	     unsigned int entryIndex,
-	     UINT32 *entry)
- *
- * @brief Read an entry from a queue without moving the read pointer.
- *
- * This function inspects an entry in a queue. The entry is inspected directly
- * in AQM SRAM and is not read from queue access registers. The entry is NOT removed
- * from the queue and the read/write pointers are unchanged.
- * N.B: The queue should not be accessed when this function is called.
- *
- * @param  qId @ref IxQMgrQId [in]   - the queue identifier.
- * @param  entryIndex unsigned int [in] - index of entry in queue in the range
- *                          [0].......[current number of entries in queue].
- * @param  *entry UINT32 [out] - pointer to the entry word(s).
- *
- * @return @li IX_SUCCESS, entry was successfully inspected.
- * @return @li IX_QMGR_PARAMETER_ERROR, invalid paramter(s).
- * @return @li IX_QMGR_Q_NOT_CONFIGURED, queue not configured for this QId.
- * @return @li IX_QMGR_ENTRY_INDEX_OUT_OF_BOUNDS, an entry does not exist at
- *             specified index.
- * @return @li IX_FAIL, failed to inpected the queue entry.
- */
-PUBLIC IX_STATUS
-ixQMgrQPeek (IxQMgrQId qId,
-	     unsigned int entryIndex,
-	     UINT32 *entry);
-
-/**
- *
- * @ingroup IxQMgrAPI
- * 
- * @fn ixQMgrQWriteWithChecks (IxQMgrQId qId,
-                        UINT32 *entry)
- *
- * @brief Write an entry to an AQM queue.
- *
- * This function will write the entry size number of words pointed to by entry to
- * the queue specified by qId. The queue configuration word is read to
- * determine the entry size of queue and the corresponding number of words is
- * then written to the queue.
- *
- * @note - IX_QMGR_Q_OVERFLOW is only returned for queues 0-31 as queues 32-63
- * do not have an overflow status maintained.
- *
- * @param qId @ref IxQMgrQId [in] - the queue identifier.
- * @param *entry UINT32 [in] - the word(s) to write.
- *
- * @return @li IX_SUCCESS, value was successfully written.
- * @return @li IX_QMGR_PARAMETER_ERROR, invalid paramter(s).
- * @return @li IX_QMGR_Q_NOT_CONFIGURED, queue not configured for this QId
- * @return @li IX_QMGR_Q_OVERFLOW, attempt to write to a full queue
- *
- */
-PUBLIC IX_STATUS
-ixQMgrQWriteWithChecks (IxQMgrQId qId,
-                        UINT32 *entry);
-
-/**
- *
- * @ingroup IxQMgrAPI
- * 
- * @fn ixQMgrQWrite (IxQMgrQId qId,
-	      UINT32 *entry)
- *
- * @brief Fast write of an entry to a queue.
- *
- * This function is a heavily streamlined version of ixQMgrQWriteWithChecks(),
- * but performs essentially the same task.  It will write the entry size number
- * of words pointed to by entry to the queue specified by qId.
- *
- * @note - This function is inlined, to reduce unnecessary function call
- * overhead.  It does not perform any parameter checks, or update any
- * statistics. Also, it does not check that the queue specified by qId has
- * been configured. It simply writes an entry to the queue, and checks for
- * overflow.
- *
- * @note - IX_QMGR_Q_OVERFLOW is only returned for queues 0-31 as queues 32-63
- * do not have an overflow status maintained.
- *
- * @param  qId @ref IxQMgrQId [in]   - the queue identifier.
- * @param  *entry UINT32 [in] - pointer to the entry word(s).
- *
- * @return @li IX_SUCCESS, entry was successfully read.
- * @return @li IX_QMGR_Q_OVERFLOW, attempt to write to a full queue
- *
- */
-#ifdef NO_INLINE_APIS
-PUBLIC IX_STATUS
-ixQMgrQWrite (IxQMgrQId qId,
-	      UINT32 *entry);
-#else
-IX_QMGR_INLINE PUBLIC IX_STATUS
-ixQMgrQWrite (IxQMgrQId qId,
-	      UINT32 *entry);
-#endif /* NO_INLINE_APIS */
-
-IX_QMGR_INLINE PUBLIC IX_STATUS
-ixQMgrQWrite (IxQMgrQId qId,
-	      UINT32 *entry)
-#ifdef NO_INLINE_APIS
-    ;
-#else
-{
-    IxQMgrQInlinedReadWriteInfo *infoPtr = &ixQMgrQInlinedReadWriteInfo[qId];
-    UINT32 entrySize;
-
-    /* write the entry */
-    IX_QMGR_INLINE_WRITE_LONG(infoPtr->qAccRegAddr, *entry);
-    entrySize = infoPtr->qEntrySizeInWords;
-
-    if (entrySize != IX_QMGR_Q_ENTRY_SIZE1)
-    {	
-	/* process the remaining part of the entry */
-	volatile UINT32 *qAccRegAddr = infoPtr->qAccRegAddr;
-	while (--entrySize)
-	{
-	    ++entry;
-	    IX_QMGR_INLINE_WRITE_LONG(++qAccRegAddr, *entry);
-	}
-	entrySize = infoPtr->qEntrySizeInWords;
-    }
-
-    /* overflow is available for lower queues only */
-    if (qId < IX_QMGR_MIN_QUEUPP_QID)
-    {   
-	UINT32 qSize = infoPtr->qSizeInEntries;
-	/* increment the current number of entries in the queue
-	 * and check for overflow 
-	 */
-	if (infoPtr->qWriteCount++ == qSize)
-	{
-	    /* the queue may have overflow */
-	    UINT32 qPtrs; /* queue internal pointers */
-  
-	    /* get the queue status */
-	    UINT32 status = IX_QMGR_INLINE_READ_LONG(infoPtr->qUOStatRegAddr);
-
-	    /* read the status twice because the status may 
-	     * not be immediately ready after the write operation
-	     */
-	    if ((status & infoPtr->qOflowStatBitMask) ||
-		((status = IX_QMGR_INLINE_READ_LONG(infoPtr->qUOStatRegAddr))
-		 & infoPtr->qOflowStatBitMask))
-	    {
-		/* the queue is full, clear the overflow status
-		 *  bit if it was set 
-		 */
-		IX_QMGR_INLINE_WRITE_LONG(infoPtr->qUOStatRegAddr,
-				     status & ~infoPtr->qOflowStatBitMask);
-		infoPtr->qWriteCount = infoPtr->qSizeInEntries;
-		return IX_QMGR_Q_OVERFLOW;
-	    }
-	    /* No overflow occured : someone is draining the queue
-	     * and the current counter needs to be
-	     * updated from the current number of entries in the queue
-	     */
-
-	    /* get q pointer snapshot */
-	    qPtrs = IX_QMGR_INLINE_READ_LONG(infoPtr->qConfigRegAddr);
-
-	    /* Mod subtraction of pointers to get number of words in Q. */
-	    qPtrs = (qPtrs - (qPtrs >> 7)) & 0x7f; 
-
-	    if (qPtrs == 0)
-	    {
-		/* the queue may be full at the time of the 
-		 * snapshot. Next access will check 
-		 * the overflow status again.
-		 */
-		infoPtr->qWriteCount = qSize;
-	    }
-	    else 
-	    {
-		/* convert the number of words to a number of entries */
-		if (entrySize == IX_QMGR_Q_ENTRY_SIZE1)
-		{
-		    infoPtr->qWriteCount = qPtrs & (qSize - 1);
-		}
-		else
-		{
-		    infoPtr->qWriteCount = (qPtrs / entrySize) & (qSize - 1);
-		}
-	    }
-	}
-    }
-    return IX_SUCCESS;
-}
-#endif
-
-/**
- *
- * @ingroup IxQMgrAPI
- * 
- * @fn ixQMgrQBurstWrite (IxQMgrQId qId,
-		   unsigned numEntries,
-		   UINT32 *entries)
- *
- * @brief Write a number of entries to an AQM queue.
- *
- * This function will burst write a number of entries to the specified queue.
- * The entry size of queue is auto-detected. The function will attempt to
- * write as many entries as specified by the numEntries parameter and will
- * return an OVERFLOW if any one of the individual entry writes fail.
- *
- * @warning
- * IX_QMGR_Q_OVERFLOW is only returned for queues 0-31 as queues 32-63
- * do not have an overflow status maintained, hence there is a potential for
- * silent failure here. This function must be used with caution.
- *
- * @note
- * This function is intended for fast population of queues, so to make it
- * as efficient as possible, it has the following features:
- * - This function is inlined, to reduce unnecessary function call overhead.
- * - It does not perform any parameter checks, or update any statistics.
- * - It does not check that the queue specified by qId has been configured.
- * - It does not check that the queue has enough free space to hold the entries
- * before writing, and only checks for overflow after all writes have been
- * performed.  Therefore, the client should ensure before calling this function
- * that there is enough free space in the queue to hold the number of entries
- * to be written.  ixQMgrQWrite() or ixQMgrQWriteWithChecks(), which only writes
- * a single queue entry per call, should be used instead if the user requires
- * checks for OVERFLOW after each entry written.
- *
- * @param qId @ref IxQMgrQId [in]   - the queue identifier.
- * @param numEntries unsigned [in] - the number of entries to write.
- * @param *entries UINT32 [in]  - the word(s) to write.
- *
- * @return @li IX_SUCCESS, value was successfully written.
- * @return @li IX_QMGR_Q_OVERFLOW, attempt to write to a full queue
- *
- */
-#ifdef NO_INLINE_APIS
-PUBLIC IX_STATUS
-ixQMgrQBurstWrite (IxQMgrQId qId,
-		   unsigned numEntries,
-		   UINT32 *entries);
-#else
-IX_QMGR_INLINE PUBLIC IX_STATUS
-ixQMgrQBurstWrite (IxQMgrQId qId,
-		   unsigned numEntries,
-		   UINT32 *entries);
-#endif /* NO_INLINE_APIS */
-
-IX_QMGR_INLINE PUBLIC IX_STATUS
-ixQMgrQBurstWrite (IxQMgrQId qId,
-		   unsigned numEntries,
-		   UINT32 *entries)
-#ifdef NO_INLINE_APIS
-;
-#else
-{
-    IxQMgrQInlinedReadWriteInfo *infoPtr = &ixQMgrQInlinedReadWriteInfo[qId];
-    UINT32 status;
-
-    /* update the current write count */
-    infoPtr->qWriteCount += numEntries;
-
-    if (infoPtr->qEntrySizeInWords == IX_QMGR_Q_ENTRY_SIZE1)
-    {
-	volatile UINT32 *qAccRegAddr = infoPtr->qAccRegAddr;
-	while (numEntries--)
-	{
-	    IX_QMGR_INLINE_WRITE_LONG(qAccRegAddr, *entries);
-	    entries++;
-	}
-    }
-    else
-    {
-	IxQMgrQEntrySizeInWords entrySizeInWords = infoPtr->qEntrySizeInWords;
-	UINT32 i;
-
-	/* write each queue entry */
-	while (numEntries--)
-	{
-	    /* write the queueEntrySize number of words for each entry */
-	    for (i = 0; i < (UINT32)entrySizeInWords; i++)
-	    {
-		IX_QMGR_INLINE_WRITE_LONG((infoPtr->qAccRegAddr + i), *entries);
-		entries++;
-	    }
-	}
-    }
-
-    /* check if the write count overflows */
-    if (infoPtr->qWriteCount > infoPtr->qSizeInEntries)
-    {
-	/* reset the current write count */
-	infoPtr->qWriteCount = infoPtr->qSizeInEntries;
-    }
-
-    /* Check if overflow occurred on the write operation */
-    if (qId < IX_QMGR_MIN_QUEUPP_QID)
-    {
-	/* get the queue status */
-	status = IX_QMGR_INLINE_READ_LONG(infoPtr->qUOStatRegAddr);
-
-	/* read the status twice because the status may 
-	 * not be ready at the time of the write
-	 */
-	if ((status & infoPtr->qOflowStatBitMask) ||
-	    ((status = IX_QMGR_INLINE_READ_LONG(infoPtr->qUOStatRegAddr))
-	     & infoPtr->qOflowStatBitMask))
-	{
-	    /* clear the underflow status bit if it was set */
-	    IX_QMGR_INLINE_WRITE_LONG(infoPtr->qUOStatRegAddr,
-				 status & ~infoPtr->qOflowStatBitMask);
-	    return IX_QMGR_Q_OVERFLOW;
-	}
-    }
-
-    return IX_SUCCESS;
-}
-#endif
-
-/**
- * @ingroup IxQMgrAPI
- * 
- * @fn ixQMgrQPoke (IxQMgrQId qId,
-	     unsigned int entryIndex,
-	     UINT32 *entry)
- *
- * @brief Write an entry to a queue without moving the write pointer.
- *
- * This function modifies an entry in a queue. The entry is modified directly
- * in AQM SRAM and not using the queue access registers. The entry is NOT added to the
- * queue and the read/write pointers are unchanged.
- * N.B: The queue should not be accessed when this function is called.
- *
- * @param qId @ref IxQMgrQId [in]  - the queue identifier.
- * @param  entryIndex unsigned int [in] - index of entry in queue in the range
- *                          [0].......[current number of entries in queue].
- * @param  *entry UINT32 [in] - pointer to the entry word(s).
- *
- * @return @li IX_SUCCESS, entry was successfully modified.
- * @return @li IX_QMGR_PARAMETER_ERROR, invalid paramter(s).
- * @return @li IX_QMGR_Q_NOT_CONFIGURED, queue not configured for this QId.
- * @return @li IX_QMGR_ENTRY_INDEX_OUT_OF_BOUNDS, an entry does not exist at
- *             specified index.
- * @return @li IX_FAIL, failed to modify the queue entry.
- */
-PUBLIC IX_STATUS
-ixQMgrQPoke (IxQMgrQId qId,
-	     unsigned int entryIndex,
-	     UINT32 *entry);
-
-/**
- *
- * @ingroup IxQMgrAPI
- * 
- * @fn ixQMgrQNumEntriesGet (IxQMgrQId qId,
-		      unsigned *numEntries)
- *
- * @brief Get a snapshot of the number of entries in a queue.
- *
- * This function gets the number of entries in a queue.
- *
- * @param qId @ref IxQMgrQId [in] qId - the queue idenfifier
- * @param *numEntries unsigned [out] - the number of entries in a queue
- *
- * @return @li IX_SUCCESS, got the number of entries for the queue
- * @return @li IX_QMGR_PARAMETER_ERROR, invalid paramter(s).
- * @return @li IX_QMGR_Q_NOT_CONFIGURED, the specified qId has not been configured
- * @return @li IX_QMGR_WARNING, could not determine num entries at this time
- *
- */
-PUBLIC IX_STATUS
-ixQMgrQNumEntriesGet (IxQMgrQId qId,
-		      unsigned *numEntries);
-
-/**
- *
- * @ingroup IxQMgrAPI
- *
- * @fn ixQMgrQStatusGetWithChecks (IxQMgrQId qId,
-                            IxQMgrQStatus *qStatus)
- *
- * @brief Get a queues status.
- *
- * This function reads the specified queues status. A queues status is defined
- * by its status flags. For queues 0-31 these flags are E,NE,NF,F. For
- * queues 32-63 these flags are NE and F.
- *
- * @param qId @ref IxQMgrQId [in] - the queue identifier.
- * @param &qStatus @ref IxQMgrQStatus [out] - the status of the specified queue.
- *
- * @return @li IX_SUCCESS, queue status was successfully read.
- * @return @li IX_QMGR_Q_NOT_CONFIGURED, the specified qId has not been configured
- * @return @li IX_QMGR_PARAMETER_ERROR, invalid paramter.
- *
- */
-PUBLIC IX_STATUS
-ixQMgrQStatusGetWithChecks (IxQMgrQId qId,
-                            IxQMgrQStatus *qStatus);
-
-/**
- *
- * @ingroup IxQMgrAPI
- * 
- * @fn ixQMgrQStatusGet (IxQMgrQId qId,
-		  IxQMgrQStatus *qStatus)
- *
- * @brief Fast get of a queue's status.
- *
- * This function is a streamlined version of ixQMgrQStatusGetWithChecks(), but
- * performs essentially the same task.  It reads the specified queue's status.
- * A queues status is defined by its status flags. For queues 0-31 these flags
- * are E,NE,NF,F. For queues 32-63 these flags are NE and F.
- *
- * @note - This function is inlined, to reduce unnecessary function call
- * overhead.  It does not perform any parameter checks, or update any
- * statistics.  Also, it does not check that the queue specified by qId has
- * been configured.  It simply reads the specified queue's status.
- *
- * @param qId @ref IxQMgrQId [in] - the queue identifier.
- * @param *qStatus @ref IxQMgrQStatus [out] - the status of the specified queue.
- *
- * @return @li void.
- *
- */
-
-#ifdef NO_INLINE_APIS
-PUBLIC IX_STATUS
-ixQMgrQStatusGet (IxQMgrQId qId,
-		  IxQMgrQStatus *qStatus);
-#else  
-extern UINT32 ixQMgrAqmIfQueLowStatRegAddr[];
-extern UINT32 ixQMgrAqmIfQueLowStatBitsOffset[];
-extern UINT32 ixQMgrAqmIfQueLowStatBitsMask;
-extern UINT32 ixQMgrAqmIfQueUppStat0RegAddr;
-extern UINT32 ixQMgrAqmIfQueUppStat1RegAddr;
-extern UINT32 ixQMgrAqmIfQueUppStat0BitMask[];
-extern UINT32 ixQMgrAqmIfQueUppStat1BitMask[];
-
-IX_QMGR_INLINE PUBLIC IX_STATUS
-ixQMgrQStatusGet (IxQMgrQId qId,
-		  IxQMgrQStatus *qStatus);
-#endif  /* endif NO_INLINE_APIS */
-
-IX_QMGR_INLINE PUBLIC IX_STATUS
-ixQMgrQStatusGet (IxQMgrQId qId,
-		  IxQMgrQStatus *qStatus)
-#ifdef NO_INLINE_APIS
-    ;
-#else
-{
-    /* read the status of a queue in the range 0-31 */
-    if (qId < IX_QMGR_MIN_QUEUPP_QID)
-    {
-	volatile UINT32 *lowStatRegAddr = (UINT32*)ixQMgrAqmIfQueLowStatRegAddr[qId];
-
-	UINT32 lowStatBitsOffset = ixQMgrAqmIfQueLowStatBitsOffset[qId];
-	UINT32 lowStatBitsMask   = ixQMgrAqmIfQueLowStatBitsMask;
-
-	/* read the status register for this queue */
-	*qStatus = IX_QMGR_INLINE_READ_LONG(lowStatRegAddr);
-
-	/* mask out the status bits relevant only to this queue */
-	*qStatus = (*qStatus >> lowStatBitsOffset) & lowStatBitsMask;
-
-    }
-    else /* read status of a queue in the range 32-63 */
-    {
-
-	volatile UINT32 *qNearEmptyStatRegAddr = (UINT32*)ixQMgrAqmIfQueUppStat0RegAddr;
-	volatile UINT32 *qFullStatRegAddr      = (UINT32*)ixQMgrAqmIfQueUppStat1RegAddr;
-	int maskIndex = qId - IX_QMGR_MIN_QUEUPP_QID;
-	UINT32 qNearEmptyStatBitMask = ixQMgrAqmIfQueUppStat0BitMask[maskIndex];
-	UINT32 qFullStatBitMask      = ixQMgrAqmIfQueUppStat1BitMask[maskIndex];
-
-	/* Reset the status bits */
-	*qStatus = 0;
-
-	/* Check if the queue is nearly empty */
-	if (IX_QMGR_INLINE_READ_LONG(qNearEmptyStatRegAddr) & qNearEmptyStatBitMask)
-	{
-	    *qStatus |= IX_QMGR_Q_STATUS_NE_BIT_MASK;
-	}
-
-	/* Check if the queue is full */
-	if (IX_QMGR_INLINE_READ_LONG(qFullStatRegAddr) & qFullStatBitMask)
-	{
-	    *qStatus |= IX_QMGR_Q_STATUS_F_BIT_MASK;
-	}
-    }
-    return IX_SUCCESS;
-}
-#endif
-
-/* ------------------------------------------------------------
-   Queue dispatch related functions
-   ---------------------------------------------------------- */
-
-/**
- *
- * @ingroup IxQMgrAPI
- * 
- * @fn ixQMgrDispatcherPrioritySet (IxQMgrQId qId,
-			     IxQMgrPriority priority)
- *
- * @brief Set the dispatch priority of a queue.
- *
- * This function is called to set the dispatch priority of queue. The effect of
- * this function is to add a priority change request to a queue. This queue is
- * serviced by @a ixQMgrDispatcherLoopRunA0, @a ixQMgrDispatcherLoopRunB0 or 
- * @a ixQMgrDispatcherLoopRunB0LLP.
- *
- * This function is re-entrant. and can be used from an interrupt context
- *
- * @param qId @ref IxQMgrQId [in] - the queue identifier
- * @param priority @ref IxQMgrPriority [in] - the new queue dispatch priority
- *
- * @return @li IX_SUCCESS, priority change request is queued
- * @return @li IX_QMGR_Q_NOT_CONFIGURED, the specified qId has not been configured
- * @return @li IX_QMGR_Q_INVALID_PRIORITY, specified priority is invalid
- *
- */
-PUBLIC IX_STATUS
-ixQMgrDispatcherPrioritySet (IxQMgrQId qId,
-			     IxQMgrPriority priority);
-/**
- *
- * @ingroup IxQMgrAPI
- * 
- * @fn ixQMgrNotificationEnable (IxQMgrQId qId,
-			  IxQMgrSourceId sourceId)
- *
- * @brief Enable notification on a queue for a specified queue source flag.
- *
- * This function is called by a client of the QMgr to enable notifications on a
- * specified condition.
- * If the condition for the notification is set after the client has called this
- * function but before the function has enabled the interrupt source, then the
- * notification will not occur.
- * For queues 32-63 the notification source is fixed to the NE(Nearly Empty) flag
- * and cannot be changed so the sourceId parameter is ignored for these queues.
- * The status register is read before the notofication is enabled and is read again
- * after the notification has been enabled, if they differ then the warning status
- * is returned.
- *
- * This function is re-entrant. and can be used from an interrupt context
- *
- * @param qId @ref IxQMgrQId [in] - the queue identifier
- * @param sourceId @ref IxQMgrSourceId [in] - the interrupt src condition identifier
- *
- * @return @li IX_SUCCESS, the interrupt has been enabled for the specified source
- * @return @li IX_QMGR_Q_NOT_CONFIGURED, the specified qId has not been configured
- * @return @li IX_QMGR_INVALID_INT_SOURCE_ID, interrupt source invalid for this queue
- * @return @li IX_QMGR_WARNING, the status register may not be constistent
- *
- */
-PUBLIC IX_STATUS
-ixQMgrNotificationEnable (IxQMgrQId qId,
-			  IxQMgrSourceId sourceId);
-
-/**
- * @ingroup IxQMgrAPI
- * 
- * @fn ixQMgrNotificationDisable (IxQMgrQId qId)
- *
- * @brief Disable notifications on a queue.
- *
- * This function is called to disable notifications on a specified queue.
- *
- * This function is re-entrant. and can be used from an interrupt context
- *
- * @param qId @ref IxQMgrQId [in] - the queue identifier
- *
- * @return @li IX_SUCCESS, the interrupt has been disabled
- * @return @li IX_QMGR_Q_NOT_CONFIGURED, the specified qId has not been configured
- *
- */
-PUBLIC IX_STATUS
-ixQMgrNotificationDisable (IxQMgrQId qId);
-
-/**
- *
- * @ingroup IxQMgrAPI
- * 
- * @fn ixQMgrDispatcherLoopRunA0 (IxQMgrDispatchGroup group)
- *
- * @brief Run the callback dispatcher.
- *
- * This function runs the dispatcher for a group of queues.
- * Callbacks are made for interrupts that have occurred on queues within
- * the group that have registered callbacks. The order in which queues are
- * serviced depends on the queue priorities set by the client.
- * This function may be called from interrupt or task context.
- * For optimisations that were introduced in IXP42X B0 and supported IXP46X
- * the @a ixQMgrDispatcherLoopRunB0, or @a ixQMgrDispatcherLoopRunB0LLP 
- * should be used.
- *
- * This function is not re-entrant.
- *
- * @param group @ref IxQMgrDispatchGroup [in] - the group of queues over which the
- *                                        dispatcher will run
- *
- * @return @li void
- *
- * @note This function may be called from interrupt or task context.
- * However, for optimal performance the choice of context depends also on the
- * operating system used.
- *
- */
-PUBLIC void
-ixQMgrDispatcherLoopRunA0 (IxQMgrDispatchGroup group);
-
-/**
- *
- * @ingroup IxQMgrAPI
- * 
- * @fn ixQMgrDispatcherLoopRunB0 (IxQMgrDispatchGroup group)
- *
- * @brief Run the callback dispatcher.
- *
- * The enhanced version of @a ixQMgrDispatcherLoopRunA0 that is optimised for
- * features introduced in IXP42X B0 silicon and supported on IXP46X. 
- * This is the default dispatcher for IXP42X B0 and IXP46X silicon. 
- * The function runs the dispatcher for a group of queues.
- * Callbacks are made for interrupts that have occurred on queues within
- * the group that have registered callbacks. The order in which queues are
- * serviced depends on the queue priorities set by the client.
- * This  function may be called from interrupt or task context.
- *
- * This function is not re-entrant.
- *
- * @param group @ref IxQMgrDispatchGroup [in] - the group of queues over which the
- *                                        dispatcher will run
- *
- * @return @li void
- *
- *
- * @note This function may be called from interrupt or task context.
- * However, for optimal performance the choice of context depends also on the
- * operating system used.
- *
- */
-PUBLIC void
-ixQMgrDispatcherLoopRunB0 (IxQMgrDispatchGroup group);
-
-/**
- *
- * @ingroup IxQMgrAPI
- * 
- * @fn ixQMgrDispatcherLoopRunB0LLP (IxQMgrDispatchGroup group)
- *
- * @brief Run the callback dispatcher.
- *
- * This is a version of the optimised dispatcher for IXP42X B0 and IXP46X, 
- * @a ixQMgrDispatcherLoopRunB0, with added support for livelock prevention. 
- * This dispatcher will only be used for the IXP42X B0 or IXP46X silicon if 
- * feature control indicates that IX_FEATURECTRL_ORIGB0_DISPATCHER is set to   
- * IX_FEATURE_CTRL_SWCONFIG_DISABLED. Otherwise the @a ixQMgrDispatcherLoopRunB0 
- * dispatcher will be used (Default). 
- *
- * When this dispatcher notifies for a queue that is type
- * IX_QMGR_TYPE_REALTIME_PERIODIC, notifications for queues that are set
- * as type IX_QMGR_REALTIME_SPORADIC are not processed and disabled.
- * This helps prevent any tasks resulting from the notification of the 
- * IX_QMGR_TYPE_REALTIME_PERIODIC type queue to being subject to livelock.
- * The function runs the dispatcher for a group of queues.
- * Callbacks are made for interrupts that have occurred on queues within
- * the group that have registered callbacks. The order in which queues are
- * serviced depends on their type along with the  queue priorities set by the 
- * client. This function may be called from interrupt or task context.
- *
- * This function is not re-entrant.
- *
- * @param group @ref IxQMgrDispatchGroup [in] - the group of queues over which 
- *                                        the dispatcher will run
- *
- * @return @li void
- *
- * @note This function may be called from interrupt or task context.
- * However, for optimal performance the choice of context depends also on the
- * operating system used.
- *
- */
-PUBLIC void
-ixQMgrDispatcherLoopRunB0LLP (IxQMgrDispatchGroup group);
-
-/**
- *
- * @ingroup IxQMgrAPI
- * 
- * @fn ixQMgrNotificationCallbackSet (IxQMgrQId qId,
-			       IxQMgrCallback callback,
-			       IxQMgrCallbackId callbackId)
- *
- * @brief Set the notification callback for a queue.
- *
- * This function sets the callback for the specified queue. This callback will
- * be called by the dispatcher, and may be called in the context of a interrupt
- * If callback has a value of NULL the previously registered callback, if one
- * exists will be unregistered.
- *
- * @param qId @ref IxQMgrQId [in] - the queue idenfifier
- * @param callback @ref IxQMgrCallback  [in] - the callback registered for this queue
- * @param callbackId @ref IxQMgrCallbackId [in] - the callback identifier
- *
- * @return @li IX_SUCCESS, the callback for the specified queue has been set
- * @return @li IX_QMGR_Q_NOT_CONFIGURED, the specified qId has not been configured
- *
- */
-PUBLIC IX_STATUS
-ixQMgrNotificationCallbackSet (IxQMgrQId qId,
-			       IxQMgrCallback callback,
-			       IxQMgrCallbackId callbackId);
-
-/**
- *
- * @ingroup IxQMgrAPI
- *
- * @fn ixQMgrDispatcherLoopGet (IxQMgrDispatcherFuncPtr *qDispatcherFuncPtr)
- *
- * @brief Get QMgr DispatcherLoopRun for respective silicon device
- *
- * This function gets a function pointer to ixQMgrDispatcherLoopRunA0() for IXP42X A0
- * Silicon. If the IXP42X B0 or 46X Silicon, the default is the ixQMgrDispatcherLoopRunB0()
- * function, however if live lock prevention is enabled a function pointer to
- * ixQMgrDispatcherLoopRunB0LLP() is given.
- *
- * @param *qDispatchFuncPtr @ref IxQMgrDispatcherFuncPtr [out]  - 
- *              the function pointer of QMgr Dispatcher
- *
- */
-PUBLIC void
-ixQMgrDispatcherLoopGet (IxQMgrDispatcherFuncPtr *qDispatcherFuncPtr);
-
-/**
- *
- * @ingroup IxQMgrAPI
- *
- * @fn ixQMgrStickyInterruptRegEnable(void)
- *
- * @brief Enable AQM's sticky interrupt register behaviour only available
- *        on B0 Silicon. 
- * 
- * When AQM's sticky interrupt register is enabled, interrupt register bit will
- * only be cleared when a '1' is written to interrupt register bit and the
- * interrupting condition is satisfied, i.e.queue condition does not exist.
- * 
- * @note This function must be called before any queue is enabled.
- *       Calling this function after queue is enabled will cause
- *       undefined results. 
- *
- * @return none
- *
- */
-PUBLIC void
-ixQMgrStickyInterruptRegEnable(void);
-
-
-/**
- * @ingroup IxQMgrAPI
- *
- * @fn ixQMgrCallbackTypeSet(IxQMgrQId qId,
-                             IxQMgrType type)
- *
- * @brief Set the Callback Type of a queue.
- *
- * This function is only used for live lock prevention.
- * This function allows the callback type of a queue to be set. The default for
- * all queues is IX_QMGR_TYPE_REALTIME_OTHER. Setting the type to
- * IX_QMGR_TYPE_REALTIME_SPORADIC means that this queue will have it's 
- * notifications disabled while there is a task associated with a 
- * queue of type IX_QMGR_TYPE_REALTIME_PERIODIC running. As live lock
- * prevention operates on lower queues, this function should
- * be called for lower queues only.
- * This function is not re-entrant.  
- *
- * @param qId @ref IxQMgrQId [in] - the queue identifier
- * @param type @ref IxQMgrType [in] - the type of callback
- *
- * @return @li IX_SUCCESS, successfully set callback type for the queue entry
- * @return @li IX_QMGR_Q_NOT_CONFIGURED, queue not configured for this QId
- * @return @li IX_QMGR_PARAMETER_ERROR, invalid parameter(s).
- *
- */
-PUBLIC IX_STATUS
-ixQMgrCallbackTypeSet(IxQMgrQId qId,
-                      IxQMgrType type);
-
-/**
- * @ingroup IxQMgrAPI
- *
- * @fn ixQMgrCallbackTypeGet(IxQMgrQId qId,
-                             IxQMgrType *type)
- *
- * @brief Get the Callback Type of a queue.
- *
- * This function allows the callback type of a queue to be got. As live lock
- * prevention operates on lower queues, this function should
- * be called for lower queues only.
- * This function is re-entrant.
- *
- * @param qId @ref IxQMgrQId [in] - the queue identifier
- * @param *type @ref IxQMgrType [out] - the type of callback
- *
- * @return @li IX_SUCCESS, successfully set callback type for the queue entry
- * @return @li IX_QMGR_Q_NOT_CONFIGURED, queue not configured for this QId
- * @return @li IX_QMGR_PARAMETER_ERROR, invalid parameter(s)
- *
- */
-PUBLIC IX_STATUS
-ixQMgrCallbackTypeGet(IxQMgrQId qId,
-                      IxQMgrType *type);
-
-/**
- * @ingroup IxQMgrAPI
- *
- * @fn ixQMgrPeriodicDone(void)
- *
- * @brief Indicate that the Periodic task is completed for LLP
- *
- * This function is used as part of live lock prevention. 
- * A periodic task is a task that results from a queue that 
- * is set as type IX_QMGR_TYPE_REALTIME_PERIODIC. This function 
- * should be called to indicate to the dispatcher that the
- * the periodic task is completed. This ensures that the notifications
- * for queues set as type sporadic queues are re-enabled.
- * This function is re-entrant.
- *
- */
-PUBLIC void
-ixQMgrPeriodicDone(void);
-
-
-/**
- * @ingroup IxQMgrAPI
- *
- * @fn ixQMgrLLPShow(int resetStats)
- *
- * @brief Print out the live lock prevention statistics when in debug mode.
- *
- * This function prints out statistics related to the livelock. These
- * statistics are only collected in debug mode.
- * This function is not re-entrant.
- *
- * @param resetStats @ref int [in] - if set the the stats are reset.
- *
- */
-PUBLIC void
-ixQMgrLLPShow(int resetStats);
-
-
-#endif /* IXQMGR_H */
-
-/**
- * @} defgroup IxQMgrAPI
- */
-
-
diff --git a/arch/arm/cpu/ixp/npe/include/IxQMgrAqmIf_p.h b/arch/arm/cpu/ixp/npe/include/IxQMgrAqmIf_p.h
deleted file mode 100644
index 4f0f64d..0000000
--- a/arch/arm/cpu/ixp/npe/include/IxQMgrAqmIf_p.h
+++ /dev/null
@@ -1,927 +0,0 @@
-/**
- * @file    IxQMgrAqmIf_p.h
- *
- * @author Intel Corporation
- * @date    30-Oct-2001
- *
- * @brief   The IxQMgrAqmIf sub-component provides a number of inline
- * functions for performing I/O on the AQM. 
- *
- * Because  some functions contained in this module are inline and are
- * used in other modules (within the QMgr component) the definitions are
- * contained in this header file. The "normal" use of inline functions
- * is to use the inline functions in the module in which they are
- * defined. In this case these inline functions are used in external
- * modules and therefore the use of "inline extern". What this means
- * is as follows: if a function foo is declared as "inline extern"this
- * definition is only used for inlining, in no case is the function
- * compiled on its own. If the compiler cannot inline the function it
- * becomes an external reference. Therefore in IxQMgrAqmIf.c all
- * inline functions are defined without the "inline extern" specifier
- * and so define the external references. In all other modules these
- * funtions are defined as "inline extern".
- *
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- * 
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- * 
- * @par
- * -- End of Copyright Notice --
-*/
-
-#ifndef IXQMGRAQMIF_P_H
-#define IXQMGRAQMIF_P_H
-
-#include "IxOsalTypes.h"
-
-/*
- * inline definition
- */
- 
-#ifdef IX_OSAL_INLINE_ALL
-/* If IX_OSAL_INLINE_ALL is set then each inlineable API functions will be defined as
-   inline functions */
-#define IX_QMGR_AQMIF_INLINE IX_OSAL_INLINE_EXTERN
-#else   
-#ifdef IXQMGRAQMIF_C
-#ifndef IX_QMGR_AQMIF_INLINE
-#define IX_QMGR_AQMIF_INLINE
-#endif
-#else  
-#ifndef IX_QMGR_AQMIF_INLINE
-#define IX_QMGR_AQMIF_INLINE IX_OSAL_INLINE_EXTERN
-#endif
-#endif /* IXQMGRAQMIF_C */
-#endif /* IX_OSAL_INLINE */
-
-
-/*
- * User defined include files.
- */
-#include "IxQMgr.h"
-#include "IxQMgrLog_p.h"
-#include "IxQMgrQCfg_p.h"
-
-/* Because this file contains inline functions which will be compiled into
- * other components, we need to ensure that the IX_COMPONENT_NAME define
- * is set to ix_qmgr while this code is being compiled.  This will ensure
- * that the correct implementation is provided for the memory access macros
- * IX_OSAL_READ_LONG and IX_OSAL_WRITE_LONG which are used in this file.
- * This must be done before including "IxOsalMemAccess.h"
- */
-#define IX_QMGR_AQMIF_SAVED_COMPONENT_NAME IX_COMPONENT_NAME
-#undef  IX_COMPONENT_NAME
-#define IX_COMPONENT_NAME ix_qmgr
-#include "IxOsal.h" 
-
-/*
- * #defines and macros used in this file.
- */
-
-/* Number of bytes per word */
-#define IX_QMGR_NUM_BYTES_PER_WORD 4
-
-/* Underflow bit mask  */
-#define IX_QMGR_UNDERFLOW_BIT_OFFSET    0x0
-
-/* Overflow bit mask */
-#define IX_QMGR_OVERFLOW_BIT_OFFSET     0x1
-
-/* Queue access register, queue 0 */
-#define IX_QMGR_QUEACC0_OFFSET      0x0000
-
-/* Size of queue access register in words */
-#define IX_QMGR_QUEACC_SIZE         0x4/*words*/
-
-/* Queue status register, queues 0-7 */
-#define IX_QMGR_QUELOWSTAT0_OFFSET  (IX_QMGR_QUEACC0_OFFSET +\
-(IX_QMGR_MAX_NUM_QUEUES * IX_QMGR_QUEACC_SIZE * IX_QMGR_NUM_BYTES_PER_WORD))
-
-/* Queue status register, queues 8-15 */
-#define IX_QMGR_QUELOWSTAT1_OFFSET  (IX_QMGR_QUELOWSTAT0_OFFSET +\
-                                     IX_QMGR_NUM_BYTES_PER_WORD)
-
-/* Queue status register, queues 16-23 */
-#define IX_QMGR_QUELOWSTAT2_OFFSET  (IX_QMGR_QUELOWSTAT1_OFFSET +\
-                                     IX_QMGR_NUM_BYTES_PER_WORD)
-
-/* Queue status register, queues 24-31 */
-#define IX_QMGR_QUELOWSTAT3_OFFSET  (IX_QMGR_QUELOWSTAT2_OFFSET +\
-                                     IX_QMGR_NUM_BYTES_PER_WORD)
-
-/* Queue status register Q status bits mask */
-#define IX_QMGR_QUELOWSTAT_QUE_STS_BITS_MASK 0xF
-
-/* Size of queue 0-31 status register */
-#define IX_QMGR_QUELOWSTAT_SIZE     0x4 /*words*/
-
-/* The number of queues' status specified per word */
-#define IX_QMGR_QUELOWSTAT_NUM_QUE_PER_WORD 0x8
-
-/* Queue UF/OF status register queues 0-15  */
-#define IX_QMGR_QUEUOSTAT0_OFFSET   (IX_QMGR_QUELOWSTAT3_OFFSET +\
-                                     IX_QMGR_NUM_BYTES_PER_WORD)
-/* Queue UF/OF status register queues 16-31 */
-#define IX_QMGR_QUEUOSTAT1_OFFSET   (IX_QMGR_QUEUOSTAT0_OFFSET +\
-                                     IX_QMGR_NUM_BYTES_PER_WORD)
-
-/* The number of queues' underflow/overflow status specified per word */
-#define IX_QMGR_QUEUOSTAT_NUM_QUE_PER_WORD 0x10
-
-/* Queue NE status register, queues 32-63   */
-#define IX_QMGR_QUEUPPSTAT0_OFFSET  (IX_QMGR_QUEUOSTAT1_OFFSET +\
-                                     IX_QMGR_NUM_BYTES_PER_WORD)
-
-/* Queue F status register, queues 32-63    */
-#define IX_QMGR_QUEUPPSTAT1_OFFSET  (IX_QMGR_QUEUPPSTAT0_OFFSET +\
-                                     IX_QMGR_NUM_BYTES_PER_WORD)
-
-/* Size of queue 32-63 status register */
-#define IX_QMGR_QUEUPPSTAT_SIZE     0x2 /*words*/
-
-/* The number of queues' status specified per word */
-#define IX_QMGR_QUEUPPSTAT_NUM_QUE_PER_WORD 0x20
-
-/* Queue INT source select register, queues 0-7   */
-#define IX_QMGR_INT0SRCSELREG0_OFFSET (IX_QMGR_QUEUPPSTAT1_OFFSET   +\
-                                       IX_QMGR_NUM_BYTES_PER_WORD)
-
-/* Queue INT source select register, queues 8-15  */
-#define IX_QMGR_INT0SRCSELREG1_OFFSET (IX_QMGR_INT0SRCSELREG0_OFFSET+\
-                                       IX_QMGR_NUM_BYTES_PER_WORD)
-
-/* Queue INT source select register, queues 16-23 */
-#define IX_QMGR_INT0SRCSELREG2_OFFSET (IX_QMGR_INT0SRCSELREG1_OFFSET+\
-                                       IX_QMGR_NUM_BYTES_PER_WORD)
-
-/* Queue INT source select register, queues 24-31 */
-#define IX_QMGR_INT0SRCSELREG3_OFFSET (IX_QMGR_INT0SRCSELREG2_OFFSET+\
-                                       IX_QMGR_NUM_BYTES_PER_WORD)
-
-/* Size of interrupt source select reegister */
-#define IX_QMGR_INT0SRCSELREG_SIZE  0x4 /*words*/
-
-/* The number of queues' interrupt source select specified per word*/
-#define IX_QMGR_INTSRC_NUM_QUE_PER_WORD 0x8
-
-/* Queue INT enable register, queues 0-31  */
-#define IX_QMGR_QUEIEREG0_OFFSET    (IX_QMGR_INT0SRCSELREG3_OFFSET +\
-                                     IX_QMGR_NUM_BYTES_PER_WORD)
-
-/* Queue INT enable register, queues 32-63 */
-#define IX_QMGR_QUEIEREG1_OFFSET    (IX_QMGR_QUEIEREG0_OFFSET      +\
-                                     IX_QMGR_NUM_BYTES_PER_WORD)
-
-/* Queue INT register, queues 0-31  */
-#define IX_QMGR_QINTREG0_OFFSET     (IX_QMGR_QUEIEREG1_OFFSET +\
-                                     IX_QMGR_NUM_BYTES_PER_WORD)
-
-/* Queue INT register, queues 32-63 */
-#define IX_QMGR_QINTREG1_OFFSET     (IX_QMGR_QINTREG0_OFFSET  +\
-                                     IX_QMGR_NUM_BYTES_PER_WORD)
-
-/* Size of interrupt register */
-#define IX_QMGR_QINTREG_SIZE        0x2 /*words*/
-
-/* Number of queues' status specified per word */
-#define IX_QMGR_QINTREG_NUM_QUE_PER_WORD 0x20
-
-/* Number of bits per queue interrupt status */
-#define IX_QMGR_QINTREG_BITS_PER_QUEUE 0x1
-#define IX_QMGR_QINTREG_BIT_OFFSET 0x1
-
-/* Size of address space not used by AQM */
-#define IX_QMGR_AQM_UNUSED_ADDRESS_SPACE_SIZE_IN_BYTES  0x1bC0
-
-/* Queue config register, queue 0 */
-#define IX_QMGR_QUECONFIG_BASE_OFFSET (IX_QMGR_QINTREG1_OFFSET +\
-                             IX_QMGR_NUM_BYTES_PER_WORD +\
-                             IX_QMGR_AQM_UNUSED_ADDRESS_SPACE_SIZE_IN_BYTES)
-
-/* Total size of configuration words */
-#define IX_QMGR_QUECONFIG_SIZE      0x100
-
-/* Start of SRAM queue buffer space */
-#define IX_QMGR_QUEBUFFER_SPACE_OFFSET (IX_QMGR_QUECONFIG_BASE_OFFSET +\
-                                 IX_QMGR_MAX_NUM_QUEUES * IX_QMGR_NUM_BYTES_PER_WORD)
-
-/* Total bits in a word */
-#define BITS_PER_WORD 32
-
-/* Size of queue buffer space */
-#define IX_QMGR_QUE_BUFFER_SPACE_SIZE 0x1F00
-
-/*
- * This macro will return the address of the access register for the
- * queue  specified by qId
- */
-#define IX_QMGR_Q_ACCESS_ADDR_GET(qId)\
-        (((qId) * (IX_QMGR_QUEACC_SIZE * IX_QMGR_NUM_BYTES_PER_WORD))\
-	 + IX_QMGR_QUEACC0_OFFSET)
-
-/* 
- * Bit location of bit-3 of INT0SRCSELREG0 register to enabled
- * sticky interrupt register.
- */
-#define IX_QMGR_INT0SRCSELREG0_BIT3 3
-
-/*
- * Variable declerations global to this file. Externs are followed by
- * statics.
- */
-extern UINT32 aqmBaseAddress;
-
-/*
- * Function declarations.
- */
-void
-ixQMgrAqmIfInit (void);
-
-void
-ixQMgrAqmIfUninit (void);
-
-unsigned
-ixQMgrAqmIfLog2 (unsigned number);
-
-void
-ixQMgrAqmIfQRegisterBitsWrite (IxQMgrQId qId, 
-			       UINT32 registerBaseAddrOffset,
-			       unsigned queuesPerRegWord,
-			       UINT32 value);
-
-void
-ixQMgrAqmIfQStatusCheckValsCalc (IxQMgrQId qId,
-				 IxQMgrSourceId srcSel,
-				 unsigned int *statusWordOffset,
-				 UINT32 *checkValue,
-				 UINT32 *mask);
-/*
- * The Xscale software allways deals with logical addresses and so the
- * base address of the AQM memory space is not a hardcoded value. This
- * function must be called before any other function in this component.
- * NO CHECKING is performed to ensure that the base address has been
- * set.
- */
-void
-ixQMgrAqmIfBaseAddressSet (UINT32 address);
-
-/*
- * Get the base address of the AQM memory space.
- */
-void
-ixQMgrAqmIfBaseAddressGet (UINT32 *address);
-
-/*
- * Get the sram base address
- */
-void
-ixQMgrAqmIfSramBaseAddressGet (UINT32 *address);
-
-/*
- * Read a queue status
- */
-void
-ixQMgrAqmIfQueStatRead (IxQMgrQId qId,
-			IxQMgrQStatus* status);
-
-
-/*
- *   Set INT0SRCSELREG0 Bit3 
- */ 
-void ixQMgrAqmIfIntSrcSelReg0Bit3Set (void);
-
-
-/*
- * Set the interrupt source
- */
-void
-ixQMgrAqmIfIntSrcSelWrite (IxQMgrQId qId,
-			   IxQMgrSourceId sourceId);
-
-/*
- * Enable interruptson a queue
- */
-void
-ixQMgrAqmIfQInterruptEnable (IxQMgrQId qId);
-
-/*
- * Disable interrupt on a quee
- */
-void
-ixQMgrAqmIfQInterruptDisable (IxQMgrQId qId);
-
-/*
- * Write the config register of the specified queue
- */
-void
-ixQMgrAqmIfQueCfgWrite (IxQMgrQId qId,
-			IxQMgrQSizeInWords qSizeInWords,
-			IxQMgrQEntrySizeInWords entrySizeInWords,
-			UINT32 freeSRAMAddress);
-
-/*
- * read fields from the config of the specified queue.
- */
-void
-ixQMgrAqmIfQueCfgRead (IxQMgrQId qId,
-		       unsigned int numEntries,
-		       UINT32 *baseAddress,
-		       unsigned int *ne,
-		       unsigned int *nf,
-		       UINT32 *readPtr,
-		       UINT32 *writePtr);
-
-/*
- * Set the ne and nf watermark level on a queue.
- */
-void
-ixQMgrAqmIfWatermarkSet (IxQMgrQId qId,
-			 unsigned ne,
-			 unsigned nf);
-
-/* Inspect an entry without moving the read pointer */
-IX_STATUS
-ixQMgrAqmIfQPeek (IxQMgrQId qId,
-		  unsigned int entryIndex,
-		  unsigned int *entry);
-
-/* Modify an entry without moving the write pointer */
-IX_STATUS
-ixQMgrAqmIfQPoke (IxQMgrQId qId,
-		  unsigned int entryIndex,
-		  unsigned int *entry);
-
-/*
- * Function prototype for inline functions. For description refers to 
- * the functions defintion below.
- */
-IX_QMGR_AQMIF_INLINE void
-ixQMgrAqmIfWordWrite (VUINT32 *address,
-		      UINT32 word);
-
-IX_QMGR_AQMIF_INLINE void
-ixQMgrAqmIfWordRead (VUINT32 *address,
-		     UINT32 *word);
-
-IX_QMGR_AQMIF_INLINE void
-ixQMgrAqmIfQPop (IxQMgrQId qId,
-		 IxQMgrQEntrySizeInWords numWords,
-		 UINT32 *entry);
-
-IX_QMGR_AQMIF_INLINE void
-ixQMgrAqmIfQPush (IxQMgrQId qId,
-		  IxQMgrQEntrySizeInWords numWords,
-		  UINT32 *entry);
-
-IX_QMGR_AQMIF_INLINE void
-ixQMgrAqmIfQStatusRegsRead (IxQMgrDispatchGroup group, 
-			    UINT32 *qStatusWords);
-
-IX_QMGR_AQMIF_INLINE BOOL
-ixQMgrAqmIfQStatusCheck (UINT32 *oldQStatusWords,
-			 UINT32 *newQStatusWords,
-			 unsigned int statusWordOffset,			 
-			 UINT32 checkValue,
-			 UINT32 mask);
-
-IX_QMGR_AQMIF_INLINE BOOL
-ixQMgrAqmIfRegisterBitCheck (IxQMgrQId qId, 
-			     UINT32 registerBaseAddrOffset,
-			     unsigned queuesPerRegWord,
-			     unsigned relativeBitOffset,
-			     BOOL reset);
-
-IX_QMGR_AQMIF_INLINE BOOL
-ixQMgrAqmIfUnderflowCheck (IxQMgrQId qId);
-
-IX_QMGR_AQMIF_INLINE BOOL
-ixQMgrAqmIfOverflowCheck (IxQMgrQId qId);
-
-IX_QMGR_AQMIF_INLINE UINT32
-ixQMgrAqmIfQRegisterBitsRead (IxQMgrQId qId, 
-			      UINT32 registerBaseAddrOffset,
-			      unsigned queuesPerRegWord);
-IX_QMGR_AQMIF_INLINE void
-ixQMgrAqmIfQInterruptRegWrite (IxQMgrDispatchGroup group, 
-			       UINT32 reg);
-IX_QMGR_AQMIF_INLINE void
-ixQMgrAqmIfQInterruptRegRead (IxQMgrDispatchGroup group, 
-			      UINT32 *regVal);
-
-IX_QMGR_AQMIF_INLINE void
-ixQMgrAqmIfQueLowStatRead (IxQMgrQId qId,
-			   IxQMgrQStatus *status);
-
-IX_QMGR_AQMIF_INLINE void
-ixQMgrAqmIfQueUppStatRead (IxQMgrQId qId,
-			   IxQMgrQStatus *status);
-
-IX_QMGR_AQMIF_INLINE void
-ixQMgrAqmIfQueStatRead (IxQMgrQId qId, 
-			IxQMgrQStatus *qStatus);
-
-IX_QMGR_AQMIF_INLINE unsigned
-ixQMgrAqmIfPow2NumDivide (unsigned numerator, 
-			  unsigned denominator);
-
-IX_QMGR_AQMIF_INLINE void
-ixQMgrAqmIfQInterruptEnableRegRead (IxQMgrDispatchGroup group, 
-			            UINT32 *regVal);
-/*
- * Inline functions
- */
-
-/*
- * This inline function is used by other QMgr components to write one
- * word to the specified address.
- */
-IX_QMGR_AQMIF_INLINE void
-ixQMgrAqmIfWordWrite (VUINT32 *address,
-		      UINT32 word)
-{
-    IX_OSAL_WRITE_LONG(address, word);
-}
-
-/*
- * This inline function is used by other QMgr components to read a
- * word from the specified address.
- */
-IX_QMGR_AQMIF_INLINE void
-ixQMgrAqmIfWordRead (VUINT32 *address,
-		     UINT32 *word)
-{
-    *word = IX_OSAL_READ_LONG(address);
-}
-
-
-/*
- * This inline function is used by other QMgr components to pop an
- * entry off the specified queue.
- */
-IX_QMGR_AQMIF_INLINE void
-ixQMgrAqmIfQPop (IxQMgrQId qId,
-		 IxQMgrQEntrySizeInWords numWords,
-		 UINT32 *entry)
-{
-    volatile UINT32 *accRegAddr;
-
-    accRegAddr = (UINT32*)(aqmBaseAddress +
-			   IX_QMGR_Q_ACCESS_ADDR_GET(qId));
-
-    switch (numWords)
-    {
-	case IX_QMGR_Q_ENTRY_SIZE1:
-	    ixQMgrAqmIfWordRead (accRegAddr, entry);
-	    break;
-	case IX_QMGR_Q_ENTRY_SIZE2:
-	    ixQMgrAqmIfWordRead (accRegAddr++, entry++);
-	    ixQMgrAqmIfWordRead (accRegAddr, entry);
-	    break;
-	case IX_QMGR_Q_ENTRY_SIZE4:
-	    ixQMgrAqmIfWordRead (accRegAddr++, entry++);
-	    ixQMgrAqmIfWordRead (accRegAddr++, entry++);
-	    ixQMgrAqmIfWordRead (accRegAddr++, entry++);
-	    ixQMgrAqmIfWordRead (accRegAddr, entry);
-	    break;
-	default:
-	    IX_QMGR_LOG_ERROR0("Invalid Q Entry size passed to ixQMgrAqmIfQPop");
-	    break;
-    }
-}
-
-/*
- * This inline function is used by other QMgr components to push an
- * entry to the specified queue.
- */
-IX_QMGR_AQMIF_INLINE void
-ixQMgrAqmIfQPush (IxQMgrQId qId,
-		  IxQMgrQEntrySizeInWords numWords,
-		  UINT32 *entry)
-{
-    volatile UINT32 *accRegAddr;
-
-    accRegAddr = (UINT32*)(aqmBaseAddress +
-			   IX_QMGR_Q_ACCESS_ADDR_GET(qId));
-    
-    switch (numWords)
-    {
-	case IX_QMGR_Q_ENTRY_SIZE1:
-	    ixQMgrAqmIfWordWrite (accRegAddr, *entry);
-	    break;
-	case IX_QMGR_Q_ENTRY_SIZE2:
-	    ixQMgrAqmIfWordWrite (accRegAddr++, *entry++);
-	    ixQMgrAqmIfWordWrite (accRegAddr, *entry);
-	    break;
-	case IX_QMGR_Q_ENTRY_SIZE4:
-	    ixQMgrAqmIfWordWrite (accRegAddr++, *entry++);
-	    ixQMgrAqmIfWordWrite (accRegAddr++, *entry++);
-	    ixQMgrAqmIfWordWrite (accRegAddr++, *entry++);
-	    ixQMgrAqmIfWordWrite (accRegAddr, *entry);
-	    break;
-	default:
-	    IX_QMGR_LOG_ERROR0("Invalid Q Entry size passed to ixQMgrAqmIfQPush");
-	    break;
-    }
-}
-
-/*
- * The AQM interrupt registers contains a bit for each AQM queue
- * specifying the queue (s) that cause an interrupt to fire. This
- * function is called by IxQMGrDispatcher component.
- */
-IX_QMGR_AQMIF_INLINE void
-ixQMgrAqmIfQStatusRegsRead (IxQMgrDispatchGroup group, 
-			    UINT32 *qStatusWords)
-{
-    volatile UINT32 *regAddress = NULL;
-
-    if (group == IX_QMGR_QUELOW_GROUP)
-    {
-	regAddress = (UINT32*)(aqmBaseAddress +
-			       IX_QMGR_QUELOWSTAT0_OFFSET);
-
-	ixQMgrAqmIfWordRead (regAddress++, qStatusWords++);
-	ixQMgrAqmIfWordRead (regAddress++, qStatusWords++);
-	ixQMgrAqmIfWordRead (regAddress++, qStatusWords++);
-	ixQMgrAqmIfWordRead (regAddress, qStatusWords);
-    }
-    else /* We have the upper queues */
-    {
-       /* Only need to read the Nearly Empty status register for
-	* queues 32-63 as for therse queues the interrtupt source
-	* condition is fixed to Nearly Empty
-	*/
-	regAddress = (UINT32*)(aqmBaseAddress +
-			       IX_QMGR_QUEUPPSTAT0_OFFSET);
-	ixQMgrAqmIfWordRead (regAddress, qStatusWords);
-    }
-}
-
-
-/*
- * This function check if the status for a queue has changed between
- * 2 snapshots and if it has, that the status matches a particular
- * value after masking.
- */
-IX_QMGR_AQMIF_INLINE BOOL
-ixQMgrAqmIfQStatusCheck (UINT32 *oldQStatusWords,
-			 UINT32 *newQStatusWords,
-			 unsigned int statusWordOffset,			 
-			 UINT32 checkValue,
-			 UINT32 mask)
-{
-    if (((oldQStatusWords[statusWordOffset] & mask) != 
-	 (newQStatusWords[statusWordOffset] & mask)) &&
-	((newQStatusWords[statusWordOffset] & mask) == checkValue))
-    {
-	return TRUE;
-    }
-
-    return FALSE;
-}
-
-/*
- * The AQM interrupt register contains a bit for each AQM queue
- * specifying the queue (s) that cause an interrupt to fire. This
- * function is called by IxQMgrDispatcher component.
- */
-IX_QMGR_AQMIF_INLINE void
-ixQMgrAqmIfQInterruptRegRead (IxQMgrDispatchGroup group, 
-			      UINT32 *regVal)
-{
-    volatile UINT32 *regAddress;
-
-    if (group == IX_QMGR_QUELOW_GROUP)
-    {
-	regAddress = (UINT32*)(aqmBaseAddress +
-			       IX_QMGR_QINTREG0_OFFSET);
-    }
-    else
-    {
-	regAddress = (UINT32*)(aqmBaseAddress +
-			       IX_QMGR_QINTREG1_OFFSET);
-    }
-
-    ixQMgrAqmIfWordRead (regAddress, regVal);
-}
-
-/*
- * The AQM interrupt enable register contains a bit for each AQM queue.
- * This function reads the interrupt enable register. This
- * function is called by IxQMgrDispatcher component.
- */
-IX_QMGR_AQMIF_INLINE void
-ixQMgrAqmIfQInterruptEnableRegRead (IxQMgrDispatchGroup group, 
-			            UINT32 *regVal)
-{
-    volatile UINT32 *regAddress;
-
-    if (group == IX_QMGR_QUELOW_GROUP)
-    {
-	regAddress = (UINT32*)(aqmBaseAddress +
-			       IX_QMGR_QUEIEREG0_OFFSET);
-    }
-    else
-    {
-	regAddress = (UINT32*)(aqmBaseAddress +
-			       IX_QMGR_QUEIEREG1_OFFSET);
-    }
-
-    ixQMgrAqmIfWordRead (regAddress, regVal);
-}
-
-
-/*
- * This inline function will read the status bit of a queue
- * specified by qId. If reset is TRUE the bit is cleared.
- */
-IX_QMGR_AQMIF_INLINE BOOL
-ixQMgrAqmIfRegisterBitCheck (IxQMgrQId qId, 
-			     UINT32 registerBaseAddrOffset,
-			     unsigned queuesPerRegWord,
-			     unsigned relativeBitOffset,
-			     BOOL reset)
-{
-    UINT32 actualBitOffset;
-    volatile UINT32 *registerAddress;
-    UINT32 registerWord;
-
-    /*
-     * Calculate the registerAddress
-     * multiple queues split accross registers
-     */
-    registerAddress = (UINT32*)(aqmBaseAddress +
-				registerBaseAddrOffset +
-				((qId / queuesPerRegWord) *
-				 IX_QMGR_NUM_BYTES_PER_WORD));
-
-    /*
-     * Get the status word
-     */
-    ixQMgrAqmIfWordRead (registerAddress, &registerWord);
-    
-    /*
-     * Calculate the actualBitOffset
-     * status for multiple queues stored in one register
-     */
-    actualBitOffset = (relativeBitOffset + 1) <<
-	((qId & (queuesPerRegWord - 1)) * (BITS_PER_WORD / queuesPerRegWord));
-
-    /* Check if the status bit is set */
-    if (registerWord & actualBitOffset)
-    {
-	/* Clear the bit if reset */
-	if (reset)
-	{
-	    ixQMgrAqmIfWordWrite (registerAddress, registerWord & (~actualBitOffset));
-	}
-	return TRUE;
-    }
-
-    /* Bit not set */
-    return FALSE;
-}
-
-
-/*
- * @ingroup IxQmgrAqmIfAPI
- *
- * @brief Read the underflow status of a queue 
- *
- * This inline function will read the underflow status of a queue
- * specified by qId.
- * 
- */
-IX_QMGR_AQMIF_INLINE BOOL
-ixQMgrAqmIfUnderflowCheck (IxQMgrQId qId)
-{
-    if (qId < IX_QMGR_MIN_QUEUPP_QID)
-    {
-	return (ixQMgrAqmIfRegisterBitCheck (qId,
-					     IX_QMGR_QUEUOSTAT0_OFFSET,
-					     IX_QMGR_QUEUOSTAT_NUM_QUE_PER_WORD,
-					     IX_QMGR_UNDERFLOW_BIT_OFFSET,
-					     TRUE/*reset*/));
-    }
-    else
-    {
-	/* Qs 32-63 have no underflow status */
-	return FALSE;
-    }
-}
-
-/*
- * This inline function will read the overflow status of a queue
- * specified by qId.
- */
-IX_QMGR_AQMIF_INLINE BOOL
-ixQMgrAqmIfOverflowCheck (IxQMgrQId qId)
-{
-    if (qId < IX_QMGR_MIN_QUEUPP_QID)
-    {
-	return (ixQMgrAqmIfRegisterBitCheck (qId,
-					     IX_QMGR_QUEUOSTAT0_OFFSET,
-					     IX_QMGR_QUEUOSTAT_NUM_QUE_PER_WORD,
-					     IX_QMGR_OVERFLOW_BIT_OFFSET,
-					     TRUE/*reset*/));
-    }
-    else
-    {
-	/* Qs 32-63 have no overflow status */
-	return FALSE;
-    }
-}
-
-/*
- * This inline function will read the status bits of a queue
- * specified by qId.
- */
-IX_QMGR_AQMIF_INLINE UINT32
-ixQMgrAqmIfQRegisterBitsRead (IxQMgrQId qId, 
-			      UINT32 registerBaseAddrOffset,
-			      unsigned queuesPerRegWord)
-{
-    volatile UINT32 *registerAddress;
-    UINT32 registerWord;
-    UINT32 statusBitsMask;
-    UINT32 bitsPerQueue;
-
-    bitsPerQueue = BITS_PER_WORD / queuesPerRegWord;
-
-    /*
-     * Calculate the registerAddress
-     * multiple queues split accross registers
-     */
-    registerAddress = (UINT32*)(aqmBaseAddress +
-				registerBaseAddrOffset +
-				((qId / queuesPerRegWord) *
-				 IX_QMGR_NUM_BYTES_PER_WORD));
-    /*
-     * Read the status word
-     */
-    ixQMgrAqmIfWordRead (registerAddress, &registerWord);
-    
-
-    /*
-     * Calculate the mask for the status bits for this queue.
-     */
-    statusBitsMask = ((1 << bitsPerQueue) - 1);
-
-    /*
-     * Shift the status word so it is right justified
-     */    
-    registerWord >>= ((qId & (queuesPerRegWord - 1)) * bitsPerQueue);
-
-    /*
-     * Mask out all bar the status bits for this queue
-     */
-    return (registerWord &= statusBitsMask);
-}
-
-/*
- * This function is called by IxQMgrDispatcher to set the contents of
- * the AQM interrupt register.
- */
-IX_QMGR_AQMIF_INLINE void
-ixQMgrAqmIfQInterruptRegWrite (IxQMgrDispatchGroup group, 
-			       UINT32 reg)
-{
-    volatile UINT32 *address;
-
-    if (group == IX_QMGR_QUELOW_GROUP)
-    {
-	address = (UINT32*)(aqmBaseAddress +
-			    IX_QMGR_QINTREG0_OFFSET);
-    }
-    else
-    {
-	address = (UINT32*)(aqmBaseAddress +
-			    IX_QMGR_QINTREG1_OFFSET);
-    }
-
-    ixQMgrAqmIfWordWrite (address, reg);
-}
-
-/*
- * Read the status of a queue in the range 0-31.
- *
- * This function is used by other QMgr components to read the
- * status of the queue specified by qId.
- */
-IX_QMGR_AQMIF_INLINE void
-ixQMgrAqmIfQueLowStatRead (IxQMgrQId qId,
-			   IxQMgrQStatus *status)
-{
-    /* Read the general status bits */
-    *status = ixQMgrAqmIfQRegisterBitsRead (qId,
-					    IX_QMGR_QUELOWSTAT0_OFFSET,
-					    IX_QMGR_QUELOWSTAT_NUM_QUE_PER_WORD);
-}
-
-/*
- * This function will read the status of the queue specified
- * by qId.
- */
-IX_QMGR_AQMIF_INLINE void
-ixQMgrAqmIfQueUppStatRead (IxQMgrQId qId,
-			   IxQMgrQStatus *status)
-{
-    /* Reset the status bits */
-    *status = 0;
-
-    /* 
-     * Check if the queue is nearly empty,
-     * N.b. QUPP stat register contains status for regs 32-63 at each
-     *      bit position so subtract 32 to get bit offset
-     */
-    if (ixQMgrAqmIfRegisterBitCheck ((qId - IX_QMGR_MIN_QUEUPP_QID),
-				     IX_QMGR_QUEUPPSTAT0_OFFSET,
-				     IX_QMGR_QUEUPPSTAT_NUM_QUE_PER_WORD,
-				     0/*relativeBitOffset*/,
-				     FALSE/*!reset*/))
-    {
-	*status |= IX_QMGR_Q_STATUS_NE_BIT_MASK;
-    }
-
-    /* 
-     * Check if the queue is full,
-     * N.b. QUPP stat register contains status for regs 32-63 at each
-     *      bit position so subtract 32 to get bit offset
-     */
-    if (ixQMgrAqmIfRegisterBitCheck ((qId - IX_QMGR_MIN_QUEUPP_QID),
-				     IX_QMGR_QUEUPPSTAT1_OFFSET,
-				     IX_QMGR_QUEUPPSTAT_NUM_QUE_PER_WORD,
-				     0/*relativeBitOffset*/,
-				     FALSE/*!reset*/))
-    {
-	*status |= IX_QMGR_Q_STATUS_F_BIT_MASK;
-    }
-}
-
-/*
- * This function is used by other QMgr components to read the
- * status of the queue specified by qId.
- */
-IX_QMGR_AQMIF_INLINE void
-ixQMgrAqmIfQueStatRead (IxQMgrQId qId, 
-			IxQMgrQStatus *qStatus)
-{
-    if (qId < IX_QMGR_MIN_QUEUPP_QID)
-    {
-	ixQMgrAqmIfQueLowStatRead (qId, qStatus);
-    }
-    else
-    {
-	ixQMgrAqmIfQueUppStatRead (qId, qStatus);
-    }
-}
-
-
-/*
- * This function performs a mod division
- */
-IX_QMGR_AQMIF_INLINE unsigned
-ixQMgrAqmIfPow2NumDivide (unsigned numerator, 
-			  unsigned denominator)
-{
-    /* Number is evenly divisable by 2 */
-    return (numerator >> ixQMgrAqmIfLog2 (denominator));
-}
-
-/* Restore IX_COMPONENT_NAME */
-#undef IX_COMPONENT_NAME
-#define IX_COMPONENT_NAME IX_QMGR_AQMIF_SAVED_COMPONENT_NAME
-
-#endif/*IXQMGRAQMIF_P_H*/
diff --git a/arch/arm/cpu/ixp/npe/include/IxQMgrDefines_p.h b/arch/arm/cpu/ixp/npe/include/IxQMgrDefines_p.h
deleted file mode 100644
index 0183596..0000000
--- a/arch/arm/cpu/ixp/npe/include/IxQMgrDefines_p.h
+++ /dev/null
@@ -1,55 +0,0 @@
-/**
- * @file    IxQMgrDefines_p.h
- *
- * @author Intel Corporation
- * @date    19-Jul-2002
- *
- * @brief   IxQMgr Defines and tuneable constants
- *
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- * 
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- * 
- * @par
- * -- End of Copyright Notice --
-*/
-
-#ifndef IXQMGRDEFINES_P_H
-#define IXQMGRDEFINES_P_H
-
-#define IX_QMGR_PARM_CHECKS_ENABLED   1
-#define IX_QMGR_STATS_UPDATE_ENABLED  1
-
-#endif /* IXQMGRDEFINES_P_H */
diff --git a/arch/arm/cpu/ixp/npe/include/IxQMgrDispatcher_p.h b/arch/arm/cpu/ixp/npe/include/IxQMgrDispatcher_p.h
deleted file mode 100644
index 71a3f85..0000000
--- a/arch/arm/cpu/ixp/npe/include/IxQMgrDispatcher_p.h
+++ /dev/null
@@ -1,106 +0,0 @@
-/**
- * @file    IxQMgrDispatcher_p.h
- *
- * @author Intel Corporation
- * @date    07-Feb-2002
- *
- * @brief   This file contains the internal functions for dispatcher
- *
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- * 
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- * 
- * @par
- * -- End of Copyright Notice --
-*/
-
-#ifndef IXQMGRDISPATCHER_P_H
-#define IXQMGRDISPATCHER_P_H
-
-/*
- * User defined include files
- */
-#include "IxQMgr.h"
-
-/*
- * This structure defines the statistic data for a queue
- */
-typedef struct
-{
-    unsigned callbackCnt;       /* Call count of callback                    */
-    unsigned priorityChangeCnt; /* Priority change count                     */
-    unsigned intNoCallbackCnt;  /* Interrupt fired but no callback set count */
-    unsigned intLostCallbackCnt;  /* Interrupt lost and detected ;  SCR541   */
-    BOOL notificationEnabled;    /* Interrupt enabled for this queue         */
-    IxQMgrSourceId srcSel;       /* interrupt source                         */
-    unsigned enableCount;        /* num times notif enabled by LLP           */
-    unsigned disableCount;       /* num of times notif disabled by LLP       */
-} IxQMgrDispatcherQStats;
-
-/*
- * This structure defines statistic data for the disatcher
- */
-typedef struct
- {
-    unsigned loopRunCnt;       /* ixQMgrDispatcherLoopRun count */
-
-    IxQMgrDispatcherQStats queueStats[IX_QMGR_MAX_NUM_QUEUES];
-
-} IxQMgrDispatcherStats;
-
-/*
- * Initialise the dispatcher component
- */
-void
-ixQMgrDispatcherInit (void);
-
-/*
- * Get the dispatcher statistics
- */
-IxQMgrDispatcherStats*
-ixQMgrDispatcherStatsGet (void);
-
-/**
- * Retrieve the number of leading zero bits starting from the MSB 
- * This function is implemented as an (extremely fast) asm routine 
- * for XSCALE processor (see clz instruction) and as a (slower) C 
- * function for other systems.
- */
-unsigned int
-ixQMgrCountLeadingZeros(unsigned int value);
-
-#endif/*IXQMGRDISPATCHER_P_H*/
-
-
diff --git a/arch/arm/cpu/ixp/npe/include/IxQMgrLog_p.h b/arch/arm/cpu/ixp/npe/include/IxQMgrLog_p.h
deleted file mode 100644
index 6b685b8..0000000
--- a/arch/arm/cpu/ixp/npe/include/IxQMgrLog_p.h
+++ /dev/null
@@ -1,124 +0,0 @@
-/**
- * @file    IxQMgrLog_p.h
- *
- * @author Intel Corporation
- * @date    07-Feb-2002
- *
- * @brief   This file contains the internal functions for config
- *
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- * 
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- * 
- * @par
- * -- End of Copyright Notice --
-*/
-
-#ifndef IXQMGRLOG_P_H
-#define IXQMGRLOG_P_H
-
-/*
- * User defined header files
- */
-#include "IxOsal.h"
-
-/*
- * Macros
- */
-
-#define IX_QMGR_LOG0(string) do\
-{\
-    ixOsalLog(IX_OSAL_LOG_LVL_USER, IX_OSAL_LOG_DEV_STDOUT, string, 0, 0, 0, 0, 0, 0);\
-}while(0);
-
-#define IX_QMGR_LOG1(string, arg1) do\
-{\
-    ixOsalLog(IX_OSAL_LOG_LVL_USER, IX_OSAL_LOG_DEV_STDOUT, string, (int)arg1, 0, 0, 0, 0, 0);\
-}while(0);
-
-#define IX_QMGR_LOG2(string, arg1, arg2) do\
-{\
-    ixOsalLog(IX_OSAL_LOG_LVL_USER, IX_OSAL_LOG_DEV_STDOUT, string, (int)arg1, (int)arg2, 0, 0, 0, 0);\
-}while(0);
-
-#define IX_QMGR_LOG3(string, arg1, arg2, arg3) do\
-{\
-    ixOsalLog(IX_OSAL_LOG_LVL_USER, IX_OSAL_LOG_DEV_STDOUT, string, (int)arg1, (int)arg2, (int)arg3, 0, 0, 0);\
-}while(0);
-
-#define IX_QMGR_LOG6(string, arg1, arg2, arg3, arg4, arg5, arg6) do\
-{\
-    ixOsalLog(IX_OSAL_LOG_LVL_USER, IX_OSAL_LOG_DEV_STDOUT, string, (int)arg1, (int)arg2, (int)arg3, (int)arg4, (int)arg5, (int)arg6); \
-}while(0);
-
-#define IX_QMGR_LOG_WARNING0(string) do\
-{\
-    ixOsalLog(IX_OSAL_LOG_LVL_WARNING, IX_OSAL_LOG_DEV_STDOUT, string, 0, 0, 0, 0, 0, 0);\
-}while(0);
-
-#define IX_QMGR_LOG_WARNING1(string, arg1) do\
-{\
-    ixOsalLog(IX_OSAL_LOG_LVL_WARNING, IX_OSAL_LOG_DEV_STDOUT, string, (int)arg1, 0, 0, 0, 0, 0);\
-}while(0);
-
-#define IX_QMGR_LOG_WARNING2(string, arg1, arg2) do\
-{\
-    ixOsalLog(IX_OSAL_LOG_LVL_WARNING, IX_OSAL_LOG_DEV_STDOUT, string, (int)arg1, (int)arg2, 0, 0, 0, 0);\
-}while(0);
-
-#define IX_QMGR_LOG_ERROR0(string) do\
-{\
-    ixOsalLog(IX_OSAL_LOG_LVL_ERROR, IX_OSAL_LOG_DEV_STDERR, string, 0, 0, 0, 0, 0, 0);\
-}while(0);
-
-#define IX_QMGR_LOG_ERROR1(string, arg1) do\
-{\
-    ixOsalLog(IX_OSAL_LOG_LVL_ERROR, IX_OSAL_LOG_DEV_STDERR, string, (int)arg1, 0, 0, 0, 0, 0);\
-}while(0);
-
-#define IX_QMGR_LOG_ERROR2(string, arg1, arg2) do\
-{\
-    ixOsalLog(IX_OSAL_LOG_LVL_ERROR, IX_OSAL_LOG_DEV_STDERR, string, (int)arg1, (int)arg2, 0, 0, 0, 0);\
-}while(0);
-
-#define IX_QMGR_LOG_ERROR3(string, arg1, arg2, arg3) do\
-{\
-    ixOsalLog(IX_OSAL_LOG_LVL_ERROR, IX_OSAL_LOG_DEV_STDERR, string, (int)arg1, (int)arg2, (int)arg3, 0, 0, 0);\
-}while(0);
-#endif /* IX_QMGRLOG_P_H */
-
-
-
-
diff --git a/arch/arm/cpu/ixp/npe/include/IxQMgrQAccess_p.h b/arch/arm/cpu/ixp/npe/include/IxQMgrQAccess_p.h
deleted file mode 100644
index 8612670..0000000
--- a/arch/arm/cpu/ixp/npe/include/IxQMgrQAccess_p.h
+++ /dev/null
@@ -1,96 +0,0 @@
-/**
- * @file    IxQMgrQAccess_p.h
- *
- * @author Intel Corporation
- * @date    30-Oct-2001
- *
- * @brief   QAccess private header file
- *
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- * 
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- * 
- * @par
- * -- End of Copyright Notice --
-*/
-
-#ifndef IXQMGRQACCESS_P_H
-#define IXQMGRQACCESS_P_H
-
-/*
- * User defined header files
- */
-#include "IxQMgr.h"
-
-/* 
- * Global variables declarations.
- */
-extern volatile UINT32 * ixQMgrAqmIfQueAccRegAddr[]; 
-
-/* 
- * Initialise the Queue Access component
- */
-void
-ixQMgrQAccessInit (void);
-
-/*
- * read the remainder of a multi-word queue entry 
- * (the first word is already read)
- */
-IX_STATUS
-ixQMgrQReadMWordsMinus1 (IxQMgrQId qId,
-                         UINT32 *entry);
-
-/*
- * Fast access : pop a q entry from a single word queue
- */
-extern __inline__ UINT32 ixQMgrQAccessPop(IxQMgrQId qId);
-
-extern __inline__ UINT32 ixQMgrQAccessPop(IxQMgrQId qId)
-{
-  return *(ixQMgrAqmIfQueAccRegAddr[qId]);
-}
-
-/*
- * Fast access : push a q entry in a single word queue
- */
-extern __inline__ void ixQMgrQAccessPush(IxQMgrQId qId, UINT32 entry);
-
-extern __inline__ void ixQMgrQAccessPush(IxQMgrQId qId, UINT32 entry)
-{
-  *(ixQMgrAqmIfQueAccRegAddr[qId]) = entry;
-}
-
-#endif/*IXQMGRQACCESS_P_H*/
diff --git a/arch/arm/cpu/ixp/npe/include/IxQMgrQCfg_p.h b/arch/arm/cpu/ixp/npe/include/IxQMgrQCfg_p.h
deleted file mode 100644
index c9dae1e..0000000
--- a/arch/arm/cpu/ixp/npe/include/IxQMgrQCfg_p.h
+++ /dev/null
@@ -1,122 +0,0 @@
-/**
- * @file    IxQMgrQCfg_p.h
- *
- * @author Intel Corporation
- * @date    07-Feb-2002
- *
- * @brief   This file contains the internal functions for config
- *
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- * 
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- * 
- * @par
- * -- End of Copyright Notice --
-*/
-
-#ifndef IXQMGRQCFG_P_H
-#define IXQMGRQCFG_P_H
-
-/*
- * User defined header files
- */
-#include "IxQMgr.h"
-
-/*
- * Typedefs
- */
-typedef struct
-{
-    unsigned wmSetCnt;    
-
-    struct
-    {
-	char *qName;
-	BOOL isConfigured;	
-	unsigned int qSizeInWords;
-	unsigned int qEntrySizeInWords;
-	unsigned int ne;
-	unsigned int nf;
-	unsigned int numEntries;
-	UINT32 baseAddress;
-	UINT32 readPtr;
-	UINT32 writePtr;
-    } qStats[IX_QMGR_MAX_NUM_QUEUES];
-
-} IxQMgrQCfgStats;
-
-/*
- * Initialize the QCfg subcomponent
- */ 
-void
-ixQMgrQCfgInit (void);
-
-/*
- * Uninitialize the QCfg subcomponent
- */ 
-void
-ixQMgrQCfgUninit (void);
-
-/*
- * Get the Q size in words
- */ 
-IxQMgrQSizeInWords
-ixQMgrQSizeInWordsGet (IxQMgrQId qId);
-
-/*
- * Get the Q entry size in words
- */ 
-IxQMgrQEntrySizeInWords
-ixQMgrQEntrySizeInWordsGet (IxQMgrQId qId);
-
-/*
- * Get the generic cfg stats
- */
-IxQMgrQCfgStats*
-ixQMgrQCfgStatsGet (void);
-
-/*
- * Get queue specific stats
- */
-IxQMgrQCfgStats*
-ixQMgrQCfgQStatsGet (IxQMgrQId qId);
-
-/*
- * Check is the queue configured
- */
-BOOL
-ixQMgrQIsConfigured(IxQMgrQId qId);
- 
-#endif /* IX_QMGRQCFG_P_H */
diff --git a/arch/arm/cpu/ixp/npe/include/IxQueueAssignments.h b/arch/arm/cpu/ixp/npe/include/IxQueueAssignments.h
deleted file mode 100644
index f7194e7..0000000
--- a/arch/arm/cpu/ixp/npe/include/IxQueueAssignments.h
+++ /dev/null
@@ -1,516 +0,0 @@
-/**
- * @file IxQueueAssignments.h
- *
- * @author Intel Corporation
- * @date 29-Oct-2004
- *
- * @brief Central definition for queue assignments
- *
- * Design Notes:
- * This file contains queue assignments used by Ethernet (EthAcc),
- * HSS (HssAcc), ATM (atmdAcc) and DMA (dmaAcc) access libraries.
- *
- * Note: Ethernet QoS traffic class definitions are managed separately
- * by EthDB in IxEthDBQoS.h.
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- * 
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- * 
- * @par
- * -- End of Copyright Notice --
- */
-
-#ifndef IxQueueAssignments_H
-#define IxQueueAssignments_H
-
-#include "IxQMgr.h"
-
-/***************************************************************************
- *  Queue assignments for ATM
- ***************************************************************************/
-
-/** 
- * @brief Global compiler switch to select between 3 possible NPE Modes
- * Define this macro to enable MPHY mode
- *
- * Default(No Switch) = MultiPHY Utopia2
- * IX_UTOPIAMODE = 1 for single Phy Utopia1
- * IX_MPHYSINGLEPORT = 1 for single Phy Utopia2 
- */
-#define IX_NPE_MPHYMULTIPORT 1
-#if IX_UTOPIAMODE == 1
-#undef  IX_NPE_MPHYMULTIPORT
-#endif
-#if IX_MPHYSINGLEPORT == 1
-#undef  IX_NPE_MPHYMULTIPORT
-#endif
-
-/**
- * @def IX_NPE_A_TXDONE_QUEUE_HIGHWATERMARK
- *
- * @brief The NPE reserves the High Watermark for its operation. But it must be set by the Xscale
- */
-#define IX_NPE_A_TXDONE_QUEUE_HIGHWATERMARK  2
-
-/**
- * @def IX_NPE_A_QMQ_ATM_TX_DONE
- *
- * @brief Queue ID for ATM Transmit Done queue
- */
-#define IX_NPE_A_QMQ_ATM_TX_DONE       IX_QMGR_QUEUE_1
-
-/**
- * @def IX_NPE_A_QMQ_ATM_TX0
- *
- * @brief Queue ID for ATM transmit Queue in a single phy configuration
- */
-#define IX_NPE_A_QMQ_ATM_TX0           IX_QMGR_QUEUE_2
-
-
-/**
- * @def IX_NPE_A_QMQ_ATM_TXID_MIN
- *
- * @brief Queue Manager Queue ID for ATM transmit Queue with minimum number of queue
- *
- */
-
-/**
- * @def IX_NPE_A_QMQ_ATM_TXID_MAX
- *
- * @brief Queue Manager Queue ID for ATM transmit Queue with maximum number of queue
- *
- */
-
-/**
- * @def IX_NPE_A_QMQ_ATM_RX_HI
- *
- * @brief Queue Manager Queue ID for ATM Receive high Queue
- *
- */
-
-/**
- * @def IX_NPE_A_QMQ_ATM_RX_LO
- *
- * @brief Queue Manager Queue ID for ATM Receive low Queue
- */
-
-#ifdef IX_NPE_MPHYMULTIPORT
-/**
- * @def IX_NPE_A_QMQ_ATM_TX1
- *
- * @brief Queue ID for ATM transmit Queue Multiphy from 1 to 11
- */
-#define IX_NPE_A_QMQ_ATM_TX1           IX_NPE_A_QMQ_ATM_TX0+1
-#define IX_NPE_A_QMQ_ATM_TX2           IX_NPE_A_QMQ_ATM_TX1+1
-#define IX_NPE_A_QMQ_ATM_TX3           IX_NPE_A_QMQ_ATM_TX2+1
-#define IX_NPE_A_QMQ_ATM_TX4           IX_NPE_A_QMQ_ATM_TX3+1
-#define IX_NPE_A_QMQ_ATM_TX5           IX_NPE_A_QMQ_ATM_TX4+1
-#define IX_NPE_A_QMQ_ATM_TX6           IX_NPE_A_QMQ_ATM_TX5+1
-#define IX_NPE_A_QMQ_ATM_TX7           IX_NPE_A_QMQ_ATM_TX6+1
-#define IX_NPE_A_QMQ_ATM_TX8           IX_NPE_A_QMQ_ATM_TX7+1
-#define IX_NPE_A_QMQ_ATM_TX9           IX_NPE_A_QMQ_ATM_TX8+1
-#define IX_NPE_A_QMQ_ATM_TX10          IX_NPE_A_QMQ_ATM_TX9+1
-#define IX_NPE_A_QMQ_ATM_TX11          IX_NPE_A_QMQ_ATM_TX10+1
-#define IX_NPE_A_QMQ_ATM_TXID_MIN      IX_NPE_A_QMQ_ATM_TX0
-#define IX_NPE_A_QMQ_ATM_TXID_MAX      IX_NPE_A_QMQ_ATM_TX11
-#define IX_NPE_A_QMQ_ATM_RX_HI         IX_QMGR_QUEUE_21
-#define IX_NPE_A_QMQ_ATM_RX_LO         IX_QMGR_QUEUE_22
-#else
-#define IX_NPE_A_QMQ_ATM_TXID_MIN      IX_NPE_A_QMQ_ATM_TX0
-#define IX_NPE_A_QMQ_ATM_TXID_MAX      IX_NPE_A_QMQ_ATM_TX0
-#define IX_NPE_A_QMQ_ATM_RX_HI         IX_QMGR_QUEUE_10
-#define IX_NPE_A_QMQ_ATM_RX_LO         IX_QMGR_QUEUE_11
-#endif /* MPHY */
-
-/**
- * @def IX_NPE_A_QMQ_ATM_FREE_VC0
- *
- * @brief Hardware QMgr Queue ID for ATM Free VC Queue.
- *
- * There are 32 Hardware QMgr Queue ID; from IX_NPE_A_QMQ_ATM_FREE_VC1 to
- * IX_NPE_A_QMQ_ATM_FREE_VC30
- */
-#define IX_NPE_A_QMQ_ATM_FREE_VC0      IX_QMGR_QUEUE_32
-#define IX_NPE_A_QMQ_ATM_FREE_VC1      IX_NPE_A_QMQ_ATM_FREE_VC0+1
-#define IX_NPE_A_QMQ_ATM_FREE_VC2      IX_NPE_A_QMQ_ATM_FREE_VC1+1
-#define IX_NPE_A_QMQ_ATM_FREE_VC3      IX_NPE_A_QMQ_ATM_FREE_VC2+1
-#define IX_NPE_A_QMQ_ATM_FREE_VC4      IX_NPE_A_QMQ_ATM_FREE_VC3+1
-#define IX_NPE_A_QMQ_ATM_FREE_VC5      IX_NPE_A_QMQ_ATM_FREE_VC4+1
-#define IX_NPE_A_QMQ_ATM_FREE_VC6      IX_NPE_A_QMQ_ATM_FREE_VC5+1
-#define IX_NPE_A_QMQ_ATM_FREE_VC7      IX_NPE_A_QMQ_ATM_FREE_VC6+1
-#define IX_NPE_A_QMQ_ATM_FREE_VC8      IX_NPE_A_QMQ_ATM_FREE_VC7+1
-#define IX_NPE_A_QMQ_ATM_FREE_VC9      IX_NPE_A_QMQ_ATM_FREE_VC8+1
-#define IX_NPE_A_QMQ_ATM_FREE_VC10     IX_NPE_A_QMQ_ATM_FREE_VC9+1
-#define IX_NPE_A_QMQ_ATM_FREE_VC11     IX_NPE_A_QMQ_ATM_FREE_VC10+1
-#define IX_NPE_A_QMQ_ATM_FREE_VC12     IX_NPE_A_QMQ_ATM_FREE_VC11+1
-#define IX_NPE_A_QMQ_ATM_FREE_VC13     IX_NPE_A_QMQ_ATM_FREE_VC12+1
-#define IX_NPE_A_QMQ_ATM_FREE_VC14     IX_NPE_A_QMQ_ATM_FREE_VC13+1
-#define IX_NPE_A_QMQ_ATM_FREE_VC15     IX_NPE_A_QMQ_ATM_FREE_VC14+1
-#define IX_NPE_A_QMQ_ATM_FREE_VC16     IX_NPE_A_QMQ_ATM_FREE_VC15+1
-#define IX_NPE_A_QMQ_ATM_FREE_VC17     IX_NPE_A_QMQ_ATM_FREE_VC16+1
-#define IX_NPE_A_QMQ_ATM_FREE_VC18     IX_NPE_A_QMQ_ATM_FREE_VC17+1
-#define IX_NPE_A_QMQ_ATM_FREE_VC19     IX_NPE_A_QMQ_ATM_FREE_VC18+1
-#define IX_NPE_A_QMQ_ATM_FREE_VC20     IX_NPE_A_QMQ_ATM_FREE_VC19+1
-#define IX_NPE_A_QMQ_ATM_FREE_VC21     IX_NPE_A_QMQ_ATM_FREE_VC20+1
-#define IX_NPE_A_QMQ_ATM_FREE_VC22     IX_NPE_A_QMQ_ATM_FREE_VC21+1
-#define IX_NPE_A_QMQ_ATM_FREE_VC23     IX_NPE_A_QMQ_ATM_FREE_VC22+1
-#define IX_NPE_A_QMQ_ATM_FREE_VC24     IX_NPE_A_QMQ_ATM_FREE_VC23+1
-#define IX_NPE_A_QMQ_ATM_FREE_VC25     IX_NPE_A_QMQ_ATM_FREE_VC24+1
-#define IX_NPE_A_QMQ_ATM_FREE_VC26     IX_NPE_A_QMQ_ATM_FREE_VC25+1
-#define IX_NPE_A_QMQ_ATM_FREE_VC27     IX_NPE_A_QMQ_ATM_FREE_VC26+1
-#define IX_NPE_A_QMQ_ATM_FREE_VC28     IX_NPE_A_QMQ_ATM_FREE_VC27+1
-#define IX_NPE_A_QMQ_ATM_FREE_VC29     IX_NPE_A_QMQ_ATM_FREE_VC28+1
-#define IX_NPE_A_QMQ_ATM_FREE_VC30     IX_NPE_A_QMQ_ATM_FREE_VC29+1
-#define IX_NPE_A_QMQ_ATM_FREE_VC31     IX_NPE_A_QMQ_ATM_FREE_VC30+1
-
-/**
- * @def IX_NPE_A_QMQ_ATM_RXFREE_MIN
- *
- * @brief The minimum queue ID for FreeVC queue
- */
-#define IX_NPE_A_QMQ_ATM_RXFREE_MIN  IX_NPE_A_QMQ_ATM_FREE_VC0
-
-/**
- * @def IX_NPE_A_QMQ_ATM_RXFREE_MAX
- *
- * @brief The maximum queue ID for FreeVC queue
- */
-#define IX_NPE_A_QMQ_ATM_RXFREE_MAX  IX_NPE_A_QMQ_ATM_FREE_VC31
-
-/**
- * @def IX_NPE_A_QMQ_OAM_FREE_VC
- * @brief OAM Rx Free queue ID
- */
-#ifdef IX_NPE_MPHYMULTIPORT
-#define IX_NPE_A_QMQ_OAM_FREE_VC       IX_QMGR_QUEUE_14
-#else
-#define IX_NPE_A_QMQ_OAM_FREE_VC       IX_QMGR_QUEUE_3
-#endif /* MPHY */
-
-/****************************************************************************
- * Queue assignments for HSS
- ****************************************************************************/
-
-/****  HSS Port 0 ****/
-
-/**
- * @def IX_NPE_A_QMQ_HSS0_CHL_RX_TRIG
- *
- * @brief Hardware QMgr Queue ID for HSS Port 0 Channelized Receive trigger
- */
-#define IX_NPE_A_QMQ_HSS0_CHL_RX_TRIG   IX_QMGR_QUEUE_12
-
-/**
- * @def IX_NPE_A_QMQ_HSS0_PKT_RX
- *
- * @brief Hardware QMgr Queue ID for HSS Port 0 Packetized Receive
- */
-#define IX_NPE_A_QMQ_HSS0_PKT_RX        IX_QMGR_QUEUE_13
-
-/**
- * @def IX_NPE_A_QMQ_HSS0_PKT_TX0
- *
- * @brief Hardware QMgr Queue ID for HSS Port 0 Packetized Transmit queue 0
- */
-#define IX_NPE_A_QMQ_HSS0_PKT_TX0       IX_QMGR_QUEUE_14
-
-/**
- * @def IX_NPE_A_QMQ_HSS0_PKT_TX1
- *
- * @brief Hardware QMgr Queue ID for HSS Port 0 Packetized Transmit queue 1
- */
-#define IX_NPE_A_QMQ_HSS0_PKT_TX1       IX_QMGR_QUEUE_15
-
-/**
- * @def IX_NPE_A_QMQ_HSS0_PKT_TX2
- *
- * @brief Hardware QMgr Queue ID for HSS Port 0 Packetized Transmit queue 2
- */
-#define IX_NPE_A_QMQ_HSS0_PKT_TX2       IX_QMGR_QUEUE_16
-
-/**
- * @def IX_NPE_A_QMQ_HSS0_PKT_TX3
- *
- * @brief Hardware QMgr Queue ID for HSS Port 0 Packetized Transmit queue 3
- */
-#define IX_NPE_A_QMQ_HSS0_PKT_TX3       IX_QMGR_QUEUE_17
-
-/**
- * @def IX_NPE_A_QMQ_HSS0_PKT_RX_FREE0
- *
- * @brief Hardware QMgr Queue ID for HSS Port 0 Packetized Receive Free queue 0
- */
-#define IX_NPE_A_QMQ_HSS0_PKT_RX_FREE0  IX_QMGR_QUEUE_18
-
-/**
- * @def IX_NPE_A_QMQ_HSS0_PKT_RX_FREE1
- *
- * @brief Hardware QMgr Queue ID for HSS Port 0 Packetized Receive Free queue 1
- */
-#define IX_NPE_A_QMQ_HSS0_PKT_RX_FREE1  IX_QMGR_QUEUE_19
-
-/**
- * @def IX_NPE_A_QMQ_HSS0_PKT_RX_FREE2
- *
- * @brief Hardware QMgr Queue ID for HSS Port 0 Packetized Receive Free queue 2
- */
-#define IX_NPE_A_QMQ_HSS0_PKT_RX_FREE2  IX_QMGR_QUEUE_20
-
-/**
- * @def IX_NPE_A_QMQ_HSS0_PKT_RX_FREE3
- *
- * @brief Hardware QMgr Queue ID for HSS Port 0 Packetized Receive Free queue 3
- */
-#define IX_NPE_A_QMQ_HSS0_PKT_RX_FREE3  IX_QMGR_QUEUE_21
-
-/**
- * @def IX_NPE_A_QMQ_HSS0_PKT_TX_DONE
- *
- * @brief Hardware QMgr Queue ID for HSS Port 0 Packetized Transmit Done queue
- */
-#define IX_NPE_A_QMQ_HSS0_PKT_TX_DONE   IX_QMGR_QUEUE_22
-
-/****  HSS Port 1 ****/
-
-/**
- * @def IX_NPE_A_QMQ_HSS1_CHL_RX_TRIG
- *
- * @brief Hardware QMgr Queue ID for HSS Port 1 Channelized Receive trigger
- */
-#define IX_NPE_A_QMQ_HSS1_CHL_RX_TRIG   IX_QMGR_QUEUE_10
-
-/**
- * @def IX_NPE_A_QMQ_HSS1_PKT_RX
- *
- * @brief Hardware QMgr Queue ID for HSS Port 1 Packetized Receive
- */
-#define IX_NPE_A_QMQ_HSS1_PKT_RX        IX_QMGR_QUEUE_0
-
-/**
- * @def IX_NPE_A_QMQ_HSS1_PKT_TX0
- *
- * @brief Hardware QMgr Queue ID for HSS Port 1 Packetized Transmit queue 0
- */
-#define IX_NPE_A_QMQ_HSS1_PKT_TX0       IX_QMGR_QUEUE_5
-
-/**
- * @def IX_NPE_A_QMQ_HSS1_PKT_TX1
- *
- * @brief Hardware QMgr Queue ID for HSS Port 1 Packetized Transmit queue 1
- */
-#define IX_NPE_A_QMQ_HSS1_PKT_TX1       IX_QMGR_QUEUE_6
-
-/**
- * @def IX_NPE_A_QMQ_HSS1_PKT_TX2
- *
- * @brief Hardware QMgr Queue ID for HSS Port 1 Packetized Transmit queue 2
- */
-#define IX_NPE_A_QMQ_HSS1_PKT_TX2       IX_QMGR_QUEUE_7
-
-/**
- * @def IX_NPE_A_QMQ_HSS1_PKT_TX3
- *
- * @brief Hardware QMgr Queue ID for HSS Port 1 Packetized Transmit queue 3
- */
-#define IX_NPE_A_QMQ_HSS1_PKT_TX3       IX_QMGR_QUEUE_8
-
-/**
- * @def IX_NPE_A_QMQ_HSS1_PKT_RX_FREE0
- *
- * @brief Hardware QMgr Queue ID for HSS Port 1 Packetized Receive Free queue 0
- */
-#define IX_NPE_A_QMQ_HSS1_PKT_RX_FREE0  IX_QMGR_QUEUE_1
-
-/**
- * @def IX_NPE_A_QMQ_HSS1_PKT_RX_FREE1
- *
- * @brief Hardware QMgr Queue ID for HSS Port 1 Packetized Receive Free queue 1
- */
-#define IX_NPE_A_QMQ_HSS1_PKT_RX_FREE1  IX_QMGR_QUEUE_2
-
-/**
- * @def IX_NPE_A_QMQ_HSS1_PKT_RX_FREE2
- *
- * @brief Hardware QMgr Queue ID for HSS Port 1 Packetized Receive Free queue 2
- */
-#define IX_NPE_A_QMQ_HSS1_PKT_RX_FREE2  IX_QMGR_QUEUE_3
-
-/**
- * @def IX_NPE_A_QMQ_HSS1_PKT_RX_FREE3
- *
- * @brief Hardware QMgr Queue ID for HSS Port 1 Packetized Receive Free queue 3
- */
-#define IX_NPE_A_QMQ_HSS1_PKT_RX_FREE3  IX_QMGR_QUEUE_4
-
-/**
- * @def IX_NPE_A_QMQ_HSS1_PKT_TX_DONE
- *
- * @brief Hardware QMgr Queue ID for HSS Port 1 Packetized Transmit Done queue
- */
-#define IX_NPE_A_QMQ_HSS1_PKT_TX_DONE   IX_QMGR_QUEUE_9
-
-/*****************************************************************************************
- * Queue assignments for DMA
- *****************************************************************************************/
-
-#define IX_DMA_NPE_A_REQUEST_QID IX_QMGR_QUEUE_19   /**< Queue Id for NPE A DMA Request */
-#define IX_DMA_NPE_A_DONE_QID    IX_QMGR_QUEUE_20   /**< Queue Id for NPE A DMA Done    */
-#define IX_DMA_NPE_B_REQUEST_QID IX_QMGR_QUEUE_24   /**< Queue Id for NPE B DMA Request */
-#define IX_DMA_NPE_B_DONE_QID    IX_QMGR_QUEUE_26   /**< Queue Id for NPE B DMA Done    */
-#define IX_DMA_NPE_C_REQUEST_QID IX_QMGR_QUEUE_25   /**< Queue Id for NPE C DMA Request */
-#define IX_DMA_NPE_C_DONE_QID    IX_QMGR_QUEUE_27   /**< Queue Id for NPE C DMA Done    */
-
-
-/*****************************************************************************************
- * Queue assignments for Ethernet
- *
- * Note: Rx queue definitions, which include QoS traffic class definitions
- * are managed by EthDB and declared in IxEthDBQoS.h
- *****************************************************************************************/
-
-/**
-*
-* @def IX_ETH_ACC_RX_FRAME_ETH_Q 
-*
-* @brief  Eth0/Eth1 NPE Frame Recieve Q.
-*
-* @note THIS IS NOT USED - the Rx queues are read from EthDB QoS configuration
-* 
-*/
-#define IX_ETH_ACC_RX_FRAME_ETH_Q	(IX_QMGR_QUEUE_4)
-
-/**
-*
-* @def IX_ETH_ACC_RX_FREE_BUFF_ENET0_Q
-*
-* @brief Supply Rx Buffers Ethernet Q for NPEB - Eth 0 - Port 1
-*
-*/
-#define IX_ETH_ACC_RX_FREE_BUFF_ENET0_Q    (IX_QMGR_QUEUE_27)
-
-/**
-*
-* @def IX_ETH_ACC_RX_FREE_BUFF_ENET1_Q
-*
-* @brief Supply Rx Buffers Ethernet Q for NPEC - Eth 1 - Port 2
-*
-*/
-#define IX_ETH_ACC_RX_FREE_BUFF_ENET1_Q    (IX_QMGR_QUEUE_28)
-
-/**
-*
-* @def IX_ETH_ACC_RX_FREE_BUFF_ENET2_Q
-*
-* @brief Supply Rx Buffers Ethernet Q for NPEA - Eth 2 - Port 3
-*
-*/
-#define IX_ETH_ACC_RX_FREE_BUFF_ENET2_Q    (IX_QMGR_QUEUE_26)
-
-
-/**
-*
-* @def IX_ETH_ACC_TX_FRAME_ENET0_Q
-*
-* @brief Submit frame Q for NPEB Eth 0 - Port 1
-*
-*/
-#define IX_ETH_ACC_TX_FRAME_ENET0_Q    (IX_QMGR_QUEUE_24)
-
-
-/**
-*
-* @def IX_ETH_ACC_TX_FRAME_ENET1_Q
-*
-* @brief Submit frame Q for NPEC Eth 1 - Port 2
-*
-*/
-#define IX_ETH_ACC_TX_FRAME_ENET1_Q    (IX_QMGR_QUEUE_25)
-
-/**
-*
-* @def IX_ETH_ACC_TX_FRAME_ENET2_Q
-*
-* @brief Submit frame Q for NPEA Eth 2 - Port 3
-*
-*/
-#define IX_ETH_ACC_TX_FRAME_ENET2_Q    (IX_QMGR_QUEUE_23)
-
-/**
-*
-* @def IX_ETH_ACC_TX_FRAME_DONE_ETH_Q
-*
-* @brief Transmit complete Q for NPE Eth 0/1, Port 1&2
-*
-*/
-#define IX_ETH_ACC_TX_FRAME_DONE_ETH_Q    (IX_QMGR_QUEUE_31)
-
-/*****************************************************************************************
- * Queue assignments for Crypto
- *****************************************************************************************/
-
-/** Crypto Service Request Queue */
-#define IX_CRYPTO_ACC_CRYPTO_REQ_Q  (IX_QMGR_QUEUE_29)
-
-/** Crypto Service Done Queue */
-#define IX_CRYPTO_ACC_CRYPTO_DONE_Q (IX_QMGR_QUEUE_30)
-
-/** Crypto Req Q CB tag */
-#define IX_CRYPTO_ACC_CRYPTO_REQ_Q_CB_TAG   (0)
-
-/** Crypto Done Q CB tag */
-#define IX_CRYPTO_ACC_CRYPTO_DONE_Q_CB_TAG  (1)
-
-/** WEP Service Request Queue */
-#define IX_CRYPTO_ACC_WEP_REQ_Q  (IX_QMGR_QUEUE_21)
-
-/** WEP Service Done Queue */
-#define IX_CRYPTO_ACC_WEP_DONE_Q (IX_QMGR_QUEUE_22)
-
-/** WEP Req Q CB tag */
-#define IX_CRYPTO_ACC_WEP_REQ_Q_CB_TAG      (2)
-
-/** WEP Done Q CB tag */
-#define IX_CRYPTO_ACC_WEP_DONE_Q_CB_TAG     (3)
-
-/** Number of queues allocate to crypto hardware accelerator services */
-#define IX_CRYPTO_ACC_NUM_OF_CRYPTO_Q       (2)
-
-/** Number of queues allocate to WEP NPE services */
-#define IX_CRYPTO_ACC_NUM_OF_WEP_NPE_Q      (2)
-                                                      
-/** Number of queues allocate to CryptoAcc component */
-#define IX_CRYPTO_ACC_NUM_OF_Q (IX_CRYPTO_ACC_NUM_OF_CRYPTO_Q + IX_CRYPTO_ACC_NUM_OF_WEP_NPE_Q)   
-
-#endif /* IxQueueAssignments_H */
diff --git a/arch/arm/cpu/ixp/npe/include/IxSspAcc.h b/arch/arm/cpu/ixp/npe/include/IxSspAcc.h
deleted file mode 100644
index 35e7abf..0000000
--- a/arch/arm/cpu/ixp/npe/include/IxSspAcc.h
+++ /dev/null
@@ -1,1271 +0,0 @@
-/**
- * @file IxSspAcc.h
- *
- * @brief  Header file for the IXP400 SSP Serial Port Access (IxSspAcc)
- *
- * @version $Revision: 0.1 $
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- * 
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- * 
- * @par
- * -- End of Copyright Notice --
- */
-
-/**
- * @defgroup IxSspAcc IXP400 SSP Serial Port Access (IxSspAcc) API 
- *
- * @brief IXP400 SSP Serial Port Access Public API
- *
- * @{
- */
-#ifndef IXSSPACC_H
-#define IXSSPACC_H
-
-#ifdef __ixp46X
-
-#include "IxOsal.h"
-
-/*
- * Section for enum
- */
-/**
- * @ingroup IxSspAcc
- * 
- * @enum IxSspAccDataSize
- *
- * @brief The data sizes in bits that are supported by the protocol
- */
-typedef enum
-{
-	DATA_SIZE_TOO_SMALL = 0x2,
-	DATA_SIZE_4 = 0x3,
-	DATA_SIZE_5,
-	DATA_SIZE_6,
-	DATA_SIZE_7,
-	DATA_SIZE_8,
-	DATA_SIZE_9,
-	DATA_SIZE_10,
-	DATA_SIZE_11,
-	DATA_SIZE_12,
-	DATA_SIZE_13,
-	DATA_SIZE_14,
-	DATA_SIZE_15,
-	DATA_SIZE_16,
-	DATA_SIZE_TOO_BIG
-} IxSspAccDataSize;
-
-/**
- * @ingroup IxSspAcc
- * 
- * @enum IxSspAccPortStatus
- *
- * @brief The status of the SSP port to be set to enable/disable
- */
-typedef enum
-{
-	SSP_PORT_DISABLE = 0x0,
-	SSP_PORT_ENABLE,
-	INVALID_SSP_PORT_STATUS
-} IxSspAccPortStatus;
-
-/**
- * @ingroup IxSspAcc
- * 
- * @enum IxSspAccFrameFormat
- *
- * @brief The frame format that is to be used - SPI, SSP, or Microwire
- */
-typedef enum
-{
-	SPI_FORMAT = 0x0,
-	SSP_FORMAT,
-	MICROWIRE_FORMAT,
-	INVALID_FORMAT
-} IxSspAccFrameFormat;
-
-/**
- * @ingroup IxSspAcc
- * 
- * @enum IxSspAccClkSource
- *
- * @brief The source to produce the SSP serial clock
- */
-typedef enum
-{
-	ON_CHIP_CLK = 0x0,
-	EXTERNAL_CLK,
-	INVALID_CLK_SOURCE
-} IxSspAccClkSource;
-
-/**
- * @ingroup IxSspAcc
- * 
- * @enum IxSspAccSpiSclkPhase
- *
- * @brief The SPI SCLK Phase: 
- * 0 - SCLK is inactive one cycle at the start of a frame and 1/2 cycle at the
- *		end of a frame.
- * 1 - SCLK is inactive 1/2 cycle at the start of a frame and one cycle at the
- *		end of a frame.
- */
-typedef enum
-{
-	START_ONE_END_HALF = 0x0,
-	START_HALF_END_ONE,
-	INVALID_SPI_PHASE
-} IxSspAccSpiSclkPhase;
-
-/**
- * @ingroup IxSspAcc
- * 
- * @enum IxSspAccSpiSclkPolarity
- *
- * @brief The SPI SCLK Polarity can be set to either low or high.
- */
-typedef enum
-{
-	SPI_POLARITY_LOW = 0x0,
-	SPI_POLARITY_HIGH,
-	INVALID_SPI_POLARITY
-} IxSspAccSpiSclkPolarity;
-
-/**
- * @ingroup IxSspAcc
- * 
- * @enum IxSspAccMicrowireCtlWord
- *
- * @brief The Microwire control word can be either 8 or 16 bit.
- */
-typedef enum
-{
-	MICROWIRE_8_BIT = 0x0,
-	MICROWIRE_16_BIT,
-	INVALID_MICROWIRE_CTL_WORD
-} IxSspAccMicrowireCtlWord;
-
-/**
- * @ingroup IxSspAcc
- * 
- * @enum IxSspAccFifoThreshold
- *
- * @brief The threshold in frames (each frame is defined by IxSspAccDataSize)
- *			that can be set for the FIFO to trigger a threshold exceed when
- *			checking with the ExceedThresholdCheck functions or an interrupt
- *			when it is enabled.
- */
-typedef enum
-{
-	FIFO_TSHLD_1 =	0x0,
-	FIFO_TSHLD_2,
-	FIFO_TSHLD_3,
-	FIFO_TSHLD_4,
-	FIFO_TSHLD_5,
-	FIFO_TSHLD_6,
-	FIFO_TSHLD_7,
-	FIFO_TSHLD_8,
-	FIFO_TSHLD_9,
-	FIFO_TSHLD_10,
-	FIFO_TSHLD_11,
-	FIFO_TSHLD_12,
-	FIFO_TSHLD_13,
-	FIFO_TSHLD_14,
-	FIFO_TSHLD_15,
-	FIFO_TSHLD_16,
-	INVALID_FIFO_TSHLD
-} IxSspAccFifoThreshold;
-
-/**
- * @ingroup IxSspAcc
- * 
- * @enum IX_SSP_STATUS
- *
- * @brief The statuses that can be returned in a SSP Serial Port Access
- */
-typedef enum
-{
-	IX_SSP_SUCCESS = IX_SUCCESS, /**< Success status */
-	IX_SSP_FAIL, /**< Fail status */
-	IX_SSP_RX_FIFO_OVERRUN_HANDLER_MISSING, /**<
-						Rx FIFO Overrun handler is NULL. */
-	IX_SSP_RX_FIFO_HANDLER_MISSING, /**<
-					Rx FIFO threshold hit or above handler is NULL
-					*/
-	IX_SSP_TX_FIFO_HANDLER_MISSING, /**<
-					Tx FIFO threshold hit or below handler is NULL
-					*/
-	IX_SSP_FIFO_NOT_EMPTY_FOR_SETTING_CTL_CMD, /**<
-					Tx FIFO not empty and therefore microwire
-					control command size setting is not allowed.	*/
-	IX_SSP_INVALID_FRAME_FORMAT_ENUM_VALUE, /**<
-					frame format selected is invalid. */
-	IX_SSP_INVALID_DATA_SIZE_ENUM_VALUE, /**<
-					data size selected is invalid. */
-	IX_SSP_INVALID_CLOCK_SOURCE_ENUM_VALUE, /**<
-					source clock selected is invalid. */
-	IX_SSP_INVALID_TX_FIFO_THRESHOLD_ENUM_VALUE, /**<
-					Tx FIFO threshold selected is invalid. */
-	IX_SSP_INVALID_RX_FIFO_THRESHOLD_ENUM_VALUE, /**<
-					Rx FIFO threshold selected is invalid. */
-	IX_SSP_INVALID_SPI_PHASE_ENUM_VALUE, /**<
-					SPI phase selected is invalid. */
-	IX_SSP_INVALID_SPI_POLARITY_ENUM_VALUE, /**<
-					SPI polarity selected is invalid. */
-	IX_SSP_INVALID_MICROWIRE_CTL_CMD_ENUM_VALUE, /**<
-					Microwire control command selected is invalid
-					*/
-	IX_SSP_INT_UNBIND_FAIL, /**< Interrupt unbind fail to unbind SSP
-	                interrupt */
-	IX_SSP_INT_BIND_FAIL, /**< Interrupt bind fail during init */
-	IX_SSP_RX_FIFO_NOT_EMPTY, /**<
-					Rx FIFO not empty while trying to change data
-					size. */
-	IX_SSP_TX_FIFO_NOT_EMPTY, /**<
-					Rx FIFO not empty while trying to change data
-					size or microwire control command size.	*/
-	IX_SSP_POLL_MODE_BLOCKING, /**<
-					poll mode selected blocks interrupt mode from
-					being selected.	*/
-	IX_SSP_TX_FIFO_HIT_BELOW_THRESHOLD, /**<
-					Tx FIFO level hit or below threshold. */
-	IX_SSP_TX_FIFO_EXCEED_THRESHOLD, /**<
-					Tx FIFO level exceeded threshold. */
-	IX_SSP_RX_FIFO_HIT_ABOVE_THRESHOLD, /**<
-					Rx FIFO level hit or exceeded threshold. */
-	IX_SSP_RX_FIFO_BELOW_THRESHOLD, /**<
-					Rx FIFO level below threshold. */
-	IX_SSP_BUSY, /**< SSP is busy. */
-	IX_SSP_IDLE, /**< SSP is idle. */
-	IX_SSP_OVERRUN_OCCURRED, /**<
-					SSP has experienced an overrun. */
-	IX_SSP_NO_OVERRUN, /**<
-					SSP did not experience an overrun. */
-	IX_SSP_NOT_SUPORTED, /**< hardware does not support SSP */
-	IX_SSP_NOT_INIT, /**< SSP Access not intialized */
-	IX_SSP_NULL_POINTER /**< parameter passed in is NULL */
-} IX_SSP_STATUS;
-
-/**
- * @ingroup IxSspAcc
- *
- * @brief SSP Rx FIFO Overrun handler
- *
- * This function is called for the client to handle Rx FIFO Overrun that occurs
- * in the SSP hardware
- */
-typedef void (*RxFIFOOverrunHandler)(void);
-
-/**
- * @ingroup IxSspAcc
- * 
- * @brief SSP Rx FIFO Threshold hit or above handler
- *
- * This function is called for the client to handle Rx FIFO threshold hit or
- * or above that occurs in the SSP hardware
- */
-typedef void (*RxFIFOThresholdHandler)(void);
-
-/**
- * @ingroup IxSspAcc
- * 
- * @brief SSP Tx FIFO Threshold hit or below handler
- *
- * This function is called for the client to handle Tx FIFO threshold hit or
- * or below that occurs in the SSP hardware
- */
-typedef void (*TxFIFOThresholdHandler)(void);
-
-
-/*
- * Section for struct
- */
-/**
- * @ingroup IxSspAcc
- *
- * @brief contains all the variables required to initialize the SSP serial port
- *		hardware.
- * 
- * Structure to be filled and used for calling initialization
- */
-typedef struct
-{
-	IxSspAccFrameFormat FrameFormatSelected;/**<Select between SPI, SSP and
-												Microwire. */
-	IxSspAccDataSize DataSizeSelected;		/**<Select between 4 and 16. */
-	IxSspAccClkSource ClkSourceSelected;	/**<Select clock source to be
-												on-chip or external. */
-	IxSspAccFifoThreshold TxFIFOThresholdSelected;
-											/**<Select Tx FIFO threshold
-												between 1 to 16. */
-	IxSspAccFifoThreshold RxFIFOThresholdSelected;
-											/**<Select Rx FIFO threshold
-												between 1 to 16. */
-	BOOL RxFIFOIntrEnable;					/**<Enable/disable Rx FIFO
-												threshold interrupt. Disabling
-												this interrupt will require
-												the use of the polling function
-												RxFIFOExceedThresholdCheck. */
-	BOOL TxFIFOIntrEnable;					/**<Enable/disable Tx FIFO
-												threshold interrupt. Disabling
-												this interrupt will require
-												the use of the polling function
-												TxFIFOExceedThresholdCheck. */
-	RxFIFOThresholdHandler RxFIFOThsldHdlr;	/**<Pointer to function to handle
-												a Rx FIFO interrupt. */
-	TxFIFOThresholdHandler TxFIFOThsldHdlr;	/**<Pointer to function to handle
-												a Tx FIFO interrupt. */
-	RxFIFOOverrunHandler RxFIFOOverrunHdlr;	/**<Pointer to function to handle
-												a Rx FIFO overrun interrupt. */
-	BOOL LoopbackEnable;					/**<Select operation mode to be
-												normal or loopback mode. */
-	IxSspAccSpiSclkPhase SpiSclkPhaseSelected;
-											/**<Select SPI SCLK phase to start
-												with one inactive cycle and end
-												with 1/2 inactive cycle or
-												start with 1/2 inactive cycle
-												and end with one inactive
-												cycle. (Only used in
-												SPI format). */
-	IxSspAccSpiSclkPolarity SpiSclkPolaritySelected;
-											/**<Select SPI SCLK idle state
-												to be low or high. (Only used in
-												SPI format). */
-	IxSspAccMicrowireCtlWord MicrowireCtlWordSelected;
-											/**<Select Microwire control
-												format to be 8 or 16-bit. (Only
-												used in Microwire format). */
-	UINT8 SerialClkRateSelected;			/**<Select between 0 (1.8432Mbps)
-												and 255 (7.2Kbps). The
-												formula used is	Bit rate = 
-												3.6864x10^6 / 
-												(2 x (SerialClkRateSelect + 1))
-												*/
-} IxSspInitVars;
-
-/**
- * @ingroup IxSspAcc
- *
- * @brief contains counters of the SSP statistics
- * 
- * Structure contains all values of counters and associated overflows.
- */
-typedef struct
-{
-	UINT32 ixSspRcvCounter;		/**<Total frames received. */
-	UINT32 ixSspXmitCounter;	/**<Total frames transmitted. */
-	UINT32 ixSspOverflowCounter;/**<Total occurrences of overflow. */
-} IxSspAccStatsCounters;
-
-
-/*
- * Section for prototypes interface functions
- */
-
-/**
- * @ingroup IxSspAcc
- * 
- * @fn ixSspAccInit (
-	IxSspInitVars *initVarsSelected);
- *
- * @brief Initializes the SSP Access module.
- *
- * @param "IxSspAccInitVars [in] *initVarsSelected" - struct containing required
- *			variables for initialization 
- *
- * Global Data	:
- *		- None.
- *                        
- * This API will initialize the SSP Serial Port hardware to the user specified
- * configuration. Then it will enable the SSP Serial Port.
- * *NOTE*: Once interrupt or polling mode is selected, the mode cannot be
- * changed via the interrupt enable/disable function but the init needs to be
- * called again to change it.
- *
- * @return 
- *      - IX_SSP_SUCCESS - Successfully initialize and enable the SSP
- *									serial port.
- *		- IX_SSP_RX_FIFO_HANDLER_MISSING - interrupt mode is selected but RX FIFO
- *									handler pointer is NULL
- *		- IX_SSP_TX_FIFO_HANDLER_MISSING - interrupt mode is selected but TX FIFO
- *									handler pointer is NULL
- *		- IX_SSP_RX_FIFO_OVERRUN_HANDLER_MISSING - interrupt mode is selected but
- *									RX FIFO Overrun handler pointer is NULL
- *		- IX_SSP_RX_FIFO_NOT_EMPTY - Rx FIFO not empty, data size change is not
- *			                        allowed.
- *		- IX_SSP_TX_FIFO_NOT_EMPTY - Tx FIFO not empty, data size change is not
- *			                        allowed.
- *		- IX_SSP_INVALID_FRAME_FORMAT_ENUM_VALUE - frame format selected is invalid
- *		- IX_SSP_INVALID_DATA_SIZE_ENUM_VALUE - data size selected is invalid
- *		- IX_SSP_INVALID_CLOCK_SOURCE_ENUM_VALUE - clock source selected is invalid
- *		- IX_SSP_INVALID_TX_FIFO_THRESHOLD_ENUM_VALUE - Tx FIFO threshold level
- *									selected is invalid
- *		- IX_SSP_INVALID_RX_FIFO_THRESHOLD_ENUM_VALUE - Rx FIFO threshold level
- *									selected is invalid
- *		- IX_SSP_INVALID_SPI_PHASE_ENUM_VALUE - SPI phase selected is invalid
- *		- IX_SSP_INVALID_SPI_POLARITY_ENUM_VALUE - SPI polarity selected is invalid
- *		- IX_SSP_INVALID_MICROWIRE_CTL_CMD_ENUM_VALUE - microwire control command
- *									size is invalid
- *      - IX_SSP_INT_UNBIND_FAIL - interrupt handler failed to unbind SSP interrupt
- *		- IX_SSP_INT_BIND_FAIL - interrupt handler failed to bind to SSP interrupt
- *									hardware trigger
- *      - IX_SSP_NOT_SUPORTED - hardware does not support SSP
- *      - IX_SSP_NULL_POINTER - parameter passed in is NULL
- *              
- * @li   Reentrant    : yes
- * @li   ISR Callable : yes
- *
- */
-PUBLIC IX_SSP_STATUS
-ixSspAccInit (IxSspInitVars *initVarsSelected);
-
-/**
- * @ingroup IxSspAcc
- * 
- * @fn ixSspAccUninit (
-	void)
- *
- * @brief Un-initializes the SSP Serial Port Access component
- *
- * @param - None
- *
- * Global Data	:
- *		- None.
- *                        
- * This API will disable the SSP Serial Port hardware. The client can call the
- * init function again if they wish to enable the SSP.
- *
- * @return 
- *      - IX_SSP_SUCCESS - successfully uninit SSP component
- *      - IX_SSP_INT_UNBIND_FAIL - interrupt handler failed to unbind SSP interrupt
- *              
- * @li   Reentrant    : yes
- * @li   ISR Callable : yes
- *
- */
-PUBLIC IX_SSP_STATUS
-ixSspAccUninit (void);
-
-/**
- * @ingroup IxSspAcc
- * 
- * @fn ixSspAccFIFODataSubmit (
-	UINT16 *data,
-	UINT32 amtOfData)
- *
- * @brief Inserts data into the SSP Serial Port's FIFO
- *
- * @param	"UINT16 [in] *data" - pointer to the location to transmit the data
- *				from
- *			"UINT32 [in] amtOfData" - number of data to be transmitted.
- *
- * Global Data	:
- *		- None.
- *                        
- * This API will insert the amount of data specified by "amtOfData" from buffer
- * pointed to by "data" into the FIFO to be transmitted by the hardware.
- *
- * @return 
- *      - IX_SSP_SUCCESS - Data inserted successfully into FIFO
- *		- IX_SSP_FAIL - FIFO insufficient space
- *		- IX_SSP_NULL_POINTER - data pointer passed by client is NULL
- *		- IX_SSP_NOT_INIT - SSP not initialized. SSP init needs to be called.
- *              
- * @li   Reentrant    : yes
- * @li   ISR Callable : yes
- *
- */
-PUBLIC IX_SSP_STATUS
-ixSspAccFIFODataSubmit (
-	UINT16* data,
-	UINT32 amtOfData);
-
-/**
- * @ingroup IxSspAcc
- * 
- * @fn ixSspAccFIFODataReceive (
-	UINT16 *data,
-	UINT32 amtOfData)
- *
- * @brief Extract data from the SSP Serial Port's FIFO
- *
- * @param	"UINT16 [in] *data" - pointer to the location to receive the data into
- *			"UINT32 [in] amtOfData" - number of data to be received.
- *
- * Global Data	:
- *		- None.
- *                        
- * This API will extract the amount of data specified by "amtOfData" from the
- * FIFO already received by the hardware into the buffer pointed to by "data".
- *
- * @return 
- *      - IX_SSP_SUCCESS - Data extracted successfully from FIFO
- *		- IX_SSP_FAIL - FIFO has no data
- *		- IX_SSP_NULL_POINTER - data pointer passed by client is NULL
- *		- IX_SSP_NOT_INIT - SSP not initialized. SSP init needs to be called.
- *              
- * @li   Reentrant    : yes
- * @li   ISR Callable : yes
- *
- */
-PUBLIC IX_SSP_STATUS
-ixSspAccFIFODataReceive (
-	UINT16* data,
-	UINT32 amtOfData);
-
-
-/**
- * Polling Functions
- */
-
-/**
- * @ingroup IxSspAcc
- * 
- * @fn ixSspAccTxFIFOHitOrBelowThresholdCheck (
-		void)
- *
- * @brief Check if the Tx FIFO threshold has been hit or fallen below.
- *
- * @param - None
- *
- * Global Data	:
- *		- None.
- *                        
- * This API will return whether the Tx FIFO threshold has been exceeded or not
- *
- * @return 
- *      - IX_SSP_TX_FIFO_HIT_BELOW_THRESHOLD - Tx FIFO level hit or below threshold .
- *		- IX_SSP_TX_FIFO_EXCEED_THRESHOLD - Tx FIFO level exceeded threshold.
- *		- IX_SSP_NOT_INIT - SSP not initialized. SSP init needs to be called.
- *              
- * @li   Reentrant    : yes
- * @li   ISR Callable : yes
- *
- */
-PUBLIC IX_SSP_STATUS
-ixSspAccTxFIFOHitOrBelowThresholdCheck (
-	void);
-
-/**
- * @ingroup IxSspAcc
- * 
- * @fn ixSspAccRxFIFOHitOrAboveThresholdCheck (
-		void)
- *
- * @brief Check if the Rx FIFO threshold has been hit or exceeded.
- *
- * @param - None
- *
- * Global Data	:
- *		- None.
- *                        
- * This API will return whether the Rx FIFO level is below threshold or not
- *
- * @return 
- *      - IX_SSP_RX_FIFO_HIT_ABOVE_THRESHOLD - Rx FIFO level hit or exceeded threshold
- *		- IX_SSP_RX_FIFO_BELOW_THRESHOLD - Rx FIFO level below threshold
- *		- IX_SSP_NOT_INIT - SSP not initialized. SSP init needs to be called.
- *              
- * @li   Reentrant    : yes
- * @li   ISR Callable : yes
- *
- */
-PUBLIC IX_SSP_STATUS
-ixSspAccRxFIFOHitOrAboveThresholdCheck (
-	void);
-
-
-/**
- * Configuration functions
- *
- * NOTE: These configurations are not required to be called once init is called
- * unless configurations need to be changed on the fly.
- */
-
-/**
- * @ingroup IxSspAcc
- * 
- * @fn ixSspAccSSPPortStatusSet (
-	IxSspAccPortStatus portStatusSelected)
- *
- * @brief Enables/disables the SSP Serial Port hardware.
- *
- * @param "IxSspAccPortStatus [in] portStatusSelected" - Set the SSP port to
- *			enable or disable
- *
- * Global Data	:
- *		- None.
- *                        
- * This API will enable/disable the SSP Serial Port hardware.
- * NOTE: This function is called by init to enable the SSP after setting up the
- * configurations and by uninit to disable the SSP.
- *
- * @return 
- *      - IX_SSP_SUCCESS - Port status set with valid enum value
- *		- IX_SSP_FAIL - invalid enum value
- *		- IX_SSP_NOT_INIT - SSP not initialized. SSP init needs to be called.
- *              
- * @li   Reentrant    : yes
- * @li   ISR Callable : yes
- *
- */
-PUBLIC IX_SSP_STATUS
-ixSspAccSSPPortStatusSet (
-	IxSspAccPortStatus portStatusSelected);
-
-/**
- * @ingroup IxSspAcc
- * 
- * @fn ixSspAccFrameFormatSelect (
-	IxSspAccFrameFormat frameFormatSelected)
- *
- * @brief Sets the frame format for the SSP Serial Port hardware
- *
- * @param "IxSspAccFrameFormat [in] frameFormatSelected" - The frame format of
- *			SPI, SSP or Microwire can be selected as the format
- *
- * Global Data	:
- *		- None.
- *                        
- * This API will set the format for the transfers via user input.
- * *NOTE*: The SSP hardware will be disabled to clear the FIFOs. Then its
- * previous state (enabled/disabled) restored after changing the format.
- *
- * @return 
- *      - IX_SSP_SUCCESS - frame format set with valid enum value
- *		- IX_SSP_INVALID_FRAME_FORMAT_ENUM_VALUE - invalid frame format value
- *		- IX_SSP_NOT_INIT - SSP not initialized. SSP init needs to be called.
- *              
- * @li   Reentrant    : yes
- * @li   ISR Callable : yes
- *
- */
-PUBLIC IX_SSP_STATUS
-ixSspAccFrameFormatSelect (
-	IxSspAccFrameFormat frameFormatSelected);
-
-/**
- * @ingroup IxSspAcc
- * 
- * @fn ixSspAccDataSizeSelect (
-	IxSspAccDataSize dataSizeSelected)
- *
- * @brief Sets the data size for transfers
- *
- * @param "IxSspAccDataSize [in] dataSizeSelected" - The data size between 4
- *			and 16 that can be selected for data transfers
- *
- * Global Data	:
- *		- None.
- *                        
- * This API will set the data size for the transfers via user input. It will
- * disallow the change of the data size if either of the Rx/Tx FIFO is not
- * empty to prevent data loss.
- * *NOTE*: The SSP port will be disabled if the FIFOs are found to be empty and
- *			if between the check and disabling of the SSP (which clears the
- *			FIFOs) data is received into the FIFO, it might be lost.
- * *NOTE*: The FIFOs can be cleared by disabling the SSP Port if necessary to
- *			force the data size change.
- *
- * @return 
- *      - IX_SSP_SUCCESS - data size set with valid enum value
- *		- IX_SSP_RX_FIFO_NOT_EMPTY - Rx FIFO not empty, data size change is not
- *							allowed.
- *		- IX_SSP_TX_FIFO_NOT_EMPTY - Tx FIFO not empty, data size change is not
- *							allowed.
- *		- IX_SSP_INVALID_DATA_SIZE_ENUM_VALUE - invalid enum value
- *		- IX_SSP_NOT_INIT - SSP not initialized. SSP init needs to be called.
- *              
- * @li   Reentrant    : yes
- * @li   ISR Callable : yes
- *
- */
-PUBLIC IX_SSP_STATUS
-ixSspAccDataSizeSelect (
-	IxSspAccDataSize dataSizeSelected);
-
-/**
- * @ingroup IxSspAcc
- * 
- * @fn ixSspAccClockSourceSelect(
-	IxSspAccClkSource clkSourceSelected)
- *
- * @brief Sets the clock source of the SSP Serial Port hardware
- *
- * @param "IxSspAccClkSource [in] clkSourceSelected" - The clock source from
- *			either external source on on-chip can be selected as the source
- *
- * Global Data	:
- *		- None.
- *                        
- * This API will set the clock source for the transfers via user input.
- *
- * @return 
- *      - IX_SSP_SUCCESS - clock source set with valid enum value
- *		- IX_SSP_INVALID_CLOCK_SOURCE_ENUM_VALUE - invalid enum value
- *		- IX_SSP_NOT_INIT - SSP not initialized. SSP init needs to be called.
- *              
- * @li   Reentrant    : yes
- * @li   ISR Callable : yes
- *
- */
-PUBLIC IX_SSP_STATUS
-ixSspAccClockSourceSelect (
-	IxSspAccClkSource clkSourceSelected);
-
-/**
- * @ingroup IxSspAcc
- * 
- * @fn ixSspAccSerialClockRateConfigure (
-	UINT8 serialClockRateSelected)
- *
- * @brief Sets the on-chip Serial Clock Rate of the SSP Serial Port hardware.
- *
- * @param "UINT8 [in] serialClockRateSelected" - The serial clock rate that can
- *			be set is between 7.2Kbps and 1.8432Mbps. The formula used is
- *			Bit rate = 3.6864x10^6 / (2 x (SerialClockRateSelected + 1))
- *
- * Global Data	:
- *		- None.
- *                        
- * This API will set the serial clock rate for the transfers via user input.
- *
- * @return 
- *      - IX_SSP_SUCCESS - Serial clock rate configured successfully
- *		- IX_SSP_NOT_INIT - SSP not initialized. SSP init needs to be called.
- *              
- * @li   Reentrant    : yes
- * @li   ISR Callable : yes
- *
- */
-PUBLIC IX_SSP_STATUS
-ixSspAccSerialClockRateConfigure (
-	UINT8 serialClockRateSelected);
-
-/**
- * @ingroup IxSspAcc
- * 
- * @fn ixSspAccRxFIFOIntEnable (
-	RxFIFOThresholdHandler rxFIFOIntrHandler)
- *
- * @brief Enables service request interrupt whenever the Rx FIFO hits its
- *		threshold
- *
- * @param "void [in] *rxFIFOIntrHandler(UINT32)" - function pointer to the
- *				interrupt handler for the Rx FIFO exceeded.
- *
- * Global Data	:
- *		- None.
- *                        
- * This API will enable the service request interrupt for the Rx FIFO
- *
- * @return 
- *      - IX_SSP_SUCCESS - Rx FIFO level interrupt enabled successfully
- *		- IX_SSP_RX_FIFO_HANDLER_MISSING - missing handler for Rx FIFO level interrupt
- *		- IX_SSP_POLL_MODE_BLOCKING - poll mode is selected at init, interrupt not
- *				allowed to be enabled. Use init to enable interrupt mode.
- *		- IX_SSP_NOT_INIT - SSP not initialized. SSP init needs to be called.
- *              
- * @li   Reentrant    : yes
- * @li   ISR Callable : yes
- *
- */
-PUBLIC IX_SSP_STATUS
-ixSspAccRxFIFOIntEnable (
-	RxFIFOThresholdHandler rxFIFOIntrHandler);
-
-/**
- * @ingroup IxSspAcc
- * 
- * @fn ixSspAccRxFIFOIntDisable (
-	void)
- *
- * @brief Disables service request interrupt of the Rx FIFO.
- *
- * @param - None
- *
- * Global Data	:
- *		- None.
- *                        
- * This API will disable the service request interrupt of the Rx FIFO.
- *
- * @return 
- *		- IX_SSP_SUCCESS - Rx FIFO Interrupt disabled successfully
- *		- IX_SSP_NOT_INIT - SSP not initialized. SSP init needs to be called.
- *              
- * @li   Reentrant    : yes
- * @li   ISR Callable : yes
- *
- */
-PUBLIC IX_SSP_STATUS
-ixSspAccRxFIFOIntDisable (
-	void);
-
-/**
- * @ingroup IxSspAcc
- * 
- * @fn ixSspAccTxFIFOIntEnable (
-	TxFIFOThresholdHandler txFIFOIntrHandler)
- *
- * @brief Enables service request interrupt of the Tx FIFO.
- *
- * @param "void [in] *txFIFOIntrHandler(UINT32)" - function pointer to the
- *				interrupt handler for the Tx FIFO exceeded.
- *
- * Global Data	:
- *		- None.
- *                        
- * This API will enable the service request interrupt of the Tx FIFO.
- *
- * @return 
- *      - IX_SSP_SUCCESS - Tx FIFO level interrupt enabled successfully
- *		- IX_SSP_TX_FIFO_HANDLER_MISSING - missing handler for Tx FIFO level interrupt
- *		- IX_SSP_POLL_MODE_BLOCKING - poll mode is selected at init, interrupt not
- *				allowed to be enabled. Use init to enable interrupt mode.
- *		- IX_SSP_NOT_INIT - SSP not initialized. SSP init needs to be called.
- *              
- * @li   Reentrant    : yes
- * @li   ISR Callable : yes
- *
- */
-PUBLIC IX_SSP_STATUS
-ixSspAccTxFIFOIntEnable (
-	TxFIFOThresholdHandler txFIFOIntrHandler);
-
-/**
- * @ingroup IxSspAcc
- * 
- * @fn ixSspAccTxFIFOIntDisable (
-	void)
- *
- * @brief Disables service request interrupt of the Tx FIFO
- *
- * @param - None
- *
- * Global Data	:
- *		- None.
- *                        
- * This API will disable the service request interrupt of the Tx FIFO
- *
- * @return 
- *		- IX_SSP_SUCCESS - Tx FIFO Interrupt disabled successfuly.
- *		- IX_SSP_NOT_INIT - SSP not initialized. SSP init needs to be called.
- *              
- * @li   Reentrant    : yes
- * @li   ISR Callable : yes
- *
- */
-PUBLIC IX_SSP_STATUS
-ixSspAccTxFIFOIntDisable (
-	void);
-
-/**
- * @ingroup IxSspAcc
- * 
- * @fn ixSspAccLoopbackEnable (
-	BOOL loopbackEnable)
- *
- * @brief Enables/disables the loopback mode
- *
- * @param "BOOL [in] loopbackEnable" - True to enable and false to disable.
- *
- * Global Data	:
- *		- None.
- *                        
- * This API will set the mode of operation to either loopback or normal mode
- * according to the user input.
- *
- * @return 
- *		- IX_SSP_SUCCESS - Loopback enabled successfully
- *		- IX_SSP_NOT_INIT - SSP not initialized. SSP init needs to be called.
- *              
- * @li   Reentrant    : yes
- * @li   ISR Callable : yes
- *
- */
-PUBLIC IX_SSP_STATUS
-ixSspAccLoopbackEnable (
-	BOOL loopbackEnable);
-
-/**
- * @ingroup IxSspAcc
- * 
- * @fn ixSspAccSpiSclkPolaritySet (
-	IxSspAccSpiSclkPolarity spiSclkPolaritySelected)
- *
- * @brief Sets the SPI SCLK Polarity to Low or High
- *
- * @param - "IxSspAccSpiSclkPolarity [in] spiSclkPolaritySelected" - SPI SCLK
- *				polarity that can be selected to either high or low
- *
- * Global Data	:
- *		- None.
- *                        
- * This API is only used for the SPI frame format and will set the SPI SCLK polarity
- * to either low or high
- *
- * @return 
- *      - IX_SSP_SUCCESS - SPI Sclk polarity set with valid enum value
- *		- IX_SSP_INVALID_SPI_POLARITY_ENUM_VALUE - invalid SPI polarity value
- *		- IX_SSP_NOT_INIT - SSP not initialized. SSP init needs to be called.
- *              
- * @li   Reentrant    : yes
- * @li   ISR Callable : yes
- *
- */
-PUBLIC IX_SSP_STATUS
-ixSspAccSpiSclkPolaritySet (
-	IxSspAccSpiSclkPolarity spiSclkPolaritySelected);
-
-/**
- * @ingroup IxSspAcc
- * 
- * @fn ixSspAccSpiSclkPhaseSet (
-	IxSspAccSpiSclkPhase spiSclkPhaseSelected)
- *
- * @brief Sets the SPI SCLK Phase
- *
- * @param "IxSspAccSpiSclkPhase [in] spiSclkPhaseSelected" - Phase of either
- *			the SCLK is inactive one cycle at the start of a frame and 1/2
- *			cycle at the end of a frame, OR
- *			the SCLK is inactive 1/2 cycle at the start of a frame and one
- *			cycle at the end of a frame.
- *
- * Global Data	:
- *		- IX_SSP_SUCCESS - SPI Sclk phase set with valid enum value
- *		- IX_SSP_INVALID_SPI_PHASE_ENUM_VALUE - invalid SPI phase value
- *		- IX_SSP_NOT_INIT - SSP not initialized. SSP init needs to be called.
- *                        
- * This API is only used for the SPI frame format and will set the SPI SCLK
- * phase according to user input.
- *
- * @return 
- *      - None
- *              
- * @li   Reentrant    : yes
- * @li   ISR Callable : yes
- *
- */
-PUBLIC IX_SSP_STATUS
-ixSspAccSpiSclkPhaseSet (
-	IxSspAccSpiSclkPhase spiSclkPhaseSelected);
-
-/**
- * @ingroup IxSspAcc
- * 
- * @fn ixSspAccMicrowireControlWordSet (
-	IxSspAccMicrowireCtlWord microwireCtlWordSelected)
- *
- * @brief Sets the Microwire control word to 8 or 16 bit format
- *
- * @param "IxSspAccMicrowireCtlWord [in] microwireCtlWordSelected" - Microwire
- *			control word format can be either 8 or 16 bit format
- *
- * Global Data	:
- *		- None.
- *                        
- * This API is only used for the Microwire frame format and will set the
- * control word to 8 or 16 bit format
- *
- * @return 
- *      - IX_SSP_SUCCESS - Microwire Control Word set with valid enum value
- *		- IX_SSP_TX_FIFO_NOT_EMPTY - Tx FIFO not empty, data size change is not
- *							allowed.
- *		- IX_SSP_INVALID_MICROWIRE_CTL_CMD_ENUM_VALUE - invalid enum value
- *		- IX_SSP_NOT_INIT - SSP not initialized. SSP init needs to be called.
- *              
- * @li   Reentrant    : yes
- * @li   ISR Callable : yes
- *
- */
-PUBLIC IX_SSP_STATUS
-ixSspAccMicrowireControlWordSet (
-	IxSspAccMicrowireCtlWord microwireCtlWordSelected);
-
-/**
- * @ingroup IxSspAcc
- * 
- * @fn ixSspAccTxFIFOThresholdSet (
-	IxSspAccFifoThreshold txFIFOThresholdSelected)
- *
- * @brief Sets the Tx FIFO Threshold.
- *
- * @param "IxSspAccFifoThreshold [in] txFIFOThresholdSelected" - Threshold that
- *		is set for a Tx FIFO service request to be triggered
- *
- * Global Data	:
- *		- None.
- *                        
- * This API will set the threshold for a Tx FIFO threshold to be triggered
- *
- * @return 
- *      - IX_SSP_SUCCESS - Tx FIFO Threshold set with valid enum value
- *		- IX_SSP_INVALID_TX_FIFO_THRESHOLD_ENUM_VALUE - invalid enum value
- *		- IX_SSP_NOT_INIT - SSP not initialized. SSP init needs to be called.
- *              
- * @li   Reentrant    : yes
- * @li   ISR Callable : yes
- *
- */
-PUBLIC IX_SSP_STATUS
-ixSspAccTxFIFOThresholdSet (
-	IxSspAccFifoThreshold txFIFOThresholdSelected);
-
-/**
- * @ingroup IxSspAcc
- * 
- * @fn ixSspAccRxFIFOThresholdSet (
-	IxSspAccFifoThreshold rxFIFOThresholdSelected)
- *
- * @brief Sets the Rx FIFO Threshold.
- *
- * @param "IxSspAccFifoThreshold [in] rxFIFOThresholdSelected" - Threshold that
- *		is set for a Tx FIFO service request to be triggered
- *
- * Global Data	:
- *		- None.
- *                        
- * This API will will set the threshold for a Rx FIFO threshold to be triggered
- *
- * @return 
- *      - IX_SSP_SUCCESS - Rx FIFO Threshold set with valid enum value
- *		- IX_SSP_INVALID_RX_FIFO_THRESHOLD_ENUM_VALUE - invalid enum value
- *		- IX_SSP_NOT_INIT - SSP not initialized. SSP init needs to be called.
- *              
- * @li   Reentrant    : yes
- * @li   ISR Callable : yes
- *
- */
-PUBLIC IX_SSP_STATUS
-ixSspAccRxFIFOThresholdSet (
-	IxSspAccFifoThreshold rxFIFOThresholdSelected);
-
-
-/**
- * Debug functions
- */
-
-/**
- * @ingroup IxSspAcc
- * 
- * @fn ixSspAccStatsGet (
-	IxSspAccStatsCounters *sspStats)
- *
- * @brief Returns the SSP Statistics through the pointer passed in
- *
- * @param "IxSspAccStatsCounters [in] *sspStats" - SSP statistics counter will
- *			be read and written to the location pointed by this pointer.
- *
- * Global Data	:
- *		- None.
- *                        
- * This API will return the statistics counters of the SSP transfers.
- *
- * @return 
- *      - IX_SSP_SUCCESS - Stats obtained into the pointer provided successfully
- *		- IX_SSP_FAIL - client provided pointer is NULL
- *              
- * @li   Reentrant    : yes
- * @li   ISR Callable : yes
- *
- */
-PUBLIC IX_SSP_STATUS
-ixSspAccStatsGet (
-	IxSspAccStatsCounters *sspStats);
-
-/**
- * @ingroup IxSspAcc
- * 
- * @fn ixSspAccStatsReset (
-	void)
- *
- * @brief Resets the SSP Statistics
- *
- * @param - None
- *
- * Global Data	:
- *		- None.
- *                        
- * This API will reset the SSP statistics counters.
- *
- * @return 
- *      - None
- *              
- * @li   Reentrant    : yes
- * @li   ISR Callable : yes
- *
- */
-PUBLIC void
-ixSspAccStatsReset (
-	void);
-
-/**
- * @ingroup IxSspAcc
- * 
- * @fn ixSspAccShow (
-		void)
- *
- * @brief Display SSP status registers and statistics counters.
- *
- * @param - None
- *
- * Global Data	:
- *		- None.
- *                        
- * This API will display the status registers of the SSP and the statistics
- * counters.
- *
- * @return 
- *		- IX_SSP_SUCCESS - SSP show called successfully.
- *		- IX_SSP_NOT_INIT - SSP not initialized. SSP init needs to be called.
- *              
- * @li   Reentrant    : yes
- * @li   ISR Callable : yes
- *
- */
-PUBLIC IX_SSP_STATUS
-ixSspAccShow (
-	void);
-
-/**
- * @ingroup IxSspAcc
- * 
- * @fn ixSspAccSSPBusyCheck (
-		void)
- *
- * @brief Determine the state of the SSP serial port hardware.
- *
- * @param - None
- *
- * Global Data	:
- *		- None.
- *                        
- * This API will return the state of the SSP serial port hardware - busy or
- * idle
- *
- * @return 
- *      - IX_SSP_BUSY - SSP is busy
- *		- IX_SSP_IDLE - SSP is idle.
- *		- IX_SSP_NOT_INIT - SSP not initialized. SSP init needs to be called.
- *              
- * @li   Reentrant    : yes
- * @li   ISR Callable : yes
- *
- */
-PUBLIC IX_SSP_STATUS
-ixSspAccSSPBusyCheck (
-	void);
-
-/**
- * @ingroup IxSspAcc
- * 
- * @fn ixSspAccTxFIFOLevelGet (
-		void)
- *
- * @brief Obtain the Tx FIFO's level
- *
- * @param - None
- *
- * Global Data	:
- *		- None.
- *                        
- * This API will return the level of the Tx FIFO
- *
- * @return 
- *      - 0..16; 0 can also mean SSP not initialized and will need to be init.
- *              
- * @li   Reentrant    : yes
- * @li   ISR Callable : yes
- *
- */
-PUBLIC UINT8
-ixSspAccTxFIFOLevelGet (
-	void);
-
-/**
- * @ingroup IxSspAcc
- * 
- * @fn ixSspAccRxFIFOLevelGet (
-		void)
- *
- * @brief Obtain the Rx FIFO's level
- *
- * @param - None
- *
- * Global Data	:
- *		- None.
- *                        
- * This API will return the level of the Rx FIFO
- *
- * @return 
- *      - 0..16; 0 can also mean SSP not initialized and will need to be init.
- *              
- * @li   Reentrant    : yes
- * @li   ISR Callable : yes
- *
- */
-PUBLIC UINT8
-ixSspAccRxFIFOLevelGet (
-	void);
-
-/**
- * @ingroup IxSspAcc
- * 
- * @fn ixSspAccRxFIFOOverrunCheck (
-		void)
- *
- * @brief Check if the Rx FIFO has overrun its FIFOs
- *
- * @param - None
- *
- * Global Data	:
- *		- None.
- *                        
- * This API will return whether the Rx FIFO has overrun its 16 FIFOs
- *
- * @return 
- *      - IX_SSP_OVERRUN_OCCURRED - Rx FIFO overrun occurred
- *		- IX_SSP_NO_OVERRUN - Rx FIFO did not overrun
- *		- IX_SSP_NOT_INIT - SSP not initialized. SSP init needs to be called.
- *
- * @li   Reentrant    : yes
- * @li   ISR Callable : yes
- *
- */
-PUBLIC IX_SSP_STATUS
-ixSspAccRxFIFOOverrunCheck (
-	void);
-
-#endif /* __ixp46X */
-#endif /* IXSSPACC_H */
diff --git a/arch/arm/cpu/ixp/npe/include/IxTimeSyncAcc.h b/arch/arm/cpu/ixp/npe/include/IxTimeSyncAcc.h
deleted file mode 100644
index 25effed..0000000
--- a/arch/arm/cpu/ixp/npe/include/IxTimeSyncAcc.h
+++ /dev/null
@@ -1,783 +0,0 @@
-/**
- * @file IxTimeSyncAcc.h
- *
- * @author Intel Corporation
- * @date 07 May 2004
- *
- * @brief  Header file for IXP400 Access Layer to IEEE 1588(TM) Precision
- * Clock Synchronisation Protocol Hardware Assist
- *
- * @version 1
- *
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- * 
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- * 
- * @par
- * -- End of Copyright Notice --
- */
-
-/**
- * @defgroup IxTimeSyncAcc IXP400 Time Sync Access Component API 
- *
- * @brief Public API for IxTimeSyncAcc
- *
- * @{
- */
-#ifndef IXTIMESYNCACC_H
-#define IXTIMESYNCACC_H
-
-#ifdef  __ixp46X
-
-#include "IxOsal.h"
-
-/**
- * Section for enum
- */
-
-/**
- * @ingroup IxTimeSyncAcc
- * 
- * @enum IxTimeSyncAccStatus
- *
- * @brief The status as returned from the API
- */
-typedef enum /**< IxTimeSyncAccStatus */
-{
-    IX_TIMESYNCACC_SUCCESS = IX_SUCCESS,    /**< Requested operation successful */
-    IX_TIMESYNCACC_INVALIDPARAM,            /**< An invalid parameter was passed */
-    IX_TIMESYNCACC_NOTIMESTAMP,             /**< While polling no time stamp available */
-    IX_TIMESYNCACC_INTERRUPTMODEINUSE,      /**< Polling not allowed while operating in interrupt mode */
-    IX_TIMESYNCACC_FAILED                   /**< Internal error occurred */
-}IxTimeSyncAccStatus;
-
-/**
- * @ingroup IxTimeSyncAcc
- * 
- * @enum IxTimeSyncAccAuxMode
- *
- * @brief Master or Slave Auxiliary Time Stamp (Snap Shot)
- */
-typedef enum /**< IxTimeSyncAccAuxMode */
-{
-    IX_TIMESYNCACC_AUXMODE_MASTER,          /**< Auxiliary Master Mode */
-    IX_TIMESYNCACC_AUXMODE_SLAVE,           /**< Auxiliary Slave Mode */
-    IX_TIMESYNCACC_AUXMODE_INVALID          /**< Invalid Auxiliary Mode */
-}IxTimeSyncAccAuxMode;
-
-/**
- * @ingroup IxTimeSyncAcc
- * 
- * @enum IxTimeSyncAcc1588PTPPort
- *
- * @brief IEEE 1588 PTP Communication Port(Channel)
- */
-typedef enum /**< IxTimeSyncAcc1588PTPPort */
-{
-    IX_TIMESYNCACC_NPE_A_1588PTP_PORT,      /**< PTP Communication Port on NPE-A */
-    IX_TIMESYNCACC_NPE_B_1588PTP_PORT,      /**< PTP Communication Port on NPE-B */
-    IX_TIMESYNCACC_NPE_C_1588PTP_PORT,      /**< PTP Communication Port on NPE-C */
-    IX_TIMESYNCACC_NPE_1588PORT_INVALID     /**< Invalid PTP Communication Port */
-} IxTimeSyncAcc1588PTPPort;
-
-/**
- * @ingroup IxTimeSyncAcc
- * 
- * @enum IxTimeSyncAcc1588PTPPortMode
- *
- * @brief Master or Slave mode for IEEE 1588 PTP Communication Port
- */
-typedef enum  /**< IxTimeSyncAcc1588PTPPortMode */
-{
-    IX_TIMESYNCACC_1588PTP_PORT_MASTER,       /**< PTP Communication Port in Master Mode */
-    IX_TIMESYNCACC_1588PTP_PORT_SLAVE,        /**< PTP Communication Port in Slave Mode */
-    IX_TIMESYNCACC_1588PTP_PORT_ANYMODE,      /**< PTP Communication Port in ANY Mode
-                                                  allows time stamping of all messages
-                                                  including non-1588 PTP */
-    IX_TIMESYNCACC_1588PTP_PORT_MODE_INVALID  /**< Invalid PTP Port Mode */
-}IxTimeSyncAcc1588PTPPortMode;
-
-/**
- * @ingroup IxTimeSyncAcc
- * 
- * @enum IxTimeSyncAcc1588PTPMsgType
- *
- * @brief 1588 PTP Messages types that can be detected on communication port
- *
- * Note that client code can determine this based on master/slave mode in which
- * it is already operating in and this information is made available for the sake
- * of convenience only.
- */
-typedef enum  /**< IxTimeSyncAcc1588PTPMsgType */
-{
-    IX_TIMESYNCACC_1588PTP_MSGTYPE_SYNC,     /**< PTP Sync message sent by Master or received by Slave */
-    IX_TIMESYNCACC_1588PTP_MSGTYPE_DELAYREQ, /**< PTP Delay_Req message sent by Slave or received by Master */
-    IX_TIMESYNCACC_1588PTP_MSGTYPE_UNKNOWN   /**< Other PTP and non-PTP message sent or received by both
-                                                Master and/or Slave */
-} IxTimeSyncAcc1588PTPMsgType;
-
-/**
- * Section for struct
- */
-
-/**
- * @ingroup IxTimeSyncAcc
- *
- * @struct IxTimeSyncAccTimeValue
- *
- * @brief Struct to hold 64 bit SystemTime and TimeStamp values
- */
-typedef struct  /**< IxTimeSyncAccTimeValue */
-{
-    UINT32 timeValueLowWord;               /**< Lower 32 bits of the time value */
-    UINT32 timeValueHighWord;              /**< Upper 32 bits of the time value */  
-} IxTimeSyncAccTimeValue;
-
-/**
- * @ingroup IxTimeSyncAcc
- *
- * @struct IxTimeSyncAccUuid
- *
- * @brief Struct to hold 48 bit UUID values captured in Sync or Delay_Req messages
- */
-typedef struct  /**< IxTimeSyncAccUuid */
-{
-    UINT32 uuidValueLowWord;               /**<The lower 32 bits of the UUID */
-    UINT16 uuidValueHighHalfword;          /**<The upper 16 bits of the UUID */  
-} IxTimeSyncAccUuid;
-
-/**
- * @ingroup IxTimeSyncAcc
- *
- * @struct IxTimeSyncAccPtpMsgData
- *
- * @brief Struct for data from the PTP message returned when TimeStamp available
- */
-typedef struct  /**< IxTimeSyncAccPtpMsgData */
-{
-    IxTimeSyncAcc1588PTPMsgType ptpMsgType; /**< PTP Messages type */
-    IxTimeSyncAccTimeValue ptpTimeStamp;    /**< 64 bit TimeStamp value from PTP Message */
-    IxTimeSyncAccUuid ptpUuid;              /**< 48 bit UUID value from the PTP Message */
-    UINT16 ptpSequenceNumber;               /**< 16 bit Sequence Number from PTP Message */
-} IxTimeSyncAccPtpMsgData;
-
-/**
- * @ingroup IxTimeSyncAcc
- *
- * @struct IxTimeSyncAccStats
- *
- * @brief Statistics for the PTP messages
- */
-typedef struct  /**< IxTimeSyncAccStats */
-{
-    UINT32 rxMsgs; /**< Count of timestamps for received PTP Messages */
-    UINT32 txMsgs; /**< Count of timestamps for transmitted PTP Messages */
-} IxTimeSyncAccStats;
-
-/**
- * @ingroup IxTimeSyncAcc
- *
- * @typedef IxTimeSyncAccTargetTimeCallback
- *
- * @brief Callback for use by target time stamp interrupt
- */
-typedef void (*IxTimeSyncAccTargetTimeCallback)(IxTimeSyncAccTimeValue targetTime);
-
-/**
- * @ingroup IxTimeSyncAcc
- *
- * @typedef IxTimeSyncAccAuxTimeCallback
- *
- * @brief Callback for use by auxiliary time interrupts
- */
-typedef void (*IxTimeSyncAccAuxTimeCallback)(IxTimeSyncAccAuxMode auxMode,
-             IxTimeSyncAccTimeValue auxTime);
-
-/*
- * Section for prototypes interface functions
- */
-
-/**
- * @ingroup IxTimeSyncAcc
- * 
- * @fn IxTimeSyncAccStatus ixTimeSyncAccPTPPortConfigSet(
-                               IxTimeSyncAcc1588PTPPort ptpPort,
-                               IxTimeSyncAcc1588PTPPortMode ptpPortMode)
- *
- * @brief Configures the IEEE 1588 message detect on particular PTP port.
- *
- * @param ptpPort [in] - PTP port to config
- * @param ptpPortMode [in]- Port to operate in Master or Slave mode
- *
- * This API will enable the time stamping on a particular PTP port.
- *          
- * @li Re-entrant   : No
- * @li ISR Callable : No
- * 
- * @return @li IX_TIMESYNCACC_SUCCESS - Operation is successful
- *         @li IX_TIMESYNCACC_INVALIDPARAM - Invalid parameters passed
- *         @li IX_TIMESYNCACC_FAILED - Internal error occurred
- */
-PUBLIC IxTimeSyncAccStatus
-ixTimeSyncAccPTPPortConfigSet(IxTimeSyncAcc1588PTPPort ptpPort,
-       IxTimeSyncAcc1588PTPPortMode ptpPortMode);
-
-/**
- * @ingroup IxTimeSyncAcc
- * 
- * @fn IxTimeSyncAccStatus ixTimeSyncAccPTPPortConfigGet(
-                               IxTimeSyncAcc1588PTPPort ptpPort,
-                               IxTimeSyncAcc1588PTPPortMode *ptpPortMode)
- *
- * @brief Retrieves IEEE 1588 PTP operation mode on particular PTP port.
- *
- * @param ptpPort [in] - PTP port
- * @param ptpPortMode [in]- Mode of operation of PTP port (Master or Slave)
- *
- * This API will identify the time stamping capability of a PTP port by means
- * of obtaining its mode of operation.
- *          
- * @li Re-entrant   : No
- * @li ISR Callable : No
- * 
- * @return @li IX_TIMESYNCACC_SUCCESS - Operation is successful
- *         @li IX_TIMESYNCACC_INVALIDPARAM - Invalid parameters passed
- *         @li IX_TIMESYNCACC_FAILED - Internal error occurred
- */
-PUBLIC IxTimeSyncAccStatus
-ixTimeSyncAccPTPPortConfigGet(IxTimeSyncAcc1588PTPPort ptpPort,
-    IxTimeSyncAcc1588PTPPortMode *ptpPortMode);
-
-/**
- * @ingroup IxTimeSyncAcc
- * 
- * @fn IxTimeSyncAccStatus ixTimeSyncAccPTPRxPoll(
-                               IxTimeSyncAcc1588PTPPort ptpPort,
-                               IxTimeSyncAccPtpMsgData  *ptpMsgData)
- *
- * @brief Polls the IEEE 1588 message/time stamp detect status on a particular 
- * PTP Port on the Receive side.
- *
- * @param ptpPort [in] - PTP port to poll
- * @param ptpMsgData [out] - Current TimeStamp and other Data
- *
- * This API will poll for the availability of a time stamp on the received Sync 
- * (Slave) or Delay_Req (Master) messages.
- * The client application will provide the buffer.
- *              
- * @li Re-entrant   : No
- * @li ISR Callable : No
- * 
- * @return @li IX_TIMESYNCACC_SUCCESS - Operation is successful
- *         @li IX_TIMESYNCACC_INVALIDPARAM - Invalid parameters passed
- *         @li IX_TIMESYNCACC_NOTIMESTAMP - No time stamp available
- *         @li IX_TIMESYNCACC_FAILED - Internal error occurred
- */
-PUBLIC IxTimeSyncAccStatus
-ixTimeSyncAccPTPRxPoll(IxTimeSyncAcc1588PTPPort ptpPort,
-    IxTimeSyncAccPtpMsgData  *ptpMsgData);
-
-/**
- * @ingroup IxTimeSyncAcc
- * 
- * @fn IxTimeSyncAccStatus ixTimeSyncAccPTPTxPoll(
-                               IxTimeSyncAcc1588PTPPort ptpPort,
-                               IxTimeSyncAccPtpMsgData  *ptpMsgData)
- *
- *
- * @brief Polls the IEEE 1588 message/time stamp detect status on a particular 
- * PTP Port on the Transmit side.
- *
- * @param ptpPort [in] - PTP port to poll
- * @param ptpMsgData [out] - Current TimeStamp and other Data
- *                        
- * This API will poll for the availability of a time stamp on the transmitted
- * Sync (Master) or Delay_Req (Slave) messages.
- * The client application will provide the buffer.
- *              
- * @li Re-entrant   : No
- * @li ISR Callable : No
- * 
- * @return @li IX_TIMESYNCACC_SUCCESS - Operation is successful
- *         @li IX_TIMESYNCACC_INVALIDPARAM - Invalid parameters passed
- *         @li IX_TIMESYNCACC_NOTIMESTAMP - No time stamp available
- *         @li IX_TIMESYNCACC_FAILED - Internal error occurred
- */
-PUBLIC IxTimeSyncAccStatus
-ixTimeSyncAccPTPTxPoll(IxTimeSyncAcc1588PTPPort ptpPort,
-    IxTimeSyncAccPtpMsgData  *ptpMsgData);
-
-/**
- * @ingroup IxTimeSyncAcc
- * 
- * @fn IxTimeSyncAccStatus ixTimeSyncAccSystemTimeSet(
-                               IxTimeSyncAccTimeValue systemTime)
- *
- * @brief Sets the System Time in the IEEE 1588 hardware assist block
- *
- * @param systemTime [in] - Value to set System Time
- *                        
- * This API will set the SystemTime to given value.
- *              
- * @li Re-entrant   : yes
- * @li ISR Callable : no
- * 
- * @return @li IX_TIMESYNCACC_SUCCESS - Operation is successful
- *         @li IX_TIMESYNCACC_FAILED - Internal error occurred
- */
-PUBLIC IxTimeSyncAccStatus
-ixTimeSyncAccSystemTimeSet(IxTimeSyncAccTimeValue systemTime);
-
-/**
- * @ingroup IxTimeSyncAcc
- * 
- * @fn IxTimeSyncAccStatus ixTimeSyncAccSystemTimeGet(
-                               IxTimeSyncAccTimeValue *systemTime)
- *
- * @brief Gets the System Time from the IEEE 1588 hardware assist block
- *
- * @param systemTime [out] - Copy the current System Time into the client 
- * application provided buffer
- *
- * This API will get the SystemTime from IEEE1588 block and return to client
- *      
- * @li Re-entrant   : no
- * @li ISR Callable : no
- * 
- * @return @li IX_TIMESYNCACC_SUCCESS - Operation is successful
- *         @li IX_TIMESYNCACC_INVALIDPARAM - Invalid parameters passed
- *         @li IX_TIMESYNCACC_FAILED - Internal error occurred
- */
-PUBLIC IxTimeSyncAccStatus
-ixTimeSyncAccSystemTimeGet(IxTimeSyncAccTimeValue *systemTime);
-
-/**
- * @ingroup IxTimeSyncAcc
- * 
- * @fn IxTimeSyncAccStatus ixTimeSyncAccTickRateSet(
-                               UINT32 tickRate)
- *
- * @brief Sets the Tick Rate (Frequency Scaling Value) in the IEEE 1588
- * hardware assist block
- *
- * @param tickRate [in] - Value to set Tick Rate
- *                        
- * This API will set the Tick Rate (Frequency Scaling Value) in the IEEE
- * 1588 block to the given value. The Accumulator register (not client 
- * visible) is incremented by this TickRate value every clock cycle. When 
- * the Accumulator overflows, the SystemTime is incremented by one. This
- * TickValue can therefore be used to adjust the system timer.
- *           
- * @li Re-entrant   : yes
- * @li ISR Callable : no
- *
- * @return @li IX_TIMESYNCACC_SUCCESS - Operation is successful
- *         @li IX_TIMESYNCACC_FAILED - Internal error occurred
- */
-PUBLIC IxTimeSyncAccStatus
-ixTimeSyncAccTickRateSet(UINT32 tickRate);
-
-/**
- * @ingroup IxTimeSyncAcc
- * 
- * @fn IxTimeSyncAccStatus ixTimeSyncAccTickRateGet(
-                               UINT32 *tickRate)
- *
- * @brief Gets the Tick Rate (Frequency Scaling Value) from the IEEE 1588
- * hardware assist block
- *
- * @param tickRate [out] - Current Tick Rate value in the IEEE 1588 block
- *
- * This API will get the TickRate on IEE15588 block. Refer to @ref 
- * ixTimeSyncAccTickRateSet for notes on usage of this value.
- *         
- * @li   Reentrant    : yes
- * @li   ISR Callable : no
- *
- * @return @li IX_TIMESYNCACC_SUCCESS - Operation is successful
- *         @li IX_TIMESYNCACC_INVALIDPARAM - Invalid parameters passed
- *         @li IX_TIMESYNCACC_FAILED - Internal error occurred
- */
-PUBLIC IxTimeSyncAccStatus
-ixTimeSyncAccTickRateGet(UINT32 *tickRate);
-
-/**
- * @ingroup IxTimeSyncAcc
- * 
- * @fn IxTimeSyncAccStatus ixTimeSyncAccTargetTimeInterruptEnable(
-                               IxTimeSyncAccTargetTimeCallback targetTimeCallback)
- *
- * @brief Enables the interrupt to verify the condition where the System Time 
- * greater or equal to the Target Time in the IEEE 1588 hardware assist block. 
- * If the condition is true an interrupt will be sent to XScale.
- *
- * @param targetTimeCallback [in] - Callback to be invoked when interrupt fires
- *
- * This API will enable the Target Time reached/hit condition interrupt.
- *
- * NOTE: The client application needs to ensure that the APIs 
- * @ref ixTimeSyncAccTargetTimeInterruptEnable, @ref ixTimeSyncAccTargetTimeSet and
- * @ref ixTimeSyncAccTargetTimeInterruptDisable are accessed in mutual exclusive 
- * manner with respect to each other.
- *
- * @li Re-entrant   : no
- * @li ISR Callable : yes
- *
- * @return @li IX_TIMESYNCACC_SUCCESS - Operation is successful
- *         @li IX_TIMESYNCACC_INVALIDPARAM - Null parameter passed for callback
- *         @li IX_TIMESYNCACC_FAILED - Internal error occurred
- */
-PUBLIC IxTimeSyncAccStatus
-ixTimeSyncAccTargetTimeInterruptEnable(IxTimeSyncAccTargetTimeCallback targetTimeCallback);
-
-/**
- * @ingroup IxTimeSyncAcc
- * 
- * @fn IxTimeSyncAccStatus ixTimeSyncAccTargetTimeInterruptDisable(
-                               void)
- *
- * @brief Disables the interrupt for the condition explained in the function
- * description of @ref ixTimeSyncAccTargetTimeInterruptEnable.
- *
- * This API will disable the Target Time interrupt.
- *
- * NOTE: The client application needs to ensure that the APIs 
- * @ref ixTimeSyncAccTargetTimeInterruptEnable, @ref ixTimeSyncAccTargetTimeSet and
- * @ref ixTimeSyncAccTargetTimeInterruptDisable are accessed in mutual exclusive 
- * manner with respect to each other.
- *              
- * @li Re-entrant   : no
- * @li ISR Callable : yes
- *
- * @return @li IX_TIMESYNCACC_SUCCESS - Operation is successful
- *         @li IX_TIMESYNCACC_FAILED - Internal error occurred
- */
-PUBLIC IxTimeSyncAccStatus
-ixTimeSyncAccTargetTimeInterruptDisable(void);
-
-/**
- * @ingroup IxTimeSyncAcc
- * 
- * @fn IxTimeSyncAccStatus ixTimeSyncAccTargetTimePoll(
-                               BOOL *ttmPollFlag,
-                               IxTimeSyncAccTimeValue *targetTime)
- *
- * @brief Poll to verify the condition where the System Time greater or equal to
- * the Target Time in the IEEE 1588 hardware assist block. If the condition is
- * true an event flag is set in the hardware.
- *
- * @param ttmPollFlag [out] - TRUE  if the target time reached/hit condition event set
- *                            FALSE if the target time reached/hit condition event is 
-                                    not set
- * @param targetTime [out] - Capture current targetTime into client provided buffer
- *
- * Poll the target time reached/hit condition status. Return true and the current
- * target time value, if the condition is true else return false.
- *
- * NOTE: The client application will need to clear the event flag that will be set
- * as long as the condition that the System Time greater or equal to the Target Time is
- * valid, in one of the following ways:
- *     1) Invoke the API to change the target time
- *     2) Change the system timer value 
- *              
- * @li Re-entrant   : yes
- * @li ISR Callable : no
- *
- * @return @li IX_TIMESYNCACC_SUCCESS - Operation is successful
- *         @li IX_TIMESYNCACC_INVALIDPARAM - Null parameter passed
- *         @li IX_TIMESYNCACC_FAILED - Internal error occurred
- *         @li IX_TIMESYNCACC_INTERRUPTMODEINUSE - Interrupt mode in use
- */
-PUBLIC IxTimeSyncAccStatus
-ixTimeSyncAccTargetTimePoll(BOOL *ttmPollFlag,
-    IxTimeSyncAccTimeValue *targetTime);
-
-/**
- * @ingroup IxTimeSyncAcc
- * 
- * @fn IxTimeSyncAccStatus ixTimeSyncAccTargetTimeSet(
-                               IxTimeSyncAccTimeValue targetTime)
- *
- * @brief Sets the Target Time in the IEEE 1588 hardware assist block
- *
- * @param targetTime [in] - Value to set Target Time
- *                        
- * This API will set the Target Time to a given value.
- *
- * NOTE: The client application needs to ensure that the APIs 
- * @ref ixTimeSyncAccTargetTimeInterruptEnable, @ref ixTimeSyncAccTargetTimeSet and
- * @ref ixTimeSyncAccTargetTimeInterruptDisable are accessed in mutual exclusive 
- * manner with respect to each other.
- *              
- * @li   Reentrant    : no
- * @li   ISR Callable : yes
- *
- * @return @li IX_TIMESYNCACC_SUCCESS - Operation is successful
- *         @li IX_TIMESYNCACC_FAILED - Internal error occurred
- */
-PUBLIC IxTimeSyncAccStatus
-ixTimeSyncAccTargetTimeSet(IxTimeSyncAccTimeValue targetTime);
-
-/**
- * @ingroup IxTimeSyncAcc
- * 
- * @fn IxTimeSyncAccStatus ixTimeSyncAccTargetTimeGet(
-                               IxTimeSyncAccTimeValue *targetTime)
- *
- * @brief Gets the Target Time in the IEEE 1588 hardware assist block
- *
- * @param targetTime [out] - Copy current time to client provided buffer
- *                                                 
- * This API will get the Target Time from IEEE 1588 block and return to the 
- * client application
- *            
- * @li Re-entrant   : yes
- * @li ISR Callable : no
- *
- * @return @li IX_TIMESYNCACC_SUCCESS - Operation is successful
- *         @li IX_TIMESYNCACC_INVALIDPARAM - Null parameter passed
- *         @li IX_TIMESYNCACC_FAILED - Internal error occurred
- */
-PUBLIC IxTimeSyncAccStatus
-ixTimeSyncAccTargetTimeGet(IxTimeSyncAccTimeValue *targetTime);
-
-/**
- * @ingroup IxTimeSyncAcc
- * 
- * @fn IxTimeSyncAccStatus ixTimeSyncAccAuxTimeInterruptEnable(
-                               IxTimeSyncAccAuxMode auxMode, 
-                               IxTimeSyncAccAuxTimeCallback auxTimeCallback)
- *
- * @brief Enables the interrupt notification for the given mode of Auxiliary Time 
- * Stamp in the IEEE 1588 hardware assist block
- * 
- * @param auxMode [in] - Auxiliary time stamp register (slave or master) to use
- * @param auxTimeCallback [in] - Callback to be invoked when interrupt fires 
- *                                                              
- * This API will enable the Auxiliary Master/Slave Time stamp Interrupt.
- *
- * <pre>
- * NOTE: 1) An individual callback is to be registered for each Slave and Master 
- * Auxiliary Time Stamp registers. Thus to register for both Master and Slave time
- * stamp interrupts either the same callback or two separate callbacks the API has
- * to be invoked twice.
- *       2) On the IXDP465 Development Platform, the Auxiliary Timestamp signal for 
- * slave mode is tied to GPIO 8 pin. This signal is software routed by default to 
- * PCI for backwards compatibility with the IXDP425 Development Platform. This
- * routing must be disabled for the auxiliary slave time stamp register to work 
- * properly. The following commands may be used to accomplish this. However, refer
- * to the IXDP465 Development Platform Users Guide or the BSP/LSP documentation for
- * more specific information.
- *
- * For Linux (at the Redboot prompt i.e., before loading zImage):
- *     mfill -b 0x54100000 -1 -l 1 -p 8
- *     mfill -b 0x54100001 -1 -l 1 -p 0x7f
- * For vxWorks, at the prompt:
- *     intDisable(25)
- *     ixdp400FpgaIODetach(8)
- * </pre>
- *              
- * @li Re-entrant   : no
- * @li ISR Callable : no
- *
- * @return @li IX_TIMESYNCACC_SUCCESS - Operation is successful
- *         @li IX_TIMESYNCACC_INVALIDPARAM - Null parameter passed for callback or
-                                            invalid auxiliary snapshot mode
- *         @li IX_TIMESYNCACC_FAILED - Internal error occurred
- */
-PUBLIC IxTimeSyncAccStatus
-ixTimeSyncAccAuxTimeInterruptEnable(IxTimeSyncAccAuxMode auxMode,
-    IxTimeSyncAccAuxTimeCallback auxTimeCallback);
-
-/**
- * @ingroup IxTimeSyncAcc
- * 
- * @fn IxTimeSyncAccStatus ixTimeSyncAccAuxTimeInterruptDisable(
-                               IxTimeSyncAccAuxMode auxMode)
- *
- * @brief Disables the interrupt for the indicated mode of Auxiliary Time Stamp
- * in the IEEE 1588 hardware assist block
- *
- * @param auxMode [in] - Auxiliary time stamp mode (slave or master) using which
- * the interrupt will be disabled.
- *                        
- * This API will disable the Auxiliary Time Stamp Interrupt (Master or Slave)
- *              
- * @li Re-entrant   : yes
- * @li ISR Callable : no
- *
- * @return @li IX_TIMESYNCACC_SUCCESS - Operation is successful
- *         @li IX_TIMESYNCACC_INVALIDPARAM - Invalid parameters passed
- *         @li IX_TIMESYNCACC_FAILED - Internal error occurred
- */
-PUBLIC IxTimeSyncAccStatus
-ixTimeSyncAccAuxTimeInterruptDisable(IxTimeSyncAccAuxMode auxMode);
-
-/**
- * @ingroup IxTimeSyncAcc
- * 
- * @fn IxTimeSyncAccStatus ixTimeSyncAccAuxTimePoll(
-                               IxTimeSyncAccAuxMode auxMode,
-                               BOOL *auxPollFlag,
-                               IxTimeSyncAccTimeValue *auxTime)
- *
- * @brief Poll for the Auxiliary Time Stamp captured for the mode indicated 
- * (Master or Slave)
- *
- * @param auxMode [in] - Auxiliary Snapshot Register (Slave or Master) to be checked
- * @param auxPollFlag [out] - TRUE if the time stamp captured in auxiliary 
-                                   snapshot register
- *                            FALSE if the time stamp not captured in 
-                                   auxiliary snapshot register
- * @param auxTime [out] - Copy the current Auxiliary Snapshot Register value into the
- * client provided buffer
- *
- * Polls for the Time stamp in the appropriate Auxiliary Snapshot Registers based 
- * on the mode specified. Return true and the contents of the Auxiliary snapshot,
- * if it is available else return false.
- * 
- * Please refer to the note #2 of the API @ref ixTimeSyncAccAuxTimeInterruptEnable
- * for more information for Auxiliary Slave mode.
- *
- * @li Re-entrant   : yes
- * @li ISR Callable : no
- *
- * @return @li IX_TIMESYNCACC_SUCCESS - Operation is successful
- *         @li IX_TIMESYNCACC_INVALIDPARAM - Null parameter passed for auxPollFlag,
-                   callback or invalid auxiliary snapshot mode
- *         @li IX_TIMESYNCACC_FAILED - Internal error occurred
- *         @li IX_TIMESYNCACC_INTERRUPTMODEINUSE - Interrupt mode in use
- */
-PUBLIC IxTimeSyncAccStatus
-ixTimeSyncAccAuxTimePoll(IxTimeSyncAccAuxMode auxMode,
-    BOOL *auxPollFlag,
-    IxTimeSyncAccTimeValue *auxTime);
-
-/**
- * @ingroup IxTimeSyncAcc
- *
- * @fn IxTimeSyncAccStatus ixTimeSyncAccReset(void)
- *
- * @brief Resets the IEEE 1588 hardware assist block
- *
- * Sets the reset bit in the IEEE1588 silicon which fully resets the silicon block
- *            
- * @li Reentrant    : yes
- * @li ISR Callable : no
- *
- * @return @li IX_TIMESYNCACC_SUCCESS - Operation is successful
- *         @li IX_TIMESYNCACC_FAILED  - Internal error occurred
- */
-PUBLIC IxTimeSyncAccStatus
-ixTimeSyncAccReset(void);
-
-/**
- * @ingroup IxTimeSyncAcc
- *
- * @fn IxTimeSyncAccStatus ixTimeSyncAccStatsGet(IxTimeSyncAccStats
-                               *timeSyncStats)
- *
- * @brief Returns the IxTimeSyncAcc Statistics in the client supplied buffer
- *
- * @param timeSyncStats [out] - TimeSync statistics counter values
- *
- * This API will return the statistics of the received or transmitted messages.
- * 
- * NOTE: 1) These counters are updated only when the client polls for the time 
- * stamps or interrupt are enabled. This is because the IxTimeSyncAcc module 
- * does not either transmit or receive messages and does only run the code 
- * when explicit requests received by client application.
- *
- *       2) These statistics reflect the number of valid PTP messages exchanged
- * in Master and Slave modes but includes all the messages (including valid 
- * non-PTP messages) while operating in the Any mode.
- *              
- * @li Reentrant    : no
- * @li ISR Callable : no
- *
- * @return @li IX_TIMESYNCACC_SUCCESS - Operation is successful
- *         @li IX_TIMESYNCACC_INVALIDPARAM - NULL parameter passed
- *         @li IX_TIMESYNCACC_FAILED - Internal error occurred
- */
-PUBLIC IxTimeSyncAccStatus
-ixTimeSyncAccStatsGet(IxTimeSyncAccStats *timeSyncStats);
-
-/**
- * @ingroup IxTimeSyncAcc
- *
- * @fn void ixTimeSyncAccStatsReset(void)
- *
- * @brief Reset Time Sync statistics
- *
- * This API will reset the statistics counters of the TimeSync access layer.
- *             
- * @li Reentrant    : yes
- * @li ISR Callable:  no
- *
- * @return @li None
- */
-PUBLIC void
-ixTimeSyncAccStatsReset(void);
-
-/**
- * @ingroup IxTimeSyncAcc
- *
- * @fn IxTimeSyncAccStatus ixTimeSyncAccShow(void)
- *
- * @brief Displays the Time Sync current status
- *
- * This API will display status on the current configuration of the IEEE
- * 1588 hardware assist block, contents of the various time stamp registers,
- * outstanding interrupts and/or events.
- *
- * Note that this is intended for debug only, and in contrast to the other
- * functions, it does not clear the any of the status bits associated with
- * active timestamps and so is passive in its nature.
- *            
- * @li Reentrant    : yes
- * @li ISR Callable : no
- *
- * @return @li IX_TIMESYNCACC_SUCCESS - Operation is successful
- *         @li IX_TIMESYNCACC_FAILED - Internal error occurred
- */
-PUBLIC IxTimeSyncAccStatus
-ixTimeSyncAccShow(void);
-
-#endif /* __ixp46X */
-#endif /* IXTIMESYNCACC_H */
-
-/**
- * @} defgroup IxTimeSyncAcc
- */
-
diff --git a/arch/arm/cpu/ixp/npe/include/IxTimerCtrl.h b/arch/arm/cpu/ixp/npe/include/IxTimerCtrl.h
deleted file mode 100644
index 669dd3e..0000000
--- a/arch/arm/cpu/ixp/npe/include/IxTimerCtrl.h
+++ /dev/null
@@ -1,263 +0,0 @@
-/** 
- * @file IxTimerCtrl.h
- * @brief 
- *    This is the header file for the Timer Control component.
- *
- *    The timer callback control component provides a mechanism by which different 
- *    client components can start a timer and have a supplied callback function
- *    invoked when the timer expires.
- *    The callbacks are all dispatched from one thread inside this component. 
- *    Any component that needs to be called periodically should use this facility 
- *    rather than create its own task with a sleep loop. 
- *
- * @par
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- * 
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- * 
- * @par
- * -- End of Copyright Notice --
-*/
-
-/**
- * @defgroup IxTimerCtrl IXP400 Timer Control (IxTimerCtrl) API
- *
- * @brief The public API for the IXP400 Timer Control Component.
- *
- * @{
- */
-
-#ifndef IxTimerCtrl_H
-#define IxTimerCtrl_H
-
-
-#include "IxTypes.h"
-/* #include "Ossl.h" */
-
-/*
- * #defines and macros used in this file.
- */
-
-/**
- * @ingroup IxTimerCtrl
- *
- * @def IX_TIMERCTRL_NO_FREE_TIMERS
- *
- * @brief Timer schedule return code.
- *
- * Indicates that the request to start a timer failed because
- * all available timer resources are used. 
- */
-#define IX_TIMERCTRL_NO_FREE_TIMERS 2
-
-
-/**
- * @ingroup IxTimerCtrl
- *
- * @def IX_TIMERCTRL_PARAM_ERROR
- *
- * @brief Timer schedule return code.
- *
- * Indicates that the request to start a timer failed because
- * the client has supplied invalid parameters.
- */
-#define IX_TIMERCTRL_PARAM_ERROR 3
-
- 
-/*
- * Typedefs whose scope is limited to this file.
- */
-
-/**
- * @ingroup IxTimerCtrl
- *
- * @brief A typedef for a pointer to a timer callback function. 
- * @para void * - This parameter is supplied by the client when the
- * timer is started and passed back to the client in the callback.
- * @note in general timer callback functions should not block or 
- * take longer than 100ms. This constraint is required to ensure that
- * higher priority callbacks are not held up. 
- * All callbacks are called from the same thread. 
- * This thread is a shared resource. 
- * The parameter passed is provided when the timer is scheduled.
- */
-typedef void (*IxTimerCtrlTimerCallback)(void *userParam);
-
-
-/**
- * @ingroup IxTimerCtrl
- *
- * @brief List used to identify the users of timers.
- * @note The order in this list indicates priority.  Components appearing 
- * higher in the list will be given priority over components lower in the
- * list.  When adding components, please insert at an appropriate position
- * for priority ( i.e values should be less than IxTimerCtrlMaxPurpose ) .
- */
-typedef enum 
-{
-    IxTimerCtrlAdslPurpose,
-   /* Insert new purposes above this line only
-    */
-   IxTimerCtrlMaxPurpose
-}
-IxTimerCtrlPurpose;
-
-
-/*
- * Function definition
- */
-
-/**
- * @ingroup IxTimerCtrl
- *
- * @fn ixTimerCtrlSchedule(IxTimerCtrlTimerCallback func, 
-                       void *userParam, 
-                       IxTimerCtrlPurpose purpose,
-	               UINT32 relativeTime,
-                       unsigned *timerId )
- * 
- * @brief Schedules a callback function to be called after a period of "time".
- * The callback function should not block or run for more than 100ms.
- * This function 
- *
- * @param func @ref IxTimerCtrlTimerCallback [in] - the callback function to be called.
- * @param userParam void [in] - a parameter to send to the callback function, can be NULL.
- * @param purpose @ref IxTimerCtrlPurpose [in] - the purpose of the callback, internally this component will 
- * decide the priority of callbacks with different purpose.
- * @param relativeTime UINT32 [in] - time relative to now in milliseconds after which the callback 
- * will be called. The time must be greater than the duration of one OS tick.
- * @param *timerId unsigned [out] -  An id for the callback scheduled. 
- * This id can be used to cancel the callback.
- * @return 
- * @li IX_SUCCESS - The timer was started successfully.
- * @li IX_TIMERCTRL_NO_FREE_TIMERS - The timer was not started because the maximum number
- * of running timers has been exceeded.
- * @li IX_TIMERCTRL_PARAM_ERROR - The timer was not started because the client has supplied 
- * a NULL callback func, or the requested timeout is less than one OS tick.
- * @note  This function is re-entrant. The function accesses a list of running timers
- * and may suspend the calling thread if this list is being accesed by another thread.
- */
-PUBLIC IX_STATUS 
-ixTimerCtrlSchedule(IxTimerCtrlTimerCallback func, 
-                       void *userParam, 
-                       IxTimerCtrlPurpose purpose,
-	               UINT32 relativeTime,
-                       unsigned *timerId );
-
-
-/**
- * @ingroup IxTimerCtrl
- *
- * @fn ixTimerCtrlScheduleRepeating(IxTimerCtrlTimerCallback func, 
-                                void *param, 
-                                IxTimerCtrlPurpose purpose,
-			        UINT32 interval,
-                                unsigned *timerId )
- * 
- * @brief Schedules a callback function to be called after a period of "time".
- * The callback function should not block or run for more than 100ms.
- *
- * @param func @ref IxTimerCtrlTimerCallback [in] - the callback function to be called.
- * @param userParam void [in] - a parameter to send to the callback function, can be NULL.
- * @param purpose @ref IxTimerCtrlPurpose [in] - the purpose of the callback, internally this component will 
- * decide the priority of callbacks with different purpose.
- * @param interval UINT32 [in] - the interval in milliseconds between calls to func. 
- * @param timerId unsigned [out] - An id for the callback scheduled. 
- * This id can be used to cancel the callback.
- * @return 
- * @li IX_SUCCESS - The timer was started successfully.
- * @li IX_TIMERCTRL_NO_FREE_TIMERS - The timer was not started because the maximum number
- * of running timers has been exceeded.
- * @li IX_TIMERCTRL_PARAM_ERROR - The timer was not started because the client has supplied 
- * a NULL callback func, or the requested timeout is less than one OS tick.
- * @note  This function is re-entrant. The function accesses a list of running timers
- * and may suspend the calling thread if this list is being accesed by another thread.
- */
-PUBLIC IX_STATUS 
-ixTimerCtrlScheduleRepeating(IxTimerCtrlTimerCallback func, 
-                                void *param, 
-                                IxTimerCtrlPurpose purpose,
-			        UINT32 interval,
-                                unsigned *timerId );
-
-/**
- * @ingroup IxTimerCtrl
- *
- * @fn ixTimerCtrlCancel (unsigned id)
- *
- * @brief Cancels a scheduled callback.
- *
- * @param id unsigned [in] - the id of the callback to be cancelled.
- * @return
- * @li IX_SUCCESS - The timer was successfully stopped.
- * @li IX_FAIL - The id parameter did not corrrespond to any running timer..
- * @note This function is re-entrant. The function accesses a list of running timers
- * and may suspend the calling thread if this list is being accesed by another thread.
- */
-PUBLIC IX_STATUS
-ixTimerCtrlCancel (unsigned id);
-
-/**
- * @ingroup IxTimerCtrl
- *
- * @fn ixTimerCtrlInit(void)
- *
- * @brief Initialise the Timer Control Component.
- * @return 
- * @li IX_SUCCESS - The timer control component initialized successfully.
- * @li IX_FAIL - The timer control component initialization failed,
- * or the component was already initialized.
- * @note This must be done before any other API function is called.
- * This function should be called once only and is not re-entrant.
- */
-PUBLIC IX_STATUS
-ixTimerCtrlInit(void);
-
-
-/**
- * @ingroup IxTimerCtrl
- *
- * @fn ixTimerCtrlShow( void )
- *
- * @brief Display the status of the Timer Control Component. 
- * @return void
- * @note Displays a list of running timers.
- * This function is not re-entrant. This function does not suspend the calling thread.
- */
-PUBLIC void
-ixTimerCtrlShow( void );
-
-#endif  /* IXTIMERCTRL_H */
-
diff --git a/arch/arm/cpu/ixp/npe/include/IxTypes.h b/arch/arm/cpu/ixp/npe/include/IxTypes.h
deleted file mode 100644
index c4c5a2d..0000000
--- a/arch/arm/cpu/ixp/npe/include/IxTypes.h
+++ /dev/null
@@ -1,86 +0,0 @@
-/**
- * @file IxTypes.h (Replaced by OSAL)
- *
- * @date 28-NOV-2001
-
- * @brief This file contains basic types used by the IXP400 software
- *
- * Design Notes:
- *    This file shall only include fundamental types and definitions to be
- *    shared by all the IXP400 components.
- *    Please DO NOT add component-specific types here.
- *
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- * 
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- * 
- * @par
- * -- End of Copyright Notice --
- */
-
-/**
- * @defgroup IxTypes IXP400 Types (IxTypes) 
- *
- * @brief Basic data types used by the IXP400 project
- *
- * @{
- */
-
-#ifndef IxTypes_H
-
-#ifndef __doxygen_HIDE
-
-#define IxTypes_H
-
-#endif /* __doxygen_HIDE */
-
-
-/* WR51880: Undefined data types workaround for backward compatibility */
-#ifdef __linux
-#ifndef __INCvxTypesOldh
-typedef int (*FUNCPTR)(void);
-typedef int STATUS;
-#define OK (0)
-#define ERROR (-1)
-#endif
-#endif
-
-#include "IxOsalBackward.h"
-
-#endif /* IxTypes_H */
-
-/**
- * @} addtogroup IxTypes
- */
diff --git a/arch/arm/cpu/ixp/npe/include/IxUART.h b/arch/arm/cpu/ixp/npe/include/IxUART.h
deleted file mode 100644
index 03a4444..0000000
--- a/arch/arm/cpu/ixp/npe/include/IxUART.h
+++ /dev/null
@@ -1,458 +0,0 @@
-/** 
- * @file IxUART.h
- *
- * @date 12-OCT-01
- *
- * @brief Public header for the Intel IXP400 internal UART, generic driver.
- * 
- * Design Notes:
- * This driver allows you to perform the following functions: 
- *	Device Initialization,
- *	send/receive characters.
- *
- * Perform Uart IOCTL for the following:
- *	Set/Get the current baud rate,
- *	set parity,
- *	set the number of Stop bits,
- *	set the character Length (5,6,7,8),
- *	enable/disable Hardware flow control.
- *
- * Only Polled mode is supported for now.
- *    
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- * 
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- * 
- * @par
- * -- End of Copyright Notice --
-*/
-
-/**
- * @defgroup IxUARTAccAPI IXP400 UART Access (IxUARTAcc) API
- *
- * @brief IXP400 UARTAcc Driver Public API
- * 
- * @{
- */
-
-
-/* Defaults */
-
-/**
- * @defgroup DefaultDefines Defines for Default Values
- *
- * @brief Default values which can be used for UART configuration
- *
- * @sa ixUARTDev
- */
-
-/**
- * @def IX_UART_DEF_OPTS
- *
- * @brief The default hardware options to set the UART to -
- * no flow control, 8 bit word, 1 stop bit, no parity 
- *
- * @ingroup DefaultDefines
- */
-#define IX_UART_DEF_OPTS (CLOCAL | CS8)
-
-/**
- * @def IX_UART_DEF_XMIT
- *
- * @brief The default UART FIFO size - must be no bigger than 64
- *
- * @ingroup DefaultDefines
- */
-#define IX_UART_DEF_XMIT 64
-
-/**
- * @def IX_UART_DEF_BAUD
- *
- * @brief The default UART baud rate - 9600
- *
- * @ingroup DefaultDefines
- */
-#define IX_UART_DEF_BAUD 9600
-
-/**
- * @def IX_UART_MIN_BAUD
- *
- * @brief The minimum UART baud rate - 9600
- *
- * @ingroup DefaultDefines
- */
-#define IX_UART_MIN_BAUD 9600
-
-/**
- * @def IX_UART_MAX_BAUD
- *
- * @brief The maximum UART baud rate - 926100
- *
- * @ingroup DefaultDefines
- */
-#define IX_UART_MAX_BAUD 926100
-
-/**
- * @def IX_UART_XTAL
- *
- * @brief The UART clock speed
- *
- * @ingroup DefaultDefines
- */
-#define IX_UART_XTAL 14745600
-
-
-
-/* IOCTL commands (Request codes) */
-
-/**
- * @defgroup IoctlCommandDefines Defines for IOCTL Commands
- *
- * @brief IOCTL Commands (Request codes) which can be used
- *        with @ref ixUARTIoctl
- */
-
-
-/**
- * @ingroup IoctlCommandDefines
- *
- * @def IX_BAUD_SET
- *
- * @brief Set the baud rate
- */
-#define IX_BAUD_SET	0
-
-/**
- * @ingroup IoctlCommandDefines
- *
- * @def IX_BAUD_GET
- *
- * @brief Get the baud rate
- */
-#define IX_BAUD_GET	1
-
-/**
- * @ingroup IoctlCommandDefines
- * @def IX_MODE_SET
- * @brief Set the UART mode of operation
- */
-#define IX_MODE_SET	2
-
-/**
- * @ingroup IoctlCommandDefines
- *
- * @def IX_MODE_GET
- *
- * @brief Get the current UART mode of operation
- */
-#define IX_MODE_GET	3
-
-/**
- * @ingroup IoctlCommandDefines
- *
- * @def IX_OPTS_SET
- *
- * @brief Set the UART device options
- */
-#define IX_OPTS_SET	4
-
-/**
- * @ingroup IoctlCommandDefines
- *
- * @def IX_OPTS_GET
- *
- * @brief Get the UART device options
- */
-#define IX_OPTS_GET	5
-
-/**
- * @ingroup IoctlCommandDefines
- *
- * @def IX_STATS_GET
- *
- * @brief Get the UART statistics
- */
-#define IX_STATS_GET	6
-
-
-/* POSIX style ioctl arguments */
-
-/**
- * @defgroup IoctlArgDefines Defines for IOCTL Arguments
- *
- * @brief POSIX style IOCTL arguments which can be used
- *        with @ref ixUARTIoctl
- *
- * @sa ixUARTMode
- */
-
-
-/**
- * @ingroup IoctlArgDefines
- *
- * @def CLOCAL
- *
- * @brief Software flow control
- */
-#ifdef CLOCAL
-#undef CLOCAL
-#endif
-#define CLOCAL		0x1
-
-/**
- * @ingroup IoctlArgDefines
- *
- * @def CREAD
- *
- * @brief Enable interrupt receiver
- */
-#ifdef CREAD
-#undef CREAD
-#endif
-#define CREAD		0x2
-
-/**
- * @ingroup IoctlArgDefines
- *
- * @def CSIZE
- *
- * @brief Characters size
- */
-#ifdef CSIZE
-#undef CSIZE
-#endif
-#define CSIZE		0xc
-
-/**
- * @ingroup IoctlArgDefines
- *
- * @def CS5
- *
- * @brief 5 bits
- */
-#ifdef CS5
-#undef CS5
-#endif
-#define CS5		0x0
-
-/**
- * @ingroup IoctlArgDefines
- *
- * @def CS6
- *
- * @brief 6 bits
- */
-#ifdef CS6
-#undef CS6
-#endif
-#define CS6		0x4
-
-/**
- * @ingroup IoctlArgDefines
- *
- * @def CS7
- *
- * @brief 7 bits
- */
-#ifdef CS7
-#undef CS7
-#endif
-#define CS7		0x8
-
-/**
- * @ingroup IoctlArgDefines
- *
- * @def CS8
- *
- * @brief 8 bits
- */
-#ifdef CS8
-#undef CS8
-#endif
-#define CS8		0xc
-
-/**
- * @ingroup IoctlArgDefines
- *
- * @def STOPB
- *
- * @brief Send two stop bits (else one)
- */
-#define STOPB		0x20
-
-/**
- * @ingroup IoctlArgDefines
- *
- * @def PARENB
- *
- * @brief Parity detection enabled (else disabled)
- */
-#ifdef PARENB
-#undef PARENB
-#endif
-#define PARENB		0x40
-
-/**
- * @ingroup IoctlArgDefines
- *
- * @def PARODD
- *
- * @brief Odd parity  (else even)
- */
-#ifdef PARODD
-#undef PARODD
-#endif
-#define PARODD		0x80
-
-/**
- * @enum ixUARTMode
- * @brief The mode to set to UART to.
- */
-typedef enum
-{
-    INTERRUPT=0,	/**< Interrupt mode */
-    POLLED,		/**< Polled mode */
-    LOOPBACK		/**< Loopback mode */
-} ixUARTMode;
-
-/**
- * @struct ixUARTStats
- * @brief Statistics for the UART.
- */
-typedef struct
-{
-    UINT32  rxCount;
-    UINT32  txCount;	
-    UINT32  overrunErr;
-    UINT32  parityErr;
-    UINT32  framingErr;
-    UINT32  breakErr;
-} ixUARTStats;
-
-/**
- * @struct ixUARTDev
- * @brief Device descriptor for the UART.
- */
-typedef struct
-{
-    UINT8 *addr;	/**< device base address */
-    ixUARTMode mode;	/**< interrupt, polled or loopback */
-    int baudRate;	/**< baud rate */
-    int freq;		/**< UART clock frequency */     
-    int options;	/**< hardware options */
-    int fifoSize;	/**< FIFO xmit size */
-
-    ixUARTStats   stats;	/**< device statistics */
-} ixUARTDev;
-
-/**
- * @ingroup IxUARTAccAPI
- *
- * @fn IX_STATUS ixUARTInit(ixUARTDev* pUART)
- * 
- * @param pUART	@ref ixUARTDev [in] - pointer to UART structure describing our device.
- * 
- * @brief Initialise the UART. This puts the chip in a quiescent state.
- * 
- * @pre The base address for the UART must contain a valid value.
- *      Also the baud rate and hardware options must contain sensible values
- *      otherwise the defaults will be used as defined in ixUART.h
- *
- * @post UART is initialized and ready to send and receive data.
- *
- * @note This function should only be called once per device.
- *
- * @retval IX_SUCCESS - UART device successfully initialised.
- * @retval IX_FAIL - Critical error, device not initialised.
- ***************************************************************************/
-PUBLIC IX_STATUS ixUARTInit(ixUARTDev* pUART);
-
-/**
- * @ingroup IxUARTAccAPI
- *
- * @fn IX_STATUS ixUARTPollOutput(ixUARTDev* pUART, int outChar)
- *
- * @param pUART @ref ixUARTDev [out] - pointer to UART structure describing our device.
- * @param outChar int [out] - character to transmit.
- *
- * @brief Transmit a character in polled mode.
- *
- * @pre UART device must be initialised.
- *
- * @retval IX_SUCCESS - character was successfully transmitted.
- * @retval IX_FAIL - output buffer is full (try again).
- ***************************************************************************/
-PUBLIC IX_STATUS ixUARTPollOutput(ixUARTDev* pUART, int outChar);
-
-/**
- * @ingroup IxUARTAccAPI
- *
- * @fn IX_STATUS ixUARTPollInput(ixUARTDev* pUART, char *inChar)
- *
- * @param pUART	@ref ixUARTDev [in] - pointer to UART structure describing our device.
- * @param *inChar char [in] - character read from the device.
- *
- * @brief Receive a character in polled mode.
- *
- * @pre UART device must be initialised.
- *
- * @retval IX_SUCCESS - character was successfully read.
- * @retval IX_FAIL - input buffer empty (try again).
- ***************************************************************************/
-PUBLIC IX_STATUS ixUARTPollInput(ixUARTDev* pUART, char *inChar);
-
-/**
- * @ingroup IxUARTAccAPI
- *
- * @fn IX_STATUS ixUARTIoctl(ixUARTDev* pUART, int cmd, void* arg)
- *
- * @param pUART	@ref ixUARTDev [in] - pointer to UART structure describing our device.
- * @param cmd int [in] - an ioctl request code.
- * @param arg void* [in] - optional argument used to set the device mode,
- *	 baud rate, and hardware options.
- *
- * @brief Perform I/O control routines on the device.
- *
- * @retval IX_SUCCESS - requested feature was set/read successfully.
- * @retval IX_FAIL - error setting/reading the requested feature.
- *
- * @sa IoctlCommandDefines
- * @sa IoctlArgDefines
- ***************************************************************************/    
-PUBLIC IX_STATUS ixUARTIoctl(ixUARTDev* pUART, int cmd, void* arg);
-
-/**
- * @} defgroup IxUARTAcc
- */
diff --git a/arch/arm/cpu/ixp/npe/include/IxVersionId.h b/arch/arm/cpu/ixp/npe/include/IxVersionId.h
deleted file mode 100644
index 27796ed..0000000
--- a/arch/arm/cpu/ixp/npe/include/IxVersionId.h
+++ /dev/null
@@ -1,155 +0,0 @@
-/**
- * @file IxVersionId.h
- *
- * @date 22-Aug-2002
- *
- * @brief This file contains the IXP400 Software version identifier
- *
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- * 
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- * 
- * @par
- * -- End of Copyright Notice --
- */
-
-/**
- * @defgroup IxVersionId IXP400 Version ID (IxVersionId)
- *
- * @brief Version Identifiers
- *
- * @{
- */
-
-#ifndef IXVERSIONID_H
-#define IXVERSIONID_H
-
-/**
- * @brief Version Identifier String
- *
- * This string will be updated with each customer release of the IXP400
- * Software.
- */
-#define IX_VERSION_ID "2_0"
-
-/**
- * This string will be updated with each customer release of the IXP400
- * ADSL driver package.
- */
-#define IX_VERSION_ADSL_ID "1_12"
-
-
-/**
- * This string will be updated with each customer release of the IXP400
- * USB Client driver package.
- */
-#define IX_VERSION_USBRNDIS_ID "1_9"
-
-/**
- * This string will be updated with each customer release of the IXP400
- * I2C Linux driver package.
- */
-#define IX_VERSION_I2C_LINUX_ID "1_0"
-
-/**
- * @brief Linux Ethernet Driver Patch Version Identifier String
- *
- * This string will be updated with each release of Linux Ethernet Patch
- */
-#define LINUX_ETHERNET_DRIVER_PATCH_ID "1_4"
-
-/**
- * @brief Linux Integration Patch Version Identifier String
- *
- * This String will be updated with each release of Linux Integration Patch
- */
-#define LINUX_INTEGRATION_PATCH_ID "1_3"
-
-/**
- * @brief Linux Ethernet Readme version Identifier String
- *
- * This string will be updated with each release of Linux Ethernet Readme
- */
-#define LINUX_ETHERNET_README_ID "1_3"
-
-/**
- * @brief Linux Integration Readme version Identifier String
- *
- * This string will be updated with each release of Linux Integration Readme
- */
-
-#define LINUX_INTEGRATION_README_ID "1_3"
-
-/**
- * @brief Linux I2C driver Readme version Identifier String
- *
- * This string will be updated with each release of Linux I2C Driver Readme
- */
-#define LINUX_I2C_DRIVER_README_ID "1_0"
-
-/**
- * @brief ixp425_eth_update_nf_bridge.patch version Identifier String
- *
- * This string will be updated with each release of ixp425_eth_update_nf_bridge.
-patch
- *
- */
-
-#define IXP425_ETH_UPDATE_NF_BRIDGE_ID "1_3"
-
-/**
- * @brief Internal Release Identifier String
- *
- * This string will be updated with each internal release (SQA drop)
- * of the IXP400 Software.
- */
-#define IX_VERSION_INTERNAL_ID "SQA3_5"
-
-/**
- * @brief Compatible Tornado Version Identifier
- */
-#define IX_VERSION_COMPATIBLE_TORNADO "Tornado2_2_1-PNE2_0"
-
-/**
- * @brief Compatible Linux Version Identifier
- */
-#define IX_VERSION_COMPATIBLE_LINUX "MVL3_1"
-
-
-#endif /* IXVERSIONID_H */
-
-/**
- * @} addtogroup IxVersionId
- */
diff --git a/arch/arm/cpu/ixp/npe/include/ix_error.h b/arch/arm/cpu/ixp/npe/include/ix_error.h
deleted file mode 100644
index d32ace2..0000000
--- a/arch/arm/cpu/ixp/npe/include/ix_error.h
+++ /dev/null
@@ -1,66 +0,0 @@
-/**
- * ============================================================================
- * = COPYRIGHT
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- * 
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- * 
- * @par
- * -- End of Copyright Notice --
- * = PRODUCT
- *      Intel(r) IXP425 Software Release
- *
- * = FILENAME
- *      ix_error.h (Replaced by OSAL)
- *
- * = DESCRIPTION
- *      This file will describe the basic error type and support functions that
- *      will be used by the IXA SDK Framework API.
- *
- * = AUTHOR
- *      Intel Corporation
- *
- * = CHANGE HISTORY
- *      4/22/2002 4:19:03 PM - creation time 
- * ============================================================================
- */
-
-#if !defined(__IX_ERROR_H__)
-#define __IX_ERROR_H__
-
-#include "IxOsalBackward.h"
-
-#endif /* end !defined(__IX_ERROR_H__) */
-
diff --git a/arch/arm/cpu/ixp/npe/include/ix_macros.h b/arch/arm/cpu/ixp/npe/include/ix_macros.h
deleted file mode 100644
index 53f5942..0000000
--- a/arch/arm/cpu/ixp/npe/include/ix_macros.h
+++ /dev/null
@@ -1,266 +0,0 @@
-/**
- * ============================================================================
- * = COPYRIGHT
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- * 
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- * 
- * @par
- * -- End of Copyright Notice --
- * = PRODUCT
- *      Intel(r) IXP425 Software Release
- *
- * = FILENAME
- *      ix_macros.h
- *
- * = DESCRIPTION
- *      This file will define the basic preprocessor macros that are going to be used
- *      the IXA SDK Framework API.
- *
- * = AUTHOR
- *      Intel Corporation
- *
- * = CHANGE HISTORY
- *      4/22/2002 4:41:05 PM - creation time 
- * ============================================================================
- */
-
-#if !defined(__IX_MACROS_H__)
-#define __IX_MACROS_H__
-
-
-#if defined(__cplusplus)
-extern "C"
-{
-#endif /* end defined(__cplusplus) */
-
-
-/**
- * MACRO NAME: IX_BIT_FIELD_MASK16
- *
- * DESCRIPTION: Builds the mask required to extract the bit field from a 16 bit unsigned integer value.
- *
- * @Param:  - IN arg_FieldLSBBit an unsigned integer value representing the position of the least significant
- *          bit of the bit field.
- * @Param:  - IN arg_FieldMSBBit an unsigned integer value representing the position of the most significant
- *          bit of the bit field.
- *
- * @Return: Returns a 16 bit mask that will extract the bit field from a 16 bit unsigned integer value.
- */
-#define IX_BIT_FIELD_MASK16( \
-                             arg_FieldLSBBit, \
-                             arg_FieldMSBBit \
-                            ) \
-                            ((ix_bit_mask16)((((ix_uint16)1 << (arg_FieldMSBBit + 1 - arg_FieldLSBBit)) - \
-                            (ix_uint16)1) << arg_FieldLSBBit))
-
-
-
-/**
- * MACRO NAME: IX_GET_BIT_FIELD16
- *
- * DESCRIPTION: Extracts a bit field from 16 bit unsigned integer. The returned value is normalized in
- *          in the sense that will be right aligned.
- *
- * @Param:  - IN arg_PackedData16 a 16 bit unsigned integer that contains the bit field of interest.
- * @Param:  - IN arg_FieldLSBBit an unsigned integer value representing the position of the least significant
- *          bit of the bit field.
- * @Param:  - IN arg_FieldMSBBit an unsigned integer value representing the position of the most significant
- *          bit of the bit field.
- *
- * @Return: Returns the value of the bit field. The value can be from 0 to (1 << (arg_FieldMSBBit + 1 -
- *          arg_FieldLSBBit)) - 1.
- */
-#define IX_GET_BIT_FIELD16( \
-                            arg_PackedData16, \
-                            arg_FieldLSBBit, \
-                            arg_FieldMSBBit \
-                          ) \
-                          (((ix_uint16)(arg_PackedData16) & IX_BIT_FIELD_MASK16(arg_FieldLSBBit, arg_FieldMSBBit)) >> \
-                             arg_FieldLSBBit)
-
-
-/**
- * MACRO NAME: IX_MAKE_BIT_FIELD16
- *
- * DESCRIPTION: This macro will create a temporary 16 bit value with the bit field
- *          desired set to the desired value.
- *
- * @Param:  - IN arg_BitFieldValue is the new value of the bit field. The value can be from 0 to 
- *          (1 << (arg_FieldMSBBit + 1 - arg_FieldLSBBit)) - 1.
- * @Param:  - IN arg_FieldLSBBit an unsigned integer value representing the position of the least significant
- *          bit of the bit field.
- * @Param:  - IN arg_FieldMSBBit an unsigned integer value representing the position of the most significant
- *          bit of the bit field.
- * 
- * @Return: Returns a temporary ix_uint16 value that has the bit field set to the appropriate value.
- */
-#define IX_MAKE_BIT_FIELD16( \
-                             arg_BitFieldValue, \
-                             arg_FieldLSBBit, \
-                             arg_FieldMSBBit \
-                           ) \
-                           (((ix_uint16)(arg_BitFieldValue) << arg_FieldLSBBit) & \
-                           IX_BIT_FIELD_MASK16(arg_FieldLSBBit, arg_FieldMSBBit))
-                                 
-/**
- * MACRO NAME: IX_SET_BIT_FIELD16
- *
- * DESCRIPTION: Sets a new value for a bit field from a 16 bit unsigned integer.
- *
- * @Param:  - IN arg_PackedData16 a 16 bit unsigned integer that contains the bit field of interest.
- * @Param:  - IN arg_BitFieldValue is the new vale of the bit field. The value can be from 0 to 
- *          (1 << (arg_FieldMSBBit + 1 - arg_FieldLSBBit)) - 1.
- * @Param:  - IN arg_FieldLSBBit an unsigned integer value representing the position of the least significant
- *          bit of the bit field.
- * @Param:  - IN arg_FieldMSBBit an unsigned integer value representing the position of the most significant
- *          bit of the bit field.
- *
- * @Return: Returns the updated value of arg_PackedData16.
- */
-#define IX_SET_BIT_FIELD16( \
-                            arg_PackedData16, \
-                            arg_BitFieldValue, \
-                            arg_FieldLSBBit, \
-                            arg_FieldMSBBit \
-                          ) \
-                          (arg_PackedData16 = (((ix_uint16)(arg_PackedData16) & \
-                          ~(IX_BIT_FIELD_MASK16(arg_FieldLSBBit, arg_FieldMSBBit))) | \
-                          IX_MAKE_BIT_FIELD16(arg_BitFieldValue, arg_FieldLSBBit, arg_FieldMSBBit))) 
-
-
-/**
- * MACRO NAME: IX_BIT_FIELD_MASK32
- *
- * DESCRIPTION: Builds the mask required to extract the bit field from a 32 bit unsigned integer value.
- *
- * @Param:  - IN arg_FieldLSBBit an unsigned integer value representing the position of the least significant
- *          bit of the bit field.
- * @Param:  - IN arg_FieldMSBBit an unsigned integer value representing the position of the most significant
- *          bit of the bit field.
- *
- * @Return: Returns a 32 bit mask that will extract the bit field from a 32 bit unsigned integer value.
- */
-#define IX_BIT_FIELD_MASK32( \
-                             arg_FieldLSBBit, \
-                             arg_FieldMSBBit \
-                           ) \
-                           ((ix_bit_mask32)((((ix_uint32)1 << (arg_FieldMSBBit + 1 - arg_FieldLSBBit)) - \
-                           (ix_uint32)1) << arg_FieldLSBBit))
-
-
-
-/**
- * MACRO NAME: IX_GET_BIT_FIELD32
- *
- * DESCRIPTION: Extracts a bit field from 32 bit unsigned integer. The returned value is normalized in
- *          in the sense that will be right aligned.
- *
- * @Param:  - IN arg_PackedData32 a 32 bit unsigned integer that contains the bit field of interest.
- * @Param:  - IN arg_FieldLSBBit an unsigned integer value representing the position of the least significant
- *          bit of the bit field.
- * @Param:  - IN arg_FieldMSBBit an unsigned integer value representing the position of the most significant
- *          bit of the bit field.
- *
- * @Return: Returns the value of the bit field. The value can be from 0 to (1 << (arg_FieldMSBBit + 1 -
- *          arg_FieldLSBBit)) - 1.
- */
-#define IX_GET_BIT_FIELD32( \
-                            arg_PackedData32, \
-                            arg_FieldLSBBit, \
-                            arg_FieldMSBBit \
-                          ) \
-                          (((ix_uint32)(arg_PackedData32) & IX_BIT_FIELD_MASK32(arg_FieldLSBBit, arg_FieldMSBBit)) >> \
-                             arg_FieldLSBBit)
-
-
-
-
-/**
- * MACRO NAME: IX_MAKE_BIT_FIELD32
- *
- * DESCRIPTION: This macro will create a temporary 32 bit value with the bit field
- *          desired set to the desired value.
- *
- * @Param:  - IN arg_BitFieldValue is the new value of the bit field. The value can be from 0 to 
- *          (1 << (arg_FieldMSBBit + 1 - arg_FieldLSBBit)) - 1.
- * @Param:  - IN arg_FieldLSBBit an unsigned integer value representing the position of the least significant
- *          bit of the bit field.
- * @Param:  - IN arg_FieldMSBBit an unsigned integer value representing the position of the most significant
- *          bit of the bit field.
- * 
- * @Return: Returns a temporary ix_uint32 value that has the bit field set to the appropriate value.
- */
-#define IX_MAKE_BIT_FIELD32( \
-                             arg_BitFieldValue, \
-                             arg_FieldLSBBit, \
-                             arg_FieldMSBBit \
-                           ) \
-                           (((ix_uint32)(arg_BitFieldValue) << arg_FieldLSBBit) & \
-                           IX_BIT_FIELD_MASK32(arg_FieldLSBBit, arg_FieldMSBBit))
-                            
-                                
-/**
- * MACRO NAME: IX_SET_BIT_FIELD32
- *
- * DESCRIPTION: Sets a new value for a bit field from a 32 bit unsigned integer.
- *
- * @Param:  - IN arg_PackedData32 a 32 bit unsigned integer that contains the bit field of interest.
- * @Param:  - IN arg_BitFieldValue is the new value of the bit field. The value can be from 0 to 
- *          (1 << (arg_FieldMSBBit + 1 - arg_FieldLSBBit)) - 1.
- * @Param:  - IN arg_FieldLSBBit an unsigned integer value representing the position of the least significant
- *          bit of the bit field.
- * @Param:  - IN arg_FieldMSBBit an unsigned integer value representing the position of the most significant
- *          bit of the bit field.
- *
- * @Return: Returns the updated value of arg_PackedData32.
- */
-#define IX_SET_BIT_FIELD32( \
-                            arg_PackedData32, \
-                            arg_BitFieldValue, \
-                            arg_FieldLSBBit, \
-                            arg_FieldMSBBit \
-                          ) \
-                          (arg_PackedData32 = (((ix_uint32)(arg_PackedData32) & \
-                          ~(IX_BIT_FIELD_MASK32(arg_FieldLSBBit, arg_FieldMSBBit))) | \
-                          IX_MAKE_BIT_FIELD32(arg_BitFieldValue, arg_FieldLSBBit, arg_FieldMSBBit))) 
-
-
-
-#if defined(__cplusplus)
-}
-#endif /* end defined(__cplusplus) */
-
-#endif /* end !defined(__IX_MACROS_H__) */
diff --git a/arch/arm/cpu/ixp/npe/include/ix_os_type.h b/arch/arm/cpu/ixp/npe/include/ix_os_type.h
deleted file mode 100644
index 8575096..0000000
--- a/arch/arm/cpu/ixp/npe/include/ix_os_type.h
+++ /dev/null
@@ -1,65 +0,0 @@
-/**
- * ============================================================================
- * = COPYRIGHT
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- * 
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- * 
- * @par
- * -- End of Copyright Notice --
- * = PRODUCT
- *      Intel(r) IXP425 Software Release
- *
- * = FILENAME
- *      ix_os_type.h (Replaced by OSAL)
- *
- * = DESCRIPTION
- *      This file provides protable symbol definitions for the current OS type.
- *
- * = AUTHOR
- *      Intel Corporation
- *
- * = CHANGE HISTORY
- *      4/22/2002 4:43:30 PM - creation time 
- * ============================================================================
- */
-
-#if !defined(__IX_OS_TYPE_H__)
-#define __IX_OS_TYPE_H__
-
-#include "IxOsalBackward.h"
-
-#endif /* end !defined(__IX_OS_TYPE_H__) */
-
diff --git a/arch/arm/cpu/ixp/npe/include/ix_ossl.h b/arch/arm/cpu/ixp/npe/include/ix_ossl.h
deleted file mode 100644
index b59f7d0..0000000
--- a/arch/arm/cpu/ixp/npe/include/ix_ossl.h
+++ /dev/null
@@ -1,160 +0,0 @@
-/**
- * ============================================================================
- * = COPYRIGHT
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- * 
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- * 
- * @par
- * -- End of Copyright Notice --
- * = PRODUCT
- *      Intel(r) IXP425 Software Release
- *
- * = LIBRARY
- *      OSSL - Operating System Services  Library
- *
- * = MODULE
- *      OSSL  Abstraction layer header file
- *
- * = FILENAME
- *       ix_ossl.h (Replaced by OSAL)
- *
- * = DESCRIPTION
- *   This file contains the prototypes of OS-independent wrapper
- *   functions which allow the programmer not to be tied to a specific
- *   operating system. The OSSL functions can be divided into three classes:
- *
- *   1) synchronization-related wrapper functions around thread system calls
- *   2) thread-related wrapper functions around thread calls
- *   3) transactor/workbench osapi calls -- defined in osApi.h
- *
- *   Both 1 and 2 classes of functions provide Thread Management, Thread 
- *   Synchronization, Mutual Exclusion and  Timer primitives. Namely, 
- *   creation and deletion functions as well as the standard "wait" and
- *   "exit". Additionally, a couple of utility functions which enable to 
- *   pause the execution of a thread are also provided.
- *
- *   The 3rd class provides a  slew of other OSAPI functions to handle
- *   Transactor/WorkBench OS calls.
- *
- *
- *   OSSL Thread APIs:
- *             The OSSL thread functions that allow for thread creation,
- *             get thread id, thread deletion and set thread priroity.
- *
- *             ix_ossl_thread_create
- *             ix_ossl_thread_get_id
- *             ix_ossl_thread_exit
- *             ix_ossl_thread_kill
- *             ix_ossl_thread_set_priority
- *             ix_ossl_thread__delay
- * 
- *   OSSL Semaphore APIs:
- *             The OSSL semaphore functions that allow for initialization,
- *             posting, waiting and deletion of semaphores.
- *
- *             ix_ossl_sem_init
- *             ix_ossl_sem_fini
- *             ix_ossl_sem_take
- *             ix_ossl_sem_give
- *             ix_ossl_sem_flush
- *
- *   OSSL Mutex APIs:
- *             The OSSL wrapper functions that allow for initialization,
- *             posting, waiting and deletion of mutexes.
- *
- *             ix_ossl_mutex_init
- *             ix_ossl_mutex_fini
- *             ix_ossl_mutex_lock
- *             ix_ossl_mutex_unlock
- *
- *   OSSL Timer APIs:
- *     	       The timer APIs provide sleep and get time functions.
- *
- *             ix_ossl_sleep
- *             ix_ossl_sleep_tick
- *             ix_ossl_time_get
- * 
- *   OSAPIs for Transactor/WorkBench:
- *             These OSAPI functions are used for transator OS calls. 
- *             They are defined in osApi.h. 
- *
- *             Sem_Init 			
- *             Sem_Destroy 		
- *             Sem_Wait 			
- *             Sem_Wait			
- *             Thread_Create		
- *             Thread_Cancel 		
- *             Thread_SetPriority 		
- *             delayMs 			
- *             delayTick			
- *             
- *
- *
- **********************************************************************
- *      
- *
- * = AUTHOR
- *      Intel Corporation
- *
- * = ACKNOWLEDGEMENTS
- *      
- *
- * = CREATION TIME
- *      1/8/2002 1:53:42 PM
- *
- * = CHANGE HISTORY
- *   02/22/2002 : Renamed osapi.h os_api.h
- *                Moved OS header file includes from OSSL.h to os_api.h
- *                Moved OS specific datatypes to os_api.h 
- *                Modified data types, macros and functions as per
- *                'C' coding guidelines.
- *
- *
- * ============================================================================
- */
-
-#ifndef _IX_OSSL_H
-#ifndef __doxygen_hide
-#define _IX_OSSL_H
-#endif /* __doxygen_hide */
-
-#include "IxOsalBackward.h"
- 
-#endif /* _IX_OSSL_H */
-
-/**
- * @} defgroup IxOSSL
- */
diff --git a/arch/arm/cpu/ixp/npe/include/ix_symbols.h b/arch/arm/cpu/ixp/npe/include/ix_symbols.h
deleted file mode 100644
index f7bb029..0000000
--- a/arch/arm/cpu/ixp/npe/include/ix_symbols.h
+++ /dev/null
@@ -1,106 +0,0 @@
-/**
- * ============================================================================
- * = COPYRIGHT
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- * 
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- * 
- * @par
- * -- End of Copyright Notice --
- * = PRODUCT
- *      Intel(r) IXP425 Software Release
- *
- * = FILENAME
- *      ix_symbols.h
- *
- * = DESCRIPTION
- *      This file declares all the global preprocessor symbols required by 
- *      the IXA SDK Framework API.
- *
- * = AUTHOR
- *      Intel Corporation
- *
- * = CHANGE HISTORY
- *      4/23/2002 10:41:13 AM - creation time 
- * ============================================================================
- */
-
-#if !defined(__IX_SYMBOLS_H__)
-#define __IX_SYMBOLS_H__
-
-
-#if defined(__cplusplus)
-extern "C"
-{
-#endif /* end defined(__cplusplus) */
-
-/**
- * The IX_EXPORT_FUNCTION symbol will be used for compilation on different platforms.
- * We are planning to provide a simulation version of the library that should work
- * with the Transactor rather than the hardware. This implementation will be done on
- * WIN32 in the form of a DLL that will need to export functions and symbols.
- */
-#if (_IX_OS_TYPE_ == _IX_OS_WIN32_)
-#    if defined(_IX_LIB_INTERFACE_IMPLEMENTATION_)
-#        define IX_EXPORT_FUNCTION __declspec( dllexport )
-#    elif defined(_IX_LIB_INTERFACE_IMPORT_DLL_)
-#        define IX_EXPORT_FUNCTION __declspec( dllimport )
-#    else
-#        define IX_EXPORT_FUNCTION extern 
-#    endif
-#elif (_IX_OS_TYPE_ == _IX_OS_WINCE_)
-#    define IX_EXPORT_FUNCTION __declspec(dllexport)
-#else
-#    define IX_EXPORT_FUNCTION  extern
-#endif
-
-
-/**
- * This symbols should be defined when we want to build for a multithreaded environment
- */
-#define _IX_MULTI_THREADED_     1
-    
-
-/**
- * This symbol should be defined in the case we to buils for a multithreaded environment
- * but we want that our modules to work as if they are used in a single threaded environment.
- */
-/* #define _IX_RM_EXPLICIT_SINGLE_THREADED_    1  */
-
-#if defined(__cplusplus)
-}
-#endif /* end defined(__cplusplus) */
-
-#endif /* end !defined(__IX_SYMBOLS_H__) */
diff --git a/arch/arm/cpu/ixp/npe/include/ix_types.h b/arch/arm/cpu/ixp/npe/include/ix_types.h
deleted file mode 100644
index fc7b1e9..0000000
--- a/arch/arm/cpu/ixp/npe/include/ix_types.h
+++ /dev/null
@@ -1,208 +0,0 @@
-/**
- * ============================================================================
- * = COPYRIGHT
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- * 
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- * 
- * @par
- * -- End of Copyright Notice --
- * = PRODUCT
- *      Intel(r) IXP425 Software Release
- *
- * = FILENAME
- *      ix_types.h
- *
- * = DESCRIPTION
- *      This file will define generic types that will guarantee the protability
- *      between different architectures and compilers. It should be used the entire
- *      IXA SDK Framework API.
- *
- * = AUTHOR
- *      Intel Corporation
- *
- * = CHANGE HISTORY
- *      4/22/2002 4:44:17 PM - creation time 
- * ============================================================================
- */
-
-#if !defined(__IX_TYPES_H__)
-#define __IX_TYPES_H__
-
-
-#if defined(__cplusplus)
-extern "C"
-{
-#endif /* end defined(__cplusplus) */
-
-
-/**
- * Define generic integral data types that will guarantee the size.
- */
-
-/**
- * TYPENAME: ix_int8
- * 
- * DESCRIPTION: This type defines an 8 bit signed integer value.
- *
- */
-typedef signed char ix_int8;
-
-
-/**
- * TYPENAME: ix_uint8
- * 
- * DESCRIPTION: This type defines an 8 bit unsigned integer value.
- *
- */
-typedef unsigned char ix_uint8;
-
-
-/**
- * TYPENAME: ix_int16
- * 
- * DESCRIPTION: This type defines an 16 bit signed integer value.
- *
- */
-typedef signed short int ix_int16;
-
-
-/**
- * TYPENAME: ix_uint16
- * 
- * DESCRIPTION: This type defines an 16 bit unsigned integer value.
- *
- */
-typedef unsigned short int ix_uint16;
-
-
-/**
- * TYPENAME: ix_int32
- * 
- * DESCRIPTION: This type defines an 32 bit signed integer value.
- *
- */
-typedef signed int ix_int32;
-
-
-/**
- * TYPENAME: ix_uint32
- * 
- * DESCRIPTION: This type defines an 32 bit unsigned integer value.
- *
- */
-#ifndef __wince
-typedef unsigned int ix_uint32;
-#else
-typedef unsigned long ix_uint32;
-#endif
-
-/**
- * TYPENAME: ix_int64
- * 
- * DESCRIPTION: This type defines an 64 bit signed integer value.
- *
- */
-#ifndef __wince
-__extension__ typedef signed long long int ix_int64;
-#endif
-
-/**
- * TYPENAME: ix_uint64
- * 
- * DESCRIPTION: This type defines an 64 bit unsigned integer value.
- *
- */
-#ifndef __wince
-__extension__ typedef unsigned long long int ix_uint64;
-#endif
-
-
-/**
- * TYPENAME: ix_bit_mask8
- * 
- * DESCRIPTION: This is a generic type for a 8 bit mask. 
- */
-typedef ix_uint8 ix_bit_mask8;
-
-
-/**
- * TYPENAME: ix_bit_mask16
- * 
- * DESCRIPTION: This is a generic type for a 16 bit mask. 
- */
-typedef ix_uint16 ix_bit_mask16;
-
-
-/**
- * TYPENAME: ix_bit_mask32
- * 
- * DESCRIPTION: This is a generic type for a 32 bit mask. 
- */
-typedef ix_uint32 ix_bit_mask32;
-
-
-/**
- * TYPENAME: ix_bit_mask64
- * 
- * DESCRIPTION: This is a generic type for a 64 bit mask. 
- */
-#ifndef __wince
-typedef ix_uint64 ix_bit_mask64;
-#endif
-
-
-/**
- * TYPENAME: ix_handle
- * 
- * DESCRIPTION: This type defines a generic handle.
- *
- */
-typedef ix_uint32 ix_handle;
-
-
-
-/**
- * DESCRIPTION: This symbol defines a NULL handle
- *
- */
-#define IX_NULL_HANDLE   ((ix_handle)0) 
-
-
-#if defined(__cplusplus)
-}
-#endif /* end defined(__cplusplus) */
-
-#endif /* end !defined(__IX_TYPES_H__) */
diff --git a/arch/arm/cpu/ixp/npe/include/npe.h b/arch/arm/cpu/ixp/npe/include/npe.h
deleted file mode 100644
index b5eef86..0000000
--- a/arch/arm/cpu/ixp/npe/include/npe.h
+++ /dev/null
@@ -1,90 +0,0 @@
-/*
- * (C) Copyright 2005
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef NPE_H
-#define NPE_H
-
-/*
- * defines...
- */
-#define CONFIG_SYS_NPE_NUMS		1
-#ifdef CONFIG_HAS_ETH1
-#undef CONFIG_SYS_NPE_NUMS
-#define CONFIG_SYS_NPE_NUMS		2
-#endif
-
-#define NPE_NUM_PORTS		3
-#define ACTIVE_PORTS		1
-
-#define NPE_PKT_SIZE		1600
-
-#define CONFIG_DEVS_ETH_INTEL_NPE_MAX_RX_DESCRIPTORS	64
-#define CONFIG_DEVS_ETH_INTEL_NPE_MAX_TX_DESCRIPTORS	2
-
-#define NPE_MBUF_POOL_SIZE					\
-	((CONFIG_DEVS_ETH_INTEL_NPE_MAX_TX_DESCRIPTORS +	\
-	  CONFIG_DEVS_ETH_INTEL_NPE_MAX_RX_DESCRIPTORS) *	\
-	 sizeof(IX_OSAL_MBUF) * ACTIVE_PORTS)
-
-#define NPE_PKT_POOL_SIZE					\
-	((CONFIG_DEVS_ETH_INTEL_NPE_MAX_TX_DESCRIPTORS +	\
-	  CONFIG_DEVS_ETH_INTEL_NPE_MAX_RX_DESCRIPTORS) *	\
-	 NPE_PKT_SIZE * ACTIVE_PORTS)
-
-#define NPE_MEM_POOL_SIZE (NPE_MBUF_POOL_SIZE + NPE_PKT_POOL_SIZE)
-
-#define PHY_AUTONEGOTIATE_TIMEOUT 4000	/* 4000 ms autonegotiate timeout */
-
-/*
- * structs...
- */
-struct npe {
-	u8			active;           /* NPE active				*/
-	u8			eth_id;           /* IX_ETH_PORT_1 or IX_ETH_PORT_2	*/
-	u8			phy_no;           /* which PHY (0 - 31)			*/
-	u8			mac_address[6];
-
-	IX_OSAL_MBUF		*rxQHead;
-	IX_OSAL_MBUF		*txQHead;
-
-	u8			*tx_pkts;
-	u8			*rx_pkts;
-	IX_OSAL_MBUF		*rx_mbufs;
-	IX_OSAL_MBUF		*tx_mbufs;
-
-	int			print_speed;
-
-	int			rx_read;
-	int			rx_write;
-	int			rx_len[PKTBUFSRX];
-};
-
-/*
- * prototypes...
- */
-extern int npe_miiphy_read (const char *devname, unsigned char addr,
-			    unsigned char reg, unsigned short *value);
-extern int npe_miiphy_write (const char *devname, unsigned char addr,
-			     unsigned char reg, unsigned short value);
-
-#endif /* ifndef NPE_H */
diff --git a/arch/arm/cpu/ixp/npe/include/os_datatypes.h b/arch/arm/cpu/ixp/npe/include/os_datatypes.h
deleted file mode 100644
index 4387b2a..0000000
--- a/arch/arm/cpu/ixp/npe/include/os_datatypes.h
+++ /dev/null
@@ -1,82 +0,0 @@
-/**
- * ============================================================================
- * = COPYRIGHT
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- * 
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- * 
- * @par
- * -- End of Copyright Notice --
- * = PRODUCT
- *      Intel(r) IXP425 Software Release
- *
- * = LIBRARY
- *      OSSL - Operating System Services  Library
- *
- * = MODULE
- *      OS Specific Data Types header file
- *
- * = FILENAME
- *       OSSL.h (Replaced by OSAL)
- *
- * = DESCRIPTION
- *   This file  contains definitions and encapsulations for OS specific data types. These
- *   encapsulated  data types are  used by OSSL header files and OS API functions.
- *
- *
- **********************************************************************
- *      
- *
- * = AUTHOR
- *      Intel Corporation
- *
- * = AKNOWLEDGEMENTS
- *      
- *
- * = CREATION TIME
- *      1/8/2002 1:53:42 PM
- *
- * = CHANGE HISTORY
- 
- * ============================================================================
- */
-
-#ifndef _OS_DATATYPES_H
-#define _OS_DATATYPES_H
-
-#include "IxOsalBackward.h"
-
-#endif /* _OS_DATATYPES_H */
-
diff --git a/arch/arm/cpu/ixp/npe/miiphy.c b/arch/arm/cpu/ixp/npe/miiphy.c
deleted file mode 100644
index a04779a..0000000
--- a/arch/arm/cpu/ixp/npe/miiphy.c
+++ /dev/null
@@ -1,120 +0,0 @@
-/*-----------------------------------------------------------------------------+
-  |   This source code is dual-licensed.  You may use it under the terms of the
-  |   GNU General Public License version 2, or under the license below.
-  |
-  |	  This source code has been made available to you by IBM on an AS-IS
-  |	  basis.  Anyone receiving this source is licensed under IBM
-  |	  copyrights to use it in any way he or she deems fit, including
-  |	  copying it, modifying it, compiling it, and redistributing it either
-  |	  with or without modifications.  No license under IBM patents or
-  |	  patent applications is to be implied by the copyright license.
-  |
-  |	  Any user of this software should understand that IBM cannot provide
-  |	  technical support for this software and will not be responsible for
-  |	  any consequences resulting from the use of this software.
-  |
-  |	  Any person who transfers this source code or any derivative work
-  |	  must include the IBM copyright notice, this paragraph, and the
-  |	  preceding two paragraphs in the transferred software.
-  |
-  |	  COPYRIGHT   I B M   CORPORATION 1995
-  |	  LICENSED MATERIAL  -	PROGRAM PROPERTY OF I B M
-  +-----------------------------------------------------------------------------*/
-/*-----------------------------------------------------------------------------+
-  |
-  |  File Name:	 miiphy.c
-  |
-  |  Function:	 This module has utilities for accessing the MII PHY through
-  |	       the EMAC3 macro.
-  |
-  |  Author:	 Mark Wisner
-  |
-  |  Change Activity-
-  |
-  |  Date	 Description of Change					     BY
-  |  ---------	 ---------------------					     ---
-  |  05-May-99	 Created						     MKW
-  |  01-Jul-99	 Changed clock setting of sta_reg from 66MHz to 50MHz to
-  |		 better match OPB speed. Also modified delay times.	     JWB
-  |  29-Jul-99	 Added Full duplex support				     MKW
-  |  24-Aug-99	 Removed printf from dp83843_duplex()			     JWB
-  |  19-Jul-00	 Ported to esd cpci405					     sr
-  |  23-Dec-03	 Ported from miiphy.c to 440GX Travis Sawyer		     TBS
-  |		 <travis.sawyer@sandburst.com>
-  |
-  +-----------------------------------------------------------------------------*/
-
-#include <common.h>
-#include <miiphy.h>
-#include "IxOsal.h"
-#include "IxEthAcc.h"
-#include "IxEthAcc_p.h"
-#include "IxEthAccMac_p.h"
-#include "IxEthAccMii_p.h"
-
-/***********************************************************/
-/* Dump out to the screen PHY regs			   */
-/***********************************************************/
-
-void miiphy_dump (char *devname, unsigned char addr)
-{
-	unsigned long i;
-	unsigned short data;
-
-
-	for (i = 0; i < 0x1A; i++) {
-		if (miiphy_read (devname, addr, i, &data)) {
-			printf ("read error for reg %lx\n", i);
-			return;
-		}
-		printf ("Phy reg %lx ==> %4x\n", i, data);
-
-		/* jump to the next set of regs */
-		if (i == 0x07)
-			i = 0x0f;
-
-	}			/* end for loop */
-}				/* end dump */
-
-
-/***********************************************************/
-/* (Re)start autonegotiation				   */
-/***********************************************************/
-int phy_setup_aneg (char *devname, unsigned char addr)
-{
-	unsigned short ctl, adv;
-
-	/* Setup standard advertise */
-	miiphy_read (devname, addr, MII_ADVERTISE, &adv);
-	adv |= (LPA_LPACK | LPA_RFAULT | LPA_100BASE4 |
-		LPA_100FULL | LPA_100HALF | LPA_10FULL |
-		LPA_10HALF);
-	miiphy_write (devname, addr, MII_ADVERTISE, adv);
-
-	/* Start/Restart aneg */
-	miiphy_read (devname, addr, MII_BMCR, &ctl);
-	ctl |= (BMCR_ANENABLE | BMCR_ANRESTART);
-	miiphy_write (devname, addr, MII_BMCR, ctl);
-
-	return 0;
-}
-
-
-int npe_miiphy_read (const char *devname, unsigned char addr,
-		     unsigned char reg, unsigned short *value)
-{
-	u16 val;
-
-	ixEthAccMiiReadRtn(addr, reg, &val);
-	*value = val;
-
-	return 0;
-}				/* phy_read */
-
-
-int npe_miiphy_write (const char *devname, unsigned char addr,
-		      unsigned char reg, unsigned short value)
-{
-	ixEthAccMiiWriteRtn(addr, reg, value);
-	return 0;
-}				/* phy_write */
diff --git a/arch/arm/cpu/ixp/npe/npe.c b/arch/arm/cpu/ixp/npe/npe.c
deleted file mode 100644
index 857bcad..0000000
--- a/arch/arm/cpu/ixp/npe/npe.c
+++ /dev/null
@@ -1,676 +0,0 @@
-/*
- * (C) Copyright 2005-2006
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#if 0
-#define DEBUG		/* define for debug output */
-#endif
-
-#include <config.h>
-#include <common.h>
-#include <net.h>
-#include <miiphy.h>
-#include <malloc.h>
-#include <asm/processor.h>
-#include <asm/arch-ixp/ixp425.h>
-
-#include <IxOsal.h>
-#include <IxEthAcc.h>
-#include <IxEthDB.h>
-#include <IxNpeDl.h>
-#include <IxQMgr.h>
-#include <IxNpeMh.h>
-#include <ix_ossl.h>
-#include <IxFeatureCtrl.h>
-
-#include <npe.h>
-
-static IxQMgrDispatcherFuncPtr qDispatcherFunc = NULL;
-static int npe_exists[NPE_NUM_PORTS];
-static int npe_used[NPE_NUM_PORTS];
-
-/* A little extra so we can align to cacheline. */
-static u8 npe_alloc_pool[NPE_MEM_POOL_SIZE + CONFIG_SYS_CACHELINE_SIZE - 1];
-static u8 *npe_alloc_end;
-static u8 *npe_alloc_free;
-
-static void *npe_alloc(int size)
-{
-	static int count = 0;
-	void *p = NULL;
-
-	size = (size + (CONFIG_SYS_CACHELINE_SIZE-1)) & ~(CONFIG_SYS_CACHELINE_SIZE-1);
-	count++;
-
-	if ((npe_alloc_free + size) < npe_alloc_end) {
-		p = npe_alloc_free;
-		npe_alloc_free += size;
-	} else {
-		printf("npe_alloc: failed (count=%d, size=%d)!\n", count, size);
-	}
-	return p;
-}
-
-/* Not interrupt safe! */
-static void mbuf_enqueue(IX_OSAL_MBUF **q, IX_OSAL_MBUF *new)
-{
-	IX_OSAL_MBUF *m = *q;
-
-	IX_OSAL_MBUF_NEXT_PKT_IN_CHAIN_PTR(new) = NULL;
-
-	if (m) {
-		while(IX_OSAL_MBUF_NEXT_PKT_IN_CHAIN_PTR(m))
-			m = IX_OSAL_MBUF_NEXT_PKT_IN_CHAIN_PTR(m);
-		IX_OSAL_MBUF_NEXT_PKT_IN_CHAIN_PTR(m) = new;
-	} else
-		*q = new;
-}
-
-/* Not interrupt safe! */
-static IX_OSAL_MBUF *mbuf_dequeue(IX_OSAL_MBUF **q)
-{
-	IX_OSAL_MBUF *m = *q;
-	if (m)
-		*q = IX_OSAL_MBUF_NEXT_PKT_IN_CHAIN_PTR(m);
-	return m;
-}
-
-static void reset_tx_mbufs(struct npe* p_npe)
-{
-	IX_OSAL_MBUF *m;
-	int i;
-
-	p_npe->txQHead = NULL;
-
-	for (i = 0; i < CONFIG_DEVS_ETH_INTEL_NPE_MAX_TX_DESCRIPTORS; i++) {
-		m = &p_npe->tx_mbufs[i];
-
-		memset(m, 0, sizeof(*m));
-
-		IX_OSAL_MBUF_MDATA(m) = (void *)&p_npe->tx_pkts[i * NPE_PKT_SIZE];
-		IX_OSAL_MBUF_MLEN(m) = IX_OSAL_MBUF_PKT_LEN(m) = NPE_PKT_SIZE;
-		mbuf_enqueue(&p_npe->txQHead, m);
-	}
-}
-
-static void reset_rx_mbufs(struct npe* p_npe)
-{
-	IX_OSAL_MBUF *m;
-	int i;
-
-	p_npe->rxQHead = NULL;
-
-	HAL_DCACHE_INVALIDATE(p_npe->rx_pkts, NPE_PKT_SIZE *
-			      CONFIG_DEVS_ETH_INTEL_NPE_MAX_RX_DESCRIPTORS);
-
-	for (i = 0; i < CONFIG_DEVS_ETH_INTEL_NPE_MAX_RX_DESCRIPTORS; i++) {
-		m = &p_npe->rx_mbufs[i];
-
-		memset(m, 0, sizeof(*m));
-
-		IX_OSAL_MBUF_MDATA(m) = (void *)&p_npe->rx_pkts[i * NPE_PKT_SIZE];
-		IX_OSAL_MBUF_MLEN(m) = IX_OSAL_MBUF_PKT_LEN(m) = NPE_PKT_SIZE;
-
-		if(ixEthAccPortRxFreeReplenish(p_npe->eth_id, m) != IX_SUCCESS) {
-			printf("ixEthAccPortRxFreeReplenish failed for port %d\n", p_npe->eth_id);
-			break;
-		}
-	}
-}
-
-static void init_rx_mbufs(struct npe* p_npe)
-{
-	p_npe->rxQHead = NULL;
-
-	p_npe->rx_pkts = npe_alloc(NPE_PKT_SIZE *
-				   CONFIG_DEVS_ETH_INTEL_NPE_MAX_RX_DESCRIPTORS);
-	if (p_npe->rx_pkts == NULL) {
-		printf("alloc of packets failed.\n");
-		return;
-	}
-
-	p_npe->rx_mbufs = (IX_OSAL_MBUF *)
-		npe_alloc(sizeof(IX_OSAL_MBUF) *
-			  CONFIG_DEVS_ETH_INTEL_NPE_MAX_RX_DESCRIPTORS);
-	if (p_npe->rx_mbufs == NULL) {
-		printf("alloc of mbufs failed.\n");
-		return;
-	}
-
-	reset_rx_mbufs(p_npe);
-}
-
-static void init_tx_mbufs(struct npe* p_npe)
-{
-	p_npe->tx_pkts = npe_alloc(NPE_PKT_SIZE *
-				   CONFIG_DEVS_ETH_INTEL_NPE_MAX_TX_DESCRIPTORS);
-	if (p_npe->tx_pkts == NULL) {
-		printf("alloc of packets failed.\n");
-		return;
-	}
-
-	p_npe->tx_mbufs = (IX_OSAL_MBUF *)
-		npe_alloc(sizeof(IX_OSAL_MBUF) *
-			  CONFIG_DEVS_ETH_INTEL_NPE_MAX_TX_DESCRIPTORS);
-	if (p_npe->tx_mbufs == NULL) {
-		printf("alloc of mbufs failed.\n");
-		return;
-	}
-
-	reset_tx_mbufs(p_npe);
-}
-
-/* Convert IX_ETH_PORT_n to IX_NPEMH_NPEID_NPEx */
-static int __eth_to_npe(int eth_id)
-{
-	switch(eth_id) {
-	case IX_ETH_PORT_1:
-		return IX_NPEMH_NPEID_NPEB;
-
-	case IX_ETH_PORT_2:
-		return IX_NPEMH_NPEID_NPEC;
-
-	case IX_ETH_PORT_3:
-		return IX_NPEMH_NPEID_NPEA;
-	}
-	return 0;
-}
-
-/* Poll the CSR machinery. */
-static void npe_poll(int eth_id)
-{
-	if (qDispatcherFunc != NULL) {
-		ixNpeMhMessagesReceive(__eth_to_npe(eth_id));
-		(*qDispatcherFunc)(IX_QMGR_QUELOW_GROUP);
-	}
-}
-
-/* ethAcc RX callback */
-static void npe_rx_callback(u32 cbTag, IX_OSAL_MBUF *m, IxEthAccPortId portid)
-{
-	struct npe* p_npe = (struct npe *)cbTag;
-
-	if (IX_OSAL_MBUF_MLEN(m) > 0) {
-		mbuf_enqueue(&p_npe->rxQHead, m);
-
-		if (p_npe->rx_write == ((p_npe->rx_read-1) & (PKTBUFSRX-1))) {
-			debug("Rx overflow: rx_write=%d rx_read=%d\n",
-			      p_npe->rx_write, p_npe->rx_read);
-		} else {
-			debug("Received message #%d (len=%d)\n", p_npe->rx_write,
-			      IX_OSAL_MBUF_MLEN(m));
-			memcpy((void *)NetRxPackets[p_npe->rx_write], IX_OSAL_MBUF_MDATA(m),
-			       IX_OSAL_MBUF_MLEN(m));
-			p_npe->rx_len[p_npe->rx_write] = IX_OSAL_MBUF_MLEN(m);
-			p_npe->rx_write++;
-			if (p_npe->rx_write == PKTBUFSRX)
-				p_npe->rx_write = 0;
-
-#ifdef CONFIG_PRINT_RX_FRAMES
-			{
-				u8 *ptr = IX_OSAL_MBUF_MDATA(m);
-				int i;
-
-				for (i=0; i<60; i++) {
-					debug("%02x ", *ptr++);
-				}
-				debug("\n");
-			}
-#endif
-		}
-
-		m = mbuf_dequeue(&p_npe->rxQHead);
-	} else {
-		debug("Received frame with length 0!!!\n");
-		m = mbuf_dequeue(&p_npe->rxQHead);
-	}
-
-	/* Now return mbuf to NPE */
-	IX_OSAL_MBUF_MLEN(m) = IX_OSAL_MBUF_PKT_LEN(m) = NPE_PKT_SIZE;
-	IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR(m) = NULL;
-	IX_OSAL_MBUF_FLAGS(m) = 0;
-
-	if(ixEthAccPortRxFreeReplenish(p_npe->eth_id, m) != IX_SUCCESS) {
-		debug("npe_rx_callback: Error returning mbuf.\n");
-	}
-}
-
-/* ethAcc TX callback */
-static void npe_tx_callback(u32 cbTag, IX_OSAL_MBUF *m)
-{
-	struct npe* p_npe = (struct npe *)cbTag;
-
-	debug("%s\n", __FUNCTION__);
-
-	IX_OSAL_MBUF_MLEN(m) = IX_OSAL_MBUF_PKT_LEN(m) = NPE_PKT_SIZE;
-	IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR(m) = NULL;
-	IX_OSAL_MBUF_FLAGS(m) = 0;
-
-	mbuf_enqueue(&p_npe->txQHead, m);
-}
-
-
-static int npe_set_mac_address(struct eth_device *dev)
-{
-	struct npe *p_npe = (struct npe *)dev->priv;
-	IxEthAccMacAddr npeMac;
-
-	debug("%s\n", __FUNCTION__);
-
-	/* Set MAC address */
-	memcpy(npeMac.macAddress, dev->enetaddr, 6);
-
-	if (ixEthAccPortUnicastMacAddressSet(p_npe->eth_id, &npeMac) != IX_ETH_ACC_SUCCESS) {
-		printf("Error setting unicast address! %02x:%02x:%02x:%02x:%02x:%02x\n",
-		       npeMac.macAddress[0], npeMac.macAddress[1],
-		       npeMac.macAddress[2], npeMac.macAddress[3],
-		       npeMac.macAddress[4], npeMac.macAddress[5]);
-		return 0;
-	}
-
-	return 1;
-}
-
-/* Boot-time CSR library initialization. */
-static int npe_csr_load(void)
-{
-	int i;
-
-	if (ixQMgrInit() != IX_SUCCESS) {
-		debug("Error initialising queue manager!\n");
-		return 0;
-	}
-
-	ixQMgrDispatcherLoopGet(&qDispatcherFunc);
-
-	if(ixNpeMhInitialize(IX_NPEMH_NPEINTERRUPTS_YES) != IX_SUCCESS) {
-		printf("Error initialising NPE Message handler!\n");
-		return 0;
-	}
-
-	if (npe_used[IX_ETH_PORT_1] && npe_exists[IX_ETH_PORT_1] &&
-	    ixNpeDlNpeInitAndStart(IX_NPEDL_NPEIMAGE_NPEB_ETH_LEARN_FILTER_SPAN_FIREWALL_VLAN_QOS)
-	    != IX_SUCCESS) {
-		printf("Error downloading firmware to NPE-B!\n");
-		return 0;
-	}
-
-	if (npe_used[IX_ETH_PORT_2] && npe_exists[IX_ETH_PORT_2] &&
-	    ixNpeDlNpeInitAndStart(IX_NPEDL_NPEIMAGE_NPEC_ETH_LEARN_FILTER_SPAN_FIREWALL_VLAN_QOS)
-	    != IX_SUCCESS) {
-		printf("Error downloading firmware to NPE-C!\n");
-		return 0;
-	}
-
-	/* don't need this for U-Boot */
-	ixFeatureCtrlSwConfigurationWrite(IX_FEATURECTRL_ETH_LEARNING, FALSE);
-
-	if (ixEthAccInit() != IX_ETH_ACC_SUCCESS) {
-		printf("Error initialising Ethernet access driver!\n");
-		return 0;
-	}
-
-	for (i = 0; i < IX_ETH_ACC_NUMBER_OF_PORTS; i++) {
-		if (!npe_used[i] || !npe_exists[i])
-			continue;
-		if (ixEthAccPortInit(i) != IX_ETH_ACC_SUCCESS) {
-			printf("Error initialising Ethernet port%d!\n", i);
-		}
-		if (ixEthAccTxSchedulingDisciplineSet(i, FIFO_NO_PRIORITY) != IX_ETH_ACC_SUCCESS) {
-			printf("Error setting scheduling discipline for port %d.\n", i);
-		}
-		if (ixEthAccPortRxFrameAppendFCSDisable(i) != IX_ETH_ACC_SUCCESS) {
-			printf("Error disabling RX FCS for port %d.\n", i);
-		}
-		if (ixEthAccPortTxFrameAppendFCSEnable(i) != IX_ETH_ACC_SUCCESS) {
-			printf("Error enabling TX FCS for port %d.\n", i);
-		}
-	}
-
-	return 1;
-}
-
-static int npe_init(struct eth_device *dev, bd_t * bis)
-{
-	struct npe *p_npe = (struct npe *)dev->priv;
-	int i;
-	u16 reg_short;
-	int speed;
-	int duplex;
-
-	debug("%s: 1\n", __FUNCTION__);
-
-	miiphy_read (dev->name, p_npe->phy_no, MII_BMSR, &reg_short);
-
-	/*
-	 * Wait if PHY is capable of autonegotiation and autonegotiation is not complete
-	 */
-	if ((reg_short & BMSR_ANEGCAPABLE) && !(reg_short & BMSR_ANEGCOMPLETE)) {
-		puts ("Waiting for PHY auto negotiation to complete");
-		i = 0;
-		while (!(reg_short & BMSR_ANEGCOMPLETE)) {
-			/*
-			 * Timeout reached ?
-			 */
-			if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
-				puts (" TIMEOUT !\n");
-				break;
-			}
-
-			if ((i++ % 1000) == 0) {
-				putc ('.');
-				miiphy_read (dev->name, p_npe->phy_no, MII_BMSR, &reg_short);
-			}
-			udelay (1000);	/* 1 ms */
-		}
-		puts (" done\n");
-		udelay (500000);	/* another 500 ms (results in faster booting) */
-	}
-
-	speed = miiphy_speed (dev->name, p_npe->phy_no);
-	duplex = miiphy_duplex (dev->name, p_npe->phy_no);
-
-	if (p_npe->print_speed) {
-		p_npe->print_speed = 0;
-		printf ("ENET Speed is %d Mbps - %s duplex connection\n",
-			(int) speed, (duplex == HALF) ? "HALF" : "FULL");
-	}
-
-	npe_alloc_end = npe_alloc_pool + sizeof(npe_alloc_pool);
-	npe_alloc_free = (u8 *)(((unsigned)npe_alloc_pool +
-				 CONFIG_SYS_CACHELINE_SIZE - 1) & ~(CONFIG_SYS_CACHELINE_SIZE - 1));
-
-	/* initialize mbuf pool */
-	init_rx_mbufs(p_npe);
-	init_tx_mbufs(p_npe);
-
-	if (ixEthAccPortRxCallbackRegister(p_npe->eth_id, npe_rx_callback,
-					   (u32)p_npe) != IX_ETH_ACC_SUCCESS) {
-		printf("can't register RX callback!\n");
-		return -1;
-	}
-
-	if (ixEthAccPortTxDoneCallbackRegister(p_npe->eth_id, npe_tx_callback,
-					       (u32)p_npe) != IX_ETH_ACC_SUCCESS) {
-		printf("can't register TX callback!\n");
-		return -1;
-	}
-
-	npe_set_mac_address(dev);
-
-	if (ixEthAccPortEnable(p_npe->eth_id) != IX_ETH_ACC_SUCCESS) {
-		printf("can't enable port!\n");
-		return -1;
-	}
-
-	p_npe->active = 1;
-
-	return 0;
-}
-
-#if 0 /* test-only: probably have to deal with it when booting linux (for a clean state) */
-/* Uninitialize CSR library. */
-static void npe_csr_unload(void)
-{
-	ixEthAccUnload();
-	ixEthDBUnload();
-	ixNpeMhUnload();
-	ixQMgrUnload();
-}
-
-/* callback which is used by ethAcc to recover RX buffers when stopping */
-static void npe_rx_stop_callback(u32 cbTag, IX_OSAL_MBUF *m, IxEthAccPortId portid)
-{
-	debug("%s\n", __FUNCTION__);
-}
-
-/* callback which is used by ethAcc to recover TX buffers when stopping */
-static void npe_tx_stop_callback(u32 cbTag, IX_OSAL_MBUF *m)
-{
-	debug("%s\n", __FUNCTION__);
-}
-#endif
-
-static void npe_halt(struct eth_device *dev)
-{
-	struct npe *p_npe = (struct npe *)dev->priv;
-	int i;
-
-	debug("%s\n", __FUNCTION__);
-
-	/* Delay to give time for recovery of mbufs */
-	for (i = 0; i < 100; i++) {
-		npe_poll(p_npe->eth_id);
-		udelay(100);
-	}
-
-#if 0 /* test-only: probably have to deal with it when booting linux (for a clean state) */
-	if (ixEthAccPortRxCallbackRegister(p_npe->eth_id, npe_rx_stop_callback,
-					   (u32)p_npe) != IX_ETH_ACC_SUCCESS) {
-		debug("Error registering rx callback!\n");
-	}
-
-	if (ixEthAccPortTxDoneCallbackRegister(p_npe->eth_id, npe_tx_stop_callback,
-					       (u32)p_npe) != IX_ETH_ACC_SUCCESS) {
-		debug("Error registering tx callback!\n");
-	}
-
-	if (ixEthAccPortDisable(p_npe->eth_id) != IX_ETH_ACC_SUCCESS) {
-		debug("npe_stop: Error disabling NPEB!\n");
-	}
-
-	/* Delay to give time for recovery of mbufs */
-	for (i = 0; i < 100; i++) {
-		npe_poll(p_npe->eth_id);
-		udelay(10000);
-	}
-
-	/*
-	 * For U-Boot only, we are probably launching Linux or other OS that
-	 * needs a clean slate for its NPE library.
-	 */
-#if 0 /* test-only */
-	for (i = 0; i < IX_ETH_ACC_NUMBER_OF_PORTS; i++) {
-		if (npe_used[i] && npe_exists[i])
-			if (ixNpeDlNpeStopAndReset(__eth_to_npe(i)) != IX_SUCCESS)
-				printf("Failed to stop and reset NPE B.\n");
-	}
-#endif
-
-#endif
-	p_npe->active = 0;
-}
-
-
-static int npe_send(struct eth_device *dev, volatile void *packet, int len)
-{
-	struct npe *p_npe = (struct npe *)dev->priv;
-	u8 *dest;
-	int err;
-	IX_OSAL_MBUF *m;
-
-	debug("%s\n", __FUNCTION__);
-	m = mbuf_dequeue(&p_npe->txQHead);
-	dest = IX_OSAL_MBUF_MDATA(m);
-	IX_OSAL_MBUF_PKT_LEN(m) = IX_OSAL_MBUF_MLEN(m) = len;
-	IX_OSAL_MBUF_NEXT_PKT_IN_CHAIN_PTR(m) = NULL;
-
-	memcpy(dest, (char *)packet, len);
-
-	if ((err = ixEthAccPortTxFrameSubmit(p_npe->eth_id, m, IX_ETH_ACC_TX_DEFAULT_PRIORITY))
-	    != IX_ETH_ACC_SUCCESS) {
-		printf("npe_send: Can't submit frame. err[%d]\n", err);
-		mbuf_enqueue(&p_npe->txQHead, m);
-		return 0;
-	}
-
-#ifdef DEBUG_PRINT_TX_FRAMES
-	{
-		u8 *ptr = IX_OSAL_MBUF_MDATA(m);
-		int i;
-
-		for (i=0; i<IX_OSAL_MBUF_MLEN(m); i++) {
-			printf("%02x ", *ptr++);
-		}
-		printf(" (tx-len=%d)\n", IX_OSAL_MBUF_MLEN(m));
-	}
-#endif
-
-	npe_poll(p_npe->eth_id);
-
-	return len;
-}
-
-static int npe_rx(struct eth_device *dev)
-{
-	struct npe *p_npe = (struct npe *)dev->priv;
-
-	debug("%s\n", __FUNCTION__);
-	npe_poll(p_npe->eth_id);
-
-	debug("%s: rx_write=%d rx_read=%d\n", __FUNCTION__, p_npe->rx_write, p_npe->rx_read);
-	while (p_npe->rx_write != p_npe->rx_read) {
-		debug("Reading message #%d\n", p_npe->rx_read);
-		NetReceive(NetRxPackets[p_npe->rx_read], p_npe->rx_len[p_npe->rx_read]);
-		p_npe->rx_read++;
-		if (p_npe->rx_read == PKTBUFSRX)
-			p_npe->rx_read = 0;
-	}
-
-	return 0;
-}
-
-int npe_initialize(bd_t * bis)
-{
-	static int virgin = 0;
-	struct eth_device *dev;
-	int eth_num = 0;
-	struct npe *p_npe = NULL;
-	uchar enetaddr[6];
-
-	for (eth_num = 0; eth_num < CONFIG_SYS_NPE_NUMS; eth_num++) {
-
-		/* See if we can actually bring up the interface, otherwise, skip it */
-#ifdef CONFIG_HAS_ETH1
-		if (eth_num == 1) {
-			if (!eth_getenv_enetaddr("eth1addr", enetaddr))
-				continue;
-		} else
-#endif
-			if (!eth_getenv_enetaddr("ethaddr", enetaddr))
-				continue;
-
-		/* Allocate device structure */
-		dev = (struct eth_device *)malloc(sizeof(*dev));
-		if (dev == NULL) {
-			printf ("%s: Cannot allocate eth_device %d\n", __FUNCTION__, eth_num);
-			return -1;
-		}
-		memset(dev, 0, sizeof(*dev));
-
-		/* Allocate our private use data */
-		p_npe = (struct npe *)malloc(sizeof(struct npe));
-		if (p_npe == NULL) {
-			printf("%s: Cannot allocate private hw data for eth_device %d",
-			       __FUNCTION__, eth_num);
-			free(dev);
-			return -1;
-		}
-		memset(p_npe, 0, sizeof(struct npe));
-
-		p_npe->eth_id = eth_num;
-		memcpy(dev->enetaddr, enetaddr, 6);
-#ifdef CONFIG_HAS_ETH1
-		if (eth_num == 1)
-			p_npe->phy_no = CONFIG_PHY1_ADDR;
-		else
-#endif
-			p_npe->phy_no = CONFIG_PHY_ADDR;
-
-		sprintf(dev->name, "NPE%d", eth_num);
-		dev->priv = (void *)p_npe;
-		dev->init = npe_init;
-		dev->halt = npe_halt;
-		dev->send = npe_send;
-		dev->recv = npe_rx;
-
-		p_npe->print_speed = 1;
-
-		if (0 == virgin) {
-			virgin = 1;
-
-			if (ixFeatureCtrlDeviceRead() == IX_FEATURE_CTRL_DEVICE_TYPE_IXP42X) {
-				switch (ixFeatureCtrlProductIdRead() & IX_FEATURE_CTRL_SILICON_STEPPING_MASK) {
-				case IX_FEATURE_CTRL_SILICON_TYPE_B0:
-					/*
-					 * If it is B0 Silicon, we only enable port when its corresponding
-					 * Eth Coprocessor is available.
-					 */
-					if (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_ETH0) ==
-					    IX_FEATURE_CTRL_COMPONENT_ENABLED)
-						npe_exists[IX_ETH_PORT_1] = TRUE;
-
-					if (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_ETH1) ==
-					    IX_FEATURE_CTRL_COMPONENT_ENABLED)
-						npe_exists[IX_ETH_PORT_2] = TRUE;
-					break;
-				case IX_FEATURE_CTRL_SILICON_TYPE_A0:
-					/*
-					 * If it is A0 Silicon, we enable both as both Eth Coprocessors
-					 * are available.
-					 */
-					npe_exists[IX_ETH_PORT_1] = TRUE;
-					npe_exists[IX_ETH_PORT_2] = TRUE;
-					break;
-				}
-			} else if (ixFeatureCtrlDeviceRead() == IX_FEATURE_CTRL_DEVICE_TYPE_IXP46X) {
-				if (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_ETH0) ==
-				    IX_FEATURE_CTRL_COMPONENT_ENABLED)
-					npe_exists[IX_ETH_PORT_1] = TRUE;
-
-				if (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_ETH1) ==
-				    IX_FEATURE_CTRL_COMPONENT_ENABLED)
-					npe_exists[IX_ETH_PORT_2] = TRUE;
-			}
-
-			npe_used[IX_ETH_PORT_1] = 1;
-			npe_used[IX_ETH_PORT_2] = 1;
-
-			npe_alloc_end = npe_alloc_pool + sizeof(npe_alloc_pool);
-			npe_alloc_free = (u8 *)(((unsigned)npe_alloc_pool +
-						 CONFIG_SYS_CACHELINE_SIZE - 1)
-						& ~(CONFIG_SYS_CACHELINE_SIZE - 1));
-
-			if (!npe_csr_load())
-				return 0;
-		}
-
-		eth_register(dev);
-
-#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
-		miiphy_register(dev->name, npe_miiphy_read, npe_miiphy_write);
-#endif
-
-	}			/* end for each supported device */
-
-	return 1;
-}
diff --git a/arch/arm/cpu/ixp/start.S b/arch/arm/cpu/ixp/start.S
deleted file mode 100644
index f71a398..0000000
--- a/arch/arm/cpu/ixp/start.S
+++ /dev/null
@@ -1,603 +0,0 @@
-/* vi: set ts=8 sw=8 noet: */
-/*
- *  u-boot - Startup Code for XScale IXP
- *
- * Copyright (C) 2003	Kyle Harris <kharris@nexus-tech.net>
- *
- * Based on startup code example contained in the
- * Intel IXP4xx Programmer's Guide and past u-boot Start.S
- * samples.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <asm-offsets.h>
-#include <config.h>
-#include <version.h>
-#include <asm/arch/ixp425.h>
-
-#define MMU_Control_M  0x001    /* Enable MMU */
-#define MMU_Control_A  0x002    /* Enable address alignment faults */
-#define MMU_Control_C  0x004    /* Enable cache */
-#define MMU_Control_W  0x008    /* Enable write-buffer */
-#define MMU_Control_P  0x010    /* Compatability: 32 bit code */
-#define MMU_Control_D  0x020    /* Compatability: 32 bit data */
-#define MMU_Control_L  0x040    /* Compatability: */
-#define MMU_Control_B  0x080    /* Enable Big-Endian */
-#define MMU_Control_S  0x100    /* Enable system protection */
-#define MMU_Control_R  0x200    /* Enable ROM protection */
-#define MMU_Control_I  0x1000   /* Enable Instruction cache */
-#define MMU_Control_X  0x2000   /* Set interrupt vectors at 0xFFFF0000 */
-#define MMU_Control_Init (MMU_Control_P|MMU_Control_D|MMU_Control_L)
-
-
-/*
- * Macro definitions
- */
-	/* Delay a bit */
-	.macro DELAY_FOR cycles, reg0
-	ldr     \reg0, =\cycles
-	subs    \reg0, \reg0, #1
-	subne   pc,  pc, #0xc
-	.endm
-
-	/* wait for coprocessor write complete */
-	.macro CPWAIT reg
-	mrc  p15,0,\reg,c2,c0,0
-	mov  \reg,\reg
-	sub  pc,pc,#4
-	.endm
-
-.globl _start
-_start: b	reset
-	ldr	pc, _undefined_instruction
-	ldr	pc, _software_interrupt
-	ldr	pc, _prefetch_abort
-	ldr	pc, _data_abort
-	ldr	pc, _not_used
-	ldr	pc, _irq
-	ldr	pc, _fiq
-
-_undefined_instruction: .word undefined_instruction
-_software_interrupt:	.word software_interrupt
-_prefetch_abort:	.word prefetch_abort
-_data_abort:		.word data_abort
-_not_used:		.word not_used
-_irq:			.word irq
-_fiq:			.word fiq
-
-	.balignl 16,0xdeadbeef
-
-
-/*
- * Startup Code (reset vector)
- *
- * do important init only if we don't start from memory!
- * - relocate armboot to ram
- * - setup stack
- * - jump to second stage
- */
-
-.globl _TEXT_BASE
-_TEXT_BASE:
-	.word	CONFIG_SYS_TEXT_BASE
-
-/*
- * These are defined in the board-specific linker script.
- * Subtracting _start from them lets the linker put their
- * relative position in the executable instead of leaving
- * them null.
- */
-.globl _bss_start_ofs
-_bss_start_ofs:
-	.word __bss_start - _start
-
-.globl _bss_end_ofs
-_bss_end_ofs:
-	.word _end - _start
-
-#ifdef CONFIG_USE_IRQ
-/* IRQ stack memory (calculated at run-time) */
-.globl IRQ_STACK_START
-IRQ_STACK_START:
-	.word	0x0badc0de
-
-/* IRQ stack memory (calculated at run-time) */
-.globl FIQ_STACK_START
-FIQ_STACK_START:
-	.word 0x0badc0de
-#endif
-
-/* IRQ stack memory (calculated at run-time) + 8 bytes */
-.globl IRQ_STACK_START_IN
-IRQ_STACK_START_IN:
-	.word	0x0badc0de
-
-/*
- * the actual reset code
- */
-
-reset:
-	/* disable mmu, set big-endian */
-	mov	r0, #0xf8
-	mcr	p15, 0, r0, c1, c0, 0
-	CPWAIT  r0
-
-	/* invalidate I & D caches & BTB */
-	mcr	p15, 0, r0, c7, c7, 0
-	CPWAIT	r0
-
-	/* invalidate I & Data TLB */
-	mcr	p15, 0, r0, c8, c7, 0
-	CPWAIT r0
-
-	/* drain write and fill buffers */
-	mcr	p15, 0, r0, c7, c10, 4
-	CPWAIT	r0
-
-	/* disable write buffer coalescing */
-	mrc	p15, 0, r0, c1, c0, 1
-	orr	r0, r0, #1
-	mcr	p15, 0, r0, c1, c0, 1
-	CPWAIT	r0
-
-	/* set EXP CS0 to the optimum timing */
-	ldr	r1, =CONFIG_SYS_EXP_CS0
-	ldr     r2, =IXP425_EXP_CS0
-	str     r1, [r2]
-
-	/* make sure flash is visible at 0 */
-#if 0
-	ldr	r2, =IXP425_EXP_CFG0
-	ldr     r1, [r2]
-	orr     r1, r1, #0x80000000
-	str     r1, [r2]
-#endif
-	mov	r1, #CONFIG_SYS_SDR_CONFIG
-	ldr     r2, =IXP425_SDR_CONFIG
-	str     r1, [r2]
-
-	/* disable refresh cycles */
-	mov	r1, #0
-	ldr     r3, =IXP425_SDR_REFRESH
-	str	r1, [r3]
-
-	/* send nop command */
-	mov	r1, #3
-	ldr	r4, =IXP425_SDR_IR
-	str	r1, [r4]
-	DELAY_FOR 0x4000, r0
-
-	/* set SDRAM internal refresh val */
-	ldr	r1, =CONFIG_SYS_SDRAM_REFRESH_CNT
-	str     r1, [r3]
-	DELAY_FOR 0x4000, r0
-
-	/* send precharge-all command to close all open banks */
-	mov     r1, #2
-	str     r1, [r4]
-	DELAY_FOR 0x4000, r0
-
-	/* provide 8 auto-refresh cycles */
-	mov     r1, #4
-	mov     r5, #8
-111:    str	r1, [r4]
-	DELAY_FOR 0x100, r0
-	subs	r5, r5, #1
-	bne	111b
-
-	/* set mode register in sdram */
-	mov	r1, #CONFIG_SYS_SDR_MODE_CONFIG
-	str	r1, [r4]
-	DELAY_FOR 0x4000, r0
-
-	/* send normal operation command */
-	mov	r1, #6
-	str	r1, [r4]
-	DELAY_FOR 0x4000, r0
-
-	/* copy */
-	mov     r0, #0
-	mov     r4, r0
-	add     r2, r0, #CONFIG_SYS_MONITOR_LEN
-	mov     r1, #0x10000000
-	mov     r5, r1
-
-    30:
-	ldr     r3, [r0], #4
-	str     r3, [r1], #4
-	cmp     r0, r2
-	bne     30b
-
-	/* invalidate I & D caches & BTB */
-	mcr	p15, 0, r0, c7, c7, 0
-	CPWAIT	r0
-
-	/* invalidate I & Data TLB */
-	mcr	p15, 0, r0, c8, c7, 0
-	CPWAIT r0
-
-	/* drain write and fill buffers */
-	mcr	p15, 0, r0, c7, c10, 4
-	CPWAIT	r0
-
-	/* move flash to 0x50000000 */
-	ldr	r2, =IXP425_EXP_CFG0
-	ldr     r1, [r2]
-	bic     r1, r1, #0x80000000
-	str     r1, [r2]
-
-	nop
-	nop
-	nop
-	nop
-	nop
-	nop
-
-	/* invalidate I & Data TLB */
-	mcr	p15, 0, r0, c8, c7, 0
-	CPWAIT r0
-
-	/* enable I cache */
-	mrc     p15, 0, r0, c1, c0, 0
-	orr     r0, r0, #MMU_Control_I
-	mcr     p15, 0, r0, c1, c0, 0
-	CPWAIT  r0
-
-	mrs	r0,cpsr			/* set the cpu to SVC32 mode	    */
-	bic	r0,r0,#0x1f		/* (superviser mode, M=10011)	    */
-	orr	r0,r0,#0x13
-	msr	cpsr,r0
-
-/* Set stackpointer in internal RAM to call board_init_f */
-call_board_init_f:
-	ldr	sp, =(CONFIG_SYS_INIT_SP_ADDR)
-	bic	sp, sp, #7 /* 8-byte alignment for ABI compliance */
-	ldr	r0,=0x00000000
-	bl	board_init_f
-
-/*------------------------------------------------------------------------------*/
-
-/*
- * void relocate_code (addr_sp, gd, addr_moni)
- *
- * This "function" does not return, instead it continues in RAM
- * after relocating the monitor code.
- *
- */
-	.globl	relocate_code
-relocate_code:
-	mov	r4, r0	/* save addr_sp */
-	mov	r5, r1	/* save addr of gd */
-	mov	r6, r2	/* save addr of destination */
-
-	/* Set up the stack						    */
-stack_setup:
-	mov	sp, r4
-
-	adr	r0, _start
-	cmp	r0, r6
-	beq	clear_bss		/* skip relocation */
-	mov	r1, r6			/* r1 <- scratch for copy_loop */
-	ldr	r3, _bss_start_ofs
-	add	r2, r0, r3		/* r2 <- source end address	    */
-
-copy_loop:
-	ldmia	r0!, {r9-r10}		/* copy from source address [r0]    */
-	stmia	r1!, {r9-r10}		/* copy to   target address [r1]    */
-	cmp	r0, r2			/* until source end address [r2]    */
-	blo	copy_loop
-
-#ifndef CONFIG_PRELOADER
-	/*
-	 * fix .rel.dyn relocations
-	 */
-	ldr	r0, _TEXT_BASE		/* r0 <- Text base */
-	sub	r9, r6, r0		/* r9 <- relocation offset */
-	ldr	r10, _dynsym_start_ofs	/* r10 <- sym table ofs */
-	add	r10, r10, r0		/* r10 <- sym table in FLASH */
-	ldr	r2, _rel_dyn_start_ofs	/* r2 <- rel dyn start ofs */
-	add	r2, r2, r0		/* r2 <- rel dyn start in FLASH */
-	ldr	r3, _rel_dyn_end_ofs	/* r3 <- rel dyn end ofs */
-	add	r3, r3, r0		/* r3 <- rel dyn end in FLASH */
-fixloop:
-	ldr	r0, [r2]		/* r0 <- location to fix up, IN FLASH! */
-	add	r0, r0, r9		/* r0 <- location to fix up in RAM */
-	ldr	r1, [r2, #4]
-	and	r7, r1, #0xff
-	cmp	r7, #23			/* relative fixup? */
-	beq	fixrel
-	cmp	r7, #2			/* absolute fixup? */
-	beq	fixabs
-	/* ignore unknown type of fixup */
-	b	fixnext
-fixabs:
-	/* absolute fix: set location to (offset) symbol value */
-	mov	r1, r1, LSR #4		/* r1 <- symbol index in .dynsym */
-	add	r1, r10, r1		/* r1 <- address of symbol in table */
-	ldr	r1, [r1, #4]		/* r1 <- symbol value */
-	add	r1, r1, r9		/* r1 <- relocated sym addr */
-	b	fixnext
-fixrel:
-	/* relative fix: increase location by offset */
-	ldr	r1, [r0]
-	add	r1, r1, r9
-fixnext:
-	str	r1, [r0]
-	add	r2, r2, #8		/* each rel.dyn entry is 8 bytes */
-	cmp	r2, r3
-	blo	fixloop
-#endif
-
-clear_bss:
-#ifndef CONFIG_PRELOADER
-	ldr	r0, _bss_start_ofs
-	ldr	r1, _bss_end_ofs
-	mov	r4, r6			/* reloc addr */
-	add	r0, r0, r4
-	add	r1, r1, r4
-	mov	r2, #0x00000000		/* clear			    */
-
-clbss_l:str	r2, [r0]		/* clear loop...		    */
-	add	r0, r0, #4
-	cmp	r0, r1
-	bne	clbss_l
-
-	bl coloured_LED_init
-	bl red_LED_on
-#endif
-
-/*
- * We are done. Do not return, instead branch to second part of board
- * initialization, now running from RAM.
- */
-	ldr	r0, _board_init_r_ofs
-	adr	r1, _start
-	add	lr, r0, r1
-	add	lr, lr, r9
-	/* setup parameters for board_init_r */
-	mov	r0, r5		/* gd_t */
-	mov	r1, r6		/* dest_addr */
-	/* jump to it ... */
-	mov	pc, lr
-
-_board_init_r_ofs:
-	.word board_init_r - _start
-
-_rel_dyn_start_ofs:
-	.word __rel_dyn_start - _start
-_rel_dyn_end_ofs:
-	.word __rel_dyn_end - _start
-_dynsym_start_ofs:
-	.word __dynsym_start - _start
-
-/****************************************************************************/
-/*									    */
-/* Interrupt handling							    */
-/*									    */
-/****************************************************************************/
-
-/* IRQ stack frame							    */
-
-#define S_FRAME_SIZE	72
-
-#define S_OLD_R0	68
-#define S_PSR		64
-#define S_PC		60
-#define S_LR		56
-#define S_SP		52
-
-#define S_IP		48
-#define S_FP		44
-#define S_R10		40
-#define S_R9		36
-#define S_R8		32
-#define S_R7		28
-#define S_R6		24
-#define S_R5		20
-#define S_R4		16
-#define S_R3		12
-#define S_R2		8
-#define S_R1		4
-#define S_R0		0
-
-#define MODE_SVC 0x13
-
-	/* use bad_save_user_regs for abort/prefetch/undef/swi ...	    */
-
-	.macro	bad_save_user_regs
-	sub	sp, sp, #S_FRAME_SIZE
-	stmia	sp, {r0 - r12}			/* Calling r0-r12	    */
-	add	r8, sp, #S_PC
-
-	ldr	r2, IRQ_STACK_START_IN
-	ldmia	r2, {r2 - r4}			/* get pc, cpsr, old_r0	    */
-	add	r0, sp, #S_FRAME_SIZE		/* restore sp_SVC	    */
-
-	add	r5, sp, #S_SP
-	mov	r1, lr
-	stmia	r5, {r0 - r4}			/* save sp_SVC, lr_SVC, pc, cpsr, old_r */
-	mov	r0, sp
-	.endm
-
-
-	/* use irq_save_user_regs / irq_restore_user_regs for		     */
-	/* IRQ/FIQ handling						     */
-
-	.macro	irq_save_user_regs
-	sub	sp, sp, #S_FRAME_SIZE
-	stmia	sp, {r0 - r12}			/* Calling r0-r12	     */
-	add	r8, sp, #S_PC
-	stmdb	r8, {sp, lr}^			/* Calling SP, LR	     */
-	str	lr, [r8, #0]			/* Save calling PC	     */
-	mrs	r6, spsr
-	str	r6, [r8, #4]			/* Save CPSR		     */
-	str	r0, [r8, #8]			/* Save OLD_R0		     */
-	mov	r0, sp
-	.endm
-
-	.macro	irq_restore_user_regs
-	ldmia	sp, {r0 - lr}^			@ Calling r0 - lr
-	mov	r0, r0
-	ldr	lr, [sp, #S_PC]			@ Get PC
-	add	sp, sp, #S_FRAME_SIZE
-	subs	pc, lr, #4			@ return & move spsr_svc into cpsr
-	.endm
-
-	.macro get_bad_stack
-	ldr	r13, IRQ_STACK_START_IN		@ setup our mode stack
-
-	str	lr, [r13]			@ save caller lr / spsr
-	mrs	lr, spsr
-	str	lr, [r13, #4]
-
-	mov	r13, #MODE_SVC			@ prepare SVC-Mode
-	msr	spsr_c, r13
-	mov	lr, pc
-	movs	pc, lr
-	.endm
-
-	.macro get_irq_stack			@ setup IRQ stack
-	ldr	sp, IRQ_STACK_START
-	.endm
-
-	.macro get_fiq_stack			@ setup FIQ stack
-	ldr	sp, FIQ_STACK_START
-	.endm
-
-
-/****************************************************************************/
-/*									    */
-/* exception handlers							    */
-/*									    */
-/****************************************************************************/
-
-	.align	5
-undefined_instruction:
-	get_bad_stack
-	bad_save_user_regs
-	bl	do_undefined_instruction
-
-	.align	5
-software_interrupt:
-	get_bad_stack
-	bad_save_user_regs
-	bl	do_software_interrupt
-
-	.align	5
-prefetch_abort:
-	get_bad_stack
-	bad_save_user_regs
-	bl	do_prefetch_abort
-
-	.align	5
-data_abort:
-	get_bad_stack
-	bad_save_user_regs
-	bl	do_data_abort
-
-	.align	5
-not_used:
-	get_bad_stack
-	bad_save_user_regs
-	bl	do_not_used
-
-#ifdef CONFIG_USE_IRQ
-
-	.align	5
-irq:
-	get_irq_stack
-	irq_save_user_regs
-	bl	do_irq
-	irq_restore_user_regs
-
-	.align	5
-fiq:
-	get_fiq_stack
-	irq_save_user_regs		/* someone ought to write a more    */
-	bl	do_fiq			/* effiction fiq_save_user_regs	    */
-	irq_restore_user_regs
-
-#else
-
-	.align	5
-irq:
-	get_bad_stack
-	bad_save_user_regs
-	bl	do_irq
-
-	.align	5
-fiq:
-	get_bad_stack
-	bad_save_user_regs
-	bl	do_fiq
-
-#endif
-
-/****************************************************************************/
-/*                                                                          */
-/* Reset function: Use Watchdog to reset                                    */
-/*                                                                          */
-/****************************************************************************/
-
-	.align	5
-.globl reset_cpu
-
-reset_cpu:
-	ldr	r1, =0x482e
-	ldr     r2, =IXP425_OSWK
-	str     r1, [r2]
-	ldr	r1, =0x0fff
-	ldr     r2, =IXP425_OSWT
-	str     r1, [r2]
-	ldr	r1, =0x5
-	ldr     r2, =IXP425_OSWE
-	str     r1, [r2]
-	b	reset_endless
-
-
-reset_endless:
-
-	b	reset_endless
-
-#ifdef CONFIG_USE_IRQ
-
-.LC0:		.word	loops_per_jiffy
-
-/*
- * 0 <= r0 <= 2000
- */
-.globl __udelay
-__udelay:
-	mov	r2,     #0x6800
-	orr	r2, r2, #0x00db
-	mul	r0, r2, r0
-	ldr	r2, .LC0
-	ldr	r2, [r2]		@ max = 0x0fffffff
-	mov	r0, r0, lsr #11		@ max = 0x00003fff
-	mov	r2, r2, lsr #11		@ max = 0x0003ffff
-	mul	r0, r2, r0		@ max = 2^32-1
-	movs	r0, r0, lsr #6
-
-delay_loop:
-	subs	r0, r0, #1
-	bne	delay_loop
-	mov	pc, lr
-
-#endif /* CONFIG_USE_IRQ */
diff --git a/arch/arm/cpu/ixp/timer.c b/arch/arm/cpu/ixp/timer.c
deleted file mode 100644
index edf341f..0000000
--- a/arch/arm/cpu/ixp/timer.c
+++ /dev/null
@@ -1,135 +0,0 @@
-/*
- * (C) Copyright 2006
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Alex Zuepke <azu@sysgo.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/arch/ixp425.h>
-
-#ifdef CONFIG_TIMER_IRQ
-
-#define FREQ		66666666
-#define CLOCK_TICK_RATE	(((FREQ / CONFIG_SYS_HZ & ~IXP425_OST_RELOAD_MASK) + 1) * CONFIG_SYS_HZ)
-#define LATCH		((CLOCK_TICK_RATE + CONFIG_SYS_HZ/2) / CONFIG_SYS_HZ)	/* For divider */
-
-/*
- * When interrupts are enabled, use timer 2 for time/delay generation...
- */
-
-static volatile ulong timestamp;
-
-static void timer_isr(void *data)
-{
-	unsigned int *pTime = (unsigned int *)data;
-
-	(*pTime)++;
-
-	/*
-	 * Reset IRQ source
-	 */
-	*IXP425_OSST = IXP425_OSST_TIMER_2_PEND;
-}
-
-ulong get_timer (ulong base)
-{
-	return timestamp - base;
-}
-
-void reset_timer (void)
-{
-	timestamp = 0;
-}
-
-int timer_init (void)
-{
-	/* install interrupt handler for timer */
-	irq_install_handler(IXP425_TIMER_2_IRQ, timer_isr, (void *)&timestamp);
-
-	/* setup the Timer counter value */
-	*IXP425_OSRT2 = (LATCH & ~IXP425_OST_RELOAD_MASK) | IXP425_OST_ENABLE;
-
-	/* enable timer irq */
-	*IXP425_ICMR = (1 << IXP425_TIMER_2_IRQ);
-
-	return 0;
-}
-#else
-ulong get_timer (ulong base)
-{
-       return get_timer_masked () - base;
-}
-
-void ixp425_udelay(unsigned long usec)
-{
-	/*
-	 * This function has a max usec, but since it is called from udelay
-	 * we should not have to worry... be happy
-	 */
-	unsigned long usecs = CONFIG_SYS_HZ/1000000L & ~IXP425_OST_RELOAD_MASK;
-
-	*IXP425_OSST = IXP425_OSST_TIMER_1_PEND;
-	usecs |= IXP425_OST_ONE_SHOT | IXP425_OST_ENABLE;
-	*IXP425_OSRT1 = usecs;
-	while (!(*IXP425_OSST & IXP425_OSST_TIMER_1_PEND));
-}
-
-void __udelay (unsigned long usec)
-{
-	while (usec--) ixp425_udelay(1);
-}
-
-static ulong reload_constant = 0xfffffff0;
-
-void reset_timer_masked (void)
-{
-	ulong reload = reload_constant | IXP425_OST_ONE_SHOT | IXP425_OST_ENABLE;
-
-	*IXP425_OSST = IXP425_OSST_TIMER_1_PEND;
-	*IXP425_OSRT1 = reload;
-}
-
-ulong get_timer_masked (void)
-{
-	/*
-	 * Note that it is possible for this to wrap!
-	 * In this case we return max.
-	 */
-	ulong current = *IXP425_OST1;
-	if (*IXP425_OSST & IXP425_OSST_TIMER_1_PEND)
-	{
-		return reload_constant;
-	}
-	return (reload_constant - current);
-}
-
-int timer_init(void)
-{
-	return 0;
-}
-#endif
diff --git a/arch/arm/cpu/ixp/u-boot.lds b/arch/arm/cpu/ixp/u-boot.lds
deleted file mode 100644
index a55eb8a..0000000
--- a/arch/arm/cpu/ixp/u-boot.lds
+++ /dev/null
@@ -1,78 +0,0 @@
-/*
- * (C) Copyright 2000-2006
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_FORMAT("elf32-bigarm", "elf32-bigarm", "elf32-bigarm")
-OUTPUT_ARCH(arm)
-ENTRY(_start)
-SECTIONS
-{
-	. = 0x00000000;
-
-	. = ALIGN(4);
-	.text :
-	{
-		arch/arm/cpu/ixp/start.o(.text)
-		*(.text)
-	}
-
-	. = ALIGN(4);
-	.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
-
-	. = ALIGN(4);
-	.data : {
-		*(.data)
-	}
-
-	. = ALIGN(4);
-
-	. = .;
-	__u_boot_cmd_start = .;
-	.u_boot_cmd : { *(.u_boot_cmd) }
-	__u_boot_cmd_end = .;
-
-	. = ALIGN(4);
-
-	.rel.dyn : {
-		__rel_dyn_start = .;
-		*(.rel*)
-		__rel_dyn_end = .;
-	}
-
-	.dynsym : {
-		__dynsym_start = .;
-		*(.dynsym)
-	}
-
-	.bss __rel_dyn_start (OVERLAY) : {
-		__bss_start = .;
-		*(.bss)
-		 . = ALIGN(4);
-		_end = .;
-	}
-
-	/DISCARD/ : { *(.dynstr*) }
-	/DISCARD/ : { *(.dynamic*) }
-	/DISCARD/ : { *(.plt*) }
-	/DISCARD/ : { *(.interp*) }
-	/DISCARD/ : { *(.gnu*) }
-}
diff --git a/arch/arm/cpu/lh7a40x/Makefile b/arch/arm/cpu/lh7a40x/Makefile
deleted file mode 100644
index 01cf7f5..0000000
--- a/arch/arm/cpu/lh7a40x/Makefile
+++ /dev/null
@@ -1,47 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(CPU).o
-
-START	= start.o
-COBJS	= cpu.o speed.o timer.o
-
-SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
-START	:= $(addprefix $(obj),$(START))
-
-all:	$(obj).depend $(START) $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/arch/arm/cpu/lh7a40x/config.mk b/arch/arm/cpu/lh7a40x/config.mk
deleted file mode 100644
index 47b2b7b..0000000
--- a/arch/arm/cpu/lh7a40x/config.mk
+++ /dev/null
@@ -1,32 +0,0 @@
-#
-# (C) Copyright 2002
-# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float
-
-PLATFORM_CPPFLAGS += -march=armv4
-# =========================================================================
-#
-# Supply options according to compiler version
-#
-# ========================================================================
-PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))
diff --git a/arch/arm/cpu/lh7a40x/cpu.c b/arch/arm/cpu/lh7a40x/cpu.c
deleted file mode 100644
index b193189..0000000
--- a/arch/arm/cpu/lh7a40x/cpu.c
+++ /dev/null
@@ -1,65 +0,0 @@
-/*
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * CPU specific code
- */
-
-#include <common.h>
-#include <command.h>
-#include <asm/system.h>
-
-static void cache_flush(void);
-
-int cleanup_before_linux (void)
-{
-	/*
-	 * this function is called just before we call linux
-	 * it prepares the processor for linux
-	 *
-	 * we turn off caches etc ...
-	 */
-
-	disable_interrupts ();
-
-	/* turn off I/D-cache */
-	icache_disable();
-	dcache_disable();
-
-	/* flush I/D-cache */
-	cache_flush();
-
-	return 0;
-}
-
-/* flush I/D-cache */
-static void cache_flush (void)
-{
-	unsigned long i = 0;
-
-	asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i));
-}
diff --git a/arch/arm/cpu/lh7a40x/speed.c b/arch/arm/cpu/lh7a40x/speed.c
deleted file mode 100644
index 333ebb5..0000000
--- a/arch/arm/cpu/lh7a40x/speed.c
+++ /dev/null
@@ -1,83 +0,0 @@
-/*
- * (C) Copyright 2001-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2002
- * David Mueller, ELSOFT AG, d.mueller@elsoft.ch
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <lh7a40x.h>
-
-
-/* ------------------------------------------------------------------------- */
-/* NOTE: This describes the proper use of this file.
- *
- * CONFIG_SYS_CLK_FREQ should be defined as the input frequency of the PLL.
- *
- * get_FCLK(), get_HCLK(), get_PCLK() return the clock of
- * the specified bus in HZ.
- */
-/* ------------------------------------------------------------------------- */
-
-ulong get_PLLCLK (void)
-{
-	return CONFIG_SYS_CLK_FREQ;
-}
-
-/* return FCLK frequency */
-ulong get_FCLK (void)
-{
-	lh7a40x_csc_t* csc = LH7A40X_CSC_PTR;
-	ulong maindiv1, maindiv2, prediv, ps;
-
-	/*
-	 * from userguide 6.1.1.2
-	 *
-	 * FCLK = ((MAINDIV1 +2) * (MAINDIV2 +2) * 14.7456MHz) /
-	 *                   ((PREDIV+2) * (2^PS))
-	 */
-	maindiv2 = (csc->clkset & CLKSET_MAINDIV2) >> 11;
-	maindiv1 = (csc->clkset & CLKSET_MAINDIV1) >> 7;
-	prediv = (csc->clkset & CLKSET_PREDIV) >> 2;
-	ps = (csc->clkset & CLKSET_PS) >> 16;
-
-	return (((maindiv2 + 2) * (maindiv1 + 2) * CONFIG_SYS_CLK_FREQ) /
-		((prediv + 2) * (1 << ps)));
-}
-
-
-/* return HCLK frequency */
-ulong get_HCLK (void)
-{
-	lh7a40x_csc_t* csc = LH7A40X_CSC_PTR;
-
-	return (get_FCLK () / ((csc->clkset & CLKSET_HCLKDIV) + 1));
-}
-
-/* return PCLK frequency */
-ulong get_PCLK (void)
-{
-	lh7a40x_csc_t* csc = LH7A40X_CSC_PTR;
-
-	return (get_HCLK () /
-		(1 << (((csc->clkset & CLKSET_PCLKDIV) >> 16) + 1)));
-}
diff --git a/arch/arm/cpu/lh7a40x/start.S b/arch/arm/cpu/lh7a40x/start.S
deleted file mode 100644
index 1457427..0000000
--- a/arch/arm/cpu/lh7a40x/start.S
+++ /dev/null
@@ -1,499 +0,0 @@
-/*
- *  armboot - Startup Code for ARM920 CPU-core
- *
- *  Copyright (c) 2001	Marius Gröger <mag@sysgo.de>
- *  Copyright (c) 2002	Alex Züpke <azu@sysgo.de>
- *  Copyright (c) 2002	Gary Jennejohn <garyj@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <asm-offsets.h>
-#include <config.h>
-#include <version.h>
-
-/*
- *************************************************************************
- *
- * Jump vector table as in table 3.1 in [1]
- *
- *************************************************************************
- */
-
-
-.globl _start
-_start:	b       reset
-	ldr	pc, _undefined_instruction
-	ldr	pc, _software_interrupt
-	ldr	pc, _prefetch_abort
-	ldr	pc, _data_abort
-	ldr	pc, _not_used
-	ldr	pc, _irq
-	ldr	pc, _fiq
-
-_undefined_instruction:	.word undefined_instruction
-_software_interrupt:	.word software_interrupt
-_prefetch_abort:	.word prefetch_abort
-_data_abort:		.word data_abort
-_not_used:		.word not_used
-_irq:			.word irq
-_fiq:			.word fiq
-
-	.balignl 16,0xdeadbeef
-
-
-/*
- *************************************************************************
- *
- * Startup Code (reset vector)
- *
- * do important init only if we don't start from memory!
- * relocate armboot to ram
- * setup stack
- * jump to second stage
- *
- *************************************************************************
- */
-
-.globl _TEXT_BASE
-_TEXT_BASE:
-	.word	CONFIG_SYS_TEXT_BASE
-
-/*
- * These are defined in the board-specific linker script.
- * Subtracting _start from them lets the linker put their
- * relative position in the executable instead of leaving
- * them null.
- */
-.globl _bss_start_ofs
-_bss_start_ofs:
-	.word __bss_start - _start
-
-.globl _bss_end_ofs
-_bss_end_ofs:
-	.word _end - _start
-
-#ifdef CONFIG_USE_IRQ
-/* IRQ stack memory (calculated at run-time) */
-.globl IRQ_STACK_START
-IRQ_STACK_START:
-	.word	0x0badc0de
-
-/* IRQ stack memory (calculated at run-time) */
-.globl FIQ_STACK_START
-FIQ_STACK_START:
-	.word 0x0badc0de
-#endif
-
-/* IRQ stack memory (calculated at run-time) + 8 bytes */
-.globl IRQ_STACK_START_IN
-IRQ_STACK_START_IN:
-	.word	0x0badc0de
-
-/*
- * the actual reset code
- */
-
-reset:
-	/*
-	 * set the cpu to SVC32 mode
-	 */
-	mrs	r0,cpsr
-	bic	r0,r0,#0x1f
-	orr	r0,r0,#0xd3
-	msr	cpsr,r0
-
-#define pWDTCTL		0x80001400  /* Watchdog Timer control register */
-#define pINTENC		0x8000050C  /* Interupt-Controller enable clear register */
-#define pCLKSET		0x80000420  /* clock divisor register */
-
-	/* disable watchdog, set watchdog control register to
-	 * all zeros (default reset)
-	 */
-	ldr     r0, =pWDTCTL
-	mov     r1, #0x0
-	str     r1, [r0]
-
-	/*
-	 * mask all IRQs by setting all bits in the INTENC register (default)
-	 */
-	mov	r1, #0xffffffff
-	ldr	r0, =pINTENC
-	str	r1, [r0]
-
-	/* FCLK:HCLK:PCLK = 1:2:2 */
-	/* default FCLK is 200 MHz, using 14.7456 MHz fin */
-	ldr	r0, =pCLKSET
-	ldr r1, =0x0004ee39
-@	ldr r1, =0x0005ee39	@ 1: 2: 4
-	str	r1, [r0]
-
-	/*
-	 * we do sys-critical inits only at reboot,
-	 * not when booting from ram!
-	 */
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
-	bl	cpu_init_crit
-#endif
-
-/* Set stackpointer in internal RAM to call board_init_f */
-call_board_init_f:
-	ldr	sp, =(CONFIG_SYS_INIT_SP_ADDR)
-	bic	sp, sp, #7 /* 8-byte alignment for ABI compliance */
-	ldr	r0,=0x00000000
-	bl	board_init_f
-
-/*------------------------------------------------------------------------------*/
-
-/*
- * void relocate_code (addr_sp, gd, addr_moni)
- *
- * This "function" does not return, instead it continues in RAM
- * after relocating the monitor code.
- *
- */
-	.globl	relocate_code
-relocate_code:
-	mov	r4, r0	/* save addr_sp */
-	mov	r5, r1	/* save addr of gd */
-	mov	r6, r2	/* save addr of destination */
-
-	/* Set up the stack						    */
-stack_setup:
-	mov	sp, r4
-
-	adr	r0, _start
-	cmp	r0, r6
-	beq	clear_bss		/* skip relocation */
-	mov	r1, r6			/* r1 <- scratch for copy_loop */
-	ldr	r3, _bss_start_ofs
-	add	r2, r0, r3		/* r2 <- source end address	    */
-
-copy_loop:
-	ldmia	r0!, {r9-r10}		/* copy from source address [r0]    */
-	stmia	r1!, {r9-r10}		/* copy to   target address [r1]    */
-	cmp	r0, r2			/* until source end address [r2]    */
-	blo	copy_loop
-
-#ifndef CONFIG_PRELOADER
-	/*
-	 * fix .rel.dyn relocations
-	 */
-	ldr	r0, _TEXT_BASE		/* r0 <- Text base */
-	sub	r9, r6, r0		/* r9 <- relocation offset */
-	ldr	r10, _dynsym_start_ofs	/* r10 <- sym table ofs */
-	add	r10, r10, r0		/* r10 <- sym table in FLASH */
-	ldr	r2, _rel_dyn_start_ofs	/* r2 <- rel dyn start ofs */
-	add	r2, r2, r0		/* r2 <- rel dyn start in FLASH */
-	ldr	r3, _rel_dyn_end_ofs	/* r3 <- rel dyn end ofs */
-	add	r3, r3, r0		/* r3 <- rel dyn end in FLASH */
-fixloop:
-	ldr	r0, [r2]		/* r0 <- location to fix up, IN FLASH! */
-	add	r0, r0, r9		/* r0 <- location to fix up in RAM */
-	ldr	r1, [r2, #4]
-	and	r7, r1, #0xff
-	cmp	r7, #23			/* relative fixup? */
-	beq	fixrel
-	cmp	r7, #2			/* absolute fixup? */
-	beq	fixabs
-	/* ignore unknown type of fixup */
-	b	fixnext
-fixabs:
-	/* absolute fix: set location to (offset) symbol value */
-	mov	r1, r1, LSR #4		/* r1 <- symbol index in .dynsym */
-	add	r1, r10, r1		/* r1 <- address of symbol in table */
-	ldr	r1, [r1, #4]		/* r1 <- symbol value */
-	add	r1, r1, r9		/* r1 <- relocated sym addr */
-	b	fixnext
-fixrel:
-	/* relative fix: increase location by offset */
-	ldr	r1, [r0]
-	add	r1, r1, r9
-fixnext:
-	str	r1, [r0]
-	add	r2, r2, #8		/* each rel.dyn entry is 8 bytes */
-	cmp	r2, r3
-	blo	fixloop
-#endif
-
-clear_bss:
-#ifndef CONFIG_PRELOADER
-	ldr	r0, _bss_start_ofs
-	ldr	r1, _bss_end_ofs
-	mov	r4, r6			/* reloc addr */
-	add	r0, r0, r4
-	add	r1, r1, r4
-	mov	r2, #0x00000000		/* clear			    */
-
-clbss_l:str	r2, [r0]		/* clear loop...		    */
-	add	r0, r0, #4
-	cmp	r0, r1
-	bne	clbss_l
-#endif
-
-/*
- * We are done. Do not return, instead branch to second part of board
- * initialization, now running from RAM.
- */
-	ldr	r0, _board_init_r_ofs
-	adr	r1, _start
-	add	lr, r0, r1
-	add	lr, lr, r9
-	/* setup parameters for board_init_r */
-	mov	r0, r5		/* gd_t */
-	mov	r1, r6		/* dest_addr */
-	/* jump to it ... */
-	mov	pc, lr
-
-_board_init_r_ofs:
-	.word board_init_r - _start
-
-_rel_dyn_start_ofs:
-	.word __rel_dyn_start - _start
-_rel_dyn_end_ofs:
-	.word __rel_dyn_end - _start
-_dynsym_start_ofs:
-	.word __dynsym_start - _start
-
-/*
- *************************************************************************
- *
- * CPU_init_critical registers
- *
- * setup important registers
- * setup memory timing
- *
- *************************************************************************
- */
-
-
-cpu_init_crit:
-	/*
-	 * flush v4 I/D caches
-	 */
-	mov	r0, #0
-	mcr	p15, 0, r0, c7, c7, 0	/* flush v3/v4 cache */
-	mcr	p15, 0, r0, c8, c7, 0	/* flush v4 TLB */
-
-	/*
-	 * disable MMU stuff and caches
-	 */
-	mrc	p15, 0, r0, c1, c0, 0
-	bic	r0, r0, #0x00002300	@ clear bits 13, 9:8 (--V- --RS)
-	bic	r0, r0, #0x00000087	@ clear bits 7, 2:0 (B--- -CAM)
-	orr	r0, r0, #0x00000002	@ set bit 2 (A) Align
-	orr	r0, r0, #0x00001000	@ set bit 12 (I) I-Cache
-	orr	r0, r0, #0x40000000	@ set bit 30 (nF) notFastBus
-	mcr	p15, 0, r0, c1, c0, 0
-
-
-	/*
-	 * before relocating, we have to setup RAM timing
-	 * because memory timing is board-dependend, you will
-	 * find a lowlevel_init.S in your board directory.
-	 */
-	mov	ip, lr
-	bl	lowlevel_init
-	mov	lr, ip
-
-	mov	pc, lr
-
-
-/*
- *************************************************************************
- *
- * Interrupt handling
- *
- *************************************************************************
- */
-
-@
-@ IRQ stack frame.
-@
-#define S_FRAME_SIZE	72
-
-#define S_OLD_R0	68
-#define S_PSR		64
-#define S_PC		60
-#define S_LR		56
-#define S_SP		52
-
-#define S_IP		48
-#define S_FP		44
-#define S_R10		40
-#define S_R9		36
-#define S_R8		32
-#define S_R7		28
-#define S_R6		24
-#define S_R5		20
-#define S_R4		16
-#define S_R3		12
-#define S_R2		8
-#define S_R1		4
-#define S_R0		0
-
-#define MODE_SVC 0x13
-#define I_BIT	 0x80
-
-/*
- * use bad_save_user_regs for abort/prefetch/undef/swi ...
- * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
- */
-
-	.macro	bad_save_user_regs
-	sub	sp, sp, #S_FRAME_SIZE
-	stmia	sp, {r0 - r12}			@ Calling r0-r12
-	ldr	r2, IRQ_STACK_START_IN
-	ldmia	r2, {r2 - r3}			@ get pc, cpsr
-	add	r0, sp, #S_FRAME_SIZE		@ restore sp_SVC
-
-	add	r5, sp, #S_SP
-	mov	r1, lr
-	stmia	r5, {r0 - r3}			@ save sp_SVC, lr_SVC, pc, cpsr
-	mov	r0, sp
-	.endm
-
-	.macro	irq_save_user_regs
-	sub	sp, sp, #S_FRAME_SIZE
-	stmia	sp, {r0 - r12}			@ Calling r0-r12
-	add     r8, sp, #S_PC
-	stmdb   r8, {sp, lr}^                   @ Calling SP, LR
-	str     lr, [r8, #0]                    @ Save calling PC
-	mrs     r6, spsr
-	str     r6, [r8, #4]                    @ Save CPSR
-	str     r0, [r8, #8]                    @ Save OLD_R0
-	mov	r0, sp
-	.endm
-
-	.macro	irq_restore_user_regs
-	ldmia	sp, {r0 - lr}^			@ Calling r0 - lr
-	mov	r0, r0
-	ldr	lr, [sp, #S_PC]			@ Get PC
-	add	sp, sp, #S_FRAME_SIZE
-	subs	pc, lr, #4			@ return & move spsr_svc into cpsr
-	.endm
-
-	.macro get_bad_stack
-	ldr	r13, IRQ_STACK_START_IN		@ setup our mode stack
-
-	str	lr, [r13]			@ save caller lr / spsr
-	mrs	lr, spsr
-	str     lr, [r13, #4]
-
-	mov	r13, #MODE_SVC			@ prepare SVC-Mode
-	@ msr	spsr_c, r13
-	msr	spsr, r13
-	mov	lr, pc
-	movs	pc, lr
-	.endm
-
-	.macro get_irq_stack			@ setup IRQ stack
-	ldr	sp, IRQ_STACK_START
-	.endm
-
-	.macro get_fiq_stack			@ setup FIQ stack
-	ldr	sp, FIQ_STACK_START
-	.endm
-
-/*
- * exception handlers
- */
-	.align  5
-undefined_instruction:
-	get_bad_stack
-	bad_save_user_regs
-	bl	do_undefined_instruction
-
-	.align	5
-software_interrupt:
-	get_bad_stack
-	bad_save_user_regs
-	bl	do_software_interrupt
-
-	.align	5
-prefetch_abort:
-	get_bad_stack
-	bad_save_user_regs
-	bl	do_prefetch_abort
-
-	.align	5
-data_abort:
-	get_bad_stack
-	bad_save_user_regs
-	bl	do_data_abort
-
-	.align	5
-not_used:
-	get_bad_stack
-	bad_save_user_regs
-	bl	do_not_used
-
-#ifdef CONFIG_USE_IRQ
-
-	.align	5
-irq:
-	get_irq_stack
-	irq_save_user_regs
-	bl	do_irq
-	irq_restore_user_regs
-
-	.align	5
-fiq:
-	get_fiq_stack
-	/* someone ought to write a more effiction fiq_save_user_regs */
-	irq_save_user_regs
-	bl	do_fiq
-	irq_restore_user_regs
-
-#else
-
-	.align	5
-irq:
-	get_bad_stack
-	bad_save_user_regs
-	bl	do_irq
-
-	.align	5
-fiq:
-	get_bad_stack
-	bad_save_user_regs
-	bl	do_fiq
-
-#endif
-
-	.align	5
-.globl reset_cpu
-reset_cpu:
-	bl	disable_interrupts
-
-	/* Disable watchdog */
-	ldr	r1, =pWDTCTL
-	mov	r3, #0
-	str	r3, [r1]
-
-	/* reset counter */
-	ldr	r3, =0x00001984
-	str	r3, [r1, #4]
-
-	/* Enable the watchdog */
-	mov	r3, #1
-	str	r3, [r1]
-
-_loop_forever:
-	b	_loop_forever
diff --git a/arch/arm/cpu/lh7a40x/timer.c b/arch/arm/cpu/lh7a40x/timer.c
deleted file mode 100644
index 2691315..0000000
--- a/arch/arm/cpu/lh7a40x/timer.c
+++ /dev/null
@@ -1,193 +0,0 @@
-/*
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Alex Zuepke <azu@sysgo.de>
- *
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <lh7a40x.h>
-
-static ulong timer_load_val = 0;
-
-/* macro to read the 16 bit timer */
-static inline ulong READ_TIMER(void)
-{
-	lh7a40x_timers_t* timers = LH7A40X_TIMERS_PTR;
-	lh7a40x_timer_t* timer = &timers->timer1;
-
-	return (timer->value & 0x0000ffff);
-}
-
-static ulong timestamp;
-static ulong lastdec;
-
-int timer_init (void)
-{
-	lh7a40x_timers_t* timers = LH7A40X_TIMERS_PTR;
-	lh7a40x_timer_t* timer = &timers->timer1;
-
-	/* a periodic timer using the 508kHz source */
-	timer->control = (TIMER_PER | TIMER_CLK508K);
-
-	if (timer_load_val == 0) {
-		/*
-		 * 10ms period with 508.469kHz clock = 5084
-		 */
-		timer_load_val = CONFIG_SYS_HZ/100;
-	}
-
-	/* load value for 10 ms timeout */
-	lastdec = timer->load = timer_load_val;
-
-	/* auto load, start timer */
-	timer->control = timer->control | TIMER_EN;
-	timestamp = 0;
-
-	return (0);
-}
-
-/*
- * timer without interrupts
- */
-
-void reset_timer (void)
-{
-	reset_timer_masked ();
-}
-
-ulong get_timer (ulong base)
-{
-	return (get_timer_masked() - base);
-}
-
-void set_timer (ulong t)
-{
-	timestamp = t;
-}
-
-void __udelay (unsigned long usec)
-{
-	ulong tmo,tmp;
-
-	/* normalize */
-	if (usec >= 1000) {
-		tmo = usec / 1000;
-		tmo *= CONFIG_SYS_HZ;
-		tmo /= 1000;
-	}
-	else {
-		if (usec > 1) {
-			tmo = usec * CONFIG_SYS_HZ;
-			tmo /= (1000*1000);
-		}
-		else
-			tmo = 1;
-	}
-
-	/* check for rollover during this delay */
-	tmp = get_timer (0);
-	if ((tmp + tmo) < tmp )
-		reset_timer_masked();  /* timer would roll over */
-	else
-		tmo += tmp;
-
-	while (get_timer_masked () < tmo);
-}
-
-void reset_timer_masked (void)
-{
-	/* reset time */
-	lastdec = READ_TIMER();
-	timestamp = 0;
-}
-
-ulong get_timer_masked (void)
-{
-	ulong now = READ_TIMER();
-
-	if (lastdec >= now) {
-		/* normal mode */
-		timestamp += (lastdec - now);
-	} else {
-		/* we have an overflow ... */
-		timestamp += ((lastdec + timer_load_val) - now);
-	}
-	lastdec = now;
-
-	return timestamp;
-}
-
-void udelay_masked (unsigned long usec)
-{
-	ulong tmo;
-	ulong endtime;
-	signed long diff;
-
-	/* normalize */
-	if (usec >= 1000) {
-		tmo = usec / 1000;
-		tmo *= CONFIG_SYS_HZ;
-		tmo /= 1000;
-	} else {
-		if (usec > 1) {
-			tmo = usec * CONFIG_SYS_HZ;
-			tmo /= (1000*1000);
-		} else {
-			tmo = 1;
-		}
-	}
-
-	endtime = get_timer_masked () + tmo;
-
-	do {
-		ulong now = get_timer_masked ();
-		diff = endtime - now;
-	} while (diff >= 0);
-}
-
-/*
- * This function is derived from PowerPC code (read timebase as long long).
- * On ARM it just returns the timer value.
- */
-unsigned long long get_ticks(void)
-{
-	return get_timer(0);
-}
-
-/*
- * This function is derived from PowerPC code (timebase clock frequency).
- * On ARM it returns the number of timer ticks per second.
- */
-ulong get_tbclk (void)
-{
-	ulong tbclk;
-
-	tbclk = timer_load_val * 100;
-
-	return tbclk;
-}
diff --git a/arch/arm/cpu/lh7a40x/u-boot.lds b/arch/arm/cpu/lh7a40x/u-boot.lds
deleted file mode 100644
index 463237d..0000000
--- a/arch/arm/cpu/lh7a40x/u-boot.lds
+++ /dev/null
@@ -1,78 +0,0 @@
-/*
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-ENTRY(_start)
-SECTIONS
-{
-	. = 0x00000000;
-
-	. = ALIGN(4);
-	.text :
-	{
-		arch/arm/cpu/lh7a40x/start.o	(.text)
-		*(.text)
-	}
-
-	. = ALIGN(4);
-	.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
-
-	. = ALIGN(4);
-	.data : {
-		*(.data)
-	}
-
-	. = ALIGN(4);
-
-	. = .;
-	__u_boot_cmd_start = .;
-	.u_boot_cmd : { *(.u_boot_cmd) }
-	__u_boot_cmd_end = .;
-
-	. = ALIGN(4);
-
-	.rel.dyn : {
-		__rel_dyn_start = .;
-		*(.rel*)
-		__rel_dyn_end = .;
-	}
-
-	.dynsym : {
-		__dynsym_start = .;
-		*(.dynsym)
-	}
-
-	.bss __rel_dyn_start (OVERLAY) : {
-		__bss_start = .;
-		*(.bss)
-		 . = ALIGN(4);
-		_end = .;
-	}
-
-	/DISCARD/ : { *(.dynstr*) }
-	/DISCARD/ : { *(.dynamic*) }
-	/DISCARD/ : { *(.plt*) }
-	/DISCARD/ : { *(.interp*) }
-	/DISCARD/ : { *(.gnu*) }
-}
diff --git a/arch/arm/cpu/pxa/Makefile b/arch/arm/cpu/pxa/Makefile
deleted file mode 100644
index 49a6ed3..0000000
--- a/arch/arm/cpu/pxa/Makefile
+++ /dev/null
@@ -1,52 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(CPU).o
-
-START	= start.o
-
-COBJS	+= cpu.o
-COBJS	+= i2c.o
-COBJS	+= pxafb.o
-COBJS	+= timer.o
-COBJS	+= usb.o
-
-SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
-START	:= $(addprefix $(obj),$(START))
-
-all:	$(obj).depend $(START) $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/arch/arm/cpu/pxa/config.mk b/arch/arm/cpu/pxa/config.mk
deleted file mode 100644
index a05d69c..0000000
--- a/arch/arm/cpu/pxa/config.mk
+++ /dev/null
@@ -1,33 +0,0 @@
-#
-# (C) Copyright 2002
-# Sysgo Real-Time Solutions, GmbH <www.elinos.com>
-# Marius Groeger <mgroeger@sysgo.de>
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float
-
-PLATFORM_CPPFLAGS += -march=armv5te -mtune=xscale
-# =========================================================================
-#
-# Supply options according to compiler version
-#
-# ========================================================================
-PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))
diff --git a/arch/arm/cpu/pxa/cpu.c b/arch/arm/cpu/pxa/cpu.c
deleted file mode 100644
index 7d49cbb..0000000
--- a/arch/arm/cpu/pxa/cpu.c
+++ /dev/null
@@ -1,320 +0,0 @@
-/*
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Alex Zuepke <azu@sysgo.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * CPU specific code
- */
-
-#include <asm/io.h>
-#include <asm/system.h>
-#include <command.h>
-#include <common.h>
-#include <asm/arch/pxa-regs.h>
-
-static void cache_flush(void);
-
-int cleanup_before_linux (void)
-{
-	/*
-	 * this function is called just before we call linux
-	 * it prepares the processor for linux
-	 *
-	 * just disable everything that can disturb booting linux
-	 */
-
-	disable_interrupts ();
-
-	/* turn off I-cache */
-	icache_disable();
-	dcache_disable();
-
-	/* flush I-cache */
-	cache_flush();
-
-	return (0);
-}
-
-/* flush I/D-cache */
-static void cache_flush (void)
-{
-	unsigned long i = 0;
-
-	asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i));
-}
-
-#ifndef CONFIG_CPU_MONAHANS
-void set_GPIO_mode(int gpio_mode)
-{
-	int gpio = gpio_mode & GPIO_MD_MASK_NR;
-	int fn = (gpio_mode & GPIO_MD_MASK_FN) >> 8;
-	int val;
-
-	/* This below changes direction setting of GPIO "gpio" */
-	val = readl(GPDR(gpio));
-
-	if (gpio_mode & GPIO_MD_MASK_DIR)
-		val |= GPIO_bit(gpio);
-	else
-		val &= ~GPIO_bit(gpio);
-
-	writel(val, GPDR(gpio));
-
-	/* This below updates only AF of GPIO "gpio" */
-	val = readl(GAFR(gpio));
-	val &= ~(0x3 << (((gpio) & 0xf) * 2));
-	val |= fn << (((gpio) & 0xf) * 2);
-	writel(val, GAFR(gpio));
-}
-#endif /* CONFIG_CPU_MONAHANS */
-
-void pxa_wait_ticks(int ticks)
-{
-	writel(0, OSCR);
-	while (readl(OSCR) < ticks)
-		asm volatile("":::"memory");
-}
-
-inline void writelrb(uint32_t val, uint32_t addr)
-{
-	writel(val, addr);
-	asm volatile("":::"memory");
-	readl(addr);
-	asm volatile("":::"memory");
-}
-
-void pxa_dram_init(void)
-{
-	uint32_t tmp;
-	int i;
-	/*
-	 * 1) Initialize Asynchronous static memory controller
-	 */
-
-	writelrb(CONFIG_SYS_MSC0_VAL, MSC0);
-	writelrb(CONFIG_SYS_MSC1_VAL, MSC1);
-	writelrb(CONFIG_SYS_MSC2_VAL, MSC2);
-	/*
-	 * 2) Initialize Card Interface
-	 */
-
-	/* MECR: Memory Expansion Card Register */
-	writelrb(CONFIG_SYS_MECR_VAL, MECR);
-	/* MCMEM0: Card Interface slot 0 timing */
-	writelrb(CONFIG_SYS_MCMEM0_VAL, MCMEM0);
-	/* MCMEM1: Card Interface slot 1 timing */
-	writelrb(CONFIG_SYS_MCMEM1_VAL, MCMEM1);
-	/* MCATT0: Card Interface Attribute Space Timing, slot 0 */
-	writelrb(CONFIG_SYS_MCATT0_VAL, MCATT0);
-	/* MCATT1: Card Interface Attribute Space Timing, slot 1 */
-	writelrb(CONFIG_SYS_MCATT1_VAL, MCATT1);
-	/* MCIO0: Card Interface I/O Space Timing, slot 0 */
-	writelrb(CONFIG_SYS_MCIO0_VAL, MCIO0);
-	/* MCIO1: Card Interface I/O Space Timing, slot 1 */
-	writelrb(CONFIG_SYS_MCIO1_VAL, MCIO1);
-
-	/*
-	 * 3) Configure Fly-By DMA register
-	 */
-
-	writelrb(CONFIG_SYS_FLYCNFG_VAL, FLYCNFG);
-
-	/*
-	 * 4) Initialize Timing for Sync Memory (SDCLK0)
-	 */
-
-	/*
-	 * Before accessing MDREFR we need a valid DRI field, so we set
-	 * this to power on defaults + DRI field.
-	 */
-
-	/* Read current MDREFR config and zero out DRI */
-	tmp = readl(MDREFR) & ~0xfff;
-	/* Add user-specified DRI */
-	tmp |= CONFIG_SYS_MDREFR_VAL & 0xfff;
-	/* Configure important bits */
-	tmp |= MDREFR_K0RUN | MDREFR_SLFRSH;
-	tmp &= ~(MDREFR_APD | MDREFR_E1PIN);
-
-	/* Write MDREFR back */
-	writelrb(tmp, MDREFR);
-
-	/*
-	 * 5) Initialize Synchronous Static Memory (Flash/Peripherals)
-	 */
-
-	/* Initialize SXCNFG register. Assert the enable bits.
-	 *
-	 * Write SXMRS to cause an MRS command to all enabled banks of
-	 * synchronous static memory. Note that SXLCR need not be written
-	 * at this time.
-	 */
-	writelrb(CONFIG_SYS_SXCNFG_VAL, SXCNFG);
-
-	/*
-	 * 6) Initialize SDRAM
-	 */
-
-	writelrb(CONFIG_SYS_MDREFR_VAL & ~MDREFR_SLFRSH, MDREFR);
-	writelrb(CONFIG_SYS_MDREFR_VAL | MDREFR_E1PIN, MDREFR);
-
-	/*
-	 * 7) Write MDCNFG with MDCNFG:DEx deasserted (set to 0), to configure
-	 *    but not enable each SDRAM partition pair.
-	 */
-
-	writelrb(CONFIG_SYS_MDCNFG_VAL &
-		~(MDCNFG_DE0 | MDCNFG_DE1 | MDCNFG_DE2 | MDCNFG_DE3), MDCNFG);
-	/* Wait for the clock to the SDRAMs to stabilize, 100..200 usec. */
-	pxa_wait_ticks(0x300);
-
-	/*
-	 * 8) Trigger a number (usually 8) refresh cycles by attempting
-	 *    non-burst read or write accesses to disabled SDRAM, as commonly
-	 *    specified in the power up sequence documented in SDRAM data
-	 *    sheets. The address(es) used for this purpose must not be
-	 *    cacheable.
-	 */
-	for (i = 9; i >= 0; i--) {
-		writel(i, 0xa0000000);
-		asm volatile("":::"memory");
-	}
-	/*
-	 * 9) Write MDCNFG with enable bits asserted (MDCNFG:DEx set to 1).
-	 */
-
-	tmp = CONFIG_SYS_MDCNFG_VAL &
-		(MDCNFG_DE0 | MDCNFG_DE1 | MDCNFG_DE2 | MDCNFG_DE3);
-	tmp |= readl(MDCNFG);
-	writelrb(tmp, MDCNFG);
-
-	/*
-	 * 10) Write MDMRS.
-	 */
-
-	writelrb(CONFIG_SYS_MDMRS_VAL, MDMRS);
-
-	/*
-	 * 11) Enable APD
-	 */
-
-	if (CONFIG_SYS_MDREFR_VAL & MDREFR_APD) {
-		tmp = readl(MDREFR);
-		tmp |= MDREFR_APD;
-		writelrb(tmp, MDREFR);
-	}
-}
-
-void pxa_gpio_setup(void)
-{
-	writel(CONFIG_SYS_GPSR0_VAL, GPSR0);
-	writel(CONFIG_SYS_GPSR1_VAL, GPSR1);
-	writel(CONFIG_SYS_GPSR2_VAL, GPSR2);
-#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
-	writel(CONFIG_SYS_GPSR3_VAL, GPSR3);
-#endif
-
-	writel(CONFIG_SYS_GPCR0_VAL, GPCR0);
-	writel(CONFIG_SYS_GPCR1_VAL, GPCR1);
-	writel(CONFIG_SYS_GPCR2_VAL, GPCR2);
-#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
-	writel(CONFIG_SYS_GPCR3_VAL, GPCR3);
-#endif
-
-	writel(CONFIG_SYS_GPDR0_VAL, GPDR0);
-	writel(CONFIG_SYS_GPDR1_VAL, GPDR1);
-	writel(CONFIG_SYS_GPDR2_VAL, GPDR2);
-#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
-	writel(CONFIG_SYS_GPDR3_VAL, GPDR3);
-#endif
-
-	writel(CONFIG_SYS_GAFR0_L_VAL, GAFR0_L);
-	writel(CONFIG_SYS_GAFR0_U_VAL, GAFR0_U);
-	writel(CONFIG_SYS_GAFR1_L_VAL, GAFR1_L);
-	writel(CONFIG_SYS_GAFR1_U_VAL, GAFR1_U);
-	writel(CONFIG_SYS_GAFR2_L_VAL, GAFR2_L);
-	writel(CONFIG_SYS_GAFR2_U_VAL, GAFR2_U);
-#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
-	writel(CONFIG_SYS_GAFR3_L_VAL, GAFR3_L);
-	writel(CONFIG_SYS_GAFR3_U_VAL, GAFR3_U);
-#endif
-
-	writel(CONFIG_SYS_PSSR_VAL, PSSR);
-}
-
-void pxa_interrupt_setup(void)
-{
-	writel(0, ICLR);
-	writel(0, ICMR);
-#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
-	writel(0, ICLR2);
-	writel(0, ICMR2);
-#endif
-}
-
-void pxa_clock_setup(void)
-{
-#ifndef CONFIG_CPU_MONAHANS
-	writel(CONFIG_SYS_CKEN, CKEN);
-	writel(CONFIG_SYS_CCCR, CCCR);
-	asm volatile("mcr	p14, 0, %0, c6, c0, 0"::"r"(2));
-#else
-/* Set CKENA/CKENB/ACCR for MH */
-#endif
-
-	/* enable the 32Khz oscillator for RTC and PowerManager */
-	writel(OSCC_OON, OSCC);
-	while(!(readl(OSCC) & OSCC_OOK))
-		asm volatile("":::"memory");
-}
-
-void pxa_wakeup(void)
-{
-	uint32_t rcsr;
-
-	rcsr = readl(RCSR);
-	writel(rcsr & (RCSR_GPR | RCSR_SMR | RCSR_WDR | RCSR_HWR), RCSR);
-
-	/* Wakeup */
-	if (rcsr & RCSR_SMR) {
-		writel(PSSR_PH, PSSR);
-		pxa_dram_init();
-		icache_disable();
-		dcache_disable();
-		asm volatile("mov	pc, %0"::"r"(readl(PSSR)));
-	}
-}
-
-int arch_cpu_init(void)
-{
-	pxa_gpio_setup();
-/*	pxa_wait_ticks(0x8000); */
-	pxa_wakeup();
-	pxa_interrupt_setup();
-	pxa_clock_setup();
-	return 0;
-}
diff --git a/arch/arm/cpu/pxa/i2c.c b/arch/arm/cpu/pxa/i2c.c
deleted file mode 100644
index 7aa49ae..0000000
--- a/arch/arm/cpu/pxa/i2c.c
+++ /dev/null
@@ -1,469 +0,0 @@
-/*
- * (C) Copyright 2000
- * Paolo Scaffardi, AIRVENT SAM s.p.a - RIMINI(ITALY), arsenio@tin.it
- *
- * (C) Copyright 2000 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2003 Pengutronix e.K.
- * Robert Schwebel <r.schwebel@pengutronix.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- * Back ported to the 8xx platform (from the 8260 platform) by
- * Murray.Jensen@cmst.csiro.au, 27-Jan-01.
- */
-
-/* FIXME: this file is PXA255 specific! What about other XScales? */
-
-#include <common.h>
-#include <asm/io.h>
-
-#ifdef CONFIG_HARD_I2C
-
-/*
- *	- CONFIG_SYS_I2C_SPEED
- *	- I2C_PXA_SLAVE_ADDR
- */
-
-#include <asm/arch/hardware.h>
-#include <asm/arch/pxa-regs.h>
-#include <i2c.h>
-
-/*#define	DEBUG_I2C	1	/###* activate local debugging output  */
-#define I2C_PXA_SLAVE_ADDR	0x1	/* slave pxa unit address           */
-
-#if (CONFIG_SYS_I2C_SPEED == 400000)
-#define I2C_ICR_INIT	(ICR_FM | ICR_BEIE | ICR_IRFIE | ICR_ITEIE | ICR_GCD | ICR_SCLE)
-#else
-#define I2C_ICR_INIT	(ICR_BEIE | ICR_IRFIE | ICR_ITEIE | ICR_GCD | ICR_SCLE)
-#endif
-
-#define I2C_ISR_INIT		0x7FF
-
-#ifdef DEBUG_I2C
-#define PRINTD(x) printf x
-#else
-#define PRINTD(x)
-#endif
-
-
-/* Shall the current transfer have a start/stop condition? */
-#define I2C_COND_NORMAL		0
-#define I2C_COND_START		1
-#define I2C_COND_STOP		2
-
-/* Shall the current transfer be ack/nacked or being waited for it? */
-#define I2C_ACKNAK_WAITACK	1
-#define I2C_ACKNAK_SENDACK	2
-#define I2C_ACKNAK_SENDNAK	4
-
-/* Specify who shall transfer the data (master or slave) */
-#define I2C_READ		0
-#define I2C_WRITE		1
-
-/* All transfers are described by this data structure */
-struct i2c_msg {
-	u8 condition;
-	u8 acknack;
-	u8 direction;
-	u8 data;
-};
-
-
-/**
- * i2c_pxa_reset: - reset the host controller
- *
- */
-
-static void i2c_reset( void )
-{
-	writel(readl(ICR) & ~ICR_IUE, ICR);	/* disable unit */
-	writel(readl(ICR) | ICR_UR, ICR);	/* reset the unit */
-	udelay(100);
-	writel(readl(ICR) & ~ICR_IUE, ICR);	/* disable unit */
-#ifdef CONFIG_CPU_MONAHANS
-	/* | CKENB_1_PWM1 | CKENB_0_PWM0); */
-	writel(readl(CKENB) | (CKENB_4_I2C), CKENB);
-#else /* CONFIG_CPU_MONAHANS */
-	/* set the global I2C clock on */
-	writel(readl(CKEN) | CKEN14_I2C, CKEN);
-#endif
-	writel(I2C_PXA_SLAVE_ADDR, ISAR);	/* set our slave address */
-	writel(I2C_ICR_INIT, ICR);		/* set control reg values */
-	writel(I2C_ISR_INIT, ISR);		/* set clear interrupt bits */
-	writel(readl(ICR) | ICR_IUE, ICR);	/* enable unit */
-	udelay(100);
-}
-
-
-/**
- * i2c_isr_set_cleared: - wait until certain bits of the I2C status register
- *	                  are set and cleared
- *
- * @return: 1 in case of success, 0 means timeout (no match within 10 ms).
- */
-static int i2c_isr_set_cleared( unsigned long set_mask, unsigned long cleared_mask )
-{
-	int timeout = 10000;
-
-	while( ((ISR & set_mask)!=set_mask) || ((ISR & cleared_mask)!=0) ){
-		udelay( 10 );
-		if( timeout-- < 0 ) return 0;
-	}
-
-	return 1;
-}
-
-
-/**
- * i2c_transfer: - Transfer one byte over the i2c bus
- *
- * This function can tranfer a byte over the i2c bus in both directions.
- * It is used by the public API functions.
- *
- * @return:  0: transfer successful
- *          -1: message is empty
- *          -2: transmit timeout
- *          -3: ACK missing
- *          -4: receive timeout
- *          -5: illegal parameters
- *          -6: bus is busy and couldn't be aquired
- */
-int i2c_transfer(struct i2c_msg *msg)
-{
-	int ret;
-
-	if (!msg)
-		goto transfer_error_msg_empty;
-
-	switch(msg->direction) {
-
-	case I2C_WRITE:
-
-		/* check if bus is not busy */
-		if (!i2c_isr_set_cleared(0,ISR_IBB))
-			goto transfer_error_bus_busy;
-
-		/* start transmission */
-		writel(readl(ICR) & ~ICR_START, ICR);
-		writel(readl(ICR) & ~ICR_STOP, ICR);
-		writel(msg->data, IDBR);
-		if (msg->condition == I2C_COND_START)
-			writel(readl(ICR) | ICR_START, ICR);
-		if (msg->condition == I2C_COND_STOP)
-			writel(readl(ICR) | ICR_STOP, ICR);
-		if (msg->acknack == I2C_ACKNAK_SENDNAK)
-			writel(readl(ICR) | ICR_ACKNAK, ICR);
-		if (msg->acknack == I2C_ACKNAK_SENDACK)
-			writel(readl(ICR) & ~ICR_ACKNAK, ICR);
-		writel(readl(ICR) & ~ICR_ALDIE, ICR);
-		writel(readl(ICR) | ICR_TB, ICR);
-
-		/* transmit register empty? */
-		if (!i2c_isr_set_cleared(ISR_ITE,0))
-			goto transfer_error_transmit_timeout;
-
-		/* clear 'transmit empty' state */
-		writel(readl(ISR) | ISR_ITE, ISR);
-
-		/* wait for ACK from slave */
-		if (msg->acknack == I2C_ACKNAK_WAITACK)
-			if (!i2c_isr_set_cleared(0,ISR_ACKNAK))
-				goto transfer_error_ack_missing;
-		break;
-
-	case I2C_READ:
-
-		/* check if bus is not busy */
-		if (!i2c_isr_set_cleared(0,ISR_IBB))
-			goto transfer_error_bus_busy;
-
-		/* start receive */
-		writel(readl(ICR) & ~ICR_START, ICR);
-		writel(readl(ICR) & ~ICR_STOP, ICR);
-		if (msg->condition == I2C_COND_START)
-			writel(readl(ICR) | ICR_START, ICR);
-		if (msg->condition == I2C_COND_STOP)
-			writel(readl(ICR) | ICR_STOP, ICR);
-		if (msg->acknack == I2C_ACKNAK_SENDNAK)
-			writel(readl(ICR) | ICR_ACKNAK, ICR);
-		if (msg->acknack == I2C_ACKNAK_SENDACK)
-			writel(readl(ICR) & ~ICR_ACKNAK, ICR);
-		writel(readl(ICR) & ~ICR_ALDIE, ICR);
-		writel(readl(ICR) | ICR_TB, ICR);
-
-		/* receive register full? */
-		if (!i2c_isr_set_cleared(ISR_IRF,0))
-			goto transfer_error_receive_timeout;
-
-		msg->data = readl(IDBR);
-
-		/* clear 'receive empty' state */
-		writel(readl(ISR) | ISR_IRF, ISR);
-
-		break;
-
-	default:
-
-		goto transfer_error_illegal_param;
-
-	}
-
-	return 0;
-
-transfer_error_msg_empty:
-		PRINTD(("i2c_transfer: error: 'msg' is empty\n"));
-		ret = -1; goto i2c_transfer_finish;
-
-transfer_error_transmit_timeout:
-		PRINTD(("i2c_transfer: error: transmit timeout\n"));
-		ret = -2; goto i2c_transfer_finish;
-
-transfer_error_ack_missing:
-		PRINTD(("i2c_transfer: error: ACK missing\n"));
-		ret = -3; goto i2c_transfer_finish;
-
-transfer_error_receive_timeout:
-		PRINTD(("i2c_transfer: error: receive timeout\n"));
-		ret = -4; goto i2c_transfer_finish;
-
-transfer_error_illegal_param:
-		PRINTD(("i2c_transfer: error: illegal parameters\n"));
-		ret = -5; goto i2c_transfer_finish;
-
-transfer_error_bus_busy:
-		PRINTD(("i2c_transfer: error: bus is busy\n"));
-		ret = -6; goto i2c_transfer_finish;
-
-i2c_transfer_finish:
-		PRINTD(("i2c_transfer: ISR: 0x%04x\n",ISR));
-		i2c_reset();
-		return ret;
-
-}
-
-/* ------------------------------------------------------------------------ */
-/* API Functions                                                            */
-/* ------------------------------------------------------------------------ */
-
-void i2c_init(int speed, int slaveaddr)
-{
-#ifdef CONFIG_SYS_I2C_INIT_BOARD
-	/* call board specific i2c bus reset routine before accessing the   */
-	/* environment, which might be in a chip on that bus. For details   */
-	/* about this problem see doc/I2C_Edge_Conditions.                  */
-	i2c_init_board();
-#endif
-}
-
-
-/**
- * i2c_probe: - Test if a chip answers for a given i2c address
- *
- * @chip:	address of the chip which is searched for
- * @return:	0 if a chip was found, -1 otherwhise
- */
-
-int i2c_probe(uchar chip)
-{
-	struct i2c_msg msg;
-
-	i2c_reset();
-
-	msg.condition = I2C_COND_START;
-	msg.acknack   = I2C_ACKNAK_WAITACK;
-	msg.direction = I2C_WRITE;
-	msg.data      = (chip << 1) + 1;
-	if (i2c_transfer(&msg)) return -1;
-
-	msg.condition = I2C_COND_STOP;
-	msg.acknack   = I2C_ACKNAK_SENDNAK;
-	msg.direction = I2C_READ;
-	msg.data      = 0x00;
-	if (i2c_transfer(&msg)) return -1;
-
-	return 0;
-}
-
-
-/**
- * i2c_read: - Read multiple bytes from an i2c device
- *
- * The higher level routines take into account that this function is only
- * called with len < page length of the device (see configuration file)
- *
- * @chip:	address of the chip which is to be read
- * @addr:	i2c data address within the chip
- * @alen:	length of the i2c data address (1..2 bytes)
- * @buffer:	where to write the data
- * @len:	how much byte do we want to read
- * @return:	0 in case of success
- */
-
-int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
-{
-	struct i2c_msg msg;
-	u8 addr_bytes[3]; /* lowest...highest byte of data address */
-	int ret;
-
-	PRINTD(("i2c_read(chip=0x%02x, addr=0x%02x, alen=0x%02x, len=0x%02x)\n",chip,addr,alen,len));
-
-	i2c_reset();
-
-	/* dummy chip address write */
-	PRINTD(("i2c_read: dummy chip address write\n"));
-	msg.condition = I2C_COND_START;
-	msg.acknack   = I2C_ACKNAK_WAITACK;
-	msg.direction = I2C_WRITE;
-	msg.data      = (chip << 1);
-	msg.data     &= 0xFE;
-	if ((ret=i2c_transfer(&msg))) return -1;
-
-	/*
-	 * send memory address bytes;
-	 * alen defines how much bytes we have to send.
-	 */
-	/*addr &= ((1 << CONFIG_SYS_EEPROM_PAGE_WRITE_BITS)-1); */
-	addr_bytes[0] = (u8)((addr >>  0) & 0x000000FF);
-	addr_bytes[1] = (u8)((addr >>  8) & 0x000000FF);
-	addr_bytes[2] = (u8)((addr >> 16) & 0x000000FF);
-
-	while (--alen >= 0) {
-
-		PRINTD(("i2c_read: send memory word address byte %1d\n",alen));
-		msg.condition = I2C_COND_NORMAL;
-		msg.acknack   = I2C_ACKNAK_WAITACK;
-		msg.direction = I2C_WRITE;
-		msg.data      = addr_bytes[alen];
-		if ((ret=i2c_transfer(&msg))) return -1;
-	}
-
-
-	/* start read sequence */
-	PRINTD(("i2c_read: start read sequence\n"));
-	msg.condition = I2C_COND_START;
-	msg.acknack   = I2C_ACKNAK_WAITACK;
-	msg.direction = I2C_WRITE;
-	msg.data      = (chip << 1);
-	msg.data     |= 0x01;
-	if ((ret=i2c_transfer(&msg))) return -1;
-
-	/* read bytes; send NACK at last byte */
-	while (len--) {
-
-		if (len==0) {
-			msg.condition = I2C_COND_STOP;
-			msg.acknack   = I2C_ACKNAK_SENDNAK;
-		} else {
-			msg.condition = I2C_COND_NORMAL;
-			msg.acknack   = I2C_ACKNAK_SENDACK;
-		}
-
-		msg.direction = I2C_READ;
-		msg.data      = 0x00;
-		if ((ret=i2c_transfer(&msg))) return -1;
-
-		*buffer = msg.data;
-		PRINTD(("i2c_read: reading byte (0x%08x)=0x%02x\n",(unsigned int)buffer,*buffer));
-		buffer++;
-
-	}
-
-	i2c_reset();
-
-	return 0;
-}
-
-
-/**
- * i2c_write: -  Write multiple bytes to an i2c device
- *
- * The higher level routines take into account that this function is only
- * called with len < page length of the device (see configuration file)
- *
- * @chip:	address of the chip which is to be written
- * @addr:	i2c data address within the chip
- * @alen:	length of the i2c data address (1..2 bytes)
- * @buffer:	where to find the data to be written
- * @len:	how much byte do we want to read
- * @return:	0 in case of success
- */
-
-int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
-{
-	struct i2c_msg msg;
-	u8 addr_bytes[3]; /* lowest...highest byte of data address */
-
-	PRINTD(("i2c_write(chip=0x%02x, addr=0x%02x, alen=0x%02x, len=0x%02x)\n",chip,addr,alen,len));
-
-	i2c_reset();
-
-	/* chip address write */
-	PRINTD(("i2c_write: chip address write\n"));
-	msg.condition = I2C_COND_START;
-	msg.acknack   = I2C_ACKNAK_WAITACK;
-	msg.direction = I2C_WRITE;
-	msg.data      = (chip << 1);
-	msg.data     &= 0xFE;
-	if (i2c_transfer(&msg)) return -1;
-
-	/*
-	 * send memory address bytes;
-	 * alen defines how much bytes we have to send.
-	 */
-	addr_bytes[0] = (u8)((addr >>  0) & 0x000000FF);
-	addr_bytes[1] = (u8)((addr >>  8) & 0x000000FF);
-	addr_bytes[2] = (u8)((addr >> 16) & 0x000000FF);
-
-	while (--alen >= 0) {
-
-		PRINTD(("i2c_write: send memory word address\n"));
-		msg.condition = I2C_COND_NORMAL;
-		msg.acknack   = I2C_ACKNAK_WAITACK;
-		msg.direction = I2C_WRITE;
-		msg.data      = addr_bytes[alen];
-		if (i2c_transfer(&msg)) return -1;
-	}
-
-	/* write bytes; send NACK at last byte */
-	while (len--) {
-
-		PRINTD(("i2c_write: writing byte (0x%08x)=0x%02x\n",(unsigned int)buffer,*buffer));
-
-		if (len==0)
-			msg.condition = I2C_COND_STOP;
-		else
-			msg.condition = I2C_COND_NORMAL;
-
-		msg.acknack   = I2C_ACKNAK_WAITACK;
-		msg.direction = I2C_WRITE;
-		msg.data      = *(buffer++);
-
-		if (i2c_transfer(&msg)) return -1;
-
-	}
-
-	i2c_reset();
-
-	return 0;
-
-}
-
-#endif	/* CONFIG_HARD_I2C */
diff --git a/arch/arm/cpu/pxa/pxafb.c b/arch/arm/cpu/pxa/pxafb.c
deleted file mode 100644
index 987fa06..0000000
--- a/arch/arm/cpu/pxa/pxafb.c
+++ /dev/null
@@ -1,652 +0,0 @@
-/*
- * PXA LCD Controller
- *
- * (C) Copyright 2001-2002
- * Wolfgang Denk, DENX Software Engineering -- wd@denx.de
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/************************************************************************/
-/* ** HEADER FILES							*/
-/************************************************************************/
-
-#include <config.h>
-#include <common.h>
-#include <version.h>
-#include <stdarg.h>
-#include <linux/types.h>
-#include <stdio_dev.h>
-#include <lcd.h>
-#include <asm/arch/pxa-regs.h>
-#include <asm/io.h>
-
-/* #define DEBUG */
-
-#ifdef CONFIG_LCD
-
-/*----------------------------------------------------------------------*/
-/*
- * Define panel bpp, LCCR0, LCCR3 and panel_info video struct for
- * your display.
- */
-
-#ifdef CONFIG_PXA_VGA
-/* LCD outputs connected to a video DAC  */
-# define LCD_BPP	LCD_COLOR8
-
-/* you have to set lccr0 and lccr3 (including pcd) */
-# define REG_LCCR0	0x003008f8
-# define REG_LCCR3	0x0300FF01
-
-/* 640x480x16 @ 61 Hz */
-vidinfo_t panel_info = {
-	.vl_col		= 640,
-	.vl_row		= 480,
-	.vl_width	= 640,
-	.vl_height	= 480,
-	.vl_clkp	= CONFIG_SYS_HIGH,
-	.vl_oep		= CONFIG_SYS_HIGH,
-	.vl_hsp		= CONFIG_SYS_HIGH,
-	.vl_vsp		= CONFIG_SYS_HIGH,
-	.vl_dp		= CONFIG_SYS_HIGH,
-	.vl_bpix	= LCD_BPP,
-	.vl_lbw		= 0,
-	.vl_splt	= 0,
-	.vl_clor	= 0,
-	.vl_tft		= 1,
-	.vl_hpw		= 40,
-	.vl_blw		= 56,
-	.vl_elw		= 56,
-	.vl_vpw		= 20,
-	.vl_bfw		= 8,
-	.vl_efw		= 8,
-};
-#endif /* CONFIG_PXA_VIDEO */
-
-/*----------------------------------------------------------------------*/
-#ifdef CONFIG_SHARP_LM8V31
-
-# define LCD_BPP	LCD_COLOR8
-# define LCD_INVERT_COLORS	/* Needed for colors to be correct, but why?	*/
-
-/* you have to set lccr0 and lccr3 (including pcd) */
-# define REG_LCCR0	0x0030087C
-# define REG_LCCR3	0x0340FF08
-
-vidinfo_t panel_info = {
-	.vl_col		= 640,
-	.vl_row		= 480,
-	.vl_width	= 157,
-	.vl_height	= 118,
-	.vl_clkp	= CONFIG_SYS_HIGH,
-	.vl_oep		= CONFIG_SYS_HIGH,
-	.vl_hsp		= CONFIG_SYS_HIGH,
-	.vl_vsp		= CONFIG_SYS_HIGH,
-	.vl_dp		= CONFIG_SYS_HIGH,
-	.vl_bpix	= LCD_BPP,
-	.vl_lbw		= 0,
-	.vl_splt	= 1,
-	.vl_clor	= 1,
-	.vl_tft		= 0,
-	.vl_hpw		= 1,
-	.vl_blw		= 3,
-	.vl_elw		= 3,
-	.vl_vpw		= 1,
-	.vl_bfw		= 0,
-	.vl_efw		= 0,
-};
-#endif /* CONFIG_SHARP_LM8V31 */
-/*----------------------------------------------------------------------*/
-#ifdef CONFIG_VOIPAC_LCD
-
-# define LCD_BPP	LCD_COLOR8
-# define LCD_INVERT_COLORS
-
-/* you have to set lccr0 and lccr3 (including pcd) */
-# define REG_LCCR0	0x043008f8
-# define REG_LCCR3	0x0340FF08
-
-vidinfo_t panel_info = {
-	.vl_col		= 640,
-	.vl_row		= 480,
-	.vl_width	= 157,
-	.vl_height	= 118,
-	.vl_clkp	= CONFIG_SYS_HIGH,
-	.vl_oep		= CONFIG_SYS_HIGH,
-	.vl_hsp		= CONFIG_SYS_HIGH,
-	.vl_vsp		= CONFIG_SYS_HIGH,
-	.vl_dp		= CONFIG_SYS_HIGH,
-	.vl_bpix	= LCD_BPP,
-	.vl_lbw		= 0,
-	.vl_splt	= 1,
-	.vl_clor	= 1,
-	.vl_tft		= 1,
-	.vl_hpw		= 32,
-	.vl_blw		= 144,
-	.vl_elw		= 32,
-	.vl_vpw		= 2,
-	.vl_bfw		= 13,
-	.vl_efw		= 30,
-};
-#endif /* CONFIG_VOIPAC_LCD */
-
-/*----------------------------------------------------------------------*/
-#ifdef CONFIG_HITACHI_SX14
-/* Hitachi SX14Q004-ZZA color STN LCD */
-#define LCD_BPP		LCD_COLOR8
-
-/* you have to set lccr0 and lccr3 (including pcd) */
-#define REG_LCCR0	0x00301079
-#define REG_LCCR3	0x0340FF20
-
-vidinfo_t panel_info = {
-	.vl_col		= 320,
-	.vl_row		= 240,
-	.vl_width	= 167,
-	.vl_height	= 109,
-	.vl_clkp	= CONFIG_SYS_HIGH,
-	.vl_oep		= CONFIG_SYS_HIGH,
-	.vl_hsp		= CONFIG_SYS_HIGH,
-	.vl_vsp		= CONFIG_SYS_HIGH,
-	.vl_dp		= CONFIG_SYS_HIGH,
-	.vl_bpix	= LCD_BPP,
-	.vl_lbw		= 1,
-	.vl_splt	= 0,
-	.vl_clor	= 1,
-	.vl_tft		= 0,
-	.vl_hpw		= 1,
-	.vl_blw		= 1,
-	.vl_elw		= 1,
-	.vl_vpw		= 7,
-	.vl_bfw		= 0,
-	.vl_efw		= 0,
-};
-#endif /* CONFIG_HITACHI_SX14 */
-
-/*----------------------------------------------------------------------*/
-#ifdef CONFIG_LMS283GF05
-
-# define LCD_BPP	LCD_COLOR8
-/*# define LCD_INVERT_COLORS*/
-
-/* you have to set lccr0 and lccr3 (including pcd) */
-# define REG_LCCR0	0x043008f8
-# define REG_LCCR3	0x03b00009
-
-vidinfo_t panel_info = {
-	.vl_col		= 240,
-	.vl_row		= 320,
-	.vl_width	= 240,
-	.vl_height	= 320,
-	.vl_clkp	= CONFIG_SYS_HIGH,
-	.vl_oep		= CONFIG_SYS_LOW,
-	.vl_hsp		= CONFIG_SYS_LOW,
-	.vl_vsp		= CONFIG_SYS_LOW,
-	.vl_dp		= CONFIG_SYS_HIGH,
-	.vl_bpix	= LCD_BPP,
-	.vl_lbw		= 0,
-	.vl_splt	= 1,
-	.vl_clor	= 1,
-	.vl_tft		= 1,
-	.vl_hpw		= 4,
-	.vl_blw		= 4,
-	.vl_elw		= 8,
-	.vl_vpw		= 4,
-	.vl_bfw		= 4,
-	.vl_efw		= 8,
-};
-#endif /* CONFIG_LMS283GF05 */
-
-/*----------------------------------------------------------------------*/
-
-#ifdef CONFIG_ACX517AKN
-
-# define LCD_BPP	LCD_COLOR8
-
-/* you have to set lccr0 and lccr3 (including pcd) */
-# define REG_LCCR0	0x003008f9
-# define REG_LCCR3	0x03700006
-
-vidinfo_t panel_info = {
-	.vl_col		= 320,
-	.vl_row		= 320,
-	.vl_width	= 320,
-	.vl_height	= 320,
-	.vl_clkp	= CONFIG_SYS_HIGH,
-	.vl_oep		= CONFIG_SYS_LOW,
-	.vl_hsp		= CONFIG_SYS_LOW,
-	.vl_vsp		= CONFIG_SYS_LOW,
-	.vl_dp		= CONFIG_SYS_HIGH,
-	.vl_bpix	= LCD_BPP,
-	.vl_lbw		= 0,
-	.vl_splt	= 1,
-	.vl_clor	= 1,
-	.vl_tft		= 1,
-	.vl_hpw		= 0x04,
-	.vl_blw		= 0x1c,
-	.vl_elw		= 0x08,
-	.vl_vpw		= 0x01,
-	.vl_bfw		= 0x07,
-	.vl_efw		= 0x08,
-};
-#endif /* CONFIG_ACX517AKN */
-
-/*----------------------------------------------------------------------*/
-
-#ifdef CONFIG_LQ038J7DH53
-
-# define LCD_BPP	LCD_COLOR8
-
-/* you have to set lccr0 and lccr3 (including pcd) */
-# define REG_LCCR0	0x003008f9
-# define REG_LCCR3	0x03700004
-
-vidinfo_t panel_info = {
-	.vl_col		= 320,
-	.vl_row		= 480,
-	.vl_width	= 320,
-	.vl_height	= 480,
-	.vl_clkp	= CONFIG_SYS_HIGH,
-	.vl_oep		= CONFIG_SYS_LOW,
-	.vl_hsp		= CONFIG_SYS_LOW,
-	.vl_vsp		= CONFIG_SYS_LOW,
-	.vl_dp		= CONFIG_SYS_HIGH,
-	.vl_bpix	= LCD_BPP,
-	.vl_lbw		= 0,
-	.vl_splt	= 1,
-	.vl_clor	= 1,
-	.vl_tft		= 1,
-	.vl_hpw		= 0x04,
-	.vl_blw		= 0x20,
-	.vl_elw		= 0x01,
-	.vl_vpw		= 0x01,
-	.vl_bfw		= 0x04,
-	.vl_efw		= 0x01,
-};
-#endif /* CONFIG_ACX517AKN */
-
-/*----------------------------------------------------------------------*/
-
-#ifdef CONFIG_LITTLETON_LCD
-# define LCD_BPP	LCD_COLOR8
-
-/* you have to set lccr0 and lccr3 (including pcd) */
-# define REG_LCCR0	0x003008f8
-# define REG_LCCR3	0x0300FF04
-
-vidinfo_t panel_info = {
-	.vl_col		= 480,
-	.vl_row		= 640,
-	.vl_width	= 480,
-	.vl_height	= 640,
-	.vl_clkp	= CONFIG_SYS_HIGH,
-	.vl_oep		= CONFIG_SYS_HIGH,
-	.vl_hsp		= CONFIG_SYS_HIGH,
-	.vl_vsp		= CONFIG_SYS_HIGH,
-	.vl_dp		= CONFIG_SYS_HIGH,
-	.vl_bpix	= LCD_BPP,
-	.vl_lbw		= 0,
-	.vl_splt	= 0,
-	.vl_clor	= 0,
-	.vl_tft		= 1,
-	.vl_hpw		= 9,
-	.vl_blw		= 8,
-	.vl_elw		= 24,
-	.vl_vpw		= 2,
-	.vl_bfw		= 2,
-	.vl_efw		= 4,
-};
-#endif /* CONFIG_LITTLETON_LCD */
-
-/*----------------------------------------------------------------------*/
-
-#if LCD_BPP == LCD_COLOR8
-void lcd_setcolreg (ushort regno, ushort red, ushort green, ushort blue);
-#endif
-#if LCD_BPP == LCD_MONOCHROME
-void lcd_initcolregs (void);
-#endif
-
-#ifdef NOT_USED_SO_FAR
-void lcd_disable (void);
-void lcd_getcolreg (ushort regno, ushort *red, ushort *green, ushort *blue);
-#endif /* NOT_USED_SO_FAR */
-
-void lcd_ctrl_init	(void *lcdbase);
-void lcd_enable	(void);
-
-int lcd_line_length;
-int lcd_color_fg;
-int lcd_color_bg;
-
-void *lcd_base;			/* Start of framebuffer memory	*/
-void *lcd_console_address;		/* Start of console buffer	*/
-
-short console_col;
-short console_row;
-
-static int pxafb_init_mem (void *lcdbase, vidinfo_t *vid);
-static void pxafb_setup_gpio (vidinfo_t *vid);
-static void pxafb_enable_controller (vidinfo_t *vid);
-static int pxafb_init (vidinfo_t *vid);
-/************************************************************************/
-
-/************************************************************************/
-/* ---------------  PXA chipset specific functions  ------------------- */
-/************************************************************************/
-
-void lcd_ctrl_init (void *lcdbase)
-{
-	pxafb_init_mem(lcdbase, &panel_info);
-	pxafb_init(&panel_info);
-	pxafb_setup_gpio(&panel_info);
-	pxafb_enable_controller(&panel_info);
-}
-
-/*----------------------------------------------------------------------*/
-#ifdef NOT_USED_SO_FAR
-void
-lcd_getcolreg (ushort regno, ushort *red, ushort *green, ushort *blue)
-{
-}
-#endif /* NOT_USED_SO_FAR */
-
-/*----------------------------------------------------------------------*/
-#if LCD_BPP == LCD_COLOR8
-void
-lcd_setcolreg (ushort regno, ushort red, ushort green, ushort blue)
-{
-	struct pxafb_info *fbi = &panel_info.pxa;
-	unsigned short *palette = (unsigned short *)fbi->palette;
-	u_int val;
-
-	if (regno < fbi->palette_size) {
-		val = ((red << 8) & 0xf800);
-		val |= ((green << 4) & 0x07e0);
-		val |= (blue & 0x001f);
-
-#ifdef LCD_INVERT_COLORS
-		palette[regno] = ~val;
-#else
-		palette[regno] = val;
-#endif
-	}
-
-	debug ("setcolreg: reg %2d @ %p: R=%02X G=%02X B=%02X => %04X\n",
-		regno, &palette[regno],
-		red, green, blue,
-		palette[regno]);
-}
-#endif /* LCD_COLOR8 */
-
-/*----------------------------------------------------------------------*/
-#if LCD_BPP == LCD_MONOCHROME
-void lcd_initcolregs (void)
-{
-	struct pxafb_info *fbi = &panel_info.pxa;
-	cmap = (ushort *)fbi->palette;
-	ushort regno;
-
-	for (regno = 0; regno < 16; regno++) {
-		cmap[regno * 2] = 0;
-		cmap[(regno * 2) + 1] = regno & 0x0f;
-	}
-}
-#endif /* LCD_MONOCHROME */
-
-/*----------------------------------------------------------------------*/
-void lcd_enable (void)
-{
-}
-
-/*----------------------------------------------------------------------*/
-#ifdef	NOT_USED_SO_FAR
-static void lcd_disable (void)
-{
-}
-#endif /* NOT_USED_SO_FAR */
-
-/*----------------------------------------------------------------------*/
-
-/************************************************************************/
-/* ** PXA255 specific routines						*/
-/************************************************************************/
-
-/*
- * Calculate fb size for VIDEOLFB_ATAG. Size returned contains fb,
- * descriptors and palette areas.
- */
-ulong calc_fbsize (void)
-{
-	ulong size;
-	int line_length = (panel_info.vl_col * NBITS (panel_info.vl_bpix)) / 8;
-
-	size = line_length * panel_info.vl_row;
-	size += PAGE_SIZE;
-
-	return size;
-}
-
-static int pxafb_init_mem (void *lcdbase, vidinfo_t *vid)
-{
-	u_long palette_mem_size;
-	struct pxafb_info *fbi = &vid->pxa;
-	int fb_size = vid->vl_row * (vid->vl_col * NBITS (vid->vl_bpix)) / 8;
-
-	fbi->screen = (u_long)lcdbase;
-
-	fbi->palette_size = NBITS(vid->vl_bpix) == 8 ? 256 : 16;
-	palette_mem_size = fbi->palette_size * sizeof(u16);
-
-	debug("palette_mem_size = 0x%08lx\n", (u_long) palette_mem_size);
-	/* locate palette and descs at end of page following fb */
-	fbi->palette = (u_long)lcdbase + fb_size + PAGE_SIZE - palette_mem_size;
-
-	return 0;
-}
-#ifdef	CONFIG_CPU_MONAHANS
-static inline void pxafb_setup_gpio (vidinfo_t *vid) {}
-#else
-static void pxafb_setup_gpio (vidinfo_t *vid)
-{
-	u_long lccr0;
-
-	/*
-	 * setup is based on type of panel supported
-	 */
-
-	lccr0 = vid->pxa.reg_lccr0;
-
-	/* 4 bit interface */
-	if ((lccr0 & LCCR0_CMS) && (lccr0 & LCCR0_SDS) && !(lccr0 & LCCR0_DPD))
-	{
-		debug("Setting GPIO for 4 bit data\n");
-		/* bits 58-61 */
-		writel(readl(GPDR1) | (0xf << 26), GPDR1);
-		writel((readl(GAFR1_U) & ~(0xff << 20)) | (0xaa << 20),
-			GAFR1_U);
-
-		/* bits 74-77 */
-		writel(readl(GPDR2) | (0xf << 10), GPDR2);
-		writel((readl(GAFR2_L) & ~(0xff << 20)) | (0xaa << 20),
-			GAFR2_L);
-	}
-
-	/* 8 bit interface */
-	else if (((lccr0 & LCCR0_CMS) && ((lccr0 & LCCR0_SDS) || (lccr0 & LCCR0_DPD))) ||
-		(!(lccr0 & LCCR0_CMS) && !(lccr0 & LCCR0_PAS) && !(lccr0 & LCCR0_SDS)))
-	{
-		debug("Setting GPIO for 8 bit data\n");
-		/* bits 58-65 */
-		writel(readl(GPDR1) | (0x3f << 26), GPDR1);
-		writel(readl(GPDR2) | (0x3), GPDR2);
-
-		writel((readl(GAFR1_U) & ~(0xfff << 20)) | (0xaaa << 20),
-			GAFR1_U);
-		writel((readl(GAFR2_L) & ~0xf) | (0xa), GAFR2_L);
-
-		/* bits 74-77 */
-		writel(readl(GPDR2) | (0xf << 10), GPDR2);
-		writel((readl(GAFR2_L) & ~(0xff << 20)) | (0xaa << 20),
-			GAFR2_L);
-	}
-
-	/* 16 bit interface */
-	else if (!(lccr0 & LCCR0_CMS) && ((lccr0 & LCCR0_SDS) || (lccr0 & LCCR0_PAS)))
-	{
-		debug("Setting GPIO for 16 bit data\n");
-		/* bits 58-77 */
-		writel(readl(GPDR1) | (0x3f << 26), GPDR1);
-		writel(readl(GPDR2) | 0x00003fff, GPDR2);
-
-		writel((readl(GAFR1_U) & ~(0xfff << 20)) | (0xaaa << 20),
-			GAFR1_U);
-		writel((readl(GAFR2_L) & 0xf0000000) | 0x0aaaaaaa, GAFR2_L);
-	}
-	else
-	{
-		printf("pxafb_setup_gpio: unable to determine bits per pixel\n");
-	}
-}
-#endif
-
-static void pxafb_enable_controller (vidinfo_t *vid)
-{
-	debug("Enabling LCD controller\n");
-
-	/* Sequence from 11.7.10 */
-	writel(vid->pxa.reg_lccr3, LCCR3);
-	writel(vid->pxa.reg_lccr2, LCCR2);
-	writel(vid->pxa.reg_lccr1, LCCR1);
-	writel(vid->pxa.reg_lccr0 & ~LCCR0_ENB, LCCR0);
-	writel(vid->pxa.fdadr0, FDADR0);
-	writel(vid->pxa.fdadr1, FDADR1);
-	writel(readl(LCCR0) | LCCR0_ENB, LCCR0);
-
-#ifdef	CONFIG_CPU_MONAHANS
-	writel(readl(CKENA) | CKENA_1_LCD, CKENA);
-#else
-	writel(readl(CKEN) | CKEN16_LCD, CKEN);
-#endif
-
-	debug("FDADR0 = 0x%08x\n", readl(FDADR0));
-	debug("FDADR1 = 0x%08x\n", readl(FDADR1));
-	debug("LCCR0 = 0x%08x\n", readl(LCCR0));
-	debug("LCCR1 = 0x%08x\n", readl(LCCR1));
-	debug("LCCR2 = 0x%08x\n", readl(LCCR2));
-	debug("LCCR3 = 0x%08x\n", readl(LCCR3));
-}
-
-static int pxafb_init (vidinfo_t *vid)
-{
-	struct pxafb_info *fbi = &vid->pxa;
-
-	debug("Configuring PXA LCD\n");
-
-	fbi->reg_lccr0 = REG_LCCR0;
-	fbi->reg_lccr3 = REG_LCCR3;
-
-	debug("vid: vl_col=%d hslen=%d lm=%d rm=%d\n",
-		vid->vl_col, vid->vl_hpw,
-		vid->vl_blw, vid->vl_elw);
-	debug("vid: vl_row=%d vslen=%d um=%d bm=%d\n",
-		vid->vl_row, vid->vl_vpw,
-		vid->vl_bfw, vid->vl_efw);
-
-	fbi->reg_lccr1 =
-		LCCR1_DisWdth(vid->vl_col) +
-		LCCR1_HorSnchWdth(vid->vl_hpw) +
-		LCCR1_BegLnDel(vid->vl_blw) +
-		LCCR1_EndLnDel(vid->vl_elw);
-
-	fbi->reg_lccr2 =
-		LCCR2_DisHght(vid->vl_row) +
-		LCCR2_VrtSnchWdth(vid->vl_vpw) +
-		LCCR2_BegFrmDel(vid->vl_bfw) +
-		LCCR2_EndFrmDel(vid->vl_efw);
-
-	fbi->reg_lccr3 = REG_LCCR3 & ~(LCCR3_HSP | LCCR3_VSP);
-	fbi->reg_lccr3 |= (vid->vl_hsp ? LCCR3_HorSnchL : LCCR3_HorSnchH)
-			| (vid->vl_vsp ? LCCR3_VrtSnchL : LCCR3_VrtSnchH);
-
-
-	/* setup dma descriptors */
-	fbi->dmadesc_fblow = (struct pxafb_dma_descriptor *)((unsigned int)fbi->palette - 3*16);
-	fbi->dmadesc_fbhigh = (struct pxafb_dma_descriptor *)((unsigned int)fbi->palette - 2*16);
-	fbi->dmadesc_palette = (struct pxafb_dma_descriptor *)((unsigned int)fbi->palette - 1*16);
-
-	#define BYTES_PER_PANEL	((fbi->reg_lccr0 & LCCR0_SDS) ? \
-		(vid->vl_col * vid->vl_row * NBITS(vid->vl_bpix) / 8 / 2) : \
-		(vid->vl_col * vid->vl_row * NBITS(vid->vl_bpix) / 8))
-
-	/* populate descriptors */
-	fbi->dmadesc_fblow->fdadr = (u_long)fbi->dmadesc_fblow;
-	fbi->dmadesc_fblow->fsadr = fbi->screen + BYTES_PER_PANEL;
-	fbi->dmadesc_fblow->fidr  = 0;
-	fbi->dmadesc_fblow->ldcmd = BYTES_PER_PANEL;
-
-	fbi->fdadr1 = (u_long)fbi->dmadesc_fblow; /* only used in dual-panel mode */
-
-	fbi->dmadesc_fbhigh->fsadr = fbi->screen;
-	fbi->dmadesc_fbhigh->fidr = 0;
-	fbi->dmadesc_fbhigh->ldcmd = BYTES_PER_PANEL;
-
-	fbi->dmadesc_palette->fsadr = fbi->palette;
-	fbi->dmadesc_palette->fidr  = 0;
-	fbi->dmadesc_palette->ldcmd = (fbi->palette_size * 2) | LDCMD_PAL;
-
-	if( NBITS(vid->vl_bpix) < 12)
-	{
-		/* assume any mode with <12 bpp is palette driven */
-		fbi->dmadesc_palette->fdadr = (u_long)fbi->dmadesc_fbhigh;
-		fbi->dmadesc_fbhigh->fdadr = (u_long)fbi->dmadesc_palette;
-		/* flips back and forth between pal and fbhigh */
-		fbi->fdadr0 = (u_long)fbi->dmadesc_palette;
-	}
-	else
-	{
-		/* palette shouldn't be loaded in true-color mode */
-		fbi->dmadesc_fbhigh->fdadr = (u_long)fbi->dmadesc_fbhigh;
-		fbi->fdadr0 = (u_long)fbi->dmadesc_fbhigh; /* no pal just fbhigh */
-	}
-
-	debug("fbi->dmadesc_fblow = 0x%lx\n", (u_long)fbi->dmadesc_fblow);
-	debug("fbi->dmadesc_fbhigh = 0x%lx\n", (u_long)fbi->dmadesc_fbhigh);
-	debug("fbi->dmadesc_palette = 0x%lx\n", (u_long)fbi->dmadesc_palette);
-
-	debug("fbi->dmadesc_fblow->fdadr = 0x%lx\n", fbi->dmadesc_fblow->fdadr);
-	debug("fbi->dmadesc_fbhigh->fdadr = 0x%lx\n", fbi->dmadesc_fbhigh->fdadr);
-	debug("fbi->dmadesc_palette->fdadr = 0x%lx\n", fbi->dmadesc_palette->fdadr);
-
-	debug("fbi->dmadesc_fblow->fsadr = 0x%lx\n", fbi->dmadesc_fblow->fsadr);
-	debug("fbi->dmadesc_fbhigh->fsadr = 0x%lx\n", fbi->dmadesc_fbhigh->fsadr);
-	debug("fbi->dmadesc_palette->fsadr = 0x%lx\n", fbi->dmadesc_palette->fsadr);
-
-	debug("fbi->dmadesc_fblow->ldcmd = 0x%lx\n", fbi->dmadesc_fblow->ldcmd);
-	debug("fbi->dmadesc_fbhigh->ldcmd = 0x%lx\n", fbi->dmadesc_fbhigh->ldcmd);
-	debug("fbi->dmadesc_palette->ldcmd = 0x%lx\n", fbi->dmadesc_palette->ldcmd);
-
-	return 0;
-}
-
-/************************************************************************/
-/************************************************************************/
-
-#endif /* CONFIG_LCD */
diff --git a/arch/arm/cpu/pxa/start.S b/arch/arm/cpu/pxa/start.S
deleted file mode 100644
index d2d391e..0000000
--- a/arch/arm/cpu/pxa/start.S
+++ /dev/null
@@ -1,603 +0,0 @@
-/*
- *  armboot - Startup Code for XScale
- *
- *  Copyright (C) 1998	Dan Malek <dmalek@jlc.net>
- *  Copyright (C) 1999	Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
- *  Copyright (C) 2000	Wolfgang Denk <wd@denx.de>
- *  Copyright (C) 2001	Alex Zuepke <azu@sysgo.de>
- *  Copyright (C) 2002	Kyle Harris <kharris@nexus-tech.net>
- *  Copyright (C) 2003	Robert Schwebel <r.schwebel@pengutronix.de>
- *  Copyright (C) 2003	Kai-Uwe Bloem <kai-uwe.bloem@auerswald.de>
- *  Copyright (c) 2010	Marek Vasut <marek.vasut@gmail.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <asm-offsets.h>
-#include <config.h>
-#include <version.h>
-#include <asm/arch/pxa-regs.h>
-
-/* takes care the CP15 update has taken place */
-.macro CPWAIT reg
-mrc  p15,0,\reg,c2,c0,0
-mov  \reg,\reg
-sub  pc,pc,#4
-.endm
-
-.globl _start
-_start: b	reset
-#ifdef CONFIG_PRELOADER
-	ldr	pc, _hang
-	ldr	pc, _hang
-	ldr	pc, _hang
-	ldr	pc, _hang
-	ldr	pc, _hang
-	ldr	pc, _hang
-	ldr	pc, _hang
-
-_hang:
-	.word	do_hang
-	.word	0x12345678
-	.word	0x12345678
-	.word	0x12345678
-	.word	0x12345678
-	.word	0x12345678
-	.word	0x12345678
-	.word	0x12345678	/* now 16*4=64 */
-#else
-	ldr	pc, _undefined_instruction
-	ldr	pc, _software_interrupt
-	ldr	pc, _prefetch_abort
-	ldr	pc, _data_abort
-	ldr	pc, _not_used
-	ldr	pc, _irq
-	ldr	pc, _fiq
-
-_undefined_instruction: .word undefined_instruction
-_software_interrupt:	.word software_interrupt
-_prefetch_abort:	.word prefetch_abort
-_data_abort:		.word data_abort
-_not_used:		.word not_used
-_irq:			.word irq
-_fiq:			.word fiq
-#endif	/* CONFIG_PRELOADER */
-
-	.balignl 16,0xdeadbeef
-
-
-/*
- * Startup Code (reset vector)
- *
- * do important init only if we don't start from RAM!
- * - relocate armboot to RAM
- * - setup stack
- * - jump to second stage
- */
-
-.globl _TEXT_BASE
-_TEXT_BASE:
-	.word	CONFIG_SYS_TEXT_BASE
-
-/*
- * These are defined in the board-specific linker script.
- */
-.globl _bss_start_ofs
-_bss_start_ofs:
-	.word __bss_start - _start
-
-.globl _bss_end_ofs
-_bss_end_ofs:
-	.word _end - _start
-
-#ifdef CONFIG_USE_IRQ
-/* IRQ stack memory (calculated at run-time) */
-.globl IRQ_STACK_START
-IRQ_STACK_START:
-	.word	0x0badc0de
-
-/* IRQ stack memory (calculated at run-time) */
-.globl FIQ_STACK_START
-FIQ_STACK_START:
-	.word 0x0badc0de
-#endif /* CONFIG_USE_IRQ */
-
-#ifndef CONFIG_PRELOADER
-/* IRQ stack memory (calculated at run-time) + 8 bytes */
-.globl IRQ_STACK_START_IN
-IRQ_STACK_START_IN:
-	.word	0x0badc0de
-
-/*
- * the actual reset code
- */
-
-reset:
-	/*
-	 * set the cpu to SVC32 mode
-	 */
-	mrs	r0,cpsr
-	bic	r0,r0,#0x1f
-	orr	r0,r0,#0xd3
-	msr	cpsr,r0
-
-	/*
-	 * Enable MMU to use DCache as DRAM
-	 */
-	/* Domain access -- enable for all CPs */
-	ldr	r0, =0x0000ffff
-	mcr	p15, 0, r0, c3, c0, 0
-
-	/* Point TTBR to MMU table */
-	ldr	r0, =mmu_table
-	adr	r2, _start
-	orr	r0, r2
-	mcr	p15, 0, r0, c2, c0, 0
-
-/* !!! Hereby, check if the code is running from SRAM !!! */
-/* If the code is running from SRAM, alias SRAM to 0x0 to simulate NOR. The code
- * is linked to 0x0 too, so this makes things easier. */
-	cmp	r2, #0x5c000000
-
-	ldreq	r1, [r0]
-	orreq	r1, r2
-	streq	r1, [r0]
-
-	/* Kick in MMU, ICache, DCache, BTB */
-	mrc	p15, 0, r0, c1, c0, 0
-	bic	r0, #0x1b00
-	bic	r0, #0x0087
-	orr	r0, #0x1800
-	orr	r0, #0x0005
-	mcr	p15, 0, r0, c1, c0, 0
-	CPWAIT	r0
-
-	/* Unlock Icache, Dcache */
-	mcr	p15, 0, r0, c9, c1, 1
-	mcr	p15, 0, r0, c9, c2, 1
-
-	/* Flush Icache, Dcache, BTB */
-	mcr	p15, 0, r0, c7, c7, 0
-
-	/* Unlock I-TLB, D-TLB */
-	mcr	p15, 0, r0, c10, c4, 1
-	mcr	p15, 0, r0, c10, c8, 1
-
-	/* Flush TLB */
-	mcr	p15, 0, r0, c8, c7, 0
-	/* Allocate 4096 bytes of Dcache as RAM */
-
-	/* Drain pending loads and stores */
-	mcr	p15, 0, r0, c7, c10, 4
-
-	mov	r4, #0x00
-	mov	r5, #0x00
-	mov	r2, #0x01
-	mcr	p15, 0, r0, c9, c2, 0
-	CPWAIT	r0
-
-	/* 128 lines reserved (128 x 32bytes = 4096 bytes total) */
-	mov	r0, #128
-	mov	r1, #0xa0000000
-alloc:
-	mcr	p15, 0, r1, c7, c2, 5
-	/* Drain pending loads and stores */
-	mcr	p15, 0, r0, c7, c10, 4
-	strd	r4, [r1], #8
-	strd	r4, [r1], #8
-	strd	r4, [r1], #8
-	strd	r4, [r1], #8
-	subs	r0, #0x01
-	bne	alloc
-	/* Drain pending loads and stores */
-	mcr	p15, 0, r0, c7, c10, 4
-	mov	r2, #0x00
-	mcr	p15, 0, r2, c9, c2, 0
-	CPWAIT	r0
-
-	/* Jump to 0x0 ( + offset) if running from SRAM */
-	adr	r0, zerojmp
-	bic	r0, #0x5c000000
-	mov	pc, r0
-zerojmp:
-
-/* Set stackpointer in internal RAM to call board_init_f */
-call_board_init_f:
-	ldr	sp, =(CONFIG_SYS_INIT_SP_ADDR)
-	bic	sp, sp, #7 /* 8-byte alignment for ABI compliance */
-	ldr	r0,=0x00000000
-	bl	board_init_f
-
-/*------------------------------------------------------------------------------*/
-
-/*
- * void relocate_code (addr_sp, gd, addr_moni)
- *
- * This "function" does not return, instead it continues in RAM
- * after relocating the monitor code.
- *
- */
-	.globl	relocate_code
-relocate_code:
-	mov	r4, r0	/* save addr_sp */
-	mov	r5, r1	/* save addr of gd */
-	mov	r6, r2	/* save addr of destination */
-
-	/* Set up the stack						    */
-stack_setup:
-	mov	sp, r4
-
-	adr	r0, _start
-	cmp	r0, r6
-	beq	clear_bss		/* skip relocation */
-	mov	r1, r6			/* r1 <- scratch for copy_loop */
-	ldr	r3, _bss_start_ofs
-	add	r2, r0, r3		/* r2 <- source end address	    */
-
-	stmfd sp!, {r0-r12}
-copy_loop:
-	ldmia	r0!, {r3-r5, r7-r11}	/* copy from source address [r0]    */
-	stmia	r1!, {r3-r5, r7-r11}	/* copy to   target address [r1]    */
-	cmp	r0, r2			/* until source end address [r2]    */
-	blo	copy_loop
-	ldmfd sp!, {r0-r12}
-
-#ifndef CONFIG_PRELOADER
-	/*
-	 * fix .rel.dyn relocations
-	 */
-	ldr	r0, _TEXT_BASE		/* r0 <- Text base */
-	sub	r9, r6, r0		/* r9 <- relocation offset */
-	ldr	r10, _dynsym_start_ofs	/* r10 <- sym table ofs */
-	add	r10, r10, r0		/* r10 <- sym table in FLASH */
-	ldr	r2, _rel_dyn_start_ofs	/* r2 <- rel dyn start ofs */
-	add	r2, r2, r0		/* r2 <- rel dyn start in FLASH */
-	ldr	r3, _rel_dyn_end_ofs	/* r3 <- rel dyn end ofs */
-	add	r3, r3, r0		/* r3 <- rel dyn end in FLASH */
-fixloop:
-	ldr	r0, [r2]	/* r0 <- location to fix up, IN FLASH! */
-	add	r0, r9		/* r0 <- location to fix up in RAM */
-	ldr	r1, [r2, #4]
-	and	r7, r1, #0xff
-	cmp	r7, #23		/* relative fixup? */
-	beq	fixrel
-	cmp	r7, #2		/* absolute fixup? */
-	beq	fixabs
-	/* ignore unknown type of fixup */
-	b	fixnext
-fixabs:
-	/* absolute fix: set location to (offset) symbol value */
-	mov	r1, r1, LSR #4		/* r1 <- symbol index in .dynsym */
-	add	r1, r10, r1		/* r1 <- address of symbol in table */
-	ldr	r1, [r1, #4]		/* r1 <- symbol value */
-	add	r1, r1, r9		/* r1 <- relocated sym addr */
-	b	fixnext
-fixrel:
-	/* relative fix: increase location by offset */
-	ldr	r1, [r0]
-	add	r1, r1, r9
-fixnext:
-	str	r1, [r0]
-	add	r2, r2, #8	/* each rel.dyn entry is 8 bytes */
-	cmp	r2, r3
-	blo	fixloop
-#endif	/* #ifndef CONFIG_PRELOADER */
-
-clear_bss:
-#ifndef CONFIG_PRELOADER
-	ldr	r0, _bss_start_ofs
-	ldr	r1, _bss_end_ofs
-	mov	r4, r6			/* reloc addr */
-	add	r0, r0, r4
-	add	r1, r1, r4
-	mov	r2, #0x00000000		/* clear			    */
-
-clbss_l:str	r2, [r0]		/* clear loop...		    */
-	add	r0, r0, #4
-	cmp	r0, r1
-	bne	clbss_l
-#endif	/* #ifndef CONFIG_PRELOADER */
-
-/*
- * We are done. Do not return, instead branch to second part of board
- * initialization, now running from RAM.
- */
-#ifdef CONFIG_ONENAND_IPL
-	ldr     r0, _start_oneboot_ofs
-	mov	pc, r0
-
-_start_oneboot_ofs
-	: .word start_oneboot
-#else
-	ldr	r0, _board_init_r_ofs
-	adr	r1, _start
-	add	lr, r0, r1
-	add	lr, lr, r9
-	/* setup parameters for board_init_r */
-	mov	r0, r5		/* gd_t */
-	mov	r1, r6		/* dest_addr */
-	/* jump to it ... */
-	mov	pc, lr
-
-_board_init_r_ofs:
-	.word board_init_r - _start
-#endif	/* CONFIG_ONENAND_IPL */
-
-_rel_dyn_start_ofs:
-	.word __rel_dyn_start - _start
-_rel_dyn_end_ofs:
-	.word __rel_dyn_end - _start
-_dynsym_start_ofs:
-	.word __dynsym_start - _start
-
-#else /* CONFIG_PRELOADER */
-
-/****************************************************************************/
-/*									    */
-/* the actual reset code for OneNAND IPL				    */
-/*									    */
-/****************************************************************************/
-
-#ifndef	CONFIG_PXA27X
-#error OneNAND IPL is not supported on PXA25x and 26x due to lack of SRAM
-#endif
-
-reset:
-	/* Set CPU to SVC32 mode */
-	mrs	r0,cpsr
-	bic	r0,r0,#0x1f
-	orr	r0,r0,#0x13
-	msr	cpsr,r0
-
-	/* Point stack at the end of SRAM and leave 32 words for abort-stack */
-	ldr	sp, =0x5c03ff80
-
-	/* Start OneNAND IPL */
-	ldr	pc, =start_oneboot
-
-#endif /* CONFIG_PRELOADER */
-
-#ifndef CONFIG_PRELOADER
-/****************************************************************************/
-/*									    */
-/* Interrupt handling							    */
-/*									    */
-/****************************************************************************/
-
-/* IRQ stack frame							    */
-
-#define S_FRAME_SIZE	72
-
-#define S_OLD_R0	68
-#define S_PSR		64
-#define S_PC		60
-#define S_LR		56
-#define S_SP		52
-
-#define S_IP		48
-#define S_FP		44
-#define S_R10		40
-#define S_R9		36
-#define S_R8		32
-#define S_R7		28
-#define S_R6		24
-#define S_R5		20
-#define S_R4		16
-#define S_R3		12
-#define S_R2		8
-#define S_R1		4
-#define S_R0		0
-
-#define MODE_SVC 0x13
-
-	/* use bad_save_user_regs for abort/prefetch/undef/swi ...	    */
-
-	.macro	bad_save_user_regs
-	sub	sp, sp, #S_FRAME_SIZE
-	stmia	sp, {r0 - r12}			/* Calling r0-r12	    */
-	add	r8, sp, #S_PC
-
-	ldr	r2, IRQ_STACK_START_IN
-	ldmia	r2, {r2 - r4}			/* get pc, cpsr, old_r0	    */
-	add	r0, sp, #S_FRAME_SIZE		/* restore sp_SVC	    */
-
-	add	r5, sp, #S_SP
-	mov	r1, lr
-	stmia	r5, {r0 - r4}			/* save sp_SVC, lr_SVC, pc, cpsr, old_r */
-	mov	r0, sp
-	.endm
-
-
-	/* use irq_save_user_regs / irq_restore_user_regs for		     */
-	/* IRQ/FIQ handling						     */
-
-	.macro	irq_save_user_regs
-	sub	sp, sp, #S_FRAME_SIZE
-	stmia	sp, {r0 - r12}			/* Calling r0-r12	     */
-	add	r8, sp, #S_PC
-	stmdb	r8, {sp, lr}^			/* Calling SP, LR	     */
-	str	lr, [r8, #0]			/* Save calling PC	     */
-	mrs	r6, spsr
-	str	r6, [r8, #4]			/* Save CPSR		     */
-	str	r0, [r8, #8]			/* Save OLD_R0		     */
-	mov	r0, sp
-	.endm
-
-	.macro	irq_restore_user_regs
-	ldmia	sp, {r0 - lr}^			@ Calling r0 - lr
-	mov	r0, r0
-	ldr	lr, [sp, #S_PC]			@ Get PC
-	add	sp, sp, #S_FRAME_SIZE
-	subs	pc, lr, #4			@ return & move spsr_svc into cpsr
-	.endm
-
-	.macro get_bad_stack
-	ldr	r13, IRQ_STACK_START_IN		@ setup our mode stack
-
-	str	lr, [r13]			@ save caller lr / spsr
-	mrs	lr, spsr
-	str	lr, [r13, #4]
-
-	mov	r13, #MODE_SVC			@ prepare SVC-Mode
-	msr	spsr_c, r13
-	mov	lr, pc
-	movs	pc, lr
-	.endm
-
-	.macro get_irq_stack			@ setup IRQ stack
-	ldr	sp, IRQ_STACK_START
-	.endm
-
-	.macro get_fiq_stack			@ setup FIQ stack
-	ldr	sp, FIQ_STACK_START
-	.endm
-#endif	/* CONFIG_PRELOADER
-
-
-/****************************************************************************/
-/*									    */
-/* exception handlers							    */
-/*									    */
-/****************************************************************************/
-
-#ifdef CONFIG_PRELOADER
-	.align	5
-do_hang:
-	ldr	sp, _TEXT_BASE			/* use 32 words abort stack */
-	bl	hang				/* hang and never return */
-#else
-	.align	5
-undefined_instruction:
-	get_bad_stack
-	bad_save_user_regs
-	bl	do_undefined_instruction
-
-	.align	5
-software_interrupt:
-	get_bad_stack
-	bad_save_user_regs
-	bl	do_software_interrupt
-
-	.align	5
-prefetch_abort:
-	get_bad_stack
-	bad_save_user_regs
-	bl	do_prefetch_abort
-
-	.align	5
-data_abort:
-	get_bad_stack
-	bad_save_user_regs
-	bl	do_data_abort
-
-	.align	5
-not_used:
-	get_bad_stack
-	bad_save_user_regs
-	bl	do_not_used
-
-#ifdef CONFIG_USE_IRQ
-
-	.align	5
-irq:
-	get_irq_stack
-	irq_save_user_regs
-	bl	do_irq
-	irq_restore_user_regs
-
-	.align	5
-fiq:
-	get_fiq_stack
-	irq_save_user_regs		/* someone ought to write a more    */
-	bl	do_fiq			/* effiction fiq_save_user_regs	    */
-	irq_restore_user_regs
-
-#else /* !CONFIG_USE_IRQ */
-
-	.align	5
-irq:
-	get_bad_stack
-	bad_save_user_regs
-	bl	do_irq
-
-	.align	5
-fiq:
-	get_bad_stack
-	bad_save_user_regs
-	bl	do_fiq
-#endif	/* CONFIG_PRELOADER */
-#endif /* CONFIG_USE_IRQ */
-
-/****************************************************************************/
-/*									    */
-/* Reset function: the PXA250 doesn't have a reset function, so we have to  */
-/* perform a watchdog timeout for a soft reset.				    */
-/*									    */
-/****************************************************************************/
-/* Operating System Timer */
-.align	5
-.globl reset_cpu
-
-	/* FIXME: this code is PXA250 specific. How is this handled on	    */
-	/*	  other XScale processors?				    */
-
-reset_cpu:
-
-	/* We set OWE:WME (watchdog enable) and wait until timeout happens  */
-
-	ldr	r0, =OWER
-	ldr	r1, [r0]
-	orr	r1, r1, #0x0001			/* bit0: WME		    */
-	str	r1, [r0]
-
-	/* OS timer does only wrap every 1165 seconds, so we have to set    */
-	/* the match register as well.					    */
-
-	ldr	r0, =OSCR
-	ldr	r1, [r0]			/* read OS timer	    */
-	add	r1, r1, #0x800			/* let OSMR3 match after    */
-	add	r1, r1, #0x800			/* 4096*(1/3.6864MHz)=1ms   */
-	ldr	r0, =OSMR3
-	str	r1, [r0]
-
-reset_endless:
-
-	b	reset_endless
-
-#ifndef CONFIG_PRELOADER
-.section .mmudata, "a"
-	.align	14
-	.globl	mmu_table
-mmu_table:
-	/* 0x00000000 - 0xa0000000 : 1:1, uncached mapping */
-	.set	__base, 0
-	.rept	0xa00
-	.word	(__base << 20) | 0xc12
-	.set	__base, __base + 1
-	.endr
-
-	/* 0xa0000000 - 0xa0100000 : 1:1, cached mapping */
-	.word	(0xa00 << 20) | 0x1c1e
-
-	.set	__base, 0xa01
-	.rept	0x1000 - 0xa01
-	.word	(__base << 20) | 0xc12
-	.set	__base, __base + 1
-	.endr
-#endif	/* CONFIG_PRELOADER */
diff --git a/arch/arm/cpu/pxa/timer.c b/arch/arm/cpu/pxa/timer.c
deleted file mode 100644
index ec950c7..0000000
--- a/arch/arm/cpu/pxa/timer.c
+++ /dev/null
@@ -1,129 +0,0 @@
-/*
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Alex Zuepke <azu@sysgo.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <asm/arch/pxa-regs.h>
-#include <asm/io.h>
-#include <common.h>
-#include <div64.h>
-
-#ifdef CONFIG_USE_IRQ
-#error: interrupts not implemented yet
-#endif
-
-#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
-#define TIMER_FREQ_HZ 3250000
-#elif defined(CONFIG_PXA250)
-#define TIMER_FREQ_HZ 3686400
-#else
-#error "Timer frequency unknown - please config PXA CPU type"
-#endif
-
-static inline unsigned long long tick_to_time(unsigned long long tick)
-{
-	tick *= CONFIG_SYS_HZ;
-	do_div(tick, TIMER_FREQ_HZ);
-	return tick;
-}
-
-static inline unsigned long long us_to_tick(unsigned long long us)
-{
-	us = us * TIMER_FREQ_HZ + 999999;
-	do_div(us, 1000000);
-	return us;
-}
-
-int timer_init (void)
-{
-	reset_timer();
-
-	return 0;
-}
-
-void reset_timer (void)
-{
-	reset_timer_masked ();
-}
-
-ulong get_timer (ulong base)
-{
-	return get_timer_masked () - base;
-}
-
-void set_timer (ulong t)
-{
-	/* nop */
-}
-
-void __udelay (unsigned long usec)
-{
-	udelay_masked (usec);
-}
-
-
-void reset_timer_masked (void)
-{
-	writel(0, OSCR);
-}
-
-ulong get_timer_masked (void)
-{
-	return tick_to_time(get_ticks());
-}
-
-void udelay_masked (unsigned long usec)
-{
-	unsigned long long tmp;
-	ulong tmo;
-
-	tmo = us_to_tick(usec);
-	tmp = get_ticks() + tmo;	/* get current timestamp */
-
-	while (get_ticks() < tmp)	/* loop till event */
-		 /*NOP*/;
-
-}
-
-/*
- * This function is derived from PowerPC code (read timebase as long long).
- * On ARM it just returns the timer value.
- */
-unsigned long long get_ticks(void)
-{
-	return readl(OSCR);
-}
-
-/*
- * This function is derived from PowerPC code (timebase clock frequency).
- * On ARM it returns the number of timer ticks per second.
- */
-ulong get_tbclk (void)
-{
-	ulong tbclk;
-	tbclk = TIMER_FREQ_HZ;
-	return tbclk;
-}
diff --git a/arch/arm/cpu/pxa/u-boot.lds b/arch/arm/cpu/pxa/u-boot.lds
deleted file mode 100644
index 0818d0b..0000000
--- a/arch/arm/cpu/pxa/u-boot.lds
+++ /dev/null
@@ -1,78 +0,0 @@
-/*
- * (C) Copyright 2000-2005
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-ENTRY(_start)
-SECTIONS
-{
-	. = 0x00000000;
-
-	. = ALIGN(4);
-	.text :
-	{
-		arch/arm/cpu/pxa/start.o	(.text)
-		*(.text)
-	}
-
-	. = ALIGN(4);
-	.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
-
-	. = ALIGN(4);
-	.data : {
-		*(.data)
-	}
-
-	. = ALIGN(4);
-
-	. = .;
-	__u_boot_cmd_start = .;
-	.u_boot_cmd : { *(.u_boot_cmd) }
-	__u_boot_cmd_end = .;
-
-	. = ALIGN(4);
-
-	.rel.dyn : {
-		__rel_dyn_start = .;
-		*(.rel*)
-		__rel_dyn_end = .;
-	}
-
-	.dynsym : {
-		__dynsym_start = .;
-		*(.dynsym)
-	}
-
-	.bss __rel_dyn_start (OVERLAY) : {
-		__bss_start = .;
-		*(.bss)
-		 . = ALIGN(4);
-		_end = .;
-	}
-
-	/DISCARD/ : { *(.dynstr*) }
-	/DISCARD/ : { *(.dynamic*) }
-	/DISCARD/ : { *(.plt*) }
-	/DISCARD/ : { *(.interp*) }
-	/DISCARD/ : { *(.gnu*) }
-}
diff --git a/arch/arm/cpu/pxa/usb.c b/arch/arm/cpu/pxa/usb.c
deleted file mode 100644
index 0311d5e..0000000
--- a/arch/arm/cpu/pxa/usb.c
+++ /dev/null
@@ -1,105 +0,0 @@
-/*
- * (C) Copyright 2006
- * Markus Klotzbuecher, DENX Software Engineering <mk@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-
-#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT)
-# if defined(CONFIG_CPU_MONAHANS) || defined(CONFIG_PXA27X)
-
-#include <asm/arch/pxa-regs.h>
-#include <asm/io.h>
-#include <usb.h>
-
-int usb_cpu_init(void)
-{
-#if defined(CONFIG_CPU_MONAHANS)
-	/* Enable USB host clock. */
-	writel(readl(CKENA) | CKENA_2_USBHOST | CKENA_20_UDC, CKENA);
-	udelay(100);
-#endif
-#if defined(CONFIG_PXA27X)
-	/* Enable USB host clock. */
-	writel(readl(CKEN) | CKEN10_USBHOST, CKEN);
-#endif
-
-#if defined(CONFIG_CPU_MONAHANS)
-	/* Configure Port 2 for Host (USB Client Registers) */
-	writel(0x3000c, UP2OCR);
-#endif
-
-	writel(readl(UHCHR) | UHCHR_FHR, UHCHR);
-	wait_ms(11);
-	writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR);
-
-	writel(readl(UHCHR) | UHCHR_FSBIR, UHCHR);
-	while (readl(UHCHR) & UHCHR_FSBIR)
-		udelay(1);
-
-#if defined(CONFIG_CPU_MONAHANS)
-	writel(readl(UHCHR) & ~UHCHR_SSEP0, UHCHR);
-#endif
-#if defined(CONFIG_PXA27X)
-	writel(readl(UHCHR) & ~UHCHR_SSEP2, UHCHR);
-#endif
-	writel(readl(UHCHR) & ~(UHCHR_SSEP1 | UHCHR_SSE), UHCHR);
-
-	return 0;
-}
-
-int usb_cpu_stop(void)
-{
-	writel(readl(UHCHR) | UHCHR_FHR, UHCHR);
-	udelay(11);
-	writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR);
-
-	writel(readl(UHCCOMS) | UHCHR_FHR, UHCCOMS);
-	udelay(10);
-
-#if defined(CONFIG_CPU_MONAHANS)
-	writel(readl(UHCHR) | UHCHR_SSEP0, UHCHR);
-#endif
-#if defined(CONFIG_PXA27X)
-	writel(readl(UHCHR) | UHCHR_SSEP2, UHCHR);
-#endif
-	writel(readl(UHCHR) | UHCHR_SSEP1 | UHCHR_SSE, UHCHR);
-
-#if defined(CONFIG_CPU_MONAHANS)
-	/* Disable USB host clock. */
-	writel(readl(CKENA) & ~(CKENA_2_USBHOST | CKENA_20_UDC), CKENA);
-	udelay(100);
-#endif
-#if defined(CONFIG_PXA27X)
-	/* Disable USB host clock. */
-	writel(readl(CKEN) & ~CKEN10_USBHOST, CKEN);
-#endif
-
-	return 0;
-}
-
-int usb_cpu_init_fail(void)
-{
-	return usb_cpu_stop();
-}
-
-# endif /* defined(CONFIG_CPU_MONAHANS) || defined(CONFIG_PXA27X) */
-#endif /* defined(CONFIG_USB_OHCI) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT) */
diff --git a/arch/arm/cpu/s3c44b0/Makefile b/arch/arm/cpu/s3c44b0/Makefile
deleted file mode 100644
index 7742dc2..0000000
--- a/arch/arm/cpu/s3c44b0/Makefile
+++ /dev/null
@@ -1,50 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(CPU).o
-
-START	= start.o
-
-COBJS	+= cache.o
-COBJS	+= cpu.o
-COBJS	+= timer.o
-
-SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
-START	:= $(addprefix $(obj),$(START))
-
-all:	$(obj).depend $(START) $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/arch/arm/cpu/s3c44b0/cache.c b/arch/arm/cpu/s3c44b0/cache.c
deleted file mode 100644
index 66974f6..0000000
--- a/arch/arm/cpu/s3c44b0/cache.c
+++ /dev/null
@@ -1,90 +0,0 @@
-/*
- * (C) Copyright 2004
- * DAVE Srl
- * http://www.dave-tech.it
- * http://www.wawnet.biz
- * mailto:info@wawnet.biz
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <command.h>
-#include <asm/hardware.h>
-
-static void s3c44b0_flush_cache(void)
-{
-	volatile int i;
-	/* flush cycle */
-	for(i=0x10002000;i<0x10004800;i+=16)
-	{
-		*((int *)i)=0x0;
-	}
-}
-
-void icache_enable (void)
-{
-	ulong reg;
-
-	s3c44b0_flush_cache();
-
-	/*
-		Init cache
-		Non-cacheable area (everything outside RAM)
-		0x0000:0000 - 0x0C00:0000
-	 */
-	NCACHBE0 = 0xC0000000;
-	NCACHBE1 = 0x00000000;
-
-	/*
-		Enable chache
-	*/
-	reg = SYSCFG;
-	reg |= 0x00000006; /* 8kB */
-	SYSCFG = reg;
-}
-
-void icache_disable (void)
-{
-	ulong reg;
-
-	reg = SYSCFG;
-	reg &= ~0x00000006; /* 8kB */
-	SYSCFG = reg;
-}
-
-int icache_status (void)
-{
-	return 0;
-}
-
-void dcache_enable (void)
-{
-	icache_enable();
-}
-
-void dcache_disable (void)
-{
-	icache_disable();
-}
-
-int dcache_status (void)
-{
-	return dcache_status();
-}
diff --git a/arch/arm/cpu/s3c44b0/config.mk b/arch/arm/cpu/s3c44b0/config.mk
deleted file mode 100644
index 7454d72..0000000
--- a/arch/arm/cpu/s3c44b0/config.mk
+++ /dev/null
@@ -1,33 +0,0 @@
-#
-# (C) Copyright 2002
-# Sysgo Real-Time Solutions, GmbH <www.elinos.com>
-# Marius Groeger <mgroeger@sysgo.de>
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float
-
-PLATFORM_CPPFLAGS += -march=armv4 -mtune=arm7tdmi -msoft-float
-# =========================================================================
-#
-# Supply options according to compiler version
-#
-# ========================================================================
-PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))
diff --git a/arch/arm/cpu/s3c44b0/cpu.c b/arch/arm/cpu/s3c44b0/cpu.c
deleted file mode 100644
index bca38f8..0000000
--- a/arch/arm/cpu/s3c44b0/cpu.c
+++ /dev/null
@@ -1,74 +0,0 @@
-/*
- * (C) Copyright 2004
- * DAVE Srl
- * http://www.dave-tech.it
- * http://www.wawnet.biz
- * mailto:info@wawnet.biz
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * S3C44B0 CPU specific code
- */
-
-#include <common.h>
-#include <command.h>
-#include <asm/hardware.h>
-
-int arch_cpu_init (void)
-{
-	icache_enable();
-
-	return 0;
-}
-
-int cleanup_before_linux (void)
-{
-	/*
-		cache memory should be enabled before calling
-		Linux to make the kernel uncompression faster
-	*/
-	icache_enable();
-
-	disable_interrupts ();
-
-	return 0;
-}
-
-void reset_cpu (ulong addr)
-{
-	/*
-		reset the cpu using watchdog
-	*/
-
-	/* Disable the watchdog.*/
-	WTCON&=~(1<<5);
-
-	/* set the timeout value to a short time... */
-	WTCNT = 0x1;
-
-	/* Enable the watchdog. */
-	WTCON|=1;
-	WTCON|=(1<<5);
-
-	while(1) {
-		/*NOP*/
-	}
-}
diff --git a/arch/arm/cpu/s3c44b0/start.S b/arch/arm/cpu/s3c44b0/start.S
deleted file mode 100644
index 9c9c3b3..0000000
--- a/arch/arm/cpu/s3c44b0/start.S
+++ /dev/null
@@ -1,349 +0,0 @@
-/*
- * Startup Code for S3C44B0 CPU-core
- *
- * (C) Copyright 2004
- * DAVE Srl
- *
- * http://www.dave-tech.it
- * http://www.wawnet.biz
- * mailto:info@wawnet.biz
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <asm-offsets.h>
-#include <config.h>
-#include <version.h>
-
-/*
- * Jump vector table
- */
-
-
-.globl _start
-_start:	b       reset
-	add	pc, pc, #0x0c000000
-	add	pc, pc, #0x0c000000
-	add	pc, pc, #0x0c000000
-	add	pc, pc, #0x0c000000
-	add	pc, pc, #0x0c000000
-	add	pc, pc, #0x0c000000
-	add	pc, pc, #0x0c000000
-
-	.balignl 16,0xdeadbeef
-
-
-/*
- *************************************************************************
- *
- * Startup Code (reset vector)
- *
- * do important init only if we don't start from memory!
- * relocate u-boot to ram
- * setup stack
- * jump to second stage
- *
- *************************************************************************
- */
-
-.globl _TEXT_BASE
-_TEXT_BASE:
-	.word	CONFIG_SYS_TEXT_BASE
-
-/*
- * These are defined in the board-specific linker script.
- * Subtracting _start from them lets the linker put their
- * relative position in the executable instead of leaving
- * them null.
- */
-.globl _bss_start_ofs
-_bss_start_ofs:
-	.word __bss_start - _start
-
-.globl _bss_end_ofs
-_bss_end_ofs:
-	.word _end - _start
-
-#ifdef CONFIG_USE_IRQ
-/* IRQ stack memory (calculated at run-time) */
-.globl IRQ_STACK_START
-IRQ_STACK_START:
-	.word	0x0badc0de
-
-/* IRQ stack memory (calculated at run-time) */
-.globl FIQ_STACK_START
-FIQ_STACK_START:
-	.word 0x0badc0de
-#endif
-
-/* IRQ stack memory (calculated at run-time) + 8 bytes */
-.globl IRQ_STACK_START_IN
-IRQ_STACK_START_IN:
-	.word	0x0badc0de
-
-/*
- * the actual reset code
- */
-
-reset:
-	/*
-	 * set the cpu to SVC32 mode
-	 */
-	mrs	r0,cpsr
-	bic	r0,r0,#0x1f
-	orr	r0,r0,#0xd3
-	msr	cpsr,r0
-
-	/*
-	 * we do sys-critical inits only at reboot,
-	 * not when booting from ram!
-	 */
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
-	bl	cpu_init_crit
-	/*
-	 * before relocating, we have to setup RAM timing
-	 * because memory timing is board-dependend, you will
-	 * find a lowlevel_init.S in your board directory.
-	 */
-	bl	lowlevel_init
-#endif
-
-/* Set stackpointer in internal RAM to call board_init_f */
-call_board_init_f:
-	ldr	sp, =(CONFIG_SYS_INIT_SP_ADDR)
-	bic	sp, sp, #7 /* 8-byte alignment for ABI compliance */
-	ldr	r0,=0x00000000
-	bl	board_init_f
-
-/*------------------------------------------------------------------------------*/
-
-/*
- * void relocate_code (addr_sp, gd, addr_moni)
- *
- * This "function" does not return, instead it continues in RAM
- * after relocating the monitor code.
- *
- */
-	.globl	relocate_code
-relocate_code:
-	mov	r4, r0	/* save addr_sp */
-	mov	r5, r1	/* save addr of gd */
-	mov	r6, r2	/* save addr of destination */
-
-	/* Set up the stack						    */
-stack_setup:
-	mov	sp, r4
-
-	adr	r0, _start
-	cmp	r0, r6
-	beq	clear_bss		/* skip relocation */
-	mov	r1, r6			/* r1 <- scratch for copy_loop */
-	ldr	r3, _bss_start_ofs
-	add	r2, r0, r3		/* r2 <- source end address	    */
-
-copy_loop:
-	ldmia	r0!, {r9-r10}		/* copy from source address [r0]    */
-	stmia	r1!, {r9-r10}		/* copy to   target address [r1]    */
-	cmp	r0, r2			/* until source end address [r2]    */
-	blo	copy_loop
-
-#ifndef CONFIG_PRELOADER
-	/*
-	 * fix .rel.dyn relocations
-	 */
-	ldr	r0, _TEXT_BASE		/* r0 <- Text base */
-	sub	r9, r6, r0		/* r9 <- relocation offset */
-	ldr	r10, _dynsym_start_ofs	/* r10 <- sym table ofs */
-	add	r10, r10, r0		/* r10 <- sym table in FLASH */
-	ldr	r2, _rel_dyn_start_ofs	/* r2 <- rel dyn start ofs */
-	add	r2, r2, r0		/* r2 <- rel dyn start in FLASH */
-	ldr	r3, _rel_dyn_end_ofs	/* r3 <- rel dyn end ofs */
-	add	r3, r3, r0		/* r3 <- rel dyn end in FLASH */
-fixloop:
-	ldr	r0, [r2]		/* r0 <- location to fix up, IN FLASH! */
-	add	r0, r0, r9		/* r0 <- location to fix up in RAM */
-	ldr	r1, [r2, #4]
-	and	r7, r1, #0xff
-	cmp	r7, #23			/* relative fixup? */
-	beq	fixrel
-	cmp	r7, #2			/* absolute fixup? */
-	beq	fixabs
-	/* ignore unknown type of fixup */
-	b	fixnext
-fixabs:
-	/* absolute fix: set location to (offset) symbol value */
-	mov	r1, r1, LSR #4		/* r1 <- symbol index in .dynsym */
-	add	r1, r10, r1		/* r1 <- address of symbol in table */
-	ldr	r1, [r1, #4]		/* r1 <- symbol value */
-	add	r1, r1, r9		/* r1 <- relocated sym addr */
-	b	fixnext
-fixrel:
-	/* relative fix: increase location by offset */
-	ldr	r1, [r0]
-	add	r1, r1, r9
-fixnext:
-	str	r1, [r0]
-	add	r2, r2, #8		/* each rel.dyn entry is 8 bytes */
-	cmp	r2, r3
-	blo	fixloop
-#endif
-
-clear_bss:
-#ifndef CONFIG_PRELOADER
-	ldr	r0, _bss_start_ofs
-	ldr	r1, _bss_end_ofs
-	mov	r4, r6			/* reloc addr */
-	add	r0, r0, r4
-	add	r1, r1, r4
-	mov	r2, #0x00000000		/* clear			    */
-
-clbss_l:str	r2, [r0]		/* clear loop...		    */
-	add	r0, r0, #4
-	cmp	r0, r1
-	bne	clbss_l
-
-	bl coloured_LED_init
-	bl red_LED_on
-#endif
-
-/*
- * We are done. Do not return, instead branch to second part of board
- * initialization, now running from RAM.
- */
-	ldr	r0, _board_init_r_ofs
-	adr	r1, _start
-	add	lr, r0, r1
-	add	lr, lr, r9
-	/* setup parameters for board_init_r */
-	mov	r0, r5		/* gd_t */
-	mov	r1, r6		/* dest_addr */
-	/* jump to it ... */
-	mov	pc, lr
-
-_board_init_r_ofs:
-	.word board_init_r - _start
-
-_rel_dyn_start_ofs:
-	.word __rel_dyn_start - _start
-_rel_dyn_end_ofs:
-	.word __rel_dyn_end - _start
-_dynsym_start_ofs:
-	.word __dynsym_start - _start
-
-/*
- *************************************************************************
- *
- * CPU_init_critical registers
- *
- * setup important registers
- * setup memory timing
- *
- *************************************************************************
- */
-
-#define INTCON (0x01c00000+0x200000)
-#define INTMSK (0x01c00000+0x20000c)
-#define LOCKTIME (0x01c00000+0x18000c)
-#define PLLCON (0x01c00000+0x180000)
-#define CLKCON (0x01c00000+0x180004)
-#define WTCON (0x01c00000+0x130000)
-cpu_init_crit:
-	/* disable watch dog */
-	ldr	r0, =WTCON
-	ldr	r1, =0x0
-	str	r1, [r0]
-
-	/*
-	 * mask all IRQs by clearing all bits in the INTMRs
-	 */
-	ldr	r1,=INTMSK
-	ldr	r0, =0x03fffeff
-	str	r0, [r1]
-
-	ldr	r1, =INTCON
-	ldr	r0, =0x05
-	str	r0, [r1]
-
-	/* Set Clock Control Register */
-	ldr	r1, =LOCKTIME
-	ldrb	r0, =800
-	strb	r0, [r1]
-
-	ldr	r1, =PLLCON
-
-#if CONFIG_S3C44B0_CLOCK_SPEED==66
-	ldr	r0, =0x34031	/* 66MHz (Quartz=11MHz) */
-#elif CONFIG_S3C44B0_CLOCK_SPEED==75
-	ldr	r0, =0x610c1 /*B2: Xtal=20mhz Fclk=75MHz  */
-#else
-# error CONFIG_S3C44B0_CLOCK_SPEED undefined
-#endif
-
-	str	r0, [r1]
-
-	ldr	r1,=CLKCON
-	ldr	r0, =0x7ff8
-	str	r0, [r1]
-
-	mov	pc, lr
-
-
-/*************************************************/
-/*	interrupt vectors	*/
-/*************************************************/
-real_vectors:
-	b	reset
-	b	undefined_instruction
-	b	software_interrupt
-	b	prefetch_abort
-	b	data_abort
-	b	not_used
-	b	irq
-	b	fiq
-
-/*************************************************/
-
-undefined_instruction:
-	mov	r6, #3
-	b	reset
-
-software_interrupt:
-	mov	r6, #4
-	b	reset
-
-prefetch_abort:
-	mov	r6, #5
-	b	reset
-
-data_abort:
-	mov	r6, #6
-	b	reset
-
-not_used:
-	/* we *should* never reach this */
-	mov	r6, #7
-	b	reset
-
-irq:
-	mov	r6, #8
-	b	reset
-
-fiq:
-	mov	r6, #9
-	b	reset
diff --git a/arch/arm/cpu/s3c44b0/timer.c b/arch/arm/cpu/s3c44b0/timer.c
deleted file mode 100644
index 6f1d8f6..0000000
--- a/arch/arm/cpu/s3c44b0/timer.c
+++ /dev/null
@@ -1,136 +0,0 @@
-/*
- * (C) Copyright 2004
- * DAVE Srl
- * http://www.dave-tech.it
- * http://www.wawnet.biz
- * mailto:info@wawnet.biz
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/hardware.h>
-
-/* we always count down the max. */
-#define TIMER_LOAD_VAL 0xffff
-
-/* macro to read the 16 bit timer */
-#define READ_TIMER (TCNTO1 & 0xffff)
-
-#ifdef CONFIG_USE_IRQ
-#error CONFIG_USE_IRQ NOT supported
-#endif
-
-static ulong timestamp;
-static ulong lastdec;
-
-int timer_init (void)
-{
-	TCFG0 = 0x000000E9;
-	TCFG1 = 0x00000004;
-	TCON = 0x00000900;
-	TCNTB1 = TIMER_LOAD_VAL;
-	TCMPB1 = 0;
-	TCON = 0x00000B00;
-	TCON = 0x00000900;
-
-
-	lastdec = TCNTB1 = TIMER_LOAD_VAL;
-	timestamp = 0;
-	return 0;
-}
-
-/*
- * timer without interrupts
- */
-
-void reset_timer (void)
-{
-	reset_timer_masked ();
-}
-
-ulong get_timer (ulong base)
-{
-	return get_timer_masked () - base;
-}
-
-void set_timer (ulong t)
-{
-	timestamp = t;
-}
-
-void __udelay (unsigned long usec)
-{
-	ulong tmo;
-
-	tmo = usec / 1000;
-	tmo *= CONFIG_SYS_HZ;
-	tmo /= 8;
-
-	tmo += get_timer (0);
-
-	while (get_timer_masked () < tmo)
-		/*NOP*/;
-}
-
-void reset_timer_masked (void)
-{
-	/* reset time */
-	lastdec = READ_TIMER;
-	timestamp = 0;
-}
-
-ulong get_timer_masked (void)
-{
-	ulong now = READ_TIMER;
-
-	if (lastdec >= now) {
-		/* normal mode */
-		timestamp += lastdec - now;
-	} else {
-		/* we have an overflow ... */
-		timestamp += lastdec + TIMER_LOAD_VAL - now;
-	}
-	lastdec = now;
-
-	return timestamp;
-}
-
-void udelay_masked (unsigned long usec)
-{
-	ulong tmo;
-	ulong endtime;
-	signed long diff;
-
-	if (usec >= 1000) {
-		tmo = usec / 1000;
-		tmo *= CONFIG_SYS_HZ;
-		tmo /= 8;
-	} else {
-		tmo = usec * CONFIG_SYS_HZ;
-		tmo /= (1000*8);
-	}
-
-	endtime = get_timer(0) + tmo;
-
-	do {
-		ulong now = get_timer_masked ();
-		diff = endtime - now;
-	} while (diff >= 0);
-}
diff --git a/arch/arm/cpu/s3c44b0/u-boot.lds b/arch/arm/cpu/s3c44b0/u-boot.lds
deleted file mode 100644
index ac29440..0000000
--- a/arch/arm/cpu/s3c44b0/u-boot.lds
+++ /dev/null
@@ -1,78 +0,0 @@
-/*
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-ENTRY(_start)
-SECTIONS
-{
-	. = 0x00000000;
-
-	. = ALIGN(4);
-	.text :
-	{
-		arch/arm/cpu/s3c44b0/start.o	(.text)
-		*(.text)
-	}
-
-	. = ALIGN(4);
-	.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
-
-	. = ALIGN(4);
-	.data : {
-		*(.data)
-	}
-
-	. = ALIGN(4);
-
-	. = .;
-	__u_boot_cmd_start = .;
-	.u_boot_cmd : { *(.u_boot_cmd) }
-	__u_boot_cmd_end = .;
-
-	. = ALIGN(4);
-
-	.rel.dyn : {
-		__rel_dyn_start = .;
-		*(.rel*)
-		__rel_dyn_end = .;
-	}
-
-	.dynsym : {
-		__dynsym_start = .;
-		*(.dynsym)
-	}
-
-	.bss __rel_dyn_start (OVERLAY) : {
-		__bss_start = .;
-		*(.bss)
-		 . = ALIGN(4);
-		_end = .;
-	}
-
-	/DISCARD/ : { *(.dynstr*) }
-	/DISCARD/ : { *(.dynamic*) }
-	/DISCARD/ : { *(.plt*) }
-	/DISCARD/ : { *(.interp*) }
-	/DISCARD/ : { *(.gnu*) }
-}
diff --git a/arch/arm/cpu/sa1100/Makefile b/arch/arm/cpu/sa1100/Makefile
deleted file mode 100644
index 1021c99..0000000
--- a/arch/arm/cpu/sa1100/Makefile
+++ /dev/null
@@ -1,49 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(CPU).o
-
-START	= start.o
-
-COBJS	+= cpu.o
-COBJS	+= timer.o
-
-SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
-START	:= $(addprefix $(obj),$(START))
-
-all:	$(obj).depend $(START) $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/arch/arm/cpu/sa1100/config.mk b/arch/arm/cpu/sa1100/config.mk
deleted file mode 100644
index 6f21f41..0000000
--- a/arch/arm/cpu/sa1100/config.mk
+++ /dev/null
@@ -1,33 +0,0 @@
-#
-# (C) Copyright 2002
-# Sysgo Real-Time Solutions, GmbH <www.elinos.com>
-# Marius Groeger <mgroeger@sysgo.de>
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float
-
-PLATFORM_CPPFLAGS += -march=armv4 -mtune=strongarm1100
-# =========================================================================
-#
-# Supply options according to compiler version
-#
-# ========================================================================
-PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))
diff --git a/arch/arm/cpu/sa1100/cpu.c b/arch/arm/cpu/sa1100/cpu.c
deleted file mode 100644
index 58e90dc..0000000
--- a/arch/arm/cpu/sa1100/cpu.c
+++ /dev/null
@@ -1,70 +0,0 @@
-/*
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Alex Zuepke <azu@sysgo.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * CPU specific code
- */
-
-#include <common.h>
-#include <command.h>
-#include <asm/system.h>
-
-#ifdef CONFIG_USE_IRQ
-DECLARE_GLOBAL_DATA_PTR;
-#endif
-
-static void cache_flush(void);
-
-int cleanup_before_linux (void)
-{
-	/*
-	 * this function is called just before we call linux
-	 * it prepares the processor for linux
-	 *
-	 * just disable everything that can disturb booting linux
-	 */
-
-	disable_interrupts ();
-
-	/* turn off I-cache */
-	icache_disable();
-	dcache_disable();
-
-	/* flush I-cache */
-	cache_flush();
-
-	return (0);
-}
-
-/* flush I/D-cache */
-static void cache_flush (void)
-{
-	unsigned long i = 0;
-
-	asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i));
-}
diff --git a/arch/arm/cpu/sa1100/start.S b/arch/arm/cpu/sa1100/start.S
deleted file mode 100644
index 815d704..0000000
--- a/arch/arm/cpu/sa1100/start.S
+++ /dev/null
@@ -1,493 +0,0 @@
-/*
- *  armboot - Startup Code for SA1100 CPU
- *
- *  Copyright (C) 1998	Dan Malek <dmalek@jlc.net>
- *  Copyright (C) 1999	Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
- *  Copyright (C) 2000	Wolfgang Denk <wd@denx.de>
- *  Copyright (c) 2001	Alex Züpke <azu@sysgo.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <asm-offsets.h>
-#include <config.h>
-#include <version.h>
-
-/*
- *************************************************************************
- *
- * Jump vector table as in table 3.1 in [1]
- *
- *************************************************************************
- */
-
-
-.globl _start
-_start:	b       reset
-	ldr	pc, _undefined_instruction
-	ldr	pc, _software_interrupt
-	ldr	pc, _prefetch_abort
-	ldr	pc, _data_abort
-	ldr	pc, _not_used
-	ldr	pc, _irq
-	ldr	pc, _fiq
-
-_undefined_instruction:	.word undefined_instruction
-_software_interrupt:	.word software_interrupt
-_prefetch_abort:	.word prefetch_abort
-_data_abort:		.word data_abort
-_not_used:		.word not_used
-_irq:			.word irq
-_fiq:			.word fiq
-
-	.balignl 16,0xdeadbeef
-
-
-/*
- *************************************************************************
- *
- * Startup Code (reset vector)
- *
- * do important init only if we don't start from memory!
- * relocate armboot to ram
- * setup stack
- * jump to second stage
- *
- *************************************************************************
- */
-
-.globl _TEXT_BASE
-_TEXT_BASE:
-	.word	CONFIG_SYS_TEXT_BASE
-
-/*
- * These are defined in the board-specific linker script.
- * Subtracting _start from them lets the linker put their
- * relative position in the executable instead of leaving
- * them null.
- */
-.globl _bss_start_ofs
-_bss_start_ofs:
-	.word __bss_start - _start
-
-.globl _bss_end_ofs
-_bss_end_ofs:
-	.word _end - _start
-
-#ifdef CONFIG_USE_IRQ
-/* IRQ stack memory (calculated at run-time) */
-.globl IRQ_STACK_START
-IRQ_STACK_START:
-	.word	0x0badc0de
-
-/* IRQ stack memory (calculated at run-time) */
-.globl FIQ_STACK_START
-FIQ_STACK_START:
-	.word 0x0badc0de
-#endif
-
-/* IRQ stack memory (calculated at run-time) + 8 bytes */
-.globl IRQ_STACK_START_IN
-IRQ_STACK_START_IN:
-	.word	0x0badc0de
-
-/*
- * the actual reset code
- */
-
-reset:
-	/*
-	 * set the cpu to SVC32 mode
-	 */
-	mrs	r0,cpsr
-	bic	r0,r0,#0x1f
-	orr	r0,r0,#0xd3
-	msr	cpsr,r0
-
-	/*
-	 * we do sys-critical inits only at reboot,
-	 * not when booting from ram!
-	 */
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
-	bl	cpu_init_crit
-#endif
-
-/* Set stackpointer in internal RAM to call board_init_f */
-call_board_init_f:
-	ldr	sp, =(CONFIG_SYS_INIT_SP_ADDR)
-	bic	sp, sp, #7 /* 8-byte alignment for ABI compliance */
-	ldr	r0,=0x00000000
-	bl	board_init_f
-
-/*------------------------------------------------------------------------------*/
-
-/*
- * void relocate_code (addr_sp, gd, addr_moni)
- *
- * This "function" does not return, instead it continues in RAM
- * after relocating the monitor code.
- *
- */
-	.globl	relocate_code
-relocate_code:
-	mov	r4, r0	/* save addr_sp */
-	mov	r5, r1	/* save addr of gd */
-	mov	r6, r2	/* save addr of destination */
-
-	/* Set up the stack						    */
-stack_setup:
-	mov	sp, r4
-
-	adr	r0, _start
-	cmp	r0, r6
-	beq	clear_bss		/* skip relocation */
-	mov	r1, r6			/* r1 <- scratch for copy_loop */
-	ldr	r3, _bss_start_ofs
-	add	r2, r0, r3		/* r2 <- source end address	    */
-
-copy_loop:
-	ldmia	r0!, {r9-r10}		/* copy from source address [r0]    */
-	stmia	r1!, {r9-r10}		/* copy to   target address [r1]    */
-	cmp	r0, r2			/* until source end address [r2]    */
-	blo	copy_loop
-
-#ifndef CONFIG_PRELOADER
-	/*
-	 * fix .rel.dyn relocations
-	 */
-	ldr	r0, _TEXT_BASE		/* r0 <- Text base */
-	sub	r9, r6, r0		/* r9 <- relocation offset */
-	ldr	r10, _dynsym_start_ofs	/* r10 <- sym table ofs */
-	add	r10, r10, r0		/* r10 <- sym table in FLASH */
-	ldr	r2, _rel_dyn_start_ofs	/* r2 <- rel dyn start ofs */
-	add	r2, r2, r0		/* r2 <- rel dyn start in FLASH */
-	ldr	r3, _rel_dyn_end_ofs	/* r3 <- rel dyn end ofs */
-	add	r3, r3, r0		/* r3 <- rel dyn end in FLASH */
-fixloop:
-	ldr	r0, [r2]		/* r0 <- location to fix up, IN FLASH! */
-	add	r0, r0, r9		/* r0 <- location to fix up in RAM */
-	ldr	r1, [r2, #4]
-	and	r7, r1, #0xff
-	cmp	r7, #23			/* relative fixup? */
-	beq	fixrel
-	cmp	r7, #2			/* absolute fixup? */
-	beq	fixabs
-	/* ignore unknown type of fixup */
-	b	fixnext
-fixabs:
-	/* absolute fix: set location to (offset) symbol value */
-	mov	r1, r1, LSR #4		/* r1 <- symbol index in .dynsym */
-	add	r1, r10, r1		/* r1 <- address of symbol in table */
-	ldr	r1, [r1, #4]		/* r1 <- symbol value */
-	add	r1, r1, r9		/* r1 <- relocated sym addr */
-	b	fixnext
-fixrel:
-	/* relative fix: increase location by offset */
-	ldr	r1, [r0]
-	add	r1, r1, r9
-fixnext:
-	str	r1, [r0]
-	add	r2, r2, #8		/* each rel.dyn entry is 8 bytes */
-	cmp	r2, r3
-	blo	fixloop
-#endif
-
-clear_bss:
-#ifndef CONFIG_PRELOADER
-	ldr	r0, _bss_start_ofs
-	ldr	r1, _bss_end_ofs
-	mov	r4, r6			/* reloc addr */
-	add	r0, r0, r4
-	add	r1, r1, r4
-	mov	r2, #0x00000000		/* clear			    */
-
-clbss_l:str	r2, [r0]		/* clear loop...		    */
-	add	r0, r0, #4
-	cmp	r0, r1
-	bne	clbss_l
-#endif
-
-/*
- * We are done. Do not return, instead branch to second part of board
- * initialization, now running from RAM.
- */
-	ldr	r0, _board_init_r_ofs
-	adr	r1, _start
-	add	lr, r0, r1
-	add	lr, lr, r9
-	/* setup parameters for board_init_r */
-	mov	r0, r5		/* gd_t */
-	mov	r1, r6		/* dest_addr */
-	/* jump to it ... */
-	mov	pc, lr
-
-_board_init_r_ofs:
-	.word board_init_r - _start
-
-_rel_dyn_start_ofs:
-	.word __rel_dyn_start - _start
-_rel_dyn_end_ofs:
-	.word __rel_dyn_end - _start
-_dynsym_start_ofs:
-	.word __dynsym_start - _start
-
-/*
- *************************************************************************
- *
- * CPU_init_critical registers
- *
- * setup important registers
- * setup memory timing
- *
- *************************************************************************
- */
-
-
-/* Interupt-Controller base address */
-IC_BASE:	.word	0x90050000
-#define ICMR	0x04
-
-
-/* Reset-Controller */
-RST_BASE:		.word   0x90030000
-#define RSRR	0x00
-#define RCSR	0x04
-
-
-/* PWR */
-PWR_BASE:		.word   0x90020000
-#define PSPR    0x08
-#define PPCR    0x14
-cpuspeed:		.word   CONFIG_SYS_CPUSPEED
-
-
-cpu_init_crit:
-	/*
-	 * mask all IRQs
-	 */
-	ldr	r0, IC_BASE
-	mov	r1, #0x00
-	str	r1, [r0, #ICMR]
-
-	/* set clock speed */
-	ldr	r0, PWR_BASE
-	ldr	r1, cpuspeed
-	str	r1, [r0, #PPCR]
-
-	/*
-	 * before relocating, we have to setup RAM timing
-	 * because memory timing is board-dependend, you will
-	 * find a lowlevel_init.S in your board directory.
-	 */
-	mov	ip,	lr
-	bl	lowlevel_init
-	mov	lr,	ip
-
-	/*
-	 * disable MMU stuff and enable I-cache
-	 */
-	mrc	p15,0,r0,c1,c0
-	bic	r0, r0, #0x00002000	@ clear bit 13 (X)
-	bic	r0, r0, #0x0000000f	@ clear bits 3-0 (WCAM)
-	orr	r0, r0, #0x00001000	@ set bit 12 (I) Icache
-	orr	r0, r0, #0x00000002	@ set bit 2 (A) Align
-	mcr	p15,0,r0,c1,c0
-
-	/*
-	 * flush v4 I/D caches
-	 */
-	mov	r0, #0
-	mcr	p15, 0, r0, c7, c7, 0	/* flush v3/v4 cache */
-	mcr	p15, 0, r0, c8, c7, 0	/* flush v4 TLB */
-
-	mov	pc, lr
-
-
-/*
- *************************************************************************
- *
- * Interrupt handling
- *
- *************************************************************************
- */
-
-@
-@ IRQ stack frame.
-@
-#define S_FRAME_SIZE	72
-
-#define S_OLD_R0	68
-#define S_PSR		64
-#define S_PC		60
-#define S_LR		56
-#define S_SP		52
-
-#define S_IP		48
-#define S_FP		44
-#define S_R10		40
-#define S_R9		36
-#define S_R8		32
-#define S_R7		28
-#define S_R6		24
-#define S_R5		20
-#define S_R4		16
-#define S_R3		12
-#define S_R2		8
-#define S_R1		4
-#define S_R0		0
-
-#define MODE_SVC 0x13
-#define I_BIT	 0x80
-
-/*
- * use bad_save_user_regs for abort/prefetch/undef/swi ...
- * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
- */
-
-	.macro	bad_save_user_regs
-	sub	sp, sp, #S_FRAME_SIZE
-	stmia	sp, {r0 - r12}			@ Calling r0-r12
-	add     r8, sp, #S_PC
-
-	ldr	r2, IRQ_STACK_START_IN
-	ldmia	r2, {r2 - r4}                   @ get pc, cpsr, old_r0
-	add	r0, sp, #S_FRAME_SIZE		@ restore sp_SVC
-
-	add	r5, sp, #S_SP
-	mov	r1, lr
-	stmia	r5, {r0 - r4}                   @ save sp_SVC, lr_SVC, pc, cpsr, old_r
-	mov	r0, sp
-	.endm
-
-	.macro	irq_save_user_regs
-	sub	sp, sp, #S_FRAME_SIZE
-	stmia	sp, {r0 - r12}			@ Calling r0-r12
-	add     r8, sp, #S_PC
-	stmdb   r8, {sp, lr}^                   @ Calling SP, LR
-	str     lr, [r8, #0]                    @ Save calling PC
-	mrs     r6, spsr
-	str     r6, [r8, #4]                    @ Save CPSR
-	str     r0, [r8, #8]                    @ Save OLD_R0
-	mov	r0, sp
-	.endm
-
-	.macro	irq_restore_user_regs
-	ldmia	sp, {r0 - lr}^			@ Calling r0 - lr
-	mov	r0, r0
-	ldr	lr, [sp, #S_PC]			@ Get PC
-	add	sp, sp, #S_FRAME_SIZE
-	subs	pc, lr, #4			@ return & move spsr_svc into cpsr
-	.endm
-
-	.macro get_bad_stack
-	ldr	r13, IRQ_STACK_START_IN		@ setup our mode stack
-
-	str	lr, [r13]			@ save caller lr / spsr
-	mrs	lr, spsr
-	str     lr, [r13, #4]
-
-	mov	r13, #MODE_SVC			@ prepare SVC-Mode
-	msr	spsr_c, r13
-	mov	lr, pc
-	movs	pc, lr
-	.endm
-
-	.macro get_irq_stack			@ setup IRQ stack
-	ldr	sp, IRQ_STACK_START
-	.endm
-
-	.macro get_fiq_stack			@ setup FIQ stack
-	ldr	sp, FIQ_STACK_START
-	.endm
-
-/*
- * exception handlers
- */
-	.align  5
-undefined_instruction:
-	get_bad_stack
-	bad_save_user_regs
-	bl	do_undefined_instruction
-
-	.align	5
-software_interrupt:
-	get_bad_stack
-	bad_save_user_regs
-	bl	do_software_interrupt
-
-	.align	5
-prefetch_abort:
-	get_bad_stack
-	bad_save_user_regs
-	bl	do_prefetch_abort
-
-	.align	5
-data_abort:
-	get_bad_stack
-	bad_save_user_regs
-	bl	do_data_abort
-
-	.align	5
-not_used:
-	get_bad_stack
-	bad_save_user_regs
-	bl	do_not_used
-
-#ifdef CONFIG_USE_IRQ
-
-	.align	5
-irq:
-	get_irq_stack
-	irq_save_user_regs
-	bl	do_irq
-	irq_restore_user_regs
-
-	.align	5
-fiq:
-	get_fiq_stack
-	/* someone ought to write a more effiction fiq_save_user_regs */
-	irq_save_user_regs
-	bl	do_fiq
-	irq_restore_user_regs
-
-#else
-
-	.align	5
-irq:
-	get_bad_stack
-	bad_save_user_regs
-	bl	do_irq
-
-	.align	5
-fiq:
-	get_bad_stack
-	bad_save_user_regs
-	bl	do_fiq
-
-#endif
-
-	.align	5
-.globl reset_cpu
-reset_cpu:
-	ldr	r0, RST_BASE
-	mov	r1, #0x0			@ set bit 3-0 ...
-	str	r1, [r0, #RCSR]			@ ... to clear in RCSR
-	mov	r1, #0x1
-	str	r1, [r0, #RSRR]			@ and perform reset
-	b	reset_cpu			@ silly, but repeat endlessly
diff --git a/arch/arm/cpu/sa1100/timer.c b/arch/arm/cpu/sa1100/timer.c
deleted file mode 100644
index 0207501..0000000
--- a/arch/arm/cpu/sa1100/timer.c
+++ /dev/null
@@ -1,110 +0,0 @@
-/*
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Alex Zuepke <azu@sysgo.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <SA-1100.h>
-
-int timer_init (void)
-{
-	return 0;
-}
-
-void reset_timer (void)
-{
-	reset_timer_masked ();
-}
-
-ulong get_timer (ulong base)
-{
-	return get_timer_masked ();
-}
-
-void set_timer (ulong t)
-{
-	/* nop */
-}
-
-void __udelay (unsigned long usec)
-{
-	udelay_masked (usec);
-}
-
-
-void reset_timer_masked (void)
-{
-	OSCR = 0;
-}
-
-ulong get_timer_masked (void)
-{
-	return OSCR;
-}
-
-void udelay_masked (unsigned long usec)
-{
-	ulong tmo;
-	ulong endtime;
-	signed long diff;
-
-	if (usec >= 1000) {
-		tmo = usec / 1000;
-		tmo *= CONFIG_SYS_HZ;
-		tmo /= 1000;
-	} else {
-		tmo = usec * CONFIG_SYS_HZ;
-		tmo /= (1000*1000);
-	}
-
-	endtime = get_timer_masked () + tmo;
-
-	do {
-		ulong now = get_timer_masked ();
-		diff = endtime - now;
-	} while (diff >= 0);
-}
-
-/*
- * This function is derived from PowerPC code (read timebase as long long).
- * On ARM it just returns the timer value.
- */
-unsigned long long get_ticks(void)
-{
-	return get_timer(0);
-}
-
-/*
- * This function is derived from PowerPC code (timebase clock frequency).
- * On ARM it returns the number of timer ticks per second.
- */
-ulong get_tbclk (void)
-{
-	ulong tbclk;
-
-	tbclk = CONFIG_SYS_HZ;
-	return tbclk;
-}
diff --git a/arch/arm/cpu/sa1100/u-boot.lds b/arch/arm/cpu/sa1100/u-boot.lds
deleted file mode 100644
index fa6d05c..0000000
--- a/arch/arm/cpu/sa1100/u-boot.lds
+++ /dev/null
@@ -1,81 +0,0 @@
-/*
- * (C) Copyright 2003-2004
- * MontaVista Software, Inc.
- *
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-ENTRY(_start)
-SECTIONS
-{
-	. = 0x00000000;
-
-	. = ALIGN(4);
-	.text :
-	{
-		arch/arm/cpu/sa1100/start.o	(.text)
-		*(.text)
-	}
-
-	. = ALIGN(4);
-	.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
-
-	. = ALIGN(4);
-	.data : {
-		*(.data)
-	}
-
-	. = ALIGN(4);
-
-	. = .;
-	__u_boot_cmd_start = .;
-	.u_boot_cmd : { *(.u_boot_cmd) }
-	__u_boot_cmd_end = .;
-
-	. = ALIGN(4);
-
-	.rel.dyn : {
-		__rel_dyn_start = .;
-		*(.rel*)
-		__rel_dyn_end = .;
-	}
-
-	.dynsym : {
-		__dynsym_start = .;
-		*(.dynsym)
-	}
-
-	.bss __rel_dyn_start (OVERLAY) : {
-		__bss_start = .;
-		*(.bss)
-		 . = ALIGN(4);
-		_end = .;
-	}
-
-	/DISCARD/ : { *(.dynstr*) }
-	/DISCARD/ : { *(.dynamic*) }
-	/DISCARD/ : { *(.plt*) }
-	/DISCARD/ : { *(.interp*) }
-	/DISCARD/ : { *(.gnu*) }
-}
diff --git a/arch/arm/include/asm/arch-a320/a320.h b/arch/arm/include/asm/arch-a320/a320.h
deleted file mode 100644
index fbd1583..0000000
--- a/arch/arm/include/asm/arch-a320/a320.h
+++ /dev/null
@@ -1,34 +0,0 @@
-/*
- * (C) Copyright 2009 Faraday Technology
- * Po-Yu Chuang <ratbert@faraday-tech.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#ifndef __A320_H
-#define __A320_H
-
-/*
- * Hardware register bases
- */
-#define CONFIG_FTSMC020_BASE	0x90200000	/* Static Memory Controller */
-#define CONFIG_DEBUG_LED	0x902ffffc	/* Debug LED */
-#define CONFIG_FTSDMC020_BASE	0x90300000	/* SDRAM Controller */
-#define CONFIG_FTMAC100_BASE	0x90900000	/* Ethernet */
-#define CONFIG_FTPMU010_BASE	0x98100000	/* Power Management Unit */
-#define CONFIG_FTTMR010_BASE	0x98400000	/* Timer */
-#define CONFIG_FTRTC010_BASE	0x98600000	/* Real Time Clock*/
-
-#endif	/* __A320_H */
diff --git a/arch/arm/include/asm/arch-a320/ftsdmc020.h b/arch/arm/include/asm/arch-a320/ftsdmc020.h
deleted file mode 100644
index 0699772..0000000
--- a/arch/arm/include/asm/arch-a320/ftsdmc020.h
+++ /dev/null
@@ -1,103 +0,0 @@
-/*
- * (C) Copyright 2009 Faraday Technology
- * Po-Yu Chuang <ratbert@faraday-tech.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-/*
- * SDRAM Controller
- */
-#ifndef __FTSDMC020_H
-#define __FTSDMC020_H
-
-#define FTSDMC020_OFFSET_TP0		0x00
-#define FTSDMC020_OFFSET_TP1		0x04
-#define FTSDMC020_OFFSET_CR		0x08
-#define FTSDMC020_OFFSET_BANK0_BSR	0x0C
-#define FTSDMC020_OFFSET_BANK1_BSR	0x10
-#define FTSDMC020_OFFSET_BANK2_BSR	0x14
-#define FTSDMC020_OFFSET_BANK3_BSR	0x18
-#define FTSDMC020_OFFSET_BANK4_BSR	0x1C
-#define FTSDMC020_OFFSET_BANK5_BSR	0x20
-#define FTSDMC020_OFFSET_BANK6_BSR	0x24
-#define FTSDMC020_OFFSET_BANK7_BSR	0x28
-#define FTSDMC020_OFFSET_ACR		0x34
-
-/*
- * Timing Parametet 0 Register
- */
-#define FTSDMC020_TP0_TCL(x)	((x) & 0x3)
-#define FTSDMC020_TP0_TWR(x)	(((x) & 0x3) << 4)
-#define FTSDMC020_TP0_TRF(x)	(((x) & 0xf) << 8)
-#define FTSDMC020_TP0_TRCD(x)	(((x) & 0x7) << 12)
-#define FTSDMC020_TP0_TRP(x)	(((x) & 0xf) << 16)
-#define FTSDMC020_TP0_TRAS(x)	(((x) & 0xf) << 20)
-
-/*
- * Timing Parametet 1 Register
- */
-#define FTSDMC020_TP1_REF_INTV(x)	((x) & 0xffff)
-#define FTSDMC020_TP1_INI_REFT(x)	(((x) & 0xf) << 16)
-#define FTSDMC020_TP1_INI_PREC(x)	(((x) & 0xf) << 20)
-
-/*
- * Configuration Register
- */
-#define FTSDMC020_CR_SREF	(1 << 0)
-#define FTSDMC020_CR_PWDN	(1 << 1)
-#define FTSDMC020_CR_ISMR	(1 << 2)
-#define FTSDMC020_CR_IREF	(1 << 3)
-#define FTSDMC020_CR_IPREC	(1 << 4)
-#define FTSDMC020_CR_REFTYPE	(1 << 5)
-
-/*
- * SDRAM External Bank Base/Size Register
- */
-#define FTSDMC020_BANK_ENABLE		(1 << 28)
-
-#define FTSDMC020_BANK_BASE(addr)	(((addr) >> 20) << 16)
-
-#define FTSDMC020_BANK_DDW_X4		(0 << 12)
-#define FTSDMC020_BANK_DDW_X8		(1 << 12)
-#define FTSDMC020_BANK_DDW_X16		(2 << 12)
-#define FTSDMC020_BANK_DDW_X32		(3 << 12)
-
-#define FTSDMC020_BANK_DSZ_16M		(0 << 8)
-#define FTSDMC020_BANK_DSZ_64M		(1 << 8)
-#define FTSDMC020_BANK_DSZ_128M		(2 << 8)
-#define FTSDMC020_BANK_DSZ_256M		(3 << 8)
-
-#define FTSDMC020_BANK_MBW_8		(0 << 4)
-#define FTSDMC020_BANK_MBW_16		(1 << 4)
-#define FTSDMC020_BANK_MBW_32		(2 << 4)
-
-#define FTSDMC020_BANK_SIZE_1M		0x0
-#define FTSDMC020_BANK_SIZE_2M		0x1
-#define FTSDMC020_BANK_SIZE_4M		0x2
-#define FTSDMC020_BANK_SIZE_8M		0x3
-#define FTSDMC020_BANK_SIZE_16M		0x4
-#define FTSDMC020_BANK_SIZE_32M		0x5
-#define FTSDMC020_BANK_SIZE_64M		0x6
-#define FTSDMC020_BANK_SIZE_128M	0x7
-#define FTSDMC020_BANK_SIZE_256M	0x8
-
-/*
- * Arbiter Control Register
- */
-#define FTSDMC020_ACR_TOC(x)	((x) & 0x1f)
-#define FTSDMC020_ACR_TOE	(1 << 8)
-
-#endif	/* __FTSDMC020_H */
diff --git a/arch/arm/include/asm/arch-a320/ftsmc020.h b/arch/arm/include/asm/arch-a320/ftsmc020.h
deleted file mode 100644
index 95d9500..0000000
--- a/arch/arm/include/asm/arch-a320/ftsmc020.h
+++ /dev/null
@@ -1,79 +0,0 @@
-/*
- * (C) Copyright 2009 Faraday Technology
- * Po-Yu Chuang <ratbert@faraday-tech.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-/*
- * Static Memory Controller
- */
-#ifndef __FTSMC020_H
-#define __FTSMC020_H
-
-#ifndef __ASSEMBLY__
-
-struct ftsmc020 {
-	struct {
-		unsigned int	cr;	/* 0x00, 0x08, 0x10, 0x18 */
-		unsigned int	tpr;	/* 0x04, 0x0c, 0x14, 0x1c */
-	} bank[4];
-	unsigned int	pad[8];	/* 0x20 - 0x3c */
-	unsigned int	ssr;	/* 0x40 */
-};
-
-void ftsmc020_init(void);
-
-#endif /* __ASSEMBLY__ */
-
-/*
- * Memory Bank Configuration Register
- */
-#define FTSMC020_BANK_ENABLE	(1 << 28)
-#define FTSMC020_BANK_BASE(x)	((x) & 0x0fff1000)
-
-#define FTSMC020_BANK_WPROT	(1 << 11)
-
-#define FTSMC020_BANK_SIZE_32K	(0xb << 4)
-#define FTSMC020_BANK_SIZE_64K	(0xc << 4)
-#define FTSMC020_BANK_SIZE_128K	(0xd << 4)
-#define FTSMC020_BANK_SIZE_256K	(0xe << 4)
-#define FTSMC020_BANK_SIZE_512K	(0xf << 4)
-#define FTSMC020_BANK_SIZE_1M	(0x0 << 4)
-#define FTSMC020_BANK_SIZE_2M	(0x1 << 4)
-#define FTSMC020_BANK_SIZE_4M	(0x2 << 4)
-#define FTSMC020_BANK_SIZE_8M	(0x3 << 4)
-#define FTSMC020_BANK_SIZE_16M	(0x4 << 4)
-#define FTSMC020_BANK_SIZE_32M	(0x5 << 4)
-
-#define FTSMC020_BANK_MBW_8	(0x0 << 0)
-#define FTSMC020_BANK_MBW_16	(0x1 << 0)
-#define FTSMC020_BANK_MBW_32	(0x2 << 0)
-
-/*
- * Memory Bank Timing Parameter Register
- */
-#define FTSMC020_TPR_ETRNA(x)	(((x) & 0xf) << 28)
-#define FTSMC020_TPR_EATI(x)	(((x) & 0xf) << 24)
-#define FTSMC020_TPR_RBE	(1 << 20)
-#define FTSMC020_TPR_AST(x)	(((x) & 0x3) << 18)
-#define FTSMC020_TPR_CTW(x)	(((x) & 0x3) << 16)
-#define FTSMC020_TPR_ATI(x)	(((x) & 0xf) << 12)
-#define FTSMC020_TPR_AT2(x)	(((x) & 0x3) << 8)
-#define FTSMC020_TPR_WTC(x)	(((x) & 0x3) << 6)
-#define FTSMC020_TPR_AHT(x)	(((x) & 0x3) << 4)
-#define FTSMC020_TPR_TRNA(x)	(((x) & 0xf) << 0)
-
-#endif	/* __FTSMC020_H */
diff --git a/arch/arm/include/asm/arch-a320/fttmr010.h b/arch/arm/include/asm/arch-a320/fttmr010.h
deleted file mode 100644
index 72abcb3..0000000
--- a/arch/arm/include/asm/arch-a320/fttmr010.h
+++ /dev/null
@@ -1,73 +0,0 @@
-/*
- * (C) Copyright 2009 Faraday Technology
- * Po-Yu Chuang <ratbert@faraday-tech.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-/*
- * Timer
- */
-#ifndef __FTTMR010_H
-#define __FTTMR010_H
-
-struct fttmr010 {
-	unsigned int	timer1_counter;		/* 0x00 */
-	unsigned int	timer1_load;		/* 0x04 */
-	unsigned int	timer1_match1;		/* 0x08 */
-	unsigned int	timer1_match2;		/* 0x0c */
-	unsigned int	timer2_counter;		/* 0x10 */
-	unsigned int	timer2_load;		/* 0x14 */
-	unsigned int	timer2_match1;		/* 0x18 */
-	unsigned int	timer2_match2;		/* 0x1c */
-	unsigned int	timer3_counter;		/* 0x20 */
-	unsigned int	timer3_load;		/* 0x24 */
-	unsigned int	timer3_match1;		/* 0x28 */
-	unsigned int	timer3_match2;		/* 0x2c */
-	unsigned int	cr;			/* 0x30 */
-	unsigned int	interrupt_state;	/* 0x34 */
-	unsigned int	interrupt_mask;		/* 0x38 */
-};
-
-/*
- * Timer Control Register
- */
-#define FTTMR010_TM3_UPDOWN	(1 << 11)
-#define FTTMR010_TM2_UPDOWN	(1 << 10)
-#define FTTMR010_TM1_UPDOWN	(1 << 9)
-#define FTTMR010_TM3_OFENABLE	(1 << 8)
-#define FTTMR010_TM3_CLOCK	(1 << 7)
-#define FTTMR010_TM3_ENABLE	(1 << 6)
-#define FTTMR010_TM2_OFENABLE	(1 << 5)
-#define FTTMR010_TM2_CLOCK	(1 << 4)
-#define FTTMR010_TM2_ENABLE	(1 << 3)
-#define FTTMR010_TM1_OFENABLE	(1 << 2)
-#define FTTMR010_TM1_CLOCK	(1 << 1)
-#define FTTMR010_TM1_ENABLE	(1 << 0)
-
-/*
- * Timer Interrupt State & Mask Registers
- */
-#define FTTMR010_TM3_OVERFLOW	(1 << 8)
-#define FTTMR010_TM3_MATCH2	(1 << 7)
-#define FTTMR010_TM3_MATCH1	(1 << 6)
-#define FTTMR010_TM2_OVERFLOW	(1 << 5)
-#define FTTMR010_TM2_MATCH2	(1 << 4)
-#define FTTMR010_TM2_MATCH1	(1 << 3)
-#define FTTMR010_TM1_OVERFLOW	(1 << 2)
-#define FTTMR010_TM1_MATCH2	(1 << 1)
-#define FTTMR010_TM1_MATCH1	(1 << 0)
-
-#endif	/* __FTTMR010_H */
diff --git a/arch/arm/include/asm/arch-arm720t/hardware.h b/arch/arm/include/asm/arch-arm720t/hardware.h
deleted file mode 100644
index 9bee19f..0000000
--- a/arch/arm/include/asm/arch-arm720t/hardware.h
+++ /dev/null
@@ -1,41 +0,0 @@
-#ifndef __ARM7_HW_H
-#define __ARM7_HW_H
-
-/*
- * Copyright (c) 2004	Cucy Systems (http://www.cucy.com)
- * Curt Brune <curt@cucy.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#if defined(CONFIG_NETARM)
-#include <asm/arch-arm720t/netarm_registers.h>
-#elif defined(CONFIG_IMPA7)
-/* include IMPA7 specific hardware file if there was one */
-#elif defined(CONFIG_EP7312)
-/* include EP7312 specific hardware file if there was one */
-#elif defined(CONFIG_ARMADILLO)
-/* include armadillo specific hardware file if there was one */
-#elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
-/* include IntegratorCP/CM720T specific hardware file if there was one */
-#else
-#error No hardware file defined for this configuration
-#endif
-
-#endif /* __ARM7_HW_H */
diff --git a/arch/arm/include/asm/arch-arm720t/netarm_dma_module.h b/arch/arm/include/asm/arch-arm720t/netarm_dma_module.h
deleted file mode 100644
index 328eaf0..0000000
--- a/arch/arm/include/asm/arch-arm720t/netarm_dma_module.h
+++ /dev/null
@@ -1,182 +0,0 @@
-/* * include/asm-armnommu/arch-netarm/netarm_dma_module.h
- *
- * Copyright (C) 2000 NETsilicon, Inc.
- * Copyright (C) 2000 WireSpeed Communications Corporation
- *
- * This software is copyrighted by WireSpeed. LICENSEE agrees that
- * it will not delete this copyright notice, trademarks or protective
- * notices from any copy made by LICENSEE.
- *
- * This software is provided "AS-IS" and any express or implied
- * warranties or conditions, including but not limited to any
- * implied warranties of merchantability and fitness for a particular
- * purpose regarding this software. In no event shall WireSpeed
- * be liable for any indirect, consequential, or incidental damages,
- * loss of profits or revenue, loss of use or data, or interruption
- * of business, whether the alleged damages are labeled in contract,
- * tort, or indemnity.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- * author(s) : Joe deBlaquiere
- *             David Smith
- */
-
-#ifndef __NETARM_DMA_MODULE_REGISTERS_H
-#define __NETARM_DMA_MODULE_REGISTERS_H
-
-/* GEN unit register offsets */
-
-#define	NETARM_DMA_MODULE_BASE		(0xFF900000)
-
-#define get_dma_reg_addr(c) ((volatile unsigned int *)(NETARM_DMA_MODULE_BASE + (c)))
-
-#define	NETARM_DMA1A_BFR_DESCRPTOR_PTR	(0x00)
-#define	NETARM_DMA1A_CONTROL		(0x10)
-#define	NETARM_DMA1A_STATUS		(0x14)
-#define	NETARM_DMA1B_BFR_DESCRPTOR_PTR	(0x20)
-#define	NETARM_DMA1B_CONTROL		(0x30)
-#define	NETARM_DMA1B_STATUS		(0x34)
-#define	NETARM_DMA1C_BFR_DESCRPTOR_PTR	(0x40)
-#define	NETARM_DMA1C_CONTROL		(0x50)
-#define	NETARM_DMA1C_STATUS		(0x54)
-#define	NETARM_DMA1D_BFR_DESCRPTOR_PTR	(0x60)
-#define	NETARM_DMA1D_CONTROL		(0x70)
-#define	NETARM_DMA1D_STATUS		(0x74)
-
-#define	NETARM_DMA2_BFR_DESCRPTOR_PTR	(0x80)
-#define	NETARM_DMA2_CONTROL		(0x90)
-#define	NETARM_DMA2_STATUS		(0x94)
-
-#define	NETARM_DMA3_BFR_DESCRPTOR_PTR	(0xA0)
-#define	NETARM_DMA3_CONTROL		(0xB0)
-#define	NETARM_DMA3_STATUS		(0xB4)
-
-#define	NETARM_DMA4_BFR_DESCRPTOR_PTR	(0xC0)
-#define	NETARM_DMA4_CONTROL		(0xD0)
-#define	NETARM_DMA4_STATUS		(0xD4)
-
-#define	NETARM_DMA5_BFR_DESCRPTOR_PTR	(0xE0)
-#define	NETARM_DMA5_CONTROL		(0xF0)
-#define	NETARM_DMA5_STATUS		(0xF4)
-
-#define	NETARM_DMA6_BFR_DESCRPTOR_PTR	(0x100)
-#define	NETARM_DMA6_CONTROL		(0x110)
-#define	NETARM_DMA6_STATUS		(0x114)
-
-#define	NETARM_DMA7_BFR_DESCRPTOR_PTR	(0x120)
-#define	NETARM_DMA7_CONTROL		(0x130)
-#define	NETARM_DMA7_STATUS		(0x134)
-
-#define	NETARM_DMA8_BFR_DESCRPTOR_PTR	(0x140)
-#define	NETARM_DMA8_CONTROL		(0x150)
-#define	NETARM_DMA8_STATUS		(0x154)
-
-#define	NETARM_DMA9_BFR_DESCRPTOR_PTR	(0x160)
-#define	NETARM_DMA9_CONTROL		(0x170)
-#define	NETARM_DMA9_STATUS		(0x174)
-
-#define	NETARM_DMA10_BFR_DESCRPTOR_PTR	(0x180)
-#define	NETARM_DMA10_CONTROL		(0x190)
-#define	NETARM_DMA10_STATUS		(0x194)
-
-/* select bitfield defintions */
-
-/* DMA Control Register ( 0xFF90_0XX0 ) */
-
-#define NETARM_DMA_CTL_ENABLE		(0x80000000)
-
-#define NETARM_DMA_CTL_ABORT		(0x40000000)
-
-#define NETARM_DMA_CTL_BUS_100_PERCENT	(0x00000000)
-#define NETARM_DMA_CTL_BUS_75_PERCENT	(0x10000000)
-#define NETARM_DMA_CTL_BUS_50_PERCENT	(0x20000000)
-#define NETARM_DMA_CTL_BUS_25_PERCENT	(0x30000000)
-
-#define NETARM_DMA_CTL_BUS_MASK		(0x30000000)
-
-#define NETARM_DMA_CTL_MODE_FB_TO_MEM	(0x00000000)
-#define NETARM_DMA_CTL_MODE_FB_FROM_MEM	(0x04000000)
-#define NETARM_DMA_CTL_MODE_MEM_TO_MEM	(0x08000000)
-
-#define NETARM_DMA_CTL_BURST_NONE	(0x00000000)
-#define NETARM_DMA_CTL_BURST_8_BYTE	(0x01000000)
-#define NETARM_DMA_CTL_BURST_16_BYTE	(0x02000000)
-
-#define NETARM_DMA_CTL_BURST_MASK	(0x03000000)
-
-#define NETARM_DMA_CTL_SRC_INCREMENT	(0x00200000)
-
-#define NETARM_DMA_CTL_DST_INCREMENT	(0x00100000)
-
-/* these apply only to ext xfers on DMA 3 or 4 */
-
-#define NETARM_DMA_CTL_CH_3_4_REQ_EXT	(0x00800000)
-
-#define NETARM_DMA_CTL_CH_3_4_DATA_32	(0x00000000)
-#define NETARM_DMA_CTL_CH_3_4_DATA_16	(0x00010000)
-#define NETARM_DMA_CTL_CH_3_4_DATA_8	(0x00020000)
-
-#define NETARM_DMA_CTL_STATE(X)	((X) & 0xFC00)
-#define NETARM_DMA_CTL_INDEX(X)	((X) & 0x03FF)
-
-/* DMA Status Register ( 0xFF90_0XX4 ) */
-
-#define NETARM_DMA_STAT_NC_INTPEN	(0x80000000)
-#define NETARM_DMA_STAT_EC_INTPEN	(0x40000000)
-#define NETARM_DMA_STAT_NR_INTPEN	(0x20000000)
-#define NETARM_DMA_STAT_CA_INTPEN	(0x10000000)
-#define NETARM_DMA_STAT_INTPEN_MASK	(0xF0000000)
-
-#define NETARM_DMA_STAT_NC_INT_EN	(0x00800000)
-#define NETARM_DMA_STAT_EC_INT_EN	(0x00400000)
-#define NETARM_DMA_STAT_NR_INT_EN	(0x00200000)
-#define NETARM_DMA_STAT_CA_INT_EN	(0x00100000)
-#define NETARM_DMA_STAT_INT_EN_MASK	(0x00F00000)
-
-#define NETARM_DMA_STAT_WRAP		(0x00080000)
-#define NETARM_DMA_STAT_IDONE		(0x00040000)
-#define NETARM_DMA_STAT_LAST		(0x00020000)
-#define NETARM_DMA_STAT_FULL		(0x00010000)
-
-#define	NETARM_DMA_STAT_BUFLEN(X)	((X) & 0x7FFF)
-
-/* DMA Buffer Descriptor Word 0 bitfields. */
-
-#define NETARM_DMA_BD0_WRAP		(0x80000000)
-#define NETARM_DMA_BD0_IDONE		(0x40000000)
-#define NETARM_DMA_BD0_LAST		(0x20000000)
-#define NETARM_DMA_BD0_BUFPTR_MASK	(0x1FFFFFFF)
-
-/* DMA Buffer Descriptor Word 1 bitfields. */
-
-#define NETARM_DMA_BD1_STATUS_MASK	(0xFFFF0000)
-#define NETARM_DMA_BD1_FULL		(0x00008000)
-#define NETARM_DMA_BD1_BUFLEN_MASK	(0x00007FFF)
-
-#ifndef	__ASSEMBLER__
-
-typedef	struct __NETARM_DMA_Buff_Desc_FlyBy
-{
-	unsigned int word0;
-	unsigned int word1;
-} NETARM_DMA_Buff_Desc_FlyBy, *pNETARM_DMA_Buff_Desc_FlyBy ;
-
-typedef	struct __NETARM_DMA_Buff_Desc_M_to_M
-{
-	unsigned int word0;
-	unsigned int word1;
-	unsigned int word2;
-	unsigned int word3;
-} NETARM_DMA_Buff_Desc_M_to_M, *pNETARM_DMA_Buff_Desc_M_to_M ;
-
-#endif
-
-#endif
diff --git a/arch/arm/include/asm/arch-arm720t/netarm_eni_module.h b/arch/arm/include/asm/arch-arm720t/netarm_eni_module.h
deleted file mode 100644
index 317b354..0000000
--- a/arch/arm/include/asm/arch-arm720t/netarm_eni_module.h
+++ /dev/null
@@ -1,121 +0,0 @@
-/*
- * include/asm-armnommu/arch-netarm/netarm_eni_module.h
- *
- * Copyright (C) 2000 NETsilicon, Inc.
- * Copyright (C) 2000 WireSpeed Communications Corporation
- *
- * This software is copyrighted by WireSpeed. LICENSEE agrees that
- * it will not delete this copyright notice, trademarks or protective
- * notices from any copy made by LICENSEE.
- *
- * This software is provided "AS-IS" and any express or implied
- * warranties or conditions, including but not limited to any
- * implied warranties of merchantability and fitness for a particular
- * purpose regarding this software. In no event shall WireSpeed
- * be liable for any indirect, consequential, or incidental damages,
- * loss of profits or revenue, loss of use or data, or interruption
- * of business, whether the alleged damages are labeled in contract,
- * tort, or indemnity.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- * author(s) : David Smith
- */
-
-#ifndef __NETARM_ENI_MODULE_REGISTERS_H
-#define __NETARM_ENI_MODULE_REGISTERS_H
-
-/* ENI unit register offsets */
-
-/* #ifdef CONFIG_ARCH_NETARM */
-#define	NETARM_ENI_MODULE_BASE		(0xFFA00000)
-/* #endif / * CONFIG_ARCH_NETARM */
-
-#define get_eni_reg_addr(c) ((volatile unsigned int *)(NETARM_ENI_MODULE_BASE + (c)))
-#define get_eni_ctl_reg_addr(minor) \
-	(get_eni_reg_addr(NETARM_ENI_1284_PORT1_CONTROL) + (minor))
-
-#define	NETARM_ENI_GENERAL_CONTROL	(0x00)
-#define	NETARM_ENI_STATUS_CONTROL	(0x04)
-#define	NETARM_ENI_FIFO_MODE_DATA	(0x08)
-
-#define	NETARM_ENI_1284_PORT1_CONTROL	(0x10)
-#define	NETARM_ENI_1284_PORT2_CONTROL	(0x14)
-#define	NETARM_ENI_1284_PORT3_CONTROL	(0x18)
-#define	NETARM_ENI_1284_PORT4_CONTROL	(0x1c)
-
-#define	NETARM_ENI_1284_CHANNEL1_DATA	(0x20)
-#define	NETARM_ENI_1284_CHANNEL2_DATA	(0x24)
-#define	NETARM_ENI_1284_CHANNEL3_DATA	(0x28)
-#define	NETARM_ENI_1284_CHANNEL4_DATA	(0x2c)
-
-#define	NETARM_ENI_ENI_CONTROL		(0x30)
-#define	NETARM_ENI_ENI_PULSED_INTR	(0x34)
-#define	NETARM_ENI_ENI_SHARED_RAM_ADDR	(0x38)
-#define	NETARM_ENI_ENI_SHARED		(0x3c)
-
-/* select bitfield defintions */
-
-/* General Control Register (0xFFA0_0000) */
-
-#define NETARM_ENI_GCR_ENIMODE_IEEE1284	(0x00000001)
-#define NETARM_ENI_GCR_ENIMODE_SHRAM16	(0x00000004)
-#define NETARM_ENI_GCR_ENIMODE_SHRAM8	(0x00000005)
-#define NETARM_ENI_GCR_ENIMODE_FIFO16	(0x00000006)
-#define NETARM_ENI_GCR_ENIMODE_FIFO8	(0x00000007)
-
-#define NETARM_ENI_GCR_ENIMODE_MASK	(0x00000007)
-
-/* IEEE 1284 Port Control Registers 1-4 (0xFFA0_0010, 0xFFA0_0014,
-   0xFFA0_0018, 0xFFA0_001c) */
-
-#define NETARM_ENI_1284PC_PORT_ENABLE	(0x80000000)
-#define NETARM_ENI_1284PC_DMA_ENABLE	(0x40000000)
-#define NETARM_ENI_1284PC_OBE_INT_EN	(0x20000000)
-#define NETARM_ENI_1284PC_ACK_INT_EN	(0x10000000)
-#define NETARM_ENI_1284PC_ECP_MODE	(0x08000000)
-#define NETARM_ENI_1284PC_LOOPBACK_MODE	(0x04000000)
-
-#define NETARM_ENI_1284PC_STROBE_TIME0	(0x00000000) /* 0.5 uS */
-#define NETARM_ENI_1284PC_STROBE_TIME1	(0x01000000) /* 1.0 uS */
-#define NETARM_ENI_1284PC_STROBE_TIME2	(0x02000000) /* 5.0 uS */
-#define NETARM_ENI_1284PC_STROBE_TIME3	(0x03000000) /* 10.0 uS */
-#define NETARM_ENI_1284PC_STROBE_MASK	(0x03000000)
-
-#define NETARM_ENI_1284PC_MAN_STROBE_EN	(0x00800000)
-#define NETARM_ENI_1284PC_FAST_MODE	(0x00400000)
-#define NETARM_ENI_1284PC_BIDIR_MODE	(0x00200000)
-
-#define NETARM_ENI_1284PC_MAN_STROBE	(0x00080000)
-#define NETARM_ENI_1284PC_AUTO_FEED	(0x00040000)
-#define NETARM_ENI_1284PC_INIT		(0x00020000)
-#define NETARM_ENI_1284PC_HSELECT	(0x00010000)
-#define NETARM_ENI_1284PC_FE_INT_EN	(0x00008000)
-#define NETARM_ENI_1284PC_EPP_MODE	(0x00004000)
-#define NETARM_ENI_1284PC_IBR_INT_EN	(0x00002000)
-#define NETARM_ENI_1284PC_IBR		(0x00001000)
-
-#define NETARM_ENI_1284PC_RXFDB_1BYTE	(0x00000400)
-#define NETARM_ENI_1284PC_RXFDB_2BYTE	(0x00000800)
-#define NETARM_ENI_1284PC_RXFDB_3BYTE	(0x00000c00)
-#define NETARM_ENI_1284PC_RXFDB_4BYTE	(0x00000000)
-
-#define NETARM_ENI_1284PC_RBCC		(0x00000200)
-#define NETARM_ENI_1284PC_RBCT		(0x00000100)
-#define NETARM_ENI_1284PC_ACK		(0x00000080)
-#define NETARM_ENI_1284PC_FIFO_E	(0x00000040)
-#define NETARM_ENI_1284PC_OBE		(0x00000020)
-#define NETARM_ENI_1284PC_ACK_INT	(0x00000010)
-#define NETARM_ENI_1284PC_BUSY		(0x00000008)
-#define NETARM_ENI_1284PC_PE		(0x00000004)
-#define NETARM_ENI_1284PC_PSELECT	(0x00000002)
-#define NETARM_ENI_1284PC_FAULT		(0x00000001)
-
-#endif /* __NETARM_ENI_MODULE_REGISTERS_H */
diff --git a/arch/arm/include/asm/arch-arm720t/netarm_eth_module.h b/arch/arm/include/asm/arch-arm720t/netarm_eth_module.h
deleted file mode 100644
index 8f2f369..0000000
--- a/arch/arm/include/asm/arch-arm720t/netarm_eth_module.h
+++ /dev/null
@@ -1,160 +0,0 @@
-/*
- * include/asm-armnommu/arch-netarm/netarm_eth_module.h
- *
- * Copyright (C) 2000 NETsilicon, Inc.
- * Copyright (C) 2000 WireSpeed Communications Corporation
- *
- * This software is copyrighted by WireSpeed. LICENSEE agrees that
- * it will not delete this copyright notice, trademarks or protective
- * notices from any copy made by LICENSEE.
- *
- * This software is provided "AS-IS" and any express or implied
- * warranties or conditions, including but not limited to any
- * implied warranties of merchantability and fitness for a particular
- * purpose regarding this software. In no event shall WireSpeed
- * be liable for any indirect, consequential, or incidental damages,
- * loss of profits or revenue, loss of use or data, or interruption
- * of business, whether the alleged damages are labeled in contract,
- * tort, or indemnity.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- * author(s) : Jackie Smith Cashion
- *             David Smith
- */
-
-#ifndef __NETARM_ETH_MODULE_REGISTERS_H
-#define __NETARM_ETH_MODULE_REGISTERS_H
-
-/* ETH unit register offsets */
-
-#define	NETARM_ETH_MODULE_BASE		(0xFF800000)
-
-#define get_eth_reg_addr(c) ((volatile unsigned int *)(NETARM_ETH_MODULE_BASE + (c)))
-
-#define NETARM_ETH_GEN_CTRL		(0x000) /* Ethernet Gen Control Reg */
-#define NETARM_ETH_GEN_STAT		(0x004) /* Ethernet Gen Status Reg */
-#define NETARM_ETH_FIFO_DAT1            (0x008) /* Fifo Data Reg 1 */
-#define NETARM_ETH_FIFO_DAT2            (0x00C) /* Fifo Data Reg 2 */
-#define NETARM_ETH_TX_STAT              (0x010) /* Transmit Status Reg */
-#define NETARM_ETH_RX_STAT              (0x014) /* Receive Status Reg */
-
-#define NETARM_ETH_MAC_CFG		(0x400) /* MAC Configuration Reg */
-#define NETARM_ETH_PCS_CFG		(0x408) /* PCS Configuration Reg */
-#define NETARM_ETH_STL_CFG		(0x410) /* STL Configuration Reg */
-#define NETARM_ETH_B2B_IPG_GAP_TMR	(0x440) /* Back-to-back IPG
-						   Gap Timer Reg */
-#define NETARM_ETH_NB2B_IPG_GAP_TMR	(0x444) /* Non Back-to-back
-						   IPG Gap Timer Reg */
-#define NETARM_ETH_MII_CMD		(0x540) /* MII (PHY) Command Reg */
-#define NETARM_ETH_MII_ADDR		(0x544) /* MII Address Reg */
-#define NETARM_ETH_MII_WRITE		(0x548) /* MII Write Data Reg */
-#define NETARM_ETH_MII_READ		(0x54C) /* MII Read Data Reg */
-#define NETARM_ETH_MII_IND		(0x550) /* MII Indicators Reg */
-#define NETARM_ETH_MIB_CRCEC		(0x580) /* (MIB) CRC Error Counter */
-#define NETARM_ETH_MIB_AEC		(0x584) /* Alignment Error Counter */
-#define NETARM_ETH_MIB_CEC		(0x588) /* Code Error Counter */
-#define NETARM_ETH_MIB_LFC		(0x58C) /* Long Frame Counter */
-#define NETARM_ETH_MIB_SFC		(0x590) /* Short Frame Counter */
-#define NETARM_ETH_MIB_LCC		(0x594) /* Late Collision Counter */
-#define NETARM_ETH_MIB_EDC		(0x598) /* Excessive Deferral
-						   Counter */
-#define NETARM_ETH_MIB_MCC		(0x59C) /* Maximum Collision Counter */
-#define NETARM_ETH_SAL_FILTER		(0x5C0) /* SAL Station Address
-						   Filter Reg */
-#define NETARM_ETH_SAL_STATION_ADDR_1	(0x5C4) /* SAL Station Address
-						   Reg */
-#define NETARM_ETH_SAL_STATION_ADDR_2	(0x5C8)
-#define NETARM_ETH_SAL_STATION_ADDR_3	(0x5CC)
-#define NETARM_ETH_SAL_HASH_TBL_1	(0x5D0) /* SAL Multicast Hash Table*/
-#define NETARM_ETH_SAL_HASH_TBL_2	(0x5D4)
-#define NETARM_ETH_SAL_HASH_TBL_3	(0x5D8)
-#define NETARM_ETH_SAL_HASH_TBL_4	(0x5DC)
-
-/* select bitfield defintions */
-
-/* Ethernet General Control Register (0xFF80_0000) */
-
-#define NETARM_ETH_GCR_ERX		(0x80000000) /* Enable Receive FIFO */
-#define NETARM_ETH_GCR_ERXDMA		(0x40000000) /* Enable Receive DMA */
-#define NETARM_ETH_GCR_ETX		(0x00800000) /* Enable Transmit FIFO */
-#define NETARM_ETH_GCR_ETXDMA		(0x00400000) /* Enable Transmit DMA */
-#define NETARM_ETH_GCR_ETXWM_50		(0x00100000) /* Transmit FIFO Water
-							Mark.  Start transmit
-							when FIFO is 50%
-							full. */
-#define NETARM_ETH_GCR_PNA		(0x00000400) /* pSOS pNA Buffer
-							Descriptor Format */
-
-/* Ethernet General Status Register (0xFF80_0004) */
-
-#define NETARM_ETH_GST_RXFDB            (0x30000000)
-#define NETARM_ETH_GST_RXREGR		(0x08000000) /* Receive Register
-							Ready */
-#define NETARM_ETH_GST_RXFIFOH		(0x04000000)
-#define NETARM_ETH_GST_RXBR		(0x02000000)
-#define NETARM_ETH_GST_RXSKIP		(0x01000000)
-
-#define NETARM_ETH_GST_TXBC             (0x00020000)
-
-
-/* Ethernet Transmit Status Register (0xFF80_0010) */
-
-#define NETARM_ETH_TXSTAT_TXOK          (0x00008000)
-
-
-/* Ethernet Receive Status Register (0xFF80_0014) */
-
-#define NETARM_ETH_RXSTAT_SIZE          (0xFFFF0000)
-#define NETARM_ETH_RXSTAT_RXOK          (0x00002000)
-
-
-/* PCS Configuration Register (0xFF80_0408) */
-
-#define NETARM_ETH_PCSC_NOCFR		(0x1) /* Disable Ciphering */
-#define NETARM_ETH_PCSC_ENJAB		(0x2) /* Enable Jabber Protection */
-#define NETARM_ETH_PCSC_CLKS_25M	(0x0) /* 25 MHz Clock Speed Select */
-#define NETARM_ETH_PCSC_CLKS_33M	(0x4) /* 33 MHz Clock Speed Select */
-
-/* STL Configuration Register (0xFF80_0410) */
-
-#define NETARM_ETH_STLC_RXEN		(0x2) /* Enable Packet Receiver */
-#define NETARM_ETH_STLC_AUTOZ		(0x4) /* Auto Zero Statistics */
-
-/* MAC Configuration Register (0xFF80_0400) */
-
-#define NETARM_ETH_MACC_HUGEN		(0x1) /* Enable Unlimited Transmit
-						 Frame Sizes */
-#define NETARM_ETH_MACC_PADEN		(0x4) /* Automatic Pad Fill Frames
-						 to 64 Bytes */
-#define NETARM_ETH_MACC_CRCEN		(0x8) /* Append CRC to Transmit
-						 Frames */
-
-/* MII (PHY) Command Register (0xFF80_0540) */
-
-#define NETARM_ETH_MIIC_RSTAT		(0x1) /* Single Scan for Read Data */
-
-/* MII Indicators Register (0xFF80_0550) */
-
-#define NETARM_ETH_MIII_BUSY		(0x1) /* MII I/F Busy with
-						 Read/Write */
-
-/* SAL Station Address Filter Register (0xFF80_05C0) */
-
-#define NETARM_ETH_SALF_PRO		(0x8) /* Enable Promiscuous Mode */
-#define NETARM_ETH_SALF_PRM		(0x4) /* Accept All Multicast
-						 Packets */
-#define NETARM_ETH_SALF_PRA		(0x2) /* Accept Mulitcast Packets
-						 using Hash Table */
-#define NETARM_ETH_SALF_BROAD		(0x1) /* Accept All Broadcast
-						 Packets */
-
-
-#endif /* __NETARM_GEN_MODULE_REGISTERS_H */
diff --git a/arch/arm/include/asm/arch-arm720t/netarm_gen_module.h b/arch/arm/include/asm/arch-arm720t/netarm_gen_module.h
deleted file mode 100644
index 13656a3..0000000
--- a/arch/arm/include/asm/arch-arm720t/netarm_gen_module.h
+++ /dev/null
@@ -1,186 +0,0 @@
-/*
- * include/asm-armnommu/arch-netarm/netarm_gen_module.h
- *
- * Copyright (C) 2005
- * Art Shipkowski, Videon Central, Inc., <art@videon-central.com>
- *
- * Copyright (C) 2000, 2001 NETsilicon, Inc.
- * Copyright (C) 2000, 2001 Red Hat, Inc.
- *
- * This software is copyrighted by Red Hat. LICENSEE agrees that
- * it will not delete this copyright notice, trademarks or protective
- * notices from any copy made by LICENSEE.
- *
- * This software is provided "AS-IS" and any express or implied
- * warranties or conditions, including but not limited to any
- * implied warranties of merchantability and fitness for a particular
- * purpose regarding this software. In no event shall Red Hat
- * be liable for any indirect, consequential, or incidental damages,
- * loss of profits or revenue, loss of use or data, or interruption
- * of business, whether the alleged damages are labeled in contract,
- * tort, or indemnity.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- * author(s) : Joe deBlaquiere
- *
- * Modified to support NS7520 by Art Shipkowski.
- */
-
-#ifndef __NETARM_GEN_MODULE_REGISTERS_H
-#define __NETARM_GEN_MODULE_REGISTERS_H
-
-/* GEN unit register offsets */
-
-#define NETARM_GEN_MODULE_BASE		(0xFFB00000)
-
-#define get_gen_reg_addr(c) ((volatile unsigned int *)(NETARM_GEN_MODULE_BASE + (c)))
-
-#define NETARM_GEN_SYSTEM_CONTROL	(0x00)
-#define NETARM_GEN_STATUS_CONTROL	(0x04)
-#define NETARM_GEN_PLL_CONTROL		(0x08)
-#define NETARM_GEN_SOFTWARE_SERVICE	(0x0c)
-
-#define NETARM_GEN_TIMER1_CONTROL	(0x10)
-#define NETARM_GEN_TIMER1_STATUS	(0x14)
-#define NETARM_GEN_TIMER2_CONTROL	(0x18)
-#define NETARM_GEN_TIMER2_STATUS	(0x1c)
-
-#define NETARM_GEN_PORTA		(0x20)
-#ifndef CONFIG_NETARM_NS7520
-#define NETARM_GEN_PORTB		(0x24)
-#endif
-#define NETARM_GEN_PORTC		(0x28)
-
-#define NETARM_GEN_INTR_ENABLE		(0x30)
-#define NETARM_GEN_INTR_ENABLE_SET	(0x34)
-#define NETARM_GEN_INTR_ENABLE_CLR	(0x38)
-#define NETARM_GEN_INTR_STATUS_EN	(0x34)
-#define NETARM_GEN_INTR_STATUS_RAW	(0x38)
-
-#define NETARM_GEN_CACHE_CONTROL1	(0x40)
-#define NETARM_GEN_CACHE_CONTROL2	(0x44)
-
-/* select bitfield definitions */
-
-/* System Control Register ( 0xFFB0_0000 ) */
-
-#define NETARM_GEN_SYS_CFG_LENDIAN	(0x80000000)
-#define NETARM_GEN_SYS_CFG_BENDIAN	(0x00000000)
-
-#define NETARM_GEN_SYS_CFG_BUSQRTR	(0x00000000)
-#define NETARM_GEN_SYS_CFG_BUSHALF	(0x20000000)
-#define NETARM_GEN_SYS_CFG_BUSFULL	(0x40000000)
-
-#define NETARM_GEN_SYS_CFG_BCLK_DISABLE (0x10000000)
-
-#define NETARM_GEN_SYS_CFG_WDOG_EN	(0x01000000)
-#define NETARM_GEN_SYS_CFG_WDOG_IRQ	(0x00000000)
-#define NETARM_GEN_SYS_CFG_WDOG_FIQ	(0x00400000)
-#define NETARM_GEN_SYS_CFG_WDOG_RST	(0x00800000)
-#define NETARM_GEN_SYS_CFG_WDOG_24	(0x00000000)
-#define NETARM_GEN_SYS_CFG_WDOG_26	(0x00100000)
-#define NETARM_GEN_SYS_CFG_WDOG_28	(0x00200000)
-#define NETARM_GEN_SYS_CFG_WDOG_29	(0x00300000)
-
-#define NETARM_GEN_SYS_CFG_BUSMON_EN	(0x00040000)
-#define NETARM_GEN_SYS_CFG_BUSMON_128	(0x00000000)
-#define NETARM_GEN_SYS_CFG_BUSMON_64	(0x00010000)
-#define NETARM_GEN_SYS_CFG_BUSMON_32	(0x00020000)
-#define NETARM_GEN_SYS_CFG_BUSMON_16	(0x00030000)
-
-#define NETARM_GEN_SYS_CFG_USER_EN	(0x00008000)
-#define NETARM_GEN_SYS_CFG_BUSER_EN	(0x00004000)
-
-#define NETARM_GEN_SYS_CFG_BUSARB_INT	(0x00002000)
-#define NETARM_GEN_SYS_CFG_BUSARB_EXT	(0x00000000)
-
-#define NETARM_GEN_SYS_CFG_DMATST	(0x00001000)
-
-#define NETARM_GEN_SYS_CFG_TEALAST	(0x00000800)
-
-#define NETARM_GEN_SYS_CFG_ALIGN_ABORT	(0x00000400)
-
-#define NETARM_GEN_SYS_CFG_CACHE_EN	(0x00000200)
-
-#define NETARM_GEN_SYS_CFG_WRI_BUF_EN	(0x00000100)
-
-#define NETARM_GEN_SYS_CFG_CACHE_INIT	(0x00000080)
-
-/* PLL Control Register ( 0xFFB0_0008 ) */
-
-#define NETARM_GEN_PLL_CTL_PLLCNT_MASK	(0x0F000000)
-
-#define NETARM_GEN_PLL_CTL_PLLCNT(x)	(((x)<<24) & \
-					 NETARM_GEN_PLL_CTL_PLLCNT_MASK)
-
-/* Defaults for POLTST and ICP Fields in PLL CTL */
-#define NETARM_GEN_PLL_CTL_OUTDIV(x)	(x)
-#define NETARM_GEN_PLL_CTL_INDIV(x)	((x)<<6)
-#define NETARM_GEN_PLL_CTL_POLTST_DEF	(0x00000E00)
-#define NETARM_GEN_PLL_CTL_ICP_DEF	(0x0000003C)
-
-
-/* Software Service Register ( 0xFFB0_000C ) */
-
-#define NETARM_GEN_SW_SVC_RESETA	(0x123)
-#define NETARM_GEN_SW_SVC_RESETB	(0x321)
-
-/* PORT C Register ( 0xFFB0_0028 ) */
-
-#ifndef CONFIG_NETARM_NS7520
-#define NETARM_GEN_PORT_MODE(x)		(((x)<<24) + (0xFF00))
-#define NETARM_GEN_PORT_DIR(x)		(((x)<<16) + (0xFF00))
-#else
-#define NETARM_GEN_PORT_MODE(x)		((x)<<24)
-#define NETARM_GEN_PORT_DIR(x)		((x)<<16)
-#define NETARM_GEN_PORT_CSF(x)		((x)<<8)
-#endif
-
-/* Timer Registers ( 0xFFB0_0010 0xFFB0_0018 ) */
-
-#define NETARM_GEN_TCTL_ENABLE		(0x80000000)
-#define NETARM_GEN_TCTL_INT_ENABLE	(0x40000000)
-
-#define NETARM_GEN_TCTL_USE_IRQ		(0x00000000)
-#define NETARM_GEN_TCTL_USE_FIQ		(0x20000000)
-
-#define NETARM_GEN_TCTL_USE_PRESCALE	(0x10000000)
-#define NETARM_GEN_TCTL_INIT_COUNT(x)	((x) & 0x1FF)
-
-#define NETARM_GEN_TSTAT_INTPEN		(0x40000000)
-#if ~defined(CONFIG_NETARM_NS7520)
-#define NETARM_GEN_TSTAT_CTC_MASK	(0x000001FF)
-#else
-#define NETARM_GEN_TSTAT_CTC_MASK	(0x0FFFFFFF)
-#endif
-
-/* prescale to msecs conversion */
-
-#if !defined(CONFIG_NETARM_PLL_BYPASS)
-#define NETARM_GEN_TIMER_MSEC_P(x)	( ( ( 20480 ) * ( 0x1FF - ( (x) &	    \
-					    NETARM_GEN_TSTAT_CTC_MASK ) +   \
-					    1 ) ) / (NETARM_XTAL_FREQ/1000) )
-
-#define NETARM_GEN_TIMER_SET_HZ(x)	( ( ((NETARM_XTAL_FREQ/(20480*(x)))-1) & \
-					  NETARM_GEN_TSTAT_CTC_MASK ) | \
-					  NETARM_GEN_TCTL_USE_PRESCALE )
-
-#else
-#define NETARM_GEN_TIMER_MSEC_P(x)	( ( ( 4096 ) * ( 0x1FF - ( (x) &    \
-					    NETARM_GEN_TSTAT_CTC_MASK ) +   \
-					    1 ) ) / (NETARM_XTAL_FREQ/1000) )
-
-#define NETARM_GEN_TIMER_SET_HZ(x)	( ( ((NETARM_XTAL_FREQ/(4096*(x)))-1) & \
-					  NETARM_GEN_TSTAT_CTC_MASK ) | \
-					  NETARM_GEN_TCTL_USE_PRESCALE )
-#endif
-
-#endif
diff --git a/arch/arm/include/asm/arch-arm720t/netarm_mem_module.h b/arch/arm/include/asm/arch-arm720t/netarm_mem_module.h
deleted file mode 100644
index c650c3b..0000000
--- a/arch/arm/include/asm/arch-arm720t/netarm_mem_module.h
+++ /dev/null
@@ -1,184 +0,0 @@
-/*
- * include/asm-armnommu/arch-netarm/netarm_mem_module.h
- *
- * Copyright (C) 2005
- * Art Shipkowski, Videon Central, Inc., <art@videon-central.com>
- *
- * Copyright (C) 2000, 2001 NETsilicon, Inc.
- * Copyright (C) 2000, 2001 Red Hat, Inc.
- *
- * This software is copyrighted by Red Hat. LICENSEE agrees that
- * it will not delete this copyright notice, trademarks or protective
- * notices from any copy made by LICENSEE.
- *
- * This software is provided "AS-IS" and any express or implied
- * warranties or conditions, including but not limited to any
- * implied warranties of merchantability and fitness for a particular
- * purpose regarding this software. In no event shall Red Hat
- * be liable for any indirect, consequential, or incidental damages,
- * loss of profits or revenue, loss of use or data, or interruption
- * of business, whether the alleged damages are labeled in contract,
- * tort, or indemnity.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- * author(s) : Joe deBlaquiere
- *
- * Modified to support NS7520 by Art Shipkowski.
- */
-
-#ifndef __NETARM_MEM_MODULE_REGISTERS_H
-#define __NETARM_MEM_MODULE_REGISTERS_H
-
-/* GEN unit register offsets */
-
-#define	NETARM_MEM_MODULE_BASE		(0xFFC00000)
-
-#define	NETARM_MEM_MODULE_CONFIG	(0x00)
-#define	NETARM_MEM_CS0_BASE_ADDR	(0x10)
-#define	NETARM_MEM_CS0_OPTIONS		(0x14)
-#define	NETARM_MEM_CS1_BASE_ADDR	(0x20)
-#define	NETARM_MEM_CS1_OPTIONS		(0x24)
-#define	NETARM_MEM_CS2_BASE_ADDR	(0x30)
-#define	NETARM_MEM_CS2_OPTIONS		(0x34)
-#define	NETARM_MEM_CS3_BASE_ADDR	(0x40)
-#define	NETARM_MEM_CS3_OPTIONS		(0x44)
-#define	NETARM_MEM_CS4_BASE_ADDR	(0x50)
-#define	NETARM_MEM_CS4_OPTIONS		(0x54)
-
-/* select bitfield defintions */
-
-/* Module Configuration Register ( 0xFFC0_0000 ) */
-
-#define NETARM_MEM_CFG_REFR_COUNT_MASK	(0xFF000000)
-#define NETARM_MEM_CFG_REFRESH_EN	(0x00800000)
-
-#define NETARM_MEM_CFG_REFR_CYCLE_8CLKS	(0x00000000)
-#define NETARM_MEM_CFG_REFR_CYCLE_6CLKS	(0x00200000)
-#define NETARM_MEM_CFG_REFR_CYCLE_5CLKS	(0x00400000)
-#define NETARM_MEM_CFG_REFR_CYCLE_4CLKS	(0x00600000)
-
-#define NETARM_MEM_CFG_PORTC_AMUX	(0x00100000)
-
-#define NETARM_MEM_CFG_A27_ADDR		(0x00080000)
-#define NETARM_MEM_CFG_A27_CS0OE	(0x00000000)
-
-#define NETARM_MEM_CFG_A26_ADDR		(0x00040000)
-#define NETARM_MEM_CFG_A26_CS0WE	(0x00000000)
-
-#define NETARM_MEM_CFG_A25_ADDR		(0x00020000)
-#define NETARM_MEM_CFG_A25_BLAST	(0x00000000)
-
-#define NETARM_MEM_CFG_PORTC_AMUX2	(0x00010000)
-
-
-/* range on this period is about 1 to 275 usec (with 18.432MHz clock)   */
-/* the expression will round down, so make sure to reverse it to verify */
-/* it is what you want. period = [( count + 1 ) * 20] / Fcrystal        */
-/* (note: Fxtal = Fcrystal/5, see HWRefGuide sections 8.2.5 and 11.3.2) */
-
-#define	NETARM_MEM_REFR_PERIOD_USEC(p)	(NETARM_MEM_CFG_REFR_COUNT_MASK & \
-					 (((((NETARM_XTAL_FREQ/(1000))*p)/(20000) \
-					    ) - (1) ) << (24)))
-
-#if 0
-/* range on this period is about 1 to 275 usec (with 18.432MHz clock) */
-/* the expression will round down, so make sure to reverse it toverify */
-/* it is what you want. period = [( count + 1 ) * 4] / Fxtal          */
-
-#define	NETARM_MEM_REFR_PERIOD_USEC(p)	(NETARM_MEM_CFG_REFR_COUNT_MASK & \
-					 (((((NETARM_XTAL_FREQ/(1000))*p)/(4000) \
-					    ) - (1) ) << (24)))
-#endif
-
-/* Base Address Registers (0xFFC0_00X0) */
-
-#define NETARM_MEM_BAR_BASE_MASK	(0xFFFFF000)
-
-/* macro to define base */
-
-#define NETARM_MEM_BAR_BASE(x)		((x) & NETARM_MEM_BAR_BASE_MASK)
-
-#define NETARM_MEM_BAR_DRAM_FP		(0x00000000)
-#define NETARM_MEM_BAR_DRAM_EDO		(0x00000100)
-#define NETARM_MEM_BAR_DRAM_SYNC	(0x00000200)
-
-#define NETARM_MEM_BAR_DRAM_MUX_INT	(0x00000000)
-#define NETARM_MEM_BAR_DRAM_MUX_EXT	(0x00000080)
-
-#define NETARM_MEM_BAR_DRAM_MUX_BAL	(0x00000000)
-#define NETARM_MEM_BAR_DRAM_MUX_UNBAL	(0x00000020)
-
-#define NETARM_MEM_BAR_1BCLK_IDLE	(0x00000010)
-
-#define NETARM_MEM_BAR_DRAM_SEL		(0x00000008)
-
-#define NETARM_MEM_BAR_BURST_EN		(0x00000004)
-
-#define NETARM_MEM_BAR_WRT_PROT		(0x00000002)
-
-#define NETARM_MEM_BAR_VALID		(0x00000001)
-
-/* Option Registers (0xFFC0_00X4) */
-
-/* macro to define which bits of the base are significant */
-
-#define NETARM_MEM_OPT_BASE_USE(x)	((x) & NETARM_MEM_BAR_BASE_MASK)
-
-#define NETARM_MEM_OPT_WAIT_MASK	(0x00000F00)
-
-#define	NETARM_MEM_OPT_WAIT_STATES(x)	(((x) << 8 ) & NETARM_MEM_OPT_WAIT_MASK )
-
-#define NETARM_MEM_OPT_BCYC_1		(0x00000000)
-#define NETARM_MEM_OPT_BCYC_2		(0x00000040)
-#define NETARM_MEM_OPT_BCYC_3		(0x00000080)
-#define NETARM_MEM_OPT_BCYC_4		(0x000000C0)
-
-#define NETARM_MEM_OPT_BSIZE_2		(0x00000000)
-#define NETARM_MEM_OPT_BSIZE_4		(0x00000010)
-#define NETARM_MEM_OPT_BSIZE_8		(0x00000020)
-#define NETARM_MEM_OPT_BSIZE_16		(0x00000030)
-
-#define NETARM_MEM_OPT_32BIT		(0x00000000)
-#define NETARM_MEM_OPT_16BIT		(0x00000004)
-#define NETARM_MEM_OPT_8BIT		(0x00000008)
-#define NETARM_MEM_OPT_32BIT_EXT_ACK	(0x0000000C)
-
-#define NETARM_MEM_OPT_BUS_SIZE_MASK	(0x0000000C)
-
-#define NETARM_MEM_OPT_READ_ASYNC	(0x00000000)
-#define NETARM_MEM_OPT_READ_SYNC	(0x00000002)
-
-#define NETARM_MEM_OPT_WRITE_ASYNC	(0x00000000)
-#define NETARM_MEM_OPT_WRITE_SYNC	(0x00000001)
-
-#ifdef CONFIG_NETARM_NS7520
-/* The NS7520 has a second options register for each chip select */
-#define	NETARM_MEM_CS0_OPTIONS_B  (0x18)
-#define	NETARM_MEM_CS1_OPTIONS_B  (0x28)
-#define	NETARM_MEM_CS2_OPTIONS_B  (0x38)
-#define	NETARM_MEM_CS3_OPTIONS_B  (0x48)
-#define	NETARM_MEM_CS4_OPTIONS_B  (0x58)
-
-/* Option B Registers (0xFFC0_00x8) */
-#define NETARM_MEM_OPTB_SYNC_1_STAGE	(0x00000001)
-#define NETARM_MEM_OPTB_SYNC_2_STAGE	(0x00000002)
-#define NETARM_MEM_OPTB_BCYC_PLUS0	(0x00000000)
-#define NETARM_MEM_OPTB_BCYC_PLUS4	(0x00000004)
-#define NETARM_MEM_OPTB_BCYC_PLUS8	(0x00000008)
-#define NETARM_MEM_OPTB_BCYC_PLUS12	(0x0000000C)
-
-#define NETARM_MEM_OPTB_WAIT_PLUS0	(0x00000000)
-#define NETARM_MEM_OPTB_WAIT_PLUS16	(0x00000010)
-#define NETARM_MEM_OPTB_WAIT_PLUS32	(0x00000020)
-#define NETARM_MEM_OPTB_WAIT_PLUS48	(0x00000030)
-#endif
-
-#endif
diff --git a/arch/arm/include/asm/arch-arm720t/netarm_registers.h b/arch/arm/include/asm/arch-arm720t/netarm_registers.h
deleted file mode 100644
index fa88128..0000000
--- a/arch/arm/include/asm/arch-arm720t/netarm_registers.h
+++ /dev/null
@@ -1,96 +0,0 @@
-/*
- * linux/include/asm-arm/arch-netarm/netarm_registers.h
- *
- * Copyright (C) 2005
- * Art Shipkowski, Videon Central, Inc., <art@videon-central.com>
- *
- * Copyright (C) 2000, 2001 NETsilicon, Inc.
- * Copyright (C) 2000, 2001 WireSpeed Communications Corporation
- *
- * This software is copyrighted by WireSpeed. LICENSEE agrees that
- * it will not delete this copyright notice, trademarks or protective
- * notices from any copy made by LICENSEE.
- *
- * This software is provided "AS-IS" and any express or implied
- * warranties or conditions, including but not limited to any
- * implied warranties of merchantability and fitness for a particular
- * purpose regarding this software. In no event shall WireSpeed
- * be liable for any indirect, consequential, or incidental damages,
- * loss of profits or revenue, loss of use or data, or interruption
- * of business, whether the alleged damages are labeled in contract,
- * tort, or indemnity.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- * author(s) : Joe deBlaquiere
- *
- * Modified to support NS7520 by Art Shipkowski.
- */
-
-#ifndef __NET_ARM_REGISTERS_H
-#define __NET_ARM_REGISTERS_H
-
-#include <config.h>
-
-/* fundamental constants : */
-/* the input crystal/clock frequency ( in Hz ) */
-#define	NETARM_XTAL_FREQ_25MHz		(18432000)
-#define	NETARM_XTAL_FREQ_33MHz		(23698000)
-#define	NETARM_XTAL_FREQ_48MHz		(48000000)
-#define	NETARM_XTAL_FREQ_55MHz		(55000000)
-#define NETARM_XTAL_FREQ_EMLIN1		(20000000)
-
-/* the frequency of SYS_CLK */
-#if defined(CONFIG_NETARM_EMLIN)
-
-/* EMLIN board:  33 MHz (exp.) */
-#define	NETARM_PLL_COUNT_VAL		6
-#define NETARM_XTAL_FREQ		NETARM_XTAL_FREQ_25MHz
-
-#elif defined(CONFIG_NETARM_NET40_REV2)
-
-/* NET+40 Rev2 boards:  33 MHz (with NETARM_XTAL_FREQ_25MHz) */
-#define	NETARM_PLL_COUNT_VAL		6
-#define	NETARM_XTAL_FREQ		NETARM_XTAL_FREQ_25MHz
-
-#elif defined(CONFIG_NETARM_NET40_REV4)
-
-/* NET+40 Rev4 boards with EDO must clock slower: 25 MHz (with
-   NETARM_XTAL_FREQ_25MHz) 4 */
-#define	NETARM_PLL_COUNT_VAL		4
-#define	NETARM_XTAL_FREQ		NETARM_XTAL_FREQ_25MHz
-
-#elif defined(CONFIG_NETARM_NET50)
-
-/* NET+50 boards:  40 MHz (with NETARM_XTAL_FREQ_25MHz) */
-#define NETARM_PLL_COUNT_VAL		8
-#define	NETARM_XTAL_FREQ		NETARM_XTAL_FREQ_25MHz
-
-#else	/* CONFIG_NETARM_NS7520 */
-
-#define	NETARM_PLL_COUNT_VAL		0
-
-#if defined(CONFIG_BOARD_UNC20)
-#define	NETARM_XTAL_FREQ		NETARM_XTAL_FREQ_48MHz
-#else
-#define	NETARM_XTAL_FREQ		NETARM_XTAL_FREQ_55MHz
-#endif
-
-#endif
-
-/* #include "arm_registers.h" */
-#include <asm/arch/netarm_gen_module.h>
-#include <asm/arch/netarm_mem_module.h>
-#include <asm/arch/netarm_ser_module.h>
-#include <asm/arch/netarm_eni_module.h>
-#include <asm/arch/netarm_dma_module.h>
-#include <asm/arch/netarm_eth_module.h>
-
-#endif
diff --git a/arch/arm/include/asm/arch-arm720t/netarm_ser_module.h b/arch/arm/include/asm/arch-arm720t/netarm_ser_module.h
deleted file mode 100644
index 6fbae11..0000000
--- a/arch/arm/include/asm/arch-arm720t/netarm_ser_module.h
+++ /dev/null
@@ -1,347 +0,0 @@
-/*
- * linux/include/asm-arm/arch-netarm/netarm_ser_module.h
- *
- * Copyright (C) 2000 NETsilicon, Inc.
- * Copyright (C) 2000 Red Hat, Inc.
- *
- * This software is copyrighted by Red Hat. LICENSEE agrees that
- * it will not delete this copyright notice, trademarks or protective
- * notices from any copy made by LICENSEE.
- *
- * This software is provided "AS-IS" and any express or implied
- * warranties or conditions, including but not limited to any
- * implied warranties of merchantability and fitness for a particular
- * purpose regarding this software. In no event shall Red Hat
- * be liable for any indirect, consequential, or incidental damages,
- * loss of profits or revenue, loss of use or data, or interruption
- * of business, whether the alleged damages are labeled in contract,
- * tort, or indemnity.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- * author(s) : Joe deBlaquiere
- *             Clark Williams
- */
-
-#ifndef __NETARM_SER_MODULE_REGISTERS_H
-#define __NETARM_SER_MODULE_REGISTERS_H
-
-#ifndef	__ASSEMBLER__
-
-/* (--sub)#include "types.h" */
-
-/* serial channel control structure */
-typedef struct {
-  u32	ctrl_a;
-  u32	ctrl_b;
-  u32	status_a;
-  u32	bitrate;
-  u32	fifo;
-  u32	rx_buf_timer;
-  u32	rx_char_timer;
-  u32	rx_match;
-  u32	rx_match_mask;
-  u32	ctrl_c;
-  u32	status_b;
-  u32	status_c;
-  u32	fifo_last;
-  u32	unused[3];
-} netarm_serial_channel_t;
-
-#endif
-
-/* SER unit register offsets */
-
-/* #ifdef CONFIG_ARCH_NETARM */
-#define	NETARM_SER_MODULE_BASE		(0xFFD00000)
-/* #else */
-/* extern serial_channel_t netarm_dummy_registers[]; */
-/* #define NETARM_SER_MODULE_BASE		(netarm_dummy_registers) */
-/* #ifndef NETARM_XTAL_FREQ */
-/* #define NETARM_XTAL_FREQ                18432000 */
-/* #endif */
-/* #endif */
-
-/* calculate the sysclk value from the pll setting */
-#define	NETARM_PLLED_SYSCLK_FREQ	(( NETARM_XTAL_FREQ / 5 ) * \
-					 ( NETARM_PLL_COUNT_VAL + 3 ))
-
-#define get_serial_channel(c) (&(((netarm_serial_channel_t *)NETARM_SER_MODULE_BASE)[c]))
-
-#define	NETARM_SER_CH1_CTRL_A		(0x00)
-#define	NETARM_SER_CH1_CTRL_B		(0x04)
-#define	NETARM_SER_CH1_STATUS_A		(0x08)
-#define	NETARM_SER_CH1_BITRATE		(0x0C)
-#define	NETARM_SER_CH1_FIFO		(0x10)
-#define	NETARM_SER_CH1_RX_BUF_TMR	(0x14)
-#define	NETARM_SER_CH1_RX_CHAR_TMR	(0x18)
-#define	NETARM_SER_CH1_RX_MATCH		(0x1c)
-#define	NETARM_SER_CH1_RX_MATCH_MASK	(0x20)
-#define	NETARM_SER_CH1_CTRL_C		(0x24)
-#define	NETARM_SER_CH1_STATUS_B		(0x28)
-#define	NETARM_SER_CH1_STATUS_C		(0x2c)
-#define	NETARM_SER_CH1_FIFO_LAST	(0x30)
-
-#define	NETARM_SER_CH2_CTRL_A		(0x40)
-#define	NETARM_SER_CH2_CTRL_B		(0x44)
-#define	NETARM_SER_CH2_STATUS_A		(0x48)
-#define	NETARM_SER_CH2_BITRATE		(0x4C)
-#define	NETARM_SER_CH2_FIFO		(0x50)
-#define	NETARM_SER_CH2_RX_BUF_TMR	(0x54)
-#define	NETARM_SER_CH2_RX_CHAR_TMR	(0x58)
-#define	NETARM_SER_CH2_RX_MATCH		(0x5c)
-#define	NETARM_SER_CH2_RX_MATCH_MASK	(0x60)
-#define	NETARM_SER_CH2_CTRL_C		(0x64)
-#define	NETARM_SER_CH2_STATUS_B		(0x68)
-#define	NETARM_SER_CH2_STATUS_C		(0x6c)
-#define	NETARM_SER_CH2_FIFO_LAST	(0x70)
-
-/* select bitfield defintions */
-
-/* Control Register A */
-
-#define	NETARM_SER_CTLA_ENABLE		(0x80000000)
-#define	NETARM_SER_CTLA_BRK		(0x40000000)
-
-#define	NETARM_SER_CTLA_STICKP		(0x20000000)
-
-#define	NETARM_SER_CTLA_P_EVEN		(0x18000000)
-#define	NETARM_SER_CTLA_P_ODD		(0x08000000)
-#define	NETARM_SER_CTLA_P_NONE		(0x00000000)
-
-/* if you read the errata, you will find that the STOP bits don't work right */
-#define	NETARM_SER_CTLA_2STOP		(0x00000000)
-#define	NETARM_SER_CTLA_3STOP		(0x04000000)
-
-#define	NETARM_SER_CTLA_5BITS		(0x00000000)
-#define	NETARM_SER_CTLA_6BITS		(0x01000000)
-#define	NETARM_SER_CTLA_7BITS		(0x02000000)
-#define	NETARM_SER_CTLA_8BITS		(0x03000000)
-
-#define	NETARM_SER_CTLA_CTSTX		(0x00800000)
-#define	NETARM_SER_CTLA_RTSRX		(0x00400000)
-
-#define	NETARM_SER_CTLA_LOOP_REM	(0x00200000)
-#define	NETARM_SER_CTLA_LOOP_LOC	(0x00100000)
-
-#define	NETARM_SER_CTLA_GPIO2		(0x00080000)
-#define	NETARM_SER_CTLA_GPIO1		(0x00040000)
-
-#define	NETARM_SER_CTLA_DTR_EN		(0x00020000)
-#define	NETARM_SER_CTLA_RTS_EN		(0x00010000)
-
-#define	NETARM_SER_CTLA_IE_RX_BRK	(0x00008000)
-#define	NETARM_SER_CTLA_IE_RX_FRMERR	(0x00004000)
-#define	NETARM_SER_CTLA_IE_RX_PARERR	(0x00002000)
-#define	NETARM_SER_CTLA_IE_RX_OVERRUN	(0x00001000)
-#define	NETARM_SER_CTLA_IE_RX_RDY	(0x00000800)
-#define	NETARM_SER_CTLA_IE_RX_HALF	(0x00000400)
-#define	NETARM_SER_CTLA_IE_RX_FULL	(0x00000200)
-#define	NETARM_SER_CTLA_IE_RX_DMAEN	(0x00000100)
-#define	NETARM_SER_CTLA_IE_RX_DCD	(0x00000080)
-#define	NETARM_SER_CTLA_IE_RX_RI	(0x00000040)
-#define	NETARM_SER_CTLA_IE_RX_DSR	(0x00000020)
-
-#define NETARM_SER_CTLA_IE_RX_ALL	(NETARM_SER_CTLA_IE_RX_BRK \
-					|NETARM_SER_CTLA_IE_RX_FRMERR \
-					|NETARM_SER_CTLA_IE_RX_PARERR \
-					|NETARM_SER_CTLA_IE_RX_OVERRUN \
-					|NETARM_SER_CTLA_IE_RX_RDY \
-					|NETARM_SER_CTLA_IE_RX_HALF \
-					|NETARM_SER_CTLA_IE_RX_FULL \
-					|NETARM_SER_CTLA_IE_RX_DMAEN \
-					|NETARM_SER_CTLA_IE_RX_DCD \
-					|NETARM_SER_CTLA_IE_RX_RI \
-					|NETARM_SER_CTLA_IE_RX_DSR)
-
-#define	NETARM_SER_CTLA_IE_TX_CTS	(0x00000010)
-#define	NETARM_SER_CTLA_IE_TX_EMPTY	(0x00000008)
-#define	NETARM_SER_CTLA_IE_TX_HALF	(0x00000004)
-#define	NETARM_SER_CTLA_IE_TX_FULL	(0x00000002)
-#define	NETARM_SER_CTLA_IE_TX_DMAEN	(0x00000001)
-
-#define NETARM_SER_CTLA_IE_TX_ALL	(NETARM_SER_CTLA_IE_TX_CTS \
-					|NETARM_SER_CTLA_IE_TX_EMPTY \
-					|NETARM_SER_CTLA_IE_TX_HALF \
-					|NETARM_SER_CTLA_IE_TX_FULL \
-					|NETARM_SER_CTLA_IE_TX_DMAEN)
-
-/* Control Register B */
-
-#define	NETARM_SER_CTLB_MATCH1_EN	(0x80000000)
-#define	NETARM_SER_CTLB_MATCH2_EN	(0x40000000)
-#define	NETARM_SER_CTLB_MATCH3_EN	(0x20000000)
-#define	NETARM_SER_CTLB_MATCH4_EN	(0x10000000)
-
-#define	NETARM_SER_CTLB_RBGT_EN		(0x08000000)
-#define	NETARM_SER_CTLB_RCGT_EN		(0x04000000)
-
-#define	NETARM_SER_CTLB_UART_MODE	(0x00000000)
-#define	NETARM_SER_CTLB_HDLC_MODE	(0x00100000)
-#define	NETARM_SER_CTLB_SPI_MAS_MODE	(0x00200000)
-#define	NETARM_SER_CTLB_SPI_SLV_MODE	(0x00300000)
-
-#define	NETARM_SER_CTLB_REV_BIT_ORDER	(0x00080000)
-
-#define	NETARM_SER_CTLB_MAM1		(0x00040000)
-#define	NETARM_SER_CTLB_MAM2		(0x00020000)
-
-/* Status Register A */
-
-#define	NETARM_SER_STATA_MATCH1		(0x80000000)
-#define	NETARM_SER_STATA_MATCH2		(0x40000000)
-#define	NETARM_SER_STATA_MATCH3		(0x20000000)
-#define	NETARM_SER_STATA_MATCH4		(0x10000000)
-
-#define	NETARM_SER_STATA_BGAP		(0x80000000)
-#define	NETARM_SER_STATA_CGAP		(0x40000000)
-
-#define	NETARM_SER_STATA_RX_1B		(0x00100000)
-#define	NETARM_SER_STATA_RX_2B		(0x00200000)
-#define	NETARM_SER_STATA_RX_3B		(0x00300000)
-#define	NETARM_SER_STATA_RX_4B		(0x00000000)
-
-/* downshifted values */
-
-#define	NETARM_SER_STATA_RXFDB_1BYTES	(0x001)
-#define	NETARM_SER_STATA_RXFDB_2BYTES	(0x002)
-#define	NETARM_SER_STATA_RXFDB_3BYTES	(0x003)
-#define	NETARM_SER_STATA_RXFDB_4BYTES	(0x000)
-
-#define	NETARM_SER_STATA_RXFDB_MASK	(0x00300000)
-#define	NETARM_SER_STATA_RXFDB(x)	(((x) & NETARM_SER_STATA_RXFDB_MASK) \
-					 >> 20)
-
-#define	NETARM_SER_STATA_DCD		(0x00080000)
-#define	NETARM_SER_STATA_RI		(0x00040000)
-#define	NETARM_SER_STATA_DSR		(0x00020000)
-#define	NETARM_SER_STATA_CTS		(0x00010000)
-
-#define	NETARM_SER_STATA_RX_BRK		(0x00008000)
-#define	NETARM_SER_STATA_RX_FRMERR	(0x00004000)
-#define	NETARM_SER_STATA_RX_PARERR	(0x00002000)
-#define	NETARM_SER_STATA_RX_OVERRUN	(0x00001000)
-#define	NETARM_SER_STATA_RX_RDY		(0x00000800)
-#define	NETARM_SER_STATA_RX_HALF	(0x00000400)
-#define	NETARM_SER_STATA_RX_CLOSED	(0x00000200)
-#define	NETARM_SER_STATA_RX_FULL	(0x00000100)
-#define	NETARM_SER_STATA_RX_DCD		(0x00000080)
-#define	NETARM_SER_STATA_RX_RI		(0x00000040)
-#define	NETARM_SER_STATA_RX_DSR		(0x00000020)
-
-#define	NETARM_SER_STATA_TX_CTS		(0x00000010)
-#define	NETARM_SER_STATA_TX_RDY		(0x00000008)
-#define	NETARM_SER_STATA_TX_HALF	(0x00000004)
-#define	NETARM_SER_STATA_TX_FULL	(0x00000002)
-#define	NETARM_SER_STATA_TX_DMAEN	(0x00000001)
-
-/* you have to clear all receive signals to get the fifo to move forward */
-#define NETARM_SER_STATA_CLR_ALL	(NETARM_SER_STATA_RX_BRK | \
-					 NETARM_SER_STATA_RX_FRMERR | \
-					 NETARM_SER_STATA_RX_PARERR | \
-					 NETARM_SER_STATA_RX_OVERRUN | \
-					 NETARM_SER_STATA_RX_HALF | \
-					 NETARM_SER_STATA_RX_CLOSED | \
-					 NETARM_SER_STATA_RX_FULL | \
-					 NETARM_SER_STATA_RX_DCD | \
-					 NETARM_SER_STATA_RX_RI | \
-					 NETARM_SER_STATA_RX_DSR | \
-					 NETARM_SER_STATA_TX_CTS )
-
-/* Bit Rate Registers */
-
-#define	NETARM_SER_BR_EN		(0x80000000)
-#define	NETARM_SER_BR_TMODE		(0x40000000)
-
-#define	NETARM_SER_BR_RX_CLK_INT	(0x00000000)
-#define	NETARM_SER_BR_RX_CLK_EXT	(0x20000000)
-#define	NETARM_SER_BR_TX_CLK_INT	(0x00000000)
-#define	NETARM_SER_BR_TX_CLK_EXT	(0x10000000)
-
-#define	NETARM_SER_BR_RX_CLK_DRV	(0x08000000)
-#define	NETARM_SER_BR_TX_CLK_DRV	(0x04000000)
-
-#define	NETARM_SER_BR_CLK_EXT_5		(0x00000000)
-#define	NETARM_SER_BR_CLK_SYSTEM	(0x01000000)
-#define	NETARM_SER_BR_CLK_OUT1A		(0x02000000)
-#define	NETARM_SER_BR_CLK_OUT2A		(0x03000000)
-
-#define	NETARM_SER_BR_TX_CLK_INV	(0x00800000)
-#define	NETARM_SER_BR_RX_CLK_INV	(0x00400000)
-
-/* complete settings assuming system clock input is 18MHz */
-
-#define	NETARM_SER_BR_MASK		(0x000007FF)
-
-/* bit rate determined from equation Fbr = Fxtal / [ 10 * ( N + 1 ) ] */
-/* from section 7.5.4 of HW Ref Guide */
-
-/* #ifdef CONFIG_NETARM_PLL_BYPASS */
-#define	NETARM_SER_BR_X16(x)	( NETARM_SER_BR_EN |			\
-				  NETARM_SER_BR_RX_CLK_INT |		\
-				  NETARM_SER_BR_TX_CLK_INT |		\
-				  NETARM_SER_BR_CLK_EXT_5 |		\
-				  ( ( ( ( NETARM_XTAL_FREQ /		\
-				          ( x * 10 ) ) - 1 ) /	16 ) &	\
-				    NETARM_SER_BR_MASK ) )
-/*
-#else
-#define	NETARM_SER_BR_X16(x)	( NETARM_SER_BR_EN |			\
-				  NETARM_SER_BR_RX_CLK_INT |		\
-				  NETARM_SER_BR_TX_CLK_INT |		\
-				  NETARM_SER_BR_CLK_SYSTEM |		\
-				  ( ( ( ( NETARM_PLLED_SYSCLK_FREQ /		\
-				          ( x * 2 ) ) - 1 ) /	16 ) &	\
-				    NETARM_SER_BR_MASK ) )
-#endif
-*/
-
-/* Receive Buffer Gap Timer */
-
-#define	NETARM_SER_RX_GAP_TIMER_EN	(0x80000000)
-#define	NETARM_SER_RX_GAP_MASK		(0x00003FFF)
-
-/* rx gap is a function of bit rate x */
-
-/* #ifdef CONFIG_NETARM_PLL_BYPASS */
-#define	NETARM_SER_RXGAP(x)	( NETARM_SER_RX_GAP_TIMER_EN |		\
-				  ( ( ( ( 10 * NETARM_XTAL_FREQ ) /	\
-				        ( x * 5 * 512 ) ) - 1 ) &	\
-			              NETARM_SER_RX_GAP_MASK ) )
-/*
-#else
-#define	NETARM_SER_RXGAP(x)	( NETARM_SER_RX_GAP_TIMER_EN |			\
-				  ( ( ( ( 2 * NETARM_PLLED_SYSCLK_FREQ ) /	\
-				        ( x * 512 ) ) - 1 ) &			\
-			              NETARM_SER_RX_GAP_MASK ) )
-#endif
-*/
-
-#if 0
-#define	NETARM_SER_RXGAP(x)	( NETARM_SER_RX_GAP_TIMER_EN |		\
-				  ( ( ( ( 2 * NETARM_PLLED_SYSCLK_FREQ ) /	\
-				        ( x * 5 * 512 ) ) - 1 ) &	\
-			              NETARM_SER_RX_GAP_MASK ) )
-#define	NETARM_SER_RXGAP(x)	( NETARM_SER_RX_GAP_TIMER_EN |		\
-				  ( ( ( ( 10 * NETARM_XTAL_FREQ ) /	\
-				        ( x * 512 ) ) - 1 ) &	\
-			              NETARM_SER_RX_GAP_MASK ) )
-#endif
-
-#define MIN_BAUD_RATE        600
-#define MAX_BAUD_RATE     115200
-
-/* the default BAUD rate for the BOOTLOADER, there is a separate */
-/* setting in the serial driver <arch/armnommu/drivers/char/serial-netarm.h> */
-#define DEFAULT_BAUD_RATE 9600
-#define NETARM_SER_FIFO_SIZE 32
-#define MIN_GAP 0
-
-#endif
diff --git a/arch/arm/include/asm/arch-armada100/armada100.h b/arch/arm/include/asm/arch-armada100/armada100.h
deleted file mode 100644
index d5d125a..0000000
--- a/arch/arm/include/asm/arch-armada100/armada100.h
+++ /dev/null
@@ -1,121 +0,0 @@
-/*
- * (C) Copyright 2010
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
- * Contributor: Mahavir Jain <mjain@marvell.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-#ifndef _ASM_ARCH_ARMADA100_H
-#define _ASM_ARCH_ARMADA100_H
-
-#ifndef __ASSEMBLY__
-#include <asm/types.h>
-#include <asm/io.h>
-#endif	/* __ASSEMBLY__ */
-
-#if defined (CONFIG_ARMADA100)
-#include <asm/arch/cpu.h>
-
-/* Common APB clock register bit definitions */
-#define APBC_APBCLK     (1<<0)  /* APB Bus Clock Enable */
-#define APBC_FNCLK      (1<<1)  /* Functional Clock Enable */
-#define APBC_RST        (1<<2)  /* Reset Generation */
-/* Functional Clock Selection Mask */
-#define APBC_FNCLKSEL(x)        (((x) & 0xf) << 4)
-
-/* Register Base Addresses */
-#define ARMD1_DRAM_BASE		0xB0000000
-#define ARMD1_TIMER_BASE	0xD4014000
-#define ARMD1_APBC1_BASE	0xD4015000
-#define ARMD1_APBC2_BASE	0xD4015800
-#define ARMD1_UART1_BASE	0xD4017000
-#define ARMD1_UART2_BASE	0xD4018000
-#define ARMD1_GPIO_BASE		0xD4019000
-#define ARMD1_SSP1_BASE		0xD401B000
-#define ARMD1_SSP2_BASE		0xD401C000
-#define ARMD1_MFPR_BASE		0xD401E000
-#define ARMD1_SSP3_BASE		0xD401F000
-#define ARMD1_SSP4_BASE		0xD4020000
-#define ARMD1_SSP5_BASE		0xD4021000
-#define ARMD1_UART3_BASE	0xD4026000
-#define ARMD1_MPMU_BASE		0xD4050000
-#define ARMD1_APMU_BASE		0xD4282800
-#define ARMD1_CPU_BASE		0xD4282C00
-
-/*
- * Main Power Management (MPMU) Registers
- * Refer Datasheet Appendix A.8
- */
-struct armd1mpmu_registers {
-	u8 pad0[0x08 - 0x00];
-	u32 fccr;	/*0x0008*/
-	u32 pocr;	/*0x000c*/
-	u32 posr;	/*0x0010*/
-	u32 succr;	/*0x0014*/
-	u8 pad1[0x030 - 0x014 - 4];
-	u32 gpcr;	/*0x0030*/
-	u8 pad2[0x200 - 0x030 - 4];
-	u32 wdtpcr;	/*0x0200*/
-	u8 pad3[0x1000 - 0x200 - 4];
-	u32 apcr;	/*0x1000*/
-	u32 apsr;	/*0x1004*/
-	u8 pad4[0x1020 - 0x1004 - 4];
-	u32 aprr;	/*0x1020*/
-	u32 acgr;	/*0x1024*/
-	u32 arsr;	/*0x1028*/
-};
-
-/*
- * APB1 Clock Reset/Control Registers
- * Refer Datasheet Appendix A.10
- */
-struct armd1apb1_registers {
-	u32 uart1;	/*0x000*/
-	u32 uart2;	/*0x004*/
-	u32 gpio;	/*0x008*/
-	u32 pwm1;	/*0x00c*/
-	u32 pwm2;	/*0x010*/
-	u32 pwm3;	/*0x014*/
-	u32 pwm4;	/*0x018*/
-	u8 pad0[0x028 - 0x018 - 4];
-	u32 rtc;	/*0x028*/
-	u32 twsi0;	/*0x02c*/
-	u32 kpc;	/*0x030*/
-	u32 timers;	/*0x034*/
-	u8 pad1[0x03c - 0x034 - 4];
-	u32 aib;	/*0x03c*/
-	u32 sw_jtag;	/*0x040*/
-	u32 timer1;	/*0x044*/
-	u32 onewire;	/*0x048*/
-	u8 pad2[0x050 - 0x048 - 4];
-	u32 asfar;	/*0x050 AIB Secure First Access Reg*/
-	u32 assar;	/*0x054 AIB Secure Second Access Reg*/
-	u8 pad3[0x06c - 0x054 - 4];
-	u32 twsi1;	/*0x06c*/
-	u32 uart3;	/*0x070*/
-	u8 pad4[0x07c - 0x070 - 4];
-	u32 timer2;	/*0x07C*/
-	u8 pad5[0x084 - 0x07c - 4];
-	u32 ac97;	/*0x084*/
-};
-
-#endif /* CONFIG_ARMADA100 */
-#endif /* _ASM_ARCH_ARMADA100_H */
diff --git a/arch/arm/include/asm/arch-armada100/config.h b/arch/arm/include/asm/arch-armada100/config.h
deleted file mode 100644
index d804002..0000000
--- a/arch/arm/include/asm/arch-armada100/config.h
+++ /dev/null
@@ -1,44 +0,0 @@
-/*
- * (C) Copyright 2011
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Lei Wen <leiwen@marvell.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-/*
- * This file should be included in board config header file.
- *
- * It supports common definitions for Armada100 platform
- */
-
-#ifndef _ARMD1_CONFIG_H
-#define _ARMD1_CONFIG_H
-
-#define CONFIG_ARM926EJS	1	/* Basic Architecture */
-
-#define CONFIG_SYS_TCLK		(14745600)	/* NS16550 clk config */
-#define CONFIG_SYS_HZ_CLOCK	(3250000)	/* Timer Freq. 3.25MHZ */
-#define CONFIG_MARVELL_MFP			/* Enable mvmfp driver */
-#define MV_MFPR_BASE		ARMD1_MFPR_BASE
-#define MV_UART_CONSOLE_BASE	ARMD1_UART1_BASE
-#define CONFIG_SYS_NS16550_IER	(1 << 6)	/* Bit 6 in UART_IER register
-						represents UART Unit Enable */
-
-#endif /* _ARMD1_CONFIG_H */
diff --git a/arch/arm/include/asm/arch-armada100/cpu.h b/arch/arm/include/asm/arch-armada100/cpu.h
deleted file mode 100644
index 0518a6a..0000000
--- a/arch/arm/include/asm/arch-armada100/cpu.h
+++ /dev/null
@@ -1,53 +0,0 @@
-/*
- * (C) Copyright 2010
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Prafulla Wadaskar <prafulla@marvell.com>, Contributor: Mahavir Jain <mjain@marvell.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-#ifndef _ARMADA100CPU_H
-#define _ARMADA100CPU_H
-
-#include <asm/io.h>
-#include <asm/system.h>
-
-/*
- * CPU Interface Registers
- * Refer Datasheet Appendix A.2
- */
-struct armd1cpu_registers {
-	u32 chip_id;		/* Chip Id Reg */
-	u32 pad;
-	u32 cpu_conf;		/* CPU Conf Reg */
-	u32 pad1;
-	u32 cpu_sram_spd;	/* CPU SRAM Speed Reg */
-	u32 pad2;
-	u32 cpu_l2c_spd;	/* CPU L2cache Speed Conf */
-	u32 mcb_conf;		/* MCB Conf Reg */
-	u32 sys_boot_ctl;	/* Sytem Boot Control */
-};
-
-/*
- * Functions
- */
-u32 armd1_sdram_base(int);
-u32 armd1_sdram_size(int);
-
-#endif /* _ARMADA100CPU_H */
diff --git a/arch/arm/include/asm/arch-armada100/mfp.h b/arch/arm/include/asm/arch-armada100/mfp.h
deleted file mode 100644
index d21a79f..0000000
--- a/arch/arm/include/asm/arch-armada100/mfp.h
+++ /dev/null
@@ -1,67 +0,0 @@
-/*
- * Based on linux/arch/arm/mach-mpp/include/mfp-pxa168.h
- * (C) Copyright 2007
- * Marvell Semiconductor <www.marvell.com>
- * 2007-08-21: eric miao <eric.miao@marvell.com>
- *
- * (C) Copyright 2010
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
- * Contributor: Mahavir Jain <mjain@marvell.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-#ifndef __ARMADA100_MFP_H
-#define __ARMADA100_MFP_H
-
-/*
- * Frequently used MFP Configuration macros for all ARMADA100 family of SoCs
- *
- * 				    offset, pull,pF, drv,dF, edge,eF ,afn,aF
- */
-/* UART1 */
-#define MFP107_UART1_TXD	MFP_REG(0x01ac) | MFP_AF1 | MFP_DRIVE_FAST
-#define MFP107_UART1_RXD	MFP_REG(0x01ac) | MFP_AF2 | MFP_DRIVE_FAST
-#define MFP108_UART1_RXD	MFP_REG(0x01b0) | MFP_AF1 | MFP_DRIVE_FAST
-#define MFP108_UART1_TXD	MFP_REG(0x01b0) | MFP_AF2 | MFP_DRIVE_FAST
-#define MFP109_UART1_CTS	MFP_REG(0x01b4) | MFP_AF1 | MFP_DRIVE_MEDIUM
-#define MFP109_UART1_RTS	MFP_REG(0x01b4) | MFP_AF2 | MFP_DRIVE_MEDIUM
-#define MFP110_UART1_RTS	MFP_REG(0x01b8) | MFP_AF1 | MFP_DRIVE_MEDIUM
-#define MFP110_UART1_CTS	MFP_REG(0x01b8) | MFP_AF2 | MFP_DRIVE_MEDIUM
-#define MFP111_UART1_RI		MFP_REG(0x01bc) | MFP_AF1 | MFP_DRIVE_MEDIUM
-#define MFP111_UART1_DSR	MFP_REG(0x01bc) | MFP_AF2 | MFP_DRIVE_MEDIUM
-#define MFP112_UART1_DTR	MFP_REG(0x01c0) | MFP_AF1 | MFP_DRIVE_MEDIUM
-#define MFP112_UART1_DCD	MFP_REG(0x01c0) | MFP_AF2 | MFP_DRIVE_MEDIUM
-
-/* UART2 */
-#define MFP47_UART2_RXD		MFP_REG(0x0028) | MFP_AF6 | MFP_DRIVE_MEDIUM
-#define MFP48_UART2_TXD		MFP_REG(0x002c) | MFP_AF6 | MFP_DRIVE_MEDIUM
-#define MFP88_UART2_RXD		MFP_REG(0x0160) | MFP_AF2 | MFP_DRIVE_MEDIUM
-#define MFP89_UART2_TXD		MFP_REG(0x0164) | MFP_AF2 | MFP_DRIVE_MEDIUM
-
-/* UART3 */
-#define MFPO8_UART3_RXD		MFP_REG(0x06c) | MFP_AF2 | MFP_DRIVE_MEDIUM
-#define MFPO9_UART3_TXD		MFP_REG(0x070) | MFP_AF2 | MFP_DRIVE_MEDIUM
-
-/* More macros can be defined here... */
-
-#define MFP_PIN_MAX	117
-
-#endif /* __ARMADA100_MFP_H */
diff --git a/arch/arm/include/asm/arch-armv7/sysctrl.h b/arch/arm/include/asm/arch-armv7/sysctrl.h
deleted file mode 100644
index 4e45167..0000000
--- a/arch/arm/include/asm/arch-armv7/sysctrl.h
+++ /dev/null
@@ -1,70 +0,0 @@
-/*
- * (C) Copyright 2010 Linaro
- * Matt Waddel, <matt.waddel@linaro.org>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-#ifndef _SYSCTRL_H_
-#define _SYSCTRL_H_
-
-/* System controller (SP810) register definitions */
-#define SP810_TIMER0_ENSEL	(1 << 15)
-#define SP810_TIMER1_ENSEL	(1 << 17)
-#define SP810_TIMER2_ENSEL	(1 << 19)
-#define SP810_TIMER3_ENSEL	(1 << 21)
-
-struct sysctrl {
-	u32 scctrl;		/* 0x000 */
-	u32 scsysstat;
-	u32 scimctrl;
-	u32 scimstat;
-	u32 scxtalctrl;
-	u32 scpllctrl;
-	u32 scpllfctrl;
-	u32 scperctrl0;
-	u32 scperctrl1;
-	u32 scperen;
-	u32 scperdis;
-	u32 scperclken;
-	u32 scperstat;
-	u32 res1[0x006];
-	u32 scflashctrl;	/* 0x04c */
-	u32 res2[0x3a4];
-	u32 scsysid0;		/* 0xee0 */
-	u32 scsysid1;
-	u32 scsysid2;
-	u32 scsysid3;
-	u32 scitcr;
-	u32 scitir0;
-	u32 scitir1;
-	u32 scitor;
-	u32 sccntctrl;
-	u32 sccntdata;
-	u32 sccntstep;
-	u32 res3[0x32];
-	u32 scperiphid0;	/* 0xfe0 */
-	u32 scperiphid1;
-	u32 scperiphid2;
-	u32 scperiphid3;
-	u32 scpcellid0;
-	u32 scpcellid1;
-	u32 scpcellid2;
-	u32 scpcellid3;
-};
-#endif /* _SYSCTRL_H_ */
diff --git a/arch/arm/include/asm/arch-armv7/systimer.h b/arch/arm/include/asm/arch-armv7/systimer.h
deleted file mode 100644
index e745e37..0000000
--- a/arch/arm/include/asm/arch-armv7/systimer.h
+++ /dev/null
@@ -1,50 +0,0 @@
-/*
- * (C) Copyright 2010 Linaro
- * Matt Waddel, <matt.waddel@linaro.org>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-#ifndef _SYSTIMER_H_
-#define _SYSTIMER_H_
-
-/* AMBA timer register base address */
-#define SYSTIMER_BASE		0x10011000
-
-#define SYSHZ_CLOCK		1000000		/* Timers -> 1Mhz */
-#define SYSTIMER_RELOAD		0xFFFFFFFF
-#define SYSTIMER_EN		(1 << 7)
-#define SYSTIMER_32BIT		(1 << 1)
-
-struct systimer {
-	u32 timer0load;		/* 0x00 */
-	u32 timer0value;
-	u32 timer0control;
-	u32 timer0intclr;
-	u32 timer0ris;
-	u32 timer0mis;
-	u32 timer0bgload;
-	u32 timer1load;		/* 0x20 */
-	u32 timer1value;
-	u32 timer1control;
-	u32 timer1intclr;
-	u32 timer1ris;
-	u32 timer1mis;
-	u32 timer1bgload;
-};
-#endif /* _SYSTIMER_H_ */
diff --git a/arch/arm/include/asm/arch-armv7/wdt.h b/arch/arm/include/asm/arch-armv7/wdt.h
deleted file mode 100644
index ee74c38..0000000
--- a/arch/arm/include/asm/arch-armv7/wdt.h
+++ /dev/null
@@ -1,55 +0,0 @@
-/*
- * (C) Copyright 2010
- * Matt Waddel, <matt.waddel@linaro.org>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-#ifndef _WDT_H_
-#define _WDT_H_
-
-/* Watchdog timer (SP805) register base address */
-#define WDT_BASE	0x100E5000
-
-#define WDT_EN		0x2
-#define WDT_RESET_LOAD	0x0
-
-struct wdt {
-	u32 wdogload;		/* 0x000 */
-	u32 wdogvalue;
-	u32 wdogcontrol;
-	u32 wdogintclr;
-	u32 wdogris;
-	u32 wdogmis;
-	u32 res1[0x2F9];
-	u32 wdoglock;		/* 0xC00 */
-	u32 res2[0xBE];
-	u32 wdogitcr;		/* 0xF00 */
-	u32 wdogitop;
-	u32 res3[0x35];
-	u32 wdogperiphid0;	/* 0xFE0 */
-	u32 wdogperiphid1;
-	u32 wdogperiphid2;
-	u32 wdogperiphid3;
-	u32 wdogpcellid0;
-	u32 wdogpcellid1;
-	u32 wdogpcellid2;
-	u32 wdogpcellid3;
-};
-
-#endif /* _WDT_H_ */
diff --git a/arch/arm/include/asm/arch-at91/at91_common.h b/arch/arm/include/asm/arch-at91/at91_common.h
deleted file mode 100644
index 0067190..0000000
--- a/arch/arm/include/asm/arch-at91/at91_common.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
- * (C) Copyright 2007-2008
- * Stelian Pop <stelian.pop@leadtechdesign.com>
- * Lead Tech Design <www.leadtechdesign.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef AT91_COMMON_H
-#define AT91_COMMON_H
-
-void at91_can_hw_init(void);
-void at91_macb_hw_init(void);
-void at91_mci_hw_init(void);
-void at91_serial_hw_init(void);
-void at91_serial0_hw_init(void);
-void at91_serial1_hw_init(void);
-void at91_serial2_hw_init(void);
-void at91_serial3_hw_init(void);
-void at91_spi0_hw_init(unsigned long cs_mask);
-void at91_spi1_hw_init(unsigned long cs_mask);
-void at91_uhp_hw_init(void);
-
-#endif /* AT91_COMMON_H */
diff --git a/arch/arm/include/asm/arch-at91/at91_dbu.h b/arch/arm/include/asm/arch-at91/at91_dbu.h
deleted file mode 100644
index 3429293..0000000
--- a/arch/arm/include/asm/arch-at91/at91_dbu.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/*
- * Copyright (C) 2010
- * Reinhard Meyer, reinhard.meyer@emk-elektronik.de
- *
- * Debug Unit
- * Based on AT91SAM9XE datasheet
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#ifndef AT91_DBU_H
-#define AT91_DBU_H
-
-#ifndef __ASSEMBLY__
-
-typedef struct at91_dbu {
-	u32	cr;	/* Control Register WO */
-	u32	mr;	/* Mode Register  RW */
-	u32	ier;	/* Interrupt Enable Register WO */
-	u32	idr;	/* Interrupt Disable Register WO */
-	u32	imr;	/* Interrupt Mask Register RO */
-	u32	sr;	/* Status Register RO */
-	u32	rhr;	/* Receive Holding Register RO */
-	u32	thr;	/* Transmit Holding Register WO */
-	u32	brgr;	/* Baud Rate Generator Register RW */
-	u32	res1[7];/* 0x0024 - 0x003C Reserved */
-	u32	cidr;	/* Chip ID Register RO */
-	u32	exid;	/* Chip ID Extension Register RO */
-	u32	fnr;	/* Force NTRST Register RW */
-} at91_dbu_t;
-
-#endif /* __ASSEMBLY__ */
-
-#define AT91_DBU_CID_ARCH_MASK		0x0ff00000
-#define AT91_DBU_CID_ARCH_9xx		0x01900000
-#define AT91_DBU_CID_ARCH_9XExx	0x02900000
-
-#endif
diff --git a/arch/arm/include/asm/arch-at91/at91_eefc.h b/arch/arm/include/asm/arch-at91/at91_eefc.h
deleted file mode 100644
index d45b3de..0000000
--- a/arch/arm/include/asm/arch-at91/at91_eefc.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * Copyright (C) 2010
- * Reinhard Meyer, reinhard.meyer@emk-elektronik.de
- *
- * Enhanced Embedded Flash Controller
- * Based on AT91SAM9XE datasheet
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#ifndef AT91_EEFC_H
-#define AT91_EEFC_H
-
-#ifndef __ASSEMBLY__
-
-typedef struct at91_eefc {
-	u32	fmr;	/* Flash Mode Register RW */
-	u32	fcr;	/* Flash Command Register WO */
-	u32	fsr;	/* Flash Status Register RO */
-	u32	frr;	/* Flash Result Register RO */
-} at91_eefc_t;
-
-#endif /* __ASSEMBLY__ */
-
-#define AT91_EEFC_FMR_FWS_MASK	0x00000f00
-#define AT91_EEFC_FMR_FRDY_BIT	0x00000001
-
-#define AT91_EEFC_FCR_KEY		0x5a000000
-#define AT91_EEFC_FCR_FARG_MASK	0x00ffff00
-#define AT91_EEFC_FCR_FARG_SHIFT	8
-#define AT91_EEFC_FCR_FCMD_GETD	0x0
-#define AT91_EEFC_FCR_FCMD_WP		0x1
-#define AT91_EEFC_FCR_FCMD_WPL		0x2
-#define AT91_EEFC_FCR_FCMD_EWP		0x3
-#define AT91_EEFC_FCR_FCMD_EWPL	0x4
-#define AT91_EEFC_FCR_FCMD_EA		0x5
-#define AT91_EEFC_FCR_FCMD_SLB		0x8
-#define AT91_EEFC_FCR_FCMD_CLB		0x9
-#define AT91_EEFC_FCR_FCMD_GLB		0xA
-#define AT91_EEFC_FCR_FCMD_SGPB	0xB
-#define AT91_EEFC_FCR_FCMD_CGPB	0xC
-#define AT91_EEFC_FCR_FCMD_GGPB	0xD
-
-#define AT91_EEFC_FSR_FRDY	1
-#define AT91_EEFC_FSR_FCMDE	2
-#define AT91_EEFC_FSR_FLOCKE	4
-
-#endif
diff --git a/arch/arm/include/asm/arch-at91/at91_emac.h b/arch/arm/include/asm/arch-at91/at91_emac.h
deleted file mode 100644
index 0e2ff78..0000000
--- a/arch/arm/include/asm/arch-at91/at91_emac.h
+++ /dev/null
@@ -1,143 +0,0 @@
-/*
- * Copyright (C) 2009 Jens Scharsig (js_at_ng@scharsoft.de)
- *
- * based on AT91RM9200 datasheet revision I (36. Ethernet MAC (EMAC))
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef AT91_H
-#define AT91_H
-
-typedef struct at91_emac {
-	u32	 ctl;
-	u32	 cfg;
-	u32	 sr;
-	u32	 tar;
-	u32	 tcr;
-	u32	 tsr;
-	u32	 rbqp;
-	u32	 reserved0;
-	u32	 rsr;
-	u32	 isr;
-	u32	 ier;
-	u32	 idr;
-	u32	 imr;
-	u32	 man;
-	u32	 reserved1[2];
-	u32	 fra;
-	u32	 scol;
-	u32	 mocl;
-	u32	 ok;
-	u32	 seqe;
-	u32	 ale;
-	u32	 dte;
-	u32	 lcol;
-	u32	 ecol;
-	u32	 cse;
-	u32	 tue;
-	u32	 cde;
-	u32	 elr;
-	u32	 rjb;
-	u32	 usf;
-	u32	 sqee;
-	u32	 drfc;
-	u32	 reserved2[3];
-	u32	 hsh;
-	u32	 hsl;
-	u32	 sa1l;
-	u32	 sa1h;
-	u32	 sa2l;
-	u32	 sa2h;
-	u32	 sa3l;
-	u32	 sa3h;
-	u32	 sa4l;
-	u32	 sa4h;
-} at91_emac_t;
-
-#define AT91_EMAC_CTL_LB	0x0001
-#define AT91_EMAC_CTL_LBL	0x0002
-#define AT91_EMAC_CTL_RE	0x0004
-#define AT91_EMAC_CTL_TE	0x0008
-#define AT91_EMAC_CTL_MPE	0x0010
-#define AT91_EMAC_CTL_CSR	0x0020
-#define AT91_EMAC_CTL_ISR	0x0040
-#define AT91_EMAC_CTL_WES	0x0080
-#define AT91_EMAC_CTL_BP	0x1000
-
-#define AT91_EMAC_CFG_SPD	0x0001
-#define AT91_EMAC_CFG_FD	0x0002
-#define AT91_EMAC_CFG_BR	0x0004
-#define AT91_EMAC_CFG_CAF	0x0010
-#define AT91_EMAC_CFG_NBC	0x0020
-#define AT91_EMAC_CFG_MTI	0x0040
-#define AT91_EMAC_CFG_UNI	0x0080
-#define AT91_EMAC_CFG_BIG	0x0100
-#define AT91_EMAC_CFG_EAE	0x0200
-#define AT91_EMAC_CFG_CLK_MASK	0xFFFFF3FF
-#define AT91_EMAC_CFG_MCLK_8	0x0000
-#define AT91_EMAC_CFG_MCLK_16	0x0400
-#define AT91_EMAC_CFG_MCLK_32	0x0800
-#define AT91_EMAC_CFG_MCLK_64	0x0C00
-#define AT91_EMAC_CFG_RTY	0x1000
-#define AT91_EMAC_CFG_RMII	0x2000
-
-#define AT91_EMAC_SR_LINK	0x0001
-#define AT91_EMAC_SR_MDIO	0x0002
-#define AT91_EMAC_SR_IDLE	0x0004
-
-#define AT91_EMAC_TCR_LEN(x)	(x & 0x7FF)
-#define AT91_EMAC_TCR_NCRC	0x8000
-
-#define AT91_EMAC_TSR_OVR	0x0001
-#define AT91_EMAC_TSR_COL	0x0002
-#define AT91_EMAC_TSR_RLE	0x0004
-#define AT91_EMAC_TSR_TXIDLE	0x0008
-#define AT91_EMAC_TSR_BNQ	0x0010
-#define AT91_EMAC_TSR_COMP	0x0020
-#define AT91_EMAC_TSR_UND	0x0040
-
-#define AT91_EMAC_RSR_BNA	0x0001
-#define AT91_EMAC_RSR_REC	0x0002
-#define AT91_EMAC_RSR_OVR	0x0004
-
-/*  ISR, IER, IDR, IMR use the same bits */
-#define AT91_EMAC_IxR_DONE	0x0001
-#define AT91_EMAC_IxR_RCOM	0x0002
-#define AT91_EMAC_IxR_RBNA	0x0004
-#define AT91_EMAC_IxR_TOVR	0x0008
-#define AT91_EMAC_IxR_TUND	0x0010
-#define AT91_EMAC_IxR_RTRY	0x0020
-#define AT91_EMAC_IxR_TBRE	0x0040
-#define AT91_EMAC_IxR_TCOM	0x0080
-#define AT91_EMAC_IxR_TIDLE	0x0100
-#define AT91_EMAC_IxR_LINK	0x0200
-#define AT91_EMAC_IxR_ROVR	0x0400
-#define AT91_EMAC_IxR_HRESP	0x0800
-
-#define AT91_EMAC_MAN_DATA_MASK		0xFFFF
-#define AT91_EMAC_MAN_CODE_802_3	0x00020000
-#define AT91_EMAC_MAN_REGA(reg)		((reg & 0x1F) << 18)
-#define AT91_EMAC_MAN_PHYA(phy)		((phy & 0x1F) << 23)
-#define AT91_EMAC_MAN_RW_R		0x20000000
-#define AT91_EMAC_MAN_RW_W		0x10000000
-#define AT91_EMAC_MAN_HIGH		0x40000000
-#define AT91_EMAC_MAN_LOW		0x80000000
-
-#endif
diff --git a/arch/arm/include/asm/arch-at91/at91_gpbr.h b/arch/arm/include/asm/arch-at91/at91_gpbr.h
deleted file mode 100644
index cf1d790..0000000
--- a/arch/arm/include/asm/arch-at91/at91_gpbr.h
+++ /dev/null
@@ -1,45 +0,0 @@
-/*
- * Copyright (C) 2010
- * Reinhard Meyer, reinhard.meyer@emk-elektronik.de
- *
- * General Purpose Backup Registers
- * Based on AT91SAM9XE datasheet
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#ifndef AT91_GPBR_H
-#define AT91_GPBR_H
-
-/*
- * The Atmel AT91SAM9 series has a small resource of 4 nonvolatile
- * 32 Bit registers (buffered by the Vbu power).
- *
- * Please consider carefully before using this resource for tasks
- * that do not really need nonvolatile registers. Maybe you can
- * store information in EEPROM or FLASH instead.
- *
- * However, if you use a GPBR please document its use here and
- * reference the define in your code!
- *
- * known typical uses of the GPBRs:
- * GPBR[0]: offset for RTT timekeeping (u-boot, kernel)
- * GPBR[1]: unused
- * GPBR[2]: unused
- * GPBR[3]: bootcount (u-boot)
- */
-#define AT91_GPBR_INDEX_TIMEOFF 0
-#define AT91_GPBR_INDEX_BOOTCOUNT 3
-
-#ifndef __ASSEMBLY__
-
-typedef struct at91_gpbr {
-	u32 reg[4];
-} at91_gpbr_t;
-
-#endif /* __ASSEMBLY__ */
-
-#endif
diff --git a/arch/arm/include/asm/arch-at91/at91_matrix.h b/arch/arm/include/asm/arch-at91/at91_matrix.h
deleted file mode 100644
index f99b1d4..0000000
--- a/arch/arm/include/asm/arch-at91/at91_matrix.h
+++ /dev/null
@@ -1,254 +0,0 @@
-/*
- * Copyright (C) 2009 Jens Scharsig (js_at_ng@scharsoft.de)
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef AT91_MATRIX_H
-#define AT91_MATRIX_H
-
-#ifdef __ASSEMBLY__
-
-#if defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9G20)
-#define AT91_ASM_MATRIX_CSA0	(AT91_MATRIX_BASE + 0x11C)
-#elif defined(CONFIG_AT91SAM9261)
-#define AT91_ASM_MATRIX_CSA0	(AT91_MATRIX_BASE + 0x30)
-#elif defined(CONFIG_AT91SAM9263)
-#define AT91_ASM_MATRIX_CSA0	(AT91_MATRIX_BASE + 0x120)
-#elif defined(CONFIG_AT91SAM9G45)
-#define AT91_ASM_MATRIX_CSA0	(AT91_MATRIX_BASE + 0x128)
-#else
-#error AT91_ASM_MATRIX_CSA0 is not definied for current CPU
-#endif
-
-#define AT91_ASM_MATRIX_MCFG	AT91_MATRIX_BASE
-
-#else
-#if defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9G20)
-#define AT91_MATRIX_MASTERS	6
-#define AT91_MATRIX_SLAVES	5
-#elif defined(CONFIG_AT91SAM9261)
-#define AT91_MATRIX_MASTERS	1
-#define AT91_MATRIX_SLAVES	5
-#elif defined(CONFIG_AT91SAM9263)
-#define AT91_MATRIX_MASTERS	9
-#define AT91_MATRIX_SLAVES	7
-#elif defined(CONFIG_AT91SAM9G45)
-#define AT91_MATRIX_MASTERS	11
-#define AT91_MATRIX_SLAVES	8
-#else
-#error CPU not supported. Please update at91_matrix.h
-#endif
-
-typedef struct at91_priority {
-	u32	a;
-	u32	b;
-} at91_priority_t;
-
-typedef struct at91_matrix {
-	u32		mcfg[AT91_MATRIX_MASTERS];
-#if defined(CONFIG_AT91SAM9261)
-	u32		scfg[AT91_MATRIX_SLAVES];
-	u32		res61_1[3];
-	u32		tcr;
-	u32		res61_2[2];
-	u32		csa;
-	u32		pucr;
-	u32		res61_3[114];
-#else
-	u32		reserve1[16 - AT91_MATRIX_MASTERS];
-	u32		scfg[AT91_MATRIX_SLAVES];
-	u32		reserve2[16 - AT91_MATRIX_SLAVES];
-	at91_priority_t	pr[AT91_MATRIX_SLAVES];
-	u32		reserve3[32 - (2 * AT91_MATRIX_SLAVES)];
-	u32		mrcr;		/* 0x100 Master Remap Control */
-	u32		reserve4[3];
-#if	defined(CONFIG_AT91SAM9G45)
-	u32		ccr[52];	/* 0x110 - 0x1E0 Chip Configuration */
-	u32		womr;		/* 0x1E4 Write Protect Mode  */
-	u32		wpsr;		/* 0x1E8 Write Protect Status */
-	u32		resg45_1[10];
-#elif defined(CONFIG_AT91SAM9260)  || defined(CONFIG_AT91SAM9G20)
-	u32		res60_1[3];
-	u32		csa;
-	u32		res60_2[56];
-#elif defined(CONFIG_AT91SAM9263)
-	u32		res63_1;
-	u32		tcmr;
-	u32		res63_2[2];
-	u32		csa[2];
-	u32		res63_3[54];
-#else
-	u32		reserve5[60];
-#endif
-#endif
-} at91_matrix_t;
-
-#endif /* __ASSEMBLY__ */
-
-#define AT91_MATRIX_CSA_DBPUC		0x00000100
-#define AT91_MATRIX_CSA_VDDIOMSEL_1_8V	0x00000000
-#define AT91_MATRIX_CSA_VDDIOMSEL_3_3V	0x00010000
-
-#define AT91_MATRIX_CSA_EBI_CS1A	0x00000002
-#define AT91_MATRIX_CSA_EBI_CS3A	0x00000008
-#define AT91_MATRIX_CSA_EBI_CS4A	0x00000010
-#define AT91_MATRIX_CSA_EBI_CS5A	0x00000020
-
-#define AT91_MATRIX_CSA_EBI1_CS2A	0x00000008
-
-#if defined CONFIG_AT91SAM9261
-/* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
-#define	AT91_MATRIX_MCFG_RCB0	(1 << 0)
-/* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
-#define	AT91_MATRIX_MCFG_RCB1	(1 << 1)
-#endif
-
-/* Undefined Length Burst Type */
-#if defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9263) || \
-	defined(CONFIG_AT91SAM9G45)
-#define AT91_MATRIX_MCFG_ULBT_INFINITE	0x00000000
-#define AT91_MATRIX_MCFG_ULBT_SINGLE	0x00000001
-#define AT91_MATRIX_MCFG_ULBT_FOUR	0x00000002
-#define AT91_MATRIX_MCFG_ULBT_EIGHT	0x00000003
-#define AT91_MATRIX_MCFG_ULBT_SIXTEEN	0x00000004
-#endif
-#if defined(CONFIG_AT91SAM9G45)
-#define AT91_MATRIX_MCFG_ULBT_THIRTYTWO	0x00000005
-#define AT91_MATRIX_MCFG_ULBT_SIXTYFOUR	0x00000006
-#define AT91_MATRIX_MCFG_ULBT_128	0x00000007
-#endif
-
-/* Default Master Type */
-#define AT91_MATRIX_SCFG_DEFMSTR_TYPE_NONE	0x00000000
-#define AT91_MATRIX_SCFG_DEFMSTR_TYPE_LAST	0x00010000
-#define AT91_MATRIX_SCFG_DEFMSTR_TYPE_FIXED	0x00020000
-
-/* Fixed Index of Default Master */
-#if defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9263)
-#define	AT91_MATRIX_SCFG_FIXED_DEFMSTR(x)	((x & 0xf) << 18)
-#elif defined(CONFIG_AT91SAM9261) || defined(CONFIG_AT91SAM9260)
-#define	AT91_MATRIX_SCFG_FIXED_DEFMSTR(x)	((x & 7) << 18)
-#endif
-
-/* Maximum Number of Allowed Cycles for a Burst */
-#if defined(CONFIG_AT91SAM9G45)
-#define	AT91_MATRIX_SCFG_SLOT_CYCLE(x)	((x & 0x1ff) << 0)
-#elif defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9261) || \
-	defined(CONFIG_AT91SAM9263)
-#define	AT91_MATRIX_SCFG_SLOT_CYCLE(x)	((x & 0xff) << 0)
-#endif
-
-/* Arbitration Type */
-#if defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9263)
-#define	AT91_MATRIX_SCFG_ARBT_ROUND_ROBIN	0x00000000
-#define	AT91_MATRIX_SCFG_ARBT_FIXED_PRIORITY	0x01000000
-#endif
-
-/* Master Remap Control Register */
-#if defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9263) || \
-	defined(CONFIG_AT91SAM9G45)
-/* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
-#define	AT91_MATRIX_MRCR_RCB0	(1 << 0)
-/* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
-#define	AT91_MATRIX_MRCR_RCB1	(1 << 1)
-#endif
-#if defined(CONFIG_AT91SAM9263) || defined(CONFIG_AT91SAM9G45)
-#define	AT91_MATRIX_MRCR_RCB2	0x00000004
-#define	AT91_MATRIX_MRCR_RCB3	0x00000008
-#define	AT91_MATRIX_MRCR_RCB4	0x00000010
-#define	AT91_MATRIX_MRCR_RCB5	0x00000020
-#define	AT91_MATRIX_MRCR_RCB6	0x00000040
-#define	AT91_MATRIX_MRCR_RCB7	0x00000080
-#define	AT91_MATRIX_MRCR_RCB8	0x00000100
-#endif
-#if defined(CONFIG_AT91SAM9G45)
-#define	AT91_MATRIX_MRCR_RCB9	0x00000200
-#define	AT91_MATRIX_MRCR_RCB10	0x00000400
-#define	AT91_MATRIX_MRCR_RCB11	0x00000800
-#endif
-
-/* TCM Configuration Register */
-#if defined(CONFIG_AT91SAM9G45)
-/* Size of ITCM enabled memory block */
-#define	AT91_MATRIX_TCMR_ITCM_0		0x00000000
-#define	AT91_MATRIX_TCMR_ITCM_32	0x00000040
-/* Size of DTCM enabled memory block */
-#define	AT91_MATRIX_TCMR_DTCM_0		0x00000000
-#define	AT91_MATRIX_TCMR_DTCM_32	0x00000060
-#define	AT91_MATRIX_TCMR_DTCM_64	0x00000070
-/* Wait state TCM register */
-#define	AT91_MATRIX_TCMR_TCM_NO_WS	0x00000000
-#define	AT91_MATRIX_TCMR_TCM_ONE_WS	0x00000800
-#endif
-#if defined(CONFIG_AT91SAM9263)
-/* Size of ITCM enabled memory block */
-#define	AT91_MATRIX_TCMR_ITCM_0		0x00000000
-#define	AT91_MATRIX_TCMR_ITCM_16	0x00000005
-#define	AT91_MATRIX_TCMR_ITCM_32	0x00000006
-/* Size of DTCM enabled memory block */
-#define	AT91_MATRIX_TCMR_DTCM_0		0x00000000
-#define	AT91_MATRIX_TCMR_DTCM_16	0x00000050
-#define	AT91_MATRIX_TCMR_DTCM_32	0x00000060
-#endif
-#if defined(CONFIG_AT91SAM9261)
-/* Size of ITCM enabled memory block */
-#define	AT91_MATRIX_TCMR_ITCM_0		0x00000000
-#define	AT91_MATRIX_TCMR_ITCM_16	0x00000005
-#define	AT91_MATRIX_TCMR_ITCM_32	0x00000006
-#define	AT91_MATRIX_TCMR_ITCM_64	0x00000007
-/* Size of DTCM enabled memory block */
-#define	AT91_MATRIX_TCMR_DTCM_0		0x00000000
-#define	AT91_MATRIX_TCMR_DTCM_16	0x00000050
-#define	AT91_MATRIX_TCMR_DTCM_32	0x00000060
-#define	AT91_MATRIX_TCMR_DTCM_64	0x00000070
-#endif
-
-#if defined(CONFIG_AT91SAM9G45)
-/* Video Mode Configuration Register */
-#define	AT91C_MATRIX_VDEC_SEL_OFF	0x00000000
-#define	AT91C_MATRIX_VDEC_SEL_ON	0x00000001
-/* Write Protect Mode Register */
-#define	AT91_MATRIX_WPMR_WP_WPDIS	0x00000000
-#define	AT91_MATRIX_WPMR_WP_WPEN	0x00000001
-#define	AT91_MATRIX_WPMR_WPKEY		0xFFFFFF00	/* Write Protect KEY */
-/* Write Protect Status Register */
-#define	AT91_MATRIX_WPSR_NO_WPV		0x00000000
-#define	AT91_MATRIX_WPSR_WPV		0x00000001
-#define	AT91_MATRIX_WPSR_WPVSRC		0x00FFFF00	/* Write Protect Violation Source */
-#endif
-
-/* USB Pad Pull-Up Control Register */
-#if defined(CONFIG_AT91SAM9261)
-#define	AT91_MATRIX_USBPUCR_PUON	0x40000000
-#endif
-
-#define AT91_MATRIX_PRA_M0(x)	((x & 3) << 0)	/* Master 0 Priority Reg. A*/
-#define AT91_MATRIX_PRA_M1(x)	((x & 3) << 4)	/* Master 1 Priority Reg. A*/
-#define AT91_MATRIX_PRA_M2(x)	((x & 3) << 8)	/* Master 2 Priority Reg. A*/
-#define AT91_MATRIX_PRA_M3(x)	((x & 3) << 12)	/* Master 3 Priority Reg. A*/
-#define AT91_MATRIX_PRA_M4(x)	((x & 3) << 16)	/* Master 4 Priority Reg. A*/
-#define AT91_MATRIX_PRA_M5(x)	((x & 3) << 20)	/* Master 5 Priority Reg. A*/
-#define AT91_MATRIX_PRA_M6(x)	((x & 3) << 24)	/* Master 6 Priority Reg. A*/
-#define AT91_MATRIX_PRA_M7(x)	((x & 3) << 28)	/* Master 7 Priority Reg. A*/
-#define AT91_MATRIX_PRB_M8(x)	((x & 3) << 0)	/* Master 8 Priority Reg. B) */
-#define AT91_MATRIX_PRB_M9(x)	((x & 3) << 4)	/* Master 9 Priority Reg. B) */
-#define AT91_MATRIX_PRB_M10(x)	((x & 3) << 8)	/* Master 10 Priority Reg. B) */
-
-#endif
diff --git a/arch/arm/include/asm/arch-at91/at91_mc.h b/arch/arm/include/asm/arch-at91/at91_mc.h
deleted file mode 100644
index acfbd10..0000000
--- a/arch/arm/include/asm/arch-at91/at91_mc.h
+++ /dev/null
@@ -1,97 +0,0 @@
-/*
- * Copyright (C) 2009 Jens Scharsig (js_at_ng@scharsoft.de)
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef AT91_MC_H
-#define AT91_MC_H
-
-#define AT91_ASM_MC_EBI_CSA	(AT91_MC_BASE + 0x60)
-#define AT91_ASM_MC_EBI_CFG	(AT91_MC_BASE + 0x64)
-#define AT91_ASM_MC_SMC_CSR0	(AT91_MC_BASE + 0x70)
-#define AT91_ASM_MC_SDRAMC_MR	(AT91_MC_BASE + 0x90)
-#define AT91_ASM_MC_SDRAMC_TR	(AT91_MC_BASE + 0x94)
-#define AT91_ASM_MC_SDRAMC_CR	(AT91_MC_BASE + 0x98)
-
-#ifndef __ASSEMBLY__
-
-typedef struct at91_ebi {
-	u32 	csa;		/* 0x00 Chip Select Assignment Register */
-	u32	cfgr;		/* 0x04 Configuration Register */
-	u32	reserved[2];
-} __attribute__ ((packed)) at91_ebi_t;
-
-#define AT91_EBI_CSA_CS0A	0x0001
-#define AT91_EBI_CSA_CS1A	0x0002
-
-#define AT91_EBI_CSA_CS3A	0x0008
-#define AT91_EBI_CSA_CS4A	0x0010
-
-typedef struct at91_sdramc {
-	u32	mr; 	/* 0x00 SDRAMC Mode Register */
-	u32	tr; 	/* 0x04 SDRAMC Refresh Timer Register */
-	u32	cr; 	/* 0x08 SDRAMC Configuration Register */
-	u32	ssr; 	/* 0x0C SDRAMC Self Refresh Register */
-	u32	lpr; 	/* 0x10 SDRAMC Low Power Register */
-	u32	ier; 	/* 0x14 SDRAMC Interrupt Enable Register */
-	u32	idr; 	/* 0x18 SDRAMC Interrupt Disable Register */
-	u32	imr; 	/* 0x1C SDRAMC Interrupt Mask Register */
-	u32	icr; 	/* 0x20 SDRAMC Interrupt Status Register */
-	u32	reserved[3];
-} __attribute__ ((packed)) at91_sdramc_t;
-
-typedef struct at91_smc {
-	u32	csr[8]; 	/* 0x00 SDRAMC Mode Register */
-} __attribute__ ((packed)) at91_smc_t;
-
-#define AT91_SMC_CSR_RWHOLD(x)		((x & 0x7) << 28)
-#define AT91_SMC_CSR_RWSETUP(x)		((x & 0x7) << 24)
-#define AT91_SMC_CSR_ACSS_STANDARD	0x00000000
-#define AT91_SMC_CSR_ACSS_1CYCLE	0x00010000
-#define AT91_SMC_CSR_ACSS_2CYCLE	0x00020000
-#define AT91_SMC_CSR_ACSS_3CYCLE	0x00030000
-#define AT91_SMC_CSR_DRP		0x00008000
-#define AT91_SMC_CSR_DBW_8		0x00004000
-#define AT91_SMC_CSR_DBW_16		0x00002000
-#define AT91_SMC_CSR_BAT_8		0x00000000
-#define AT91_SMC_CSR_BAT_16		0x00001000
-#define AT91_SMC_CSR_TDF(x)		((x & 0xF) << 8)
-#define AT91_SMC_CSR_WSEN		0x00000080
-#define AT91_SMC_CSR_NWS(x)		(x & 0x7F)
-
-typedef struct at91_bfc {
-	u32	mr; 	/* 0x00 SDRAMC Mode Register */
-} __attribute__ ((packed)) at91_bfc_t;
-
-typedef struct at91_mc {
-	u32		rcr;		/* 0x00 MC Remap Control Register */
-	u32		asr;		/* 0x04 MC Abort Status Register */
-	u32		aasr;		/* 0x08 MC Abort Address Status Reg */
-	u32		mpr;		/* 0x0C MC Master Priority Register */
-	u32		reserved1[20];	/* 0x10-0x5C */
-	at91_ebi_t	ebi;		/* 0x60	- 0x6C EBI */
-	at91_smc_t	smc;		/* 0x70 - 0x8C SMC User Interface */
-	at91_sdramc_t	sdramc;		/* 0x90 - 0xBC SDRAMC User Interface */
-	at91_bfc_t	bfc;		/* 0xC0 BFC User Interface */
-	u32		reserved2[15];
-} __attribute__ ((packed)) at91_mc_t;
-
-#endif
-#endif
diff --git a/arch/arm/include/asm/arch-at91/at91_pdc.h b/arch/arm/include/asm/arch-at91/at91_pdc.h
deleted file mode 100644
index 42f87ca..0000000
--- a/arch/arm/include/asm/arch-at91/at91_pdc.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- * Copyright (C) 2009 Jens Scharsig (js_at_ng@scharsoft.de)
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef AT91_PDC_H
-#define AT91_PDC_H
-
-typedef struct at91_pdc {
-	u32	rpr;		/* 0x100 Receive Pointer Register */
-	u32	rcr;		/* 0x104 Receive Counter Register */
-	u32	tpr;		/* 0x108 Transmit Pointer Register */
-	u32	tcr;		/* 0x10C Transmit Counter Register */
-	u32	pnpr;		/* 0x110 Receive Next Pointer Register */
-	u32	pncr;		/* 0x114 Receive Next Counter Register */
-	u32	tnpr;		/* 0x118 Transmit Next Pointer Register */
-	u32	tncr;		/* 0x11C Transmit Next Counter Register */
-	u32	ptcr;		/* 0x120 Transfer Control Register */
-	u32	ptsr;		/* 0x124 Transfer Status Register */
-} at91_pdc_t;
-
-#endif
diff --git a/arch/arm/include/asm/arch-at91/at91_pio.h b/arch/arm/include/asm/arch-at91/at91_pio.h
deleted file mode 100644
index f7915a3..0000000
--- a/arch/arm/include/asm/arch-at91/at91_pio.h
+++ /dev/null
@@ -1,160 +0,0 @@
-/*
- * [origin: Linux kernel include/asm-arm/arch-at91/at91_pio.h]
- *
- * Copyright (C) 2005 Ivan Kokshaysky
- * Copyright (C) SAN People
- * Copyright (C) 2009 Jens Scharsig (js_at_ng@scharsoft.de)
- *
- * Parallel I/O Controller (PIO) - System peripherals registers.
- * Based on AT91RM9200 datasheet revision E.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#ifndef AT91_PIO_H
-#define AT91_PIO_H
-
-
-#define AT91_ASM_PIO_RANGE	0x200
-#define AT91_ASM_PIOC_ASR	\
-	(AT91_PIO_BASE + AT91_PIO_PORTC * AT91_ASM_PIO_RANGE + 0x70)
-#define AT91_ASM_PIOC_BSR	\
-	(AT91_PIO_BASE + AT91_PIO_PORTC * AT91_ASM_PIO_RANGE + 0x74)
-#define AT91_ASM_PIOC_PDR	\
-	(AT91_PIO_BASE + AT91_PIO_PORTC * AT91_ASM_PIO_RANGE + 0x04)
-#define AT91_ASM_PIOC_PUDR	\
-	(AT91_PIO_BASE + AT91_PIO_PORTC * AT91_ASM_PIO_RANGE + 0x60)
-
-#define AT91_ASM_PIOD_PDR	\
-	(AT91_PIO_BASE + AT91_PIO_PORTD * AT91_ASM_PIO_RANGE + 0x04)
-#define AT91_ASM_PIOD_PUDR	\
-	(AT91_PIO_BASE + AT91_PIO_PORTD * AT91_ASM_PIO_RANGE + 0x60)
-#define AT91_ASM_PIOD_ASR	\
-	(AT91_PIO_BASE + AT91_PIO_PORTD * AT91_ASM_PIO_RANGE + 0x70)
-
-#ifndef __ASSEMBLY__
-
-typedef struct at91_port {
-	u32	per;		/* 0x00 PIO Enable Register */
-	u32	pdr;		/* 0x04 PIO Disable Register */
-	u32	psr;		/* 0x08 PIO Status Register */
-	u32	reserved0;
-	u32	oer;		/* 0x10 Output Enable Register */
-	u32	odr;		/* 0x14 Output Disable Registerr */
-	u32	osr;		/* 0x18 Output Status Register */
-	u32	reserved1;
-	u32	ifer;		/* 0x20 Input Filter Enable Register */
-	u32	ifdr;		/* 0x24 Input Filter Disable Register */
-	u32	ifsr;		/* 0x28 Input Filter Status Register */
-	u32	reserved2;
-	u32	sodr;		/* 0x30 Set Output Data Register */
-	u32	codr;		/* 0x34 Clear Output Data Register */
-	u32	odsr;		/* 0x38 Output Data Status Register */
-	u32	pdsr;		/* 0x3C Pin Data Status Register */
-	u32	ier;		/* 0x40 Interrupt Enable Register */
-	u32	idr;		/* 0x44 Interrupt Disable Register */
-	u32	imr;		/* 0x48 Interrupt Mask Register */
-	u32	isr;		/* 0x4C Interrupt Status Register */
-	u32	mder;		/* 0x50 Multi-driver Enable Register */
-	u32	mddr;		/* 0x54 Multi-driver Disable Register */
-	u32	mdsr;		/* 0x58 Multi-driver Status Register */
-	u32	reserved3;
-	u32	pudr;		/* 0x60 Pull-up Disable Register */
-	u32	puer;		/* 0x64 Pull-up Enable Register */
-	u32	pusr;		/* 0x68 Pad Pull-up Status Register */
-	u32	reserved4;
-	u32	asr;		/* 0x70 Select A Register */
-	u32	bsr;		/* 0x74 Select B Register */
-	u32	absr;		/* 0x78 AB Select Status Register */
-	u32	reserved5[9];	/*  */
-	u32	ower;		/* 0xA0 Output Write Enable Register */
-	u32	owdr;		/* 0xA4 Output Write Disable Register */
-	u32	owsr;		/* OxA8 utput Write Status Register */
-	u32	reserved6[85];
-} at91_port_t;
-
-#if defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9261) || \
-	defined(CONFIG_AT91SAM9G10) || defined(CONFIG_AT91SAM9G20)
-#define AT91_PIO_PORTS	3
-#elif defined(CONFIG_AT91SAM9263) || defined(CONFIG_AT91SAM9G45) || \
-	defined(CONFIG_AT91SAM9M10G45)
-#define AT91_PIO_PORTS	5
-#elif defined(CONFIG_AT91RM9200) || defined(CONFIG_AT91CAP9) || \
-	defined(CONFIG_AT91SAM9RL)
-#define AT91_PIO_PORTS	4
-#else
-#error "Unsupported cpu. Please update at91_pio.h"
-#endif
-
-typedef union at91_pio {
-	struct {
-		at91_port_t	pioa;
-		at91_port_t	piob;
-		at91_port_t	pioc;
-	#if (AT91_PIO_PORTS > 3)
-		at91_port_t	piod;
-	#endif
-	#if (AT91_PIO_PORTS > 4)
-		at91_port_t	pioe;
-	#endif
-	} ;
-	at91_port_t port[AT91_PIO_PORTS];
-} at91_pio_t;
-
-#ifdef CONFIG_AT91_GPIO
-int at91_set_a_periph(unsigned port, unsigned pin, int use_pullup);
-int at91_set_b_periph(unsigned port, unsigned pin, int use_pullup);
-int at91_set_pio_input(unsigned port, unsigned pin, int use_pullup);
-int at91_set_pio_multi_drive(unsigned port, unsigned pin, int is_on);
-int at91_set_pio_output(unsigned port, unsigned pin, int value);
-int at91_set_pio_periph(unsigned port, unsigned pin, int use_pullup);
-int at91_set_pio_pullup(unsigned port, unsigned pin, int use_pullup);
-int at91_set_pio_deglitch(unsigned port, unsigned pin, int is_on);
-int at91_set_pio_value(unsigned port, unsigned pin, int value);
-int at91_get_pio_value(unsigned port, unsigned pin);
-#endif
-#endif
-
-#define	AT91_PIO_PORTA		0x0
-#define	AT91_PIO_PORTB		0x1
-#define	AT91_PIO_PORTC		0x2
-#define	AT91_PIO_PORTD		0x3
-#define	AT91_PIO_PORTE		0x4
-
-#ifdef CONFIG_AT91_LEGACY
-
-#define PIO_PER		0x00	/* Enable Register */
-#define PIO_PDR		0x04	/* Disable Register */
-#define PIO_PSR		0x08	/* Status Register */
-#define PIO_OER		0x10	/* Output Enable Register */
-#define PIO_ODR		0x14	/* Output Disable Register */
-#define PIO_OSR		0x18	/* Output Status Register */
-#define PIO_IFER	0x20	/* Glitch Input Filter Enable */
-#define PIO_IFDR	0x24	/* Glitch Input Filter Disable */
-#define PIO_IFSR	0x28	/* Glitch Input Filter Status */
-#define PIO_SODR	0x30	/* Set Output Data Register */
-#define PIO_CODR	0x34	/* Clear Output Data Register */
-#define PIO_ODSR	0x38	/* Output Data Status Register */
-#define PIO_PDSR	0x3c	/* Pin Data Status Register */
-#define PIO_IER		0x40	/* Interrupt Enable Register */
-#define PIO_IDR		0x44	/* Interrupt Disable Register */
-#define PIO_IMR		0x48	/* Interrupt Mask Register */
-#define PIO_ISR		0x4c	/* Interrupt Status Register */
-#define PIO_MDER	0x50	/* Multi-driver Enable Register */
-#define PIO_MDDR	0x54	/* Multi-driver Disable Register */
-#define PIO_MDSR	0x58	/* Multi-driver Status Register */
-#define PIO_PUDR	0x60	/* Pull-up Disable Register */
-#define PIO_PUER	0x64	/* Pull-up Enable Register */
-#define PIO_PUSR	0x68	/* Pull-up Status Register */
-#define PIO_ASR		0x70	/* Peripheral A Select Register */
-#define PIO_BSR		0x74	/* Peripheral B Select Register */
-#define PIO_ABSR	0x78	/* AB Status Register */
-#define PIO_OWER	0xa0	/* Output Write Enable Register */
-#define PIO_OWDR	0xa4	/* Output Write Disable Register */
-#define PIO_OWSR	0xa8	/* Output Write Status Register */
-#endif
-
-#endif
diff --git a/arch/arm/include/asm/arch-at91/at91_pit.h b/arch/arm/include/asm/arch-at91/at91_pit.h
deleted file mode 100644
index 61aca79..0000000
--- a/arch/arm/include/asm/arch-at91/at91_pit.h
+++ /dev/null
@@ -1,47 +0,0 @@
-/*
- * [origin: Linux kernel include/asm-arm/arch-at91/at91_pit.h]
- *
- * Copyright (C) 2007 Andrew Victor
- * Copyright (C) 2007 Atmel Corporation.
- *
- * Periodic Interval Timer (PIT) - System peripherals regsters.
- * Based on AT91SAM9261 datasheet revision D.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#ifndef AT91_PIT_H
-#define AT91_PIT_H
-
-typedef struct at91_pit {
-	u32	mr;	/* 0x00 Mode Register */
-	u32	sr;	/* 0x04 Status Register */
-	u32	pivr;	/* 0x08 Periodic Interval Value Register */
-	u32	piir;	/* 0x0C Periodic Interval Image Register */
-} at91_pit_t;
-
-#define		AT91_PIT_MR_IEN		0x02000000
-#define		AT91_PIT_MR_EN		0x01000000
-#define		AT91_PIT_MR_PIV_MASK(x)	(x & 0x000fffff)
-#define		AT91_PIT_MR_PIV(x)	(x & AT91_PIT_MR_PIV_MASK)
-
-#ifdef CONFIG_AT91_LEGACY
-
-#define AT91_PIT_MR		(AT91_PIT + 0x00)	/* Mode Register */
-#define		AT91_PIT_PITIEN		(1 << 25)		/* Timer Interrupt Enable */
-#define		AT91_PIT_PITEN		(1 << 24)		/* Timer Enabled */
-#define		AT91_PIT_PIV		(0xfffff)		/* Periodic Interval Value */
-
-#define AT91_PIT_SR		(AT91_PIT + 0x04)	/* Status Register */
-#define		AT91_PIT_PITS		(1 << 0)		/* Timer Status */
-
-#define AT91_PIT_PIVR		(AT91_PIT + 0x08)	/* Periodic Interval Value Register */
-#define AT91_PIT_PIIR		(AT91_PIT + 0x0c)	/* Periodic Interval Image Register */
-#define		AT91_PIT_PICNT		(0xfff << 20)		/* Interval Counter */
-#define		AT91_PIT_CPIV		(0xfffff)		/* Inverval Value */
-
-#endif /* CONFIG_AT91_LEGACY */
-#endif
diff --git a/arch/arm/include/asm/arch-at91/at91_pmc.h b/arch/arm/include/asm/arch-at91/at91_pmc.h
deleted file mode 100644
index fb8bb17..0000000
--- a/arch/arm/include/asm/arch-at91/at91_pmc.h
+++ /dev/null
@@ -1,245 +0,0 @@
-/*
- * [origin: Linux kernel arch/arm/mach-at91/include/mach/at91_pmc.h]
- *
- * Copyright (C) 2005 Ivan Kokshaysky
- * Copyright (C) SAN People
- * Copyright (C) 2009 Jens Scharsig (js_at_ng@scharsoft.de)
- *
- * Power Management Controller (PMC) - System peripherals registers.
- * Based on AT91RM9200 datasheet revision E.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#ifndef AT91_PMC_H
-#define AT91_PMC_H
-
-#define	AT91_ASM_PMC_MOR	(AT91_PMC_BASE + 0x20)
-#define	AT91_ASM_PMC_PLLAR	(AT91_PMC_BASE + 0x28)
-#define	AT91_ASM_PMC_PLLBR	(AT91_PMC_BASE + 0x2c)
-#define AT91_ASM_PMC_MCKR	(AT91_PMC_BASE + 0x30)
-#define AT91_ASM_PMC_SR		(AT91_PMC_BASE + 0x68)
-
-#ifndef __ASSEMBLY__
-
-#include <asm/types.h>
-
-typedef struct at91_pmc {
-	u32	scer;		/* 0x00 System Clock Enable Register */
-	u32	scdr;		/* 0x04 System Clock Disable Register */
-	u32	scsr;		/* 0x08 System Clock Status Register */
-	u32	reserved0;
-	u32	pcer;		/* 0x10 Peripheral Clock Enable Register */
-	u32	pcdr;		/* 0x14 Peripheral Clock Disable Register */
-	u32	pcsr;		/* 0x18 Peripheral Clock Status Register */
-	u32	uckr;		/* 0x1C UTMI Clock Register */
-	u32	mor;		/* 0x20 Main Oscilator Register */
-	u32	mcfr;		/* 0x24 Main Clock Frequency Register */
-	u32	pllar;		/* 0x28 PLL A Register */
-	u32	pllbr;		/* 0x2C PLL B Register */
-	u32	mckr;		/* 0x30 Master Clock Register */
-	u32	reserved1;
-	u32	usb;		/* 0x38 USB Clock Register */
-	u32	reserved2;
-	u32	pck[4];		/* 0x40 Programmable Clock Register 0 - 3 */
-	u32	reserved3[4];
-	u32	ier;		/* 0x60 Interrupt Enable Register */
-	u32	idr;		/* 0x64 Interrupt Disable Register */
-	u32	sr;		/* 0x68 Status Register */
-	u32	imr;		/* 0x6C Interrupt Mask Register */
-	u32	reserved4[4];
-	u32	pllicpr;	/* 0x80 Change Pump Current Register (SAM9) */
-	u32	reserved5[21];
-	u32	wpmr;		/* 0xE4 Write Protect Mode Register (CAP0) */
-	u32	wpsr;		/* 0xE8 Write Protect Status Register (CAP0) */
-	u32	reserved8[5];
-} at91_pmc_t;
-
-#endif	/* end not assembly */
-
-#define AT91_PMC_MOR_MOSCEN		0x01
-#define AT91_PMC_MOR_OSCBYPASS		0x02
-#define AT91_PMC_MOR_OSCOUNT(x)		((x & 0xff) << 8)
-
-#define AT91_PMC_PLLXR_DIV(x)		(x & 0xFF)
-#define AT91_PMC_PLLXR_PLLCOUNT(x)	((x & 0x3F) << 8)
-#define AT91_PMC_PLLXR_OUT(x)		((x & 0x03) << 14)
-#define AT91_PMC_PLLXR_MUL(x)		((x & 0x7FF) << 16)
-#define AT91_PMC_PLLAR_29		0x20000000
-#define AT91_PMC_PLLBR_USBDIV_1		0x00000000
-#define AT91_PMC_PLLBR_USBDIV_2		0x10000000
-#define AT91_PMC_PLLBR_USBDIV_4		0x20000000
-
-#define AT91_PMC_MCFR_MAINRDY		0x00010000
-#define AT91_PMC_MCFR_MAINF_MASK	0x0000FFFF
-
-#define AT91_PMC_MCKR_CSS_SLOW		0x00000000
-#define AT91_PMC_MCKR_CSS_MAIN		0x00000001
-#define AT91_PMC_MCKR_CSS_PLLA		0x00000002
-#define AT91_PMC_MCKR_CSS_PLLB		0x00000003
-#define AT91_PMC_MCKR_CSS_MASK		0x00000003
-
-#define AT91_PMC_MCKR_PRES_1		0x00000000
-#define AT91_PMC_MCKR_PRES_2		0x00000004
-#define AT91_PMC_MCKR_PRES_4		0x00000008
-#define AT91_PMC_MCKR_PRES_8		0x0000000C
-#define AT91_PMC_MCKR_PRES_16		0x00000010
-#define AT91_PMC_MCKR_PRES_32		0x00000014
-#define AT91_PMC_MCKR_PRES_64		0x00000018
-#define AT91_PMC_MCKR_PRES_MASK		0x0000001C
-
-#ifdef CONFIG_AT91RM9200
-#define AT91_PMC_MCKR_MDIV_1		0x00000000
-#define AT91_PMC_MCKR_MDIV_2		0x00000100
-#define AT91_PMC_MCKR_MDIV_3		0x00000200
-#define AT91_PMC_MCKR_MDIV_4		0x00000300
-#define AT91_PMC_MCKR_MDIV_MASK		0x00000300
-#else
-#define AT91_PMC_MCKR_MDIV_1		0x00000000
-#define AT91_PMC_MCKR_MDIV_2		0x00000100
-#define AT91_PMC_MCKR_MDIV_4		0x00000200
-#define AT91_PMC_MCKR_MDIV_MASK		0x00000300
-#endif
-
-#define AT91_PMC_MCKR_PLLADIV_1		0x00001000
-#define AT91_PMC_MCKR_PLLADIV_2		0x00002000
-
-#define AT91_PMC_IXR_MOSCS		0x00000001
-#define AT91_PMC_IXR_LOCKA		0x00000002
-#define AT91_PMC_IXR_LOCKB		0x00000004
-#define AT91_PMC_IXR_MCKRDY		0x00000008
-#define AT91_PMC_IXR_LOCKU		0x00000040
-#define AT91_PMC_IXR_PCKRDY0		0x00000100
-#define AT91_PMC_IXR_PCKRDY1		0x00000200
-#define AT91_PMC_IXR_PCKRDY2		0x00000400
-#define AT91_PMC_IXR_PCKRDY3		0x00000800
-
-#ifdef CONFIG_AT91_LEGACY
-#define	AT91_PMC_SCER		(AT91_PMC + 0x00)	/* System Clock Enable Register */
-#define	AT91_PMC_SCDR		(AT91_PMC + 0x04)	/* System Clock Disable Register */
-
-#define	AT91_PMC_SCSR		(AT91_PMC + 0x08)	/* System Clock Status Register */
-#endif
-
-#define		AT91_PMC_PCK		(1 <<  0)		/* Processor Clock */
-#define		AT91RM9200_PMC_UDP	(1 <<  1)		/* USB Devcice Port Clock [AT91RM9200 only] */
-#define		AT91RM9200_PMC_MCKUDP	(1 <<  2)		/* USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only] */
-#define		AT91CAP9_PMC_DDR	(1 <<  2)		/* DDR Clock [AT91CAP9 revC only] */
-#define		AT91RM9200_PMC_UHP	(1 <<  4)		/* USB Host Port Clock [AT91RM9200 only] */
-#define		AT91SAM926x_PMC_UHP	(1 <<  6)		/* USB Host Port Clock [AT91SAM926x only] */
-#define		AT91CAP9_PMC_UHP	(1 <<  6)		/* USB Host Port Clock [AT91CAP9 only] */
-#define		AT91SAM926x_PMC_UDP	(1 <<  7)		/* USB Devcice Port Clock [AT91SAM926x only] */
-#define		AT91_PMC_PCK0		(1 <<  8)		/* Programmable Clock 0 */
-#define		AT91_PMC_PCK1		(1 <<  9)		/* Programmable Clock 1 */
-#define		AT91_PMC_PCK2		(1 << 10)		/* Programmable Clock 2 */
-#define		AT91_PMC_PCK3		(1 << 11)		/* Programmable Clock 3 */
-#define		AT91_PMC_HCK0		(1 << 16)		/* AHB Clock (USB host) [AT91SAM9261 only] */
-#define		AT91_PMC_HCK1		(1 << 17)		/* AHB Clock (LCD) [AT91SAM9261 only] */
-
-#ifdef CONFIG_AT91_LEGACY
-#define	AT91_PMC_PCER		(AT91_PMC + 0x10)	/* Peripheral Clock Enable Register */
-#define	AT91_PMC_PCDR		(AT91_PMC + 0x14)	/* Peripheral Clock Disable Register */
-#define	AT91_PMC_PCSR		(AT91_PMC + 0x18)	/* Peripheral Clock Status Register */
-
-#define	AT91_CKGR_UCKR		(AT91_PMC + 0x1C)	/* UTMI Clock Register [SAM9RL, CAP9] */
-#endif
-
-#define		AT91_PMC_UPLLEN		(1   << 16)		/* UTMI PLL Enable */
-#define		AT91_PMC_UPLLCOUNT	(0xf << 20)		/* UTMI PLL Start-up Time */
-#define		AT91_PMC_BIASEN		(1   << 24)		/* UTMI BIAS Enable */
-#define		AT91_PMC_BIASCOUNT	(0xf << 28)		/* UTMI PLL Start-up Time */
-
-#ifdef CONFIG_AT91_LEGACY
-#define	AT91_CKGR_MOR		(AT91_PMC + 0x20)	/* Main Oscillator Register [not on SAM9RL] */
-#endif
-#define		AT91_PMC_MOSCEN		(1    << 0)		/* Main Oscillator Enable */
-#define		AT91_PMC_OSCBYPASS	(1    << 1)		/* Oscillator Bypass [SAM9x, CAP9] */
-#define		AT91_PMC_OSCOUNT	(0xff << 8)		/* Main Oscillator Start-up Time */
-#ifdef CONFIG_AT91_LEGACY
-#define	AT91_CKGR_MCFR		(AT91_PMC + 0x24)	/* Main Clock Frequency Register */
-#endif
-#define		AT91_PMC_MAINF		(0xffff <<  0)		/* Main Clock Frequency */
-#define		AT91_PMC_MAINRDY	(1	<< 16)		/* Main Clock Ready */
-#ifdef CONFIG_AT91_LEGACY
-#define	AT91_CKGR_PLLAR		(AT91_PMC + 0x28)	/* PLL A Register */
-#define	AT91_CKGR_PLLBR		(AT91_PMC + 0x2c)	/* PLL B Register */
-#endif
-#define		AT91_PMC_DIV		(0xff  <<  0)		/* Divider */
-#define		AT91_PMC_PLLCOUNT	(0x3f  <<  8)		/* PLL Counter */
-#define		AT91_PMC_OUT		(3     << 14)		/* PLL Clock Frequency Range */
-#define		AT91_PMC_MUL		(0x7ff << 16)		/* PLL Multiplier */
-#define		AT91_PMC_USBDIV		(3     << 28)		/* USB Divisor (PLLB only) */
-#define			AT91_PMC_USBDIV_1		(0 << 28)
-#define			AT91_PMC_USBDIV_2		(1 << 28)
-#define			AT91_PMC_USBDIV_4		(2 << 28)
-#define		AT91_PMC_USB96M		(1     << 28)		/* Divider by 2 Enable (PLLB only) */
-#define		AT91_PMC_PLLA_WR_ERRATA	(1     << 29)		/* Bit 29 must always be set to 1 when programming the CKGR_PLLAR register */
-
-#ifdef CONFIG_AT91_LEGACY
-#define	AT91_PMC_MCKR		(AT91_PMC + 0x30)	/* Master Clock Register */
-#endif
-#define		AT91_PMC_CSS		(3 <<  0)		/* Master Clock Selection */
-#define			AT91_PMC_CSS_SLOW		(0 << 0)
-#define			AT91_PMC_CSS_MAIN		(1 << 0)
-#define			AT91_PMC_CSS_PLLA		(2 << 0)
-#define			AT91_PMC_CSS_PLLB		(3 << 0)
-#define		AT91_PMC_PRES		(7 <<  2)		/* Master Clock Prescaler */
-#define			AT91_PMC_PRES_1			(0 << 2)
-#define			AT91_PMC_PRES_2			(1 << 2)
-#define			AT91_PMC_PRES_4			(2 << 2)
-#define			AT91_PMC_PRES_8			(3 << 2)
-#define			AT91_PMC_PRES_16		(4 << 2)
-#define			AT91_PMC_PRES_32		(5 << 2)
-#define			AT91_PMC_PRES_64		(6 << 2)
-#define		AT91_PMC_MDIV		(3 <<  8)		/* Master Clock Division */
-#define			AT91RM9200_PMC_MDIV_1		(0 << 8)	/* [AT91RM9200 only] */
-#define			AT91RM9200_PMC_MDIV_2		(1 << 8)
-#define			AT91RM9200_PMC_MDIV_3		(2 << 8)
-#define			AT91RM9200_PMC_MDIV_4		(3 << 8)
-#define			AT91SAM9_PMC_MDIV_1		(0 << 8)	/* [SAM9,CAP9 only] */
-#define			AT91SAM9_PMC_MDIV_2		(1 << 8)
-#define			AT91SAM9_PMC_MDIV_4		(2 << 8)
-#define			AT91SAM9_PMC_MDIV_3		(3 << 8)	/* [some SAM9 only] */
-#define			AT91SAM9_PMC_MDIV_6		(3 << 8)
-#define		AT91_PMC_PDIV		(1 << 12)		/* Processor Clock Division [some SAM9 only] */
-#define			AT91_PMC_PDIV_1			(0 << 12)
-#define			AT91_PMC_PDIV_2			(1 << 12)
-
-#ifdef CONFIG_AT91_LEGACY
-#define		AT91_PMC_USB			(AT91_PMC + 0x38)	/* USB Clock Register */
-#endif
-#define		AT91_PMC_USBS_USB_PLLA		(0x0)		/* USB Clock Input is PLLA */
-#define		AT91_PMC_USBS_USB_UPLL		(0x1)		/* USB Clock Input is UPLL */
-#define		AT91_PMC_USBDIV_8		(0x7 <<  8)	/* USB Clock divided by 8 */
-#define		AT91_PMC_USBDIV_10		(0x9 <<  8)	/* USB Clock divided by 10 */
-
-#ifdef CONFIG_AT91_LEGACY
-#define	AT91_PMC_PCKR(n)	(AT91_PMC + 0x40 + ((n) * 4))	/* Programmable Clock 0-3 Registers */
-
-#define	AT91_PMC_IER		(AT91_PMC + 0x60)	/* Interrupt Enable Register */
-#define	AT91_PMC_IDR		(AT91_PMC + 0x64)	/* Interrupt Disable Register */
-#define	AT91_PMC_SR		(AT91_PMC + 0x68)	/* Status Register */
-#endif
-#define		AT91_PMC_MOSCS		(1 <<  0)		/* MOSCS Flag */
-#define		AT91_PMC_LOCKA		(1 <<  1)		/* PLLA Lock */
-#define		AT91_PMC_LOCKB		(1 <<  2)		/* PLLB Lock */
-#define		AT91_PMC_MCKRDY		(1 <<  3)		/* Master Clock */
-#define		AT91_PMC_LOCKU		(1 <<  6)		/* UPLL Lock [AT91CAP9 only] */
-#define		AT91_PMC_OSCSEL		(1 <<  7)		/* Slow Clock Oscillator [AT91CAP9 revC only] */
-#define		AT91_PMC_PCK0RDY	(1 <<  8)		/* Programmable Clock 0 */
-#define		AT91_PMC_PCK1RDY	(1 <<  9)		/* Programmable Clock 1 */
-#define		AT91_PMC_PCK2RDY	(1 << 10)		/* Programmable Clock 2 */
-#define		AT91_PMC_PCK3RDY	(1 << 11)		/* Programmable Clock 3 */
-#ifdef CONFIG_AT91_LEGACY
-#define	AT91_PMC_IMR		(AT91_PMC + 0x6c)	/* Interrupt Mask Register */
-
-#define AT91_PMC_PROT		(AT91_PMC + 0xe4)	/* Protect Register [AT91CAP9 revC only] */
-#endif
-#define		AT91_PMC_PROTKEY	0x504d4301	/* Activation Code */
-#ifdef CONFIG_AT91_LEGACY
-#define AT91_PMC_VER		(AT91_PMC + 0xfc)	/* PMC Module Version [AT91CAP9 only] */
-#endif /* CONFIG_AT91_LEGACY */
-#endif
diff --git a/arch/arm/include/asm/arch-at91/at91_rstc.h b/arch/arm/include/asm/arch-at91/at91_rstc.h
deleted file mode 100644
index 9ff2c5b..0000000
--- a/arch/arm/include/asm/arch-at91/at91_rstc.h
+++ /dev/null
@@ -1,69 +0,0 @@
-/*
- * [origin: Linux kernel include/asm-arm/arch-at91/at91_rstc.h]
- *
- * Copyright (C) 2007 Andrew Victor
- * Copyright (C) 2007 Atmel Corporation.
- *
- * Reset Controller (RSTC) - System peripherals regsters.
- * Based on AT91SAM9261 datasheet revision D.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#ifndef AT91_RSTC_H
-#define AT91_RSTC_H
-
-#define AT91_ASM_RSTC_MR	(AT91_RSTC_BASE + 0x08)
-
-#ifndef __ASSEMBLY__
-
-typedef struct at91_rstc {
-	u32	cr;	/* Reset Controller Control Register */
-	u32	sr;	/* Reset Controller Status Register */
-	u32	mr;	/* Reset Controller Mode Register */
-} at91_rstc_t;
-
-#endif /* __ASSEMBLY__ */
-
-#define AT91_RSTC_KEY		0xA5000000
-
-#define AT91_RSTC_CR_PROCRST	0x00000001
-#define AT91_RSTC_CR_PERRST	0x00000004
-#define AT91_RSTC_CR_EXTRST	0x00000008
-
-#define AT91_RSTC_MR_URSTEN	0x00000001
-#define AT91_RSTC_MR_URSTIEN	0x00000010
-#define AT91_RSTC_MR_ERSTL(x)	((x & 0xf) << 8)
-#define AT91_RSTC_MR_ERSTL_MASK	0x0000FF00
-
-#define AT91_RSTC_SR_NRSTL	0x00010000
-
-#ifdef CONFIG_AT91_LEGACY
-
-#define AT91_RSTC_CR		(AT91_RSTC + 0x00)	/* Reset Controller Control Register */
-#define		AT91_RSTC_PROCRST	(1 << 0)		/* Processor Reset */
-#define		AT91_RSTC_PERRST	(1 << 2)		/* Peripheral Reset */
-#define		AT91_RSTC_EXTRST	(1 << 3)		/* External Reset */
-
-#define AT91_RSTC_SR		(AT91_RSTC + 0x04)	/* Reset Controller Status Register */
-#define		AT91_RSTC_URSTS		(1 << 0)		/* User Reset Status */
-#define		AT91_RSTC_RSTTYP	(7 << 8)		/* Reset Type */
-#define			AT91_RSTC_RSTTYP_GENERAL	(0 << 8)
-#define			AT91_RSTC_RSTTYP_WAKEUP		(1 << 8)
-#define			AT91_RSTC_RSTTYP_WATCHDOG	(2 << 8)
-#define			AT91_RSTC_RSTTYP_SOFTWARE	(3 << 8)
-#define			AT91_RSTC_RSTTYP_USER	(4 << 8)
-#define		AT91_RSTC_NRSTL		(1 << 16)		/* NRST Pin Level */
-#define		AT91_RSTC_SRCMP		(1 << 17)		/* Software Reset Command in Progress */
-
-#define AT91_RSTC_MR		(AT91_RSTC + 0x08)	/* Reset Controller Mode Register */
-#define		AT91_RSTC_URSTEN	(1 << 0)		/* User Reset Enable */
-#define		AT91_RSTC_URSTIEN	(1 << 4)		/* User Reset Interrupt Enable */
-#define		AT91_RSTC_ERSTL		(0xf << 8)		/* External Reset Length */
-
-#endif /* CONFIG_AT91_LEGACY */
-
-#endif
diff --git a/arch/arm/include/asm/arch-at91/at91_rtt.h b/arch/arm/include/asm/arch-at91/at91_rtt.h
deleted file mode 100644
index e0253ef..0000000
--- a/arch/arm/include/asm/arch-at91/at91_rtt.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/*
- * Copyright (C) 2010
- * Reinhard Meyer, reinhard.meyer@emk-elektronik.de
- *
- * Real-time Timer
- * Based on AT91SAM9XE datasheet
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#ifndef AT91_RTT_H
-#define AT91_RTT_H
-
-#ifndef __ASSEMBLY__
-
-typedef struct at91_rtt {
-	u32	mr;	/* Mode Register   RW 0x00008000 */
-	u32	ar;	/* Alarm Register  RW 0xFFFFFFFF */
-	u32	vr;	/* Value Register  RO 0x00000000 */
-	u32	sr;	/* Status Register RO 0x00000000 */
-} at91_rtt_t;
-
-#endif /* __ASSEMBLY__ */
-
-#define AT91_RTT_MR_RTPRES	0x0000ffff
-#define AT91_RTT_MR_ALMIEN	0x00010000
-#define AT91_RTT_RTTINCIEN	0x00020000
-#define AT91_RTT_RTTRST	0x00040000
-
-#define AT91_RTT_SR_ALMS	0x00000001
-#define AT91_RTT_SR_RTTINC	0x00000002
-
-#endif
diff --git a/arch/arm/include/asm/arch-at91/at91_shdwn.h b/arch/arm/include/asm/arch-at91/at91_shdwn.h
deleted file mode 100644
index 874f988..0000000
--- a/arch/arm/include/asm/arch-at91/at91_shdwn.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- * Copyright (C) 2010
- * Reinhard Meyer, reinhard.meyer@emk-elektronik.de
- *
- * Shutdown Controller
- * Based on AT91SAM9XE datasheet
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#ifndef AT91_SHDWN_H
-#define AT91_SHDWN_H
-
-#ifndef __ASSEMBLY__
-
-struct at91_shdwn {
-	u32	cr;	/* Control Rer.    WO */
-	u32	mr;	/* Mode Register   RW 0x00000003 */
-	u32	sr;	/* Status Register RO 0x00000000 */
-};
-
-#endif /* __ASSEMBLY__ */
-
-#define AT91_SHDW_CR_KEY	0xa5000000
-#define AT91_SHDW_CR_SHDW	0x00000001
-
-#define AT91_SHDW_MR_RTTWKEN	0x00010000
-#define AT91_SHDW_MR_CPTWK0	0x000000f0
-#define AT91_SHDW_MR_WKMODE0H2L	0x00000002
-#define AT91_SHDW_MR_WKMODE0L2H	0x00000001
-
-#define AT91_SHDW_SR_RTTWK	0x00010000
-#define AT91_SHDW_SR_WAKEUP0	0x00000001
-
-#endif
diff --git a/arch/arm/include/asm/arch-at91/at91_spi.h b/arch/arm/include/asm/arch-at91/at91_spi.h
deleted file mode 100644
index c520e89..0000000
--- a/arch/arm/include/asm/arch-at91/at91_spi.h
+++ /dev/null
@@ -1,126 +0,0 @@
-/*
- * [origin: Linux kernel include/asm-arm/arch-at91/at91_spi.h]
- *
- * Copyright (C) 2005 Ivan Kokshaysky
- * Copyright (C) SAN People
- *
- * Serial Peripheral Interface (SPI) registers.
- * Based on AT91RM9200 datasheet revision E.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#ifndef AT91_SPI_H
-#define AT91_SPI_H
-
-#include <asm/arch/at91_pdc.h>
-
-typedef struct at91_spi {
-	u32		cr;		/* 0x00 Control Register */
-	u32		mr;		/* 0x04 Mode Register */
-	u32		rdr;		/* 0x08 Receive Data Register */
-	u32		tdr;		/* 0x0C Transmit Data Register */
-	u32		sr;		/* 0x10 Status Register */
-	u32		ier;		/* 0x14 Interrupt Enable Register */
-	u32		idr;		/* 0x18 Interrupt Disable Register */
-	u32		imr;		/* 0x1C Interrupt Mask Register */
-	u32		reserve1[4];
-	u32		csr[4];		/* 0x30 Chip Select Register 0-3 */
-	u32		reserve2[48];
-	at91_pdc_t	pdc;
-} at91_spi_t;
-
-#ifdef CONFIG_AT91_LEGACY
-
-#define AT91_SPI_CR			0x00		/* Control Register */
-#define		AT91_SPI_SPIEN		(1 <<  0)		/* SPI Enable */
-#define		AT91_SPI_SPIDIS		(1 <<  1)		/* SPI Disable */
-#define		AT91_SPI_SWRST		(1 <<  7)		/* SPI Software Reset */
-#define		AT91_SPI_LASTXFER	(1 << 24)		/* Last Transfer [SAM9261 only] */
-
-#define AT91_SPI_MR			0x04		/* Mode Register */
-#define		AT91_SPI_MSTR		(1    <<  0)		/* Master/Slave Mode */
-#define		AT91_SPI_PS		(1    <<  1)		/* Peripheral Select */
-#define			AT91_SPI_PS_FIXED	(0 << 1)
-#define			AT91_SPI_PS_VARIABLE	(1 << 1)
-#define		AT91_SPI_PCSDEC		(1    <<  2)		/* Chip Select Decode */
-#define		AT91_SPI_DIV32		(1    <<  3)		/* Clock Selection [AT91RM9200 only] */
-#define		AT91_SPI_MODFDIS	(1    <<  4)		/* Mode Fault Detection */
-#define		AT91_SPI_LLB		(1    <<  7)		/* Local Loopback Enable */
-#define		AT91_SPI_PCS		(0xf  << 16)		/* Peripheral Chip Select */
-#define		AT91_SPI_DLYBCS		(0xff << 24)		/* Delay Between Chip Selects */
-
-#define AT91_SPI_RDR		0x08			/* Receive Data Register */
-#define		AT91_SPI_RD		(0xffff <<  0)		/* Receive Data */
-#define		AT91_SPI_PCS		(0xf	<< 16)		/* Peripheral Chip Select */
-
-#define AT91_SPI_TDR		0x0c			/* Transmit Data Register */
-#define		AT91_SPI_TD		(0xffff <<  0)		/* Transmit Data */
-#define		AT91_SPI_PCS		(0xf	<< 16)		/* Peripheral Chip Select */
-#define		AT91_SPI_LASTXFER	(1	<< 24)		/* Last Transfer [SAM9261 only] */
-
-#define AT91_SPI_SR		0x10			/* Status Register */
-#define		AT91_SPI_RDRF		(1 <<  0)		/* Receive Data Register Full */
-#define		AT91_SPI_TDRE		(1 <<  1)		/* Transmit Data Register Full */
-#define		AT91_SPI_MODF		(1 <<  2)		/* Mode Fault Error */
-#define		AT91_SPI_OVRES		(1 <<  3)		/* Overrun Error Status */
-#define		AT91_SPI_ENDRX		(1 <<  4)		/* End of RX buffer */
-#define		AT91_SPI_ENDTX		(1 <<  5)		/* End of TX buffer */
-#define		AT91_SPI_RXBUFF		(1 <<  6)		/* RX Buffer Full */
-#define		AT91_SPI_TXBUFE		(1 <<  7)		/* TX Buffer Empty */
-#define		AT91_SPI_NSSR		(1 <<  8)		/* NSS Rising [SAM9261 only] */
-#define		AT91_SPI_TXEMPTY	(1 <<  9)		/* Transmission Register Empty [SAM9261 only] */
-#define		AT91_SPI_SPIENS		(1 << 16)		/* SPI Enable Status */
-
-#define AT91_SPI_IER		0x14			/* Interrupt Enable Register */
-#define AT91_SPI_IDR		0x18			/* Interrupt Disable Register */
-#define AT91_SPI_IMR		0x1c			/* Interrupt Mask Register */
-
-#define AT91_SPI_CSR(n)		(0x30 + ((n) * 4))	/* Chip Select Registers 0-3 */
-#define		AT91_SPI_CPOL		(1    <<  0)		/* Clock Polarity */
-#define		AT91_SPI_NCPHA		(1    <<  1)		/* Clock Phase */
-#define		AT91_SPI_CSAAT		(1    <<  3)		/* Chip Select Active After Transfer [SAM9261 only] */
-#define		AT91_SPI_BITS		(0xf  <<  4)		/* Bits Per Transfer */
-#define			AT91_SPI_BITS_8		(0 << 4)
-#define			AT91_SPI_BITS_9		(1 << 4)
-#define			AT91_SPI_BITS_10	(2 << 4)
-#define			AT91_SPI_BITS_11	(3 << 4)
-#define			AT91_SPI_BITS_12	(4 << 4)
-#define			AT91_SPI_BITS_13	(5 << 4)
-#define			AT91_SPI_BITS_14	(6 << 4)
-#define			AT91_SPI_BITS_15	(7 << 4)
-#define			AT91_SPI_BITS_16	(8 << 4)
-#define		AT91_SPI_SCBR		(0xff <<  8)		/* Serial Clock Baud Rate */
-#define		AT91_SPI_DLYBS		(0xff << 16)		/* Delay before SPCK */
-#define		AT91_SPI_DLYBCT		(0xff << 24)		/* Delay between Consecutive Transfers */
-
-#define AT91_SPI_RPR		0x0100			/* Receive Pointer Register */
-
-#define AT91_SPI_RCR		0x0104			/* Receive Counter Register */
-
-#define AT91_SPI_TPR		0x0108			/* Transmit Pointer Register */
-
-#define AT91_SPI_TCR		0x010c			/* Transmit Counter Register */
-
-#define AT91_SPI_RNPR		0x0110			/* Receive Next Pointer Register */
-
-#define AT91_SPI_RNCR		0x0114			/* Receive Next Counter Register */
-
-#define AT91_SPI_TNPR		0x0118			/* Transmit Next Pointer Register */
-
-#define AT91_SPI_TNCR		0x011c			/* Transmit Next Counter Register */
-
-#define AT91_SPI_PTCR		0x0120			/* PDC Transfer Control Register */
-#define		AT91_SPI_RXTEN		(0x1 << 0)		/* Receiver Transfer Enable */
-#define		AT91_SPI_RXTDIS		(0x1 << 1)		/* Receiver Transfer Disable */
-#define		AT91_SPI_TXTEN		(0x1 << 8)		/* Transmitter Transfer Enable */
-#define		AT91_SPI_TXTDIS		(0x1 << 9)		/* Transmitter Transfer Disable */
-
-#define AT91_SPI_PTSR		0x0124			/* PDC Transfer Status Register */
-
-#endif /* CONFIG_AT91_LEGACY */
-
-#endif
diff --git a/arch/arm/include/asm/arch-at91/at91_st.h b/arch/arm/include/asm/arch-at91/at91_st.h
deleted file mode 100644
index 53f9320..0000000
--- a/arch/arm/include/asm/arch-at91/at91_st.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/*
- * Copyright (C) 2009 Jens Scharsig (js_at_ng@scharsoft.de)
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef AT91_ST_H
-#define AT91_ST_H
-
-typedef struct at91_st {
-
-	u32	cr;
-	u32	pimr;
-	u32	wdmr;
-	u32	rtmr;
-	u32	sr;
-	u32	ier;
-	u32	idr;
-	u32	imr;
-	u32	rtar;
-	u32	crtr;
-} __attribute__ ((packed)) at91_st_t ;
-
-#define AT91_ST_CR_WDRST	1
-
-#define AT91_ST_WDMR_WDV(x)	(x & 0xFFFF)
-#define AT91_ST_WDMR_RSTEN	0x00010000
-#define AT91_ST_WDMR_EXTEN 	0x00020000
-
-#endif
diff --git a/arch/arm/include/asm/arch-at91/at91_tc.h b/arch/arm/include/asm/arch-at91/at91_tc.h
deleted file mode 100644
index 1e180ad..0000000
--- a/arch/arm/include/asm/arch-at91/at91_tc.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/*
- * Copyright (C) 2009 Jens Scharsig (js_at_ng@scharsoft.de)
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef AT91_TC_H
-#define AT91_TC_H
-
-typedef struct at91_tcc {
-	u32		ccr;	/* 0x00 Channel Control Register */
-	u32		cmr;	/* 0x04 Channel Mode Register */
-	u32		reserved1[2];
-	u32		cv;	/* 0x10 Counter Value */
-	u32		ra;	/* 0x14 Register A */
-	u32		rb;	/* 0x18 Register B */
-	u32		rc;	/* 0x1C Register C */
-	u32		sr;	/* 0x20 Status Register */
-	u32		ier;	/* 0x24 Interrupt Enable Register */
-	u32		idr;	/* 0x28 Interrupt Disable Register */
-	u32		imr;	/* 0x2C Interrupt Mask Register */
-	u32		reserved3[4];
-} __attribute__ ((packed)) at91_tcc_t;
-
-#define AT91_TC_CCR_CLKEN		0x00000001
-#define AT91_TC_CCR_CLKDIS		0x00000002
-#define AT91_TC_CCR_SWTRG		0x00000004
-
-#define AT91_TC_CMR_CPCTRG		0x00004000
-
-#define AT91_TC_CMR_TCCLKS_CLOCK1	0x00000000
-#define AT91_TC_CMR_TCCLKS_CLOCK2	0x00000001
-#define AT91_TC_CMR_TCCLKS_CLOCK3	0x00000002
-#define AT91_TC_CMR_TCCLKS_CLOCK4	0x00000003
-#define AT91_TC_CMR_TCCLKS_CLOCK5	0x00000004
-#define AT91_TC_CMR_TCCLKS_XC0		0x00000005
-#define AT91_TC_CMR_TCCLKS_XC1		0x00000006
-#define AT91_TC_CMR_TCCLKS_XC2		0x00000007
-
-typedef struct at91_tc {
-	at91_tcc_t	tc[3];	/* 0x00 TC Channel 0-2 */
-	u32		bcr;	/* 0xC0 TC Block Control Register */
-	u32		bmr;	/* 0xC4 TC Block Mode Register */
-} __attribute__ ((packed)) at91_tc_t;
-
-#define AT91_TC_BMR_TC0XC0S_TCLK0	0x00000000
-#define AT91_TC_BMR_TC0XC0S_NONE	0x00000001
-#define AT91_TC_BMR_TC0XC0S_TIOA1	0x00000002
-#define AT91_TC_BMR_TC0XC0S_TIOA2	0x00000003
-
-#define AT91_TC_BMR_TC1XC1S_TCLK1	0x00000000
-#define AT91_TC_BMR_TC1XC1S_NONE	0x00000004
-#define AT91_TC_BMR_TC1XC1S_TIOA0	0x00000008
-#define AT91_TC_BMR_TC1XC1S_TIOA2	0x0000000C
-
-#define AT91_TC_BMR_TC2XC2S_TCLK2	0x00000000
-#define AT91_TC_BMR_TC2XC2S_NONE	0x00000010
-#define AT91_TC_BMR_TC2XC2S_TIOA0	0x00000020
-#define AT91_TC_BMR_TC2XC2S_TIOA1	0x00000030
-
-#endif
diff --git a/arch/arm/include/asm/arch-at91/at91_wdt.h b/arch/arm/include/asm/arch-at91/at91_wdt.h
deleted file mode 100644
index cf08daf..0000000
--- a/arch/arm/include/asm/arch-at91/at91_wdt.h
+++ /dev/null
@@ -1,67 +0,0 @@
-/*
- * [origin: Linux kernel arch/arm/mach-at91/include/mach/at91_wdt.h]
- *
- * Copyright (C) 2008 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
- * Copyright (C) 2007 Andrew Victor
- * Copyright (C) 2007 Atmel Corporation.
- *
- * Watchdog Timer (WDT) - System peripherals regsters.
- * Based on AT91SAM9261 datasheet revision D.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#ifndef AT91_WDT_H
-#define AT91_WDT_H
-
-#ifdef __ASSEMBLY__
-
-#define AT91_ASM_WDT_MR	(AT91_WDT_BASE +  0x04)
-
-#else
-
-typedef struct at91_wdt {
-	u32	cr;
-	u32	mr;
-	u32	sr;
-} at91_wdt_t;
-
-#endif
-
-#define AT91_WDT_CR_WDRSTT		1
-#define AT91_WDT_CR_KEY			0xa5000000	/* KEY Password */
-
-#define AT91_WDT_MR_WDV(x)		(x & 0xfff)
-#define AT91_WDT_MR_WDFIEN		0x00001000
-#define AT91_WDT_MR_WDRSTEN		0x00002000
-#define AT91_WDT_MR_WDRPROC		0x00004000
-#define AT91_WDT_MR_WDDIS		0x00008000
-#define AT91_WDT_MR_WDD(x)		((x & 0xfff) << 16)
-#define AT91_WDT_MR_WDDBGHLT		0x10000000
-#define AT91_WDT_MR_WDIDLEHLT		0x20000000
-
-#ifdef CONFIG_AT91_LEGACY
-
-#define AT91_WDT_CR		(AT91_WDT + 0x00)	/* Watchdog Control Register */
-#define		AT91_WDT_WDRSTT		(1    << 0)		/* Restart */
-#define		AT91_WDT_KEY		(0xa5 << 24)		/* KEY Password */
-
-#define AT91_WDT_MR		(AT91_WDT + 0x04)	/* Watchdog Mode Register */
-#define		AT91_WDT_WDV		(0xfff << 0)		/* Counter Value */
-#define		AT91_WDT_WDFIEN		(1     << 12)		/* Fault Interrupt Enable */
-#define		AT91_WDT_WDRSTEN	(1     << 13)		/* Reset Processor */
-#define		AT91_WDT_WDRPROC	(1     << 14)		/* Timer Restart */
-#define		AT91_WDT_WDDIS		(1     << 15)		/* Watchdog Disable */
-#define		AT91_WDT_WDD		(0xfff << 16)		/* Delta Value */
-#define		AT91_WDT_WDDBGHLT	(1     << 28)		/* Debug Halt */
-#define		AT91_WDT_WDIDLEHLT	(1     << 29)		/* Idle Halt */
-
-#define AT91_WDT_SR		(AT91_WDT + 0x08)	/* Watchdog Status Register */
-#define		AT91_WDT_WDUNF		(1 << 0)		/* Watchdog Underflow */
-#define		AT91_WDT_WDERR		(1 << 1)		/* Watchdog Error */
-
-#endif /* CONFIG_AT91_LEGACY */
-#endif
diff --git a/arch/arm/include/asm/arch-at91/at91cap9.h b/arch/arm/include/asm/arch-at91/at91cap9.h
deleted file mode 100644
index 5af6fdc..0000000
--- a/arch/arm/include/asm/arch-at91/at91cap9.h
+++ /dev/null
@@ -1,150 +0,0 @@
-/*
- * [origin: Linux kernel include/asm-arm/arch-at91/at91cap9.h]
- *
- *  Copyright (C) 2007 Stelian Pop <stelian.pop@leadtechdesign.com>
- *  Copyright (C) 2007 Lead Tech Design <www.leadtechdesign.com>
- *  Copyright (C) 2007 Atmel Corporation.
- *
- * Common definitions.
- * Based on AT91CAP9 datasheet revision B (Preliminary).
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#ifndef AT91CAP9_H
-#define AT91CAP9_H
-
-/*
- * Peripheral identifiers/interrupts.
- */
-#define AT91_ID_FIQ		0	/* Advanced Interrupt Controller (FIQ) */
-#define AT91_ID_SYS		1	/* System Peripherals */
-#define AT91CAP9_ID_PIOABCD	2	/* Parallel IO Controller A, B, C and D */
-#define AT91CAP9_ID_MPB0	3	/* MP Block Peripheral 0 */
-#define AT91CAP9_ID_MPB1	4	/* MP Block Peripheral 1 */
-#define AT91CAP9_ID_MPB2	5	/* MP Block Peripheral 2 */
-#define AT91CAP9_ID_MPB3	6	/* MP Block Peripheral 3 */
-#define AT91CAP9_ID_MPB4	7	/* MP Block Peripheral 4 */
-#define AT91CAP9_ID_US0		8	/* USART 0 */
-#define AT91CAP9_ID_US1		9	/* USART 1 */
-#define AT91CAP9_ID_US2		10	/* USART 2 */
-#define AT91CAP9_ID_MCI0	11	/* Multimedia Card Interface 0 */
-#define AT91CAP9_ID_MCI1	12	/* Multimedia Card Interface 1 */
-#define AT91CAP9_ID_CAN		13	/* CAN */
-#define AT91CAP9_ID_TWI		14	/* Two-Wire Interface */
-#define AT91CAP9_ID_SPI0	15	/* Serial Peripheral Interface 0 */
-#define AT91CAP9_ID_SPI1	16	/* Serial Peripheral Interface 0 */
-#define AT91CAP9_ID_SSC0	17	/* Serial Synchronous Controller 0 */
-#define AT91CAP9_ID_SSC1	18	/* Serial Synchronous Controller 1 */
-#define AT91CAP9_ID_AC97C	19	/* AC97 Controller */
-#define AT91CAP9_ID_TCB		20	/* Timer Counter 0, 1 and 2 */
-#define AT91CAP9_ID_PWMC	21	/* Pulse Width Modulation Controller */
-#define AT91CAP9_ID_EMAC	22	/* Ethernet */
-#define AT91CAP9_ID_AESTDES	23	/* Advanced Encryption Standard, Triple DES */
-#define AT91CAP9_ID_ADC		24	/* Analog-to-Digital Converter */
-#define AT91CAP9_ID_ISI		25	/* Image Sensor Interface */
-#define AT91CAP9_ID_LCDC	26	/* LCD Controller */
-#define AT91CAP9_ID_DMA		27	/* DMA Controller */
-#define AT91CAP9_ID_UDPHS	28	/* USB High Speed Device Port */
-#define AT91CAP9_ID_UHP		29	/* USB Host Port */
-#define AT91CAP9_ID_IRQ0	30	/* Advanced Interrupt Controller (IRQ0) */
-#define AT91CAP9_ID_IRQ1	31	/* Advanced Interrupt Controller (IRQ1) */
-
-#define AT91_PIO_BASE	0xfffff200
-#define AT91_PMC_BASE	0xfffffc00
-#define AT91_RSTC_BASE	0xfffffd00
-#define AT91_PIT_BASE	0xfffffd30
-
-#ifdef CONFIG_AT91_LEGACY
-
-/*
- * User Peripheral physical base addresses.
- */
-#define AT91CAP9_BASE_UDPHS		0xfff78000
-#define AT91CAP9_BASE_TCB0		0xfff7c000
-#define AT91CAP9_BASE_TC0		0xfff7c000
-#define AT91CAP9_BASE_TC1		0xfff7c040
-#define AT91CAP9_BASE_TC2		0xfff7c080
-#define AT91CAP9_BASE_MCI0		0xfff80000
-#define AT91CAP9_BASE_MCI1		0xfff84000
-#define AT91CAP9_BASE_TWI		0xfff88000
-#define AT91CAP9_BASE_US0		0xfff8c000
-#define AT91CAP9_BASE_US1		0xfff90000
-#define AT91CAP9_BASE_US2		0xfff94000
-#define AT91CAP9_BASE_SSC0		0xfff98000
-#define AT91CAP9_BASE_SSC1		0xfff9c000
-#define AT91CAP9_BASE_AC97C		0xfffa0000
-#define AT91CAP9_BASE_SPI0		0xfffa4000
-#define AT91CAP9_BASE_SPI1		0xfffa8000
-#define AT91CAP9_BASE_CAN		0xfffac000
-#define AT91CAP9_BASE_PWMC		0xfffb8000
-#define AT91CAP9_BASE_EMAC		0xfffbc000
-#define AT91CAP9_BASE_ADC		0xfffc0000
-#define AT91CAP9_BASE_ISI		0xfffc4000
-#define AT91_BASE_SYS			0xffffe200
-
-/*
- * System Peripherals (offset from AT91_BASE_SYS)
- */
-#define AT91_ECC	(0xffffe200 - AT91_BASE_SYS)
-#define AT91_BCRAMC	(0xffffe400 - AT91_BASE_SYS)
-#define AT91_DDRSDRC	(0xffffe600 - AT91_BASE_SYS)
-#define AT91_SMC	(0xffffe800 - AT91_BASE_SYS)
-#define AT91_MATRIX	(0xffffea00 - AT91_BASE_SYS)
-#define AT91_CCFG	(0xffffeb10 - AT91_BASE_SYS)
-#define AT91_DMA	(0xffffec00 - AT91_BASE_SYS)
-#define AT91_DBGU	(0xffffee00 - AT91_BASE_SYS)
-#define AT91_AIC	(0xfffff000 - AT91_BASE_SYS)
-#define AT91_PIOA	(0xfffff200 - AT91_BASE_SYS)
-#define AT91_PIOB	(0xfffff400 - AT91_BASE_SYS)
-#define AT91_PIOC	(0xfffff600 - AT91_BASE_SYS)
-#define AT91_PIOD	(0xfffff800 - AT91_BASE_SYS)
-#define AT91_PMC	(0xfffffc00 - AT91_BASE_SYS)
-#define AT91_RSTC	(0xfffffd00 - AT91_BASE_SYS)
-#define AT91_SHDWC	(0xfffffd10 - AT91_BASE_SYS)
-#define AT91_RTT	(0xfffffd20 - AT91_BASE_SYS)
-#define AT91_PIT	(0xfffffd30 - AT91_BASE_SYS)
-#define AT91_WDT	(0xfffffd40 - AT91_BASE_SYS)
-#define AT91_SCKCR	(0xfffffd50 - AT91_BASE_SYS)
-#define AT91_GPBR_REVB	(0xfffffd50 - AT91_BASE_SYS)
-#define AT91_GPBR_REVC	(0xfffffd60 - AT91_BASE_SYS)
-
-#define AT91_USART0	AT91CAP9_BASE_US0
-#define AT91_USART1	AT91CAP9_BASE_US1
-#define AT91_USART2	AT91CAP9_BASE_US2
-
-/*
- * SCKCR flags
- */
-#define AT91CAP9_SCKCR_RCEN	(1 << 0)	/* RC Oscillator Enable */
-#define AT91CAP9_SCKCR_OSC32EN	(1 << 1)	/* 32kHz Oscillator Enable */
-#define AT91CAP9_SCKCR_OSC32BYP	(1 << 2)	/* 32kHz Oscillator Bypass */
-#define AT91CAP9_SCKCR_OSCSEL	(1 << 3)	/* Slow Clock Selector */
-#define		AT91CAP9_SCKCR_OSCSEL_RC	(0 << 3)
-#define		AT91CAP9_SCKCR_OSCSEL_32	(1 << 3)
-
-#endif /* CONFIG_AT91_LEGACY */
-/*
- * Internal Memory.
- */
-#define AT91CAP9_SRAM_BASE	0x00100000	/* Internal SRAM base address */
-#define AT91CAP9_SRAM_SIZE	(32 * SZ_1K)	/* Internal SRAM size (32Kb) */
-
-#define AT91CAP9_ROM_BASE	0x00400000	/* Internal ROM base address */
-#define AT91CAP9_ROM_SIZE	(32 * SZ_1K)	/* Internal ROM size (32Kb) */
-
-#define AT91CAP9_LCDC_BASE	0x00500000	/* LCD Controller */
-#define AT91CAP9_UDPHS_BASE	0x00600000	/* USB High Speed Device Port */
-#define AT91CAP9_UHP_BASE	0x00700000	/* USB Host controller */
-
-#define CONFIG_DRAM_BASE	AT91_CHIPSELECT_6
-
-/*
- * Cpu Name
- */
-#define CONFIG_SYS_AT91_CPU_NAME	"AT91CAP9"
-
-#endif
diff --git a/arch/arm/include/asm/arch-at91/at91cap9_matrix.h b/arch/arm/include/asm/arch-at91/at91cap9_matrix.h
deleted file mode 100644
index 22b7e9b..0000000
--- a/arch/arm/include/asm/arch-at91/at91cap9_matrix.h
+++ /dev/null
@@ -1,132 +0,0 @@
-/*
- * [origin: Linux kernel include/asm-arm/arch-at91/at91cap9_matrix.h]
- *
- *  Copyright (C) 2007 Stelian Pop <stelian.pop@leadtechdesign.com>
- *  Copyright (C) 2007 Lead Tech Design <www.leadtechdesign.com>
- *  Copyright (C) 2006 Atmel Corporation.
- *
- * Memory Controllers (MATRIX, EBI) - System peripherals registers.
- * Based on AT91CAP9 datasheet revision B (Preliminary).
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#ifndef AT91CAP9_MATRIX_H
-#define AT91CAP9_MATRIX_H
-
-#define AT91_MATRIX_MCFG0	(AT91_MATRIX + 0x00)	/* Master Configuration Register 0 */
-#define AT91_MATRIX_MCFG1	(AT91_MATRIX + 0x04)	/* Master Configuration Register 1 */
-#define AT91_MATRIX_MCFG2	(AT91_MATRIX + 0x08)	/* Master Configuration Register 2 */
-#define AT91_MATRIX_MCFG3	(AT91_MATRIX + 0x0C)	/* Master Configuration Register 3 */
-#define AT91_MATRIX_MCFG4	(AT91_MATRIX + 0x10)	/* Master Configuration Register 4 */
-#define AT91_MATRIX_MCFG5	(AT91_MATRIX + 0x14)	/* Master Configuration Register 5 */
-#define AT91_MATRIX_MCFG6	(AT91_MATRIX + 0x18)	/* Master Configuration Register 6 */
-#define AT91_MATRIX_MCFG7	(AT91_MATRIX + 0x1C)	/* Master Configuration Register 7 */
-#define AT91_MATRIX_MCFG8	(AT91_MATRIX + 0x20)	/* Master Configuration Register 8 */
-#define AT91_MATRIX_MCFG9	(AT91_MATRIX + 0x24)	/* Master Configuration Register 9 */
-#define AT91_MATRIX_MCFG10	(AT91_MATRIX + 0x28)	/* Master Configuration Register 10 */
-#define AT91_MATRIX_MCFG11	(AT91_MATRIX + 0x2C)	/* Master Configuration Register 11 */
-#define		AT91_MATRIX_ULBT	(7 << 0)	/* Undefined Length Burst Type */
-#define			AT91_MATRIX_ULBT_INFINITE	(0 << 0)
-#define			AT91_MATRIX_ULBT_SINGLE		(1 << 0)
-#define			AT91_MATRIX_ULBT_FOUR		(2 << 0)
-#define			AT91_MATRIX_ULBT_EIGHT		(3 << 0)
-#define			AT91_MATRIX_ULBT_SIXTEEN	(4 << 0)
-
-#define AT91_MATRIX_SCFG0	(AT91_MATRIX + 0x40)	/* Slave Configuration Register 0 */
-#define AT91_MATRIX_SCFG1	(AT91_MATRIX + 0x44)	/* Slave Configuration Register 1 */
-#define AT91_MATRIX_SCFG2	(AT91_MATRIX + 0x48)	/* Slave Configuration Register 2 */
-#define AT91_MATRIX_SCFG3	(AT91_MATRIX + 0x4C)	/* Slave Configuration Register 3 */
-#define AT91_MATRIX_SCFG4	(AT91_MATRIX + 0x50)	/* Slave Configuration Register 4 */
-#define AT91_MATRIX_SCFG5	(AT91_MATRIX + 0x54)	/* Slave Configuration Register 5 */
-#define AT91_MATRIX_SCFG6	(AT91_MATRIX + 0x58)	/* Slave Configuration Register 6 */
-#define AT91_MATRIX_SCFG7	(AT91_MATRIX + 0x5C)	/* Slave Configuration Register 7 */
-#define AT91_MATRIX_SCFG8	(AT91_MATRIX + 0x60)	/* Slave Configuration Register 8 */
-#define AT91_MATRIX_SCFG9	(AT91_MATRIX + 0x64)	/* Slave Configuration Register 9 */
-#define		AT91_MATRIX_SLOT_CYCLE		(0xff << 0)	/* Maximum Number of Allowed Cycles for a Burst */
-#define		AT91_MATRIX_DEFMSTR_TYPE	(3    << 16)	/* Default Master Type */
-#define			AT91_MATRIX_DEFMSTR_TYPE_NONE	(0 << 16)
-#define			AT91_MATRIX_DEFMSTR_TYPE_LAST	(1 << 16)
-#define			AT91_MATRIX_DEFMSTR_TYPE_FIXED	(2 << 16)
-#define		AT91_MATRIX_FIXED_DEFMSTR	(0xf  << 18)	/* Fixed Index of Default Master */
-#define		AT91_MATRIX_ARBT		(3    << 24)	/* Arbitration Type */
-#define			AT91_MATRIX_ARBT_ROUND_ROBIN	(0 << 24)
-#define			AT91_MATRIX_ARBT_FIXED_PRIORITY	(1 << 24)
-
-#define AT91_MATRIX_PRAS0	(AT91_MATRIX + 0x80)	/* Priority Register A for Slave 0 */
-#define AT91_MATRIX_PRBS0	(AT91_MATRIX + 0x84)	/* Priority Register B for Slave 0 */
-#define AT91_MATRIX_PRAS1	(AT91_MATRIX + 0x88)	/* Priority Register A for Slave 1 */
-#define AT91_MATRIX_PRBS1	(AT91_MATRIX + 0x8C)	/* Priority Register B for Slave 1 */
-#define AT91_MATRIX_PRAS2	(AT91_MATRIX + 0x90)	/* Priority Register A for Slave 2 */
-#define AT91_MATRIX_PRBS2	(AT91_MATRIX + 0x94)	/* Priority Register B for Slave 2 */
-#define AT91_MATRIX_PRAS3	(AT91_MATRIX + 0x98)	/* Priority Register A for Slave 3 */
-#define AT91_MATRIX_PRBS3	(AT91_MATRIX + 0x9C)	/* Priority Register B for Slave 3 */
-#define AT91_MATRIX_PRAS4	(AT91_MATRIX + 0xA0)	/* Priority Register A for Slave 4 */
-#define AT91_MATRIX_PRBS4	(AT91_MATRIX + 0xA4)	/* Priority Register B for Slave 4 */
-#define AT91_MATRIX_PRAS5	(AT91_MATRIX + 0xA8)	/* Priority Register A for Slave 5 */
-#define AT91_MATRIX_PRBS5	(AT91_MATRIX + 0xAC)	/* Priority Register B for Slave 5 */
-#define AT91_MATRIX_PRAS6	(AT91_MATRIX + 0xB0)	/* Priority Register A for Slave 6 */
-#define AT91_MATRIX_PRBS6	(AT91_MATRIX + 0xB4)	/* Priority Register B for Slave 6 */
-#define AT91_MATRIX_PRAS7	(AT91_MATRIX + 0xB8)	/* Priority Register A for Slave 7 */
-#define AT91_MATRIX_PRBS7	(AT91_MATRIX + 0xBC)	/* Priority Register B for Slave 7 */
-#define AT91_MATRIX_PRAS8	(AT91_MATRIX + 0xC0)	/* Priority Register A for Slave 8 */
-#define AT91_MATRIX_PRBS8	(AT91_MATRIX + 0xC4)	/* Priority Register B for Slave 8 */
-#define AT91_MATRIX_PRAS9	(AT91_MATRIX + 0xC8)	/* Priority Register A for Slave 9 */
-#define AT91_MATRIX_PRBS9	(AT91_MATRIX + 0xCC)	/* Priority Register B for Slave 9 */
-#define		AT91_MATRIX_M0PR		(3 << 0)	/* Master 0 Priority */
-#define		AT91_MATRIX_M1PR		(3 << 4)	/* Master 1 Priority */
-#define		AT91_MATRIX_M2PR		(3 << 8)	/* Master 2 Priority */
-#define		AT91_MATRIX_M3PR		(3 << 12)	/* Master 3 Priority */
-#define		AT91_MATRIX_M4PR		(3 << 16)	/* Master 4 Priority */
-#define		AT91_MATRIX_M5PR		(3 << 20)	/* Master 5 Priority */
-#define		AT91_MATRIX_M6PR		(3 << 24)	/* Master 6 Priority */
-#define		AT91_MATRIX_M7PR		(3 << 28)	/* Master 7 Priority */
-#define		AT91_MATRIX_M8PR		(3 << 0)	/* Master 8 Priority (in Register B) */
-#define		AT91_MATRIX_M9PR		(3 << 4)	/* Master 9 Priority (in Register B) */
-#define		AT91_MATRIX_M10PR		(3 << 8)	/* Master 10 Priority (in Register B) */
-#define		AT91_MATRIX_M11PR		(3 << 12)	/* Master 11 Priority (in Register B) */
-
-#define AT91_MATRIX_MRCR	(AT91_MATRIX + 0x100)	/* Master Remap Control Register */
-#define		AT91_MATRIX_RCB0		(1 << 0)	/* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
-#define		AT91_MATRIX_RCB1		(1 << 1)	/* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
-#define		AT91_MATRIX_RCB2		(1 << 2)
-#define		AT91_MATRIX_RCB3		(1 << 3)
-#define		AT91_MATRIX_RCB4		(1 << 4)
-#define		AT91_MATRIX_RCB5		(1 << 5)
-#define		AT91_MATRIX_RCB6		(1 << 6)
-#define		AT91_MATRIX_RCB7		(1 << 7)
-#define		AT91_MATRIX_RCB8		(1 << 8)
-#define		AT91_MATRIX_RCB9		(1 << 9)
-#define		AT91_MATRIX_RCB10		(1 << 10)
-#define		AT91_MATRIX_RCB11		(1 << 11)
-
-#define AT91_MPBS0_SFR		(AT91_MATRIX + 0x114)	/* MPBlock Slave 0 Special Function Register */
-#define AT91_MPBS1_SFR		(AT91_MATRIX + 0x11C)	/* MPBlock Slave 1 Special Function Register */
-
-#define AT91_MATRIX_EBICSA	(AT91_MATRIX + 0x120)	/* EBI Chip Select Assignment Register */
-#define		AT91_MATRIX_EBI_CS1A		(1 << 1)	/* Chip Select 1 Assignment */
-#define			AT91_MATRIX_EBI_CS1A_SMC		(0 << 1)
-#define			AT91_MATRIX_EBI_CS1A_BCRAMC		(1 << 1)
-#define		AT91_MATRIX_EBI_CS3A		(1 << 3)	/* Chip Select 3 Assignment */
-#define			AT91_MATRIX_EBI_CS3A_SMC		(0 << 3)
-#define			AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA	(1 << 3)
-#define		AT91_MATRIX_EBI_CS4A		(1 << 4)	/* Chip Select 4 Assignment */
-#define			AT91_MATRIX_EBI_CS4A_SMC		(0 << 4)
-#define			AT91_MATRIX_EBI_CS4A_SMC_CF1		(1 << 4)
-#define		AT91_MATRIX_EBI_CS5A		(1 << 5)	/* Chip Select 5 Assignment */
-#define			AT91_MATRIX_EBI_CS5A_SMC		(0 << 5)
-#define			AT91_MATRIX_EBI_CS5A_SMC_CF2		(1 << 5)
-#define		AT91_MATRIX_EBI_DBPUC		(1 << 8)	/* Data Bus Pull-up Configuration */
-#define		AT91_MATRIX_EBI_DQSPDC		(1 << 9)	/* Data Qualifier Strobe Pull-Down Configuration */
-#define		AT91_MATRIX_EBI_VDDIOMSEL	(1 << 16)	/* Memory voltage selection */
-#define			AT91_MATRIX_EBI_VDDIOMSEL_1_8V		(0 << 16)
-#define			AT91_MATRIX_EBI_VDDIOMSEL_3_3V		(1 << 16)
-
-#define AT91_MPBS2_SFR		(AT91_MATRIX + 0x12C)	/* MPBlock Slave 2 Special Function Register */
-#define AT91_MPBS3_SFR		(AT91_MATRIX + 0x130)	/* MPBlock Slave 3 Special Function Register */
-#define AT91_APB_SFR		(AT91_MATRIX + 0x134)	/* APB Bridge Special Function Register */
-
-#endif
diff --git a/arch/arm/include/asm/arch-at91/at91rm9200.h b/arch/arm/include/asm/arch-at91/at91rm9200.h
deleted file mode 100644
index 1bee6f2..0000000
--- a/arch/arm/include/asm/arch-at91/at91rm9200.h
+++ /dev/null
@@ -1,135 +0,0 @@
-/*
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __AT91RM9200_H__
-#define __AT91RM9200_H__
-
-/* Periperial Identifiers */
-
-#define AT91_ID_SYS	1	/* System Peripheral */
-#define AT91_ID_PIOA	2	/* PIO port A */
-#define AT91_ID_PIOB	3	/* PIO port B */
-#define AT91_ID_PIOC	4	/* PIO port C */
-#define AT91_ID_PIOD	5	/* PIO port D BGA only */
-#define AT91_ID_USART0	6	/* USART 0 */
-#define AT91_ID_USART1	7	/* USART 1 */
-#define AT91_ID_USART2	8	/* USART 2 */
-#define AT91_ID_USART3	9	/* USART 3 */
-#define AT91_ID_MCI	10	/* Multimedia Card Interface */
-#define AT91_ID_UDP	11	/* USB Device Port */
-#define AT91_ID_TWI	12	/* Two Wire Interface */
-#define AT91_ID_SPI	13	/* Serial Peripheral Interface */
-#define AT91_ID_SSC0	14	/* Synch. Serial Controller 0 */
-#define AT91_ID_SSC1	15	/* Synch. Serial Controller 1 */
-#define AT91_ID_SSC2	16	/* Synch. Serial Controller 2 */
-#define AT91_ID_TC0	17	/* Timer Counter 0 */
-#define AT91_ID_TC1	18	/* Timer Counter 1 */
-#define AT91_ID_TC2	19	/* Timer Counter 2 */
-#define AT91_ID_TC3	20	/* Timer Counter 3 */
-#define AT91_ID_TC4	21	/* Timer Counter 4 */
-#define AT91_ID_TC5	22	/* Timer Counter 5 */
-#define AT91_ID_UHP	23	/* OHCI USB Host Port */
-#define AT91_ID_EMAC	24	/* Ethernet MAC */
-#define AT91_ID_IRQ0	25	/* Advanced Interrupt Controller */
-#define AT91_ID_IRQ1	26	/* Advanced Interrupt Controller */
-#define AT91_ID_IRQ2	27	/* Advanced Interrupt Controller */
-#define AT91_ID_IRQ3	28	/* Advanced Interrupt Controller */
-#define AT91_ID_IRQ4	29	/* Advanced Interrupt Controller */
-#define AT91_ID_IRQ5	30	/* Advanced Interrupt Controller */
-#define AT91_ID_IRQ6	31	/* Advanced Interrupt Controller */
-
-#define AT91_USB_HOST_BASE	0x00300000
-
-#define AT91_TC_BASE		0xFFFA0000
-#define AT91_UDP_BASE		0xFFFB0000
-#define AT91_MCI_BASE		0xFFFB4000
-#define AT91_TWI_BASE		0xFFFB8000
-#define AT91_EMAC_BASE		0xFFFBC000
-#define AT91_USART_BASE		0xFFFC0000	/* 4x 0x4000 Offset */
-#define AT91_SCC_BASE		0xFFFD0000	/* 4x 0x4000 Offset */
-#define AT91_SPI_BASE		0xFFFE0000
-
-#define AT91_AIC_BASE		0xFFFFF000
-#define AT91_DBGU_BASE		0xFFFFF200
-#define AT91_PIO_BASE		0xFFFFF400	/* 4x 0x200 Offset */
-#define AT91_PMC_BASE		0xFFFFFC00
-#define AT91_ST_BASE		0xFFFFFD00
-#define AT91_ST_BASE		0xFFFFFD00
-#define AT91_RTC_BASE		0xFFFFFE00
-#define AT91_MC_BASE		0xFFFFFF00
-
-
-/* AT91RM9200 Periperial Multiplexing A */
-/* Port A */
-#define AT91_PMX_AA_EREFCK	0x00000080
-#define AT91_PMX_AA_ETXCK	0x00000080
-#define AT91_PMX_AA_ETXEN	0x00000100
-#define AT91_PMX_AA_ETX0	0x00000200
-#define AT91_PMX_AA_ETX1	0x00000400
-#define AT91_PMX_AA_ECRS	0x00000800
-#define AT91_PMX_AA_ECRSDV	0x00000800
-#define AT91_PMX_AA_ERX0	0x00001000
-#define AT91_PMX_AA_ERX1	0x00002000
-#define AT91_PMX_AA_ERXER	0x00004000
-#define AT91_PMX_AA_EMDC	0x00008000
-#define AT91_PMX_AA_EMDIO	0x00010000
-
-#define AT91_PMX_AA_TXD2	0x00810000
-
-#define AT91_PMX_AA_TWD		0x02000000
-#define AT91_PMX_AA_TWCK	0x04000000
-
-/* Port B */
-#define AT91_PMX_BA_ERXCK	0x00080000
-#define AT91_PMX_BA_ECOL	0x00040000
-#define AT91_PMX_BA_ERXDV	0x00020000
-#define AT91_PMX_BA_ERX3	0x00010000
-#define AT91_PMX_BA_ERX2 	0x00008000
-#define AT91_PMX_BA_ETXER	0x00004000
-#define AT91_PMX_BA_ETX3	0x00002000
-#define AT91_PMX_BA_ETX2	0x00001000
-
-/* Port B */
-
-#define AT91_PMX_CA_BFCK	0x00000001
-#define AT91_PMX_CA_BFRDY	0x00000002
-#define AT91_PMX_CA_SMOE	0x00000002
-#define AT91_PMX_CA_BFAVD	0x00000004
-#define AT91_PMX_CA_BFBAA	0x00000008
-#define AT91_PMX_CA_SMWE	0x00000008
-#define AT91_PMX_CA_BFOE	0x00000010
-#define AT91_PMX_CA_BFWE	0x00000020
-#define AT91_PMX_CA_NWAIT	0x00000040
-#define AT91_PMX_CA_A23		0x00000080
-#define AT91_PMX_CA_A24		0x00000100
-#define AT91_PMX_CA_A25		0x00000200
-#define AT91_PMX_CA_CFRNW	0x00000200
-#define AT91_PMX_CA_NCS4	0x00000400
-#define AT91_PMX_CA_CFCS	0x00000400
-#define AT91_PMX_CA_NCS5	0x00000800
-#define AT91_PMX_CA_CFCE1	0x00001000
-#define AT91_PMX_CA_NCS6	0x00001000
-#define AT91_PMX_CA_CFCE2	0x00002000
-#define AT91_PMX_CA_NCS7	0x00002000
-#define AT91_PMX_CA_D16_31	0xFFFF0000
-
-#define CONFIG_SYS_AT91_CPU_NAME	"AT91RM9200"
-
-#endif
diff --git a/arch/arm/include/asm/arch-at91/at91sam9260.h b/arch/arm/include/asm/arch-at91/at91sam9260.h
deleted file mode 100644
index 7fd60b7..0000000
--- a/arch/arm/include/asm/arch-at91/at91sam9260.h
+++ /dev/null
@@ -1,160 +0,0 @@
-/*
- * [origin: Linux kernel include/asm-arm/arch-at91/at91sam9260.h]
- *
- * (C) 2006 Andrew Victor
- *
- * Common definitions.
- * Based on AT91SAM9260 datasheet revision A (Preliminary).
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#ifndef AT91SAM9260_H
-#define AT91SAM9260_H
-
-/*
- * Peripheral identifiers/interrupts.
- */
-#define AT91_ID_FIQ		0	/* Advanced Interrupt Controller (FIQ) */
-#define AT91_ID_SYS		1	/* System Peripherals */
-#define AT91SAM9260_ID_PIOA	2	/* Parallel IO Controller A */
-#define AT91SAM9260_ID_PIOB	3	/* Parallel IO Controller B */
-#define AT91SAM9260_ID_PIOC	4	/* Parallel IO Controller C */
-#define AT91SAM9260_ID_ADC	5	/* Analog-to-Digital Converter */
-#define AT91SAM9260_ID_US0	6	/* USART 0 */
-#define AT91SAM9260_ID_US1	7	/* USART 1 */
-#define AT91SAM9260_ID_US2	8	/* USART 2 */
-#define AT91SAM9260_ID_MCI	9	/* Multimedia Card Interface */
-#define AT91SAM9260_ID_UDP	10	/* USB Device Port */
-#define AT91SAM9260_ID_TWI	11	/* Two-Wire Interface */
-#define AT91SAM9260_ID_SPI0	12	/* Serial Peripheral Interface 0 */
-#define AT91SAM9260_ID_SPI1	13	/* Serial Peripheral Interface 1 */
-#define AT91SAM9260_ID_SSC	14	/* Serial Synchronous Controller */
-#define AT91SAM9260_ID_TC0	17	/* Timer Counter 0 */
-#define AT91SAM9260_ID_TC1	18	/* Timer Counter 1 */
-#define AT91SAM9260_ID_TC2	19	/* Timer Counter 2 */
-#define AT91SAM9260_ID_UHP	20	/* USB Host port */
-#define AT91SAM9260_ID_EMAC	21	/* Ethernet */
-#define AT91SAM9260_ID_ISI	22	/* Image Sensor Interface */
-#define AT91SAM9260_ID_US3	23	/* USART 3 */
-#define AT91SAM9260_ID_US4	24	/* USART 4 */
-#define AT91SAM9260_ID_US5	25	/* USART 5 */
-#define AT91SAM9260_ID_TC3	26	/* Timer Counter 3 */
-#define AT91SAM9260_ID_TC4	27	/* Timer Counter 4 */
-#define AT91SAM9260_ID_TC5	28	/* Timer Counter 5 */
-#define AT91SAM9260_ID_IRQ0	29	/* Advanced Interrupt Controller (IRQ0) */
-#define AT91SAM9260_ID_IRQ1	30	/* Advanced Interrupt Controller (IRQ1) */
-#define AT91SAM9260_ID_IRQ2	31	/* Advanced Interrupt Controller (IRQ2) */
-
-#define AT91_EMAC_BASE		0xfffc4000
-#define AT91_SDRAMC_BASE	0xffffea00
-#define AT91_SMC_BASE		0xffffec00
-#define AT91_MATRIX_BASE	0xffffee00
-#define AT91_PIO_BASE		0xfffff400
-#define AT91_PMC_BASE		0xfffffc00
-#define AT91_RSTC_BASE		0xfffffd00
-#define AT91_SHDWN_BASE		0xfffffd10
-#define AT91_RTT_BASE		0xfffffd20
-#define AT91_PIT_BASE		0xfffffd30
-#define AT91_WDT_BASE		0xfffffd40
-/*
- * The AT91SAM9XE has the GPBRs at a different address than
- * the AT91SAM9260/9G20.
- */
-#ifdef CONFIG_AT91SAM9XE
-# define AT91_GPR_BASE		0xfffffd60
-#else
-# define AT91_GPR_BASE		0xfffffd50
-#endif
-
-#ifdef CONFIG_AT91_LEGACY
-
-/*
- * User Peripheral physical base addresses.
- */
-#define AT91SAM9260_BASE_TCB0		0xfffa0000
-#define AT91SAM9260_BASE_TC0		0xfffa0000
-#define AT91SAM9260_BASE_TC1		0xfffa0040
-#define AT91SAM9260_BASE_TC2		0xfffa0080
-#define AT91SAM9260_BASE_UDP		0xfffa4000
-#define AT91SAM9260_BASE_MCI		0xfffa8000
-#define AT91SAM9260_BASE_TWI		0xfffac000
-#define AT91SAM9260_BASE_US0		0xfffb0000
-#define AT91SAM9260_BASE_US1		0xfffb4000
-#define AT91SAM9260_BASE_US2		0xfffb8000
-#define AT91SAM9260_BASE_SSC		0xfffbc000
-#define AT91SAM9260_BASE_ISI		0xfffc0000
-#define AT91SAM9260_BASE_EMAC		0xfffc4000
-#define AT91SAM9260_BASE_SPI0		0xfffc8000
-#define AT91SAM9260_BASE_SPI1		0xfffcc000
-#define AT91SAM9260_BASE_US3		0xfffd0000
-#define AT91SAM9260_BASE_US4		0xfffd4000
-#define AT91SAM9260_BASE_US5		0xfffd8000
-#define AT91SAM9260_BASE_TCB1		0xfffdc000
-#define AT91SAM9260_BASE_TC3		0xfffdc000
-#define AT91SAM9260_BASE_TC4		0xfffdc040
-#define AT91SAM9260_BASE_TC5		0xfffdc080
-#define AT91SAM9260_BASE_ADC		0xfffe0000
-#define AT91_BASE_SYS			0xffffe800
-
-/*
- * System Peripherals (offset from AT91_BASE_SYS)
- */
-#define AT91_ECC	(0xffffe800 - AT91_BASE_SYS)
-#define AT91_SDRAMC	(0xffffea00 - AT91_BASE_SYS)
-#define AT91_SMC	(0xffffec00 - AT91_BASE_SYS)
-#define AT91_MATRIX	(0xffffee00 - AT91_BASE_SYS)
-#define AT91_CCFG	(0xffffef10 - AT91_BASE_SYS)
-#define AT91_AIC	(0xfffff000 - AT91_BASE_SYS)
-#define AT91_DBGU	(0xfffff200 - AT91_BASE_SYS)
-#define AT91_PIOA	(0xfffff400 - AT91_BASE_SYS)
-#define AT91_PIOB	(0xfffff600 - AT91_BASE_SYS)
-#define AT91_PIOC	(0xfffff800 - AT91_BASE_SYS)
-#define AT91_PMC	(0xfffffc00 - AT91_BASE_SYS)
-#define AT91_RSTC	(0xfffffd00 - AT91_BASE_SYS)
-#define AT91_SHDWC	(0xfffffd10 - AT91_BASE_SYS)
-#define AT91_RTT	(0xfffffd20 - AT91_BASE_SYS)
-#define AT91_PIT	(0xfffffd30 - AT91_BASE_SYS)
-#define AT91_WDT	(0xfffffd40 - AT91_BASE_SYS)
-#define AT91_GPBR	(0xfffffd50 - AT91_BASE_SYS)
-
-#define AT91_USART0	AT91SAM9260_BASE_US0
-#define AT91_USART1	AT91SAM9260_BASE_US1
-#define AT91_USART2	AT91SAM9260_BASE_US2
-#define AT91_USART3	AT91SAM9260_BASE_US3
-#define AT91_USART4	AT91SAM9260_BASE_US4
-#define AT91_USART5	AT91SAM9260_BASE_US5
-
-#endif /* CONFIG_AT91_LEGACY */
-
-/*
- * Internal Memory.
- */
-#define AT91SAM9260_ROM_BASE	0x00100000	/* Internal ROM base address */
-#define AT91SAM9260_ROM_SIZE	SZ_32K		/* Internal ROM size (32Kb) */
-
-#define AT91SAM9260_SRAM0_BASE	0x00200000	/* Internal SRAM 0 base address */
-#define AT91SAM9260_SRAM0_SIZE	SZ_4K		/* Internal SRAM 0 size (4Kb) */
-#define AT91SAM9260_SRAM1_BASE	0x00300000	/* Internal SRAM 1 base address */
-#define AT91SAM9260_SRAM1_SIZE	SZ_4K		/* Internal SRAM 1 size (4Kb) */
-
-#define AT91SAM9260_UHP_BASE	0x00500000	/* USB Host controller */
-
-#define AT91SAM9XE_FLASH_BASE	0x00200000	/* Internal FLASH base address */
-#define AT91SAM9XE_SRAM_BASE	0x00300000	/* Internal SRAM base address */
-
-/*
- * Cpu Name
- */
-#if defined(CONFIG_AT91SAM9XE)
-# define CONFIG_SYS_AT91_CPU_NAME	"AT91SAM9XE"
-#elif defined(CONFIG_AT91SAM9260)
-# define CONFIG_SYS_AT91_CPU_NAME	"AT91SAM9260"
-#elif defined(CONFIG_AT91SAM9G20)
-# define CONFIG_SYS_AT91_CPU_NAME	"AT91SAM9G20"
-#endif
-
-#endif
diff --git a/arch/arm/include/asm/arch-at91/at91sam9260_matrix.h b/arch/arm/include/asm/arch-at91/at91sam9260_matrix.h
deleted file mode 100644
index f8b023d..0000000
--- a/arch/arm/include/asm/arch-at91/at91sam9260_matrix.h
+++ /dev/null
@@ -1,80 +0,0 @@
-/*
- * [origin: Linux kernel include/asm-arm/arch-at91/at91sam9260_matrix.h]
- *
- * Copyright (C) 2007 Atmel Corporation.
- *
- * Memory Controllers (MATRIX, EBI) - System peripherals registers.
- * Based on AT91SAM9260 datasheet revision B.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#ifndef AT91SAM9260_MATRIX_H
-#define AT91SAM9260_MATRIX_H
-
-#define AT91_MATRIX_MCFG0	(AT91_MATRIX + 0x00)	/* Master Configuration Register 0 */
-#define AT91_MATRIX_MCFG1	(AT91_MATRIX + 0x04)	/* Master Configuration Register 1 */
-#define AT91_MATRIX_MCFG2	(AT91_MATRIX + 0x08)	/* Master Configuration Register 2 */
-#define AT91_MATRIX_MCFG3	(AT91_MATRIX + 0x0C)	/* Master Configuration Register 3 */
-#define AT91_MATRIX_MCFG4	(AT91_MATRIX + 0x10)	/* Master Configuration Register 4 */
-#define AT91_MATRIX_MCFG5	(AT91_MATRIX + 0x14)	/* Master Configuration Register 5 */
-#define		AT91_MATRIX_ULBT		(7 << 0)	/* Undefined Length Burst Type */
-#define			AT91_MATRIX_ULBT_INFINITE	(0 << 0)
-#define			AT91_MATRIX_ULBT_SINGLE		(1 << 0)
-#define			AT91_MATRIX_ULBT_FOUR		(2 << 0)
-#define			AT91_MATRIX_ULBT_EIGHT		(3 << 0)
-#define			AT91_MATRIX_ULBT_SIXTEEN	(4 << 0)
-
-#define AT91_MATRIX_SCFG0	(AT91_MATRIX + 0x40)	/* Slave Configuration Register 0 */
-#define AT91_MATRIX_SCFG1	(AT91_MATRIX + 0x44)	/* Slave Configuration Register 1 */
-#define AT91_MATRIX_SCFG2	(AT91_MATRIX + 0x48)	/* Slave Configuration Register 2 */
-#define AT91_MATRIX_SCFG3	(AT91_MATRIX + 0x4C)	/* Slave Configuration Register 3 */
-#define AT91_MATRIX_SCFG4	(AT91_MATRIX + 0x50)	/* Slave Configuration Register 4 */
-#define		AT91_MATRIX_SLOT_CYCLE		(0xff <<  0)	/* Maximum Number of Allowed Cycles for a Burst */
-#define		AT91_MATRIX_DEFMSTR_TYPE	(3    << 16)	/* Default Master Type */
-#define			AT91_MATRIX_DEFMSTR_TYPE_NONE	(0 << 16)
-#define			AT91_MATRIX_DEFMSTR_TYPE_LAST	(1 << 16)
-#define			AT91_MATRIX_DEFMSTR_TYPE_FIXED	(2 << 16)
-#define		AT91_MATRIX_FIXED_DEFMSTR	(7    << 18)	/* Fixed Index of Default Master */
-#define		AT91_MATRIX_ARBT		(3    << 24)	/* Arbitration Type */
-#define			AT91_MATRIX_ARBT_ROUND_ROBIN	(0 << 24)
-#define			AT91_MATRIX_ARBT_FIXED_PRIORITY	(1 << 24)
-
-#define AT91_MATRIX_PRAS0	(AT91_MATRIX + 0x80)	/* Priority Register A for Slave 0 */
-#define AT91_MATRIX_PRAS1	(AT91_MATRIX + 0x88)	/* Priority Register A for Slave 1 */
-#define AT91_MATRIX_PRAS2	(AT91_MATRIX + 0x90)	/* Priority Register A for Slave 2 */
-#define AT91_MATRIX_PRAS3	(AT91_MATRIX + 0x98)	/* Priority Register A for Slave 3 */
-#define AT91_MATRIX_PRAS4	(AT91_MATRIX + 0xA0)	/* Priority Register A for Slave 4 */
-#define		AT91_MATRIX_M0PR		(3 << 0)	/* Master 0 Priority */
-#define		AT91_MATRIX_M1PR		(3 << 4)	/* Master 1 Priority */
-#define		AT91_MATRIX_M2PR		(3 << 8)	/* Master 2 Priority */
-#define		AT91_MATRIX_M3PR		(3 << 12)	/* Master 3 Priority */
-#define		AT91_MATRIX_M4PR		(3 << 16)	/* Master 4 Priority */
-#define		AT91_MATRIX_M5PR		(3 << 20)	/* Master 5 Priority */
-
-#define AT91_MATRIX_MRCR	(AT91_MATRIX + 0x100)	/* Master Remap Control Register */
-#define		AT91_MATRIX_RCB0		(1 << 0)	/* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
-#define		AT91_MATRIX_RCB1		(1 << 1)	/* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
-
-#define AT91_MATRIX_EBICSA	(AT91_MATRIX + 0x11C)	/* EBI Chip Select Assignment Register */
-#define		AT91_MATRIX_CS1A		(1 << 1)	/* Chip Select 1 Assignment */
-#define			AT91_MATRIX_CS1A_SMC		(0 << 1)
-#define			AT91_MATRIX_CS1A_SDRAMC		(1 << 1)
-#define		AT91_MATRIX_CS3A		(1 << 3)	/* Chip Select 3 Assignment */
-#define			AT91_MATRIX_CS3A_SMC		(0 << 3)
-#define			AT91_MATRIX_CS3A_SMC_SMARTMEDIA	(1 << 3)
-#define		AT91_MATRIX_CS4A		(1 << 4)	/* Chip Select 4 Assignment */
-#define			AT91_MATRIX_CS4A_SMC		(0 << 4)
-#define			AT91_MATRIX_CS4A_SMC_CF1	(1 << 4)
-#define		AT91_MATRIX_CS5A		(1 << 5)	/* Chip Select 5 Assignment */
-#define			AT91_MATRIX_CS5A_SMC		(0 << 5)
-#define			AT91_MATRIX_CS5A_SMC_CF2	(1 << 5)
-#define		AT91_MATRIX_DBPUC		(1 << 8)	/* Data Bus Pull-up Configuration */
-#define		AT91_MATRIX_VDDIOMSEL		(1 << 16)	/* Memory voltage selection */
-#define			AT91_MATRIX_VDDIOMSEL_1_8V	(0 << 16)
-#define			AT91_MATRIX_VDDIOMSEL_3_3V	(1 << 16)
-
-#endif
diff --git a/arch/arm/include/asm/arch-at91/at91sam9261.h b/arch/arm/include/asm/arch-at91/at91sam9261.h
deleted file mode 100644
index 7ca0283..0000000
--- a/arch/arm/include/asm/arch-at91/at91sam9261.h
+++ /dev/null
@@ -1,121 +0,0 @@
-/*
- * [origin: Linux kernel include/asm-arm/arch-at91/at91sam9261.h]
- *
- * Copyright (C) SAN People
- *
- * Common definitions.
- * Based on AT91SAM9261 datasheet revision E. (Preliminary)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#ifndef AT91SAM9261_H
-#define AT91SAM9261_H
-
-/*
- * Peripheral identifiers/interrupts.
- */
-#define AT91_ID_FIQ		0	/* Advanced Interrupt Controller (FIQ) */
-#define AT91_ID_SYS		1	/* System Peripherals */
-#define AT91SAM9261_ID_PIOA	2	/* Parallel IO Controller A */
-#define AT91SAM9261_ID_PIOB	3	/* Parallel IO Controller B */
-#define AT91SAM9261_ID_PIOC	4	/* Parallel IO Controller C */
-#define AT91SAM9261_ID_US0	6	/* USART 0 */
-#define AT91SAM9261_ID_US1	7	/* USART 1 */
-#define AT91SAM9261_ID_US2	8	/* USART 2 */
-#define AT91SAM9261_ID_MCI	9	/* Multimedia Card Interface */
-#define AT91SAM9261_ID_UDP	10	/* USB Device Port */
-#define AT91SAM9261_ID_TWI	11	/* Two-Wire Interface */
-#define AT91SAM9261_ID_SPI0	12	/* Serial Peripheral Interface 0 */
-#define AT91SAM9261_ID_SPI1	13	/* Serial Peripheral Interface 1 */
-#define AT91SAM9261_ID_SSC0	14	/* Serial Synchronous Controller 0 */
-#define AT91SAM9261_ID_SSC1	15	/* Serial Synchronous Controller 1 */
-#define AT91SAM9261_ID_SSC2	16	/* Serial Synchronous Controller 2 */
-#define AT91SAM9261_ID_TC0	17	/* Timer Counter 0 */
-#define AT91SAM9261_ID_TC1	18	/* Timer Counter 1 */
-#define AT91SAM9261_ID_TC2	19	/* Timer Counter 2 */
-#define AT91SAM9261_ID_UHP	20	/* USB Host port */
-#define AT91SAM9261_ID_LCDC	21	/* LDC Controller */
-#define AT91SAM9261_ID_IRQ0	29	/* Advanced Interrupt Controller (IRQ0) */
-#define AT91SAM9261_ID_IRQ1	30	/* Advanced Interrupt Controller (IRQ1) */
-#define AT91SAM9261_ID_IRQ2	31	/* Advanced Interrupt Controller (IRQ2) */
-
-#define AT91_SDRAMC_BASE	0xffffea00
-#define AT91_SMC_BASE		0xffffec00
-#define AT91_MATRIX_BASE	0xffffee00
-#define AT91_PIO_BASE		0xfffff400
-#define AT91_PMC_BASE		0xfffffc00
-#define AT91_RSTC_BASE		0xfffffd00
-#define AT91_RTT_BASE		0xfffffd20
-#define AT91_PIT_BASE		0xfffffd30
-#define AT91_WDT_BASE		0xfffffd40
-#define AT91_GPBR_BASE		0xfffffd50
-
-#ifdef CONFIG_AT91_LEGACY
-
-/*
- * User Peripheral physical base addresses.
- */
-#define AT91SAM9261_BASE_TCB0		0xfffa0000
-#define AT91SAM9261_BASE_TC0		0xfffa0000
-#define AT91SAM9261_BASE_TC1		0xfffa0040
-#define AT91SAM9261_BASE_TC2		0xfffa0080
-#define AT91SAM9261_BASE_UDP		0xfffa4000
-#define AT91SAM9261_BASE_MCI		0xfffa8000
-#define AT91SAM9261_BASE_TWI		0xfffac000
-#define AT91SAM9261_BASE_US0		0xfffb0000
-#define AT91SAM9261_BASE_US1		0xfffb4000
-#define AT91SAM9261_BASE_US2		0xfffb8000
-#define AT91SAM9261_BASE_SSC0		0xfffbc000
-#define AT91SAM9261_BASE_SSC1		0xfffc0000
-#define AT91SAM9261_BASE_SSC2		0xfffc4000
-#define AT91SAM9261_BASE_SPI0		0xfffc8000
-#define AT91SAM9261_BASE_SPI1		0xfffcc000
-#define AT91_BASE_SYS			0xffffea00
-
-/*
- * System Peripherals (offset from AT91_BASE_SYS)
- */
-#define AT91_SDRAMC	(0xffffea00 - AT91_BASE_SYS)
-#define AT91_SMC	(0xffffec00 - AT91_BASE_SYS)
-#define AT91_MATRIX	(0xffffee00 - AT91_BASE_SYS)
-#define AT91_AIC	(0xfffff000 - AT91_BASE_SYS)
-#define AT91_DBGU	(0xfffff200 - AT91_BASE_SYS)
-#define AT91_PIOA	(0xfffff400 - AT91_BASE_SYS)
-#define AT91_PIOB	(0xfffff600 - AT91_BASE_SYS)
-#define AT91_PIOC	(0xfffff800 - AT91_BASE_SYS)
-#define AT91_PMC	(0xfffffc00 - AT91_BASE_SYS)
-#define AT91_RSTC	(0xfffffd00 - AT91_BASE_SYS)
-#define AT91_SHDWC	(0xfffffd10 - AT91_BASE_SYS)
-#define AT91_RTT	(0xfffffd20 - AT91_BASE_SYS)
-#define AT91_PIT	(0xfffffd30 - AT91_BASE_SYS)
-#define AT91_WDT	(0xfffffd40 - AT91_BASE_SYS)
-#define AT91_GPBR	(0xfffffd50 - AT91_BASE_SYS)
-
-#define AT91_USART0	AT91SAM9261_BASE_US0
-#define AT91_USART1	AT91SAM9261_BASE_US1
-#define AT91_USART2	AT91SAM9261_BASE_US2
-
-#endif /* CONFIG_AT91_LEGACY */
-
-/*
- * Internal Memory.
- */
-#define AT91SAM9261_SRAM_BASE	0x00300000	/* Internal SRAM base address */
-#define AT91SAM9261_SRAM_SIZE	0x00028000	/* Internal SRAM size (160Kb) */
-
-#define AT91SAM9261_ROM_BASE	0x00400000	/* Internal ROM base address */
-#define AT91SAM9261_ROM_SIZE	SZ_32K		/* Internal ROM size (32Kb) */
-
-#define AT91SAM9261_UHP_BASE	0x00500000	/* USB Host controller */
-#define AT91SAM9261_LCDC_BASE	0x00600000	/* LDC controller */
-
-/*
- * Cpu Name
- */
-#define CONFIG_SYS_AT91_CPU_NAME	"AT91SAM9261"
-
-#endif
diff --git a/arch/arm/include/asm/arch-at91/at91sam9261_matrix.h b/arch/arm/include/asm/arch-at91/at91sam9261_matrix.h
deleted file mode 100644
index e2bfc4b..0000000
--- a/arch/arm/include/asm/arch-at91/at91sam9261_matrix.h
+++ /dev/null
@@ -1,64 +0,0 @@
-/*
- * [origin: Linux kernel include/asm-arm/arch-at91/at91sam9261_matrix.h]
- *
- * Copyright (C) 2007 Atmel Corporation.
- *
- * Memory Controllers (MATRIX, EBI) - System peripherals registers.
- * Based on AT91SAM9261 datasheet revision D.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#ifndef AT91SAM9261_MATRIX_H
-#define AT91SAM9261_MATRIX_H
-
-#define AT91_MATRIX_MCFG	(AT91_MATRIX + 0x00)	/* Master Configuration Register */
-#define		AT91_MATRIX_RCB0	(1 << 0)		/* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
-#define		AT91_MATRIX_RCB1	(1 << 1)		/* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
-
-#define AT91_MATRIX_SCFG0	(AT91_MATRIX + 0x04)	/* Slave Configuration Register 0 */
-#define AT91_MATRIX_SCFG1	(AT91_MATRIX + 0x08)	/* Slave Configuration Register 1 */
-#define AT91_MATRIX_SCFG2	(AT91_MATRIX + 0x0C)	/* Slave Configuration Register 2 */
-#define AT91_MATRIX_SCFG3	(AT91_MATRIX + 0x10)	/* Slave Configuration Register 3 */
-#define AT91_MATRIX_SCFG4	(AT91_MATRIX + 0x14)	/* Slave Configuration Register 4 */
-#define		AT91_MATRIX_SLOT_CYCLE		(0xff << 0)	/* Maximum Number of Allowed Cycles for a Burst */
-#define		AT91_MATRIX_DEFMSTR_TYPE	(3    << 16)	/* Default Master Type */
-#define			AT91_MATRIX_DEFMSTR_TYPE_NONE	(0 << 16)
-#define			AT91_MATRIX_DEFMSTR_TYPE_LAST	(1 << 16)
-#define			AT91_MATRIX_DEFMSTR_TYPE_FIXED	(2 << 16)
-#define		AT91_MATRIX_FIXED_DEFMSTR	(7    << 18)	/* Fixed Index of Default Master */
-
-#define AT91_MATRIX_TCR		(AT91_MATRIX + 0x24)	/* TCM Configuration Register */
-#define		AT91_MATRIX_ITCM_SIZE		(0xf << 0)	/* Size of ITCM enabled memory block */
-#define			AT91_MATRIX_ITCM_0		(0 << 0)
-#define			AT91_MATRIX_ITCM_16		(5 << 0)
-#define			AT91_MATRIX_ITCM_32		(6 << 0)
-#define			AT91_MATRIX_ITCM_64		(7 << 0)
-#define		AT91_MATRIX_DTCM_SIZE		(0xf << 4)	/* Size of DTCM enabled memory block */
-#define			AT91_MATRIX_DTCM_0		(0 << 4)
-#define			AT91_MATRIX_DTCM_16		(5 << 4)
-#define			AT91_MATRIX_DTCM_32		(6 << 4)
-#define			AT91_MATRIX_DTCM_64		(7 << 4)
-
-#define AT91_MATRIX_EBICSA	(AT91_MATRIX + 0x30)	/* EBI Chip Select Assignment Register */
-#define		AT91_MATRIX_CS1A		(1 << 1)	/* Chip Select 1 Assignment */
-#define			AT91_MATRIX_CS1A_SMC		(0 << 1)
-#define			AT91_MATRIX_CS1A_SDRAMC		(1 << 1)
-#define		AT91_MATRIX_CS3A		(1 << 3)	/* Chip Select 3 Assignment */
-#define			AT91_MATRIX_CS3A_SMC		(0 << 3)
-#define			AT91_MATRIX_CS3A_SMC_SMARTMEDIA	(1 << 3)
-#define		AT91_MATRIX_CS4A		(1 << 4)	/* Chip Select 4 Assignment */
-#define			AT91_MATRIX_CS4A_SMC		(0 << 4)
-#define			AT91_MATRIX_CS4A_SMC_CF1	(1 << 4)
-#define		AT91_MATRIX_CS5A		(1 << 5)	/* Chip Select 5 Assignment */
-#define			AT91_MATRIX_CS5A_SMC		(0 << 5)
-#define			AT91_MATRIX_CS5A_SMC_CF2	(1 << 5)
-#define		AT91_MATRIX_DBPUC		(1 << 8)	/* Data Bus Pull-up Configuration */
-
-#define AT91_MATRIX_USBPUCR	(AT91_MATRIX + 0x34)	/* USB Pad Pull-Up Control Register */
-#define		AT91_MATRIX_USBPUCR_PUON	(1 << 30)	/* USB Device PAD Pull-up Enable */
-
-#endif
diff --git a/arch/arm/include/asm/arch-at91/at91sam9263.h b/arch/arm/include/asm/arch-at91/at91sam9263.h
deleted file mode 100644
index 4ada1ce..0000000
--- a/arch/arm/include/asm/arch-at91/at91sam9263.h
+++ /dev/null
@@ -1,155 +0,0 @@
-/*
- * [origin: Linux kernel include/asm-arm/arch-at91/at91sam9263.h]
- *
- * (C) 2007 Atmel Corporation.
- *
- * Common definitions.
- * Based on AT91SAM9263 datasheet revision B (Preliminary).
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#ifndef AT91SAM9263_H
-#define AT91SAM9263_H
-
-/*
- * Peripheral identifiers/interrupts.
- */
-#define AT91_ID_FIQ		0	/* Advanced Interrupt Controller (FIQ) */
-#define AT91_ID_SYS		1	/* System Peripherals */
-#define AT91SAM9263_ID_PIOA	2	/* Parallel IO Controller A */
-#define AT91SAM9263_ID_PIOB	3	/* Parallel IO Controller B */
-#define AT91SAM9263_ID_PIOCDE	4	/* Parallel IO Controller C, D and E */
-#define AT91SAM9263_ID_US0	7	/* USART 0 */
-#define AT91SAM9263_ID_US1	8	/* USART 1 */
-#define AT91SAM9263_ID_US2	9	/* USART 2 */
-#define AT91SAM9263_ID_MCI0	10	/* Multimedia Card Interface 0 */
-#define AT91SAM9263_ID_MCI1	11	/* Multimedia Card Interface 1 */
-#define AT91SAM9263_ID_CAN	12	/* CAN */
-#define AT91SAM9263_ID_TWI	13	/* Two-Wire Interface */
-#define AT91SAM9263_ID_SPI0	14	/* Serial Peripheral Interface 0 */
-#define AT91SAM9263_ID_SPI1	15	/* Serial Peripheral Interface 1 */
-#define AT91SAM9263_ID_SSC0	16	/* Serial Synchronous Controller 0 */
-#define AT91SAM9263_ID_SSC1	17	/* Serial Synchronous Controller 1 */
-#define AT91SAM9263_ID_AC97C	18	/* AC97 Controller */
-#define AT91SAM9263_ID_TCB	19	/* Timer Counter 0, 1 and 2 */
-#define AT91SAM9263_ID_PWMC	20	/* Pulse Width Modulation Controller */
-#define AT91SAM9263_ID_EMAC	21	/* Ethernet */
-#define AT91SAM9263_ID_2DGE	23	/* 2D Graphic Engine */
-#define AT91SAM9263_ID_UDP	24	/* USB Device Port */
-#define AT91SAM9263_ID_ISI	25	/* Image Sensor Interface */
-#define AT91SAM9263_ID_LCDC	26	/* LCD Controller */
-#define AT91SAM9263_ID_DMA	27	/* DMA Controller */
-#define AT91SAM9263_ID_UHP	29	/* USB Host port */
-#define AT91SAM9263_ID_IRQ0	30	/* Advanced Interrupt Controller (IRQ0) */
-#define AT91SAM9263_ID_IRQ1	31	/* Advanced Interrupt Controller (IRQ1) */
-
-#define AT91_EMAC_BASE		0xfffbc000
-#define AT91_ECC0_BASE		0xffffe000
-#define AT91_SDRAMC0_BASE	0xffffe200
-#define AT91_SMC0_BASE		0xffffe400
-#define AT91_ECC1_BASE		0xffffe600
-#define AT91_SDRAMC1_BASE	0xffffe800
-#define AT91_SMC1_BASE		0xffffea00
-#define AT91_MATRIX_BASE	0xffffec00
-#define AT91_CCFG_BASE		0xffffed10
-#define AT91_DBGU_BASE		0xffffee00
-#define AT91_AIC_BASE		0xfffff000
-#define AT91_PIO_BASE		0xfffff200
-#define AT91_PMC_BASE		0xfffffc00
-#define AT91_RSTC_BASE		0xfffffd00
-#define AT91_RTT0_BASE		0xfffffd20
-#define AT91_PIT_BASE		0xfffffd30
-#define AT91_WDT_BASE		0xfffffd40
-#define AT91_RTT1_BASE		0xfffffd50
-#define AT91_GPBR_BASE		0xfffffd60
-
-#ifdef CONFIG_AT91_LEGACY
-
-/*
- * User Peripheral physical base addresses.
- */
-#define AT91SAM9263_BASE_UDP		0xfff78000
-#define AT91SAM9263_BASE_TCB0		0xfff7c000
-#define AT91SAM9263_BASE_TC0		0xfff7c000
-#define AT91SAM9263_BASE_TC1		0xfff7c040
-#define AT91SAM9263_BASE_TC2		0xfff7c080
-#define AT91SAM9263_BASE_MCI0		0xfff80000
-#define AT91SAM9263_BASE_MCI1		0xfff84000
-#define AT91SAM9263_BASE_TWI		0xfff88000
-#define AT91SAM9263_BASE_US0		0xfff8c000
-#define AT91SAM9263_BASE_US1		0xfff90000
-#define AT91SAM9263_BASE_US2		0xfff94000
-#define AT91SAM9263_BASE_SSC0		0xfff98000
-#define AT91SAM9263_BASE_SSC1		0xfff9c000
-#define AT91SAM9263_BASE_AC97C		0xfffa0000
-#define AT91SAM9263_BASE_SPI0		0xfffa4000
-#define AT91SAM9263_BASE_SPI1		0xfffa8000
-#define AT91SAM9263_BASE_CAN		0xfffac000
-#define AT91SAM9263_BASE_PWMC		0xfffb8000
-#define AT91SAM9263_BASE_EMAC		0xfffbc000
-#define AT91SAM9263_BASE_ISI		0xfffc4000
-#define AT91SAM9263_BASE_2DGE		0xfffc8000
-#define AT91_BASE_SYS			0xffffe000
-
-/*
- * System Peripherals (offset from AT91_BASE_SYS)
- */
-#define AT91_ECC0	(0xffffe000 - AT91_BASE_SYS)
-#define AT91_SDRAMC0	(0xffffe200 - AT91_BASE_SYS)
-#define AT91_SMC0	(0xffffe400 - AT91_BASE_SYS)
-#define AT91_ECC1	(0xffffe600 - AT91_BASE_SYS)
-#define AT91_SDRAMC1	(0xffffe800 - AT91_BASE_SYS)
-#define AT91_SMC1	(0xffffea00 - AT91_BASE_SYS)
-#define AT91_MATRIX	(0xffffec00 - AT91_BASE_SYS)
-#define AT91_CCFG	(0xffffed10 - AT91_BASE_SYS)
-#define AT91_DBGU	(0xffffee00 - AT91_BASE_SYS)
-#define AT91_AIC	(0xfffff000 - AT91_BASE_SYS)
-#define AT91_PIOA	(0xfffff200 - AT91_BASE_SYS)
-#define AT91_PIOB	(0xfffff400 - AT91_BASE_SYS)
-#define AT91_PIOC	(0xfffff600 - AT91_BASE_SYS)
-#define AT91_PIOD	(0xfffff800 - AT91_BASE_SYS)
-#define AT91_PIOE	(0xfffffa00 - AT91_BASE_SYS)
-#define AT91_PMC	(0xfffffc00 - AT91_BASE_SYS)
-#define AT91_RSTC	(0xfffffd00 - AT91_BASE_SYS)
-#define AT91_SHDWC	(0xfffffd10 - AT91_BASE_SYS)
-#define AT91_RTT0	(0xfffffd20 - AT91_BASE_SYS)
-#define AT91_PIT	(0xfffffd30 - AT91_BASE_SYS)
-#define AT91_WDT	(0xfffffd40 - AT91_BASE_SYS)
-#define AT91_RTT1	(0xfffffd50 - AT91_BASE_SYS)
-#define AT91_GPBR	(0xfffffd60 - AT91_BASE_SYS)
-
-#define AT91_USART0	AT91SAM9263_BASE_US0
-#define AT91_USART1	AT91SAM9263_BASE_US1
-#define AT91_USART2	AT91SAM9263_BASE_US2
-
-#define AT91_SMC	AT91_SMC0
-#define AT91_SDRAMC	AT91_SDRAMC0
-
-#endif /* CONFIG_AT91_LEGACY */
-
-/*
- * Internal Memory.
- */
-#define AT91SAM9263_SRAM0_BASE	0x00300000	/* Internal SRAM 0 base address */
-#define AT91SAM9263_SRAM0_SIZE	(80 * SZ_1K)	/* Internal SRAM 0 size (80Kb) */
-
-#define AT91SAM9263_ROM_BASE	0x00400000	/* Internal ROM base address */
-#define AT91SAM9263_ROM_SIZE	SZ_128K		/* Internal ROM size (128Kb) */
-
-#define AT91SAM9263_SRAM1_BASE	0x00500000	/* Internal SRAM 1 base address */
-#define AT91SAM9263_SRAM1_SIZE	SZ_16K		/* Internal SRAM 1 size (16Kb) */
-
-#define AT91SAM9263_LCDC_BASE	0x00700000	/* LCD Controller */
-#define AT91SAM9263_DMAC_BASE	0x00800000	/* DMA Controller */
-#define AT91SAM9263_UHP_BASE	0x00a00000	/* USB Host controller */
-
-/*
- * Cpu Name
- */
-#define CONFIG_SYS_AT91_CPU_NAME	"AT91SAM9263"
-
-#endif
diff --git a/arch/arm/include/asm/arch-at91/at91sam9263_matrix.h b/arch/arm/include/asm/arch-at91/at91sam9263_matrix.h
deleted file mode 100644
index 83aaaab..0000000
--- a/arch/arm/include/asm/arch-at91/at91sam9263_matrix.h
+++ /dev/null
@@ -1,129 +0,0 @@
-/*
- * [origin: Linux kernel include/asm-arm/arch-at91/at91sam9263_matrix.h]
- *
- *  Copyright (C) 2006 Atmel Corporation.
- *
- * Memory Controllers (MATRIX, EBI) - System peripherals registers.
- * Based on AT91SAM9263 datasheet revision B (Preliminary).
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#ifndef AT91SAM9263_MATRIX_H
-#define AT91SAM9263_MATRIX_H
-
-#define AT91_MATRIX_MCFG0	(AT91_MATRIX + 0x00)	/* Master Configuration Register 0 */
-#define AT91_MATRIX_MCFG1	(AT91_MATRIX + 0x04)	/* Master Configuration Register 1 */
-#define AT91_MATRIX_MCFG2	(AT91_MATRIX + 0x08)	/* Master Configuration Register 2 */
-#define AT91_MATRIX_MCFG3	(AT91_MATRIX + 0x0C)	/* Master Configuration Register 3 */
-#define AT91_MATRIX_MCFG4	(AT91_MATRIX + 0x10)	/* Master Configuration Register 4 */
-#define AT91_MATRIX_MCFG5	(AT91_MATRIX + 0x14)	/* Master Configuration Register 5 */
-#define AT91_MATRIX_MCFG6	(AT91_MATRIX + 0x18)	/* Master Configuration Register 6 */
-#define AT91_MATRIX_MCFG7	(AT91_MATRIX + 0x1C)	/* Master Configuration Register 7 */
-#define AT91_MATRIX_MCFG8	(AT91_MATRIX + 0x20)	/* Master Configuration Register 8 */
-#define		AT91_MATRIX_ULBT	(7 << 0)	/* Undefined Length Burst Type */
-#define			AT91_MATRIX_ULBT_INFINITE	(0 << 0)
-#define			AT91_MATRIX_ULBT_SINGLE		(1 << 0)
-#define			AT91_MATRIX_ULBT_FOUR		(2 << 0)
-#define			AT91_MATRIX_ULBT_EIGHT		(3 << 0)
-#define			AT91_MATRIX_ULBT_SIXTEEN	(4 << 0)
-
-#define AT91_MATRIX_SCFG0	(AT91_MATRIX + 0x40)	/* Slave Configuration Register 0 */
-#define AT91_MATRIX_SCFG1	(AT91_MATRIX + 0x44)	/* Slave Configuration Register 1 */
-#define AT91_MATRIX_SCFG2	(AT91_MATRIX + 0x48)	/* Slave Configuration Register 2 */
-#define AT91_MATRIX_SCFG3	(AT91_MATRIX + 0x4C)	/* Slave Configuration Register 3 */
-#define AT91_MATRIX_SCFG4	(AT91_MATRIX + 0x50)	/* Slave Configuration Register 4 */
-#define AT91_MATRIX_SCFG5	(AT91_MATRIX + 0x54)	/* Slave Configuration Register 5 */
-#define AT91_MATRIX_SCFG6	(AT91_MATRIX + 0x58)	/* Slave Configuration Register 6 */
-#define AT91_MATRIX_SCFG7	(AT91_MATRIX + 0x5C)	/* Slave Configuration Register 7 */
-#define		AT91_MATRIX_SLOT_CYCLE		(0xff << 0)	/* Maximum Number of Allowed Cycles for a Burst */
-#define		AT91_MATRIX_DEFMSTR_TYPE	(3    << 16)	/* Default Master Type */
-#define			AT91_MATRIX_DEFMSTR_TYPE_NONE	(0 << 16)
-#define			AT91_MATRIX_DEFMSTR_TYPE_LAST	(1 << 16)
-#define			AT91_MATRIX_DEFMSTR_TYPE_FIXED	(2 << 16)
-#define		AT91_MATRIX_FIXED_DEFMSTR	(0xf  << 18)	/* Fixed Index of Default Master */
-#define		AT91_MATRIX_ARBT		(3    << 24)	/* Arbitration Type */
-#define			AT91_MATRIX_ARBT_ROUND_ROBIN	(0 << 24)
-#define			AT91_MATRIX_ARBT_FIXED_PRIORITY	(1 << 24)
-
-#define AT91_MATRIX_PRAS0	(AT91_MATRIX + 0x80)	/* Priority Register A for Slave 0 */
-#define AT91_MATRIX_PRBS0	(AT91_MATRIX + 0x84)	/* Priority Register B for Slave 0 */
-#define AT91_MATRIX_PRAS1	(AT91_MATRIX + 0x88)	/* Priority Register A for Slave 1 */
-#define AT91_MATRIX_PRBS1	(AT91_MATRIX + 0x8C)	/* Priority Register B for Slave 1 */
-#define AT91_MATRIX_PRAS2	(AT91_MATRIX + 0x90)	/* Priority Register A for Slave 2 */
-#define AT91_MATRIX_PRBS2	(AT91_MATRIX + 0x94)	/* Priority Register B for Slave 2 */
-#define AT91_MATRIX_PRAS3	(AT91_MATRIX + 0x98)	/* Priority Register A for Slave 3 */
-#define AT91_MATRIX_PRBS3	(AT91_MATRIX + 0x9C)	/* Priority Register B for Slave 3 */
-#define AT91_MATRIX_PRAS4	(AT91_MATRIX + 0xA0)	/* Priority Register A for Slave 4 */
-#define AT91_MATRIX_PRBS4	(AT91_MATRIX + 0xA4)	/* Priority Register B for Slave 4 */
-#define AT91_MATRIX_PRAS5	(AT91_MATRIX + 0xA8)	/* Priority Register A for Slave 5 */
-#define AT91_MATRIX_PRBS5	(AT91_MATRIX + 0xAC)	/* Priority Register B for Slave 5 */
-#define AT91_MATRIX_PRAS6	(AT91_MATRIX + 0xB0)	/* Priority Register A for Slave 6 */
-#define AT91_MATRIX_PRBS6	(AT91_MATRIX + 0xB4)	/* Priority Register B for Slave 6 */
-#define AT91_MATRIX_PRAS7	(AT91_MATRIX + 0xB8)	/* Priority Register A for Slave 7 */
-#define AT91_MATRIX_PRBS7	(AT91_MATRIX + 0xBC)	/* Priority Register B for Slave 7 */
-#define		AT91_MATRIX_M0PR		(3 << 0)	/* Master 0 Priority */
-#define		AT91_MATRIX_M1PR		(3 << 4)	/* Master 1 Priority */
-#define		AT91_MATRIX_M2PR		(3 << 8)	/* Master 2 Priority */
-#define		AT91_MATRIX_M3PR		(3 << 12)	/* Master 3 Priority */
-#define		AT91_MATRIX_M4PR		(3 << 16)	/* Master 4 Priority */
-#define		AT91_MATRIX_M5PR		(3 << 20)	/* Master 5 Priority */
-#define		AT91_MATRIX_M6PR		(3 << 24)	/* Master 6 Priority */
-#define		AT91_MATRIX_M7PR		(3 << 28)	/* Master 7 Priority */
-#define		AT91_MATRIX_M8PR		(3 << 0)	/* Master 8 Priority (in Register B) */
-
-#define AT91_MATRIX_MRCR	(AT91_MATRIX + 0x100)	/* Master Remap Control Register */
-#define		AT91_MATRIX_RCB0		(1 << 0)	/* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
-#define		AT91_MATRIX_RCB1		(1 << 1)	/* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
-#define		AT91_MATRIX_RCB2		(1 << 2)
-#define		AT91_MATRIX_RCB3		(1 << 3)
-#define		AT91_MATRIX_RCB4		(1 << 4)
-#define		AT91_MATRIX_RCB5		(1 << 5)
-#define		AT91_MATRIX_RCB6		(1 << 6)
-#define		AT91_MATRIX_RCB7		(1 << 7)
-#define		AT91_MATRIX_RCB8		(1 << 8)
-
-#define AT91_MATRIX_TCMR	(AT91_MATRIX + 0x114)	/* TCM Configuration Register */
-#define		AT91_MATRIX_ITCM_SIZE		(0xf << 0)	/* Size of ITCM enabled memory block */
-#define			AT91_MATRIX_ITCM_0		(0 << 0)
-#define			AT91_MATRIX_ITCM_16		(5 << 0)
-#define			AT91_MATRIX_ITCM_32		(6 << 0)
-#define		AT91_MATRIX_DTCM_SIZE		(0xf << 4)	/* Size of DTCM enabled memory block */
-#define			AT91_MATRIX_DTCM_0		(0 << 4)
-#define			AT91_MATRIX_DTCM_16		(5 << 4)
-#define			AT91_MATRIX_DTCM_32		(6 << 4)
-
-#define AT91_MATRIX_EBI0CSA	(AT91_MATRIX + 0x120)	/* EBI0 Chip Select Assignment Register */
-#define		AT91_MATRIX_EBI0_CS1A		(1 << 1)	/* Chip Select 1 Assignment */
-#define			AT91_MATRIX_EBI0_CS1A_SMC		(0 << 1)
-#define			AT91_MATRIX_EBI0_CS1A_SDRAMC		(1 << 1)
-#define		AT91_MATRIX_EBI0_CS3A		(1 << 3)	/* Chip Select 3 Assignment */
-#define			AT91_MATRIX_EBI0_CS3A_SMC		(0 << 3)
-#define			AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA	(1 << 3)
-#define		AT91_MATRIX_EBI0_CS4A		(1 << 4)	/* Chip Select 4 Assignment */
-#define			AT91_MATRIX_EBI0_CS4A_SMC		(0 << 4)
-#define			AT91_MATRIX_EBI0_CS4A_SMC_CF1		(1 << 4)
-#define		AT91_MATRIX_EBI0_CS5A		(1 << 5)	/* Chip Select 5 Assignment */
-#define			AT91_MATRIX_EBI0_CS5A_SMC		(0 << 5)
-#define			AT91_MATRIX_EBI0_CS5A_SMC_CF2		(1 << 5)
-#define		AT91_MATRIX_EBI0_DBPUC		(1 << 8)	/* Data Bus Pull-up Configuration */
-#define		AT91_MATRIX_EBI0_VDDIOMSEL	(1 << 16)	/* Memory voltage selection */
-#define			AT91_MATRIX_EBI0_VDDIOMSEL_1_8V		(0 << 16)
-#define			AT91_MATRIX_EBI0_VDDIOMSEL_3_3V		(1 << 16)
-
-#define AT91_MATRIX_EBI1CSA	(AT91_MATRIX + 0x124)	/* EBI1 Chip Select Assignment Register */
-#define		AT91_MATRIX_EBI1_CS1A		(1 << 1)	/* Chip Select 1 Assignment */
-#define			AT91_MATRIX_EBI1_CS1A_SMC		(0 << 1)
-#define			AT91_MATRIX_EBI1_CS1A_SDRAMC		(1 << 1)
-#define		AT91_MATRIX_EBI1_CS2A		(1 << 3)	/* Chip Select 3 Assignment */
-#define			AT91_MATRIX_EBI1_CS2A_SMC		(0 << 3)
-#define			AT91_MATRIX_EBI1_CS2A_SMC_SMARTMEDIA	(1 << 3)
-#define		AT91_MATRIX_EBI1_DBPUC		(1 << 8)	/* Data Bus Pull-up Configuration */
-#define		AT91_MATRIX_EBI1_VDDIOMSEL	(1 << 16)	/* Memory voltage selection */
-#define			AT91_MATRIX_EBI1_VDDIOMSEL_1_8V		(0 << 16)
-#define			AT91_MATRIX_EBI1_VDDIOMSEL_3_3V		(1 << 16)
-
-#endif
diff --git a/arch/arm/include/asm/arch-at91/at91sam9_matrix.h b/arch/arm/include/asm/arch-at91/at91sam9_matrix.h
deleted file mode 100644
index 6d97189..0000000
--- a/arch/arm/include/asm/arch-at91/at91sam9_matrix.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jrosoft.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- */
-
-#ifndef __ASM_ARCH_AT91SAM9_MATRIX_H
-#define __ASM_ARCH_AT91SAM9_MATRIX_H
-
-#if defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9G20)
-#include <asm/arch/at91sam9260_matrix.h>
-#elif defined(CONFIG_AT91SAM9261)
-#include <asm/arch/at91sam9261_matrix.h>
-#elif defined(CONFIG_AT91SAM9263)
-#include <asm/arch/at91sam9263_matrix.h>
-#elif defined(CONFIG_AT91SAM9RL)
-#include <asm/arch/at91sam9rl_matrix.h>
-#elif defined(CONFIG_AT91CAP9)
-#include <asm/arch/at91cap9_matrix.h>
-#elif defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45)
-#include <asm/arch/at91sam9g45_matrix.h>
-#else
-#error "Unsupported AT91SAM9/CAP9 processor"
-#endif
-
-#endif /* __ASM_ARCH_AT91SAM9_MATRIX_H */
diff --git a/arch/arm/include/asm/arch-at91/at91sam9_sdramc.h b/arch/arm/include/asm/arch-at91/at91sam9_sdramc.h
deleted file mode 100644
index c3da3a6..0000000
--- a/arch/arm/include/asm/arch-at91/at91sam9_sdramc.h
+++ /dev/null
@@ -1,100 +0,0 @@
-/*
- * [origin: Linux kernel arch/arm/mach-at91/include/mach/at91_wdt.h]
- *
- * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
- * Copyright (C) 2007 Andrew Victor
- * Copyright (C) 2007 Atmel Corporation.
- *
- * SDRAM Controllers (SDRAMC) - System peripherals registers.
- * Based on AT91SAM9261 datasheet revision D.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#ifndef AT91SAM9_SDRAMC_H
-#define AT91SAM9_SDRAMC_H
-
-#ifdef __ASSEMBLY__
-
-#ifndef AT91_SDRAMC_BASE
-#define AT91_SDRAMC_BASE	AT91_SDRAMC0_BASE
-#endif
-
-#define AT91_ASM_SDRAMC_MR	AT91_SDRAMC_BASE
-#define AT91_ASM_SDRAMC_TR	(AT91_SDRAMC_BASE + 0x04)
-#define AT91_ASM_SDRAMC_CR	(AT91_SDRAMC_BASE + 0x08)
-#define AT91_ASM_SDRAMC_MDR	(AT91_SDRAMC_BASE + 0x24)
-
-#endif
-
-/* SDRAM Controller (SDRAMC) registers */
-#define AT91_SDRAMC_MR		(AT91_SDRAMC + 0x00)	/* SDRAM Controller Mode Register */
-#define		AT91_SDRAMC_MODE	(0xf << 0)		/* Command Mode */
-#define			AT91_SDRAMC_MODE_NORMAL		0
-#define			AT91_SDRAMC_MODE_NOP		1
-#define			AT91_SDRAMC_MODE_PRECHARGE	2
-#define			AT91_SDRAMC_MODE_LMR		3
-#define			AT91_SDRAMC_MODE_REFRESH	4
-#define			AT91_SDRAMC_MODE_EXT_LMR	5
-#define			AT91_SDRAMC_MODE_DEEP		6
-
-#define AT91_SDRAMC_TR		(AT91_SDRAMC + 0x04)	/* SDRAM Controller Refresh Timer Register */
-#define		AT91_SDRAMC_COUNT	(0xfff << 0)		/* Refresh Timer Counter */
-
-#define AT91_SDRAMC_CR		(AT91_SDRAMC + 0x08)	/* SDRAM Controller Configuration Register */
-#define		AT91_SDRAMC_NC		(3 << 0)		/* Number of Column Bits */
-#define			AT91_SDRAMC_NC_8	(0 << 0)
-#define			AT91_SDRAMC_NC_9	(1 << 0)
-#define			AT91_SDRAMC_NC_10	(2 << 0)
-#define			AT91_SDRAMC_NC_11	(3 << 0)
-#define		AT91_SDRAMC_NR		(3 << 2)		/* Number of Row Bits */
-#define			AT91_SDRAMC_NR_11	(0 << 2)
-#define			AT91_SDRAMC_NR_12	(1 << 2)
-#define			AT91_SDRAMC_NR_13	(2 << 2)
-#define		AT91_SDRAMC_NB		(1 << 4)		/* Number of Banks */
-#define			AT91_SDRAMC_NB_2	(0 << 4)
-#define			AT91_SDRAMC_NB_4	(1 << 4)
-#define		AT91_SDRAMC_CAS		(3 << 5)		/* CAS Latency */
-#define			AT91_SDRAMC_CAS_1	(1 << 5)
-#define			AT91_SDRAMC_CAS_2	(2 << 5)
-#define			AT91_SDRAMC_CAS_3	(3 << 5)
-#define		AT91_SDRAMC_DBW		(1 << 7)		/* Data Bus Width */
-#define			AT91_SDRAMC_DBW_32	(0 << 7)
-#define			AT91_SDRAMC_DBW_16	(1 << 7)
-#define		AT91_SDRAMC_TWR		(0xf <<  8)		/* Write Recovery Delay */
-#define		AT91_SDRAMC_TRC		(0xf << 12)		/* Row Cycle Delay */
-#define		AT91_SDRAMC_TRP		(0xf << 16)		/* Row Precharge Delay */
-#define		AT91_SDRAMC_TRCD	(0xf << 20)		/* Row to Column Delay */
-#define		AT91_SDRAMC_TRAS	(0xf << 24)		/* Active to Precharge Delay */
-#define		AT91_SDRAMC_TXSR	(0xf << 28)		/* Exit Self Refresh to Active Delay */
-
-#define AT91_SDRAMC_LPR		(AT91_SDRAMC + 0x10)	/* SDRAM Controller Low Power Register */
-#define		AT91_SDRAMC_LPCB		(3 << 0)	/* Low-power Configurations */
-#define			AT91_SDRAMC_LPCB_DISABLE		0
-#define			AT91_SDRAMC_LPCB_SELF_REFRESH		1
-#define			AT91_SDRAMC_LPCB_POWER_DOWN		2
-#define			AT91_SDRAMC_LPCB_DEEP_POWER_DOWN	3
-#define		AT91_SDRAMC_PASR		(7 << 4)	/* Partial Array Self Refresh */
-#define		AT91_SDRAMC_TCSR		(3 << 8)	/* Temperature Compensated Self Refresh */
-#define		AT91_SDRAMC_DS			(3 << 10)	/* Drive Strength */
-#define		AT91_SDRAMC_TIMEOUT		(3 << 12)	/* Time to define when Low Power Mode is enabled */
-#define			AT91_SDRAMC_TIMEOUT_0_CLK_CYCLES	(0 << 12)
-#define			AT91_SDRAMC_TIMEOUT_64_CLK_CYCLES	(1 << 12)
-#define			AT91_SDRAMC_TIMEOUT_128_CLK_CYCLES	(2 << 12)
-
-#define AT91_SDRAMC_IER		(AT91_SDRAMC + 0x14)	/* SDRAM Controller Interrupt Enable Register */
-#define AT91_SDRAMC_IDR		(AT91_SDRAMC + 0x18)	/* SDRAM Controller Interrupt Disable Register */
-#define AT91_SDRAMC_IMR		(AT91_SDRAMC + 0x1C)	/* SDRAM Controller Interrupt Mask Register */
-#define AT91_SDRAMC_ISR		(AT91_SDRAMC + 0x20)	/* SDRAM Controller Interrupt Status Register */
-#define		AT91_SDRAMC_RES		(1 << 0)		/* Refresh Error Status */
-
-#define AT91_SDRAMC_MDR		(AT91_SDRAMC + 0x24)	/* SDRAM Memory Device Register */
-#define		AT91_SDRAMC_MD		(3 << 0)		/* Memory Device Type */
-#define			AT91_SDRAMC_MD_SDRAM		0
-#define			AT91_SDRAMC_MD_LOW_POWER_SDRAM	1
-
-
-#endif
diff --git a/arch/arm/include/asm/arch-at91/at91sam9_smc.h b/arch/arm/include/asm/arch-at91/at91sam9_smc.h
deleted file mode 100644
index d180c8a..0000000
--- a/arch/arm/include/asm/arch-at91/at91sam9_smc.h
+++ /dev/null
@@ -1,139 +0,0 @@
-/*
- * [origin: Linux kernel include/asm-arm/arch-at91/at91sam9_smc.h]
- *
- * Copyright (C) 2007 Andrew Victor
- * Copyright (C) 2007 Atmel Corporation.
- *
- * Static Memory Controllers (SMC) - System peripherals registers.
- * Based on AT91SAM9261 datasheet revision D.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#ifndef AT91SAM9_SMC_H
-#define AT91SAM9_SMC_H
-
-#ifdef __ASSEMBLY__
-
-#ifndef AT91_SMC_BASE
-#define AT91_SMC_BASE	AT91_SMC0_BASE
-#endif
-
-#define AT91_ASM_SMC_SETUP0	AT91_SMC_BASE
-#define AT91_ASM_SMC_PULSE0	(AT91_SMC_BASE + 0x04)
-#define AT91_ASM_SMC_CYCLE0	(AT91_SMC_BASE + 0x08)
-#define AT91_ASM_SMC_MODE0	(AT91_SMC_BASE + 0x0C)
-
-#else
-
-typedef struct	at91_cs {
-	u32	setup;		/* 0x00 SMC Setup Register */
-	u32	pulse;		/* 0x04 SMC Pulse Register */
-	u32	cycle;		/* 0x08 SMC Cycle Register */
-	u32	mode;		/* 0x0C SMC Mode Register */
-} at91_cs_t;
-
-typedef struct	at91_smc {
-	at91_cs_t	cs[8];
-} at91_smc_t;
-
-#endif /*  __ASSEMBLY__ */
-
-#define AT91_SMC_SETUP_NWE(x)		(x & 0x3f)
-#define AT91_SMC_SETUP_NCS_WR(x)	((x & 0x3f) << 8)
-#define AT91_SMC_SETUP_NRD(x)		((x & 0x3f) << 16)
-#define AT91_SMC_SETUP_NCS_RD(x)	((x & 0x3f) << 24)
-
-#define AT91_SMC_PULSE_NWE(x)		(x & 0x7f)
-#define AT91_SMC_PULSE_NCS_WR(x)	((x & 0x7f) << 8)
-#define AT91_SMC_PULSE_NRD(x)		((x & 0x7f) << 16)
-#define AT91_SMC_PULSE_NCS_RD(x)	((x & 0x7f) << 24)
-
-#define AT91_SMC_CYCLE_NWE(x)		(x & 0x1ff)
-#define AT91_SMC_CYCLE_NRD(x)		((x & 0x1ff) << 16)
-
-#define AT91_SMC_MODE_RM_NCS		0x00000000
-#define AT91_SMC_MODE_RM_NRD		0x00000001
-#define AT91_SMC_MODE_WM_NCS		0x00000000
-#define AT91_SMC_MODE_WM_NWE		0x00000002
-
-#define AT91_SMC_MODE_EXNW_DISABLE	0x00000000
-#define AT91_SMC_MODE_EXNW_FROZEN	0x00000020
-#define AT91_SMC_MODE_EXNW_READY	0x00000030
-
-#define AT91_SMC_MODE_BAT		0x00000100
-#define AT91_SMC_MODE_DBW_8		0x00000000
-#define AT91_SMC_MODE_DBW_16		0x00001000
-#define AT91_SMC_MODE_DBW_32		0x00002000
-#define AT91_SMC_MODE_TDF_CYCLE(x)	((x & 0xf) << 16)
-#define AT91_SMC_MODE_TDF		0x00100000
-#define AT91_SMC_MODE_PMEN		0x01000000
-#define AT91_SMC_MODE_PS_4		0x00000000
-#define AT91_SMC_MODE_PS_8		0x10000000
-#define AT91_SMC_MODE_PS_16		0x20000000
-#define AT91_SMC_MODE_PS_32		0x30000000
-
-#ifdef CONFIG_AT91_LEGACY
-
-#define AT91_SMC_SETUP(n)	(AT91_SMC + 0x00 + ((n)*0x10))	/* Setup Register for CS n */
-#define		AT91_SMC_NWESETUP	(0x3f << 0)			/* NWE Setup Length */
-#define			AT91_SMC_NWESETUP_(x)	((x) << 0)
-#define		AT91_SMC_NCS_WRSETUP	(0x3f << 8)			/* NCS Setup Length in Write Access */
-#define			AT91_SMC_NCS_WRSETUP_(x)	((x) << 8)
-#define		AT91_SMC_NRDSETUP	(0x3f << 16)			/* NRD Setup Length */
-#define			AT91_SMC_NRDSETUP_(x)	((x) << 16)
-#define		AT91_SMC_NCS_RDSETUP	(0x3f << 24)			/* NCS Setup Length in Read Access */
-#define			AT91_SMC_NCS_RDSETUP_(x)	((x) << 24)
-
-#define AT91_SMC_PULSE(n)	(AT91_SMC + 0x04 + ((n)*0x10))	/* Pulse Register for CS n */
-#define		AT91_SMC_NWEPULSE	(0x7f <<  0)			/* NWE Pulse Length */
-#define			AT91_SMC_NWEPULSE_(x)	((x) << 0)
-#define		AT91_SMC_NCS_WRPULSE	(0x7f <<  8)			/* NCS Pulse Length in Write Access */
-#define			AT91_SMC_NCS_WRPULSE_(x)((x) << 8)
-#define		AT91_SMC_NRDPULSE	(0x7f << 16)			/* NRD Pulse Length */
-#define			AT91_SMC_NRDPULSE_(x)	((x) << 16)
-#define		AT91_SMC_NCS_RDPULSE	(0x7f << 24)			/* NCS Pulse Length in Read Access */
-#define			AT91_SMC_NCS_RDPULSE_(x)((x) << 24)
-
-#define AT91_SMC_CYCLE(n)	(AT91_SMC + 0x08 + ((n)*0x10))	/* Cycle Register for CS n */
-#define		AT91_SMC_NWECYCLE	(0x1ff << 0 )			/* Total Write Cycle Length */
-#define			AT91_SMC_NWECYCLE_(x)	((x) << 0)
-#define		AT91_SMC_NRDCYCLE	(0x1ff << 16)			/* Total Read Cycle Length */
-#define			AT91_SMC_NRDCYCLE_(x)	((x) << 16)
-
-#define AT91_SMC_MODE(n)	(AT91_SMC + 0x0c + ((n)*0x10))	/* Mode Register for CS n */
-#define		AT91_SMC_READMODE	(1 <<  0)			/* Read Mode */
-#define		AT91_SMC_WRITEMODE	(1 <<  1)			/* Write Mode */
-#define		AT91_SMC_EXNWMODE	(3 <<  4)			/* NWAIT Mode */
-#define			AT91_SMC_EXNWMODE_DISABLE	(0 << 4)
-#define			AT91_SMC_EXNWMODE_FROZEN	(2 << 4)
-#define			AT91_SMC_EXNWMODE_READY		(3 << 4)
-#define		AT91_SMC_BAT		(1 <<  8)			/* Byte Access Type */
-#define			AT91_SMC_BAT_SELECT		(0 << 8)
-#define			AT91_SMC_BAT_WRITE		(1 << 8)
-#define		AT91_SMC_DBW		(3 << 12)			/* Data Bus Width */
-#define			AT91_SMC_DBW_8			(0 << 12)
-#define			AT91_SMC_DBW_16			(1 << 12)
-#define			AT91_SMC_DBW_32			(2 << 12)
-#define		AT91_SMC_TDF		(0xf << 16)			/* Data Float Time. */
-#define			AT91_SMC_TDF_(x)		((x) << 16)
-#define		AT91_SMC_TDFMODE	(1 << 20)			/* TDF Optimization - Enabled */
-#define		AT91_SMC_PMEN		(1 << 24)			/* Page Mode Enabled */
-#define		AT91_SMC_PS		(3 << 28)			/* Page Size */
-#define			AT91_SMC_PS_4			(0 << 28)
-#define			AT91_SMC_PS_8			(1 << 28)
-#define			AT91_SMC_PS_16			(2 << 28)
-#define			AT91_SMC_PS_32			(3 << 28)
-
-#if defined(AT91_SMC1)		/* The AT91SAM9263 has 2 Static Memory contollers */
-#define AT91_SMC1_SETUP(n)	(AT91_SMC1 + 0x00 + ((n)*0x10))	/* Setup Register for CS n */
-#define AT91_SMC1_PULSE(n)	(AT91_SMC1 + 0x04 + ((n)*0x10))	/* Pulse Register for CS n */
-#define AT91_SMC1_CYCLE(n)	(AT91_SMC1 + 0x08 + ((n)*0x10))	/* Cycle Register for CS n */
-#define AT91_SMC1_MODE(n)	(AT91_SMC1 + 0x0c + ((n)*0x10))	/* Mode Register for CS n */
-#endif
-
-#endif
-#endif
diff --git a/arch/arm/include/asm/arch-at91/at91sam9g45.h b/arch/arm/include/asm/arch-at91/at91sam9g45.h
deleted file mode 100644
index 445f4b2..0000000
--- a/arch/arm/include/asm/arch-at91/at91sam9g45.h
+++ /dev/null
@@ -1,152 +0,0 @@
-/*
- * Chip-specific header file for the AT91SAM9M1x family
- *
- *  Copyright (C) 2008 Atmel Corporation.
- *
- * Common definitions.
- * Based on AT91SAM9G45 preliminary datasheet.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#ifndef AT91SAM9G45_H
-#define AT91SAM9G45_H
-
-/*
- * Peripheral identifiers/interrupts.
- */
-#define AT91_ID_FIQ		0	/* Advanced Interrupt Controller (FIQ) */
-#define AT91_ID_SYS		1	/* System Controller Interrupt */
-#define AT91SAM9G45_ID_PIOA	2	/* Parallel I/O Controller A */
-#define AT91SAM9G45_ID_PIOB	3	/* Parallel I/O Controller B */
-#define AT91SAM9G45_ID_PIOC	4	/* Parallel I/O Controller C */
-#define AT91SAM9G45_ID_PIODE	5	/* Parallel I/O Controller D and E */
-#define AT91SAM9G45_ID_TRNG	6	/* True Random Number Generator */
-#define AT91SAM9G45_ID_US0	7	/* USART 0 */
-#define AT91SAM9G45_ID_US1	8	/* USART 1 */
-#define AT91SAM9G45_ID_US2	9	/* USART 2 */
-#define AT91SAM9G45_ID_US3	10	/* USART 3 */
-#define AT91SAM9G45_ID_MCI0	11	/* High Speed Multimedia Card Interface 0 */
-#define AT91SAM9G45_ID_TWI0	12	/* Two-Wire Interface 0 */
-#define AT91SAM9G45_ID_TWI1	13	/* Two-Wire Interface 1 */
-#define AT91SAM9G45_ID_SPI0	14	/* Serial Peripheral Interface 0 */
-#define AT91SAM9G45_ID_SPI1	15	/* Serial Peripheral Interface 1 */
-#define AT91SAM9G45_ID_SSC0	16	/* Synchronous Serial Controller 0 */
-#define AT91SAM9G45_ID_SSC1	17	/* Synchronous Serial Controller 1 */
-#define AT91SAM9G45_ID_TCB	18	/* Timer Counter 0, 1, 2, 3, 4 and 5 */
-#define AT91SAM9G45_ID_PWMC	19	/* Pulse Width Modulation Controller */
-#define AT91SAM9G45_ID_TSC	20	/* Touch Screen ADC Controller */
-#define AT91SAM9G45_ID_DMA	21	/* DMA Controller */
-#define AT91SAM9G45_ID_UHPHS	22	/* USB Host High Speed */
-#define AT91SAM9G45_ID_LCDC	23	/* LCD Controller */
-#define AT91SAM9G45_ID_AC97C	24	/* AC97 Controller */
-#define AT91SAM9G45_ID_EMAC	25	/* Ethernet MAC */
-#define AT91SAM9G45_ID_ISI	26	/* Image Sensor Interface */
-#define AT91SAM9G45_ID_UDPHS	27	/* USB Device High Speed */
-#define AT91SAM9G45_ID_AESTDESSHA 28	/* AES + T-DES + SHA */
-#define AT91SAM9G45_ID_MCI1	29	/* High Speed Multimedia Card Interface 1 */
-#define AT91SAM9G45_ID_VDEC	30	/* Video Decoder */
-#define AT91SAM9G45_ID_IRQ0	31	/* Advanced Interrupt Controller */
-
-#define AT91_EMAC_BASE		0xfffbc000
-#define AT91_SMC_BASE		0xffffe800
-#define AT91_MATRIX_BASE	0xffffea00
-#define AT91_PIO_BASE		0xfffff200
-#define AT91_PMC_BASE		0xfffffc00
-#define AT91_RSTC_BASE		0xfffffd00
-#define AT91_PIT_BASE		0xfffffd30
-#define AT91_WDT_BASE		0xfffffd40
-
-#ifdef CONFIG_AT91_LEGACY
-
-/*
- * User Peripheral physical base addresses.
- */
-#define AT91SAM9G45_BASE_UDPHS		0xfff78000
-#define AT91SAM9G45_BASE_TC0		0xfff7c000
-#define AT91SAM9G45_BASE_TC1		0xfff7c040
-#define AT91SAM9G45_BASE_TC2		0xfff7c080
-#define AT91SAM9G45_BASE_MCI0		0xfff80000
-#define AT91SAM9G45_BASE_TWI0		0xfff84000
-#define AT91SAM9G45_BASE_TWI1		0xfff88000
-#define AT91SAM9G45_BASE_US0		0xfff8c000
-#define AT91SAM9G45_BASE_US1		0xfff90000
-#define AT91SAM9G45_BASE_US2		0xfff94000
-#define AT91SAM9G45_BASE_US3		0xfff98000
-#define AT91SAM9G45_BASE_SSC0		0xfff9c000
-#define AT91SAM9G45_BASE_SSC1		0xfffa0000
-#define AT91SAM9G45_BASE_SPI0		0xfffa4000
-#define AT91SAM9G45_BASE_SPI1		0xfffa8000
-#define AT91SAM9G45_BASE_AC97C		0xfffac000
-#define AT91SAM9G45_BASE_TSC		0xfffb0000
-#define AT91SAM9G45_BASE_ISI		0xfffb4000
-#define AT91SAM9G45_BASE_PWMC		0xfffb8000
-#define AT91SAM9G45_BASE_EMAC		0xfffbc000
-#define AT91SAM9G45_BASE_AES		0xfffc0000
-#define AT91SAM9G45_BASE_TDES		0xfffc4000
-#define AT91SAM9G45_BASE_SHA		0xfffc8000
-#define AT91SAM9G45_BASE_TRNG		0xfffcc000
-#define AT91SAM9G45_BASE_MCI1		0xfffd0000
-#define AT91SAM9G45_BASE_TC3		0xfffd4000
-#define AT91SAM9G45_BASE_TC4		0xfffd4040
-#define AT91SAM9G45_BASE_TC5		0xfffd4080
-#define AT91_BASE_SYS			0xffffe200
-
-/*
- * System Peripherals (offset from AT91_BASE_SYS)
- */
-#define AT91_ECC	(0xffffe200 - AT91_BASE_SYS)
-#define AT91_DDRSDRC1	(0xffffe400 - AT91_BASE_SYS)
-#define AT91_DDRSDRC0	(0xffffe600 - AT91_BASE_SYS)
-#define AT91_SMC	(0xffffe800 - AT91_BASE_SYS)
-#define AT91_MATRIX	(0xffffea00 - AT91_BASE_SYS)
-#define AT91_DMA	(0xffffec00 - AT91_BASE_SYS)
-#define AT91_DBGU	(0xffffee00 - AT91_BASE_SYS)
-#define AT91_AIC	(0xfffff000 - AT91_BASE_SYS)
-#define AT91_PIOA	(0xfffff200 - AT91_BASE_SYS)
-#define AT91_PIOB	(0xfffff400 - AT91_BASE_SYS)
-#define AT91_PIOC	(0xfffff600 - AT91_BASE_SYS)
-#define AT91_PIOD	(0xfffff800 - AT91_BASE_SYS)
-#define AT91_PIOE	(0xfffffa00 - AT91_BASE_SYS)
-#define AT91_PMC	(0xfffffc00 - AT91_BASE_SYS)
-#define AT91_RSTC	(0xfffffd00 - AT91_BASE_SYS)
-#define AT91_SHDWC	(0xfffffd10 - AT91_BASE_SYS)
-#define AT91_RTT	(0xfffffd20 - AT91_BASE_SYS)
-#define AT91_PIT	(0xfffffd30 - AT91_BASE_SYS)
-#define AT91_WDT	(0xfffffd40 - AT91_BASE_SYS)
-#define AT91_GPBR	(0xfffffd60 - AT91_BASE_SYS)
-#define AT91_RTC	(0xfffffdb0 - AT91_BASE_SYS)
-
-#define AT91_USART0	AT91SAM9G45_BASE_US0
-#define AT91_USART1	AT91SAM9G45_BASE_US1
-#define AT91_USART2	AT91SAM9G45_BASE_US2
-#define AT91_USART3	AT91SAM9G45_BASE_US3
-
-#endif
-
-/*
- * Internal Memory.
- */
-#define AT91SAM9G45_SRAM_BASE	0x00300000	/* Internal SRAM base address */
-#define AT91SAM9G45_SRAM_SIZE	SZ_64K		/* Internal SRAM size (64Kb) */
-
-#define AT91SAM9G45_ROM_BASE	0x00400000	/* Internal ROM base address */
-#define AT91SAM9G45_ROM_SIZE	SZ_64K		/* Internal ROM size (64Kb) */
-
-#define AT91SAM9G45_LCDC_BASE	0x00500000	/* LCD Controller */
-#define AT91SAM9G45_UDPHS_FIFO	0x00600000	/* USB Device HS controller */
-#define AT91SAM9G45_HCI_BASE	0x00700000	/* USB Host controller (OHCI) */
-#define AT91SAM9G45_EHCI_BASE	0x00800000	/* USB Host controller (EHCI) */
-#define AT91SAM9G45_VDEC_BASE	0x00900000	/* Video Decoder Controller */
-
-#define CONFIG_DRAM_BASE	AT91_CHIPSELECT_6
-
-/*
- * Cpu Name
- */
-#define CONFIG_SYS_AT91_CPU_NAME	"AT91SAM9G45"
-
-#endif
diff --git a/arch/arm/include/asm/arch-at91/at91sam9g45_matrix.h b/arch/arm/include/asm/arch-at91/at91sam9g45_matrix.h
deleted file mode 100644
index 1620e1b..0000000
--- a/arch/arm/include/asm/arch-at91/at91sam9g45_matrix.h
+++ /dev/null
@@ -1,153 +0,0 @@
-/*
- * Matrix-centric header file for the AT91SAM9M1x family
- *
- *  Copyright (C) 2008 Atmel Corporation.
- *
- * Memory Controllers (MATRIX, EBI) - System peripherals registers.
- * Based on AT91SAM9G45 preliminary datasheet.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#ifndef AT91SAM9G45_MATRIX_H
-#define AT91SAM9G45_MATRIX_H
-
-#define AT91_MATRIX_MCFG0	(AT91_MATRIX + 0x00)	/* Master Configuration Register 0 */
-#define AT91_MATRIX_MCFG1	(AT91_MATRIX + 0x04)	/* Master Configuration Register 1 */
-#define AT91_MATRIX_MCFG2	(AT91_MATRIX + 0x08)	/* Master Configuration Register 2 */
-#define AT91_MATRIX_MCFG3	(AT91_MATRIX + 0x0C)	/* Master Configuration Register 3 */
-#define AT91_MATRIX_MCFG4	(AT91_MATRIX + 0x10)	/* Master Configuration Register 4 */
-#define AT91_MATRIX_MCFG5	(AT91_MATRIX + 0x14)	/* Master Configuration Register 5 */
-#define AT91_MATRIX_MCFG6	(AT91_MATRIX + 0x18)	/* Master Configuration Register 6 */
-#define AT91_MATRIX_MCFG7	(AT91_MATRIX + 0x1C)	/* Master Configuration Register 7 */
-#define AT91_MATRIX_MCFG8	(AT91_MATRIX + 0x20)	/* Master Configuration Register 8 */
-#define AT91_MATRIX_MCFG9	(AT91_MATRIX + 0x24)	/* Master Configuration Register 9 */
-#define AT91_MATRIX_MCFG10	(AT91_MATRIX + 0x28)	/* Master Configuration Register 10 */
-#define AT91_MATRIX_MCFG11	(AT91_MATRIX + 0x2C)	/* Master Configuration Register 11 */
-#define		AT91_MATRIX_ULBT	(7 << 0)	/* Undefined Length Burst Type */
-#define			AT91_MATRIX_ULBT_INFINITE	(0 << 0)
-#define			AT91_MATRIX_ULBT_SINGLE		(1 << 0)
-#define			AT91_MATRIX_ULBT_FOUR		(2 << 0)
-#define			AT91_MATRIX_ULBT_EIGHT		(3 << 0)
-#define			AT91_MATRIX_ULBT_SIXTEEN	(4 << 0)
-#define			AT91_MATRIX_ULBT_THIRTYTWO	(5 << 0)
-#define			AT91_MATRIX_ULBT_SIXTYFOUR	(6 << 0)
-#define			AT91_MATRIX_ULBT_128		(7 << 0)
-
-#define AT91_MATRIX_SCFG0	(AT91_MATRIX + 0x40)	/* Slave Configuration Register 0 */
-#define AT91_MATRIX_SCFG1	(AT91_MATRIX + 0x44)	/* Slave Configuration Register 1 */
-#define AT91_MATRIX_SCFG2	(AT91_MATRIX + 0x48)	/* Slave Configuration Register 2 */
-#define AT91_MATRIX_SCFG3	(AT91_MATRIX + 0x4C)	/* Slave Configuration Register 3 */
-#define AT91_MATRIX_SCFG4	(AT91_MATRIX + 0x50)	/* Slave Configuration Register 4 */
-#define AT91_MATRIX_SCFG5	(AT91_MATRIX + 0x54)	/* Slave Configuration Register 5 */
-#define AT91_MATRIX_SCFG6	(AT91_MATRIX + 0x58)	/* Slave Configuration Register 6 */
-#define AT91_MATRIX_SCFG7	(AT91_MATRIX + 0x5C)	/* Slave Configuration Register 7 */
-#define		AT91_MATRIX_SLOT_CYCLE		(0x1ff << 0)	/* Maximum Number of Allowed Cycles for a Burst */
-#define		AT91_MATRIX_DEFMSTR_TYPE	(3    << 16)	/* Default Master Type */
-#define			AT91_MATRIX_DEFMSTR_TYPE_NONE	(0 << 16)
-#define			AT91_MATRIX_DEFMSTR_TYPE_LAST	(1 << 16)
-#define			AT91_MATRIX_DEFMSTR_TYPE_FIXED	(2 << 16)
-#define		AT91_MATRIX_FIXED_DEFMSTR	(0xf  << 18)	/* Fixed Index of Default Master */
-
-#define AT91_MATRIX_PRAS0	(AT91_MATRIX + 0x80)	/* Priority Register A for Slave 0 */
-#define AT91_MATRIX_PRBS0	(AT91_MATRIX + 0x84)	/* Priority Register B for Slave 0 */
-#define AT91_MATRIX_PRAS1	(AT91_MATRIX + 0x88)	/* Priority Register A for Slave 1 */
-#define AT91_MATRIX_PRBS1	(AT91_MATRIX + 0x8C)	/* Priority Register B for Slave 1 */
-#define AT91_MATRIX_PRAS2	(AT91_MATRIX + 0x90)	/* Priority Register A for Slave 2 */
-#define AT91_MATRIX_PRBS2	(AT91_MATRIX + 0x94)	/* Priority Register B for Slave 2 */
-#define AT91_MATRIX_PRAS3	(AT91_MATRIX + 0x98)	/* Priority Register A for Slave 3 */
-#define AT91_MATRIX_PRBS3	(AT91_MATRIX + 0x9C)	/* Priority Register B for Slave 3 */
-#define AT91_MATRIX_PRAS4	(AT91_MATRIX + 0xA0)	/* Priority Register A for Slave 4 */
-#define AT91_MATRIX_PRBS4	(AT91_MATRIX + 0xA4)	/* Priority Register B for Slave 4 */
-#define AT91_MATRIX_PRAS5	(AT91_MATRIX + 0xA8)	/* Priority Register A for Slave 5 */
-#define AT91_MATRIX_PRBS5	(AT91_MATRIX + 0xAC)	/* Priority Register B for Slave 5 */
-#define AT91_MATRIX_PRAS6	(AT91_MATRIX + 0xB0)	/* Priority Register A for Slave 6 */
-#define AT91_MATRIX_PRBS6	(AT91_MATRIX + 0xB4)	/* Priority Register B for Slave 6 */
-#define AT91_MATRIX_PRAS7	(AT91_MATRIX + 0xB8)	/* Priority Register A for Slave 7 */
-#define AT91_MATRIX_PRBS7	(AT91_MATRIX + 0xBC)	/* Priority Register B for Slave 7 */
-#define		AT91_MATRIX_M0PR		(3 << 0)	/* Master 0 Priority */
-#define		AT91_MATRIX_M1PR		(3 << 4)	/* Master 1 Priority */
-#define		AT91_MATRIX_M2PR		(3 << 8)	/* Master 2 Priority */
-#define		AT91_MATRIX_M3PR		(3 << 12)	/* Master 3 Priority */
-#define		AT91_MATRIX_M4PR		(3 << 16)	/* Master 4 Priority */
-#define		AT91_MATRIX_M5PR		(3 << 20)	/* Master 5 Priority */
-#define		AT91_MATRIX_M6PR		(3 << 24)	/* Master 6 Priority */
-#define		AT91_MATRIX_M7PR		(3 << 28)	/* Master 7 Priority */
-#define		AT91_MATRIX_M8PR		(3 << 0)	/* Master 8 Priority (in Register B) */
-#define		AT91_MATRIX_M9PR		(3 << 4)	/* Master 9 Priority (in Register B) */
-#define		AT91_MATRIX_M10PR		(3 << 8)	/* Master 10 Priority (in Register B) */
-#define		AT91_MATRIX_M11PR		(3 << 12)	/* Master 11 Priority (in Register B) */
-
-#define AT91_MATRIX_MRCR	(AT91_MATRIX + 0x100)	/* Master Remap Control Register */
-#define		AT91_MATRIX_RCB0		(1 << 0)	/* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
-#define		AT91_MATRIX_RCB1		(1 << 1)	/* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
-#define		AT91_MATRIX_RCB2		(1 << 2)
-#define		AT91_MATRIX_RCB3		(1 << 3)
-#define		AT91_MATRIX_RCB4		(1 << 4)
-#define		AT91_MATRIX_RCB5		(1 << 5)
-#define		AT91_MATRIX_RCB6		(1 << 6)
-#define		AT91_MATRIX_RCB7		(1 << 7)
-#define		AT91_MATRIX_RCB8		(1 << 8)
-#define		AT91_MATRIX_RCB9		(1 << 9)
-#define		AT91_MATRIX_RCB10		(1 << 10)
-#define		AT91_MATRIX_RCB11		(1 << 11)
-
-#define AT91_MATRIX_TCMR	(AT91_MATRIX + 0x110)	/* TCM Configuration Register */
-#define		AT91_MATRIX_ITCM_SIZE		(0xf << 0)	/* Size of ITCM enabled memory block */
-#define			AT91_MATRIX_ITCM_0		(0 << 0)
-#define			AT91_MATRIX_ITCM_32		(6 << 0)
-#define		AT91_MATRIX_DTCM_SIZE		(0xf << 4)	/* Size of DTCM enabled memory block */
-#define			AT91_MATRIX_DTCM_0		(0 << 4)
-#define			AT91_MATRIX_DTCM_32		(6 << 4)
-#define			AT91_MATRIX_DTCM_64		(7 << 4)
-#define		AT91_MATRIX_TCM_NWS		(0x1 << 11)	/* Wait state TCM register */
-#define			AT91_MATRIX_TCM_NO_WS		(0x0 << 11)
-#define			AT91_MATRIX_TCM_ONE_WS		(0x1 << 11)
-
-#define AT91_MATRIX_VIDEO	(AT91_MATRIX + 0x118)	/* Video Mode Configuration Register */
-#define		AT91C_VDEC_SEL			(0x1 <<  0) /* Video Mode Selection */
-#define			AT91C_VDEC_SEL_OFF		(0 << 0)
-#define			AT91C_VDEC_SEL_ON		(1 << 0)
-
-#define AT91_MATRIX_EBICSA	(AT91_MATRIX + 0x128)	/* EBI Chip Select Assignment Register */
-#define		AT91_MATRIX_EBI_CS1A		(1 << 1)	/* Chip Select 1 Assignment */
-#define			AT91_MATRIX_EBI_CS1A_SMC		(0 << 1)
-#define			AT91_MATRIX_EBI_CS1A_SDRAMC		(1 << 1)
-#define		AT91_MATRIX_EBI_CS3A		(1 << 3)	/* Chip Select 3 Assignment */
-#define			AT91_MATRIX_EBI_CS3A_SMC		(0 << 3)
-#define			AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA	(1 << 3)
-#define		AT91_MATRIX_EBI_CS4A		(1 << 4)	/* Chip Select 4 Assignment */
-#define			AT91_MATRIX_EBI_CS4A_SMC		(0 << 4)
-#define			AT91_MATRIX_EBI_CS4A_SMC_CF0		(1 << 4)
-#define		AT91_MATRIX_EBI_CS5A		(1 << 5)	/* Chip Select 5 Assignment */
-#define			AT91_MATRIX_EBI_CS5A_SMC		(0 << 5)
-#define			AT91_MATRIX_EBI_CS5A_SMC_CF1		(1 << 5)
-#define		AT91_MATRIX_EBI_DBPUC		(1 << 8)	/* Data Bus Pull-up Configuration */
-#define			AT91_MATRIX_EBI_DBPU_ON			(0 << 8)
-#define			AT91_MATRIX_EBI_DBPU_OFF		(1 << 8)
-#define		AT91_MATRIX_EBI_VDDIOMSEL	(1 << 16)	/* Memory voltage selection */
-#define			AT91_MATRIX_EBI_VDDIOMSEL_1_8V		(0 << 16)
-#define			AT91_MATRIX_EBI_VDDIOMSEL_3_3V		(1 << 16)
-#define		AT91_MATRIX_EBI_EBI_IOSR	(1 << 17)	/* EBI I/O slew rate selection */
-#define			AT91_MATRIX_EBI_EBI_IOSR_REDUCED	(0 << 17)
-#define			AT91_MATRIX_EBI_EBI_IOSR_NORMAL		(1 << 17)
-#define		AT91_MATRIX_EBI_DDR_IOSR	(1 << 18)	/* DDR2 dedicated port I/O slew rate selection */
-#define			AT91_MATRIX_EBI_DDR_IOSR_REDUCED	(0 << 18)
-#define			AT91_MATRIX_EBI_DDR_IOSR_NORMAL		(1 << 18)
-
-#define AT91_MATRIX_WPMR	(AT91_MATRIX + 0x1E4)	/* Write Protect Mode Register */
-#define		AT91_MATRIX_WPMR_WPEN		(1 << 0)	/* Write Protect ENable */
-#define			AT91_MATRIX_WPMR_WP_WPDIS		(0 << 0)
-#define			AT91_MATRIX_WPMR_WP_WPEN		(1 << 0)
-#define		AT91_MATRIX_WPMR_WPKEY		(0xFFFFFF << 8)	/* Write Protect KEY */
-
-#define AT91_MATRIX_WPSR	(AT91_MATRIX + 0x1E8)	/* Write Protect Status Register */
-#define		AT91_MATRIX_WPSR_WPVS		(1 << 0)	/* Write Protect Violation Status */
-#define			AT91_MATRIX_WPSR_NO_WPV		(0 << 0)
-#define			AT91_MATRIX_WPSR_WPV		(1 << 0)
-#define		AT91_MATRIX_WPSR_WPVSRC		(0xFFFF << 8)	/* Write Protect Violation Source */
-
-#endif
diff --git a/arch/arm/include/asm/arch-at91/at91sam9rl.h b/arch/arm/include/asm/arch-at91/at91sam9rl.h
deleted file mode 100644
index 8eb0d4f..0000000
--- a/arch/arm/include/asm/arch-at91/at91sam9rl.h
+++ /dev/null
@@ -1,130 +0,0 @@
-/*
- * [origin: Linux kernel include/asm-arm/arch-at91/at91sam9rl.h]
- *
- *  Copyright (C) 2007 Atmel Corporation
- *
- * Common definitions.
- * Based on AT91SAM9RL datasheet revision A. (Preliminary)
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file COPYING in the main directory of this archive for
- * more details.
- */
-
-#ifndef AT91SAM9RL_H
-#define AT91SAM9RL_H
-
-/*
- * Peripheral identifiers/interrupts.
- */
-#define AT91_ID_FIQ		0	/* Advanced Interrupt Controller (FIQ) */
-#define AT91_ID_SYS		1	/* System Controller */
-#define AT91SAM9RL_ID_PIOA	2	/* Parallel IO Controller A */
-#define AT91SAM9RL_ID_PIOB	3	/* Parallel IO Controller B */
-#define AT91SAM9RL_ID_PIOC	4	/* Parallel IO Controller C */
-#define AT91SAM9RL_ID_PIOD	5	/* Parallel IO Controller D */
-#define AT91SAM9RL_ID_US0	6	/* USART 0 */
-#define AT91SAM9RL_ID_US1	7	/* USART 1 */
-#define AT91SAM9RL_ID_US2	8	/* USART 2 */
-#define AT91SAM9RL_ID_US3	9	/* USART 3 */
-#define AT91SAM9RL_ID_MCI	10	/* Multimedia Card Interface */
-#define AT91SAM9RL_ID_TWI0	11	/* TWI 0 */
-#define AT91SAM9RL_ID_TWI1	12	/* TWI 1 */
-#define AT91SAM9RL_ID_SPI	13	/* Serial Peripheral Interface */
-#define AT91SAM9RL_ID_SSC0	14	/* Serial Synchronous Controller 0 */
-#define AT91SAM9RL_ID_SSC1	15	/* Serial Synchronous Controller 1 */
-#define AT91SAM9RL_ID_TC0	16	/* Timer Counter 0 */
-#define AT91SAM9RL_ID_TC1	17	/* Timer Counter 1 */
-#define AT91SAM9RL_ID_TC2	18	/* Timer Counter 2 */
-#define AT91SAM9RL_ID_PWMC	19	/* Pulse Width Modulation Controller */
-#define AT91SAM9RL_ID_TSC	20	/* Touch Screen Controller */
-#define AT91SAM9RL_ID_DMA	21	/* DMA Controller */
-#define AT91SAM9RL_ID_UDPHS	22	/* USB Device HS */
-#define AT91SAM9RL_ID_LCDC	23	/* LCD Controller */
-#define AT91SAM9RL_ID_AC97C	24	/* AC97 Controller */
-#define AT91SAM9RL_ID_IRQ0	31	/* Advanced Interrupt Controller (IRQ0) */
-
-#define AT91_SDRAMC_BASE	0xffffea00
-#define AT91_SMC_BASE		0xffffec00
-#define AT91_MATRIX_BASE	0xffffee00
-#define AT91_PIO_BASE		0xfffff400
-#define AT91_PMC_BASE		0xfffffc00
-#define AT91_RSTC_BASE		0xfffffd00
-#define AT91_PIT_BASE		0xfffffd30
-#define AT91_WDT_BASE		0xfffffd40
-
-#ifdef CONFIG_AT91_LEGACY
-
-/*
- * User Peripheral physical base addresses.
- */
-#define AT91SAM9RL_BASE_TCB0	0xfffa0000
-#define AT91SAM9RL_BASE_TC0	0xfffa0000
-#define AT91SAM9RL_BASE_TC1	0xfffa0040
-#define AT91SAM9RL_BASE_TC2	0xfffa0080
-#define AT91SAM9RL_BASE_MCI	0xfffa4000
-#define AT91SAM9RL_BASE_TWI0	0xfffa8000
-#define AT91SAM9RL_BASE_TWI1	0xfffac000
-#define AT91SAM9RL_BASE_US0	0xfffb0000
-#define AT91SAM9RL_BASE_US1	0xfffb4000
-#define AT91SAM9RL_BASE_US2	0xfffb8000
-#define AT91SAM9RL_BASE_US3	0xfffbc000
-#define AT91SAM9RL_BASE_SSC0	0xfffc0000
-#define AT91SAM9RL_BASE_SSC1	0xfffc4000
-#define AT91SAM9RL_BASE_PWMC	0xfffc8000
-#define AT91SAM9RL_BASE_SPI	0xfffcc000
-#define AT91SAM9RL_BASE_TSC	0xfffd0000
-#define AT91SAM9RL_BASE_UDPHS	0xfffd4000
-#define AT91SAM9RL_BASE_AC97C	0xfffd8000
-#define AT91_BASE_SYS		0xffffc000
-
-/*
- * System Peripherals (offset from AT91_BASE_SYS)
- */
-#define AT91_DMA	(0xffffe600 - AT91_BASE_SYS)
-#define AT91_ECC	(0xffffe800 - AT91_BASE_SYS)
-#define AT91_SDRAMC	(0xffffea00 - AT91_BASE_SYS)
-#define AT91_SMC	(0xffffec00 - AT91_BASE_SYS)
-#define AT91_MATRIX	(0xffffee00 - AT91_BASE_SYS)
-#define AT91_CCFG	(0xffffef10 - AT91_BASE_SYS)
-#define AT91_AIC	(0xfffff000 - AT91_BASE_SYS)
-#define AT91_DBGU	(0xfffff200 - AT91_BASE_SYS)
-#define AT91_PIOA	(0xfffff400 - AT91_BASE_SYS)
-#define AT91_PIOB	(0xfffff600 - AT91_BASE_SYS)
-#define AT91_PIOC	(0xfffff800 - AT91_BASE_SYS)
-#define AT91_PIOD	(0xfffffa00 - AT91_BASE_SYS)
-#define AT91_PMC	(0xfffffc00 - AT91_BASE_SYS)
-#define AT91_RSTC	(0xfffffd00 - AT91_BASE_SYS)
-#define AT91_SHDWC	(0xfffffd10 - AT91_BASE_SYS)
-#define AT91_RTT	(0xfffffd20 - AT91_BASE_SYS)
-#define AT91_PIT	(0xfffffd30 - AT91_BASE_SYS)
-#define AT91_WDT	(0xfffffd40 - AT91_BASE_SYS)
-#define AT91_SCKCR	(0xfffffd50 - AT91_BASE_SYS)
-#define AT91_GPBR	(0xfffffd60 - AT91_BASE_SYS)
-#define AT91_RTC	(0xfffffe00 - AT91_BASE_SYS)
-
-#define AT91_USART0	AT91SAM9RL_BASE_US0
-#define AT91_USART1	AT91SAM9RL_BASE_US1
-#define AT91_USART2	AT91SAM9RL_BASE_US2
-#define AT91_USART3	AT91SAM9RL_BASE_US3
-
-#endif /* CONFIG_AT91_LEGACY */
-
-/*
- * Internal Memory.
- */
-#define AT91SAM9RL_SRAM_BASE	0x00300000	/* Internal SRAM base address */
-#define AT91SAM9RL_SRAM_SIZE	SZ_16K		/* Internal SRAM size (16Kb) */
-
-#define AT91SAM9RL_ROM_BASE	0x00400000	/* Internal ROM base address */
-#define AT91SAM9RL_ROM_SIZE	(2 * SZ_16K)	/* Internal ROM size (32Kb) */
-
-#define AT91SAM9RL_LCDC_BASE	0x00500000	/* LCD Controller */
-#define AT91SAM9RL_UDPHS_BASE	0x00600000	/* USB Device HS controller */
-
-/*
- * Cpu Name
- */
-#define CONFIG_SYS_AT91_CPU_NAME	"AT91SAM9RL"
-
-#endif
diff --git a/arch/arm/include/asm/arch-at91/at91sam9rl_matrix.h b/arch/arm/include/asm/arch-at91/at91sam9rl_matrix.h
deleted file mode 100644
index af8d914..0000000
--- a/arch/arm/include/asm/arch-at91/at91sam9rl_matrix.h
+++ /dev/null
@@ -1,96 +0,0 @@
-/*
- * [origin: Linux kernel include/asm-arm/arch-at91/at91sam9rl_matrix.h]
- *
- *  Copyright (C) 2007 Atmel Corporation
- *
- * Memory Controllers (MATRIX, EBI) - System peripherals registers.
- * Based on AT91SAM9RL datasheet revision A. (Preliminary)
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file COPYING in the main directory of this archive for
- * more details.
- */
-
-#ifndef AT91SAM9RL_MATRIX_H
-#define AT91SAM9RL_MATRIX_H
-
-#define AT91_MATRIX_MCFG0	(AT91_MATRIX + 0x00)	/* Master Configuration Register 0 */
-#define AT91_MATRIX_MCFG1	(AT91_MATRIX + 0x04)	/* Master Configuration Register 1 */
-#define AT91_MATRIX_MCFG2	(AT91_MATRIX + 0x08)	/* Master Configuration Register 2 */
-#define AT91_MATRIX_MCFG3	(AT91_MATRIX + 0x0C)	/* Master Configuration Register 3 */
-#define AT91_MATRIX_MCFG4	(AT91_MATRIX + 0x10)	/* Master Configuration Register 4 */
-#define AT91_MATRIX_MCFG5	(AT91_MATRIX + 0x14)	/* Master Configuration Register 5 */
-#define		AT91_MATRIX_ULBT	(7 << 0)	/* Undefined Length Burst Type */
-#define			AT91_MATRIX_ULBT_INFINITE	(0 << 0)
-#define			AT91_MATRIX_ULBT_SINGLE		(1 << 0)
-#define			AT91_MATRIX_ULBT_FOUR		(2 << 0)
-#define			AT91_MATRIX_ULBT_EIGHT		(3 << 0)
-#define			AT91_MATRIX_ULBT_SIXTEEN	(4 << 0)
-
-#define AT91_MATRIX_SCFG0	(AT91_MATRIX + 0x40)	/* Slave Configuration Register 0 */
-#define AT91_MATRIX_SCFG1	(AT91_MATRIX + 0x44)	/* Slave Configuration Register 1 */
-#define AT91_MATRIX_SCFG2	(AT91_MATRIX + 0x48)	/* Slave Configuration Register 2 */
-#define AT91_MATRIX_SCFG3	(AT91_MATRIX + 0x4C)	/* Slave Configuration Register 3 */
-#define AT91_MATRIX_SCFG4	(AT91_MATRIX + 0x50)	/* Slave Configuration Register 4 */
-#define AT91_MATRIX_SCFG5	(AT91_MATRIX + 0x54)	/* Slave Configuration Register 5 */
-#define		AT91_MATRIX_SLOT_CYCLE		(0xff << 0)	/* Maximum Number of Allowed Cycles for a Burst */
-#define		AT91_MATRIX_DEFMSTR_TYPE	(3    << 16)	/* Default Master Type */
-#define			AT91_MATRIX_DEFMSTR_TYPE_NONE	(0 << 16)
-#define			AT91_MATRIX_DEFMSTR_TYPE_LAST	(1 << 16)
-#define			AT91_MATRIX_DEFMSTR_TYPE_FIXED	(2 << 16)
-#define		AT91_MATRIX_FIXED_DEFMSTR	(0xf  << 18)	/* Fixed Index of Default Master */
-#define		AT91_MATRIX_ARBT		(3    << 24)	/* Arbitration Type */
-#define			AT91_MATRIX_ARBT_ROUND_ROBIN	(0 << 24)
-#define			AT91_MATRIX_ARBT_FIXED_PRIORITY	(1 << 24)
-
-#define AT91_MATRIX_PRAS0	(AT91_MATRIX + 0x80)	/* Priority Register A for Slave 0 */
-#define AT91_MATRIX_PRAS1	(AT91_MATRIX + 0x88)	/* Priority Register A for Slave 1 */
-#define AT91_MATRIX_PRAS2	(AT91_MATRIX + 0x90)	/* Priority Register A for Slave 2 */
-#define AT91_MATRIX_PRAS3	(AT91_MATRIX + 0x98)	/* Priority Register A for Slave 3 */
-#define AT91_MATRIX_PRAS4	(AT91_MATRIX + 0xA0)	/* Priority Register A for Slave 4 */
-#define AT91_MATRIX_PRAS5	(AT91_MATRIX + 0xA8)	/* Priority Register A for Slave 5 */
-#define		AT91_MATRIX_M0PR		(3 << 0)	/* Master 0 Priority */
-#define		AT91_MATRIX_M1PR		(3 << 4)	/* Master 1 Priority */
-#define		AT91_MATRIX_M2PR		(3 << 8)	/* Master 2 Priority */
-#define		AT91_MATRIX_M3PR		(3 << 12)	/* Master 3 Priority */
-#define		AT91_MATRIX_M4PR		(3 << 16)	/* Master 4 Priority */
-#define		AT91_MATRIX_M5PR		(3 << 20)	/* Master 5 Priority */
-
-#define AT91_MATRIX_MRCR	(AT91_MATRIX + 0x100)	/* Master Remap Control Register */
-#define		AT91_MATRIX_RCB0		(1 << 0)	/* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
-#define		AT91_MATRIX_RCB1		(1 << 1)	/* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
-#define		AT91_MATRIX_RCB2		(1 << 2)
-#define		AT91_MATRIX_RCB3		(1 << 3)
-#define		AT91_MATRIX_RCB4		(1 << 4)
-#define		AT91_MATRIX_RCB5		(1 << 5)
-
-#define AT91_MATRIX_TCMR	(AT91_MATRIX + 0x114)	/* TCM Configuration Register */
-#define		AT91_MATRIX_ITCM_SIZE		(0xf << 0)	/* Size of ITCM enabled memory block */
-#define			AT91_MATRIX_ITCM_0		(0 << 0)
-#define			AT91_MATRIX_ITCM_16		(5 << 0)
-#define			AT91_MATRIX_ITCM_32		(6 << 0)
-#define		AT91_MATRIX_DTCM_SIZE		(0xf << 4)	/* Size of DTCM enabled memory block */
-#define			AT91_MATRIX_DTCM_0		(0 << 4)
-#define			AT91_MATRIX_DTCM_16		(5 << 4)
-#define			AT91_MATRIX_DTCM_32		(6 << 4)
-
-#define AT91_MATRIX_EBICSA	(AT91_MATRIX + 0x120)	/* EBI0 Chip Select Assignment Register */
-#define		AT91_MATRIX_CS1A		(1 << 1)	/* Chip Select 1 Assignment */
-#define			AT91_MATRIX_CS1A_SMC		(0 << 1)
-#define			AT91_MATRIX_CS1A_SDRAMC		(1 << 1)
-#define		AT91_MATRIX_CS3A		(1 << 3)	/* Chip Select 3 Assignment */
-#define			AT91_MATRIX_CS3A_SMC		(0 << 3)
-#define			AT91_MATRIX_CS3A_SMC_SMARTMEDIA	(1 << 3)
-#define		AT91_MATRIX_CS4A		(1 << 4)	/* Chip Select 4 Assignment */
-#define			AT91_MATRIX_CS4A_SMC		(0 << 4)
-#define			AT91_MATRIX_CS4A_SMC_CF1	(1 << 4)
-#define		AT91_MATRIX_CS5A		(1 << 5)	/* Chip Select 5 Assignment */
-#define			AT91_MATRIX_CS5A_SMC		(0 << 5)
-#define			AT91_MATRIX_CS5A_SMC_CF2	(1 << 5)
-#define		AT91_MATRIX_DBPUC		(1 << 8)	/* Data Bus Pull-up Configuration */
-#define		AT91_MATRIX_VDDIOMSEL		(1 << 16)	/* Memory voltage selection */
-#define			AT91_MATRIX_VDDIOMSEL_1_8V	(0 << 16)
-#define			AT91_MATRIX_VDDIOMSEL_3_3V	(1 << 16)
-
-
-#endif
diff --git a/arch/arm/include/asm/arch-at91/clk.h b/arch/arm/include/asm/arch-at91/clk.h
deleted file mode 100644
index 457e6c9..0000000
--- a/arch/arm/include/asm/arch-at91/clk.h
+++ /dev/null
@@ -1,68 +0,0 @@
-/*
- * (C) Copyright 2007
- * Stelian Pop <stelian.pop@leadtechdesign.com>
- * Lead Tech Design <www.leadtechdesign.com>
- * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-#ifndef __ASM_ARM_ARCH_CLK_H__
-#define __ASM_ARM_ARCH_CLK_H__
-
-#include <asm/arch/hardware.h>
-
-unsigned long get_cpu_clk_rate(void);
-unsigned long get_main_clk_rate(void);
-unsigned long get_mck_clk_rate(void);
-unsigned long get_plla_clk_rate(void);
-unsigned long get_pllb_clk_rate(void);
-unsigned int  get_pllb_init(void);
-
-static inline unsigned long get_macb_pclk_rate(unsigned int dev_id)
-{
-	return get_mck_clk_rate();
-}
-
-static inline unsigned long get_usart_clk_rate(unsigned int dev_id)
-{
-	return get_mck_clk_rate();
-}
-
-static inline unsigned long get_lcdc_clk_rate(unsigned int dev_id)
-{
-	return get_mck_clk_rate();
-}
-
-static inline unsigned long get_spi_clk_rate(unsigned int dev_id)
-{
-	return get_mck_clk_rate();
-}
-
-static inline unsigned long get_twi_clk_rate(unsigned int dev_id)
-{
-	return get_mck_clk_rate();
-}
-
-static inline unsigned long get_mci_clk_rate(void)
-{
-	return get_mck_clk_rate();
-}
-
-int at91_clock_init(unsigned long main_clock);
-#endif /* __ASM_ARM_ARCH_CLK_H__ */
diff --git a/arch/arm/include/asm/arch-at91/gpio.h b/arch/arm/include/asm/arch-at91/gpio.h
deleted file mode 100644
index 716f81f..0000000
--- a/arch/arm/include/asm/arch-at91/gpio.h
+++ /dev/null
@@ -1,238 +0,0 @@
-/*
- * [origin: Linux kernel include/asm-arm/arch-at91/gpio.h]
- *
- *  Copyright (C) 2005 HP Labs
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- */
-
-#ifndef __ASM_ARCH_AT91_GPIO_H
-#define __ASM_ARCH_AT91_GPIO_H
-
-#include <asm/io.h>
-#include <asm/errno.h>
-#include <asm/arch/at91_pio.h>
-#include <asm/arch/hardware.h>
-
-#ifdef CONFIG_AT91_LEGACY
-
-#define PIN_BASE		32
-
-#define MAX_GPIO_BANKS		5
-
-/* these pin numbers double as IRQ numbers, like AT91xxx_ID_* values */
-
-#define	AT91_PIN_PA0	(PIN_BASE + 0x00 + 0)
-#define	AT91_PIN_PA1	(PIN_BASE + 0x00 + 1)
-#define	AT91_PIN_PA2	(PIN_BASE + 0x00 + 2)
-#define	AT91_PIN_PA3	(PIN_BASE + 0x00 + 3)
-#define	AT91_PIN_PA4	(PIN_BASE + 0x00 + 4)
-#define	AT91_PIN_PA5	(PIN_BASE + 0x00 + 5)
-#define	AT91_PIN_PA6	(PIN_BASE + 0x00 + 6)
-#define	AT91_PIN_PA7	(PIN_BASE + 0x00 + 7)
-#define	AT91_PIN_PA8	(PIN_BASE + 0x00 + 8)
-#define	AT91_PIN_PA9	(PIN_BASE + 0x00 + 9)
-#define	AT91_PIN_PA10	(PIN_BASE + 0x00 + 10)
-#define	AT91_PIN_PA11	(PIN_BASE + 0x00 + 11)
-#define	AT91_PIN_PA12	(PIN_BASE + 0x00 + 12)
-#define	AT91_PIN_PA13	(PIN_BASE + 0x00 + 13)
-#define	AT91_PIN_PA14	(PIN_BASE + 0x00 + 14)
-#define	AT91_PIN_PA15	(PIN_BASE + 0x00 + 15)
-#define	AT91_PIN_PA16	(PIN_BASE + 0x00 + 16)
-#define	AT91_PIN_PA17	(PIN_BASE + 0x00 + 17)
-#define	AT91_PIN_PA18	(PIN_BASE + 0x00 + 18)
-#define	AT91_PIN_PA19	(PIN_BASE + 0x00 + 19)
-#define	AT91_PIN_PA20	(PIN_BASE + 0x00 + 20)
-#define	AT91_PIN_PA21	(PIN_BASE + 0x00 + 21)
-#define	AT91_PIN_PA22	(PIN_BASE + 0x00 + 22)
-#define	AT91_PIN_PA23	(PIN_BASE + 0x00 + 23)
-#define	AT91_PIN_PA24	(PIN_BASE + 0x00 + 24)
-#define	AT91_PIN_PA25	(PIN_BASE + 0x00 + 25)
-#define	AT91_PIN_PA26	(PIN_BASE + 0x00 + 26)
-#define	AT91_PIN_PA27	(PIN_BASE + 0x00 + 27)
-#define	AT91_PIN_PA28	(PIN_BASE + 0x00 + 28)
-#define	AT91_PIN_PA29	(PIN_BASE + 0x00 + 29)
-#define	AT91_PIN_PA30	(PIN_BASE + 0x00 + 30)
-#define	AT91_PIN_PA31	(PIN_BASE + 0x00 + 31)
-
-#define	AT91_PIN_PB0	(PIN_BASE + 0x20 + 0)
-#define	AT91_PIN_PB1	(PIN_BASE + 0x20 + 1)
-#define	AT91_PIN_PB2	(PIN_BASE + 0x20 + 2)
-#define	AT91_PIN_PB3	(PIN_BASE + 0x20 + 3)
-#define	AT91_PIN_PB4	(PIN_BASE + 0x20 + 4)
-#define	AT91_PIN_PB5	(PIN_BASE + 0x20 + 5)
-#define	AT91_PIN_PB6	(PIN_BASE + 0x20 + 6)
-#define	AT91_PIN_PB7	(PIN_BASE + 0x20 + 7)
-#define	AT91_PIN_PB8	(PIN_BASE + 0x20 + 8)
-#define	AT91_PIN_PB9	(PIN_BASE + 0x20 + 9)
-#define	AT91_PIN_PB10	(PIN_BASE + 0x20 + 10)
-#define	AT91_PIN_PB11	(PIN_BASE + 0x20 + 11)
-#define	AT91_PIN_PB12	(PIN_BASE + 0x20 + 12)
-#define	AT91_PIN_PB13	(PIN_BASE + 0x20 + 13)
-#define	AT91_PIN_PB14	(PIN_BASE + 0x20 + 14)
-#define	AT91_PIN_PB15	(PIN_BASE + 0x20 + 15)
-#define	AT91_PIN_PB16	(PIN_BASE + 0x20 + 16)
-#define	AT91_PIN_PB17	(PIN_BASE + 0x20 + 17)
-#define	AT91_PIN_PB18	(PIN_BASE + 0x20 + 18)
-#define	AT91_PIN_PB19	(PIN_BASE + 0x20 + 19)
-#define	AT91_PIN_PB20	(PIN_BASE + 0x20 + 20)
-#define	AT91_PIN_PB21	(PIN_BASE + 0x20 + 21)
-#define	AT91_PIN_PB22	(PIN_BASE + 0x20 + 22)
-#define	AT91_PIN_PB23	(PIN_BASE + 0x20 + 23)
-#define	AT91_PIN_PB24	(PIN_BASE + 0x20 + 24)
-#define	AT91_PIN_PB25	(PIN_BASE + 0x20 + 25)
-#define	AT91_PIN_PB26	(PIN_BASE + 0x20 + 26)
-#define	AT91_PIN_PB27	(PIN_BASE + 0x20 + 27)
-#define	AT91_PIN_PB28	(PIN_BASE + 0x20 + 28)
-#define	AT91_PIN_PB29	(PIN_BASE + 0x20 + 29)
-#define	AT91_PIN_PB30	(PIN_BASE + 0x20 + 30)
-#define	AT91_PIN_PB31	(PIN_BASE + 0x20 + 31)
-
-#define	AT91_PIN_PC0	(PIN_BASE + 0x40 + 0)
-#define	AT91_PIN_PC1	(PIN_BASE + 0x40 + 1)
-#define	AT91_PIN_PC2	(PIN_BASE + 0x40 + 2)
-#define	AT91_PIN_PC3	(PIN_BASE + 0x40 + 3)
-#define	AT91_PIN_PC4	(PIN_BASE + 0x40 + 4)
-#define	AT91_PIN_PC5	(PIN_BASE + 0x40 + 5)
-#define	AT91_PIN_PC6	(PIN_BASE + 0x40 + 6)
-#define	AT91_PIN_PC7	(PIN_BASE + 0x40 + 7)
-#define	AT91_PIN_PC8	(PIN_BASE + 0x40 + 8)
-#define	AT91_PIN_PC9	(PIN_BASE + 0x40 + 9)
-#define	AT91_PIN_PC10	(PIN_BASE + 0x40 + 10)
-#define	AT91_PIN_PC11	(PIN_BASE + 0x40 + 11)
-#define	AT91_PIN_PC12	(PIN_BASE + 0x40 + 12)
-#define	AT91_PIN_PC13	(PIN_BASE + 0x40 + 13)
-#define	AT91_PIN_PC14	(PIN_BASE + 0x40 + 14)
-#define	AT91_PIN_PC15	(PIN_BASE + 0x40 + 15)
-#define	AT91_PIN_PC16	(PIN_BASE + 0x40 + 16)
-#define	AT91_PIN_PC17	(PIN_BASE + 0x40 + 17)
-#define	AT91_PIN_PC18	(PIN_BASE + 0x40 + 18)
-#define	AT91_PIN_PC19	(PIN_BASE + 0x40 + 19)
-#define	AT91_PIN_PC20	(PIN_BASE + 0x40 + 20)
-#define	AT91_PIN_PC21	(PIN_BASE + 0x40 + 21)
-#define	AT91_PIN_PC22	(PIN_BASE + 0x40 + 22)
-#define	AT91_PIN_PC23	(PIN_BASE + 0x40 + 23)
-#define	AT91_PIN_PC24	(PIN_BASE + 0x40 + 24)
-#define	AT91_PIN_PC25	(PIN_BASE + 0x40 + 25)
-#define	AT91_PIN_PC26	(PIN_BASE + 0x40 + 26)
-#define	AT91_PIN_PC27	(PIN_BASE + 0x40 + 27)
-#define	AT91_PIN_PC28	(PIN_BASE + 0x40 + 28)
-#define	AT91_PIN_PC29	(PIN_BASE + 0x40 + 29)
-#define	AT91_PIN_PC30	(PIN_BASE + 0x40 + 30)
-#define	AT91_PIN_PC31	(PIN_BASE + 0x40 + 31)
-
-#define	AT91_PIN_PD0	(PIN_BASE + 0x60 + 0)
-#define	AT91_PIN_PD1	(PIN_BASE + 0x60 + 1)
-#define	AT91_PIN_PD2	(PIN_BASE + 0x60 + 2)
-#define	AT91_PIN_PD3	(PIN_BASE + 0x60 + 3)
-#define	AT91_PIN_PD4	(PIN_BASE + 0x60 + 4)
-#define	AT91_PIN_PD5	(PIN_BASE + 0x60 + 5)
-#define	AT91_PIN_PD6	(PIN_BASE + 0x60 + 6)
-#define	AT91_PIN_PD7	(PIN_BASE + 0x60 + 7)
-#define	AT91_PIN_PD8	(PIN_BASE + 0x60 + 8)
-#define	AT91_PIN_PD9	(PIN_BASE + 0x60 + 9)
-#define	AT91_PIN_PD10	(PIN_BASE + 0x60 + 10)
-#define	AT91_PIN_PD11	(PIN_BASE + 0x60 + 11)
-#define	AT91_PIN_PD12	(PIN_BASE + 0x60 + 12)
-#define	AT91_PIN_PD13	(PIN_BASE + 0x60 + 13)
-#define	AT91_PIN_PD14	(PIN_BASE + 0x60 + 14)
-#define	AT91_PIN_PD15	(PIN_BASE + 0x60 + 15)
-#define	AT91_PIN_PD16	(PIN_BASE + 0x60 + 16)
-#define	AT91_PIN_PD17	(PIN_BASE + 0x60 + 17)
-#define	AT91_PIN_PD18	(PIN_BASE + 0x60 + 18)
-#define	AT91_PIN_PD19	(PIN_BASE + 0x60 + 19)
-#define	AT91_PIN_PD20	(PIN_BASE + 0x60 + 20)
-#define	AT91_PIN_PD21	(PIN_BASE + 0x60 + 21)
-#define	AT91_PIN_PD22	(PIN_BASE + 0x60 + 22)
-#define	AT91_PIN_PD23	(PIN_BASE + 0x60 + 23)
-#define	AT91_PIN_PD24	(PIN_BASE + 0x60 + 24)
-#define	AT91_PIN_PD25	(PIN_BASE + 0x60 + 25)
-#define	AT91_PIN_PD26	(PIN_BASE + 0x60 + 26)
-#define	AT91_PIN_PD27	(PIN_BASE + 0x60 + 27)
-#define	AT91_PIN_PD28	(PIN_BASE + 0x60 + 28)
-#define	AT91_PIN_PD29	(PIN_BASE + 0x60 + 29)
-#define	AT91_PIN_PD30	(PIN_BASE + 0x60 + 30)
-#define	AT91_PIN_PD31	(PIN_BASE + 0x60 + 31)
-
-#define	AT91_PIN_PE0	(PIN_BASE + 0x80 + 0)
-#define	AT91_PIN_PE1	(PIN_BASE + 0x80 + 1)
-#define	AT91_PIN_PE2	(PIN_BASE + 0x80 + 2)
-#define	AT91_PIN_PE3	(PIN_BASE + 0x80 + 3)
-#define	AT91_PIN_PE4	(PIN_BASE + 0x80 + 4)
-#define	AT91_PIN_PE5	(PIN_BASE + 0x80 + 5)
-#define	AT91_PIN_PE6	(PIN_BASE + 0x80 + 6)
-#define	AT91_PIN_PE7	(PIN_BASE + 0x80 + 7)
-#define	AT91_PIN_PE8	(PIN_BASE + 0x80 + 8)
-#define	AT91_PIN_PE9	(PIN_BASE + 0x80 + 9)
-#define	AT91_PIN_PE10	(PIN_BASE + 0x80 + 10)
-#define	AT91_PIN_PE11	(PIN_BASE + 0x80 + 11)
-#define	AT91_PIN_PE12	(PIN_BASE + 0x80 + 12)
-#define	AT91_PIN_PE13	(PIN_BASE + 0x80 + 13)
-#define	AT91_PIN_PE14	(PIN_BASE + 0x80 + 14)
-#define	AT91_PIN_PE15	(PIN_BASE + 0x80 + 15)
-#define	AT91_PIN_PE16	(PIN_BASE + 0x80 + 16)
-#define	AT91_PIN_PE17	(PIN_BASE + 0x80 + 17)
-#define	AT91_PIN_PE18	(PIN_BASE + 0x80 + 18)
-#define	AT91_PIN_PE19	(PIN_BASE + 0x80 + 19)
-#define	AT91_PIN_PE20	(PIN_BASE + 0x80 + 20)
-#define	AT91_PIN_PE21	(PIN_BASE + 0x80 + 21)
-#define	AT91_PIN_PE22	(PIN_BASE + 0x80 + 22)
-#define	AT91_PIN_PE23	(PIN_BASE + 0x80 + 23)
-#define	AT91_PIN_PE24	(PIN_BASE + 0x80 + 24)
-#define	AT91_PIN_PE25	(PIN_BASE + 0x80 + 25)
-#define	AT91_PIN_PE26	(PIN_BASE + 0x80 + 26)
-#define	AT91_PIN_PE27	(PIN_BASE + 0x80 + 27)
-#define	AT91_PIN_PE28	(PIN_BASE + 0x80 + 28)
-#define	AT91_PIN_PE29	(PIN_BASE + 0x80 + 29)
-#define	AT91_PIN_PE30	(PIN_BASE + 0x80 + 30)
-#define	AT91_PIN_PE31	(PIN_BASE + 0x80 + 31)
-
-static unsigned long at91_pios[] = {
-	AT91_PIOA,
-	AT91_PIOB,
-	AT91_PIOC,
-#ifdef AT91_PIOD
-	AT91_PIOD,
-#ifdef AT91_PIOE
-	AT91_PIOE
-#endif
-#endif
-};
-
-static inline void *pin_to_controller(unsigned pin)
-{
-	pin -= PIN_BASE;
-	pin /= 32;
-	return (void *)(AT91_BASE_SYS + at91_pios[pin]);
-}
-
-static inline unsigned pin_to_mask(unsigned pin)
-{
-	pin -= PIN_BASE;
-	return 1 << (pin % 32);
-}
-
-/* The following macros are need for backward compatibility */
-#define at91_set_GPIO_periph(x, y) \
-	at91_set_gpio_periph((x - PIN_BASE) / 32,(x % 32), y)
-#define at91_set_A_periph(x, y) \
-	at91_set_a_periph((x - PIN_BASE) / 32,(x % 32), y)
-#define at91_set_B_periph(x, y) \
-	at91_set_b_periph((x - PIN_BASE) / 32,(x % 32), y)
-#define at91_set_gpio_output(x, y) \
-	at91_set_pio_output((x - PIN_BASE) / 32,(x % 32), y)
-#define at91_set_gpio_input(x, y) \
-	at91_set_pio_input((x - PIN_BASE) / 32,(x % 32), y)
-#define at91_set_gpio_value(x, y) \
-	at91_set_pio_value((x - PIN_BASE) / 32,(x % 32), y)
-#define at91_get_gpio_value(x) \
-	at91_get_pio_value((x - PIN_BASE) / 32,(x % 32))
-#else
-#define at91_set_gpio_value(x, y)	at91_set_pio_value(x, y)
-#define at91_get_gpio_value(x)		at91_get_pio_value(x)
-#endif
-#endif
diff --git a/arch/arm/include/asm/arch-at91/hardware.h b/arch/arm/include/asm/arch-at91/hardware.h
deleted file mode 100644
index 6b44d61..0000000
--- a/arch/arm/include/asm/arch-at91/hardware.h
+++ /dev/null
@@ -1,80 +0,0 @@
-/*
- * [origin: Linux kernel include/asm-arm/arch-at91/hardware.h]
- *
- *  Copyright (C) 2003 SAN People
- *  Copyright (C) 2003 ATMEL
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- */
-
-#ifndef __ASM_ARCH_HARDWARE_H
-#define __ASM_ARCH_HARDWARE_H
-
-#include <asm/sizes.h>
-
-#if defined(CONFIG_AT91RM9200)
-#include <asm/arch-at91/at91rm9200.h>
-#define AT91_PMC_UHP	AT91RM9200_PMC_UHP
-#elif defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9G20)
-#include <asm/arch/at91sam9260.h>
-#define AT91_BASE_MCI	AT91SAM9260_BASE_MCI
-#define AT91_BASE_SPI	AT91SAM9260_BASE_SPI0
-#define AT91_BASE_SPI1	AT91SAM9260_BASE_SPI1
-#define AT91_ID_UHP	AT91SAM9260_ID_UHP
-#define AT91_PMC_UHP	AT91SAM926x_PMC_UHP
-#elif defined(CONFIG_AT91SAM9261) || defined(CONFIG_AT91SAM9G10)
-#include <asm/arch/at91sam9261.h>
-#define AT91_BASE_SPI	AT91SAM9261_BASE_SPI0
-#define AT91_ID_UHP	AT91SAM9261_ID_UHP
-#define AT91_PMC_UHP	AT91SAM926x_PMC_UHP
-#elif defined(CONFIG_AT91SAM9263)
-#include <asm/arch/at91sam9263.h>
-#define AT91_BASE_SPI	AT91SAM9263_BASE_SPI0
-#define AT91_ID_UHP	AT91SAM9263_ID_UHP
-#define AT91_PMC_UHP	AT91SAM926x_PMC_UHP
-#elif defined(CONFIG_AT91SAM9RL)
-#include <asm/arch/at91sam9rl.h>
-#define AT91_BASE_SPI	AT91SAM9RL_BASE_SPI
-#define AT91_ID_UHP	AT91SAM9RL_ID_UHP
-#elif defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45)
-#include <asm/arch/at91sam9g45.h>
-#define AT91_BASE_EMAC  AT91SAM9G45_BASE_EMAC
-#define AT91_BASE_SPI   AT91SAM9G45_BASE_SPI0
-#define AT91_ID_UHP     AT91SAM9G45_ID_UHPHS
-#define AT91_PMC_UHP    AT91SAM926x_PMC_UHP
-#elif defined(CONFIG_AT91CAP9)
-#include <asm/arch/at91cap9.h>
-#define AT91_BASE_SPI	AT91CAP9_BASE_SPI0
-#define AT91_ID_UHP	AT91CAP9_ID_UHP
-#define AT91_PMC_UHP	AT91CAP9_PMC_UHP
-#elif defined(CONFIG_AT91X40)
-#include <asm/arch/at91x40.h>
-#else
-#error "Unsupported AT91 processor"
-#endif
-
-/* External Memory Map */
-#define AT91_CHIPSELECT_0	0x10000000
-#define AT91_CHIPSELECT_1	0x20000000
-#define AT91_CHIPSELECT_2	0x30000000
-#define AT91_CHIPSELECT_3	0x40000000
-#define AT91_CHIPSELECT_4	0x50000000
-#define AT91_CHIPSELECT_5	0x60000000
-#define AT91_CHIPSELECT_6	0x70000000
-#define AT91_CHIPSELECT_7	0x80000000
-
-/* SDRAM */
-#ifdef CONFIG_DRAM_BASE
-#define AT91_SDRAM_BASE		CONFIG_DRAM_BASE
-#else
-#define AT91_SDRAM_BASE		AT91_CHIPSELECT_1
-#endif
-
-/* Clocks */
-#define AT91_SLOW_CLOCK		32768		/* slow clock */
-
-#endif
diff --git a/arch/arm/include/asm/arch-at91/io.h b/arch/arm/include/asm/arch-at91/io.h
deleted file mode 100644
index 38d185e..0000000
--- a/arch/arm/include/asm/arch-at91/io.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/*
- * [origin: Linux kernel include/asm-arm/arch-at91/io.h]
- *
- *  Copyright (C) 2003 SAN People
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-#ifndef __ASM_ARCH_IO_H
-#define __ASM_ARCH_IO_H
-
-#include <asm/io.h>
-
-#ifdef CONFIG_AT91_LEGACY
-
-static inline unsigned int at91_sys_read(unsigned int reg_offset)
-{
-	void *addr = (void *)AT91_BASE_SYS;
-
-	return __raw_readl(addr + reg_offset);
-}
-
-static inline void at91_sys_write(unsigned int reg_offset, unsigned long value)
-{
-	void *addr = (void *)AT91_BASE_SYS;
-
-	__raw_writel(value, addr + reg_offset);
-}
-#endif
-
-#endif
diff --git a/arch/arm/include/asm/arch-at91/memory-map.h b/arch/arm/include/asm/arch-at91/memory-map.h
deleted file mode 100644
index d489fa2..0000000
--- a/arch/arm/include/asm/arch-at91/memory-map.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/*
- * (C) Copyright 2007-2008
- * Stelian Pop <stelian.pop@leadtechdesign.com>
- * Lead Tech Design <www.leadtechdesign.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-#ifndef __ASM_ARM_ARCH_MEMORYMAP_H__
-#define __ASM_ARM_ARCH_MEMORYMAP_H__
-
-#include <asm/arch/hardware.h>
-
-#define USART0_BASE AT91_USART0
-#define USART1_BASE AT91_USART1
-#define USART2_BASE AT91_USART2
-#define USART3_BASE (AT91_BASE_SYS + AT91_DBGU)
-#define SPI0_BASE	AT91_BASE_SPI
-#define SPI1_BASE	AT91_BASE_SPI1
-
-#endif /* __ASM_ARM_ARCH_MEMORYMAP_H__ */
diff --git a/arch/arm/include/asm/arch-at91rm9200/AT91RM9200.h b/arch/arm/include/asm/arch-at91rm9200/AT91RM9200.h
deleted file mode 100644
index 00bae1c..0000000
--- a/arch/arm/include/asm/arch-at91rm9200/AT91RM9200.h
+++ /dev/null
@@ -1,812 +0,0 @@
-/*
- * (C) Copyright 2003
- * AT91RM9200 definitions
- * Author : ATMEL AT91 application group
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef AT91RM9200_H
-#define AT91RM9200_H
-
-#ifndef __ASSEMBLY__
-typedef volatile unsigned int AT91_REG;		/* Hardware register definition */
-
-/*****************************************************************************/
-/*        SOFTWARE API DEFINITION  FOR Timer Counter Channel Interface       */
-/*****************************************************************************/
-typedef struct _AT91S_TC
-{
-	AT91_REG	 TC_CCR;	/* Channel Control Register */
-	AT91_REG	 TC_CMR;	/* Channel Mode Register */
-	AT91_REG	 Reserved0[2];	/*  */
-	AT91_REG	 TC_CV;		/* Counter Value */
-	AT91_REG	 TC_RA;		/* Register A */
-	AT91_REG	 TC_RB;		/* Register B */
-	AT91_REG	 TC_RC;		/* Register C */
-	AT91_REG	 TC_SR;		/* Status Register */
-	AT91_REG	 TC_IER;	/* Interrupt Enable Register */
-	AT91_REG	 TC_IDR;	/* Interrupt Disable Register */
-	AT91_REG	 TC_IMR;	/* Interrupt Mask Register */
-} AT91S_TC, *AT91PS_TC;
-
-#define AT91C_TC_TIMER_DIV1_CLOCK ((unsigned int) 0x0 <<  0) /* (TC) MCK/2 */
-#define AT91C_TC_TIMER_DIV2_CLOCK ((unsigned int) 0x1 <<  0) /* (TC) MCK/8 */
-#define AT91C_TC_TIMER_DIV3_CLOCK ((unsigned int) 0x2 <<  0) /* (TC) MCK/32 */
-#define AT91C_TC_TIMER_DIV4_CLOCK ((unsigned int) 0x3 <<  0) /* (TC) MCK/128 */
-#define AT91C_TC_SLOW_CLOCK	  ((unsigned int) 0x4 <<  0) /* (TC) SLOW CLK*/
-#define AT91C_TC_XC0_CLOCK	  ((unsigned int) 0x5 <<  0) /* (TC) XC0 */
-#define AT91C_TC_XC1_CLOCK	  ((unsigned int) 0x6 <<  0) /* (TC) XC1 */
-#define AT91C_TC_XC2_CLOCK	  ((unsigned int) 0x7 <<  0) /* (TC) XC2 */
-#define AT91C_TCB_TC0XC0S_NONE	  ((unsigned int) 0x1)       /* (TCB) None signal connected to XC0 */
-#define AT91C_TCB_TC1XC1S_NONE	  ((unsigned int) 0x1 <<  2) /* (TCB) None signal connected to XC1 */
-#define AT91C_TCB_TC2XC2S_NONE	  ((unsigned int) 0x1 <<  4) /* (TCB) None signal connected to XC2 */
-#define AT91C_TC_CLKDIS		  ((unsigned int) 0x1 <<  1) /* (TC) Counter Clock Disable Command */
-#define AT91C_TC_SWTRG		  ((unsigned int) 0x1 <<  2) /* (TC) Software Trigger Command */
-#define AT91C_TC_CLKEN		  ((unsigned int) 0x1 <<  0) /* (TC) Counter Clock Enable Command */
-
-/*****************************************************************************/
-/*                  SOFTWARE API DEFINITION  FOR Usart                       */
-/*****************************************************************************/
-typedef struct _AT91S_USART
-{
-	AT91_REG	 US_CR;		/* Control Register */
-	AT91_REG	 US_MR;		/* Mode Register */
-	AT91_REG	 US_IER;	/* Interrupt Enable Register */
-	AT91_REG	 US_IDR;	/* Interrupt Disable Register */
-	AT91_REG	 US_IMR;	/* Interrupt Mask Register */
-	AT91_REG	 US_CSR;	/* Channel Status Register */
-	AT91_REG	 US_RHR;	/* Receiver Holding Register */
-	AT91_REG	 US_THR;	/* Transmitter Holding Register */
-	AT91_REG	 US_BRGR;	/* Baud Rate Generator Register */
-	AT91_REG	 US_RTOR;	/* Receiver Time-out Register */
-	AT91_REG	 US_TTGR;	/* Transmitter Time-guard Register */
-	AT91_REG	 Reserved0[5];	/*  */
-	AT91_REG	 US_FIDI;	/* FI_DI_Ratio Register */
-	AT91_REG	 US_NER;	/* Nb Errors Register */
-	AT91_REG	 US_XXR;	/* XON_XOFF Register */
-	AT91_REG	 US_IF;		/* IRDA_FILTER Register */
-	AT91_REG	 Reserved1[44];	/*  */
-	AT91_REG	 US_RPR;	/* Receive Pointer Register */
-	AT91_REG	 US_RCR;	/* Receive Counter Register */
-	AT91_REG	 US_TPR;	/* Transmit Pointer Register */
-	AT91_REG	 US_TCR;	/* Transmit Counter Register */
-	AT91_REG	 US_RNPR;	/* Receive Next Pointer Register */
-	AT91_REG	 US_RNCR;	/* Receive Next Counter Register */
-	AT91_REG	 US_TNPR;	/* Transmit Next Pointer Register */
-	AT91_REG	 US_TNCR;	/* Transmit Next Counter Register */
-	AT91_REG	 US_PTCR;	/* PDC Transfer Control Register */
-	AT91_REG	 US_PTSR;	/* PDC Transfer Status Register */
-} AT91S_USART, *AT91PS_USART;
-
-/*****************************************************************************/
-/*          SOFTWARE API DEFINITION  FOR Clock Generator Controler           */
-/*****************************************************************************/
-typedef struct _AT91S_CKGR
-{
-	AT91_REG	 CKGR_MOR;	/* Main Oscillator Register */
-	AT91_REG	 CKGR_MCFR;	/* Main Clock  Frequency Register */
-	AT91_REG	 CKGR_PLLAR;	/* PLL A Register */
-	AT91_REG	 CKGR_PLLBR;	/* PLL B Register */
-} AT91S_CKGR, *AT91PS_CKGR;
-
-/* -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- */
-#define AT91C_CKGR_MOSCEN	((unsigned int) 0x1  <<  0)	/* (CKGR) Main Oscillator Enable */
-#define AT91C_CKGR_OSCTEST	((unsigned int) 0x1  <<  1)	/* (CKGR) Oscillator Test */
-#define AT91C_CKGR_OSCOUNT	((unsigned int) 0xFF <<  8)	/* (CKGR) Main Oscillator Start-up Time */
-
-/* -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- */
-#define AT91C_CKGR_MAINF	((unsigned int) 0xFFFF <<  0)	/* (CKGR) Main Clock Frequency */
-#define AT91C_CKGR_MAINRDY	((unsigned int) 0x1 << 16)	/* (CKGR) Main Clock Ready */
-
-/* -------- CKGR_PLLAR : (CKGR Offset: 0x8) PLL A Register -------- */
-#define AT91C_CKGR_DIVA		((unsigned int) 0xFF  <<  0)	/* (CKGR) Divider Selected */
-#define AT91C_CKGR_DIVA_0	((unsigned int) 0x0)		/* (CKGR) Divider output is 0 */
-#define AT91C_CKGR_DIVA_BYPASS	((unsigned int) 0x1)		/* (CKGR) Divider is bypassed */
-#define AT91C_CKGR_PLLACOUNT	((unsigned int) 0x3F  <<  8)	/* (CKGR) PLL A Counter */
-#define AT91C_CKGR_OUTA		((unsigned int) 0x3   << 14)	/* (CKGR) PLL A Output Frequency Range */
-#define AT91C_CKGR_OUTA_0	((unsigned int) 0x0   << 14)	/* (CKGR) Please refer to the PLLA datasheet */
-#define AT91C_CKGR_OUTA_1	((unsigned int) 0x1   << 14)	/* (CKGR) Please refer to the PLLA datasheet */
-#define AT91C_CKGR_OUTA_2	((unsigned int) 0x2   << 14)	/* (CKGR) Please refer to the PLLA datasheet */
-#define AT91C_CKGR_OUTA_3	((unsigned int) 0x3   << 14)	/* (CKGR) Please refer to the PLLA datasheet */
-#define AT91C_CKGR_MULA		((unsigned int) 0x7FF << 16)	/* (CKGR) PLL A Multiplier */
-#define AT91C_CKGR_SRCA		((unsigned int) 0x1   << 29)	/* (CKGR) PLL A Source */
-
-/* -------- CKGR_PLLBR : (CKGR Offset: 0xc) PLL B Register -------- */
-#define AT91C_CKGR_DIVB		((unsigned int) 0xFF  <<  0)	/* (CKGR) Divider Selected */
-#define AT91C_CKGR_DIVB_0	((unsigned int) 0x0)		/* (CKGR) Divider output is 0 */
-#define AT91C_CKGR_DIVB_BYPASS	((unsigned int) 0x1)		/* (CKGR) Divider is bypassed */
-#define AT91C_CKGR_PLLBCOUNT	((unsigned int) 0x3F  <<  8)	/* (CKGR) PLL B Counter */
-#define AT91C_CKGR_OUTB		((unsigned int) 0x3   << 14)	/* (CKGR) PLL B Output Frequency Range */
-#define AT91C_CKGR_OUTB_0	((unsigned int) 0x0   << 14)	/* (CKGR) Please refer to the PLLB datasheet */
-#define AT91C_CKGR_OUTB_1	((unsigned int) 0x1   << 14)	/* (CKGR) Please refer to the PLLB datasheet */
-#define AT91C_CKGR_OUTB_2	((unsigned int) 0x2   << 14)	/* (CKGR) Please refer to the PLLB datasheet */
-#define AT91C_CKGR_OUTB_3	((unsigned int) 0x3   << 14)	/* (CKGR) Please refer to the PLLB datasheet */
-#define AT91C_CKGR_MULB		((unsigned int) 0x7FF << 16)	/* (CKGR) PLL B Multiplier */
-#define AT91C_CKGR_USB_96M	((unsigned int) 0x1   << 28)	/* (CKGR) Divider for USB Ports */
-#define AT91C_CKGR_USB_PLL	((unsigned int) 0x1   << 29)	/* (CKGR) PLL Use */
-
-/*****************************************************************************/
-/*        SOFTWARE API DEFINITION  FOR Parallel Input Output Controler       */
-/*****************************************************************************/
-typedef struct _AT91S_PIO
-{
-	AT91_REG	 PIO_PER;	/* PIO Enable Register */
-	AT91_REG	 PIO_PDR;	/* PIO Disable Register */
-	AT91_REG	 PIO_PSR;	/* PIO Status Register */
-	AT91_REG	 Reserved0[1];	/*  */
-	AT91_REG	 PIO_OER;	/* Output Enable Register */
-	AT91_REG	 PIO_ODR;	/* Output Disable Registerr */
-	AT91_REG	 PIO_OSR;	/* Output Status Register */
-	AT91_REG	 Reserved1[1];	/*  */
-	AT91_REG	 PIO_IFER;	/* Input Filter Enable Register */
-	AT91_REG	 PIO_IFDR;	/* Input Filter Disable Register */
-	AT91_REG	 PIO_IFSR;	/* Input Filter Status Register */
-	AT91_REG	 Reserved2[1];	/*  */
-	AT91_REG	 PIO_SODR;	/* Set Output Data Register */
-	AT91_REG	 PIO_CODR;	/* Clear Output Data Register */
-	AT91_REG	 PIO_ODSR;	/* Output Data Status Register */
-	AT91_REG	 PIO_PDSR;	/* Pin Data Status Register */
-	AT91_REG	 PIO_IER;	/* Interrupt Enable Register */
-	AT91_REG	 PIO_IDR;	/* Interrupt Disable Register */
-	AT91_REG	 PIO_IMR;	/* Interrupt Mask Register */
-	AT91_REG	 PIO_ISR;	/* Interrupt Status Register */
-	AT91_REG	 PIO_MDER;	/* Multi-driver Enable Register */
-	AT91_REG	 PIO_MDDR;	/* Multi-driver Disable Register */
-	AT91_REG	 PIO_MDSR;	/* Multi-driver Status Register */
-	AT91_REG	 Reserved3[1];	/*  */
-	AT91_REG	 PIO_PPUDR;	/* Pull-up Disable Register */
-	AT91_REG	 PIO_PPUER;	/* Pull-up Enable Register */
-	AT91_REG	 PIO_PPUSR;	/* Pad Pull-up Status Register */
-	AT91_REG	 Reserved4[1];	/*  */
-	AT91_REG	 PIO_ASR;	/* Select A Register */
-	AT91_REG	 PIO_BSR;	/* Select B Register */
-	AT91_REG	 PIO_ABSR;	/* AB Select Status Register */
-	AT91_REG	 Reserved5[9];	/*  */
-	AT91_REG	 PIO_OWER;	/* Output Write Enable Register */
-	AT91_REG	 PIO_OWDR;	/* Output Write Disable Register */
-	AT91_REG	 PIO_OWSR;	/* Output Write Status Register */
-} AT91S_PIO, *AT91PS_PIO;
-
-
-/*****************************************************************************/
-/*              SOFTWARE API DEFINITION  FOR Debug Unit                      */
-/*****************************************************************************/
-typedef struct _AT91S_DBGU
-{
-	AT91_REG	 DBGU_CR;	/* Control Register */
-	AT91_REG	 DBGU_MR;	/* Mode Register */
-	AT91_REG	 DBGU_IER;	/* Interrupt Enable Register */
-	AT91_REG	 DBGU_IDR;	/* Interrupt Disable Register */
-	AT91_REG	 DBGU_IMR;	/* Interrupt Mask Register */
-	AT91_REG	 DBGU_CSR;	/* Channel Status Register */
-	AT91_REG	 DBGU_RHR;	/* Receiver Holding Register */
-	AT91_REG	 DBGU_THR;	/* Transmitter Holding Register */
-	AT91_REG	 DBGU_BRGR;	/* Baud Rate Generator Register */
-	AT91_REG	 Reserved0[7];	/*  */
-	AT91_REG	 DBGU_C1R;	/* Chip ID1 Register */
-	AT91_REG	 DBGU_C2R;	/* Chip ID2 Register */
-	AT91_REG	 DBGU_FNTR;	/* Force NTRST Register */
-	AT91_REG	 Reserved1[45];	/*  */
-	AT91_REG	 DBGU_RPR;	/* Receive Pointer Register */
-	AT91_REG	 DBGU_RCR;	/* Receive Counter Register */
-	AT91_REG	 DBGU_TPR;	/* Transmit Pointer Register */
-	AT91_REG	 DBGU_TCR;	/* Transmit Counter Register */
-	AT91_REG	 DBGU_RNPR;	/* Receive Next Pointer Register */
-	AT91_REG	 DBGU_RNCR;	/* Receive Next Counter Register */
-	AT91_REG	 DBGU_TNPR;	/* Transmit Next Pointer Register */
-	AT91_REG	 DBGU_TNCR;	/* Transmit Next Counter Register */
-	AT91_REG	 DBGU_PTCR;	/* PDC Transfer Control Register */
-	AT91_REG	 DBGU_PTSR;	/* PDC Transfer Status Register */
-} AT91S_DBGU, *AT91PS_DBGU;
-
-/* -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register --------  */
-#define AT91C_US_RXRDY		((unsigned int) 0x1 <<  0) /* (DBGU) RXRDY Interrupt */
-#define AT91C_US_TXRDY		((unsigned int) 0x1 <<  1) /* (DBGU) TXRDY Interrupt */
-#define AT91C_US_ENDRX		((unsigned int) 0x1 <<  3) /* (DBGU) End of Receive Transfer Interrupt */
-#define AT91C_US_ENDTX		((unsigned int) 0x1 <<  4) /* (DBGU) End of Transmit Interrupt */
-#define AT91C_US_OVRE		((unsigned int) 0x1 <<  5) /* (DBGU) Overrun Interrupt */
-#define AT91C_US_FRAME		((unsigned int) 0x1 <<  6) /* (DBGU) Framing Error Interrupt */
-#define AT91C_US_PARE		((unsigned int) 0x1 <<  7) /* (DBGU) Parity Error Interrupt */
-#define AT91C_US_TXEMPTY	((unsigned int) 0x1 <<  9) /* (DBGU) TXEMPTY Interrupt */
-#define AT91C_US_TXBUFE		((unsigned int) 0x1 << 11) /* (DBGU) TXBUFE Interrupt */
-#define AT91C_US_RXBUFF		((unsigned int) 0x1 << 12) /* (DBGU) RXBUFF Interrupt */
-#define AT91C_US_COMM_TX	((unsigned int) 0x1 << 30) /* (DBGU) COMM_TX Interrupt */
-#define AT91C_US_COMM_RX	((unsigned int) 0x1 << 31) /* (DBGU) COMM_RX Interrupt */
-
-/* -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register --------  */
-#define AT91C_US_RSTRX		((unsigned int) 0x1 <<  2) /* (DBGU) Reset Receiver */
-#define AT91C_US_RSTTX		((unsigned int) 0x1 <<  3) /* (DBGU) Reset Transmitter */
-#define AT91C_US_RXEN		((unsigned int) 0x1 <<  4) /* (DBGU) Receiver Enable */
-#define AT91C_US_RXDIS		((unsigned int) 0x1 <<  5) /* (DBGU) Receiver Disable */
-#define AT91C_US_TXEN		((unsigned int) 0x1 <<  6) /* (DBGU) Transmitter Enable */
-#define AT91C_US_TXDIS		((unsigned int) 0x1 <<  7) /* (DBGU) Transmitter Disable */
-
-#define AT91C_US_CLKS_CLOCK	((unsigned int) 0x0 <<  4) /* (USART) Clock */
-#define AT91C_US_CHRL_8_BITS	((unsigned int) 0x3 <<  6) /* (USART) Character Length: 8 bits */
-#define AT91C_US_PAR_NONE	((unsigned int) 0x4 <<  9) /* (DBGU) No Parity */
-#define AT91C_US_NBSTOP_1_BIT	((unsigned int) 0x0 << 12) /* (USART) 1 stop bit */
-
-/*****************************************************************************/
-/*      SOFTWARE API DEFINITION  FOR Static Memory Controller 2 Interface    */
-/*****************************************************************************/
-typedef struct _AT91S_SMC2
-{
-	AT91_REG	 SMC2_CSR[8];	/* SMC2 Chip Select Register */
-} AT91S_SMC2, *AT91PS_SMC2;
-
-/* -------- SMC2_CSR : (SMC2 Offset: 0x0) SMC2 Chip Select Register --------  */
-#define AT91C_SMC2_NWS			((unsigned int) 0x7F << 0) /* (SMC2) Number of Wait States */
-#define AT91C_SMC2_WSEN			((unsigned int) 0x1 <<  7) /* (SMC2) Wait State Enable */
-#define AT91C_SMC2_TDF			((unsigned int) 0xF <<  8) /* (SMC2) Data Float Time */
-#define AT91C_SMC2_BAT			((unsigned int) 0x1 << 12) /* (SMC2) Byte Access Type */
-#define AT91C_SMC2_DBW			((unsigned int) 0x1 << 13) /* (SMC2) Data Bus Width */
-#define AT91C_SMC2_DBW_16		((unsigned int) 0x1 << 13) /* (SMC2) 16-bit. */
-#define AT91C_SMC2_DBW_8		((unsigned int) 0x2 << 13) /* (SMC2) 8-bit. */
-#define AT91C_SMC2_DRP			((unsigned int) 0x1 << 15) /* (SMC2) Data Read Protocol */
-#define AT91C_SMC2_ACSS			((unsigned int) 0x3 << 16) /* (SMC2) Address to Chip Select Setup */
-#define AT91C_SMC2_ACSS_STANDARD	((unsigned int) 0x0 << 16) /* (SMC2) Standard, asserted at the beginning of the access and deasserted at the end. */
-#define AT91C_SMC2_ACSS_1_CYCLE		((unsigned int) 0x1 << 16) /* (SMC2) One cycle less at the beginning and the end of the access. */
-#define AT91C_SMC2_ACSS_2_CYCLES	((unsigned int) 0x2 << 16) /* (SMC2) Two cycles less at the beginning and the end of the access. */
-#define AT91C_SMC2_ACSS_3_CYCLES	((unsigned int) 0x3 << 16) /* (SMC2) Three cycles less at the beginning and the end of the access. */
-#define AT91C_SMC2_RWSETUP		((unsigned int) 0x7 << 24) /* (SMC2) Read and Write Signal Setup Time */
-#define AT91C_SMC2_RWHOLD		((unsigned int) 0x7 << 29) /* (SMC2) Read and Write Signal Hold Time */
-
-/*****************************************************************************/
-/*           SOFTWARE API DEFINITION  FOR Power Management Controler         */
-/*****************************************************************************/
-typedef struct _AT91S_PMC
-{
-	AT91_REG	 PMC_SCER;	/* System Clock Enable Register */
-	AT91_REG	 PMC_SCDR;	/* System Clock Disable Register */
-	AT91_REG	 PMC_SCSR;	/* System Clock Status Register */
-	AT91_REG	 Reserved0[1];	/* */
-	AT91_REG	 PMC_PCER;	/* Peripheral Clock Enable Register */
-	AT91_REG	 PMC_PCDR;	/* Peripheral Clock Disable Register */
-	AT91_REG	 PMC_PCSR;	/* Peripheral Clock Status Register */
-	AT91_REG	 Reserved1[5];	/* */
-	AT91_REG	 PMC_MCKR;	/* Master Clock Register */
-	AT91_REG	 Reserved2[3];	/* */
-	AT91_REG	 PMC_PCKR[8];	/* Programmable Clock Register */
-	AT91_REG	 PMC_IER;	/* Interrupt Enable Register */
-	AT91_REG	 PMC_IDR;	/* Interrupt Disable Register */
-	AT91_REG	 PMC_SR;	/* Status Register */
-	AT91_REG	 PMC_IMR;	/* Interrupt Mask Register */
-} AT91S_PMC, *AT91PS_PMC;
-
-/*------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register --------*/
-#define AT91C_PMC_PCK		((unsigned int) 0x1 <<  0) /* (PMC) Processor Clock */
-#define AT91C_PMC_UDP		((unsigned int) 0x1 <<  1) /* (PMC) USB Device Port Clock */
-#define AT91C_PMC_MCKUDP	((unsigned int) 0x1 <<  2) /* (PMC) USB Device Port Master Clock Automatic Disable on Suspend */
-#define AT91C_PMC_UHP		((unsigned int) 0x1 <<  4) /* (PMC) USB Host Port Clock */
-#define AT91C_PMC_PCK0		((unsigned int) 0x1 <<  8) /* (PMC) Programmable Clock Output */
-#define AT91C_PMC_PCK1		((unsigned int) 0x1 <<  9) /* (PMC) Programmable Clock Output */
-#define AT91C_PMC_PCK2		((unsigned int) 0x1 << 10) /* (PMC) Programmable Clock Output */
-#define AT91C_PMC_PCK3		((unsigned int) 0x1 << 11) /* (PMC) Programmable Clock Output */
-#define AT91C_PMC_PCK4		((unsigned int) 0x1 << 12) /* (PMC) Programmable Clock Output */
-#define AT91C_PMC_PCK5		((unsigned int) 0x1 << 13) /* (PMC) Programmable Clock Output */
-#define AT91C_PMC_PCK6		((unsigned int) 0x1 << 14) /* (PMC) Programmable Clock Output */
-#define AT91C_PMC_PCK7		((unsigned int) 0x1 << 15) /* (PMC) Programmable Clock Output */
-/*-------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register ------*/
-/*-------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------*/
-/*-------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register --------*/
-#define AT91C_PMC_CSS		((unsigned int) 0x3 <<  0) /* (PMC) Programmable Clock Selection */
-#define AT91C_PMC_CSS_SLOW_CLK	((unsigned int) 0x0)       /* (PMC) Slow Clock is selected */
-#define AT91C_PMC_CSS_MAIN_CLK	((unsigned int) 0x1)       /* (PMC) Main Clock is selected */
-#define AT91C_PMC_CSS_PLLA_CLK	((unsigned int) 0x2)       /* (PMC) Clock from PLL A is selected */
-#define AT91C_PMC_CSS_PLLB_CLK	((unsigned int) 0x3)       /* (PMC) Clock from PLL B is selected */
-#define AT91C_PMC_PRES		((unsigned int) 0x7 <<  2) /* (PMC) Programmable Clock Prescaler */
-#define AT91C_PMC_PRES_CLK	((unsigned int) 0x0 <<  2) /* (PMC) Selected clock */
-#define AT91C_PMC_PRES_CLK_2	((unsigned int) 0x1 <<  2) /* (PMC) Selected clock divided by 2 */
-#define AT91C_PMC_PRES_CLK_4	((unsigned int) 0x2 <<  2) /* (PMC) Selected clock divided by 4 */
-#define AT91C_PMC_PRES_CLK_8	((unsigned int) 0x3 <<  2) /* (PMC) Selected clock divided by 8 */
-#define AT91C_PMC_PRES_CLK_16	((unsigned int) 0x4 <<  2) /* (PMC) Selected clock divided by 16 */
-#define AT91C_PMC_PRES_CLK_32	((unsigned int) 0x5 <<  2) /* (PMC) Selected clock divided by 32 */
-#define AT91C_PMC_PRES_CLK_64	((unsigned int) 0x6 <<  2) /* (PMC) Selected clock divided by 64 */
-#define AT91C_PMC_MDIV		((unsigned int) 0x3 <<  8) /* (PMC) Master Clock Division */
-#define AT91C_PMC_MDIV_1	((unsigned int) 0x0 <<  8) /* (PMC) The master clock and the processor clock are the same */
-#define AT91C_PMC_MDIV_2	((unsigned int) 0x1 <<  8) /* (PMC) The processor clock is twice as fast as the master clock */
-#define AT91C_PMC_MDIV_3	((unsigned int) 0x2 <<  8) /* (PMC) The processor clock is three times faster than the master clock */
-#define AT91C_PMC_MDIV_4	((unsigned int) 0x3 <<  8) /* (PMC) The processor clock is four times faster than the master clock */
-/*------ PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register --------*/
-/*------ PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------*/
-#define AT91C_PMC_MOSCS		((unsigned int) 0x1 <<  0) /* (PMC) MOSC Status/Enable/Disable/Mask */
-#define AT91C_PMC_LOCKA		((unsigned int) 0x1 <<  1) /* (PMC) PLL A Status/Enable/Disable/Mask */
-#define AT91C_PMC_LOCKB		((unsigned int) 0x1 <<  2) /* (PMC) PLL B Status/Enable/Disable/Mask */
-#define AT91C_PMC_MCKRDY	((unsigned int) 0x1 <<  3) /* (PMC) MCK_RDY Status/Enable/Disable/Mask */
-#define AT91C_PMC_PCK0RDY	((unsigned int) 0x1 <<  8) /* (PMC) PCK0_RDY Status/Enable/Disable/Mask */
-#define AT91C_PMC_PCK1RDY	((unsigned int) 0x1 <<  9) /* (PMC) PCK1_RDY Status/Enable/Disable/Mask */
-#define AT91C_PMC_PCK2RDY	((unsigned int) 0x1 << 10) /* (PMC) PCK2_RDY Status/Enable/Disable/Mask */
-#define AT91C_PMC_PCK3RDY	((unsigned int) 0x1 << 11) /* (PMC) PCK3_RDY Status/Enable/Disable/Mask */
-#define AT91C_PMC_PCK4RDY	((unsigned int) 0x1 << 12) /* (PMC) PCK4_RDY Status/Enable/Disable/Mask */
-#define AT91C_PMC_PCK5RDY	((unsigned int) 0x1 << 13) /* (PMC) PCK5_RDY Status/Enable/Disable/Mask */
-#define AT91C_PMC_PCK6RDY	((unsigned int) 0x1 << 14) /* (PMC) PCK6_RDY Status/Enable/Disable/Mask */
-#define AT91C_PMC_PCK7RDY	((unsigned int) 0x1 << 15) /* (PMC) PCK7_RDY Status/Enable/Disable/Mask */
-/*---- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register --------*/
-/*-------- PMC_SR : (PMC Offset: 0x68) PMC Status Register --------*/
-/*-------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register --------*/
-
-/*****************************************************************************/
-/*              SOFTWARE API DEFINITION  FOR Ethernet MAC                    */
-/*****************************************************************************/
-typedef struct _AT91S_EMAC
-{
-	AT91_REG	 EMAC_CTL;	/* Network Control Register */
-	AT91_REG	 EMAC_CFG;	/* Network Configuration Register */
-	AT91_REG	 EMAC_SR;	/* Network Status Register */
-	AT91_REG	 EMAC_TAR;	/* Transmit Address Register */
-	AT91_REG	 EMAC_TCR;	/* Transmit Control Register */
-	AT91_REG	 EMAC_TSR;	/* Transmit Status Register */
-	AT91_REG	 EMAC_RBQP;	/* Receive Buffer Queue Pointer */
-	AT91_REG	 Reserved0[1];	/*  */
-	AT91_REG	 EMAC_RSR;	/* Receive Status Register */
-	AT91_REG	 EMAC_ISR;	/* Interrupt Status Register */
-	AT91_REG	 EMAC_IER;	/* Interrupt Enable Register */
-	AT91_REG	 EMAC_IDR;	/* Interrupt Disable Register */
-	AT91_REG	 EMAC_IMR;	/* Interrupt Mask Register */
-	AT91_REG	 EMAC_MAN;	/* PHY Maintenance Register */
-	AT91_REG	 Reserved1[2];	/*  */
-	AT91_REG	 EMAC_FRA;	/* Frames Transmitted OK Register */
-	AT91_REG	 EMAC_SCOL;	/* Single Collision Frame Register */
-	AT91_REG	 EMAC_MCOL;	/* Multiple Collision Frame Register */
-	AT91_REG	 EMAC_OK;	/* Frames Received OK Register */
-	AT91_REG	 EMAC_SEQE;	/* Frame Check Sequence Error Register */
-	AT91_REG	 EMAC_ALE;	/* Alignment Error Register */
-	AT91_REG	 EMAC_DTE;	/* Deferred Transmission Frame Register */
-	AT91_REG	 EMAC_LCOL;	/* Late Collision Register */
-	AT91_REG	 EMAC_ECOL;	/* Excessive Collision Register */
-	AT91_REG	 EMAC_CSE;	/* Carrier Sense Error Register */
-	AT91_REG	 EMAC_TUE;	/* Transmit Underrun Error Register */
-	AT91_REG	 EMAC_CDE;	/* Code Error Register */
-	AT91_REG	 EMAC_ELR;	/* Excessive Length Error Register */
-	AT91_REG	 EMAC_RJB;	/* Receive Jabber Register */
-	AT91_REG	 EMAC_USF;	/* Undersize Frame Register */
-	AT91_REG	 EMAC_SQEE;	/* SQE Test Error Register */
-	AT91_REG	 EMAC_DRFC;	/* Discarded RX Frame Register */
-	AT91_REG	 Reserved2[3];	/*  */
-	AT91_REG	 EMAC_HSH;	/* Hash Address High[63:32] */
-	AT91_REG	 EMAC_HSL;	/* Hash Address Low[31:0] */
-	AT91_REG	 EMAC_SA1L;	/* Specific Address 1 Low, First 4 bytes */
-	AT91_REG	 EMAC_SA1H;	/* Specific Address 1 High, Last 2 bytes */
-	AT91_REG	 EMAC_SA2L;	/* Specific Address 2 Low, First 4 bytes */
-	AT91_REG	 EMAC_SA2H;	/* Specific Address 2 High, Last 2 bytes */
-	AT91_REG	 EMAC_SA3L;	/* Specific Address 3 Low, First 4 bytes */
-	AT91_REG	 EMAC_SA3H;	/* Specific Address 3 High, Last 2 bytes */
-	AT91_REG	 EMAC_SA4L;	/* Specific Address 4 Low, First 4 bytes */
-	AT91_REG	 EMAC_SA4H;	/* Specific Address 4 High, Last 2 bytesr */
-} AT91S_EMAC, *AT91PS_EMAC;
-
-/* -------- EMAC_CTL : (EMAC Offset: 0x0)  --------  */
-#define AT91C_EMAC_LB		((unsigned int) 0x1 <<  0) /* (EMAC) Loopback. Optional. When set, loopback signal is at high level. */
-#define AT91C_EMAC_LBL		((unsigned int) 0x1 <<  1) /* (EMAC) Loopback local. */
-#define AT91C_EMAC_RE		((unsigned int) 0x1 <<  2) /* (EMAC) Receive enable. */
-#define AT91C_EMAC_TE		((unsigned int) 0x1 <<  3) /* (EMAC) Transmit enable. */
-#define AT91C_EMAC_MPE		((unsigned int) 0x1 <<  4) /* (EMAC) Management port enable. */
-#define AT91C_EMAC_CSR		((unsigned int) 0x1 <<  5) /* (EMAC) Clear statistics registers. */
-#define AT91C_EMAC_ISR		((unsigned int) 0x1 <<  6) /* (EMAC) Increment statistics registers. */
-#define AT91C_EMAC_WES		((unsigned int) 0x1 <<  7) /* (EMAC) Write enable for statistics registers. */
-#define AT91C_EMAC_BP		((unsigned int) 0x1 <<  8) /* (EMAC) Back pressure. */
-
-/* -------- EMAC_CFG : (EMAC Offset: 0x4) Network Configuration Register --------  */
-#define AT91C_EMAC_SPD		((unsigned int) 0x1 <<  0) /* (EMAC) Speed. */
-#define AT91C_EMAC_FD		((unsigned int) 0x1 <<  1) /* (EMAC) Full duplex. */
-#define AT91C_EMAC_BR		((unsigned int) 0x1 <<  2) /* (EMAC) Bit rate. */
-#define AT91C_EMAC_CAF		((unsigned int) 0x1 <<  4) /* (EMAC) Copy all frames. */
-#define AT91C_EMAC_NBC		((unsigned int) 0x1 <<  5) /* (EMAC) No broadcast. */
-#define AT91C_EMAC_MTI		((unsigned int) 0x1 <<  6) /* (EMAC) Multicast hash enable */
-#define AT91C_EMAC_UNI		((unsigned int) 0x1 <<  7) /* (EMAC) Unicast hash enable. */
-#define AT91C_EMAC_BIG		((unsigned int) 0x1 <<  8) /* (EMAC) Receive 1522 bytes. */
-#define AT91C_EMAC_EAE		((unsigned int) 0x1 <<  9) /* (EMAC) External address match enable. */
-#define AT91C_EMAC_CLK		((unsigned int) 0x3 << 10) /* (EMAC) */
-#define AT91C_EMAC_CLK_HCLK_8	((unsigned int) 0x0 << 10) /* (EMAC) HCLK divided by 8 */
-#define AT91C_EMAC_CLK_HCLK_16	((unsigned int) 0x1 << 10) /* (EMAC) HCLK divided by 16 */
-#define AT91C_EMAC_CLK_HCLK_32	((unsigned int) 0x2 << 10) /* (EMAC) HCLK divided by 32 */
-#define AT91C_EMAC_CLK_HCLK_64	((unsigned int) 0x3 << 10) /* (EMAC) HCLK divided by 64 */
-#define AT91C_EMAC_RTY		((unsigned int) 0x1 << 12) /* (EMAC) */
-#define AT91C_EMAC_RMII		((unsigned int) 0x1 << 13) /* (EMAC) */
-
-/* -------- EMAC_SR : (EMAC Offset: 0x8) Network Status Register --------  */
-#define AT91C_EMAC_MDIO		((unsigned int) 0x1 <<  1) /* (EMAC) */
-#define AT91C_EMAC_IDLE		((unsigned int) 0x1 <<  2) /* (EMAC) */
-
-/* -------- EMAC_TCR : (EMAC Offset: 0x10) Transmit Control Register ------- */
-#define AT91C_EMAC_LEN		((unsigned int) 0x7FF <<  0) /* (EMAC) */
-#define AT91C_EMAC_NCRC		((unsigned int) 0x1 << 15) /* (EMAC) */
-
-/* -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Control Register ------- */
-#define AT91C_EMAC_OVR		((unsigned int) 0x1 <<  0) /* (EMAC) */
-#define AT91C_EMAC_COL		((unsigned int) 0x1 <<  1) /* (EMAC) */
-#define AT91C_EMAC_RLE		((unsigned int) 0x1 <<  2) /* (EMAC) */
-#define AT91C_EMAC_TXIDLE	((unsigned int) 0x1 <<  3) /* (EMAC) */
-#define AT91C_EMAC_BNQ		((unsigned int) 0x1 <<  4) /* (EMAC) */
-#define AT91C_EMAC_COMP		((unsigned int) 0x1 <<  5) /* (EMAC) */
-#define AT91C_EMAC_UND		((unsigned int) 0x1 <<  6) /* (EMAC) */
-
-/* -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- */
-#define AT91C_EMAC_BNA		((unsigned int) 0x1 <<  0) /* (EMAC) */
-#define AT91C_EMAC_REC		((unsigned int) 0x1 <<  1) /* (EMAC) */
-#define AT91C_EMAC_RSR_OVR	((unsigned int) 0x1 <<  2) /* (EMAC) */
-
-/* -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register ------- */
-#define AT91C_EMAC_DONE		((unsigned int) 0x1 <<  0) /* (EMAC) */
-#define AT91C_EMAC_RCOM		((unsigned int) 0x1 <<  1) /* (EMAC) */
-#define AT91C_EMAC_RBNA		((unsigned int) 0x1 <<  2) /* (EMAC) */
-#define AT91C_EMAC_TOVR		((unsigned int) 0x1 <<  3) /* (EMAC) */
-#define AT91C_EMAC_TUND		((unsigned int) 0x1 <<  4) /* (EMAC) */
-#define AT91C_EMAC_RTRY		((unsigned int) 0x1 <<  5) /* (EMAC) */
-#define AT91C_EMAC_TBRE		((unsigned int) 0x1 <<  6) /* (EMAC) */
-#define AT91C_EMAC_TCOM		((unsigned int) 0x1 <<  7) /* (EMAC) */
-#define AT91C_EMAC_TIDLE	((unsigned int) 0x1 <<  8) /* (EMAC) */
-#define AT91C_EMAC_LINK		((unsigned int) 0x1 <<  9) /* (EMAC) */
-#define AT91C_EMAC_ROVR		((unsigned int) 0x1 << 10) /* (EMAC) */
-#define AT91C_EMAC_HRESP	((unsigned int) 0x1 << 11) /* (EMAC) */
-
-/* -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register ------- */
-/* -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register ------ */
-/* -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- */
-/* -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- */
-#define AT91C_EMAC_DATA		((unsigned int) 0xFFFF <<  0) /* (EMAC) */
-#define AT91C_EMAC_CODE		((unsigned int) 0x3  << 16) /* (EMAC) */
-#define AT91C_EMAC_CODE_802_3	((unsigned int) 0x2  << 16) /* (EMAC) Write Operation */
-#define AT91C_EMAC_REGA		((unsigned int) 0x1F << 18) /* (EMAC) */
-#define AT91C_EMAC_PHYA		((unsigned int) 0x1F << 23) /* (EMAC) */
-#define AT91C_EMAC_RW		((unsigned int) 0x3  << 28) /* (EMAC) */
-#define AT91C_EMAC_RW_R		((unsigned int) 0x2  << 28) /* (EMAC) Read Operation */
-#define AT91C_EMAC_RW_W		((unsigned int) 0x1  << 28) /* (EMAC) Write Operation */
-#define AT91C_EMAC_HIGH		((unsigned int) 0x1  << 30) /* (EMAC) */
-#define AT91C_EMAC_LOW		((unsigned int) 0x1  << 31) /* (EMAC) */
-
-/*****************************************************************************/
-/*           SOFTWARE API DEFINITION  FOR Serial Parallel Interface          */
-/*****************************************************************************/
-typedef struct _AT91S_SPI
-{
-	AT91_REG	 SPI_CR;	/* Control Register */
-	AT91_REG	 SPI_MR;	/* Mode Register */
-	AT91_REG	 SPI_RDR;	/* Receive Data Register */
-	AT91_REG	 SPI_TDR;	/* Transmit Data Register */
-	AT91_REG	 SPI_SR;	/* Status Register */
-	AT91_REG	 SPI_IER;	/* Interrupt Enable Register */
-	AT91_REG	 SPI_IDR;	/* Interrupt Disable Register */
-	AT91_REG	 SPI_IMR;	/* Interrupt Mask Register */
-	AT91_REG	 Reserved0[4];	/* */
-	AT91_REG	 SPI_CSR[4];	/* Chip Select Register */
-	AT91_REG	 Reserved1[48]; /* */
-	AT91_REG	 SPI_RPR;	/* Receive Pointer Register */
-	AT91_REG	 SPI_RCR;	/* Receive Counter Register */
-	AT91_REG	 SPI_TPR;	/* Transmit Pointer Register */
-	AT91_REG	 SPI_TCR;	/* Transmit Counter Register */
-	AT91_REG	 SPI_RNPR;	/* Receive Next Pointer Register */
-	AT91_REG	 SPI_RNCR;	/* Receive Next Counter Register */
-	AT91_REG	 SPI_TNPR;	/* Transmit Next Pointer Register */
-	AT91_REG	 SPI_TNCR;	/* Transmit Next Counter Register */
-	AT91_REG	 SPI_PTCR;	/* PDC Transfer Control Register */
-	AT91_REG	 SPI_PTSR;	/* PDC Transfer Status Register */
-} AT91S_SPI, *AT91PS_SPI;
-
-/* -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- */
-#define AT91C_SPI_SPIEN		((unsigned int) 0x1 <<  0) /* (SPI) SPI Enable */
-#define AT91C_SPI_SPIDIS	((unsigned int) 0x1 <<  1) /* (SPI) SPI Disable */
-#define AT91C_SPI_SWRST		((unsigned int) 0x1 <<  7) /* (SPI) SPI Software reset */
-
-/* -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- */
-#define AT91C_SPI_MSTR		((unsigned int) 0x1 <<  0) /* (SPI) Master/Slave Mode */
-#define AT91C_SPI_PS		((unsigned int) 0x1 <<  1) /* (SPI) Peripheral Select */
-#define AT91C_SPI_PS_FIXED	((unsigned int) 0x0 <<  1) /* (SPI) Fixed Peripheral Select */
-#define AT91C_SPI_PS_VARIABLE	((unsigned int) 0x1 <<  1) /* (SPI) Variable Peripheral Select */
-#define AT91C_SPI_PCSDEC	((unsigned int) 0x1 <<  2) /* (SPI) Chip Select Decode */
-#define AT91C_SPI_DIV32		((unsigned int) 0x1 <<  3) /* (SPI) Clock Selection */
-#define AT91C_SPI_MODFDIS	((unsigned int) 0x1 <<  4) /* (SPI) Mode Fault Detection */
-#define AT91C_SPI_LLB		((unsigned int) 0x1 <<  7) /* (SPI) Clock Selection */
-#define AT91C_SPI_PCS		((unsigned int) 0xF << 16) /* (SPI) Peripheral Chip Select */
-#define AT91C_SPI_DLYBCS	((unsigned int) 0xFF << 24) /* (SPI) Delay Between Chip Selects */
-
-/* -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- */
-#define AT91C_SPI_RD		((unsigned int) 0xFFFF <<  0) /* (SPI) Receive Data */
-#define AT91C_SPI_RPCS		((unsigned int) 0xF << 16) /* (SPI) Peripheral Chip Select Status */
-
-/* -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- */
-#define AT91C_SPI_TD		((unsigned int) 0xFFFF <<  0) /* (SPI) Transmit Data */
-#define AT91C_SPI_TPCS		((unsigned int) 0xF << 16) /* (SPI) Peripheral Chip Select Status */
-
-/* -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- */
-#define AT91C_SPI_RDRF		((unsigned int) 0x1 <<  0) /* (SPI) Receive Data Register Full */
-#define AT91C_SPI_TDRE		((unsigned int) 0x1 <<  1) /* (SPI) Transmit Data Register Empty */
-#define AT91C_SPI_MODF		((unsigned int) 0x1 <<  2) /* (SPI) Mode Fault Error */
-#define AT91C_SPI_OVRES		((unsigned int) 0x1 <<  3) /* (SPI) Overrun Error Status */
-#define AT91C_SPI_SPENDRX	((unsigned int) 0x1 <<  4) /* (SPI) End of Receiver Transfer */
-#define AT91C_SPI_SPENDTX	((unsigned int) 0x1 <<  5) /* (SPI) End of Receiver Transfer */
-#define AT91C_SPI_RXBUFF	((unsigned int) 0x1 <<  6) /* (SPI) RXBUFF Interrupt */
-#define AT91C_SPI_TXBUFE	((unsigned int) 0x1 <<  7) /* (SPI) TXBUFE Interrupt */
-#define AT91C_SPI_SPIENS	((unsigned int) 0x1 << 16) /* (SPI) Enable Status */
-
-/* -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- */
-/* -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register ------- */
-/* -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- */
-/* -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- */
-#define AT91C_SPI_CPOL		((unsigned int) 0x1  <<  0) /* (SPI) Clock Polarity */
-#define AT91C_SPI_NCPHA		((unsigned int) 0x1  <<  1) /* (SPI) Clock Phase */
-#define AT91C_SPI_BITS		((unsigned int) 0xF  <<  4) /* (SPI) Bits Per Transfer */
-#define AT91C_SPI_BITS_8	((unsigned int) 0x0  <<  4) /* (SPI) 8 Bits Per transfer */
-#define AT91C_SPI_BITS_9	((unsigned int) 0x1  <<  4) /* (SPI) 9 Bits Per transfer */
-#define AT91C_SPI_BITS_10	((unsigned int) 0x2  <<  4) /* (SPI) 10 Bits Per transfer */
-#define AT91C_SPI_BITS_11	((unsigned int) 0x3  <<  4) /* (SPI) 11 Bits Per transfer */
-#define AT91C_SPI_BITS_12	((unsigned int) 0x4  <<  4) /* (SPI) 12 Bits Per transfer */
-#define AT91C_SPI_BITS_13	((unsigned int) 0x5  <<  4) /* (SPI) 13 Bits Per transfer */
-#define AT91C_SPI_BITS_14	((unsigned int) 0x6  <<  4) /* (SPI) 14 Bits Per transfer */
-#define AT91C_SPI_BITS_15	((unsigned int) 0x7  <<  4) /* (SPI) 15 Bits Per transfer */
-#define AT91C_SPI_BITS_16	((unsigned int) 0x8  <<  4) /* (SPI) 16 Bits Per transfer */
-#define AT91C_SPI_SCBR		((unsigned int) 0xFF <<  8) /* (SPI) Serial Clock Baud Rate */
-#define AT91C_SPI_DLYBS		((unsigned int) 0xFF << 16) /* (SPI) Serial Clock Baud Rate */
-#define AT91C_SPI_DLYBCT	((unsigned int) 0xFF << 24) /* (SPI) Delay Between Consecutive Transfers */
-
-/*****************************************************************************/
-/*           SOFTWARE API DEFINITION  FOR Peripheral Data Controller         */
-/*****************************************************************************/
-typedef struct _AT91S_PDC
-{
-	AT91_REG	 PDC_RPR;	/* Receive Pointer Register */
-	AT91_REG	 PDC_RCR;	/* Receive Counter Register */
-	AT91_REG	 PDC_TPR;	/* Transmit Pointer Register */
-	AT91_REG	 PDC_TCR;	/* Transmit Counter Register */
-	AT91_REG	 PDC_RNPR;	/* Receive Next Pointer Register */
-	AT91_REG	 PDC_RNCR;	/* Receive Next Counter Register */
-	AT91_REG	 PDC_TNPR;	/* Transmit Next Pointer Register */
-	AT91_REG	 PDC_TNCR;	/* Transmit Next Counter Register */
-	AT91_REG	 PDC_PTCR;	/* PDC Transfer Control Register */
-	AT91_REG	 PDC_PTSR;	/* PDC Transfer Status Register */
-} AT91S_PDC, *AT91PS_PDC;
-
-/* -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- */
-#define AT91C_PDC_RXTEN		((unsigned int) 0x1 <<  0) /* (PDC) Receiver Transfer Enable */
-#define AT91C_PDC_RXTDIS	((unsigned int) 0x1 <<  1) /* (PDC) Receiver Transfer Disable */
-#define AT91C_PDC_TXTEN		((unsigned int) 0x1 <<  8) /* (PDC) Transmitter Transfer Enable */
-#define AT91C_PDC_TXTDIS	((unsigned int) 0x1 <<  9) /* (PDC) Transmitter Transfer Disable */
-/* -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register --------  */
-
-/* ========== Register definition ==================================== */
-#define AT91C_SPI_CSR		((AT91_REG *)	0xFFFE0030) /* (SPI) Chip Select Register */
-#define AT91C_PMC_PCER		((AT91_REG *)	0xFFFFFC10) /* (PMC) Peripheral Clock Enable Register */
-#define AT91C_PMC_PCDR		((AT91_REG *)	0xFFFFFC14) /* (PMC) Peripheral Clock Enable Register */
-#define AT91C_PMC_SCER		((AT91_REG *)	0xFFFFFC00) /* (PMC) Peripheral Clock Enable Register */
-#define AT91C_PMC_SCDR		((AT91_REG *)	0xFFFFFC04) /* (PMC) Peripheral Clock Enable Register */
-#define AT91C_PIOA_PER		((AT91_REG *)	0xFFFFF400) /* (PIOA) PIO Enable Register */
-#define AT91C_PIOA_PDR		((AT91_REG *)	0xFFFFF404) /* (PIOA) PIO Disable Register */
-#define AT91C_PIOA_PSR		((AT91_REG *)	0xFFFFF408) /* (PIOA) PIO Status Register */
-#define AT91C_PIOA_OER		((AT91_REG *)	0xFFFFF410) /* (PIOA) PIO Output Enable Register */
-#define AT91C_PIOA_ODR		((AT91_REG *)	0xFFFFF414) /* (PIOA) PIO Output Disable Register */
-#define AT91C_PIOA_OSR		((AT91_REG *)	0xFFFFF418) /* (PIOA) PIO Output Status Register */
-#define AT91C_PIOA_IFER		((AT91_REG *)	0xFFFFF420) /* (PIOA) PIO Glitch Input Filter Enable Register */
-#define AT91C_PIOA_IFDR		((AT91_REG *)	0xFFFFF424) /* (PIOA) PIO Glitch Input Filter Disable Register */
-#define AT91C_PIOA_IFSR		((AT91_REG *)	0xFFFFF428) /* (PIOA) PIO Glitch Input Filter Status Register */
-#define AT91C_PIOA_SODR		((AT91_REG *)	0xFFFFF430) /* (PIOA) PIO Set Output Data Register */
-#define AT91C_PIOA_CODR		((AT91_REG *)	0xFFFFF434) /* (PIOA) PIO Clear Output Data Register */
-#define AT91C_PIOA_ODSR		((AT91_REG *)	0xFFFFF438) /* (PIOA) PIO Output Data Status Register */
-#define AT91C_PIOA_PDSR		((AT91_REG *)	0xFFFFF43C) /* (PIOA) PIO Pin Data Status Register */
-#define AT91C_PIOA_IER		((AT91_REG *)	0xFFFFF440) /* (PIOA) PIO Interrupt Enable Register */
-#define AT91C_PIOA_IDR		((AT91_REG *)	0xFFFFF444) /* (PIOA) PIO Interrupt Disable Register */
-#define AT91C_PIOA_IMR		((AT91_REG *)	0xFFFFF448) /* (PIOA) PIO Interrupt Mask Register */
-#define AT91C_PIOA_ISR		((AT91_REG *)	0xFFFFF44C) /* (PIOA) PIO Interrupt Status Register */
-#define AT91C_PIOA_MDER		((AT91_REG *)	0xFFFFF450) /* (PIOA) PIO Multi-drive Enable Register */
-#define AT91C_PIOA_MDDR		((AT91_REG *)	0xFFFFF454) /* (PIOA) PIO Multi-drive Disable Register */
-#define AT91C_PIOA_MDSR		((AT91_REG *)	0xFFFFF458) /* (PIOA) PIO Multi-drive Status Register */
-#define AT91C_PIOA_PUDR		((AT91_REG *)	0xFFFFF460) /* (PIOA) PIO Pull-up Disable Register */
-#define AT91C_PIOA_PUER		((AT91_REG *)	0xFFFFF464) /* (PIOA) PIO Pull-up Enable Register */
-#define AT91C_PIOA_PUSR		((AT91_REG *)	0xFFFFF468) /* (PIOA) PIO Pull-up Status Register */
-#define AT91C_PIOA_ASR		((AT91_REG *)	0xFFFFF470) /* (PIOA) PIO Peripheral A Select Register */
-#define AT91C_PIOA_BSR		((AT91_REG *)	0xFFFFF474) /* (PIOA) PIO Peripheral B Select Register */
-#define AT91C_PIOA_ABSR		((AT91_REG *)	0xFFFFF478) /* (PIOA) PIO Peripheral AB Select Register */
-#define AT91C_PIOA_OWER		((AT91_REG *)	0xFFFFF4A0) /* (PIOA) PIO Output Write Enable Register */
-#define AT91C_PIOA_OWDR		((AT91_REG *)	0xFFFFF4A4) /* (PIOA) PIO Output Write Disable Register */
-#define AT91C_PIOA_OWSR		((AT91_REG *)	0xFFFFF4A8) /* (PIOA) PIO Output Write Status Register */
-#define AT91C_PIOB_PDR		((AT91_REG *)	0xFFFFF604) /* (PIOB) PIO Disable Register */
-
-#define AT91C_PIO_PA30		((unsigned int) 1 << 30)	/* Pin Controlled by PA30 */
-#define AT91C_PIO_PC0		((unsigned int) 1 <<  0)	/* Pin Controlled by PC0 */
-#define AT91C_PC0_BFCK		((unsigned int) AT91C_PIO_PC0)	/* Burst Flash Clock */
-#define AT91C_PA30_DRXD		((unsigned int) AT91C_PIO_PA30)	/* DBGU Debug Receive Data */
-#define AT91C_PIO_PA31		((unsigned int) 1 << 31)	/* Pin Controlled by PA31 */
-#define AT91C_PA25_TWD		((unsigned int) 1 << 25)
-#define AT91C_PA26_TWCK		((unsigned int) 1 << 26)
-#define AT91C_PA31_DTXD		((unsigned int) AT91C_PIO_PA31)	/* DBGU Debug Transmit Data */
-#define AT91C_PIO_PA17		((unsigned int) 1 << 17)	/* Pin Controlled by PA17 */
-#define AT91C_PA17_TXD0		AT91C_PIO_PA17			/* USART0 Transmit Data */
-#define AT91C_PIO_PA18		((unsigned int) 1 << 18)	/* Pin Controlled by PA18 */
-#define AT91C_PA18_RXD0		AT91C_PIO_PA18			/* USART0 Receive Data */
-#define AT91C_PIO_PB20		((unsigned int) 1 << 20)	/* Pin Controlled by PB20 */
-#define AT91C_PB20_RXD1		AT91C_PIO_PB20			/* USART1 Receive Data */
-#define AT91C_PIO_PB21		((unsigned int) 1 << 21)	/* Pin Controlled by PB21 */
-#define AT91C_PB21_TXD1		AT91C_PIO_PB21			/* USART1 Transmit Data */
-
-#define AT91C_ID_SYS		((unsigned int)  1) /* System Peripheral */
-#define AT91C_ID_PIOA		((unsigned int)  2) /* PIO port A */
-#define AT91C_ID_PIOB		((unsigned int)  3) /* PIO port B */
-#define AT91C_ID_PIOC		((unsigned int)  4) /* PIO port C */
-#define AT91C_ID_USART0		((unsigned int)  6) /* USART 0 */
-#define AT91C_ID_USART1		((unsigned int)  7) /* USART 1 */
-#define AT91C_ID_TWI		((unsigned int) 12) /* Two Wire Interface */
-#define AT91C_ID_SPI		((unsigned int) 13) /* Serial Peripheral Interface */
-#define AT91C_ID_TC0		((unsigned int) 17) /* Timer Counter 0 */
-#define AT91C_ID_UHP		((unsigned int) 23) /* OHCI USB Host Port */
-#define AT91C_ID_EMAC		((unsigned int) 24) /* Ethernet MAC */
-
-#define AT91C_PIO_PC1		((unsigned int) 1 <<  1)	/* Pin Controlled by PC1 */
-#define AT91C_PC1_BFRDY_SMOE	((unsigned int) AT91C_PIO_PC1)	/*  Burst Flash Ready */
-#define AT91C_PIO_PC3		((unsigned int) 1 <<  3)	/* Pin Controlled by PC3 */
-#define AT91C_PC3_BFBAA_SMWE	((unsigned int) AT91C_PIO_PC3)	/*  Burst Flash Address Advance / SmartMedia Write Enable */
-#define AT91C_PIO_PC2		((unsigned int) 1 <<  2)	/* Pin Controlled by PC2 */
-#define AT91C_PC2_BFAVD		((unsigned int) AT91C_PIO_PC2)	/*  Burst Flash Address Valid */
-#define AT91C_PIO_PB1		((unsigned int) 1 <<  1)	/* Pin Controlled by PB1 */
-
-#define AT91C_PIO_PA23		((unsigned int) 1 << 23)	/* Pin Controlled by PA23 */
-#define AT91C_PA23_TXD2		((unsigned int) AT91C_PIO_PA23)	/* USART 2 Transmit Data */
-
-#define AT91C_PIO_PA0		((unsigned int) 1 <<  0)	/* Pin Controlled by PA0 */
-#define AT91C_PA0_MISO		((unsigned int) AT91C_PIO_PA0)	/* SPI Master In Slave */
-#define AT91C_PIO_PA1		((unsigned int) 1 <<  1)	/* Pin Controlled by PA1 */
-#define AT91C_PA1_MOSI		((unsigned int) AT91C_PIO_PA1)	/* SPI Master Out Slave */
-#define AT91C_PIO_PA2		((unsigned int) 1 <<  2)	/* Pin Controlled by PA2 */
-#define AT91C_PA2_SPCK		((unsigned int) AT91C_PIO_PA2)	/* SPI Serial Clock */
-#define AT91C_PIO_PA3		((unsigned int) 1 <<  3)	/* Pin Controlled by PA3 */
-#define AT91C_PA3_NPCS0		((unsigned int) AT91C_PIO_PA3)	/* SPI Peripheral Chip Select 0 */
-#define AT91C_PIO_PA4		((unsigned int) 1 <<  4)	/* Pin Controlled by PA4 */
-#define AT91C_PA4_NPCS1		((unsigned int) AT91C_PIO_PA4)	/* SPI Peripheral Chip Select 1 */
-#define AT91C_PIO_PA5		((unsigned int) 1 <<  5)	/* Pin Controlled by PA5 */
-#define AT91C_PA5_NPCS2		((unsigned int) AT91C_PIO_PA5)	/* SPI Peripheral Chip Select 2 */
-#define AT91C_PIO_PA6		((unsigned int) 1 <<  6)	/* Pin Controlled by PA6 */
-#define AT91C_PA6_NPCS3		((unsigned int) AT91C_PIO_PA6)	/* SPI Peripheral Chip Select 3 */
-
-#define AT91C_PIO_PA16		((unsigned int) 1 << 16)	/* Pin Controlled by PA16 */
-#define AT91C_PA16_EMDIO	((unsigned int) AT91C_PIO_PA16)	/* Ethernet MAC Management Data Input/Output */
-#define AT91C_PIO_PA15		((unsigned int) 1 << 15)	/* Pin Controlled by PA15 */
-#define AT91C_PA15_EMDC		((unsigned int) AT91C_PIO_PA15)	/* Ethernet MAC Management Data Clock */
-#define AT91C_PIO_PA14		((unsigned int) 1 << 14)	/* Pin Controlled by PA14 */
-#define AT91C_PA14_ERXER	((unsigned int) AT91C_PIO_PA14)	/* Ethernet MAC Receive Error */
-#define AT91C_PIO_PA13		((unsigned int) 1 << 13)	/* Pin Controlled by PA13 */
-#define AT91C_PA13_ERX1		((unsigned int) AT91C_PIO_PA13)	/* Ethernet MAC Receive Data 1 */
-#define AT91C_PIO_PA12		((unsigned int) 1 << 12)	/* Pin Controlled by PA12 */
-#define AT91C_PA12_ERX0		((unsigned int) AT91C_PIO_PA12)	/* Ethernet MAC Receive Data 0 */
-#define AT91C_PIO_PA11		((unsigned int) 1 << 11)	/* Pin Controlled by PA11 */
-#define AT91C_PA11_ECRS_ECRSDV	((unsigned int) AT91C_PIO_PA11)	/* Ethernet MAC Carrier Sense/Carrier Sense and Data Valid */
-#define AT91C_PIO_PA10		((unsigned int) 1 << 10)	/* Pin Controlled by PA10 */
-#define AT91C_PA10_ETX1		((unsigned int) AT91C_PIO_PA10)	/* Ethernet MAC Transmit Data 1 */
-#define AT91C_PIO_PA9		((unsigned int) 1 <<  9)	/* Pin Controlled by PA9 */
-#define AT91C_PA9_ETX0		((unsigned int) AT91C_PIO_PA9)	/* Ethernet MAC Transmit Data 0 */
-#define AT91C_PIO_PA8		((unsigned int) 1 <<  8)	/* Pin Controlled by PA8 */
-#define AT91C_PA8_ETXEN		((unsigned int) AT91C_PIO_PA8)	/* Ethernet MAC Transmit Enable */
-#define AT91C_PIO_PA7		((unsigned int) 1 <<  7)	/* Pin Controlled by PA7 */
-#define AT91C_PA7_ETXCK_EREFCK	((unsigned int) AT91C_PIO_PA7)	/* Ethernet MAC Transmit Clock/Reference Clock */
-
-#define AT91C_PIO_PB0		((unsigned int) 1 <<  0)	/* Pin Controlled by PB3 */
-#define AT91C_PIO_PB1		((unsigned int) 1 <<  1)	/* Pin Controlled by PB3 */
-#define AT91C_PIO_PB2		((unsigned int) 1 <<  2)	/* Pin Controlled by PB3 */
-#define AT91C_PIO_PB3		((unsigned int) 1 <<  3)	/* Pin Controlled by PB3 */
-#define AT91C_PIO_PB4		((unsigned int) 1 <<  4)	/* Pin Controlled by PB4 */
-#define AT91C_PIO_PB5		((unsigned int) 1 <<  5)	/* Pin Controlled by PB5 */
-#define AT91C_PIO_PB6		((unsigned int) 1 <<  6)	/* Pin Controlled by PB6 */
-#define AT91C_PIO_PB7		((unsigned int) 1 <<  7)	/* Pin Controlled by PB7 */
-#define AT91C_PIO_PB22		((unsigned int) 1 << 22)	/* Pin Controlled by PB22 */
-#define AT91C_PIO_PB25		((unsigned int) 1 << 25)	/* Pin Controlled by PB25 */
-#define AT91C_PB25_DSR1		((unsigned int) AT91C_PIO_PB25)	/* USART 1 Data Set ready */
-#define AT91C_PB25_EF100	((unsigned int) AT91C_PIO_PB25)	/* Ethernet MAC Force 100 Mbits */
-#define AT91C_PIO_PB19		((unsigned int) 1 << 19)	/* Pin Controlled by PB19 */
-#define AT91C_PB19_DTR1		((unsigned int) AT91C_PIO_PB19)	/* USART 1 Data Terminal ready */
-#define AT91C_PB19_ERXCK	((unsigned int) AT91C_PIO_PB19)	/* Ethernet MAC Receive Clock */
-#define AT91C_PIO_PB18		((unsigned int) 1 << 18)	/* Pin Controlled by PB18 */
-#define AT91C_PB18_RI1		((unsigned int) AT91C_PIO_PB18)	/* USART 1 Ring Indicator */
-#define AT91C_PB18_ECOL		((unsigned int) AT91C_PIO_PB18)	/* Ethernet MAC Collision Detected */
-#define AT91C_PIO_PB17		((unsigned int) 1 << 17)	/* Pin Controlled by PB17 */
-#define AT91C_PB17_RF2		((unsigned int) AT91C_PIO_PB17)	/* SSC Receive Frame Sync 2 */
-#define AT91C_PB17_ERXDV	((unsigned int) AT91C_PIO_PB17)	/* Ethernet MAC Receive Data Valid */
-#define AT91C_PIO_PB16		((unsigned int) 1 << 16)	/* Pin Controlled by PB16 */
-#define AT91C_PB16_RK2		((unsigned int) AT91C_PIO_PB16)	/* SSC Receive Clock 2 */
-#define AT91C_PB16_ERX3		((unsigned int) AT91C_PIO_PB16)	/* Ethernet MAC Receive Data 3 */
-#define AT91C_PIO_PB15		((unsigned int) 1 << 15)	/* Pin Controlled by PB15 */
-#define AT91C_PB15_RD2		((unsigned int) AT91C_PIO_PB15)	/* SSC Receive Data 2 */
-#define AT91C_PB15_ERX2		((unsigned int) AT91C_PIO_PB15)	/* Ethernet MAC Receive Data 2 */
-#define AT91C_PIO_PB14		((unsigned int) 1 << 14)	/* Pin Controlled by PB14 */
-#define AT91C_PB14_TD2		((unsigned int) AT91C_PIO_PB14)	/* SSC Transmit Data 2 */
-#define AT91C_PB14_ETXER	((unsigned int) AT91C_PIO_PB14)	/* Ethernet MAC Transmikt Coding Error */
-#define AT91C_PIO_PB13		((unsigned int) 1 << 13)	/* Pin Controlled by PB13 */
-#define AT91C_PB13_TK2		((unsigned int) AT91C_PIO_PB13)	/* SSC Transmit Clock 2 */
-#define AT91C_PB13_ETX3		((unsigned int) AT91C_PIO_PB13)	/* Ethernet MAC Transmit Data 3 */
-#define AT91C_PIO_PB12		((unsigned int) 1 << 12)	/* Pin Controlled by PB12 */
-#define AT91C_PB12_TF2		((unsigned int) AT91C_PIO_PB12)	/* SSC Transmit Frame Sync 2 */
-#define AT91C_PB12_ETX2		((unsigned int) AT91C_PIO_PB12)	/* Ethernet MAC Transmit Data 2 */
-
-#define AT91C_PIOB_BSR		((AT91_REG *)	0xFFFFF674)	/* (PIOB) Select B Register */
-#define AT91C_PIOB_PDR		((AT91_REG *)	0xFFFFF604)	/* (PIOB) PIO Disable Register */
-
-#define AT91C_EBI_CS3A_SMC_SmartMedia	((unsigned int) 0x1 <<  3) /* (EBI) Chip Select 3 is assigned to the Static Memory Controller and the SmartMedia Logic is activated. */
-#define AT91C_SMC2_ACSS_STANDARD	((unsigned int) 0x0 << 16) /* (SMC2) Standard, asserted at the beginning of the access and deasserted at the end. */
-#define AT91C_SMC2_DBW_8	((unsigned int) 0x2 << 13) /* (SMC2) 8-bit. */
-#define AT91C_SMC2_WSEN		((unsigned int) 0x1 <<  7) /* (SMC2) Wait State Enable */
-#define AT91C_PIOC_ASR		((AT91_REG *)	0xFFFFF870) /* (PIOC) Select A Register */
-#define AT91C_PIOC_SODR		((AT91_REG *)	0xFFFFF830) /* (PIOC) Set Output Data Register */
-#define AT91C_PIOC_CODR		((AT91_REG *)	0xFFFFF834) /* (PIOC) Clear Output Data Register */
-#define AT91C_PIOC_PDSR		((AT91_REG *)	0xFFFFF83C) /* (PIOC) Pin Data Status Register */
-
-#define AT91C_BASE_AIC		((AT91PS_AIC)	0xFFFFF000) /* (AIC) Base Address */
-#define AT91C_BASE_DBGU		((AT91PS_DBGU)	0xFFFFF200) /* (DBGU) Base Address */
-#define AT91C_BASE_PIOA		((AT91PS_PIO)	0xFFFFF400) /* (PIOA) Base Address */
-#define AT91C_BASE_PIOB		((AT91PS_PIO)	0xFFFFF600) /* (PIOB) Base Address */
-#define AT91C_BASE_PIOC		((AT91PS_PIO)	0xFFFFF800) /* (PIOC) Base Address */
-#define AT91C_BASE_PIOD		((AT91PS_PIO)	0xFFFFFA00) /* (PIOC) Base Address */
-#define AT91C_BASE_PMC		((AT91PS_PMC)	0xFFFFFC00) /* (PMC) Base Address */
-#if	0
-#define AT91C_BASE_ST		((AT91PS_ST)	0xFFFFFD00) /* (PMC) Base Address */
-#define AT91C_BASE_RTC		((AT91PS_RTC)	0xFFFFFE00) /* (PMC) Base Address */
-#define AT91C_BASE_MC		((AT91PS_MC)	0xFFFFFF00) /* (PMC) Base Address */
-#endif
-
-#define AT91C_BASE_TC0		((AT91PS_TC)	0xFFFA0000) /* (TC0) Base Address */
-#define AT91C_BASE_TC1		((AT91PS_TC)	0xFFFA4000) /* (TC0) Base Address */
-#if	0
-#define AT91C_BASE_UDP		((AT91PS_UDP)	0xFFFB0000) /* (TC0) Base Address */
-#define AT91C_BASE_MCI		((AT91PS_MCI)	0xFFFB4000) /* (TC0) Base Address */
-#define AT91C_BASE_TWI		((AT91PS_TWI)	0xFFFB8000) /* (TC0) Base Address */
-#endif
-#define AT91C_BASE_EMAC		((AT91PS_EMAC)	0xFFFBC000) /* (EMAC) Base Address */
-#define AT91C_BASE_US0		((AT91PS_USART)	0xFFFC0000) /* (US0) Base Address */
-#define AT91C_BASE_US1		((AT91PS_USART) 0xFFFC4000) /* (US1) Base Address */
-#define AT91C_BASE_US2		((AT91PS_USART) 0xFFFC8000) /* (US1) Base Address */
-#define AT91C_BASE_US3		((AT91PS_USART) 0xFFFCC000) /* (US1) Base Address */
-#define AT91C_BASE_SPI		((AT91PS_SPI)	0xFFFE0000) /* (SPI) Base Address */
-
-#define AT91C_BASE_CKGR		((AT91PS_CKGR)	0xFFFFFC20) /* (CKGR) Base Address */
-#define AT91C_EBI_CSA		((AT91_REG *)	0xFFFFFF60) /* (EBI) Chip Select Assignment Register */
-#define AT91C_BASE_SMC2		((AT91PS_SMC2)	0xFFFFFF70) /* (SMC2) Base Address */
-#define AT91C_TCB0_BMR		((AT91_REG *)	0xFFFA00C4) /* (TCB0) TC Block Mode Register */
-#define AT91C_TCB0_BCR		((AT91_REG *)	0xFFFA00C0) /* (TCB0) TC Block Control Register */
-#define AT91C_PIOC_PDR		((AT91_REG *)	0xFFFFF804) /* (PIOC) PIO Disable Register */
-#define AT91C_PIOC_PER		((AT91_REG *)	0xFFFFF800) /* (PIOC) PIO Enable Register */
-#define AT91C_PIOC_ODR		((AT91_REG *)	0xFFFFF814) /* (PIOC) Output Disable Registerr */
-#define AT91C_PIOB_PER		((AT91_REG *)	0xFFFFF600) /* (PIOB) PIO Enable Register */
-#define AT91C_PIOB_ODR		((AT91_REG *)	0xFFFFF614) /* (PIOB) Output Disable Registerr */
-#define AT91C_PIOB_PDSR		((AT91_REG *)	0xFFFFF63C) /* (PIOB) Pin Data Status Register */
-
-#else
-/* flash */
-#define AT91C_MC_PUIA		0xFFFFFF10
-#define AT91C_MC_PUP		0xFFFFFF50
-#define AT91C_MC_PUER		0xFFFFFF54
-#define AT91C_MC_ASR		0xFFFFFF04
-#define AT91C_MC_AASR		0xFFFFFF08
-#define AT91C_EBI_CFGR		0xFFFFFF64
-#define AT91C_SMC_CSR0		0xFFFFFF70
-
-/* clocks */
-#define AT91C_PLLAR		0xFFFFFC28
-#define AT91C_PLLBR		0xFFFFFC2C
-#define AT91C_MCKR		0xFFFFFC30
-
-#define AT91C_BASE_CKGR		0xFFFFFC20
-#define AT91C_CKGR_MOR		0
-
-/* sdram */
-#define AT91C_PIOC_ASR		0xFFFFF870
-#define AT91C_PIOC_BSR		0xFFFFF874
-#define AT91C_PIOC_PDR		0xFFFFF804
-#define AT91C_EBI_CSA		0xFFFFFF60
-#define AT91C_SDRC_CR		0xFFFFFF98
-#define AT91C_SDRC_MR		0xFFFFFF90
-#define AT91C_SDRC_TR		0xFFFFFF94
-
-#endif /* __ASSEMBLY__ */
-#endif /* AT91RM9200_H */
diff --git a/arch/arm/include/asm/arch-at91rm9200/hardware.h b/arch/arm/include/asm/arch-at91rm9200/hardware.h
deleted file mode 100644
index b868e38..0000000
--- a/arch/arm/include/asm/arch-at91rm9200/hardware.h
+++ /dev/null
@@ -1,75 +0,0 @@
-/*
- * linux/include/asm-arm/arch-at91/hardware.h
- *
- *  Copyright (C) 2003 SAN People
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#ifndef __ASM_ARCH_HARDWARE_H
-#define __ASM_ARCH_HARDWARE_H
-
-#include <asm/sizes.h>
-
-#ifndef __ASSEMBLY__
-#include "AT91RM9200.h"
-#endif
-
-/* Virtual and Physical base address for system peripherals */
-#define AT91_SYS_BASE		0xFFFFF000 /*4K */
-
-/* Virtual and Physical base addresses of user peripherals */
-#define AT91_SPI_BASE		0xFFFE0000 /*16K */
-#define AT91_SSC2_BASE		0xFFFD8000 /*16K */
-#define AT91_SSC1_BASE		0xFFFD4000 /*16K */
-#define AT91_SSC0_BASE		0xFFFD0000 /*16K */
-#define AT91_USART3_BASE	0xFFFCC000 /*16K */
-#define AT91_USART2_BASE	0xFFFC8000 /*16K */
-#define AT91_USART1_BASE	0xFFFC4000 /*16K */
-#define AT91_USART0_BASE	0xFFFC0000 /*16K */
-#define AT91_EMAC_BASE		0xFFFBC000 /*16K */
-#define AT91_TWI_BASE		0xFFFB8000 /*16K */
-#define AT91_MCI_BASE		0xFFFB4000 /*16K */
-#define AT91_UDP_BASE		0xFFFB0000 /*16K */
-#define AT91_TCB1_BASE		0xFFFA4000 /*16K */
-#define AT91_TCB0_BASE		0xFFFA0000 /*16K */
-
-#define AT91_USB_HOST_BASE	0x00300000
-
-/*
- * Where in virtual memory the IO devices (timers, system controllers
- * and so on)
- */
-#define AT91_IO_BASE		0xF0000000	/* Virt/Phys Address of IO */
-
-/* FLASH */
-#define AT91_FLASH_BASE		0x10000000	/* NCS0 */
-
-/* SDRAM */
-#define AT91_SDRAM_BASE		0x20000000	/* NCS1 */
-
-/* SmartMedia */
-#define AT91_SMARTMEDIA_BASE	0x40000000	/* NCS3 */
-
-/* Definition of interrupt priority levels */
-#define AT91C_AIC_PRIOR_0 AT91C_AIC_PRIOR_LOWEST
-#define AT91C_AIC_PRIOR_1 ((unsigned int) 0x1)
-#define AT91C_AIC_PRIOR_2 ((unsigned int) 0x2)
-#define AT91C_AIC_PRIOR_3 ((unsigned int) 0x3)
-#define AT91C_AIC_PRIOR_4 ((unsigned int) 0x4)
-#define AT91C_AIC_PRIOR_5 ((unsigned int) 0x5)
-#define AT91C_AIC_PRIOR_6 ((unsigned int) 0x6)
-#define AT91C_AIC_PRIOR_7 AT91C_AIC_PRIOR_HIGEST
-
-#endif
diff --git a/arch/arm/include/asm/arch-davinci/davinci_misc.h b/arch/arm/include/asm/arch-davinci/davinci_misc.h
deleted file mode 100644
index 347aa89..0000000
--- a/arch/arm/include/asm/arch-davinci/davinci_misc.h
+++ /dev/null
@@ -1,69 +0,0 @@
-/*
- * Copyright (C) 2008 Lyrtech <www.lyrtech.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#ifndef __MISC_H
-#define __MISC_H
-
-/* pin muxer definitions */
-#define PIN_MUX_NUM_FIELDS	8	/* Per register */
-#define PIN_MUX_FIELD_SIZE	4	/* n in bits */
-#define PIN_MUX_FIELD_MASK	((1 << PIN_MUX_FIELD_SIZE) - 1)
-
-/* pin definition */
-struct pinmux_config {
-	dv_reg		*mux;		/* Address of mux register */
-	unsigned char	value;		/* Value to set in field */
-	unsigned char	field;		/* field number */
-};
-
-/* pin table definition */
-struct pinmux_resource {
-	const struct pinmux_config	*pins;
-	const int 			n_pins;
-};
-
-#define PINMUX_ITEM(item) { \
-				.pins = item, \
-				.n_pins = ARRAY_SIZE(item) \
-			  }
-
-#define HAWKBOARD_KICK0_UNLOCK          0x83e70b13
-#define HAWKBOARD_KICK1_UNLOCK          0x95a4f1e0
-
-struct lpsc_resource {
-	const int	lpsc_no;
-};
-
-int dvevm_read_mac_address(uint8_t *buf);
-void davinci_sync_env_enetaddr(uint8_t *rom_enetaddr);
-int davinci_configure_pin_mux(const struct pinmux_config *pins, int n_pins);
-int davinci_configure_pin_mux_items(const struct pinmux_resource *item,
-				    int n_items);
-#if defined(CONFIG_DRIVER_TI_EMAC) && defined(CONFIG_MACH_DAVINCI_DA850_EVM)
-void davinci_emac_mii_mode_sel(int mode_sel);
-#endif
-#if defined(CONFIG_SOC_DA8XX)
-void irq_init(void);
-int da8xx_configure_lpsc_items(const struct lpsc_resource *item,
-				    const int n_items);
-#endif
-
-#endif /* __MISC_H */
diff --git a/arch/arm/include/asm/arch-davinci/emac_defs.h b/arch/arm/include/asm/arch-davinci/emac_defs.h
deleted file mode 100644
index 4a4ee04..0000000
--- a/arch/arm/include/asm/arch-davinci/emac_defs.h
+++ /dev/null
@@ -1,395 +0,0 @@
-/*
- * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
- *
- * Based on:
- *
- * ----------------------------------------------------------------------------
- *
- * dm644x_emac.h
- *
- * TI DaVinci (DM644X) EMAC peripheral driver header for DV-EVM
- *
- * Copyright (C) 2005 Texas Instruments.
- *
- * ----------------------------------------------------------------------------
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License
- *  along with this program; if not, write to the Free Software
- *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- * ----------------------------------------------------------------------------
-
- * Modifications:
- * ver. 1.0: Sep 2005, TI PSP Team - Created EMAC version for uBoot.
- *
- */
-
-#ifndef _DM644X_EMAC_H_
-#define _DM644X_EMAC_H_
-
-#include <asm/arch/hardware.h>
-
-#ifdef CONFIG_SOC_DM365
-#define EMAC_BASE_ADDR			(0x01d07000)
-#define EMAC_WRAPPER_BASE_ADDR		(0x01d0a000)
-#define EMAC_WRAPPER_RAM_ADDR		(0x01d08000)
-#define EMAC_MDIO_BASE_ADDR		(0x01d0b000)
-#define DAVINCI_EMAC_VERSION2
-#elif defined(CONFIG_SOC_DA8XX)
-#define EMAC_BASE_ADDR			DAVINCI_EMAC_CNTRL_REGS_BASE
-#define EMAC_WRAPPER_BASE_ADDR		DAVINCI_EMAC_WRAPPER_CNTRL_REGS_BASE
-#define EMAC_WRAPPER_RAM_ADDR		DAVINCI_EMAC_WRAPPER_RAM_BASE
-#define EMAC_MDIO_BASE_ADDR		DAVINCI_MDIO_CNTRL_REGS_BASE
-#define DAVINCI_EMAC_VERSION2
-#else
-#define EMAC_BASE_ADDR			(0x01c80000)
-#define EMAC_WRAPPER_BASE_ADDR		(0x01c81000)
-#define EMAC_WRAPPER_RAM_ADDR		(0x01c82000)
-#define EMAC_MDIO_BASE_ADDR		(0x01c84000)
-#endif
-
-#ifdef CONFIG_SOC_DM646X
-#define DAVINCI_EMAC_VERSION2
-#define DAVINCI_EMAC_GIG_ENABLE
-#endif
-
-#ifdef CONFIG_SOC_DM646X
-/* MDIO module input frequency */
-#define EMAC_MDIO_BUS_FREQ		76500000
-/* MDIO clock output frequency */
-#define EMAC_MDIO_CLOCK_FREQ		2500000		/* 2.5 MHz */
-#elif defined(CONFIG_SOC_DM365)
-/* MDIO module input frequency */
-#define EMAC_MDIO_BUS_FREQ		121500000
-/* MDIO clock output frequency */
-#define EMAC_MDIO_CLOCK_FREQ		2200000		/* 2.2 MHz */
-#elif defined(CONFIG_SOC_DA8XX)
-/* MDIO module input frequency */
-#define EMAC_MDIO_BUS_FREQ		clk_get(DAVINCI_MDIO_CLKID)
-/* MDIO clock output frequency */
-#define EMAC_MDIO_CLOCK_FREQ		2000000		/* 2.0 MHz */
-#else
-/* MDIO module input frequency */
-#define EMAC_MDIO_BUS_FREQ		99000000	/* PLL/6 - 99 MHz */
-/* MDIO clock output frequency */
-#define EMAC_MDIO_CLOCK_FREQ		2000000		/* 2.0 MHz */
-#endif
-
-/* PHY mask - set only those phy number bits where phy is/can be connected */
-#define EMAC_MDIO_PHY_NUM           CONFIG_EMAC_MDIO_PHY_NUM
-#define EMAC_MDIO_PHY_MASK          (1 << EMAC_MDIO_PHY_NUM)
-
-/* Ethernet Min/Max packet size */
-#define EMAC_MIN_ETHERNET_PKT_SIZE	60
-#define EMAC_MAX_ETHERNET_PKT_SIZE	1518
-#define EMAC_PKT_ALIGN			18	/* 1518 + 18 = 1536 (packet aligned on 32 byte boundry) */
-
-/* Number of RX packet buffers
- * NOTE: Only 1 buffer supported as of now
- */
-#define EMAC_MAX_RX_BUFFERS		10
-
-
-/***********************************************
- ******** Internally used macros ***************
- ***********************************************/
-
-#define EMAC_CH_TX			1
-#define EMAC_CH_RX			0
-
-/* Each descriptor occupies 4 words, lets start RX desc's at 0 and
- * reserve space for 64 descriptors max
- */
-#define EMAC_RX_DESC_BASE		0x0
-#define EMAC_TX_DESC_BASE		0x1000
-
-/* EMAC Teardown value */
-#define EMAC_TEARDOWN_VALUE		0xfffffffc
-
-/* MII Status Register */
-#define MII_STATUS_REG			1
-
-/* Number of statistics registers */
-#define EMAC_NUM_STATS			36
-
-
-/* EMAC Descriptor */
-typedef volatile struct _emac_desc
-{
-	u_int32_t	next;		/* Pointer to next descriptor in chain */
-	u_int8_t	*buffer;	/* Pointer to data buffer */
-	u_int32_t	buff_off_len;	/* Buffer Offset(MSW) and Length(LSW) */
-	u_int32_t	pkt_flag_len;	/* Packet Flags(MSW) and Length(LSW) */
-} emac_desc;
-
-/* CPPI bit positions */
-#define EMAC_CPPI_SOP_BIT		(0x80000000)
-#define EMAC_CPPI_EOP_BIT		(0x40000000)
-#define EMAC_CPPI_OWNERSHIP_BIT		(0x20000000)
-#define EMAC_CPPI_EOQ_BIT		(0x10000000)
-#define EMAC_CPPI_TEARDOWN_COMPLETE_BIT	(0x08000000)
-#define EMAC_CPPI_PASS_CRC_BIT		(0x04000000)
-
-#define EMAC_CPPI_RX_ERROR_FRAME	(0x03fc0000)
-
-#define EMAC_MACCONTROL_MIIEN_ENABLE		(0x20)
-#define EMAC_MACCONTROL_FULLDUPLEX_ENABLE	(0x1)
-#define EMAC_MACCONTROL_GIGABIT_ENABLE		(1 << 7)
-#define EMAC_MACCONTROL_GIGFORCE		(1 << 17)
-#define EMAC_MACCONTROL_RMIISPEED_100		(1 << 15)
-
-#define EMAC_MAC_ADDR_MATCH		(1 << 19)
-#define EMAC_MAC_ADDR_IS_VALID		(1 << 20)
-
-#define EMAC_RXMBPENABLE_RXCAFEN_ENABLE	(0x200000)
-#define EMAC_RXMBPENABLE_RXBROADEN	(0x2000)
-
-
-#define MDIO_CONTROL_IDLE		(0x80000000)
-#define MDIO_CONTROL_ENABLE		(0x40000000)
-#define MDIO_CONTROL_FAULT_ENABLE	(0x40000)
-#define MDIO_CONTROL_FAULT		(0x80000)
-#define MDIO_USERACCESS0_GO		(0x80000000)
-#define MDIO_USERACCESS0_WRITE_READ	(0x0)
-#define MDIO_USERACCESS0_WRITE_WRITE	(0x40000000)
-#define MDIO_USERACCESS0_ACK		(0x20000000)
-
-/* Ethernet MAC Registers Structure */
-typedef struct  {
-	dv_reg		TXIDVER;
-	dv_reg		TXCONTROL;
-	dv_reg		TXTEARDOWN;
-	u_int8_t	RSVD0[4];
-	dv_reg		RXIDVER;
-	dv_reg		RXCONTROL;
-	dv_reg		RXTEARDOWN;
-	u_int8_t	RSVD1[100];
-	dv_reg		TXINTSTATRAW;
-	dv_reg		TXINTSTATMASKED;
-	dv_reg		TXINTMASKSET;
-	dv_reg		TXINTMASKCLEAR;
-	dv_reg		MACINVECTOR;
-	u_int8_t	RSVD2[12];
-	dv_reg		RXINTSTATRAW;
-	dv_reg		RXINTSTATMASKED;
-	dv_reg		RXINTMASKSET;
-	dv_reg		RXINTMASKCLEAR;
-	dv_reg		MACINTSTATRAW;
-	dv_reg		MACINTSTATMASKED;
-	dv_reg		MACINTMASKSET;
-	dv_reg		MACINTMASKCLEAR;
-	u_int8_t	RSVD3[64];
-	dv_reg		RXMBPENABLE;
-	dv_reg		RXUNICASTSET;
-	dv_reg		RXUNICASTCLEAR;
-	dv_reg		RXMAXLEN;
-	dv_reg		RXBUFFEROFFSET;
-	dv_reg		RXFILTERLOWTHRESH;
-	u_int8_t	RSVD4[8];
-	dv_reg		RX0FLOWTHRESH;
-	dv_reg		RX1FLOWTHRESH;
-	dv_reg		RX2FLOWTHRESH;
-	dv_reg		RX3FLOWTHRESH;
-	dv_reg		RX4FLOWTHRESH;
-	dv_reg		RX5FLOWTHRESH;
-	dv_reg		RX6FLOWTHRESH;
-	dv_reg		RX7FLOWTHRESH;
-	dv_reg		RX0FREEBUFFER;
-	dv_reg		RX1FREEBUFFER;
-	dv_reg		RX2FREEBUFFER;
-	dv_reg		RX3FREEBUFFER;
-	dv_reg		RX4FREEBUFFER;
-	dv_reg		RX5FREEBUFFER;
-	dv_reg		RX6FREEBUFFER;
-	dv_reg		RX7FREEBUFFER;
-	dv_reg		MACCONTROL;
-	dv_reg		MACSTATUS;
-	dv_reg		EMCONTROL;
-	dv_reg		FIFOCONTROL;
-	dv_reg		MACCONFIG;
-	dv_reg		SOFTRESET;
-	u_int8_t	RSVD5[88];
-	dv_reg		MACSRCADDRLO;
-	dv_reg		MACSRCADDRHI;
-	dv_reg		MACHASH1;
-	dv_reg		MACHASH2;
-	dv_reg		BOFFTEST;
-	dv_reg		TPACETEST;
-	dv_reg		RXPAUSE;
-	dv_reg		TXPAUSE;
-	u_int8_t	RSVD6[16];
-	dv_reg		RXGOODFRAMES;
-	dv_reg		RXBCASTFRAMES;
-	dv_reg		RXMCASTFRAMES;
-	dv_reg		RXPAUSEFRAMES;
-	dv_reg		RXCRCERRORS;
-	dv_reg		RXALIGNCODEERRORS;
-	dv_reg		RXOVERSIZED;
-	dv_reg		RXJABBER;
-	dv_reg		RXUNDERSIZED;
-	dv_reg		RXFRAGMENTS;
-	dv_reg		RXFILTERED;
-	dv_reg		RXQOSFILTERED;
-	dv_reg		RXOCTETS;
-	dv_reg		TXGOODFRAMES;
-	dv_reg		TXBCASTFRAMES;
-	dv_reg		TXMCASTFRAMES;
-	dv_reg		TXPAUSEFRAMES;
-	dv_reg		TXDEFERRED;
-	dv_reg		TXCOLLISION;
-	dv_reg		TXSINGLECOLL;
-	dv_reg		TXMULTICOLL;
-	dv_reg		TXEXCESSIVECOLL;
-	dv_reg		TXLATECOLL;
-	dv_reg		TXUNDERRUN;
-	dv_reg		TXCARRIERSENSE;
-	dv_reg		TXOCTETS;
-	dv_reg		FRAME64;
-	dv_reg		FRAME65T127;
-	dv_reg		FRAME128T255;
-	dv_reg		FRAME256T511;
-	dv_reg		FRAME512T1023;
-	dv_reg		FRAME1024TUP;
-	dv_reg		NETOCTETS;
-	dv_reg		RXSOFOVERRUNS;
-	dv_reg		RXMOFOVERRUNS;
-	dv_reg		RXDMAOVERRUNS;
-	u_int8_t	RSVD7[624];
-	dv_reg		MACADDRLO;
-	dv_reg		MACADDRHI;
-	dv_reg		MACINDEX;
-	u_int8_t	RSVD8[244];
-	dv_reg		TX0HDP;
-	dv_reg		TX1HDP;
-	dv_reg		TX2HDP;
-	dv_reg		TX3HDP;
-	dv_reg		TX4HDP;
-	dv_reg		TX5HDP;
-	dv_reg		TX6HDP;
-	dv_reg		TX7HDP;
-	dv_reg		RX0HDP;
-	dv_reg		RX1HDP;
-	dv_reg		RX2HDP;
-	dv_reg		RX3HDP;
-	dv_reg		RX4HDP;
-	dv_reg		RX5HDP;
-	dv_reg		RX6HDP;
-	dv_reg		RX7HDP;
-	dv_reg		TX0CP;
-	dv_reg		TX1CP;
-	dv_reg		TX2CP;
-	dv_reg		TX3CP;
-	dv_reg		TX4CP;
-	dv_reg		TX5CP;
-	dv_reg		TX6CP;
-	dv_reg		TX7CP;
-	dv_reg		RX0CP;
-	dv_reg		RX1CP;
-	dv_reg		RX2CP;
-	dv_reg		RX3CP;
-	dv_reg		RX4CP;
-	dv_reg		RX5CP;
-	dv_reg		RX6CP;
-	dv_reg		RX7CP;
-} emac_regs;
-
-/* EMAC Wrapper Registers Structure */
-typedef struct  {
-#ifdef DAVINCI_EMAC_VERSION2
-	dv_reg		idver;
-	dv_reg		softrst;
-	dv_reg		emctrl;
-	dv_reg		c0rxthreshen;
-	dv_reg		c0rxen;
-	dv_reg		c0txen;
-	dv_reg		c0miscen;
-	dv_reg		c1rxthreshen;
-	dv_reg		c1rxen;
-	dv_reg		c1txen;
-	dv_reg		c1miscen;
-	dv_reg		c2rxthreshen;
-	dv_reg		c2rxen;
-	dv_reg		c2txen;
-	dv_reg		c2miscen;
-	dv_reg		c0rxthreshstat;
-	dv_reg		c0rxstat;
-	dv_reg		c0txstat;
-	dv_reg		c0miscstat;
-	dv_reg		c1rxthreshstat;
-	dv_reg		c1rxstat;
-	dv_reg		c1txstat;
-	dv_reg		c1miscstat;
-	dv_reg		c2rxthreshstat;
-	dv_reg		c2rxstat;
-	dv_reg		c2txstat;
-	dv_reg		c2miscstat;
-	dv_reg		c0rximax;
-	dv_reg		c0tximax;
-	dv_reg		c1rximax;
-	dv_reg		c1tximax;
-	dv_reg		c2rximax;
-	dv_reg		c2tximax;
-#else
-	u_int8_t	RSVD0[4100];
-	dv_reg		EWCTL;
-	dv_reg		EWINTTCNT;
-#endif
-} ewrap_regs;
-
-/* EMAC MDIO Registers Structure */
-typedef struct  {
-	dv_reg		VERSION;
-	dv_reg		CONTROL;
-	dv_reg		ALIVE;
-	dv_reg		LINK;
-	dv_reg		LINKINTRAW;
-	dv_reg		LINKINTMASKED;
-	u_int8_t	RSVD0[8];
-	dv_reg		USERINTRAW;
-	dv_reg		USERINTMASKED;
-	dv_reg		USERINTMASKSET;
-	dv_reg		USERINTMASKCLEAR;
-	u_int8_t	RSVD1[80];
-	dv_reg		USERACCESS0;
-	dv_reg		USERPHYSEL0;
-	dv_reg		USERACCESS1;
-	dv_reg		USERPHYSEL1;
-} mdio_regs;
-
-int davinci_eth_phy_read(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t *data);
-int davinci_eth_phy_write(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t data);
-
-typedef struct
-{
-	char	name[64];
-	int	(*init)(int phy_addr);
-	int	(*is_phy_connected)(int phy_addr);
-	int	(*get_link_speed)(int phy_addr);
-	int	(*auto_negotiate)(int phy_addr);
-} phy_t;
-
-#define PHY_LXT972	(0x001378e2)
-int lxt972_is_phy_connected(int phy_addr);
-int lxt972_get_link_speed(int phy_addr);
-int lxt972_init_phy(int phy_addr);
-int lxt972_auto_negotiate(int phy_addr);
-
-#define PHY_DP83848	(0x20005c90)
-int dp83848_is_phy_connected(int phy_addr);
-int dp83848_get_link_speed(int phy_addr);
-int dp83848_init_phy(int phy_addr);
-int dp83848_auto_negotiate(int phy_addr);
-
-#define PHY_ET1011C	(0x282f013)
-int et1011c_get_link_speed(int phy_addr);
-
-#endif  /* _DM644X_EMAC_H_ */
diff --git a/arch/arm/include/asm/arch-davinci/emif_defs.h b/arch/arm/include/asm/arch-davinci/emif_defs.h
deleted file mode 100644
index b48ec17..0000000
--- a/arch/arm/include/asm/arch-davinci/emif_defs.h
+++ /dev/null
@@ -1,87 +0,0 @@
-/*
- * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-#ifndef _EMIF_DEFS_H_
-#define _EMIF_DEFS_H_
-
-#include <asm/arch/hardware.h>
-
-struct davinci_emif_regs {
-	u_int32_t	ercsr;
-	u_int32_t	awccr;
-	u_int32_t	sdbcr;
-	u_int32_t	sdrcr;
-	u_int32_t	ab1cr;
-	u_int32_t	ab2cr;
-	u_int32_t	ab3cr;
-	u_int32_t	ab4cr;
-	u_int32_t	sdtimr;
-	u_int32_t	ddrsr;
-	u_int32_t	ddrphycr;
-	u_int32_t	ddrphysr;
-	u_int32_t	totar;
-	u_int32_t	totactr;
-	u_int32_t	ddrphyid_rev;
-	u_int32_t	sdsretr;
-	u_int32_t	eirr;
-	u_int32_t	eimr;
-	u_int32_t	eimsr;
-	u_int32_t	eimcr;
-	u_int32_t	ioctrlr;
-	u_int32_t	iostatr;
-	u_int8_t	rsvd0[8];
-	u_int32_t	nandfcr;
-	u_int32_t	nandfsr;
-	u_int8_t	rsvd1[8];
-	u_int32_t	nandfecc[4];
-	u_int8_t	rsvd2[60];
-	u_int32_t	nand4biteccload;
-	u_int32_t	nand4bitecc[4];
-	u_int32_t	nanderradd1;
-	u_int32_t	nanderradd2;
-	u_int32_t	nanderrval1;
-	u_int32_t	nanderrval2;
-};
-
-#define davinci_emif_regs \
-	((struct davinci_emif_regs *)DAVINCI_ASYNC_EMIF_CNTRL_BASE)
-
-#define DAVINCI_NANDFCR_NAND_ENABLE(n)			(1 << (n-2))
-#define DAVINCI_NANDFCR_4BIT_ECC_SEL_MASK		(3 << 4)
-#define DAVINCI_NANDFCR_4BIT_ECC_SEL(n)			((n-2) << 4)
-#define DAVINCI_NANDFCR_1BIT_ECC_START(n)		(1 << (8 + (n-2)))
-#define DAVINCI_NANDFCR_4BIT_ECC_START			(1 << 12)
-#define DAVINCI_NANDFCR_4BIT_CALC_START			(1 << 13)
-
-/* Chip Select setup */
-#define DAVINCI_ABCR_STROBE_SELECT			(1 << 31)
-#define DAVINCI_ABCR_EXT_WAIT				(1 << 30)
-#define DAVINCI_ABCR_WSETUP(n)				(n << 26)
-#define DAVINCI_ABCR_WSTROBE(n)				(n << 20)
-#define DAVINCI_ABCR_WHOLD(n)				(n << 17)
-#define DAVINCI_ABCR_RSETUP(n)				(n << 13)
-#define DAVINCI_ABCR_RSTROBE(n)				(n << 7)
-#define DAVINCI_ABCR_RHOLD(n)				(n << 4)
-#define DAVINCI_ABCR_TA(n)				(n << 2)
-#define DAVINCI_ABCR_ASIZE_16BIT			1
-#define DAVINCI_ABCR_ASIZE_8BIT				0
-
-#endif
diff --git a/arch/arm/include/asm/arch-davinci/gpio_defs.h b/arch/arm/include/asm/arch-davinci/gpio_defs.h
deleted file mode 100644
index 1be2ac2..0000000
--- a/arch/arm/include/asm/arch-davinci/gpio_defs.h
+++ /dev/null
@@ -1,66 +0,0 @@
-/*
- * Copyright (C) 2009 Texas Instruments Incorporated
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-#ifndef _GPIO_DEFS_H_
-#define _GPIO_DEFS_H_
-
-#ifndef CONFIG_SOC_DA8XX
-#define DAVINCI_GPIO_BINTEN	0x01C67008
-#define DAVINCI_GPIO_BANK01	0x01C67010
-#define DAVINCI_GPIO_BANK23	0x01C67038
-#define DAVINCI_GPIO_BANK45	0x01C67060
-#define DAVINCI_GPIO_BANK67	0x01C67088
-
-#else /* CONFIG_SOC_DA8XX */
-#define DAVINCI_GPIO_BINTEN	0x01E26008
-#define DAVINCI_GPIO_BANK01	0x01E26010
-#define DAVINCI_GPIO_BANK23	0x01E26038
-#define DAVINCI_GPIO_BANK45	0x01E26060
-#define DAVINCI_GPIO_BANK67	0x01E26088
-#endif /* CONFIG_SOC_DA8XX */
-
-struct davinci_gpio {
-	unsigned int dir;
-	unsigned int out_data;
-	unsigned int set_data;
-	unsigned int clr_data;
-	unsigned int in_data;
-	unsigned int set_rising;
-	unsigned int clr_rising;
-	unsigned int set_falling;
-	unsigned int clr_falling;
-	unsigned int intstat;
-};
-
-struct davinci_gpio_bank {
-	int num_gpio;
-	unsigned int irq_num;
-	unsigned int irq_mask;
-	unsigned long *in_use;
-	unsigned long base;
-};
-
-#define davinci_gpio_bank01 ((struct davinci_gpio *)DAVINCI_GPIO_BANK01)
-#define davinci_gpio_bank23 ((struct davinci_gpio *)DAVINCI_GPIO_BANK23)
-#define davinci_gpio_bank45 ((struct davinci_gpio *)DAVINCI_GPIO_BANK45)
-#define davinci_gpio_bank67 ((struct davinci_gpio *)DAVINCI_GPIO_BANK67)
-
-#endif
diff --git a/arch/arm/include/asm/arch-davinci/hardware.h b/arch/arm/include/asm/arch-davinci/hardware.h
deleted file mode 100644
index df3f549..0000000
--- a/arch/arm/include/asm/arch-davinci/hardware.h
+++ /dev/null
@@ -1,481 +0,0 @@
-/*
- * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
- *
- * Based on:
- *
- * -------------------------------------------------------------------------
- *
- *  linux/include/asm-arm/arch-davinci/hardware.h
- *
- *  Copyright (C) 2006 Texas Instruments.
- *
- *  This program is free software; you can redistribute  it and/or modify it
- *  under  the terms of  the GNU General  Public License as published by the
- *  Free Software Foundation;  either version 2 of the  License, or (at your
- *  option) any later version.
- *
- *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
- *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
- *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
- *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
- *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
- *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- *  You should have received a copy of the  GNU General Public License along
- *  with this program; if not, write  to the Free Software Foundation, Inc.,
- *  675 Mass Ave, Cambridge, MA 02139, USA.
- *
- */
-#ifndef __ASM_ARCH_HARDWARE_H
-#define __ASM_ARCH_HARDWARE_H
-
-#include <config.h>
-#include <asm/sizes.h>
-
-#define	REG(addr)	(*(volatile unsigned int *)(addr))
-#define REG_P(addr)	((volatile unsigned int *)(addr))
-
-typedef volatile unsigned int	dv_reg;
-typedef volatile unsigned int *	dv_reg_p;
-
-/*
- * Base register addresses
- *
- * NOTE:  some of these DM6446-specific addresses DO NOT WORK
- * on other DaVinci chips.  Double check them before you try
- * using the addresses ... or PSC module identifiers, etc.
- */
-#ifndef CONFIG_SOC_DA8XX
-
-#define DAVINCI_DMA_3PCC_BASE			(0x01c00000)
-#define DAVINCI_DMA_3PTC0_BASE			(0x01c10000)
-#define DAVINCI_DMA_3PTC1_BASE			(0x01c10400)
-#define DAVINCI_UART0_BASE			(0x01c20000)
-#define DAVINCI_UART1_BASE			(0x01c20400)
-#define DAVINCI_I2C_BASE			(0x01c21000)
-#define DAVINCI_TIMER0_BASE			(0x01c21400)
-#define DAVINCI_TIMER1_BASE			(0x01c21800)
-#define DAVINCI_WDOG_BASE			(0x01c21c00)
-#define DAVINCI_PWM0_BASE			(0x01c22000)
-#define DAVINCI_PWM1_BASE			(0x01c22400)
-#define DAVINCI_PWM2_BASE			(0x01c22800)
-#define DAVINCI_SYSTEM_MODULE_BASE		(0x01c40000)
-#define DAVINCI_PLL_CNTRL0_BASE			(0x01c40800)
-#define DAVINCI_PLL_CNTRL1_BASE			(0x01c40c00)
-#define DAVINCI_PWR_SLEEP_CNTRL_BASE		(0x01c41000)
-#define DAVINCI_ARM_INTC_BASE			(0x01c48000)
-#define DAVINCI_USB_OTG_BASE			(0x01c64000)
-#define DAVINCI_CFC_ATA_BASE			(0x01c66000)
-#define DAVINCI_SPI_BASE			(0x01c66800)
-#define DAVINCI_GPIO_BASE			(0x01c67000)
-#define DAVINCI_VPSS_REGS_BASE			(0x01c70000)
-#if !defined(CONFIG_SOC_DM646X)
-#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE	(0x02000000)
-#define DAVINCI_ASYNC_EMIF_DATA_CE1_BASE	(0x04000000)
-#define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE	(0x06000000)
-#define DAVINCI_ASYNC_EMIF_DATA_CE3_BASE	(0x08000000)
-#endif
-#define DAVINCI_DDR_BASE			(0x80000000)
-
-#ifdef CONFIG_SOC_DM644X
-#define DAVINCI_UART2_BASE			0x01c20800
-#define DAVINCI_UHPI_BASE			0x01c67800
-#define DAVINCI_EMAC_CNTRL_REGS_BASE		0x01c80000
-#define DAVINCI_EMAC_WRAPPER_CNTRL_REGS_BASE	0x01c81000
-#define DAVINCI_EMAC_WRAPPER_RAM_BASE		0x01c82000
-#define DAVINCI_MDIO_CNTRL_REGS_BASE		0x01c84000
-#define DAVINCI_IMCOP_BASE			0x01cc0000
-#define DAVINCI_ASYNC_EMIF_CNTRL_BASE		0x01e00000
-#define DAVINCI_VLYNQ_BASE			0x01e01000
-#define DAVINCI_ASP_BASE			0x01e02000
-#define DAVINCI_MMC_SD_BASE			0x01e10000
-#define DAVINCI_MS_BASE				0x01e20000
-#define DAVINCI_VLYNQ_REMOTE_BASE		0x0c000000
-
-#elif defined(CONFIG_SOC_DM355)
-#define DAVINCI_MMC_SD1_BASE			0x01e00000
-#define DAVINCI_ASP0_BASE			0x01e02000
-#define DAVINCI_ASP1_BASE			0x01e04000
-#define DAVINCI_UART2_BASE			0x01e06000
-#define DAVINCI_ASYNC_EMIF_CNTRL_BASE		0x01e10000
-#define DAVINCI_MMC_SD0_BASE			0x01e11000
-
-#elif defined(CONFIG_SOC_DM365)
-#define DAVINCI_MMC_SD1_BASE			0x01d00000
-#define DAVINCI_ASYNC_EMIF_CNTRL_BASE		0x01d10000
-#define DAVINCI_MMC_SD0_BASE			0x01d11000
-
-#elif defined(CONFIG_SOC_DM646X)
-#define DAVINCI_ASYNC_EMIF_CNTRL_BASE		0x20008000
-#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE	0x42000000
-#define DAVINCI_ASYNC_EMIF_DATA_CE1_BASE	0x44000000
-#define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE	0x46000000
-#define DAVINCI_ASYNC_EMIF_DATA_CE3_BASE	0x48000000
-
-#endif
-
-#else /* CONFIG_SOC_DA8XX */
-
-#define DAVINCI_UART0_BASE			0x01c42000
-#define DAVINCI_UART1_BASE			0x01d0c000
-#define DAVINCI_UART2_BASE			0x01d0d000
-#define DAVINCI_I2C0_BASE			0x01c22000
-#define DAVINCI_I2C1_BASE			0x01e28000
-#define DAVINCI_TIMER0_BASE			0x01c20000
-#define DAVINCI_TIMER1_BASE			0x01c21000
-#define DAVINCI_WDOG_BASE			0x01c21000
-#define DAVINCI_PLL_CNTRL0_BASE			0x01c11000
-#define DAVINCI_PSC0_BASE			0x01c10000
-#define DAVINCI_PSC1_BASE			0x01e27000
-#define DAVINCI_SPI0_BASE			0x01c41000
-#define DAVINCI_USB_OTG_BASE			0x01e00000
-#define DAVINCI_SPI1_BASE			(cpu_is_da830() ? \
-						0x01e12000 : 0x01f0e000)
-#define DAVINCI_GPIO_BASE			0x01e26000
-#define DAVINCI_EMAC_CNTRL_REGS_BASE		0x01e23000
-#define DAVINCI_EMAC_WRAPPER_CNTRL_REGS_BASE	0x01e22000
-#define DAVINCI_EMAC_WRAPPER_RAM_BASE		0x01e20000
-#define DAVINCI_MDIO_CNTRL_REGS_BASE		0x01e24000
-#define DAVINCI_ASYNC_EMIF_CNTRL_BASE		0x68000000
-#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE	0x40000000
-#define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE	0x60000000
-#define DAVINCI_ASYNC_EMIF_DATA_CE3_BASE	0x62000000
-#define DAVINCI_ASYNC_EMIF_DATA_CE4_BASE	0x64000000
-#define DAVINCI_ASYNC_EMIF_DATA_CE5_BASE	0x66000000
-#define DAVINCI_DDR_EMIF_CTRL_BASE		0xb0000000
-#define DAVINCI_DDR_EMIF_DATA_BASE		0xc0000000
-#define DAVINCI_INTC_BASE			0xfffee000
-#define DAVINCI_BOOTCFG_BASE			0x01c14000
-#define JTAG_ID_REG                            (DAVINCI_BOOTCFG_BASE + 0x18)
-
-#define GPIO_BANK2_REG_DIR_ADDR			(DAVINCI_GPIO_BASE + 0x38)
-#define GPIO_BANK2_REG_OPDATA_ADDR		(DAVINCI_GPIO_BASE + 0x3c)
-#define GPIO_BANK2_REG_SET_ADDR			(DAVINCI_GPIO_BASE + 0x40)
-#define GPIO_BANK2_REG_CLR_ADDR			(DAVINCI_GPIO_BASE + 0x44)
-#endif /* CONFIG_SOC_DA8XX */
-
-/* Power and Sleep Controller (PSC) Domains */
-#define DAVINCI_GPSC_ARMDOMAIN		0
-#define DAVINCI_GPSC_DSPDOMAIN		1
-
-#ifndef CONFIG_SOC_DA8XX
-
-#define DAVINCI_LPSC_VPSSMSTR		0
-#define DAVINCI_LPSC_VPSSSLV		1
-#define DAVINCI_LPSC_TPCC		2
-#define DAVINCI_LPSC_TPTC0		3
-#define DAVINCI_LPSC_TPTC1		4
-#define DAVINCI_LPSC_EMAC		5
-#define DAVINCI_LPSC_EMAC_WRAPPER	6
-#define DAVINCI_LPSC_MDIO		7
-#define DAVINCI_LPSC_IEEE1394		8
-#define DAVINCI_LPSC_USB		9
-#define DAVINCI_LPSC_ATA		10
-#define DAVINCI_LPSC_VLYNQ		11
-#define DAVINCI_LPSC_UHPI		12
-#define DAVINCI_LPSC_DDR_EMIF		13
-#define DAVINCI_LPSC_AEMIF		14
-#define DAVINCI_LPSC_MMC_SD		15
-#define DAVINCI_LPSC_MEMSTICK		16
-#define DAVINCI_LPSC_McBSP		17
-#define DAVINCI_LPSC_I2C		18
-#define DAVINCI_LPSC_UART0		19
-#define DAVINCI_LPSC_UART1		20
-#define DAVINCI_LPSC_UART2		21
-#define DAVINCI_LPSC_SPI		22
-#define DAVINCI_LPSC_PWM0		23
-#define DAVINCI_LPSC_PWM1		24
-#define DAVINCI_LPSC_PWM2		25
-#define DAVINCI_LPSC_GPIO		26
-#define DAVINCI_LPSC_TIMER0		27
-#define DAVINCI_LPSC_TIMER1		28
-#define DAVINCI_LPSC_TIMER2		29
-#define DAVINCI_LPSC_SYSTEM_SUBSYS	30
-#define DAVINCI_LPSC_ARM		31
-#define DAVINCI_LPSC_SCR2		32
-#define DAVINCI_LPSC_SCR3		33
-#define DAVINCI_LPSC_SCR4		34
-#define DAVINCI_LPSC_CROSSBAR		35
-#define DAVINCI_LPSC_CFG27		36
-#define DAVINCI_LPSC_CFG3		37
-#define DAVINCI_LPSC_CFG5		38
-#define DAVINCI_LPSC_GEM		39
-#define DAVINCI_LPSC_IMCOP		40
-
-#define DAVINCI_DM646X_LPSC_EMAC	14
-#define DAVINCI_DM646X_LPSC_UART0	26
-#define DAVINCI_DM646X_LPSC_I2C		31
-#define DAVINCI_DM646X_LPSC_TIMER0	34
-
-#else /* CONFIG_SOC_DA8XX */
-
-enum davinci_lpsc_ids {
-	DAVINCI_LPSC_TPCC = 0,
-	DAVINCI_LPSC_TPTC0,
-	DAVINCI_LPSC_TPTC1,
-	DAVINCI_LPSC_AEMIF,
-	DAVINCI_LPSC_SPI0,
-	DAVINCI_LPSC_MMC_SD,
-	DAVINCI_LPSC_AINTC,
-	DAVINCI_LPSC_ARM_RAM_ROM,
-	DAVINCI_LPSC_SECCTL_KEYMGR,
-	DAVINCI_LPSC_UART0,
-	DAVINCI_LPSC_SCR0,
-	DAVINCI_LPSC_SCR1,
-	DAVINCI_LPSC_SCR2,
-	DAVINCI_LPSC_DMAX,
-	DAVINCI_LPSC_ARM,
-	DAVINCI_LPSC_GEM,
-	/* for LPSCs in PSC1, offset from 32 for differentiation */
-	DAVINCI_LPSC_PSC1_BASE = 32,
-	DAVINCI_LPSC_USB11,
-	DAVINCI_LPSC_USB20,
-	DAVINCI_LPSC_GPIO,
-	DAVINCI_LPSC_UHPI,
-	DAVINCI_LPSC_EMAC,
-	DAVINCI_LPSC_DDR_EMIF,
-	DAVINCI_LPSC_McASP0,
-	DAVINCI_LPSC_McASP1,
-	DAVINCI_LPSC_McASP2,
-	DAVINCI_LPSC_SPI1,
-	DAVINCI_LPSC_I2C1,
-	DAVINCI_LPSC_UART1,
-	DAVINCI_LPSC_UART2,
-	DAVINCI_LPSC_LCDC,
-	DAVINCI_LPSC_ePWM,
-	DAVINCI_LPSC_eCAP,
-	DAVINCI_LPSC_eQEP,
-	DAVINCI_LPSC_SCR_P0,
-	DAVINCI_LPSC_SCR_P1,
-	DAVINCI_LPSC_CR_P3,
-	DAVINCI_LPSC_L3_CBA_RAM
-};
-
-#endif /* CONFIG_SOC_DA8XX */
-
-void lpsc_on(unsigned int id);
-void dsp_on(void);
-
-void davinci_enable_uart0(void);
-void davinci_enable_emac(void);
-void davinci_enable_i2c(void);
-void davinci_errata_workarounds(void);
-
-#ifndef CONFIG_SOC_DA8XX
-
-/* Some PSC defines */
-#define PSC_CHP_SHRTSW			(0x01c40038)
-#define PSC_GBLCTL			(0x01c41010)
-#define PSC_EPCPR			(0x01c41070)
-#define PSC_EPCCR			(0x01c41078)
-#define PSC_PTCMD			(0x01c41120)
-#define PSC_PTSTAT			(0x01c41128)
-#define PSC_PDSTAT			(0x01c41200)
-#define PSC_PDSTAT1			(0x01c41204)
-#define PSC_PDCTL			(0x01c41300)
-#define PSC_PDCTL1			(0x01c41304)
-
-#define PSC_MDCTL_BASE			(0x01c41a00)
-#define PSC_MDSTAT_BASE			(0x01c41800)
-
-#define VDD3P3V_PWDN			(0x01c40048)
-#define UART0_PWREMU_MGMT		(0x01c20030)
-
-#define PSC_SILVER_BULLET		(0x01c41a20)
-
-#else /* CONFIG_SOC_DA8XX */
-
-#define PSC_PSC0_MODULE_ID_CNT		16
-#define PSC_PSC1_MODULE_ID_CNT		32
-
-struct davinci_psc_regs {
-	dv_reg	revid;
-	dv_reg	rsvd0[71];
-	dv_reg	ptcmd;
-	dv_reg	rsvd1;
-	dv_reg	ptstat;
-	dv_reg	rsvd2[437];
-	union {
-		struct {
-			dv_reg	mdstat[PSC_PSC0_MODULE_ID_CNT];
-			dv_reg	rsvd3[112];
-			dv_reg	mdctl[PSC_PSC0_MODULE_ID_CNT];
-		} psc0;
-		struct {
-			dv_reg	mdstat[PSC_PSC1_MODULE_ID_CNT];
-			dv_reg	rsvd3[96];
-			dv_reg	mdctl[PSC_PSC1_MODULE_ID_CNT];
-		} psc1;
-	};
-};
-
-#define davinci_psc0_regs ((struct davinci_psc_regs *)DAVINCI_PSC0_BASE)
-#define davinci_psc1_regs ((struct davinci_psc_regs *)DAVINCI_PSC1_BASE)
-
-#endif /* CONFIG_SOC_DA8XX */
-
-#ifndef CONFIG_SOC_DA8XX
-
-/* Miscellania... */
-#define VBPR				(0x20000020)
-
-/* NOTE:  system control modules are *highly* chip-specific, both
- * as to register content (e.g. for muxing) and which registers exist.
- */
-#define PINMUX0				0x01c40000
-#define PINMUX1				0x01c40004
-#define PINMUX2				0x01c40008
-#define PINMUX3				0x01c4000c
-#define PINMUX4				0x01c40010
-
-#else /* CONFIG_SOC_DA8XX */
-
-struct davinci_pllc_regs {
-	dv_reg	revid;
-	dv_reg	rsvd1[56];
-	dv_reg	rstype;
-	dv_reg	rsvd2[6];
-	dv_reg	pllctl;
-	dv_reg	ocsel;
-	dv_reg	rsvd3[2];
-	dv_reg	pllm;
-	dv_reg	prediv;
-	dv_reg	plldiv1;
-	dv_reg	plldiv2;
-	dv_reg	plldiv3;
-	dv_reg	oscdiv;
-	dv_reg	postdiv;
-	dv_reg	rsvd4[3];
-	dv_reg	pllcmd;
-	dv_reg	pllstat;
-	dv_reg	alnctl;
-	dv_reg	dchange;
-	dv_reg	cken;
-	dv_reg	ckstat;
-	dv_reg	systat;
-	dv_reg	rsvd5[3];
-	dv_reg	plldiv4;
-	dv_reg	plldiv5;
-	dv_reg	plldiv6;
-	dv_reg	plldiv7;
-	dv_reg	rsvd6[32];
-	dv_reg	emucnt0;
-	dv_reg	emucnt1;
-};
-
-#define davinci_pllc_regs ((struct davinci_pllc_regs *)DAVINCI_PLL_CNTRL0_BASE)
-#define DAVINCI_PLLC_DIV_MASK	0x1f
-
-#define ASYNC3          get_async3_src()
-#define PLL1_SYSCLK2		((1 << 16) | 0x2)
-#define DAVINCI_SPI1_CLKID  (cpu_is_da830() ? 2 : ASYNC3)
-/* Clock IDs */
-enum davinci_clk_ids {
-	DAVINCI_SPI0_CLKID = 2,
-	DAVINCI_UART2_CLKID = 2,
-	DAVINCI_MDIO_CLKID = 4,
-	DAVINCI_ARM_CLKID = 6,
-	DAVINCI_PLLM_CLKID = 0xff,
-	DAVINCI_PLLC_CLKID = 0x100,
-	DAVINCI_AUXCLK_CLKID = 0x101
-};
-
-int clk_get(enum davinci_clk_ids id);
-
-/* Boot config */
-struct davinci_syscfg_regs {
-	dv_reg	revid;
-	dv_reg	rsvd[13];
-	dv_reg	kick0;
-	dv_reg	kick1;
-	dv_reg	rsvd1[56];
-	dv_reg	pinmux[20];
-	dv_reg	suspsrc;
-	dv_reg	chipsig;
-	dv_reg	chipsig_clr;
-	dv_reg	cfgchip0;
-	dv_reg	cfgchip1;
-	dv_reg	cfgchip2;
-	dv_reg	cfgchip3;
-	dv_reg	cfgchip4;
-};
-
-#define davinci_syscfg_regs \
-	((struct davinci_syscfg_regs *)DAVINCI_BOOTCFG_BASE)
-
-/* Emulation suspend bits */
-#define DAVINCI_SYSCFG_SUSPSRC_EMAC		(1 << 5)
-#define DAVINCI_SYSCFG_SUSPSRC_I2C		(1 << 16)
-#define DAVINCI_SYSCFG_SUSPSRC_SPI0		(1 << 21)
-#define DAVINCI_SYSCFG_SUSPSRC_SPI1		(1 << 22)
-#define DAVINCI_SYSCFG_SUSPSRC_UART2		(1 << 20)
-#define DAVINCI_SYSCFG_SUSPSRC_TIMER0		(1 << 27)
-
-/* Interrupt controller */
-struct davinci_aintc_regs {
-	dv_reg	revid;
-	dv_reg	cr;
-	dv_reg	dummy0[2];
-	dv_reg	ger;
-	dv_reg	dummy1[219];
-	dv_reg	ecr1;
-	dv_reg	ecr2;
-	dv_reg	ecr3;
-	dv_reg	dummy2[1117];
-	dv_reg	hier;
-};
-
-#define davinci_aintc_regs ((struct davinci_aintc_regs *)DAVINCI_INTC_BASE)
-
-struct davinci_uart_ctrl_regs {
-	dv_reg	revid1;
-	dv_reg	revid2;
-	dv_reg	pwremu_mgmt;
-	dv_reg	mdr;
-};
-
-#define DAVINCI_UART_CTRL_BASE 0x28
-#define DAVINCI_UART0_CTRL_ADDR (DAVINCI_UART0_BASE + DAVINCI_UART_CTRL_BASE)
-#define DAVINCI_UART1_CTRL_ADDR (DAVINCI_UART1_BASE + DAVINCI_UART_CTRL_BASE)
-#define DAVINCI_UART2_CTRL_ADDR (DAVINCI_UART2_BASE + DAVINCI_UART_CTRL_BASE)
-
-#define davinci_uart0_ctrl_regs \
-	((struct davinci_uart_ctrl_regs *)DAVINCI_UART0_CTRL_ADDR)
-#define davinci_uart1_ctrl_regs \
-	((struct davinci_uart_ctrl_regs *)DAVINCI_UART1_CTRL_ADDR)
-#define davinci_uart2_ctrl_regs \
-	((struct davinci_uart_ctrl_regs *)DAVINCI_UART2_CTRL_ADDR)
-
-/* UART PWREMU_MGMT definitions */
-#define DAVINCI_UART_PWREMU_MGMT_FREE	(1 << 0)
-#define DAVINCI_UART_PWREMU_MGMT_URRST	(1 << 13)
-#define DAVINCI_UART_PWREMU_MGMT_UTRST	(1 << 14)
-
-static inline int cpu_is_da830(void)
-{
-	unsigned int jtag_id	= REG(JTAG_ID_REG);
-	unsigned short part_no	= (jtag_id >> 12) & 0xffff;
-
-	return ((part_no == 0xb7df) ? 1 : 0);
-}
-static inline int cpu_is_da850(void)
-{
-	unsigned int jtag_id    = REG(JTAG_ID_REG);
-	unsigned short part_no  = (jtag_id >> 12) & 0xffff;
-
-	return ((part_no == 0xb7d1) ? 1 : 0);
-}
-
-static inline int get_async3_src(void)
-{
-	return (REG(&davinci_syscfg_regs->cfgchip3) & 0x10) ?
-			PLL1_SYSCLK2 : 2;
-}
-
-#endif /* CONFIG_SOC_DA8XX */
-
-#endif /* __ASM_ARCH_HARDWARE_H */
diff --git a/arch/arm/include/asm/arch-davinci/i2c_defs.h b/arch/arm/include/asm/arch-davinci/i2c_defs.h
deleted file mode 100644
index 24cd268..0000000
--- a/arch/arm/include/asm/arch-davinci/i2c_defs.h
+++ /dev/null
@@ -1,99 +0,0 @@
-/*
- * (C) Copyright 2004
- * Texas Instruments, <www.ti.com>
- *
- * Some changes copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-#ifndef _DAVINCI_I2C_H_
-#define _DAVINCI_I2C_H_
-
-#define I2C_WRITE		0
-#define I2C_READ		1
-
-#ifndef CONFIG_SOC_DA8XX
-#define I2C_BASE		0x01c21000
-#else
-#define I2C_BASE		0x01c22000
-#endif
-
-#define	I2C_OA			(I2C_BASE + 0x00)
-#define I2C_IE			(I2C_BASE + 0x04)
-#define I2C_STAT		(I2C_BASE + 0x08)
-#define I2C_SCLL		(I2C_BASE + 0x0c)
-#define I2C_SCLH		(I2C_BASE + 0x10)
-#define I2C_CNT			(I2C_BASE + 0x14)
-#define I2C_DRR			(I2C_BASE + 0x18)
-#define I2C_SA			(I2C_BASE + 0x1c)
-#define I2C_DXR			(I2C_BASE + 0x20)
-#define I2C_CON			(I2C_BASE + 0x24)
-#define I2C_IV			(I2C_BASE + 0x28)
-#define I2C_PSC			(I2C_BASE + 0x30)
-
-/* I2C masks */
-
-/* I2C Interrupt Enable Register (I2C_IE): */
-#define I2C_IE_SCD_IE	(1 << 5)	/* Stop condition detect interrupt enable */
-#define I2C_IE_XRDY_IE	(1 << 4)	/* Transmit data ready interrupt enable */
-#define I2C_IE_RRDY_IE	(1 << 3)	/* Receive data ready interrupt enable */
-#define I2C_IE_ARDY_IE	(1 << 2)	/* Register access ready interrupt enable */
-#define I2C_IE_NACK_IE	(1 << 1)	/* No acknowledgment interrupt enable */
-#define I2C_IE_AL_IE	(1 << 0)	/* Arbitration lost interrupt enable */
-
-/* I2C Status Register (I2C_STAT): */
-
-#define I2C_STAT_BB	(1 << 12)	/* Bus busy */
-#define I2C_STAT_ROVR	(1 << 11)	/* Receive overrun */
-#define I2C_STAT_XUDF	(1 << 10)	/* Transmit underflow */
-#define I2C_STAT_AAS	(1 << 9)	/* Address as slave */
-#define I2C_STAT_SCD	(1 << 5)	/* Stop condition detect */
-#define I2C_STAT_XRDY	(1 << 4)	/* Transmit data ready */
-#define I2C_STAT_RRDY	(1 << 3)	/* Receive data ready */
-#define I2C_STAT_ARDY	(1 << 2)	/* Register access ready */
-#define I2C_STAT_NACK	(1 << 1)	/* No acknowledgment interrupt enable */
-#define I2C_STAT_AL	(1 << 0)	/* Arbitration lost interrupt enable */
-
-
-/* I2C Interrupt Code Register (I2C_INTCODE): */
-
-#define I2C_INTCODE_MASK	7
-#define I2C_INTCODE_NONE	0
-#define I2C_INTCODE_AL		1	/* Arbitration lost */
-#define I2C_INTCODE_NAK		2	/* No acknowledgement/general call */
-#define I2C_INTCODE_ARDY	3	/* Register access ready */
-#define I2C_INTCODE_RRDY	4	/* Rcv data ready */
-#define I2C_INTCODE_XRDY	5	/* Xmit data ready */
-#define I2C_INTCODE_SCD		6	/* Stop condition detect */
-
-
-/* I2C Configuration Register (I2C_CON): */
-
-#define I2C_CON_EN	(1 << 5)	/* I2C module enable */
-#define I2C_CON_STB	(1 << 4)	/* Start byte mode (master mode only) */
-#define I2C_CON_MST	(1 << 10)	/* Master/slave mode */
-#define I2C_CON_TRX	(1 << 9)	/* Transmitter/receiver mode (master mode only) */
-#define I2C_CON_XA	(1 << 8)	/* Expand address */
-#define I2C_CON_STP	(1 << 11)	/* Stop condition (master mode only) */
-#define I2C_CON_STT	(1 << 13)	/* Start condition (master mode only) */
-#define I2C_CON_FREE	(1 << 14)	/* Free run on emulation */
-
-#define I2C_TIMEOUT	0xffff0000	/* Timeout mask for poll_i2c_irq() */
-
-#endif
diff --git a/arch/arm/include/asm/arch-davinci/nand_defs.h b/arch/arm/include/asm/arch-davinci/nand_defs.h
deleted file mode 100644
index 10f3a39..0000000
--- a/arch/arm/include/asm/arch-davinci/nand_defs.h
+++ /dev/null
@@ -1,45 +0,0 @@
-/*
- * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
- *
- * Parts shamelesly stolen from Linux Kernel source tree.
- *
- * ------------------------------------------------------------
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-#ifndef _NAND_DEFS_H_
-#define _NAND_DEFS_H_
-
-#include <asm/arch/hardware.h>
-
-#ifdef CONFIG_SOC_DM646X
-#define	MASK_CLE	0x80000
-#define	MASK_ALE	0x40000
-#else
-#define	MASK_CLE	0x10
-#define	MASK_ALE	0x08
-#endif
-
-#define NAND_READ_START		0x00
-#define NAND_READ_END		0x30
-#define NAND_STATUS		0x70
-
-extern void davinci_nand_init(struct nand_chip *nand);
-
-#endif
diff --git a/arch/arm/include/asm/arch-davinci/sdmmc_defs.h b/arch/arm/include/asm/arch-davinci/sdmmc_defs.h
deleted file mode 100644
index 853fd40..0000000
--- a/arch/arm/include/asm/arch-davinci/sdmmc_defs.h
+++ /dev/null
@@ -1,175 +0,0 @@
-/*
- * Davinci MMC Controller Defines - Based on Linux davinci_mmc.c
- *
- * Copyright (C) 2010 Texas Instruments Incorporated
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#ifndef _SDMMC_DEFS_H_
-#define _SDMMC_DEFS_H_
-
-#include <asm/arch/hardware.h>
-
-/* MMC Control Reg fields */
-#define MMCCTL_DATRST		(1 << 0)
-#define MMCCTL_CMDRST		(1 << 1)
-#define MMCCTL_WIDTH_4_BIT	(1 << 2)
-#define MMCCTL_DATEG_DISABLED	(0 << 6)
-#define MMCCTL_DATEG_RISING	(1 << 6)
-#define MMCCTL_DATEG_FALLING	(2 << 6)
-#define MMCCTL_DATEG_BOTH	(3 << 6)
-#define MMCCTL_PERMDR_LE	(0 << 9)
-#define MMCCTL_PERMDR_BE	(1 << 9)
-#define MMCCTL_PERMDX_LE	(0 << 10)
-#define MMCCTL_PERMDX_BE	(1 << 10)
-
-/* MMC Clock Control Reg fields */
-#define MMCCLK_CLKEN		(1 << 8)
-#define MMCCLK_CLKRT_MASK	(0xFF << 0)
-
-/* MMC Status Reg0 fields */
-#define MMCST0_DATDNE		(1 << 0)
-#define MMCST0_BSYDNE		(1 << 1)
-#define MMCST0_RSPDNE		(1 << 2)
-#define MMCST0_TOUTRD		(1 << 3)
-#define MMCST0_TOUTRS		(1 << 4)
-#define MMCST0_CRCWR		(1 << 5)
-#define MMCST0_CRCRD		(1 << 6)
-#define MMCST0_CRCRS		(1 << 7)
-#define MMCST0_DXRDY		(1 << 9)
-#define MMCST0_DRRDY		(1 << 10)
-#define MMCST0_DATED		(1 << 11)
-#define MMCST0_TRNDNE		(1 << 12)
-
-#define MMCST0_ERR_MASK		(0x00F8)
-
-/* MMC Status Reg1 fields */
-#define MMCST1_BUSY		(1 << 0)
-#define MMCST1_CLKSTP		(1 << 1)
-#define MMCST1_DXEMP		(1 << 2)
-#define MMCST1_DRFUL		(1 << 3)
-#define MMCST1_DAT3ST		(1 << 4)
-#define MMCST1_FIFOEMP		(1 << 5)
-#define MMCST1_FIFOFUL		(1 << 6)
-
-/* MMC INT Mask Reg fields */
-#define MMCIM_EDATDNE		(1 << 0)
-#define MMCIM_EBSYDNE		(1 << 1)
-#define MMCIM_ERSPDNE		(1 << 2)
-#define MMCIM_ETOUTRD		(1 << 3)
-#define MMCIM_ETOUTRS		(1 << 4)
-#define MMCIM_ECRCWR		(1 << 5)
-#define MMCIM_ECRCRD		(1 << 6)
-#define MMCIM_ECRCRS		(1 << 7)
-#define MMCIM_EDXRDY		(1 << 9)
-#define MMCIM_EDRRDY		(1 << 10)
-#define MMCIM_EDATED		(1 << 11)
-#define MMCIM_ETRNDNE		(1 << 12)
-
-#define MMCIM_MASKALL		(0xFFFFFFFF)
-
-/* MMC Resp Tout Reg fields */
-#define MMCTOR_TOR_MASK		(0xFF)		/* dont write to reg, | it */
-#define MMCTOR_TOD_20_16_SHIFT  (8)
-
-/* MMC Data Read Tout Reg fields */
-#define MMCTOD_TOD_0_15_MASK	(0xFFFF)
-
-/* MMC Block len Reg fields */
-#define MMCBLEN_BLEN_MASK	(0xFFF)
-
-/* MMC Num Blocks Reg fields */
-#define MMCNBLK_NBLK_MASK	(0xFFFF)
-#define MMCNBLK_NBLK_MAX	(0xFFFF)
-
-/* MMC Num Blocks Counter Reg fields */
-#define MMCNBLC_NBLC_MASK	(0xFFFF)
-
-/* MMC Cmd Reg fields */
-#define MMCCMD_CMD_MASK		(0x3F)
-#define MMCCMD_PPLEN		(1 << 7)
-#define MMCCMD_BSYEXP		(1 << 8)
-#define MMCCMD_RSPFMT_NONE	(0 << 9)
-#define MMCCMD_RSPFMT_R1567	(1 << 9)
-#define MMCCMD_RSPFMT_R2	(2 << 9)
-#define MMCCMD_RSPFMT_R3	(3 << 9)
-#define MMCCMD_DTRW		(1 << 11)
-#define MMCCMD_STRMTP		(1 << 12)
-#define MMCCMD_WDATX		(1 << 13)
-#define MMCCMD_INITCK		(1 << 14)
-#define MMCCMD_DCLR		(1 << 15)
-#define MMCCMD_DMATRIG		(1 << 16)
-
-/* FIFO control Reg fields */
-#define MMCFIFOCTL_FIFORST	(1 << 0)
-#define MMCFIFOCTL_FIFODIR	(1 << 1)
-#define MMCFIFOCTL_FIFOLEV	(1 << 2)
-#define MMCFIFOCTL_ACCWD_4	(0 << 3)	/* access width of 4 bytes */
-#define MMCFIFOCTL_ACCWD_3	(1 << 3)	/* access width of 3 bytes */
-#define MMCFIFOCTL_ACCWD_2	(2 << 3)	/* access width of 2 bytes */
-#define MMCFIFOCTL_ACCWD_1	(3 << 3)	/* access width of 1 byte */
-
-/* Davinci MMC Register definitions */
-struct davinci_mmc_regs {
-	dv_reg mmcctl;
-	dv_reg mmcclk;
-	dv_reg mmcst0;
-	dv_reg mmcst1;
-	dv_reg mmcim;
-	dv_reg mmctor;
-	dv_reg mmctod;
-	dv_reg mmcblen;
-	dv_reg mmcnblk;
-	dv_reg mmcnblc;
-	dv_reg mmcdrr;
-	dv_reg mmcdxr;
-	dv_reg mmccmd;
-	dv_reg mmcarghl;
-	dv_reg mmcrsp01;
-	dv_reg mmcrsp23;
-	dv_reg mmcrsp45;
-	dv_reg mmcrsp67;
-	dv_reg mmcdrsp;
-	dv_reg mmcetok;
-	dv_reg mmccidx;
-	dv_reg mmcckc;
-	dv_reg mmctorc;
-	dv_reg mmctodc;
-	dv_reg mmcblnc;
-	dv_reg sdioctl;
-	dv_reg sdiost0;
-	dv_reg sdioien;
-	dv_reg sdioist;
-	dv_reg mmcfifoctl;
-};
-
-/* Davinci MMC board definitions */
-struct davinci_mmc {
-	struct davinci_mmc_regs *reg_base;	/* Register base address */
-	uint input_clk;		/* Input clock to MMC controller */
-	uint host_caps;		/* Host capabilities */
-	uint voltages;		/* Host supported voltages */
-	uint version;		/* MMC Controller version */
-};
-
-enum {
-	MMC_CTLR_VERSION_1 = 0,	/* DM644x and DM355 */
-	MMC_CTLR_VERSION_2,	/* DA830 */
-};
-
-int davinci_mmc_init(bd_t *bis, struct davinci_mmc *host);
-
-#endif /* _SDMMC_DEFS_H */
diff --git a/arch/arm/include/asm/arch-ep93xx/ep93xx.h b/arch/arm/include/asm/arch-ep93xx/ep93xx.h
deleted file mode 100644
index 806557a..0000000
--- a/arch/arm/include/asm/arch-ep93xx/ep93xx.h
+++ /dev/null
@@ -1,596 +0,0 @@
-/*
- * Cirrus Logic EP93xx register definitions.
- *
- * Copyright (C) 2009
- * Matthias Kaehlcke <matthias@kaehlcke.net>
- *
- * Copyright (C) 2006
- * Dominic Rath <Dominic.Rath@gmx.de>
- *
- * Copyright (C) 2004, 2005
- * Cory T. Tusar, Videon Central, Inc., <ctusar@videon-central.com>
- *
- * Based in large part on linux/include/asm-arm/arch-ep93xx/regmap.h, which is
- *
- * Copyright (C) 2004 Ray Lehtiniemi
- * Copyright (C) 2003 Cirrus Logic, Inc
- * Copyright (C) 1999 ARM Limited.
- *
- * See file CREDITS for list of people who contributed to this project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
- * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
- * for more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#define EP93XX_AHB_BASE			0x80000000
-#define EP93XX_APB_BASE			0x80800000
-
-/*
- * 0x80000000 - 0x8000FFFF: DMA
- */
-#define DMA_OFFSET			0x000000
-#define DMA_BASE			(EP93XX_AHB_BASE | DMA_OFFSET)
-
-#ifndef __ASSEMBLY__
-struct dma_channel {
-	uint32_t control;
-	uint32_t interrupt;
-	uint32_t ppalloc;
-	uint32_t status;
-	uint32_t reserved0;
-	uint32_t remain;
-	uint32_t reserved1[2];
-	uint32_t maxcnt0;
-	uint32_t base0;
-	uint32_t current0;
-	uint32_t reserved2;
-	uint32_t maxcnt1;
-	uint32_t base1;
-	uint32_t current1;
-	uint32_t reserved3;
-};
-
-struct dma_regs {
-	struct dma_channel m2p_channel_0;
-	struct dma_channel m2p_channel_1;
-	struct dma_channel m2p_channel_2;
-	struct dma_channel m2p_channel_3;
-	struct dma_channel m2m_channel_0;
-	struct dma_channel m2m_channel_1;
-	struct dma_channel reserved0[2];
-	struct dma_channel m2p_channel_5;
-	struct dma_channel m2p_channel_4;
-	struct dma_channel m2p_channel_7;
-	struct dma_channel m2p_channel_6;
-	struct dma_channel m2p_channel_9;
-	struct dma_channel m2p_channel_8;
-	uint32_t channel_arbitration;
-	uint32_t reserved[15];
-	uint32_t global_interrupt;
-};
-#endif
-
-/*
- * 0x80010000 - 0x8001FFFF: Ethernet MAC
- */
-#define MAC_OFFSET			0x010000
-#define MAC_BASE			(EP93XX_AHB_BASE | MAC_OFFSET)
-
-#ifndef __ASSEMBLY__
-struct mac_queue {
-	uint32_t badd;
-	union { /* deal with half-word aligned registers */
-		uint32_t blen;
-		union {
-			uint16_t filler;
-			uint16_t curlen;
-		};
-	};
-	uint32_t curadd;
-};
-
-struct mac_regs {
-	uint32_t rxctl;
-	uint32_t txctl;
-	uint32_t testctl;
-	uint32_t reserved0;
-	uint32_t miicmd;
-	uint32_t miidata;
-	uint32_t miists;
-	uint32_t reserved1;
-	uint32_t selfctl;
-	uint32_t inten;
-	uint32_t intstsp;
-	uint32_t intstsc;
-	uint32_t reserved2[2];
-	uint32_t diagad;
-	uint32_t diagdata;
-	uint32_t gt;
-	uint32_t fct;
-	uint32_t fcf;
-	uint32_t afp;
-	union {
-		struct {
-			uint32_t indad;
-			uint32_t indad_upper;
-		};
-		uint32_t hashtbl;
-	};
-	uint32_t reserved3[2];
-	uint32_t giintsts;
-	uint32_t giintmsk;
-	uint32_t giintrosts;
-	uint32_t giintfrc;
-	uint32_t txcollcnt;
-	uint32_t rxmissnct;
-	uint32_t rxruntcnt;
-	uint32_t reserved4;
-	uint32_t bmctl;
-	uint32_t bmsts;
-	uint32_t rxbca;
-	uint32_t reserved5;
-	struct mac_queue rxdq;
-	uint32_t rxdqenq;
-	struct mac_queue rxstsq;
-	uint32_t rxstsqenq;
-	struct mac_queue txdq;
-	uint32_t txdqenq;
-	struct mac_queue txstsq;
-	uint32_t reserved6;
-	uint32_t rxbufthrshld;
-	uint32_t txbufthrshld;
-	uint32_t rxststhrshld;
-	uint32_t txststhrshld;
-	uint32_t rxdthrshld;
-	uint32_t txdthrshld;
-	uint32_t maxfrmlen;
-	uint32_t maxhdrlen;
-};
-#endif
-
-#define SELFCTL_RWP		(1 << 7)
-#define SELFCTL_GPO0		(1 << 5)
-#define SELFCTL_PUWE		(1 << 4)
-#define SELFCTL_PDWE		(1 << 3)
-#define SELFCTL_MIIL		(1 << 2)
-#define SELFCTL_RESET		(1 << 0)
-
-#define INTSTS_RWI		(1 << 30)
-#define INTSTS_RXMI		(1 << 29)
-#define INTSTS_RXBI		(1 << 28)
-#define INTSTS_RXSQI		(1 << 27)
-#define INTSTS_TXLEI		(1 << 26)
-#define INTSTS_ECIE		(1 << 25)
-#define INTSTS_TXUHI		(1 << 24)
-#define INTSTS_MOI		(1 << 18)
-#define INTSTS_TXCOI		(1 << 17)
-#define INTSTS_RXROI		(1 << 16)
-#define INTSTS_MIII		(1 << 12)
-#define INTSTS_PHYI		(1 << 11)
-#define INTSTS_TI		(1 << 10)
-#define INTSTS_AHBE		(1 << 8)
-#define INTSTS_OTHER		(1 << 4)
-#define INTSTS_TXSQ		(1 << 3)
-#define INTSTS_RXSQ		(1 << 2)
-
-#define BMCTL_MT		(1 << 13)
-#define BMCTL_TT		(1 << 12)
-#define BMCTL_UNH		(1 << 11)
-#define BMCTL_TXCHR		(1 << 10)
-#define BMCTL_TXDIS		(1 << 9)
-#define BMCTL_TXEN		(1 << 8)
-#define BMCTL_EH2		(1 << 6)
-#define BMCTL_EH1		(1 << 5)
-#define BMCTL_EEOB		(1 << 4)
-#define BMCTL_RXCHR		(1 << 2)
-#define BMCTL_RXDIS		(1 << 1)
-#define BMCTL_RXEN		(1 << 0)
-
-#define BMSTS_TXACT		(1 << 7)
-#define BMSTS_TP		(1 << 4)
-#define BMSTS_RXACT		(1 << 3)
-#define BMSTS_QID_MASK		0x07
-#define BMSTS_QID_RXDATA	0x00
-#define BMSTS_QID_TXDATA	0x01
-#define BMSTS_QID_RXSTS		0x02
-#define BMSTS_QID_TXSTS		0x03
-#define BMSTS_QID_RXDESC	0x04
-#define BMSTS_QID_TXDESC	0x05
-
-#define AFP_MASK		0x07
-#define AFP_IAPRIMARY		0x00
-#define AFP_IASECONDARY1	0x01
-#define AFP_IASECONDARY2	0x02
-#define AFP_IASECONDARY3	0x03
-#define AFP_TX			0x06
-#define AFP_HASH		0x07
-
-#define RXCTL_PAUSEA		(1 << 20)
-#define RXCTL_RXFCE1		(1 << 19)
-#define RXCTL_RXFCE0		(1 << 18)
-#define RXCTL_BCRC		(1 << 17)
-#define RXCTL_SRXON		(1 << 16)
-#define RXCTL_RCRCA		(1 << 13)
-#define RXCTL_RA		(1 << 12)
-#define RXCTL_PA		(1 << 11)
-#define RXCTL_BA		(1 << 10)
-#define RXCTL_MA		(1 << 9)
-#define RXCTL_IAHA		(1 << 8)
-#define RXCTL_IA3		(1 << 3)
-#define RXCTL_IA2		(1 << 2)
-#define RXCTL_IA1		(1 << 1)
-#define RXCTL_IA0		(1 << 0)
-
-#define TXCTL_DEFDIS		(1 << 7)
-#define TXCTL_MBE		(1 << 6)
-#define TXCTL_ICRC		(1 << 5)
-#define TXCTL_TPD		(1 << 4)
-#define TXCTL_OCOLL		(1 << 3)
-#define TXCTL_SP		(1 << 2)
-#define TXCTL_PB		(1 << 1)
-#define TXCTL_STXON		(1 << 0)
-
-#define MIICMD_REGAD_MASK	(0x001F)
-#define MIICMD_PHYAD_MASK	(0x03E0)
-#define MIICMD_OPCODE_MASK	(0xC000)
-#define MIICMD_PHYAD_8950	(0x0000)
-#define MIICMD_OPCODE_READ	(0x8000)
-#define MIICMD_OPCODE_WRITE	(0x4000)
-
-#define MIISTS_BUSY		(1 << 0)
-
-/*
- * 0x80020000 - 0x8002FFFF: USB OHCI
- */
-#define USB_OFFSET			0x020000
-#define USB_BASE			(EP93XX_AHB_BASE | USB_OFFSET)
-
-/*
- * 0x80030000 - 0x8003FFFF: Raster engine
- */
-#if (defined(CONFIG_EP9307) || defined(CONFIG_EP9312) || defined(CONFIG_EP9315))
-#define RASTER_OFFSET			0x030000
-#define RASTER_BASE			(EP93XX_AHB_BASE | RASTER_OFFSET)
-#endif
-
-/*
- * 0x80040000 - 0x8004FFFF: Graphics accelerator
- */
-#if defined(CONFIG_EP9315)
-#define GFX_OFFSET			0x040000
-#define GFX_BASE			(EP93XX_AHB_BASE | GFX_OFFSET)
-#endif
-
-/*
- * 0x80050000 - 0x8005FFFF: Reserved
- */
-
-/*
- * 0x80060000 - 0x8006FFFF: SDRAM controller
- */
-#define SDRAM_OFFSET			0x060000
-#define SDRAM_BASE			(EP93XX_AHB_BASE | SDRAM_OFFSET)
-
-#ifndef __ASSEMBLY__
-struct sdram_regs {
-	uint32_t reserved;
-	uint32_t glconfig;
-	uint32_t refrshtimr;
-	uint32_t bootsts;
-	uint32_t devcfg0;
-	uint32_t devcfg1;
-	uint32_t devcfg2;
-	uint32_t devcfg3;
-};
-#endif
-
-#define SDRAM_DEVCFG_EXTBUSWIDTH	(1 << 2)
-#define SDRAM_DEVCFG_BANKCOUNT		(1 << 3)
-#define SDRAM_DEVCFG_SROMLL		(1 << 5)
-#define SDRAM_DEVCFG_CASLAT_2		0x00010000
-#define SDRAM_DEVCFG_RASTOCAS_2		0x00200000
-
-#define GLCONFIG_INIT			(1 << 0)
-#define GLCONFIG_MRS			(1 << 1)
-#define GLCONFIG_SMEMBUSY		(1 << 5)
-#define GLCONFIG_LCR			(1 << 6)
-#define GLCONFIG_REARBEN		(1 << 7)
-#define GLCONFIG_CLKSHUTDOWN		(1 << 30)
-#define GLCONFIG_CKE			(1 << 31)
-
-/*
- * 0x80070000 - 0x8007FFFF: Reserved
- */
-
-/*
- * 0x80080000 - 0x8008FFFF: SRAM controller & PCMCIA
- */
-#define SMC_OFFSET			0x080000
-#define SMC_BASE			(EP93XX_AHB_BASE | SMC_OFFSET)
-
-#ifndef __ASSEMBLY__
-struct smc_regs {
-	uint32_t bcr0;
-	uint32_t bcr1;
-	uint32_t bcr2;
-	uint32_t bcr3;
-	uint32_t reserved0[2];
-	uint32_t bcr6;
-	uint32_t bcr7;
-#if defined(CONFIG_EP9315)
-	uint32_t pcattribute;
-	uint32_t pccommon;
-	uint32_t pcio;
-	uint32_t reserved1[5];
-	uint32_t pcmciactrl;
-#endif
-};
-#endif
-
-#define SMC_BCR_IDCY_SHIFT	0
-#define SMC_BCR_WST1_SHIFT	5
-#define SMC_BCR_BLE		(1 << 10)
-#define SMC_BCR_WST2_SHIFT	11
-#define SMC_BCR_MW_SHIFT	28
-
-/*
- * 0x80090000 - 0x8009FFFF: Boot ROM
- */
-
-/*
- * 0x800A0000 - 0x800AFFFF: IDE interface
- */
-
-/*
- * 0x800B0000 - 0x800BFFFF: VIC1
- */
-
-/*
- * 0x800C0000 - 0x800CFFFF: VIC2
- */
-
-/*
- * 0x800D0000 - 0x800FFFFF: Reserved
- */
-
-/*
- * 0x80800000 - 0x8080FFFF: Reserved
- */
-
-/*
- * 0x80810000 - 0x8081FFFF: Timers
- */
-#define TIMER_OFFSET		0x010000
-#define TIMER_BASE		(EP93XX_APB_BASE | TIMER_OFFSET)
-
-#ifndef __ASSEMBLY__
-struct timer {
-	uint32_t load;
-	uint32_t value;
-	uint32_t control;
-	uint32_t clear;
-};
-
-struct timer4 {
-	uint32_t value_low;
-	uint32_t value_high;
-};
-
-struct timer_regs {
-	struct timer timer1;
-	uint32_t reserved0[4];
-	struct timer timer2;
-	uint32_t reserved1[12];
-	struct timer4 timer4;
-	uint32_t reserved2[6];
-	struct timer timer3;
-};
-#endif
-
-/*
- * 0x80820000 - 0x8082FFFF: I2S
- */
-#define I2S_OFFSET		0x020000
-#define I2S_BASE		(EP93XX_APB_BASE | I2S_OFFSET)
-
-/*
- * 0x80830000 - 0x8083FFFF: Security
- */
-#define SECURITY_OFFSET		0x030000
-#define SECURITY_BASE		(EP93XX_APB_BASE | SECURITY_OFFSET)
-
-#define EXTENSIONID		(SECURITY_BASE + 0x2714)
-
-/*
- * 0x80840000 - 0x8084FFFF: GPIO
- */
-#define GPIO_OFFSET		0x040000
-#define GPIO_BASE		(EP93XX_APB_BASE | GPIO_OFFSET)
-
-#ifndef __ASSEMBLY__
-struct gpio_int {
-	uint32_t inttype1;
-	uint32_t inttype2;
-	uint32_t eoi;
-	uint32_t inten;
-	uint32_t intsts;
-	uint32_t rawintsts;
-	uint32_t db;
-};
-
-struct gpio_regs {
-	uint32_t padr;
-	uint32_t pbdr;
-	uint32_t pcdr;
-	uint32_t pddr;
-	uint32_t paddr;
-	uint32_t pbddr;
-	uint32_t pcddr;
-	uint32_t pdddr;
-	uint32_t pedr;
-	uint32_t peddr;
-	uint32_t reserved0[2];
-	uint32_t pfdr;
-	uint32_t pfddr;
-	uint32_t pgdr;
-	uint32_t pgddr;
-	uint32_t phdr;
-	uint32_t phddr;
-	uint32_t reserved1;
-	uint32_t finttype1;
-	uint32_t finttype2;
-	uint32_t reserved2;
-	struct gpio_int pfint;
-	uint32_t reserved3[10];
-	struct gpio_int paint;
-	struct gpio_int pbint;
-	uint32_t eedrive;
-};
-#endif
-
-/*
- * 0x80850000 - 0x8087FFFF: Reserved
- */
-
-/*
- * 0x80880000 - 0x8088FFFF: AAC
- */
-#define AAC_OFFSET		0x080000
-#define AAC_BASE		(EP93XX_APB_BASE | AAC_OFFSET)
-
-/*
- * 0x80890000 - 0x8089FFFF: Reserved
- */
-
-/*
- * 0x808A0000 - 0x808AFFFF: SPI
- */
-#define SPI_OFFSET		0x0A0000
-#define SPI_BASE		(EP93XX_APB_BASE | SPI_OFFSET)
-
-/*
- * 0x808B0000 - 0x808BFFFF: IrDA
- */
-#define IRDA_OFFSET		0x0B0000
-#define IRDA_BASE		(EP93XX_APB_BASE | IRDA_OFFSET)
-
-/*
- * 0x808C0000 - 0x808CFFFF: UART1
- */
-#define UART1_OFFSET		0x0C0000
-#define UART1_BASE		(EP93XX_APB_BASE | UART1_OFFSET)
-
-/*
- * 0x808D0000 - 0x808DFFFF: UART2
- */
-#define UART2_OFFSET		0x0D0000
-#define UART2_BASE		(EP93XX_APB_BASE | UART2_OFFSET)
-
-/*
- * 0x808E0000 - 0x808EFFFF: UART3
- */
-#define UART3_OFFSET		0x0E0000
-#define UART3_BASE		(EP93XX_APB_BASE | UART3_OFFSET)
-
-/*
- * 0x808F0000 - 0x808FFFFF: Key Matrix
- */
-#define KEY_OFFSET		0x0F0000
-#define KEY_BASE		(EP93XX_APB_BASE | KEY_OFFSET)
-
-/*
- * 0x80900000 - 0x8090FFFF: Touchscreen
- */
-#define TOUCH_OFFSET		0x900000
-#define TOUCH_BASE		(EP93XX_APB_BASE | TOUCH_OFFSET)
-
-/*
- * 0x80910000 - 0x8091FFFF: Pulse Width Modulation
- */
-#define PWM_OFFSET		0x910000
-#define PWM_BASE		(EP93XX_APB_BASE | PWM_OFFSET)
-
-/*
- * 0x80920000 - 0x8092FFFF: Real time clock
- */
-#define RTC_OFFSET		0x920000
-#define RTC_BASE		(EP93XX_APB_BASE | RTC_OFFSET)
-
-/*
- * 0x80930000 - 0x8093FFFF: Syscon
- */
-#define SYSCON_OFFSET		0x930000
-#define SYSCON_BASE		(EP93XX_APB_BASE | SYSCON_OFFSET)
-
-#ifndef __ASSEMBLY__
-struct syscon_regs {
-	uint32_t pwrsts;
-	uint32_t pwrcnt;
-	uint32_t halt;
-	uint32_t stby;
-	uint32_t reserved0[2];
-	uint32_t teoi;
-	uint32_t stfclr;
-	uint32_t clkset1;
-	uint32_t clkset2;
-	uint32_t reserved1[6];
-	uint32_t scratch0;
-	uint32_t scratch1;
-	uint32_t reserved2[2];
-	uint32_t apbwait;
-	uint32_t bustmstrarb;
-	uint32_t bootmodeclr;
-	uint32_t reserved3[9];
-	uint32_t devicecfg;
-	uint32_t vidclkdiv;
-	uint32_t mirclkdiv;
-	uint32_t i2sclkdiv;
-	uint32_t keytchclkdiv;
-	uint32_t chipid;
-	uint32_t reserved4;
-	uint32_t syscfg;
-	uint32_t reserved5[8];
-	uint32_t sysswlock;
-};
-#else
-#define SYSCON_SCRATCH0		(SYSCON_BASE + 0x0040)
-#endif
-
-#define SYSCON_PWRCNT_UART_BAUD			(1 << 29)
-
-#define SYSCON_CLKSET_PLL_X2IPD_SHIFT		0
-#define SYSCON_CLKSET_PLL_X2FBD2_SHIFT		5
-#define SYSCON_CLKSET_PLL_X1FBD1_SHIFT		11
-#define SYSCON_CLKSET_PLL_PS_SHIFT		16
-#define SYSCON_CLKSET1_PCLK_DIV_SHIFT		18
-#define SYSCON_CLKSET1_HCLK_DIV_SHIFT		20
-#define SYSCON_CLKSET1_NBYP1			(1 << 23)
-#define SYSCON_CLKSET1_FCLK_DIV_SHIFT		25
-
-#define SYSCON_CLKSET2_PLL2_EN			(1 << 18)
-#define SYSCON_CLKSET2_NBYP2			(1 << 19)
-#define SYSCON_CLKSET2_USB_DIV_SHIFT		28
-
-#define SYSCON_CHIPID_REV_MASK			0xF0000000
-#define SYSCON_DEVICECFG_SWRST			(1 << 31)
-
-/*
- * 0x80930000 - 0x8093FFFF: Watchdog Timer
- */
-#define WATCHDOG_OFFSET		0x940000
-#define WATCHDOG_BASE		(EP93XX_APB_BASE | WATCHDOG_OFFSET)
-
-/*
- * 0x80950000 - 0x9000FFFF: Reserved
- */
diff --git a/arch/arm/include/asm/arch-imx/imx-regs.h b/arch/arm/include/asm/arch-imx/imx-regs.h
deleted file mode 100644
index ec94ba9..0000000
--- a/arch/arm/include/asm/arch-imx/imx-regs.h
+++ /dev/null
@@ -1,634 +0,0 @@
-#ifndef _IMX_REGS_H
-#define _IMX_REGS_H
-/* ------------------------------------------------------------------------
- *  Motorola IMX system registers
- * ------------------------------------------------------------------------
- *
- */
-
-#define IO_ADDRESS(x) ((x) | IMX_IO_BASE)
-
-# ifndef __ASSEMBLY__
-# define __REG(x)	(*((volatile u32 *)IO_ADDRESS(x)))
-# define __REG2(x,y)        (*(volatile u32 *)((u32)&__REG(x) + (y)))
-# else
-#  define __REG(x) (x)
-#  define __REG2(x,y) ((x)+(y))
-#endif
-
-#define IMX_IO_BASE		0x00200000
-
-/*
- *  Register BASEs, based on OFFSETs
- *
- */
-#define IMX_AIPI1_BASE             (0x00000 + IMX_IO_BASE)
-#define IMX_WDT_BASE               (0x01000 + IMX_IO_BASE)
-#define IMX_TIM1_BASE              (0x02000 + IMX_IO_BASE)
-#define IMX_TIM2_BASE              (0x03000 + IMX_IO_BASE)
-#define IMX_RTC_BASE               (0x04000 + IMX_IO_BASE)
-#define IMX_LCDC_BASE              (0x05000 + IMX_IO_BASE)
-#define IMX_UART1_BASE             (0x06000 + IMX_IO_BASE)
-#define IMX_UART2_BASE             (0x07000 + IMX_IO_BASE)
-#define IMX_PWM_BASE               (0x08000 + IMX_IO_BASE)
-#define IMX_DMAC_BASE              (0x09000 + IMX_IO_BASE)
-#define IMX_AIPI2_BASE             (0x10000 + IMX_IO_BASE)
-#define IMX_SIM_BASE               (0x11000 + IMX_IO_BASE)
-#define IMX_USBD_BASE              (0x12000 + IMX_IO_BASE)
-#define IMX_SPI1_BASE              (0x13000 + IMX_IO_BASE)
-#define IMX_MMC_BASE               (0x14000 + IMX_IO_BASE)
-#define IMX_ASP_BASE               (0x15000 + IMX_IO_BASE)
-#define IMX_BTA_BASE               (0x16000 + IMX_IO_BASE)
-#define IMX_I2C_BASE               (0x17000 + IMX_IO_BASE)
-#define IMX_SSI_BASE               (0x18000 + IMX_IO_BASE)
-#define IMX_SPI2_BASE              (0x19000 + IMX_IO_BASE)
-#define IMX_MSHC_BASE              (0x1A000 + IMX_IO_BASE)
-#define IMX_PLL_BASE               (0x1B000 + IMX_IO_BASE)
-#define IMX_SYSCTRL_BASE           (0x1B800 + IMX_IO_BASE)
-#define IMX_GPIO_BASE              (0x1C000 + IMX_IO_BASE)
-#define IMX_EIM_BASE               (0x20000 + IMX_IO_BASE)
-#define IMX_SDRAMC_BASE            (0x21000 + IMX_IO_BASE)
-#define IMX_MMA_BASE               (0x22000 + IMX_IO_BASE)
-#define IMX_AITC_BASE              (0x23000 + IMX_IO_BASE)
-#define IMX_CSI_BASE               (0x24000 + IMX_IO_BASE)
-
-/* Watchdog Registers*/
-
-#define WCR  __REG(IMX_WDT_BASE + 0x00) /* Watchdog Control Register */
-#define WSR  __REG(IMX_WDT_BASE + 0x04) /* Watchdog Service Register */
-#define WSTR __REG(IMX_WDT_BASE + 0x08) /* Watchdog Status Register  */
-
-/* SYSCTRL Registers */
-#define SIDR   __REG(IMX_SYSCTRL_BASE + 0x4) /* Silicon ID Register		    */
-#define FMCR   __REG(IMX_SYSCTRL_BASE + 0x8) /* Function Multiplex Control Register */
-#define GPCR   __REG(IMX_SYSCTRL_BASE + 0xC) /* Function Multiplex Control Register */
-
-/* Chip Select Registers */
-#define CS0U __REG(IMX_EIM_BASE)        /* Chip Select 0 Upper Register */
-#define CS0L __REG(IMX_EIM_BASE + 0x4)  /* Chip Select 0 Lower Register */
-#define CS1U __REG(IMX_EIM_BASE + 0x8)  /* Chip Select 1 Upper Register */
-#define CS1L __REG(IMX_EIM_BASE + 0xc)  /* Chip Select 1 Lower Register */
-#define CS2U __REG(IMX_EIM_BASE + 0x10) /* Chip Select 2 Upper Register */
-#define CS2L __REG(IMX_EIM_BASE + 0x14) /* Chip Select 2 Lower Register */
-#define CS3U __REG(IMX_EIM_BASE + 0x18) /* Chip Select 3 Upper Register */
-#define CS3L __REG(IMX_EIM_BASE + 0x1c) /* Chip Select 3 Lower Register */
-#define CS4U __REG(IMX_EIM_BASE + 0x20) /* Chip Select 4 Upper Register */
-#define CS4L __REG(IMX_EIM_BASE + 0x24) /* Chip Select 4 Lower Register */
-#define CS5U __REG(IMX_EIM_BASE + 0x28) /* Chip Select 5 Upper Register */
-#define CS5L __REG(IMX_EIM_BASE + 0x2c) /* Chip Select 5 Lower Register */
-#define EIM  __REG(IMX_EIM_BASE + 0x30) /* EIM Configuration Register */
-
-/* SDRAM controller registers */
-
-#define SDCTL0 __REG(IMX_SDRAMC_BASE)        /* SDRAM 0 Control Register */
-#define SDCTL1 __REG(IMX_SDRAMC_BASE + 0x4)  /* SDRAM 1 Control Register */
-#define SDMISC __REG(IMX_SDRAMC_BASE + 0x14) /* Miscellaneous Register */
-#define SDRST  __REG(IMX_SDRAMC_BASE + 0x18) /* SDRAM Reset Register */
-
-/* PLL registers */
-#define CSCR   __REG(IMX_PLL_BASE)        /* Clock Source Control Register */
-#define CSCR_SPLL_RESTART	(1<<22)
-#define CSCR_MPLL_RESTART	(1<<21)
-#define CSCR_SYSTEM_SEL		(1<<16)
-#define CSCR_BCLK_DIV		(0xf<<10)
-#define CSCR_MPU_PRESC		(1<<15)
-#define CSCR_SPEN		(1<<1)
-#define CSCR_MPEN		(1<<0)
-
-#define MPCTL0 __REG(IMX_PLL_BASE + 0x4)  /* MCU PLL Control Register 0 */
-#define MPCTL1 __REG(IMX_PLL_BASE + 0x8)  /* MCU PLL and System Clock Register 1 */
-#define SPCTL0 __REG(IMX_PLL_BASE + 0xc)  /* System PLL Control Register 0 */
-#define SPCTL1 __REG(IMX_PLL_BASE + 0x10) /* System PLL Control Register 1 */
-#define PCDR   __REG(IMX_PLL_BASE + 0x20) /* Peripheral Clock Divider Register */
-
-/*
- *  GPIO Module and I/O Multiplexer
- *  x = 0..3 for reg_A, reg_B, reg_C, reg_D
- */
-#define DDIR(x)    __REG2(IMX_GPIO_BASE + 0x00, ((x) & 3) << 8)
-#define OCR1(x)    __REG2(IMX_GPIO_BASE + 0x04, ((x) & 3) << 8)
-#define OCR2(x)    __REG2(IMX_GPIO_BASE + 0x08, ((x) & 3) << 8)
-#define ICONFA1(x) __REG2(IMX_GPIO_BASE + 0x0c, ((x) & 3) << 8)
-#define ICONFA2(x) __REG2(IMX_GPIO_BASE + 0x10, ((x) & 3) << 8)
-#define ICONFB1(x) __REG2(IMX_GPIO_BASE + 0x14, ((x) & 3) << 8)
-#define ICONFB2(x) __REG2(IMX_GPIO_BASE + 0x18, ((x) & 3) << 8)
-#define DR(x)      __REG2(IMX_GPIO_BASE + 0x1c, ((x) & 3) << 8)
-#define GIUS(x)    __REG2(IMX_GPIO_BASE + 0x20, ((x) & 3) << 8)
-#define SSR(x)     __REG2(IMX_GPIO_BASE + 0x24, ((x) & 3) << 8)
-#define ICR1(x)    __REG2(IMX_GPIO_BASE + 0x28, ((x) & 3) << 8)
-#define ICR2(x)    __REG2(IMX_GPIO_BASE + 0x2c, ((x) & 3) << 8)
-#define IMR(x)     __REG2(IMX_GPIO_BASE + 0x30, ((x) & 3) << 8)
-#define ISR(x)     __REG2(IMX_GPIO_BASE + 0x34, ((x) & 3) << 8)
-#define GPR(x)     __REG2(IMX_GPIO_BASE + 0x38, ((x) & 3) << 8)
-#define SWR(x)     __REG2(IMX_GPIO_BASE + 0x3c, ((x) & 3) << 8)
-#define PUEN(x)    __REG2(IMX_GPIO_BASE + 0x40, ((x) & 3) << 8)
-
-#define GPIO_PORT_MAX  3
-
-#define GPIO_PIN_MASK 0x1f
-#define GPIO_PORT_MASK (0x3 << 5)
-
-#define GPIO_PORT_SHIFT 5
-#define GPIO_PORTA (0<<5)
-#define GPIO_PORTB (1<<5)
-#define GPIO_PORTC (2<<5)
-#define GPIO_PORTD (3<<5)
-
-#define GPIO_OUT   (1<<7)
-#define GPIO_IN    (0<<7)
-#define GPIO_PUEN  (1<<8)
-
-#define GPIO_PF    (0<<9)
-#define GPIO_AF    (1<<9)
-
-#define GPIO_OCR_SHIFT 10
-#define GPIO_OCR_MASK (3<<10)
-#define GPIO_AIN   (0<<10)
-#define GPIO_BIN   (1<<10)
-#define GPIO_CIN   (2<<10)
-#define GPIO_DR    (3<<10)
-
-#define GPIO_AOUT_SHIFT 12
-#define GPIO_AOUT_MASK (3<<12)
-#define GPIO_AOUT     (0<<12)
-#define GPIO_AOUT_ISR (1<<12)
-#define GPIO_AOUT_0   (2<<12)
-#define GPIO_AOUT_1   (3<<12)
-
-#define GPIO_BOUT_SHIFT 14
-#define GPIO_BOUT_MASK (3<<14)
-#define GPIO_BOUT      (0<<14)
-#define GPIO_BOUT_ISR  (1<<14)
-#define GPIO_BOUT_0    (2<<14)
-#define GPIO_BOUT_1    (3<<14)
-
-#define GPIO_GIUS      (1<<16)
-
-/* assignements for GPIO alternate/primary functions */
-
-/* FIXME: This list is not completed. The correct directions are
- * missing on some (many) pins
- */
-#define PA0_AIN_SPI2_CLK     ( GPIO_GIUS | GPIO_PORTA | GPIO_OUT | 0 )
-#define PA0_AF_ETMTRACESYNC  ( GPIO_PORTA | GPIO_AF | 0 )
-#define PA1_AOUT_SPI2_RXD    ( GPIO_GIUS | GPIO_PORTA | GPIO_IN | 1 )
-#define PA1_PF_TIN           ( GPIO_PORTA | GPIO_PF | 1 )
-#define PA2_PF_PWM0          ( GPIO_PORTA | GPIO_OUT | GPIO_PF | 2 )
-#define PA3_PF_CSI_MCLK      ( GPIO_PORTA | GPIO_PF | 3 )
-#define PA4_PF_CSI_D0        ( GPIO_PORTA | GPIO_PF | 4 )
-#define PA5_PF_CSI_D1        ( GPIO_PORTA | GPIO_PF | 5 )
-#define PA6_PF_CSI_D2        ( GPIO_PORTA | GPIO_PF | 6 )
-#define PA7_PF_CSI_D3        ( GPIO_PORTA | GPIO_PF | 7 )
-#define PA8_PF_CSI_D4        ( GPIO_PORTA | GPIO_PF | 8 )
-#define PA9_PF_CSI_D5        ( GPIO_PORTA | GPIO_PF | 9 )
-#define PA10_PF_CSI_D6       ( GPIO_PORTA | GPIO_PF | 10 )
-#define PA11_PF_CSI_D7       ( GPIO_PORTA | GPIO_PF | 11 )
-#define PA12_PF_CSI_VSYNC    ( GPIO_PORTA | GPIO_PF | 12 )
-#define PA13_PF_CSI_HSYNC    ( GPIO_PORTA | GPIO_PF | 13 )
-#define PA14_PF_CSI_PIXCLK   ( GPIO_PORTA | GPIO_PF | 14 )
-#define PA15_PF_I2C_SDA      ( GPIO_PORTA | GPIO_OUT | GPIO_PF | 15 )
-#define PA16_PF_I2C_SCL      ( GPIO_PORTA | GPIO_OUT | GPIO_PF | 16 )
-#define PA17_AF_ETMTRACEPKT4 ( GPIO_PORTA | GPIO_AF | 17 )
-#define PA17_AIN_SPI2_SS     ( GPIO_GIUS | GPIO_PORTA | GPIO_OUT | 17 )
-#define PA18_AF_ETMTRACEPKT5 ( GPIO_PORTA | GPIO_AF | 18 )
-#define PA19_AF_ETMTRACEPKT6 ( GPIO_PORTA | GPIO_AF | 19 )
-#define PA20_AF_ETMTRACEPKT7 ( GPIO_PORTA | GPIO_AF | 20 )
-#define PA21_PF_A0           ( GPIO_PORTA | GPIO_PF | 21 )
-#define PA22_PF_CS4          ( GPIO_PORTA | GPIO_PF | 22 )
-#define PA23_PF_CS5          ( GPIO_PORTA | GPIO_PF | 23 )
-#define PA24_PF_A16          ( GPIO_PORTA | GPIO_PF | 24 )
-#define PA24_AF_ETMTRACEPKT0 ( GPIO_PORTA | GPIO_AF | 24 )
-#define PA25_PF_A17          ( GPIO_PORTA | GPIO_PF | 25 )
-#define PA25_AF_ETMTRACEPKT1 ( GPIO_PORTA | GPIO_AF | 25 )
-#define PA26_PF_A18          ( GPIO_PORTA | GPIO_PF | 26 )
-#define PA26_AF_ETMTRACEPKT2 ( GPIO_PORTA | GPIO_AF | 26 )
-#define PA27_PF_A19          ( GPIO_PORTA | GPIO_PF | 27 )
-#define PA27_AF_ETMTRACEPKT3 ( GPIO_PORTA | GPIO_AF | 27 )
-#define PA28_PF_A20          ( GPIO_PORTA | GPIO_PF | 28 )
-#define PA28_AF_ETMPIPESTAT0 ( GPIO_PORTA | GPIO_AF | 28 )
-#define PA29_PF_A21          ( GPIO_PORTA | GPIO_PF | 29 )
-#define PA29_AF_ETMPIPESTAT1 ( GPIO_PORTA | GPIO_AF | 29 )
-#define PA30_PF_A22          ( GPIO_PORTA | GPIO_PF | 30 )
-#define PA30_AF_ETMPIPESTAT2 ( GPIO_PORTA | GPIO_AF | 30 )
-#define PA31_PF_A23          ( GPIO_PORTA | GPIO_PF | 31 )
-#define PA31_AF_ETMTRACECLK  ( GPIO_PORTA | GPIO_AF | 31 )
-#define PB8_PF_SD_DAT0       ( GPIO_PORTB | GPIO_PF | GPIO_PUEN | 8 )
-#define PB8_AF_MS_PIO        ( GPIO_PORTB | GPIO_AF | 8 )
-#define PB9_PF_SD_DAT1       ( GPIO_PORTB | GPIO_PF | GPIO_PUEN  | 9 )
-#define PB9_AF_MS_PI1        ( GPIO_PORTB | GPIO_AF | 9 )
-#define PB10_PF_SD_DAT2      ( GPIO_PORTB | GPIO_PF | GPIO_PUEN  | 10 )
-#define PB10_AF_MS_SCLKI     ( GPIO_PORTB | GPIO_AF | 10 )
-#define PB11_PF_SD_DAT3      ( GPIO_PORTB | GPIO_PF | 11 )
-#define PB11_AF_MS_SDIO      ( GPIO_PORTB | GPIO_AF | 11 )
-#define PB12_PF_SD_CLK       ( GPIO_PORTB | GPIO_PF | 12 )
-#define PB12_AF_MS_SCLK0     ( GPIO_PORTB | GPIO_AF | 12 )
-#define PB13_PF_SD_CMD       ( GPIO_PORTB | GPIO_PF | GPIO_PUEN | 13 )
-#define PB13_AF_MS_BS        ( GPIO_PORTB | GPIO_AF | 13 )
-#define PB14_AF_SSI_RXFS     ( GPIO_PORTB | GPIO_AF | 14 )
-#define PB15_AF_SSI_RXCLK    ( GPIO_PORTB | GPIO_AF | 15 )
-#define PB16_AF_SSI_RXDAT    ( GPIO_PORTB | GPIO_IN | GPIO_AF | 16 )
-#define PB17_AF_SSI_TXDAT    ( GPIO_PORTB | GPIO_OUT | GPIO_AF | 17 )
-#define PB18_AF_SSI_TXFS     ( GPIO_PORTB | GPIO_AF | 18 )
-#define PB19_AF_SSI_TXCLK    ( GPIO_PORTB | GPIO_AF | 19 )
-#define PB20_PF_USBD_AFE     ( GPIO_PORTB | GPIO_PF | 20 )
-#define PB21_PF_USBD_OE      ( GPIO_PORTB | GPIO_PF | 21 )
-#define PB22_PFUSBD_RCV      ( GPIO_PORTB | GPIO_PF | 22 )
-#define PB23_PF_USBD_SUSPND  ( GPIO_PORTB | GPIO_PF | 23 )
-#define PB24_PF_USBD_VP      ( GPIO_PORTB | GPIO_PF | 24 )
-#define PB25_PF_USBD_VM      ( GPIO_PORTB | GPIO_PF | 25 )
-#define PB26_PF_USBD_VPO     ( GPIO_PORTB | GPIO_PF | 26 )
-#define PB27_PF_USBD_VMO     ( GPIO_PORTB | GPIO_PF | 27 )
-#define PB28_PF_UART2_CTS    ( GPIO_PORTB | GPIO_OUT | GPIO_PF | 28 )
-#define PB29_PF_UART2_RTS    ( GPIO_PORTB | GPIO_IN | GPIO_PF | 29 )
-#define PB30_PF_UART2_TXD    ( GPIO_PORTB | GPIO_OUT | GPIO_PF | 30 )
-#define PB31_PF_UART2_RXD    ( GPIO_PORTB | GPIO_IN | GPIO_PF | 31 )
-#define PC3_PF_SSI_RXFS      ( GPIO_PORTC | GPIO_PF | 3 )
-#define PC4_PF_SSI_RXCLK     ( GPIO_PORTC | GPIO_PF | 4 )
-#define PC5_PF_SSI_RXDAT     ( GPIO_PORTC | GPIO_IN | GPIO_PF | 5 )
-#define PC6_PF_SSI_TXDAT     ( GPIO_PORTC | GPIO_OUT | GPIO_PF | 6 )
-#define PC7_PF_SSI_TXFS      ( GPIO_PORTC | GPIO_PF | 7 )
-#define PC8_PF_SSI_TXCLK     ( GPIO_PORTC | GPIO_PF | 8 )
-#define PC9_PF_UART1_CTS     ( GPIO_PORTC | GPIO_OUT | GPIO_PF | 9 )
-#define PC10_PF_UART1_RTS    ( GPIO_PORTC | GPIO_IN | GPIO_PF | 10 )
-#define PC11_PF_UART1_TXD    ( GPIO_PORTC | GPIO_OUT | GPIO_PF | 11 )
-#define PC12_PF_UART1_RXD    ( GPIO_PORTC | GPIO_IN | GPIO_PF | 12 )
-#define PC13_PF_SPI1_SPI_RDY ( GPIO_PORTC | GPIO_PF | 13 )
-#define PC14_PF_SPI1_SCLK    ( GPIO_PORTC | GPIO_PF | 14 )
-#define PC15_PF_SPI1_SS      ( GPIO_PORTC | GPIO_PF | 15 )
-#define PC16_PF_SPI1_MISO    ( GPIO_PORTC | GPIO_PF | 16 )
-#define PC17_PF_SPI1_MOSI    ( GPIO_PORTC | GPIO_PF | 17 )
-#define PC24_BIN_UART3_RI    ( GPIO_GIUS | GPIO_PORTC | GPIO_OUT | GPIO_BIN | 24 )
-#define PC25_BIN_UART3_DSR   ( GPIO_GIUS | GPIO_PORTC | GPIO_OUT | GPIO_BIN | 25 )
-#define PC26_AOUT_UART3_DTR  ( GPIO_GIUS | GPIO_PORTC | GPIO_IN | 26 )
-#define PC27_BIN_UART3_DCD   ( GPIO_GIUS | GPIO_PORTC | GPIO_OUT | GPIO_BIN | 27 )
-#define PC28_BIN_UART3_CTS   ( GPIO_GIUS | GPIO_PORTC | GPIO_OUT | GPIO_BIN | 28 )
-#define PC29_AOUT_UART3_RTS  ( GPIO_GIUS | GPIO_PORTC | GPIO_IN | 29 )
-#define PC30_BIN_UART3_TX    ( GPIO_GIUS | GPIO_PORTC | GPIO_BIN | 30 )
-#define PC31_AOUT_UART3_RX   ( GPIO_GIUS | GPIO_PORTC | GPIO_IN | 31)
-#define PD6_PF_LSCLK         ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 6 )
-#define PD7_PF_REV           ( GPIO_PORTD | GPIO_PF | 7 )
-#define PD7_AF_UART2_DTR     ( GPIO_GIUS | GPIO_PORTD | GPIO_IN | GPIO_AF | 7 )
-#define PD7_AIN_SPI2_SCLK    ( GPIO_GIUS | GPIO_PORTD | GPIO_AIN | 7 )
-#define PD8_PF_CLS           ( GPIO_PORTD | GPIO_PF | 8 )
-#define PD8_AF_UART2_DCD     ( GPIO_PORTD | GPIO_OUT | GPIO_AF | 8 )
-#define PD8_AIN_SPI2_SS      ( GPIO_GIUS | GPIO_PORTD | GPIO_AIN | 8 )
-#define PD9_PF_PS            ( GPIO_PORTD | GPIO_PF | 9 )
-#define PD9_AF_UART2_RI      ( GPIO_PORTD | GPIO_OUT | GPIO_AF | 9 )
-#define PD9_AOUT_SPI2_RXD    ( GPIO_GIUS | GPIO_PORTD | GPIO_IN | 9 )
-#define PD10_PF_SPL_SPR      ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 10 )
-#define PD10_AF_UART2_DSR    ( GPIO_PORTD | GPIO_OUT | GPIO_AF | 10 )
-#define PD10_AIN_SPI2_TXD    ( GPIO_GIUS | GPIO_PORTD | GPIO_OUT | 10 )
-#define PD11_PF_CONTRAST     ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 11 )
-#define PD12_PF_ACD_OE       ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 12 )
-#define PD13_PF_LP_HSYNC     ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 13 )
-#define PD14_PF_FLM_VSYNC    ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 14 )
-#define PD15_PF_LD0          ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 15 )
-#define PD16_PF_LD1          ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 16 )
-#define PD17_PF_LD2          ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 17 )
-#define PD18_PF_LD3          ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 18 )
-#define PD19_PF_LD4          ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 19 )
-#define PD20_PF_LD5          ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 20 )
-#define PD21_PF_LD6          ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 21 )
-#define PD22_PF_LD7          ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 22 )
-#define PD23_PF_LD8          ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 23 )
-#define PD24_PF_LD9          ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 24 )
-#define PD25_PF_LD10         ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 25 )
-#define PD26_PF_LD11         ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 26 )
-#define PD27_PF_LD12         ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 27 )
-#define PD28_PF_LD13         ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 28 )
-#define PD29_PF_LD14         ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 29 )
-#define PD30_PF_LD15         ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 30 )
-#define PD31_PF_TMR2OUT      ( GPIO_PORTD | GPIO_PF | 31 )
-#define PD31_BIN_SPI2_TXD    ( GPIO_GIUS | GPIO_PORTD | GPIO_BIN | 31 )
-
-/*
- * PWM controller
- */
-#define PWMC	__REG(IMX_PWM_BASE + 0x00)	/* PWM Control Register		*/
-#define PWMS	__REG(IMX_PWM_BASE + 0x04)	/* PWM Sample Register		*/
-#define PWMP	__REG(IMX_PWM_BASE + 0x08)	/* PWM Period Register		*/
-#define PWMCNT	__REG(IMX_PWM_BASE + 0x0C)	/* PWM Counter Register		*/
-
-#define PWMC_HCTR		(0x01<<18)		/* Halfword FIFO Data Swapping	*/
-#define PWMC_BCTR		(0x01<<17)		/* Byte FIFO Data Swapping	*/
-#define PWMC_SWR		(0x01<<16)		/* Software Reset		*/
-#define PWMC_CLKSRC		(0x01<<15)		/* Clock Source			*/
-#define PWMC_PRESCALER(x)	(((x-1) & 0x7F) << 8)	/* PRESCALER			*/
-#define PWMC_IRQ		(0x01<< 7)		/* Interrupt Request		*/
-#define PWMC_IRQEN		(0x01<< 6)		/* Interrupt Request Enable	*/
-#define PWMC_FIFOAV		(0x01<< 5)		/* FIFO Available		*/
-#define PWMC_EN			(0x01<< 4)		/* Enables/Disables the PWM	*/
-#define PWMC_REPEAT(x)		(((x) & 0x03) << 2)	/* Sample Repeats		*/
-#define PWMC_CLKSEL(x)		(((x) & 0x03) << 0)	/* Clock Selection		*/
-
-#define PWMS_SAMPLE(x)		((x) & 0xFFFF)		/* Contains a two-sample word	*/
-#define PWMP_PERIOD(x)		((x) & 0xFFFF)		/* Represents the PWM's period	*/
-#define PWMC_COUNTER(x)		((x) & 0xFFFF)		/* Represents the current count value	*/
-
-/*
- *  DMA Controller
- */
-#define DCR     __REG(IMX_DMAC_BASE +0x00)	/* DMA Control Register */
-#define DISR    __REG(IMX_DMAC_BASE +0x04)	/* DMA Interrupt status Register */
-#define DIMR    __REG(IMX_DMAC_BASE +0x08)	/* DMA Interrupt mask Register */
-#define DBTOSR  __REG(IMX_DMAC_BASE +0x0c)	/* DMA Burst timeout status Register */
-#define DRTOSR  __REG(IMX_DMAC_BASE +0x10)	/* DMA Request timeout Register */
-#define DSESR   __REG(IMX_DMAC_BASE +0x14)	/* DMA Transfer Error Status Register */
-#define DBOSR   __REG(IMX_DMAC_BASE +0x18)	/* DMA Buffer overflow status Register */
-#define DBTOCR  __REG(IMX_DMAC_BASE +0x1c)	/* DMA Burst timeout control Register */
-#define WSRA    __REG(IMX_DMAC_BASE +0x40)	/* W-Size Register A */
-#define XSRA    __REG(IMX_DMAC_BASE +0x44)	/* X-Size Register A */
-#define YSRA    __REG(IMX_DMAC_BASE +0x48)	/* Y-Size Register A */
-#define WSRB    __REG(IMX_DMAC_BASE +0x4c)	/* W-Size Register B */
-#define XSRB    __REG(IMX_DMAC_BASE +0x50)	/* X-Size Register B */
-#define YSRB    __REG(IMX_DMAC_BASE +0x54)	/* Y-Size Register B */
-#define SAR(x)  __REG2( IMX_DMAC_BASE + 0x80, (x) << 6)	/* Source Address Registers */
-#define DAR(x)  __REG2( IMX_DMAC_BASE + 0x84, (x) << 6)	/* Destination Address Registers */
-#define CNTR(x) __REG2( IMX_DMAC_BASE + 0x88, (x) << 6)	/* Count Registers */
-#define CCR(x)  __REG2( IMX_DMAC_BASE + 0x8c, (x) << 6)	/* Control Registers */
-#define RSSR(x) __REG2( IMX_DMAC_BASE + 0x90, (x) << 6)	/* Request source select Registers */
-#define BLR(x)  __REG2( IMX_DMAC_BASE + 0x94, (x) << 6)	/* Burst length Registers */
-#define RTOR(x) __REG2( IMX_DMAC_BASE + 0x98, (x) << 6)	/* Request timeout Registers */
-#define BUCR(x) __REG2( IMX_DMAC_BASE + 0x98, (x) << 6)	/* Bus Utilization Registers */
-
-/* TODO: define DMA_REQ lines */
-
-#define DCR_DRST           (1<<1)
-#define DCR_DEN            (1<<0)
-#define DBTOCR_EN          (1<<15)
-#define DBTOCR_CNT(x)      ((x) & 0x7fff )
-#define CNTR_CNT(x)        ((x) & 0xffffff )
-#define CCR_DMOD_LINEAR    ( 0x0 << 12 )
-#define CCR_DMOD_2D        ( 0x1 << 12 )
-#define CCR_DMOD_FIFO      ( 0x2 << 12 )
-#define CCR_DMOD_EOBFIFO   ( 0x3 << 12 )
-#define CCR_SMOD_LINEAR    ( 0x0 << 10 )
-#define CCR_SMOD_2D        ( 0x1 << 10 )
-#define CCR_SMOD_FIFO      ( 0x2 << 10 )
-#define CCR_SMOD_EOBFIFO   ( 0x3 << 10 )
-#define CCR_MDIR_DEC       (1<<9)
-#define CCR_MSEL_B         (1<<8)
-#define CCR_DSIZ_32        ( 0x0 << 6 )
-#define CCR_DSIZ_8         ( 0x1 << 6 )
-#define CCR_DSIZ_16        ( 0x2 << 6 )
-#define CCR_SSIZ_32        ( 0x0 << 4 )
-#define CCR_SSIZ_8         ( 0x1 << 4 )
-#define CCR_SSIZ_16        ( 0x2 << 4 )
-#define CCR_REN            (1<<3)
-#define CCR_RPT            (1<<2)
-#define CCR_FRC            (1<<1)
-#define CCR_CEN            (1<<0)
-#define RTOR_EN            (1<<15)
-#define RTOR_CLK           (1<<14)
-#define RTOR_PSC           (1<<13)
-
-/*
- * LCD Controller
- */
-
-#define LCDC_SSA	__REG(IMX_LCDC_BASE+0x00)
-
-#define LCDC_SIZE	__REG(IMX_LCDC_BASE+0x04)
-#define SIZE_XMAX(x)	((((x) >> 4) & 0x3f) << 20)
-#define SIZE_YMAX(y)    ( (y) & 0x1ff )
-
-#define LCDC_VPW	__REG(IMX_LCDC_BASE+0x08)
-#define VPW_VPW(x)	( (x) & 0x3ff )
-
-#define LCDC_CPOS	__REG(IMX_LCDC_BASE+0x0C)
-#define CPOS_CC1        (1<<31)
-#define CPOS_CC0        (1<<30)
-#define CPOS_OP         (1<<28)
-#define CPOS_CXP(x)     (((x) & 3ff) << 16)
-#define CPOS_CYP(y)     ((y) & 0x1ff)
-
-#define LCDC_LCWHB	__REG(IMX_LCDC_BASE+0x10)
-#define LCWHB_BK_EN     (1<<31)
-#define LCWHB_CW(w)     (((w) & 0x1f) << 24)
-#define LCWHB_CH(h)     (((h) & 0x1f) << 16)
-#define LCWHB_BD(x)     ((x) & 0xff)
-
-#define LCDC_LCHCC	__REG(IMX_LCDC_BASE+0x14)
-#define LCHCC_CUR_COL_R(r) (((r) & 0x1f) << 11)
-#define LCHCC_CUR_COL_G(g) (((g) & 0x3f) << 5)
-#define LCHCC_CUR_COL_B(b) ((b) & 0x1f)
-
-#define LCDC_PCR	__REG(IMX_LCDC_BASE+0x18)
-#define PCR_TFT         (1<<31)
-#define PCR_COLOR       (1<<30)
-#define PCR_PBSIZ_1     (0<<28)
-#define PCR_PBSIZ_2     (1<<28)
-#define PCR_PBSIZ_4     (2<<28)
-#define PCR_PBSIZ_8     (3<<28)
-#define PCR_BPIX_1      (0<<25)
-#define PCR_BPIX_2      (1<<25)
-#define PCR_BPIX_4      (2<<25)
-#define PCR_BPIX_8      (3<<25)
-#define PCR_BPIX_12     (4<<25)
-#define PCR_BPIX_16     (4<<25)
-#define PCR_PIXPOL      (1<<24)
-#define PCR_FLMPOL      (1<<23)
-#define PCR_LPPOL       (1<<22)
-#define PCR_CLKPOL      (1<<21)
-#define PCR_OEPOL       (1<<20)
-#define PCR_SCLKIDLE    (1<<19)
-#define PCR_END_SEL     (1<<18)
-#define PCR_END_BYTE_SWAP (1<<17)
-#define PCR_REV_VS      (1<<16)
-#define PCR_ACD_SEL     (1<<15)
-#define PCR_ACD(x)      (((x) & 0x7f) << 8)
-#define PCR_SCLK_SEL    (1<<7)
-#define PCR_SHARP       (1<<6)
-#define PCR_PCD(x)      ((x) & 0x3f)
-
-#define LCDC_HCR	__REG(IMX_LCDC_BASE+0x1C)
-#define HCR_H_WIDTH(x)  (((x) & 0x3f) << 26)
-#define HCR_H_WAIT_1(x) (((x) & 0xff) << 8)
-#define HCR_H_WAIT_2(x) ((x) & 0xff)
-
-#define LCDC_VCR	__REG(IMX_LCDC_BASE+0x20)
-#define VCR_V_WIDTH(x)  (((x) & 0x3f) << 26)
-#define VCR_V_WAIT_1(x) (((x) & 0xff) << 8)
-#define VCR_V_WAIT_2(x) ((x) & 0xff)
-
-#define LCDC_POS	__REG(IMX_LCDC_BASE+0x24)
-#define POS_POS(x)      ((x) & 1f)
-
-#define LCDC_LSCR1	__REG(IMX_LCDC_BASE+0x28)
-#define LSCR1_PS_RISE_DELAY(x)    (((x) & 0x7f) << 26)
-#define LSCR1_CLS_RISE_DELAY(x)   (((x) & 0x3f) << 16)
-#define LSCR1_REV_TOGGLE_DELAY(x) (((x) & 0xf) << 8)
-#define LSCR1_GRAY2(x)            (((x) & 0xf) << 4)
-#define LSCR1_GRAY1(x)            (((x) & 0xf))
-
-#define LCDC_PWMR	__REG(IMX_LCDC_BASE+0x2C)
-#define PWMR_CLS(x)     (((x) & 0x1ff) << 16)
-#define PWMR_LDMSK      (1<<15)
-#define PWMR_SCR1       (1<<10)
-#define PWMR_SCR0       (1<<9)
-#define PWMR_CC_EN      (1<<8)
-#define PWMR_PW(x)      ((x) & 0xff)
-
-#define LCDC_DMACR	__REG(IMX_LCDC_BASE+0x30)
-#define DMACR_BURST     (1<<31)
-#define DMACR_HM(x)     (((x) & 0xf) << 16)
-#define DMACR_TM(x)     ((x) &0xf)
-
-#define LCDC_RMCR	__REG(IMX_LCDC_BASE+0x34)
-#define RMCR_LCDC_EN		(1<<1)
-#define RMCR_SELF_REF		(1<<0)
-
-#define LCDC_LCDICR	__REG(IMX_LCDC_BASE+0x38)
-#define LCDICR_INT_SYN  (1<<2)
-#define LCDICR_INT_CON  (1)
-
-#define LCDC_LCDISR	__REG(IMX_LCDC_BASE+0x40)
-#define LCDISR_UDR_ERR (1<<3)
-#define LCDISR_ERR_RES (1<<2)
-#define LCDISR_EOF     (1<<1)
-#define LCDISR_BOF     (1<<0)
-/*
- *  UART Module
- */
-#define URXD0(x) __REG2( IMX_UART1_BASE + 0x0, ((x) & 1) << 12)	/* Receiver Register */
-#define URTX0(x) __REG2( IMX_UART1_BASE + 0x40, ((x) & 1) << 12)	/* Transmitter Register */
-#define UCR1(x)  __REG2( IMX_UART1_BASE + 0x80, ((x) & 1) << 12)	/* Control Register 1 */
-#define UCR2(x)  __REG2( IMX_UART1_BASE + 0x84, ((x) & 1) << 12)	/* Control Register 2 */
-#define UCR3(x)  __REG2( IMX_UART1_BASE + 0x88, ((x) & 1) << 12)	/* Control Register 3 */
-#define UCR4(x)  __REG2( IMX_UART1_BASE + 0x8c, ((x) & 1) << 12)	/* Control Register 4 */
-#define UFCR(x)  __REG2( IMX_UART1_BASE + 0x90, ((x) & 1) << 12)	/* FIFO Control Register */
-#define USR1(x)  __REG2( IMX_UART1_BASE + 0x94, ((x) & 1) << 12)	/* Status Register 1 */
-#define USR2(x)  __REG2( IMX_UART1_BASE + 0x98, ((x) & 1) << 12)	/* Status Register 2 */
-#define UESC(x)  __REG2( IMX_UART1_BASE + 0x9c, ((x) & 1) << 12)	/* Escape Character Register */
-#define UTIM(x)  __REG2( IMX_UART1_BASE + 0xa0, ((x) & 1) << 12)	/* Escape Timer Register */
-#define UBIR(x)  __REG2( IMX_UART1_BASE + 0xa4, ((x) & 1) << 12)	/* BRM Incremental Register */
-#define UBMR(x)  __REG2( IMX_UART1_BASE + 0xa8, ((x) & 1) << 12)	/* BRM Modulator Register */
-#define UBRC(x)  __REG2( IMX_UART1_BASE + 0xac, ((x) & 1) << 12)	/* Baud Rate Count Register */
-#define BIPR1(x) __REG2( IMX_UART1_BASE + 0xb0, ((x) & 1) << 12)	/* Incremental Preset Register 1 */
-#define BIPR2(x) __REG2( IMX_UART1_BASE + 0xb4, ((x) & 1) << 12)	/* Incremental Preset Register 2 */
-#define BIPR3(x) __REG2( IMX_UART1_BASE + 0xb8, ((x) & 1) << 12)	/* Incremental Preset Register 3 */
-#define BIPR4(x) __REG2( IMX_UART1_BASE + 0xbc, ((x) & 1) << 12)	/* Incremental Preset Register 4 */
-#define BMPR1(x) __REG2( IMX_UART1_BASE + 0xc0, ((x) & 1) << 12)	/* BRM Modulator Register 1 */
-#define BMPR2(x) __REG2( IMX_UART1_BASE + 0xc4, ((x) & 1) << 12)	/* BRM Modulator Register 2 */
-#define BMPR3(x) __REG2( IMX_UART1_BASE + 0xc8, ((x) & 1) << 12)	/* BRM Modulator Register 3 */
-#define BMPR4(x) __REG2( IMX_UART1_BASE + 0xcc, ((x) & 1) << 12)	/* BRM Modulator Register 4 */
-#define UTS(x)   __REG2( IMX_UART1_BASE + 0xd0, ((x) & 1) << 12)	/* UART Test Register */
-
-/* UART Control Register Bit Fields.*/
-#define  URXD_CHARRDY    (1<<15)
-#define  URXD_ERR        (1<<14)
-#define  URXD_OVRRUN     (1<<13)
-#define  URXD_FRMERR     (1<<12)
-#define  URXD_BRK        (1<<11)
-#define  URXD_PRERR      (1<<10)
-#define  UCR1_ADEN       (1<<15) /* Auto dectect interrupt */
-#define  UCR1_ADBR       (1<<14) /* Auto detect baud rate */
-#define  UCR1_TRDYEN     (1<<13) /* Transmitter ready interrupt enable */
-#define  UCR1_IDEN       (1<<12) /* Idle condition interrupt */
-#define  UCR1_RRDYEN     (1<<9)	 /* Recv ready interrupt enable */
-#define  UCR1_RDMAEN     (1<<8)	 /* Recv ready DMA enable */
-#define  UCR1_IREN       (1<<7)	 /* Infrared interface enable */
-#define  UCR1_TXMPTYEN   (1<<6)	 /* Transimitter empty interrupt enable */
-#define  UCR1_RTSDEN     (1<<5)	 /* RTS delta interrupt enable */
-#define  UCR1_SNDBRK     (1<<4)	 /* Send break */
-#define  UCR1_TDMAEN     (1<<3)	 /* Transmitter ready DMA enable */
-#define  UCR1_UARTCLKEN  (1<<2)	 /* UART clock enabled */
-#define  UCR1_DOZE       (1<<1)	 /* Doze */
-#define  UCR1_UARTEN     (1<<0)	 /* UART enabled */
-#define  UCR2_ESCI	 (1<<15) /* Escape seq interrupt enable */
-#define  UCR2_IRTS	 (1<<14) /* Ignore RTS pin */
-#define  UCR2_CTSC	 (1<<13) /* CTS pin control */
-#define  UCR2_CTS        (1<<12) /* Clear to send */
-#define  UCR2_ESCEN      (1<<11) /* Escape enable */
-#define  UCR2_PREN       (1<<8) /* Parity enable */
-#define  UCR2_PROE       (1<<7) /* Parity odd/even */
-#define  UCR2_STPB       (1<<6)	/* Stop */
-#define  UCR2_WS         (1<<5)	/* Word size */
-#define  UCR2_RTSEN      (1<<4)	/* Request to send interrupt enable */
-#define  UCR2_TXEN       (1<<2)	/* Transmitter enabled */
-#define  UCR2_RXEN       (1<<1)	/* Receiver enabled */
-#define  UCR2_SRST	 (1<<0)	/* SW reset */
-#define  UCR3_DTREN	 (1<<13) /* DTR interrupt enable */
-#define  UCR3_PARERREN   (1<<12) /* Parity enable */
-#define  UCR3_FRAERREN   (1<<11) /* Frame error interrupt enable */
-#define  UCR3_DSR        (1<<10) /* Data set ready */
-#define  UCR3_DCD        (1<<9)  /* Data carrier detect */
-#define  UCR3_RI         (1<<8)  /* Ring indicator */
-#define  UCR3_TIMEOUTEN  (1<<7)  /* Timeout interrupt enable */
-#define  UCR3_RXDSEN	 (1<<6)  /* Receive status interrupt enable */
-#define  UCR3_AIRINTEN   (1<<5)  /* Async IR wake interrupt enable */
-#define  UCR3_AWAKEN	 (1<<4)  /* Async wake interrupt enable */
-#define  UCR3_REF25	 (1<<3)  /* Ref freq 25 MHz */
-#define  UCR3_REF30	 (1<<2)  /* Ref Freq 30 MHz */
-#define  UCR3_INVT	 (1<<1)  /* Inverted Infrared transmission */
-#define  UCR3_BPEN	 (1<<0)  /* Preset registers enable */
-#define  UCR4_CTSTL_32   (32<<10) /* CTS trigger level (32 chars) */
-#define  UCR4_INVR	 (1<<9)  /* Inverted infrared reception */
-#define  UCR4_ENIRI	 (1<<8)  /* Serial infrared interrupt enable */
-#define  UCR4_WKEN	 (1<<7)  /* Wake interrupt enable */
-#define  UCR4_REF16	 (1<<6)  /* Ref freq 16 MHz */
-#define  UCR4_IRSC	 (1<<5) /* IR special case */
-#define  UCR4_TCEN	 (1<<3) /* Transmit complete interrupt enable */
-#define  UCR4_BKEN	 (1<<2) /* Break condition interrupt enable */
-#define  UCR4_OREN	 (1<<1) /* Receiver overrun interrupt enable */
-#define  UCR4_DREN	 (1<<0) /* Recv data ready interrupt enable */
-#define  UFCR_RXTL_SHF   0      /* Receiver trigger level shift */
-#define  UFCR_RFDIV      (7<<7) /* Reference freq divider mask */
-#define  UFCR_TXTL_SHF   10     /* Transmitter trigger level shift */
-#define  USR1_PARITYERR  (1<<15) /* Parity error interrupt flag */
-#define  USR1_RTSS	 (1<<14) /* RTS pin status */
-#define  USR1_TRDY	 (1<<13) /* Transmitter ready interrupt/dma flag */
-#define  USR1_RTSD	 (1<<12) /* RTS delta */
-#define  USR1_ESCF	 (1<<11) /* Escape seq interrupt flag */
-#define  USR1_FRAMERR    (1<<10) /* Frame error interrupt flag */
-#define  USR1_RRDY       (1<<9)	/* Receiver ready interrupt/dma flag */
-#define  USR1_TIMEOUT    (1<<7)	/* Receive timeout interrupt status */
-#define  USR1_RXDS	 (1<<6)	/* Receiver idle interrupt flag */
-#define  USR1_AIRINT	 (1<<5)	/* Async IR wake interrupt flag */
-#define  USR1_AWAKE	 (1<<4)	/* Aysnc wake interrupt flag */
-#define  USR2_ADET	 (1<<15) /* Auto baud rate detect complete */
-#define  USR2_TXFE	 (1<<14) /* Transmit buffer FIFO empty */
-#define  USR2_DTRF	 (1<<13) /* DTR edge interrupt flag */
-#define  USR2_IDLE	 (1<<12) /* Idle condition */
-#define  USR2_IRINT	 (1<<8)	/* Serial infrared interrupt flag */
-#define  USR2_WAKE	 (1<<7)	/* Wake */
-#define  USR2_RTSF	 (1<<4)	/* RTS edge interrupt flag */
-#define  USR2_TXDC	 (1<<3)	/* Transmitter complete */
-#define  USR2_BRCD	 (1<<2)	/* Break condition */
-#define  USR2_ORE        (1<<1)	/* Overrun error */
-#define  USR2_RDR        (1<<0)	/* Recv data ready */
-#define  UTS_FRCPERR	 (1<<13) /* Force parity error */
-#define  UTS_LOOP        (1<<12) /* Loop tx and rx */
-#define  UTS_TXEMPTY	 (1<<6)	/* TxFIFO empty */
-#define  UTS_RXEMPTY	 (1<<5)	/* RxFIFO empty */
-#define  UTS_TXFULL	 (1<<4)	/* TxFIFO full */
-#define  UTS_RXFULL	 (1<<3)	/* RxFIFO full */
-#define  UTS_SOFTRST	 (1<<0)	/* Software reset */
-
-/* General purpose timers registers */
-#define TCTL1   __REG(IMX_TIM1_BASE)
-#define TPRER1  __REG(IMX_TIM1_BASE + 0x4)
-#define TCMP1   __REG(IMX_TIM1_BASE + 0x8)
-#define TCR1    __REG(IMX_TIM1_BASE + 0xc)
-#define TCN1    __REG(IMX_TIM1_BASE + 0x10)
-#define TSTAT1  __REG(IMX_TIM1_BASE + 0x14)
-#define TCTL2   __REG(IMX_TIM2_BASE)
-#define TPRER2  __REG(IMX_TIM2_BASE + 0x4)
-#define TCMP2   __REG(IMX_TIM2_BASE + 0x8)
-#define TCR2    __REG(IMX_TIM2_BASE + 0xc)
-#define TCN2    __REG(IMX_TIM2_BASE + 0x10)
-#define TSTAT2  __REG(IMX_TIM2_BASE + 0x14)
-
-/* General purpose timers bitfields */
-#define TCTL_SWR       (1<<15) /* Software reset */
-#define TCTL_FRR       (1<<8)  /* Freerun / restart */
-#define TCTL_CAP       (3<<6)  /* Capture Edge */
-#define TCTL_OM        (1<<5)  /* output mode */
-#define TCTL_IRQEN     (1<<4)  /* interrupt enable */
-#define TCTL_CLKSOURCE (7<<1)  /* Clock source */
-#define TCTL_TEN       (1)     /* Timer enable */
-#define TPRER_PRES     (0xff)  /* Prescale */
-#define TSTAT_CAPT     (1<<1)  /* Capture event */
-#define TSTAT_COMP     (1)     /* Compare event */
-
-#endif				/* _IMX_REGS_H */
diff --git a/arch/arm/include/asm/arch-ixp/ixp425.h b/arch/arm/include/asm/arch-ixp/ixp425.h
deleted file mode 100644
index 2114437..0000000
--- a/arch/arm/include/asm/arch-ixp/ixp425.h
+++ /dev/null
@@ -1,543 +0,0 @@
-/*
- * include/asm-arm/arch-ixp425/ixp425.h
- *
- * Register definitions for IXP425
- *
- * Copyright (C) 2002 Intel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-
-#ifndef _ASM_ARM_IXP425_H_
-#define _ASM_ARM_IXP425_H_
-
-#define BIT(x)	(1<<(x))
-
-/* FIXME: Only this does work for u-boot... find out why... [RS] */
-#define UBOOT_REG_FIX 1
-#ifdef UBOOT_REG_FIX
-# undef	io_p2v
-# undef __REG
-# ifndef __ASSEMBLY__
-#  define io_p2v(PhAdd)    (PhAdd)
-#  define __REG(x)	(*((volatile u32 *)io_p2v(x)))
-#  define __REG2(x,y)	(*(volatile u32 *)((u32)&__REG(x) + (y)))
-# else
-#  define __REG(x) (x)
-# endif
-#endif /* UBOOT_REG_FIX */
-
-/*
- *
- * IXP425 Memory map:
- *
- * Phy		Phy Size	Map Size	Virt		Description
- * =========================================================================
- *
- * 0x00000000	0x10000000					SDRAM 1
- *
- * 0x10000000	0x10000000					SDRAM 2
- *
- * 0x20000000	0x10000000					SDRAM 3
- *
- * 0x30000000	0x10000000					SDRAM 4
- *
- * The above four are aliases to the same memory location  (0x00000000)
- *
- * 0x48000000	 0x4000000					PCI Memory
- *
- * 0x50000000	0x10000000			Not Mapped	EXP BUS
- *
- * 0x6000000	0x00004000	    0x4000	0xFFFEB000	QMgr
- *
- * 0xC0000000	     0x100	    0x1000	0xFFFDD000	PCI CFG
- *
- * 0xC4000000	     0x100          0x1000	0xFFFDE000	EXP CFG
- *
- * 0xC8000000	    0xC000          0xC000	0xFFFDF000	PERIPHERAL
- *
- * 0xCC000000	     0x100	    0x1000	Not Mapped	SDRAM CFG
- */
-
-/*
- * SDRAM
- */
-#define IXP425_SDRAM_BASE		(0x00000000)
-#define IXP425_SDRAM_BASE_ALT		(0x10000000)
-
-
-/*
- * PCI Configuration space
- */
-#define IXP425_PCI_CFG_BASE_PHYS	(0xC0000000)
-#define IXP425_PCI_CFG_REGION_SIZE	(0x00001000)
-
-/*
- * Expansion BUS Configuration registers
- */
-#define IXP425_EXP_CFG_BASE_PHYS	(0xC4000000)
-#define IXP425_EXP_CFG_REGION_SIZE	(0x00001000)
-
-/*
- * Peripheral space
- */
-#define IXP425_PERIPHERAL_BASE_PHYS	(0xC8000000)
-#define IXP425_PERIPHERAL_REGION_SIZE	(0x0000C000)
-
-/*
- * SDRAM configuration registers
- */
-#define IXP425_SDRAM_CFG_BASE_PHYS	(0xCC000000)
-
-/*
- * Q Manager space .. not static mapped
- */
-#define IXP425_QMGR_BASE_PHYS		(0x60000000)
-#define IXP425_QMGR_REGION_SIZE		(0x00004000)
-
-/*
- * Expansion BUS
- *
- * Expansion Bus 'lives' at either base1 or base 2 depending on the value of
- * Exp Bus config registers:
- *
- * Setting bit 31 of IXP425_EXP_CFG0 puts SDRAM at zero,
- * and The expansion bus to IXP425_EXP_BUS_BASE2
- */
-#define IXP425_EXP_BUS_BASE1_PHYS	(0x00000000)
-#define IXP425_EXP_BUS_BASE2_PHYS	(0x50000000)
-
-#define IXP425_EXP_BUS_BASE_PHYS	IXP425_EXP_BUS_BASE2_PHYS
-
-#define IXP425_EXP_BUS_REGION_SIZE	(0x08000000)
-#define IXP425_EXP_BUS_CSX_REGION_SIZE	(0x01000000)
-
-#define IXP425_EXP_BUS_CS0_BASE_PHYS	(IXP425_EXP_BUS_BASE2_PHYS + 0x00000000)
-#define IXP425_EXP_BUS_CS1_BASE_PHYS	(IXP425_EXP_BUS_BASE2_PHYS + 0x01000000)
-#define IXP425_EXP_BUS_CS2_BASE_PHYS	(IXP425_EXP_BUS_BASE2_PHYS + 0x02000000)
-#define IXP425_EXP_BUS_CS3_BASE_PHYS	(IXP425_EXP_BUS_BASE2_PHYS + 0x03000000)
-#define IXP425_EXP_BUS_CS4_BASE_PHYS	(IXP425_EXP_BUS_BASE2_PHYS + 0x04000000)
-#define IXP425_EXP_BUS_CS5_BASE_PHYS	(IXP425_EXP_BUS_BASE2_PHYS + 0x05000000)
-#define IXP425_EXP_BUS_CS6_BASE_PHYS	(IXP425_EXP_BUS_BASE2_PHYS + 0x06000000)
-#define IXP425_EXP_BUS_CS7_BASE_PHYS	(IXP425_EXP_BUS_BASE2_PHYS + 0x07000000)
-
-#define IXP425_FLASH_WRITABLE	(0x2)
-#define IXP425_FLASH_DEFAULT	(0xbcd23c40)
-#define IXP425_FLASH_WRITE	(0xbcd23c42)
-
-#define IXP425_EXP_CS0_OFFSET	0x00
-#define IXP425_EXP_CS1_OFFSET   0x04
-#define IXP425_EXP_CS2_OFFSET   0x08
-#define IXP425_EXP_CS3_OFFSET   0x0C
-#define IXP425_EXP_CS4_OFFSET   0x10
-#define IXP425_EXP_CS5_OFFSET   0x14
-#define IXP425_EXP_CS6_OFFSET   0x18
-#define IXP425_EXP_CS7_OFFSET   0x1C
-#define IXP425_EXP_CFG0_OFFSET	0x20
-#define IXP425_EXP_CFG1_OFFSET	0x24
-#define IXP425_EXP_CFG2_OFFSET	0x28
-#define IXP425_EXP_CFG3_OFFSET	0x2C
-
-/*
- * Expansion Bus Controller registers.
- */
-#ifndef __ASSEMBLY__
-#define IXP425_EXP_REG(x) ((volatile u32 *)(IXP425_EXP_CFG_BASE_PHYS+(x)))
-#else
-#define IXP425_EXP_REG(x) (IXP425_EXP_CFG_BASE_PHYS+(x))
-#endif
-
-#define IXP425_EXP_CS0      IXP425_EXP_REG(IXP425_EXP_CS0_OFFSET)
-#define IXP425_EXP_CS1      IXP425_EXP_REG(IXP425_EXP_CS1_OFFSET)
-#define IXP425_EXP_CS2      IXP425_EXP_REG(IXP425_EXP_CS2_OFFSET)
-#define IXP425_EXP_CS3      IXP425_EXP_REG(IXP425_EXP_CS3_OFFSET)
-#define IXP425_EXP_CS4      IXP425_EXP_REG(IXP425_EXP_CS4_OFFSET)
-#define IXP425_EXP_CS5      IXP425_EXP_REG(IXP425_EXP_CS5_OFFSET)
-#define IXP425_EXP_CS6      IXP425_EXP_REG(IXP425_EXP_CS6_OFFSET)
-#define IXP425_EXP_CS7      IXP425_EXP_REG(IXP425_EXP_CS7_OFFSET)
-
-#define IXP425_EXP_CFG0     IXP425_EXP_REG(IXP425_EXP_CFG0_OFFSET)
-#define IXP425_EXP_CFG1     IXP425_EXP_REG(IXP425_EXP_CFG1_OFFSET)
-#define IXP425_EXP_CFG2     IXP425_EXP_REG(IXP425_EXP_CFG2_OFFSET)
-#define IXP425_EXP_CFG3     IXP425_EXP_REG(IXP425_EXP_CFG3_OFFSET)
-
-/*
- * SDRAM Controller registers.
- */
-#define IXP425_SDR_CONFIG_OFFSET	0x00
-#define IXP425_SDR_REFRESH_OFFSET	0x04
-#define IXP425_SDR_IR_OFFSET		0x08
-
-#define IXP425_SDRAM_REG(x)	(IXP425_SDRAM_CFG_BASE_PHYS+(x))
-
-#define IXP425_SDR_CONFIG	IXP425_SDRAM_REG(IXP425_SDR_CONFIG_OFFSET)
-#define IXP425_SDR_REFRESH	IXP425_SDRAM_REG(IXP425_SDR_REFRESH_OFFSET)
-#define IXP425_SDR_IR		IXP425_SDRAM_REG(IXP425_SDR_IR_OFFSET)
-
-/*
- * UART registers
- */
-#define IXP425_UART1		0
-#define IXP425_UART2		0x1000
-
-#define IXP425_UART_RBR_OFFSET	0x00
-#define IXP425_UART_THR_OFFSET	0x00
-#define IXP425_UART_DLL_OFFSET	0x00
-#define IXP425_UART_IER_OFFSET	0x04
-#define IXP425_UART_DLH_OFFSET	0x04
-#define IXP425_UART_IIR_OFFSET	0x08
-#define IXP425_UART_FCR_OFFSET	0x00
-#define IXP425_UART_LCR_OFFSET	0x0c
-#define IXP425_UART_MCR_OFFSET	0x10
-#define IXP425_UART_LSR_OFFSET	0x14
-#define IXP425_UART_MSR_OFFSET	0x18
-#define IXP425_UART_SPR_OFFSET	0x1c
-#define IXP425_UART_ISR_OFFSET	0x20
-
-#define IXP425_UART_CFG_BASE_PHYS	(0xc8000000)
-
-#define RBR(x)		__REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_RBR_OFFSET)
-#define THR(x)		__REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_THR_OFFSET)
-#define DLL(x)		__REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_DLL_OFFSET)
-#define IER(x)		__REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_IER_OFFSET)
-#define DLH(x)		__REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_DLH_OFFSET)
-#define IIR(x)		__REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_IIR_OFFSET)
-#define FCR(x)		__REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_FCR_OFFSET)
-#define LCR(x)		__REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_LCR_OFFSET)
-#define MCR(x)		__REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_MCR_OFFSET)
-#define LSR(x)		__REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_LSR_OFFSET)
-#define MSR(x)		__REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_MSR_OFFSET)
-#define SPR(x)		__REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_SPR_OFFSET)
-#define ISR(x)		__REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_ISR_OFFSET)
-
-#define IER_DMAE	(1 << 7)	/* DMA Requests Enable */
-#define IER_UUE		(1 << 6)	/* UART Unit Enable */
-#define IER_NRZE	(1 << 5)	/* NRZ coding Enable */
-#define IER_RTIOE	(1 << 4)	/* Receiver Time Out Interrupt Enable */
-#define IER_MIE		(1 << 3)	/* Modem Interrupt Enable */
-#define IER_RLSE	(1 << 2)	/* Receiver Line Status Interrupt Enable */
-#define IER_TIE		(1 << 1)	/* Transmit Data request Interrupt Enable */
-#define IER_RAVIE	(1 << 0)	/* Receiver Data Available Interrupt Enable */
-
-#define IIR_FIFOES1	(1 << 7)	/* FIFO Mode Enable Status */
-#define IIR_FIFOES0	(1 << 6)	/* FIFO Mode Enable Status */
-#define IIR_TOD		(1 << 3)	/* Time Out Detected */
-#define IIR_IID2	(1 << 2)	/* Interrupt Source Encoded */
-#define IIR_IID1	(1 << 1)	/* Interrupt Source Encoded */
-#define IIR_IP		(1 << 0)	/* Interrupt Pending (active low) */
-
-#define FCR_ITL2	(1 << 7)	/* Interrupt Trigger Level */
-#define FCR_ITL1	(1 << 6)	/* Interrupt Trigger Level */
-#define FCR_RESETTF	(1 << 2)	/* Reset Transmitter FIFO */
-#define FCR_RESETRF	(1 << 1)	/* Reset Receiver FIFO */
-#define FCR_TRFIFOE	(1 << 0)	/* Transmit and Receive FIFO Enable */
-#define FCR_ITL_1	(0)
-#define FCR_ITL_8	(FCR_ITL1)
-#define FCR_ITL_16	(FCR_ITL2)
-#define FCR_ITL_32	(FCR_ITL2|FCR_ITL1)
-
-#define LCR_DLAB	(1 << 7)	/* Divisor Latch Access Bit */
-#define LCR_SB		(1 << 6)	/* Set Break */
-#define LCR_STKYP	(1 << 5)	/* Sticky Parity */
-#define LCR_EPS		(1 << 4)	/* Even Parity Select */
-#define LCR_PEN		(1 << 3)	/* Parity Enable */
-#define LCR_STB		(1 << 2)	/* Stop Bit */
-#define LCR_WLS1	(1 << 1)	/* Word Length Select */
-#define LCR_WLS0	(1 << 0)	/* Word Length Select */
-
-#define LSR_FIFOE	(1 << 7)	/* FIFO Error Status */
-#define LSR_TEMT	(1 << 6)	/* Transmitter Empty */
-#define LSR_TDRQ	(1 << 5)	/* Transmit Data Request */
-#define LSR_BI		(1 << 4)	/* Break Interrupt */
-#define LSR_FE		(1 << 3)	/* Framing Error */
-#define LSR_PE		(1 << 2)	/* Parity Error */
-#define LSR_OE		(1 << 1)	/* Overrun Error */
-#define LSR_DR		(1 << 0)	/* Data Ready */
-
-#define MCR_LOOP	(1 << 4)	*/
-#define MCR_OUT2	(1 << 3)	/* force MSR_DCD in loopback mode */
-#define MCR_OUT1	(1 << 2)	/* force MSR_RI in loopback mode */
-#define MCR_RTS		(1 << 1)	/* Request to Send */
-#define MCR_DTR		(1 << 0)	/* Data Terminal Ready */
-
-#define MSR_DCD		(1 << 7)	/* Data Carrier Detect */
-#define MSR_RI		(1 << 6)	/* Ring Indicator */
-#define MSR_DSR		(1 << 5)	/* Data Set Ready */
-#define MSR_CTS		(1 << 4)	/* Clear To Send */
-#define MSR_DDCD	(1 << 3)	/* Delta Data Carrier Detect */
-#define MSR_TERI	(1 << 2)	/* Trailing Edge Ring Indicator */
-#define MSR_DDSR	(1 << 1)	/* Delta Data Set Ready */
-#define MSR_DCTS	(1 << 0)	/* Delta Clear To Send */
-
-#define IXP425_CONSOLE_UART_BASE_PHYS IXP425_UART1_BASE_PHYS
-/*
- * Peripheral Space Registers
- */
-#define IXP425_UART1_BASE_PHYS	(IXP425_PERIPHERAL_BASE_PHYS + 0x0000)
-#define IXP425_UART2_BASE_PHYS	(IXP425_PERIPHERAL_BASE_PHYS + 0x1000)
-#define IXP425_PMU_BASE_PHYS	(IXP425_PERIPHERAL_BASE_PHYS + 0x2000)
-#define IXP425_INTC_BASE_PHYS	(IXP425_PERIPHERAL_BASE_PHYS + 0x3000)
-#define IXP425_GPIO_BASE_PHYS	(IXP425_PERIPHERAL_BASE_PHYS + 0x4000)
-#define IXP425_TIMER_BASE_PHYS	(IXP425_PERIPHERAL_BASE_PHYS + 0x5000)
-#define IXP425_NPEA_BASE_PHYS	(IXP425_PERIPHERAL_BASE_PHYS + 0x6000)
-#define IXP425_NPEB_BASE_PHYS	(IXP425_PERIPHERAL_BASE_PHYS + 0x7000)
-#define IXP425_NPEC_BASE_PHYS	(IXP425_PERIPHERAL_BASE_PHYS + 0x8000)
-#define IXP425_EthA_BASE_PHYS	(IXP425_PERIPHERAL_BASE_PHYS + 0x9000)
-#define IXP425_EthB_BASE_PHYS	(IXP425_PERIPHERAL_BASE_PHYS + 0xA000)
-#define IXP425_USB_BASE_PHYS	(IXP425_PERIPHERAL_BASE_PHYS + 0xB000)
-
-/*
- * UART Register Definitions , Offsets only as there are 2 UARTS.
- *   IXP425_UART1_BASE , IXP425_UART2_BASE.
- */
-
-#undef  UART_NO_RX_INTERRUPT
-
-#define IXP425_UART_XTAL        14745600
-
-/*
- * Constants to make it easy to access  Interrupt Controller registers
- */
-#define IXP425_ICPR_OFFSET	0x00 /* Interrupt Status */
-#define IXP425_ICMR_OFFSET	0x04 /* Interrupt Enable */
-#define IXP425_ICLR_OFFSET	0x08 /* Interrupt IRQ/FIQ Select */
-#define IXP425_ICIP_OFFSET      0x0C /* IRQ Status */
-#define IXP425_ICFP_OFFSET	0x10 /* FIQ Status */
-#define IXP425_ICHR_OFFSET	0x14 /* Interrupt Priority */
-#define IXP425_ICIH_OFFSET	0x18 /* IRQ Highest Pri Int */
-#define IXP425_ICFH_OFFSET	0x1C /* FIQ Highest Pri Int */
-
-#define N_IRQS			32
-#define IXP425_TIMER_2_IRQ	11
-
-/*
- * Interrupt Controller Register Definitions.
- */
-#ifndef __ASSEMBLY__
-#define IXP425_INTC_REG(x) ((volatile u32 *)(IXP425_INTC_BASE_PHYS+(x)))
-#else
-#define IXP425_INTC_REG(x) (IXP425_INTC_BASE_PHYS+(x))
-#endif
-
-#define IXP425_ICPR     IXP425_INTC_REG(IXP425_ICPR_OFFSET)
-#define IXP425_ICMR     IXP425_INTC_REG(IXP425_ICMR_OFFSET)
-#define IXP425_ICLR     IXP425_INTC_REG(IXP425_ICLR_OFFSET)
-#define IXP425_ICIP     IXP425_INTC_REG(IXP425_ICIP_OFFSET)
-#define IXP425_ICFP     IXP425_INTC_REG(IXP425_ICFP_OFFSET)
-#define IXP425_ICHR     IXP425_INTC_REG(IXP425_ICHR_OFFSET)
-#define IXP425_ICIH     IXP425_INTC_REG(IXP425_ICIH_OFFSET)
-#define IXP425_ICFH     IXP425_INTC_REG(IXP425_ICFH_OFFSET)
-
-/*
- * Constants to make it easy to access GPIO registers
- */
-#define IXP425_GPIO_GPOUTR_OFFSET       0x00
-#define IXP425_GPIO_GPOER_OFFSET        0x04
-#define IXP425_GPIO_GPINR_OFFSET        0x08
-#define IXP425_GPIO_GPISR_OFFSET        0x0C
-#define IXP425_GPIO_GPIT1R_OFFSET	0x10
-#define IXP425_GPIO_GPIT2R_OFFSET	0x14
-#define IXP425_GPIO_GPCLKR_OFFSET	0x18
-#define IXP425_GPIO_GPDBSELR_OFFSET	0x1C
-
-/*
- * GPIO Register Definitions.
- * [Only perform 32bit reads/writes]
- */
-#define IXP425_GPIO_REG(x) ((volatile u32 *)(IXP425_GPIO_BASE_PHYS+(x)))
-
-#define IXP425_GPIO_GPOUTR	IXP425_GPIO_REG(IXP425_GPIO_GPOUTR_OFFSET)
-#define IXP425_GPIO_GPOER       IXP425_GPIO_REG(IXP425_GPIO_GPOER_OFFSET)
-#define IXP425_GPIO_GPINR       IXP425_GPIO_REG(IXP425_GPIO_GPINR_OFFSET)
-#define IXP425_GPIO_GPISR       IXP425_GPIO_REG(IXP425_GPIO_GPISR_OFFSET)
-#define IXP425_GPIO_GPIT1R      IXP425_GPIO_REG(IXP425_GPIO_GPIT1R_OFFSET)
-#define IXP425_GPIO_GPIT2R      IXP425_GPIO_REG(IXP425_GPIO_GPIT2R_OFFSET)
-#define IXP425_GPIO_GPCLKR      IXP425_GPIO_REG(IXP425_GPIO_GPCLKR_OFFSET)
-#define IXP425_GPIO_GPDBSELR    IXP425_GPIO_REG(IXP425_GPIO_GPDBSELR_OFFSET)
-
-/*
- * Macros to make it easy to access the GPIO registers
- */
-#define GPIO_OUTPUT_ENABLE(line)	*IXP425_GPIO_GPOER &= ~(1 << (line))
-#define GPIO_OUTPUT_DISABLE(line)	*IXP425_GPIO_GPOER |= (1 << (line))
-#define GPIO_OUTPUT_SET(line)		*IXP425_GPIO_GPOUTR |= (1 << (line))
-#define GPIO_OUTPUT_CLEAR(line)		*IXP425_GPIO_GPOUTR &= ~(1 << (line))
-#define GPIO_INT_ACT_LOW_SET(line)	*IXP425_GPIO_GPIT1R = \
-		(*IXP425_GPIO_GPIT1R & ~(0x7 << (line * 3))) | (0x1 << (line * 3))
-
-/*
- * Constants to make it easy to access Timer Control/Status registers
- */
-#define IXP425_OSTS_OFFSET	0x00  /* Continious TimeStamp */
-#define IXP425_OST1_OFFSET	0x04  /* Timer 1 Timestamp */
-#define IXP425_OSRT1_OFFSET	0x08  /* Timer 1 Reload */
-#define IXP425_OST2_OFFSET	0x0C  /* Timer 2 Timestamp */
-#define IXP425_OSRT2_OFFSET	0x10  /* Timer 2 Reload */
-#define IXP425_OSWT_OFFSET	0x14  /* Watchdog Timer */
-#define IXP425_OSWE_OFFSET	0x18  /* Watchdog Enable */
-#define IXP425_OSWK_OFFSET	0x1C  /* Watchdog Key */
-#define IXP425_OSST_OFFSET	0x20  /* Timer Status */
-
-/*
- * Operating System Timer Register Definitions.
- */
-
-#ifndef __ASSEMBLY__
-#define IXP425_TIMER_REG(x) ((volatile u32 *)(IXP425_TIMER_BASE_PHYS+(x)))
-#else
-#define IXP425_TIMER_REG(x) (IXP425_TIMER_BASE_PHYS+(x))
-#endif
-
-#if 0 /* test-only: also defined in npe/include/... */
-#define IXP425_OSTS	IXP425_TIMER_REG(IXP425_OSTS_OFFSET)
-#endif
-#define IXP425_OST1	IXP425_TIMER_REG(IXP425_OST1_OFFSET)
-#define IXP425_OSRT1	IXP425_TIMER_REG(IXP425_OSRT1_OFFSET)
-#define IXP425_OST2	IXP425_TIMER_REG(IXP425_OST2_OFFSET)
-#define IXP425_OSRT2	IXP425_TIMER_REG(IXP425_OSRT2_OFFSET)
-#define IXP425_OSWT	IXP425_TIMER_REG(IXP425_OSWT_OFFSET)
-#define IXP425_OSWE	IXP425_TIMER_REG(IXP425_OSWE_OFFSET)
-#define IXP425_OSWK	IXP425_TIMER_REG(IXP425_OSWK_OFFSET)
-#define IXP425_OSST	IXP425_TIMER_REG(IXP425_OSST_OFFSET)
-
-/*
- * Timer register values and bit definitions
- */
-#define IXP425_OST_ENABLE              BIT(0)
-#define IXP425_OST_ONE_SHOT            BIT(1)
-/* Low order bits of reload value ignored */
-#define IXP425_OST_RELOAD_MASK         (0x3)
-#define IXP425_OST_DISABLED            (0x0)
-#define IXP425_OSST_TIMER_1_PEND       BIT(0)
-#define IXP425_OSST_TIMER_2_PEND       BIT(1)
-#define IXP425_OSST_TIMER_TS_PEND      BIT(2)
-#define IXP425_OSST_TIMER_WDOG_PEND    BIT(3)
-#define IXP425_OSST_TIMER_WARM_RESET   BIT(4)
-
-/*
- * Constants to make it easy to access PCI Control/Status registers
- */
-#define PCI_NP_AD_OFFSET            0x00
-#define PCI_NP_CBE_OFFSET           0x04
-#define PCI_NP_WDATA_OFFSET         0x08
-#define PCI_NP_RDATA_OFFSET         0x0c
-#define PCI_CRP_AD_CBE_OFFSET       0x10
-#define PCI_CRP_WDATA_OFFSET        0x14
-#define PCI_CRP_RDATA_OFFSET        0x18
-#define PCI_CSR_OFFSET              0x1c
-#define PCI_ISR_OFFSET              0x20
-#define PCI_INTEN_OFFSET            0x24
-#define PCI_DMACTRL_OFFSET          0x28
-#define PCI_AHBMEMBASE_OFFSET       0x2c
-#define PCI_AHBIOBASE_OFFSET        0x30
-#define PCI_PCIMEMBASE_OFFSET       0x34
-#define PCI_AHBDOORBELL_OFFSET      0x38
-#define PCI_PCIDOORBELL_OFFSET      0x3C
-#define PCI_ATPDMA0_AHBADDR_OFFSET  0x40
-#define PCI_ATPDMA0_PCIADDR_OFFSET  0x44
-#define PCI_ATPDMA0_LENADDR_OFFSET  0x48
-#define PCI_ATPDMA1_AHBADDR_OFFSET  0x4C
-#define PCI_ATPDMA1_PCIADDR_OFFSET  0x50
-#define PCI_ATPDMA1_LENADDR_OFFSET  0x54
-
-/*
- * PCI Control/Status Registers
- */
-#define IXP425_PCI_CSR(x) ((volatile u32 *)(IXP425_PCI_CFG_BASE_PHYS+(x)))
-
-#define PCI_NP_AD               IXP425_PCI_CSR(PCI_NP_AD_OFFSET)
-#define PCI_NP_CBE              IXP425_PCI_CSR(PCI_NP_CBE_OFFSET)
-#define PCI_NP_WDATA            IXP425_PCI_CSR(PCI_NP_WDATA_OFFSET)
-#define PCI_NP_RDATA            IXP425_PCI_CSR(PCI_NP_RDATA_OFFSET)
-#define PCI_CRP_AD_CBE          IXP425_PCI_CSR(PCI_CRP_AD_CBE_OFFSET)
-#define PCI_CRP_WDATA           IXP425_PCI_CSR(PCI_CRP_WDATA_OFFSET)
-#define PCI_CRP_RDATA           IXP425_PCI_CSR(PCI_CRP_RDATA_OFFSET)
-#define PCI_CSR                 IXP425_PCI_CSR(PCI_CSR_OFFSET)
-#define PCI_ISR                 IXP425_PCI_CSR(PCI_ISR_OFFSET)
-#define PCI_INTEN               IXP425_PCI_CSR(PCI_INTEN_OFFSET)
-#define PCI_DMACTRL             IXP425_PCI_CSR(PCI_DMACTRL_OFFSET)
-#define PCI_AHBMEMBASE          IXP425_PCI_CSR(PCI_AHBMEMBASE_OFFSET)
-#define PCI_AHBIOBASE           IXP425_PCI_CSR(PCI_AHBIOBASE_OFFSET)
-#define PCI_PCIMEMBASE          IXP425_PCI_CSR(PCI_PCIMEMBASE_OFFSET)
-#define PCI_AHBDOORBELL         IXP425_PCI_CSR(PCI_AHBDOORBELL_OFFSET)
-#define PCI_PCIDOORBELL         IXP425_PCI_CSR(PCI_PCIDOORBELL_OFFSET)
-#define PCI_ATPDMA0_AHBADDR     IXP425_PCI_CSR(PCI_ATPDMA0_AHBADDR_OFFSET)
-#define PCI_ATPDMA0_PCIADDR     IXP425_PCI_CSR(PCI_ATPDMA0_PCIADDR_OFFSET)
-#define PCI_ATPDMA0_LENADDR     IXP425_PCI_CSR(PCI_ATPDMA0_LENADDR_OFFSET)
-#define PCI_ATPDMA1_AHBADDR     IXP425_PCI_CSR(PCI_ATPDMA1_AHBADDR_OFFSET)
-#define PCI_ATPDMA1_PCIADDR     IXP425_PCI_CSR(PCI_ATPDMA1_PCIADDR_OFFSET)
-#define PCI_ATPDMA1_LENADDR     IXP425_PCI_CSR(PCI_ATPDMA1_LENADDR_OFFSET)
-
-/*
- * PCI register values and bit definitions
- */
-
-/* CSR bit definitions */
-#define PCI_CSR_HOST		BIT(0)
-#define PCI_CSR_ARBEN		BIT(1)
-#define PCI_CSR_ADS		BIT(2)
-#define PCI_CSR_PDS		BIT(3)
-#define PCI_CSR_ABE		BIT(4)
-#define PCI_CSR_DBT		BIT(5)
-#define PCI_CSR_ASE		BIT(8)
-#define PCI_CSR_IC		BIT(15)
-
-/* ISR (Interrupt status) Register bit definitions */
-#define PCI_ISR_PSE		BIT(0)
-#define PCI_ISR_PFE		BIT(1)
-#define PCI_ISR_PPE		BIT(2)
-#define PCI_ISR_AHBE		BIT(3)
-#define PCI_ISR_APDC		BIT(4)
-#define PCI_ISR_PADC		BIT(5)
-#define PCI_ISR_ADB		BIT(6)
-#define PCI_ISR_PDB		BIT(7)
-
-/* INTEN (Interrupt Enable) Register bit definitions */
-#define PCI_INTEN_PSE		BIT(0)
-#define PCI_INTEN_PFE		BIT(1)
-#define PCI_INTEN_PPE		BIT(2)
-#define PCI_INTEN_AHBE		BIT(3)
-#define PCI_INTEN_APDC		BIT(4)
-#define PCI_INTEN_PADC		BIT(5)
-#define PCI_INTEN_ADB		BIT(6)
-#define PCI_INTEN_PDB		BIT(7)
-
-/*
- * Shift value for byte enable on NP cmd/byte enable register
- */
-#define IXP425_PCI_NP_CBE_BESL	4
-
-/*
- * PCI commands supported by NP access unit
- */
-#define NP_CMD_IOREAD		0x2
-#define NP_CMD_IOWRITE		0x3
-#define NP_CMD_CONFIGREAD	0xa
-#define NP_CMD_CONFIGWRITE	0xb
-#define NP_CMD_MEMREAD		0x6
-#define	NP_CMD_MEMWRITE		0x7
-
-#if 0
-#ifndef __ASSEMBLY__
-extern int ixp425_pci_read(u32 addr, u32 cmd, u32* data);
-extern int ixp425_pci_write(u32 addr, u32 cmd, u32 data);
-extern void ixp425_pci_init(void *);
-#endif
-#endif
-
-/*
- * Constants for CRP access into local config space
- */
-#define CRP_AD_CBE_BESL         20
-#define CRP_AD_CBE_WRITE        BIT(16)
-
-/*
- * Clock Speed Definitions.
- */
-#define IXP425_PERIPHERAL_BUS_CLOCK (66) /* 66Mhzi APB BUS   */
-
-
-#endif
diff --git a/arch/arm/include/asm/arch-ixp/ixp425pci.h b/arch/arm/include/asm/arch-ixp/ixp425pci.h
deleted file mode 100644
index 9ea3319..0000000
--- a/arch/arm/include/asm/arch-ixp/ixp425pci.h
+++ /dev/null
@@ -1,312 +0,0 @@
-/*
- * IXP PCI Init
- * (C) Copyright 2004 eslab.whut.edu.cn
- * Yue Hu(huyue_whut@yahoo.com.cn), Ligong Xue(lgxue@hotmail.com)
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef _IXP425PCI_H_
-#define _IXP425PCI_H_
-
-#define TRUE	1
-#define FALSE	0
-#define OK	0
-#define ERROR	-1
-#define BOOL	int
-
-#define IXP425_PCI_MAX_BAR_PER_FUNC  6
-#define IXP425_PCI_MAX_BAR (IXP425_PCI_MAX_BAR_PER_FUNC * \
-			    IXP425_PCI_MAX_FUNC_ON_BUS)
-
-enum PciBarId
-{
-	CSR_BAR=0,
-	IO_BAR,
-	SD_BAR,
-	NO_BAR
-};
-
-/*Base address register descriptor*/
-typedef struct
-{
-	unsigned int size;
-	unsigned int address;
-} PciBar;
-
-typedef struct
-{
-	unsigned int bus;
-	unsigned int device;
-	unsigned int func;
-	unsigned int irq;
-	BOOL error;
-	unsigned short vendor_id;
-	unsigned short device_id;
-	/*We need an extra entry in this array for dummy placeholder*/
-	PciBar bar[IXP425_PCI_MAX_BAR_PER_FUNC + 1];
-} PciDevice;
-
-/* Mask definitions*/
-#define IXP425_PCI_TOP_WORD_OF_LONG_MASK	0xffff0000
-#define IXP425_PCI_TOP_BYTE_OF_LONG_MASK	0xff000000
-#define IXP425_PCI_BOTTOM_WORD_OF_LONG_MASK	0x0000ffff
-#define IXP425_PCI_BOTTOM_TRIBYTES_OF_LONG_MASK 0x00ffffff
-#define IXP425_PCI_BOTTOM_NIBBLE_OF_LONG_MASK	0x0000000f
-#define IXP425_PCI_MAX_UINT32			0xffffffff
-
-
-#define IXP425_PCI_BAR_QUERY			0xffffffff
-
-#define IXP425_PCI_BAR_MEM_BASE 0x100000
-#define IXP425_PCI_BAR_IO_BASE	0x000000
-
-/*define the maximum number of bus segments - we support a single segment*/
-#define IXP425_PCI_MAX_BUS  1
-/*define the maximum number of cards per bus segment*/
-#define IXP425_PCI_MAX_DEV  4
-/*define the maximum number of functions per device*/
-#define IXP425_PCI_MAX_FUNC 8
-/* define the maximum number of separate functions that we can
-   potentially have on the bus*/
-#define IXP425_PCI_MAX_FUNC_ON_BUS (1+ IXP425_PCI_MAX_FUNC *	\
-				    IXP425_PCI_MAX_DEV *	\
-				    IXP425_PCI_MAX_BUS)
-/*define the maximum number of BARs per function*/
-#define IXP425_PCI_MAX_BAR_PER_FUNC  6
-#define IXP425_PCI_MAX_BAR (IXP425_PCI_MAX_BAR_PER_FUNC *	\
-			    IXP425_PCI_MAX_FUNC_ON_BUS)
-
-#define PCI_NP_CBE_BESL	 (4)
-#define PCI_NP_AD_FUNCSL (8)
-
-#define REG_WRITE(b,o,v) (*(volatile unsigned int*)((b+o))=(v))
-#define REG_READ(b,o,v)	 ((v)=(*(volatile unsigned int*)((b+o))))
-
-#define PCI_DELAY	500
-#define USEC_LOOP_COUNT 533
-#define PCI_SETTLE_USEC 200
-#define PCI_MIN_RESET_ASSERT_USEC 2000
-
-/*Register addressing definitions for PCI controller configuration
-  and status registers*/
-
-#define PCI_CSR_BASE (0xC0000000)
-/*
-#define PCI_NP_AD_OFFSET       (0x00)
-#define PCI_NP_CBE_OFFSET      (0x04)
-#define PCI_NP_WDATA_OFFSET    (0x08)
-#define PCI_NP_RDATA_OFFSET    (0x0C)
-#define PCI_CRP_OFFSET	       (0x10)
-#define PCI_CRP_WDATA_OFFSET   (0x14)
-#define PCI_CRP_RDATA_OFFSET   (0x18)
-#define PCI_CSR_OFFSET	       (0x1C)
-#define PCI_ISR_OFFSET	       (0x20)
-#define PCI_INTEN_OFFSET       (0x24)
-#define PCI_DMACTRL_OFFSET     (0x28)
-#define PCI_AHBMEMBASE_OFFSET  (0x2C)
-#define PCI_AHBIOBASE_OFFSET   (0x30)
-#define PCI_PCIMEMBASE_OFFSET  (0x34)
-#define PCI_AHBDOORBELL_OFFSET (0x38)
-#define PCI_PCIDOORBELL_OFFSET (0x3C)
-#define PCI_ATPDMA0_AHBADDR    (0x40)
-#define PCI_ATPDMA0_PCIADDR    (0x44)
-#define PCI_ATPDMA0_LENADDR    (0x48)
-#define PCI_ATPDMA1_AHBADDR    (0x4C)
-#define PCI_ATPDMA1_PCIADDR    (0x50)
-#define PCI_ATPDMA1_LENADDR    (0x54)
-#define PCI_PTADMA0_AHBADDR    (0x58)
-#define PCI_PTADMA0_PCIADDR    (0x5C)
-#define PCI_PTADMA0_LENADDR    (0x60)
-#define PCI_PTADMA1_AHBADDR    (0x64)
-#define PCI_PTADMA1_PCIADDR    (0x68)
-#define PCI_PTADMA1_LENADDR    (0x6C)
-*/
-/*Non prefetch registers bit definitions*/
-/*
-#define NP_CMD_INTACK	   (0x0)
-#define NP_CMD_SPECIAL	   (0x1)
-#define NP_CMD_IOREAD	   (0x2)
-#define NP_CMD_IOWRITE	   (0x3)
-#define NP_CMD_MEMREAD	   (0x6)
-#define NP_CMD_MEMWRITE	   (0x7)
-#define NP_CMD_CONFIGREAD  (0xa)
-#define NP_CMD_CONFIGWRITE (0xb)
-*/
-
-/*define the default setting of the AHB memory base reg*/
-#define IXP425_PCI_AHBMEMBASE_DEFAULT 0x00010203
-#define IXP425_PCI_AHBIOBASE_DEFAULT  0x0
-#define IXP425_PCI_PCIMEMBASE_DEFAULT 0x0
-
-/*define the default settings for the controller's BARs*/
-#ifdef IXP425_PCI_SIMPLE_MAPPING
-#define IXP425_PCI_BAR_0_DEFAULT 0x00000000
-#define IXP425_PCI_BAR_1_DEFAULT 0x01000000
-#define IXP425_PCI_BAR_2_DEFAULT 0x02000000
-#define IXP425_PCI_BAR_3_DEFAULT 0x03000000
-#define IXP425_PCI_BAR_4_DEFAULT 0x00000000
-#define IXP425_PCI_BAR_5_DEFAULT 0x00000000
-#else
-#define IXP425_PCI_BAR_0_DEFAULT 0x40000000
-#define IXP425_PCI_BAR_1_DEFAULT 0x41000000
-#define IXP425_PCI_BAR_2_DEFAULT 0x42000000
-#define IXP425_PCI_BAR_3_DEFAULT 0x43000000
-#define IXP425_PCI_BAR_4_DEFAULT 0x00000000
-#define IXP425_PCI_BAR_5_DEFAULT 0x00000000
-#endif
-
-/*Configuration Port register bit definitions*/
-#define PCI_CRP_WRITE BIT(16)
-
-/*ISR (Interrupt status) Register bit definitions*/
-#define PCI_ISR_PSE   BIT(0)
-#define PCI_ISR_PFE   BIT(1)
-#define PCI_ISR_PPE   BIT(2)
-#define PCI_ISR_AHBE  BIT(3)
-#define PCI_ISR_APDC  BIT(4)
-#define PCI_ISR_PADC  BIT(5)
-#define PCI_ISR_ADB   BIT(6)
-#define PCI_ISR_PDB   BIT(7)
-
-/*INTEN (Interrupt Enable) Register bit definitions*/
-#define PCI_INTEN_PSE	BIT(0)
-#define PCI_INTEN_PFE	BIT(1)
-#define PCI_INTEN_PPE	BIT(2)
-#define PCI_INTEN_AHBE	BIT(3)
-#define PCI_INTEN_APDC	BIT(4)
-#define PCI_INTEN_PADC	BIT(5)
-#define PCI_INTEN_ADB	BIT(6)
-#define PCI_INTEN_PDB	BIT(7)
-
-/*PCI configuration regs.*/
-
-#define PCI_CFG_VENDOR_ID	0x00
-#define PCI_CFG_DEVICE_ID	0x02
-#define PCI_CFG_COMMAND		0x04
-#define PCI_CFG_STATUS		0x06
-#define PCI_CFG_REVISION	0x08
-#define PCI_CFG_PROGRAMMING_IF	0x09
-#define PCI_CFG_SUBCLASS	0x0a
-#define PCI_CFG_CLASS		0x0b
-#define PCI_CFG_CACHE_LINE_SIZE 0x0c
-#define PCI_CFG_LATENCY_TIMER	0x0d
-#define PCI_CFG_HEADER_TYPE	0x0e
-#define PCI_CFG_BIST		0x0f
-#define PCI_CFG_BASE_ADDRESS_0	0x10
-#define PCI_CFG_BASE_ADDRESS_1	0x14
-#define PCI_CFG_BASE_ADDRESS_2	0x18
-#define PCI_CFG_BASE_ADDRESS_3	0x1c
-#define PCI_CFG_BASE_ADDRESS_4	0x20
-#define PCI_CFG_BASE_ADDRESS_5	0x24
-#define PCI_CFG_CIS		0x28
-#define PCI_CFG_SUB_VENDOR_ID	0x2c
-#define PCI_CFG_SUB_SYSTEM_ID	0x2e
-#define PCI_CFG_EXPANSION_ROM	0x30
-#define PCI_CFG_RESERVED_0	0x34
-#define PCI_CFG_RESERVED_1	0x38
-#define PCI_CFG_DEV_INT_LINE	0x3c
-#define PCI_CFG_DEV_INT_PIN	0x3d
-#define PCI_CFG_MIN_GRANT	0x3e
-#define PCI_CFG_MAX_LATENCY	0x3f
-#define PCI_CFG_SPECIAL_USE	0x41
-#define PCI_CFG_MODE		0x43
-
-/*Specify the initial command we send to PCI devices*/
-#define INITIAL_PCI_CMD (PCI_CMD_IO_ENABLE	   \
-			 | PCI_CMD_MEM_ENABLE	   \
-			 | PCI_CMD_MASTER_ENABLE   \
-			 | PCI_CMD_WI_ENABLE)
-
-/*define the sub vendor and subsystem to be used */
-#define IXP425_PCI_SUB_VENDOR_SYSTEM 0x00000000
-
-#define PCI_IRQ_LINES		4
-
-#define PCI_CMD_IO_ENABLE	0x0001	/* IO access enable */
-#define PCI_CMD_MEM_ENABLE	0x0002	/* memory access enable */
-#define PCI_CMD_MASTER_ENABLE	0x0004	/* bus master enable */
-#define PCI_CMD_MON_ENABLE	0x0008	/* monitor special cycles enable */
-#define PCI_CMD_WI_ENABLE	0x0010	/* write and invalidate enable */
-#define PCI_CMD_SNOOP_ENABLE	0x0020	/* palette snoop enable */
-#define PCI_CMD_PERR_ENABLE	0x0040	/* parity error enable */
-#define PCI_CMD_WC_ENABLE	0x0080	/* wait cycle enable */
-#define PCI_CMD_SERR_ENABLE	0x0100	/* system error enable */
-#define PCI_CMD_FBTB_ENABLE	0x0200	/* fast back to back enable */
-
-
-/*CSR Register bit definitions*/
-#define PCI_CSR_HOST  BIT(0)
-#define PCI_CSR_ARBEN BIT(1)
-#define PCI_CSR_ADS   BIT(2)
-#define PCI_CSR_PDS   BIT(3)
-#define PCI_CSR_ABE   BIT(4)
-#define PCI_CSR_DBT   BIT(5)
-#define PCI_CSR_ASE   BIT(8)
-#define PCI_CSR_IC    BIT(15)
-
-/*Configuration command bit definitions*/
-#define PCI_CFG_CMD_IOAE BIT(0)
-#define PCI_CFG_CMD_MAE	 BIT(1)
-#define PCI_CFG_CMD_BME	 BIT(2)
-#define PCI_CFG_CMD_MWIE BIT(4)
-#define PCI_CFG_CMD_SER	 BIT(8)
-#define PCI_CFG_CMD_FBBE BIT(9)
-#define PCI_CFG_CMD_MDPE BIT(24)
-#define PCI_CFG_CMD_STA	 BIT(27)
-#define PCI_CFG_CMD_RTA	 BIT(28)
-#define PCI_CFG_CMD_RMA	 BIT(29)
-#define PCI_CFG_CMD_SSE	 BIT(30)
-#define PCI_CFG_CMD_DPE	 BIT(31)
-
-/*DMACTRL DMA Control and status Register*/
-#define PCI_DMACTRL_APDCEN  BIT(0)
-#define PCI_DMACTRL_APDC0   BIT(4)
-#define PCI_DMACTRL_APDE0   BIT(5)
-#define PCI_DMACTRL_APDC1   BIT(6)
-#define PCI_DMACTRL_APDE1   BIT(7)
-#define PCI_DMACTRL_PADCEN  BIT(8)
-#define PCI_DMACTRL_PADC0   BIT(12)
-#define PCI_DMACTRL_PADE0   BIT(13)
-#define PCI_DMACTRL_PADC1   BIT(14)
-#define PCI_DMACTRL_PADE1   BIT(15)
-
-/* GPIO related register */
-#undef IXP425_GPIO_GPOUTR
-#undef IXP425_GPIO_GPOER
-#undef IXP425_GPIO_GPINR
-#undef IXP425_GPIO_GPISR
-#undef IXP425_GPIO_GPIT1R
-#undef IXP425_GPIO_GPIT2R
-#undef IXP425_GPIO_GPCLKR
-
-#define IXP425_GPIO_GPOUTR	0xC8004000
-#define IXP425_GPIO_GPOER	0xC8004004
-#define IXP425_GPIO_GPINR	0xC8004008
-#define IXP425_GPIO_GPISR	0xC800400C
-#define IXP425_GPIO_GPIT1R	0xC8004010
-#define IXP425_GPIO_GPIT2R	0xC8004014
-#define IXP425_GPIO_GPCLKR	0xC8004018
-
-#define READ_GPIO_REG(addr,val) \
-		(val) = *((volatile int *)(addr));
-#define WRITE_GPIO_REG(addr,val) \
-		*((volatile int *)(addr)) = (val);
-
-#endif
diff --git a/arch/arm/include/asm/arch-kirkwood/config.h b/arch/arm/include/asm/arch-kirkwood/config.h
deleted file mode 100644
index 71ba464..0000000
--- a/arch/arm/include/asm/arch-kirkwood/config.h
+++ /dev/null
@@ -1,145 +0,0 @@
-/*
- * (C) Copyright 2011
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Lei Wen <leiwen@marvell.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-/*
- * This file should be included in board config header file.
- *
- * It supports common definitions for Kirkwood platform
- */
-
-#ifndef _KW_CONFIG_H
-#define _KW_CONFIG_H
-
-#if defined (CONFIG_KW88F6281)
-#include <asm/arch/kw88f6281.h>
-#elif defined (CONFIG_KW88F6192)
-#include <asm/arch/kw88f6192.h>
-#else
-#error "SOC Name not defined"
-#endif /* CONFIG_KW88F6281 */
-
-#define CONFIG_ARM926EJS	1	/* Basic Architecture */
-
-#define CONFIG_MD5	/* get_random_hex on krikwood needs MD5 support */
-#define CONFIG_KIRKWOOD_EGIGA_INIT	/* Enable GbePort0/1 for kernel */
-#define CONFIG_KIRKWOOD_RGMII_PAD_1V8	/* Set RGMII Pad voltage to 1.8V */
-#define CONFIG_KIRKWOOD_PCIE_INIT       /* Enable PCIE Port0 for kernel */
-
-/*
- * By default kwbimage.cfg from board specific folder is used
- * If for some board, different configuration file need to be used,
- * CONFIG_SYS_KWD_CONFIG should be defined in board specific header file
- */
-#ifndef CONFIG_SYS_KWD_CONFIG
-#define	CONFIG_SYS_KWD_CONFIG	$(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage.cfg
-#endif /* CONFIG_SYS_KWD_CONFIG */
-
-/* Kirkwood has 2k of Security SRAM, use it for SP */
-#define CONFIG_SYS_INIT_SP_ADDR		0xC8012000
-#define CONFIG_NR_DRAM_BANKS_MAX	2
-
-#define CONFIG_I2C_MVTWSI_BASE	KW_TWSI_BASE
-#define MV_UART_CONSOLE_BASE	KW_UART0_BASE
-#define MV_SATA_BASE		KW_SATA_BASE
-#define MV_SATA_PORT0_OFFSET	KW_SATA_PORT0_OFFSET
-#define MV_SATA_PORT1_OFFSET	KW_SATA_PORT1_OFFSET
-
-/*
- * NAND configuration
- */
-#ifdef CONFIG_CMD_NAND
-#define CONFIG_NAND_KIRKWOOD
-#define CONFIG_SYS_NAND_BASE		0xD8000000	/* MV_DEFADR_NANDF */
-#define NAND_ALLOW_ERASE_ALL		1
-#endif
-
-/*
- * SPI Flash configuration
- */
-#ifdef CONFIG_CMD_SF
-#define CONFIG_HARD_SPI			1
-#define CONFIG_KIRKWOOD_SPI		1
-#define CONFIG_ENV_SPI_BUS		0
-#define CONFIG_ENV_SPI_CS		0
-#define CONFIG_ENV_SPI_MAX_HZ		50000000	/*50Mhz */
-#endif
-
-/*
- * Ethernet Driver configuration
- */
-#ifdef CONFIG_CMD_NET
-#define CONFIG_CMD_MII
-#define CONFIG_NETCONSOLE	/* include NetConsole support   */
-#define CONFIG_NET_MULTI	/* specify more that one ports available */
-#define CONFIG_MII		/* expose smi ove miiphy interface */
-#define CONFIG_MVGBE		/* Enable Marvell Gbe Controller Driver */
-#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN	/* detect link using phy */
-#define CONFIG_ENV_OVERWRITE	/* ethaddr can be reprogrammed */
-#define CONFIG_RESET_PHY_R	/* use reset_phy() to init mv8831116 PHY */
-#endif /* CONFIG_CMD_NET */
-
-/*
- * USB/EHCI
- */
-#ifdef CONFIG_CMD_USB
-#define CONFIG_USB_EHCI_KIRKWOOD
-#define CONFIG_EHCI_IS_TDI
-#endif /* CONFIG_CMD_USB */
-
-/*
- * IDE Support on SATA ports
- */
-#ifdef CONFIG_CMD_IDE
-#define __io
-#define CONFIG_CMD_EXT2
-#define CONFIG_MVSATA_IDE
-#define CONFIG_IDE_PREINIT
-#define CONFIG_MVSATA_IDE_USE_PORT1
-/* Needs byte-swapping for ATA data register */
-#define CONFIG_IDE_SWAP_IO
-/* Data, registers and alternate blocks are at the same offset */
-#define CONFIG_SYS_ATA_DATA_OFFSET	(0x0100)
-#define CONFIG_SYS_ATA_REG_OFFSET	(0x0100)
-#define CONFIG_SYS_ATA_ALT_OFFSET	(0x0100)
-/* Each 8-bit ATA register is aligned to a 4-bytes address */
-#define CONFIG_SYS_ATA_STRIDE		4
-/* Controller supports 48-bits LBA addressing */
-#define CONFIG_LBA48
-/* CONFIG_CMD_IDE requires some #defines for ATA registers */
-#define CONFIG_SYS_IDE_MAXBUS		2
-#define CONFIG_SYS_IDE_MAXDEVICE	2
-/* ATA registers base is at SATA controller base */
-#define CONFIG_SYS_ATA_BASE_ADDR	MV_SATA_BASE
-#endif /* CONFIG_CMD_IDE */
-
-/*
- * I2C related stuff
- */
-#ifdef CONFIG_CMD_I2C
-#define CONFIG_I2C_MVTWSI
-#define CONFIG_SYS_I2C_SLAVE		0x0
-#define CONFIG_SYS_I2C_SPEED		100000
-#endif
-
-#endif /* _KW_CONFIG_H */
diff --git a/arch/arm/include/asm/arch-kirkwood/cpu.h b/arch/arm/include/asm/arch-kirkwood/cpu.h
deleted file mode 100644
index d28c51a..0000000
--- a/arch/arm/include/asm/arch-kirkwood/cpu.h
+++ /dev/null
@@ -1,171 +0,0 @@
-/*
- * (C) Copyright 2009
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-#ifndef _KWCPU_H
-#define _KWCPU_H
-
-#include <asm/system.h>
-
-#ifndef __ASSEMBLY__
-
-#define KWCPU_WIN_CTRL_DATA(size, target, attr, en) (en | (target << 4) \
-			| (attr << 8) | (kw_winctrl_calcsize(size) << 16))
-
-#define KWGBE_PORT_SERIAL_CONTROL1_REG(_x)	\
-		((_x ? KW_EGIGA0_BASE : KW_EGIGA1_BASE) + 0x44c)
-
-#define KW_REG_PCIE_DEVID		(KW_REG_PCIE_BASE + 0x00)
-#define KW_REG_PCIE_REVID		(KW_REG_PCIE_BASE + 0x08)
-#define KW_REG_DEVICE_ID		(KW_MPP_BASE + 0x34)
-#define KW_REG_SYSRST_CNT		(KW_MPP_BASE + 0x50)
-#define SYSRST_CNT_1SEC_VAL		(25*1000000)
-#define KW_REG_MPP_OUT_DRV_REG		(KW_MPP_BASE + 0xE0)
-
-enum memory_bank {
-	BANK0,
-	BANK1,
-	BANK2,
-	BANK3
-};
-
-enum kwcpu_winen {
-	KWCPU_WIN_DISABLE,
-	KWCPU_WIN_ENABLE
-};
-
-enum kwcpu_target {
-	KWCPU_TARGET_RESERVED,
-	KWCPU_TARGET_MEMORY,
-	KWCPU_TARGET_1RESERVED,
-	KWCPU_TARGET_SASRAM,
-	KWCPU_TARGET_PCIE
-};
-
-enum kwcpu_attrib {
-	KWCPU_ATTR_SASRAM = 0x01,
-	KWCPU_ATTR_DRAM_CS0 = 0x0e,
-	KWCPU_ATTR_DRAM_CS1 = 0x0d,
-	KWCPU_ATTR_DRAM_CS2 = 0x0b,
-	KWCPU_ATTR_DRAM_CS3 = 0x07,
-	KWCPU_ATTR_NANDFLASH = 0x2f,
-	KWCPU_ATTR_SPIFLASH = 0x1e,
-	KWCPU_ATTR_BOOTROM = 0x1d,
-	KWCPU_ATTR_PCIE_IO = 0xe0,
-	KWCPU_ATTR_PCIE_MEM = 0xe8
-};
-
-/*
- * Default Device Address MAP BAR values
- */
-#define KW_DEFADR_PCI_MEM	0x90000000
-#define KW_DEFADR_PCI_IO	0xC0000000
-#define KW_DEFADR_PCI_IO_REMAP	0xC0000000
-#define KW_DEFADR_SASRAM	0xC8010000
-#define KW_DEFADR_NANDF		0xD8000000
-#define KW_DEFADR_SPIF		0xE8000000
-#define KW_DEFADR_BOOTROM	0xF8000000
-
-/*
- * read feroceon/sheeva core extra feature register
- * using co-proc instruction
- */
-static inline unsigned int readfr_extra_feature_reg(void)
-{
-	unsigned int val;
-	asm volatile ("mrc p15, 1, %0, c15, c1, 0 @ readfr exfr":"=r"
-			(val)::"cc");
-	return val;
-}
-
-/*
- * write feroceon/sheeva core extra feature register
- * using co-proc instruction
- */
-static inline void writefr_extra_feature_reg(unsigned int val)
-{
-	asm volatile ("mcr p15, 1, %0, c15, c1, 0 @ writefr exfr"::"r"
-			(val):"cc");
-	isb();
-}
-
-/*
- * MBus-L to Mbus Bridge Registers
- * Ref: Datasheet sec:A.3
- */
-struct kwwin_registers {
-	u32 ctrl;
-	u32 base;
-	u32 remap_lo;
-	u32 remap_hi;
-};
-
-/*
- * CPU control and status Registers
- * Ref: Datasheet sec:A.3.2
- */
-struct kwcpu_registers {
-	u32 config;	/*0x20100 */
-	u32 ctrl_stat;	/*0x20104 */
-	u32 rstoutn_mask; /* 0x20108 */
-	u32 sys_soft_rst; /* 0x2010C */
-	u32 ahb_mbus_cause_irq; /* 0x20110 */
-	u32 ahb_mbus_mask_irq; /* 0x20114 */
-	u32 pad1[2];
-	u32 ftdll_config; /* 0x20120 */
-	u32 pad2;
-	u32 l2_cfg;	/* 0x20128 */
-};
-
-/*
- * GPIO Registers
- * Ref: Datasheet sec:A.19
- */
-struct kwgpio_registers {
-	u32 dout;
-	u32 oe;
-	u32 blink_en;
-	u32 din_pol;
-	u32 din;
-	u32 irq_cause;
-	u32 irq_mask;
-	u32 irq_level;
-};
-
-/*
- * functions
- */
-void reset_cpu(unsigned long ignored);
-unsigned char get_random_hex(void);
-unsigned int kw_sdram_bar(enum memory_bank bank);
-unsigned int kw_sdram_bs(enum memory_bank bank);
-int kw_config_adr_windows(void);
-void kw_config_gpio(unsigned int gpp0_oe_val, unsigned int gpp1_oe_val,
-		unsigned int gpp0_oe, unsigned int gpp1_oe);
-int kw_config_mpp(unsigned int mpp0_7, unsigned int mpp8_15,
-		unsigned int mpp16_23, unsigned int mpp24_31,
-		unsigned int mpp32_39, unsigned int mpp40_47,
-		unsigned int mpp48_55);
-unsigned int kw_winctrl_calcsize(unsigned int sizeval);
-#endif /* __ASSEMBLY__ */
-#endif /* _KWCPU_H */
diff --git a/arch/arm/include/asm/arch-kirkwood/gpio.h b/arch/arm/include/asm/arch-kirkwood/gpio.h
deleted file mode 100644
index cd1bc00..0000000
--- a/arch/arm/include/asm/arch-kirkwood/gpio.h
+++ /dev/null
@@ -1,65 +0,0 @@
-/*
- * arch/asm-arm/mach-kirkwood/include/mach/gpio.h
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-/*
- * Based on (mostly copied from) plat-orion based Linux 2.6 kernel driver.
- * Removed kernel level irq handling. Took some macros from kernel to
- * allow build.
- *
- * Dieter Kiermaier dk-arm-linux@gmx.de
- */
-
-#ifndef __KIRKWOOD_GPIO_H
-#define __KIRKWOOD_GPIO_H
-
-/* got from kernel include/linux/bitops.h */
-#define BITS_PER_BYTE 8
-#define BITS_TO_LONGS(nr)	DIV_ROUND_UP(nr, BITS_PER_BYTE * sizeof(long))
-
-#define GPIO_MAX		50
-#define GPIO_OFF(pin)		(((pin) >> 5) ? 0x0040 : 0x0000)
-#define GPIO_OUT(pin)		(KW_GPIO0_BASE + GPIO_OFF(pin) + 0x00)
-#define GPIO_IO_CONF(pin)	(KW_GPIO0_BASE + GPIO_OFF(pin) + 0x04)
-#define GPIO_BLINK_EN(pin)	(KW_GPIO0_BASE + GPIO_OFF(pin) + 0x08)
-#define GPIO_IN_POL(pin)	(KW_GPIO0_BASE + GPIO_OFF(pin) + 0x0c)
-#define GPIO_DATA_IN(pin)	(KW_GPIO0_BASE + GPIO_OFF(pin) + 0x10)
-#define GPIO_EDGE_CAUSE(pin)	(KW_GPIO0_BASE + GPIO_OFF(pin) + 0x14)
-#define GPIO_EDGE_MASK(pin)	(KW_GPIO0_BASE + GPIO_OFF(pin) + 0x18)
-#define GPIO_LEVEL_MASK(pin)	(KW_GPIO0_BASE + GPIO_OFF(pin) + 0x1c)
-
-/*
- * Kirkwood-specific GPIO API
- */
-
-void kw_gpio_set_valid(unsigned pin, int mode);
-int kw_gpio_is_valid(unsigned pin, int mode);
-int kw_gpio_direction_input(unsigned pin);
-int kw_gpio_direction_output(unsigned pin, int value);
-int kw_gpio_get_value(unsigned pin);
-void kw_gpio_set_value(unsigned pin, int value);
-void kw_gpio_set_blink(unsigned pin, int blink);
-void kw_gpio_set_unused(unsigned pin);
-
-#define GPIO_INPUT_OK		(1 << 0)
-#define GPIO_OUTPUT_OK		(1 << 1)
-
-#endif
diff --git a/arch/arm/include/asm/arch-kirkwood/kirkwood.h b/arch/arm/include/asm/arch-kirkwood/kirkwood.h
deleted file mode 100644
index 0104418..0000000
--- a/arch/arm/include/asm/arch-kirkwood/kirkwood.h
+++ /dev/null
@@ -1,81 +0,0 @@
-/*
- * (C) Copyright 2009
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
- *
- * Header file for the Marvell's Feroceon CPU core.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-#ifndef _ASM_ARCH_KIRKWOOD_H
-#define _ASM_ARCH_KIRKWOOD_H
-
-#ifndef __ASSEMBLY__
-#include <asm/types.h>
-#include <asm/io.h>
-#endif /* __ASSEMBLY__ */
-
-#if defined (CONFIG_FEROCEON_88FR131) || defined (CONFIG_SHEEVA_88SV131)
-#include <asm/arch/cpu.h>
-
-/* SOC specific definations */
-#define INTREG_BASE			0xd0000000
-#define KW_REGISTER(x)			(KW_REGS_PHY_BASE + x)
-#define KW_OFFSET_REG			(INTREG_BASE + 0x20080)
-
-/* undocumented registers */
-#define KW_REG_UNDOC_0x1470		(KW_REGISTER(0x1470))
-#define KW_REG_UNDOC_0x1478		(KW_REGISTER(0x1478))
-
-#define KW_TWSI_BASE			(KW_REGISTER(0x11000))
-#define KW_UART0_BASE			(KW_REGISTER(0x12000))
-#define KW_UART1_BASE			(KW_REGISTER(0x12100))
-#define KW_MPP_BASE			(KW_REGISTER(0x10000))
-#define KW_GPIO0_BASE			(KW_REGISTER(0x10100))
-#define KW_GPIO1_BASE			(KW_REGISTER(0x10140))
-#define KW_NANDF_BASE			(KW_REGISTER(0x10418))
-#define KW_SPI_BASE			(KW_REGISTER(0x10600))
-#define KW_CPU_WIN_BASE			(KW_REGISTER(0x20000))
-#define KW_CPU_REG_BASE			(KW_REGISTER(0x20100))
-#define KW_TIMER_BASE			(KW_REGISTER(0x20300))
-#define KW_REG_PCIE_BASE		(KW_REGISTER(0x40000))
-#define KW_USB20_BASE			(KW_REGISTER(0x50000))
-#define KW_EGIGA0_BASE			(KW_REGISTER(0x72000))
-#define KW_EGIGA1_BASE			(KW_REGISTER(0x76000))
-#define KW_SATA_BASE			(KW_REGISTER(0x80000))
-
-/* Kirkwood Sata controller has two ports */
-#define KW_SATA_PORT0_OFFSET		0x2000
-#define KW_SATA_PORT1_OFFSET		0x4000
-
-/* Kirkwood GbE controller has two ports */
-#define MAX_MVGBE_DEVS	2
-#define MVGBE0_BASE	KW_EGIGA0_BASE
-#define MVGBE1_BASE	KW_EGIGA1_BASE
-
-#if defined (CONFIG_KW88F6281)
-#include <asm/arch/kw88f6281.h>
-#elif defined (CONFIG_KW88F6192)
-#include <asm/arch/kw88f6192.h>
-#else
-#error "SOC Name not defined"
-#endif /* CONFIG_KW88F6281 */
-#endif /* CONFIG_FEROCEON_88FR131 */
-#endif /* _ASM_ARCH_KIRKWOOD_H */
diff --git a/arch/arm/include/asm/arch-kirkwood/kw88f6192.h b/arch/arm/include/asm/arch-kirkwood/kw88f6192.h
deleted file mode 100644
index bbb7cee..0000000
--- a/arch/arm/include/asm/arch-kirkwood/kw88f6192.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/*
- * (C) Copyright 2009
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
- *
- * Header file for Feroceon CPU core 88FR131 Based KW88F6192 SOC.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-#ifndef _CONFIG_KW88F6192_H
-#define _CONFIG_KW88F6192_H
-
-/* SOC specific definations */
-#define KW88F6192_REGS_PHYS_BASE	0xf1000000
-#define KW_REGS_PHY_BASE		KW88F6192_REGS_PHYS_BASE
-
-/* TCLK Core Clock defination */
-#define CONFIG_SYS_TCLK	  166000000 /* 166MHz */
-
-#endif /* _CONFIG_KW88F6192_H */
diff --git a/arch/arm/include/asm/arch-kirkwood/kw88f6281.h b/arch/arm/include/asm/arch-kirkwood/kw88f6281.h
deleted file mode 100644
index 80723ea..0000000
--- a/arch/arm/include/asm/arch-kirkwood/kw88f6281.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/*
- * (C) Copyright 2009
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
- *
- * Header file for Feroceon CPU core 88FR131 Based KW88F6281 SOC.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-#ifndef _ASM_ARCH_KW88F6281_H
-#define _ASM_ARCH_KW88F6281_H
-
-/* SOC specific definations */
-#define KW88F6281_REGS_PHYS_BASE	0xf1000000
-#define KW_REGS_PHY_BASE		KW88F6281_REGS_PHYS_BASE
-
-/* TCLK Core Clock defination*/
-#define CONFIG_SYS_TCLK	  200000000 /* 200MHz */
-
-#endif /* _ASM_ARCH_KW88F6281_H */
diff --git a/arch/arm/include/asm/arch-kirkwood/mpp.h b/arch/arm/include/asm/arch-kirkwood/mpp.h
deleted file mode 100644
index b3c090e..0000000
--- a/arch/arm/include/asm/arch-kirkwood/mpp.h
+++ /dev/null
@@ -1,317 +0,0 @@
-/*
- * linux/arch/arm/mach-kirkwood/mpp.h -- Multi Purpose Pins
- *
- * Copyright 2009: Marvell Technology Group Ltd.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-#ifndef __KIRKWOOD_MPP_H
-#define __KIRKWOOD_MPP_H
-
-#define MPP(_num, _sel, _in, _out, _F6180, _F6190, _F6192, _F6281) ( \
-	/* MPP number */		((_num) & 0xff) | \
-	/* MPP select value */		(((_sel) & 0xf) << 8) | \
-	/* may be input signal */	((!!(_in)) << 12) | \
-	/* may be output signal */	((!!(_out)) << 13) | \
-	/* available on F6180 */	((!!(_F6180)) << 14) | \
-	/* available on F6190 */	((!!(_F6190)) << 15) | \
-	/* available on F6192 */	((!!(_F6192)) << 16) | \
-	/* available on F6281 */	((!!(_F6281)) << 17))
-
-#define MPP_NUM(x)	((x) & 0xff)
-#define MPP_SEL(x)	(((x) >> 8) & 0xf)
-
-				/*   num sel  i  o  6180 6190 6192 6281 */
-
-#define MPP_INPUT_MASK		MPP(  0, 0x0, 1, 0, 0,   0,   0,   0    )
-#define MPP_OUTPUT_MASK		MPP(  0, 0x0, 0, 1, 0,   0,   0,   0    )
-
-#define MPP_F6180_MASK		MPP(  0, 0x0, 0, 0, 1,   0,   0,   0    )
-#define MPP_F6190_MASK		MPP(  0, 0x0, 0, 0, 0,   1,   0,   0    )
-#define MPP_F6192_MASK		MPP(  0, 0x0, 0, 0, 0,   0,   1,   0    )
-#define MPP_F6281_MASK		MPP(  0, 0x0, 0, 0, 0,   0,   0,   1    )
-
-#define MPP0_GPIO		MPP(  0, 0x0, 1, 1, 1,   1,   1,   1    )
-#define MPP0_NF_IO2		MPP(  0, 0x1, 1, 1, 1,   1,   1,   1    )
-#define MPP0_SPI_SCn		MPP(  0, 0x2, 0, 1, 1,   1,   1,   1    )
-
-#define MPP1_GPO		MPP(  1, 0x0, 0, 1, 1,   1,   1,   1    )
-#define MPP1_NF_IO3		MPP(  1, 0x1, 1, 1, 1,   1,   1,   1    )
-#define MPP1_SPI_MOSI		MPP(  1, 0x2, 0, 1, 1,   1,   1,   1    )
-
-#define MPP2_GPO		MPP(  2, 0x0, 0, 1, 1,   1,   1,   1    )
-#define MPP2_NF_IO4		MPP(  2, 0x1, 1, 1, 1,   1,   1,   1    )
-#define MPP2_SPI_SCK		MPP(  2, 0x2, 0, 1, 1,   1,   1,   1    )
-
-#define MPP3_GPO		MPP(  3, 0x0, 0, 1, 1,   1,   1,   1    )
-#define MPP3_NF_IO5		MPP(  3, 0x1, 1, 1, 1,   1,   1,   1    )
-#define MPP3_SPI_MISO		MPP(  3, 0x2, 1, 0, 1,   1,   1,   1    )
-
-#define MPP4_GPIO		MPP(  4, 0x0, 1, 1, 1,   1,   1,   1    )
-#define MPP4_NF_IO6		MPP(  4, 0x1, 1, 1, 1,   1,   1,   1    )
-#define MPP4_UART0_RXD		MPP(  4, 0x2, 1, 0, 1,   1,   1,   1    )
-#define MPP4_SATA1_ACTn		MPP(  4, 0x5, 0, 1, 0,   0,   1,   1    )
-#define MPP4_PTP_CLK		MPP(  4, 0xd, 1, 0, 1,   1,   1,   1    )
-
-#define MPP5_GPO		MPP(  5, 0x0, 0, 1, 1,   1,   1,   1    )
-#define MPP5_NF_IO7		MPP(  5, 0x1, 1, 1, 1,   1,   1,   1    )
-#define MPP5_UART0_TXD		MPP(  5, 0x2, 0, 1, 1,   1,   1,   1    )
-#define MPP5_PTP_TRIG_GEN	MPP(  5, 0x4, 0, 1, 1,   1,   1,   1    )
-#define MPP5_SATA0_ACTn		MPP(  5, 0x5, 0, 1, 0,   1,   1,   1    )
-
-#define MPP6_SYSRST_OUTn	MPP(  6, 0x1, 0, 1, 1,   1,   1,   1    )
-#define MPP6_SPI_MOSI		MPP(  6, 0x2, 0, 1, 1,   1,   1,   1    )
-#define MPP6_PTP_TRIG_GEN	MPP(  6, 0x3, 0, 1, 1,   1,   1,   1    )
-
-#define MPP7_GPO		MPP(  7, 0x0, 0, 1, 1,   1,   1,   1    )
-#define MPP7_PEX_RST_OUTn	MPP(  7, 0x1, 0, 1, 1,   1,   1,   1    )
-#define MPP7_SPI_SCn		MPP(  7, 0x2, 0, 1, 1,   1,   1,   1    )
-#define MPP7_PTP_TRIG_GEN	MPP(  7, 0x3, 0, 1, 1,   1,   1,   1    )
-
-#define MPP8_GPIO		MPP(  8, 0x0, 1, 1, 1,    1,  1,   1    )
-#define MPP8_TW_SDA		MPP(  8, 0x1, 1, 1, 1,   1,   1,   1    )
-#define MPP8_UART0_RTS		MPP(  8, 0x2, 0, 1, 1,   1,   1,   1    )
-#define MPP8_UART1_RTS		MPP(  8, 0x3, 0, 1, 1,   1,   1,   1    )
-#define MPP8_MII0_RXERR		MPP(  8, 0x4, 1, 0, 0,   1,   1,   1    )
-#define MPP8_SATA1_PRESENTn	MPP(  8, 0x5, 0, 1, 0,   0,   1,   1    )
-#define MPP8_PTP_CLK		MPP(  8, 0xc, 1, 0, 1,   1,   1,   1    )
-#define MPP8_MII0_COL		MPP(  8, 0xd, 1, 0, 1,   1,   1,   1    )
-
-#define MPP9_GPIO		MPP(  9, 0x0, 1, 1, 1,   1,   1,   1    )
-#define MPP9_TW_SCK		MPP(  9, 0x1, 1, 1, 1,   1,   1,   1    )
-#define MPP9_UART0_CTS		MPP(  9, 0x2, 1, 0, 1,   1,   1,   1    )
-#define MPP9_UART1_CTS		MPP(  9, 0x3, 1, 0, 1,   1,   1,   1    )
-#define MPP9_SATA0_PRESENTn	MPP(  9, 0x5, 0, 1, 0,   1,   1,   1    )
-#define MPP9_PTP_EVENT_REQ	MPP(  9, 0xc, 1, 0, 1,   1,   1,   1    )
-#define MPP9_MII0_CRS		MPP(  9, 0xd, 1, 0, 1,   1,   1,   1    )
-
-#define MPP10_GPO		MPP( 10, 0x0, 0, 1, 1,   1,   1,   1    )
-#define MPP10_SPI_SCK		MPP( 10, 0x2, 0, 1, 1,   1,   1,   1    )
-#define MPP10_UART0_TXD		MPP( 10, 0X3, 0, 1, 1,   1,   1,   1    )
-#define MPP10_SATA1_ACTn	MPP( 10, 0x5, 0, 1, 0,   0,   1,   1    )
-#define MPP10_PTP_TRIG_GEN	MPP( 10, 0xc, 0, 1, 1,   1,   1,   1    )
-
-#define MPP11_GPIO		MPP( 11, 0x0, 1, 1, 1,   1,   1,   1    )
-#define MPP11_SPI_MISO		MPP( 11, 0x2, 1, 0, 1,   1,   1,   1    )
-#define MPP11_UART0_RXD		MPP( 11, 0x3, 1, 0, 1,   1,   1,   1    )
-#define MPP11_PTP_EVENT_REQ	MPP( 11, 0x4, 1, 0, 1,   1,   1,   1    )
-#define MPP11_PTP_TRIG_GEN	MPP( 11, 0xc, 0, 1, 1,   1,   1,   1    )
-#define MPP11_PTP_CLK		MPP( 11, 0xd, 1, 0, 1,   1,   1,   1    )
-#define MPP11_SATA0_ACTn	MPP( 11, 0x5, 0, 1, 0,   1,   1,   1    )
-
-#define MPP12_GPO		MPP( 12, 0x0, 0, 1, 1,   1,   1,   1    )
-#define MPP12_SD_CLK		MPP( 12, 0x1, 0, 1, 1,   1,   1,   1    )
-
-#define MPP13_GPIO		MPP( 13, 0x0, 1, 1, 1,   1,   1,   1    )
-#define MPP13_SD_CMD		MPP( 13, 0x1, 1, 1, 1,   1,   1,   1    )
-#define MPP13_UART1_TXD		MPP( 13, 0x3, 0, 1, 1,   1,   1,   1    )
-
-#define MPP14_GPIO		MPP( 14, 0x0, 1, 1, 1,   1,   1,   1    )
-#define MPP14_SD_D0		MPP( 14, 0x1, 1, 1, 1,   1,   1,   1    )
-#define MPP14_UART1_RXD		MPP( 14, 0x3, 1, 0, 1,   1,   1,   1    )
-#define MPP14_SATA1_PRESENTn	MPP( 14, 0x4, 0, 1, 0,   0,   1,   1    )
-#define MPP14_MII0_COL		MPP( 14, 0xd, 1, 0, 1,   1,   1,   1    )
-
-#define MPP15_GPIO		MPP( 15, 0x0, 1, 1, 1,   1,   1,   1    )
-#define MPP15_SD_D1		MPP( 15, 0x1, 1, 1, 1,   1,   1,   1    )
-#define MPP15_UART0_RTS		MPP( 15, 0x2, 0, 1, 1,   1,   1,   1    )
-#define MPP15_UART1_TXD		MPP( 15, 0x3, 0, 1, 1,   1,   1,   1    )
-#define MPP15_SATA0_ACTn	MPP( 15, 0x4, 0, 1, 0,   1,   1,   1    )
-
-#define MPP16_GPIO		MPP( 16, 0x0, 1, 1, 1,   1,   1,   1    )
-#define MPP16_SD_D2		MPP( 16, 0x1, 1, 1, 1,   1,   1,   1    )
-#define MPP16_UART0_CTS		MPP( 16, 0x2, 1, 0, 1,   1,   1,   1    )
-#define MPP16_UART1_RXD		MPP( 16, 0x3, 1, 0, 1,   1,   1,   1    )
-#define MPP16_SATA1_ACTn	MPP( 16, 0x4, 0, 1, 0,   0,   1,   1    )
-#define MPP16_MII0_CRS		MPP( 16, 0xd, 1, 0, 1,   1,   1,   1    )
-
-#define MPP17_GPIO		MPP( 17, 0x0, 1, 1, 1,   1,   1,   1    )
-#define MPP17_SD_D3		MPP( 17, 0x1, 1, 1, 1,   1,   1,   1    )
-#define MPP17_SATA0_PRESENTn	MPP( 17, 0x4, 0, 1, 0,   1,   1,   1    )
-
-#define MPP18_GPO		MPP( 18, 0x0, 0, 1, 1,   1,   1,   1    )
-#define MPP18_NF_IO0		MPP( 18, 0x1, 1, 1, 1,   1,   1,   1    )
-
-#define MPP19_GPO		MPP( 19, 0x0, 0, 1, 1,   1,   1,   1    )
-#define MPP19_NF_IO1		MPP( 19, 0x1, 1, 1, 1,   1,   1,   1    )
-
-#define MPP20_GPIO		MPP( 20, 0x0, 1, 1, 0,   1,   1,   1    )
-#define MPP20_TSMP0		MPP( 20, 0x1, 1, 1, 0,   0,   1,   1    )
-#define MPP20_TDM_CH0_TX_QL	MPP( 20, 0x2, 0, 1, 0,   0,   1,   1    )
-#define MPP20_GE1_0		MPP( 20, 0x3, 0, 0, 0,   1,   1,   1    )
-#define MPP20_AUDIO_SPDIFI	MPP( 20, 0x4, 1, 0, 0,   0,   1,   1    )
-#define MPP20_SATA1_ACTn	MPP( 20, 0x5, 0, 1, 0,   0,   1,   1    )
-
-#define MPP21_GPIO		MPP( 21, 0x0, 1, 1, 0,   1,   1,   1    )
-#define MPP21_TSMP1		MPP( 21, 0x1, 1, 1, 0,   0,   1,   1    )
-#define MPP21_TDM_CH0_RX_QL	MPP( 21, 0x2, 0, 1, 0,   0,   1,   1    )
-#define MPP21_GE1_1		MPP( 21, 0x3, 0, 0, 0,   1,   1,   1    )
-#define MPP21_AUDIO_SPDIFO	MPP( 21, 0x4, 0, 1, 0,   0,   1,   1    )
-#define MPP21_SATA0_ACTn	MPP( 21, 0x5, 0, 1, 0,   1,   1,   1    )
-
-#define MPP22_GPIO		MPP( 22, 0x0, 1, 1, 0,   1,   1,   1    )
-#define MPP22_TSMP2		MPP( 22, 0x1, 1, 1, 0,   0,   1,   1    )
-#define MPP22_TDM_CH2_TX_QL	MPP( 22, 0x2, 0, 1, 0,   0,   1,   1    )
-#define MPP22_GE1_2		MPP( 22, 0x3, 0, 0, 0,   1,   1,   1    )
-#define MPP22_AUDIO_SPDIFRMKCLK	MPP( 22, 0x4, 0, 1, 0,   0,   1,   1    )
-#define MPP22_SATA1_PRESENTn	MPP( 22, 0x5, 0, 1, 0,   0,   1,   1    )
-
-#define MPP23_GPIO		MPP( 23, 0x0, 1, 1, 0,   1,   1,   1    )
-#define MPP23_TSMP3		MPP( 23, 0x1, 1, 1, 0,   0,   1,   1    )
-#define MPP23_TDM_CH2_RX_QL	MPP( 23, 0x2, 1, 0, 0,   0,   1,   1    )
-#define MPP23_GE1_3		MPP( 23, 0x3, 0, 0, 0,   1,   1,   1    )
-#define MPP23_AUDIO_I2SBCLK	MPP( 23, 0x4, 0, 1, 0,   0,   1,   1    )
-#define MPP23_SATA0_PRESENTn	MPP( 23, 0x5, 0, 1, 0,   1,   1,   1    )
-
-#define MPP24_GPIO		MPP( 24, 0x0, 1, 1, 0,   1,   1,   1    )
-#define MPP24_TSMP4		MPP( 24, 0x1, 1, 1, 0,   0,   1,   1    )
-#define MPP24_TDM_SPI_CS0	DEV( 24, 0x2, 0, 1, 0,   0,   1,   1    )
-#define MPP24_GE1_4		MPP( 24, 0x3, 0, 0, 0,   1,   1,   1    )
-#define MPP24_AUDIO_I2SDO	MPP( 24, 0x4, 0, 1, 0,   0,   1,   1    )
-
-#define MPP25_GPIO		MPP( 25, 0x0, 1, 1, 0,   1,   1,   1    )
-#define MPP25_TSMP5		MPP( 25, 0x1, 1, 1, 0,   0,   1,   1    )
-#define MPP25_TDM_SPI_SCK	MPP( 25, 0x2, 0, 1, 0,   0,   1,   1    )
-#define MPP25_GE1_5		MPP( 25, 0x3, 0, 0, 0,   1,   1,   1    )
-#define MPP25_AUDIO_I2SLRCLK	MPP( 25, 0x4, 0, 1, 0,   0,   1,   1    )
-
-#define MPP26_GPIO		MPP( 26, 0x0, 1, 1, 0,   1,   1,   1    )
-#define MPP26_TSMP6		MPP( 26, 0x1, 1, 1, 0,   0,   1,   1    )
-#define MPP26_TDM_SPI_MISO	MPP( 26, 0x2, 1, 0, 0,   0,   1,   1    )
-#define MPP26_GE1_6		MPP( 26, 0x3, 0, 0, 0,   1,   1,   1    )
-#define MPP26_AUDIO_I2SMCLK	MPP( 26, 0x4, 0, 1, 0,   0,   1,   1    )
-
-#define MPP27_GPIO		MPP( 27, 0x0, 1, 1, 0,   1,   1,   1    )
-#define MPP27_TSMP7		MPP( 27, 0x1, 1, 1, 0,   0,   1,   1    )
-#define MPP27_TDM_SPI_MOSI	MPP( 27, 0x2, 0, 1, 0,   0,   1,   1    )
-#define MPP27_GE1_7		MPP( 27, 0x3, 0, 0, 0,   1,   1,   1    )
-#define MPP27_AUDIO_I2SDI	MPP( 27, 0x4, 1, 0, 0,   0,   1,   1    )
-
-#define MPP28_GPIO		MPP( 28, 0x0, 1, 1, 0,   1,   1,   1    )
-#define MPP28_TSMP8		MPP( 28, 0x1, 1, 1, 0,   0,   1,   1    )
-#define MPP28_TDM_CODEC_INTn	MPP( 28, 0x2, 0, 0, 0,   0,   1,   1    )
-#define MPP28_GE1_8		MPP( 28, 0x3, 0, 0, 0,   1,   1,   1    )
-#define MPP28_AUDIO_EXTCLK	MPP( 28, 0x4, 1, 0, 0,   0,   1,   1    )
-
-#define MPP29_GPIO		MPP( 29, 0x0, 1, 1, 0,   1,   1,   1    )
-#define MPP29_TSMP9		MPP( 29, 0x1, 1, 1, 0,   0,   1,   1    )
-#define MPP29_TDM_CODEC_RSTn	MPP( 29, 0x2, 0, 0, 0,   0,   1,   1    )
-#define MPP29_GE1_9		MPP( 29, 0x3, 0, 0, 0,   1,   1,   1    )
-
-#define MPP30_GPIO		MPP( 30, 0x0, 1, 1, 0,   1,   1,   1    )
-#define MPP30_TSMP10		MPP( 30, 0x1, 1, 1, 0,   0,   1,   1    )
-#define MPP30_TDM_PCLK		MPP( 30, 0x2, 1, 1, 0,   0,   1,   1    )
-#define MPP30_GE1_10		MPP( 30, 0x3, 0, 0, 0,   1,   1,   1    )
-
-#define MPP31_GPIO		MPP( 31, 0x0, 1, 1, 0,   1,   1,   1    )
-#define MPP31_TSMP11		MPP( 31, 0x1, 1, 1, 0,   0,   1,   1    )
-#define MPP31_TDM_FS		MPP( 31, 0x2, 1, 1, 0,   0,   1,   1    )
-#define MPP31_GE1_11		MPP( 31, 0x3, 0, 0, 0,   1,   1,   1    )
-
-#define MPP32_GPIO		MPP( 32, 0x0, 1, 1, 0,   1,   1,   1    )
-#define MPP32_TSMP12		MPP( 32, 0x1, 1, 1, 0,   0,   1,   1    )
-#define MPP32_TDM_DRX		MPP( 32, 0x2, 1, 0, 0,   0,   1,   1    )
-#define MPP32_GE1_12		MPP( 32, 0x3, 0, 0, 0,   1,   1,   1    )
-
-#define MPP33_GPIO		MPP( 33, 0x0, 1, 1, 0,   1,   1,   1    )
-#define MPP33_TDM_DTX		MPP( 33, 0x2, 0, 1, 0,   0,   1,   1    )
-#define MPP33_GE1_13		MPP( 33, 0x3, 0, 0, 0,   1,   1,   1    )
-
-#define MPP34_GPIO		MPP( 34, 0x0, 1, 1, 0,   1,   1,   1    )
-#define MPP34_TDM_SPI_CS1	MPP( 34, 0x2, 0, 1, 0,   0,   1,   1    )
-#define MPP34_GE1_14		MPP( 34, 0x3, 0, 0, 0,   1,   1,   1    )
-
-#define MPP35_GPIO		MPP( 35, 0x0, 1, 1, 1,   1,   1,   1    )
-#define MPP35_TDM_CH0_TX_QL	MPP( 35, 0x2, 0, 1, 0,   0,   1,   1    )
-#define MPP35_GE1_15		MPP( 35, 0x3, 0, 0, 0,   1,   1,   1    )
-#define MPP35_SATA0_ACTn	MPP( 35, 0x5, 0, 1, 0,   1,   1,   1    )
-#define MPP35_MII0_RXERR	MPP( 35, 0xc, 1, 0, 1,   1,   1,   1    )
-
-#define MPP36_GPIO		MPP( 36, 0x0, 1, 1, 1,   0,   0,   1    )
-#define MPP36_TSMP0		MPP( 36, 0x1, 1, 1, 0,   0,   0,   1    )
-#define MPP36_TDM_SPI_CS1	MPP( 36, 0x2, 0, 1, 0,   0,   0,   1    )
-#define MPP36_AUDIO_SPDIFI	MPP( 36, 0x4, 1, 0, 1,   0,   0,   1    )
-
-#define MPP37_GPIO		MPP( 37, 0x0, 1, 1, 1,   0,   0,   1    )
-#define MPP37_TSMP1		MPP( 37, 0x1, 1, 1, 0,   0,   0,   1    )
-#define MPP37_TDM_CH2_TX_QL	MPP( 37, 0x2, 0, 1, 0,   0,   0,   1    )
-#define MPP37_AUDIO_SPDIFO	MPP( 37, 0x4, 0, 1, 1,   0,   0,   1    )
-
-#define MPP38_GPIO		MPP( 38, 0x0, 1, 1, 1,   0,   0,   1    )
-#define MPP38_TSMP2		MPP( 38, 0x1, 1, 1, 0,   0,   0,   1    )
-#define MPP38_TDM_CH2_RX_QL	MPP( 38, 0x2, 0, 1, 0,   0,   0,   1    )
-#define MPP38_AUDIO_SPDIFRMLCLK	MPP( 38, 0x4, 0, 1, 1,   0,   0,   1    )
-
-#define MPP39_GPIO		MPP( 39, 0x0, 1, 1, 1,   0,   0,   1    )
-#define MPP39_TSMP3		MPP( 39, 0x1, 1, 1, 0,   0,   0,   1    )
-#define MPP39_TDM_SPI_CS0	MPP( 39, 0x2, 0, 1, 0,   0,   0,   1    )
-#define MPP39_AUDIO_I2SBCLK	MPP( 39, 0x4, 0, 1, 1,   0,   0,   1    )
-
-#define MPP40_GPIO		MPP( 40, 0x0, 1, 1, 1,   0,   0,   1    )
-#define MPP40_TSMP4		MPP( 40, 0x1, 1, 1, 0,   0,   0,   1    )
-#define MPP40_TDM_SPI_SCK	MPP( 40, 0x2, 0, 1, 0,   0,   0,   1    )
-#define MPP40_AUDIO_I2SDO	MPP( 40, 0x4, 0, 1, 1,   0,   0,   1    )
-
-#define MPP41_GPIO		MPP( 41, 0x0, 1, 1, 1,   0,   0,   1    )
-#define MPP41_TSMP5		MPP( 41, 0x1, 1, 1, 0,   0,   0,   1    )
-#define MPP41_TDM_SPI_MISO	MPP( 41, 0x2, 1, 0, 0,   0,   0,   1    )
-#define MPP41_AUDIO_I2SLRC	MPP( 41, 0x4, 0, 1, 1,   0,   0,   1    )
-
-#define MPP42_GPIO		MPP( 42, 0x0, 1, 1, 1,   0,   0,   1    )
-#define MPP42_TSMP6		MPP( 42, 0x1, 1, 1, 0,   0,   0,   1    )
-#define MPP42_TDM_SPI_MOSI	MPP( 42, 0x2, 0, 1, 0,   0,   0,   1    )
-#define MPP42_AUDIO_I2SMCLK	MPP( 42, 0x4, 0, 1, 1,   0,   0,   1    )
-
-#define MPP43_GPIO		MPP( 43, 0x0, 1, 1, 1,   0,   0,   1    )
-#define MPP43_TSMP7		MPP( 43, 0x1, 1, 1, 0,   0,   0,   1    )
-#define MPP43_TDM_CODEC_INTn	MPP( 43, 0x2, 0, 0, 0,   0,   0,   1    )
-#define MPP43_AUDIO_I2SDI	MPP( 43, 0x4, 1, 0, 1,   0,   0,   1    )
-
-#define MPP44_GPIO		MPP( 44, 0x0, 1, 1, 1,   0,   0,   1    )
-#define MPP44_TSMP8		MPP( 44, 0x1, 1, 1, 0,   0,   0,   1    )
-#define MPP44_TDM_CODEC_RSTn	MPP( 44, 0x2, 0, 0, 0,   0,   0,   1    )
-#define MPP44_AUDIO_EXTCLK	MPP( 44, 0x4, 1, 0, 1,   0,   0,   1    )
-
-#define MPP45_GPIO		MPP( 45, 0x0, 1, 1, 0,   0,   0,   1    )
-#define MPP45_TSMP9		MPP( 45, 0x1, 1, 1, 0,   0,   0,   1    )
-#define MPP45_TDM_PCLK		MPP( 45, 0x2, 1, 1, 0,   0,   0,   1    )
-
-#define MPP46_GPIO		MPP( 46, 0x0, 1, 1, 0,   0,   0,   1    )
-#define MPP46_TSMP10		MPP( 46, 0x1, 1, 1, 0,   0,   0,   1    )
-#define MPP46_TDM_FS		MPP( 46, 0x2, 1, 1, 0,   0,   0,   1    )
-
-#define MPP47_GPIO		MPP( 47, 0x0, 1, 1, 0,   0,   0,   1    )
-#define MPP47_TSMP11		MPP( 47, 0x1, 1, 1, 0,   0,   0,   1    )
-#define MPP47_TDM_DRX		MPP( 47, 0x2, 1, 0, 0,   0,   0,   1    )
-
-#define MPP48_GPIO		MPP( 48, 0x0, 1, 1, 0,   0,   0,   1    )
-#define MPP48_TSMP12		MPP( 48, 0x1, 1, 1, 0,   0,   0,   1    )
-#define MPP48_TDM_DTX		MPP( 48, 0x2, 0, 1, 0,   0,   0,   1    )
-
-#define MPP49_GPIO		MPP( 49, 0x0, 1, 1, 0,   0,   0,   1    )
-#define MPP49_TSMP9		MPP( 49, 0x1, 1, 1, 0,   0,   0,   1    )
-#define MPP49_TDM_CH0_RX_QL	MPP( 49, 0x2, 0, 1, 0,   0,   0,   1    )
-#define MPP49_PTP_CLK		MPP( 49, 0x5, 1, 0, 0,   0,   0,   1    )
-
-#define MPP_MAX			49
-
-void kirkwood_mpp_conf(unsigned int *mpp_list);
-
-#endif
diff --git a/arch/arm/include/asm/arch-kirkwood/spi.h b/arch/arm/include/asm/arch-kirkwood/spi.h
deleted file mode 100644
index 1d5043f..0000000
--- a/arch/arm/include/asm/arch-kirkwood/spi.h
+++ /dev/null
@@ -1,56 +0,0 @@
-/*
- * (C) Copyright 2009
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
- *
- * Derived from drivers/spi/mpc8xxx_spi.c
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-#ifndef __KW_SPI_H__
-#define __KW_SPI_H__
-
-/* SPI Registers on kirkwood SOC */
-struct kwspi_registers {
-	u32 ctrl;	/* 0x10600 */
-	u32 cfg;	/* 0x10604 */
-	u32 dout;	/* 0x10608 */
-	u32 din;	/* 0x1060c */
-	u32 irq_cause;	/* 0x10610 */
-	u32 irq_mask;	/* 0x10614 */
-};
-
-#define KWSPI_CLKPRESCL_MASK	0x1f
-#define KWSPI_CSN_ACT		1 /* Activates serial memory interface */
-#define KWSPI_SMEMRDY		(1 << 1) /* SerMem Data xfer ready */
-#define KWSPI_IRQUNMASK		1 /* unmask SPI interrupt */
-#define KWSPI_IRQMASK		0 /* mask SPI interrupt */
-#define KWSPI_SMEMRDIRQ		1 /* SerMem data xfer ready irq */
-#define KWSPI_XFERLEN_1BYTE	0
-#define KWSPI_XFERLEN_2BYTE	(1 << 5)
-#define KWSPI_XFERLEN_MASK	(1 << 5)
-#define KWSPI_ADRLEN_1BYTE	0
-#define KWSPI_ADRLEN_2BYTE	1 << 8
-#define KWSPI_ADRLEN_3BYTE	2 << 8
-#define KWSPI_ADRLEN_4BYTE	3 << 8
-#define KWSPI_ADRLEN_MASK	3 << 8
-#define KWSPI_TIMEOUT		10000
-
-#endif /* __KW_SPI_H__ */
diff --git a/arch/arm/include/asm/arch-ks8695/platform.h b/arch/arm/include/asm/arch-ks8695/platform.h
deleted file mode 100644
index de20015..0000000
--- a/arch/arm/include/asm/arch-ks8695/platform.h
+++ /dev/null
@@ -1,306 +0,0 @@
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307	 USA
- */
-#ifndef __address_h
-#define __address_h			1
-
-#define KS8695_SDRAM_START	    0x00000000
-#define KS8695_SDRAM_SIZE	    0x01000000
-#define KS8695_MEM_SIZE		    KS8695_SDRAM_SIZE
-#define KS8695_MEM_START	    KS8695_SDRAM_START
-
-#define KS8695_PCMCIA_IO_BASE	    0x03800000
-#define KS8695_PCMCIA_IO_SIZE	    0x00040000
-
-#define KS8695_IO_BASE		    0x03FF0000
-#define KS8695_IO_SIZE		    0x00010000
-
-#define KS8695_SYSTEN_CONFIG	    0x00
-#define KS8695_SYSTEN_BUS_CLOCK	    0x04
-
-#define KS8695_FLASH_START	    0x02800000
-#define KS8695_FLASH_SIZE	    0x00400000
-
-/*i/o control registers offset difinitions*/
-#define KS8695_IO_CTRL0		    0x4000
-#define KS8695_IO_CTRL1		    0x4004
-#define KS8695_IO_CTRL2		    0x4008
-#define KS8695_IO_CTRL3		    0x400C
-
-/*memory control registers offset difinitions*/
-#define KS8695_MEM_CTRL0	    0x4010
-#define KS8695_MEM_CTRL1	    0x4014
-#define KS8695_MEM_CTRL2	    0x4018
-#define KS8695_MEM_CTRL3	    0x401C
-#define KS8695_MEM_GENERAL	    0x4020
-#define KS8695_SDRAM_CTRL0	    0x4030
-#define KS8695_SDRAM_CTRL1	    0x4034
-#define KS8695_SDRAM_GENERAL	    0x4038
-#define KS8695_SDRAM_BUFFER	    0x403C
-#define KS8695_SDRAM_REFRESH	    0x4040
-
-/*WAN control registers offset difinitions*/
-#define KS8695_WAN_DMA_TX	    0x6000
-#define KS8695_WAN_DMA_RX	    0x6004
-#define KS8695_WAN_DMA_TX_START	    0x6008
-#define KS8695_WAN_DMA_RX_START	    0x600C
-#define KS8695_WAN_TX_LIST	    0x6010
-#define KS8695_WAN_RX_LIST	    0x6014
-#define KS8695_WAN_MAC_LOW	    0x6018
-#define KS8695_WAN_MAC_HIGH	    0x601C
-#define KS8695_WAN_MAC_ELOW	    0x6080
-#define KS8695_WAN_MAC_EHIGH	    0x6084
-
-/*LAN control registers offset difinitions*/
-#define KS8695_LAN_DMA_TX	    0x8000
-#define KS8695_LAN_DMA_RX	    0x8004
-#define KS8695_LAN_DMA_TX_START	    0x8008
-#define KS8695_LAN_DMA_RX_START	    0x800C
-#define KS8695_LAN_TX_LIST	    0x8010
-#define KS8695_LAN_RX_LIST	    0x8014
-#define KS8695_LAN_MAC_LOW	    0x8018
-#define KS8695_LAN_MAC_HIGH	    0x801C
-#define KS8695_LAN_MAC_ELOW	    0X8080
-#define KS8695_LAN_MAC_EHIGH	    0X8084
-
-/*HPNA control registers offset difinitions*/
-#define KS8695_HPNA_DMA_TX	    0xA000
-#define KS8695_HPNA_DMA_RX	    0xA004
-#define KS8695_HPNA_DMA_TX_START    0xA008
-#define KS8695_HPNA_DMA_RX_START    0xA00C
-#define KS8695_HPNA_TX_LIST	    0xA010
-#define KS8695_HPNA_RX_LIST	    0xA014
-#define KS8695_HPNA_MAC_LOW	    0xA018
-#define KS8695_HPNA_MAC_HIGH	    0xA01C
-#define KS8695_HPNA_MAC_ELOW	    0xA080
-#define KS8695_HPNA_MAC_EHIGH	    0xA084
-
-/*UART control registers offset difinitions*/
-#define KS8695_UART_RX_BUFFER	    0xE000
-#define KS8695_UART_TX_HOLDING	    0xE004
-
-#define KS8695_UART_FIFO_CTRL	    0xE008
-#define KS8695_UART_FIFO_TRIG01	    0x00
-#define KS8695_UART_FIFO_TRIG04	    0x80
-#define KS8695_UART_FIFO_TXRST	    0x03
-#define KS8695_UART_FIFO_RXRST	    0x02
-#define KS8695_UART_FIFO_FEN	    0x01
-
-#define KS8695_UART_LINE_CTRL	    0xE00C
-#define KS8695_UART_LINEC_BRK	    0x40
-#define KS8695_UART_LINEC_EPS	    0x10
-#define KS8695_UART_LINEC_PEN	    0x08
-#define KS8695_UART_LINEC_STP2	    0x04
-#define KS8695_UART_LINEC_WLEN8	    0x03
-#define KS8695_UART_LINEC_WLEN7	    0x02
-#define KS8695_UART_LINEC_WLEN6	    0x01
-#define KS8695_UART_LINEC_WLEN5	    0x00
-
-#define KS8695_UART_MODEM_CTRL	    0xE010
-#define KS8695_UART_MODEMC_RTS	    0x02
-#define KS8695_UART_MODEMC_DTR	    0x01
-
-#define KS8695_UART_LINE_STATUS	    0xE014
-#define KS8695_UART_LINES_TXFE	    0x20
-#define KS8695_UART_LINES_BE	    0x10
-#define KS8695_UART_LINES_FE	    0x08
-#define KS8695_UART_LINES_PE	    0x04
-#define KS8695_UART_LINES_OE	    0x02
-#define KS8695_UART_LINES_RXFE	    0x01
-#define KS8695_UART_LINES_ANY	    (KS8695_UART_LINES_OE|KS8695_UART_LINES_BE|KS8695_UART_LINES_PE|KS8695_UART_LINES_FE)
-
-#define KS8695_UART_MODEM_STATUS    0xE018
-#define KS8695_UART_MODEM_DCD	    0x80
-#define KS8695_UART_MODEM_DSR	    0x20
-#define KS8695_UART_MODEM_CTS	    0x10
-#define KS8695_UART_MODEM_DDCD	    0x08
-#define KS8695_UART_MODEM_DDSR	    0x02
-#define KS8695_UART_MODEM_DCTS	    0x01
-#define UART8695_MODEM_ANY	    0xFF
-
-#define KS8695_UART_DIVISOR	    0xE01C
-#define KS8695_UART_STATUS	    0xE020
-
-/*Interrupt controlller registers offset difinitions*/
-#define KS8695_INT_CONTL	    0xE200
-#define KS8695_INT_ENABLE	    0xE204
-#define KS8695_INT_ENABLE_MODEM	    0x0800
-#define KS8695_INT_ENABLE_ERR	    0x0400
-#define KS8695_INT_ENABLE_RX	    0x0200
-#define KS8695_INT_ENABLE_TX	    0x0100
-
-#define KS8695_INT_STATUS	    0xE208
-#define KS8695_INT_WAN_PRIORITY	    0xE20C
-#define KS8695_INT_HPNA_PRIORITY    0xE210
-#define KS8695_INT_LAN_PRIORITY	    0xE214
-#define KS8695_INT_TIMER_PRIORITY   0xE218
-#define KS8695_INT_UART_PRIORITY    0xE21C
-#define KS8695_INT_EXT_PRIORITY	    0xE220
-#define KS8695_INT_CHAN_PRIORITY    0xE224
-#define KS8695_INT_BUSERROR_PRO	    0xE228
-#define KS8695_INT_MASK_STATUS	    0xE22C
-#define KS8695_FIQ_PEND_PRIORITY    0xE230
-#define KS8695_IRQ_PEND_PRIORITY    0xE234
-
-/*timer registers offset difinitions*/
-#define KS8695_TIMER_CTRL	    0xE400
-#define KS8695_TIMER1		    0xE404
-#define KS8695_TIMER0		    0xE408
-#define KS8695_TIMER1_PCOUNT	    0xE40C
-#define KS8695_TIMER0_PCOUNT	    0xE410
-
-/*GPIO registers offset difinitions*/
-#define KS8695_GPIO_MODE	    0xE600
-#define KS8695_GPIO_CTRL	    0xE604
-#define KS8695_GPIO_DATA	    0xE608
-
-/*SWITCH registers offset difinitions*/
-#define KS8695_SWITCH_CTRL0	    0xE800
-#define KS8695_SWITCH_CTRL1	    0xE804
-#define KS8695_SWITCH_PORT1	    0xE808
-#define KS8695_SWITCH_PORT2	    0xE80C
-#define KS8695_SWITCH_PORT3	    0xE810
-#define KS8695_SWITCH_PORT4	    0xE814
-#define KS8695_SWITCH_PORT5	    0xE818
-#define KS8695_SWITCH_AUTO0	    0xE81C
-#define KS8695_SWITCH_AUTO1	    0xE820
-#define KS8695_SWITCH_LUE_CTRL	    0xE824
-#define KS8695_SWITCH_LUE_HIGH	    0xE828
-#define KS8695_SWITCH_LUE_LOW	    0xE82C
-#define KS8695_SWITCH_ADVANCED	    0xE830
-
-#define KS8695_SWITCH_LPPM12	    0xE874
-#define KS8695_SWITCH_LPPM34	    0xE878
-
-/*host communication registers difinitions*/
-#define KS8695_DSCP_HIGH	    0xE834
-#define KS8695_DSCP_LOW		    0xE838
-#define KS8695_SWITCH_MAC_HIGH	    0xE83C
-#define KS8695_SWITCH_MAC_LOW	    0xE840
-
-/*miscellaneours registers difinitions*/
-#define KS8695_MANAGE_COUNTER	    0xE844
-#define KS8695_MANAGE_DATA	    0xE848
-#define KS8695_LAN12_POWERMAGR	    0xE84C
-#define KS8695_LAN34_POWERMAGR	    0xE850
-
-#define KS8695_DEVICE_ID	    0xEA00
-#define KS8695_REVISION_ID	    0xEA04
-
-#define KS8695_MISC_CONTROL	    0xEA08
-#define KS8695_WAN_CONTROL	    0xEA0C
-#define KS8695_WAN_POWERMAGR	    0xEA10
-#define KS8695_WAN_PHY_CONTROL	    0xEA14
-#define KS8695_WAN_PHY_STATUS	    0xEA18
-
-/* bus clock definitions*/
-#define KS8695_BUS_CLOCK_125MHZ	    0x0
-#define KS8695_BUS_CLOCK_100MHZ	    0x1
-#define KS8695_BUS_CLOCK_62MHZ	    0x2
-#define KS8695_BUS_CLOCK_50MHZ	    0x3
-#define KS8695_BUS_CLOCK_41MHZ	    0x4
-#define KS8695_BUS_CLOCK_33MHZ	    0x5
-#define KS8695_BUS_CLOCK_31MHZ	    0x6
-#define KS8695_BUS_CLOCK_25MHZ	    0x7
-
-/* -------------------------------------------------------------------------------
- *  definations for IRQ
- * -------------------------------------------------------------------------------*/
-
-#define KS8695_INT_EXT_INT0		       2
-#define KS8695_INT_EXT_INT1		       3
-#define KS8695_INT_EXT_INT2		       4
-#define KS8695_INT_EXT_INT3		       5
-#define KS8695_INT_TIMERINT0		       6
-#define KS8695_INT_TIMERINT1		       7
-#define KS8695_INT_UART_TX		       8
-#define KS8695_INT_UART_RX		       9
-#define KS8695_INT_UART_LINE_ERR	       10
-#define KS8695_INT_UART_MODEMS		       11
-#define KS8695_INT_LAN_STOP_RX		       12
-#define KS8695_INT_LAN_STOP_TX		       13
-#define KS8695_INT_LAN_BUF_RX_STATUS	       14
-#define KS8695_INT_LAN_BUF_TX_STATUS	       15
-#define KS8695_INT_LAN_RX_STATUS	       16
-#define KS8695_INT_LAN_TX_STATUS	       17
-#define KS8695_INT_HPAN_STOP_RX		       18
-#define KS8695_INT_HPNA_STOP_TX		       19
-#define KS8695_INT_HPNA_BUF_RX_STATUS	       20
-#define KS8695_INT_HPNA_BUF_TX_STATUS	       21
-#define KS8695_INT_HPNA_RX_STATUS	       22
-#define KS8695_INT_HPNA_TX_STATUS	       23
-#define KS8695_INT_BUS_ERROR		       24
-#define KS8695_INT_WAN_STOP_RX		       25
-#define KS8695_INT_WAN_STOP_TX		       26
-#define KS8695_INT_WAN_BUF_RX_STATUS	       27
-#define KS8695_INT_WAN_BUF_TX_STATUS	       28
-#define KS8695_INT_WAN_RX_STATUS	       29
-#define KS8695_INT_WAN_TX_STATUS	       30
-
-#define KS8695_INT_UART			       KS8695_INT_UART_TX
-
-/* -------------------------------------------------------------------------------
- *  Interrupt bit positions
- *
- * -------------------------------------------------------------------------------
- */
-
-#define KS8695_INTMASK_EXT_INT0		       ( 1 << KS8695_INT_EXT_INT0 )
-#define KS8695_INTMASK_EXT_INT1		       ( 1 << KS8695_INT_EXT_INT1 )
-#define KS8695_INTMASK_EXT_INT2		       ( 1 << KS8695_INT_EXT_INT2 )
-#define KS8695_INTMASK_EXT_INT3		       ( 1 << KS8695_INT_EXT_INT3 )
-#define KS8695_INTMASK_TIMERINT0	       ( 1 << KS8695_INT_TIMERINT0 )
-#define KS8695_INTMASK_TIMERINT1	       ( 1 << KS8695_INT_TIMERINT1 )
-#define KS8695_INTMASK_UART_TX		       ( 1 << KS8695_INT_UART_TX  )
-#define KS8695_INTMASK_UART_RX		       ( 1 << KS8695_INT_UART_RX  )
-#define KS8695_INTMASK_UART_LINE_ERR	       ( 1 << KS8695_INT_UART_LINE_ERR )
-#define KS8695_INTMASK_UART_MODEMS	       ( 1 << KS8695_INT_UART_MODEMS )
-#define KS8695_INTMASK_LAN_STOP_RX	       ( 1 << KS8695_INT_LAN_STOP_RX )
-#define KS8695_INTMASK_LAN_STOP_TX	       ( 1 << KS8695_INT_LAN_STOP_TX )
-#define KS8695_INTMASK_LAN_BUF_RX_STATUS       ( 1 << KS8695_INT_LAN_BUF_RX_STATUS )
-#define KS8695_INTMASK_LAN_BUF_TX_STATUS       ( 1 << KS8695_INT_LAN_BUF_TX_STATUS )
-#define KS8695_INTMASK_LAN_RX_STATUS	       ( 1 << KS8695_INT_LAN_RX_STATUS )
-#define KS8695_INTMASK_LAN_TX_STATUS	       ( 1 << KS8695_INT_LAN_RX_STATUS )
-#define KS8695_INTMASK_HPAN_STOP_RX	       ( 1 << KS8695_INT_HPAN_STOP_RX )
-#define KS8695_INTMASK_HPNA_STOP_TX	       ( 1 << KS8695_INT_HPNA_STOP_TX )
-#define KS8695_INTMASK_HPNA_BUF_RX_STATUS      ( 1 << KS8695_INT_HPNA_BUF_RX_STATUS )
-#define KS8695_INTMAKS_HPNA_BUF_TX_STATUS      ( 1 << KS8695_INT_HPNA_BUF_TX_STATUS
-#define KS8695_INTMASK_HPNA_RX_STATUS	       ( 1 << KS8695_INT_HPNA_RX_STATUS )
-#define KS8695_INTMASK_HPNA_TX_STATUS	       ( 1 << KS8695_INT_HPNA_TX_STATUS )
-#define KS8695_INTMASK_BUS_ERROR	       ( 1 << KS8695_INT_BUS_ERROR )
-#define KS8695_INTMASK_WAN_STOP_RX	       ( 1 << KS8695_INT_WAN_STOP_RX )
-#define KS8695_INTMASK_WAN_STOP_TX	       ( 1 << KS8695_INT_WAN_STOP_TX )
-#define KS8695_INTMASK_WAN_BUF_RX_STATUS       ( 1 << KS8695_INT_WAN_BUF_RX_STATUS )
-#define KS8695_INTMASK_WAN_BUF_TX_STATUS       ( 1 << KS8695_INT_WAN_BUF_TX_STATUS )
-#define KS8695_INTMASK_WAN_RX_STATUS	       ( 1 << KS8695_INT_WAN_RX_STATUS )
-#define KS8695_INTMASK_WAN_TX_STATUS	       ( 1 << KS8695_INT_WAN_TX_STATUS )
-
-#define KS8695_SC_VALID_INT		       0xFFFFFFFF
-#define MAXIRQNUM			       31
-
-/*
- *  Timer definitions
- *
- *  Use timer 1 & 2
- *  (both run at 25MHz).
- *
- */
-#define TICKS_PER_uSEC			25
-#define mSEC_1				1000
-#define mSEC_10				(mSEC_1 * 10)
-
-#endif
-
-/*	END */
diff --git a/arch/arm/include/asm/arch-lpc2292/hardware.h b/arch/arm/include/asm/arch-lpc2292/hardware.h
deleted file mode 100644
index 5e227e3..0000000
--- a/arch/arm/include/asm/arch-lpc2292/hardware.h
+++ /dev/null
@@ -1,33 +0,0 @@
-#ifndef __ASM_ARCH_HARDWARE_H
-#define __ASM_ARCH_HARDWARE_H
-
-/*
- * Copyright (c) 2004	Cucy Systems (http://www.cucy.com)
- * Curt Brune <curt@cucy.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#if defined(CONFIG_LPC2292)
-#include <asm/arch-lpc2292/lpc2292_registers.h>
-#else
-#error No hardware file defined for this configuration
-#endif
-
-#endif /* __ASM_ARCH_HARDWARE_H */
diff --git a/arch/arm/include/asm/arch-lpc2292/lpc2292_registers.h b/arch/arm/include/asm/arch-lpc2292/lpc2292_registers.h
deleted file mode 100644
index 5715f3e..0000000
--- a/arch/arm/include/asm/arch-lpc2292/lpc2292_registers.h
+++ /dev/null
@@ -1,225 +0,0 @@
-#ifndef __LPC2292_REGISTERS_H
-#define __LPC2292_REGISTERS_H
-
-#include <config.h>
-
-/* Macros for reading/writing registers */
-#define PUT8(reg, value) (*(volatile unsigned char*)(reg) = (value))
-#define PUT16(reg, value) (*(volatile unsigned short*)(reg) = (value))
-#define PUT32(reg, value) (*(volatile unsigned int*)(reg) = (value))
-#define GET8(reg) (*(volatile unsigned char*)(reg))
-#define GET16(reg) (*(volatile unsigned short*)(reg))
-#define GET32(reg) (*(volatile unsigned int*)(reg))
-
-/* External Memory Controller */
-
-#define BCFG0 0xFFE00000	/* 32-bits */
-#define BCFG1 0xFFE00004	/* 32-bits */
-#define BCFG2 0xFFE00008	/* 32-bits */
-#define BCFG3 0xFFE0000c	/* 32-bits */
-
-/* System Control Block */
-
-#define EXTINT   0xE01FC140
-#define EXTWAKE  0xE01FC144
-#define EXTMODE  0xE01FC148
-#define EXTPOLAR 0xE01FC14C
-#define MEMMAP   0xE01FC040
-#define PLLCON   0xE01FC080
-#define PLLCFG   0xE01FC084
-#define PLLSTAT  0xE01FC088
-#define PLLFEED  0xE01FC08C
-#define PCON     0xE01FC0C0
-#define PCONP    0xE01FC0C4
-#define VPBDIV   0xE01FC100
-
-/* Memory Acceleration Module */
-
-#define MAMCR  0xE01FC000
-#define MAMTIM 0xE01FC004
-
-/* Vectored Interrupt Controller */
-
-#define VICIRQStatus    0xFFFFF000
-#define VICFIQStatus    0xFFFFF004
-#define VICRawIntr      0xFFFFF008
-#define VICIntSelect    0xFFFFF00C
-#define VICIntEnable    0xFFFFF010
-#define VICIntEnClr     0xFFFFF014
-#define VICSoftInt      0xFFFFF018
-#define VICSoftIntClear 0xFFFFF01C
-#define VICProtection   0xFFFFF020
-#define VICVectAddr     0xFFFFF030
-#define VICDefVectAddr  0xFFFFF034
-#define VICVectAddr0    0xFFFFF100
-#define VICVectAddr1    0xFFFFF104
-#define VICVectAddr2    0xFFFFF108
-#define VICVectAddr3    0xFFFFF10C
-#define VICVectAddr4    0xFFFFF110
-#define VICVectAddr5    0xFFFFF114
-#define VICVectAddr6    0xFFFFF118
-#define VICVectAddr7    0xFFFFF11C
-#define VICVectAddr8    0xFFFFF120
-#define VICVectAddr9    0xFFFFF124
-#define VICVectAddr10   0xFFFFF128
-#define VICVectAddr11   0xFFFFF12C
-#define VICVectAddr12   0xFFFFF130
-#define VICVectAddr13   0xFFFFF134
-#define VICVectAddr14   0xFFFFF138
-#define VICVectAddr15   0xFFFFF13C
-#define VICVectCntl0    0xFFFFF200
-#define VICVectCntl1	0xFFFFF204
-#define VICVectCntl2	0xFFFFF208
-#define VICVectCntl3	0xFFFFF20C
-#define VICVectCntl4	0xFFFFF210
-#define VICVectCntl5	0xFFFFF214
-#define VICVectCntl6	0xFFFFF218
-#define VICVectCntl7	0xFFFFF21C
-#define VICVectCntl8	0xFFFFF220
-#define VICVectCntl9	0xFFFFF224
-#define VICVectCntl10	0xFFFFF228
-#define VICVectCntl11	0xFFFFF22C
-#define VICVectCntl12	0xFFFFF230
-#define VICVectCntl13	0xFFFFF234
-#define VICVectCntl14	0xFFFFF238
-#define VICVectCntl15	0xFFFFF23C
-
-/* Pin connect block */
-
-#define PINSEL0 0xE002C000	/* 32 bits */
-#define PINSEL1 0xE002C004	/* 32 bits */
-#define PINSEL2 0xE002C014	/* 32 bits */
-
-/* GPIO */
-
-#define IO0PIN 0xE0028000
-#define IO0SET 0xE0028004
-#define IO0DIR 0xE0028008
-#define IO0CLR 0xE002800C
-#define IO1PIN 0xE0028010
-#define IO1SET 0xE0028014
-#define IO1DIR 0xE0028018
-#define IO1CLR 0xE002801C
-#define IO2PIN 0xE0028020
-#define IO2SET 0xE0028024
-#define IO2DIR 0xE0028028
-#define IO2CLR 0xE002802C
-#define IO3PIN 0xE0028030
-#define IO3SET 0xE0028034
-#define IO3DIR 0xE0028038
-#define IO3CLR 0xE002803C
-
-/* Uarts */
-
-#define U0RBR 0xE000C000
-#define U0THR 0xE000C000
-#define U0IER 0xE000C004
-#define U0IIR 0xE000C008
-#define U0FCR 0xE000C008
-#define U0LCR 0xE000C00C
-#define U0LSR 0xE000C014
-#define U0SCR 0xE000C01C
-#define U0DLL 0xE000C000
-#define U0DLM 0xE000C004
-
-#define U1RBR 0xE0010000
-#define U1THR 0xE0010000
-#define U1IER 0xE0010004
-#define U1IIR 0xE0010008
-#define U1FCR 0xE0010008
-#define U1LCR 0xE001000C
-#define U1MCR 0xE0010010
-#define U1LSR 0xE0010014
-#define U1MSR 0xE0010018
-#define U1SCR 0xE001001C
-#define U1DLL 0xE0010000
-#define U1DLM 0xE0010004
-
-/* I2C */
-
-#define I2CONSET 0xE001C000
-#define I2STAT   0xE001C004
-#define I2DAT    0xE001C008
-#define I2ADR    0xE001C00C
-#define I2SCLH   0xE001C010
-#define I2SCLL   0xE001C014
-#define I2CONCLR 0xE001C018
-
-/* SPI */
-
-#define S0SPCR  0xE0020000
-#define S0SPSR  0xE0020004
-#define S0SPDR  0xE0020008
-#define S0SPCCR 0xE002000C
-#define S0SPINT 0xE002001C
-
-#define S1SPCR  0xE0030000
-#define S1SPSR  0xE0030004
-#define S1SPDR  0xE0030008
-#define S1SPCCR 0xE003000C
-#define S1SPINT 0xE003001C
-
-/* CAN controller */
-
-/* skip for now */
-
-/* Timers */
-
-#define T0IR  0xE0004000
-#define T0TCR 0xE0004004
-#define T0TC  0xE0004008
-#define T0PR  0xE000400C
-#define T0PC  0xE0004010
-#define T0MCR 0xE0004014
-#define T0MR0 0xE0004018
-#define T0MR1 0xE000401C
-#define T0MR2 0xE0004020
-#define T0MR3 0xE0004024
-#define T0CCR 0xE0004028
-#define T0CR0 0xE000402C
-#define T0CR1 0xE0004030
-#define T0CR2 0xE0004034
-#define T0CR3 0xE0004038
-#define T0EMR 0xE000403C
-
-#define T1IR  0xE0008000
-#define T1TCR 0xE0008004
-#define T1TC  0xE0008008
-#define T1PR  0xE000800C
-#define T1PC  0xE0008010
-#define T1MCR 0xE0008014
-#define T1MR0 0xE0008018
-#define T1MR1 0xE000801C
-#define T1MR2 0xE0008020
-#define T1MR3 0xE0008024
-#define T1CCR 0xE0008028
-#define T1CR0 0xE000802C
-#define T1CR1 0xE0008030
-#define T1CR2 0xE0008034
-#define T1CR3 0xE0008038
-#define T1EMR 0xE000803C
-
-/* PWM */
-
-/* skip for now */
-
-/* A/D converter */
-
-/* skip for now */
-
-/* Real Time Clock */
-
-/* skip for now */
-
-/* Watchdog */
-
-#define WDMOD  0xE0000000
-#define WDTC   0xE0000004
-#define WDFEED 0xE0000008
-#define WDTV   0xE000000C
-
-/* EmbeddedICE LOGIC */
-
-/* skip for now */
-
-#endif
diff --git a/arch/arm/include/asm/arch-lpc2292/spi.h b/arch/arm/include/asm/arch-lpc2292/spi.h
deleted file mode 100644
index 6ae66e8..0000000
--- a/arch/arm/include/asm/arch-lpc2292/spi.h
+++ /dev/null
@@ -1,82 +0,0 @@
-/*
-    This file defines the interface to the lpc22xx SPI module.
-    Copyright (C) 2006  Embedded Artists AB (www.embeddedartists.com)
-
-    This file may be included in software not adhering to the GPL.
-
-    This program is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 2 of the License, or
-    (at your option) any later version.
-
-    This program is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program; if not, write to the Free Software
-    Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
-*/
-
-#ifndef SPI_H
-#define SPI_H
-
-#include <config.h>
-#include <common.h>
-#include <asm/errno.h>
-#include <asm/arch/hardware.h>
-
-#define SPIF 0x80
-
-#define spi_lock() disable_interrupts();
-#define spi_unlock() enable_interrupts();
-
-extern unsigned long spi_flags;
-extern unsigned char spi_idle;
-
-int spi_init(void);
-
-static inline unsigned char spi_read(void)
-{
-	unsigned char b;
-
-	PUT8(S0SPDR, spi_idle);
-	while (!(GET8(S0SPSR) & SPIF));
-	b = GET8(S0SPDR);
-
-	return b;
-}
-
-static inline void spi_write(unsigned char b)
-{
-	PUT8(S0SPDR, b);
-	while (!(GET8(S0SPSR) & SPIF));
-	GET8(S0SPDR);		/* this will clear the SPIF bit */
-}
-
-static inline void spi_set_clock(unsigned char clk_value)
-{
-	PUT8(S0SPCCR, clk_value);
-}
-
-static inline void spi_set_cfg(unsigned char phase,
-			       unsigned char polarity,
-			       unsigned char lsbf)
-{
-	unsigned char v = 0x20;	/* master bit set */
-
-	if (phase)
-		v |= 0x08;			/* set phase bit */
-	if (polarity) {
-		v |= 0x10;			/* set polarity bit */
-		spi_idle = 0xFF;
-	} else {
-		spi_idle = 0x00;
-	}
-	if (lsbf)
-		v |= 0x40;			/* set lsbf bit */
-
-	PUT8(S0SPCR, v);
-}
-#endif /* SPI_H */
diff --git a/arch/arm/include/asm/arch-mb86r0x/asm-offsets.h b/arch/arm/include/asm/arch-mb86r0x/asm-offsets.h
deleted file mode 100644
index 0bc5279..0000000
--- a/arch/arm/include/asm/arch-mb86r0x/asm-offsets.h
+++ /dev/null
@@ -1,74 +0,0 @@
-/*
- * (C) Copyright 2010
- * Matthias Weisser <weisserm@arcor.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef ASM_OFFSETS_H
-#define ASM_OFFSETS_H
-
-/*
- * Offset definitions for DDR controller
- */
-#define DDR2_DRIC		0x00
-#define DDR2_DRIC1		0x02
-#define DDR2_DRIC2		0x04
-#define DDR2_DRCA		0x06
-#define DDR2_DRCM		0x08
-#define DDR2_DRCST1		0x0a
-#define DDR2_DRCST2		0x0c
-#define DDR2_DRCR		0x0e
-#define DDR2_DRCF		0x20
-#define DDR2_DRASR		0x30
-#define DDR2_DRIMS		0x50
-#define DDR2_DROS		0x60
-#define DDR2_DRIBSODT1		0x64
-#define DDR2_DROABA		0x70
-#define DDR2_DROBS		0x84
-
-/*
- * Offset definitions Chip Control Module
- */
-#define CCNT_CDCRC		0xec
-
-/*
- * Offset definitions clock reset generator
- */
-#define CRG_CRPR		0x00
-#define CRG_CRHA		0x18
-#define CRG_CRPA		0x1c
-#define CRG_CRPB		0x20
-#define CRG_CRHB		0x24
-#define CRG_CRAM		0x28
-
-/*
- * Offset definitions External bus interface
- */
-#define MEMC_MCFMODE0		0x00
-#define MEMC_MCFMODE2		0x08
-#define MEMC_MCFMODE4		0x10
-#define MEMC_MCFTIM0		0x20
-#define MEMC_MCFTIM2		0x28
-#define MEMC_MCFTIM4		0x30
-#define MEMC_MCFAREA0		0x40
-#define MEMC_MCFAREA2		0x48
-#define MEMC_MCFAREA4		0x50
-
-#endif /* ASM_OFFSETS_H */
diff --git a/arch/arm/include/asm/arch-mb86r0x/hardware.h b/arch/arm/include/asm/arch-mb86r0x/hardware.h
deleted file mode 100644
index d1e57c0..0000000
--- a/arch/arm/include/asm/arch-mb86r0x/hardware.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * (C) Copyright 2007
- *
- * Author : Carsten Schneider, mycable GmbH
- *          <cs@mycable.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-#ifndef __ASM_ARCH_HARDWARE_H
-#define __ASM_ARCH_HARDWARE_H
-
-#include <asm/sizes.h>
-#include <asm/arch/mb86r0x.h>
-
-#endif
diff --git a/arch/arm/include/asm/arch-mb86r0x/mb86r0x.h b/arch/arm/include/asm/arch-mb86r0x/mb86r0x.h
deleted file mode 100644
index 36a28b7..0000000
--- a/arch/arm/include/asm/arch-mb86r0x/mb86r0x.h
+++ /dev/null
@@ -1,573 +0,0 @@
-/*
- * (C) Copyright 2007
- *
- * mb86r0x definitions
- *
- * Author : Carsten Schneider, mycable GmbH
- *          <cs@mycable.de>
- *
- * (C) Copyright 2010
- * Matthias Weisser <weisserm@arcor.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef MB86R0X_H
-#define MB86R0X_H
-
-#ifndef __ASSEMBLY__
-
-/* GPIO registers */
-struct mb86r0x_gpio {
-	uint32_t gpdr0;
-	uint32_t gpdr1;
-	uint32_t gpdr2;
-	uint32_t res;
-	uint32_t gpddr0;
-	uint32_t gpddr1;
-	uint32_t gpddr2;
-};
-
-/* PWM registers */
-struct mb86r0x_pwm {
-	uint32_t bcr;
-	uint32_t tpr;
-	uint32_t pr;
-	uint32_t dr;
-	uint32_t cr;
-	uint32_t sr;
-	uint32_t ccr;
-	uint32_t ir;
-};
-
-/* The mb86r0x chip control (CCNT) register set. */
-struct mb86r0x_ccnt {
-	uint32_t ccid;
-	uint32_t csrst;
-	uint32_t pad0[2];
-	uint32_t cist;
-	uint32_t cistm;
-	uint32_t cgpio_ist;
-	uint32_t cgpio_istm;
-	uint32_t cgpio_ip;
-	uint32_t cgpio_im;
-	uint32_t caxi_bw;
-	uint32_t caxi_ps;
-	uint32_t cmux_md;
-	uint32_t cex_pin_st;
-	uint32_t cmlb;
-	uint32_t pad1[1];
-	uint32_t cusb;
-	uint32_t pad2[41];
-	uint32_t cbsc;
-	uint32_t cdcrc;
-	uint32_t cmsr0;
-	uint32_t cmsr1;
-	uint32_t pad3[2];
-};
-
-/* The mb86r0x clock reset generator */
-struct mb86r0x_crg {
-	uint32_t crpr;
-	uint32_t pad0;
-	uint32_t crwr;
-	uint32_t crsr;
-	uint32_t crda;
-	uint32_t crdb;
-	uint32_t crha;
-	uint32_t crpa;
-	uint32_t crpb;
-	uint32_t crhb;
-	uint32_t cram;
-};
-
-/* The mb86r0x timer */
-struct mb86r0x_timer {
-	uint32_t load;
-	uint32_t value;
-	uint32_t control;
-	uint32_t intclr;
-	uint32_t ris;
-	uint32_t mis;
-	uint32_t bgload;
-};
-
-/* mb86r0x gdc display controller */
-struct mb86r0x_gdc_dsp {
-	/* Display settings */
-	uint32_t dcm0;
-	uint16_t pad00;
-	uint16_t htp;
-	uint16_t hdp;
-	uint16_t hdb;
-	uint16_t hsp;
-	uint8_t  hsw;
-	uint8_t  vsw;
-	uint16_t pad01;
-	uint16_t vtr;
-	uint16_t vsp;
-	uint16_t vdp;
-	uint16_t wx;
-	uint16_t wy;
-	uint16_t ww;
-	uint16_t wh;
-
-	/* Layer 0 */
-	uint32_t l0m;
-	uint32_t l0oa;
-	uint32_t l0da;
-	uint16_t l0dx;
-	uint16_t l0dy;
-
-	/* Layer 1 */
-	uint32_t l1m;
-	uint32_t cbda0;
-	uint32_t cbda1;
-	uint32_t pad02;
-
-	/* Layer 2 */
-	uint32_t l2m;
-	uint32_t l2oa0;
-	uint32_t l2da0;
-	uint32_t l2oa1;
-	uint32_t l2da1;
-	uint16_t l2dx;
-	uint16_t l2dy;
-
-	/* Layer 3 */
-	uint32_t l3m;
-	uint32_t l3oa0;
-	uint32_t l3da0;
-	uint32_t l3oa1;
-	uint32_t l3da1;
-	uint16_t l3dx;
-	uint16_t l3dy;
-
-	/* Layer 4 */
-	uint32_t l4m;
-	uint32_t l4oa0;
-	uint32_t l4da0;
-	uint32_t l4oa1;
-	uint32_t l4da1;
-	uint16_t l4dx;
-	uint16_t l4dy;
-
-	/* Layer 5 */
-	uint32_t l5m;
-	uint32_t l5oa0;
-	uint32_t l5da0;
-	uint32_t l5oa1;
-	uint32_t l5da1;
-	uint16_t l5dx;
-	uint16_t l5dy;
-
-	/* Cursor */
-	uint16_t cutc;
-	uint8_t  cpm;
-	uint8_t  csize;
-	uint32_t cuoa0;
-	uint16_t cux0;
-	uint16_t cuy0;
-	uint32_t cuoa1;
-	uint16_t cux1;
-	uint16_t cuy1;
-
-	/* Layer blending */
-	uint32_t l0bld;
-	uint32_t pad03;
-	uint32_t l0tc;
-	uint16_t l3tc;
-	uint16_t l2tc;
-	uint32_t pad04[15];
-
-	/* Display settings */
-	uint32_t dcm1;
-	uint32_t dcm2;
-	uint32_t dcm3;
-	uint32_t pad05;
-
-	/* Layer 0 extended */
-	uint32_t l0em;
-	uint16_t l0wx;
-	uint16_t l0wy;
-	uint16_t l0ww;
-	uint16_t l0wh;
-	uint32_t pad06;
-
-	/* Layer 1 extended */
-	uint32_t l1em;
-	uint16_t l1wx;
-	uint16_t l1wy;
-	uint16_t l1ww;
-	uint16_t l1wh;
-	uint32_t pad07;
-
-	/* Layer 2 extended */
-	uint32_t l2em;
-	uint16_t l2wx;
-	uint16_t l2wy;
-	uint16_t l2ww;
-	uint16_t l2wh;
-	uint32_t pad08;
-
-	/* Layer 3 extended */
-	uint32_t l3em;
-	uint16_t l3wx;
-	uint16_t l3wy;
-	uint16_t l3ww;
-	uint16_t l3wh;
-	uint32_t pad09;
-
-	/* Layer 4 extended */
-	uint32_t l4em;
-	uint16_t l4wx;
-	uint16_t l4wy;
-	uint16_t l4ww;
-	uint16_t l4wh;
-	uint32_t pad10;
-
-	/* Layer 5 extended */
-	uint32_t l5em;
-	uint16_t l5wx;
-	uint16_t l5wy;
-	uint16_t l5ww;
-	uint16_t l5wh;
-	uint32_t pad11;
-
-	/* Multi screen control */
-	uint32_t msc;
-	uint32_t pad12[3];
-	uint32_t dls;
-	uint32_t dbgc;
-
-	/* Layer blending */
-	uint32_t l1bld;
-	uint32_t l2bld;
-	uint32_t l3bld;
-	uint32_t l4bld;
-	uint32_t l5bld;
-	uint32_t pad13;
-
-	/* Extended transparency control */
-	uint32_t l0etc;
-	uint32_t l1etc;
-	uint32_t l2etc;
-	uint32_t l3etc;
-	uint32_t l4etc;
-	uint32_t l5etc;
-	uint32_t pad14[10];
-
-	/* YUV coefficients */
-	uint32_t l1ycr0;
-	uint32_t l1ycr1;
-	uint32_t l1ycg0;
-	uint32_t l1ycg1;
-	uint32_t l1ycb0;
-	uint32_t l1ycb1;
-	uint32_t pad15[130];
-
-	/* Layer palletes */
-	uint32_t l0pal[256];
-	uint32_t l1pal[256];
-	uint32_t pad16[256];
-	uint32_t l2pal[256];
-	uint32_t l3pal[256];
-	uint32_t pad17[256];
-
-	/* PWM settings */
-	uint32_t vpwmm;
-	uint16_t vpwms;
-	uint16_t vpwme;
-	uint32_t vpwmc;
-	uint32_t pad18[253];
-};
-
-/* mb86r0x gdc capture controller */
-struct mb86r0x_gdc_cap {
-	uint32_t vcm;
-	uint32_t csc;
-	uint32_t vcs;
-	uint32_t pad01;
-
-	uint32_t cbm;
-	uint32_t cboa;
-	uint32_t cbla;
-	uint16_t cihstr;
-	uint16_t civstr;
-	uint16_t cihend;
-	uint16_t civend;
-	uint32_t pad02;
-
-	uint32_t chp;
-	uint32_t cvp;
-	uint32_t pad03[4];
-
-	uint32_t clpf;
-	uint32_t pad04;
-	uint32_t cmss;
-	uint32_t cmds;
-	uint32_t pad05[12];
-
-	uint32_t rgbhc;
-	uint32_t rgbhen;
-	uint32_t rgbven;
-	uint32_t pad06;
-	uint32_t rgbs;
-	uint32_t pad07[11];
-
-	uint32_t rgbcmy;
-	uint32_t rgbcmcb;
-	uint32_t rgbcmcr;
-	uint32_t rgbcmb;
-	uint32_t pad08[12 + 1984];
-};
-
-/* mb86r0x gdc draw */
-struct mb86r0x_gdc_draw {
-	uint32_t ys;
-	uint32_t xs;
-	uint32_t dxdy;
-	uint32_t xus;
-	uint32_t dxudy;
-	uint32_t xls;
-	uint32_t dxldy;
-	uint32_t usn;
-	uint32_t lsn;
-	uint32_t pad01[7];
-	uint32_t rs;
-	uint32_t drdx;
-	uint32_t drdy;
-	uint32_t gs;
-	uint32_t dgdx;
-	uint32_t dgdy;
-	uint32_t bs;
-	uint32_t dbdx;
-	uint32_t dbdy;
-	uint32_t pad02[7];
-	uint32_t zs;
-	uint32_t dzdx;
-	uint32_t dzdy;
-	uint32_t pad03[13];
-	uint32_t ss;
-	uint32_t dsdx;
-	uint32_t dsdy;
-	uint32_t ts;
-	uint32_t dtdx;
-	uint32_t dtdy;
-	uint32_t qs;
-	uint32_t dqdx;
-	uint32_t dqdy;
-	uint32_t pad04[23];
-	uint32_t lpn;
-	uint32_t lxs;
-	uint32_t lxde;
-	uint32_t lys;
-	uint32_t lyde;
-	uint32_t lzs;
-	uint32_t lzde;
-	uint32_t pad05[13];
-	uint32_t pxdc;
-	uint32_t pydc;
-	uint32_t pzdc;
-	uint32_t pad06[25];
-	uint32_t rxs;
-	uint32_t rys;
-	uint32_t rsizex;
-	uint32_t rsizey;
-	uint32_t pad07[12];
-	uint32_t saddr;
-	uint32_t sstride;
-	uint32_t srx;
-	uint32_t sry;
-	uint32_t daddr;
-	uint32_t dstride;
-	uint32_t drx;
-	uint32_t dry;
-	uint32_t brsizex;
-	uint32_t brsizey;
-	uint32_t tcolor;
-	uint32_t pad08[93];
-	uint32_t blpo;
-	uint32_t pad09[7];
-	uint32_t ctr;
-	uint32_t ifsr;
-	uint32_t ifcnt;
-	uint32_t sst;
-	uint32_t ds;
-	uint32_t pst;
-	uint32_t est;
-	uint32_t pad10;
-	uint32_t mdr0;
-	uint32_t mdr1;
-	uint32_t mdr2;
-	uint32_t mdr3;
-	uint32_t mdr4;
-	uint32_t pad14[2];
-	uint32_t mdr7;
-	uint32_t fbr;
-	uint32_t xres;
-	uint32_t zbr;
-	uint32_t tbr;
-	uint32_t pfbr;
-	uint32_t cxmin;
-	uint32_t cxmax;
-	uint32_t cymin;
-	uint32_t cymax;
-	uint32_t txs;
-	uint32_t tis;
-	uint32_t toa;
-	uint32_t sho;
-	uint32_t abr;
-	uint32_t pad15[2];
-	uint32_t fc;
-	uint32_t bc;
-	uint32_t alf;
-	uint32_t blp;
-	uint32_t pad16;
-	uint32_t tbc;
-	uint32_t pad11[42];
-	uint32_t lx0dc;
-	uint32_t ly0dc;
-	uint32_t lx1dc;
-	uint32_t ly1dc;
-	uint32_t pad12[12];
-	uint32_t x0dc;
-	uint32_t y0dc;
-	uint32_t x1dc;
-	uint32_t y1dc;
-	uint32_t x2dc;
-	uint32_t y2dc;
-	uint32_t pad13[666];
-};
-
-/* mb86r0x gdc geometry engine */
-struct mb86r0x_gdc_geom {
-	uint32_t gctr;
-	uint32_t pad00[15];
-	uint32_t gmdr0;
-	uint32_t gmdr1;
-	uint32_t gmdr2;
-	uint32_t pad01[237];
-	uint32_t dfifog;
-	uint32_t pad02[767];
-};
-
-/* mb86r0x gdc */
-struct mb86r0x_gdc {
-	uint32_t pad00[2];
-	uint32_t lts;
-	uint32_t pad01;
-	uint32_t lsta;
-	uint32_t pad02[3];
-	uint32_t ist;
-	uint32_t imask;
-	uint32_t pad03[6];
-	uint32_t lsa;
-	uint32_t lco;
-	uint32_t lreq;
-
-	uint32_t pad04[16*1024 - 19];
-	struct mb86r0x_gdc_dsp dsp0;
-	struct mb86r0x_gdc_dsp dsp1;
-	uint32_t pad05[4*1024 - 2];
-	uint32_t vccc;
-	uint32_t vcsr;
-	struct mb86r0x_gdc_cap cap0;
-	struct mb86r0x_gdc_cap cap1;
-	uint32_t pad06[4*1024];
-	uint32_t texture_base[16*1024];
-	struct mb86r0x_gdc_draw draw;
-	uint32_t pad07[7*1024];
-	struct mb86r0x_gdc_geom geom;
-	uint32_t pad08[7*1024];
-};
-
-#endif /* __ASSEMBLY__ */
-
-/*
- * Physical Address Defines
- */
-#define MB86R0x_DDR2_BASE		0xf3000000
-#define MB86R0x_GDC_BASE		0xf1fc0000
-#define MB86R0x_CCNT_BASE		0xfff42000
-#define MB86R0x_CAN0_BASE		0xfff54000
-#define MB86R0x_CAN1_BASE		0xfff55000
-#define MB86R0x_I2C0_BASE		0xfff56000
-#define MB86R0x_I2C1_BASE		0xfff57000
-#define MB86R0x_EHCI_BASE		0xfff80000
-#define MB86R0x_OHCI_BASE		0xfff81000
-#define MB86R0x_IRC1_BASE		0xfffb0000
-#define MB86R0x_MEMC_BASE		0xfffc0000
-#define MB86R0x_TIMER_BASE		0xfffe0000
-#define MB86R0x_UART0_BASE		0xfffe1000
-#define MB86R0x_UART1_BASE		0xfffe2000
-#define MB86R0x_IRCE_BASE		0xfffe4000
-#define MB86R0x_CRG_BASE		0xfffe7000
-#define MB86R0x_IRC0_BASE		0xfffe8000
-#define MB86R0x_GPIO_BASE		0xfffe9000
-#define MB86R0x_PWM0_BASE		0xfff41000
-#define MB86R0x_PWM1_BASE		0xfff41100
-
-#define MB86R0x_CRSR_SWRSTREQ 		(1 << 1)
-
-/*
- * Timer register bits
- */
-#define MB86R0x_TIMER_ENABLE		(1 << 7)
-#define MB86R0x_TIMER_MODE_MSK		(1 << 6)
-#define MB86R0x_TIMER_MODE_FR		(0 << 6)
-#define MB86R0x_TIMER_MODE_PD		(1 << 6)
-
-#define MB86R0x_TIMER_INT_EN		(1 << 5)
-#define MB86R0x_TIMER_PRS_MSK		(3 << 2)
-#define MB86R0x_TIMER_PRS_4S		(1 << 2)
-#define MB86R0x_TIMER_PRS_8S		(1 << 3)
-#define MB86R0x_TIMER_SIZE_32		(1 << 1)
-#define MB86R0x_TIMER_ONE_SHT		(1 << 0)
-
-/*
- * Clock reset generator bits
- */
-#define MB86R0x_CRG_CRPR_PLLRDY		(1 << 8)
-#define MB86R0x_CRG_CRPR_PLLMODE	(0x1f << 0)
-#define MB86R0x_CRG_CRPR_PLLMODE_X49	(0 << 0)
-#define MB86R0x_CRG_CRPR_PLLMODE_X46	(1 << 0)
-#define MB86R0x_CRG_CRPR_PLLMODE_X37	(2 << 0)
-#define MB86R0x_CRG_CRPR_PLLMODE_X20	(3 << 0)
-#define MB86R0x_CRG_CRPR_PLLMODE_X47	(4 << 0)
-#define MB86R0x_CRG_CRPR_PLLMODE_X44	(5 << 0)
-#define MB86R0x_CRG_CRPR_PLLMODE_X36	(6 << 0)
-#define MB86R0x_CRG_CRPR_PLLMODE_X19	(7 << 0)
-#define MB86R0x_CRG_CRPR_PLLMODE_X39	(8 << 0)
-#define MB86R0x_CRG_CRPR_PLLMODE_X38	(9 << 0)
-#define MB86R0x_CRG_CRPR_PLLMODE_X30	(10 << 0)
-#define MB86R0x_CRG_CRPR_PLLMODE_X15	(11 << 0)
-/*
- * DDR2 controller bits
- */
-#define MB86R0x_DDR2_DRCI_DRINI		(1 << 15)
-#define MB86R0x_DDR2_DRCI_CKEN		(1 << 14)
-#define MB86R0x_DDR2_DRCI_DRCMD		(1 << 0)
-#define MB86R0x_DDR2_DRCI_CMD		(MB86R0x_DDR2_DRCI_DRINI | \
-					MB86R0x_DDR2_DRCI_CKEN | \
-					MB86R0x_DDR2_DRCI_DRCMD)
-#define MB86R0x_DDR2_DRCI_INIT		(MB86R0x_DDR2_DRCI_DRINI | \
-					MB86R0x_DDR2_DRCI_CKEN)
-#define MB86R0x_DDR2_DRCI_NORMAL	MB86R0x_DDR2_DRCI_CKEN
-#endif /* MB86R0X_H */
diff --git a/arch/arm/include/asm/arch-mx25/clock.h b/arch/arm/include/asm/arch-mx25/clock.h
deleted file mode 100644
index c59f588..0000000
--- a/arch/arm/include/asm/arch-mx25/clock.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/*
- *
- * (c) 2009 Ilya Yanok, Emcraft Systems <yanok@emcraft.com>
- *
- * Modified for mx25 by John Rigby <jrigby@gmail.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __ASM_ARCH_CLOCK_H
-#define __ASM_ARCH_CLOCK_H
-
-ulong imx_get_perclk(int clk);
-ulong imx_get_ahbclk(void);
-
-#define imx_get_uartclk() imx_get_perclk(15)
-#define imx_get_fecclk() (imx_get_ahbclk()/2)
-
-
-#endif /* __ASM_ARCH_CLOCK_H */
diff --git a/arch/arm/include/asm/arch-mx25/imx-regs.h b/arch/arm/include/asm/arch-mx25/imx-regs.h
deleted file mode 100644
index 55ad115..0000000
--- a/arch/arm/include/asm/arch-mx25/imx-regs.h
+++ /dev/null
@@ -1,321 +0,0 @@
-/*
- * Copyright (C) 2009, DENX Software Engineering
- * Author: John Rigby <jcrigby@gmail.com
- *
- *   Based on arch-mx31/mx31-regs.h
- *	Copyright (C) 2009 Ilya Yanok,
- *		Emcraft Systems <yanok@emcraft.com>
- *   and arch-mx27/imx-regs.h
- *	Copyright (C) 2007 Pengutronix,
- *		Sascha Hauer <s.hauer@pengutronix.de>
- *	Copyright (C) 2009 Ilya Yanok,
- *		Emcraft Systems <yanok@emcraft.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef _IMX_REGS_H
-#define _IMX_REGS_H
-
-#ifndef __ASSEMBLY__
-#ifdef CONFIG_FEC_MXC
-extern void mx25_fec_init_pins(void);
-extern void imx_get_mac_from_fuse(unsigned char *mac);
-#endif
-
-/* Clock Control Module (CCM) registers */
-struct ccm_regs {
-	u32 mpctl;	/* Core PLL Control */
-	u32 upctl;	/* USB PLL Control */
-	u32 cctl;	/* Clock Control */
-	u32 cgr0;	/* Clock Gating Control 0 */
-	u32 cgr1;	/* Clock Gating Control 1 */
-	u32 cgr2;	/* Clock Gating Control 2 */
-	u32 pcdr[4];	/* PER Clock Dividers */
-	u32 rcsr;	/* CCM Status */
-	u32 crdr;	/* CCM Reset and Debug */
-	u32 dcvr0;	/* DPTC Comparator Value 0 */
-	u32 dcvr1;	/* DPTC Comparator Value 1 */
-	u32 dcvr2;	/* DPTC Comparator Value 2 */
-	u32 dcvr3;	/* DPTC Comparator Value 3 */
-	u32 ltr0;	/* Load Tracking 0 */
-	u32 ltr1;	/* Load Tracking 1 */
-	u32 ltr2;	/* Load Tracking 2 */
-	u32 ltr3;	/* Load Tracking 3 */
-	u32 ltbr0;	/* Load Tracking Buffer 0 */
-	u32 ltbr1;	/* Load Tracking Buffer 1 */
-	u32 pcmr0;	/* Power Management Control 0 */
-	u32 pcmr1;	/* Power Management Control 1 */
-	u32 pcmr2;	/* Power Management Control 2 */
-	u32 mcr;	/* Miscellaneous Control */
-	u32 lpimr0;	/* Low Power Interrupt Mask 0 */
-	u32 lpimr1;	/* Low Power Interrupt Mask 1 */
-};
-
-/* Enhanced SDRAM Controller (ESDRAMC) registers */
-struct esdramc_regs {
-	u32 ctl0; 	/* control 0 */
-	u32 cfg0; 	/* configuration 0 */
-	u32 ctl1; 	/* control 1 */
-	u32 cfg1; 	/* configuration 1 */
-	u32 misc; 	/* miscellaneous */
-	u32 pad[3];
-	u32 cdly1;	/* Delay Line 1 configuration debug */
-	u32 cdly2;	/* delay line 2 configuration debug */
-	u32 cdly3;	/* delay line 3 configuration debug */
-	u32 cdly4;	/* delay line 4 configuration debug */
-	u32 cdly5;	/* delay line 5 configuration debug */
-	u32 cdlyl;	/* delay line cycle length debug */
-};
-
-/* GPIO registers */
-struct gpio_regs {
-	u32 dr;		/* data */
-	u32 dir;	/* direction */
-	u32 psr;	/* pad satus */
-	u32 icr1;	/* interrupt config 1 */
-	u32 icr2;	/* interrupt config 2 */
-	u32 imr;	/* interrupt mask */
-	u32 isr;	/* interrupt status */
-	u32 edge_sel;	/* edge select */
-};
-
-/* General Purpose Timer (GPT) registers */
-struct gpt_regs {
-	u32 ctrl;   	/* control */
-	u32 pre;    	/* prescaler */
-	u32 stat;   	/* status */
-	u32 intr;   	/* interrupt */
-	u32 cmp[3]; 	/* output compare 1-3 */
-	u32 capt[2];	/* input capture 1-2 */
-	u32 counter;	/* counter */
-};
-
-/* Watchdog Timer (WDOG) registers */
-struct wdog_regs {
-	u16 wcr;	/* Control */
-	u16 wsr;	/* Service */
-	u16 wrsr;	/* Reset Status */
-	u16 wicr;	/* Interrupt Control */
-	u16 wmcr;	/* Misc Control */
-};
-
-/* IIM control registers */
-struct iim_regs {
-	u32 iim_stat;
-	u32 iim_statm;
-	u32 iim_err;
-	u32 iim_emask;
-	u32 iim_fctl;
-	u32 iim_ua;
-	u32 iim_la;
-	u32 iim_sdat;
-	u32 iim_prev;
-	u32 iim_srev;
-	u32 iim_prog_p;
-	u32 res1[0x1f5];
-	struct fuse_bank {
-		u32 fuse_regs[0x20];
-		u32 fuse_rsvd[0xe0];
-	} bank[3];
-};
-
-struct fuse_bank0_regs {
-	u32 fuse0_25[0x1a];
-	u32 mac_addr[6];
-};
-
-#endif
-
-/* AIPS 1 */
-#define IMX_AIPS1_BASE		(0x43F00000)
-#define IMX_MAX_BASE		(0x43F04000)
-#define IMX_CLKCTL_BASE		(0x43F08000)
-#define IMX_ETB_SLOT4_BASE	(0x43F0C000)
-#define IMX_ETB_SLOT5_BASE	(0x43F10000)
-#define IMX_ECT_CTIO_BASE	(0x43F18000)
-#define IMX_I2C_BASE		(0x43F80000)
-#define IMX_I2C3_BASE		(0x43F84000)
-#define IMX_CAN1_BASE		(0x43F88000)
-#define IMX_CAN2_BASE		(0x43F8C000)
-#define IMX_UART1_BASE		(0x43F90000)
-#define IMX_UART2_BASE		(0x43F94000)
-#define IMX_I2C2_BASE		(0x43F98000)
-#define IMX_OWIRE_BASE		(0x43F9C000)
-#define IMX_CSPI1_BASE		(0x43FA4000)
-#define IMX_KPP_BASE		(0x43FA8000)
-#define IMX_IOPADMUX_BASE	(0x43FAC000)
-#define IMX_IOPADCTL_BASE	(0x43FAC22C)
-#define IMX_IOPADGRPCTL_BASE	(0x43FAC418)
-#define IMX_IOPADINPUTSEL_BASE	(0x43FAC460)
-#define IMX_AUDMUX_BASE		(0x43FB0000)
-#define IMX_ECT_IP1_BASE	(0x43FB8000)
-#define IMX_ECT_IP2_BASE	(0x43FBC000)
-
-/* SPBA */
-#define IMX_SPBA_BASE		(0x50000000)
-#define IMX_CSPI3_BASE		(0x50004000)
-#define IMX_UART4_BASE		(0x50008000)
-#define IMX_UART3_BASE		(0x5000C000)
-#define IMX_CSPI2_BASE		(0x50010000)
-#define IMX_SSI2_BASE		(0x50014000)
-#define IMX_ESAI_BASE		(0x50018000)
-#define IMX_ATA_DMA_BASE	(0x50020000)
-#define IMX_SIM1_BASE		(0x50024000)
-#define IMX_SIM2_BASE		(0x50028000)
-#define IMX_UART5_BASE		(0x5002C000)
-#define IMX_TSC_BASE		(0x50030000)
-#define IMX_SSI1_BASE		(0x50034000)
-#define IMX_FEC_BASE		(0x50038000)
-#define IMX_SPBA_CTRL_BASE	(0x5003C000)
-
-/* AIPS 2 */
-#define IMX_AIPS2_BASE		(0x53F00000)
-#define IMX_CCM_BASE		(0x53F80000)
-#define IMX_GPT4_BASE		(0x53F84000)
-#define IMX_GPT3_BASE		(0x53F88000)
-#define IMX_GPT2_BASE		(0x53F8C000)
-#define IMX_GPT1_BASE		(0x53F90000)
-#define IMX_EPIT1_BASE		(0x53F94000)
-#define IMX_EPIT2_BASE		(0x53F98000)
-#define IMX_GPIO4_BASE		(0x53F9C000)
-#define IMX_PWM2_BASE		(0x53FA0000)
-#define IMX_GPIO3_BASE		(0x53FA4000)
-#define IMX_PWM3_BASE		(0x53FA8000)
-#define IMX_SCC_BASE		(0x53FAC000)
-#define IMX_SCM_BASE		(0x53FAE000)
-#define IMX_SMN_BASE		(0x53FAF000)
-#define IMX_RNGD_BASE		(0x53FB0000)
-#define IMX_MMC_SDHC1_BASE	(0x53FB4000)
-#define IMX_MMC_SDHC2_BASE	(0x53FB8000)
-#define IMX_LCDC_BASE		(0x53FBC000)
-#define IMX_SLCDC_BASE		(0x53FC0000)
-#define IMX_PWM4_BASE		(0x53FC8000)
-#define IMX_GPIO1_BASE		(0x53FCC000)
-#define IMX_GPIO2_BASE		(0x53FD0000)
-#define IMX_SDMA_BASE		(0x53FD4000)
-#define IMX_WDT_BASE		(0x53FDC000)
-#define IMX_PWM1_BASE		(0x53FE0000)
-#define IMX_RTIC_BASE		(0x53FEC000)
-#define IMX_IIM_BASE		(0x53FF0000)
-#define IMX_USB_BASE		(0x53FF4000)
-#define IMX_CSI_BASE		(0x53FF8000)
-#define IMX_DRYICE_BASE		(0x53FFC000)
-
-#define IMX_ARM926_ROMPATCH	(0x60000000)
-#define IMX_ARM926_ASIC		(0x68000000)
-
-/* 128K Internal Static RAM */
-#define IMX_RAM_BASE		(0x78000000)
-
-/* SDRAM BANKS */
-#define IMX_SDRAM_BANK0_BASE	(0x80000000)
-#define IMX_SDRAM_BANK1_BASE	(0x90000000)
-
-#define IMX_WEIM_CS0		(0xA0000000)
-#define IMX_WEIM_CS1		(0xA8000000)
-#define IMX_WEIM_CS2		(0xB0000000)
-#define IMX_WEIM_CS3		(0xB2000000)
-#define IMX_WEIM_CS4		(0xB4000000)
-#define IMX_ESDRAMC_BASE	(0xB8001000)
-#define IMX_WEIM_CTRL_BASE	(0xB8002000)
-#define IMX_M3IF_CTRL_BASE	(0xB8003000)
-#define IMX_EMI_CTRL_BASE	(0xB8004000)
-
-/* NAND Flash Controller */
-#define IMX_NFC_BASE		(0xBB000000)
-#define NFC_BASE_ADDR		IMX_NFC_BASE
-
-/* CCM bitfields */
-#define CCM_PLL_MFI_SHIFT	10
-#define CCM_PLL_MFI_MASK	0xf
-#define CCM_PLL_MFN_SHIFT	0
-#define CCM_PLL_MFN_MASK	0x3ff
-#define CCM_PLL_MFD_SHIFT	16
-#define CCM_PLL_MFD_MASK	0x3ff
-#define CCM_PLL_PD_SHIFT	26
-#define CCM_PLL_PD_MASK		0xf
-#define CCM_CCTL_ARM_DIV_SHIFT	30
-#define CCM_CCTL_ARM_DIV_MASK	3
-#define CCM_CCTL_AHB_DIV_SHIFT	28
-#define CCM_CCTL_AHB_DIV_MASK	3
-#define CCM_CCTL_ARM_SRC	(1 << 14)
-#define CCM_CGR1_GPT1		(1 << 19)
-#define CCM_PERCLK_REG(clk)	(clk / 4)
-#define CCM_PERCLK_SHIFT(clk)	(8 * (clk % 4))
-#define CCM_PERCLK_MASK		0x3f
-#define CCM_RCSR_NF_16BIT_SEL	(1 << 14)
-#define CCM_RCSR_NF_PS(v)	((v >> 26) & 3)
-
-/* ESDRAM Controller register bitfields */
-#define ESDCTL_PRCT(x)		(((x) & 0x3f) << 0)
-#define ESDCTL_BL		(1 << 7)
-#define ESDCTL_FP		(1 << 8)
-#define ESDCTL_PWDT(x)		(((x) & 3) << 10)
-#define ESDCTL_SREFR(x)		(((x) & 7) << 13)
-#define ESDCTL_DSIZ_16_UPPER	(0 << 16)
-#define ESDCTL_DSIZ_16_LOWER	(1 << 16)
-#define ESDCTL_DSIZ_32		(2 << 16)
-#define ESDCTL_COL8		(0 << 20)
-#define ESDCTL_COL9		(1 << 20)
-#define ESDCTL_COL10		(2 << 20)
-#define ESDCTL_ROW11		(0 << 24)
-#define ESDCTL_ROW12		(1 << 24)
-#define ESDCTL_ROW13		(2 << 24)
-#define ESDCTL_ROW14		(3 << 24)
-#define ESDCTL_ROW15		(4 << 24)
-#define ESDCTL_SP		(1 << 27)
-#define ESDCTL_SMODE_NORMAL	(0 << 28)
-#define ESDCTL_SMODE_PRECHARGE	(1 << 28)
-#define ESDCTL_SMODE_AUTO_REF	(2 << 28)
-#define ESDCTL_SMODE_LOAD_MODE	(3 << 28)
-#define ESDCTL_SMODE_MAN_REF	(4 << 28)
-#define ESDCTL_SDE		(1 << 31)
-
-#define ESDCFG_TRC(x)		(((x) & 0xf) << 0)
-#define ESDCFG_TRCD(x)		(((x) & 0x7) << 4)
-#define ESDCFG_TCAS(x)		(((x) & 0x3) << 8)
-#define ESDCFG_TRRD(x)		(((x) & 0x3) << 10)
-#define ESDCFG_TRAS(x)		(((x) & 0x7) << 12)
-#define ESDCFG_TWR		(1 << 15)
-#define ESDCFG_TMRD(x)		(((x) & 0x3) << 16)
-#define ESDCFG_TRP(x)		(((x) & 0x3) << 18)
-#define ESDCFG_TWTR		(1 << 20)
-#define ESDCFG_TXP(x)		(((x) & 0x3) << 21)
-
-#define ESDMISC_RST		(1 << 1)
-#define ESDMISC_MDDREN		(1 << 2)
-#define ESDMISC_MDDR_DL_RST	(1 << 3)
-#define ESDMISC_MDDR_MDIS	(1 << 4)
-#define ESDMISC_LHD		(1 << 5)
-#define ESDMISC_MA10_SHARE	(1 << 6)
-#define ESDMISC_SDRAM_RDY	(1 << 31)
-
-/* GPT bits */
-#define GPT_CTRL_SWR		(1 << 15)	/* Software reset */
-#define GPT_CTRL_FRR		(1 << 9)	/* Freerun / restart */
-#define GPT_CTRL_CLKSOURCE_32	(4 << 6)	/* Clock source	*/
-#define GPT_CTRL_TEN		1		/* Timer enable	*/
-
-/* WDOG enable */
-#define WCR_WDE 		0x04
-#define WSR_UNLOCK1		0x5555
-#define WSR_UNLOCK2		0xAAAA
-
-#endif				/* _IMX_REGS_H */
diff --git a/arch/arm/include/asm/arch-mx25/imx25-pinmux.h b/arch/arm/include/asm/arch-mx25/imx25-pinmux.h
deleted file mode 100644
index a4c658b..0000000
--- a/arch/arm/include/asm/arch-mx25/imx25-pinmux.h
+++ /dev/null
@@ -1,421 +0,0 @@
-/*
- * iopin settings are controlled by four different sets of registers
- *	iopad mux control
- *	individual iopad setup (voltage select, pull/keep, drive strength ...)
- *	group iopad setup (same as above but for groups of signals)
- *	input select when multiple inputs are possible
- */
-
-/*
- * software pad mux control
- */
-/* SW Input On (Loopback) */
-#define MX25_PIN_MUX_SION		(1 << 4)
-/* MUX Mode (0-7) */
-#define MX25_PIN_MUX_MODE(mode)		((mode & 0x7) << 0)
-struct iomuxc_mux_ctl {
-	u32 gpr1;
-	u32 observe_int_mux;
-	u32 pad_a10;
-	u32 pad_a13;
-	u32 pad_a14;
-	u32 pad_a15;
-	u32 pad_a16;
-	u32 pad_a17;
-	u32 pad_a18;
-	u32 pad_a19;
-	u32 pad_a20;
-	u32 pad_a21;
-	u32 pad_a22;
-	u32 pad_a23;
-	u32 pad_a24;
-	u32 pad_a25;
-	u32 pad_eb0;
-	u32 pad_eb1;
-	u32 pad_oe;
-	u32 pad_cs0;
-	u32 pad_cs1;
-	u32 pad_cs4;
-	u32 pad_cs5;
-	u32 pad_nf_ce0;
-	u32 pad_ecb;
-	u32 pad_lba;
-	u32 pad_bclk;
-	u32 pad_rw;
-	u32 pad_nfwe_b;
-	u32 pad_nfre_b;
-	u32 pad_nfale;
-	u32 pad_nfcle;
-	u32 pad_nfwp_b;
-	u32 pad_nfrb;
-	u32 pad_d15;
-	u32 pad_d14;
-	u32 pad_d13;
-	u32 pad_d12;
-	u32 pad_d11;
-	u32 pad_d10;
-	u32 pad_d9;
-	u32 pad_d8;
-	u32 pad_d7;
-	u32 pad_d6;
-	u32 pad_d5;
-	u32 pad_d4;
-	u32 pad_d3;
-	u32 pad_d2;
-	u32 pad_d1;
-	u32 pad_d0;
-	u32 pad_ld0;
-	u32 pad_ld1;
-	u32 pad_ld2;
-	u32 pad_ld3;
-	u32 pad_ld4;
-	u32 pad_ld5;
-	u32 pad_ld6;
-	u32 pad_ld7;
-	u32 pad_ld8;
-	u32 pad_ld9;
-	u32 pad_ld10;
-	u32 pad_ld11;
-	u32 pad_ld12;
-	u32 pad_ld13;
-	u32 pad_ld14;
-	u32 pad_ld15;
-	u32 pad_hsync;
-	u32 pad_vsync;
-	u32 pad_lsclk;
-	u32 pad_oe_acd;
-	u32 pad_contrast;
-	u32 pad_pwm;
-	u32 pad_csi_d2;
-	u32 pad_csi_d3;
-	u32 pad_csi_d4;
-	u32 pad_csi_d5;
-	u32 pad_csi_d6;
-	u32 pad_csi_d7;
-	u32 pad_csi_d8;
-	u32 pad_csi_d9;
-	u32 pad_csi_mclk;
-	u32 pad_csi_vsync;
-	u32 pad_csi_hsync;
-	u32 pad_csi_pixclk;
-	u32 pad_i2c1_clk;
-	u32 pad_i2c1_dat;
-	u32 pad_cspi1_mosi;
-	u32 pad_cspi1_miso;
-	u32 pad_cspi1_ss0;
-	u32 pad_cspi1_ss1;
-	u32 pad_cspi1_sclk;
-	u32 pad_cspi1_rdy;
-	u32 pad_uart1_rxd;
-	u32 pad_uart1_txd;
-	u32 pad_uart1_rts;
-	u32 pad_uart1_cts;
-	u32 pad_uart2_rxd;
-	u32 pad_uart2_txd;
-	u32 pad_uart2_rts;
-	u32 pad_uart2_cts;
-	u32 pad_sd1_cmd;
-	u32 pad_sd1_clk;
-	u32 pad_sd1_data0;
-	u32 pad_sd1_data1;
-	u32 pad_sd1_data2;
-	u32 pad_sd1_data3;
-	u32 pad_kpp_row0;
-	u32 pad_kpp_row1;
-	u32 pad_kpp_row2;
-	u32 pad_kpp_row3;
-	u32 pad_kpp_col0;
-	u32 pad_kpp_col1;
-	u32 pad_kpp_col2;
-	u32 pad_kpp_col3;
-	u32 pad_fec_mdc;
-	u32 pad_fec_mdio;
-	u32 pad_fec_tdata0;
-	u32 pad_fec_tdata1;
-	u32 pad_fec_tx_en;
-	u32 pad_fec_rdata0;
-	u32 pad_fec_rdata1;
-	u32 pad_fec_rx_dv;
-	u32 pad_fec_tx_clk;
-	u32 pad_rtck;
-	u32 pad_de_b;
-	u32 pad_gpio_a;
-	u32 pad_gpio_b;
-	u32 pad_gpio_c;
-	u32 pad_gpio_d;
-	u32 pad_gpio_e;
-	u32 pad_gpio_f;
-	u32 pad_ext_armclk;
-	u32 pad_upll_bypclk;
-	u32 pad_vstby_req;
-	u32 pad_vstby_ack;
-	u32 pad_power_fail;
-	u32 pad_clko;
-	u32 pad_boot_mode0;
-	u32 pad_boot_mode1;
-};
-
-/*
- * software pad control
- */
-/* Select 3.3 or 1.8 volts */
-#define MX25_PIN_PAD_CTL_DVS_33			(0 << 13)
-#define MX25_PIN_PAD_CTL_DVS_18			(1 << 13)
-/* Enable hysteresis */
-#define MX25_PIN_PAD_CTL_HYS			(1 << 8)
-/* Enable pull/keeper */
-#define MX25_PIN_PAD_CTL_PKE			(1 << 7)
-/* 0 - keeper / 1 - pull */
-#define MX25_PIN_PAD_CTL_PUE			(1 << 6)
-/* pull up/down strength */
-#define MX25_PIN_PAD_CTL_100K_PD		(0 << 4)
-#define MX25_PIN_PAD_CTL_47K_PU			(1 << 4)
-#define MX25_PIN_PAD_CTL_100K_PU		(2 << 4)
-#define MX25_PIN_PAD_CTL_22K_PU			(3 << 4)
-/* open drain control */
-#define MX25_PIN_PAD_CTL_OD			(1 << 3)
-/* drive strength */
-#define MX25_PIN_PAD_CTL_DS_NOM			(0 << 1)
-#define MX25_PIN_PAD_CTL_DS_HIGH		(1 << 1)
-#define MX25_PIN_PAD_CTL_DS_MAX			(2 << 1)
-#define MX25_PIN_PAD_CTL_DS_MAX11		(3 << 1)
-/* slew rate */
-#define MX25_PIN_PAD_CTL_SRE_SLOW		(0 << 0)
-#define MX25_PIN_PAD_CTL_SRE_FAST		(1 << 0)
-struct  iomuxc_pad_ctl {
-	u32 pad_a13;
-	u32 pad_a14;
-	u32 pad_a15;
-	u32 pad_a17;
-	u32 pad_a18;
-	u32 pad_a19;
-	u32 pad_a20;
-	u32 pad_a21;
-	u32 pad_a23;
-	u32 pad_a24;
-	u32 pad_a25;
-	u32 pad_eb0;
-	u32 pad_eb1;
-	u32 pad_oe;
-	u32 pad_cs4;
-	u32 pad_cs5;
-	u32 pad_nf_ce0;
-	u32 pad_ecb;
-	u32 pad_lba;
-	u32 pad_rw;
-	u32 pad_nfrb;
-	u32 pad_d15;
-	u32 pad_d14;
-	u32 pad_d13;
-	u32 pad_d12;
-	u32 pad_d11;
-	u32 pad_d10;
-	u32 pad_d9;
-	u32 pad_d8;
-	u32 pad_d7;
-	u32 pad_d6;
-	u32 pad_d5;
-	u32 pad_d4;
-	u32 pad_d3;
-	u32 pad_d2;
-	u32 pad_d1;
-	u32 pad_d0;
-	u32 pad_ld0;
-	u32 pad_ld1;
-	u32 pad_ld2;
-	u32 pad_ld3;
-	u32 pad_ld4;
-	u32 pad_ld5;
-	u32 pad_ld6;
-	u32 pad_ld7;
-	u32 pad_ld8;
-	u32 pad_ld9;
-	u32 pad_ld10;
-	u32 pad_ld11;
-	u32 pad_ld12;
-	u32 pad_ld13;
-	u32 pad_ld14;
-	u32 pad_ld15;
-	u32 pad_hsync;
-	u32 pad_vsync;
-	u32 pad_lsclk;
-	u32 pad_oe_acd;
-	u32 pad_contrast;
-	u32 pad_pwm;
-	u32 pad_csi_d2;
-	u32 pad_csi_d3;
-	u32 pad_csi_d4;
-	u32 pad_csi_d5;
-	u32 pad_csi_d6;
-	u32 pad_csi_d7;
-	u32 pad_csi_d8;
-	u32 pad_csi_d9;
-	u32 pad_csi_mclk;
-	u32 pad_csi_vsync;
-	u32 pad_csi_hsync;
-	u32 pad_csi_pixclk;
-	u32 pad_i2c1_clk;
-	u32 pad_i2c1_dat;
-	u32 pad_cspi1_mosi;
-	u32 pad_cspi1_miso;
-	u32 pad_cspi1_ss0;
-	u32 pad_cspi1_ss1;
-	u32 pad_cspi1_sclk;
-	u32 pad_cspi1_rdy;
-	u32 pad_uart1_rxd;
-	u32 pad_uart1_txd;
-	u32 pad_uart1_rts;
-	u32 pad_uart1_cts;
-	u32 pad_uart2_rxd;
-	u32 pad_uart2_txd;
-	u32 pad_uart2_rts;
-	u32 pad_uart2_cts;
-	u32 pad_sd1_cmd;
-	u32 pad_sd1_clk;
-	u32 pad_sd1_data0;
-	u32 pad_sd1_data1;
-	u32 pad_sd1_data2;
-	u32 pad_sd1_data3;
-	u32 pad_kpp_row0;
-	u32 pad_kpp_row1;
-	u32 pad_kpp_row2;
-	u32 pad_kpp_row3;
-	u32 pad_kpp_col0;
-	u32 pad_kpp_col1;
-	u32 pad_kpp_col2;
-	u32 pad_kpp_col3;
-	u32 pad_fec_mdc;
-	u32 pad_fec_mdio;
-	u32 pad_fec_tdata0;
-	u32 pad_fec_tdata1;
-	u32 pad_fec_tx_en;
-	u32 pad_fec_rdata0;
-	u32 pad_fec_rdata1;
-	u32 pad_fec_rx_dv;
-	u32 pad_fec_tx_clk;
-	u32 pad_rtck;
-	u32 pad_tdo;
-	u32 pad_de_b;
-	u32 pad_gpio_a;
-	u32 pad_gpio_b;
-	u32 pad_gpio_c;
-	u32 pad_gpio_d;
-	u32 pad_gpio_e;
-	u32 pad_gpio_f;
-	u32 pad_vstby_req;
-	u32 pad_vstby_ack;
-	u32 pad_power_fail;
-	u32 pad_clko;
-};
-
-
-/*
- * Pad group drive strength and voltage select
- * Same fields as iomuxc_pad_ctl plus ddr type
- */
-/* Select DDR type */
-#define MX25_PIN_PAD_CTL_DDR_18			(0 << 11)
-#define MX25_PIN_PAD_CTL_DDR_33			(1 << 11)
-#define MX25_PIN_PAD_CTL_DDR_MAX		(2 << 11)
-struct iomuxc_pad_grp_ctl {
-	u32 grp_dvs_misc;
-	u32 grp_dse_fec;
-	u32 grp_dvs_jtag;
-	u32 grp_dse_nfc;
-	u32 grp_dse_csi;
-	u32 grp_dse_weim;
-	u32 grp_dse_ddr;
-	u32 grp_dvs_crm;
-	u32 grp_dse_kpp;
-	u32 grp_dse_sdhc1;
-	u32 grp_dse_lcd;
-	u32 grp_dse_uart;
-	u32 grp_dvs_nfc;
-	u32 grp_dvs_csi;
-	u32 grp_dse_cspi1;
-	u32 grp_ddrtype;
-	u32 grp_dvs_sdhc1;
-	u32 grp_dvs_lcd;
-};
-
-/*
- * Pad input select control
- * Select which pad to connect to an input port
- * where multiple pads can function as given input
- */
-#define MX25_PAD_INPUT_SELECT_DAISY(in)		((in & 0x7) << 0)
-struct iomuxc_pad_input_select {
-	u32 audmux_p4_input_da_amx;
-	u32 audmux_p4_input_db_amx;
-	u32 audmux_p4_input_rxclk_amx;
-	u32 audmux_p4_input_rxfs_amx;
-	u32 audmux_p4_input_txclk_amx;
-	u32 audmux_p4_input_txfs_amx;
-	u32 audmux_p7_input_da_amx;
-	u32 audmux_p7_input_txfs_amx;
-	u32 can1_ipp_ind_canrx;
-	u32 can2_ipp_ind_canrx;
-	u32 csi_ipp_csi_d_0;
-	u32 csi_ipp_csi_d_1;
-	u32 cspi1_ipp_ind_ss3_b;
-	u32 cspi2_ipp_cspi_clk_in;
-	u32 cspi2_ipp_ind_dataready_b;
-	u32 cspi2_ipp_ind_miso;
-	u32 cspi2_ipp_ind_mosi;
-	u32 cspi2_ipp_ind_ss0_b;
-	u32 cspi2_ipp_ind_ss1_b;
-	u32 cspi3_ipp_cspi_clk_in;
-	u32 cspi3_ipp_ind_dataready_b;
-	u32 cspi3_ipp_ind_miso;
-	u32 cspi3_ipp_ind_mosi;
-	u32 cspi3_ipp_ind_ss0_b;
-	u32 cspi3_ipp_ind_ss1_b;
-	u32 cspi3_ipp_ind_ss2_b;
-	u32 cspi3_ipp_ind_ss3_b;
-	u32 esdhc1_ipp_dat4_in;
-	u32 esdhc1_ipp_dat5_in;
-	u32 esdhc1_ipp_dat6_in;
-	u32 esdhc1_ipp_dat7_in;
-	u32 esdhc2_ipp_card_clk_in;
-	u32 esdhc2_ipp_cmd_in;
-	u32 esdhc2_ipp_dat0_in;
-	u32 esdhc2_ipp_dat1_in;
-	u32 esdhc2_ipp_dat2_in;
-	u32 esdhc2_ipp_dat3_in;
-	u32 esdhc2_ipp_dat4_in;
-	u32 esdhc2_ipp_dat5_in;
-	u32 esdhc2_ipp_dat6_in;
-	u32 esdhc2_ipp_dat7_in;
-	u32 fec_fec_col;
-	u32 fec_fec_crs;
-	u32 fec_fec_rdata_2;
-	u32 fec_fec_rdata_3;
-	u32 fec_fec_rx_clk;
-	u32 fec_fec_rx_er;
-	u32 i2c2_ipp_scl_in;
-	u32 i2c2_ipp_sda_in;
-	u32 i2c3_ipp_scl_in;
-	u32 i2c3_ipp_sda_in;
-	u32 kpp_ipp_ind_col_4;
-	u32 kpp_ipp_ind_col_5;
-	u32 kpp_ipp_ind_col_6;
-	u32 kpp_ipp_ind_col_7;
-	u32 kpp_ipp_ind_row_4;
-	u32 kpp_ipp_ind_row_5;
-	u32 kpp_ipp_ind_row_6;
-	u32 kpp_ipp_ind_row_7;
-	u32 sim1_pin_sim_rcvd1_in;
-	u32 sim1_pin_sim_simpd1;
-	u32 sim1_sim_rcvd1_io;
-	u32 sim2_pin_sim_rcvd1_in;
-	u32 sim2_pin_sim_simpd1;
-	u32 sim2_sim_rcvd1_io;
-	u32 uart3_ipp_uart_rts_b;
-	u32 uart3_ipp_uart_rxd_mux;
-	u32 uart4_ipp_uart_rts_b;
-	u32 uart4_ipp_uart_rxd_mux;
-	u32 uart5_ipp_uart_rts_b;
-	u32 uart5_ipp_uart_rxd_mux;
-	u32 usb_top_ipp_ind_otg_usb_oc;
-	u32 usb_top_ipp_ind_uh2_usb_oc;
-};
diff --git a/arch/arm/include/asm/arch-mx27/asm-offsets.h b/arch/arm/include/asm/arch-mx27/asm-offsets.h
deleted file mode 100644
index 497afe5..0000000
--- a/arch/arm/include/asm/arch-mx27/asm-offsets.h
+++ /dev/null
@@ -1,16 +0,0 @@
-#define AIPI1_PSR0	0x10000000
-#define AIPI1_PSR1	0x10000004
-#define AIPI2_PSR0	0x10020000
-#define AIPI2_PSR1	0x10020004
-#define CSCR		0x10027000
-#define MPCTL0		0x10027004
-#define SPCTL0		0x1002700c
-#define PCDR0		0x10027018
-#define PCDR1		0x1002701c
-#define PCCR0		0x10027020
-#define PCCR1		0x10027024
-#define ESDCTL0_ROF	0x00
-#define ESDCFG0_ROF	0x04
-#define ESDCTL1_ROF	0x08
-#define ESDCFG1_ROF	0x0C
-#define ESDMISC_ROF	0x10
diff --git a/arch/arm/include/asm/arch-mx27/clock.h b/arch/arm/include/asm/arch-mx27/clock.h
deleted file mode 100644
index 7e9c7aa..0000000
--- a/arch/arm/include/asm/arch-mx27/clock.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- *
- * (c) 2009 Ilya Yanok, Emcraft Systems <yanok@emcraft.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __ASM_ARCH_CLOCK_H
-#define __ASM_ARCH_CLOCK_H
-unsigned int imx_decode_pll(unsigned int pll, unsigned int f_ref);
-
-ulong imx_get_mpllclk(void);
-ulong imx_get_armclk(void);
-ulong imx_get_spllclk(void);
-ulong imx_get_fclk(void);
-ulong imx_get_hclk(void);
-ulong imx_get_bclk(void);
-ulong imx_get_perclk1(void);
-ulong imx_get_perclk2(void);
-ulong imx_get_perclk3(void);
-ulong imx_get_ahbclk(void);
-
-#define imx_get_uartclk imx_get_perclk1
-#define imx_get_fecclk imx_get_ahbclk
-
-#endif /* __ASM_ARCH_CLOCK_H */
diff --git a/arch/arm/include/asm/arch-mx27/imx-regs.h b/arch/arm/include/asm/arch-mx27/imx-regs.h
deleted file mode 100644
index 8f40aa7..0000000
--- a/arch/arm/include/asm/arch-mx27/imx-regs.h
+++ /dev/null
@@ -1,526 +0,0 @@
-/*
- * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
- * (c) 2009 Ilya Yanok, Emcraft Systems <yanok@emcraft.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef _IMX_REGS_H
-#define _IMX_REGS_H
-
-#ifndef __ASSEMBLY__
-
-extern void imx_gpio_mode (int gpio_mode);
-
-#ifdef CONFIG_MXC_UART
-extern void mx27_uart_init_pins(void);
-#endif /* CONFIG_MXC_UART */
-
-#ifdef CONFIG_FEC_MXC
-extern void mx27_fec_init_pins(void);
-extern void imx_get_mac_from_fuse(unsigned char *mac);
-#endif /* CONFIG_FEC_MXC */
-
-#ifdef CONFIG_MXC_MMC
-extern void mx27_sd1_init_pins(void);
-extern void mx27_sd2_init_pins(void);
-#endif /* CONFIG_MXC_MMC */
-
-/* AIPI */
-struct aipi_regs {
-	u32 psr0;
-	u32 psr1;
-};
-
-/* System Control */
-struct system_control_regs {
-	u32 res[5];
-	u32 fmcr;
-	u32 gpcr;
-	u32 wbcr;
-	u32 dscr1;
-	u32 dscr2;
-	u32 dscr3;
-	u32 dscr4;
-	u32 dscr5;
-	u32 dscr6;
-	u32 dscr7;
-	u32 dscr8;
-	u32 dscr9;
-	u32 dscr10;
-	u32 dscr11;
-	u32 dscr12;
-	u32 dscr13;
-	u32 pscr;
-	u32 pmcr;
-	u32 res1;
-	u32 dcvr0;
-	u32 dcvr1;
-	u32 dcvr2;
-	u32 dcvr3;
-};
-
-/* Chip Select Registers */
-struct weim_regs {
-	u32 cs0u;	/* Chip Select 0 Upper Register */
-	u32 cs0l;	/* Chip Select 0 Lower Register */
-	u32 cs0a;	/* Chip Select 0 Addition Register */
-	u32 pad0;
-	u32 cs1u;	/* Chip Select 1 Upper Register */
-	u32 cs1l;	/* Chip Select 1 Lower Register */
-	u32 cs1a;	/* Chip Select 1 Addition Register */
-	u32 pad1;
-	u32 cs2u;	/* Chip Select 2 Upper Register */
-	u32 cs2l;	/* Chip Select 2 Lower Register */
-	u32 cs2a;	/* Chip Select 2 Addition Register */
-	u32 pad2;
-	u32 cs3u;	/* Chip Select 3 Upper Register */
-	u32 cs3l;	/* Chip Select 3 Lower Register */
-	u32 cs3a;	/* Chip Select 3 Addition Register */
-	u32 pad3;
-	u32 cs4u;	/* Chip Select 4 Upper Register */
-	u32 cs4l;	/* Chip Select 4 Lower Register */
-	u32 cs4a;	/* Chip Select 4 Addition Register */
-	u32 pad4;
-	u32 cs5u;	/* Chip Select 5 Upper Register */
-	u32 cs5l;	/* Chip Select 5 Lower Register */
-	u32 cs5a;	/* Chip Select 5 Addition Register */
-	u32 pad5;
-	u32 eim;	/* WEIM Configuration Register */
-};
-
-/* SDRAM Controller registers */
-struct esdramc_regs {
-/* Enhanced SDRAM Control Register 0 */
-	u32 esdctl0;
-/* Enhanced SDRAM Configuration Register 0 */
-	u32 esdcfg0;
-/* Enhanced SDRAM Control Register 1 */
-	u32 esdctl1;
-/* Enhanced SDRAM Configuration Register 1 */
-	u32 esdcfg1;
-/* Enhanced SDRAM Miscellanious Register */
-	u32 esdmisc;
-};
-
-/* Watchdog Registers*/
-struct wdog_regs {
-	u32 wcr;
-	u32 wsr;
-	u32 wstr;
-};
-
-/* PLL registers */
-struct pll_regs {
-	u32 cscr;	/* Clock Source Control Register */
-	u32 mpctl0;	/* MCU PLL Control Register 0 */
-	u32 mpctl1;	/* MCU PLL Control Register 1 */
-	u32 spctl0;	/* System PLL Control Register 0 */
-	u32 spctl1;	/* System PLL Control Register 1 */
-	u32 osc26mctl;	/* Oscillator 26M Register */
-	u32 pcdr0;	/* Peripheral Clock Divider Register 0 */
-	u32 pcdr1;	/* Peripheral Clock Divider Register 1 */
-	u32 pccr0;	/* Peripheral Clock Control Register 0 */
-	u32 pccr1;	/* Peripheral Clock Control Register 1 */
-	u32 ccsr;	/* Clock Control Status Register */
-};
-
-/*
- * Definitions for the clocksource registers
- */
-struct gpt_regs {
-	u32 gpt_tctl;
-	u32 gpt_tprer;
-	u32 gpt_tcmp;
-	u32 gpt_tcr;
-	u32 gpt_tcn;
-	u32 gpt_tstat;
-};
-
-/*
- *  GPIO Module and I/O Multiplexer
- */
-#define PORTA 0
-#define PORTB 1
-#define PORTC 2
-#define PORTD 3
-#define PORTE 4
-#define PORTF 5
-
-struct gpio_regs {
-	struct {
-		u32 ddir;
-		u32 ocr1;
-		u32 ocr2;
-		u32 iconfa1;
-		u32 iconfa2;
-		u32 iconfb1;
-		u32 iconfb2;
-		u32 dr;
-		u32 gius;
-		u32 ssr;
-		u32 icr1;
-		u32 icr2;
-		u32 imr;
-		u32 isr;
-		u32 gpr;
-		u32 swr;
-		u32 puen;
-		u32 res[0x2f];
-	} port[6];
-};
-
-/* IIM Control Registers */
-struct iim_regs {
-	u32 iim_stat;
-	u32 iim_statm;
-	u32 iim_err;
-	u32 iim_emask;
-	u32 iim_fctl;
-	u32 iim_ua;
-	u32 iim_la;
-	u32 iim_sdat;
-	u32 iim_prev;
-	u32 iim_srev;
-	u32 iim_prog_p;
-	u32 iim_scs0;
-	u32 iim_scs1;
-	u32 iim_scs2;
-	u32 iim_scs3;
-	u32 res[0x1f1];
-	struct fuse_bank {
-		u32 fuse_regs[0x20];
-		u32 fuse_rsvd[0xe0];
-	} bank[1];
-};
-
-struct fuse_bank0_regs {
-	u32 fuse0_3[5];
-	u32 mac_addr[6];
-	u32 fuse10_31[0x16];
-};
-
-#endif
-
-#define IMX_IO_BASE		0x10000000
-
-#define IMX_AIPI1_BASE		(0x00000 + IMX_IO_BASE)
-#define IMX_WDT_BASE		(0x02000 + IMX_IO_BASE)
-#define IMX_TIM1_BASE		(0x03000 + IMX_IO_BASE)
-#define IMX_TIM2_BASE		(0x04000 + IMX_IO_BASE)
-#define IMX_TIM3_BASE		(0x05000 + IMX_IO_BASE)
-#define IMX_UART1_BASE		(0x0a000 + IMX_IO_BASE)
-#define IMX_UART2_BASE		(0x0b000 + IMX_IO_BASE)
-#define IMX_UART3_BASE		(0x0c000 + IMX_IO_BASE)
-#define IMX_UART4_BASE		(0x0d000 + IMX_IO_BASE)
-#define IMX_I2C1_BASE		(0x12000 + IMX_IO_BASE)
-#define IMX_GPIO_BASE		(0x15000 + IMX_IO_BASE)
-#define IMX_TIM4_BASE		(0x19000 + IMX_IO_BASE)
-#define IMX_TIM5_BASE		(0x1a000 + IMX_IO_BASE)
-#define IMX_UART5_BASE		(0x1b000 + IMX_IO_BASE)
-#define IMX_UART6_BASE		(0x1c000 + IMX_IO_BASE)
-#define IMX_I2C2_BASE		(0x1D000 + IMX_IO_BASE)
-#define IMX_TIM6_BASE		(0x1f000 + IMX_IO_BASE)
-#define IMX_AIPI2_BASE		(0x20000 + IMX_IO_BASE)
-#define IMX_PLL_BASE		(0x27000 + IMX_IO_BASE)
-#define IMX_SYSTEM_CTL_BASE	(0x27800 + IMX_IO_BASE)
-#define IMX_IIM_BASE		(0x28000 + IMX_IO_BASE)
-#define IMX_FEC_BASE		(0x2b000 + IMX_IO_BASE)
-
-#define IMX_ESD_BASE		(0xD8001000)
-#define IMX_WEIM_BASE		(0xD8002000)
-
-/* FMCR System Control bit definition*/
-#define UART4_RXD_CTL	(1 << 25)
-#define UART4_RTS_CTL	(1 << 24)
-#define KP_COL6_CTL	(1 << 18)
-#define KP_ROW7_CTL	(1 << 17)
-#define KP_ROW6_CTL	(1 << 16)
-#define PC_WAIT_B_CTL	(1 << 14)
-#define PC_READY_CTL	(1 << 13)
-#define PC_VS1_CTL	(1 << 12)
-#define PC_VS2_CTL	(1 << 11)
-#define PC_BVD1_CTL	(1 << 10)
-#define PC_BVD2_CTL	(1 << 9)
-#define IOS16_CTL	(1 << 8)
-#define NF_FMS		(1 << 5)
-#define NF_16BIT_SEL	(1 << 4)
-#define SLCDC_SEL	(1 << 2)
-#define SDCS1_SEL	(1 << 1)
-#define SDCS0_SEL	(1 << 0)
-
-
-/* important definition of some bits of WCR */
-#define WCR_WDE 0x04
-
-#define CSCR_MPEN		(1 << 0)
-#define CSCR_SPEN		(1 << 1)
-#define CSCR_FPM_EN		(1 << 2)
-#define CSCR_OSC26M_DIS		(1 << 3)
-#define CSCR_OSC26M_DIV1P5	(1 << 4)
-#define CSCR_AHB_DIV
-#define CSCR_ARM_DIV
-#define CSCR_ARM_SRC_MPLL	(1 << 15)
-#define CSCR_MCU_SEL		(1 << 16)
-#define CSCR_SP_SEL		(1 << 17)
-#define CSCR_MPLL_RESTART	(1 << 18)
-#define CSCR_SPLL_RESTART	(1 << 19)
-#define CSCR_MSHC_SEL		(1 << 20)
-#define CSCR_H264_SEL		(1 << 21)
-#define CSCR_SSI1_SEL		(1 << 22)
-#define CSCR_SSI2_SEL		(1 << 23)
-#define CSCR_SD_CNT
-#define CSCR_USB_DIV
-#define CSCR_UPDATE_DIS		(1 << 31)
-
-#define MPCTL1_BRMO		(1 << 6)
-#define MPCTL1_LF		(1 << 15)
-
-#define PCCR0_SSI2_EN	(1 << 0)
-#define PCCR0_SSI1_EN	(1 << 1)
-#define PCCR0_SLCDC_EN	(1 << 2)
-#define PCCR0_SDHC3_EN	(1 << 3)
-#define PCCR0_SDHC2_EN	(1 << 4)
-#define PCCR0_SDHC1_EN	(1 << 5)
-#define PCCR0_SDC_EN	(1 << 6)
-#define PCCR0_SAHARA_EN	(1 << 7)
-#define PCCR0_RTIC_EN	(1 << 8)
-#define PCCR0_RTC_EN	(1 << 9)
-#define PCCR0_PWM_EN	(1 << 11)
-#define PCCR0_OWIRE_EN	(1 << 12)
-#define PCCR0_MSHC_EN	(1 << 13)
-#define PCCR0_LCDC_EN	(1 << 14)
-#define PCCR0_KPP_EN	(1 << 15)
-#define PCCR0_IIM_EN	(1 << 16)
-#define PCCR0_I2C2_EN	(1 << 17)
-#define PCCR0_I2C1_EN	(1 << 18)
-#define PCCR0_GPT6_EN	(1 << 19)
-#define PCCR0_GPT5_EN	(1 << 20)
-#define PCCR0_GPT4_EN	(1 << 21)
-#define PCCR0_GPT3_EN	(1 << 22)
-#define PCCR0_GPT2_EN	(1 << 23)
-#define PCCR0_GPT1_EN	(1 << 24)
-#define PCCR0_GPIO_EN	(1 << 25)
-#define PCCR0_FEC_EN	(1 << 26)
-#define PCCR0_EMMA_EN	(1 << 27)
-#define PCCR0_DMA_EN	(1 << 28)
-#define PCCR0_CSPI3_EN	(1 << 29)
-#define PCCR0_CSPI2_EN	(1 << 30)
-#define PCCR0_CSPI1_EN	(1 << 31)
-
-#define PCCR1_MSHC_BAUDEN	(1 << 2)
-#define PCCR1_NFC_BAUDEN	(1 << 3)
-#define PCCR1_SSI2_BAUDEN	(1 << 4)
-#define PCCR1_SSI1_BAUDEN	(1 << 5)
-#define PCCR1_H264_BAUDEN	(1 << 6)
-#define PCCR1_PERCLK4_EN	(1 << 7)
-#define PCCR1_PERCLK3_EN	(1 << 8)
-#define PCCR1_PERCLK2_EN	(1 << 9)
-#define PCCR1_PERCLK1_EN	(1 << 10)
-#define PCCR1_HCLK_USB		(1 << 11)
-#define PCCR1_HCLK_SLCDC	(1 << 12)
-#define PCCR1_HCLK_SAHARA	(1 << 13)
-#define PCCR1_HCLK_RTIC		(1 << 14)
-#define PCCR1_HCLK_LCDC		(1 << 15)
-#define PCCR1_HCLK_H264		(1 << 16)
-#define PCCR1_HCLK_FEC		(1 << 17)
-#define PCCR1_HCLK_EMMA		(1 << 18)
-#define PCCR1_HCLK_EMI		(1 << 19)
-#define PCCR1_HCLK_DMA		(1 << 20)
-#define PCCR1_HCLK_CSI		(1 << 21)
-#define PCCR1_HCLK_BROM		(1 << 22)
-#define PCCR1_HCLK_ATA		(1 << 23)
-#define PCCR1_WDT_EN		(1 << 24)
-#define PCCR1_USB_EN		(1 << 25)
-#define PCCR1_UART6_EN		(1 << 26)
-#define PCCR1_UART5_EN		(1 << 27)
-#define PCCR1_UART4_EN		(1 << 28)
-#define PCCR1_UART3_EN		(1 << 29)
-#define PCCR1_UART2_EN		(1 << 30)
-#define PCCR1_UART1_EN		(1 << 31)
-
-/* SDRAM Controller registers bitfields */
-#define ESDCTL_PRCT(x)		(((x) & 0x3f) << 0)
-#define ESDCTL_BL		(1 << 7)
-#define ESDCTL_FP		(1 << 8)
-#define ESDCTL_PWDT(x)		(((x) & 3) << 10)
-#define ESDCTL_SREFR(x)		(((x) & 7) << 13)
-#define ESDCTL_DSIZ_16_UPPER	(0 << 16)
-#define ESDCTL_DSIZ_16_LOWER	(1 << 16)
-#define ESDCTL_DSIZ_32		(2 << 16)
-#define ESDCTL_COL8		(0 << 20)
-#define ESDCTL_COL9		(1 << 20)
-#define ESDCTL_COL10		(2 << 20)
-#define ESDCTL_ROW11		(0 << 24)
-#define ESDCTL_ROW12		(1 << 24)
-#define ESDCTL_ROW13		(2 << 24)
-#define ESDCTL_ROW14		(3 << 24)
-#define ESDCTL_ROW15		(4 << 24)
-#define ESDCTL_SP		(1 << 27)
-#define ESDCTL_SMODE_NORMAL	(0 << 28)
-#define ESDCTL_SMODE_PRECHARGE	(1 << 28)
-#define ESDCTL_SMODE_AUTO_REF	(2 << 28)
-#define ESDCTL_SMODE_LOAD_MODE	(3 << 28)
-#define ESDCTL_SMODE_MAN_REF	(4 << 28)
-#define ESDCTL_SDE		(1 << 31)
-
-#define ESDCFG_TRC(x)		(((x) & 0xf) << 0)
-#define ESDCFG_TRCD(x)		(((x) & 0x7) << 4)
-#define ESDCFG_TCAS(x)		(((x) & 0x3) << 8)
-#define ESDCFG_TRRD(x)		(((x) & 0x3) << 10)
-#define ESDCFG_TRAS(x)		(((x) & 0x7) << 12)
-#define ESDCFG_TWR		(1 << 15)
-#define ESDCFG_TMRD(x)		(((x) & 0x3) << 16)
-#define ESDCFG_TRP(x)		(((x) & 0x3) << 18)
-#define ESDCFG_TWTR		(1 << 20)
-#define ESDCFG_TXP(x)		(((x) & 0x3) << 21)
-
-#define ESDMISC_RST		(1 << 1)
-#define ESDMISC_MDDREN		(1 << 2)
-#define ESDMISC_MDDR_DL_RST	(1 << 3)
-#define ESDMISC_MDDR_MDIS	(1 << 4)
-#define ESDMISC_LHD		(1 << 5)
-#define ESDMISC_MA10_SHARE	(1 << 6)
-#define ESDMISC_SDRAM_RDY	(1 << 31)
-
-#define PC5_PF_I2C2_DATA	(GPIO_PORTC | GPIO_OUT | GPIO_PF | 5)
-#define PC6_PF_I2C2_CLK		(GPIO_PORTC | GPIO_OUT | GPIO_PF | 6)
-#define PC7_PF_USBOTG_DATA5	(GPIO_PORTC | GPIO_OUT | GPIO_PF | 7)
-#define PC8_PF_USBOTG_DATA6	(GPIO_PORTC | GPIO_OUT | GPIO_PF | 8)
-#define PC9_PF_USBOTG_DATA0	(GPIO_PORTC | GPIO_OUT | GPIO_PF | 9)
-#define PC10_PF_USBOTG_DATA2	(GPIO_PORTC | GPIO_OUT | GPIO_PF | 10)
-#define PC11_PF_USBOTG_DATA1	(GPIO_PORTC | GPIO_OUT | GPIO_PF | 11)
-#define PC12_PF_USBOTG_DATA4	(GPIO_PORTC | GPIO_OUT | GPIO_PF | 12)
-#define PC13_PF_USBOTG_DATA3	(GPIO_PORTC | GPIO_OUT | GPIO_PF | 13)
-
-#define PD0_AIN_FEC_TXD0	(GPIO_PORTD | GPIO_OUT | GPIO_AIN | 0)
-#define PD1_AIN_FEC_TXD1	(GPIO_PORTD | GPIO_OUT | GPIO_AIN | 1)
-#define PD2_AIN_FEC_TXD2	(GPIO_PORTD | GPIO_OUT | GPIO_AIN | 2)
-#define PD3_AIN_FEC_TXD3	(GPIO_PORTD | GPIO_OUT | GPIO_AIN | 3)
-#define PD4_AOUT_FEC_RX_ER	(GPIO_PORTD | GPIO_IN | GPIO_AOUT | 4)
-#define PD5_AOUT_FEC_RXD1	(GPIO_PORTD | GPIO_IN | GPIO_AOUT | 5)
-#define PD6_AOUT_FEC_RXD2	(GPIO_PORTD | GPIO_IN | GPIO_AOUT | 6)
-#define PD7_AOUT_FEC_RXD3	(GPIO_PORTD | GPIO_IN | GPIO_AOUT | 7)
-#define PD8_AF_FEC_MDIO		(GPIO_PORTD | GPIO_IN | GPIO_AF | 8)
-#define PD9_AIN_FEC_MDC		(GPIO_PORTD | GPIO_OUT | GPIO_AIN | 9)
-#define PD10_AOUT_FEC_CRS	(GPIO_PORTD | GPIO_IN | GPIO_AOUT | 10)
-#define PD11_AOUT_FEC_TX_CLK	(GPIO_PORTD | GPIO_IN | GPIO_AOUT | 11)
-#define PD12_AOUT_FEC_RXD0	(GPIO_PORTD | GPIO_IN | GPIO_AOUT | 12)
-#define PD13_AOUT_FEC_RX_DV	(GPIO_PORTD | GPIO_IN | GPIO_AOUT | 13)
-#define PD14_AOUT_FEC_CLR	(GPIO_PORTD | GPIO_IN | GPIO_AOUT | 14)
-#define PD15_AOUT_FEC_COL	(GPIO_PORTD | GPIO_IN | GPIO_AOUT | 15)
-#define PD16_AIN_FEC_TX_ER	(GPIO_PORTD | GPIO_OUT | GPIO_AIN | 16)
-#define PF23_AIN_FEC_TX_EN	(GPIO_PORTF | GPIO_OUT | GPIO_AIN | 23)
-
-#define PE0_PF_USBOTG_NXT	(GPIO_PORTE | GPIO_OUT | GPIO_PF | 0)
-#define PE1_PF_USBOTG_STP	(GPIO_PORTE | GPIO_OUT | GPIO_PF | 1)
-#define PE2_PF_USBOTG_DIR	(GPIO_PORTE | GPIO_OUT | GPIO_PF | 2)
-#define PE3_PF_UART2_CTS	(GPIO_PORTE | GPIO_OUT | GPIO_PF | 3)
-#define PE4_PF_UART2_RTS	(GPIO_PORTE | GPIO_IN  | GPIO_PF | 4)
-#define PE6_PF_UART2_TXD	(GPIO_PORTE | GPIO_OUT | GPIO_PF | 6)
-#define PE7_PF_UART2_RXD	(GPIO_PORTE | GPIO_IN  | GPIO_PF | 7)
-#define PE8_PF_UART3_TXD	(GPIO_PORTE | GPIO_OUT | GPIO_PF | 8)
-#define PE9_PF_UART3_RXD	(GPIO_PORTE | GPIO_IN  | GPIO_PF | 9)
-#define PE10_PF_UART3_CTS	(GPIO_PORTE | GPIO_OUT | GPIO_PF | 10)
-#define PE11_PF_UART3_RTS	(GPIO_PORTE | GPIO_IN  | GPIO_PF | 11)
-#define PE12_PF_UART1_TXD	(GPIO_PORTE | GPIO_OUT | GPIO_PF | 12)
-#define PE13_PF_UART1_RXD	(GPIO_PORTE | GPIO_IN  | GPIO_PF | 13)
-#define PE14_PF_UART1_CTS	(GPIO_PORTE | GPIO_OUT | GPIO_PF | 14)
-#define PE15_PF_UART1_RTS	(GPIO_PORTE | GPIO_IN  | GPIO_PF | 15)
-#define PE18_PF_SD1_D0		(GPIO_PORTE | GPIO_PF | 18)
-#define PE19_PF_SD1_D1		(GPIO_PORTE | GPIO_PF | 19)
-#define PE20_PF_SD1_D2		(GPIO_PORTE | GPIO_PF | 20)
-#define PE21_PF_SD1_D3		(GPIO_PORTE | GPIO_PF | 21)
-#define PE22_PF_SD1_CMD		(GPIO_PORTE | GPIO_PF | 22)
-#define PE23_PF_SD1_CLK		(GPIO_PORTE | GPIO_PF | 23)
-#define PB4_PF_SD2_D0		(GPIO_PORTB | GPIO_PF | 4)
-#define PB5_PF_SD2_D1		(GPIO_PORTB | GPIO_PF | 5)
-#define PB6_PF_SD2_D2		(GPIO_PORTB | GPIO_PF | 6)
-#define PB7_PF_SD2_D3		(GPIO_PORTB | GPIO_PF | 7)
-#define PB8_PF_SD2_CMD		(GPIO_PORTB | GPIO_PF | 8)
-#define PB9_PF_SD2_CLK		(GPIO_PORTB | GPIO_PF | 9)
-#define PD17_PF_I2C_DATA	(GPIO_PORTD | GPIO_OUT | GPIO_PF | 17)
-#define PD18_PF_I2C_CLK		(GPIO_PORTD | GPIO_OUT | GPIO_PF | 18)
-#define PE24_PF_USBOTG_CLK	(GPIO_PORTE | GPIO_OUT | GPIO_PF | 24)
-#define PE25_PF_USBOTG_DATA7	(GPIO_PORTE | GPIO_OUT | GPIO_PF | 25)
-
-/* Clocksource Bitfields */
-#define TCTL_SWR	(1 << 15)	/* Software reset */
-#define TCTL_FRR	(1 << 8)	/* Freerun / restart */
-#define TCTL_CAP	(3 << 6)	/* Capture Edge */
-#define TCTL_OM		(1 << 5)	/* output mode */
-#define TCTL_IRQEN	(1 << 4)	/* interrupt enable */
-#define TCTL_CLKSOURCE	1		/* Clock source bit position */
-#define TCTL_TEN	1		/* Timer enable */
-#define TPRER_PRES	0xff		/* Prescale */
-#define TSTAT_CAPT	(1 << 1)	/* Capture event */
-#define TSTAT_COMP	1		/* Compare event */
-
-#define GPIO_PIN_MASK	0x1f
-
-#define GPIO_PORT_SHIFT	5
-#define GPIO_PORT_MASK	(0x7 << GPIO_PORT_SHIFT)
-
-#define GPIO_PORTA	(PORTA << GPIO_PORT_SHIFT)
-#define GPIO_PORTB	(PORTB << GPIO_PORT_SHIFT)
-#define GPIO_PORTC	(PORTC << GPIO_PORT_SHIFT)
-#define GPIO_PORTD	(PORTD << GPIO_PORT_SHIFT)
-#define GPIO_PORTE	(PORTE << GPIO_PORT_SHIFT)
-#define GPIO_PORTF	(PORTF << GPIO_PORT_SHIFT)
-
-#define GPIO_OUT	(1 << 8)
-#define GPIO_IN		(0 << 8)
-#define GPIO_PUEN	(1 << 9)
-
-#define GPIO_PF		(1 << 10)
-#define GPIO_AF		(1 << 11)
-
-#define GPIO_OCR_SHIFT	12
-#define GPIO_OCR_MASK	(3 << GPIO_OCR_SHIFT)
-#define GPIO_AIN	(0 << GPIO_OCR_SHIFT)
-#define GPIO_BIN	(1 << GPIO_OCR_SHIFT)
-#define GPIO_CIN	(2 << GPIO_OCR_SHIFT)
-#define GPIO_GPIO	(3 << GPIO_OCR_SHIFT)
-
-#define GPIO_AOUT_SHIFT	14
-#define GPIO_AOUT_MASK	(3 << GPIO_AOUT_SHIFT)
-#define GPIO_AOUT	(0 << GPIO_AOUT_SHIFT)
-#define GPIO_AOUT_ISR	(1 << GPIO_AOUT_SHIFT)
-#define GPIO_AOUT_0	(2 << GPIO_AOUT_SHIFT)
-#define GPIO_AOUT_1	(3 << GPIO_AOUT_SHIFT)
-
-#define GPIO_BOUT_SHIFT	16
-#define GPIO_BOUT_MASK	(3 << GPIO_BOUT_SHIFT)
-#define GPIO_BOUT	(0 << GPIO_BOUT_SHIFT)
-#define GPIO_BOUT_ISR	(1 << GPIO_BOUT_SHIFT)
-#define GPIO_BOUT_0	(2 << GPIO_BOUT_SHIFT)
-#define GPIO_BOUT_1	(3 << GPIO_BOUT_SHIFT)
-
-#define IIM_STAT_BUSY	(1 << 7)
-#define IIM_STAT_PRGD	(1 << 1)
-#define IIM_STAT_SNSD	(1 << 0)
-#define IIM_ERR_PRGE	(1 << 7)
-#define IIM_ERR_WPE	(1 << 6)
-#define IIM_ERR_OPE	(1 << 5)
-#define IIM_ERR_RPE	(1 << 4)
-#define IIM_ERR_WLRE	(1 << 3)
-#define IIM_ERR_SNSE	(1 << 2)
-#define IIM_ERR_PARITYE	(1 << 1)
-
-#endif				/* _IMX_REGS_H */
diff --git a/arch/arm/include/asm/arch-mx27/mxcmmc.h b/arch/arm/include/asm/arch-mx27/mxcmmc.h
deleted file mode 100644
index 4c83cc7..0000000
--- a/arch/arm/include/asm/arch-mx27/mxcmmc.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- *  Copyright (c) 2009 Ilya Yanok <yanok@emcraft.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef ASM_ARCH_MXCMMC_H
-#define ASM_ARCH_MXCMMC_H
-
-int mxc_mmc_init(bd_t *bis);
-
-#endif
diff --git a/arch/arm/include/asm/arch-mx31/mx31-regs.h b/arch/arm/include/asm/arch-mx31/mx31-regs.h
deleted file mode 100644
index 105f7d8..0000000
--- a/arch/arm/include/asm/arch-mx31/mx31-regs.h
+++ /dev/null
@@ -1,742 +0,0 @@
-/*
- *
- * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __ASM_ARCH_MX31_REGS_H
-#define __ASM_ARCH_MX31_REGS_H
-
-#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
-#include <asm/types.h>
-
-/* Clock control module registers */
-struct clock_control_regs {
-	u32 ccmr;
-	u32 pdr0;
-	u32 pdr1;
-	u32 rcsr;
-	u32 mpctl;
-	u32 upctl;
-	u32 spctl;
-	u32 cosr;
-	u32 cgr0;
-	u32 cgr1;
-	u32 cgr2;
-	u32 wimr0;
-	u32 ldc;
-	u32 dcvr0;
-	u32 dcvr1;
-	u32 dcvr2;
-	u32 dcvr3;
-	u32 ltr0;
-	u32 ltr1;
-	u32 ltr2;
-	u32 ltr3;
-	u32 ltbr0;
-	u32 ltbr1;
-	u32 pmcr0;
-	u32 pmcr1;
-	u32 pdr2;
-};
-
-/* GPIO Registers */
-struct gpio_regs {
-	u32	gpio_dr;
-	u32	gpio_dir;
-	u32	gpio_psr;
-};
-
-struct cspi_regs {
-	u32 rxdata;
-	u32 txdata;
-	u32 ctrl;
-	u32 intr;
-	u32 dma;
-	u32 stat;
-	u32 period;
-	u32 test;
-};
-
-#define IOMUX_PADNUM_MASK	0x1ff
-#define IOMUX_PIN(gpionum, padnum) ((padnum) & IOMUX_PADNUM_MASK)
-
-/*
- * various IOMUX pad functions
- */
-enum iomux_pad_config {
-	PAD_CTL_NOLOOPBACK	= 0x0 << 9,
-	PAD_CTL_LOOPBACK	= 0x1 << 9,
-	PAD_CTL_PKE_NONE	= 0x0 << 8,
-	PAD_CTL_PKE_ENABLE	= 0x1 << 8,
-	PAD_CTL_PUE_KEEPER	= 0x0 << 7,
-	PAD_CTL_PUE_PUD		= 0x1 << 7,
-	PAD_CTL_100K_PD		= 0x0 << 5,
-	PAD_CTL_100K_PU		= 0x1 << 5,
-	PAD_CTL_47K_PU		= 0x2 << 5,
-	PAD_CTL_22K_PU		= 0x3 << 5,
-	PAD_CTL_HYS_CMOS	= 0x0 << 4,
-	PAD_CTL_HYS_SCHMITZ	= 0x1 << 4,
-	PAD_CTL_ODE_CMOS	= 0x0 << 3,
-	PAD_CTL_ODE_OpenDrain	= 0x1 << 3,
-	PAD_CTL_DRV_NORMAL	= 0x0 << 1,
-	PAD_CTL_DRV_HIGH	= 0x1 << 1,
-	PAD_CTL_DRV_MAX		= 0x2 << 1,
-	PAD_CTL_SRE_SLOW	= 0x0 << 0,
-	PAD_CTL_SRE_FAST	= 0x1 << 0
-};
-
-/*
- * This enumeration is constructed based on the Section
- * "sw_pad_ctl & sw_mux_ctl details" of the MX31 IC Spec. Each enumerated
- * value is constructed based on the rules described above.
- */
-
-enum iomux_pins {
-	MX31_PIN_TTM_PAD	= IOMUX_PIN(0xff,   0),
-	MX31_PIN_CSPI3_SPI_RDY	= IOMUX_PIN(0xff,   1),
-	MX31_PIN_CSPI3_SCLK	= IOMUX_PIN(0xff,   2),
-	MX31_PIN_CSPI3_MISO	= IOMUX_PIN(0xff,   3),
-	MX31_PIN_CSPI3_MOSI	= IOMUX_PIN(0xff,   4),
-	MX31_PIN_CLKSS		= IOMUX_PIN(0xff,   5),
-	MX31_PIN_CE_CONTROL	= IOMUX_PIN(0xff,   6),
-	MX31_PIN_ATA_RESET_B	= IOMUX_PIN(95,     7),
-	MX31_PIN_ATA_DMACK	= IOMUX_PIN(94,     8),
-	MX31_PIN_ATA_DIOW	= IOMUX_PIN(93,     9),
-	MX31_PIN_ATA_DIOR	= IOMUX_PIN(92,    10),
-	MX31_PIN_ATA_CS1	= IOMUX_PIN(91,    11),
-	MX31_PIN_ATA_CS0	= IOMUX_PIN(90,    12),
-	MX31_PIN_SD1_DATA3	= IOMUX_PIN(63,    13),
-	MX31_PIN_SD1_DATA2	= IOMUX_PIN(62,    14),
-	MX31_PIN_SD1_DATA1	= IOMUX_PIN(61,    15),
-	MX31_PIN_SD1_DATA0	= IOMUX_PIN(60,    16),
-	MX31_PIN_SD1_CLK	= IOMUX_PIN(59,    17),
-	MX31_PIN_SD1_CMD	= IOMUX_PIN(58,    18),
-	MX31_PIN_D3_SPL		= IOMUX_PIN(0xff,  19),
-	MX31_PIN_D3_CLS		= IOMUX_PIN(0xff,  20),
-	MX31_PIN_D3_REV		= IOMUX_PIN(0xff,  21),
-	MX31_PIN_CONTRAST	= IOMUX_PIN(0xff,  22),
-	MX31_PIN_VSYNC3		= IOMUX_PIN(0xff,  23),
-	MX31_PIN_READ		= IOMUX_PIN(0xff,  24),
-	MX31_PIN_WRITE		= IOMUX_PIN(0xff,  25),
-	MX31_PIN_PAR_RS		= IOMUX_PIN(0xff,  26),
-	MX31_PIN_SER_RS		= IOMUX_PIN(89,    27),
-	MX31_PIN_LCS1		= IOMUX_PIN(88,    28),
-	MX31_PIN_LCS0		= IOMUX_PIN(87,    29),
-	MX31_PIN_SD_D_CLK	= IOMUX_PIN(86,    30),
-	MX31_PIN_SD_D_IO	= IOMUX_PIN(85,    31),
-	MX31_PIN_SD_D_I		= IOMUX_PIN(84,    32),
-	MX31_PIN_DRDY0		= IOMUX_PIN(0xff,  33),
-	MX31_PIN_FPSHIFT	= IOMUX_PIN(0xff,  34),
-	MX31_PIN_HSYNC		= IOMUX_PIN(0xff,  35),
-	MX31_PIN_VSYNC0		= IOMUX_PIN(0xff,  36),
-	MX31_PIN_LD17		= IOMUX_PIN(0xff,  37),
-	MX31_PIN_LD16		= IOMUX_PIN(0xff,  38),
-	MX31_PIN_LD15		= IOMUX_PIN(0xff,  39),
-	MX31_PIN_LD14		= IOMUX_PIN(0xff,  40),
-	MX31_PIN_LD13		= IOMUX_PIN(0xff,  41),
-	MX31_PIN_LD12		= IOMUX_PIN(0xff,  42),
-	MX31_PIN_LD11		= IOMUX_PIN(0xff,  43),
-	MX31_PIN_LD10		= IOMUX_PIN(0xff,  44),
-	MX31_PIN_LD9		= IOMUX_PIN(0xff,  45),
-	MX31_PIN_LD8		= IOMUX_PIN(0xff,  46),
-	MX31_PIN_LD7		= IOMUX_PIN(0xff,  47),
-	MX31_PIN_LD6		= IOMUX_PIN(0xff,  48),
-	MX31_PIN_LD5		= IOMUX_PIN(0xff,  49),
-	MX31_PIN_LD4		= IOMUX_PIN(0xff,  50),
-	MX31_PIN_LD3		= IOMUX_PIN(0xff,  51),
-	MX31_PIN_LD2		= IOMUX_PIN(0xff,  52),
-	MX31_PIN_LD1		= IOMUX_PIN(0xff,  53),
-	MX31_PIN_LD0		= IOMUX_PIN(0xff,  54),
-	MX31_PIN_USBH2_DATA1	= IOMUX_PIN(0xff,  55),
-	MX31_PIN_USBH2_DATA0	= IOMUX_PIN(0xff,  56),
-	MX31_PIN_USBH2_NXT	= IOMUX_PIN(0xff,  57),
-	MX31_PIN_USBH2_STP	= IOMUX_PIN(0xff,  58),
-	MX31_PIN_USBH2_DIR	= IOMUX_PIN(0xff,  59),
-	MX31_PIN_USBH2_CLK	= IOMUX_PIN(0xff,  60),
-	MX31_PIN_USBOTG_DATA7	= IOMUX_PIN(0xff,  61),
-	MX31_PIN_USBOTG_DATA6	= IOMUX_PIN(0xff,  62),
-	MX31_PIN_USBOTG_DATA5	= IOMUX_PIN(0xff,  63),
-	MX31_PIN_USBOTG_DATA4	= IOMUX_PIN(0xff,  64),
-	MX31_PIN_USBOTG_DATA3	= IOMUX_PIN(0xff,  65),
-	MX31_PIN_USBOTG_DATA2	= IOMUX_PIN(0xff,  66),
-	MX31_PIN_USBOTG_DATA1	= IOMUX_PIN(0xff,  67),
-	MX31_PIN_USBOTG_DATA0	= IOMUX_PIN(0xff,  68),
-	MX31_PIN_USBOTG_NXT	= IOMUX_PIN(0xff,  69),
-	MX31_PIN_USBOTG_STP	= IOMUX_PIN(0xff,  70),
-	MX31_PIN_USBOTG_DIR	= IOMUX_PIN(0xff,  71),
-	MX31_PIN_USBOTG_CLK	= IOMUX_PIN(0xff,  72),
-	MX31_PIN_USB_BYP	= IOMUX_PIN(31,    73),
-	MX31_PIN_USB_OC		= IOMUX_PIN(30,    74),
-	MX31_PIN_USB_PWR	= IOMUX_PIN(29,    75),
-	MX31_PIN_SJC_MOD	= IOMUX_PIN(0xff,  76),
-	MX31_PIN_DE_B		= IOMUX_PIN(0xff,  77),
-	MX31_PIN_TRSTB		= IOMUX_PIN(0xff,  78),
-	MX31_PIN_TDO		= IOMUX_PIN(0xff,  79),
-	MX31_PIN_TDI		= IOMUX_PIN(0xff,  80),
-	MX31_PIN_TMS		= IOMUX_PIN(0xff,  81),
-	MX31_PIN_TCK		= IOMUX_PIN(0xff,  82),
-	MX31_PIN_RTCK		= IOMUX_PIN(0xff,  83),
-	MX31_PIN_KEY_COL7	= IOMUX_PIN(57,    84),
-	MX31_PIN_KEY_COL6	= IOMUX_PIN(56,    85),
-	MX31_PIN_KEY_COL5	= IOMUX_PIN(55,    86),
-	MX31_PIN_KEY_COL4	= IOMUX_PIN(54,    87),
-	MX31_PIN_KEY_COL3	= IOMUX_PIN(0xff,  88),
-	MX31_PIN_KEY_COL2	= IOMUX_PIN(0xff,  89),
-	MX31_PIN_KEY_COL1	= IOMUX_PIN(0xff,  90),
-	MX31_PIN_KEY_COL0	= IOMUX_PIN(0xff,  91),
-	MX31_PIN_KEY_ROW7	= IOMUX_PIN(53,    92),
-	MX31_PIN_KEY_ROW6	= IOMUX_PIN(52,    93),
-	MX31_PIN_KEY_ROW5	= IOMUX_PIN(51,    94),
-	MX31_PIN_KEY_ROW4	= IOMUX_PIN(50,    95),
-	MX31_PIN_KEY_ROW3	= IOMUX_PIN(0xff,  96),
-	MX31_PIN_KEY_ROW2	= IOMUX_PIN(0xff,  97),
-	MX31_PIN_KEY_ROW1	= IOMUX_PIN(0xff,  98),
-	MX31_PIN_KEY_ROW0	= IOMUX_PIN(0xff,  99),
-	MX31_PIN_BATT_LINE	= IOMUX_PIN(49,   100),
-	MX31_PIN_CTS2		= IOMUX_PIN(0xff, 101),
-	MX31_PIN_RTS2		= IOMUX_PIN(0xff, 102),
-	MX31_PIN_TXD2		= IOMUX_PIN(28,   103),
-	MX31_PIN_RXD2		= IOMUX_PIN(27,   104),
-	MX31_PIN_DTR_DCE2	= IOMUX_PIN(48,   105),
-	MX31_PIN_DCD_DTE1	= IOMUX_PIN(47,   106),
-	MX31_PIN_RI_DTE1	= IOMUX_PIN(46,   107),
-	MX31_PIN_DSR_DTE1	= IOMUX_PIN(45,   108),
-	MX31_PIN_DTR_DTE1	= IOMUX_PIN(44,   109),
-	MX31_PIN_DCD_DCE1	= IOMUX_PIN(43,   110),
-	MX31_PIN_RI_DCE1	= IOMUX_PIN(42,   111),
-	MX31_PIN_DSR_DCE1	= IOMUX_PIN(41,   112),
-	MX31_PIN_DTR_DCE1	= IOMUX_PIN(40,   113),
-	MX31_PIN_CTS1		= IOMUX_PIN(39,   114),
-	MX31_PIN_RTS1		= IOMUX_PIN(38,   115),
-	MX31_PIN_TXD1		= IOMUX_PIN(37,   116),
-	MX31_PIN_RXD1		= IOMUX_PIN(36,   117),
-	MX31_PIN_CSPI2_SPI_RDY	= IOMUX_PIN(0xff, 118),
-	MX31_PIN_CSPI2_SCLK	= IOMUX_PIN(0xff, 119),
-	MX31_PIN_CSPI2_SS2	= IOMUX_PIN(0xff, 120),
-	MX31_PIN_CSPI2_SS1	= IOMUX_PIN(0xff, 121),
-	MX31_PIN_CSPI2_SS0	= IOMUX_PIN(0xff, 122),
-	MX31_PIN_CSPI2_MISO	= IOMUX_PIN(0xff, 123),
-	MX31_PIN_CSPI2_MOSI	= IOMUX_PIN(0xff, 124),
-	MX31_PIN_CSPI1_SPI_RDY	= IOMUX_PIN(0xff, 125),
-	MX31_PIN_CSPI1_SCLK	= IOMUX_PIN(0xff, 126),
-	MX31_PIN_CSPI1_SS2	= IOMUX_PIN(0xff, 127),
-	MX31_PIN_CSPI1_SS1	= IOMUX_PIN(0xff, 128),
-	MX31_PIN_CSPI1_SS0	= IOMUX_PIN(0xff, 129),
-	MX31_PIN_CSPI1_MISO	= IOMUX_PIN(0xff, 130),
-	MX31_PIN_CSPI1_MOSI	= IOMUX_PIN(0xff, 131),
-	MX31_PIN_SFS6		= IOMUX_PIN(26,   132),
-	MX31_PIN_SCK6		= IOMUX_PIN(25,   133),
-	MX31_PIN_SRXD6		= IOMUX_PIN(24,   134),
-	MX31_PIN_STXD6		= IOMUX_PIN(23,   135),
-	MX31_PIN_SFS5		= IOMUX_PIN(0xff, 136),
-	MX31_PIN_SCK5		= IOMUX_PIN(0xff, 137),
-	MX31_PIN_SRXD5		= IOMUX_PIN(22,   138),
-	MX31_PIN_STXD5		= IOMUX_PIN(21,   139),
-	MX31_PIN_SFS4		= IOMUX_PIN(0xff, 140),
-	MX31_PIN_SCK4		= IOMUX_PIN(0xff, 141),
-	MX31_PIN_SRXD4		= IOMUX_PIN(20,   142),
-	MX31_PIN_STXD4		= IOMUX_PIN(19,   143),
-	MX31_PIN_SFS3		= IOMUX_PIN(0xff, 144),
-	MX31_PIN_SCK3		= IOMUX_PIN(0xff, 145),
-	MX31_PIN_SRXD3		= IOMUX_PIN(18,   146),
-	MX31_PIN_STXD3		= IOMUX_PIN(17,   147),
-	MX31_PIN_I2C_DAT	= IOMUX_PIN(0xff, 148),
-	MX31_PIN_I2C_CLK	= IOMUX_PIN(0xff, 149),
-	MX31_PIN_CSI_PIXCLK	= IOMUX_PIN(83,   150),
-	MX31_PIN_CSI_HSYNC	= IOMUX_PIN(82,   151),
-	MX31_PIN_CSI_VSYNC	= IOMUX_PIN(81,   152),
-	MX31_PIN_CSI_MCLK	= IOMUX_PIN(80,   153),
-	MX31_PIN_CSI_D15	= IOMUX_PIN(79,   154),
-	MX31_PIN_CSI_D14	= IOMUX_PIN(78,   155),
-	MX31_PIN_CSI_D13	= IOMUX_PIN(77,   156),
-	MX31_PIN_CSI_D12	= IOMUX_PIN(76,   157),
-	MX31_PIN_CSI_D11	= IOMUX_PIN(75,   158),
-	MX31_PIN_CSI_D10	= IOMUX_PIN(74,   159),
-	MX31_PIN_CSI_D9		= IOMUX_PIN(73,   160),
-	MX31_PIN_CSI_D8		= IOMUX_PIN(72,   161),
-	MX31_PIN_CSI_D7		= IOMUX_PIN(71,   162),
-	MX31_PIN_CSI_D6		= IOMUX_PIN(70,   163),
-	MX31_PIN_CSI_D5		= IOMUX_PIN(69,   164),
-	MX31_PIN_CSI_D4		= IOMUX_PIN(68,   165),
-	MX31_PIN_M_GRANT	= IOMUX_PIN(0xff, 166),
-	MX31_PIN_M_REQUEST	= IOMUX_PIN(0xff, 167),
-	MX31_PIN_PC_POE		= IOMUX_PIN(0xff, 168),
-	MX31_PIN_PC_RW_B	= IOMUX_PIN(0xff, 169),
-	MX31_PIN_IOIS16		= IOMUX_PIN(0xff, 170),
-	MX31_PIN_PC_RST		= IOMUX_PIN(0xff, 171),
-	MX31_PIN_PC_BVD2	= IOMUX_PIN(0xff, 172),
-	MX31_PIN_PC_BVD1	= IOMUX_PIN(0xff, 173),
-	MX31_PIN_PC_VS2		= IOMUX_PIN(0xff, 174),
-	MX31_PIN_PC_VS1		= IOMUX_PIN(0xff, 175),
-	MX31_PIN_PC_PWRON	= IOMUX_PIN(0xff, 176),
-	MX31_PIN_PC_READY	= IOMUX_PIN(0xff, 177),
-	MX31_PIN_PC_WAIT_B	= IOMUX_PIN(0xff, 178),
-	MX31_PIN_PC_CD2_B	= IOMUX_PIN(0xff, 179),
-	MX31_PIN_PC_CD1_B	= IOMUX_PIN(0xff, 180),
-	MX31_PIN_D0		= IOMUX_PIN(0xff, 181),
-	MX31_PIN_D1		= IOMUX_PIN(0xff, 182),
-	MX31_PIN_D2		= IOMUX_PIN(0xff, 183),
-	MX31_PIN_D3		= IOMUX_PIN(0xff, 184),
-	MX31_PIN_D4		= IOMUX_PIN(0xff, 185),
-	MX31_PIN_D5		= IOMUX_PIN(0xff, 186),
-	MX31_PIN_D6		= IOMUX_PIN(0xff, 187),
-	MX31_PIN_D7		= IOMUX_PIN(0xff, 188),
-	MX31_PIN_D8		= IOMUX_PIN(0xff, 189),
-	MX31_PIN_D9		= IOMUX_PIN(0xff, 190),
-	MX31_PIN_D10		= IOMUX_PIN(0xff, 191),
-	MX31_PIN_D11		= IOMUX_PIN(0xff, 192),
-	MX31_PIN_D12		= IOMUX_PIN(0xff, 193),
-	MX31_PIN_D13		= IOMUX_PIN(0xff, 194),
-	MX31_PIN_D14		= IOMUX_PIN(0xff, 195),
-	MX31_PIN_D15		= IOMUX_PIN(0xff, 196),
-	MX31_PIN_NFRB		= IOMUX_PIN(16,   197),
-	MX31_PIN_NFCE_B		= IOMUX_PIN(15,   198),
-	MX31_PIN_NFWP_B		= IOMUX_PIN(14,   199),
-	MX31_PIN_NFCLE		= IOMUX_PIN(13,   200),
-	MX31_PIN_NFALE		= IOMUX_PIN(12,   201),
-	MX31_PIN_NFRE_B		= IOMUX_PIN(11,   202),
-	MX31_PIN_NFWE_B		= IOMUX_PIN(10,   203),
-	MX31_PIN_SDQS3		= IOMUX_PIN(0xff, 204),
-	MX31_PIN_SDQS2		= IOMUX_PIN(0xff, 205),
-	MX31_PIN_SDQS1		= IOMUX_PIN(0xff, 206),
-	MX31_PIN_SDQS0		= IOMUX_PIN(0xff, 207),
-	MX31_PIN_SDCLK_B	= IOMUX_PIN(0xff, 208),
-	MX31_PIN_SDCLK		= IOMUX_PIN(0xff, 209),
-	MX31_PIN_SDCKE1		= IOMUX_PIN(0xff, 210),
-	MX31_PIN_SDCKE0		= IOMUX_PIN(0xff, 211),
-	MX31_PIN_SDWE		= IOMUX_PIN(0xff, 212),
-	MX31_PIN_CAS		= IOMUX_PIN(0xff, 213),
-	MX31_PIN_RAS		= IOMUX_PIN(0xff, 214),
-	MX31_PIN_RW		= IOMUX_PIN(0xff, 215),
-	MX31_PIN_BCLK		= IOMUX_PIN(0xff, 216),
-	MX31_PIN_LBA		= IOMUX_PIN(0xff, 217),
-	MX31_PIN_ECB		= IOMUX_PIN(0xff, 218),
-	MX31_PIN_CS5		= IOMUX_PIN(0xff, 219),
-	MX31_PIN_CS4		= IOMUX_PIN(0xff, 220),
-	MX31_PIN_CS3		= IOMUX_PIN(0xff, 221),
-	MX31_PIN_CS2		= IOMUX_PIN(0xff, 222),
-	MX31_PIN_CS1		= IOMUX_PIN(0xff, 223),
-	MX31_PIN_CS0		= IOMUX_PIN(0xff, 224),
-	MX31_PIN_OE		= IOMUX_PIN(0xff, 225),
-	MX31_PIN_EB1		= IOMUX_PIN(0xff, 226),
-	MX31_PIN_EB0		= IOMUX_PIN(0xff, 227),
-	MX31_PIN_DQM3		= IOMUX_PIN(0xff, 228),
-	MX31_PIN_DQM2		= IOMUX_PIN(0xff, 229),
-	MX31_PIN_DQM1		= IOMUX_PIN(0xff, 230),
-	MX31_PIN_DQM0		= IOMUX_PIN(0xff, 231),
-	MX31_PIN_SD31		= IOMUX_PIN(0xff, 232),
-	MX31_PIN_SD30		= IOMUX_PIN(0xff, 233),
-	MX31_PIN_SD29		= IOMUX_PIN(0xff, 234),
-	MX31_PIN_SD28		= IOMUX_PIN(0xff, 235),
-	MX31_PIN_SD27		= IOMUX_PIN(0xff, 236),
-	MX31_PIN_SD26		= IOMUX_PIN(0xff, 237),
-	MX31_PIN_SD25		= IOMUX_PIN(0xff, 238),
-	MX31_PIN_SD24		= IOMUX_PIN(0xff, 239),
-	MX31_PIN_SD23		= IOMUX_PIN(0xff, 240),
-	MX31_PIN_SD22		= IOMUX_PIN(0xff, 241),
-	MX31_PIN_SD21		= IOMUX_PIN(0xff, 242),
-	MX31_PIN_SD20		= IOMUX_PIN(0xff, 243),
-	MX31_PIN_SD19		= IOMUX_PIN(0xff, 244),
-	MX31_PIN_SD18		= IOMUX_PIN(0xff, 245),
-	MX31_PIN_SD17		= IOMUX_PIN(0xff, 246),
-	MX31_PIN_SD16		= IOMUX_PIN(0xff, 247),
-	MX31_PIN_SD15		= IOMUX_PIN(0xff, 248),
-	MX31_PIN_SD14		= IOMUX_PIN(0xff, 249),
-	MX31_PIN_SD13		= IOMUX_PIN(0xff, 250),
-	MX31_PIN_SD12		= IOMUX_PIN(0xff, 251),
-	MX31_PIN_SD11		= IOMUX_PIN(0xff, 252),
-	MX31_PIN_SD10		= IOMUX_PIN(0xff, 253),
-	MX31_PIN_SD9		= IOMUX_PIN(0xff, 254),
-	MX31_PIN_SD8		= IOMUX_PIN(0xff, 255),
-	MX31_PIN_SD7		= IOMUX_PIN(0xff, 256),
-	MX31_PIN_SD6		= IOMUX_PIN(0xff, 257),
-	MX31_PIN_SD5		= IOMUX_PIN(0xff, 258),
-	MX31_PIN_SD4		= IOMUX_PIN(0xff, 259),
-	MX31_PIN_SD3		= IOMUX_PIN(0xff, 260),
-	MX31_PIN_SD2		= IOMUX_PIN(0xff, 261),
-	MX31_PIN_SD1		= IOMUX_PIN(0xff, 262),
-	MX31_PIN_SD0		= IOMUX_PIN(0xff, 263),
-	MX31_PIN_SDBA0		= IOMUX_PIN(0xff, 264),
-	MX31_PIN_SDBA1		= IOMUX_PIN(0xff, 265),
-	MX31_PIN_A25		= IOMUX_PIN(0xff, 266),
-	MX31_PIN_A24		= IOMUX_PIN(0xff, 267),
-	MX31_PIN_A23		= IOMUX_PIN(0xff, 268),
-	MX31_PIN_A22		= IOMUX_PIN(0xff, 269),
-	MX31_PIN_A21		= IOMUX_PIN(0xff, 270),
-	MX31_PIN_A20		= IOMUX_PIN(0xff, 271),
-	MX31_PIN_A19		= IOMUX_PIN(0xff, 272),
-	MX31_PIN_A18		= IOMUX_PIN(0xff, 273),
-	MX31_PIN_A17		= IOMUX_PIN(0xff, 274),
-	MX31_PIN_A16		= IOMUX_PIN(0xff, 275),
-	MX31_PIN_A14		= IOMUX_PIN(0xff, 276),
-	MX31_PIN_A15		= IOMUX_PIN(0xff, 277),
-	MX31_PIN_A13		= IOMUX_PIN(0xff, 278),
-	MX31_PIN_A12		= IOMUX_PIN(0xff, 279),
-	MX31_PIN_A11		= IOMUX_PIN(0xff, 280),
-	MX31_PIN_MA10		= IOMUX_PIN(0xff, 281),
-	MX31_PIN_A10		= IOMUX_PIN(0xff, 282),
-	MX31_PIN_A9		= IOMUX_PIN(0xff, 283),
-	MX31_PIN_A8		= IOMUX_PIN(0xff, 284),
-	MX31_PIN_A7		= IOMUX_PIN(0xff, 285),
-	MX31_PIN_A6		= IOMUX_PIN(0xff, 286),
-	MX31_PIN_A5		= IOMUX_PIN(0xff, 287),
-	MX31_PIN_A4		= IOMUX_PIN(0xff, 288),
-	MX31_PIN_A3		= IOMUX_PIN(0xff, 289),
-	MX31_PIN_A2		= IOMUX_PIN(0xff, 290),
-	MX31_PIN_A1		= IOMUX_PIN(0xff, 291),
-	MX31_PIN_A0		= IOMUX_PIN(0xff, 292),
-	MX31_PIN_VPG1		= IOMUX_PIN(0xff, 293),
-	MX31_PIN_VPG0		= IOMUX_PIN(0xff, 294),
-	MX31_PIN_DVFS1		= IOMUX_PIN(0xff, 295),
-	MX31_PIN_DVFS0		= IOMUX_PIN(0xff, 296),
-	MX31_PIN_VSTBY		= IOMUX_PIN(0xff, 297),
-	MX31_PIN_POWER_FAIL	= IOMUX_PIN(0xff, 298),
-	MX31_PIN_CKIL		= IOMUX_PIN(0xff, 299),
-	MX31_PIN_BOOT_MODE4	= IOMUX_PIN(0xff, 300),
-	MX31_PIN_BOOT_MODE3	= IOMUX_PIN(0xff, 301),
-	MX31_PIN_BOOT_MODE2	= IOMUX_PIN(0xff, 302),
-	MX31_PIN_BOOT_MODE1	= IOMUX_PIN(0xff, 303),
-	MX31_PIN_BOOT_MODE0	= IOMUX_PIN(0xff, 304),
-	MX31_PIN_CLKO		= IOMUX_PIN(0xff, 305),
-	MX31_PIN_POR_B		= IOMUX_PIN(0xff, 306),
-	MX31_PIN_RESET_IN_B	= IOMUX_PIN(0xff, 307),
-	MX31_PIN_CKIH		= IOMUX_PIN(0xff, 308),
-	MX31_PIN_SIMPD0		= IOMUX_PIN(35,   309),
-	MX31_PIN_SRX0		= IOMUX_PIN(34,   310),
-	MX31_PIN_STX0		= IOMUX_PIN(33,   311),
-	MX31_PIN_SVEN0		= IOMUX_PIN(32,   312),
-	MX31_PIN_SRST0		= IOMUX_PIN(67,   313),
-	MX31_PIN_SCLK0		= IOMUX_PIN(66,   314),
-	MX31_PIN_GPIO3_1	= IOMUX_PIN(65,   315),
-	MX31_PIN_GPIO3_0	= IOMUX_PIN(64,   316),
-	MX31_PIN_GPIO1_6	= IOMUX_PIN(6,    317),
-	MX31_PIN_GPIO1_5	= IOMUX_PIN(5,    318),
-	MX31_PIN_GPIO1_4	= IOMUX_PIN(4,    319),
-	MX31_PIN_GPIO1_3	= IOMUX_PIN(3,    320),
-	MX31_PIN_GPIO1_2	= IOMUX_PIN(2,    321),
-	MX31_PIN_GPIO1_1	= IOMUX_PIN(1,    322),
-	MX31_PIN_GPIO1_0	= IOMUX_PIN(0,    323),
-	MX31_PIN_PWMO		= IOMUX_PIN(9,    324),
-	MX31_PIN_WATCHDOG_RST	= IOMUX_PIN(0xff, 325),
-	MX31_PIN_COMPARE	= IOMUX_PIN(8,    326),
-	MX31_PIN_CAPTURE	= IOMUX_PIN(7,    327),
-};
-
-/* Bit definitions for RCSR register in CCM */
-#define CCM_RCSR_NF16B	(1 << 31)
-#define CCM_RCSR_NFMS	(1 << 30)
-
-#endif
-
-#define __REG(x)     (*((volatile u32 *)(x)))
-#define __REG16(x)   (*((volatile u16 *)(x)))
-#define __REG8(x)    (*((volatile u8 *)(x)))
-
-#define CCM_BASE	0x53f80000
-#define CCM_CCMR	(CCM_BASE + 0x00)
-#define CCM_PDR0	(CCM_BASE + 0x04)
-#define CCM_PDR1	(CCM_BASE + 0x08)
-#define CCM_RCSR	(CCM_BASE + 0x0c)
-#define CCM_MPCTL	(CCM_BASE + 0x10)
-#define CCM_UPCTL	(CCM_BASE + 0x14)
-#define CCM_SPCTL	(CCM_BASE + 0x18)
-#define CCM_COSR	(CCM_BASE + 0x1C)
-#define CCM_CGR0	(CCM_BASE + 0x20)
-#define CCM_CGR1	(CCM_BASE + 0x24)
-#define CCM_CGR2	(CCM_BASE + 0x28)
-
-#define CCMR_MDS	(1 << 7)
-#define CCMR_SBYCS	(1 << 4)
-#define CCMR_MPE	(1 << 3)
-#define CCMR_PRCS_MASK	(3 << 1)
-#define CCMR_FPM	(1 << 1)
-#define CCMR_CKIH	(2 << 1)
-
-#define PDR0_CSI_PODF(x)	(((x) & 0x1ff) << 23)
-#define PDR0_PER_PODF(x)	(((x) & 0x1f) << 16)
-#define PDR0_HSP_PODF(x)	(((x) & 0x7) << 11)
-#define PDR0_NFC_PODF(x)	(((x) & 0x7) << 8)
-#define PDR0_IPG_PODF(x)	(((x) & 0x3) << 6)
-#define PDR0_MAX_PODF(x)	(((x) & 0x7) << 3)
-#define PDR0_MCU_PODF(x)	((x) & 0x7)
-
-#define PLL_PD(x)		(((x) & 0xf) << 26)
-#define PLL_MFD(x)		(((x) & 0x3ff) << 16)
-#define PLL_MFI(x)		(((x) & 0xf) << 10)
-#define PLL_MFN(x)		(((x) & 0x3ff) << 0)
-
-#define WEIM_ESDCTL0	0xB8001000
-#define WEIM_ESDCFG0	0xB8001004
-#define WEIM_ESDCTL1	0xB8001008
-#define WEIM_ESDCFG1	0xB800100C
-#define WEIM_ESDMISC	0xB8001010
-
-#define ESDCTL_SDE			(1 << 31)
-#define ESDCTL_CMD_RW			(0 << 28)
-#define ESDCTL_CMD_PRECHARGE		(1 << 28)
-#define ESDCTL_CMD_AUTOREFRESH		(2 << 28)
-#define ESDCTL_CMD_LOADMODEREG		(3 << 28)
-#define ESDCTL_CMD_MANUALREFRESH	(4 << 28)
-#define ESDCTL_ROW_13			(2 << 24)
-#define ESDCTL_ROW(x)			((x) << 24)
-#define ESDCTL_COL_9			(1 << 20)
-#define ESDCTL_COL(x)			((x) << 20)
-#define ESDCTL_DSIZ(x)			((x) << 16)
-#define ESDCTL_SREFR(x)			((x) << 13)
-#define ESDCTL_PWDT(x)			((x) << 10)
-#define ESDCTL_FP(x)			((x) << 8)
-#define ESDCTL_BL(x)			((x) << 7)
-#define ESDCTL_PRCT(x)			((x) << 0)
-
-#define WEIM_BASE	0xb8002000
-#define CSCR_U(x)	(WEIM_BASE + (x) * 0x10)
-#define CSCR_L(x)	(WEIM_BASE + 4 + (x) * 0x10)
-#define CSCR_A(x)	(WEIM_BASE + 8 + (x) * 0x10)
-
-#define IOMUXC_BASE	0x43FAC000
-#define IOMUXC_GPR	(IOMUXC_BASE + 0x8)
-#define IOMUXC_SW_MUX_CTL(x)	(IOMUXC_BASE + 0xc + (x) * 4)
-#define IOMUXC_SW_PAD_CTL(x)	(IOMUXC_BASE + 0x154 + (x) * 4)
-
-#define IPU_BASE		0x53fc0000
-#define IPU_CONF		IPU_BASE
-
-#define IPU_CONF_PXL_ENDIAN	(1<<8)
-#define IPU_CONF_DU_EN		(1<<7)
-#define IPU_CONF_DI_EN		(1<<6)
-#define IPU_CONF_ADC_EN		(1<<5)
-#define IPU_CONF_SDC_EN		(1<<4)
-#define IPU_CONF_PF_EN		(1<<3)
-#define IPU_CONF_ROT_EN		(1<<2)
-#define IPU_CONF_IC_EN		(1<<1)
-#define IPU_CONF_SCI_EN		(1<<0)
-
-#define ARM_PPMRR		0x40000015
-
-#define WDOG_BASE		0x53FDC000
-
-/*
- * GPIO
- */
-#define GPIO1_BASE_ADDR	0x53FCC000
-#define GPIO2_BASE_ADDR	0x53FD0000
-#define GPIO3_BASE_ADDR	0x53FA4000
-#define GPIO_DR		0x00000000	/* data register */
-#define GPIO_GDIR	0x00000004	/* direction register */
-#define GPIO_PSR	0x00000008	/* pad status register */
-
-/*
- * Signal Multiplexing (IOMUX)
- */
-
-/* bits in the SW_MUX_CTL registers */
-#define MUX_CTL_OUT_GPIO_DR	(0 << 4)
-#define MUX_CTL_OUT_FUNC	(1 << 4)
-#define MUX_CTL_OUT_ALT1	(2 << 4)
-#define MUX_CTL_OUT_ALT2	(3 << 4)
-#define MUX_CTL_OUT_ALT3	(4 << 4)
-#define MUX_CTL_OUT_ALT4	(5 << 4)
-#define MUX_CTL_OUT_ALT5	(6 << 4)
-#define MUX_CTL_OUT_ALT6	(7 << 4)
-#define MUX_CTL_IN_NONE		(0 << 0)
-#define MUX_CTL_IN_GPIO		(1 << 0)
-#define MUX_CTL_IN_FUNC		(2 << 0)
-#define MUX_CTL_IN_ALT1		(4 << 0)
-#define MUX_CTL_IN_ALT2		(8 << 0)
-
-#define MUX_CTL_FUNC		(MUX_CTL_OUT_FUNC | MUX_CTL_IN_FUNC)
-#define MUX_CTL_ALT1		(MUX_CTL_OUT_ALT1 | MUX_CTL_IN_ALT1)
-#define MUX_CTL_ALT2		(MUX_CTL_OUT_ALT2 | MUX_CTL_IN_ALT2)
-#define MUX_CTL_GPIO		(MUX_CTL_OUT_GPIO_DR | MUX_CTL_IN_GPIO)
-
-/* Register offsets based on IOMUXC_BASE */
-/* 0x00 .. 0x7b */
-#define MUX_CTL_USBH2_DATA1	0x40
-#define MUX_CTL_USBH2_DIR	0x44
-#define MUX_CTL_USBH2_STP	0x45
-#define MUX_CTL_USBH2_NXT	0x46
-#define MUX_CTL_USBH2_DATA0	0x47
-#define MUX_CTL_USBH2_CLK	0x4B
-#define MUX_CTL_RTS1		0x7c
-#define MUX_CTL_CTS1		0x7d
-#define MUX_CTL_DTR_DCE1	0x7e
-#define MUX_CTL_DSR_DCE1	0x7f
-#define MUX_CTL_CSPI2_SCLK	0x80
-#define MUX_CTL_CSPI2_SPI_RDY	0x81
-#define MUX_CTL_RXD1		0x82
-#define MUX_CTL_TXD1		0x83
-#define MUX_CTL_CSPI2_MISO	0x84
-#define MUX_CTL_CSPI2_SS0	0x85
-#define MUX_CTL_CSPI2_SS1	0x86
-#define MUX_CTL_CSPI2_SS2	0x87
-#define MUX_CTL_CSPI1_SS2	0x88
-#define MUX_CTL_CSPI1_SCLK	0x89
-#define MUX_CTL_CSPI1_SPI_RDY	0x8a
-#define MUX_CTL_CSPI2_MOSI	0x8b
-#define MUX_CTL_CSPI1_MOSI	0x8c
-#define MUX_CTL_CSPI1_MISO	0x8d
-#define MUX_CTL_CSPI1_SS0	0x8e
-#define MUX_CTL_CSPI1_SS1	0x8f
-#define MUX_CTL_STXD6		0x90
-#define MUX_CTL_SRXD6		0x91
-#define MUX_CTL_SCK6		0x92
-#define MUX_CTL_SFS6		0x93
-
-#define MUX_CTL_STXD3		0x9C
-#define MUX_CTL_SRXD3		0x9D
-#define MUX_CTL_SCK3		0x9E
-#define MUX_CTL_SFS3		0x9F
-
-#define MUX_CTL_NFC_WP		0xD0
-#define MUX_CTL_NFC_CE		0xD1
-#define MUX_CTL_NFC_RB		0xD2
-#define MUX_CTL_NFC_WE		0xD4
-#define MUX_CTL_NFC_RE		0xD5
-#define MUX_CTL_NFC_ALE		0xD6
-#define MUX_CTL_NFC_CLE		0xD7
-
-
-#define MUX_CTL_CAPTURE		0x150
-#define MUX_CTL_COMPARE		0x151
-
-/*
- * Helper macros for the MUX_[contact name]__[pin function] macros
- */
-#define IOMUX_MODE_POS 9
-#define IOMUX_MODE(contact, mode) (((mode) << IOMUX_MODE_POS) | (contact))
-
-/*
- * These macros can be used in mx31_gpio_mux() and have the form
- * MUX_[contact name]__[pin function]
- */
-#define MUX_RXD1__UART1_RXD_MUX	IOMUX_MODE(MUX_CTL_RXD1, MUX_CTL_FUNC)
-#define MUX_TXD1__UART1_TXD_MUX	IOMUX_MODE(MUX_CTL_TXD1, MUX_CTL_FUNC)
-#define MUX_RTS1__UART1_RTS_B	IOMUX_MODE(MUX_CTL_RTS1, MUX_CTL_FUNC)
-#define MUX_CTS1__UART1_CTS_B	IOMUX_MODE(MUX_CTL_CTS1, MUX_CTL_FUNC)
-
-#define MUX_CSPI2_SS0__CSPI2_SS0_B IOMUX_MODE(MUX_CTL_CSPI2_SS0, MUX_CTL_FUNC)
-#define MUX_CSPI2_SS1__CSPI2_SS1_B IOMUX_MODE(MUX_CTL_CSPI2_SS1, MUX_CTL_FUNC)
-#define MUX_CSPI2_SS2__CSPI2_SS2_B IOMUX_MODE(MUX_CTL_CSPI2_SS2, MUX_CTL_FUNC)
-#define MUX_CSPI2_MOSI__CSPI2_MOSI IOMUX_MODE(MUX_CTL_CSPI2_MOSI, MUX_CTL_FUNC)
-#define MUX_CSPI2_MISO__CSPI2_MISO IOMUX_MODE(MUX_CTL_CSPI2_MISO, MUX_CTL_FUNC)
-#define MUX_CSPI2_SPI_RDY__CSPI2_DATAREADY_B \
-	IOMUX_MODE(MUX_CTL_CSPI2_SPI_RDY, MUX_CTL_FUNC)
-#define MUX_CSPI2_SCLK__CSPI2_CLK IOMUX_MODE(MUX_CTL_CSPI2_SCLK, MUX_CTL_FUNC)
-
-#define MUX_CSPI1_SS0__CSPI1_SS0_B IOMUX_MODE(MUX_CTL_CSPI1_SS0, MUX_CTL_FUNC)
-#define MUX_CSPI1_SS1__CSPI1_SS1_B IOMUX_MODE(MUX_CTL_CSPI1_SS1, MUX_CTL_FUNC)
-#define MUX_CSPI1_SS2__CSPI1_SS2_B IOMUX_MODE(MUX_CTL_CSPI1_SS2, MUX_CTL_FUNC)
-#define MUX_CSPI1_MOSI__CSPI1_MOSI IOMUX_MODE(MUX_CTL_CSPI1_MOSI, MUX_CTL_FUNC)
-#define MUX_CSPI1_MISO__CSPI1_MISO IOMUX_MODE(MUX_CTL_CSPI1_MISO, MUX_CTL_FUNC)
-#define MUX_CSPI1_SPI_RDY__CSPI1_DATAREADY_B \
-	IOMUX_MODE(MUX_CTL_CSPI1_SPI_RDY, MUX_CTL_FUNC)
-#define MUX_CSPI1_SCLK__CSPI1_CLK IOMUX_MODE(MUX_CTL_CSPI1_SCLK, MUX_CTL_FUNC)
-
-#define MUX_CSPI2_MOSI__I2C2_SCL IOMUX_MODE(MUX_CTL_CSPI2_MOSI, MUX_CTL_ALT1)
-#define MUX_CSPI2_MISO__I2C2_SDA IOMUX_MODE(MUX_CTL_CSPI2_MISO, MUX_CTL_ALT1)
-
-/* PAD control registers for SDR/DDR */
-#define IOMUXC_SW_PAD_CTL_SDCKE1_SDCLK_SDCLK_B	(IOMUXC_BASE + 0x26C)
-#define IOMUXC_SW_PAD_CTL_CAS_SDWE_SDCKE0	(IOMUXC_BASE + 0x270)
-#define IOMUXC_SW_PAD_CTL_BCLK_RW_RAS		(IOMUXC_BASE + 0x274)
-#define IOMUXC_SW_PAD_CTL_CS5_ECB_LBA		(IOMUXC_BASE + 0x278)
-#define IOMUXC_SW_PAD_CTL_CS2_CS3_CS4		(IOMUXC_BASE + 0x27C)
-#define IOMUXC_SW_PAD_CTL_OE_CS0_CS1		(IOMUXC_BASE + 0x280)
-#define IOMUXC_SW_PAD_CTL_DQM3_EB0_EB1		(IOMUXC_BASE + 0x284)
-#define IOMUXC_SW_PAD_CTL_DQM0_DQM1_DQM2	(IOMUXC_BASE + 0x288)
-#define IOMUXC_SW_PAD_CTL_SD29_SD30_SD31	(IOMUXC_BASE + 0x28C)
-#define IOMUXC_SW_PAD_CTL_SD26_SD27_SD28	(IOMUXC_BASE + 0x290)
-#define IOMUXC_SW_PAD_CTL_SD23_SD24_SD25	(IOMUXC_BASE + 0x294)
-#define IOMUXC_SW_PAD_CTL_SD20_SD21_SD22	(IOMUXC_BASE + 0x298)
-#define IOMUXC_SW_PAD_CTL_SD17_SD18_SD19	(IOMUXC_BASE + 0x29C)
-#define IOMUXC_SW_PAD_CTL_SD14_SD15_SD16	(IOMUXC_BASE + 0x2A0)
-#define IOMUXC_SW_PAD_CTL_SD11_SD12_SD13	(IOMUXC_BASE + 0x2A4)
-#define IOMUXC_SW_PAD_CTL_SD8_SD9_SD10		(IOMUXC_BASE + 0x2A8)
-#define IOMUXC_SW_PAD_CTL_SD5_SD6_SD7		(IOMUXC_BASE + 0x2AC)
-#define IOMUXC_SW_PAD_CTL_SD2_SD3_SD4		(IOMUXC_BASE + 0x2B0)
-#define IOMUXC_SW_PAD_CTL_SDBA0_SD0_SD1		(IOMUXC_BASE + 0x2B4)
-#define IOMUXC_SW_PAD_CTL_A24_A25_SDBA1		(IOMUXC_BASE + 0x2B8)
-#define IOMUXC_SW_PAD_CTL_A21_A22_A23		(IOMUXC_BASE + 0x2BC)
-#define IOMUXC_SW_PAD_CTL_A18_A19_A20		(IOMUXC_BASE + 0x2C0)
-#define IOMUXC_SW_PAD_CTL_A15_A16_A17		(IOMUXC_BASE + 0x2C4)
-#define IOMUXC_SW_PAD_CTL_A12_A13_A14		(IOMUXC_BASE + 0x2C8)
-#define IOMUXC_SW_PAD_CTL_A10_MA10_A11		(IOMUXC_BASE + 0x2CC)
-#define IOMUXC_SW_PAD_CTL_A7_A8_A9		(IOMUXC_BASE + 0x2D0)
-#define IOMUXC_SW_PAD_CTL_A4_A5_A6		(IOMUXC_BASE + 0x2D4)
-#define IOMUXC_SW_PAD_CTL_A1_A2_A3		(IOMUXC_BASE + 0x2D8)
-#define IOMUXC_SW_PAD_CTL_VPG0_VPG1_A0		(IOMUXC_BASE + 0x2DC)
-
-/*
- * Memory regions and CS
- */
-#define IPU_MEM_BASE	0x70000000
-#define CSD0_BASE	0x80000000
-#define CSD1_BASE	0x90000000
-#define CS0_BASE	0xA0000000
-#define CS1_BASE	0xA8000000
-#define CS2_BASE	0xB0000000
-#define CS3_BASE	0xB2000000
-#define CS4_BASE	0xB4000000
-#define CS4_PSRAM_BASE	0xB5000000
-#define CS5_BASE	0xB6000000
-#define PCMCIA_MEM_BASE	0xC0000000
-
-/*
- * NAND controller
- */
-#define NFC_BASE_ADDR	0xB8000000
-
-/*
- * Internal RAM (16KB)
- */
-#define	IRAM_BASE_ADDR	0x1FFFC000
-#define IRAM_SIZE	(16 * 1024)
-
-#define MX31_AIPS1_BASE_ADDR	0x43f00000
-#define MX31_OTG_BASE_ADDR	(MX31_AIPS1_BASE_ADDR + 0x88000)
-
-/* USB portsc */
-/* values for portsc field */
-#define MXC_EHCI_PHY_LOW_POWER_SUSPEND	(1 << 23)
-#define MXC_EHCI_FORCE_FS		(1 << 24)
-#define MXC_EHCI_UTMI_8BIT		(0 << 28)
-#define MXC_EHCI_UTMI_16BIT		(1 << 28)
-#define MXC_EHCI_SERIAL			(1 << 29)
-#define MXC_EHCI_MODE_UTMI		(0 << 30)
-#define MXC_EHCI_MODE_PHILIPS		(1 << 30)
-#define MXC_EHCI_MODE_ULPI		(2 << 30)
-#define MXC_EHCI_MODE_SERIAL		(3 << 30)
-
-/* values for flags field */
-#define MXC_EHCI_INTERFACE_DIFF_UNI	(0 << 0)
-#define MXC_EHCI_INTERFACE_DIFF_BI	(1 << 0)
-#define MXC_EHCI_INTERFACE_SINGLE_UNI	(2 << 0)
-#define MXC_EHCI_INTERFACE_SINGLE_BI	(3 << 0)
-#define MXC_EHCI_INTERFACE_MASK		(0xf)
-
-#define MXC_EHCI_POWER_PINS_ENABLED	(1 << 5)
-#define MXC_EHCI_TTL_ENABLED		(1 << 6)
-
-#define MXC_EHCI_INTERNAL_PHY		(1 << 7)
-#define MXC_EHCI_IPPUE_DOWN		(1 << 8)
-#define MXC_EHCI_IPPUE_UP		(1 << 9)
-
-#endif /* __ASM_ARCH_MX31_REGS_H */
diff --git a/arch/arm/include/asm/arch-mx31/mx31.h b/arch/arm/include/asm/arch-mx31/mx31.h
deleted file mode 100644
index a755212..0000000
--- a/arch/arm/include/asm/arch-mx31/mx31.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- *
- * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __ASM_ARCH_MX31_H
-#define __ASM_ARCH_MX31_H
-
-extern u32 mx31_get_ipg_clk(void);
-#define imx_get_uartclk mx31_get_ipg_clk
-extern void mx31_gpio_mux(unsigned long mode);
-extern void mx31_set_pad(enum iomux_pins pin, u32 config);
-
-void mx31_uart1_hw_init(void);
-void mx31_spi2_hw_init(void);
-
-#endif /* __ASM_ARCH_MX31_H */
diff --git a/arch/arm/include/asm/arch-mx35/clock.h b/arch/arm/include/asm/arch-mx35/clock.h
deleted file mode 100644
index 4c0ddfd..0000000
--- a/arch/arm/include/asm/arch-mx35/clock.h
+++ /dev/null
@@ -1,45 +0,0 @@
-/*
- * (C) Copyright 2011
- * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __ASM_ARCH_CLOCK_H
-#define __ASM_ARCH_CLOCK_H
-
-enum mxc_clock {
-	MXC_ARM_CLK = 0,
-	MXC_AHB_CLK,
-	MXC_IPG_CLK,
-	MXC_IPG_PERCLK,
-	MXC_UART_CLK,
-	MXC_ESDHC_CLK,
-	MXC_USB_CLK,
-	MXC_CSPI_CLK,
-	MXC_FEC_CLK,
-};
-
-unsigned int imx_decode_pll(unsigned int pll, unsigned int f_ref);
-
-u32 imx_get_uartclk(void);
-u32 imx_get_fecclk(void);
-unsigned int mxc_get_clock(enum mxc_clock clk);
-
-#endif /* __ASM_ARCH_CLOCK_H */
diff --git a/arch/arm/include/asm/arch-mx35/crm_regs.h b/arch/arm/include/asm/arch-mx35/crm_regs.h
deleted file mode 100644
index e903cf1..0000000
--- a/arch/arm/include/asm/arch-mx35/crm_regs.h
+++ /dev/null
@@ -1,270 +0,0 @@
-/*
- * Copyright 2004-2009 Freescale Semiconductor, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __CPU_ARM1136_MX35_CRM_REGS_H__
-#define __CPU_ARM1136_MX35_CRM_REGS_H__
-
-/* Register bit definitions */
-#define MXC_CCM_CCMR_WFI                        (1 << 30)
-#define MXC_CCM_CCMR_STBY_EXIT_SRC              (1 << 29)
-#define MXC_CCM_CCMR_VSTBY                      (1 << 28)
-#define MXC_CCM_CCMR_WBEN                       (1 << 27)
-#define MXC_CCM_CCMR_VOL_RDY_CNT_OFFSET        20
-#define MXC_CCM_CCMR_VOL_RDY_CNT_MASK          (0xF << 20)
-#define MXC_CCM_CCMR_ROMW_OFFSET               18
-#define MXC_CCM_CCMR_ROMW_MASK                 (0x3 << 18)
-#define MXC_CCM_CCMR_RAMW_OFFSET               21
-#define MXC_CCM_CCMR_RAMW_MASK                 (0x3 << 21)
-#define MXC_CCM_CCMR_LPM_OFFSET                 14
-#define MXC_CCM_CCMR_LPM_MASK                   (0x3 << 14)
-#define MXC_CCM_CCMR_UPE                        (1 << 9)
-#define MXC_CCM_CCMR_MPE                        (1 << 3)
-
-#define MXC_CCM_PDR0_PER_SEL			(1 << 26)
-#define MXC_CCM_PDR0_IPU_HND_BYP                (1 << 23)
-#define MXC_CCM_PDR0_HSP_PODF_OFFSET            20
-#define MXC_CCM_PDR0_HSP_PODF_MASK              (0x3 << 20)
-#define MXC_CCM_PDR0_CON_MUX_DIV_OFFSET		16
-#define MXC_CCM_PDR0_CON_MUX_DIV_MASK           (0xF << 16)
-#define MXC_CCM_PDR0_CKIL_SEL			(1 << 15)
-#define MXC_CCM_PDR0_PER_PODF_OFFSET            12
-#define MXC_CCM_PDR0_PER_PODF_MASK              (0xF << 12)
-#define MXC_CCM_PDR0_AUTO_MUX_DIV_OFFSET        9
-#define MXC_CCM_PDR0_AUTO_MUX_DIV_MASK          (0x7 << 9)
-#define MXC_CCM_PDR0_AUTO_CON	                0x1
-
-#define MXC_CCM_PDR1_MSHC_PRDF_OFFSET           28
-#define MXC_CCM_PDR1_MSHC_PRDF_MASK             (0x7 << 28)
-#define MXC_CCM_PDR1_MSHC_PODF_OFFSET           22
-#define MXC_CCM_PDR1_MSHC_PODF_MASK             (0x3F << 22)
-#define MXC_CCM_PDR1_MSHC_M_U			(1 << 7)
-
-#define MXC_CCM_PDR2_SSI2_PRDF_OFFSET           27
-#define MXC_CCM_PDR2_SSI2_PRDF_MASK             (0x7 << 27)
-#define MXC_CCM_PDR2_SSI1_PRDF_OFFSET           24
-#define MXC_CCM_PDR2_SSI1_PRDF_MASK             (0x7 << 24)
-#define MXC_CCM_PDR2_CSI_PRDF_OFFSET            19
-#define MXC_CCM_PDR2_CSI_PRDF_MASK              (0x7 << 19)
-#define MXC_CCM_PDR2_CSI_PODF_OFFSET            16
-#define MXC_CCM_PDR2_CSI_PODF_MASK              (0x7 << 16)
-#define MXC_CCM_PDR2_SSI2_PODF_OFFSET           8
-#define MXC_CCM_PDR2_SSI2_PODF_MASK             (0x3F << 8)
-#define MXC_CCM_PDR2_CSI_M_U			(1 << 7)
-#define MXC_CCM_PDR2_SSI_M_U			(1 << 6)
-#define MXC_CCM_PDR2_SSI1_PODF_OFFSET           0
-#define MXC_CCM_PDR2_SSI1_PODF_MASK             (0x3F)
-
-#define MXC_CCM_PDR3_SPDIF_PRDF_OFFSET          29
-#define MXC_CCM_PDR3_SPDIF_PRDF_MASK            (0x7 << 29)
-#define MXC_CCM_PDR3_SPDIF_PODF_OFFSET          23
-#define MXC_CCM_PDR3_SPDIF_PODF_MASK            (0x3F << 23)
-#define MXC_CCM_PDR3_SPDIF_M_U			(1 << 22)
-#define MXC_CCM_PDR3_ESDHC3_PRDF_OFFSET         19
-#define MXC_CCM_PDR3_ESDHC3_PRDF_MASK           (0x7 << 19)
-#define MXC_CCM_PDR3_ESDHC3_PODF_OFFSET         16
-#define MXC_CCM_PDR3_ESDHC3_PODF_MASK           (0x7 << 16)
-#define MXC_CCM_PDR3_UART_M_U			(1 << 15)
-#define MXC_CCM_PDR3_ESDHC2_PRDF_OFFSET         11
-#define MXC_CCM_PDR3_ESDHC2_PRDF_MASK           (0x7 << 11)
-#define MXC_CCM_PDR3_ESDHC2_PODF_OFFSET         8
-#define MXC_CCM_PDR3_ESDHC2_PODF_MASK           (0x7 << 8)
-#define MXC_CCM_PDR3_ESDHC_M_U			(1 << 6)
-#define MXC_CCM_PDR3_ESDHC1_PRDF_OFFSET         3
-#define MXC_CCM_PDR3_ESDHC1_PRDF_MASK           (0x7 << 3)
-#define MXC_CCM_PDR3_ESDHC1_PODF_OFFSET         0
-#define MXC_CCM_PDR3_ESDHC1_PODF_MASK           (0x7)
-
-#define MXC_CCM_PDR4_NFC_PODF_OFFSET		28
-#define MXC_CCM_PDR4_NFC_PODF_MASK		(0xF << 28)
-#define MXC_CCM_PDR4_USB_PRDF_OFFSET		25
-#define MXC_CCM_PDR4_USB_PRDF_MASK		(0x7 << 25)
-#define MXC_CCM_PDR4_USB_PODF_OFFSET		22
-#define MXC_CCM_PDR4_USB_PODF_MASK		(0x7 << 22)
-#define MXC_CCM_PDR4_PER0_PRDF_OFFSET		19
-#define MXC_CCM_PDR4_PER0_PRDF_MASK		(0x7 << 19)
-#define MXC_CCM_PDR4_PER0_PODF_OFFSET		16
-#define MXC_CCM_PDR4_PER0_PODF_MASK		(0x7 << 16)
-#define MXC_CCM_PDR4_UART_PRDF_OFFSET		13
-#define MXC_CCM_PDR4_UART_PRDF_MASK		(0x7 << 13)
-#define MXC_CCM_PDR4_UART_PODF_OFFSET		10
-#define MXC_CCM_PDR4_UART_PODF_MASK		(0x7 << 10)
-#define MXC_CCM_PDR4_USB_M_U			(1 << 9)
-
-/* Bit definitions for RCSR */
-#define MXC_CCM_RCSR_BUS_WIDTH			(1 << 29)
-#define MXC_CCM_RCSR_BUS_16BIT			(1 << 29)
-#define MXC_CCM_RCSR_PAGE_SIZE			(3 << 27)
-#define MXC_CCM_RCSR_PAGE_512			(0 << 27)
-#define MXC_CCM_RCSR_PAGE_2K			(1 << 27)
-#define MXC_CCM_RCSR_PAGE_4K1			(2 << 27)
-#define MXC_CCM_RCSR_PAGE_4K2			(3 << 27)
-#define MXC_CCM_RCSR_SOFT_RESET			(1 << 15)
-#define MXC_CCM_RCSR_NF16B			(1 << 14)
-#define MXC_CCM_RCSR_NFC_4K			(1 << 9)
-#define MXC_CCM_RCSR_NFC_FMS			(1 << 8)
-
-/* Bit definitions for both MCU, PERIPHERAL PLL control registers */
-#define MXC_CCM_PCTL_BRM                        0x80000000
-#define MXC_CCM_PCTL_PD_OFFSET                  26
-#define MXC_CCM_PCTL_PD_MASK                    (0xF << 26)
-#define MXC_CCM_PCTL_MFD_OFFSET                 16
-#define MXC_CCM_PCTL_MFD_MASK                   (0x3FF << 16)
-#define MXC_CCM_PCTL_MFI_OFFSET                 10
-#define MXC_CCM_PCTL_MFI_MASK                   (0xF << 10)
-#define MXC_CCM_PCTL_MFN_OFFSET                 0
-#define MXC_CCM_PCTL_MFN_MASK                   0x3FF
-
-/* Bit definitions for Audio clock mux register*/
-#define MXC_CCM_ACMR_ESAI_CLK_SEL_OFFSET	12
-#define MXC_CCM_ACMR_ESAI_CLK_SEL_MASK		(0xF << 12)
-#define MXC_CCM_ACMR_SPDIF_CLK_SEL_OFFSET	8
-#define MXC_CCM_ACMR_SPDIF_CLK_SEL_MASK		(0xF << 8)
-#define MXC_CCM_ACMR_SSI1_CLK_SEL_OFFSET	4
-#define MXC_CCM_ACMR_SSI1_CLK_SEL_MASK		(0xF << 4)
-#define MXC_CCM_ACMR_SSI2_CLK_SEL_OFFSET	0
-#define MXC_CCM_ACMR_SSI2_CLK_SEL_MASK		(0xF << 0)
-
-/* Bit definitions for Clock gating Register*/
-#define MXC_CCM_CGR0_ASRC_OFFSET		0
-#define MXC_CCM_CGR0_ASRC_MASK			(0x3 << 0)
-#define MXC_CCM_CGR0_ATA_OFFSET			2
-#define MXC_CCM_CGR0_ATA_MASK			(0x3 << 2)
-#define MXC_CCM_CGR0_CAN1_OFFSET		6
-#define MXC_CCM_CGR0_CAN1_MASK			(0x3 << 6)
-#define MXC_CCM_CGR0_CAN2_OFFSET		8
-#define MXC_CCM_CGR0_CAN2_MASK			(0x3 << 8)
-#define MXC_CCM_CGR0_CSPI1_OFFSET		10
-#define MXC_CCM_CGR0_CSPI1_MASK			(0x3 << 10)
-#define MXC_CCM_CGR0_CSPI2_OFFSET		12
-#define MXC_CCM_CGR0_CSPI2_MASK			(0x3 << 12)
-#define MXC_CCM_CGR0_ECT_OFFSET			14
-#define MXC_CCM_CGR0_ECT_MASK			(0x3 << 14)
-#define MXC_CCM_CGR0_EDI0_OFFSET		16
-#define MXC_CCM_CGR0_EDI0_MASK			(0x3 << 16)
-#define MXC_CCM_CGR0_EMI_OFFSET			18
-#define MXC_CCM_CGR0_EMI_MASK			(0x3 << 18)
-#define MXC_CCM_CGR0_EPIT1_OFFSET		20
-#define MXC_CCM_CGR0_EPIT1_MASK			(0x3 << 20)
-#define MXC_CCM_CGR0_EPIT2_OFFSET		22
-#define MXC_CCM_CGR0_EPIT2_MASK			(0x3 << 22)
-#define MXC_CCM_CGR0_ESAI_OFFSET		24
-#define MXC_CCM_CGR0_ESAI_MASK			(0x3 << 24)
-#define MXC_CCM_CGR0_ESDHC1_OFFSET		26
-#define MXC_CCM_CGR0_ESDHC1_MASK		(0x3 << 26)
-#define MXC_CCM_CGR0_ESDHC2_OFFSET		28
-#define MXC_CCM_CGR0_ESDHC2_MASK		(0x3 << 28)
-#define MXC_CCM_CGR0_ESDHC3_OFFSET		30
-#define MXC_CCM_CGR0_ESDHC3_MASK		(0x3 << 30)
-
-#define MXC_CCM_CGR1_FEC_OFFSET			0
-#define MXC_CCM_CGR1_FEC_MASK			(0x3 << 0)
-#define MXC_CCM_CGR1_GPIO1_OFFSET		2
-#define MXC_CCM_CGR1_GPIO1_MASK			(0x3 << 2)
-#define MXC_CCM_CGR1_GPIO2_OFFSET		4
-#define MXC_CCM_CGR1_GPIO2_MASK			(0x3 << 4)
-#define MXC_CCM_CGR1_GPIO3_OFFSET		6
-#define MXC_CCM_CGR1_GPIO3_MASK			(0x3 << 6)
-#define MXC_CCM_CGR1_GPT_OFFSET			8
-#define MXC_CCM_CGR1_GPT_MASK			(0x3 << 8)
-#define MXC_CCM_CGR1_I2C1_OFFSET		10
-#define MXC_CCM_CGR1_I2C1_MASK			(0x3 << 10)
-#define MXC_CCM_CGR1_I2C2_OFFSET		12
-#define MXC_CCM_CGR1_I2C2_MASK			(0x3 << 12)
-#define MXC_CCM_CGR1_I2C3_OFFSET		14
-#define MXC_CCM_CGR1_I2C3_MASK			(0x3 << 14)
-#define MXC_CCM_CGR1_IOMUXC_OFFSET		16
-#define MXC_CCM_CGR1_IOMUXC_MASK		(0x3 << 16)
-#define MXC_CCM_CGR1_IPU_OFFSET			18
-#define MXC_CCM_CGR1_IPU_MASK			(0x3 << 18)
-#define MXC_CCM_CGR1_KPP_OFFSET			20
-#define MXC_CCM_CGR1_KPP_MASK			(0x3 << 20)
-#define MXC_CCM_CGR1_MLB_OFFSET			22
-#define MXC_CCM_CGR1_MLB_MASK			(0x3 << 22)
-#define MXC_CCM_CGR1_MSHC_OFFSET		24
-#define MXC_CCM_CGR1_MSHC_MASK			(0x3 << 24)
-#define MXC_CCM_CGR1_OWIRE_OFFSET		26
-#define MXC_CCM_CGR1_OWIRE_MASK			(0x3 << 26)
-#define MXC_CCM_CGR1_PWM_OFFSET			28
-#define MXC_CCM_CGR1_PWM_MASK			(0x3 << 28)
-#define MXC_CCM_CGR1_RNGC_OFFSET		30
-#define MXC_CCM_CGR1_RNGC_MASK			(0x3 << 30)
-
-#define MXC_CCM_CGR2_RTC_OFFSET			0
-#define MXC_CCM_CGR2_RTC_MASK			(0x3 << 0)
-#define MXC_CCM_CGR2_RTIC_OFFSET		2
-#define MXC_CCM_CGR2_RTIC_MASK			(0x3 << 2)
-#define MXC_CCM_CGR2_SCC_OFFSET			4
-#define MXC_CCM_CGR2_SCC_MASK			(0x3 << 4)
-#define MXC_CCM_CGR2_SDMA_OFFSET		6
-#define MXC_CCM_CGR2_SDMA_MASK			(0x3 << 6)
-#define MXC_CCM_CGR2_SPBA_OFFSET		8
-#define MXC_CCM_CGR2_SPBA_MASK			(0x3 << 8)
-#define MXC_CCM_CGR2_SPDIF_OFFSET		10
-#define MXC_CCM_CGR2_SPDIF_MASK			(0x3 << 10)
-#define MXC_CCM_CGR2_SSI1_OFFSET		12
-#define MXC_CCM_CGR2_SSI1_MASK			(0x3 << 12)
-#define MXC_CCM_CGR2_SSI2_OFFSET		14
-#define MXC_CCM_CGR2_SSI2_MASK			(0x3 << 14)
-#define MXC_CCM_CGR2_UART1_OFFSET		16
-#define MXC_CCM_CGR2_UART1_MASK			(0x3 << 16)
-#define MXC_CCM_CGR2_UART2_OFFSET		18
-#define MXC_CCM_CGR2_UART2_MASK			(0x3 << 18)
-#define MXC_CCM_CGR2_UART3_OFFSET		20
-#define MXC_CCM_CGR2_UART3_MASK			(0x3 << 20)
-#define MXC_CCM_CGR2_USBOTG_OFFSET		22
-#define MXC_CCM_CGR2_USBOTG_MASK		(0x3 << 22)
-#define MXC_CCM_CGR2_WDOG_OFFSET		24
-#define MXC_CCM_CGR2_WDOG_MASK			(0x3 << 24)
-#define MXC_CCM_CGR2_MAX_OFFSET			26
-#define MXC_CCM_CGR2_MAX_MASK			(0x3 << 26)
-#define MXC_CCM_CGR2_MAX_ENABLE			(0x2 << 26)
-#define MXC_CCM_CGR2_AUDMUX_OFFSET		30
-#define MXC_CCM_CGR2_AUDMUX_MASK		(0x3 << 30)
-
-#define MXC_CCM_CGR3_CSI_OFFSET			0
-#define MXC_CCM_CGR3_CSI_MASK			(0x3 << 0)
-#define MXC_CCM_CGR3_IIM_OFFSET			2
-#define MXC_CCM_CGR3_IIM_MASK			(0x3 << 2)
-#define MXC_CCM_CGR3_GPU2D_OFFSET		4
-#define MXC_CCM_CGR3_GPU2D_MASK			(0x3 << 4)
-
-#define MXC_CCM_COSR_CLKOSEL_MASK		0x1F
-#define MXC_CCM_COSR_CLKOSEL_OFFSET		0
-#define MXC_CCM_COSR_CLKOEN			(1 << 5)
-#define MXC_CCM_COSR_CLKOUTDIV_1		(1 << 6)
-#define MXC_CCM_COSR_CLKOUT_PREDIV_MASK		(0x7 << 10)
-#define MXC_CCM_COSR_CLKOUT_PREDIV_OFFSET	10
-#define MXC_CCM_COSR_CLKOUT_PRODIV_MASK		(0x7 << 13)
-#define MXC_CCM_COSR_CLKOUT_PRODIV_OFFSET	13
-#define MXC_CCM_COSR_SSI1_RX_SRC_SEL_MASK	(0x3 << 16)
-#define MXC_CCM_COSR_SSI1_RX_SRC_SEL_OFFSET	16
-#define MXC_CCM_COSR_SSI1_TX_SRC_SEL_MASK	(0x3 << 18)
-#define MXC_CCM_COSR_SSI1_TX_SRC_SEL_OFFSET	18
-#define MXC_CCM_COSR_SSI2_RX_SRC_SEL_MASK	(0x3 << 20)
-#define MXC_CCM_COSR_SSI2_RX_SRC_SEL_OFFSET	20
-#define MXC_CCM_COSR_SSI2_TX_SRC_SEL_MASK	(0x3 << 22)
-#define MXC_CCM_COSR_SSI2_TX_SRC_SEL_OFFSET	22
-#define MXC_CCM_COSR_ASRC_AUDIO_EN		(1 << 24)
-#define MXC_CCM_COSR_ASRC_AUDIO_PODF_MASK	(0x3F << 26)
-#define MXC_CCM_COSR_ASRC_AUDIO_PODF_OFFSET	26
-
-#endif
diff --git a/arch/arm/include/asm/arch-mx35/imx-regs.h b/arch/arm/include/asm/arch-mx35/imx-regs.h
deleted file mode 100644
index e741fb0..0000000
--- a/arch/arm/include/asm/arch-mx35/imx-regs.h
+++ /dev/null
@@ -1,303 +0,0 @@
-/*
- * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
- *
- * (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __ASM_ARCH_MX35_H
-#define __ASM_ARCH_MX35_H
-
-/*
- * IRAM
- */
-#define IRAM_BASE_ADDR		0x10000000	/* internal ram */
-#define IRAM_SIZE		0x00020000	/* 128 KB */
-
-/*
- * AIPS 1
- */
-#define AIPS1_BASE_ADDR         0x43F00000
-#define AIPS1_CTRL_BASE_ADDR    AIPS1_BASE_ADDR
-#define MAX_BASE_ADDR           0x43F04000
-#define EVTMON_BASE_ADDR        0x43F08000
-#define CLKCTL_BASE_ADDR        0x43F0C000
-#define I2C_BASE_ADDR           0x43F80000
-#define I2C3_BASE_ADDR          0x43F84000
-#define ATA_BASE_ADDR           0x43F8C000
-#define UART1_BASE_ADDR         0x43F90000
-#define UART2_BASE_ADDR         0x43F94000
-#define I2C2_BASE_ADDR          0x43F98000
-#define CSPI1_BASE_ADDR         0x43FA4000
-#define IOMUXC_BASE_ADDR        0x43FAC000
-
-/*
- * SPBA
- */
-#define SPBA_BASE_ADDR          0x50000000
-#define UART3_BASE_ADDR         0x5000C000
-#define CSPI2_BASE_ADDR         0x50010000
-#define ATA_DMA_BASE_ADDR       0x50020000
-#define FEC_BASE_ADDR           0x50038000
-#define SPBA_CTRL_BASE_ADDR     0x5003C000
-
-/*
- * AIPS 2
- */
-#define AIPS2_BASE_ADDR         0x53F00000
-#define AIPS2_CTRL_BASE_ADDR    AIPS2_BASE_ADDR
-#define CCM_BASE_ADDR           0x53F80000
-#define GPT1_BASE_ADDR          0x53F90000
-#define EPIT1_BASE_ADDR         0x53F94000
-#define EPIT2_BASE_ADDR         0x53F98000
-#define GPIO3_BASE_ADDR         0x53FA4000
-#define MMC_SDHC1_BASE_ADDR	0x53FB4000
-#define MMC_SDHC2_BASE_ADDR	0x53FB8000
-#define MMC_SDHC3_BASE_ADDR	0x53FBC000
-#define IPU_CTRL_BASE_ADDR	0x53FC0000
-#define GPIO3_BASE_ADDR		0x53FA4000
-#define GPIO1_BASE_ADDR		0x53FCC000
-#define GPIO2_BASE_ADDR		0x53FD0000
-#define SDMA_BASE_ADDR		0x53FD4000
-#define RTC_BASE_ADDR		0x53FD8000
-#define WDOG_BASE_ADDR		0x53FDC000
-#define PWM_BASE_ADDR		0x53FE0000
-#define RTIC_BASE_ADDR		0x53FEC000
-#define IIM_BASE_ADDR		0x53FF0000
-
-#define IMX_CCM_BASE		CCM_BASE_ADDR
-
-/*
- * ROMPATCH and AVIC
- */
-#define ROMPATCH_BASE_ADDR	0x60000000
-#define AVIC_BASE_ADDR		0x68000000
-
-/*
- * NAND, SDRAM, WEIM, M3IF, EMI controllers
- */
-#define EXT_MEM_CTRL_BASE	0xB8000000
-#define ESDCTL_BASE_ADDR	0xB8001000
-#define WEIM_BASE_ADDR		0xB8002000
-#define WEIM_CTRL_CS0		WEIM_BASE_ADDR
-#define WEIM_CTRL_CS1		(WEIM_BASE_ADDR + 0x10)
-#define WEIM_CTRL_CS2		(WEIM_BASE_ADDR + 0x20)
-#define WEIM_CTRL_CS3		(WEIM_BASE_ADDR + 0x30)
-#define WEIM_CTRL_CS4		(WEIM_BASE_ADDR + 0x40)
-#define WEIM_CTRL_CS5		(WEIM_BASE_ADDR + 0x50)
-#define M3IF_BASE_ADDR		0xB8003000
-#define EMI_BASE_ADDR		0xB8004000
-
-#define NFC_BASE_ADDR		0xBB000000
-
-/*
- * Memory regions and CS
- */
-#define IPU_MEM_BASE_ADDR	0x70000000
-#define CSD0_BASE_ADDR		0x80000000
-#define CSD1_BASE_ADDR		0x90000000
-#define CS0_BASE_ADDR		0xA0000000
-#define CS1_BASE_ADDR		0xA8000000
-#define CS2_BASE_ADDR		0xB0000000
-#define CS3_BASE_ADDR		0xB2000000
-#define CS4_BASE_ADDR		0xB4000000
-#define CS5_BASE_ADDR		0xB6000000
-
-/*
- * IRQ Controller Register Definitions.
- */
-#define AVIC_NIMASK		0x04
-#define AVIC_INTTYPEH		0x18
-#define AVIC_INTTYPEL		0x1C
-
-/* L210 */
-#define L2CC_BASE_ADDR		0x30000000
-#define L2_CACHE_LINE_SIZE		32
-#define L2_CACHE_CTL_REG		0x100
-#define L2_CACHE_AUX_CTL_REG		0x104
-#define L2_CACHE_SYNC_REG		0x730
-#define L2_CACHE_INV_LINE_REG		0x770
-#define L2_CACHE_INV_WAY_REG		0x77C
-#define L2_CACHE_CLEAN_LINE_REG		0x7B0
-#define L2_CACHE_CLEAN_INV_LINE_REG	0x7F0
-#define L2_CACHE_DBG_CTL_REG		0xF40
-
-#define CLKMODE_AUTO		0
-#define CLKMODE_CONSUMER	1
-
-#define PLL_PD(x)		(((x) & 0xf) << 26)
-#define PLL_MFD(x)		(((x) & 0x3ff) << 16)
-#define PLL_MFI(x)		(((x) & 0xf) << 10)
-#define PLL_MFN(x)		(((x) & 0x3ff) << 0)
-
-#define CSCR_U(x)	(WEIM_CTRL_CS#x + 0)
-#define CSCR_L(x)	(WEIM_CTRL_CS#x + 4)
-#define CSCR_A(x)	(WEIM_CTRL_CS#x + 8)
-
-#define IIM_SREV	0x24
-#define ROMPATCH_REV	0x40
-
-#define IPU_CONF	IPU_CTRL_BASE_ADDR
-
-#define IPU_CONF_PXL_ENDIAN	(1<<8)
-#define IPU_CONF_DU_EN		(1<<7)
-#define IPU_CONF_DI_EN		(1<<6)
-#define IPU_CONF_ADC_EN		(1<<5)
-#define IPU_CONF_SDC_EN		(1<<4)
-#define IPU_CONF_PF_EN		(1<<3)
-#define IPU_CONF_ROT_EN		(1<<2)
-#define IPU_CONF_IC_EN		(1<<1)
-#define IPU_CONF_SCI_EN		(1<<0)
-
-#define GPIO_PORT_NUM		3
-#define GPIO_NUM_PIN		32
-
-#define CHIP_REV_1_0		0x10
-#define CHIP_REV_2_0		0x20
-
-#define BOARD_REV_1_0		0x0
-#define BOARD_REV_2_0		0x1
-
-#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
-#include <asm/types.h>
-
-extern void imx_get_mac_from_fuse(unsigned char *mac);
-
-enum mxc_main_clocks {
-	CPU_CLK,
-	AHB_CLK,
-	IPG_CLK,
-	IPG_PER_CLK,
-	NFC_CLK,
-	USB_CLK,
-	HSP_CLK,
-};
-
-enum mxc_peri_clocks {
-	UART1_BAUD,
-	UART2_BAUD,
-	UART3_BAUD,
-	SSI1_BAUD,
-	SSI2_BAUD,
-	CSI_BAUD,
-	MSHC_CLK,
-	ESDHC1_CLK,
-	ESDHC2_CLK,
-	ESDHC3_CLK,
-	SPDIF_CLK,
-	SPI1_CLK,
-	SPI2_CLK,
-};
-
-/* Clock Control Module (CCM) registers */
-struct ccm_regs {
-	u32 ccmr;	/* Control */
-	u32 pdr0;	/* Post divider 0 */
-	u32 pdr1;	/* Post divider 1 */
-	u32 pdr2;	/* Post divider 2 */
-	u32 pdr3;	/* Post divider 3 */
-	u32 pdr4;	/* Post divider 4 */
-	u32 rcsr;	/* CCM Status */
-	u32 mpctl;	/* Core PLL Control */
-	u32 ppctl;	/* Peripheral PLL Control */
-	u32 acmr;	/* Audio clock mux */
-	u32 cosr;	/* Clock out source */
-	u32 cgr0;	/* Clock Gating Control 0 */
-	u32 cgr1;	/* Clock Gating Control 1 */
-	u32 cgr2;	/* Clock Gating Control 2 */
-	u32 cgr3;	/* Clock Gating Control 3 */
-	u32 reserved;
-	u32 dcvr0;	/* DPTC Comparator 0 */
-	u32 dcvr1;	/* DPTC Comparator 0 */
-	u32 dcvr2;	/* DPTC Comparator 0 */
-	u32 dcvr3;	/* DPTC Comparator 0 */
-	u32 ltr0;	/* Load Tracking 0 */
-	u32 ltr1;	/* Load Tracking 1 */
-	u32 ltr2;	/* Load Tracking 2 */
-	u32 ltr3;	/* Load Tracking 3 */
-	u32 ltbr0;	/* Load Tracking Buffer 0 */
-};
-
-/* IIM control registers */
-struct iim_regs {
-	u32 iim_stat;
-	u32 iim_statm;
-	u32 iim_err;
-	u32 iim_emask;
-	u32 iim_fctl;
-	u32 iim_ua;
-	u32 iim_la;
-	u32 iim_sdat;
-	u32 iim_prev;
-	u32 iim_srev;
-	u32 iim_prog_p;
-	u32 iim_scs0;
-	u32 iim_scs1;
-	u32 iim_scs2;
-	u32 iim_scs3;
-};
-
-/* General Purpose Timer (GPT) registers */
-struct gpt_regs {
-	u32 ctrl;	/* control */
-	u32 pre;	/* prescaler */
-	u32 stat;	/* status */
-	u32 intr;	/* interrupt */
-	u32 cmp[3];	/* output compare 1-3 */
-	u32 capt[2];	/* input capture 1-2 */
-	u32 counter;	/* counter */
-};
-
-/* CSPI registers */
-struct cspi_regs {
-	u32 rxdata;
-	u32 txdata;
-	u32 ctrl;
-	u32 intr;
-	u32 dma;
-	u32 stat;
-	u32 period;
-	u32 test;
-};
-
-/* Watchdog Timer (WDOG) registers */
-struct wdog_regs {
-	u16 wcr;	/* Control */
-	u16 wsr;	/* Service */
-	u16 wrsr;	/* Reset Status */
-	u16 wicr;	/* Interrupt Control */
-	u16 wmcr;	/* Misc Control */
-};
-
-/*
- * NFMS bit in RCSR register for pagesize of nandflash
- */
-#define NFMS_BIT		8
-#define NFMS_NF_DWIDTH		14
-#define NFMS_NF_PG_SZ		8
-
-#define CCM_RCSR_NF_16BIT_SEL	(1 << 14)
-
-extern unsigned int get_board_rev(void);
-extern int is_soc_rev(int rev);
-extern int sdhc_init(void);
-
-#endif
-#endif /* __ASM_ARCH_MX35_H */
diff --git a/arch/arm/include/asm/arch-mx35/iomux.h b/arch/arm/include/asm/arch-mx35/iomux.h
deleted file mode 100644
index 52c15bc..0000000
--- a/arch/arm/include/asm/arch-mx35/iomux.h
+++ /dev/null
@@ -1,295 +0,0 @@
-/*
- * (C) Copyright 2011
- * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
- *
- * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __MACH_MX35_IOMUX_H__
-#define __MACH_MX35_IOMUX_H__
-
-#include <asm/arch/imx-regs.h>
-
-/*
- * various IOMUX functions
- */
-typedef enum iomux_pin_config {
-	MUX_CONFIG_FUNC = 0,	/* used as function */
-	MUX_CONFIG_ALT1,	/* used as alternate function 1 */
-	MUX_CONFIG_ALT2,	/* used as alternate function 2 */
-	MUX_CONFIG_ALT3,	/* used as alternate function 3 */
-	MUX_CONFIG_ALT4,	/* used as alternate function 4 */
-	MUX_CONFIG_ALT5,	/* used as alternate function 5 */
-	MUX_CONFIG_ALT6,	/* used as alternate function 6 */
-	MUX_CONFIG_ALT7,	/* used as alternate function 7 */
-	MUX_CONFIG_SION = 0x1 << 4,	/* used as LOOPBACK:MUX SION bit */
-	MUX_CONFIG_GPIO = MUX_CONFIG_ALT5,	/* used as GPIO */
-} iomux_pin_cfg_t;
-
-/*
- * various IOMUX pad functions
- */
-typedef enum iomux_pad_config {
-	PAD_CTL_DRV_3_3V = 0x0 << 13,
-	PAD_CTL_DRV_1_8V = 0x1 << 13,
-	PAD_CTL_HYS_CMOS = 0x0 << 8,
-	PAD_CTL_HYS_SCHMITZ = 0x1 << 8,
-	PAD_CTL_PKE_NONE = 0x0 << 7,
-	PAD_CTL_PKE_ENABLE = 0x1 << 7,
-	PAD_CTL_PUE_KEEPER = 0x0 << 6,
-	PAD_CTL_PUE_PUD = 0x1 << 6,
-	PAD_CTL_100K_PD = 0x0 << 4,
-	PAD_CTL_47K_PU = 0x1 << 4,
-	PAD_CTL_100K_PU = 0x2 << 4,
-	PAD_CTL_22K_PU = 0x3 << 4,
-	PAD_CTL_ODE_CMOS = 0x0 << 3,
-	PAD_CTL_ODE_OpenDrain = 0x1 << 3,
-	PAD_CTL_DRV_NORMAL = 0x0 << 1,
-	PAD_CTL_DRV_HIGH = 0x1 << 1,
-	PAD_CTL_DRV_MAX = 0x2 << 1,
-	PAD_CTL_SRE_SLOW = 0x0 << 0,
-	PAD_CTL_SRE_FAST = 0x1 << 0
-} iomux_pad_config_t;
-
-/*
- * various IOMUX general purpose functions
- */
-typedef enum iomux_gp_func {
-	MUX_SDCTL_CSD0_SEL = 0x1 << 0,
-	MUX_SDCTL_CSD1_SEL = 0x1 << 1,
-	MUX_TAMPER_DETECT_EN = 0x1 << 2,
-} iomux_gp_func_t;
-
-/*
- * various IOMUX input select register index
- */
-typedef enum iomux_input_select {
-	MUX_IN_AMX_P5_RXCLK = 0,
-	MUX_IN_AMX_P5_RXFS,
-	MUX_IN_AMX_P6_DA,
-	MUX_IN_AMX_P6_DB,
-	MUX_IN_AMX_P6_RXCLK,
-	MUX_IN_AMX_P6_RXFS,
-	MUX_IN_AMX_P6_TXCLK,
-	MUX_IN_AMX_P6_TXFS,
-	MUX_IN_CAN1_CANRX,
-	MUX_IN_CAN2_CANRX,
-	MUX_IN_CCM_32K_MUXED,
-	MUX_IN_CCM_PMIC_RDY,
-	MUX_IN_CSPI1_SS2_B,
-	MUX_IN_CSPI1_SS3_B,
-	MUX_IN_CSPI2_CLK_IN,
-	MUX_IN_CSPI2_DATAREADY_B,
-	MUX_IN_CSPI2_MISO,
-	MUX_IN_CSPI2_MOSI,
-	MUX_IN_CSPI2_SS0_B,
-	MUX_IN_CSPI2_SS1_B,
-	MUX_IN_CSPI2_SS2_B,
-	MUX_IN_CSPI2_SS3_B,
-	MUX_IN_EMI_WEIM_DTACK_B,
-	MUX_IN_ESDHC1_DAT4_IN,
-	MUX_IN_ESDHC1_DAT5_IN,
-	MUX_IN_ESDHC1_DAT6_IN,
-	MUX_IN_ESDHC1_DAT7_IN,
-	MUX_IN_ESDHC3_CARD_CLK_IN,
-	MUX_IN_ESDHC3_CMD_IN,
-	MUX_IN_ESDHC3_DAT0,
-	MUX_IN_ESDHC3_DAT1,
-	MUX_IN_ESDHC3_DAT2,
-	MUX_IN_ESDHC3_DAT3,
-	MUX_IN_GPIO1_IN_0,
-	MUX_IN_GPIO1_IN_10,
-	MUX_IN_GPIO1_IN_11,
-	MUX_IN_GPIO1_IN_1,
-	MUX_IN_GPIO1_IN_20,
-	MUX_IN_GPIO1_IN_21,
-	MUX_IN_GPIO1_IN_22,
-	MUX_IN_GPIO1_IN_2,
-	MUX_IN_GPIO1_IN_3,
-	MUX_IN_GPIO1_IN_4,
-	MUX_IN_GPIO1_IN_5,
-	MUX_IN_GPIO1_IN_6,
-	MUX_IN_GPIO1_IN_7,
-	MUX_IN_GPIO1_IN_8,
-	MUX_IN_GPIO1_IN_9,
-	MUX_IN_GPIO2_IN_0,
-	MUX_IN_GPIO2_IN_10,
-	MUX_IN_GPIO2_IN_11,
-	MUX_IN_GPIO2_IN_12,
-	MUX_IN_GPIO2_IN_13,
-	MUX_IN_GPIO2_IN_14,
-	MUX_IN_GPIO2_IN_15,
-	MUX_IN_GPIO2_IN_16,
-	MUX_IN_GPIO2_IN_17,
-	MUX_IN_GPIO2_IN_18,
-	MUX_IN_GPIO2_IN_19,
-	MUX_IN_GPIO2_IN_20,
-	MUX_IN_GPIO2_IN_21,
-	MUX_IN_GPIO2_IN_22,
-	MUX_IN_GPIO2_IN_23,
-	MUX_IN_GPIO2_IN_24,
-	MUX_IN_GPIO2_IN_25,
-	MUX_IN_GPIO2_IN_26,
-	MUX_IN_GPIO2_IN_27,
-	MUX_IN_GPIO2_IN_28,
-	MUX_IN_GPIO2_IN_29,
-	MUX_IN_GPIO2_IN_2,
-	MUX_IN_GPIO2_IN_30,
-	MUX_IN_GPIO2_IN_31,
-	MUX_IN_GPIO2_IN_3,
-	MUX_IN_GPIO2_IN_4,
-	MUX_IN_GPIO2_IN_5,
-	MUX_IN_GPIO2_IN_6,
-	MUX_IN_GPIO2_IN_7,
-	MUX_IN_GPIO2_IN_8,
-	MUX_IN_GPIO2_IN_9,
-	MUX_IN_GPIO3_IN_0,
-	MUX_IN_GPIO3_IN_10,
-	MUX_IN_GPIO3_IN_11,
-	MUX_IN_GPIO3_IN_12,
-	MUX_IN_GPIO3_IN_13,
-	MUX_IN_GPIO3_IN_14,
-	MUX_IN_GPIO3_IN_15,
-	MUX_IN_GPIO3_IN_4,
-	MUX_IN_GPIO3_IN_5,
-	MUX_IN_GPIO3_IN_6,
-	MUX_IN_GPIO3_IN_7,
-	MUX_IN_GPIO3_IN_8,
-	MUX_IN_GPIO3_IN_9,
-	MUX_IN_I2C3_SCL_IN,
-	MUX_IN_I2C3_SDA_IN,
-	MUX_IN_IPU_DISPB_D0_VSYNC,
-	MUX_IN_IPU_DISPB_D12_VSYNC,
-	MUX_IN_IPU_DISPB_SD_D,
-	MUX_IN_IPU_SENSB_DATA_0,
-	MUX_IN_IPU_SENSB_DATA_1,
-	MUX_IN_IPU_SENSB_DATA_2,
-	MUX_IN_IPU_SENSB_DATA_3,
-	MUX_IN_IPU_SENSB_DATA_4,
-	MUX_IN_IPU_SENSB_DATA_5,
-	MUX_IN_IPU_SENSB_DATA_6,
-	MUX_IN_IPU_SENSB_DATA_7,
-	MUX_IN_KPP_COL_0,
-	MUX_IN_KPP_COL_1,
-	MUX_IN_KPP_COL_2,
-	MUX_IN_KPP_COL_3,
-	MUX_IN_KPP_COL_4,
-	MUX_IN_KPP_COL_5,
-	MUX_IN_KPP_COL_6,
-	MUX_IN_KPP_COL_7,
-	MUX_IN_KPP_ROW_0,
-	MUX_IN_KPP_ROW_1,
-	MUX_IN_KPP_ROW_2,
-	MUX_IN_KPP_ROW_3,
-	MUX_IN_KPP_ROW_4,
-	MUX_IN_KPP_ROW_5,
-	MUX_IN_KPP_ROW_6,
-	MUX_IN_KPP_ROW_7,
-	MUX_IN_OWIRE_BATTERY_LINE,
-	MUX_IN_SPDIF_HCKT_CLK2,
-	MUX_IN_SPDIF_SPDIF_IN1,
-	MUX_IN_UART3_UART_RTS_B,
-	MUX_IN_UART3_UART_RXD_MUX,
-	MUX_IN_USB_OTG_DATA_0,
-	MUX_IN_USB_OTG_DATA_1,
-	MUX_IN_USB_OTG_DATA_2,
-	MUX_IN_USB_OTG_DATA_3,
-	MUX_IN_USB_OTG_DATA_4,
-	MUX_IN_USB_OTG_DATA_5,
-	MUX_IN_USB_OTG_DATA_6,
-	MUX_IN_USB_OTG_DATA_7,
-	MUX_IN_USB_OTG_DIR,
-	MUX_IN_USB_OTG_NXT,
-	MUX_IN_USB_UH2_DATA_0,
-	MUX_IN_USB_UH2_DATA_1,
-	MUX_IN_USB_UH2_DATA_2,
-	MUX_IN_USB_UH2_DATA_3,
-	MUX_IN_USB_UH2_DATA_4,
-	MUX_IN_USB_UH2_DATA_5,
-	MUX_IN_USB_UH2_DATA_6,
-	MUX_IN_USB_UH2_DATA_7,
-	MUX_IN_USB_UH2_DIR,
-	MUX_IN_USB_UH2_NXT,
-	MUX_IN_USB_UH2_USB_OC,
-} iomux_input_select_t;
-
-/*
- * various IOMUX input functions
- */
-typedef enum iomux_input_config {
-	INPUT_CTL_PATH0 = 0x0,
-	INPUT_CTL_PATH1,
-	INPUT_CTL_PATH2,
-	INPUT_CTL_PATH3,
-	INPUT_CTL_PATH4,
-	INPUT_CTL_PATH5,
-	INPUT_CTL_PATH6,
-	INPUT_CTL_PATH7,
-} iomux_input_cfg_t;
-
-/*
- * Request ownership for an IO pin. This function has to be the first one
- * being called before that pin is used. The caller has to check the
- * return value to make sure it returns 0.
- *
- * @param  pin		a name defined by iomux_pin_name_t
- * @param  cfg		an input function as defined in iomux_pin_cfg_t
- *
- * @return		0 if successful; Non-zero otherwise
- */
-void mxc_request_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg);
-
-/*
- * Release ownership for an IO pin
- *
- * @param  pin		a name defined by iomux_pin_name_t
- * @param  cfg		an input function as defined in iomux_pin_cfg_t
- */
-void mxc_free_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg);
-
-/*
- * This function enables/disables the general purpose function for a particular
- * signal.
- *
- * @param  gp   one signal as defined in iomux_gp_func_t
- * @param  en   1 to enable; 0 to disable
- */
-void mxc_iomux_set_gpr(iomux_gp_func_t gp, int en);
-
-/*
- * This function configures the pad value for a IOMUX pin.
- *
- * @param  pin          a pin number as defined in iomux_pin_name_t
- * @param  config       the ORed value of elements defined in
- *				iomux_pad_config_t
- */
-void mxc_iomux_set_pad(iomux_pin_name_t pin, u32 config);
-
-/*
- * This function configures input path.
- *
- * @param  input        index of input select register as defined in
- *				iomux_input_select_t
- * @param  config       the binary value of elements defined in
- *				iomux_input_cfg_t
- */
-void mxc_iomux_set_input(iomux_input_select_t input, u32 config);
-#endif
diff --git a/arch/arm/include/asm/arch-mx35/mx35_pins.h b/arch/arm/include/asm/arch-mx35/mx35_pins.h
deleted file mode 100644
index 14669ff..0000000
--- a/arch/arm/include/asm/arch-mx35/mx35_pins.h
+++ /dev/null
@@ -1,355 +0,0 @@
-/*
- * (C) Copyright 2011
- * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
- *
- * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __ASM_ARCH_MXC_MX35_PINS_H__
-#define __ASM_ARCH_MXC_MX35_PINS_H__
-
-/*!
- * @file arch-mxc/mx35_pins.h
- *
- * @brief MX35 I/O Pin List
- *
- * @ingroup GPIO_MX35
- */
-
-#ifndef __ASSEMBLY__
-
-/*!
- * @name IOMUX/PAD Bit field definitions
- */
-
-/*! @{ */
-
-/*!
- * In order to identify pins more effectively, each mux-controlled pin's
- * enumerated value is constructed in the following way:
- *
- * -------------------------------------------------------------------
- * 31-29 | 28 - 24 |23 - 21| 20 - 10| 9 - 0
- * -------------------------------------------------------------------
- * IO_P  |  IO_I   | RSVD  | PAD_I | MUX_I
- * -------------------------------------------------------------------
- *
- * Bit 0 to 7 contains MUX_I used to identify the register
- * offset (base is IOMUX_module_base ) defined in the Section
- * "sw_pad_ctl & sw_mux_ctl details" of the IC Spec. The similar field
- * definitions are used for the pad control register.the MX35_PIN_A0 is
- * defined in the enumeration: ( 0x28 << MUX_I) |( 0x368 << PAD_I)
- * So the absolute address is: IOMUX_module_base + 0x28.
- * The pad control register offset is: 0x368.
- */
-
-/*!
- * Starting bit position within each entry of \b iomux_pins to represent the
- * MUX control register offset
- */
-#define MUX_I		0
-/*!
- * Starting bit position within each entry of \b iomux_pins to represent the
- * PAD control register offset
- */
-#define PAD_I		10
-
-/*!
- * Starting bit position within each entry of \b iomux_pins to represent the
- * reserved filed
- */
-#define RSVD_I		21
-
-#define MUX_IO_P                29
-#define MUX_IO_I                24
-#define IOMUX_TO_GPIO(pin)      ((((unsigned int)pin >> MUX_IO_P) * \
-					GPIO_NUM_PIN) + ((pin >> MUX_IO_I) &\
-					((1 << (MUX_IO_P - MUX_IO_I)) - 1)))
-#define IOMUX_TO_IRQ(pin)       (MXC_GPIO_INT_BASE + IOMUX_TO_GPIO(pin))
-#define GPIO_TO_PORT(n)         (n / GPIO_NUM_PIN)
-#define GPIO_TO_INDEX(n)        (n % GPIO_NUM_PIN)
-
-#define NON_GPIO_I	0x7
-#define PIN_TO_MUX_MASK	((1<<(PAD_I - MUX_I)) - 1)
-#define PIN_TO_PAD_MASK	((1<<(RSVD_I - PAD_I)) - 1)
-#define NON_MUX_I	PIN_TO_MUX_MASK
-
-#define _MXC_BUILD_PIN(gp, gi, mi, pi) \
-		(((gp) << MUX_IO_P) | ((gi) << MUX_IO_I) | \
-		((mi) << MUX_I) | ((pi) << PAD_I))
-
-#define _MXC_BUILD_GPIO_PIN(gp, gi, mi, pi) \
-		_MXC_BUILD_PIN(gp, gi, mi, pi)
-
-#define _MXC_BUILD_NON_GPIO_PIN(mi, pi) \
-		_MXC_BUILD_PIN(NON_GPIO_I, 0, mi, pi)
-
-#define PIN_TO_IOMUX_MUX(pin) ((pin >> MUX_I) & PIN_TO_MUX_MASK)
-#define PIN_TO_IOMUX_PAD(pin) ((pin >> PAD_I) & PIN_TO_PAD_MASK)
-
-/*! @} End IOMUX/PAD Bit field definitions */
-
-/*!
- * This enumeration is constructed based on the Section
- * "sw_pad_ctl & sw_mux_ctl details" of the MX35 IC Spec. Each enumerated
- * value is constructed based on the rules described above.
- */
-typedef enum iomux_pins {
-	MX35_PIN_CAPTURE = _MXC_BUILD_GPIO_PIN(0, 4, 0x4, 0x328),
-	MX35_PIN_COMPARE = _MXC_BUILD_GPIO_PIN(0, 5, 0x8, 0x32C),
-	MX35_PIN_WATCHDOG_RST = _MXC_BUILD_GPIO_PIN(0, 6, 0xC, 0x330),
-	MX35_PIN_GPIO1_0 = _MXC_BUILD_GPIO_PIN(0, 0, 0x10, 0x334),
-	MX35_PIN_GPIO1_1 = _MXC_BUILD_GPIO_PIN(0, 1, 0x14, 0x338),
-	MX35_PIN_GPIO2_0 = _MXC_BUILD_GPIO_PIN(1, 0, 0x18, 0x33C),
-	MX35_PIN_GPIO3_0 = _MXC_BUILD_GPIO_PIN(2, 1, 0x1C, 0x340),
-	MX35_PIN_CLKO = _MXC_BUILD_GPIO_PIN(0, 8, 0x20, 0x34C),
-
-	MX35_PIN_POWER_FAIL = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x360),
-	MX35_PIN_VSTBY = _MXC_BUILD_GPIO_PIN(0, 7, 0x24, 0x364),
-	MX35_PIN_A0 = _MXC_BUILD_NON_GPIO_PIN(0x28, 0x368),
-	MX35_PIN_A1 = _MXC_BUILD_NON_GPIO_PIN(0x2C, 0x36C),
-	MX35_PIN_A2 = _MXC_BUILD_NON_GPIO_PIN(0x30, 0x370),
-	MX35_PIN_A3 = _MXC_BUILD_NON_GPIO_PIN(0x34, 0x374),
-	MX35_PIN_A4 = _MXC_BUILD_NON_GPIO_PIN(0x38, 0x378),
-	MX35_PIN_A5 = _MXC_BUILD_NON_GPIO_PIN(0x3C, 0x37C),
-	MX35_PIN_A6 = _MXC_BUILD_NON_GPIO_PIN(0x40, 0x380),
-	MX35_PIN_A7 = _MXC_BUILD_NON_GPIO_PIN(0x44, 0x384),
-	MX35_PIN_A8 = _MXC_BUILD_NON_GPIO_PIN(0x48, 0x388),
-	MX35_PIN_A9 = _MXC_BUILD_NON_GPIO_PIN(0x4C, 0x38C),
-	MX35_PIN_A10 = _MXC_BUILD_NON_GPIO_PIN(0x50, 0x390),
-	MX35_PIN_MA10 = _MXC_BUILD_NON_GPIO_PIN(0x54, 0x394),
-	MX35_PIN_A11 = _MXC_BUILD_NON_GPIO_PIN(0x58, 0x398),
-	MX35_PIN_A12 = _MXC_BUILD_NON_GPIO_PIN(0x5C, 0x39C),
-	MX35_PIN_A13 = _MXC_BUILD_NON_GPIO_PIN(0x60, 0x3A0),
-	MX35_PIN_A14 = _MXC_BUILD_NON_GPIO_PIN(0x64, 0x3A4),
-	MX35_PIN_A15 = _MXC_BUILD_NON_GPIO_PIN(0x68, 0x3A8),
-	MX35_PIN_A16 = _MXC_BUILD_NON_GPIO_PIN(0x6C, 0x3AC),
-	MX35_PIN_A17 = _MXC_BUILD_NON_GPIO_PIN(0x70, 0x3B0),
-	MX35_PIN_A18 = _MXC_BUILD_NON_GPIO_PIN(0x74, 0x3B4),
-	MX35_PIN_A19 = _MXC_BUILD_NON_GPIO_PIN(0x78, 0x3B8),
-	MX35_PIN_A20 = _MXC_BUILD_NON_GPIO_PIN(0x7C, 0x3BC),
-	MX35_PIN_A21 = _MXC_BUILD_NON_GPIO_PIN(0x80, 0x3C0),
-	MX35_PIN_A22 = _MXC_BUILD_NON_GPIO_PIN(0x84, 0x3C4),
-	MX35_PIN_A23 = _MXC_BUILD_NON_GPIO_PIN(0x88, 0x3C8),
-	MX35_PIN_A24 = _MXC_BUILD_NON_GPIO_PIN(0x8C, 0x3CC),
-	MX35_PIN_A25 = _MXC_BUILD_NON_GPIO_PIN(0x90, 0x3D0),
-
-	MX35_PIN_EB0 = _MXC_BUILD_NON_GPIO_PIN(0x94, 0x46C),
-	MX35_PIN_EB1 = _MXC_BUILD_NON_GPIO_PIN(0x98, 0x470),
-	MX35_PIN_OE = _MXC_BUILD_NON_GPIO_PIN(0x9C, 0x474),
-	MX35_PIN_CS0 = _MXC_BUILD_NON_GPIO_PIN(0xA0, 0x478),
-	MX35_PIN_CS1 = _MXC_BUILD_NON_GPIO_PIN(0xA4, 0x47C),
-	MX35_PIN_CS2 = _MXC_BUILD_NON_GPIO_PIN(0xA8, 0x480),
-	MX35_PIN_CS3 = _MXC_BUILD_NON_GPIO_PIN(0xAC, 0x484),
-	MX35_PIN_CS4 = _MXC_BUILD_GPIO_PIN(0, 20, 0xB0, 0x488),
-	MX35_PIN_CS5 = _MXC_BUILD_GPIO_PIN(0, 21, 0xB4, 0x48C),
-	MX35_PIN_NFCE_B = _MXC_BUILD_GPIO_PIN(0, 22, 0xB8, 0x490),
-
-	MX35_PIN_LBA = _MXC_BUILD_NON_GPIO_PIN(0xBC, 0x498),
-	MX35_PIN_BCLK = _MXC_BUILD_NON_GPIO_PIN(0xC0, 0x49C),
-	MX35_PIN_RW = _MXC_BUILD_NON_GPIO_PIN(0xC4, 0x4A0),
-
-	MX35_PIN_NFWE_B = _MXC_BUILD_GPIO_PIN(0, 18, 0xC8, 0x4CC),
-	MX35_PIN_NFRE_B = _MXC_BUILD_GPIO_PIN(0, 19, 0xCC, 0x4D0),
-	MX35_PIN_NFALE = _MXC_BUILD_GPIO_PIN(0, 20, 0xD0, 0x4D4),
-	MX35_PIN_NFCLE = _MXC_BUILD_GPIO_PIN(0, 21, 0xD4, 0x4D8),
-	MX35_PIN_NFWP_B = _MXC_BUILD_GPIO_PIN(0, 22, 0xD8, 0x4DC),
-	MX35_PIN_NFRB = _MXC_BUILD_GPIO_PIN(0, 23, 0xDC, 0x4E0),
-
-	MX35_PIN_D15 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x4E4),
-	MX35_PIN_D14 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x4E8),
-	MX35_PIN_D13 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x4EC),
-	MX35_PIN_D12 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x4F0),
-	MX35_PIN_D11 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x4F4),
-	MX35_PIN_D10 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x4F8),
-	MX35_PIN_D9 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x4FC),
-	MX35_PIN_D8 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x500),
-	MX35_PIN_D7 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x504),
-	MX35_PIN_D6 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x508),
-	MX35_PIN_D5 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x50C),
-	MX35_PIN_D4 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x510),
-	MX35_PIN_D3 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x514),
-	MX35_PIN_D2 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x518),
-	MX35_PIN_D1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x51C),
-	MX35_PIN_D0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x520),
-
-	MX35_PIN_CSI_D8 = _MXC_BUILD_GPIO_PIN(0, 20, 0xE0, 0x524),
-	MX35_PIN_CSI_D9 = _MXC_BUILD_GPIO_PIN(0, 21, 0xE4, 0x528),
-	MX35_PIN_CSI_D10 = _MXC_BUILD_GPIO_PIN(0, 22, 0xE8, 0x52C),
-	MX35_PIN_CSI_D11 = _MXC_BUILD_GPIO_PIN(0, 23, 0xEC, 0x530),
-	MX35_PIN_CSI_D12 = _MXC_BUILD_GPIO_PIN(0, 24, 0xF0, 0x534),
-	MX35_PIN_CSI_D13 = _MXC_BUILD_GPIO_PIN(0, 25, 0xF4, 0x538),
-	MX35_PIN_CSI_D14 = _MXC_BUILD_GPIO_PIN(0, 26, 0xF8, 0x53C),
-	MX35_PIN_CSI_D15 = _MXC_BUILD_GPIO_PIN(0, 27, 0xFC, 0x540),
-	MX35_PIN_CSI_MCLK = _MXC_BUILD_GPIO_PIN(0, 28, 0x100, 0x544),
-	MX35_PIN_CSI_VSYNC = _MXC_BUILD_GPIO_PIN(0, 29, 0x104, 0x548),
-	MX35_PIN_CSI_HSYNC = _MXC_BUILD_GPIO_PIN(0, 30, 0x108, 0x54C),
-	MX35_PIN_CSI_PIXCLK = _MXC_BUILD_GPIO_PIN(0, 31, 0x10C, 0x550),
-
-	MX35_PIN_I2C1_CLK = _MXC_BUILD_GPIO_PIN(1, 24, 0x110, 0x554),
-	MX35_PIN_I2C1_DAT = _MXC_BUILD_GPIO_PIN(1, 25, 0x114, 0x558),
-	MX35_PIN_I2C2_CLK = _MXC_BUILD_GPIO_PIN(1, 26, 0x118, 0x55C),
-	MX35_PIN_I2C2_DAT = _MXC_BUILD_GPIO_PIN(1, 27, 0x11C, 0x560),
-
-	MX35_PIN_STXD4 = _MXC_BUILD_GPIO_PIN(1, 28, 0x120, 0x564),
-	MX35_PIN_SRXD4 = _MXC_BUILD_GPIO_PIN(1, 29, 0x124, 0x568),
-	MX35_PIN_SCK4 = _MXC_BUILD_GPIO_PIN(1, 30, 0x128, 0x56C),
-	MX35_PIN_STXFS4 = _MXC_BUILD_GPIO_PIN(1, 31, 0x12C, 0x570),
-	MX35_PIN_STXD5 = _MXC_BUILD_GPIO_PIN(0, 0, 0x130, 0x574),
-	MX35_PIN_SRXD5 = _MXC_BUILD_GPIO_PIN(0, 1, 0x134, 0x578),
-	MX35_PIN_SCK5 = _MXC_BUILD_GPIO_PIN(0, 2, 0x138, 0x57C),
-	MX35_PIN_STXFS5 = _MXC_BUILD_GPIO_PIN(0, 3, 0x13C, 0x580),
-
-	MX35_PIN_SCKR = _MXC_BUILD_GPIO_PIN(0, 4, 0x140, 0x584),
-	MX35_PIN_FSR = _MXC_BUILD_GPIO_PIN(0, 5, 0x144, 0x588),
-	MX35_PIN_HCKR = _MXC_BUILD_GPIO_PIN(0, 6, 0x148, 0x58C),
-	MX35_PIN_SCKT = _MXC_BUILD_GPIO_PIN(0, 7, 0x14C, 0x590),
-	MX35_PIN_FST = _MXC_BUILD_GPIO_PIN(0, 8, 0x150, 0x594),
-	MX35_PIN_HCKT = _MXC_BUILD_GPIO_PIN(0, 9, 0x154, 0x598),
-	MX35_PIN_TX5_RX0 = _MXC_BUILD_GPIO_PIN(0, 10, 0x158, 0x59C),
-	MX35_PIN_TX4_RX1 = _MXC_BUILD_GPIO_PIN(0, 11, 0x15C, 0x5A0),
-	MX35_PIN_TX3_RX2 = _MXC_BUILD_GPIO_PIN(0, 12, 0x160, 0x5A4),
-	MX35_PIN_TX2_RX3 = _MXC_BUILD_GPIO_PIN(0, 13, 0x164, 0x5A8),
-	MX35_PIN_TX1 = _MXC_BUILD_GPIO_PIN(0, 14, 0x168, 0x5AC),
-	MX35_PIN_TX0 = _MXC_BUILD_GPIO_PIN(0, 15, 0x16C, 0x5B0),
-
-	MX35_PIN_CSPI1_MOSI = _MXC_BUILD_GPIO_PIN(0, 16, 0x170, 0x5B4),
-	MX35_PIN_CSPI1_MISO = _MXC_BUILD_GPIO_PIN(0, 17, 0x174, 0x5B8),
-	MX35_PIN_CSPI1_SS0 = _MXC_BUILD_GPIO_PIN(0, 18, 0x178, 0x5BC),
-	MX35_PIN_CSPI1_SS1 = _MXC_BUILD_GPIO_PIN(0, 19, 0x17C, 0x5C0),
-	MX35_PIN_CSPI1_SCLK = _MXC_BUILD_GPIO_PIN(2, 4, 0x180, 0x5C4),
-	MX35_PIN_CSPI1_SPI_RDY = _MXC_BUILD_GPIO_PIN(2, 5, 0x184, 0x5C8),
-
-	MX35_PIN_RXD1 = _MXC_BUILD_GPIO_PIN(2, 6, 0x188, 0x5CC),
-	MX35_PIN_TXD1 = _MXC_BUILD_GPIO_PIN(2, 7, 0x18C, 0x5D0),
-	MX35_PIN_RTS1 = _MXC_BUILD_GPIO_PIN(2, 8, 0x190, 0x5D4),
-	MX35_PIN_CTS1 = _MXC_BUILD_GPIO_PIN(2, 9, 0x194, 0x5D8),
-	MX35_PIN_RXD2 = _MXC_BUILD_GPIO_PIN(2, 10, 0x198, 0x5DC),
-	MX35_PIN_TXD2 = _MXC_BUILD_GPIO_PIN(1, 11, 0x19C, 0x5E0),
-	MX35_PIN_RTS2 = _MXC_BUILD_GPIO_PIN(1, 12, 0x1A0, 0x5E4),
-	MX35_PIN_CTS2 = _MXC_BUILD_GPIO_PIN(1, 13, 0x1A4, 0x5E8),
-
-	MX35_PIN_USBOTG_PWR = _MXC_BUILD_GPIO_PIN(2, 14, 0x1A8, 0x60C),
-	MX35_PIN_USBOTG_OC = _MXC_BUILD_GPIO_PIN(2, 15, 0x1AC, 0x610),
-
-	MX35_PIN_LD0 = _MXC_BUILD_GPIO_PIN(1, 0, 0x1B0, 0x614),
-	MX35_PIN_LD1 = _MXC_BUILD_GPIO_PIN(1, 1, 0x1B4, 0x618),
-	MX35_PIN_LD2 = _MXC_BUILD_GPIO_PIN(1, 2, 0x1B8, 0x61C),
-	MX35_PIN_LD3 = _MXC_BUILD_GPIO_PIN(1, 3, 0x1BC, 0x620),
-	MX35_PIN_LD4 = _MXC_BUILD_GPIO_PIN(1, 4, 0x1C0, 0x624),
-	MX35_PIN_LD5 = _MXC_BUILD_GPIO_PIN(1, 5, 0x1C4, 0x628),
-	MX35_PIN_LD6 = _MXC_BUILD_GPIO_PIN(1, 6, 0x1C8, 0x62C),
-	MX35_PIN_LD7 = _MXC_BUILD_GPIO_PIN(1, 7, 0x1CC, 0x630),
-	MX35_PIN_LD8 = _MXC_BUILD_GPIO_PIN(1, 8, 0x1D0, 0x634),
-	MX35_PIN_LD9 = _MXC_BUILD_GPIO_PIN(1, 9, 0x1D4, 0x638),
-	MX35_PIN_LD10 = _MXC_BUILD_GPIO_PIN(1, 10, 0x1D8, 0x63C),
-	MX35_PIN_LD11 = _MXC_BUILD_GPIO_PIN(1, 11, 0x1DC, 0x640),
-	MX35_PIN_LD12 = _MXC_BUILD_GPIO_PIN(1, 12, 0x1E0, 0x644),
-	MX35_PIN_LD13 = _MXC_BUILD_GPIO_PIN(1, 13, 0x1E4, 0x648),
-	MX35_PIN_LD14 = _MXC_BUILD_GPIO_PIN(1, 14, 0x1E8, 0x64C),
-	MX35_PIN_LD15 = _MXC_BUILD_GPIO_PIN(1, 15, 0x1EC, 0x650),
-	MX35_PIN_LD16 = _MXC_BUILD_GPIO_PIN(1, 16, 0x1F0, 0x654),
-	MX35_PIN_LD17 = _MXC_BUILD_GPIO_PIN(1, 17, 0x1F4, 0x658),
-	MX35_PIN_LD18 = _MXC_BUILD_GPIO_PIN(2, 24, 0x1F8, 0x65C),
-	MX35_PIN_LD19 = _MXC_BUILD_GPIO_PIN(2, 25, 0x1FC, 0x660),
-	MX35_PIN_LD20 = _MXC_BUILD_GPIO_PIN(2, 26, 0x200, 0x664),
-	MX35_PIN_LD21 = _MXC_BUILD_GPIO_PIN(2, 27, 0x204, 0x668),
-	MX35_PIN_LD22 = _MXC_BUILD_GPIO_PIN(2, 28, 0x208, 0x66C),
-	MX35_PIN_LD23 = _MXC_BUILD_GPIO_PIN(2, 29, 0x20C, 0x670),
-
-	MX35_PIN_D3_HSYNC = _MXC_BUILD_GPIO_PIN(2, 30, 0x210, 0x674),
-	MX35_PIN_D3_FPSHIFT = _MXC_BUILD_GPIO_PIN(2, 31, 0x214, 0x678),
-	MX35_PIN_D3_DRDY = _MXC_BUILD_GPIO_PIN(0, 0, 0x218, 0x67C),
-	MX35_PIN_CONTRAST = _MXC_BUILD_GPIO_PIN(0, 1, 0x21C, 0x680),
-	MX35_PIN_D3_VSYNC = _MXC_BUILD_GPIO_PIN(0, 2, 0x220, 0x684),
-	MX35_PIN_D3_REV = _MXC_BUILD_GPIO_PIN(0, 3, 0x224, 0x688),
-	MX35_PIN_D3_CLS = _MXC_BUILD_GPIO_PIN(0, 4, 0x228, 0x68C),
-	MX35_PIN_D3_SPL = _MXC_BUILD_GPIO_PIN(0, 5, 0x22C, 0x690),
-
-	MX35_PIN_SD1_CMD = _MXC_BUILD_GPIO_PIN(0, 6, 0x230, 0x694),
-	MX35_PIN_SD1_CLK = _MXC_BUILD_GPIO_PIN(0, 7, 0x234, 0x698),
-	MX35_PIN_SD1_DATA0 = _MXC_BUILD_GPIO_PIN(0, 8, 0x238, 0x69C),
-	MX35_PIN_SD1_DATA1 = _MXC_BUILD_GPIO_PIN(0, 9, 0x23C, 0x6A0),
-	MX35_PIN_SD1_DATA2 = _MXC_BUILD_GPIO_PIN(0, 10, 0x240, 0x6A4),
-	MX35_PIN_SD1_DATA3 = _MXC_BUILD_GPIO_PIN(0, 11, 0x244, 0x6A8),
-	MX35_PIN_SD2_CMD = _MXC_BUILD_GPIO_PIN(1, 0, 0x248, 0x6AC),
-	MX35_PIN_SD2_CLK = _MXC_BUILD_GPIO_PIN(1, 1, 0x24C, 0x6B0),
-	MX35_PIN_SD2_DATA0 = _MXC_BUILD_GPIO_PIN(1, 2, 0x250, 0x6B4),
-	MX35_PIN_SD2_DATA1 = _MXC_BUILD_GPIO_PIN(1, 3, 0x254, 0x6B8),
-	MX35_PIN_SD2_DATA2 = _MXC_BUILD_GPIO_PIN(1, 4, 0x258, 0x6BC),
-	MX35_PIN_SD2_DATA3 = _MXC_BUILD_GPIO_PIN(1, 5, 0x25C, 0x6C0),
-
-	MX35_PIN_ATA_CS0 = _MXC_BUILD_GPIO_PIN(1, 6, 0x260, 0x6C4),
-	MX35_PIN_ATA_CS1 = _MXC_BUILD_GPIO_PIN(1, 7, 0x264, 0x6C8),
-	MX35_PIN_ATA_DIOR = _MXC_BUILD_GPIO_PIN(1, 8, 0x268, 0x6CC),
-	MX35_PIN_ATA_DIOW = _MXC_BUILD_GPIO_PIN(1, 9, 0x26C, 0x6D0),
-	MX35_PIN_ATA_DMACK = _MXC_BUILD_GPIO_PIN(1, 10, 0x270, 0x6D4),
-	MX35_PIN_ATA_RESET_B = _MXC_BUILD_GPIO_PIN(1, 11, 0x274, 0x6D8),
-	MX35_PIN_ATA_IORDY = _MXC_BUILD_GPIO_PIN(1, 12, 0x278, 0x6DC),
-	MX35_PIN_ATA_DATA0 = _MXC_BUILD_GPIO_PIN(1, 13, 0x27C, 0x6E0),
-	MX35_PIN_ATA_DATA1 = _MXC_BUILD_GPIO_PIN(1, 14, 0x280, 0x6E4),
-	MX35_PIN_ATA_DATA2 = _MXC_BUILD_GPIO_PIN(1, 15, 0x284, 0x6E8),
-	MX35_PIN_ATA_DATA3 = _MXC_BUILD_GPIO_PIN(1, 16, 0x288, 0x6EC),
-	MX35_PIN_ATA_DATA4 = _MXC_BUILD_GPIO_PIN(1, 17, 0x28C, 0x6F0),
-	MX35_PIN_ATA_DATA5 = _MXC_BUILD_GPIO_PIN(1, 18, 0x290, 0x6F4),
-	MX35_PIN_ATA_DATA6 = _MXC_BUILD_GPIO_PIN(1, 19, 0x294, 0x6F8),
-	MX35_PIN_ATA_DATA7 = _MXC_BUILD_GPIO_PIN(1, 20, 0x298, 0x6FC),
-	MX35_PIN_ATA_DATA8 = _MXC_BUILD_GPIO_PIN(1, 21, 0x29C, 0x700),
-	MX35_PIN_ATA_DATA9 = _MXC_BUILD_GPIO_PIN(1, 22, 0x2A0, 0x704),
-	MX35_PIN_ATA_DATA10 = _MXC_BUILD_GPIO_PIN(1, 23, 0x2A4, 0x708),
-	MX35_PIN_ATA_DATA11 = _MXC_BUILD_GPIO_PIN(1, 24, 0x2A8, 0x70C),
-	MX35_PIN_ATA_DATA12 = _MXC_BUILD_GPIO_PIN(1, 25, 0x2AC, 0x710),
-	MX35_PIN_ATA_DATA13 = _MXC_BUILD_GPIO_PIN(1, 26, 0x2B0, 0x714),
-	MX35_PIN_ATA_DATA14 = _MXC_BUILD_GPIO_PIN(1, 27, 0x2B4, 0x718),
-	MX35_PIN_ATA_DATA15 = _MXC_BUILD_GPIO_PIN(1, 28, 0x2B8, 0x71C),
-	MX35_PIN_ATA_INTRQ = _MXC_BUILD_GPIO_PIN(1, 29, 0x2BC, 0x720),
-	MX35_PIN_ATA_BUFF_EN = _MXC_BUILD_GPIO_PIN(1, 30, 0x2C0, 0x724),
-	MX35_PIN_ATA_DMARQ = _MXC_BUILD_GPIO_PIN(1, 31, 0x2C4, 0x728),
-	MX35_PIN_ATA_DA0 = _MXC_BUILD_GPIO_PIN(2, 0, 0x2C8, 0x72C),
-	MX35_PIN_ATA_DA1 = _MXC_BUILD_GPIO_PIN(2, 1, 0x2CC, 0x730),
-	MX35_PIN_ATA_DA2 = _MXC_BUILD_GPIO_PIN(2, 2, 0x2D0, 0x734),
-
-	MX35_PIN_MLB_CLK = _MXC_BUILD_GPIO_PIN(2, 3, 0x2D4, 0x738),
-	MX35_PIN_MLB_DAT = _MXC_BUILD_GPIO_PIN(2, 4, 0x2D8, 0x73C),
-	MX35_PIN_MLB_SIG = _MXC_BUILD_GPIO_PIN(2, 5, 0x2DC, 0x740),
-
-	MX35_PIN_FEC_TX_CLK = _MXC_BUILD_GPIO_PIN(2, 6, 0x2E0, 0x744),
-	MX35_PIN_FEC_RX_CLK = _MXC_BUILD_GPIO_PIN(2, 7, 0x2E4, 0x748),
-	MX35_PIN_FEC_RX_DV = _MXC_BUILD_GPIO_PIN(2, 8, 0x2E8, 0x74C),
-	MX35_PIN_FEC_COL = _MXC_BUILD_GPIO_PIN(2, 9, 0x2EC, 0x750),
-	MX35_PIN_FEC_RDATA0 = _MXC_BUILD_GPIO_PIN(2, 10, 0x2F0, 0x754),
-	MX35_PIN_FEC_TDATA0 = _MXC_BUILD_GPIO_PIN(2, 11, 0x2F4, 0x758),
-	MX35_PIN_FEC_TX_EN = _MXC_BUILD_GPIO_PIN(2, 12, 0x2F8, 0x75C),
-	MX35_PIN_FEC_MDC = _MXC_BUILD_GPIO_PIN(2, 13, 0x2FC, 0x760),
-	MX35_PIN_FEC_MDIO = _MXC_BUILD_GPIO_PIN(2, 14, 0x300, 0x764),
-	MX35_PIN_FEC_TX_ERR = _MXC_BUILD_GPIO_PIN(2, 15, 0x304, 0x768),
-	MX35_PIN_FEC_RX_ERR = _MXC_BUILD_GPIO_PIN(2, 16, 0x308, 0x76C),
-	MX35_PIN_FEC_CRS = _MXC_BUILD_GPIO_PIN(2, 17, 0x30C, 0x770),
-	MX35_PIN_FEC_RDATA1 = _MXC_BUILD_GPIO_PIN(2, 18, 0x310, 0x774),
-	MX35_PIN_FEC_TDATA1 = _MXC_BUILD_GPIO_PIN(2, 19, 0x314, 0x778),
-	MX35_PIN_FEC_RDATA2 = _MXC_BUILD_GPIO_PIN(2, 20, 0x318, 0x77C),
-	MX35_PIN_FEC_TDATA2 = _MXC_BUILD_GPIO_PIN(2, 21, 0x31C, 0x780),
-	MX35_PIN_FEC_RDATA3 = _MXC_BUILD_GPIO_PIN(2, 22, 0x320, 0x784),
-	MX35_PIN_FEC_TDATA3 = _MXC_BUILD_GPIO_PIN(2, 23, 0x324, 0x788),
-} iomux_pin_name_t;
-
-#endif
-#endif
diff --git a/arch/arm/include/asm/arch-mx35/sys_proto.h b/arch/arm/include/asm/arch-mx35/sys_proto.h
deleted file mode 100644
index 422eb52..0000000
--- a/arch/arm/include/asm/arch-mx35/sys_proto.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * (C) Copyright 2011
- * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef _SYS_PROTO_H_
-#define _SYS_PROTO_H_
-
-u32 get_cpu_rev(void);
-#define is_soc_rev(rev)	((get_cpu_rev() & 0xFF) - rev)
-void sdelay(unsigned long);
-
-#endif
diff --git a/arch/arm/include/asm/arch-mx5/asm-offsets.h b/arch/arm/include/asm/arch-mx5/asm-offsets.h
deleted file mode 100644
index 793f69c..0000000
--- a/arch/arm/include/asm/arch-mx5/asm-offsets.h
+++ /dev/null
@@ -1,55 +0,0 @@
-/*
- * needed for arch/arm/cpu/armv7/mx51/lowlevel_init.S
- *
- * These should be auto-generated
- */
-/* CCM */
-#define CLKCTL_CCR              0x00
-#define CLKCTL_CCDR             0x04
-#define CLKCTL_CSR              0x08
-#define CLKCTL_CCSR             0x0C
-#define CLKCTL_CACRR            0x10
-#define CLKCTL_CBCDR            0x14
-#define CLKCTL_CBCMR            0x18
-#define CLKCTL_CSCMR1           0x1C
-#define CLKCTL_CSCMR2           0x20
-#define CLKCTL_CSCDR1           0x24
-#define CLKCTL_CS1CDR           0x28
-#define CLKCTL_CS2CDR           0x2C
-#define CLKCTL_CDCDR            0x30
-#define CLKCTL_CHSCCDR          0x34
-#define CLKCTL_CSCDR2           0x38
-#define CLKCTL_CSCDR3           0x3C
-#define CLKCTL_CSCDR4           0x40
-#define CLKCTL_CWDR             0x44
-#define CLKCTL_CDHIPR           0x48
-#define CLKCTL_CDCR             0x4C
-#define CLKCTL_CTOR             0x50
-#define CLKCTL_CLPCR            0x54
-#define CLKCTL_CISR             0x58
-#define CLKCTL_CIMR             0x5C
-#define CLKCTL_CCOSR            0x60
-#define CLKCTL_CGPR             0x64
-#define CLKCTL_CCGR0            0x68
-#define CLKCTL_CCGR1            0x6C
-#define CLKCTL_CCGR2            0x70
-#define CLKCTL_CCGR3            0x74
-#define CLKCTL_CCGR4            0x78
-#define CLKCTL_CCGR5            0x7C
-#define CLKCTL_CCGR6            0x80
-#if defined(CONFIG_MX53)
-#define CLKCTL_CCGR7            0x84
-#define CLKCTL_CMEOR            0x88
-#elif defined(CONFIG_MX51)
-#define CLKCTL_CMEOR            0x84
-#endif
-
-/* DPLL */
-#define PLL_DP_CTL	0x00
-#define PLL_DP_CONFIG	0x04
-#define PLL_DP_OP	0x08
-#define PLL_DP_MFD	0x0C
-#define PLL_DP_MFN	0x10
-#define PLL_DP_HFS_OP	0x1C
-#define PLL_DP_HFS_MFD	0x20
-#define PLL_DP_HFS_MFN	0x24
diff --git a/arch/arm/include/asm/arch-mx5/clock.h b/arch/arm/include/asm/arch-mx5/clock.h
deleted file mode 100644
index 1f8a537..0000000
--- a/arch/arm/include/asm/arch-mx5/clock.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/*
- * (C) Copyright 2009
- * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __ASM_ARCH_CLOCK_H
-#define __ASM_ARCH_CLOCK_H
-
-enum mxc_clock {
-	MXC_ARM_CLK = 0,
-	MXC_AHB_CLK,
-	MXC_IPG_CLK,
-	MXC_IPG_PERCLK,
-	MXC_UART_CLK,
-	MXC_CSPI_CLK,
-	MXC_FEC_CLK,
-};
-
-unsigned int imx_decode_pll(unsigned int pll, unsigned int f_ref);
-
-u32 imx_get_uartclk(void);
-u32 imx_get_fecclk(void);
-unsigned int mxc_get_clock(enum mxc_clock clk);
-
-#endif /* __ASM_ARCH_CLOCK_H */
diff --git a/arch/arm/include/asm/arch-mx5/crm_regs.h b/arch/arm/include/asm/arch-mx5/crm_regs.h
deleted file mode 100644
index 4ed8eb3..0000000
--- a/arch/arm/include/asm/arch-mx5/crm_regs.h
+++ /dev/null
@@ -1,203 +0,0 @@
-/*
- * (C) Copyright 2009 Freescale Semiconductor, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __ARCH_ARM_MACH_MX51_CRM_REGS_H__
-#define __ARCH_ARM_MACH_MX51_CRM_REGS_H__
-
-#define MXC_CCM_BASE	CCM_BASE_ADDR
-
-/* DPLL register mapping structure */
-struct mxc_pll_reg {
-	u32 ctrl;
-	u32 config;
-	u32 op;
-	u32 mfd;
-	u32 mfn;
-	u32 mfn_minus;
-	u32 mfn_plus;
-	u32 hfs_op;
-	u32 hfs_mfd;
-	u32 hfs_mfn;
-	u32 mfn_togc;
-	u32 destat;
-};
-
-/* Register maping of CCM*/
-struct mxc_ccm_reg {
-	u32 ccr;	/* 0x0000 */
-	u32 ccdr;
-	u32 csr;
-	u32 ccsr;
-	u32 cacrr;	/* 0x0010*/
-	u32 cbcdr;
-	u32 cbcmr;
-	u32 cscmr1;
-	u32 cscmr2;	/* 0x0020 */
-	u32 cscdr1;
-	u32 cs1cdr;
-	u32 cs2cdr;
-	u32 cdcdr;	/* 0x0030 */
-	u32 chscdr;
-	u32 cscdr2;
-	u32 cscdr3;
-	u32 cscdr4;	/* 0x0040 */
-	u32 cwdr;
-	u32 cdhipr;
-	u32 cdcr;
-	u32 ctor;	/* 0x0050 */
-	u32 clpcr;
-	u32 cisr;
-	u32 cimr;
-	u32 ccosr;	/* 0x0060 */
-	u32 cgpr;
-	u32 CCGR0;
-	u32 CCGR1;
-	u32 CCGR2;	/* 0x0070 */
-	u32 CCGR3;
-	u32 CCGR4;
-	u32 CCGR5;
-	u32 CCGR6;	/* 0x0080 */
-	u32 cmeor;
-};
-
-/* Define the bits in register CACRR */
-#define MXC_CCM_CACRR_ARM_PODF_OFFSET		0
-#define MXC_CCM_CACRR_ARM_PODF_MASK		0x7
-
-/* Define the bits in register CBCDR */
-#define MXC_CCM_CBCDR_EMI_CLK_SEL		(0x1 << 26)
-#define MXC_CCM_CBCDR_PERIPH_CLK_SEL		(0x1 << 25)
-#define MXC_CCM_CBCDR_EMI_PODF_OFFSET		22
-#define MXC_CCM_CBCDR_EMI_PODF_MASK		(0x7 << 22)
-#define MXC_CCM_CBCDR_AXI_B_PODF_OFFSET		19
-#define MXC_CCM_CBCDR_AXI_B_PODF_MASK		(0x7 << 19)
-#define MXC_CCM_CBCDR_AXI_A_PODF_OFFSET		16
-#define MXC_CCM_CBCDR_AXI_A_PODF_MASK		(0x7 << 16)
-#define MXC_CCM_CBCDR_NFC_PODF_OFFSET		13
-#define MXC_CCM_CBCDR_NFC_PODF_MASK		(0x7 << 13)
-#define MXC_CCM_CBCDR_AHB_PODF_OFFSET		10
-#define MXC_CCM_CBCDR_AHB_PODF_MASK		(0x7 << 10)
-#define MXC_CCM_CBCDR_IPG_PODF_OFFSET		8
-#define MXC_CCM_CBCDR_IPG_PODF_MASK		(0x3 << 8)
-#define MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET	6
-#define MXC_CCM_CBCDR_PERCLK_PRED1_MASK		(0x3 << 6)
-#define MXC_CCM_CBCDR_PERCLK_PRED2_OFFSET	3
-#define MXC_CCM_CBCDR_PERCLK_PRED2_MASK		(0x7 << 3)
-#define MXC_CCM_CBCDR_PERCLK_PODF_OFFSET	0
-#define MXC_CCM_CBCDR_PERCLK_PODF_MASK		0x7
-
-/* Define the bits in register CSCMR1 */
-#define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_OFFSET		30
-#define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_MASK		(0x3 << 30)
-#define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_OFFSET		28
-#define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_MASK		(0x3 << 28)
-#define MXC_CCM_CSCMR1_USB_PHY_CLK_SEL_OFFSET		26
-#define MXC_CCM_CSCMR1_USB_PHY_CLK_SEL			(0x1 << 26)
-#define MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET		24
-#define MXC_CCM_CSCMR1_UART_CLK_SEL_MASK		(0x3 << 24)
-#define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_OFFSET		22
-#define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_MASK		(0x3 << 22)
-#define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_OFFSET	20
-#define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_MASK	(0x3 << 20)
-#define MXC_CCM_CSCMR1_ESDHC3_CLK_SEL			(0x1 << 19)
-#define MXC_CCM_CSCMR1_ESDHC4_CLK_SEL			(0x1 << 18)
-#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_OFFSET	16
-#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_MASK	(0x3 << 16)
-#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET		14
-#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK		(0x3 << 14)
-#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET		12
-#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK		(0x3 << 12)
-#define MXC_CCM_CSCMR1_SSI3_CLK_SEL			(0x1 << 11)
-#define MXC_CCM_CSCMR1_VPU_RCLK_SEL			(0x1 << 10)
-#define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_OFFSET		8
-#define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_MASK		(0x3 << 8)
-#define MXC_CCM_CSCMR1_TVE_CLK_SEL			(0x1 << 7)
-#define MXC_CCM_CSCMR1_TVE_EXT_CLK_SEL			(0x1 << 6)
-#define MXC_CCM_CSCMR1_CSPI_CLK_SEL_OFFSET		4
-#define MXC_CCM_CSCMR1_CSPI_CLK_SEL_MASK		(0x3 << 4)
-#define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_OFFSET		2
-#define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_MASK		(0x3 << 2)
-#define MXC_CCM_CSCMR1_SSI_EXT2_COM_CLK_SEL		(0x1 << 1)
-#define MXC_CCM_CSCMR1_SSI_EXT1_COM_CLK_SEL		0x1
-
-/* Define the bits in register CSCDR2 */
-#define MXC_CCM_CSCDR2_CSPI_CLK_PRED_OFFSET		25
-#define MXC_CCM_CSCDR2_CSPI_CLK_PRED_MASK		(0x7 << 25)
-#define MXC_CCM_CSCDR2_CSPI_CLK_PODF_OFFSET		19
-#define MXC_CCM_CSCDR2_CSPI_CLK_PODF_MASK		(0x3F << 19)
-#define MXC_CCM_CSCDR2_SIM_CLK_PRED_OFFSET		16
-#define MXC_CCM_CSCDR2_SIM_CLK_PRED_MASK		(0x7 << 16)
-#define MXC_CCM_CSCDR2_SIM_CLK_PODF_OFFSET		9
-#define MXC_CCM_CSCDR2_SIM_CLK_PODF_MASK		(0x3F << 9)
-#define MXC_CCM_CSCDR2_SLIMBUS_CLK_PRED_OFFSET		6
-#define MXC_CCM_CSCDR2_SLIMBUS_PRED_MASK		(0x7 << 6)
-#define MXC_CCM_CSCDR2_SLIMBUS_PODF_OFFSET		0
-#define MXC_CCM_CSCDR2_SLIMBUS_PODF_MASK		0x3F
-
-/* Define the bits in register CBCMR */
-#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET		14
-#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK		(0x3 << 14)
-#define MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET		12
-#define MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK		(0x3 << 12)
-#define MXC_CCM_CBCMR_DDR_CLK_SEL_OFFSET		10
-#define MXC_CCM_CBCMR_DDR_CLK_SEL_MASK			(0x3 << 10)
-#define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_OFFSET		8
-#define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_MASK		(0x3 << 8)
-#define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_OFFSET		6
-#define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_MASK		(0x3 << 6)
-#define MXC_CCM_CBCMR_GPU_CLK_SEL_OFFSET		4
-#define MXC_CCM_CBCMR_GPU_CLK_SEL_MASK			(0x3 << 4)
-#define MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL		(0x1 << 1)
-#define MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL		(0x1 << 0)
-
-/* Define the bits in register CSCDR1 */
-#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_OFFSET	22
-#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_MASK	(0x7 << 22)
-#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_OFFSET	19
-#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_MASK	(0x7 << 19)
-#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_OFFSET	16
-#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_MASK	(0x7 << 16)
-#define MXC_CCM_CSCDR1_PGC_CLK_PODF_OFFSET		14
-#define MXC_CCM_CSCDR1_PGC_CLK_PODF_MASK		(0x3 << 14)
-#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_OFFSET	11
-#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_MASK	(0x7 << 11)
-#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET		8
-#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK		(0x7 << 8)
-#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET		6
-#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK		(0x3 << 6)
-#define MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET		3
-#define MXC_CCM_CSCDR1_UART_CLK_PRED_MASK		(0x7 << 3)
-#define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET		0
-#define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK		0x7
-
-/* Define the bits in register CCDR */
-#define MXC_CCM_CCDR_IPU_HS_MASK			(0x1 << 17)
-
-/* Define the bits in register CCGRx */
-#define MXC_CCM_CCGR_CG_MASK				0x3
-
-#define MXC_CCM_CCGR5_CG5_OFFSET			10
-
-/* Define the bits in register CLPCR */
-#define MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS                 (0x1 << 18)
-
-#endif				/* __ARCH_ARM_MACH_MX51_CRM_REGS_H__ */
diff --git a/arch/arm/include/asm/arch-mx5/imx-regs.h b/arch/arm/include/asm/arch-mx5/imx-regs.h
deleted file mode 100644
index a1849f8..0000000
--- a/arch/arm/include/asm/arch-mx5/imx-regs.h
+++ /dev/null
@@ -1,302 +0,0 @@
-/*
- * (C) Copyright 2009 Freescale Semiconductor, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __ASM_ARCH_MX5_IMX_REGS_H__
-#define __ASM_ARCH_MX5_IMX_REGS_H__
-
-#if defined(CONFIG_MX51)
-#define IRAM_BASE_ADDR		0x1FFE0000	/* internal ram */
-#define IPU_CTRL_BASE_ADDR	0x40000000
-#define SPBA0_BASE_ADDR         0x70000000
-#define AIPS1_BASE_ADDR         0x73F00000
-#define AIPS2_BASE_ADDR         0x83F00000
-#define CSD0_BASE_ADDR          0x90000000
-#define CSD1_BASE_ADDR          0xA0000000
-#define NFC_BASE_ADDR_AXI       0xCFFF0000
-#elif defined(CONFIG_MX53)
-#define IPU_CTRL_BASE_ADDR      0x18000000
-#define SPBA0_BASE_ADDR         0x50000000
-#define AIPS1_BASE_ADDR         0x53F00000
-#define AIPS2_BASE_ADDR         0x63F00000
-#define CSD0_BASE_ADDR          0x70000000
-#define CSD1_BASE_ADDR          0xB0000000
-#define NFC_BASE_ADDR_AXI       0xF7FF0000
-#define IRAM_BASE_ADDR          0xF8000000
-#else
-#error "CPU_TYPE not defined"
-#endif
-
-#define IRAM_SIZE		0x00020000	/* 128 KB */
-
-/*
- * SPBA global module enabled #0
- */
-#define MMC_SDHC1_BASE_ADDR	(SPBA0_BASE_ADDR + 0x00004000)
-#define MMC_SDHC2_BASE_ADDR	(SPBA0_BASE_ADDR + 0x00008000)
-#define UART3_BASE_ADDR 	(SPBA0_BASE_ADDR + 0x0000C000)
-#define CSPI1_BASE_ADDR 	(SPBA0_BASE_ADDR + 0x00010000)
-#define SSI2_BASE_ADDR		(SPBA0_BASE_ADDR + 0x00014000)
-#define MMC_SDHC3_BASE_ADDR	(SPBA0_BASE_ADDR + 0x00020000)
-#define MMC_SDHC4_BASE_ADDR	(SPBA0_BASE_ADDR + 0x00024000)
-#define SPDIF_BASE_ADDR		(SPBA0_BASE_ADDR + 0x00028000)
-#define ATA_DMA_BASE_ADDR	(SPBA0_BASE_ADDR + 0x00030000)
-#define SLIM_DMA_BASE_ADDR	(SPBA0_BASE_ADDR + 0x00034000)
-#define HSI2C_DMA_BASE_ADDR	(SPBA0_BASE_ADDR + 0x00038000)
-#define SPBA_CTRL_BASE_ADDR	(SPBA0_BASE_ADDR + 0x0003C000)
-
-/*
- * AIPS 1
- */
-#define OTG_BASE_ADDR		(AIPS1_BASE_ADDR + 0x00080000)
-#define GPIO1_BASE_ADDR		(AIPS1_BASE_ADDR + 0x00084000)
-#define GPIO2_BASE_ADDR		(AIPS1_BASE_ADDR + 0x00088000)
-#define GPIO3_BASE_ADDR		(AIPS1_BASE_ADDR + 0x0008C000)
-#define GPIO4_BASE_ADDR		(AIPS1_BASE_ADDR + 0x00090000)
-#define KPP_BASE_ADDR		(AIPS1_BASE_ADDR + 0x00094000)
-#define WDOG1_BASE_ADDR		(AIPS1_BASE_ADDR + 0x00098000)
-#define WDOG2_BASE_ADDR		(AIPS1_BASE_ADDR + 0x0009C000)
-#define GPT1_BASE_ADDR		(AIPS1_BASE_ADDR + 0x000A0000)
-#define SRTC_BASE_ADDR		(AIPS1_BASE_ADDR + 0x000A4000)
-#define IOMUXC_BASE_ADDR	(AIPS1_BASE_ADDR + 0x000A8000)
-#define EPIT1_BASE_ADDR		(AIPS1_BASE_ADDR + 0x000AC000)
-#define EPIT2_BASE_ADDR		(AIPS1_BASE_ADDR + 0x000B0000)
-#define PWM1_BASE_ADDR		(AIPS1_BASE_ADDR + 0x000B4000)
-#define PWM2_BASE_ADDR		(AIPS1_BASE_ADDR + 0x000B8000)
-#define UART1_BASE_ADDR		(AIPS1_BASE_ADDR + 0x000BC000)
-#define UART2_BASE_ADDR		(AIPS1_BASE_ADDR + 0x000C0000)
-#define SRC_BASE_ADDR		(AIPS1_BASE_ADDR + 0x000D0000)
-#define CCM_BASE_ADDR		(AIPS1_BASE_ADDR + 0x000D4000)
-#define GPC_BASE_ADDR		(AIPS1_BASE_ADDR + 0x000D8000)
-
-#if defined(CONFIG_MX53)
-#define GPIO5_BASE_ADDR         (AIPS1_BASE_ADDR + 0x000DC000)
-#define GPIO6_BASE_ADDR         (AIPS1_BASE_ADDR + 0x000E0000)
-#define GPIO7_BASE_ADDR         (AIPS1_BASE_ADDR + 0x000E4000)
-#endif
-/*
- * AIPS 2
- */
-#define PLL1_BASE_ADDR		(AIPS2_BASE_ADDR + 0x00080000)
-#define PLL2_BASE_ADDR		(AIPS2_BASE_ADDR + 0x00084000)
-#define PLL3_BASE_ADDR		(AIPS2_BASE_ADDR + 0x00088000)
-#define AHBMAX_BASE_ADDR	(AIPS2_BASE_ADDR + 0x00094000)
-#define IIM_BASE_ADDR		(AIPS2_BASE_ADDR + 0x00098000)
-#define CSU_BASE_ADDR		(AIPS2_BASE_ADDR + 0x0009C000)
-#define ARM_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000A0000)
-#define OWIRE_BASE_ADDR 	(AIPS2_BASE_ADDR + 0x000A4000)
-#define FIRI_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000A8000)
-#define CSPI2_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000AC000)
-#define SDMA_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000B0000)
-#define SCC_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000B4000)
-#define ROMCP_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000B8000)
-#define RTIC_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000BC000)
-#define CSPI3_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000C0000)
-#define I2C2_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000C4000)
-#define I2C1_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000C8000)
-#define SSI1_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000CC000)
-#define AUDMUX_BASE_ADDR	(AIPS2_BASE_ADDR + 0x000D0000)
-#define M4IF_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000D8000)
-#define ESDCTL_BASE_ADDR	(AIPS2_BASE_ADDR + 0x000D9000)
-#define WEIM_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000DA000)
-#define NFC_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000DB000)
-#define EMI_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000DBF00)
-#define MIPI_HSC_BASE_ADDR	(AIPS2_BASE_ADDR + 0x000DC000)
-#define ATA_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000E0000)
-#define SIM_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000E4000)
-#define SSI3BASE_ADDR		(AIPS2_BASE_ADDR + 0x000E8000)
-#define FEC_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000EC000)
-#define TVE_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000F0000)
-#define VPU_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000F4000)
-#define SAHARA_BASE_ADDR	(AIPS2_BASE_ADDR + 0x000F8000)
-
-/*
- * Number of GPIO pins per port
- */
-#define GPIO_NUM_PIN            32
-
-#define IIM_SREV	0x24
-#define ROM_SI_REV	0x48
-
-#define NFC_BUF_SIZE	0x1000
-
-/* M4IF */
-#define M4IF_FBPM0	0x40
-#define M4IF_FIDBP	0x48
-
-/* Assuming 24MHz input clock with doubler ON */
-/*                            MFI         PDF */
-#define DP_OP_850	((8 << 4) + ((1 - 1)  << 0))
-#define DP_MFD_850	(48 - 1)
-#define DP_MFN_850	41
-
-#define DP_OP_800	((8 << 4) + ((1 - 1)  << 0))
-#define DP_MFD_800	(3 - 1)
-#define DP_MFN_800	1
-
-#define DP_OP_700	((7 << 4) + ((1 - 1)  << 0))
-#define DP_MFD_700	(24 - 1)
-#define DP_MFN_700	7
-
-#define DP_OP_665	((6 << 4) + ((1 - 1)  << 0))
-#define DP_MFD_665	(96 - 1)
-#define DP_MFN_665	89
-
-#define DP_OP_532	((5 << 4) + ((1 - 1)  << 0))
-#define DP_MFD_532	(24 - 1)
-#define DP_MFN_532	13
-
-#define DP_OP_400	((8 << 4) + ((2 - 1)  << 0))
-#define DP_MFD_400	(3 - 1)
-#define DP_MFN_400	1
-
-#define DP_OP_216	((6 << 4) + ((3 - 1)  << 0))
-#define DP_MFD_216	(4 - 1)
-#define DP_MFN_216	3
-
-#define CHIP_REV_1_0            0x10
-#define CHIP_REV_1_1            0x11
-#define CHIP_REV_2_0            0x20
-#define CHIP_REV_2_5		0x25
-#define CHIP_REV_3_0            0x30
-
-#define BOARD_REV_1_0           0x0
-#define BOARD_REV_2_0           0x1
-
-#define IMX_IIM_BASE            (IIM_BASE_ADDR)
-
-#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
-#include <asm/types.h>
-
-extern void imx_get_mac_from_fuse(unsigned char *mac);
-
-#define __REG(x)	(*((volatile u32 *)(x)))
-#define __REG16(x)	(*((volatile u16 *)(x)))
-#define __REG8(x)	(*((volatile u8 *)(x)))
-
-struct clkctl {
-	u32	ccr;
-	u32	ccdr;
-	u32	csr;
-	u32	ccsr;
-	u32	cacrr;
-	u32	cbcdr;
-	u32	cbcmr;
-	u32	cscmr1;
-	u32	cscmr2;
-	u32	cscdr1;
-	u32	cs1cdr;
-	u32	cs2cdr;
-	u32	cdcdr;
-	u32	chsccdr;
-	u32	cscdr2;
-	u32	cscdr3;
-	u32	cscdr4;
-	u32	cwdr;
-	u32	cdhipr;
-	u32	cdcr;
-	u32	ctor;
-	u32	clpcr;
-	u32	cisr;
-	u32	cimr;
-	u32	ccosr;
-	u32	cgpr;
-	u32	ccgr0;
-	u32	ccgr1;
-	u32	ccgr2;
-	u32	ccgr3;
-	u32	ccgr4;
-	u32	ccgr5;
-	u32	ccgr6;
-	u32	cmeor;
-};
-
-/* WEIM registers */
-struct weim {
-	u32	csgcr1;
-	u32	csgcr2;
-	u32	csrcr1;
-	u32	csrcr2;
-	u32	cswcr1;
-	u32	cswcr2;
-};
-
-/* GPIO Registers */
-struct gpio_regs {
-	u32	gpio_dr;
-	u32	gpio_dir;
-	u32	gpio_psr;
-};
-
-/* System Reset Controller (SRC) */
-struct src {
-	u32	scr;
-	u32	sbmr;
-	u32	srsr;
-	u32	reserved1[2];
-	u32	sisr;
-	u32	simr;
-};
-
-/* CSPI registers */
-struct cspi_regs {
-	u32 rxdata;
-	u32 txdata;
-	u32 ctrl;
-	u32 cfg;
-	u32 intr;
-	u32 dma;
-	u32 stat;
-	u32 period;
-};
-
-struct iim_regs {
-	u32	stat;
-	u32	statm;
-	u32     err;
-	u32	emask;
-	u32	fctl;
-	u32	ua;
-	u32	la;
-	u32	sdat;
-	u32	prev;
-	u32	srev;
-	u32	preg_p;
-	u32	scs0;
-	u32	scs1;
-	u32	scs2;
-	u32	scs3;
-	u32	res0[0x1f1];
-	struct fuse_bank {
-		u32	fuse_regs[0x20];
-		u32	fuse_rsvd[0xe0];
-	} bank[4];
-};
-
-struct fuse_bank1_regs {
-	u32	fuse0_8[9];
-	u32	mac_addr[6];
-	u32	fuse15_31[0x11];
-};
-
-#endif /* __ASSEMBLER__*/
-
-#endif				/* __ASM_ARCH_MX5_IMX_REGS_H__ */
diff --git a/arch/arm/include/asm/arch-mx5/iomux.h b/arch/arm/include/asm/arch-mx5/iomux.h
deleted file mode 100644
index 760371b..0000000
--- a/arch/arm/include/asm/arch-mx5/iomux.h
+++ /dev/null
@@ -1,91 +0,0 @@
-/*
- * (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __MACH_MX5_IOMUX_H__
-#define __MACH_MX5_IOMUX_H__
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/mx5x_pins.h>
-
-typedef unsigned int iomux_pin_name_t;
-
-/* various IOMUX output functions */
-typedef enum iomux_config {
-	IOMUX_CONFIG_ALT0,	/*!< used as alternate function 0 */
-	IOMUX_CONFIG_ALT1,	/*!< used as alternate function 1 */
-	IOMUX_CONFIG_ALT2,	/*!< used as alternate function 2 */
-	IOMUX_CONFIG_ALT3,	/*!< used as alternate function 3 */
-	IOMUX_CONFIG_ALT4,	/*!< used as alternate function 4 */
-	IOMUX_CONFIG_ALT5,	/*!< used as alternate function 5 */
-	IOMUX_CONFIG_ALT6,	/*!< used as alternate function 6 */
-	IOMUX_CONFIG_ALT7,	/*!< used as alternate function 7 */
-	IOMUX_CONFIG_GPIO,	/*!< added to help user use GPIO mode */
-	IOMUX_CONFIG_SION = 0x1 << 4,	/*!< used as LOOPBACK:MUX SION bit */
-} iomux_pin_cfg_t;
-
-/* various IOMUX pad functions */
-typedef enum iomux_pad_config {
-	PAD_CTL_SRE_SLOW = 0x0 << 0,	/* Slow slew rate */
-	PAD_CTL_SRE_FAST = 0x1 << 0,	/* Fast slew rate */
-	PAD_CTL_DRV_LOW = 0x0 << 1,	/* Low drive strength */
-	PAD_CTL_DRV_MEDIUM = 0x1 << 1,	/* Medium drive strength */
-	PAD_CTL_DRV_HIGH = 0x2 << 1,	/* High drive strength */
-	PAD_CTL_DRV_MAX = 0x3 << 1,	/* Max drive strength */
-	PAD_CTL_ODE_OPENDRAIN_NONE = 0x0 << 3,	/* Opendrain disable */
-	PAD_CTL_ODE_OPENDRAIN_ENABLE = 0x1 << 3,/* Opendrain enable */
-	PAD_CTL_100K_PD = 0x0 << 4,	/* 100Kohm pulldown */
-	PAD_CTL_47K_PU = 0x1 << 4,	/* 47Kohm pullup */
-	PAD_CTL_100K_PU = 0x2 << 4,	/* 100Kohm pullup */
-	PAD_CTL_22K_PU = 0x3 << 4,	/* 22Kohm pullup */
-	PAD_CTL_PUE_KEEPER = 0x0 << 6,	/* enable pulldown */
-	PAD_CTL_PUE_PULL = 0x1 << 6,	/* enable pullup */
-	PAD_CTL_PKE_NONE = 0x0 << 7,	/* Disable pullup/pulldown */
-	PAD_CTL_PKE_ENABLE = 0x1 << 7,	/* Enable pullup/pulldown */
-	PAD_CTL_HYS_NONE = 0x0 << 8,	/* Hysteresis disabled */
-	PAD_CTL_HYS_ENABLE = 0x1 << 8,	/* Hysteresis enabled */
-	PAD_CTL_DDR_INPUT_CMOS = 0x0 << 9,/* DDR input CMOS */
-	PAD_CTL_DDR_INPUT_DDR = 0x1 << 9,/* DDR input DDR */
-	PAD_CTL_DRV_VOT_LOW = 0x0 << 13, /* Low voltage mode */
-	PAD_CTL_DRV_VOT_HIGH = 0x1 << 13,/* High voltage mode */
-} iomux_pad_config_t;
-
-/* various IOMUX input functions */
-typedef enum iomux_input_config {
-	INPUT_CTL_PATH0 = 0x0,
-	INPUT_CTL_PATH1,
-	INPUT_CTL_PATH2,
-	INPUT_CTL_PATH3,
-	INPUT_CTL_PATH4,
-	INPUT_CTL_PATH5,
-	INPUT_CTL_PATH6,
-	INPUT_CTL_PATH7,
-} iomux_input_config_t;
-
-void mxc_request_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t config);
-void mxc_free_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t config);
-void mxc_iomux_set_pad(iomux_pin_name_t pin, u32 config);
-unsigned int mxc_iomux_get_pad(iomux_pin_name_t pin);
-void mxc_iomux_set_input(iomux_input_select_t input, u32 config);
-
-#endif				/*  __MACH_MX5_IOMUX_H__ */
diff --git a/arch/arm/include/asm/arch-mx5/mx5x_pins.h b/arch/arm/include/asm/arch-mx5/mx5x_pins.h
deleted file mode 100644
index 4e3a31b..0000000
--- a/arch/arm/include/asm/arch-mx5/mx5x_pins.h
+++ /dev/null
@@ -1,881 +0,0 @@
-/*
- * (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __ASM_ARCH_MX5_MX5X_PINS_H__
-#define __ASM_ARCH_MX5_MX5X_PINS_H__
-
-#ifndef __ASSEMBLY__
-
-/*
- * In order to identify pins more effectively, each mux-controlled pin's
- * enumerated value is constructed in the following way:
- *
- * -------------------------------------------------------------------
- * 31-29 | 28 - 24 |  23 - 21 | 20  - 10| 9 - 0
- * -------------------------------------------------------------------
- * IO_P  |  IO_I   | GPIO_I   | PAD_I   | MUX_I
- * -------------------------------------------------------------------
- *
- * Bit 0 to 9 contains MUX_I used to identify the register
- * offset (0-based. base is IOMUX_module_base) defined in the Section
- * "sw_pad_ctl & sw_mux_ctl details" of the IC Spec. The
- * similar field definitions are used for the pad control register.
- * The IOMUX controller can be split in two parts. At the begeinning,
- * there is the register definitions for the multiplexing each pin.
- * Then there is a set of registers (PAD_I) to configure each pin
- * (pullup, pulldown, etc).
- * PAD_I defines the offset of the pad register for each pin.
- * GPIO_I defines, if available, the number of gpio that can be
- * connected to that pad
- * IO_I defines the multiplexer mode required to set the pad in gpio mode
- * IO_P defines the gpio structure (gpio1..gpio4) the pad belongs
- *
- * For example, the MX51_PIN_ETM_D0 is defined in the enumeration:
- *    ( (0x28 - MUX_I_START) << MUX_I)|( (0x250 - PAD_I_START) << PAD_I)
- * It means the mux control register is at register offset 0x28. The pad control
- * register offset is: 0x250 and also occupy the least significant bits
- * within the register.
- */
-
-/*!
- * Starting bit position within each entry of \b iomux_pins to represent the
- * MUX control register offset
- */
-#define MUX_I			0
-/*!
- * Starting bit position within each entry of \b iomux_pins to represent the
- * PAD control register offset
- */
-#define PAD_I			10
-/*!
- * Starting bit position within each entry of \b iomux_pins to represent which
- * mux mode is for GPIO (0-based)
- */
-#define GPIO_I			21
-
-#define MUX_IO_P                29
-#define MUX_IO_I                24
-#define IOMUX_TO_GPIO(pin)      ((((unsigned int)pin >> MUX_IO_P) * \
-					GPIO_NUM_PIN) + ((pin >> MUX_IO_I) &\
-					((1 << (MUX_IO_P - MUX_IO_I)) - 1)))
-#define IOMUX_TO_IRQ(pin)       (MXC_GPIO_INT_BASE + IOMUX_TO_GPIO(pin))
-#define GPIO_TO_PORT(n)         (n / GPIO_NUM_PIN)
-#define GPIO_TO_INDEX(n)        (n % GPIO_NUM_PIN)
-
-#define NON_GPIO_PORT		0x7
-#define PIN_TO_MUX_MASK		((1 << (PAD_I - MUX_I)) - 1)
-#define PIN_TO_PAD_MASK		((1 << (GPIO_I - PAD_I)) - 1)
-#define PIN_TO_ALT_GPIO_MASK		((1 << (MUX_IO_I - GPIO_I)) - 1)
-
-#define NON_MUX_I              PIN_TO_MUX_MASK
-#define NON_PAD_I              PIN_TO_PAD_MASK
-
-#if defined(CONFIG_MX51)
-#define MUX_I_START		0x001C
-#define PAD_I_START		0x3F0
-#define INPUT_CTL_START		0x8C4
-#define MUX_I_END		(PAD_I_START - 4)
-#elif defined(CONFIG_MX53)
-#define MUX_I_START            0x0020
-#define PAD_I_START            0x348
-#define INPUT_CTL_START        0x730
-#define MUX_I_END              (PAD_I_START - 4)
-#else
-#error "CPU_TYPE not defined"
-#endif
-
-#define _MXC_BUILD_PIN(gp, gi, ga, mi, pi) \
-	(((gp) << MUX_IO_P) | ((gi) << MUX_IO_I) | \
-	((mi) << MUX_I) | \
-	((pi - PAD_I_START) << PAD_I) | \
-	((ga) << GPIO_I))
-
-#define _MXC_BUILD_GPIO_PIN(gp, gi, ga, mi, pi) \
-	_MXC_BUILD_PIN(gp, gi, ga, mi, pi)
-
-#define _MXC_BUILD_NON_GPIO_PIN(mi, pi) \
-	_MXC_BUILD_PIN(NON_GPIO_PORT, 0, 0, mi, pi)
-
-#define PIN_TO_IOMUX_MUX(pin)	((pin >> MUX_I) & PIN_TO_MUX_MASK)
-#define PIN_TO_IOMUX_PAD(pin)	((pin >> PAD_I) & PIN_TO_PAD_MASK)
-#define PIN_TO_ALT_GPIO(pin)	((pin >> GPIO_I) & PIN_TO_ALT_GPIO_MASK)
-#define PIN_TO_IOMUX_INDEX(pin)	(PIN_TO_IOMUX_MUX(pin) >> 2)
-
-/*
- * This enumeration is constructed based on the Section
- * "sw_pad_ctl & sw_mux_ctl details" of the MX51 IC Spec. Each enumerated
- * value is constructed based on the rules described above.
- */
-enum {
-	MX51_PIN_EIM_DA0 = _MXC_BUILD_NON_GPIO_PIN(0x1C, 0x7A8),
-	MX51_PIN_EIM_DA1 = _MXC_BUILD_NON_GPIO_PIN(0x20, 0x7A8),
-	MX51_PIN_EIM_DA2 = _MXC_BUILD_NON_GPIO_PIN(0x24, 0x7A8),
-	MX51_PIN_EIM_DA3 = _MXC_BUILD_NON_GPIO_PIN(0x28, 0x7A8),
-	MX51_PIN_EIM_DA4 = _MXC_BUILD_NON_GPIO_PIN(0x2C, 0x7AC),
-	MX51_PIN_EIM_DA5 = _MXC_BUILD_NON_GPIO_PIN(0x30, 0x7AC),
-	MX51_PIN_EIM_DA6 = _MXC_BUILD_NON_GPIO_PIN(0x34, 0x7AC),
-	MX51_PIN_EIM_DA7 = _MXC_BUILD_NON_GPIO_PIN(0x38, 0x7AC),
-	MX51_PIN_EIM_DA8 = _MXC_BUILD_NON_GPIO_PIN(0x3C, 0x7B0),
-	MX51_PIN_EIM_DA9 = _MXC_BUILD_NON_GPIO_PIN(0x40, 0x7B0),
-	MX51_PIN_EIM_DA10 = _MXC_BUILD_NON_GPIO_PIN(0x44, 0x7B0),
-	MX51_PIN_EIM_DA11 = _MXC_BUILD_NON_GPIO_PIN(0x48, 0x7B0),
-	MX51_PIN_EIM_DA12 = _MXC_BUILD_NON_GPIO_PIN(0x4C, 0x7BC),
-	MX51_PIN_EIM_DA13 = _MXC_BUILD_NON_GPIO_PIN(0x50, 0x7BC),
-	MX51_PIN_EIM_DA14 = _MXC_BUILD_NON_GPIO_PIN(0x54, 0x7BC),
-	MX51_PIN_EIM_DA15 = _MXC_BUILD_NON_GPIO_PIN(0x58, 0x7BC),
-	MX51_PIN_EIM_D16 = _MXC_BUILD_GPIO_PIN(1, 0, 1, 0x5C, 0x3F0),
-	MX51_PIN_EIM_D17 = _MXC_BUILD_GPIO_PIN(1, 1, 1, 0x60, 0x3F4),
-	MX51_PIN_EIM_D18 = _MXC_BUILD_GPIO_PIN(1, 2, 1, 0x64, 0x3F8),
-	MX51_PIN_EIM_D19 = _MXC_BUILD_GPIO_PIN(1, 3, 1, 0x68, 0x3FC),
-	MX51_PIN_EIM_D20 = _MXC_BUILD_GPIO_PIN(1, 4, 1, 0x6C, 0x400),
-	MX51_PIN_EIM_D21 = _MXC_BUILD_GPIO_PIN(1, 5, 1, 0x70, 0x404),
-	MX51_PIN_EIM_D22 = _MXC_BUILD_GPIO_PIN(1, 6, 1, 0x74, 0x408),
-	MX51_PIN_EIM_D23 = _MXC_BUILD_GPIO_PIN(1, 7, 1, 0x78, 0x40C),
-	MX51_PIN_EIM_D24 = _MXC_BUILD_GPIO_PIN(1, 8, 1, 0x7C, 0x410),
-	MX51_PIN_EIM_D25 = _MXC_BUILD_NON_GPIO_PIN(0x80, 0x414),
-	MX51_PIN_EIM_D26 = _MXC_BUILD_NON_GPIO_PIN(0x84, 0x418),
-	MX51_PIN_EIM_D27 = _MXC_BUILD_GPIO_PIN(1, 9, 1, 0x88, 0x41C),
-	MX51_PIN_EIM_D28 = _MXC_BUILD_NON_GPIO_PIN(0x8C, 0x420),
-	MX51_PIN_EIM_D29 = _MXC_BUILD_NON_GPIO_PIN(0x90, 0x424),
-	MX51_PIN_EIM_D30 = _MXC_BUILD_NON_GPIO_PIN(0x94, 0x428),
-	MX51_PIN_EIM_D31 = _MXC_BUILD_NON_GPIO_PIN(0x98, 0x42C),
-	MX51_PIN_EIM_A16 = _MXC_BUILD_GPIO_PIN(1, 10, 1, 0x9C, 0x430),
-	MX51_PIN_EIM_A17 = _MXC_BUILD_GPIO_PIN(1, 11, 1, 0xA0, 0x434),
-	MX51_PIN_EIM_A18 = _MXC_BUILD_GPIO_PIN(1, 12, 1, 0xA4, 0x438),
-	MX51_PIN_EIM_A19 = _MXC_BUILD_GPIO_PIN(1, 13, 1, 0xA8, 0x43C),
-	MX51_PIN_EIM_A20 = _MXC_BUILD_GPIO_PIN(1, 14, 1, 0xAC, 0x440),
-	MX51_PIN_EIM_A21 = _MXC_BUILD_GPIO_PIN(1, 15, 1, 0xB0, 0x444),
-	MX51_PIN_EIM_A22 = _MXC_BUILD_GPIO_PIN(1, 16, 1, 0xB4, 0x448),
-	MX51_PIN_EIM_A23 = _MXC_BUILD_GPIO_PIN(1, 17, 1, 0xB8, 0x44C),
-	MX51_PIN_EIM_A24 = _MXC_BUILD_GPIO_PIN(1, 18, 1, 0xBC, 0x450),
-	MX51_PIN_EIM_A25 = _MXC_BUILD_GPIO_PIN(1, 19, 1, 0xC0, 0x454),
-	MX51_PIN_EIM_A26 = _MXC_BUILD_GPIO_PIN(1, 20, 1, 0xC4, 0x458),
-	MX51_PIN_EIM_A27 = _MXC_BUILD_GPIO_PIN(1, 21, 1, 0xC8, 0x45C),
-	MX51_PIN_EIM_EB0 = _MXC_BUILD_NON_GPIO_PIN(0xCC, 0x460),
-	MX51_PIN_EIM_EB1 = _MXC_BUILD_NON_GPIO_PIN(0xD0, 0x464),
-	MX51_PIN_EIM_EB2 = _MXC_BUILD_GPIO_PIN(1, 22, 1, 0xD4, 0x468),
-	MX51_PIN_EIM_EB3 = _MXC_BUILD_GPIO_PIN(1, 23, 1, 0xD8, 0x46C),
-	MX51_PIN_EIM_OE = _MXC_BUILD_GPIO_PIN(1, 24, 1, 0xDC, 0x470),
-	MX51_PIN_EIM_CS0 = _MXC_BUILD_GPIO_PIN(1, 25, 1, 0xE0, 0x474),
-	MX51_PIN_EIM_CS1 = _MXC_BUILD_GPIO_PIN(1, 26, 1, 0xE4, 0x478),
-	MX51_PIN_EIM_CS2 = _MXC_BUILD_GPIO_PIN(1, 27, 1, 0xE8, 0x47C),
-	MX51_PIN_EIM_CS3 = _MXC_BUILD_GPIO_PIN(1, 28, 1, 0xEC, 0x480),
-	MX51_PIN_EIM_CS4 = _MXC_BUILD_GPIO_PIN(1, 29, 1, 0xF0, 0x484),
-	MX51_PIN_EIM_CS5 = _MXC_BUILD_GPIO_PIN(1, 30, 1, 0xF4, 0x488),
-	MX51_PIN_EIM_DTACK = _MXC_BUILD_GPIO_PIN(1, 31, 1, 0xF8, 0x48C),
-	MX51_PIN_EIM_LBA = _MXC_BUILD_GPIO_PIN(2, 1, 1, 0xFC, 0x494),
-	MX51_PIN_EIM_CRE = _MXC_BUILD_GPIO_PIN(2, 2, 1, 0x100, 0x4A0),
-	MX51_PIN_DRAM_CS1 = _MXC_BUILD_NON_GPIO_PIN(0x104, 0x4D0),
-	MX51_PIN_NANDF_WE_B = _MXC_BUILD_GPIO_PIN(2, 3, 3, 0x108, 0x4E4),
-	MX51_PIN_NANDF_RE_B = _MXC_BUILD_GPIO_PIN(2, 4, 3, 0x10C, 0x4E8),
-	MX51_PIN_NANDF_ALE = _MXC_BUILD_GPIO_PIN(2, 5, 3, 0x110, 0x4EC),
-	MX51_PIN_NANDF_CLE = _MXC_BUILD_GPIO_PIN(2, 6, 3, 0x114, 0x4F0),
-	MX51_PIN_NANDF_WP_B = _MXC_BUILD_GPIO_PIN(2, 7, 3, 0x118, 0x4F4),
-	MX51_PIN_NANDF_RB0 = _MXC_BUILD_GPIO_PIN(2, 8, 3, 0x11C, 0x4F8),
-	MX51_PIN_NANDF_RB1 = _MXC_BUILD_GPIO_PIN(2, 9, 3, 0x120, 0x4FC),
-	MX51_PIN_NANDF_RB2 = _MXC_BUILD_GPIO_PIN(2, 10, 3, 0x124, 0x500),
-	MX51_PIN_NANDF_RB3 = _MXC_BUILD_GPIO_PIN(2, 11, 3, 0x128, 0x504),
-	MX51_PIN_GPIO_NAND = _MXC_BUILD_GPIO_PIN(2, 12, 3, 0x12C, 0x514),
-	MX51_PIN_NANDF_RB4 = MX51_PIN_GPIO_NAND,
-	MX51_PIN_NANDF_RB5 = _MXC_BUILD_GPIO_PIN(2, 13, 3, 0x130, 0x5D8),
-	MX51_PIN_NANDF_RB6 = _MXC_BUILD_GPIO_PIN(2, 14, 3, 0x134, 0x5DC),
-	MX51_PIN_NANDF_RB7 = _MXC_BUILD_GPIO_PIN(2, 15, 3, 0x138, 0x5E0),
-	MX51_PIN_NANDF_CS0 = _MXC_BUILD_GPIO_PIN(2, 16, 3, 0x130, 0x518),
-	MX51_PIN_NANDF_CS1 = _MXC_BUILD_GPIO_PIN(2, 17, 3, 0x134, 0x51C),
-	MX51_PIN_NANDF_CS2 = _MXC_BUILD_GPIO_PIN(2, 18, 3, 0x138, 0x520),
-	MX51_PIN_NANDF_CS3 = _MXC_BUILD_GPIO_PIN(2, 19, 3, 0x13C, 0x524),
-	MX51_PIN_NANDF_CS4 = _MXC_BUILD_GPIO_PIN(2, 20, 3, 0x140, 0x528),
-	MX51_PIN_NANDF_CS5 = _MXC_BUILD_GPIO_PIN(2, 21, 3, 0x144, 0x52C),
-	MX51_PIN_NANDF_CS6 = _MXC_BUILD_GPIO_PIN(2, 22, 3, 0x148, 0x530),
-	MX51_PIN_NANDF_CS7 = _MXC_BUILD_GPIO_PIN(2, 23, 3, 0x14C, 0x534),
-	MX51_PIN_NANDF_RDY_INT = _MXC_BUILD_GPIO_PIN(2, 24, 3, 0x150, 0x538),
-	MX51_PIN_NANDF_D15 = _MXC_BUILD_GPIO_PIN(2, 25, 3, 0x154, 0x53C),
-	MX51_PIN_NANDF_D14 = _MXC_BUILD_GPIO_PIN(2, 26, 3, 0x158, 0x540),
-	MX51_PIN_NANDF_D13 = _MXC_BUILD_GPIO_PIN(2, 27, 3, 0x15C, 0x544),
-	MX51_PIN_NANDF_D12 = _MXC_BUILD_GPIO_PIN(2, 28, 3, 0x160, 0x548),
-	MX51_PIN_NANDF_D11 = _MXC_BUILD_GPIO_PIN(2, 29, 3, 0x164, 0x54C),
-	MX51_PIN_NANDF_D10 = _MXC_BUILD_GPIO_PIN(2, 30, 3, 0x168, 0x550),
-	MX51_PIN_NANDF_D9 = _MXC_BUILD_GPIO_PIN(2, 31, 3, 0x16C, 0x554),
-	MX51_PIN_NANDF_D8 = _MXC_BUILD_GPIO_PIN(3, 0, 3, 0x170, 0x558),
-	MX51_PIN_NANDF_D7 = _MXC_BUILD_GPIO_PIN(3, 1, 3, 0x174, 0x55C),
-	MX51_PIN_NANDF_D6 = _MXC_BUILD_GPIO_PIN(3, 2, 3, 0x178, 0x560),
-	MX51_PIN_NANDF_D5 = _MXC_BUILD_GPIO_PIN(3, 3, 3, 0x17C, 0x564),
-	MX51_PIN_NANDF_D4 = _MXC_BUILD_GPIO_PIN(3, 4, 3, 0x180, 0x568),
-	MX51_PIN_NANDF_D3 = _MXC_BUILD_GPIO_PIN(3, 5, 3, 0x184, 0x56C),
-	MX51_PIN_NANDF_D2 = _MXC_BUILD_GPIO_PIN(3, 6, 3, 0x188, 0x570),
-	MX51_PIN_NANDF_D1 = _MXC_BUILD_GPIO_PIN(3, 7, 3, 0x18C, 0x574),
-	MX51_PIN_NANDF_D0 = _MXC_BUILD_GPIO_PIN(3, 8, 3, 0x190, 0x578),
-	MX51_PIN_CSI1_D8 = _MXC_BUILD_GPIO_PIN(2, 12, 3, 0x194, 0x57C),
-	MX51_PIN_CSI1_D9 = _MXC_BUILD_GPIO_PIN(2, 13, 3, 0x198, 0x580),
-	MX51_PIN_CSI1_D10 = _MXC_BUILD_NON_GPIO_PIN(0x19C, 0x584),
-	MX51_PIN_CSI1_D11 = _MXC_BUILD_NON_GPIO_PIN(0x1A0, 0x588),
-	MX51_PIN_CSI1_D12 = _MXC_BUILD_NON_GPIO_PIN(0x1A4, 0x58C),
-	MX51_PIN_CSI1_D13 = _MXC_BUILD_NON_GPIO_PIN(0x1A8, 0x590),
-	MX51_PIN_CSI1_D14 = _MXC_BUILD_NON_GPIO_PIN(0x1AC, 0x594),
-	MX51_PIN_CSI1_D15 = _MXC_BUILD_NON_GPIO_PIN(0x1B0, 0x598),
-	MX51_PIN_CSI1_D16 = _MXC_BUILD_NON_GPIO_PIN(0x1B4, 0x59C),
-	MX51_PIN_CSI1_D17 = _MXC_BUILD_NON_GPIO_PIN(0x1B8, 0x5A0),
-	MX51_PIN_CSI1_D18 = _MXC_BUILD_NON_GPIO_PIN(0x1BC, 0x5A4),
-	MX51_PIN_CSI1_D19 = _MXC_BUILD_NON_GPIO_PIN(0x1C0, 0x5A8),
-	MX51_PIN_CSI1_VSYNC = _MXC_BUILD_NON_GPIO_PIN(0x1C4, 0x5AC),
-	MX51_PIN_CSI1_HSYNC = _MXC_BUILD_NON_GPIO_PIN(0x1C8, 0x5B0),
-	MX51_PIN_CSI1_PIXCLK = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x5B4),
-	MX51_PIN_CSI1_MCLK = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x5B8),
-	MX51_PIN_CSI1_PKE0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x860),
-	MX51_PIN_CSI2_D12 = _MXC_BUILD_GPIO_PIN(3, 9, 3, 0x1CC, 0x5BC),
-	MX51_PIN_CSI2_D13 = _MXC_BUILD_GPIO_PIN(3, 10, 3, 0x1D0, 0x5C0),
-	MX51_PIN_CSI2_D14 = _MXC_BUILD_GPIO_PIN(3, 11, 3, 0x1D4, 0x5C4),
-	MX51_PIN_CSI2_D15 = _MXC_BUILD_GPIO_PIN(3, 12, 3, 0x1D8, 0x5C8),
-	MX51_PIN_CSI2_D16 = _MXC_BUILD_GPIO_PIN(3, 11, 3, 0x1DC, 0x5CC),
-	MX51_PIN_CSI2_D17 = _MXC_BUILD_GPIO_PIN(3, 12, 3, 0x1E0, 0x5D0),
-	MX51_PIN_CSI2_D18 = _MXC_BUILD_GPIO_PIN(3, 11, 3, 0x1E4, 0x5D4),
-	MX51_PIN_CSI2_D19 = _MXC_BUILD_GPIO_PIN(3, 12, 3, 0x1E8, 0x5D8),
-	MX51_PIN_CSI2_VSYNC = _MXC_BUILD_GPIO_PIN(3, 13, 3, 0x1EC, 0x5DC),
-	MX51_PIN_CSI2_HSYNC = _MXC_BUILD_GPIO_PIN(3, 14, 3, 0x1F0, 0x5E0),
-	MX51_PIN_CSI2_PIXCLK = _MXC_BUILD_GPIO_PIN(3, 15, 3, 0x1F4, 0x5E4),
-	MX51_PIN_CSI2_PKE0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x81C),
-	MX51_PIN_I2C1_CLK = _MXC_BUILD_GPIO_PIN(3, 16, 3, 0x1F8, 0x5E8),
-	MX51_PIN_I2C1_DAT = _MXC_BUILD_GPIO_PIN(3, 17, 3, 0x1FC, 0x5EC),
-	MX51_PIN_AUD3_BB_TXD = _MXC_BUILD_GPIO_PIN(3, 18, 3, 0x200, 0x5F0),
-	MX51_PIN_AUD3_BB_RXD = _MXC_BUILD_GPIO_PIN(3, 19, 3, 0x204, 0x5F4),
-	MX51_PIN_AUD3_BB_CK = _MXC_BUILD_GPIO_PIN(3, 20, 3, 0x208, 0x5F8),
-	MX51_PIN_AUD3_BB_FS = _MXC_BUILD_GPIO_PIN(3, 21, 3, 0x20C, 0x5FC),
-	MX51_PIN_CSPI1_MOSI = _MXC_BUILD_GPIO_PIN(3, 22, 3, 0x210, 0x600),
-	MX51_PIN_CSPI1_MISO = _MXC_BUILD_GPIO_PIN(3, 23, 3, 0x214, 0x604),
-	MX51_PIN_CSPI1_SS0 = _MXC_BUILD_GPIO_PIN(3, 24, 3, 0x218, 0x608),
-	MX51_PIN_CSPI1_SS1 = _MXC_BUILD_GPIO_PIN(3, 25, 3, 0x21C, 0x60C),
-	MX51_PIN_CSPI1_RDY = _MXC_BUILD_GPIO_PIN(3, 26, 3, 0x220, 0x610),
-	MX51_PIN_CSPI1_SCLK = _MXC_BUILD_GPIO_PIN(3, 27, 3, 0x224, 0x614),
-	MX51_PIN_UART1_RXD = _MXC_BUILD_GPIO_PIN(3, 28, 3, 0x228, 0x618),
-	MX51_PIN_UART1_TXD = _MXC_BUILD_GPIO_PIN(3, 29, 3, 0x22C, 0x61C),
-	MX51_PIN_UART1_RTS = _MXC_BUILD_GPIO_PIN(3, 30, 3, 0x230, 0x620),
-	MX51_PIN_UART1_CTS = _MXC_BUILD_GPIO_PIN(3, 31, 3, 0x234, 0x624),
-	MX51_PIN_UART2_RXD = _MXC_BUILD_GPIO_PIN(0, 20, 3, 0x238, 0x628),
-	MX51_PIN_UART2_TXD = _MXC_BUILD_GPIO_PIN(0, 21, 3, 0x23C, 0x62C),
-	MX51_PIN_UART3_RXD = _MXC_BUILD_GPIO_PIN(0, 22, 3, 0x240, 0x630),
-	MX51_PIN_UART3_TXD = _MXC_BUILD_GPIO_PIN(0, 23, 3, 0x244, 0x634),
-	MX51_PIN_OWIRE_LINE = _MXC_BUILD_GPIO_PIN(0, 24, 3, 0x248, 0x638),
-	MX51_PIN_KEY_ROW0 = _MXC_BUILD_NON_GPIO_PIN(0x24C, 0x63C),
-	MX51_PIN_KEY_ROW1 = _MXC_BUILD_NON_GPIO_PIN(0x250, 0x640),
-	MX51_PIN_KEY_ROW2 = _MXC_BUILD_NON_GPIO_PIN(0x254, 0x644),
-	MX51_PIN_KEY_ROW3 = _MXC_BUILD_NON_GPIO_PIN(0x258, 0x648),
-	MX51_PIN_KEY_COL0 = _MXC_BUILD_NON_GPIO_PIN(0x25C, 0x64C),
-	MX51_PIN_KEY_COL1 = _MXC_BUILD_NON_GPIO_PIN(0x260, 0x650),
-	MX51_PIN_KEY_COL2 = _MXC_BUILD_NON_GPIO_PIN(0x264, 0x654),
-	MX51_PIN_KEY_COL3 = _MXC_BUILD_NON_GPIO_PIN(0x268, 0x658),
-	MX51_PIN_KEY_COL4 = _MXC_BUILD_NON_GPIO_PIN(0x26C, 0x65C),
-	MX51_PIN_KEY_COL5 = _MXC_BUILD_NON_GPIO_PIN(0x270, 0x660),
-	MX51_PIN_USBH1_CLK = _MXC_BUILD_GPIO_PIN(0, 25, 2, 0x278, 0x678),
-	MX51_PIN_USBH1_DIR = _MXC_BUILD_GPIO_PIN(0, 26, 2, 0x27C, 0x67C),
-	MX51_PIN_USBH1_STP = _MXC_BUILD_GPIO_PIN(0, 27, 2, 0x280, 0x680),
-	MX51_PIN_USBH1_NXT = _MXC_BUILD_GPIO_PIN(0, 28, 2, 0x284, 0x684),
-	MX51_PIN_USBH1_DATA0 = _MXC_BUILD_GPIO_PIN(0, 11, 2, 0x288, 0x688),
-	MX51_PIN_USBH1_DATA1 = _MXC_BUILD_GPIO_PIN(0, 12, 2, 0x28C, 0x68C),
-	MX51_PIN_USBH1_DATA2 = _MXC_BUILD_GPIO_PIN(0, 13, 2, 0x290, 0x690),
-	MX51_PIN_USBH1_DATA3 = _MXC_BUILD_GPIO_PIN(0, 14, 2, 0x294, 0x694),
-	MX51_PIN_USBH1_DATA4 = _MXC_BUILD_GPIO_PIN(0, 15, 2, 0x298, 0x698),
-	MX51_PIN_USBH1_DATA5 = _MXC_BUILD_GPIO_PIN(0, 16, 2, 0x29C, 0x69C),
-	MX51_PIN_USBH1_DATA6 = _MXC_BUILD_GPIO_PIN(0, 17, 2, 0x2A0, 0x6A0),
-	MX51_PIN_USBH1_DATA7 = _MXC_BUILD_GPIO_PIN(0, 18, 2, 0x2A4, 0x6A4),
-	MX51_PIN_DI1_PIN11 = _MXC_BUILD_GPIO_PIN(2, 0, 4, 0x2A8, 0x6A8),
-	MX51_PIN_DI1_PIN12 = _MXC_BUILD_GPIO_PIN(2, 1, 4, 0x2AC, 0x6AC),
-	MX51_PIN_DI1_PIN13 = _MXC_BUILD_GPIO_PIN(2, 2, 4, 0x2B0, 0x6B0),
-	MX51_PIN_DI1_D0_CS = _MXC_BUILD_GPIO_PIN(2, 3, 4, 0x2B4, 0x6B4),
-	MX51_PIN_DI1_D1_CS = _MXC_BUILD_GPIO_PIN(2, 4, 4, 0x2B8, 0x6B8),
-	MX51_PIN_DISPB2_SER_DIN = _MXC_BUILD_GPIO_PIN(2, 5, 4, 0x2BC, 0x6BC),
-	MX51_PIN_DISPB2_SER_DIO = _MXC_BUILD_GPIO_PIN(2, 6, 4, 0x2C0, 0x6C0),
-	MX51_PIN_DISPB2_SER_CLK = _MXC_BUILD_GPIO_PIN(2, 7, 4, 0x2C4, 0x6C4),
-	MX51_PIN_DISPB2_SER_RS = _MXC_BUILD_GPIO_PIN(2, 8, 4, 0x2C8, 0x6C8),
-	MX51_PIN_DISP1_DAT0 = _MXC_BUILD_NON_GPIO_PIN(0x2CC, 0x6CC),
-	MX51_PIN_DISP1_DAT1 = _MXC_BUILD_NON_GPIO_PIN(0x2D0, 0x6D0),
-	MX51_PIN_DISP1_DAT2 = _MXC_BUILD_NON_GPIO_PIN(0x2D4, 0x6D4),
-	MX51_PIN_DISP1_DAT3 = _MXC_BUILD_NON_GPIO_PIN(0x2D8, 0x6D8),
-	MX51_PIN_DISP1_DAT4 = _MXC_BUILD_NON_GPIO_PIN(0x2DC, 0x6DC),
-	MX51_PIN_DISP1_DAT5 = _MXC_BUILD_NON_GPIO_PIN(0x2E0, 0x6E0),
-	MX51_PIN_DISP1_DAT6 = _MXC_BUILD_NON_GPIO_PIN(0x2E4, 0x6E4),
-	MX51_PIN_DISP1_DAT7 = _MXC_BUILD_NON_GPIO_PIN(0x2E8, 0x6E8),
-	MX51_PIN_DISP1_DAT8 = _MXC_BUILD_NON_GPIO_PIN(0x2EC, 0x6EC),
-	MX51_PIN_DISP1_DAT9 = _MXC_BUILD_NON_GPIO_PIN(0x2F0, 0x6F0),
-	MX51_PIN_DISP1_DAT10 = _MXC_BUILD_NON_GPIO_PIN(0x2F4, 0x6F4),
-	MX51_PIN_DISP1_DAT11 = _MXC_BUILD_NON_GPIO_PIN(0x2F8, 0x6F8),
-	MX51_PIN_DISP1_DAT12 = _MXC_BUILD_NON_GPIO_PIN(0x2FC, 0x6FC),
-	MX51_PIN_DISP1_DAT13 = _MXC_BUILD_NON_GPIO_PIN(0x300, 0x700),
-	MX51_PIN_DISP1_DAT14 = _MXC_BUILD_NON_GPIO_PIN(0x304, 0x704),
-	MX51_PIN_DISP1_DAT15 = _MXC_BUILD_NON_GPIO_PIN(0x308, 0x708),
-	MX51_PIN_DISP1_DAT16 = _MXC_BUILD_NON_GPIO_PIN(0x30C, 0x70C),
-	MX51_PIN_DISP1_DAT17 = _MXC_BUILD_NON_GPIO_PIN(0x310, 0x710),
-	MX51_PIN_DISP1_DAT18 = _MXC_BUILD_NON_GPIO_PIN(0x314, 0x714),
-	MX51_PIN_DISP1_DAT19 = _MXC_BUILD_NON_GPIO_PIN(0x318, 0x718),
-	MX51_PIN_DISP1_DAT20 = _MXC_BUILD_NON_GPIO_PIN(0x31C, 0x71C),
-	MX51_PIN_DISP1_DAT21 = _MXC_BUILD_NON_GPIO_PIN(0x320, 0x720),
-	MX51_PIN_DISP1_DAT22 = _MXC_BUILD_NON_GPIO_PIN(0x324, 0x724),
-	MX51_PIN_DISP1_DAT23 = _MXC_BUILD_NON_GPIO_PIN(0x328, 0x728),
-	MX51_PIN_DI1_PIN3 = _MXC_BUILD_NON_GPIO_PIN(0x32C, 0x72C),
-	MX51_PIN_DI1_PIN2 = _MXC_BUILD_NON_GPIO_PIN(0x330, 0x734),
-	MX51_PIN_DI_GP1 = _MXC_BUILD_NON_GPIO_PIN(0x334, 0x73C),
-	MX51_PIN_DI_GP2 = _MXC_BUILD_NON_GPIO_PIN(0x338, 0x740),
-	MX51_PIN_DI_GP3 = _MXC_BUILD_NON_GPIO_PIN(0x33C, 0x744),
-	MX51_PIN_DI2_PIN4 = _MXC_BUILD_NON_GPIO_PIN(0x340, 0x748),
-	MX51_PIN_DI2_PIN2 = _MXC_BUILD_NON_GPIO_PIN(0x344, 0x74C),
-	MX51_PIN_DI2_PIN3 = _MXC_BUILD_NON_GPIO_PIN(0x348, 0x750),
-	MX51_PIN_DI2_DISP_CLK = _MXC_BUILD_NON_GPIO_PIN(0x34C, 0x754),
-	MX51_PIN_DI_GP4 = _MXC_BUILD_NON_GPIO_PIN(0x350, 0x758),
-	MX51_PIN_DISP2_DAT0 = _MXC_BUILD_NON_GPIO_PIN(0x354, 0x75C),
-	MX51_PIN_DISP2_DAT1 = _MXC_BUILD_NON_GPIO_PIN(0x358, 0x760),
-	MX51_PIN_DISP2_DAT2 = _MXC_BUILD_NON_GPIO_PIN(0x35C, 0x764),
-	MX51_PIN_DISP2_DAT3 = _MXC_BUILD_NON_GPIO_PIN(0x360, 0x768),
-	MX51_PIN_DISP2_DAT4 = _MXC_BUILD_NON_GPIO_PIN(0x364, 0x76C),
-	MX51_PIN_DISP2_DAT5 = _MXC_BUILD_NON_GPIO_PIN(0x368, 0x770),
-	MX51_PIN_DISP2_DAT6 = _MXC_BUILD_GPIO_PIN(0, 19, 5, 0x36C, 0x774),
-	MX51_PIN_DISP2_DAT7 = _MXC_BUILD_GPIO_PIN(0, 29, 5, 0x370, 0x778),
-	MX51_PIN_DISP2_DAT8 = _MXC_BUILD_GPIO_PIN(0, 30, 5, 0x374, 0x77C),
-	MX51_PIN_DISP2_DAT9 = _MXC_BUILD_GPIO_PIN(0, 31, 5, 0x378, 0x780),
-	MX51_PIN_DISP2_DAT10 = _MXC_BUILD_NON_GPIO_PIN(0x37C, 0x784),
-	MX51_PIN_DISP2_DAT11 = _MXC_BUILD_NON_GPIO_PIN(0x380, 0x788),
-	MX51_PIN_DISP2_DAT12 = _MXC_BUILD_NON_GPIO_PIN(0x384, 0x78C),
-	MX51_PIN_DISP2_DAT13 = _MXC_BUILD_NON_GPIO_PIN(0x388, 0x790),
-	MX51_PIN_DISP2_DAT14 = _MXC_BUILD_NON_GPIO_PIN(0x38C, 0x794),
-	MX51_PIN_DISP2_DAT15 = _MXC_BUILD_NON_GPIO_PIN(0x390, 0x798),
-	MX51_PIN_SD1_CMD = _MXC_BUILD_NON_GPIO_PIN(0x394, 0x79C),
-	MX51_PIN_SD1_CLK = _MXC_BUILD_NON_GPIO_PIN(0x398, 0x7A0),
-	MX51_PIN_SD1_DATA0 = _MXC_BUILD_NON_GPIO_PIN(0x39C, 0x7A4),
-	MX51_PIN_SD1_DATA1 = _MXC_BUILD_NON_GPIO_PIN(0x3A0, 0x7A8),
-	MX51_PIN_SD1_DATA2 = _MXC_BUILD_NON_GPIO_PIN(0x3A4, 0x7AC),
-	MX51_PIN_SD1_DATA3 = _MXC_BUILD_NON_GPIO_PIN(0x3A8, 0x7B0),
-	MX51_PIN_GPIO1_0 = _MXC_BUILD_GPIO_PIN(0, 0, 1, 0x3AC, 0x7B4),
-	MX51_PIN_GPIO1_1 = _MXC_BUILD_GPIO_PIN(0, 1, 1, 0x3B0, 0x7B8),
-	MX51_PIN_SD2_CMD = _MXC_BUILD_NON_GPIO_PIN(0x3B4, 0x7BC),
-	MX51_PIN_SD2_CLK = _MXC_BUILD_NON_GPIO_PIN(0x3B8, 0x7C0),
-	MX51_PIN_SD2_DATA0 = _MXC_BUILD_NON_GPIO_PIN(0x3BC, 0x7C4),
-	MX51_PIN_SD2_DATA1 = _MXC_BUILD_NON_GPIO_PIN(0x3C0, 0x7C8),
-	MX51_PIN_SD2_DATA2 = _MXC_BUILD_NON_GPIO_PIN(0x3C4, 0x7CC),
-	MX51_PIN_SD2_DATA3 = _MXC_BUILD_NON_GPIO_PIN(0x3C8, 0x7D0),
-	MX51_PIN_GPIO1_2 = _MXC_BUILD_GPIO_PIN(0, 2, 0, 0x3CC, 0x7D4),
-	MX51_PIN_GPIO1_3 = _MXC_BUILD_GPIO_PIN(0, 3, 0, 0x3D0, 0x7D8),
-	MX51_PIN_PMIC_INT_REQ = _MXC_BUILD_NON_GPIO_PIN(0x3D4, 0x7FC),
-	MX51_PIN_GPIO1_4 = _MXC_BUILD_GPIO_PIN(0, 4, 0, 0x3D8, 0x804),
-	MX51_PIN_GPIO1_5 = _MXC_BUILD_GPIO_PIN(0, 5, 0, 0x3DC, 0x808),
-	MX51_PIN_GPIO1_6 = _MXC_BUILD_GPIO_PIN(0, 6, 0, 0x3E0, 0x80C),
-	MX51_PIN_GPIO1_7 = _MXC_BUILD_GPIO_PIN(0, 7, 0, 0x3E4, 0x810),
-	MX51_PIN_GPIO1_8 = _MXC_BUILD_GPIO_PIN(0, 8, 0, 0x3E8, 0x814),
-	MX51_PIN_GPIO1_9 = _MXC_BUILD_GPIO_PIN(0, 9, 0, 0x3EC, 0x818),
-
-	/* The following are PADS used for drive strength */
-
-	MX51_PIN_CTL_GRP_DDRPKS = _MXC_BUILD_NON_GPIO_PIN(0, 0x820),
-	MX51_PIN_CTL_GRP_PKEDDR = _MXC_BUILD_NON_GPIO_PIN(0, 0x838),
-	MX51_PIN_CTL_GRP_PKEADDR = _MXC_BUILD_NON_GPIO_PIN(0, 0x890),
-	MX51_PIN_CTL_GRP_DDRAPKS = _MXC_BUILD_NON_GPIO_PIN(0, 0x87C),
-	MX51_PIN_CTL_GRP_DDRAPUS = _MXC_BUILD_NON_GPIO_PIN(0, 0x84C),
-	MX51_PIN_CTL_GRP_DDRPUS = _MXC_BUILD_NON_GPIO_PIN(0, 0x884),
-	MX51_PIN_CTL_GRP_HYSDDR0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x85C),
-	MX51_PIN_CTL_GRP_HYSDDR1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x864),
-	MX51_PIN_CTL_GRP_HYSDDR2 = _MXC_BUILD_NON_GPIO_PIN(0, 0x86C),
-	MX51_PIN_CTL_GRP_HYSDDR3 = _MXC_BUILD_NON_GPIO_PIN(0, 0x874),
-	MX51_PIN_CTL_GRP_DDR_SR_B0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x878),
-	MX51_PIN_CTL_GRP_DDR_SR_B1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x880),
-	MX51_PIN_CTL_GRP_DDR_SR_B2 = _MXC_BUILD_NON_GPIO_PIN(0, 0x88C),
-	MX51_PIN_CTL_GRP_DDR_SR_B4 = _MXC_BUILD_NON_GPIO_PIN(0, 0x89C),
-	MX51_PIN_CTL_GRP_DRAM_B0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x8A4),
-	MX51_PIN_CTL_GRP_DRAM_B1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x8AC),
-	MX51_PIN_CTL_GRP_DRAM_B2 = _MXC_BUILD_NON_GPIO_PIN(0, 0x8B8),
-	MX51_PIN_CTL_GRP_DRAM_B4 = _MXC_BUILD_NON_GPIO_PIN(0, 0x82C),
-	MX51_PIN_CTL_GRP_INMODE1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x8A0),
-	MX51_PIN_CTL_GRP_DDR_SR_A0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x8B0),
-	MX51_PIN_CTL_GRP_EMI_DS5 = _MXC_BUILD_NON_GPIO_PIN(0, 0x8B4),
-	MX51_PIN_CTL_GRP_DDR_SR_A1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x8BC),
-	MX51_PIN_CTL_GRP_DDR_A0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x83C),
-	MX51_PIN_CTL_GRP_DDR_A1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x848),
-	MX51_PIN_CTL_GRP_DISP_PKE0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x868),
-	MX51_PIN_CTL_DRAM_RAS = _MXC_BUILD_NON_GPIO_PIN(0, 0x4A4),
-	MX51_PIN_CTL_DRAM_CAS = _MXC_BUILD_NON_GPIO_PIN(0, 0x4A8),
-	MX51_PIN_CTL_DRAM_SDWE = _MXC_BUILD_NON_GPIO_PIN(0, 0x4Ac),
-	MX51_PIN_CTL_DRAM_SDCKE0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4B0),
-	MX51_PIN_CTL_DRAM_SDCKE1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4B4),
-	MX51_PIN_CTL_DRAM_SDCLK = _MXC_BUILD_NON_GPIO_PIN(0, 0x4B8),
-	MX51_PIN_CTL_DRAM_SDQS0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4BC),
-	MX51_PIN_CTL_DRAM_SDQS1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4C0),
-	MX51_PIN_CTL_DRAM_SDQS2 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4C4),
-	MX51_PIN_CTL_DRAM_SDQS3 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4C8),
-	MX51_PIN_CTL_DRAM_CS0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4CC),
-	MX51_PIN_CTL_DRAM_CS1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4D0),
-	MX51_PIN_CTL_DRAM_DQM0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4D4),
-	MX51_PIN_CTL_DRAM_DQM1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4D8),
-	MX51_PIN_CTL_DRAM_DQM2 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4DC),
-	MX51_PIN_CTL_DRAM_DQM3 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4E0),
-};
-
-enum {
-	MX53_PIN_GPIO_19  = _MXC_BUILD_GPIO_PIN(3, 5, 1, 0x20, 0x348),
-	MX53_PIN_KEY_COL0 = _MXC_BUILD_GPIO_PIN(3, 6, 1, 0x24, 0x34C),
-	MX53_PIN_KEY_ROW0 = _MXC_BUILD_GPIO_PIN(3, 7, 1, 0x28, 0x350),
-	MX53_PIN_KEY_COL1 = _MXC_BUILD_GPIO_PIN(3, 8, 1, 0x2C, 0x354),
-	MX53_PIN_KEY_ROW1 = _MXC_BUILD_GPIO_PIN(3, 9, 1, 0x30, 0x358),
-	MX53_PIN_KEY_COL2 = _MXC_BUILD_GPIO_PIN(3, 10, 1, 0x34, 0x35C),
-	MX53_PIN_KEY_ROW2 = _MXC_BUILD_GPIO_PIN(3, 11, 1, 0x38, 0x360),
-	MX53_PIN_KEY_COL3 = _MXC_BUILD_GPIO_PIN(3, 12, 1, 0x3C, 0x364),
-	MX53_PIN_KEY_ROW3 = _MXC_BUILD_GPIO_PIN(3, 13, 1, 0x40, 0x368),
-	MX53_PIN_KEY_COL4 = _MXC_BUILD_GPIO_PIN(3, 14, 1, 0x44, 0x36C),
-	MX53_PIN_KEY_ROW4 = _MXC_BUILD_GPIO_PIN(3, 15, 1, 0x48, 0x370),
-	MX53_PIN_NVCC_KEYPAD = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x374),
-	MX53_PIN_DI0_DISP_CLK = _MXC_BUILD_GPIO_PIN(3, 16, 1, 0x4C, 0x378),
-	MX53_PIN_DI0_PIN15 = _MXC_BUILD_GPIO_PIN(3, 17, 1, 0x50, 0x37C),
-	MX53_PIN_DI0_PIN2 = _MXC_BUILD_GPIO_PIN(3, 18, 1, 0x54, 0x380),
-	MX53_PIN_DI0_PIN3 = _MXC_BUILD_GPIO_PIN(3, 19, 1, 0x58, 0x384),
-	MX53_PIN_DI0_PIN4 = _MXC_BUILD_GPIO_PIN(3, 20, 1, 0x5C, 0x388),
-	MX53_PIN_DISP0_DAT0 = _MXC_BUILD_GPIO_PIN(3, 21, 1, 0x60, 0x38C),
-	MX53_PIN_DISP0_DAT1 = _MXC_BUILD_GPIO_PIN(3, 22, 1, 0x64, 0x390),
-	MX53_PIN_DISP0_DAT2 = _MXC_BUILD_GPIO_PIN(3, 23, 1, 0x68, 0x394),
-	MX53_PIN_DISP0_DAT3 = _MXC_BUILD_GPIO_PIN(3, 24, 1, 0x6C, 0x398),
-	MX53_PIN_DISP0_DAT4 = _MXC_BUILD_GPIO_PIN(3, 25, 1, 0x70, 0x39C),
-	MX53_PIN_DISP0_DAT5 = _MXC_BUILD_GPIO_PIN(3, 26, 1, 0x74, 0x3A0),
-	MX53_PIN_DISP0_DAT6 = _MXC_BUILD_GPIO_PIN(3, 27, 1, 0x78, 0x3A4),
-	MX53_PIN_DISP0_DAT7 = _MXC_BUILD_GPIO_PIN(3, 28, 1, 0x7C, 0x3A8),
-	MX53_PIN_DISP0_DAT8 = _MXC_BUILD_GPIO_PIN(3, 29, 1, 0x80, 0x3AC),
-	MX53_PIN_DISP0_DAT9 = _MXC_BUILD_GPIO_PIN(3, 30, 1, 0x84, 0x3B0),
-	MX53_PIN_DISP0_DAT10 = _MXC_BUILD_GPIO_PIN(3, 31, 1, 0x88, 0x3B4),
-	MX53_PIN_DISP0_DAT11 = _MXC_BUILD_GPIO_PIN(4, 5, 1, 0x8C, 0x3B8),
-	MX53_PIN_DISP0_DAT12 = _MXC_BUILD_GPIO_PIN(4, 6, 1, 0x90, 0x3BC),
-	MX53_PIN_DISP0_DAT13 = _MXC_BUILD_GPIO_PIN(4, 7, 1, 0x94, 0x3C0),
-	MX53_PIN_DISP0_DAT14 = _MXC_BUILD_GPIO_PIN(4, 8, 1, 0x98, 0x3C4),
-	MX53_PIN_DISP0_DAT15 = _MXC_BUILD_GPIO_PIN(4, 9, 1, 0x9C, 0x3C8),
-	MX53_PIN_DISP0_DAT16 = _MXC_BUILD_GPIO_PIN(4, 10, 1, 0xA0, 0x3CC),
-	MX53_PIN_DISP0_DAT17 = _MXC_BUILD_GPIO_PIN(4, 11, 1, 0xA4, 0x3D0),
-	MX53_PIN_DISP0_DAT18 = _MXC_BUILD_GPIO_PIN(4, 12, 1, 0xA8, 0x3D4),
-	MX53_PIN_DISP0_DAT19 = _MXC_BUILD_GPIO_PIN(4, 13, 1, 0xAC, 0x3D8),
-	MX53_PIN_DISP0_DAT20 = _MXC_BUILD_GPIO_PIN(4, 14, 1, 0xB0, 0x3DC),
-	MX53_PIN_DISP0_DAT21 = _MXC_BUILD_GPIO_PIN(4, 15, 1, 0xB4, 0x3E0),
-	MX53_PIN_DISP0_DAT22 = _MXC_BUILD_GPIO_PIN(4, 16, 1, 0xB8, 0x3E4),
-	MX53_PIN_DISP0_DAT23 = _MXC_BUILD_GPIO_PIN(4, 17, 1, 0xBC, 0x3E8),
-	MX53_PIN_CSI0_PIXCLK = _MXC_BUILD_GPIO_PIN(4, 18, 1, 0xC0, 0x3EC),
-	MX53_PIN_CSI0_MCLK = _MXC_BUILD_GPIO_PIN(4, 19, 1, 0xC4, 0x3F0),
-	MX53_PIN_CSI0_DATA_EN = _MXC_BUILD_GPIO_PIN(4, 20, 1, 0xC8, 0x3F4),
-	MX53_PIN_CSI0_VSYNC = _MXC_BUILD_GPIO_PIN(4, 21, 1, 0xCC, 0x3F8),
-	MX53_PIN_CSI0_D4 = _MXC_BUILD_GPIO_PIN(4, 22, 1, 0xD0, 0x3FC),
-	MX53_PIN_CSI0_D5 = _MXC_BUILD_GPIO_PIN(4, 23, 1, 0xD4, 0x400),
-	MX53_PIN_CSI0_D6 = _MXC_BUILD_GPIO_PIN(4, 24, 1, 0xD8, 0x404),
-	MX53_PIN_CSI0_D7 = _MXC_BUILD_GPIO_PIN(4, 25, 1, 0xDC, 0x408),
-	MX53_PIN_CSI0_D8 = _MXC_BUILD_GPIO_PIN(4, 26, 1, 0xE0, 0x40C),
-	MX53_PIN_CSI0_D9 = _MXC_BUILD_GPIO_PIN(4, 27, 1, 0xE4, 0x410),
-	MX53_PIN_CSI0_D10 = _MXC_BUILD_GPIO_PIN(4, 28, 1, 0xE8, 0x414),
-	MX53_PIN_CSI0_D11 = _MXC_BUILD_GPIO_PIN(4, 29, 1, 0xEC, 0x418),
-	MX53_PIN_CSI0_D12 = _MXC_BUILD_GPIO_PIN(4, 30, 1, 0xF0, 0x41C),
-	MX53_PIN_CSI0_D13 = _MXC_BUILD_GPIO_PIN(4, 31, 1, 0xF4, 0x420),
-	MX53_PIN_CSI0_D14 = _MXC_BUILD_GPIO_PIN(5, 0, 1, 0xF8, 0x424),
-	MX53_PIN_CSI0_D15 = _MXC_BUILD_GPIO_PIN(5, 1, 1, 0xFC, 0x428),
-	MX53_PIN_CSI0_D16 = _MXC_BUILD_GPIO_PIN(5, 2, 1, 0x100, 0x42C),
-	MX53_PIN_CSI0_D17 = _MXC_BUILD_GPIO_PIN(5, 3, 1, 0x104, 0x430),
-	MX53_PIN_CSI0_D18 = _MXC_BUILD_GPIO_PIN(5, 4, 1, 0x108, 0x434),
-	MX53_PIN_CSI0_D19 = _MXC_BUILD_GPIO_PIN(5, 5, 1, 0x10C, 0x438),
-	MX53_PIN_NVCC_CSI0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x43C),
-	MX53_PIN_JTAG_TMS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x440),
-	MX53_PIN_JTAG_MOD = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x444),
-	MX53_PIN_JTAG_TRSTB = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x448),
-	MX53_PIN_JTAG_TDI = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x44C),
-	MX53_PIN_JTAG_TCK = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x450),
-	MX53_PIN_JTAG_TDO = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x454),
-	MX53_PIN_EIM_A25 = _MXC_BUILD_GPIO_PIN(4, 2, 1, 0x110, 0x458),
-	MX53_PIN_EIM_EB2 = _MXC_BUILD_GPIO_PIN(1, 30, 1, 0x114, 0x45C),
-	MX53_PIN_EIM_D16 = _MXC_BUILD_GPIO_PIN(2, 16, 1, 0x118, 0x460),
-	MX53_PIN_EIM_D17 = _MXC_BUILD_GPIO_PIN(2, 17, 1, 0x11C, 0x464),
-	MX53_PIN_EIM_D18 = _MXC_BUILD_GPIO_PIN(2, 18, 1, 0x120, 0x468),
-	MX53_PIN_EIM_D19 = _MXC_BUILD_GPIO_PIN(2, 19, 1, 0x124, 0x46C),
-	MX53_PIN_EIM_D20 = _MXC_BUILD_GPIO_PIN(2, 20, 1, 0x128, 0x470),
-	MX53_PIN_EIM_D21 = _MXC_BUILD_GPIO_PIN(2, 21, 1, 0x12C, 0x474),
-	MX53_PIN_EIM_D22 = _MXC_BUILD_GPIO_PIN(2, 22, 1, 0x130, 0x478),
-	MX53_PIN_EIM_D23 = _MXC_BUILD_GPIO_PIN(2, 23, 1, 0x134, 0x47C),
-	MX53_PIN_EIM_EB3 = _MXC_BUILD_GPIO_PIN(1, 31, 1, 0x138, 0x480),
-	MX53_PIN_EIM_D24 = _MXC_BUILD_GPIO_PIN(2, 24, 1, 0x13C, 0x484),
-	MX53_PIN_EIM_D25 = _MXC_BUILD_GPIO_PIN(2, 25, 1, 0x140, 0x488),
-	MX53_PIN_EIM_D26 = _MXC_BUILD_GPIO_PIN(2, 26, 1, 0x144, 0x48C),
-	MX53_PIN_EIM_D27 = _MXC_BUILD_GPIO_PIN(2, 27, 1, 0x148, 0x490),
-	MX53_PIN_EIM_D28 = _MXC_BUILD_GPIO_PIN(2, 28, 1, 0x14C, 0x494),
-	MX53_PIN_EIM_D29 = _MXC_BUILD_GPIO_PIN(2, 29, 1, 0x150, 0x498),
-	MX53_PIN_EIM_D30 = _MXC_BUILD_GPIO_PIN(2, 30, 1, 0x154, 0x49C),
-	MX53_PIN_EIM_D31 = _MXC_BUILD_GPIO_PIN(2, 31, 1, 0x158, 0x4A0),
-	MX53_PIN_NVCC_EIM1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x4A4),
-	MX53_PIN_EIM_A24 = _MXC_BUILD_GPIO_PIN(4, 4, 1, 0x15C, 0x4A8),
-	MX53_PIN_EIM_A23 = _MXC_BUILD_GPIO_PIN(5, 6, 1, 0x160, 0x4AC),
-	MX53_PIN_EIM_A22 = _MXC_BUILD_GPIO_PIN(1, 16, 1, 0x164, 0x4B0),
-	MX53_PIN_EIM_A21 = _MXC_BUILD_GPIO_PIN(1, 17, 1, 0x168, 0x4B4),
-	MX53_PIN_EIM_A20 = _MXC_BUILD_GPIO_PIN(1, 18, 1, 0x16C, 0x4B8),
-	MX53_PIN_EIM_A19 = _MXC_BUILD_GPIO_PIN(1, 19, 1, 0x170, 0x4BC),
-	MX53_PIN_EIM_A18 = _MXC_BUILD_GPIO_PIN(1, 20, 1, 0x174, 0x4C0),
-	MX53_PIN_EIM_A17 = _MXC_BUILD_GPIO_PIN(1, 21, 1, 0x178, 0x4C4),
-	MX53_PIN_EIM_A16 = _MXC_BUILD_GPIO_PIN(1, 22, 1, 0x17C, 0x4C8),
-	MX53_PIN_EIM_CS0 = _MXC_BUILD_GPIO_PIN(1, 23, 1, 0x180, 0x4CC),
-	MX53_PIN_EIM_CS1 = _MXC_BUILD_GPIO_PIN(1, 24, 1, 0x184, 0x4D0),
-	MX53_PIN_EIM_OE = _MXC_BUILD_GPIO_PIN(1, 25, 1, 0x188, 0x4D4),
-	MX53_PIN_EIM_RW = _MXC_BUILD_GPIO_PIN(1, 26, 1, 0x18C, 0x4D8),
-	MX53_PIN_EIM_LBA = _MXC_BUILD_GPIO_PIN(1, 27, 1, 0x190, 0x4DC),
-	MX53_PIN_NVCC_EIM4 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x4E0),
-	MX53_PIN_EIM_EB0 = _MXC_BUILD_GPIO_PIN(1, 28, 1, 0x194, 0x4E4),
-	MX53_PIN_EIM_EB1 = _MXC_BUILD_GPIO_PIN(1, 29, 1, 0x198, 0x4E8),
-	MX53_PIN_EIM_DA0 = _MXC_BUILD_GPIO_PIN(2, 0, 1, 0x19C, 0x4EC),
-	MX53_PIN_EIM_DA1 = _MXC_BUILD_GPIO_PIN(2, 1, 1, 0x1A0, 0x4F0),
-	MX53_PIN_EIM_DA2 = _MXC_BUILD_GPIO_PIN(2, 2, 1, 0x1A4, 0x4F4),
-	MX53_PIN_EIM_DA3 = _MXC_BUILD_GPIO_PIN(2, 3, 1, 0x1A8, 0x4F8),
-	MX53_PIN_EIM_DA4 = _MXC_BUILD_GPIO_PIN(2, 4, 1, 0x1AC, 0x4FC),
-	MX53_PIN_EIM_DA5 = _MXC_BUILD_GPIO_PIN(2, 5, 1, 0x1B0, 0x500),
-	MX53_PIN_EIM_DA6 = _MXC_BUILD_GPIO_PIN(2, 6, 1, 0x1B4, 0x504),
-	MX53_PIN_EIM_DA7 = _MXC_BUILD_GPIO_PIN(2, 7, 1, 0x1B8, 0x508),
-	MX53_PIN_EIM_DA8 = _MXC_BUILD_GPIO_PIN(2, 8, 1, 0x1BC, 0x50C),
-	MX53_PIN_EIM_DA9 = _MXC_BUILD_GPIO_PIN(2, 9, 1, 0x1C0, 0x510),
-	MX53_PIN_EIM_DA10 = _MXC_BUILD_GPIO_PIN(2, 10, 1, 0x1C4, 0x514),
-	MX53_PIN_EIM_DA11 = _MXC_BUILD_GPIO_PIN(2, 11, 1, 0x1C8, 0x518),
-	MX53_PIN_EIM_DA12 = _MXC_BUILD_GPIO_PIN(2, 12, 1, 0x1CC, 0x51C),
-	MX53_PIN_EIM_DA13 = _MXC_BUILD_GPIO_PIN(2, 13, 1, 0x1D0, 0x520),
-	MX53_PIN_EIM_DA14 = _MXC_BUILD_GPIO_PIN(2, 14, 1, 0x1D4, 0x524),
-	MX53_PIN_EIM_DA15 = _MXC_BUILD_GPIO_PIN(2, 15, 1, 0x1D8, 0x528),
-	MX53_PIN_NANDF_WE_B = _MXC_BUILD_GPIO_PIN(5, 12, 1, 0x1DC, 0x52C),
-	MX53_PIN_NANDF_RE_B = _MXC_BUILD_GPIO_PIN(5, 13, 1, 0x1E0, 0x530),
-	MX53_PIN_EIM_WAIT = _MXC_BUILD_GPIO_PIN(4, 0, 1, 0x1E4, 0x534),
-	MX53_PIN_EIM_BCLK = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x538),
-	MX53_PIN_NVCC_EIM7 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x53C),
-	MX53_PIN_LVDS1_TX3_P = _MXC_BUILD_GPIO_PIN(5, 22, 0, 0x1EC, NON_PAD_I),
-	MX53_PIN_LVDS1_TX2_P = _MXC_BUILD_GPIO_PIN(5, 24, 0, 0x1F0, NON_PAD_I),
-	MX53_PIN_LVDS1_CLK_P = _MXC_BUILD_GPIO_PIN(5, 26, 0, 0x1F4, NON_PAD_I),
-	MX53_PIN_LVDS1_TX1_P = _MXC_BUILD_GPIO_PIN(5, 28, 0, 0x1F8, NON_PAD_I),
-	MX53_PIN_LVDS1_TX0_P = _MXC_BUILD_GPIO_PIN(5, 30, 0, 0x1FC, NON_PAD_I),
-	MX53_PIN_LVDS0_TX3_P = _MXC_BUILD_GPIO_PIN(6, 22, 0, 0x200, NON_PAD_I),
-	MX53_PIN_LVDS0_CLK_P = _MXC_BUILD_GPIO_PIN(6, 24, 0, 0x204, NON_PAD_I),
-	MX53_PIN_LVDS0_TX2_P = _MXC_BUILD_GPIO_PIN(6, 26, 0, 0x208, NON_PAD_I),
-	MX53_PIN_LVDS0_TX1_P = _MXC_BUILD_GPIO_PIN(6, 28, 0, 0x20C, NON_PAD_I),
-	MX53_PIN_LVDS0_TX0_P = _MXC_BUILD_GPIO_PIN(6, 30, 0, 0x210, NON_PAD_I),
-	MX53_PIN_GPIO_10 = _MXC_BUILD_GPIO_PIN(3, 0, 0, 0x214, 0x540),
-	MX53_PIN_GPIO_11 = _MXC_BUILD_GPIO_PIN(3, 1, 0, 0x218, 0x544),
-	MX53_PIN_GPIO_12 = _MXC_BUILD_GPIO_PIN(3, 2, 0, 0x21C, 0x548),
-	MX53_PIN_GPIO_13 = _MXC_BUILD_GPIO_PIN(3, 3, 0, 0x220, 0x54C),
-	MX53_PIN_GPIO_14 = _MXC_BUILD_GPIO_PIN(3, 4, 0, 0x224, 0x550),
-	MX53_PIN_DRAM_DQM3 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x554),
-	MX53_PIN_DRAM_SDQS3 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x558),
-	MX53_PIN_DRAM_SDCKE1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x55C),
-	MX53_PIN_DRAM_DQM2 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x560),
-	MX53_PIN_DRAM_SDODT1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x564),
-	MX53_PIN_DRAM_SDQS2 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x568),
-	MX53_PIN_DRAM_RESET = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x56C),
-	MX53_PIN_DRAM_SDCLK1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x570),
-	MX53_PIN_DRAM_CAS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x574),
-	MX53_PIN_DRAM_SDCLK0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x578),
-	MX53_PIN_DRAM_SDQS0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x57C),
-	MX53_PIN_DRAM_SDODT0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x580),
-	MX53_PIN_DRAM_DQM0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x584),
-	MX53_PIN_DRAM_RAS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x588),
-	MX53_PIN_DRAM_SDCKE0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x58C),
-	MX53_PIN_DRAM_SDQS1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x590),
-	MX53_PIN_DRAM_DQM1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x594),
-	MX53_PIN_PMIC_ON_REQ = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x598),
-	MX53_PIN_PMIC_STBY_REQ = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x59C),
-	MX53_PIN_NANDF_CLE = _MXC_BUILD_GPIO_PIN(5, 7, 1, 0x228, 0x5A0),
-	MX53_PIN_NANDF_ALE = _MXC_BUILD_GPIO_PIN(5, 8 , 1, 0x22C, 0x5A4),
-	MX53_PIN_NANDF_WP_B = _MXC_BUILD_GPIO_PIN(5, 9, 1, 0x230, 0x5A8),
-	MX53_PIN_NANDF_RB0 = _MXC_BUILD_GPIO_PIN(5, 10, 1, 0x234, 0x5AC),
-	MX53_PIN_NANDF_CS0 = _MXC_BUILD_GPIO_PIN(5, 11, 1, 0x238, 0x5B0),
-	MX53_PIN_NANDF_CS1 = _MXC_BUILD_GPIO_PIN(5, 14, 1, 0x23C, 0x5B4),
-	MX53_PIN_NANDF_CS2 = _MXC_BUILD_GPIO_PIN(5, 15, 1, 0x240, 0x5B8),
-	MX53_PIN_NANDF_CS3 = _MXC_BUILD_GPIO_PIN(5, 16, 1, 0x244, 0x5BC),
-	MX53_PIN_NVCC_NANDF = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x5C0),
-	MX53_PIN_FEC_MDIO = _MXC_BUILD_GPIO_PIN(0, 22, 1, 0x248, 0x5C4),
-	MX53_PIN_FEC_REF_CLK = _MXC_BUILD_GPIO_PIN(0, 23, 1, 0x24C, 0x5C8),
-	MX53_PIN_FEC_RX_ER = _MXC_BUILD_GPIO_PIN(0, 24, 1, 0x250, 0x5CC),
-	MX53_PIN_FEC_CRS_DV = _MXC_BUILD_GPIO_PIN(0, 25, 1, 0x254, 0x5D0),
-	MX53_PIN_FEC_RXD1 = _MXC_BUILD_GPIO_PIN(0, 26, 1, 0x258, 0x5D4),
-	MX53_PIN_FEC_RXD0 = _MXC_BUILD_GPIO_PIN(0, 27, 1, 0x25C, 0x5D8),
-	MX53_PIN_FEC_TX_EN = _MXC_BUILD_GPIO_PIN(0, 28, 1, 0x260, 0x5DC),
-	MX53_PIN_FEC_TXD1 = _MXC_BUILD_GPIO_PIN(0, 29, 1, 0x264, 0x5E0),
-	MX53_PIN_FEC_TXD0 = _MXC_BUILD_GPIO_PIN(0, 30, 1, 0x268, 0x5E4),
-	MX53_PIN_FEC_MDC = _MXC_BUILD_GPIO_PIN(0, 31, 1, 0x26C, 0x5E8),
-	MX53_PIN_NVCC_FEC = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x5EC),
-	MX53_PIN_ATA_DIOW = _MXC_BUILD_GPIO_PIN(5, 17, 1, 0x270, 0x5F0),
-	MX53_PIN_ATA_DMACK = _MXC_BUILD_GPIO_PIN(5, 18, 1, 0x274, 0x5F4),
-	MX53_PIN_ATA_DMARQ = _MXC_BUILD_GPIO_PIN(6, 0, 1, 0x278, 0x5F8),
-	MX53_PIN_ATA_BUFFER_EN = _MXC_BUILD_GPIO_PIN(6, 1, 1, 0x27C, 0x5FC),
-	MX53_PIN_ATA_INTRQ = _MXC_BUILD_GPIO_PIN(6, 2, 1, 0x280, 0x600),
-	MX53_PIN_ATA_DIOR = _MXC_BUILD_GPIO_PIN(6, 3, 1, 0x284, 0x604),
-	MX53_PIN_ATA_RESET_B = _MXC_BUILD_GPIO_PIN(6, 4, 1, 0x288, 0x608),
-	MX53_PIN_ATA_IORDY = _MXC_BUILD_GPIO_PIN(6, 5, 1, 0x28C, 0x60C),
-	MX53_PIN_ATA_DA_0 = _MXC_BUILD_GPIO_PIN(6, 6, 1, 0x290, 0x610),
-	MX53_PIN_ATA_DA_1 = _MXC_BUILD_GPIO_PIN(6, 7, 1, 0x294, 0x614),
-	MX53_PIN_ATA_DA_2 = _MXC_BUILD_GPIO_PIN(6, 8, 1, 0x298, 0x618),
-	MX53_PIN_ATA_CS_0 = _MXC_BUILD_GPIO_PIN(6, 9, 1, 0x29C, 0x61C),
-	MX53_PIN_ATA_CS_1 = _MXC_BUILD_GPIO_PIN(6, 10, 1, 0x2A0, 0x620),
-	MX53_PIN_NVCC_ATA2 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x624),
-	MX53_PIN_ATA_DATA0 = _MXC_BUILD_GPIO_PIN(1, 0, 1, 0x2A4, 0x628),
-	MX53_PIN_ATA_DATA1 = _MXC_BUILD_GPIO_PIN(1, 1, 1, 0x2A8, 0x62C),
-	MX53_PIN_ATA_DATA2 = _MXC_BUILD_GPIO_PIN(1, 2, 1, 0x2AC, 0x630),
-	MX53_PIN_ATA_DATA3 = _MXC_BUILD_GPIO_PIN(1, 3, 1, 0x2B0, 0x634),
-	MX53_PIN_ATA_DATA4 = _MXC_BUILD_GPIO_PIN(1, 4, 1, 0x2B4, 0x638),
-	MX53_PIN_ATA_DATA5 = _MXC_BUILD_GPIO_PIN(1, 5, 1, 0x2B8, 0x63C),
-	MX53_PIN_ATA_DATA6 = _MXC_BUILD_GPIO_PIN(1, 6, 1, 0x2BC, 0x640),
-	MX53_PIN_ATA_DATA7 = _MXC_BUILD_GPIO_PIN(1, 7, 1, 0x2C0, 0x644),
-	MX53_PIN_ATA_DATA8 = _MXC_BUILD_GPIO_PIN(1, 8, 1, 0x2C4, 0x648),
-	MX53_PIN_ATA_DATA9 = _MXC_BUILD_GPIO_PIN(1, 9, 1, 0x2C8, 0x64C),
-	MX53_PIN_ATA_DATA10 = _MXC_BUILD_GPIO_PIN(1, 10, 1, 0x2CC, 0x650),
-	MX53_PIN_ATA_DATA11 = _MXC_BUILD_GPIO_PIN(1, 11, 1, 0x2D0, 0x654),
-	MX53_PIN_ATA_DATA12 = _MXC_BUILD_GPIO_PIN(1, 12, 1, 0x2D4, 0x658),
-	MX53_PIN_ATA_DATA13 = _MXC_BUILD_GPIO_PIN(1, 13, 1, 0x2D8, 0x65C),
-	MX53_PIN_ATA_DATA14 = _MXC_BUILD_GPIO_PIN(1, 14, 1, 0x2DC, 0x660),
-	MX53_PIN_ATA_DATA15 = _MXC_BUILD_GPIO_PIN(1, 15, 1, 0x2E0, 0x664),
-	MX53_PIN_NVCC_ATA0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x668),
-	MX53_PIN_SD1_DATA0 = _MXC_BUILD_GPIO_PIN(0, 16, 1, 0x2E4, 0x66C),
-	MX53_PIN_SD1_DATA1 = _MXC_BUILD_GPIO_PIN(0, 17, 1, 0x2E8, 0x670),
-	MX53_PIN_SD1_CMD = _MXC_BUILD_GPIO_PIN(0, 18, 1, 0x2EC, 0x674),
-	MX53_PIN_SD1_DATA2 = _MXC_BUILD_GPIO_PIN(0, 19, 1, 0x2F0, 0x678),
-	MX53_PIN_SD1_CLK = _MXC_BUILD_GPIO_PIN(0, 20, 1, 0x2F4, 0x67C),
-	MX53_PIN_SD1_DATA3 = _MXC_BUILD_GPIO_PIN(0, 21, 1, 0x2F8, 0x680),
-	MX53_PIN_NVCC_SD1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x684),
-	MX53_PIN_SD2_CLK = _MXC_BUILD_GPIO_PIN(0, 10, 1, 0x2FC, 0x688),
-	MX53_PIN_SD2_CMD = _MXC_BUILD_GPIO_PIN(0, 11, 1, 0x300, 0x68C),
-	MX53_PIN_SD2_DATA3 = _MXC_BUILD_GPIO_PIN(0, 12, 1, 0x304, 0x690),
-	MX53_PIN_SD2_DATA2 = _MXC_BUILD_GPIO_PIN(0, 13, 1, 0x308, 0x694),
-	MX53_PIN_SD2_DATA1 = _MXC_BUILD_GPIO_PIN(0, 14, 1, 0x30C, 0x698),
-	MX53_PIN_SD2_DATA0 = _MXC_BUILD_GPIO_PIN(0, 15, 1, 0x310, 0x69C),
-	MX53_PIN_NVCC_SD2 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6A0),
-	MX53_PIN_GPIO_0 = _MXC_BUILD_GPIO_PIN(0, 0, 1, 0x314, 0x6A4),
-	MX53_PIN_GPIO_1 = _MXC_BUILD_GPIO_PIN(0, 1, 1, 0x318, 0x6A8),
-	MX53_PIN_GPIO_9 = _MXC_BUILD_GPIO_PIN(0, 9, 1, 0x31C, 0x6AC),
-	MX53_PIN_GPIO_3 = _MXC_BUILD_GPIO_PIN(0, 3, 1, 0x320, 0x6B0),
-	MX53_PIN_GPIO_6 = _MXC_BUILD_GPIO_PIN(0, 6, 1, 0x324, 0x6B4),
-	MX53_PIN_GPIO_2 = _MXC_BUILD_GPIO_PIN(0, 2, 1, 0x328, 0x6B8),
-	MX53_PIN_GPIO_4 = _MXC_BUILD_GPIO_PIN(0, 4, 1, 0x32C, 0x6BC),
-	MX53_PIN_GPIO_5 = _MXC_BUILD_GPIO_PIN(0, 5, 1, 0x330, 0x6C0),
-	MX53_PIN_GPIO_7 = _MXC_BUILD_GPIO_PIN(0, 7, 1, 0x334, 0x6C4),
-	MX53_PIN_GPIO_8 = _MXC_BUILD_GPIO_PIN(0, 8, 1, 0x338, 0x6C8),
-	MX53_PIN_GPIO_16 = _MXC_BUILD_GPIO_PIN(6, 11, 1, 0x33C, 0x6CC),
-	MX53_PIN_GPIO_17 = _MXC_BUILD_GPIO_PIN(6, 12, 1, 0x340, 0x6D0),
-	MX53_PIN_GPIO_18 = _MXC_BUILD_GPIO_PIN(6, 13, 1, 0x344, 0x6D4),
-	MX53_PIN_NVCC_GPIO = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6D8),
-	MX53_PIN_POR_B = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6DC),
-	MX53_PIN_BOOT_MODE1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6E0),
-	MX53_PIN_RESET_IN_B = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6E4),
-	MX53_PIN_BOOT_MODE0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6E8),
-	MX53_PIN_TEST_MODE = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6EC),
-	MX53_PIN_GRP_ADDDS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6F0),
-	MX53_PIN_GRP_DDRMODE_CTL = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6F4),
-	MX53_PIN_GRP_DDRPKE = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6FC),
-	MX53_PIN_GRP_DDRPK = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x708),
-	MX53_PIN_GRP_TERM_CTL3 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x70C),
-	MX53_PIN_GRP_DDRHYS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x710),
-	MX53_PIN_GRP_DDRMODE = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x714),
-	MX53_PIN_GRP_B0DS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x718),
-	MX53_PIN_GRP_B1DS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x71C),
-	MX53_PIN_GRP_CTLDS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x720),
-	MX53_PIN_GRP_DDR_TYPE = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x724),
-	MX53_PIN_GRP_B2DS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x728),
-	MX53_PIN_GRP_B3DS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x72C),
-};
-/* various IOMUX input select register index */
-typedef enum iomux_input_select {
-	MX51_AUDMUX_P4_INPUT_DA_AMX_SELECT_I = 0,
-	MX51_AUDMUX_P4_INPUT_DB_AMX_SELECT_I,
-	MX51_AUDMUX_P4_INPUT_TXCLK_AMX_SELECT_INPUT,
-	MX51_AUDMUX_P4_INPUT_TXFS_AMX_SELECT_INPUT,
-	MX51_AUDMUX_P5_INPUT_DA_AMX_SELECT_INPUT,
-	MX51_AUDMUX_P5_INPUT_DB_AMX_SELECT_INPUT,
-	MX51_AUDMUX_P5_INPUT_RXCLK_AMX_SELECT_INPUT,
-	MX51_AUDMUX_P5_INPUT_RXFS_AMX_SELECT,
-	MX51_AUDMUX_P5_INPUT_TXCLK_AMX_SELECT_INPUT,
-	MX51_AUDMUX_P5_INPUT_TXFS_AMX_SELECT_INPUT,
-	MX51_AUDMUX_P6_INPUT_DA_AMX_SELECT_INPUT,
-	MX51_AUDMUX_P6_INPUT_DB_AMX_SELECT_INPUT,
-	MX51_AUDMUX_P6_INPUT_RXCLK_AMX_SELECT_INPUT,
-	MX51_AUDMUX_P6_INPUT_RXFS_AMX_SELECT_INPUT,
-	MX51_AUDMUX_P6_INPUT_TXCLK_AMX_SELECT_INPUT,
-	MX51_AUDMUX_P6_INPUT_TXFS_AMX_SELECT_INPUT,
-	MX51_CCM_IPP_DI_CLK_SELECT_INPUT,
-	/* TO2 */
-	MX51_CCM_IPP_DI1_CLK_SELECT_INPUT,
-	MX51_CCM_PLL1_BYPASS_CLK_SELECT_INPUT,
-	MX51_CCM_PLL2_BYPASS_CLK_SELECT_INPUT,
-	MX51_CSPI_IPP_CSPI_CLK_IN_SELECT_INPUT,
-	MX51_CSPI_IPP_IND_MISO_SELECT_INPUT,
-	MX51_CSPI_IPP_IND_MOSI_SELECT_INPUT,
-	MX51_CSPI_IPP_IND_SS_B_1_SELECT_INPUT,
-	MX51_CSPI_IPP_IND_SS_B_2_SELECT_INPUT,
-	MX51_CSPI_IPP_IND_SS_B_3_SELECT_INPUT,
-	MX51_DPLLIP1_L1T_TOG_EN_SELECT_INPUT,
-	/* TO2 */
-	MX51_ECSPI2_IPP_IND_SS_B_1_SELECT_INPUT,
-	MX51_ECSPI2_IPP_IND_SS_B_3_SELECT_INPUT,
-	MX51_EMI_IPP_IND_RDY_INT_SELECT_INPUT,
-	MX51_ESDHC3_IPP_DAT0_IN_SELECT_INPUT,
-	MX51_ESDHC3_IPP_DAT1_IN_SELECT_INPUT,
-	MX51_ESDHC3_IPP_DAT2_IN_SELECT_INPUT,
-	MX51_ESDHC3_IPP_DAT3_IN_SELECT_INPUT,
-	MX51_FEC_FEC_COL_SELECT_INPUT,
-	MX51_FEC_FEC_CRS_SELECT_INPUT,
-	MX51_FEC_FEC_MDI_SELECT_INPUT,
-	MX51_FEC_FEC_RDATA_0_SELECT_INPUT,
-	MX51_FEC_FEC_RDATA_1_SELECT_INPUT,
-	MX51_FEC_FEC_RDATA_2_SELECT_INPUT,
-	MX51_FEC_FEC_RDATA_3_SELECT_INPUT,
-	MX51_FEC_FEC_RX_CLK_SELECT_INPUT,
-	MX51_FEC_FEC_RX_DV_SELECT_INPUT,
-	MX51_FEC_FEC_RX_ER_SELECT_INPUT,
-	MX51_FEC_FEC_TX_CLK_SELECT_INPUT,
-	MX51_GPIO3_IPP_IND_G_IN_1_SELECT_INPUT,
-	MX51_GPIO3_IPP_IND_G_IN_2_SELECT_INPUT,
-	MX51_GPIO3_IPP_IND_G_IN_3_SELECT_INPUT,
-	MX51_GPIO3_IPP_IND_G_IN_4_SELECT_INPUT,
-	MX51_GPIO3_IPP_IND_G_IN_5_SELECT_INPUT,
-	MX51_GPIO3_IPP_IND_G_IN_6_SELECT_INPUT,
-	MX51_GPIO3_IPP_IND_G_IN_7_SELECT_INPUT,
-	MX51_GPIO3_IPP_IND_G_IN_8_SELECT_INPUT,
-	/* TO2 */
-	MX51_GPIO3_IPP_IND_G_IN_12_SELECT_INPUT,
-	MX51_HSC_MIPI_MIX_IPP_IND_SENS1_DATA_EN_SELECT_INPUT,
-	MX51_HSC_MIPI_MIX_IPP_IND_SENS2_DATA_EN_SELECT_INPUT,
-	/* TO2 */
-	MX51_HSC_MIPI_MIX_PAR_VSYNC_SELECT_INPUT,
-	/* TO2 */
-	MX51_HSC_MIPI_MIX_PAR_DI_WAIT_SELECT_INPUT,
-	MX51_HSC_MIPI_MIX_PAR_SISG_TRIG_SELECT_INPUT,
-	MX51_I2C1_IPP_SCL_IN_SELECT_INPUT,
-	MX51_I2C1_IPP_SDA_IN_SELECT_INPUT,
-	MX51_I2C2_IPP_SCL_IN_SELECT_INPUT,
-	MX51_I2C2_IPP_SDA_IN_SELECT_INPUT,
-	MX51_IPU_IPP_DI_0_IND_DISPB_SD_D_SELECT_INPUT,
-	MX51_IPU_IPP_DI_1_IND_DISPB_SD_D_SELECT_INPUT,
-	MX51_KPP_IPP_IND_COL_6_SELECT_INPUT,
-	MX51_KPP_IPP_IND_COL_7_SELECT_INPUT,
-	MX51_KPP_IPP_IND_ROW_4_SELECT_INPUT,
-	MX51_KPP_IPP_IND_ROW_5_SELECT_INPUT,
-	MX51_KPP_IPP_IND_ROW_6_SELECT_INPUT,
-	MX51_KPP_IPP_IND_ROW_7_SELECT_INPUT,
-	MX51_UART1_IPP_UART_RTS_B_SELECT_INPUT,
-	MX51_UART1_IPP_UART_RXD_MUX_SELECT_INPUT,
-	MX51_UART2_IPP_UART_RTS_B_SELECT_INPUT,
-	MX51_UART2_IPP_UART_RXD_MUX_SELECT_INPUT,
-	MX51_UART3_IPP_UART_RTS_B_SELECT_INPUT,
-	MX51_UART3_IPP_UART_RXD_MUX_SELECT_INPUT,
-	MX51_USBOH3_IPP_IND_UH3_CLK_SELECT_INPUT,
-	MX51_USBOH3_IPP_IND_UH3_DATA_0_SELECT_INPUT,
-	MX51_USBOH3_IPP_IND_UH3_DATA_1_SELECT_INPUT,
-	MX51_USBOH3_IPP_IND_UH3_DATA_2_SELECT_INPUT,
-	MX51_USBOH3_IPP_IND_UH3_DATA_3_SELECT_INPUT,
-	MX51_USBOH3_IPP_IND_UH3_DATA_4_SELECT_INPUT,
-	MX51_USBOH3_IPP_IND_UH3_DATA_5_SELECT_INPUT,
-	MX51_USBOH3_IPP_IND_UH3_DATA_6_SELECT_INPUT,
-	MX51_USBOH3_IPP_IND_UH3_DATA_7_SELECT_INPUT,
-	MX51_USBOH3_IPP_IND_UH3_DIR_SELECT_INPUT,
-	MX51_USBOH3_IPP_IND_UH3_NXT_SELECT_INPUT,
-	MX51_USBOH3_IPP_IND_UH3_STP_SELECT_INPUT,
-	MX51PUT_NUM_MUX,
-	/* MX53 */
-	MX53_AUDMUX_P4_INPUT_DA_AMX_SELECT_I = 0,
-	MX53_AUDMUX_P4_INPUT_DB_AMX_SELECT_I,
-	MX53_AUDMUX_P4_INPUT_RXCLK_AMX_SELECT_INPUT,
-	MX53_AUDMUX_P4_INPUT_RXFS_AMX_SELECT_INPUT,
-	MX53_AUDMUX_P4_INPUT_TXCLK_AMX_SELECT_INPUT,
-	MX53_AUDMUX_P4_INPUT_TXFS_AMX_SELECT_INPUT,
-	MX53_AUDMUX_P5_INPUT_DA_AMX_SELECT_I,
-	MX53_AUDMUX_P5_INPUT_DB_AMX_SELECT_I,
-	MX53_AUDMUX_P5_INPUT_RXCLK_AMX_SELECT_INPUT,
-	MX53_AUDMUX_P5_INPUT_RXFS_AMX_SELECT_INPUT,
-	MX53_AUDMUX_P5_INPUT_TXCLK_AMX_SELECT_INPUT,
-	MX53_AUDMUX_P5_INPUT_TXFS_AMX_SELECT_INPUT,
-	MX53_CAN1_IPP_IND_CANRX_SELECT_INPUT,
-	MX53_CAN2_IPP_IND_CANRX_SELECT_INPUT,
-	MX53_CCM_IPP_ASRC_EXT_SELECT_INPUT,
-	MX53_CCM_IPP_DI1_CLK_SELECT_INPUT,
-	MX53_CCM_PLL1_BYPASS_CLK_SELECT_INPUT,
-	MX53_CCM_PLL2_BYPASS_CLK_SELECT_INPUT,
-	MX53_CCM_PLL3_BYPASS_CLK_SELECT_INPUT,
-	MX53_CCM_PLL4_BYPASS_CLK_SELECT_INPUT,
-	MX53_CSPI_IPP_CSPI_CLK_IN_SELECT_INPUT,
-	MX53_CSPI_IPP_IND_MISO_SELECT_INPUT,
-	MX53_CSPI_IPP_IND_MOSI_SELECT_INPUT,
-	MX53_CSPI_IPP_IND_SS_B_1_SELECT_INPUT,
-	MX53_CSPI_IPP_IND_SS_B_2_SELECT_INPUT,
-	MX53_CSPI_IPP_IND_SS_B_3_SELECT_INPUT,
-	MX53_CSPI_IPP_IND_SS_B_4_SELECT_INPUT,
-	MX53_ECSPI1_IPP_CSPI_CLK_IN_SELECT_INPUT,
-	MX53_ECSPI1_IPP_IND_MISO_SELECT_INPUT,
-	MX53_ECSPI1_IPP_IND_MOSI_SELECT_INPUT,
-	MX53_ECSPI1_IPP_IND_SS_B_1_SELECT_INPUT,
-	MX53_ECSPI1_IPP_IND_SS_B_2_SELECT_INPUT,
-	MX53_ECSPI1_IPP_IND_SS_B_3_SELECT_INPUT,
-	MX53_ECSPI1_IPP_IND_SS_B_4_SELECT_INPUT,
-	MX53_ECSPI2_IPP_CSPI_CLK_IN_SELECT_INPUT,
-	MX53_ECSPI2_IPP_IND_MISO_SELECT_INPUT,
-	MX53_ECSPI2_IPP_IND_MOSI_SELECT_INPUT,
-	MX53_ECSPI2_IPP_IND_SS_B_1_SELECT_INPUT,
-	MX53_ECSPI2_IPP_IND_SS_B_2_SELECT_INPUT,
-	MX53_ESAI1_IPP_IND_FSR_SELECT_INPUT,
-	MX53_ESAI1_IPP_IND_FST_SELECT_INPUT,
-	MX53_ESAI1_IPP_IND_HCKR_SELECT_INPUT,
-	MX53_ESAI1_IPP_IND_HCKT_SELECT_INPUT,
-	MX53_ESAI1_IPP_IND_SCKR_SELECT_INPUT,
-	MX53_ESAI1_IPP_IND_SCKT_SELECT_INPUT,
-	MX53_ESAI1_IPP_IND_SDO0_SELECT_INPUT,
-	MX53_ESAI1_IPP_IND_SDO1_SELECT_INPUT,
-	MX53_ESAI1_IPP_IND_SDO2_SDI3_SELECT_INPUT,
-	MX53_ESAI1_IPP_IND_SDO3_SDI2_SELECT_INPUT,
-	MX53_ESAI1_IPP_IND_SDO4_SDI1_SELECT_INPUT,
-	MX53_ESAI1_IPP_IND_SDO5_SDI0_SELECT_INPUT,
-	MX53_ESDHC1_IPP_WP_ON_SELECT_INPUT,
-	MX53_FEC_FEC_COL_SELECT_INPUT,
-	MX53_FEC_FEC_MDI_SELECT_INPUT,
-	MX53_FEC_FEC_RX_CLK_SELECT_INPUT,
-	MX53_FIRI_IPP_IND_RXD_SELECT_INPUT,
-	MX53_GPC_PMIC_RDY_SELECT_INPUT,
-	MX53_I2C1_IPP_SCL_IN_SELECT_INPUT,
-	MX53_I2C1_IPP_SDA_IN_SELECT_INPUT,
-	MX53_I2C2_IPP_SCL_IN_SELECT_INPUT,
-	MX53_I2C2_IPP_SDA_IN_SELECT_INPUT,
-	MX53_I2C3_IPP_SCL_IN_SELECT_INPUT,
-	MX53_I2C3_IPP_SDA_IN_SELECT_INPUT,
-	MX53_IPU_IPP_DI_0_IND_DISPB_SD_D_SELECT_INPUT,
-	MX53_IPU_IPP_DI_1_IND_DISPB_SD_D_SELECT_INPUT,
-	MX53_IPU_IPP_IND_SENS1_DATA_EN_SELECT_INPUT,
-	MX53_IPU_IPP_IND_SENS1_HSYNC_SELECT_INPUT,
-	MX53_IPU_IPP_IND_SENS1_VSYNC_SELECT_INPUT,
-	MX53_KPP_IPP_IND_COL_5_SELECT_INPUT,
-	MX53_KPP_IPP_IND_COL_6_SELECT_INPUT,
-	MX53_KPP_IPP_IND_COL_7_SELECT_INPUT,
-	MX53_KPP_IPP_IND_ROW_5_SELECT_INPUT,
-	MX53_KPP_IPP_IND_ROW_6_SELECT_INPUT,
-	MX53_KPP_IPP_IND_ROW_7_SELECT_INPUT,
-	MX53_MLB_MLBCLK_IN_SELECT_INPUT,
-	MX53_MLB_MLBDAT_IN_SELECT_INPUT,
-	MX53_MLB_MLBSIG_IN_SELECT_INPUT,
-	MX53_OWIRE_BATTERY_LINE_IN_SELECT_INPUT,
-	MX53_SDMA_EVENTS_14_SELECT_INPUT,
-	MX53_SDMA_EVENTS_15_SELECT_INPUT,
-	MX53_SPDIF_SPDIF_IN1_SELECT_INPUT,
-	MX53_UART1_IPP_UART_RTS_B_SELECT_INPUT,
-	MX53_UART1_IPP_UART_RXD_MUX_SELECT_INPUT,
-	MX53_UART2_IPP_UART_RTS_B_SELECT_INPUT,
-	MX53_UART2_IPP_UART_RXD_MUX_SELECT_INPUT,
-	MX53_UART3_IPP_UART_RTS_B_SELECT_INPUT,
-	MX53_UART3_IPP_UART_RXD_MUX_SELECT_INPUT,
-	MX53_UART4_IPP_UART_RTS_B_SELECT_INPUT,
-	MX53_UART4_IPP_UART_RXD_MUX_SELECT_INPUT,
-	MX53_UART5_IPP_UART_RTS_B_SELECT_INPUT,
-	MX53_UART5_IPP_UART_RXD_MUX_SELECT_INPUT,
-	MX53_USBOH3_IPP_IND_OTG_OC_SELECT_INPUT,
-	MX53_USBOH3_IPP_IND_UH1_OC_SELECT_INPUT,
-	MX53_USBOH3_IPP_IND_UH2_OC_SELECT_INPUT,
-} iomux_input_select_t;
-
-#endif				/* __ASSEMBLY__ */
-#endif				/* __ASM_ARCH_MX5_MX5X_PINS_H__ */
diff --git a/arch/arm/include/asm/arch-mx5/sys_proto.h b/arch/arm/include/asm/arch-mx5/sys_proto.h
deleted file mode 100644
index f687503..0000000
--- a/arch/arm/include/asm/arch-mx5/sys_proto.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * (C) Copyright 2009
- * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef _SYS_PROTO_H_
-#define _SYS_PROTO_H_
-
-u32 get_cpu_rev(void);
-#define is_soc_rev(rev)	((get_cpu_rev() & 0xFF) - rev)
-void sdelay(unsigned long);
-
-#endif
diff --git a/arch/arm/include/asm/arch-nomadik/gpio.h b/arch/arm/include/asm/arch-nomadik/gpio.h
deleted file mode 100644
index 1d3c9ce..0000000
--- a/arch/arm/include/asm/arch-nomadik/gpio.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * (C) Copyright 2009 Alessandro Rubini
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-#ifndef __NMK_GPIO_H__
-#define __NMK_GPIO_H__
-
-/*
- * These functions are called from the soft-i2c driver, but
- * are also used by board files to set output bits.
- */
-
-enum nmk_af { /* alternate function settings */
-	GPIO_GPIO = 0,
-	GPIO_ALT_A,
-	GPIO_ALT_B,
-	GPIO_ALT_C
-};
-
-extern void nmk_gpio_af(int gpio, int alternate_function);
-extern void nmk_gpio_dir(int gpio, int dir);
-extern void nmk_gpio_set(int gpio, int val);
-extern int nmk_gpio_get(int gpio);
-
-#endif /* __NMK_GPIO_H__ */
diff --git a/arch/arm/include/asm/arch-nomadik/mtu.h b/arch/arm/include/asm/arch-nomadik/mtu.h
deleted file mode 100644
index a87be9e..0000000
--- a/arch/arm/include/asm/arch-nomadik/mtu.h
+++ /dev/null
@@ -1,66 +0,0 @@
-/*
- * (C) Copyright 2009 Alessandro Rubini
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __ASM_ARCH_MTU_H
-#define __ASM_ARCH_MTU_H
-
-/*
- * The MTU device hosts four different counters, with 4 set of
- * registers. These are register names.
- */
-
-#define MTU_IMSC	0x00	/* Interrupt mask set/clear */
-#define MTU_RIS		0x04	/* Raw interrupt status */
-#define MTU_MIS		0x08	/* Masked interrupt status */
-#define MTU_ICR		0x0C	/* Interrupt clear register */
-
-/* per-timer registers take 0..3 as argument */
-#define MTU_LR(x)	(0x10 + 0x10 * (x) + 0x00)	/* Load value */
-#define MTU_VAL(x)	(0x10 + 0x10 * (x) + 0x04)	/* Current value */
-#define MTU_CR(x)	(0x10 + 0x10 * (x) + 0x08)	/* Control reg */
-#define MTU_BGLR(x)	(0x10 + 0x10 * (x) + 0x0c)	/* At next overflow */
-
-/* bits for the control register */
-#define MTU_CRn_ENA		0x80
-#define MTU_CRn_PERIODIC	0x40	/* if 0 = free-running */
-#define MTU_CRn_PRESCALE_MASK	0x0c
-#define MTU_CRn_PRESCALE_1		0x00
-#define MTU_CRn_PRESCALE_16		0x04
-#define MTU_CRn_PRESCALE_256		0x08
-#define MTU_CRn_32BITS		0x02
-#define MTU_CRn_ONESHOT		0x01	/* if 0 = wraps reloading from BGLR*/
-
-/* Other registers are usual amba/primecell registers, currently not used */
-#define MTU_ITCR	0xff0
-#define MTU_ITOP	0xff4
-
-#define MTU_PERIPH_ID0	0xfe0
-#define MTU_PERIPH_ID1	0xfe4
-#define MTU_PERIPH_ID2	0xfe8
-#define MTU_PERIPH_ID3	0xfeC
-
-#define MTU_PCELL0	0xff0
-#define MTU_PCELL1	0xff4
-#define MTU_PCELL2	0xff8
-#define MTU_PCELL3	0xffC
-
-#endif /* __ASM_ARCH_MTU_H */
diff --git a/arch/arm/include/asm/arch-omap24xx/bits.h b/arch/arm/include/asm/arch-omap24xx/bits.h
deleted file mode 100644
index 8522335..0000000
--- a/arch/arm/include/asm/arch-omap24xx/bits.h
+++ /dev/null
@@ -1,48 +0,0 @@
-/* bits.h
- * Copyright (c) 2004 Texas Instruments
- *
- * This package is free software;  you can redistribute it and/or
- * modify it under the terms of the license found in the file
- * named COPYING that should have accompanied this file.
- *
- * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
- * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
- */
-#ifndef __bits_h
-#define __bits_h 1
-
-#define BIT0  (1<<0)
-#define BIT1  (1<<1)
-#define BIT2  (1<<2)
-#define BIT3  (1<<3)
-#define BIT4  (1<<4)
-#define BIT5  (1<<5)
-#define BIT6  (1<<6)
-#define BIT7  (1<<7)
-#define BIT8  (1<<8)
-#define BIT9  (1<<9)
-#define BIT10 (1<<10)
-#define BIT11 (1<<11)
-#define BIT12 (1<<12)
-#define BIT13 (1<<13)
-#define BIT14 (1<<14)
-#define BIT15 (1<<15)
-#define BIT16 (1<<16)
-#define BIT17 (1<<17)
-#define BIT18 (1<<18)
-#define BIT19 (1<<19)
-#define BIT20 (1<<20)
-#define BIT21 (1<<21)
-#define BIT22 (1<<22)
-#define BIT23 (1<<23)
-#define BIT24 (1<<24)
-#define BIT25 (1<<25)
-#define BIT26 (1<<26)
-#define BIT27 (1<<27)
-#define BIT28 (1<<28)
-#define BIT29 (1<<29)
-#define BIT30 (1<<30)
-#define BIT31 (1<<31)
-
-#endif
diff --git a/arch/arm/include/asm/arch-omap24xx/clocks.h b/arch/arm/include/asm/arch-omap24xx/clocks.h
deleted file mode 100644
index 2e92569..0000000
--- a/arch/arm/include/asm/arch-omap24xx/clocks.h
+++ /dev/null
@@ -1,112 +0,0 @@
-/*
- * (C) Copyright 2004
- * Texas Instruments, <www.ti.com>
- * Richard Woodruff <r-woodruff2@ti.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
-  */
-#ifndef _OMAP24XX_CLOCKS_H_
-#define _OMAP24XX_CLOCKS_H_
-
-#define COMMIT_DIVIDERS  0x1
-
-#define MODE_BYPASS_FAST 0x2
-#define APLL_LOCK        0xc
-#ifdef CONFIG_APTIX
-#define DPLL_LOCK        0x1   /* stay in bypass mode */
-#else
-#define DPLL_LOCK        0x3   /* DPLL lock */
-#endif
-
-/****************************************************************************;
-; PRCM Scheme II
-;
-; Enable clocks and DPLL for:
-;  DPLL=300,	DPLLout=600	M=1,N=50   CM_CLKSEL1_PLL[21:8]  12/2*50
-;  Core=600	(core domain)   DPLLx2     CM_CLKSEL2_PLL[1:0]
-;  MPUF=300	(mpu domain)    2          CM_CLKSEL_MPU[4:0]
-;  DSPF=200    (dsp domain)    3          CM_CLKSEL_DSP[4:0]
-;  DSPI=100                    6          CM_CLKSEL_DSP[6:5]
-;  DSP_S          bypass	               CM_CLKSEL_DSP[7]
-;  IVAF=200    (dsp domain)    3          CM_CLKSEL_DSP[12:8]
-;  IVAF=100        auto
-;  IVAI            auto
-;  IVA_MPU         auto
-;  IVA_S          bypass                  CM_CLKSEL_DSP[13]
-;  GFXF=50      (gfx domain)	12         CM_CLKSEL_FGX[2:0]
-;  SSI_SSRF=200                 3         CM_CLKSEL1_CORE[24:20]
-;  SSI_SSTF=100     auto
-;  L3=100Mhz (sdram)            6         CM_CLKSEL1_CORE[4:0]
-;  L4=100Mhz                    6
-;  C_L4_USB=50                 12         CM_CLKSEL1_CORE[6:5]
-***************************************************************************/
-#define II_DPLL_OUT_X2   0x2    /* x2 core out */
-#define II_MPU_DIV       0x2    /* mpu = core/2 */
-#define II_DSP_DIV       0x343  /* dsp & iva divider */
-#define II_GFX_DIV       0x2
-#define II_BUS_DIV       0x04601026
-#define II_DPLL_300      0x01832100
-
-/****************************************************************************;
-; PRCM Scheme III
-;
-; Enable clocks and DPLL for:
-;  DPLL=266,	DPLLout=532	M=5+1,N=133 CM_CLKSEL1_PLL[21:8]  12/6*133=266
-;  Core=532	(core domain)   DPLLx2      CM_CLKSEL2_PLL[1:0]
-;  MPUF=266	(mpu domain)    /2          CM_CLKSEL_MPU[4:0]
-;  DSPF=177.3     (dsp domain)  /3          CM_CLKSEL_DSP[4:0]
-;  DSPI=88.67                   /6          CM_CLKSEL_DSP[6:5]
-;  DSP_S         ACTIVATED	            CM_CLKSEL_DSP[7]
-;  IVAF=88.67    (dsp domain)   /3          CM_CLKSEL_DSP[12:8]
-;  IVAF=88.67        auto
-;  IVAI            auto
-;  IVA_MPU         auto
-;  IVA_S         ACTIVATED                  CM_CLKSEL_DSP[13]
-;  GFXF=66.5      (gfx domain)	/8          CM_CLKSEL_FGX[2:0]:
-;  SSI_SSRF=177.3               /3          CM_CLKSEL1_CORE[24:20]
-;  SSI_SSTF=88.67     auto
-;  L3=133Mhz (sdram)            /4          CM_CLKSEL1_CORE[4:0]
-;  L4=66.5Mhz                   /8
-;  C_L4_USB=33.25               /16         CM_CLKSEL1_CORE[6:5]
-***************************************************************************/
-#define III_DPLL_OUT_X2   0x2    /* x2 core out */
-#define III_MPU_DIV       0x2    /* mpu = core/2 */
-#define III_DSP_DIV       0x23C3 /* dsp & iva divider sych enabled*/
-#define III_GFX_DIV       0x2
-#define III_BUS_DIV       0x08301044
-#define III_DPLL_266      0x01885500
-
-/* set defaults for boot up */
-#ifdef PRCM_CONFIG_II
-# define DPLL_OUT         II_DPLL_OUT_X2
-# define MPU_DIV          II_MPU_DIV
-# define DSP_DIV          II_DSP_DIV
-# define GFX_DIV          II_GFX_DIV
-# define BUS_DIV          II_BUS_DIV
-# define DPLL_VAL         II_DPLL_300
-#elif PRCM_CONFIG_III
-# define DPLL_OUT         III_DPLL_OUT_X2
-# define MPU_DIV          III_MPU_DIV
-# define DSP_DIV          III_DSP_DIV
-# define GFX_DIV          III_GFX_DIV
-# define BUS_DIV          III_BUS_DIV
-# define DPLL_VAL         III_DPLL_266
-#endif
-
-/* lock delay time out */
-#define LDELAY           12000000
-
-#endif
diff --git a/arch/arm/include/asm/arch-omap24xx/i2c.h b/arch/arm/include/asm/arch-omap24xx/i2c.h
deleted file mode 100644
index 6f64519..0000000
--- a/arch/arm/include/asm/arch-omap24xx/i2c.h
+++ /dev/null
@@ -1,68 +0,0 @@
-/*
- * (C) Copyright 2004
- * Texas Instruments, <www.ti.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-#ifndef _OMAP24XX_I2C_H_
-#define _OMAP24XX_I2C_H_
-
-#define I2C_BASE1		0x48070000
-#define I2C_BASE2               0x48072000 /* nothing hooked up on h4 */
-
-#define I2C_DEFAULT_BASE	I2C_BASE1
-
-struct i2c {
-	unsigned short rev;	/* 0x00 */
-	unsigned short res1;
-	unsigned short ie;	/* 0x04 */
-	unsigned short res2;
-	unsigned short stat;	/* 0x08 */
-	unsigned short res3;
-	unsigned short iv;	/* 0x0C */
-	unsigned short res4;
-	unsigned short syss;	/* 0x10 */
-	unsigned short res4p1;
-	unsigned short buf;	/* 0x14 */
-	unsigned short res5;
-	unsigned short cnt;	/* 0x18 */
-	unsigned short res6;
-	unsigned short data;	/* 0x1C */
-	unsigned short res7;
-	unsigned short sysc;	/* 0x20 */
-	unsigned short res8;
-	unsigned short con;	/* 0x24 */
-	unsigned short res9;
-	unsigned short oa;	/* 0x28 */
-	unsigned short res10;
-	unsigned short sa;	/* 0x2C */
-	unsigned short res11;
-	unsigned short psc;	/* 0x30 */
-	unsigned short res12;
-	unsigned short scll;	/* 0x34 */
-	unsigned short res13;
-	unsigned short sclh;	/* 0x38 */
-	unsigned short res14;
-	unsigned short systest;	/* 0x3c */
-	unsigned short res15;
-};
-
-#define I2C_BUS_MAX	2
-
-#endif
diff --git a/arch/arm/include/asm/arch-omap24xx/mem.h b/arch/arm/include/asm/arch-omap24xx/mem.h
deleted file mode 100644
index 42e8ab2..0000000
--- a/arch/arm/include/asm/arch-omap24xx/mem.h
+++ /dev/null
@@ -1,156 +0,0 @@
-/*
- * (C) Copyright 2004
- * Texas Instruments, <www.ti.com>
- * Richard Woodruff <r-woodruff2@ti.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef _OMAP24XX_MEM_H_
-#define _OMAP24XX_MEM_H_
-
-#define SDRC_CS0_OSET	 0x0
-#define SDRC_CS1_OSET	 0x30  /* mirror CS1 regs appear offset 0x30 from CS0 */
-
-#ifndef __ASSEMBLY__
-/* struct's for holding data tables for current boards, they are getting used
-   early in init when NO global access are there */
-struct sdrc_data_s {
-	u32    sdrc_sharing;
-	u32    sdrc_mdcfg_0_ddr;
-	u32    sdrc_mdcfg_0_sdr;
-	u32    sdrc_actim_ctrla_0;
-	u32    sdrc_actim_ctrlb_0;
-	u32    sdrc_rfr_ctrl;
-	u32    sdrc_mr_0_ddr;
-	u32    sdrc_mr_0_sdr;
-	u32    sdrc_dllab_ctrl;
-} /*__attribute__ ((packed))*/;
-typedef struct sdrc_data_s sdrc_data_t;
-
-typedef enum {
-	STACKED		= 0,
-	IP_DDR		= 1,
-	COMBO_DDR	= 2,
-	IP_SDR		= 3,
-} mem_t;
-
-#endif
-
-/* Slower full frequency range default timings for x32 operation*/
-#define H4_2420_SDRC_SHARING		0x00000100
-#define H4_2420_SDRC_MDCFG_0_SDR	0x00D04010 /* discrete sdr module */
-#define H4_2420_SDRC_MR_0_SDR		0x00000031
-#define H4_2420_SDRC_MDCFG_0_DDR	0x01702011 /* descrite ddr module */
-#define H4_2420_COMBO_MDCFG_0_DDR	0x00801011 /* combo module */
-#define H4_2420_SDRC_MR_0_DDR		0x00000032
-
-#define H4_2422_SDRC_SHARING		0x00004b00
-#define H4_2422_SDRC_MDCFG_0_DDR	0x00801011 /* stacked ddr on 2422 */
-#define H4_2422_SDRC_MR_0_DDR		0x00000032
-
-/* ES1 work around timings */
-#define H4_242x_SDRC_ACTIM_CTRLA_0_ES1	0x9bead909  /* 165Mhz for use with 100/133 */
-#define H4_242x_SDRC_ACTIM_CTRLB_0_ES1	0x00000020
-#define H4_242x_SDRC_RFR_CTRL_ES1	    0x00002401	/* use over refresh for ES1 */
-
-/* optimized timings good for current shipping parts */
-#define H4_242X_SDRC_ACTIM_CTRLA_0_100MHz  0x5A59B485
-#define H4_242X_SDRC_ACTIM_CTRLB_0_100MHz  0x0000000e
-#define H4_242X_SDRC_ACTIM_CTRLA_0_133MHz  0x8BA6E6C8 /* temp warn 0 settings */
-#define H4_242X_SDRC_ACTIM_CTRLB_0_133MHz  0x00000010 /* temp warn 0 settings */
-#define H4_242X_SDRC_RFR_CTRL_100MHz	   0x0002da01
-#define H4_242X_SDRC_RFR_CTRL_133MHz	   0x0003de01
-#define H4_242x_SDRC_DLLAB_CTRL_100MHz	   0x0000980E /* 72deg, allow DPLLout*1 to work (combo)*/
-#define H4_242x_SDRC_DLLAB_CTRL_133MHz	   0x0000690E /* 72deg, for ES2 */
-
-#ifdef PRCM_CONFIG_II
-# define H4_2420_SDRC_ACTIM_CTRLA_0	H4_242X_SDRC_ACTIM_CTRLA_0_100MHz
-# define H4_2420_SDRC_ACTIM_CTRLB_0	H4_242X_SDRC_ACTIM_CTRLB_0_100MHz
-# define H4_2420_SDRC_RFR_CTRL		H4_242X_SDRC_RFR_CTRL_100MHz
-# define H4_2420_SDRC_DLLAB_CTRL    H4_242x_SDRC_DLLAB_CTRL_100MHz
-# define H4_2422_SDRC_ACTIM_CTRLA_0	H4_242X_SDRC_ACTIM_CTRLA_0_100MHz
-# define H4_2422_SDRC_ACTIM_CTRLB_0	H4_242X_SDRC_ACTIM_CTRLB_0_100MHz
-# define H4_2422_SDRC_RFR_CTRL		H4_242X_SDRC_RFR_CTRL_100MHz
-# define H4_2422_SDRC_DLLAB_CTRL    H4_242x_SDRC_DLLAB_CTRL_100MHz
-#elif PRCM_CONFIG_III
-# define H4_2420_SDRC_ACTIM_CTRLA_0	H4_242X_SDRC_ACTIM_CTRLA_0_133MHz
-# define H4_2420_SDRC_ACTIM_CTRLB_0	H4_242X_SDRC_ACTIM_CTRLB_0_133MHz
-# define H4_2420_SDRC_RFR_CTRL		H4_242X_SDRC_RFR_CTRL_133MHz
-# define H4_2420_SDRC_DLLAB_CTRL    H4_242x_SDRC_DLLAB_CTRL_133MHz
-# define H4_2422_SDRC_ACTIM_CTRLA_0	H4_242X_SDRC_ACTIM_CTRLA_0_100MHz
-# define H4_2422_SDRC_ACTIM_CTRLB_0	H4_242X_SDRC_ACTIM_CTRLB_0_100MHz
-# define H4_2422_SDRC_RFR_CTRL		H4_242X_SDRC_RFR_CTRL_100MHz
-# define H4_2422_SDRC_DLLAB_CTRL    H4_242x_SDRC_DLLAB_CTRL_100MHz
-#endif
-
-
-/* GPMC settings */
-#ifdef PRCM_CONFIG_II	     /* L3 at 100MHz */
-# ifdef CONFIG_SYS_NAND_BOOT
-#  define H4_24XX_GPMC_CONFIG1_0   0x0
-#  define H4_24XX_GPMC_CONFIG2_0   0x00141400
-#  define H4_24XX_GPMC_CONFIG3_0   0x00141400
-#  define H4_24XX_GPMC_CONFIG4_0   0x0F010F01
-#  define H4_24XX_GPMC_CONFIG5_0   0x010C1414
-#  define H4_24XX_GPMC_CONFIG6_0   0x00000A80
-# else	/* else NOR */
-#  define H4_24XX_GPMC_CONFIG1_0   0x3
-#  define H4_24XX_GPMC_CONFIG2_0   0x000f0f01
-#  define H4_24XX_GPMC_CONFIG3_0   0x00050502
-#  define H4_24XX_GPMC_CONFIG4_0   0x0C060C06
-#  define H4_24XX_GPMC_CONFIG5_0   0x01131F1F
-# endif /* endif CONFIG_SYS_NAND_BOOT */
-# define H4_24XX_GPMC_CONFIG7_0	  (0x00000C40|(H4_CS0_BASE >> 24))
-# define H4_24XX_GPMC_CONFIG1_1	  0x00011000
-# define H4_24XX_GPMC_CONFIG2_1	  0x001F1F00
-# define H4_24XX_GPMC_CONFIG3_1	  0x00080802
-# define H4_24XX_GPMC_CONFIG4_1	  0x1C091C09
-# define H4_24XX_GPMC_CONFIG5_1	  0x031A1F1F
-# define H4_24XX_GPMC_CONFIG6_1	  0x000003C2
-# define H4_24XX_GPMC_CONFIG7_1	  (0x00000F40|(H4_CS1_BASE >> 24))
-#endif /* endif PRCM_CONFIG_II */
-
-#ifdef PRCM_CONFIG_III	/* L3 at 133MHz */
-# ifdef CONFIG_SYS_NAND_BOOT
-#  define H4_24XX_GPMC_CONFIG1_0   0x0
-#  define H4_24XX_GPMC_CONFIG2_0   0x00141400
-#  define H4_24XX_GPMC_CONFIG3_0   0x00141400
-#  define H4_24XX_GPMC_CONFIG4_0   0x0F010F01
-#  define H4_24XX_GPMC_CONFIG5_0   0x010C1414
-#  define H4_24XX_GPMC_CONFIG6_0   0x00000A80
-# else	/* NOR boot */
-#  define H4_24XX_GPMC_CONFIG1_0   0x3
-#  define H4_24XX_GPMC_CONFIG2_0   0x00151501
-#  define H4_24XX_GPMC_CONFIG3_0   0x00060602
-#  define H4_24XX_GPMC_CONFIG4_0   0x10081008
-#  define H4_24XX_GPMC_CONFIG5_0   0x01131F1F
-#  define H4_24XX_GPMC_CONFIG6_0   0x000004c4
-# endif /* endif CONFIG_SYS_NAND_BOOT */
-# define H4_24XX_GPMC_CONFIG7_0	  (0x00000C40|(H4_CS0_BASE >> 24))
-# define H4_24XX_GPMC_CONFIG1_1	  0x00011000
-# define H4_24XX_GPMC_CONFIG2_1	  0x001f1f01
-# define H4_24XX_GPMC_CONFIG3_1	  0x00080803
-# define H4_24XX_GPMC_CONFIG4_1	  0x1C091C09
-# define H4_24XX_GPMC_CONFIG5_1	  0x041f1F1F
-# define H4_24XX_GPMC_CONFIG6_1	  0x000004C4
-# define H4_24XX_GPMC_CONFIG7_1	  (0x00000F40|(H4_CS1_BASE >> 24))
-#endif /* endif CONFIG_SYS_PRCM_III */
-
-#endif /* endif _OMAP24XX_MEM_H_ */
diff --git a/arch/arm/include/asm/arch-omap24xx/mux.h b/arch/arm/include/asm/arch-omap24xx/mux.h
deleted file mode 100644
index 4fdb9c6..0000000
--- a/arch/arm/include/asm/arch-omap24xx/mux.h
+++ /dev/null
@@ -1,176 +0,0 @@
-/*
- * (C) Copyright 2004
- * Texas Instruments, <www.ti.com>
- * Richard Woodruff <r-woodruff2@ti.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-#ifndef _OMAP2420_MUX_H_
-#define _OMAP2420_MUX_H_
-
-#ifndef __ASSEMBLY__
-typedef  unsigned char uint8;
-typedef  unsigned int uint32;
-
-void muxSetupSDRC(void);
-void muxSetupGPMC(void);
-void muxSetupUsb0(void);
-void muxSetupUsbHost(void);
-void muxSetupUart3(void);
-void muxSetupI2C1(void);
-void muxSetupUART1(void);
-void muxSetupLCD(void);
-void muxSetupCamera(void);
-void muxSetupMMCSD(void) ;
-void muxSetupTouchScreen(void) ;
-void muxSetupHDQ(void);
-#endif
-
-#define USB_OTG_CTRL			        ((volatile uint32 *)0x4805E30C)
-
-/* Pin Muxing registers used for HDQ (Smart battery) */
-#define CONTROL_PADCONF_HDQ_SIO         ((volatile unsigned char *)0x48000115)
-
-/* Pin Muxing registers used for GPMC */
-#define CONTROL_PADCONF_GPMC_D2_BYTE0	((volatile unsigned char *)0x48000088)
-#define CONTROL_PADCONF_GPMC_D2_BYTE1	((volatile unsigned char *)0x48000089)
-#define CONTROL_PADCONF_GPMC_D2_BYTE2	((volatile unsigned char *)0x4800008A)
-#define CONTROL_PADCONF_GPMC_D2_BYTE3	((volatile unsigned char *)0x4800008B)
-
-#define CONTROL_PADCONF_GPMC_NCS0_BYTE0	((volatile unsigned char *)0x4800008C)
-#define CONTROL_PADCONF_GPMC_NCS0_BYTE1	((volatile unsigned char *)0x4800008D)
-#define CONTROL_PADCONF_GPMC_NCS0_BYTE2	((volatile unsigned char *)0x4800008E)
-#define CONTROL_PADCONF_GPMC_NCS0_BYTE3	((volatile unsigned char *)0x4800008F)
-#define CONTROL_PADCONF_GPMC_NCS0_BYTE4	(0x48000090)
-#define CONTROL_PADCONF_GPMC_NCS0_BYTE5	(0x48000091)
-#define CONTROL_PADCONF_GPMC_NCS0_BYTE6	(0x48000092)
-#define CONTROL_PADCONF_GPMC_NCS0_BYTE7	(0x48000093)
-
-/* Pin Muxing registers used for SDRC */
-#define CONTROL_PADCONF_SDRC_NCS0_BYTE0 ((volatile unsigned char *)0x480000A0)
-#define CONTROL_PADCONF_SDRC_NCS0_BYTE1 ((volatile unsigned char *)0x480000A1)
-#define CONTROL_PADCONF_SDRC_NCS0_BYTE2 ((volatile unsigned char *)0x480000A2)
-#define CONTROL_PADCONF_SDRC_NCS0_BYTE3 ((volatile unsigned char *)0x480000A3)
-
-#define CONTROL_PADCONF_SDRC_A14_BYTE0	((volatile unsigned char *)0x48000030)
-#define CONTROL_PADCONF_SDRC_A14_BYTE1	((volatile unsigned char *)0x48000031)
-#define CONTROL_PADCONF_SDRC_A14_BYTE2	((volatile unsigned char *)0x48000032)
-#define CONTROL_PADCONF_SDRC_A14_BYTE3	((volatile unsigned char *)0x48000033)
-
-/* Pin Muxing registers used for Touch Screen (SPI) */
-#define CONTROL_PADCONF_SPI1_CLK        ((volatile unsigned char *)0x480000FF)
-#define CONTROL_PADCONF_SPI1_SIMO       ((volatile unsigned char *)0x48000100)
-#define CONTROL_PADCONF_SPI1_SOMI       ((volatile unsigned char *)0x48000101)
-#define CONTROL_PADCONF_SPI1_NCS0       ((volatile unsigned char *)0x48000102)
-#define CONTROL_PADCONF_SPI1_NCS1       (0x48000103)
-
-#define CONTROL_PADCONF_MCBSP1_FSR      ((volatile unsigned char *)0x4800010B)
-
-/* Pin Muxing registers used for MMCSD */
-#define CONTROL_PADCONF_MMC_CLKI        ((volatile unsigned char *)0x480000FE)
-#define CONTROL_PADCONF_MMC_CLKO        ((volatile unsigned char *)0x480000F3)
-#define CONTROL_PADCONF_MMC_CMD         ((volatile unsigned char *)0x480000F4)
-#define CONTROL_PADCONF_MMC_DAT0        ((volatile unsigned char *)0x480000F5)
-#define CONTROL_PADCONF_MMC_DAT1        ((volatile unsigned char *)0x480000F6)
-#define CONTROL_PADCONF_MMC_DAT2        ((volatile unsigned char *)0x480000F7)
-#define CONTROL_PADCONF_MMC_DAT3        ((volatile unsigned char *)0x480000F8)
-#define CONTROL_PADCONF_MMC_DAT_DIR0    ((volatile unsigned char *)0x480000F9)
-#define CONTROL_PADCONF_MMC_DAT_DIR1    ((volatile unsigned char *)0x480000FA)
-#define CONTROL_PADCONF_MMC_DAT_DIR2    ((volatile unsigned char *)0x480000FB)
-#define CONTROL_PADCONF_MMC_DAT_DIR3    ((volatile unsigned char *)0x480000FC)
-#define CONTROL_PADCONF_MMC_CMD_DIR     ((volatile unsigned char *)0x480000FD)
-
-#define CONTROL_PADCONF_SDRC_A14        ((volatile unsigned char *)0x48000030)
-#define CONTROL_PADCONF_SDRC_A13        ((volatile unsigned char *)0x48000031)
-
-/* Pin Muxing registers used for CAMERA */
-#define CONTROL_PADCONF_SYS_NRESWARM    ((volatile unsigned char *)0x4800012B)
-
-#define CONTROL_PADCONF_CAM_XCLK        ((volatile unsigned char *)0x480000DC)
-#define CONTROL_PADCONF_CAM_LCLK        ((volatile unsigned char *)0x480000DB)
-#define CONTROL_PADCONF_CAM_VS          ((volatile unsigned char *)0x480000DA)
-#define CONTROL_PADCONF_CAM_HS          ((volatile unsigned char *)0x480000D9)
-#define CONTROL_PADCONF_CAM_D0          ((volatile unsigned char *)0x480000D8)
-#define CONTROL_PADCONF_CAM_D1          ((volatile unsigned char *)0x480000D7)
-#define CONTROL_PADCONF_CAM_D2          ((volatile unsigned char *)0x480000D6)
-#define CONTROL_PADCONF_CAM_D3          ((volatile unsigned char *)0x480000D5)
-#define CONTROL_PADCONF_CAM_D4          ((volatile unsigned char *)0x480000D4)
-#define CONTROL_PADCONF_CAM_D5          ((volatile unsigned char *)0x480000D3)
-#define CONTROL_PADCONF_CAM_D6          ((volatile unsigned char *)0x480000D2)
-#define CONTROL_PADCONF_CAM_D7          ((volatile unsigned char *)0x480000D1)
-#define CONTROL_PADCONF_CAM_D8          ((volatile unsigned char *)0x480000D0)
-#define CONTROL_PADCONF_CAM_D9          ((volatile unsigned char *)0x480000CF)
-
-/* Pin Muxing registers used for LCD */
-#define CONTROL_PADCONF_DSS_D0          ((volatile unsigned char *)0x480000B3)
-#define CONTROL_PADCONF_DSS_D1          ((volatile unsigned char *)0x480000B4)
-#define CONTROL_PADCONF_DSS_D2          ((volatile unsigned char *)0x480000B5)
-#define CONTROL_PADCONF_DSS_D3          ((volatile unsigned char *)0x480000B6)
-#define CONTROL_PADCONF_DSS_D4          ((volatile unsigned char *)0x480000B7)
-#define CONTROL_PADCONF_DSS_D5          ((volatile unsigned char *)0x480000B8)
-#define CONTROL_PADCONF_DSS_D6          ((volatile unsigned char *)0x480000B9)
-#define CONTROL_PADCONF_DSS_D7          ((volatile unsigned char *)0x480000BA)
-#define CONTROL_PADCONF_DSS_D8          ((volatile unsigned char *)0x480000BB)
-#define CONTROL_PADCONF_DSS_D9          ((volatile unsigned char *)0x480000BC)
-#define CONTROL_PADCONF_DSS_D10         ((volatile unsigned char *)0x480000BD)
-#define CONTROL_PADCONF_DSS_D11         ((volatile unsigned char *)0x480000BE)
-#define CONTROL_PADCONF_DSS_D12         ((volatile unsigned char *)0x480000BF)
-#define CONTROL_PADCONF_DSS_D13         ((volatile unsigned char *)0x480000C0)
-#define CONTROL_PADCONF_DSS_D14         ((volatile unsigned char *)0x480000C1)
-#define CONTROL_PADCONF_DSS_D15         ((volatile unsigned char *)0x480000C2)
-#define CONTROL_PADCONF_DSS_D16         ((volatile unsigned char *)0x480000C3)
-#define CONTROL_PADCONF_DSS_D17         ((volatile unsigned char *)0x480000C4)
-#define CONTROL_PADCONF_DSS_PCLK        ((volatile unsigned char *)0x480000CB)
-#define CONTROL_PADCONF_DSS_VSYNC       ((volatile unsigned char *)0x480000CC)
-#define CONTROL_PADCONF_DSS_HSYNC       ((volatile unsigned char *)0x480000CD)
-#define CONTROL_PADCONF_DSS_ACBIAS      ((volatile unsigned char *)0x480000CE)
-
-/* Pin Muxing registers used for UART1 */
-#define CONTROL_PADCONF_UART1_CTS       ((volatile unsigned char *)0x480000C5)
-#define CONTROL_PADCONF_UART1_RTS       ((volatile unsigned char *)0x480000C6)
-#define CONTROL_PADCONF_UART1_TX        ((volatile unsigned char *)0x480000C7)
-#define CONTROL_PADCONF_UART1_RX        ((volatile unsigned char *)0x480000C8)
-
-/* Pin Muxing registers used for I2C1 */
-#define CONTROL_PADCONF_I2C1_SCL        ((volatile unsigned char *)0x48000111)
-#define CONTROL_PADCONF_I2C1_SDA        ((volatile unsigned char *)0x48000112)
-
-/* Pin Muxing registres used for USB0. */
-#define CONTROL_PADCONF_USB0_PUEN		((volatile uint8 *)0x4800011D)
-#define CONTROL_PADCONF_USB0_VP			((volatile uint8 *)0x4800011E)
-#define CONTROL_PADCONF_USB0_VM			((volatile uint8 *)0x4800011F)
-#define CONTROL_PADCONF_USB0_RCV		((volatile uint8 *)0x48000120)
-#define CONTROL_PADCONF_USB0_TXEN		((volatile uint8 *)0x48000121)
-#define CONTROL_PADCONF_USB0_SE0		((volatile uint8 *)0x48000122)
-#define CONTROL_PADCONF_USB0_DAT		((volatile uint8 *)0x48000123)
-
-/* Pin Muxing registres used for USB1. */
-#define CONTROL_PADCONF_USB1_RCV	(0x480000EB)
-#define CONTROL_PADCONF_USB1_TXEN	(0x480000EC)
-
-/* Pin Muxing registers used for UART3/IRDA */
-#define CONTROL_PADCONF_UART3_TX_IRTX	((volatile uint8 *)0x48000118)
-#define CONTROL_PADCONF_UART3_RX_IRRX	((volatile uint8 *)0x48000119)
-
-/* Pin Muxing registers used for GPIO */
-#define CONTROL_PADCONF_GPIO69		(0x480000ED)
-#define CONTROL_PADCONF_GPIO70		(0x480000EE)
-#define CONTROL_PADCONF_GPIO102		(0x48000116)
-#define CONTROL_PADCONF_GPIO103		(0x48000117)
-#define CONTROL_PADCONF_GPIO104		(0x48000118)
-#define CONTROL_PADCONF_GPIO105		(0x48000119)
-
-#endif
diff --git a/arch/arm/include/asm/arch-omap24xx/omap2420.h b/arch/arm/include/asm/arch-omap24xx/omap2420.h
deleted file mode 100644
index 6032419..0000000
--- a/arch/arm/include/asm/arch-omap24xx/omap2420.h
+++ /dev/null
@@ -1,246 +0,0 @@
-/*
- * (C) Copyright 2004
- * Texas Instruments, <www.ti.com>
- * Richard Woodruff <r-woodruff2@ti.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef _OMAP2420_SYS_H_
-#define _OMAP2420_SYS_H_
-
-#include <asm/sizes.h>
-
-/*
- * 2420 specific Section
- */
-
-/* L3 Firewall */
-#define A_REQINFOPERM0        0x68005048
-#define A_READPERM0           0x68005050
-#define A_WRITEPERM0          0x68005058
-/* #define GP_DEVICE	(BIT8|BIT9)  FIXME -- commented out to make compile -- FIXME */
-
-/* L3 Firewall */
-#define A_REQINFOPERM0        0x68005048
-#define A_READPERM0           0x68005050
-#define A_WRITEPERM0          0x68005058
-
-/* CONTROL */
-#define OMAP2420_CTRL_BASE    (0x48000000)
-#define CONTROL_STATUS        (OMAP2420_CTRL_BASE + 0x2F8)
-
-/* device type */
-#define TST_DEVICE	0x0
-#define EMU_DEVICE	0x1
-#define HS_DEVICE	0x2
-#define GP_DEVICE	0x3
-
-/* TAP information */
-#define OMAP2420_TAP_BASE     (0x48014000)
-#define TAP_IDCODE_REG        (OMAP2420_TAP_BASE+0x204)
-#define PRODUCTION_ID         (OMAP2420_TAP_BASE+0x208)
-
-/* GPMC */
-#define OMAP2420_GPMC_BASE    (0x6800A000)
-#define GPMC_SYSCONFIG        (OMAP2420_GPMC_BASE+0x10)
-#define GPMC_IRQENABLE        (OMAP2420_GPMC_BASE+0x1C)
-#define GPMC_TIMEOUT_CONTROL  (OMAP2420_GPMC_BASE+0x40)
-#define GPMC_CONFIG           (OMAP2420_GPMC_BASE+0x50)
-#define GPMC_CONFIG1_0        (OMAP2420_GPMC_BASE+0x60)
-#define GPMC_CONFIG2_0        (OMAP2420_GPMC_BASE+0x64)
-#define GPMC_CONFIG3_0        (OMAP2420_GPMC_BASE+0x68)
-#define GPMC_CONFIG4_0        (OMAP2420_GPMC_BASE+0x6C)
-#define GPMC_CONFIG5_0        (OMAP2420_GPMC_BASE+0x70)
-#define GPMC_CONFIG6_0        (OMAP2420_GPMC_BASE+0x74)
-#define GPMC_CONFIG7_0	      (OMAP2420_GPMC_BASE+0x78)
-#define GPMC_CONFIG1_1        (OMAP2420_GPMC_BASE+0x90)
-#define GPMC_CONFIG2_1        (OMAP2420_GPMC_BASE+0x94)
-#define GPMC_CONFIG3_1        (OMAP2420_GPMC_BASE+0x98)
-#define GPMC_CONFIG4_1        (OMAP2420_GPMC_BASE+0x9C)
-#define GPMC_CONFIG5_1        (OMAP2420_GPMC_BASE+0xA0)
-#define GPMC_CONFIG6_1        (OMAP2420_GPMC_BASE+0xA4)
-#define GPMC_CONFIG7_1	      (OMAP2420_GPMC_BASE+0xA8)
-#define GPMC_CONFIG1_2        (OMAP2420_GPMC_BASE+0xC0)
-#define GPMC_CONFIG2_2        (OMAP2420_GPMC_BASE+0xC4)
-#define GPMC_CONFIG3_2        (OMAP2420_GPMC_BASE+0xC8)
-#define GPMC_CONFIG4_2        (OMAP2420_GPMC_BASE+0xCC)
-#define GPMC_CONFIG5_2        (OMAP2420_GPMC_BASE+0xD0)
-#define GPMC_CONFIG6_2        (OMAP2420_GPMC_BASE+0xD4)
-#define GPMC_CONFIG7_2        (OMAP2420_GPMC_BASE+0xD8)
-#define GPMC_CONFIG1_3        (OMAP2420_GPMC_BASE+0xF0)
-#define GPMC_CONFIG2_3        (OMAP2420_GPMC_BASE+0xF4)
-#define GPMC_CONFIG3_3        (OMAP2420_GPMC_BASE+0xF8)
-#define GPMC_CONFIG4_3        (OMAP2420_GPMC_BASE+0xFC)
-#define GPMC_CONFIG5_3        (OMAP2420_GPMC_BASE+0x100)
-#define GPMC_CONFIG6_3        (OMAP2420_GPMC_BASE+0x104)
-#define GPMC_CONFIG7_3	      (OMAP2420_GPMC_BASE+0x108)
-
-/* SMS */
-#define OMAP2420_SMS_BASE 0x68008000
-#define SMS_SYSCONFIG     (OMAP2420_SMS_BASE+0x10)
-#define SMS_CLASS_ARB0    (OMAP2420_SMS_BASE+0xD0)
-# define BURSTCOMPLETE_GROUP7    BIT31
-
-/* SDRC */
-#define OMAP2420_SDRC_BASE 0x68009000
-#define SDRC_SYSCONFIG     (OMAP2420_SDRC_BASE+0x10)
-#define SDRC_STATUS        (OMAP2420_SDRC_BASE+0x14)
-#define SDRC_CS_CFG        (OMAP2420_SDRC_BASE+0x40)
-#define SDRC_SHARING       (OMAP2420_SDRC_BASE+0x44)
-#define SDRC_DLLA_CTRL     (OMAP2420_SDRC_BASE+0x60)
-#define SDRC_DLLB_CTRL     (OMAP2420_SDRC_BASE+0x68)
-#define SDRC_POWER         (OMAP2420_SDRC_BASE+0x70)
-#define SDRC_MCFG_0        (OMAP2420_SDRC_BASE+0x80)
-#define SDRC_MR_0          (OMAP2420_SDRC_BASE+0x84)
-#define SDRC_ACTIM_CTRLA_0 (OMAP2420_SDRC_BASE+0x9C)
-#define SDRC_ACTIM_CTRLB_0 (OMAP2420_SDRC_BASE+0xA0)
-#define SDRC_ACTIM_CTRLA_1 (OMAP2420_SDRC_BASE+0xC4)
-#define SDRC_ACTIM_CTRLB_1 (OMAP2420_SDRC_BASE+0xC8)
-#define SDRC_RFR_CTRL      (OMAP2420_SDRC_BASE+0xA4)
-#define SDRC_MANUAL_0      (OMAP2420_SDRC_BASE+0xA8)
-#define OMAP2420_SDRC_CS0  0x80000000
-#define OMAP2420_SDRC_CS1  0xA0000000
-#define CMD_NOP            0x0
-#define CMD_PRECHARGE      0x1
-#define CMD_AUTOREFRESH    0x2
-#define CMD_ENTR_PWRDOWN   0x3
-#define CMD_EXIT_PWRDOWN   0x4
-#define CMD_ENTR_SRFRSH    0x5
-#define CMD_CKE_HIGH       0x6
-#define CMD_CKE_LOW        0x7
-#define SOFTRESET          BIT1
-#define SMART_IDLE         (0x2 << 3)
-#define REF_ON_IDLE        (0x1 << 6)
-
-
-/* UART */
-#define OMAP2420_UART1	      0x4806A000
-#define OMAP2420_UART2	      0x4806C000
-#define OMAP2420_UART3        0x4806E000
-
-/* General Purpose Timers */
-#define OMAP2420_GPT1         0x48028000
-#define OMAP2420_GPT2         0x4802A000
-#define OMAP2420_GPT3         0x48078000
-#define OMAP2420_GPT4         0x4807A000
-#define OMAP2420_GPT5         0x4807C000
-#define OMAP2420_GPT6         0x4807E000
-#define OMAP2420_GPT7         0x48080000
-#define OMAP2420_GPT8         0x48082000
-#define OMAP2420_GPT9         0x48084000
-#define OMAP2420_GPT10        0x48086000
-#define OMAP2420_GPT11        0x48088000
-#define OMAP2420_GPT12        0x4808A000
-
-/* timer regs offsets (32 bit regs) */
-#define TIDR       0x0      /* r */
-#define TIOCP_CFG  0x10     /* rw */
-#define TISTAT     0x14     /* r */
-#define TISR       0x18     /* rw */
-#define TIER       0x1C     /* rw */
-#define TWER       0x20     /* rw */
-#define TCLR       0x24     /* rw */
-#define TCRR       0x28     /* rw */
-#define TLDR       0x2C     /* rw */
-#define TTGR       0x30     /* rw */
-#define TWPS       0x34     /* r */
-#define TMAR       0x38     /* rw */
-#define TCAR1      0x3c     /* r */
-#define TSICR      0x40     /* rw */
-#define TCAR2      0x44     /* r */
-
-/* WatchDog Timers (1 secure, 3 GP) */
-#define WD1_BASE              0x48020000
-#define WD2_BASE              0x48022000
-#define WD3_BASE              0x48024000
-#define WD4_BASE              0x48026000
-#define WWPS       0x34     /* r */
-#define WSPR       0x48     /* rw */
-#define WD_UNLOCK1 0xAAAA
-#define WD_UNLOCK2 0x5555
-
-/* PRCM */
-#define OMAP2420_CM_BASE 0x48008000
-#define PRCM_CLKCFG_CTRL (OMAP2420_CM_BASE+0x080)
-#define CM_CLKSEL_MPU    (OMAP2420_CM_BASE+0x140)
-#define CM_FCLKEN1_CORE  (OMAP2420_CM_BASE+0x200)
-#define CM_FCLKEN2_CORE  (OMAP2420_CM_BASE+0x204)
-#define CM_ICLKEN1_CORE  (OMAP2420_CM_BASE+0x210)
-#define CM_ICLKEN2_CORE  (OMAP2420_CM_BASE+0x214)
-#define CM_CLKSEL1_CORE  (OMAP2420_CM_BASE+0x240)
-#define CM_CLKSEL_WKUP   (OMAP2420_CM_BASE+0x440)
-#define CM_CLKSEL2_CORE  (OMAP2420_CM_BASE+0x244)
-#define CM_CLKSEL_GFX    (OMAP2420_CM_BASE+0x340)
-#define PM_RSTCTRL_WKUP  (OMAP2420_CM_BASE+0x450)
-#define CM_CLKEN_PLL     (OMAP2420_CM_BASE+0x500)
-#define CM_IDLEST_CKGEN  (OMAP2420_CM_BASE+0x520)
-#define CM_CLKSEL1_PLL   (OMAP2420_CM_BASE+0x540)
-#define CM_CLKSEL2_PLL   (OMAP2420_CM_BASE+0x544)
-#define CM_CLKSEL_DSP    (OMAP2420_CM_BASE+0x840)
-
-/*
- * H4 specific Section
- */
-
-/*
- *  The 2420's chip selects are programmable.  The mask ROM
- *  does configure CS0 to 0x08000000 before dispatch.  So, if
- *  you want your code to live below that address, you have to
- *  be prepared to jump though hoops, to reset the base address.
- */
-#if defined(CONFIG_OMAP2420H4)
-/* GPMC */
-#ifdef CONFIG_VIRTIO_A        /* Pre version B */
-# define H4_CS0_BASE           0x08000000  /* flash (64 Meg aligned) */
-# define H4_CS1_BASE           0x04000000  /* debug board */
-# define H4_CS2_BASE           0x0A000000  /* wifi board */
-#else
-# define H4_CS0_BASE           0x04000000  /* flash (64 Meg aligned) */
-# define H4_CS1_BASE           0x08000000  /* debug board */
-# define H4_CS2_BASE           0x0A000000  /* wifi board */
-#endif
-
-/* base address for indirect vectors (internal boot mode) */
-#define SRAM_OFFSET0          0x40000000
-#define SRAM_OFFSET1          0x00200000
-#define SRAM_OFFSET2          0x0000F800
-#define SRAM_VECT_CODE       (SRAM_OFFSET0|SRAM_OFFSET1|SRAM_OFFSET2)
-
-/* FPGA on Debug board.*/
-#define ETH_CONTROL_REG       (H4_CS1_BASE+0x30b)
-#define LAN_RESET_REGISTER    (H4_CS1_BASE+0x1c)
-#endif  /* endif CONFIG_2420H4 */
-
-#if defined(CONFIG_APOLLON)
-#define APOLLON_CS0_BASE	0x00000000	/* OneNAND */
-#define APOLLON_CS1_BASE	0x08000000	/* ethernet */
-#define APOLLON_CS2_BASE	0x10000000	/* OneNAND */
-#define APOLLON_CS3_BASE	0x18000000	/* NOR */
-
-#define ETH_CONTROL_REG		(APOLLON_CS1_BASE + 0x30b)
-#define LAN_RESET_REGISTER	(APOLLON_CS1_BASE + 0x1c)
-#endif	/* endif CONFIG_APOLLON */
-
-/* Common */
-#define LOW_LEVEL_SRAM_STACK  0x4020FFFC
-
-#define PERIFERAL_PORT_BASE   0x480FE003
-
-#endif
diff --git a/arch/arm/include/asm/arch-omap24xx/sys_info.h b/arch/arm/include/asm/arch-omap24xx/sys_info.h
deleted file mode 100644
index 53c231a..0000000
--- a/arch/arm/include/asm/arch-omap24xx/sys_info.h
+++ /dev/null
@@ -1,82 +0,0 @@
-/*
- * (C) Copyright 2004
- * Texas Instruments, <www.ti.com>
- * Richard Woodruff <r-woodruff2@ti.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef _OMAP24XX_SYS_INFO_H_
-#define _OMAP24XX_SYS_INFO_H_
-
-typedef struct  h4_system_data {
-	/* base board info */
-	u32 base_b_rev;		/* rev from base board i2c */
-	/* cpu board info */
-	u32 cpu_b_rev;		/* rev from cpu board i2c */
-	u32 cpu_b_mux;		/* mux type on daughter board */
-	u32 cpu_b_ddr_type;	/* mem type */
-	u32 cpu_b_ddr_speed;	/* ddr speed rating */
-	u32 cpu_b_switches;	/* boot ctrl switch settings */
-	/* cpu info */
-	u32 cpu_type;		/* type of cpu; 2420, 2422, 2430,...*/
-	u32 cpu_rev;		/* rev of given cpu; ES1, ES2,...*/
-} h4_sys_data;
-
-#define XDR_POP           5      /* package on package part */
-#define SDR_DISCRETE      4      /* 128M memory SDR module*/
-#define DDR_STACKED       3      /* stacked part on 2422 */
-#define DDR_COMBO         2      /* combo part on cpu daughter card (menalaeus) */
-#define DDR_DISCRETE      1      /* 2x16 parts on daughter card */
-
-#define DDR_100           100    /* type found on most mem d-boards */
-#define DDR_111           111    /* some combo parts */
-#define DDR_133           133    /* most combo, some mem d-boards */
-#define DDR_165           165    /* future parts */
-
-#define CPU_2420          0x2420
-#define CPU_2422          0x2422 /* 2420 + 64M stacked */
-#define CPU_2423          0x2423 /* 2420 + 96M stacked */
-
-#define CPU_2422_ES1      1
-#define CPU_2422_ES2      2
-#define CPU_2420_ES1      1
-#define CPU_2420_ES2      2
-#define CPU_2420_2422_ES1 1
-
-#define CPU_2420_CHIPID   0x0B5D9000
-#define CPU_24XX_ID_MASK  0x0FFFF000
-#define CPU_242X_REV_MASK 0xF0000000
-#define CPU_242X_PID_MASK 0x000F0000
-
-#define BOARD_H4_MENELAUS 1
-#define BOARD_H4_SDP      2
-
-#define GPMC_MUXED        1
-#define GPMC_NONMUXED     0
-
-#define TYPE_NAND         0x800   /* bit pos for nand in gpmc reg */
-#define TYPE_NOR          0x000
-
-#define WIDTH_8BIT        0x0000
-#define WIDTH_16BIT       0x1000  /* bit pos for 16 bit in gpmc */
-
-#define I2C_MENELAUS 0x72	/* i2c id for companion chip */
-
-#endif
diff --git a/arch/arm/include/asm/arch-omap24xx/sys_proto.h b/arch/arm/include/asm/arch-omap24xx/sys_proto.h
deleted file mode 100644
index 9d8e5b2..0000000
--- a/arch/arm/include/asm/arch-omap24xx/sys_proto.h
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * (C) Copyright 2004
- * Texas Instruments, <www.ti.com>
- * Richard Woodruff <r-woodruff2@ti.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
-  */
-#ifndef _OMAP24XX_SYS_PROTO_H_
-#define _OMAP24XX_SYS_PROTO_H_
-
-void prcm_init(void);
-void memif_init(void);
-void sdrc_init(void);
-void do_sdrc_init(u32,u32);
-void gpmc_init(void);
-
-void ether_init(void);
-void watchdog_init(void);
-void set_muxconf_regs(void);
-void peripheral_enable(void);
-
-u32 get_cpu_type(void);
-u32 get_cpu_rev(void);
-u32 get_mem_type(void);
-u32 get_sysboot_value(void);
-u32 get_gpmc0_base(void);
-u32 is_gpmc_muxed(void);
-u32 get_gpmc0_type(void);
-u32 get_gpmc0_width(void);
-u32 wait_on_value(u32 read_bit_mask, u32 match_value, u32 read_addr, u32 bound);
-u32 get_board_type(void);
-void display_board_info(u32);
-void update_mux(u32,u32);
-u32 get_sdr_cs_size(u32 offset);
-
-u32 running_in_sdram(void);
-u32 running_in_sram(void);
-u32 running_in_flash(void);
-u32 running_from_internal_boot(void);
-u32 get_device_type(void);
-#endif
diff --git a/arch/arm/include/asm/arch-omap3/am35x_def.h b/arch/arm/include/asm/arch-omap3/am35x_def.h
deleted file mode 100644
index 81942a8..0000000
--- a/arch/arm/include/asm/arch-omap3/am35x_def.h
+++ /dev/null
@@ -1,52 +0,0 @@
-/*
- * am35x_def.h - TI's AM35x specific definitions.
- *
- * Based on arch/arm/include/asm/arch-omap3/cpu.h
- *
- * Author: Ajay Kumar Gupta <ajay.gupta@ti.com>
- *
- * Copyright (c) 2010 Texas Instruments Incorporated
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#ifndef _AM35X_DEF_H_
-#define _AM35X_DEF_H_
-
-#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
-#include <asm/types.h>
-#endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */
-
-#ifndef __KERNEL_STRICT_NAMES
-#ifndef __ASSEMBLY__
-
-/* General register mappings of system control module */
-#define AM35X_SCM_GEN_BASE	0x48002270
-struct am35x_scm_general {
-	u32 res1[0xC4];		/* 0x000 - 0x30C */
-	u32 devconf2;		/* 0x310 */
-	u32 devconf3;		/* 0x314 */
-	u32 res2[0x2];		/* 0x318 - 0x31C */
-	u32 cba_priority;	/* 0x320 */
-	u32 lvl_intr_clr;	/* 0x324 */
-	u32 ip_sw_reset;	/* 0x328 */
-	u32 ipss_clk_ctrl;	/* 0x32C */
-};
-#define am35x_scm_general_regs ((struct am35x_scm_general *)AM35X_SCM_GEN_BASE)
-
-#endif /*__ASSEMBLY__ */
-#endif /* __KERNEL_STRICT_NAMES */
-
-#endif /* _AM35X_DEF_H_ */
diff --git a/arch/arm/include/asm/arch-omap3/clocks.h b/arch/arm/include/asm/arch-omap3/clocks.h
deleted file mode 100644
index 40f80ba..0000000
--- a/arch/arm/include/asm/arch-omap3/clocks.h
+++ /dev/null
@@ -1,79 +0,0 @@
-/*
- * (C) Copyright 2006-2008
- * Texas Instruments, <www.ti.com>
- * Richard Woodruff <r-woodruff2@ti.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-#ifndef _CLOCKS_H_
-#define _CLOCKS_H_
-
-#define LDELAY		12000000
-
-#define S12M		12000000
-#define S13M		13000000
-#define S19_2M		19200000
-#define S24M		24000000
-#define S26M		26000000
-#define S38_4M		38400000
-
-#define FCK_IVA2_ON	0x00000001
-#define FCK_CORE1_ON	0x03fffe29
-#define ICK_CORE1_ON	0x3ffffffb
-#define ICK_CORE2_ON	0x0000001f
-#define FCK_WKUP_ON	0x000000e9
-#define ICK_WKUP_ON	0x0000003f
-#define FCK_DSS_ON	0x00000005
-#define ICK_DSS_ON	0x00000001
-#define FCK_CAM_ON	0x00000001
-#define ICK_CAM_ON	0x00000001
-#define FCK_PER_ON	0x0003ffff
-#define ICK_PER_ON	0x0003ffff
-
-/* Used to index into DPLL parameter tables */
-typedef struct {
-	unsigned int m;
-	unsigned int n;
-	unsigned int fsel;
-	unsigned int m2;
-} dpll_param;
-
-struct dpll_per_36x_param {
-	unsigned int sys_clk;
-	unsigned int m;
-	unsigned int n;
-	unsigned int m2;
-	unsigned int m3;
-	unsigned int m4;
-	unsigned int m5;
-	unsigned int m6;
-	unsigned int m2div;
-};
-
-/* Following functions are exported from lowlevel_init.S */
-extern dpll_param *get_mpu_dpll_param(void);
-extern dpll_param *get_iva_dpll_param(void);
-extern dpll_param *get_core_dpll_param(void);
-extern dpll_param *get_per_dpll_param(void);
-
-extern dpll_param *get_36x_mpu_dpll_param(void);
-extern dpll_param *get_36x_iva_dpll_param(void);
-extern dpll_param *get_36x_core_dpll_param(void);
-extern dpll_param *get_36x_per_dpll_param(void);
-
-extern void *_end_vect, *_start;
-
-#endif
diff --git a/arch/arm/include/asm/arch-omap3/clocks_omap3.h b/arch/arm/include/asm/arch-omap3/clocks_omap3.h
deleted file mode 100644
index 30ef690..0000000
--- a/arch/arm/include/asm/arch-omap3/clocks_omap3.h
+++ /dev/null
@@ -1,312 +0,0 @@
-/*
- * (C) Copyright 2006-2008
- * Texas Instruments, <www.ti.com>
- * Richard Woodruff <r-woodruff2@ti.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-#ifndef _CLOCKS_OMAP3_H_
-#define _CLOCKS_OMAP3_H_
-
-#define PLL_STOP		1	/* PER & IVA */
-#define PLL_LOW_POWER_BYPASS	5	/* MPU, IVA & CORE */
-#define PLL_FAST_RELOCK_BYPASS	6	/* CORE */
-#define PLL_LOCK		7	/* MPU, IVA, CORE & PER */
-
-/*
- * The following configurations are OPP and SysClk value independant
- * and hence are defined here. All the other DPLL related values are
- * tabulated in lowlevel_init.S.
- */
-
-/* CORE DPLL */
-#define CORE_M3X2	2	/* 332MHz : CM_CLKSEL1_EMU */
-#define CORE_SSI_DIV	3	/* 221MHz : CM_CLKSEL_CORE */
-#define CORE_FUSB_DIV	2	/* 41.5MHz: */
-#define CORE_L4_DIV	2	/* 83MHz  : L4 */
-#define CORE_L3_DIV	2	/* 166MHz : L3 {DDR} */
-#define GFX_DIV		2	/* 83MHz  : CM_CLKSEL_GFX */
-#define WKUP_RSM	2	/* 41.5MHz: CM_CLKSEL_WKUP */
-
-/* PER DPLL */
-#define PER_M6X2	3	/* 288MHz: CM_CLKSEL1_EMU */
-#define PER_M5X2	4	/* 216MHz: CM_CLKSEL_CAM */
-#define PER_M4X2	2	/* 432MHz: CM_CLKSEL_DSS-dss1 */
-#define PER_M3X2	16	/* 54MHz : CM_CLKSEL_DSS-tv */
-
-#define CLSEL1_EMU_VAL ((CORE_M3X2 << 16) | (PER_M6X2 << 24) | (0x0A50))
-
-/* MPU DPLL */
-
-#define MPU_M_12_ES1		0x0FE
-#define MPU_N_12_ES1		0x07
-#define MPU_FSEL_12_ES1		0x05
-#define MPU_M2_12_ES1		0x01
-
-#define MPU_M_12_ES2		0x0FA
-#define MPU_N_12_ES2		0x05
-#define MPU_FSEL_12_ES2		0x07
-#define MPU_M2_ES2		0x01
-
-#define MPU_M_12		0x085
-#define MPU_N_12		0x05
-#define MPU_FSEL_12		0x07
-#define MPU_M2_12		0x01
-
-#define MPU_M_13_ES1		0x17D
-#define MPU_N_13_ES1		0x0C
-#define MPU_FSEL_13_ES1		0x03
-#define MPU_M2_13_ES1		0x01
-
-#define MPU_M_13_ES2		0x1F4
-#define MPU_N_13_ES2		0x0C
-#define MPU_FSEL_13_ES2		0x03
-#define MPU_M2_13_ES2		0x01
-
-#define MPU_M_13		0x10A
-#define MPU_N_13		0x0C
-#define MPU_FSEL_13		0x03
-#define MPU_M2_13		0x01
-
-#define MPU_M_19P2_ES1		0x179
-#define MPU_N_19P2_ES1		0x12
-#define MPU_FSEL_19P2_ES1	0x04
-#define MPU_M2_19P2_ES1		0x01
-
-#define MPU_M_19P2_ES2		0x271
-#define MPU_N_19P2_ES2		0x17
-#define MPU_FSEL_19P2_ES2	0x03
-#define MPU_M2_19P2_ES2		0x01
-
-#define MPU_M_19P2		0x14C
-#define MPU_N_19P2		0x17
-#define MPU_FSEL_19P2		0x03
-#define MPU_M2_19P2		0x01
-
-#define MPU_M_26_ES1		0x17D
-#define MPU_N_26_ES1		0x19
-#define MPU_FSEL_26_ES1		0x03
-#define MPU_M2_26_ES1		0x01
-
-#define MPU_M_26_ES2		0x0FA
-#define MPU_N_26_ES2		0x0C
-#define MPU_FSEL_26_ES2		0x07
-#define MPU_M2_26_ES2		0x01
-
-#define MPU_M_26		0x085
-#define MPU_N_26		0x0C
-#define MPU_FSEL_26		0x07
-#define MPU_M2_26		0x01
-
-#define MPU_M_38P4_ES1		0x1FA
-#define MPU_N_38P4_ES1		0x32
-#define MPU_FSEL_38P4_ES1	0x03
-#define MPU_M2_38P4_ES1		0x01
-
-#define MPU_M_38P4_ES2		0x271
-#define MPU_N_38P4_ES2		0x2F
-#define MPU_FSEL_38P4_ES2	0x03
-#define MPU_M2_38P4_ES2		0x01
-
-#define MPU_M_38P4		0x14C
-#define MPU_N_38P4		0x2F
-#define MPU_FSEL_38P4		0x03
-#define MPU_M2_38P4		0x01
-
-/* IVA DPLL */
-
-#define IVA_M_12_ES1		0x07D
-#define IVA_N_12_ES1		0x05
-#define IVA_FSEL_12_ES1		0x07
-#define IVA_M2_12_ES1		0x01
-
-#define IVA_M_12_ES2		0x0B4
-#define IVA_N_12_ES2		0x05
-#define IVA_FSEL_12_ES2		0x07
-#define IVA_M2_12_ES2		0x01
-
-#define IVA_M_12		0x085
-#define IVA_N_12		0x05
-#define IVA_FSEL_12		0x07
-#define IVA_M2_12		0x01
-
-#define IVA_M_13_ES1		0x0FA
-#define IVA_N_13_ES1		0x0C
-#define IVA_FSEL_13_ES1		0x03
-#define IVA_M2_13_ES1		0x01
-
-#define IVA_M_13_ES2		0x168
-#define IVA_N_13_ES2		0x0C
-#define IVA_FSEL_13_ES2		0x03
-#define IVA_M2_13_ES2		0x01
-
-#define IVA_M_13		0x10A
-#define IVA_N_13		0x0C
-#define IVA_FSEL_13		0x03
-#define IVA_M2_13		0x01
-
-#define IVA_M_19P2_ES1		0x082
-#define IVA_N_19P2_ES1		0x09
-#define IVA_FSEL_19P2_ES1	0x07
-#define IVA_M2_19P2_ES1		0x01
-
-#define IVA_M_19P2_ES2		0x0E1
-#define IVA_N_19P2_ES2		0x0B
-#define IVA_FSEL_19P2_ES2	0x06
-#define IVA_M2_19P2_ES2		0x01
-
-#define IVA_M_19P2		0x14C
-#define IVA_N_19P2		0x17
-#define IVA_FSEL_19P2		0x03
-#define IVA_M2_19P2		0x01
-
-#define IVA_M_26_ES1		0x07D
-#define IVA_N_26_ES1		0x0C
-#define IVA_FSEL_26_ES1		0x07
-#define IVA_M2_26_ES1		0x01
-
-#define IVA_M_26_ES2		0x0B4
-#define IVA_N_26_ES2		0x0C
-#define IVA_FSEL_26_ES2		0x07
-#define IVA_M2_26_ES2		0x01
-
-#define IVA_M_26		0x085
-#define IVA_N_26		0x0C
-#define IVA_FSEL_26		0x07
-#define IVA_M2_26		0x01
-
-#define IVA_M_38P4_ES1		0x13F
-#define IVA_N_38P4_ES1		0x30
-#define IVA_FSEL_38P4_ES1	0x03
-#define IVA_M2_38P4_ES1		0x01
-
-#define IVA_M_38P4_ES2		0x0E1
-#define IVA_N_38P4_ES2		0x17
-#define IVA_FSEL_38P4_ES2	0x06
-#define IVA_M2_38P4_ES2		0x01
-
-#define IVA_M_38P4		0x14C
-#define IVA_N_38P4		0x2F
-#define IVA_FSEL_38P4		0x03
-#define IVA_M2_38P4		0x01
-
-/* CORE DPLL */
-
-#define CORE_M_12		0xA6
-#define CORE_N_12		0x05
-#define CORE_FSEL_12		0x07
-#define CORE_M2_12		0x01	/* M3 of 2 */
-
-#define CORE_M_12_ES1		0x19F
-#define CORE_N_12_ES1		0x0E
-#define CORE_FSL_12_ES1		0x03
-#define CORE_M2_12_ES1		0x1	/* M3 of 2 */
-
-#define CORE_M_13		0x14C
-#define CORE_N_13		0x0C
-#define CORE_FSEL_13		0x03
-#define CORE_M2_13		0x01	/* M3 of 2 */
-
-#define CORE_M_13_ES1		0x1B2
-#define CORE_N_13_ES1		0x10
-#define CORE_FSL_13_ES1		0x03
-#define CORE_M2_13_ES1		0x01	/* M3 of 2 */
-
-#define CORE_M_19P2		0x19F
-#define CORE_N_19P2		0x17
-#define CORE_FSEL_19P2		0x03
-#define CORE_M2_19P2		0x01	/* M3 of 2 */
-
-#define CORE_M_19P2_ES1		0x19F
-#define CORE_N_19P2_ES1		0x17
-#define CORE_FSL_19P2_ES1	0x03
-#define CORE_M2_19P2_ES1	0x01	/* M3 of 2 */
-
-#define CORE_M_26		0xA6
-#define CORE_N_26		0x0C
-#define CORE_FSEL_26		0x07
-#define CORE_M2_26		0x01	/* M3 of 2 */
-
-#define CORE_M_26_ES1		0x1B2
-#define CORE_N_26_ES1		0x21
-#define CORE_FSL_26_ES1		0x03
-#define CORE_M2_26_ES1		0x01	/* M3 of 2 */
-
-#define CORE_M_38P4		0x19F
-#define CORE_N_38P4		0x2F
-#define CORE_FSEL_38P4		0x03
-#define CORE_M2_38P4		0x01	/* M3 of 2 */
-
-#define CORE_M_38P4_ES1		0x19F
-#define CORE_N_38P4_ES1		0x2F
-#define CORE_FSL_38P4_ES1	0x03
-#define CORE_M2_38P4_ES1	0x01	/* M3 of 2 */
-
-/* PER DPLL */
-
-#define PER_M_12		0xD8
-#define PER_N_12		0x05
-#define PER_FSEL_12		0x07
-#define PER_M2_12		0x09
-
-#define PER_M_13		0x1B0
-#define PER_N_13		0x0C
-#define PER_FSEL_13		0x03
-#define PER_M2_13		0x09
-
-#define PER_M_19P2		0xE1
-#define PER_N_19P2		0x09
-#define PER_FSEL_19P2		0x07
-#define PER_M2_19P2		0x09
-
-#define PER_M_26		0xD8
-#define PER_N_26		0x0C
-#define PER_FSEL_26		0x07
-#define PER_M2_26		0x09
-
-#define PER_M_38P4		0xE1
-#define PER_N_38P4		0x13
-#define PER_FSEL_38P4		0x07
-#define PER_M2_38P4		0x09
-
-/* 36XX PER DPLL */
-
-#define PER_36XX_M_12		0x1B0
-#define PER_36XX_N_12		0x05
-#define PER_36XX_FSEL_12	0x07
-#define PER_36XX_M2_12		0x09
-
-#define PER_36XX_M_13		0x360
-#define PER_36XX_N_13		0x0C
-#define PER_36XX_FSEL_13	0x03
-#define PER_36XX_M2_13		0x09
-
-#define PER_36XX_M_19P2		0x1C2
-#define PER_36XX_N_19P2		0x09
-#define PER_36XX_FSEL_19P2	0x07
-#define PER_36XX_M2_19P2	0x09
-
-#define PER_36XX_M_26		0x1B0
-#define PER_36XX_N_26		0x0C
-#define PER_36XX_FSEL_26	0x07
-#define PER_36XX_M2_26		0x09
-
-#define PER_36XX_M_38P4		0x1C2
-#define PER_36XX_N_38P4		0x13
-#define PER_36XX_FSEL_38P4	0x07
-#define PER_36XX_M2_38P4	0x09
-
-#endif	/* endif _CLOCKS_OMAP3_H_ */
diff --git a/arch/arm/include/asm/arch-omap3/cpu.h b/arch/arm/include/asm/arch-omap3/cpu.h
deleted file mode 100644
index 962d6d4..0000000
--- a/arch/arm/include/asm/arch-omap3/cpu.h
+++ /dev/null
@@ -1,490 +0,0 @@
-/*
- * (C) Copyright 2006-2008
- * Texas Instruments, <www.ti.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- */
-
-#ifndef _CPU_H
-#define _CPU_H
-
-#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
-#include <asm/types.h>
-#endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */
-
-/* Register offsets of common modules */
-/* Control */
-#ifndef __KERNEL_STRICT_NAMES
-#ifndef __ASSEMBLY__
-struct ctrl {
-	u8 res1[0xC0];
-	u16 gpmc_nadv_ale;	/* 0xC0 */
-	u16 gpmc_noe;		/* 0xC2 */
-	u16 gpmc_nwe;		/* 0xC4 */
-	u8 res2[0x22A];
-	u32 status;		/* 0x2F0 */
-	u32 gpstatus;		/* 0x2F4 */
-	u8 res3[0x08];
-	u32 rpubkey_0;		/* 0x300 */
-	u32 rpubkey_1;		/* 0x304 */
-	u32 rpubkey_2;		/* 0x308 */
-	u32 rpubkey_3;		/* 0x30C */
-	u32 rpubkey_4;		/* 0x310 */
-	u8 res4[0x04];
-	u32 randkey_0;		/* 0x318 */
-	u32 randkey_1;		/* 0x31C */
-	u32 randkey_2;		/* 0x320 */
-	u32 randkey_3;		/* 0x324 */
-	u8 res5[0x124];
-	u32 ctrl_omap_stat;	/* 0x44C */
-};
-#else /* __ASSEMBLY__ */
-#define CONTROL_STATUS		0x2F0
-#endif /* __ASSEMBLY__ */
-#endif /* __KERNEL_STRICT_NAMES */
-
-#ifndef __KERNEL_STRICT_NAMES
-#ifndef __ASSEMBLY__
-struct ctrl_id {
-	u8 res1[0x4];
-	u32 idcode;		/* 0x04 */
-	u32 prod_id;		/* 0x08 */
-	u32 sku_id;		/* 0x0c */
-	u8 res2[0x08];
-	u32 die_id_0;		/* 0x18 */
-	u32 die_id_1;		/* 0x1C */
-	u32 die_id_2;		/* 0x20 */
-	u32 die_id_3;		/* 0x24 */
-};
-#endif /* __ASSEMBLY__ */
-#endif /* __KERNEL_STRICT_NAMES */
-
-/* device type */
-#define DEVICE_MASK		(0x7 << 8)
-#define SYSBOOT_MASK		0x1F
-#define TST_DEVICE		0x0
-#define EMU_DEVICE		0x1
-#define HS_DEVICE		0x2
-#define GP_DEVICE		0x3
-
-/* device speed */
-#define SKUID_CLK_MASK		0xf
-#define SKUID_CLK_600MHZ	0x0
-#define SKUID_CLK_720MHZ	0x8
-
-#define GPMC_BASE		(OMAP34XX_GPMC_BASE)
-#define GPMC_CONFIG_CS0		0x60
-#define GPMC_CONFIG_CS0_BASE	(GPMC_BASE + GPMC_CONFIG_CS0)
-
-#ifndef __KERNEL_STRICT_NAMES
-#ifndef __ASSEMBLY__
-struct gpmc_cs {
-	u32 config1;		/* 0x00 */
-	u32 config2;		/* 0x04 */
-	u32 config3;		/* 0x08 */
-	u32 config4;		/* 0x0C */
-	u32 config5;		/* 0x10 */
-	u32 config6;		/* 0x14 */
-	u32 config7;		/* 0x18 */
-	u32 nand_cmd;		/* 0x1C */
-	u32 nand_adr;		/* 0x20 */
-	u32 nand_dat;		/* 0x24 */
-	u8 res[8];		/* blow up to 0x30 byte */
-};
-
-struct gpmc {
-	u8 res1[0x10];
-	u32 sysconfig;		/* 0x10 */
-	u8 res2[0x4];
-	u32 irqstatus;		/* 0x18 */
-	u32 irqenable;		/* 0x1C */
-	u8 res3[0x20];
-	u32 timeout_control; 	/* 0x40 */
-	u8 res4[0xC];
-	u32 config;		/* 0x50 */
-	u32 status;		/* 0x54 */
-	u8 res5[0x8];	/* 0x58 */
-	struct gpmc_cs cs[8];	/* 0x60, 0x90, .. */
-	u8 res6[0x14];		/* 0x1E0 */
-	u32 ecc_config;		/* 0x1F4 */
-	u32 ecc_control;	/* 0x1F8 */
-	u32 ecc_size_config;	/* 0x1FC */
-	u32 ecc1_result;	/* 0x200 */
-	u32 ecc2_result;	/* 0x204 */
-	u32 ecc3_result;	/* 0x208 */
-	u32 ecc4_result;	/* 0x20C */
-	u32 ecc5_result;	/* 0x210 */
-	u32 ecc6_result;	/* 0x214 */
-	u32 ecc7_result;	/* 0x218 */
-	u32 ecc8_result;	/* 0x21C */
-	u32 ecc9_result;	/* 0x220 */
-};
-
-/* Used for board specific gpmc initialization */
-extern struct gpmc *gpmc_cfg;
-
-#else /* __ASSEMBLY__ */
-#define GPMC_CONFIG1		0x00
-#define GPMC_CONFIG2		0x04
-#define GPMC_CONFIG3		0x08
-#define GPMC_CONFIG4		0x0C
-#define GPMC_CONFIG5		0x10
-#define GPMC_CONFIG6		0x14
-#define GPMC_CONFIG7		0x18
-#endif /* __ASSEMBLY__ */
-#endif /* __KERNEL_STRICT_NAMES */
-
-/* GPMC Mapping */
-#define FLASH_BASE		0x10000000	/* NOR flash, */
-						/* aligned to 256 Meg */
-#define FLASH_BASE_SDPV1	0x04000000	/* NOR flash, */
-						/* aligned to 64 Meg */
-#define FLASH_BASE_SDPV2	0x10000000	/* NOR flash, */
-						/* aligned to 256 Meg */
-#define DEBUG_BASE		0x08000000	/* debug board */
-#define NAND_BASE		0x30000000	/* NAND addr */
-						/* (actual size small port) */
-#define PISMO2_BASE		0x18000000	/* PISMO2 CS1/2 */
-#define ONENAND_MAP		0x20000000	/* OneNand addr */
-						/* (actual size small port) */
-/* SMS */
-#ifndef __KERNEL_STRICT_NAMES
-#ifndef __ASSEMBLY__
-struct sms {
-	u8 res1[0x10];
-	u32 sysconfig;		/* 0x10 */
-	u8 res2[0x34];
-	u32 rg_att0;		/* 0x48 */
-	u8 res3[0x84];
-	u32 class_arb0;		/* 0xD0 */
-};
-#endif /* __ASSEMBLY__ */
-#endif /* __KERNEL_STRICT_NAMES */
-
-#define BURSTCOMPLETE_GROUP7	(0x1 << 31)
-
-/* SDRC */
-#ifndef __KERNEL_STRICT_NAMES
-#ifndef __ASSEMBLY__
-struct sdrc_cs {
-	u32 mcfg;		/* 0x80 || 0xB0 */
-	u32 mr;			/* 0x84 || 0xB4 */
-	u8 res1[0x4];
-	u32 emr2;		/* 0x8C || 0xBC */
-	u8 res2[0x14];
-	u32 rfr_ctrl;		/* 0x84 || 0xD4 */
-	u32 manual;		/* 0xA8 || 0xD8 */
-	u8 res3[0x4];
-};
-
-struct sdrc_actim {
-	u32 ctrla;		/* 0x9C || 0xC4 */
-	u32 ctrlb;		/* 0xA0 || 0xC8 */
-};
-
-struct sdrc {
-	u8 res1[0x10];
-	u32 sysconfig;		/* 0x10 */
-	u32 status;		/* 0x14 */
-	u8 res2[0x28];
-	u32 cs_cfg;		/* 0x40 */
-	u32 sharing;		/* 0x44 */
-	u8 res3[0x18];
-	u32 dlla_ctrl;		/* 0x60 */
-	u32 dlla_status;	/* 0x64 */
-	u32 dllb_ctrl;		/* 0x68 */
-	u32 dllb_status;	/* 0x6C */
-	u32 power;		/* 0x70 */
-	u8 res4[0xC];
-	struct sdrc_cs cs[2];	/* 0x80 || 0xB0 */
-};
-
-/* EMIF4 */
-typedef struct emif4 {
-	unsigned int sdram_sts;
-	unsigned int sdram_config;
-	unsigned int res1;
-	unsigned int sdram_refresh_ctrl;
-	unsigned int sdram_refresh_ctrl_shdw;
-	unsigned int sdram_time1;
-	unsigned int sdram_time1_shdw;
-	unsigned int sdram_time2;
-	unsigned int sdram_time2_shdw;
-	unsigned int sdram_time3;
-	unsigned int sdram_time3_shdw;
-	unsigned char res2[8];
-	unsigned int sdram_pwr_mgmt;
-	unsigned int sdram_pwr_mgmt_shdw;
-	unsigned char res3[32];
-	unsigned int sdram_iodft_tlgc;
-	unsigned char res4[128];
-	unsigned int ddr_phyctrl1;
-	unsigned int ddr_phyctrl1_shdw;
-	unsigned int ddr_phyctrl2;
-} emif4_t;
-
-#endif /* __ASSEMBLY__ */
-#endif /* __KERNEL_STRICT_NAMES */
-
-#define DLLPHASE_90		(0x1 << 1)
-#define LOADDLL			(0x1 << 2)
-#define ENADLL			(0x1 << 3)
-#define DLL_DELAY_MASK		0xFF00
-#define DLL_NO_FILTER_MASK	((0x1 << 9) | (0x1 << 8))
-
-#define PAGEPOLICY_HIGH		(0x1 << 0)
-#define SRFRONRESET		(0x1 << 7)
-#define PWDNEN			(0x1 << 2)
-#define WAKEUPPROC		(0x1 << 26)
-
-#define DDR_SDRAM		(0x1 << 0)
-#define DEEPPD			(0x1 << 3)
-#define B32NOT16		(0x1 << 4)
-#define BANKALLOCATION		(0x2 << 6)
-#define RAMSIZE_128		(0x40 << 8) /* RAM size in 2MB chunks */
-#define ADDRMUXLEGACY		(0x1 << 19)
-#define CASWIDTH_10BITS		(0x5 << 20)
-#define RASWIDTH_13BITS		(0x2 << 24)
-#define BURSTLENGTH4		(0x2 << 0)
-#define CASL3			(0x3 << 4)
-#define SDRC_ACTIM_CTRL0_BASE	(OMAP34XX_SDRC_BASE + 0x9C)
-#define SDRC_ACTIM_CTRL1_BASE	(OMAP34XX_SDRC_BASE + 0xC4)
-#define ARE_ARCV_1		(0x1 << 0)
-#define ARCV			(0x4e2 << 8) /* Autorefresh count */
-#define OMAP34XX_SDRC_CS0	0x80000000
-#define OMAP34XX_SDRC_CS1	0xA0000000
-#define CMD_NOP			0x0
-#define CMD_PRECHARGE		0x1
-#define CMD_AUTOREFRESH		0x2
-#define CMD_ENTR_PWRDOWN	0x3
-#define CMD_EXIT_PWRDOWN	0x4
-#define CMD_ENTR_SRFRSH		0x5
-#define CMD_CKE_HIGH		0x6
-#define CMD_CKE_LOW		0x7
-#define SOFTRESET		(0x1 << 1)
-#define SMART_IDLE		(0x2 << 3)
-#define REF_ON_IDLE		(0x1 << 6)
-
-/* timer regs offsets (32 bit regs) */
-
-#ifndef __KERNEL_STRICT_NAMES
-#ifndef __ASSEMBLY__
-struct gptimer {
-	u32 tidr;	/* 0x00 r */
-	u8 res[0xc];
-	u32 tiocp_cfg;	/* 0x10 rw */
-	u32 tistat;	/* 0x14 r */
-	u32 tisr;	/* 0x18 rw */
-	u32 tier;	/* 0x1c rw */
-	u32 twer;	/* 0x20 rw */
-	u32 tclr;	/* 0x24 rw */
-	u32 tcrr;	/* 0x28 rw */
-	u32 tldr;	/* 0x2c rw */
-	u32 ttgr;	/* 0x30 rw */
-	u32 twpc;	/* 0x34 r*/
-	u32 tmar;	/* 0x38 rw*/
-	u32 tcar1;	/* 0x3c r */
-	u32 tcicr;	/* 0x40 rw */
-	u32 tcar2;	/* 0x44 r */
-};
-#endif /* __ASSEMBLY__ */
-#endif /* __KERNEL_STRICT_NAMES */
-
-/* enable sys_clk NO-prescale /1 */
-#define GPT_EN			((0x0 << 2) | (0x1 << 1) | (0x1 << 0))
-
-/* Watchdog */
-#ifndef __KERNEL_STRICT_NAMES
-#ifndef __ASSEMBLY__
-struct watchdog {
-	u8 res1[0x34];
-	u32 wwps;	/* 0x34 r */
-	u8 res2[0x10];
-	u32 wspr;	/* 0x48 rw */
-};
-#endif /* __ASSEMBLY__ */
-#endif /* __KERNEL_STRICT_NAMES */
-
-#define WD_UNLOCK1		0xAAAA
-#define WD_UNLOCK2		0x5555
-
-/* PRCM */
-#define PRCM_BASE		0x48004000
-
-#ifndef __KERNEL_STRICT_NAMES
-#ifndef __ASSEMBLY__
-struct prcm {
-	u32 fclken_iva2;	/* 0x00 */
-	u32 clken_pll_iva2;	/* 0x04 */
-	u8 res1[0x1c];
-	u32 idlest_pll_iva2;	/* 0x24 */
-	u8 res2[0x18];
-	u32 clksel1_pll_iva2 ;	/* 0x40 */
-	u32 clksel2_pll_iva2;	/* 0x44 */
-	u8 res3[0x8bc];
-	u32 clken_pll_mpu;	/* 0x904 */
-	u8 res4[0x1c];
-	u32 idlest_pll_mpu;	/* 0x924 */
-	u8 res5[0x18];
-	u32 clksel1_pll_mpu;	/* 0x940 */
-	u32 clksel2_pll_mpu;	/* 0x944 */
-	u8 res6[0xb8];
-	u32 fclken1_core;	/* 0xa00 */
-	u8 res7[0xc];
-	u32 iclken1_core;	/* 0xa10 */
-	u32 iclken2_core;	/* 0xa14 */
-	u8 res8[0x28];
-	u32 clksel_core;	/* 0xa40 */
-	u8 res9[0xbc];
-	u32 fclken_gfx;		/* 0xb00 */
-	u8 res10[0xc];
-	u32 iclken_gfx;		/* 0xb10 */
-	u8 res11[0x2c];
-	u32 clksel_gfx;		/* 0xb40 */
-	u8 res12[0xbc];
-	u32 fclken_wkup;	/* 0xc00 */
-	u8 res13[0xc];
-	u32 iclken_wkup;	/* 0xc10 */
-	u8 res14[0xc];
-	u32 idlest_wkup;	/* 0xc20 */
-	u8 res15[0x1c];
-	u32 clksel_wkup;	/* 0xc40 */
-	u8 res16[0xbc];
-	u32 clken_pll;		/* 0xd00 */
-	u8 res17[0x1c];
-	u32 idlest_ckgen;	/* 0xd20 */
-	u8 res18[0x1c];
-	u32 clksel1_pll;	/* 0xd40 */
-	u32 clksel2_pll;	/* 0xd44 */
-	u32 clksel3_pll;	/* 0xd48 */
-	u8 res19[0xb4];
-	u32 fclken_dss;		/* 0xe00 */
-	u8 res20[0xc];
-	u32 iclken_dss;		/* 0xe10 */
-	u8 res21[0x2c];
-	u32 clksel_dss;		/* 0xe40 */
-	u8 res22[0xbc];
-	u32 fclken_cam;		/* 0xf00 */
-	u8 res23[0xc];
-	u32 iclken_cam;		/* 0xf10 */
-	u8 res24[0x2c];
-	u32 clksel_cam;		/* 0xf40 */
-	u8 res25[0xbc];
-	u32 fclken_per;		/* 0x1000 */
-	u8 res26[0xc];
-	u32 iclken_per;		/* 0x1010 */
-	u8 res27[0x2c];
-	u32 clksel_per;		/* 0x1040 */
-	u8 res28[0xfc];
-	u32 clksel1_emu;	/* 0x1140 */
-};
-#else /* __ASSEMBLY__ */
-#define CM_CLKSEL_CORE		0x48004a40
-#define CM_CLKSEL_GFX		0x48004b40
-#define CM_CLKSEL_WKUP		0x48004c40
-#define CM_CLKEN_PLL		0x48004d00
-#define CM_CLKSEL1_PLL		0x48004d40
-#define CM_CLKSEL1_EMU		0x48005140
-#endif /* __ASSEMBLY__ */
-#endif /* __KERNEL_STRICT_NAMES */
-
-#define PRM_BASE		0x48306000
-
-#ifndef __KERNEL_STRICT_NAMES
-#ifndef __ASSEMBLY__
-struct prm {
-	u8 res1[0xd40];
-	u32 clksel;		/* 0xd40 */
-	u8 res2[0x50c];
-	u32 rstctrl;		/* 0x1250 */
-	u8 res3[0x1c];
-	u32 clksrc_ctrl;	/* 0x1270 */
-};
-#else /* __ASSEMBLY__ */
-#define PRM_RSTCTRL		0x48307250
-#define PRM_RSTCTRL_RESET	0x04
-#endif /* __ASSEMBLY__ */
-#endif /* __KERNEL_STRICT_NAMES */
-
-#define SYSCLKDIV_1		(0x1 << 6)
-#define SYSCLKDIV_2		(0x1 << 7)
-
-#define CLKSEL_GPT1		(0x1 << 0)
-
-#define EN_GPT1			(0x1 << 0)
-#define EN_32KSYNC		(0x1 << 2)
-
-#define ST_WDT2			(0x1 << 5)
-
-#define ST_MPU_CLK		(0x1 << 0)
-
-#define ST_CORE_CLK		(0x1 << 0)
-
-#define ST_PERIPH_CLK		(0x1 << 1)
-
-#define ST_IVA2_CLK		(0x1 << 0)
-
-#define RESETDONE		(0x1 << 0)
-
-#define TCLR_ST			(0x1 << 0)
-#define TCLR_AR			(0x1 << 1)
-#define TCLR_PRE		(0x1 << 5)
-
-/* SMX-APE */
-#define PM_RT_APE_BASE_ADDR_ARM		(SMX_APE_BASE + 0x10000)
-#define PM_GPMC_BASE_ADDR_ARM		(SMX_APE_BASE + 0x12400)
-#define PM_OCM_RAM_BASE_ADDR_ARM	(SMX_APE_BASE + 0x12800)
-#define PM_IVA2_BASE_ADDR_ARM		(SMX_APE_BASE + 0x14000)
-
-#ifndef __KERNEL_STRICT_NAMES
-#ifndef __ASSEMBLY__
-struct pm {
-	u8 res1[0x48];
-	u32 req_info_permission_0;	/* 0x48 */
-	u8 res2[0x4];
-	u32 read_permission_0;		/* 0x50 */
-	u8 res3[0x4];
-	u32 wirte_permission_0;		/* 0x58 */
-	u8 res4[0x4];
-	u32 addr_match_1;		/* 0x58 */
-	u8 res5[0x4];
-	u32 req_info_permission_1;	/* 0x68 */
-	u8 res6[0x14];
-	u32 addr_match_2;		/* 0x80 */
-};
-#endif /*__ASSEMBLY__ */
-#endif /* __KERNEL_STRICT_NAMES */
-
-/* Permission values for registers -Full fledged permissions to all */
-#define UNLOCK_1			0xFFFFFFFF
-#define UNLOCK_2			0x00000000
-#define UNLOCK_3			0x0000FFFF
-
-#define NOT_EARLY			0
-
-/* I2C base */
-#define I2C_BASE1		(OMAP34XX_CORE_L4_IO_BASE + 0x70000)
-#define I2C_BASE2		(OMAP34XX_CORE_L4_IO_BASE + 0x72000)
-#define I2C_BASE3		(OMAP34XX_CORE_L4_IO_BASE + 0x60000)
-
-/* MUSB base */
-#define MUSB_BASE		(OMAP34XX_CORE_L4_IO_BASE + 0xAB000)
-
-#endif /* _CPU_H */
diff --git a/arch/arm/include/asm/arch-omap3/dss.h b/arch/arm/include/asm/arch-omap3/dss.h
deleted file mode 100644
index e5e3b0d..0000000
--- a/arch/arm/include/asm/arch-omap3/dss.h
+++ /dev/null
@@ -1,173 +0,0 @@
-/*
- * (C) Copyright 2010
- * Texas Instruments, <www.ti.com>
- * Syed Mohammed Khasim <khasim@ti.com>
- *
- * Referred to Linux DSS driver files for OMAP3
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation's version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef DSS_H
-#define DSS_H
-
-/*
- * DSS Base Registers
- */
-#define OMAP3_DSS_BASE		0x48050040
-#define OMAP3_DISPC_BASE	0x48050440
-#define OMAP3_VENC_BASE		0x48050C00
-
-/* DSS Registers */
-struct dss_regs {
-	u32 control;				/* 0x40 */
-	u32 sdi_control;			/* 0x44 */
-	u32 pll_control;			/* 0x48 */
-};
-
-/* DISPC Registers */
-struct dispc_regs {
-	u32 control;				/* 0x40 */
-	u32 config;				/* 0x44 */
-	u32 reserve_2;				/* 0x48 */
-	u32 default_color0;			/* 0x4C */
-	u32 default_color1;			/* 0x50 */
-	u32 trans_color0;			/* 0x54 */
-	u32 trans_color1;			/* 0x58 */
-	u32 line_status;			/* 0x5C */
-	u32 line_number;			/* 0x60 */
-	u32 timing_h;				/* 0x64 */
-	u32 timing_v;				/* 0x68 */
-	u32 pol_freq;				/* 0x6C */
-	u32 divisor;				/* 0x70 */
-	u32 global_alpha;			/* 0x74 */
-	u32 size_dig;				/* 0x78 */
-	u32 size_lcd;				/* 0x7C */
-};
-
-/* VENC Registers */
-struct venc_regs {
-	u32 rev_id;				/* 0x00 */
-	u32 status;				/* 0x04 */
-	u32 f_control;				/* 0x08 */
-	u32 reserve_1;				/* 0x0C */
-	u32 vidout_ctrl;			/* 0x10 */
-	u32 sync_ctrl;				/* 0x14 */
-	u32 reserve_2;				/* 0x18 */
-	u32 llen;				/* 0x1C */
-	u32 flens;				/* 0x20 */
-	u32 hfltr_ctrl;				/* 0x24 */
-	u32 cc_carr_wss_carr;			/* 0x28 */
-	u32 c_phase;				/* 0x2C */
-	u32 gain_u;				/* 0x30 */
-	u32 gain_v;				/* 0x34 */
-	u32 gain_y;				/* 0x38 */
-	u32 black_level;			/* 0x3C */
-	u32 blank_level;			/* 0x40 */
-	u32 x_color;				/* 0x44 */
-	u32 m_control;				/* 0x48 */
-	u32 bstamp_wss_data;			/* 0x4C */
-	u32 s_carr;				/* 0x50 */
-	u32 line21;				/* 0x54 */
-	u32 ln_sel;				/* 0x58 */
-	u32 l21__wc_ctl;			/* 0x5C */
-	u32 htrigger_vtrigger;			/* 0x60 */
-	u32 savid__eavid;			/* 0x64 */
-	u32 flen__fal;				/* 0x68 */
-	u32 lal__phase_reset;			/* 0x6C */
-	u32 hs_int_start_stop_x;		/* 0x70 */
-	u32 hs_ext_start_stop_x;		/* 0x74 */
-	u32 vs_int_start_x;			/* 0x78 */
-	u32 vs_int_stop_x__vs_int_start_y;	/* 0x7C */
-	u32 vs_int_stop_y__vs_ext_start_x;	/* 0x80 */
-	u32 vs_ext_stop_x__vs_ext_start_y;	/* 0x84 */
-	u32 vs_ext_stop_y;			/* 0x88 */
-	u32 reserve_3;				/* 0x8C */
-	u32 avid_start_stop_x;			/* 0x90 */
-	u32 avid_start_stop_y;			/* 0x94 */
-	u32 reserve_4;				/* 0x98 */
-	u32 reserve_5;				/* 0x9C */
-	u32 fid_int_start_x__fid_int_start_y;	/* 0xA0 */
-	u32 fid_int_offset_y__fid_ext_start_x;	/* 0xA4 */
-	u32 fid_ext_start_y__fid_ext_offset_y;	/* 0xA8 */
-	u32 reserve_6;				/* 0xAC */
-	u32 tvdetgp_int_start_stop_x;		/* 0xB0 */
-	u32 tvdetgp_int_start_stop_y;		/* 0xB4 */
-	u32 gen_ctrl;				/* 0xB8 */
-	u32 reserve_7;				/* 0xBC */
-	u32 reserve_8;				/* 0xC0 */
-	u32 output_control;			/* 0xC4 */
-	u32 dac_b__dac_c;			/* 0xC8 */
-	u32 height_width;			/* 0xCC */
-};
-
-/* Few Register Offsets */
-#define FRAME_MODE_SHIFT			1
-#define TFTSTN_SHIFT				3
-#define DATALINES_SHIFT				8
-
-/* Enabling Display controller */
-#define LCD_ENABLE				1
-#define DIG_ENABLE				(1 << 1)
-#define GO_LCD					(1 << 5)
-#define GO_DIG					(1 << 6)
-#define GP_OUT0					(1 << 15)
-#define GP_OUT1					(1 << 16)
-
-#define DISPC_ENABLE				(LCD_ENABLE | \
-						 DIG_ENABLE | \
-						 GO_LCD | \
-						 GO_DIG | \
-						 GP_OUT0| \
-						 GP_OUT1)
-
-/* Configure VENC DSS Params */
-#define VENC_CLK_ENABLE				(1 << 3)
-#define DAC_DEMEN				(1 << 4)
-#define DAC_POWERDN				(1 << 5)
-#define VENC_OUT_SEL				(1 << 6)
-#define DIG_LPP_SHIFT				16
-#define VENC_DSS_CONFIG				(VENC_CLK_ENABLE | \
-						 DAC_DEMEN | \
-						 DAC_POWERDN | \
-						 VENC_OUT_SEL)
-/*
- * Panel Configuration
- */
-struct panel_config {
-	u32 timing_h;
-	u32 timing_v;
-	u32 pol_freq;
-	u32 divisor;
-	u32 lcd_size;
-	u32 panel_type;
-	u32 data_lines;
-	u32 load_mode;
-	u32 panel_color;
-};
-
-/*
- * Generic DSS Functions
- */
-void omap3_dss_venc_config(const struct venc_regs *venc_cfg,
-			u32 height, u32 width);
-void omap3_dss_panel_config(const struct panel_config *panel_cfg);
-void omap3_dss_enable(void);
-
-#endif /* DSS_H */
diff --git a/arch/arm/include/asm/arch-omap3/emif4.h b/arch/arm/include/asm/arch-omap3/emif4.h
deleted file mode 100644
index 579da0c..0000000
--- a/arch/arm/include/asm/arch-omap3/emif4.h
+++ /dev/null
@@ -1,79 +0,0 @@
-/*
- * Auther:
- *       Vaibhav Hiremath <hvaibhav@ti.com>
- *
- * Copyright (C) 2010
- * Texas Instruments Incorporated - http://www.ti.com/
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef _EMIF_H_
-#define _EMIF_H_
-
-/*
- * Configuration values
- */
-#define EMIF4_TIM1_T_RP		(0x3 << 25)
-#define EMIF4_TIM1_T_RCD	(0x3 << 21)
-#define EMIF4_TIM1_T_WR		(0x3 << 17)
-#define EMIF4_TIM1_T_RAS	(0x8 << 12)
-#define EMIF4_TIM1_T_RC		(0xA << 6)
-#define EMIF4_TIM1_T_RRD	(0x2 << 3)
-#define EMIF4_TIM1_T_WTR	(0x2)
-
-#define EMIF4_TIM2_T_XP		(0x2 << 28)
-#define EMIF4_TIM2_T_ODT	(0x0 << 25)
-#define EMIF4_TIM2_T_XSNR	(0x1C << 16)
-#define EMIF4_TIM2_T_XSRD	(0xC8 << 6)
-#define EMIF4_TIM2_T_RTP	(0x1 << 3)
-#define EMIF4_TIM2_T_CKE	(0x2)
-
-#define EMIF4_TIM3_T_RFC	(0x25 << 4)
-#define EMIF4_TIM3_T_RAS_MAX	(0x7)
-
-#define EMIF4_PWR_IDLE_MODE	(0x2 << 30)
-#define EMIF4_PWR_DPD_DIS	(0x0 << 10)
-#define EMIF4_PWR_DPD_EN	(0x1 << 10)
-#define EMIF4_PWR_LP_MODE	(0x0 << 8)
-#define EMIF4_PWR_PM_TIM	(0x0)
-
-#define EMIF4_INITREF_DIS	(0x0 << 31)
-#define EMIF4_REFRESH_RATE	(0x50F)
-
-#define EMIF4_CFG_SDRAM_TYP	(0x2 << 29)
-#define EMIF4_CFG_IBANK_POS	(0x0 << 27)
-#define EMIF4_CFG_DDR_TERM	(0x0 << 24)
-#define EMIF4_CFG_DDR2_DDQS	(0x1 << 23)
-#define EMIF4_CFG_DDR_DIS_DLL	(0x0 << 20)
-#define EMIF4_CFG_SDR_DRV	(0x0 << 18)
-#define EMIF4_CFG_NARROW_MD	(0x0 << 14)
-#define EMIF4_CFG_CL		(0x5 << 10)
-#define EMIF4_CFG_ROWSIZE	(0x0 << 7)
-#define EMIF4_CFG_IBANK		(0x3 << 4)
-#define EMIF4_CFG_EBANK		(0x0 << 3)
-#define EMIF4_CFG_PGSIZE	(0x2)
-
-/*
- * EMIF4 PHY Control 1 register configuration
- */
-#define EMIF4_DDR1_EXT_STRB_EN	(0x1 << 7)
-#define EMIF4_DDR1_EXT_STRB_DIS	(0x0 << 7)
-#define EMIF4_DDR1_PWRDN_DIS	(0x0 << 6)
-#define EMIF4_DDR1_PWRDN_EN	(0x1 << 6)
-#define EMIF4_DDR1_READ_LAT	(0x6 << 0)
-
-#endif /* endif _EMIF_H_ */
diff --git a/arch/arm/include/asm/arch-omap3/gpio.h b/arch/arm/include/asm/arch-omap3/gpio.h
deleted file mode 100644
index 30f633c..0000000
--- a/arch/arm/include/asm/arch-omap3/gpio.h
+++ /dev/null
@@ -1,86 +0,0 @@
-/*
- * Copyright (c) 2009 Wind River Systems, Inc.
- * Tom Rix <Tom.Rix@windriver.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- * This work is derived from the linux 2.6.27 kernel source
- * To fetch, use the kernel repository
- * git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6.git
- * Use the v2.6.27 tag.
- *
- * Below is the original's header including its copyright
- *
- *  linux/arch/arm/plat-omap/gpio.c
- *
- * Support functions for OMAP GPIO
- *
- * Copyright (C) 2003-2005 Nokia Corporation
- * Written by Juha Yrjölä <juha.yrjola@nokia.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#ifndef _GPIO_H
-#define _GPIO_H
-
-#define OMAP24XX_GPIO_REVISION		0x0000
-#define OMAP24XX_GPIO_SYSCONFIG		0x0010
-#define OMAP24XX_GPIO_SYSSTATUS		0x0014
-#define OMAP24XX_GPIO_IRQSTATUS1	0x0018
-#define OMAP24XX_GPIO_IRQSTATUS2	0x0028
-#define OMAP24XX_GPIO_IRQENABLE2	0x002c
-#define OMAP24XX_GPIO_IRQENABLE1	0x001c
-#define OMAP24XX_GPIO_WAKE_EN		0x0020
-#define OMAP24XX_GPIO_CTRL		0x0030
-#define OMAP24XX_GPIO_OE		0x0034
-#define OMAP24XX_GPIO_DATAIN		0x0038
-#define OMAP24XX_GPIO_DATAOUT		0x003c
-#define OMAP24XX_GPIO_LEVELDETECT0	0x0040
-#define OMAP24XX_GPIO_LEVELDETECT1	0x0044
-#define OMAP24XX_GPIO_RISINGDETECT	0x0048
-#define OMAP24XX_GPIO_FALLINGDETECT	0x004c
-#define OMAP24XX_GPIO_DEBOUNCE_EN	0x0050
-#define OMAP24XX_GPIO_DEBOUNCE_VAL	0x0054
-#define OMAP24XX_GPIO_CLEARIRQENABLE1	0x0060
-#define OMAP24XX_GPIO_SETIRQENABLE1	0x0064
-#define OMAP24XX_GPIO_CLEARWKUENA	0x0080
-#define OMAP24XX_GPIO_SETWKUENA		0x0084
-#define OMAP24XX_GPIO_CLEARDATAOUT	0x0090
-#define OMAP24XX_GPIO_SETDATAOUT	0x0094
-
-struct gpio_bank {
-	void *base;
-	int method;
-};
-
-#define METHOD_GPIO_24XX	4
-
-/* This is the interface */
-
-/* Request a gpio before using it */
-int omap_request_gpio(int gpio);
-/* Reset and free a gpio after using it */
-void omap_free_gpio(int gpio);
-/* Sets the gpio as input or output */
-void omap_set_gpio_direction(int gpio, int is_input);
-/* Set or clear a gpio output */
-void omap_set_gpio_dataout(int gpio, int enable);
-/* Get the value of a gpio input */
-int omap_get_gpio_datain(int gpio);
-
-#endif /* _GPIO_H_ */
diff --git a/arch/arm/include/asm/arch-omap3/i2c.h b/arch/arm/include/asm/arch-omap3/i2c.h
deleted file mode 100644
index d2e7488..0000000
--- a/arch/arm/include/asm/arch-omap3/i2c.h
+++ /dev/null
@@ -1,64 +0,0 @@
-/*
- * (C) Copyright 2004-2008
- * Texas Instruments, <www.ti.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-#ifndef _OMAP3_I2C_H_
-#define _OMAP3_I2C_H_
-
-#define I2C_BUS_MAX	3
-#define I2C_DEFAULT_BASE	I2C_BASE1
-
-struct i2c {
-	unsigned short rev;	/* 0x00 */
-	unsigned short res1;
-	unsigned short ie;	/* 0x04 */
-	unsigned short res2;
-	unsigned short stat;	/* 0x08 */
-	unsigned short res3;
-	unsigned short iv;	/* 0x0C */
-	unsigned short res4;
-	unsigned short syss;	/* 0x10 */
-	unsigned short res4a;
-	unsigned short buf;	/* 0x14 */
-	unsigned short res5;
-	unsigned short cnt;	/* 0x18 */
-	unsigned short res6;
-	unsigned short data;	/* 0x1C */
-	unsigned short res7;
-	unsigned short sysc;	/* 0x20 */
-	unsigned short res8;
-	unsigned short con;	/* 0x24 */
-	unsigned short res9;
-	unsigned short oa;	/* 0x28 */
-	unsigned short res10;
-	unsigned short sa;	/* 0x2C */
-	unsigned short res11;
-	unsigned short psc;	/* 0x30 */
-	unsigned short res12;
-	unsigned short scll;	/* 0x34 */
-	unsigned short res13;
-	unsigned short sclh;	/* 0x38 */
-	unsigned short res14;
-	unsigned short systest;	/* 0x3c */
-	unsigned short res15;
-};
-
-#endif /* _OMAP3_I2C_H_ */
diff --git a/arch/arm/include/asm/arch-omap3/mem.h b/arch/arm/include/asm/arch-omap3/mem.h
deleted file mode 100644
index f165949..0000000
--- a/arch/arm/include/asm/arch-omap3/mem.h
+++ /dev/null
@@ -1,329 +0,0 @@
-/*
- * (C) Copyright 2006-2008
- * Texas Instruments, <www.ti.com>
- * Richard Woodruff <r-woodruff2@ti.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef _MEM_H_
-#define _MEM_H_
-
-#define CS0		0x0
-#define CS1		0x1 /* mirror CS1 regs appear offset 0x30 from CS0 */
-
-#ifndef __ASSEMBLY__
-enum {
-	STACKED = 0,
-	IP_DDR = 1,
-	COMBO_DDR = 2,
-	IP_SDR = 3,
-};
-#endif /* __ASSEMBLY__ */
-
-#define EARLY_INIT	1
-
-/* Slower full frequency range default timings for x32 operation*/
-#define SDRC_SHARING	0x00000100
-#define SDRC_MR_0_SDR	0x00000031
-
-#define DLL_OFFSET		0
-#define DLL_WRITEDDRCLKX2DIS	1
-#define DLL_ENADLL		1
-#define DLL_LOCKDLL		0
-#define DLL_DLLPHASE_72		0
-#define DLL_DLLPHASE_90		1
-
-/* rkw - need to find of 90/72 degree recommendation for speed like before */
-#define SDP_SDRC_DLLAB_CTRL	((DLL_ENADLL << 3) | \
-				(DLL_LOCKDLL << 2) | (DLL_DLLPHASE_90 << 1))
-
-/* Infineon part of 3430SDP (165MHz optimized) 6.06ns
- *   ACTIMA
- *	TDAL = Twr/Tck + Trp/tck = 15/6 + 18/6 = 2.5 + 3 = 5.5 -> 6
- *	TDPL (Twr) = 15/6	= 2.5 -> 3
- *	TRRD = 12/6	= 2
- *	TRCD = 18/6	= 3
- *	TRP = 18/6	= 3
- *	TRAS = 42/6	= 7
- *	TRC = 60/6	= 10
- *	TRFC = 72/6	= 12
- *   ACTIMB
- *	TCKE = 2
- *	XSR = 120/6 = 20
- */
-#define INFINEON_TDAL_165	6
-#define INFINEON_TDPL_165	3
-#define INFINEON_TRRD_165	2
-#define INFINEON_TRCD_165	3
-#define INFINEON_TRP_165	3
-#define INFINEON_TRAS_165	7
-#define INFINEON_TRC_165	10
-#define INFINEON_TRFC_165	12
-#define INFINEON_V_ACTIMA_165	((INFINEON_TRFC_165 << 27) |		\
-		(INFINEON_TRC_165 << 22) | (INFINEON_TRAS_165 << 18) |	\
-		(INFINEON_TRP_165 << 15) | (INFINEON_TRCD_165 << 12) |	\
-		(INFINEON_TRRD_165 << 9) | (INFINEON_TDPL_165 << 6) |	\
-		(INFINEON_TDAL_165))
-
-#define INFINEON_TWTR_165	1
-#define INFINEON_TCKE_165	2
-#define INFINEON_TXP_165	2
-#define INFINEON_XSR_165	20
-#define INFINEON_V_ACTIMB_165	((INFINEON_TCKE_165 << 12) |		\
-		(INFINEON_XSR_165 << 0) | (INFINEON_TXP_165 << 8) |	\
-		(INFINEON_TWTR_165 << 16))
-
-/* Micron part of 3430 EVM (165MHz optimized) 6.06ns
- * ACTIMA
- *	TDAL = Twr/Tck + Trp/tck= 15/6 + 18 /6 = 2.5 + 3 = 5.5 -> 6
- *	TDPL (Twr)	= 15/6	= 2.5 -> 3
- *	TRRD		= 12/6	= 2
- *	TRCD		= 18/6	= 3
- *	TRP		= 18/6	= 3
- *	TRAS		= 42/6	= 7
- *	TRC		= 60/6	= 10
- *	TRFC		= 125/6	= 21
- * ACTIMB
- *	TWTR		= 1
- *	TCKE		= 1
- *	TXSR		= 138/6	= 23
- *	TXP		= 25/6	= 4.1 ~5
- */
-#define MICRON_TDAL_165		6
-#define MICRON_TDPL_165		3
-#define MICRON_TRRD_165		2
-#define MICRON_TRCD_165		3
-#define MICRON_TRP_165		3
-#define MICRON_TRAS_165		7
-#define MICRON_TRC_165		10
-#define MICRON_TRFC_165		21
-#define MICRON_V_ACTIMA_165 ((MICRON_TRFC_165 << 27) |			\
-		(MICRON_TRC_165 << 22) | (MICRON_TRAS_165 << 18) |	\
-		(MICRON_TRP_165 << 15) | (MICRON_TRCD_165 << 12) |	\
-		(MICRON_TRRD_165 << 9) | (MICRON_TDPL_165 << 6) |	\
-		(MICRON_TDAL_165))
-
-#define MICRON_TWTR_165		1
-#define MICRON_TCKE_165		1
-#define MICRON_XSR_165		23
-#define MICRON_TXP_165		5
-#define MICRON_V_ACTIMB_165 ((MICRON_TCKE_165 << 12) |			\
-		(MICRON_XSR_165 << 0) | (MICRON_TXP_165 << 8) |	\
-		(MICRON_TWTR_165 << 16))
-
-/*
- * NUMONYX part of IGEP v2 (165MHz optimized) 6.06ns
- *   ACTIMA
- *      TDAL = Twr/Tck + Trp/tck = 15/6 + 18/6 = 2.5 + 3 = 5.5 -> 6
- *      TDPL (Twr) = 15/6 = 2.5 -> 3
- *      TRRD = 12/6 = 2
- *      TRCD = 22.5/6 = 3.75 -> 4
- *      TRP  = 18/6 = 3
- *      TRAS = 42/6 = 7
- *      TRC  = 60/6 = 10
- *      TRFC = 140/6 = 23.3 -> 24
- *   ACTIMB
- *	TWTR = 2
- *	TCKE = 2
- *	TXSR = 200/6 =  33.3 -> 34
- *	TXP  = 1.0 + 1.1 = 2.1 -> 3
- */
-#define NUMONYX_TDAL_165   6
-#define NUMONYX_TDPL_165   3
-#define NUMONYX_TRRD_165   2
-#define NUMONYX_TRCD_165   4
-#define NUMONYX_TRP_165    3
-#define NUMONYX_TRAS_165   7
-#define NUMONYX_TRC_165   10
-#define NUMONYX_TRFC_165  24
-#define NUMONYX_V_ACTIMA_165 ((NUMONYX_TRFC_165 << 27) | \
-		(NUMONYX_TRC_165 << 22) | (NUMONYX_TRAS_165 << 18) | \
-		(NUMONYX_TRP_165 << 15) | (NUMONYX_TRCD_165 << 12) | \
-		(NUMONYX_TRRD_165 << 9) | (NUMONYX_TDPL_165 << 6) | \
-		(NUMONYX_TDAL_165))
-
-#define NUMONYX_TWTR_165   2
-#define NUMONYX_TCKE_165   2
-#define NUMONYX_TXP_165    3
-#define NUMONYX_XSR_165    34
-#define NUMONYX_V_ACTIMB_165 ((NUMONYX_TCKE_165 << 12) | \
-		(NUMONYX_XSR_165 << 0) | (NUMONYX_TXP_165 << 8) | \
-		(NUMONYX_TWTR_165 << 16))
-
-#ifdef CONFIG_OMAP3_INFINEON_DDR
-#define V_ACTIMA_165 INFINEON_V_ACTIMA_165
-#define V_ACTIMB_165 INFINEON_V_ACTIMB_165
-#endif
-#ifdef CONFIG_OMAP3_MICRON_DDR
-#define V_ACTIMA_165 MICRON_V_ACTIMA_165
-#define V_ACTIMB_165 MICRON_V_ACTIMB_165
-#endif
-#ifdef CONFIG_OMAP3_NUMONYX_DDR
-#define V_ACTIMA_165 NUMONYX_V_ACTIMA_165
-#define V_ACTIMB_165 NUMONYX_V_ACTIMB_165
-#endif
-
-#if !defined(V_ACTIMA_165) || !defined(V_ACTIMB_165)
-#error "Please choose the right DDR type in config header"
-#endif
-
-/*
- * GPMC settings -
- * Definitions is as per the following format
- * #define <PART>_GPMC_CONFIG<x> <value>
- * Where:
- * PART is the part name e.g. STNOR - Intel Strata Flash
- * x is GPMC config registers from 1 to 6 (there will be 6 macros)
- * Value is corresponding value
- *
- * For every valid PRCM configuration there should be only one definition of
- * the same. if values are independent of the board, this definition will be
- * present in this file if values are dependent on the board, then this should
- * go into corresponding mem-boardName.h file
- *
- * Currently valid part Names are (PART):
- * STNOR - Intel Strata Flash
- * SMNAND - Samsung NAND
- * MPDB - H4 MPDB board
- * SBNOR - Sibley NOR
- * MNAND - Micron Large page x16 NAND
- * ONNAND - Samsung One NAND
- *
- * include/configs/file.h contains the defn - for all CS we are interested
- * #define OMAP34XX_GPMC_CSx PART
- * #define OMAP34XX_GPMC_CSx_SIZE Size
- * #define OMAP34XX_GPMC_CSx_MAP Map
- * Where:
- * x - CS number
- * PART - Part Name as defined above
- * SIZE - how big is the mapping to be
- *   GPMC_SIZE_128M - 0x8
- *   GPMC_SIZE_64M  - 0xC
- *   GPMC_SIZE_32M  - 0xE
- *   GPMC_SIZE_16M  - 0xF
- * MAP  - Map this CS to which address(GPMC address space)- Absolute address
- *   >>24 before being used.
- */
-#define GPMC_SIZE_128M	0x8
-#define GPMC_SIZE_64M	0xC
-#define GPMC_SIZE_32M	0xE
-#define GPMC_SIZE_16M	0xF
-
-#define SMNAND_GPMC_CONFIG1	0x00000800
-#define SMNAND_GPMC_CONFIG2	0x00141400
-#define SMNAND_GPMC_CONFIG3	0x00141400
-#define SMNAND_GPMC_CONFIG4	0x0F010F01
-#define SMNAND_GPMC_CONFIG5	0x010C1414
-#define SMNAND_GPMC_CONFIG6	0x1F0F0A80
-#define SMNAND_GPMC_CONFIG7	0x00000C44
-
-#define M_NAND_GPMC_CONFIG1	0x00001800
-#define M_NAND_GPMC_CONFIG2	0x00141400
-#define M_NAND_GPMC_CONFIG3	0x00141400
-#define M_NAND_GPMC_CONFIG4	0x0F010F01
-#define M_NAND_GPMC_CONFIG5	0x010C1414
-#define M_NAND_GPMC_CONFIG6	0x1f0f0A80
-#define M_NAND_GPMC_CONFIG7	0x00000C44
-
-#define STNOR_GPMC_CONFIG1	0x3
-#define STNOR_GPMC_CONFIG2	0x00151501
-#define STNOR_GPMC_CONFIG3	0x00060602
-#define STNOR_GPMC_CONFIG4	0x11091109
-#define STNOR_GPMC_CONFIG5	0x01141F1F
-#define STNOR_GPMC_CONFIG6	0x000004c4
-
-#define SIBNOR_GPMC_CONFIG1	0x1200
-#define SIBNOR_GPMC_CONFIG2	0x001f1f00
-#define SIBNOR_GPMC_CONFIG3	0x00080802
-#define SIBNOR_GPMC_CONFIG4	0x1C091C09
-#define SIBNOR_GPMC_CONFIG5	0x01131F1F
-#define SIBNOR_GPMC_CONFIG6	0x1F0F03C2
-
-#define SDPV2_MPDB_GPMC_CONFIG1	0x00611200
-#define SDPV2_MPDB_GPMC_CONFIG2	0x001F1F01
-#define SDPV2_MPDB_GPMC_CONFIG3	0x00080803
-#define SDPV2_MPDB_GPMC_CONFIG4	0x1D091D09
-#define SDPV2_MPDB_GPMC_CONFIG5	0x041D1F1F
-#define SDPV2_MPDB_GPMC_CONFIG6	0x1D0904C4
-
-#define MPDB_GPMC_CONFIG1	0x00011000
-#define MPDB_GPMC_CONFIG2	0x001f1f01
-#define MPDB_GPMC_CONFIG3	0x00080803
-#define MPDB_GPMC_CONFIG4	0x1c0b1c0a
-#define MPDB_GPMC_CONFIG5	0x041f1F1F
-#define MPDB_GPMC_CONFIG6	0x1F0F04C4
-
-#define P2_GPMC_CONFIG1	0x0
-#define P2_GPMC_CONFIG2	0x0
-#define P2_GPMC_CONFIG3	0x0
-#define P2_GPMC_CONFIG4	0x0
-#define P2_GPMC_CONFIG5	0x0
-#define P2_GPMC_CONFIG6	0x0
-
-#define ONENAND_GPMC_CONFIG1	0x00001200
-#define ONENAND_GPMC_CONFIG2	0x000F0F01
-#define ONENAND_GPMC_CONFIG3	0x00030301
-#define ONENAND_GPMC_CONFIG4	0x0F040F04
-#define ONENAND_GPMC_CONFIG5	0x010F1010
-#define ONENAND_GPMC_CONFIG6	0x1F060000
-
-#define NET_GPMC_CONFIG1	0x00001000
-#define NET_GPMC_CONFIG2	0x001e1e01
-#define NET_GPMC_CONFIG3	0x00080300
-#define NET_GPMC_CONFIG4	0x1c091c09
-#define NET_GPMC_CONFIG5	0x04181f1f
-#define NET_GPMC_CONFIG6	0x00000FCF
-#define NET_GPMC_CONFIG7	0x00000f6c
-
-/* max number of GPMC Chip Selects */
-#define GPMC_MAX_CS	8
-/* max number of GPMC regs */
-#define GPMC_MAX_REG	7
-
-#define PISMO1_NOR	1
-#define PISMO1_NAND	2
-#define PISMO2_CS0	3
-#define PISMO2_CS1	4
-#define PISMO1_ONENAND	5
-#define DBG_MPDB	6
-#define PISMO2_NAND_CS0 7
-#define PISMO2_NAND_CS1 8
-
-/* make it readable for the gpmc_init */
-#define PISMO1_NOR_BASE		FLASH_BASE
-#define PISMO1_NAND_BASE	NAND_BASE
-#define PISMO2_CS0_BASE		PISMO2_MAP1
-#define PISMO1_ONEN_BASE	ONENAND_MAP
-#define DBG_MPDB_BASE		DEBUG_BASE
-
-#ifndef __ASSEMBLY__
-
-/* Function prototypes */
-void mem_init(void);
-
-u32 is_mem_sdr(void);
-u32 mem_ok(u32 cs);
-
-u32 get_sdr_cs_size(u32);
-u32 get_sdr_cs_offset(u32);
-
-#endif	/* __ASSEMBLY__ */
-
-#endif /* endif _MEM_H_ */
diff --git a/arch/arm/include/asm/arch-omap3/mmc_host_def.h b/arch/arm/include/asm/arch-omap3/mmc_host_def.h
deleted file mode 100644
index ba1c2ff..0000000
--- a/arch/arm/include/asm/arch-omap3/mmc_host_def.h
+++ /dev/null
@@ -1,203 +0,0 @@
-/*
- * (C) Copyright 2008
- * Texas Instruments, <www.ti.com>
- * Syed Mohammed Khasim <khasim@ti.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation's version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef MMC_HOST_DEF_H
-#define MMC_HOST_DEF_H
-
-/* T2 Register definitions */
-#define T2_BASE			0x48002000
-
-typedef struct t2 {
-	unsigned char res1[0x274];	/* 0x000 */
-	unsigned int devconf0;		/* 0x274 */
-	unsigned char res2[0x060];	/* 0x278 */
-	unsigned int devconf1;		/* 0x2D8 */
-	unsigned char res3[0x244];	/* 0x2DC */
-	unsigned int pbias_lite;	/* 0x520 */
-} t2_t;
-
-#define MMCSDIO1ADPCLKISEL		(1 << 24)
-#define MMCSDIO2ADPCLKISEL		(1 << 6)
-
-#define EN_MMC1				(1 << 24)
-#define EN_MMC2				(1 << 25)
-#define EN_MMC3				(1 << 30)
-
-#define PBIASLITEPWRDNZ0		(1 << 1)
-#define PBIASSPEEDCTRL0			(1 << 2)
-#define PBIASLITEPWRDNZ1		(1 << 9)
-
-/*
- * OMAP HSMMC register definitions
- */
-#define OMAP_HSMMC1_BASE	0x4809C000
-#define OMAP_HSMMC2_BASE	0x480B4000
-#define OMAP_HSMMC3_BASE	0x480AD000
-
-typedef struct hsmmc {
-	unsigned char res1[0x10];
-	unsigned int sysconfig;		/* 0x10 */
-	unsigned int sysstatus;		/* 0x14 */
-	unsigned char res2[0x14];
-	unsigned int con;		/* 0x2C */
-	unsigned char res3[0xD4];
-	unsigned int blk;		/* 0x104 */
-	unsigned int arg;		/* 0x108 */
-	unsigned int cmd;		/* 0x10C */
-	unsigned int rsp10;		/* 0x110 */
-	unsigned int rsp32;		/* 0x114 */
-	unsigned int rsp54;		/* 0x118 */
-	unsigned int rsp76;		/* 0x11C */
-	unsigned int data;		/* 0x120 */
-	unsigned int pstate;		/* 0x124 */
-	unsigned int hctl;		/* 0x128 */
-	unsigned int sysctl;		/* 0x12C */
-	unsigned int stat;		/* 0x130 */
-	unsigned int ie;		/* 0x134 */
-	unsigned char res4[0x8];
-	unsigned int capa;		/* 0x140 */
-} hsmmc_t;
-
-/*
- * OMAP HS MMC Bit definitions
- */
-#define MMC_SOFTRESET			(0x1 << 1)
-#define RESETDONE			(0x1 << 0)
-#define NOOPENDRAIN			(0x0 << 0)
-#define OPENDRAIN			(0x1 << 0)
-#define OD				(0x1 << 0)
-#define INIT_NOINIT			(0x0 << 1)
-#define INIT_INITSTREAM			(0x1 << 1)
-#define HR_NOHOSTRESP			(0x0 << 2)
-#define STR_BLOCK 			(0x0 << 3)
-#define MODE_FUNC			(0x0 << 4)
-#define DW8_1_4BITMODE 			(0x0 << 5)
-#define MIT_CTO				(0x0 << 6)
-#define CDP_ACTIVEHIGH			(0x0 << 7)
-#define WPP_ACTIVEHIGH 			(0x0 << 8)
-#define RESERVED_MASK			(0x3 << 9)
-#define CTPL_MMC_SD 			(0x0 << 11)
-#define BLEN_512BYTESLEN		(0x200 << 0)
-#define NBLK_STPCNT			(0x0 << 16)
-#define DE_DISABLE			(0x0 << 0)
-#define BCE_DISABLE			(0x0 << 1)
-#define BCE_ENABLE			(0x1 << 1)
-#define ACEN_DISABLE			(0x0 << 2)
-#define DDIR_OFFSET			(4)
-#define DDIR_MASK			(0x1 << 4)
-#define DDIR_WRITE			(0x0 << 4)
-#define DDIR_READ			(0x1 << 4)
-#define MSBS_SGLEBLK			(0x0 << 5)
-#define MSBS_MULTIBLK			(0x1 << 5)
-#define RSP_TYPE_OFFSET			(16)
-#define RSP_TYPE_MASK			(0x3 << 16)
-#define RSP_TYPE_NORSP			(0x0 << 16)
-#define RSP_TYPE_LGHT136		(0x1 << 16)
-#define RSP_TYPE_LGHT48			(0x2 << 16)
-#define RSP_TYPE_LGHT48B		(0x3 << 16)
-#define CCCE_NOCHECK			(0x0 << 19)
-#define CCCE_CHECK			(0x1 << 19)
-#define CICE_NOCHECK			(0x0 << 20)
-#define CICE_CHECK			(0x1 << 20)
-#define DP_OFFSET			(21)
-#define DP_MASK				(0x1 << 21)
-#define DP_NO_DATA			(0x0 << 21)
-#define DP_DATA				(0x1 << 21)
-#define CMD_TYPE_NORMAL			(0x0 << 22)
-#define INDEX_OFFSET			(24)
-#define INDEX_MASK			(0x3f << 24)
-#define INDEX(i)			(i << 24)
-#define DATI_MASK			(0x1 << 1)
-#define DATI_CMDDIS			(0x1 << 1)
-#define DTW_1_BITMODE			(0x0 << 1)
-#define DTW_4_BITMODE			(0x1 << 1)
-#define DTW_8_BITMODE                   (0x1 << 5) /* CON[DW8]*/
-#define SDBP_PWROFF			(0x0 << 8)
-#define SDBP_PWRON			(0x1 << 8)
-#define SDVS_1V8			(0x5 << 9)
-#define SDVS_3V0			(0x6 << 9)
-#define ICE_MASK			(0x1 << 0)
-#define ICE_STOP			(0x0 << 0)
-#define ICS_MASK			(0x1 << 1)
-#define ICS_NOTREADY			(0x0 << 1)
-#define ICE_OSCILLATE			(0x1 << 0)
-#define CEN_MASK			(0x1 << 2)
-#define CEN_DISABLE			(0x0 << 2)
-#define CEN_ENABLE			(0x1 << 2)
-#define CLKD_OFFSET			(6)
-#define CLKD_MASK			(0x3FF << 6)
-#define DTO_MASK			(0xF << 16)
-#define DTO_15THDTO			(0xE << 16)
-#define SOFTRESETALL			(0x1 << 24)
-#define CC_MASK				(0x1 << 0)
-#define TC_MASK				(0x1 << 1)
-#define BWR_MASK			(0x1 << 4)
-#define BRR_MASK			(0x1 << 5)
-#define ERRI_MASK			(0x1 << 15)
-#define IE_CC				(0x01 << 0)
-#define IE_TC				(0x01 << 1)
-#define IE_BWR				(0x01 << 4)
-#define IE_BRR				(0x01 << 5)
-#define IE_CTO				(0x01 << 16)
-#define IE_CCRC				(0x01 << 17)
-#define IE_CEB				(0x01 << 18)
-#define IE_CIE				(0x01 << 19)
-#define IE_DTO				(0x01 << 20)
-#define IE_DCRC				(0x01 << 21)
-#define IE_DEB				(0x01 << 22)
-#define IE_CERR				(0x01 << 28)
-#define IE_BADA				(0x01 << 29)
-
-#define VS30_3V0SUP			(1 << 25)
-#define VS18_1V8SUP			(1 << 26)
-
-/* Driver definitions */
-#define MMCSD_SECTOR_SIZE		512
-#define MMC_CARD			0
-#define SD_CARD				1
-#define BYTE_MODE			0
-#define SECTOR_MODE			1
-#define CLK_INITSEQ			0
-#define CLK_400KHZ			1
-#define CLK_MISC			2
-
-typedef struct {
-	unsigned int card_type;
-	unsigned int version;
-	unsigned int mode;
-	unsigned int size;
-	unsigned int RCA;
-} mmc_card_data;
-#define RSP_TYPE_NONE	(RSP_TYPE_NORSP   | CCCE_NOCHECK | CICE_NOCHECK)
-#define MMC_CMD0	(INDEX(0)  | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE)
-
-/* Clock Configurations and Macros */
-#define MMC_CLOCK_REFERENCE	96 /* MHz */
-
-#define mmc_reg_out(addr, mask, val)\
-	writel((readl(addr) & (~(mask))) | ((val) & (mask)), (addr))
-
-int omap_mmc_init(int dev_index);
-
-#endif /* MMC_HOST_DEF_H */
diff --git a/arch/arm/include/asm/arch-omap3/mux.h b/arch/arm/include/asm/arch-omap3/mux.h
deleted file mode 100644
index 0c01c73..0000000
--- a/arch/arm/include/asm/arch-omap3/mux.h
+++ /dev/null
@@ -1,412 +0,0 @@
-/*
- * (C) Copyright 2006-2008
- * Texas Instruments, <www.ti.com>
- * Syed Mohammed Khasim <x0khasim@ti.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-#ifndef _MUX_H_
-#define _MUX_H_
-
-/*
- * IEN  - Input Enable
- * IDIS - Input Disable
- * PTD  - Pull type Down
- * PTU  - Pull type Up
- * DIS  - Pull type selection is inactive
- * EN   - Pull type selection is active
- * M0   - Mode 0
- */
-
-#define IEN	(1 << 8)
-
-#define IDIS	(0 << 8)
-#define PTU	(1 << 4)
-#define PTD	(0 << 4)
-#define EN	(1 << 3)
-#define DIS	(0 << 3)
-
-#define M0	0
-#define M1	1
-#define M2	2
-#define M3	3
-#define M4	4
-#define M5	5
-#define M6	6
-#define M7	7
-
-/*
- * To get the actual address the offset has to added
- * with OMAP34XX_CTRL_BASE to get the actual address
- */
-
-/*SDRC*/
-#define CONTROL_PADCONF_SDRC_D0		0x0030
-#define CONTROL_PADCONF_SDRC_D1		0x0032
-#define CONTROL_PADCONF_SDRC_D2		0x0034
-#define CONTROL_PADCONF_SDRC_D3		0x0036
-#define CONTROL_PADCONF_SDRC_D4		0x0038
-#define CONTROL_PADCONF_SDRC_D5		0x003A
-#define CONTROL_PADCONF_SDRC_D6		0x003C
-#define CONTROL_PADCONF_SDRC_D7		0x003E
-#define CONTROL_PADCONF_SDRC_D8		0x0040
-#define CONTROL_PADCONF_SDRC_D9		0x0042
-#define CONTROL_PADCONF_SDRC_D10	0x0044
-#define CONTROL_PADCONF_SDRC_D11	0x0046
-#define CONTROL_PADCONF_SDRC_D12	0x0048
-#define CONTROL_PADCONF_SDRC_D13	0x004A
-#define CONTROL_PADCONF_SDRC_D14	0x004C
-#define CONTROL_PADCONF_SDRC_D15	0x004E
-#define CONTROL_PADCONF_SDRC_D16	0x0050
-#define CONTROL_PADCONF_SDRC_D17	0x0052
-#define CONTROL_PADCONF_SDRC_D18	0x0054
-#define CONTROL_PADCONF_SDRC_D19	0x0056
-#define CONTROL_PADCONF_SDRC_D20	0x0058
-#define CONTROL_PADCONF_SDRC_D21	0x005A
-#define CONTROL_PADCONF_SDRC_D22	0x005C
-#define CONTROL_PADCONF_SDRC_D23	0x005E
-#define CONTROL_PADCONF_SDRC_D24	0x0060
-#define CONTROL_PADCONF_SDRC_D25	0x0062
-#define CONTROL_PADCONF_SDRC_D26	0x0064
-#define CONTROL_PADCONF_SDRC_D27	0x0066
-#define CONTROL_PADCONF_SDRC_D28	0x0068
-#define CONTROL_PADCONF_SDRC_D29	0x006A
-#define CONTROL_PADCONF_SDRC_D30	0x006C
-#define CONTROL_PADCONF_SDRC_D31	0x006E
-#define CONTROL_PADCONF_SDRC_CLK	0x0070
-#define CONTROL_PADCONF_SDRC_DQS0	0x0072
-#define CONTROL_PADCONF_SDRC_DQS1	0x0074
-#define CONTROL_PADCONF_SDRC_DQS2	0x0076
-#define CONTROL_PADCONF_SDRC_DQS3	0x0078
-/*GPMC*/
-#define CONTROL_PADCONF_GPMC_A1		0x007A
-#define CONTROL_PADCONF_GPMC_A2		0x007C
-#define CONTROL_PADCONF_GPMC_A3		0x007E
-#define CONTROL_PADCONF_GPMC_A4		0x0080
-#define CONTROL_PADCONF_GPMC_A5		0x0082
-#define CONTROL_PADCONF_GPMC_A6		0x0084
-#define CONTROL_PADCONF_GPMC_A7		0x0086
-#define CONTROL_PADCONF_GPMC_A8		0x0088
-#define CONTROL_PADCONF_GPMC_A9		0x008A
-#define CONTROL_PADCONF_GPMC_A10	0x008C
-#define CONTROL_PADCONF_GPMC_D0		0x008E
-#define CONTROL_PADCONF_GPMC_D1		0x0090
-#define CONTROL_PADCONF_GPMC_D2		0x0092
-#define CONTROL_PADCONF_GPMC_D3		0x0094
-#define CONTROL_PADCONF_GPMC_D4		0x0096
-#define CONTROL_PADCONF_GPMC_D5		0x0098
-#define CONTROL_PADCONF_GPMC_D6		0x009A
-#define CONTROL_PADCONF_GPMC_D7		0x009C
-#define CONTROL_PADCONF_GPMC_D8		0x009E
-#define CONTROL_PADCONF_GPMC_D9		0x00A0
-#define CONTROL_PADCONF_GPMC_D10	0x00A2
-#define CONTROL_PADCONF_GPMC_D11	0x00A4
-#define CONTROL_PADCONF_GPMC_D12	0x00A6
-#define CONTROL_PADCONF_GPMC_D13	0x00A8
-#define CONTROL_PADCONF_GPMC_D14	0x00AA
-#define CONTROL_PADCONF_GPMC_D15	0x00AC
-#define CONTROL_PADCONF_GPMC_NCS0	0x00AE
-#define CONTROL_PADCONF_GPMC_NCS1	0x00B0
-#define CONTROL_PADCONF_GPMC_NCS2	0x00B2
-#define CONTROL_PADCONF_GPMC_NCS3	0x00B4
-#define CONTROL_PADCONF_GPMC_NCS4	0x00B6
-#define CONTROL_PADCONF_GPMC_NCS5	0x00B8
-#define CONTROL_PADCONF_GPMC_NCS6	0x00BA
-#define CONTROL_PADCONF_GPMC_NCS7	0x00BC
-#define CONTROL_PADCONF_GPMC_CLK	0x00BE
-#define CONTROL_PADCONF_GPMC_NADV_ALE	0x00C0
-#define CONTROL_PADCONF_GPMC_NOE	0x00C2
-#define CONTROL_PADCONF_GPMC_NWE	0x00C4
-#define CONTROL_PADCONF_GPMC_NBE0_CLE	0x00C6
-#define CONTROL_PADCONF_GPMC_NBE1	0x00C8
-#define CONTROL_PADCONF_GPMC_NWP	0x00CA
-#define CONTROL_PADCONF_GPMC_WAIT0	0x00CC
-#define CONTROL_PADCONF_GPMC_WAIT1	0x00CE
-#define CONTROL_PADCONF_GPMC_WAIT2	0x00D0
-#define CONTROL_PADCONF_GPMC_WAIT3	0x00D2
-/*DSS*/
-#define CONTROL_PADCONF_DSS_PCLK	0x00D4
-#define CONTROL_PADCONF_DSS_HSYNC	0x00D6
-#define CONTROL_PADCONF_DSS_VSYNC	0x00D8
-#define CONTROL_PADCONF_DSS_ACBIAS	0x00DA
-#define CONTROL_PADCONF_DSS_DATA0	0x00DC
-#define CONTROL_PADCONF_DSS_DATA1	0x00DE
-#define CONTROL_PADCONF_DSS_DATA2	0x00E0
-#define CONTROL_PADCONF_DSS_DATA3	0x00E2
-#define CONTROL_PADCONF_DSS_DATA4	0x00E4
-#define CONTROL_PADCONF_DSS_DATA5	0x00E6
-#define CONTROL_PADCONF_DSS_DATA6	0x00E8
-#define CONTROL_PADCONF_DSS_DATA7	0x00EA
-#define CONTROL_PADCONF_DSS_DATA8	0x00EC
-#define CONTROL_PADCONF_DSS_DATA9	0x00EE
-#define CONTROL_PADCONF_DSS_DATA10	0x00F0
-#define CONTROL_PADCONF_DSS_DATA11	0x00F2
-#define CONTROL_PADCONF_DSS_DATA12	0x00F4
-#define CONTROL_PADCONF_DSS_DATA13	0x00F6
-#define CONTROL_PADCONF_DSS_DATA14	0x00F8
-#define CONTROL_PADCONF_DSS_DATA15	0x00FA
-#define CONTROL_PADCONF_DSS_DATA16	0x00FC
-#define CONTROL_PADCONF_DSS_DATA17	0x00FE
-#define CONTROL_PADCONF_DSS_DATA18	0x0100
-#define CONTROL_PADCONF_DSS_DATA19	0x0102
-#define CONTROL_PADCONF_DSS_DATA20	0x0104
-#define CONTROL_PADCONF_DSS_DATA21	0x0106
-#define CONTROL_PADCONF_DSS_DATA22	0x0108
-#define CONTROL_PADCONF_DSS_DATA23	0x010A
-/*CAMERA*/
-#define CONTROL_PADCONF_CAM_HS		0x010C
-#define CONTROL_PADCONF_CAM_VS		0x010E
-#define CONTROL_PADCONF_CAM_XCLKA	0x0110
-#define CONTROL_PADCONF_CAM_PCLK	0x0112
-#define CONTROL_PADCONF_CAM_FLD		0x0114
-#define CONTROL_PADCONF_CAM_D0		0x0116
-#define CONTROL_PADCONF_CAM_D1		0x0118
-#define CONTROL_PADCONF_CAM_D2		0x011A
-#define CONTROL_PADCONF_CAM_D3		0x011C
-#define CONTROL_PADCONF_CAM_D4		0x011E
-#define CONTROL_PADCONF_CAM_D5		0x0120
-#define CONTROL_PADCONF_CAM_D6		0x0122
-#define CONTROL_PADCONF_CAM_D7		0x0124
-#define CONTROL_PADCONF_CAM_D8		0x0126
-#define CONTROL_PADCONF_CAM_D9		0x0128
-#define CONTROL_PADCONF_CAM_D10		0x012A
-#define CONTROL_PADCONF_CAM_D11		0x012C
-#define CONTROL_PADCONF_CAM_XCLKB	0x012E
-#define CONTROL_PADCONF_CAM_WEN		0x0130
-#define CONTROL_PADCONF_CAM_STROBE	0x0132
-#define CONTROL_PADCONF_CSI2_DX0	0x0134
-#define CONTROL_PADCONF_CSI2_DY0	0x0136
-#define CONTROL_PADCONF_CSI2_DX1	0x0138
-#define CONTROL_PADCONF_CSI2_DY1	0x013A
-/*Audio Interface */
-#define CONTROL_PADCONF_MCBSP2_FSX	0x013C
-#define CONTROL_PADCONF_MCBSP2_CLKX	0x013E
-#define CONTROL_PADCONF_MCBSP2_DR	0x0140
-#define CONTROL_PADCONF_MCBSP2_DX	0x0142
-#define CONTROL_PADCONF_MMC1_CLK	0x0144
-#define CONTROL_PADCONF_MMC1_CMD	0x0146
-#define CONTROL_PADCONF_MMC1_DAT0	0x0148
-#define CONTROL_PADCONF_MMC1_DAT1	0x014A
-#define CONTROL_PADCONF_MMC1_DAT2	0x014C
-#define CONTROL_PADCONF_MMC1_DAT3	0x014E
-#define CONTROL_PADCONF_MMC1_DAT4	0x0150
-#define CONTROL_PADCONF_MMC1_DAT5	0x0152
-#define CONTROL_PADCONF_MMC1_DAT6	0x0154
-#define CONTROL_PADCONF_MMC1_DAT7	0x0156
-/*Wireless LAN */
-#define CONTROL_PADCONF_MMC2_CLK	0x0158
-#define CONTROL_PADCONF_MMC2_CMD	0x015A
-#define CONTROL_PADCONF_MMC2_DAT0	0x015C
-#define CONTROL_PADCONF_MMC2_DAT1	0x015E
-#define CONTROL_PADCONF_MMC2_DAT2	0x0160
-#define CONTROL_PADCONF_MMC2_DAT3	0x0162
-#define CONTROL_PADCONF_MMC2_DAT4	0x0164
-#define CONTROL_PADCONF_MMC2_DAT5	0x0166
-#define CONTROL_PADCONF_MMC2_DAT6	0x0168
-#define CONTROL_PADCONF_MMC2_DAT7	0x016A
-/*Bluetooth*/
-#define CONTROL_PADCONF_MCBSP3_DX	0x016C
-#define CONTROL_PADCONF_MCBSP3_DR	0x016E
-#define CONTROL_PADCONF_MCBSP3_CLKX	0x0170
-#define CONTROL_PADCONF_MCBSP3_FSX	0x0172
-#define CONTROL_PADCONF_UART2_CTS	0x0174
-#define CONTROL_PADCONF_UART2_RTS	0x0176
-#define CONTROL_PADCONF_UART2_TX	0x0178
-#define CONTROL_PADCONF_UART2_RX	0x017A
-/*Modem Interface */
-#define CONTROL_PADCONF_UART1_TX	0x017C
-#define CONTROL_PADCONF_UART1_RTS	0x017E
-#define CONTROL_PADCONF_UART1_CTS	0x0180
-#define CONTROL_PADCONF_UART1_RX	0x0182
-#define CONTROL_PADCONF_MCBSP4_CLKX	0x0184
-#define CONTROL_PADCONF_MCBSP4_DR	0x0186
-#define CONTROL_PADCONF_MCBSP4_DX	0x0188
-#define CONTROL_PADCONF_MCBSP4_FSX	0x018A
-#define CONTROL_PADCONF_MCBSP1_CLKR	0x018C
-#define CONTROL_PADCONF_MCBSP1_FSR	0x018E
-#define CONTROL_PADCONF_MCBSP1_DX	0x0190
-#define CONTROL_PADCONF_MCBSP1_DR	0x0192
-#define CONTROL_PADCONF_MCBSP_CLKS	0x0194
-#define CONTROL_PADCONF_MCBSP1_FSX	0x0196
-#define CONTROL_PADCONF_MCBSP1_CLKX	0x0198
-/*Serial Interface*/
-#define CONTROL_PADCONF_UART3_CTS_RCTX	0x019A
-#define CONTROL_PADCONF_UART3_RTS_SD	0x019C
-#define CONTROL_PADCONF_UART3_RX_IRRX	0x019E
-#define CONTROL_PADCONF_UART3_TX_IRTX	0x01A0
-#define CONTROL_PADCONF_HSUSB0_CLK	0x01A2
-#define CONTROL_PADCONF_HSUSB0_STP	0x01A4
-#define CONTROL_PADCONF_HSUSB0_DIR	0x01A6
-#define CONTROL_PADCONF_HSUSB0_NXT	0x01A8
-#define CONTROL_PADCONF_HSUSB0_DATA0	0x01AA
-#define CONTROL_PADCONF_HSUSB0_DATA1	0x01AC
-#define CONTROL_PADCONF_HSUSB0_DATA2	0x01AE
-#define CONTROL_PADCONF_HSUSB0_DATA3	0x01B0
-#define CONTROL_PADCONF_HSUSB0_DATA4	0x01B2
-#define CONTROL_PADCONF_HSUSB0_DATA5	0x01B4
-#define CONTROL_PADCONF_HSUSB0_DATA6	0x01B6
-#define CONTROL_PADCONF_HSUSB0_DATA7	0x01B8
-#define CONTROL_PADCONF_I2C1_SCL	0x01BA
-#define CONTROL_PADCONF_I2C1_SDA	0x01BC
-#define CONTROL_PADCONF_I2C2_SCL	0x01BE
-#define CONTROL_PADCONF_I2C2_SDA	0x01C0
-#define CONTROL_PADCONF_I2C3_SCL	0x01C2
-#define CONTROL_PADCONF_I2C3_SDA	0x01C4
-#define CONTROL_PADCONF_I2C4_SCL	0x0A00
-#define CONTROL_PADCONF_I2C4_SDA	0x0A02
-#define CONTROL_PADCONF_HDQ_SIO		0x01C6
-#define CONTROL_PADCONF_MCSPI1_CLK	0x01C8
-#define CONTROL_PADCONF_MCSPI1_SIMO	0x01CA
-#define CONTROL_PADCONF_MCSPI1_SOMI	0x01CC
-#define CONTROL_PADCONF_MCSPI1_CS0	0x01CE
-#define CONTROL_PADCONF_MCSPI1_CS1	0x01D0
-#define CONTROL_PADCONF_MCSPI1_CS2	0x01D2
-#define CONTROL_PADCONF_MCSPI1_CS3	0x01D4
-#define CONTROL_PADCONF_MCSPI2_CLK	0x01D6
-#define CONTROL_PADCONF_MCSPI2_SIMO	0x01D8
-#define CONTROL_PADCONF_MCSPI2_SOMI	0x01DA
-#define CONTROL_PADCONF_MCSPI2_CS0	0x01DC
-#define CONTROL_PADCONF_MCSPI2_CS1	0x01DE
-/*Control and debug */
-#define CONTROL_PADCONF_SYS_32K		0x0A04
-#define CONTROL_PADCONF_SYS_CLKREQ	0x0A06
-#define CONTROL_PADCONF_SYS_NIRQ	0x01E0
-#define CONTROL_PADCONF_SYS_BOOT0	0x0A0A
-#define CONTROL_PADCONF_SYS_BOOT1	0x0A0C
-#define CONTROL_PADCONF_SYS_BOOT2	0x0A0E
-#define CONTROL_PADCONF_SYS_BOOT3	0x0A10
-#define CONTROL_PADCONF_SYS_BOOT4	0x0A12
-#define CONTROL_PADCONF_SYS_BOOT5	0x0A14
-#define CONTROL_PADCONF_SYS_BOOT6	0x0A16
-#define CONTROL_PADCONF_SYS_OFF_MODE	0x0A18
-#define CONTROL_PADCONF_SYS_CLKOUT1	0x0A1A
-#define CONTROL_PADCONF_SYS_CLKOUT2	0x01E2
-#define CONTROL_PADCONF_JTAG_nTRST	0x0A1C
-#define CONTROL_PADCONF_JTAG_TCK	0x0A1E
-#define CONTROL_PADCONF_JTAG_TMS	0x0A20
-#define CONTROL_PADCONF_JTAG_TDI	0x0A22
-#define CONTROL_PADCONF_JTAG_EMU0	0x0A24
-#define CONTROL_PADCONF_JTAG_EMU1	0x0A26
-#define CONTROL_PADCONF_ETK_CLK		0x0A28
-#define CONTROL_PADCONF_ETK_CTL		0x0A2A
-#define CONTROL_PADCONF_ETK_D0		0x0A2C
-#define CONTROL_PADCONF_ETK_D1		0x0A2E
-#define CONTROL_PADCONF_ETK_D2		0x0A30
-#define CONTROL_PADCONF_ETK_D3		0x0A32
-#define CONTROL_PADCONF_ETK_D4		0x0A34
-#define CONTROL_PADCONF_ETK_D5		0x0A36
-#define CONTROL_PADCONF_ETK_D6		0x0A38
-#define CONTROL_PADCONF_ETK_D7		0x0A3A
-#define CONTROL_PADCONF_ETK_D8		0x0A3C
-#define CONTROL_PADCONF_ETK_D9		0x0A3E
-#define CONTROL_PADCONF_ETK_D10		0x0A40
-#define CONTROL_PADCONF_ETK_D11		0x0A42
-#define CONTROL_PADCONF_ETK_D12		0x0A44
-#define CONTROL_PADCONF_ETK_D13		0x0A46
-#define CONTROL_PADCONF_ETK_D14		0x0A48
-#define CONTROL_PADCONF_ETK_D15		0x0A4A
-#define CONTROL_PADCONF_ETK_CLK_ES2	0x05D8
-#define CONTROL_PADCONF_ETK_CTL_ES2	0x05DA
-#define CONTROL_PADCONF_ETK_D0_ES2	0x05DC
-#define CONTROL_PADCONF_ETK_D1_ES2	0x05DE
-#define CONTROL_PADCONF_ETK_D2_ES2	0x05E0
-#define CONTROL_PADCONF_ETK_D3_ES2	0x05E2
-#define CONTROL_PADCONF_ETK_D4_ES2	0x05E4
-#define CONTROL_PADCONF_ETK_D5_ES2	0x05E6
-#define CONTROL_PADCONF_ETK_D6_ES2	0x05E8
-#define CONTROL_PADCONF_ETK_D7_ES2	0x05EA
-#define CONTROL_PADCONF_ETK_D8_ES2	0x05EC
-#define CONTROL_PADCONF_ETK_D9_ES2	0x05EE
-#define CONTROL_PADCONF_ETK_D10_ES2	0x05F0
-#define CONTROL_PADCONF_ETK_D11_ES2	0x05F2
-#define CONTROL_PADCONF_ETK_D12_ES2	0x05F4
-#define CONTROL_PADCONF_ETK_D13_ES2	0x05F6
-#define CONTROL_PADCONF_ETK_D14_ES2	0x05F8
-#define CONTROL_PADCONF_ETK_D15_ES2	0x05FA
-/*Die to Die */
-#define CONTROL_PADCONF_D2D_MCAD0	0x01E4
-#define CONTROL_PADCONF_D2D_MCAD1	0x01E6
-#define CONTROL_PADCONF_D2D_MCAD2	0x01E8
-#define CONTROL_PADCONF_D2D_MCAD3	0x01EA
-#define CONTROL_PADCONF_D2D_MCAD4	0x01EC
-#define CONTROL_PADCONF_D2D_MCAD5	0x01EE
-#define CONTROL_PADCONF_D2D_MCAD6	0x01F0
-#define CONTROL_PADCONF_D2D_MCAD7	0x01F2
-#define CONTROL_PADCONF_D2D_MCAD8	0x01F4
-#define CONTROL_PADCONF_D2D_MCAD9	0x01F6
-#define CONTROL_PADCONF_D2D_MCAD10	0x01F8
-#define CONTROL_PADCONF_D2D_MCAD11	0x01FA
-#define CONTROL_PADCONF_D2D_MCAD12	0x01FC
-#define CONTROL_PADCONF_D2D_MCAD13	0x01FE
-#define CONTROL_PADCONF_D2D_MCAD14	0x0200
-#define CONTROL_PADCONF_D2D_MCAD15	0x0202
-#define CONTROL_PADCONF_D2D_MCAD16	0x0204
-#define CONTROL_PADCONF_D2D_MCAD17	0x0206
-#define CONTROL_PADCONF_D2D_MCAD18	0x0208
-#define CONTROL_PADCONF_D2D_MCAD19	0x020A
-#define CONTROL_PADCONF_D2D_MCAD20	0x020C
-#define CONTROL_PADCONF_D2D_MCAD21	0x020E
-#define CONTROL_PADCONF_D2D_MCAD22	0x0210
-#define CONTROL_PADCONF_D2D_MCAD23	0x0212
-#define CONTROL_PADCONF_D2D_MCAD24	0x0214
-#define CONTROL_PADCONF_D2D_MCAD25	0x0216
-#define CONTROL_PADCONF_D2D_MCAD26	0x0218
-#define CONTROL_PADCONF_D2D_MCAD27	0x021A
-#define CONTROL_PADCONF_D2D_MCAD28	0x021C
-#define CONTROL_PADCONF_D2D_MCAD29	0x021E
-#define CONTROL_PADCONF_D2D_MCAD30	0x0220
-#define CONTROL_PADCONF_D2D_MCAD31	0x0222
-#define CONTROL_PADCONF_D2D_MCAD32	0x0224
-#define CONTROL_PADCONF_D2D_MCAD33	0x0226
-#define CONTROL_PADCONF_D2D_MCAD34	0x0228
-#define CONTROL_PADCONF_D2D_MCAD35	0x022A
-#define CONTROL_PADCONF_D2D_MCAD36	0x022C
-#define CONTROL_PADCONF_D2D_CLK26MI	0x022E
-#define CONTROL_PADCONF_D2D_NRESPWRON	0x0230
-#define CONTROL_PADCONF_D2D_NRESWARM	0x0232
-#define CONTROL_PADCONF_D2D_ARM9NIRQ	0x0234
-#define CONTROL_PADCONF_D2D_UMA2P6FIQ	0x0236
-#define CONTROL_PADCONF_D2D_SPINT	0x0238
-#define CONTROL_PADCONF_D2D_FRINT	0x023A
-#define CONTROL_PADCONF_D2D_DMAREQ0	0x023C
-#define CONTROL_PADCONF_D2D_DMAREQ1	0x023E
-#define CONTROL_PADCONF_D2D_DMAREQ2	0x0240
-#define CONTROL_PADCONF_D2D_DMAREQ3	0x0242
-#define CONTROL_PADCONF_D2D_N3GTRST	0x0244
-#define CONTROL_PADCONF_D2D_N3GTDI	0x0246
-#define CONTROL_PADCONF_D2D_N3GTDO	0x0248
-#define CONTROL_PADCONF_D2D_N3GTMS	0x024A
-#define CONTROL_PADCONF_D2D_N3GTCK	0x024C
-#define CONTROL_PADCONF_D2D_N3GRTCK	0x024E
-#define CONTROL_PADCONF_D2D_MSTDBY	0x0250
-#define CONTROL_PADCONF_D2D_SWAKEUP	0x0A4C
-#define CONTROL_PADCONF_D2D_IDLEREQ	0x0252
-#define CONTROL_PADCONF_D2D_IDLEACK	0x0254
-#define CONTROL_PADCONF_D2D_MWRITE	0x0256
-#define CONTROL_PADCONF_D2D_SWRITE	0x0258
-#define CONTROL_PADCONF_D2D_MREAD	0x025A
-#define CONTROL_PADCONF_D2D_SREAD	0x025C
-#define CONTROL_PADCONF_D2D_MBUSFLAG	0x025E
-#define CONTROL_PADCONF_D2D_SBUSFLAG	0x0260
-#define CONTROL_PADCONF_SDRC_CKE0	0x0262
-#define CONTROL_PADCONF_SDRC_CKE1	0x0264
-
-#define MUX_VAL(OFFSET,VALUE)\
-	writew((VALUE), OMAP34XX_CTRL_BASE + (OFFSET));
-
-#define	CP(x)	(CONTROL_PADCONF_##x)
-
-#endif
diff --git a/arch/arm/include/asm/arch-omap3/omap3.h b/arch/arm/include/asm/arch-omap3/omap3.h
deleted file mode 100644
index 3957c79..0000000
--- a/arch/arm/include/asm/arch-omap3/omap3.h
+++ /dev/null
@@ -1,216 +0,0 @@
-/*
- * (C) Copyright 2006-2008
- * Texas Instruments, <www.ti.com>
- * Richard Woodruff <r-woodruff2@ti.com>
- * Syed Mohammed Khasim <x0khasim@ti.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef _OMAP3_H_
-#define _OMAP3_H_
-
-/* Stuff on L3 Interconnect */
-#define SMX_APE_BASE			0x68000000
-
-/* GPMC */
-#define OMAP34XX_GPMC_BASE		0x6E000000
-
-/* SMS */
-#define OMAP34XX_SMS_BASE		0x6C000000
-
-/* SDRC */
-#define OMAP34XX_SDRC_BASE		0x6D000000
-
-/*
- * L4 Peripherals - L4 Wakeup and L4 Core now
- */
-#define OMAP34XX_CORE_L4_IO_BASE	0x48000000
-#define OMAP34XX_WAKEUP_L4_IO_BASE	0x48300000
-#define OMAP34XX_ID_L4_IO_BASE		0x4830A200
-#define OMAP34XX_L4_PER			0x49000000
-#define OMAP34XX_L4_IO_BASE		OMAP34XX_CORE_L4_IO_BASE
-
-/* CONTROL */
-#define OMAP34XX_CTRL_BASE		(OMAP34XX_L4_IO_BASE + 0x2000)
-
-/* UART */
-#define OMAP34XX_UART1			(OMAP34XX_L4_IO_BASE + 0x6a000)
-#define OMAP34XX_UART2			(OMAP34XX_L4_IO_BASE + 0x6c000)
-#define OMAP34XX_UART3			(OMAP34XX_L4_PER + 0x20000)
-
-/* General Purpose Timers */
-#define OMAP34XX_GPT1			0x48318000
-#define OMAP34XX_GPT2			0x49032000
-#define OMAP34XX_GPT3			0x49034000
-#define OMAP34XX_GPT4			0x49036000
-#define OMAP34XX_GPT5			0x49038000
-#define OMAP34XX_GPT6			0x4903A000
-#define OMAP34XX_GPT7			0x4903C000
-#define OMAP34XX_GPT8			0x4903E000
-#define OMAP34XX_GPT9			0x49040000
-#define OMAP34XX_GPT10			0x48086000
-#define OMAP34XX_GPT11			0x48088000
-#define OMAP34XX_GPT12			0x48304000
-
-/* WatchDog Timers (1 secure, 3 GP) */
-#define WD1_BASE			0x4830C000
-#define WD2_BASE			0x48314000
-#define WD3_BASE			0x49030000
-
-/* 32KTIMER */
-#define SYNC_32KTIMER_BASE		0x48320000
-
-#ifndef __ASSEMBLY__
-
-struct s32ktimer {
-	unsigned char res[0x10];
-	unsigned int s32k_cr;		/* 0x10 */
-};
-
-#endif /* __ASSEMBLY__ */
-
-/* OMAP3 GPIO registers */
-#define OMAP34XX_GPIO1_BASE		0x48310000
-#define OMAP34XX_GPIO2_BASE		0x49050000
-#define OMAP34XX_GPIO3_BASE		0x49052000
-#define OMAP34XX_GPIO4_BASE		0x49054000
-#define OMAP34XX_GPIO5_BASE		0x49056000
-#define OMAP34XX_GPIO6_BASE		0x49058000
-
-#ifndef __ASSEMBLY__
-struct gpio {
-	unsigned char res1[0x34];
-	unsigned int oe;		/* 0x34 */
-	unsigned int datain;		/* 0x38 */
-	unsigned char res2[0x54];
-	unsigned int cleardataout;	/* 0x90 */
-	unsigned int setdataout;	/* 0x94 */
-};
-#endif /* __ASSEMBLY__ */
-
-#define GPIO0				(0x1 << 0)
-#define GPIO1				(0x1 << 1)
-#define GPIO2				(0x1 << 2)
-#define GPIO3				(0x1 << 3)
-#define GPIO4				(0x1 << 4)
-#define GPIO5				(0x1 << 5)
-#define GPIO6				(0x1 << 6)
-#define GPIO7				(0x1 << 7)
-#define GPIO8				(0x1 << 8)
-#define GPIO9				(0x1 << 9)
-#define GPIO10				(0x1 << 10)
-#define GPIO11				(0x1 << 11)
-#define GPIO12				(0x1 << 12)
-#define GPIO13				(0x1 << 13)
-#define GPIO14				(0x1 << 14)
-#define GPIO15				(0x1 << 15)
-#define GPIO16				(0x1 << 16)
-#define GPIO17				(0x1 << 17)
-#define GPIO18				(0x1 << 18)
-#define GPIO19				(0x1 << 19)
-#define GPIO20				(0x1 << 20)
-#define GPIO21				(0x1 << 21)
-#define GPIO22				(0x1 << 22)
-#define GPIO23				(0x1 << 23)
-#define GPIO24				(0x1 << 24)
-#define GPIO25				(0x1 << 25)
-#define GPIO26				(0x1 << 26)
-#define GPIO27				(0x1 << 27)
-#define GPIO28				(0x1 << 28)
-#define GPIO29				(0x1 << 29)
-#define GPIO30				(0x1 << 30)
-#define GPIO31				(0x1 << 31)
-
-/* base address for indirect vectors (internal boot mode) */
-#define SRAM_OFFSET0			0x40000000
-#define SRAM_OFFSET1			0x00200000
-#define SRAM_OFFSET2			0x0000F800
-#define SRAM_VECT_CODE			(SRAM_OFFSET0 | SRAM_OFFSET1 | \
-					 SRAM_OFFSET2)
-
-#define LOW_LEVEL_SRAM_STACK		0x4020FFFC
-
-#define DEBUG_LED1			149	/* gpio */
-#define DEBUG_LED2			150	/* gpio */
-
-#define XDR_POP		5	/* package on package part */
-#define SDR_DISCRETE	4	/* 128M memory SDR module */
-#define DDR_STACKED	3	/* stacked part on 2422 */
-#define DDR_COMBO	2	/* combo part on cpu daughter card */
-#define DDR_DISCRETE	1	/* 2x16 parts on daughter card */
-
-#define DDR_100		100	/* type found on most mem d-boards */
-#define DDR_111		111	/* some combo parts */
-#define DDR_133		133	/* most combo, some mem d-boards */
-#define DDR_165		165	/* future parts */
-
-#define CPU_3430	0x3430
-
-/*
- * 343x real hardware:
- *  ES1     = rev 0
- *
- *  ES2 onwards, the value maps to contents of IDCODE register [31:28].
- *
- * Note : CPU_3XX_ES20 is used in cache.S.  Please review before changing.
- */
-#define CPU_3XX_ES10		0
-#define CPU_3XX_ES20		1
-#define CPU_3XX_ES21		2
-#define CPU_3XX_ES30		3
-#define CPU_3XX_ES31		4
-#define CPU_3XX_ES312		7
-#define CPU_3XX_MAX_REV		8
-
-#define CPU_3XX_ID_SHIFT	28
-
-#define WIDTH_8BIT		0x0000
-#define WIDTH_16BIT		0x1000	/* bit pos for 16 bit in gpmc */
-
-/*
- * Hawkeye values
- */
-#define HAWKEYE_OMAP34XX	0xb7ae
-#define HAWKEYE_AM35XX		0xb868
-#define HAWKEYE_OMAP36XX	0xb891
-
-#define HAWKEYE_SHIFT		12
-
-/*
- * Define CPU families
- */
-#define CPU_OMAP34XX		0x3400	/* OMAP34xx/OMAP35 devices */
-#define CPU_AM35XX		0x3500	/* AM35xx devices          */
-#define CPU_OMAP36XX		0x3600	/* OMAP36xx devices        */
-
-/*
- * Control status register values corresponding to cpu variants
- */
-#define OMAP3503		0x5c00
-#define OMAP3515		0x1c00
-#define OMAP3525		0x4c00
-#define OMAP3530		0x0c00
-
-#define AM3505			0x5c00
-#define AM3517			0x1c00
-
-#define OMAP3730		0x0c00
-
-#endif
diff --git a/arch/arm/include/asm/arch-omap3/omap_gpmc.h b/arch/arm/include/asm/arch-omap3/omap_gpmc.h
deleted file mode 100644
index bd22bce..0000000
--- a/arch/arm/include/asm/arch-omap3/omap_gpmc.h
+++ /dev/null
@@ -1,83 +0,0 @@
-/*
- * (C) Copyright 2004-2008 Texas Instruments, <www.ti.com>
- * Rohit Choraria <rohitkc@ti.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-#ifndef __ASM_ARCH_OMAP_GPMC_H
-#define __ASM_ARCH_OMAP_GPMC_H
-
-#define GPMC_BUF_EMPTY	0
-#define GPMC_BUF_FULL	1
-
-#define ECCCLEAR	(0x1 << 8)
-#define ECCRESULTREG1	(0x1 << 0)
-#define ECCSIZE512BYTE	0xFF
-#define ECCSIZE1	(ECCSIZE512BYTE << 22)
-#define ECCSIZE0	(ECCSIZE512BYTE << 12)
-#define ECCSIZE0SEL	(0x000 << 0)
-
-/* Generic ECC Layouts */
-/* Large Page x8 NAND device Layout */
-#ifdef GPMC_NAND_ECC_LP_x8_LAYOUT
-#define GPMC_NAND_HW_ECC_LAYOUT {\
-	.eccbytes = 12,\
-	.eccpos = {1, 2, 3, 4, 5, 6, 7, 8,\
-		9, 10, 11, 12},\
-	.oobfree = {\
-		{.offset = 13,\
-		 .length = 51 } } \
-}
-#endif
-
-/* Large Page x16 NAND device Layout */
-#ifdef GPMC_NAND_ECC_LP_x16_LAYOUT
-#define GPMC_NAND_HW_ECC_LAYOUT {\
-	.eccbytes = 12,\
-	.eccpos = {2, 3, 4, 5, 6, 7, 8, 9,\
-		10, 11, 12, 13},\
-	.oobfree = {\
-		{.offset = 14,\
-		 .length = 50 } } \
-}
-#endif
-
-/* Small Page x8 NAND device Layout */
-#ifdef GPMC_NAND_ECC_SP_x8_LAYOUT
-#define GPMC_NAND_HW_ECC_LAYOUT {\
-	.eccbytes = 3,\
-	.eccpos = {1, 2, 3},\
-	.oobfree = {\
-		{.offset = 4,\
-		 .length = 12 } } \
-}
-#endif
-
-/* Small Page x16 NAND device Layout */
-#ifdef GPMC_NAND_ECC_SP_x16_LAYOUT
-#define GPMC_NAND_HW_ECC_LAYOUT {\
-	.eccbytes = 3,\
-	.eccpos = {2, 3, 4},\
-	.oobfree = {\
-		{.offset = 5,\
-		 .length = 11 } } \
-}
-#endif
-
-#endif /* __ASM_ARCH_OMAP_GPMC_H */
diff --git a/arch/arm/include/asm/arch-omap3/sys_proto.h b/arch/arm/include/asm/arch-omap3/sys_proto.h
deleted file mode 100644
index 4a28ba1..0000000
--- a/arch/arm/include/asm/arch-omap3/sys_proto.h
+++ /dev/null
@@ -1,70 +0,0 @@
-/*
- * (C) Copyright 2004-2008
- * Texas Instruments, <www.ti.com>
- * Richard Woodruff <r-woodruff2@ti.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
-  */
-#ifndef _SYS_PROTO_H_
-#define _SYS_PROTO_H_
-
-typedef struct {
-	u32 mtype;
-	char *board_string;
-	char *nand_string;
-} omap3_sysinfo;
-
-void prcm_init(void);
-void per_clocks_enable(void);
-
-void memif_init(void);
-void sdrc_init(void);
-void do_sdrc_init(u32, u32);
-void emif4_init(void);
-void gpmc_init(void);
-void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base,
-			u32 size);
-
-void watchdog_init(void);
-void set_muxconf_regs(void);
-
-u32 get_cpu_family(void);
-u32 get_cpu_rev(void);
-u32 get_sku_id(void);
-u32 get_mem_type(void);
-u32 get_sysboot_value(void);
-u32 is_gpmc_muxed(void);
-u32 get_gpmc0_type(void);
-u32 get_gpmc0_width(void);
-u32 is_running_in_sdram(void);
-u32 is_running_in_sram(void);
-u32 is_running_in_flash(void);
-u32 get_device_type(void);
-void l2cache_enable(void);
-void secureworld_exit(void);
-void setup_auxcr(void);
-void try_unlock_memory(void);
-u32 get_boot_type(void);
-void invalidate_dcache(u32);
-void sr32(void *, u32, u32, u32);
-u32 wait_on_value(u32, u32, void *, u32);
-void sdelay(unsigned long);
-void make_cs1_contiguous(void);
-void omap_nand_switch_ecc(int);
-void power_init_r(void);
-void dieid_num_r(void);
-
-#endif
diff --git a/arch/arm/include/asm/arch-omap4/cpu.h b/arch/arm/include/asm/arch-omap4/cpu.h
deleted file mode 100644
index 7d5748a..0000000
--- a/arch/arm/include/asm/arch-omap4/cpu.h
+++ /dev/null
@@ -1,145 +0,0 @@
-/*
- * (C) Copyright 2006-2010
- * Texas Instruments, <www.ti.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- */
-
-#ifndef _CPU_H
-#define _CPU_H
-
-#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
-#include <asm/types.h>
-#endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */
-
-#ifndef __KERNEL_STRICT_NAMES
-#ifndef __ASSEMBLY__
-struct gpmc_cs {
-	u32 config1;		/* 0x00 */
-	u32 config2;		/* 0x04 */
-	u32 config3;		/* 0x08 */
-	u32 config4;		/* 0x0C */
-	u32 config5;		/* 0x10 */
-	u32 config6;		/* 0x14 */
-	u32 config7;		/* 0x18 */
-	u32 nand_cmd;		/* 0x1C */
-	u32 nand_adr;		/* 0x20 */
-	u32 nand_dat;		/* 0x24 */
-	u8 res[8];		/* blow up to 0x30 byte */
-};
-
-struct gpmc {
-	u8 res1[0x10];
-	u32 sysconfig;		/* 0x10 */
-	u8 res2[0x4];
-	u32 irqstatus;		/* 0x18 */
-	u32 irqenable;		/* 0x1C */
-	u8 res3[0x20];
-	u32 timeout_control;	/* 0x40 */
-	u8 res4[0xC];
-	u32 config;		/* 0x50 */
-	u32 status;		/* 0x54 */
-	u8 res5[0x8];	/* 0x58 */
-	struct gpmc_cs cs[8];	/* 0x60, 0x90, .. */
-	u8 res6[0x14];		/* 0x1E0 */
-	u32 ecc_config;		/* 0x1F4 */
-	u32 ecc_control;	/* 0x1F8 */
-	u32 ecc_size_config;	/* 0x1FC */
-	u32 ecc1_result;	/* 0x200 */
-	u32 ecc2_result;	/* 0x204 */
-	u32 ecc3_result;	/* 0x208 */
-	u32 ecc4_result;	/* 0x20C */
-	u32 ecc5_result;	/* 0x210 */
-	u32 ecc6_result;	/* 0x214 */
-	u32 ecc7_result;	/* 0x218 */
-	u32 ecc8_result;	/* 0x21C */
-	u32 ecc9_result;	/* 0x220 */
-};
-
-/* Used for board specific gpmc initialization */
-extern struct gpmc *gpmc_cfg;
-
-struct gptimer {
-	u32 tidr;		/* 0x00 r */
-	u8 res[0xc];
-	u32 tiocp_cfg;		/* 0x10 rw */
-	u32 tistat;		/* 0x14 r */
-	u32 tisr;		/* 0x18 rw */
-	u32 tier;		/* 0x1c rw */
-	u32 twer;		/* 0x20 rw */
-	u32 tclr;		/* 0x24 rw */
-	u32 tcrr;		/* 0x28 rw */
-	u32 tldr;		/* 0x2c rw */
-	u32 ttgr;		/* 0x30 rw */
-	u32 twpc;		/* 0x34 r */
-	u32 tmar;		/* 0x38 rw */
-	u32 tcar1;		/* 0x3c r */
-	u32 tcicr;		/* 0x40 rw */
-	u32 tcar2;		/* 0x44 r */
-};
-#endif /* __ASSEMBLY__ */
-#endif /* __KERNEL_STRICT_NAMES */
-
-/* enable sys_clk NO-prescale /1 */
-#define GPT_EN			((0x0 << 2) | (0x1 << 1) | (0x1 << 0))
-
-/* Watchdog */
-#ifndef __KERNEL_STRICT_NAMES
-#ifndef __ASSEMBLY__
-struct watchdog {
-	u8 res1[0x34];
-	u32 wwps;		/* 0x34 r */
-	u8 res2[0x10];
-	u32 wspr;		/* 0x48 rw */
-};
-#endif /* __ASSEMBLY__ */
-#endif /* __KERNEL_STRICT_NAMES */
-
-#define WD_UNLOCK1		0xAAAA
-#define WD_UNLOCK2		0x5555
-
-#define SYSCLKDIV_1		(0x1 << 6)
-#define SYSCLKDIV_2		(0x1 << 7)
-
-#define CLKSEL_GPT1		(0x1 << 0)
-
-#define EN_GPT1			(0x1 << 0)
-#define EN_32KSYNC		(0x1 << 2)
-
-#define ST_WDT2			(0x1 << 5)
-
-#define RESETDONE		(0x1 << 0)
-
-#define TCLR_ST			(0x1 << 0)
-#define TCLR_AR			(0x1 << 1)
-#define TCLR_PRE		(0x1 << 5)
-
-/* GPMC BASE */
-#define GPMC_BASE		(OMAP44XX_GPMC_BASE)
-
-/* I2C base */
-#define I2C_BASE1		(OMAP44XX_L4_PER_BASE + 0x70000)
-#define I2C_BASE2		(OMAP44XX_L4_PER_BASE + 0x72000)
-#define I2C_BASE3		(OMAP44XX_L4_PER_BASE + 0x60000)
-
-/* MUSB base */
-#define MUSB_BASE		(OMAP44XX_L4_CORE_BASE + 0xAB000)
-
-#endif /* _CPU_H */
diff --git a/arch/arm/include/asm/arch-omap4/i2c.h b/arch/arm/include/asm/arch-omap4/i2c.h
deleted file mode 100644
index a91b4c2..0000000
--- a/arch/arm/include/asm/arch-omap4/i2c.h
+++ /dev/null
@@ -1,74 +0,0 @@
-/*
- * (C) Copyright 2004-2010
- * Texas Instruments, <www.ti.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-#ifndef _OMAP4_I2C_H_
-#define _OMAP4_I2C_H_
-
-#define I2C_BUS_MAX	3
-#define I2C_DEFAULT_BASE	I2C_BASE1
-
-struct i2c {
-	unsigned short revnb_lo;	/* 0x00 */
-	unsigned short res1;
-	unsigned short revnb_hi;	/* 0x04 */
-	unsigned short res2[13];
-	unsigned short sysc;		/* 0x20 */
-	unsigned short res3;
-	unsigned short irqstatus_raw;	/* 0x24 */
-	unsigned short res4;
-	unsigned short stat;		/* 0x28 */
-	unsigned short res5;
-	unsigned short ie;		/* 0x2C */
-	unsigned short res6;
-	unsigned short irqenable_clr;	/* 0x30 */
-	unsigned short res7;
-	unsigned short iv;		/* 0x34 */
-	unsigned short res8[45];
-	unsigned short syss;		/* 0x90 */
-	unsigned short res9;
-	unsigned short buf;		/* 0x94 */
-	unsigned short res10;
-	unsigned short cnt;		/* 0x98 */
-	unsigned short res11;
-	unsigned short data;		/* 0x9C */
-	unsigned short res13;
-	unsigned short res14;		/* 0xA0 */
-	unsigned short res15;
-	unsigned short con;		/* 0xA4 */
-	unsigned short res16;
-	unsigned short oa;		/* 0xA8 */
-	unsigned short res17;
-	unsigned short sa;		/* 0xAC */
-	unsigned short res18;
-	unsigned short psc;		/* 0xB0 */
-	unsigned short res19;
-	unsigned short scll;		/* 0xB4 */
-	unsigned short res20;
-	unsigned short sclh;		/* 0xB8 */
-	unsigned short res21;
-	unsigned short systest;		/* 0xBC */
-	unsigned short res22;
-	unsigned short bufstat;		/* 0xC0 */
-	unsigned short res23;
-};
-
-#endif /* _OMAP4_I2C_H_ */
diff --git a/arch/arm/include/asm/arch-omap4/mmc_host_def.h b/arch/arm/include/asm/arch-omap4/mmc_host_def.h
deleted file mode 100644
index 733d8ed..0000000
--- a/arch/arm/include/asm/arch-omap4/mmc_host_def.h
+++ /dev/null
@@ -1,181 +0,0 @@
-/*
- * (C) Copyright 2010
- * Texas Instruments, <www.ti.com>
- * Syed Mohammed Khasim <khasim@ti.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation's version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef MMC_HOST_DEF_H
-#define MMC_HOST_DEF_H
-
-/*
- * OMAP HSMMC register definitions
- */
-
-#define OMAP_HSMMC1_BASE	0x4809C100
-#define OMAP_HSMMC2_BASE	0x480B4100
-#define OMAP_HSMMC3_BASE	0x480AD100
-
-typedef struct hsmmc {
-	unsigned char res1[0x10];
-	unsigned int sysconfig;		/* 0x10 */
-	unsigned int sysstatus;		/* 0x14 */
-	unsigned char res2[0x14];
-	unsigned int con;		/* 0x2C */
-	unsigned char res3[0xD4];
-	unsigned int blk;		/* 0x104 */
-	unsigned int arg;		/* 0x108 */
-	unsigned int cmd;		/* 0x10C */
-	unsigned int rsp10;		/* 0x110 */
-	unsigned int rsp32;		/* 0x114 */
-	unsigned int rsp54;		/* 0x118 */
-	unsigned int rsp76;		/* 0x11C */
-	unsigned int data;		/* 0x120 */
-	unsigned int pstate;		/* 0x124 */
-	unsigned int hctl;		/* 0x128 */
-	unsigned int sysctl;		/* 0x12C */
-	unsigned int stat;		/* 0x130 */
-	unsigned int ie;		/* 0x134 */
-	unsigned char res4[0x8];
-	unsigned int capa;		/* 0x140 */
-} hsmmc_t;
-
-/*
- * OMAP HS MMC Bit definitions
- */
-#define MMC_SOFTRESET			(0x1 << 1)
-#define RESETDONE			(0x1 << 0)
-#define NOOPENDRAIN			(0x0 << 0)
-#define OPENDRAIN			(0x1 << 0)
-#define OD				(0x1 << 0)
-#define INIT_NOINIT			(0x0 << 1)
-#define INIT_INITSTREAM			(0x1 << 1)
-#define HR_NOHOSTRESP			(0x0 << 2)
-#define STR_BLOCK			(0x0 << 3)
-#define MODE_FUNC			(0x0 << 4)
-#define DW8_1_4BITMODE			(0x0 << 5)
-#define MIT_CTO				(0x0 << 6)
-#define CDP_ACTIVEHIGH			(0x0 << 7)
-#define WPP_ACTIVEHIGH			(0x0 << 8)
-#define RESERVED_MASK			(0x3 << 9)
-#define CTPL_MMC_SD			(0x0 << 11)
-#define BLEN_512BYTESLEN		(0x200 << 0)
-#define NBLK_STPCNT			(0x0 << 16)
-#define DE_DISABLE			(0x0 << 0)
-#define BCE_DISABLE			(0x0 << 1)
-#define BCE_ENABLE			(0x1 << 1)
-#define ACEN_DISABLE			(0x0 << 2)
-#define DDIR_OFFSET			(4)
-#define DDIR_MASK			(0x1 << 4)
-#define DDIR_WRITE			(0x0 << 4)
-#define DDIR_READ			(0x1 << 4)
-#define MSBS_SGLEBLK			(0x0 << 5)
-#define MSBS_MULTIBLK			(0x1 << 5)
-#define RSP_TYPE_OFFSET			(16)
-#define RSP_TYPE_MASK			(0x3 << 16)
-#define RSP_TYPE_NORSP			(0x0 << 16)
-#define RSP_TYPE_LGHT136		(0x1 << 16)
-#define RSP_TYPE_LGHT48			(0x2 << 16)
-#define RSP_TYPE_LGHT48B		(0x3 << 16)
-#define CCCE_NOCHECK			(0x0 << 19)
-#define CCCE_CHECK			(0x1 << 19)
-#define CICE_NOCHECK			(0x0 << 20)
-#define CICE_CHECK			(0x1 << 20)
-#define DP_OFFSET			(21)
-#define DP_MASK				(0x1 << 21)
-#define DP_NO_DATA			(0x0 << 21)
-#define DP_DATA				(0x1 << 21)
-#define CMD_TYPE_NORMAL			(0x0 << 22)
-#define INDEX_OFFSET			(24)
-#define INDEX_MASK			(0x3f << 24)
-#define INDEX(i)			(i << 24)
-#define DATI_MASK			(0x1 << 1)
-#define DATI_CMDDIS			(0x1 << 1)
-#define DTW_1_BITMODE			(0x0 << 1)
-#define DTW_4_BITMODE			(0x1 << 1)
-#define DTW_8_BITMODE                   (0x1 << 5) /* CON[DW8]*/
-#define SDBP_PWROFF			(0x0 << 8)
-#define SDBP_PWRON			(0x1 << 8)
-#define SDVS_1V8			(0x5 << 9)
-#define SDVS_3V0			(0x6 << 9)
-#define ICE_MASK			(0x1 << 0)
-#define ICE_STOP			(0x0 << 0)
-#define ICS_MASK			(0x1 << 1)
-#define ICS_NOTREADY			(0x0 << 1)
-#define ICE_OSCILLATE			(0x1 << 0)
-#define CEN_MASK			(0x1 << 2)
-#define CEN_DISABLE			(0x0 << 2)
-#define CEN_ENABLE			(0x1 << 2)
-#define CLKD_OFFSET			(6)
-#define CLKD_MASK			(0x3FF << 6)
-#define DTO_MASK			(0xF << 16)
-#define DTO_15THDTO			(0xE << 16)
-#define SOFTRESETALL			(0x1 << 24)
-#define CC_MASK				(0x1 << 0)
-#define TC_MASK				(0x1 << 1)
-#define BWR_MASK			(0x1 << 4)
-#define BRR_MASK			(0x1 << 5)
-#define ERRI_MASK			(0x1 << 15)
-#define IE_CC				(0x01 << 0)
-#define IE_TC				(0x01 << 1)
-#define IE_BWR				(0x01 << 4)
-#define IE_BRR				(0x01 << 5)
-#define IE_CTO				(0x01 << 16)
-#define IE_CCRC				(0x01 << 17)
-#define IE_CEB				(0x01 << 18)
-#define IE_CIE				(0x01 << 19)
-#define IE_DTO				(0x01 << 20)
-#define IE_DCRC				(0x01 << 21)
-#define IE_DEB				(0x01 << 22)
-#define IE_CERR				(0x01 << 28)
-#define IE_BADA				(0x01 << 29)
-
-#define VS30_3V0SUP			(1 << 25)
-#define VS18_1V8SUP			(1 << 26)
-
-/* Driver definitions */
-#define MMCSD_SECTOR_SIZE		512
-#define MMC_CARD			0
-#define SD_CARD				1
-#define BYTE_MODE			0
-#define SECTOR_MODE			1
-#define CLK_INITSEQ			0
-#define CLK_400KHZ			1
-#define CLK_MISC			2
-
-typedef struct {
-	unsigned int card_type;
-	unsigned int version;
-	unsigned int mode;
-	unsigned int size;
-	unsigned int RCA;
-} mmc_card_data;
-#define RSP_TYPE_NONE	(RSP_TYPE_NORSP   | CCCE_NOCHECK | CICE_NOCHECK)
-#define MMC_CMD0	(INDEX(0)  | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE)
-
-/* Clock Configurations and Macros */
-#define MMC_CLOCK_REFERENCE	96 /* MHz */
-
-#define mmc_reg_out(addr, mask, val)\
-	writel((readl(addr) & (~(mask))) | ((val) & (mask)), (addr))
-
-int omap_mmc_init(int dev_index);
-
-#endif /* MMC_HOST_DEF_H */
diff --git a/arch/arm/include/asm/arch-omap4/mux_omap4.h b/arch/arm/include/asm/arch-omap4/mux_omap4.h
deleted file mode 100644
index 019574b..0000000
--- a/arch/arm/include/asm/arch-omap4/mux_omap4.h
+++ /dev/null
@@ -1,344 +0,0 @@
-/*
- * (C) Copyright 2004-2009
- * Texas Instruments Incorporated
- * Richard Woodruff		<r-woodruff2@ti.com>
- * Aneesh V			<aneesh@ti.com>
- * Balaji Krishnamoorthy	<balajitk@ti.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-#ifndef _MUX_OMAP4_H_
-#define _MUX_OMAP4_H_
-
-#include <asm/types.h>
-
-struct pad_conf_entry {
-
-	u16 offset;
-
-	u16 val;
-
-} __attribute__ ((packed));
-
-#ifdef CONFIG_OFF_PADCONF
-#define OFF_PD          (1 << 12)
-#define OFF_PU          (3 << 12)
-#define OFF_OUT_PTD     (0 << 10)
-#define OFF_OUT_PTU     (2 << 10)
-#define OFF_IN          (1 << 10)
-#define OFF_OUT         (0 << 10)
-#define OFF_EN          (1 << 9)
-#else
-#define OFF_PD          (0 << 12)
-#define OFF_PU          (0 << 12)
-#define OFF_OUT_PTD     (0 << 10)
-#define OFF_OUT_PTU     (0 << 10)
-#define OFF_IN          (0 << 10)
-#define OFF_OUT         (0 << 10)
-#define OFF_EN          (0 << 9)
-#endif
-
-#define IEN             (1 << 8)
-#define IDIS            (0 << 8)
-#define PTU             (3 << 3)
-#define PTD             (1 << 3)
-#define EN              (1 << 3)
-#define DIS             (0 << 3)
-
-#define M0              0
-#define M1              1
-#define M2              2
-#define M3              3
-#define M4              4
-#define M5              5
-#define M6              6
-#define M7              7
-
-#define SAFE_MODE	M7
-
-#ifdef CONFIG_OFF_PADCONF
-#define OFF_IN_PD       (OFF_PD | OFF_IN | OFF_EN)
-#define OFF_IN_PU       (OFF_PU | OFF_IN | OFF_EN)
-#define OFF_OUT_PD      (OFF_OUT_PTD | OFF_OUT | OFF_EN)
-#define OFF_OUT_PU      (OFF_OUT_PTU | OFF_OUT | OFF_EN)
-#else
-#define OFF_IN_PD       0
-#define OFF_IN_PU       0
-#define OFF_OUT_PD      0
-#define OFF_OUT_PU      0
-#endif
-
-#define CORE_REVISION		0x0000
-#define CORE_HWINFO		0x0004
-#define CORE_SYSCONFIG		0x0010
-#define GPMC_AD0		0x0040
-#define GPMC_AD1		0x0042
-#define GPMC_AD2		0x0044
-#define GPMC_AD3		0x0046
-#define GPMC_AD4		0x0048
-#define GPMC_AD5		0x004A
-#define GPMC_AD6		0x004C
-#define GPMC_AD7		0x004E
-#define GPMC_AD8		0x0050
-#define GPMC_AD9		0x0052
-#define GPMC_AD10		0x0054
-#define GPMC_AD11		0x0056
-#define GPMC_AD12		0x0058
-#define GPMC_AD13		0x005A
-#define GPMC_AD14		0x005C
-#define GPMC_AD15		0x005E
-#define GPMC_A16		0x0060
-#define GPMC_A17		0x0062
-#define GPMC_A18		0x0064
-#define GPMC_A19		0x0066
-#define GPMC_A20		0x0068
-#define GPMC_A21		0x006A
-#define GPMC_A22		0x006C
-#define GPMC_A23		0x006E
-#define GPMC_A24		0x0070
-#define GPMC_A25		0x0072
-#define GPMC_NCS0		0x0074
-#define GPMC_NCS1		0x0076
-#define GPMC_NCS2		0x0078
-#define GPMC_NCS3		0x007A
-#define GPMC_NWP		0x007C
-#define GPMC_CLK		0x007E
-#define GPMC_NADV_ALE		0x0080
-#define GPMC_NOE		0x0082
-#define GPMC_NWE		0x0084
-#define GPMC_NBE0_CLE		0x0086
-#define GPMC_NBE1		0x0088
-#define GPMC_WAIT0		0x008A
-#define GPMC_WAIT1		0x008C
-#define C2C_DATA11		0x008E
-#define C2C_DATA12		0x0090
-#define C2C_DATA13		0x0092
-#define C2C_DATA14		0x0094
-#define C2C_DATA15		0x0096
-#define HDMI_HPD		0x0098
-#define HDMI_CEC		0x009A
-#define HDMI_DDC_SCL		0x009C
-#define HDMI_DDC_SDA		0x009E
-#define CSI21_DX0		0x00A0
-#define CSI21_DY0		0x00A2
-#define CSI21_DX1		0x00A4
-#define CSI21_DY1		0x00A6
-#define CSI21_DX2		0x00A8
-#define CSI21_DY2		0x00AA
-#define CSI21_DX3		0x00AC
-#define CSI21_DY3		0x00AE
-#define CSI21_DX4		0x00B0
-#define CSI21_DY4		0x00B2
-#define CSI22_DX0		0x00B4
-#define CSI22_DY0		0x00B6
-#define CSI22_DX1		0x00B8
-#define CSI22_DY1		0x00BA
-#define CAM_SHUTTER		0x00BC
-#define CAM_STROBE		0x00BE
-#define CAM_GLOBALRESET		0x00C0
-#define USBB1_ULPITLL_CLK	0x00C2
-#define USBB1_ULPITLL_STP	0x00C4
-#define USBB1_ULPITLL_DIR	0x00C6
-#define USBB1_ULPITLL_NXT	0x00C8
-#define USBB1_ULPITLL_DAT0	0x00CA
-#define USBB1_ULPITLL_DAT1	0x00CC
-#define USBB1_ULPITLL_DAT2	0x00CE
-#define USBB1_ULPITLL_DAT3	0x00D0
-#define USBB1_ULPITLL_DAT4	0x00D2
-#define USBB1_ULPITLL_DAT5	0x00D4
-#define USBB1_ULPITLL_DAT6	0x00D6
-#define USBB1_ULPITLL_DAT7	0x00D8
-#define USBB1_HSIC_DATA		0x00DA
-#define USBB1_HSIC_STROBE	0x00DC
-#define USBC1_ICUSB_DP		0x00DE
-#define USBC1_ICUSB_DM		0x00E0
-#define SDMMC1_CLK		0x00E2
-#define SDMMC1_CMD		0x00E4
-#define SDMMC1_DAT0		0x00E6
-#define SDMMC1_DAT1		0x00E8
-#define SDMMC1_DAT2		0x00EA
-#define SDMMC1_DAT3		0x00EC
-#define SDMMC1_DAT4		0x00EE
-#define SDMMC1_DAT5		0x00F0
-#define SDMMC1_DAT6		0x00F2
-#define SDMMC1_DAT7		0x00F4
-#define ABE_MCBSP2_CLKX		0x00F6
-#define ABE_MCBSP2_DR		0x00F8
-#define ABE_MCBSP2_DX		0x00FA
-#define ABE_MCBSP2_FSX		0x00FC
-#define ABE_MCBSP1_CLKX		0x00FE
-#define ABE_MCBSP1_DR		0x0100
-#define ABE_MCBSP1_DX		0x0102
-#define ABE_MCBSP1_FSX		0x0104
-#define ABE_PDM_UL_DATA		0x0106
-#define ABE_PDM_DL_DATA		0x0108
-#define ABE_PDM_FRAME		0x010A
-#define ABE_PDM_LB_CLK		0x010C
-#define ABE_CLKS		0x010E
-#define ABE_DMIC_CLK1		0x0110
-#define ABE_DMIC_DIN1		0x0112
-#define ABE_DMIC_DIN2		0x0114
-#define ABE_DMIC_DIN3		0x0116
-#define UART2_CTS		0x0118
-#define UART2_RTS		0x011A
-#define UART2_RX		0x011C
-#define UART2_TX		0x011E
-#define HDQ_SIO			0x0120
-#define I2C1_SCL		0x0122
-#define I2C1_SDA		0x0124
-#define I2C2_SCL		0x0126
-#define I2C2_SDA		0x0128
-#define I2C3_SCL		0x012A
-#define I2C3_SDA		0x012C
-#define I2C4_SCL		0x012E
-#define I2C4_SDA		0x0130
-#define MCSPI1_CLK		0x0132
-#define MCSPI1_SOMI		0x0134
-#define MCSPI1_SIMO		0x0136
-#define MCSPI1_CS0		0x0138
-#define MCSPI1_CS1		0x013A
-#define MCSPI1_CS2		0x013C
-#define MCSPI1_CS3		0x013E
-#define UART3_CTS_RCTX		0x0140
-#define UART3_RTS_SD		0x0142
-#define UART3_RX_IRRX		0x0144
-#define UART3_TX_IRTX		0x0146
-#define SDMMC5_CLK		0x0148
-#define SDMMC5_CMD		0x014A
-#define SDMMC5_DAT0		0x014C
-#define SDMMC5_DAT1		0x014E
-#define SDMMC5_DAT2		0x0150
-#define SDMMC5_DAT3		0x0152
-#define MCSPI4_CLK		0x0154
-#define MCSPI4_SIMO		0x0156
-#define MCSPI4_SOMI		0x0158
-#define MCSPI4_CS0		0x015A
-#define UART4_RX		0x015C
-#define UART4_TX		0x015E
-#define USBB2_ULPITLL_CLK	0x0160
-#define USBB2_ULPITLL_STP	0x0162
-#define USBB2_ULPITLL_DIR	0x0164
-#define USBB2_ULPITLL_NXT	0x0166
-#define USBB2_ULPITLL_DAT0	0x0168
-#define USBB2_ULPITLL_DAT1	0x016A
-#define USBB2_ULPITLL_DAT2	0x016C
-#define USBB2_ULPITLL_DAT3	0x016E
-#define USBB2_ULPITLL_DAT4	0x0170
-#define USBB2_ULPITLL_DAT5	0x0172
-#define USBB2_ULPITLL_DAT6	0x0174
-#define USBB2_ULPITLL_DAT7	0x0176
-#define USBB2_HSIC_DATA		0x0178
-#define USBB2_HSIC_STROBE	0x017A
-#define UNIPRO_TX0		0x017C
-#define UNIPRO_TY0		0x017E
-#define UNIPRO_TX1		0x0180
-#define UNIPRO_TY1		0x0182
-#define UNIPRO_TX2		0x0184
-#define UNIPRO_TY2		0x0186
-#define UNIPRO_RX0		0x0188
-#define UNIPRO_RY0		0x018A
-#define UNIPRO_RX1		0x018C
-#define UNIPRO_RY1		0x018E
-#define UNIPRO_RX2		0x0190
-#define UNIPRO_RY2		0x0192
-#define USBA0_OTG_CE		0x0194
-#define USBA0_OTG_DP		0x0196
-#define USBA0_OTG_DM		0x0198
-#define FREF_CLK1_OUT		0x019A
-#define FREF_CLK2_OUT		0x019C
-#define SYS_NIRQ1		0x019E
-#define SYS_NIRQ2		0x01A0
-#define SYS_BOOT0		0x01A2
-#define SYS_BOOT1		0x01A4
-#define SYS_BOOT2		0x01A6
-#define SYS_BOOT3		0x01A8
-#define SYS_BOOT4		0x01AA
-#define SYS_BOOT5		0x01AC
-#define DPM_EMU0		0x01AE
-#define DPM_EMU1		0x01B0
-#define DPM_EMU2		0x01B2
-#define DPM_EMU3		0x01B4
-#define DPM_EMU4		0x01B6
-#define DPM_EMU5		0x01B8
-#define DPM_EMU6		0x01BA
-#define DPM_EMU7		0x01BC
-#define DPM_EMU8		0x01BE
-#define DPM_EMU9		0x01C0
-#define DPM_EMU10		0x01C2
-#define DPM_EMU11		0x01C4
-#define DPM_EMU12		0x01C6
-#define DPM_EMU13		0x01C8
-#define DPM_EMU14		0x01CA
-#define DPM_EMU15		0x01CC
-#define DPM_EMU16		0x01CE
-#define DPM_EMU17		0x01D0
-#define DPM_EMU18		0x01D2
-#define DPM_EMU19		0x01D4
-#define WAKEUPEVENT_0		0x01D8
-#define WAKEUPEVENT_1		0x01DC
-#define WAKEUPEVENT_2		0x01E0
-#define WAKEUPEVENT_3		0x01E4
-#define WAKEUPEVENT_4		0x01E8
-#define WAKEUPEVENT_5		0x01EC
-#define WAKEUPEVENT_6		0x01F0
-
-#define WKUP_REVISION		0x0000
-#define WKUP_HWINFO		0x0004
-#define WKUP_SYSCONFIG		0x0010
-#define PAD0_SIM_IO		0x0040
-#define PAD1_SIM_CLK		0x0042
-#define PAD0_SIM_RESET		0x0044
-#define PAD1_SIM_CD		0x0046
-#define PAD0_SIM_PWRCTRL		0x0048
-#define PAD1_SR_SCL		0x004A
-#define PAD0_SR_SDA		0x004C
-#define PAD1_FREF_XTAL_IN		0x004E
-#define PAD0_FREF_SLICER_IN	0x0050
-#define PAD1_FREF_CLK_IOREQ	0x0052
-#define PAD0_FREF_CLK0_OUT		0x0054
-#define PAD1_FREF_CLK3_REQ		0x0056
-#define PAD0_FREF_CLK3_OUT		0x0058
-#define PAD1_FREF_CLK4_REQ		0x005A
-#define PAD0_FREF_CLK4_OUT		0x005C
-#define PAD1_SYS_32K		0x005E
-#define PAD0_SYS_NRESPWRON		0x0060
-#define PAD1_SYS_NRESWARM		0x0062
-#define PAD0_SYS_PWR_REQ		0x0064
-#define PAD1_SYS_PWRON_RESET	0x0066
-#define PAD0_SYS_BOOT6		0x0068
-#define PAD1_SYS_BOOT7		0x006A
-#define PAD0_JTAG_NTRST		0x006C
-#define PAD1_JTAG_TCK		0x006D
-#define PAD0_JTAG_RTCK		0x0070
-#define PAD1_JTAG_TMS_TMSC		0x0072
-#define PAD0_JTAG_TDI		0x0074
-#define PAD1_JTAG_TDO		0x0076
-#define PADCONF_WAKEUPEVENT_0	0x007C
-#define CONTROL_SMART1NOPMIO_PADCONF_0		0x05A0
-#define CONTROL_SMART1NOPMIO_PADCONF_1		0x05A4
-#define PADCONF_MODE		0x05A8
-#define CONTROL_XTAL_OSCILLATOR			0x05AC
-#define CONTROL_CONTROL_I2C_2			0x0604
-#define CONTROL_CONTROL_JTAG			0x0608
-#define CONTROL_CONTROL_SYS			0x060C
-#define CONTROL_SPARE_RW		0x0614
-#define CONTROL_SPARE_R		0x0618
-#define CONTROL_SPARE_R_C0		0x061C
-
-#endif /* _MUX_OMAP4_H_ */
diff --git a/arch/arm/include/asm/arch-omap4/omap4.h b/arch/arm/include/asm/arch-omap4/omap4.h
deleted file mode 100644
index a30bb33..0000000
--- a/arch/arm/include/asm/arch-omap4/omap4.h
+++ /dev/null
@@ -1,131 +0,0 @@
-/*
- * (C) Copyright 2010
- * Texas Instruments, <www.ti.com>
- *
- * Authors:
- *	Aneesh V <aneesh@ti.com>
- *
- * Derived from OMAP3 work by
- *	Richard Woodruff <r-woodruff2@ti.com>
- *	Syed Mohammed Khasim <x0khasim@ti.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef _OMAP4_H_
-#define _OMAP4_H_
-
-#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
-#include <asm/types.h>
-#endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */
-
-/*
- * L4 Peripherals - L4 Wakeup and L4 Core now
- */
-#define OMAP44XX_L4_CORE_BASE	0x4A000000
-#define OMAP44XX_L4_WKUP_BASE	0x4A300000
-#define OMAP44XX_L4_PER_BASE	0x48000000
-
-#define OMAP44XX_DRAM_ADDR_SPACE_START	0x80000000
-#define OMAP44XX_DRAM_ADDR_SPACE_END	0xD0000000
-
-
-/* CONTROL */
-#define CTRL_BASE		(OMAP44XX_L4_CORE_BASE + 0x2000)
-#define CONTROL_PADCONF_CORE	(OMAP44XX_L4_CORE_BASE + 0x100000)
-#define CONTROL_PADCONF_WKUP	(OMAP44XX_L4_CORE_BASE + 0x31E000)
-
-/* UART */
-#define UART1_BASE		(OMAP44XX_L4_PER_BASE + 0x6a000)
-#define UART2_BASE		(OMAP44XX_L4_PER_BASE + 0x6c000)
-#define UART3_BASE		(OMAP44XX_L4_PER_BASE + 0x20000)
-
-/* General Purpose Timers */
-#define GPT1_BASE		(OMAP44XX_L4_WKUP_BASE + 0x18000)
-#define GPT2_BASE		(OMAP44XX_L4_PER_BASE  + 0x32000)
-#define GPT3_BASE		(OMAP44XX_L4_PER_BASE  + 0x34000)
-
-/* Watchdog Timer2 - MPU watchdog */
-#define WDT2_BASE		(OMAP44XX_L4_WKUP_BASE + 0x14000)
-
-/* 32KTIMER */
-#define SYNC_32KTIMER_BASE	(OMAP44XX_L4_WKUP_BASE + 0x4000)
-
-/* GPMC */
-#define OMAP44XX_GPMC_BASE	0x50000000
-
-/* DMM */
-#define OMAP44XX_DMM_BASE		0x4E000000
-#define DMM_LISA_MAP_BASE		(OMAP44XX_DMM_BASE + 0x40)
-#define DMM_LISA_MAP_SYS_SIZE_MASK	(7 << 20)
-#define DMM_LISA_MAP_SYS_SIZE_SHIFT	20
-#define DMM_LISA_MAP_SYS_ADDR_MASK	(0xFF << 24)
-/*
- * Hardware Register Details
- */
-
-/* Watchdog Timer */
-#define WD_UNLOCK1		0xAAAA
-#define WD_UNLOCK2		0x5555
-
-/* GP Timer */
-#define TCLR_ST			(0x1 << 0)
-#define TCLR_AR			(0x1 << 1)
-#define TCLR_PRE		(0x1 << 5)
-
-/*
- * PRCM
- */
-
-/* PRM */
-#define PRM_BASE		0x4A306000
-#define PRM_DEVICE_BASE		(PRM_BASE + 0x1B00)
-
-#define PRM_RSTCTRL		PRM_DEVICE_BASE
-#define PRM_RSTCTRL_RESET	0x01
-
-#ifndef __ASSEMBLY__
-
-struct s32ktimer {
-	unsigned char res[0x10];
-	unsigned int s32k_cr;	/* 0x10 */
-};
-
-#endif /* __ASSEMBLY__ */
-
-/*
- * Non-secure SRAM Addresses
- * Non-secure RAM starts at 0x40300000 for GP devices. But we keep SRAM_BASE
- * at 0x40304000(EMU base) so that our code works for both EMU and GP
- */
-#define NON_SECURE_SRAM_START	0x40304000
-#define NON_SECURE_SRAM_END	0x4030E000	/* Not inclusive */
-/* base address for indirect vectors (internal boot mode) */
-#define SRAM_ROM_VECT_BASE	0x4030D000
-/* Temporary SRAM stack used while low level init is done */
-#define LOW_LEVEL_SRAM_STACK	NON_SECURE_SRAM_END
-
-/*
- * OMAP4 real hardware:
- * TODO: Change this to the IDCODE in the hw regsiter
- */
-#define CPU_OMAP4430_ES10	1
-#define CPU_OMAP4430_ES20	2
-
-#endif
diff --git a/arch/arm/include/asm/arch-omap4/sys_proto.h b/arch/arm/include/asm/arch-omap4/sys_proto.h
deleted file mode 100644
index 4813e9e..0000000
--- a/arch/arm/include/asm/arch-omap4/sys_proto.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * (C) Copyright 2010
- * Texas Instruments, <www.ti.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef _SYS_PROTO_H_
-#define _SYS_PROTO_H_
-
-#include <asm/arch/omap4.h>
-#include <asm/io.h>
-
-struct omap_sysinfo {
-	char *board_string;
-};
-
-void gpmc_init(void);
-void watchdog_init(void);
-u32 get_device_type(void);
-void invalidate_dcache(u32);
-void set_muxconf_regs(void);
-void sr32(void *, u32, u32, u32);
-u32 wait_on_value(u32, u32, void *, u32);
-void sdelay(unsigned long);
-
-extern const struct omap_sysinfo sysinfo;
-
-#endif
diff --git a/arch/arm/include/asm/arch-orion5x/cpu.h b/arch/arm/include/asm/arch-orion5x/cpu.h
deleted file mode 100644
index c84efaf..0000000
--- a/arch/arm/include/asm/arch-orion5x/cpu.h
+++ /dev/null
@@ -1,260 +0,0 @@
-/*
- * Copyright (C) 2010 Albert ARIBAUD <albert.aribaud@free.fr>
- *
- * Based on original Kirorion5x_ood support which is
- * (C) Copyright 2009
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-#ifndef _ORION5X_CPU_H
-#define _ORION5X_CPU_H
-
-#include <asm/system.h>
-
-#ifndef __ASSEMBLY__
-
-#define ORION5X_CPU_WIN_CTRL_DATA(size, target, attr, en) (en | (target << 4) \
-			| (attr << 8) | (orion5x_winctrl_calcsize(size) << 16))
-
-#define ORION5XGBE_PORT_SERIAL_CONTROL1_REG(_x)	\
-		((_x ? ORION5X_EGIGA0_BASE : ORION5X_EGIGA1_BASE) + 0x44c)
-
-enum memory_bank {
-	BANK0,
-	BANK1,
-	BANK2,
-	BANK3
-};
-
-enum orion5x_cpu_winen {
-	ORION5X_WIN_DISABLE,
-	ORION5X_WIN_ENABLE
-};
-
-enum orion5x_cpu_target {
-	ORION5X_TARGET_DRAM = 0,
-	ORION5X_TARGET_DEVICE = 1,
-	ORION5X_TARGET_PCI = 3,
-	ORION5X_TARGET_PCIE = 4,
-	ORION5X_TARGET_SASRAM = 9
-};
-
-enum orion5x_cpu_attrib {
-	ORION5X_ATTR_DRAM_CS0 = 0x0e,
-	ORION5X_ATTR_DRAM_CS1 = 0x0d,
-	ORION5X_ATTR_DRAM_CS2 = 0x0b,
-	ORION5X_ATTR_DRAM_CS3 = 0x07,
-	ORION5X_ATTR_PCI_MEM = 0x59,
-	ORION5X_ATTR_PCI_IO = 0x51,
-	ORION5X_ATTR_PCIE_MEM = 0x59,
-	ORION5X_ATTR_PCIE_IO = 0x51,
-	ORION5X_ATTR_SASRAM = 0x00,
-	ORION5X_ATTR_DEV_CS0 = 0x1e,
-	ORION5X_ATTR_DEV_CS1 = 0x1d,
-	ORION5X_ATTR_DEV_CS2 = 0x1b,
-	ORION5X_ATTR_BOOTROM = 0x0f
-};
-
-/*
- * Device Address MAP BAR values
- *
- * All addresses and sizes not defined by board code
- * will be given default values here.
- */
-
-#if !defined (ORION5X_ADR_PCIE_MEM)
-#define ORION5X_ADR_PCIE_MEM	0x90000000
-#endif
-
-#if !defined (ORION5X_ADR_PCIE_MEM_REMAP_LO)
-#define ORION5X_ADR_PCIE_MEM_REMAP_LO	0x90000000
-#endif
-
-#if !defined (ORION5X_ADR_PCIE_MEM_REMAP_HI)
-#define ORION5X_ADR_PCIE_MEM_REMAP_HI	0
-#endif
-
-#if !defined (ORION5X_SZ_PCIE_MEM)
-#define ORION5X_SZ_PCIE_MEM	(128*1024*1024)
-#endif
-
-#if !defined (ORION5X_ADR_PCIE_IO)
-#define ORION5X_ADR_PCIE_IO	0xf0000000
-#endif
-
-#if !defined (ORION5X_ADR_PCIE_IO_REMAP_LO)
-#define ORION5X_ADR_PCIE_IO_REMAP_LO	0x90000000
-#endif
-
-#if !defined (ORION5X_ADR_PCIE_IO_REMAP_HI)
-#define ORION5X_ADR_PCIE_IO_REMAP_HI	0
-#endif
-
-#if !defined (ORION5X_SZ_PCIE_IO)
-#define ORION5X_SZ_PCIE_IO	(64*1024)
-#endif
-
-#if !defined (ORION5X_ADR_PCI_MEM)
-#define ORION5X_ADR_PCI_MEM	0x98000000
-#endif
-
-#if !defined (ORION5X_SZ_PCI_MEM)
-#define ORION5X_SZ_PCI_MEM	(128*1024*1024)
-#endif
-
-#if !defined (ORION5X_ADR_PCI_IO)
-#define ORION5X_ADR_PCI_IO	0xf0100000
-#endif
-
-#if !defined (ORION5X_SZ_PCI_IO)
-#define ORION5X_SZ_PCI_IO	(64*1024)
-#endif
-
-#if !defined (ORION5X_ADR_DEV_CS0)
-#define ORION5X_ADR_DEV_CS0	0xfa000000
-#endif
-
-#if !defined (ORION5X_SZ_DEV_CS0)
-#define ORION5X_SZ_DEV_CS0	(2*1024*1024)
-#endif
-
-#if !defined (ORION5X_ADR_DEV_CS1)
-#define ORION5X_ADR_DEV_CS1	0xf8000000
-#endif
-
-#if !defined (ORION5X_SZ_DEV_CS1)
-#define ORION5X_SZ_DEV_CS1	(32*1024*1024)
-#endif
-
-#if !defined (ORION5X_ADR_DEV_CS2)
-#define ORION5X_ADR_DEV_CS2	0xfa800000
-#endif
-
-#if !defined (ORION5X_SZ_DEV_CS2)
-#define ORION5X_SZ_DEV_CS2	(1*1024*1024)
-#endif
-
-#if !defined (ORION5X_ADR_BOOTROM)
-#define ORION5X_ADR_BOOTROM	0xFFF80000
-#endif
-
-#if !defined (ORION5X_SZ_BOOTROM)
-#define ORION5X_SZ_BOOTROM	(512*1024)
-#endif
-
-/*
- * PCIE registers are used for SoC device ID and revision
- */
-#define PCIE_DEV_ID_OFF         (ORION5X_REG_PCIE_BASE + 0x0000)
-#define PCIE_DEV_REV_OFF        (ORION5X_REG_PCIE_BASE + 0x0008)
-
-/*
- * The following definitions are intended for identifying
- * the real device and revision on which u-boot is running
- * even if it was compiled only for a specific one. Thus,
- * these constants must not be considered chip-specific.
- */
-
-/* Orion-1 (88F5181) and Orion-VoIP (88F5181L) */
-#define MV88F5181_DEV_ID        0x5181
-#define MV88F5181_REV_B1        3
-#define MV88F5181L_REV_A0       8
-#define MV88F5181L_REV_A1       9
-/* Orion-NAS (88F5182) */
-#define MV88F5182_DEV_ID        0x5182
-#define MV88F5182_REV_A2        2
-/* Orion-2 (88F5281) */
-#define MV88F5281_DEV_ID        0x5281
-#define MV88F5281_REV_D0        4
-#define MV88F5281_REV_D1        5
-#define MV88F5281_REV_D2        6
-/* Orion-1-90 (88F6183) */
-#define MV88F6183_DEV_ID        0x6183
-#define MV88F6183_REV_B0        3
-
-/*
- * read feroceon core extra feature register
- * using co-proc instruction
- */
-static inline unsigned int readfr_extra_feature_reg(void)
-{
-	unsigned int val;
-	asm volatile ("mrc p15, 1, %0, c15, c1, 0 @ readfr exfr" : "=r"
-			(val) : : "cc");
-	return val;
-}
-
-/*
- * write feroceon core extra feature register
- * using co-proc instruction
- */
-static inline void writefr_extra_feature_reg(unsigned int val)
-{
-	asm volatile ("mcr p15, 1, %0, c15, c1, 0 @ writefr exfr" : : "r"
-			(val) : "cc");
-	isb();
-}
-
-/*
- * AHB to Mbus Bridge Registers
- * Source: 88F5182 User Manual, Appendix A, section A.4
- * Note: only windows 0 and 1 have remap capability.
- */
-struct orion5x_win_registers {
-	u32 ctrl;
-	u32 base;
-	u32 remap_lo;
-	u32 remap_hi;
-};
-
-/*
- * CPU control and status Registers
- * Source: 88F5182 User Manual, Appendix A, section A.4
- */
-struct orion5x_cpu_registers {
-	u32 config;	/*0x20100 */
-	u32 ctrl_stat;	/*0x20104 */
-	u32 rstoutn_mask; /* 0x20108 */
-	u32 sys_soft_rst; /* 0x2010C */
-	u32 ahb_mbus_cause_irq; /* 0x20110 */
-	u32 ahb_mbus_mask_irq; /* 0x20114 */
-};
-
-/*
- * DDR SDRAM Controller Address Decode Registers
- * Source: 88F5182 User Manual, Appendix A, section A.5.1
- */
-struct orion5x_ddr_addr_decode_registers {
-	u32 base;
-	u32 size;
-};
-
-/*
- * functions
- */
-void reset_cpu(unsigned long ignored);
-u32 orion5x_device_id(void);
-u32 orion5x_device_rev(void);
-unsigned int orion5x_winctrl_calcsize(unsigned int sizeval);
-void timer_init_r(void);
-#endif /* __ASSEMBLY__ */
-#endif /* _ORION5X_CPU_H */
diff --git a/arch/arm/include/asm/arch-orion5x/mv88f5182.h b/arch/arm/include/asm/arch-orion5x/mv88f5182.h
deleted file mode 100644
index 86ba08d..0000000
--- a/arch/arm/include/asm/arch-orion5x/mv88f5182.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
- * Copyright (C) 2010 Albert ARIBAUD <albert.aribaud@free.fr>
- *
- * Based on original Kirkwood 88F6182 support which is
- * (C) Copyright 2009
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
- *
- * Header file for Feroceon CPU core 88F5182 SOC.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-#ifndef _CONFIG_88F5182_H
-#define _CONFIG_88F5182_H
-
-/* SOC specific definitions */
-#define F88F5182_REGS_PHYS_BASE		0xf1000000
-#define ORION5X_REGS_PHY_BASE		F88F5182_REGS_PHYS_BASE
-
-/* TCLK Core Clock defination */
-#define CONFIG_SYS_TCLK			166000000 /* 166MHz */
-
-#endif /* _CONFIG_88F5182_H */
diff --git a/arch/arm/include/asm/arch-orion5x/orion5x.h b/arch/arm/include/asm/arch-orion5x/orion5x.h
deleted file mode 100644
index e3d3f76..0000000
--- a/arch/arm/include/asm/arch-orion5x/orion5x.h
+++ /dev/null
@@ -1,76 +0,0 @@
-/*
- * Copyright (C) 2010 Albert ARIBAUD <albert.aribaud@free.fr>
- *
- * Based on original Kirkwood support which is
- * (C) Copyright 2009
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
- *
- * Header file for Marvell's Orion SoC with Feroceon CPU core.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-#ifndef _ASM_ARCH_ORION5X_H
-#define _ASM_ARCH_ORION5X_H
-
-#ifndef __ASSEMBLY__
-#include <asm/types.h>
-#include <asm/io.h>
-#endif /* __ASSEMBLY__ */
-
-#if defined(CONFIG_FEROCEON)
-#include <asm/arch/cpu.h>
-
-/* SOC specific definations */
-#define ORION5X_REGISTER(x)			(ORION5X_REGS_PHY_BASE + x)
-
-/* Documented registers */
-#define ORION5X_TWSI_BASE			(ORION5X_REGISTER(0x11000))
-#define ORION5X_UART0_BASE			(ORION5X_REGISTER(0x12000))
-#define ORION5X_UART1_BASE			(ORION5X_REGISTER(0x12100))
-#define ORION5X_MPP_BASE			(ORION5X_REGISTER(0x10000))
-#define ORION5X_GPIO_BASE			(ORION5X_REGISTER(0x10100))
-#define ORION5X_CPU_WIN_BASE			(ORION5X_REGISTER(0x20000))
-#define ORION5X_CPU_REG_BASE			(ORION5X_REGISTER(0x20100))
-#define ORION5X_TIMER_BASE			(ORION5X_REGISTER(0x20300))
-#define ORION5X_REG_PCI_BASE			(ORION5X_REGISTER(0x30000))
-#define ORION5X_REG_PCIE_BASE			(ORION5X_REGISTER(0x40000))
-#define ORION5X_USB20_PORT0_BASE		(ORION5X_REGISTER(0x50000))
-#define ORION5X_USB20_PORT1_BASE		(ORION5X_REGISTER(0xA0000))
-#define ORION5X_EGIGA_BASE			(ORION5X_REGISTER(0x72000))
-#define ORION5X_SATA_BASE			(ORION5X_REGISTER(0x80000))
-#define ORION5X_SATA_PORT0_OFFSET		0x2000
-#define ORION5X_SATA_PORT1_OFFSET		0x4000
-
-/* Orion5x GbE controller has a single port */
-#define MAX_MVGBE_DEVS	1
-#define MVGBE0_BASE	ORION5X_EGIGA_BASE
-
-#define CONFIG_MAX_RAM_BANK_SIZE		(64*1024*1024)
-
-/* include here SoC variants. 5181, 5281, 6183 should go here when
-   adding support for them, and this comment should then be updated. */
-#if defined(CONFIG_88F5182)
-#include <asm/arch/mv88f5182.h>
-#else
-#error "SOC Name not defined"
-#endif
-#endif /* CONFIG_FEROCEON */
-#endif /* _ASM_ARCH_ORION5X_H */
diff --git a/arch/arm/include/asm/arch-pantheon/config.h b/arch/arm/include/asm/arch-pantheon/config.h
deleted file mode 100644
index 710b386..0000000
--- a/arch/arm/include/asm/arch-pantheon/config.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- * (C) Copyright 2011
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Lei Wen <leiwen@marvell.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-#ifndef _PANTHEON_CONFIG_H
-#define _PANTHEON_CONFIG_H
-
-#define CONFIG_ARM926EJS	1	/* Basic Architecture */
-
-#define CONFIG_SYS_TCLK		(14745600)	/* NS16550 clk config */
-#define CONFIG_SYS_HZ_CLOCK	(3250000)	/* Timer Freq. 3.25MHZ */
-#define CONFIG_MARVELL_MFP			/* Enable mvmfp driver */
-#define MV_MFPR_BASE		PANTHEON_MFPR_BASE
-#define MV_UART_CONSOLE_BASE	PANTHEON_UART1_BASE
-#define CONFIG_SYS_NS16550_IER	(1 << 6)	/* Bit 6 in UART_IER register
-						represents UART Unit Enable */
-
-#endif /* _PANTHEON_CONFIG_H */
diff --git a/arch/arm/include/asm/arch-pantheon/cpu.h b/arch/arm/include/asm/arch-pantheon/cpu.h
deleted file mode 100644
index 30f4393..0000000
--- a/arch/arm/include/asm/arch-pantheon/cpu.h
+++ /dev/null
@@ -1,79 +0,0 @@
-/*
- * (C) Copyright 2011
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Lei Wen <leiwen@marvell.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-#ifndef _PANTHEON_CPU_H
-#define _PANTHEON_CPU_H
-
-#include <asm/io.h>
-#include <asm/system.h>
-
-/*
- * Main Power Management (MPMU) Registers
- * Refer Register Datasheet 9.1
- */
-struct panthmpmu_registers {
-	u8 pad0[0x0024];
-	u32 ccgr;	/*0x0024*/
-	u8 pad1[0x0200 - 0x024 - 4];
-	u32 wdtpcr;	/*0x0200*/
-	u8 pad2[0x1020 - 0x200 - 4];
-	u32 aprr;	/*0x1020*/
-	u32 acgr;	/*0x1024*/
-};
-
-/*
- * APB Clock Reset/Control Registers
- * Refer Register Datasheet 6.14
- */
-struct panthapb_registers {
-	u32 uart0;	/*0x000*/
-	u32 uart1;	/*0x004*/
-	u32 gpio;	/*0x008*/
-	u8 pad0[0x034 - 0x08 - 4];
-	u32 timers;	/*0x034*/
-};
-
-/*
- * CPU Interface Registers
- * Refer Register Datasheet 4.3
- */
-struct panthcpu_registers {
-	u32 chip_id;		/* Chip Id Reg */
-	u32 pad;
-	u32 cpu_conf;		/* CPU Conf Reg */
-	u32 pad1;
-	u32 cpu_sram_spd;	/* CPU SRAM Speed Reg */
-	u32 pad2;
-	u32 cpu_l2c_spd;	/* CPU L2cache Speed Conf */
-	u32 mcb_conf;		/* MCB Conf Reg */
-	u32 sys_boot_ctl;	/* Sytem Boot Control */
-};
-
-/*
- * Functions
- */
-u32 panth_sdram_base(int);
-u32 panth_sdram_size(int);
-
-#endif /* _PANTHEON_CPU_H */
diff --git a/arch/arm/include/asm/arch-pantheon/mfp.h b/arch/arm/include/asm/arch-pantheon/mfp.h
deleted file mode 100644
index fb291cf..0000000
--- a/arch/arm/include/asm/arch-pantheon/mfp.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/*
- * Based on arch/arm/include/asm/arch-armada100/mfp.h
- * (C) Copyright 2011
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Lei Wen <leiwen@marvell.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-#ifndef __PANTHEON_MFP_H
-#define __PANTHEON_MFP_H
-
-/*
- * Frequently used MFP Configuration macros for all PANTHEON family of SoCs
- *
- * offset, pull,pF, drv,dF, edge,eF ,afn,aF
- */
-/* UART2 */
-#define MFP47_UART2_RXD		MFP_REG(0x198) | MFP_AF6 | MFP_DRIVE_MEDIUM
-#define MFP48_UART2_TXD		MFP_REG(0x19c) | MFP_AF6 | MFP_DRIVE_MEDIUM
-
-/* More macros can be defined here... */
-
-#define MFP_PIN_MAX	117
-#endif
diff --git a/arch/arm/include/asm/arch-pantheon/pantheon.h b/arch/arm/include/asm/arch-pantheon/pantheon.h
deleted file mode 100644
index e4ed087..0000000
--- a/arch/arm/include/asm/arch-pantheon/pantheon.h
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * (C) Copyright 2011
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Lei Wen <leiwen@marvell.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-#ifndef _PANTHEON_H
-#define _PANTHEON_H
-
-#ifndef __ASSEMBLY__
-#include <asm/types.h>
-#include <asm/io.h>
-#endif	/* __ASSEMBLY__ */
-
-#include <asm/arch/cpu.h>
-
-/* Common APB clock register bit definitions */
-#define APBC_APBCLK     (1<<0)  /* APB Bus Clock Enable */
-#define APBC_FNCLK      (1<<1)  /* Functional Clock Enable */
-#define APBC_RST        (1<<2)  /* Reset Generation */
-/* Functional Clock Selection Mask */
-#define APBC_FNCLKSEL(x)        (((x) & 0xf) << 4)
-
-/* Register Base Addresses */
-#define PANTHEON_DRAM_BASE	0xB0000000
-#define PANTHEON_TIMER_BASE	0xD4014000
-#define PANTHEON_WD_TIMER_BASE	0xD4080000
-#define PANTHEON_APBC_BASE	0xD4015000
-#define PANTHEON_UART1_BASE	0xD4017000
-#define PANTHEON_UART2_BASE	0xD4018000
-#define PANTHEON_GPIO_BASE	0xD4019000
-#define PANTHEON_MFPR_BASE	0xD401E000
-#define PANTHEON_MPMU_BASE	0xD4050000
-#define PANTHEON_CPU_BASE	0xD4282C00
-
-#endif /* _PANTHEON_H */
diff --git a/arch/arm/include/asm/arch-pxa/bitfield.h b/arch/arm/include/asm/arch-pxa/bitfield.h
deleted file mode 100644
index 104a21c..0000000
--- a/arch/arm/include/asm/arch-pxa/bitfield.h
+++ /dev/null
@@ -1,112 +0,0 @@
-/*
- *	FILE		bitfield.h
- *
- *	Version		1.1
- *	Author		Copyright (c) Marc A. Viredaz, 1998
- *			DEC Western Research Laboratory, Palo Alto, CA
- *	Date		April 1998 (April 1997)
- *	System		Advanced RISC Machine (ARM)
- *	Language	C or ARM Assembly
- *	Purpose		Definition of macros to operate on bit fields.
- */
-
-
-#ifndef __BITFIELD_H
-#define __BITFIELD_H
-
-#ifndef __ASSEMBLY__
-#define UData(Data)	((unsigned long) (Data))
-#else
-#define UData(Data)	(Data)
-#endif
-
-
-/*
- * MACRO: Fld
- *
- * Purpose
- *    The macro "Fld" encodes a bit field, given its size and its shift value
- *    with respect to bit 0.
- *
- * Note
- *    A more intuitive way to encode bit fields would have been to use their
- *    mask. However, extracting size and shift value information from a bit
- *    field's mask is cumbersome and might break the assembler (255-character
- *    line-size limit).
- *
- * Input
- *    Size		Size of the bit field, in number of bits.
- *    Shft		Shift value of the bit field with respect to bit 0.
- *
- * Output
- *    Fld		Encoded bit field.
- */
-
-#define Fld(Size, Shft)	(((Size) << 16) + (Shft))
-
-
-/*
- * MACROS: FSize, FShft, FMsk, FAlnMsk, F1stBit
- *
- * Purpose
- *    The macros "FSize", "FShft", "FMsk", "FAlnMsk", and "F1stBit" return
- *    the size, shift value, mask, aligned mask, and first bit of a
- *    bit field.
- *
- * Input
- *    Field		Encoded bit field (using the macro "Fld").
- *
- * Output
- *    FSize		Size of the bit field, in number of bits.
- *    FShft		Shift value of the bit field with respect to bit 0.
- *    FMsk		Mask for the bit field.
- *    FAlnMsk		Mask for the bit field, aligned on bit 0.
- *    F1stBit		First bit of the bit field.
- */
-
-#define FSize(Field)	((Field) >> 16)
-#define FShft(Field)	((Field) & 0x0000FFFF)
-#define FMsk(Field)	(((UData (1) << FSize (Field)) - 1) << FShft (Field))
-#define FAlnMsk(Field)	((UData (1) << FSize (Field)) - 1)
-#define F1stBit(Field)	(UData (1) << FShft (Field))
-
-
-/*
- * MACRO: FInsrt
- *
- * Purpose
- *    The macro "FInsrt" inserts a value into a bit field by shifting the
- *    former appropriately.
- *
- * Input
- *    Value		Bit-field value.
- *    Field		Encoded bit field (using the macro "Fld").
- *
- * Output
- *    FInsrt		Bit-field value positioned appropriately.
- */
-
-#define FInsrt(Value, Field) \
-			(UData (Value) << FShft (Field))
-
-
-/*
- * MACRO: FExtr
- *
- * Purpose
- *    The macro "FExtr" extracts the value of a bit field by masking and
- *    shifting it appropriately.
- *
- * Input
- *    Data		Data containing the bit-field to be extracted.
- *    Field		Encoded bit field (using the macro "Fld").
- *
- * Output
- *    FExtr		Bit-field value.
- */
-
-#define FExtr(Data, Field) \
-			((UData (Data) >> FShft (Field)) & FAlnMsk (Field))
-
-
-#endif /* __BITFIELD_H */
diff --git a/arch/arm/include/asm/arch-pxa/hardware.h b/arch/arm/include/asm/arch-pxa/hardware.h
deleted file mode 100644
index 44b800f..0000000
--- a/arch/arm/include/asm/arch-pxa/hardware.h
+++ /dev/null
@@ -1,123 +0,0 @@
-/*
- *  linux/include/asm-arm/arch-pxa/hardware.h
- *
- *  Author:	Nicolas Pitre
- *  Created:	Jun 15, 2001
- *  Copyright:	MontaVista Software Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * Note: This file was taken from linux-2.4.19-rmk4-pxa1
- *
- * - 2003/01/20 implementation specifics activated
- *   Robert Schwebel <r.schwebel@pengutronix.de>
- */
-
-#ifndef __ASM_ARCH_HARDWARE_H
-#define __ASM_ARCH_HARDWARE_H
-
-#include <linux/config.h>
-#include <asm/mach-types.h>
-
-/*
- * Define CONFIG_CPU_MONAHANS in case some CPU of the PXA3xx family is selected.
- * PXA300/310/320 all have distinct register mappings in some cases, that's why
- * the exact CPU has to be selected. CONFIG_CPU_MONAHANS is a helper for common
- * drivers and compatibility glue with old source then.
- */
-#ifndef	CONFIG_CPU_MONAHANS
-#if	defined(CONFIG_CPU_PXA300) || \
-	defined(CONFIG_CPU_PXA310) || \
-	defined(CONFIG_CPU_PXA320)
-#define	CONFIG_CPU_MONAHANS
-#endif
-#endif
-
-/*
- * These are statically mapped PCMCIA IO space for designs using it as a
- * generic IO bus, typically with ISA parts, hardwired IDE interfaces, etc.
- * The actual PCMCIA code is mapping required IO region at run time.
- */
-#define PCMCIA_IO_0_BASE	0xf6000000
-#define PCMCIA_IO_1_BASE	0xf7000000
-
-
-/*
- * We requires absolute addresses.
- */
-#define PCIO_BASE		0
-
-/*
- * Workarounds for at least 2 errata so far require this.
- * The mapping is set in mach-pxa/generic.c.
- */
-#define UNCACHED_PHYS_0		0xff000000
-#define UNCACHED_ADDR		UNCACHED_PHYS_0
-
-/*
- * Intel PXA internal I/O mappings:
- *
- * 0x40000000 - 0x41ffffff <--> 0xf8000000 - 0xf9ffffff
- * 0x44000000 - 0x45ffffff <--> 0xfa000000 - 0xfbffffff
- * 0x48000000 - 0x49ffffff <--> 0xfc000000 - 0xfdffffff
- */
-
-#include "pxa-regs.h"
-
-#ifndef __ASSEMBLY__
-
-/*
- * GPIO edge detection for IRQs:
- * IRQs are generated on Falling-Edge, Rising-Edge, or both.
- * This must be called *before* the corresponding IRQ is registered.
- * Use this instead of directly setting GRER/GFER.
- */
-#define GPIO_FALLING_EDGE	1
-#define GPIO_RISING_EDGE	2
-#define GPIO_BOTH_EDGES		3
-extern void set_GPIO_IRQ_edge( int gpio_nr, int edge_mask );
-
-/*
- * Handy routine to set GPIO alternate functions
- */
-extern void set_GPIO_mode( int gpio_mode );
-
-/*
- * return current lclk frequency in units of 10kHz
- */
-extern unsigned int get_lclk_frequency_10khz(void);
-
-#endif
-
-
-/*
- * Implementation specifics
- */
-
-#ifdef CONFIG_ARCH_LUBBOCK
-#include "lubbock.h"
-#endif
-
-#ifdef CONFIG_ARCH_PXA_IDP
-#include "idp.h"
-#endif
-
-#ifdef CONFIG_ARCH_PXA_CERF
-#include "cerf.h"
-#endif
-
-#ifdef CONFIG_ARCH_CSB226
-#include "csb226.h"
-#endif
-
-#ifdef CONFIG_ARCH_INNOKOM
-#include "innokom.h"
-#endif
-
-#ifdef CONFIG_ARCH_PLEB
-#include "pleb.h"
-#endif
-
-#endif	/* _ASM_ARCH_HARDWARE_H */
diff --git a/arch/arm/include/asm/arch-pxa/pxa-regs.h b/arch/arm/include/asm/arch-pxa/pxa-regs.h
deleted file mode 100644
index 65a387f..0000000
--- a/arch/arm/include/asm/arch-pxa/pxa-regs.h
+++ /dev/null
@@ -1,2800 +0,0 @@
-/*
- *  linux/include/asm-arm/arch-pxa/pxa-regs.h
- *
- *  Author:	Nicolas Pitre
- *  Created:	Jun 15, 2001
- *  Copyright:	MontaVista Software Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * - 2003/01/20: Robert Schwebel <r.schwebel@pengutronix.de
- *   Original file taken from linux-2.4.19-rmk4-pxa1. Added some definitions.
- *   Added include for hardware.h (for __REG definition)
- */
-#ifndef _PXA_REGS_H_
-#define _PXA_REGS_H_
-
-#include "bitfield.h"
-#include "hardware.h"
-
-/* FIXME hack so that SA-1111.h will work [cb] */
-
-#ifndef __ASSEMBLY__
-typedef unsigned short	Word16 ;
-typedef unsigned int	Word32 ;
-typedef Word32		Word ;
-typedef Word		Quad [4] ;
-typedef void		*Address ;
-typedef void		(*ExcpHndlr) (void) ;
-#endif
-
-/*
- * PXA Chip selects
- */
-#ifdef CONFIG_CPU_MONAHANS
-#define PXA_CS0_PHYS   0x00000000 /* for both small and large same start */
-#define PXA_CS1_PHYS   0x04000000 /* Small partition start address (64MB) */
-#define PXA_CS1_LPHYS  0x30000000 /* Large partition start address (256MB) */
-#define PXA_CS2_PHYS   0x10000000 /* (64MB) */
-#define PXA_CS3_PHYS   0x14000000 /* (64MB) */
-#define PXA_PCMCIA_PHYS        0x20000000 /* (256MB) */
-#else
-#define PXA_CS0_PHYS	0x00000000
-#define PXA_CS1_PHYS	0x04000000
-#define PXA_CS2_PHYS	0x08000000
-#define PXA_CS3_PHYS	0x0C000000
-#define PXA_CS4_PHYS	0x10000000
-#define PXA_CS5_PHYS	0x14000000
-#endif /* CONFIG_CPU_MONAHANS */
-
-/*
- * Personal Computer Memory Card International Association (PCMCIA) sockets
- */
-#define PCMCIAPrtSp	0x04000000	/* PCMCIA Partition Space [byte]   */
-#define PCMCIASp	(4*PCMCIAPrtSp) /* PCMCIA Space [byte]		   */
-#define PCMCIAIOSp	PCMCIAPrtSp	/* PCMCIA I/O Space [byte]	   */
-#define PCMCIAAttrSp	PCMCIAPrtSp	/* PCMCIA Attribute Space [byte]   */
-#define PCMCIAMemSp	PCMCIAPrtSp	/* PCMCIA Memory Space [byte]	   */
-
-#ifndef CONFIG_CPU_MONAHANS             /* Monahans supports only one slot */
-#define PCMCIA0Sp	PCMCIASp	/* PCMCIA 0 Space [byte]	   */
-#define PCMCIA0IOSp	PCMCIAIOSp	/* PCMCIA 0 I/O Space [byte]	   */
-#define PCMCIA0AttrSp	PCMCIAAttrSp	/* PCMCIA 0 Attribute Space [byte] */
-#define PCMCIA0MemSp	PCMCIAMemSp	/* PCMCIA 0 Memory Space [byte]	   */
-#endif
-
-#define PCMCIA1Sp	PCMCIASp	/* PCMCIA 1 Space [byte]	   */
-#define PCMCIA1IOSp	PCMCIAIOSp	/* PCMCIA 1 I/O Space [byte]	   */
-#define PCMCIA1AttrSp	PCMCIAAttrSp	/* PCMCIA 1 Attribute Space [byte] */
-#define PCMCIA1MemSp	PCMCIAMemSp	/* PCMCIA 1 Memory Space [byte]	   */
-
-#define _PCMCIA(Nb)			/* PCMCIA [0..1]		   */ \
-			(0x20000000 + (Nb)*PCMCIASp)
-#define _PCMCIAIO(Nb)	_PCMCIA (Nb)	/* PCMCIA I/O [0..1]		   */
-#define _PCMCIAAttr(Nb)			/* PCMCIA Attribute [0..1]	   */ \
-			(_PCMCIA (Nb) + 2*PCMCIAPrtSp)
-#define _PCMCIAMem(Nb)			/* PCMCIA Memory [0..1]		   */ \
-			(_PCMCIA (Nb) + 3*PCMCIAPrtSp)
-
-#define _PCMCIA0	_PCMCIA (0)	/* PCMCIA 0			   */
-#define _PCMCIA0IO	_PCMCIAIO (0)	/* PCMCIA 0 I/O			   */
-#define _PCMCIA0Attr	_PCMCIAAttr (0) /* PCMCIA 0 Attribute		   */
-#define _PCMCIA0Mem	_PCMCIAMem (0)	/* PCMCIA 0 Memory		   */
-
-#ifndef CONFIG_CPU_MONAHANS             /* Monahans supports only one slot */
-#define _PCMCIA1	_PCMCIA (1)	/* PCMCIA 1			   */
-#define _PCMCIA1IO	_PCMCIAIO (1)	/* PCMCIA 1 I/O			   */
-#define _PCMCIA1Attr	_PCMCIAAttr (1) /* PCMCIA 1 Attribute		   */
-#define _PCMCIA1Mem	_PCMCIAMem (1)	/* PCMCIA 1 Memory		   */
-#endif
-
-/*
- * DMA Controller
- */
-#define DCSR0		0x40000000  /* DMA Control / Status Register for Channel 0 */
-#define DCSR1		0x40000004  /* DMA Control / Status Register for Channel 1 */
-#define DCSR2		0x40000008  /* DMA Control / Status Register for Channel 2 */
-#define DCSR3		0x4000000c  /* DMA Control / Status Register for Channel 3 */
-#define DCSR4		0x40000010  /* DMA Control / Status Register for Channel 4 */
-#define DCSR5		0x40000014  /* DMA Control / Status Register for Channel 5 */
-#define DCSR6		0x40000018  /* DMA Control / Status Register for Channel 6 */
-#define DCSR7		0x4000001c  /* DMA Control / Status Register for Channel 7 */
-#define DCSR8		0x40000020  /* DMA Control / Status Register for Channel 8 */
-#define DCSR9		0x40000024  /* DMA Control / Status Register for Channel 9 */
-#define DCSR10		0x40000028  /* DMA Control / Status Register for Channel 10 */
-#define DCSR11		0x4000002c  /* DMA Control / Status Register for Channel 11 */
-#define DCSR12		0x40000030  /* DMA Control / Status Register for Channel 12 */
-#define DCSR13		0x40000034  /* DMA Control / Status Register for Channel 13 */
-#define DCSR14		0x40000038  /* DMA Control / Status Register for Channel 14 */
-#define DCSR15		0x4000003c  /* DMA Control / Status Register for Channel 15 */
-#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
-#define DCSR16		0x40000040  /* DMA Control / Status Register for Channel 16 */
-#define DCSR17		0x40000044  /* DMA Control / Status Register for Channel 17 */
-#define DCSR18		0x40000048  /* DMA Control / Status Register for Channel 18 */
-#define DCSR19		0x4000004c  /* DMA Control / Status Register for Channel 19 */
-#define DCSR20		0x40000050  /* DMA Control / Status Register for Channel 20 */
-#define DCSR21		0x40000054  /* DMA Control / Status Register for Channel 21 */
-#define DCSR22		0x40000058  /* DMA Control / Status Register for Channel 22 */
-#define DCSR23		0x4000005c  /* DMA Control / Status Register for Channel 23 */
-#define DCSR24		0x40000060  /* DMA Control / Status Register for Channel 24 */
-#define DCSR25		0x40000064  /* DMA Control / Status Register for Channel 25 */
-#define DCSR26		0x40000068  /* DMA Control / Status Register for Channel 26 */
-#define DCSR27		0x4000006c  /* DMA Control / Status Register for Channel 27 */
-#define DCSR28		0x40000070  /* DMA Control / Status Register for Channel 28 */
-#define DCSR29		0x40000074  /* DMA Control / Status Register for Channel 29 */
-#define DCSR30		0x40000078  /* DMA Control / Status Register for Channel 30 */
-#define DCSR31		0x4000007c  /* DMA Control / Status Register for Channel 31 */
-#endif /* CONFIG_PXA27X || CONFIG_CPU_MONAHANS */
-
-#define DCSR(x)		(0x40000000 | ((x) << 2))
-
-#define DCSR_RUN	(1 << 31)	/* Run Bit (read / write) */
-#define DCSR_NODESC	(1 << 30)	/* No-Descriptor Fetch (read / write) */
-#define DCSR_STOPIRQEN	(1 << 29)	/* Stop Interrupt Enable (read / write) */
-
-#if defined(CONFIG_PXA27X) || defined (CONFIG_CPU_MONAHANS)
-#define DCSR_EORIRQEN	(1 << 28)	/* End of Receive Interrupt Enable (R/W) */
-#define DCSR_EORJMPEN	(1 << 27)	/* Jump to next descriptor on EOR */
-#define DCSR_EORSTOPEN	(1 << 26)	/* STOP on an EOR */
-#define DCSR_SETCMPST	(1 << 25)	/* Set Descriptor Compare Status */
-#define DCSR_CLRCMPST	(1 << 24)	/* Clear Descriptor Compare Status */
-#define DCSR_CMPST	(1 << 10)	/* The Descriptor Compare Status */
-#define DCSR_ENRINTR	(1 << 9)	/* The end of Receive */
-#endif
-
-#define DCSR_REQPEND	(1 << 8)	/* Request Pending (read-only) */
-#define DCSR_STOPSTATE	(1 << 3)	/* Stop State (read-only) */
-#define DCSR_ENDINTR	(1 << 2)	/* End Interrupt (read / write) */
-#define DCSR_STARTINTR	(1 << 1)	/* Start Interrupt (read / write) */
-#define DCSR_BUSERR	(1 << 0)	/* Bus Error Interrupt (read / write) */
-
-#define DINT		0x400000f0  /* DMA Interrupt Register */
-
-#define DRCMR0		0x40000100  /* Request to Channel Map Register for DREQ 0 */
-#define DRCMR1		0x40000104  /* Request to Channel Map Register for DREQ 1 */
-#define DRCMR2		0x40000108  /* Request to Channel Map Register for I2S receive Request */
-#define DRCMR3		0x4000010c  /* Request to Channel Map Register for I2S transmit Request */
-#define DRCMR4		0x40000110  /* Request to Channel Map Register for BTUART receive Request */
-#define DRCMR5		0x40000114  /* Request to Channel Map Register for BTUART transmit Request. */
-#define DRCMR6		0x40000118  /* Request to Channel Map Register for FFUART receive Request */
-#define DRCMR7		0x4000011c  /* Request to Channel Map Register for FFUART transmit Request */
-#define DRCMR8		0x40000120  /* Request to Channel Map Register for AC97 microphone Request */
-#define DRCMR9		0x40000124  /* Request to Channel Map Register for AC97 modem receive Request */
-#define DRCMR10		0x40000128  /* Request to Channel Map Register for AC97 modem transmit Request */
-#define DRCMR11		0x4000012c  /* Request to Channel Map Register for AC97 audio receive Request */
-#define DRCMR12		0x40000130  /* Request to Channel Map Register for AC97 audio transmit Request */
-#define DRCMR13		0x40000134  /* Request to Channel Map Register for SSP receive Request */
-#define DRCMR14		0x40000138  /* Request to Channel Map Register for SSP transmit Request */
-#define DRCMR15		0x4000013c  /* Reserved */
-#define DRCMR16		0x40000140  /* Reserved */
-#define DRCMR17		0x40000144  /* Request to Channel Map Register for ICP receive Request */
-#define DRCMR18		0x40000148  /* Request to Channel Map Register for ICP transmit Request */
-#define DRCMR19		0x4000014c  /* Request to Channel Map Register for STUART receive Request */
-#define DRCMR20		0x40000150  /* Request to Channel Map Register for STUART transmit Request */
-#define DRCMR21		0x40000154  /* Request to Channel Map Register for MMC receive Request */
-#define DRCMR22		0x40000158  /* Request to Channel Map Register for MMC transmit Request */
-#define DRCMR23		0x4000015c  /* Reserved */
-#define DRCMR24		0x40000160  /* Reserved */
-#define DRCMR25		0x40000164  /* Request to Channel Map Register for USB endpoint 1 Request */
-#define DRCMR26		0x40000168  /* Request to Channel Map Register for USB endpoint 2 Request */
-#define DRCMR27		0x4000016C  /* Request to Channel Map Register for USB endpoint 3 Request */
-#define DRCMR28		0x40000170  /* Request to Channel Map Register for USB endpoint 4 Request */
-#define DRCMR29		0x40000174  /* Reserved */
-#define DRCMR30		0x40000178  /* Request to Channel Map Register for USB endpoint 6 Request */
-#define DRCMR31		0x4000017C  /* Request to Channel Map Register for USB endpoint 7 Request */
-#define DRCMR32		0x40000180  /* Request to Channel Map Register for USB endpoint 8 Request */
-#define DRCMR33		0x40000184  /* Request to Channel Map Register for USB endpoint 9 Request */
-#define DRCMR34		0x40000188  /* Reserved */
-#define DRCMR35		0x4000018C  /* Request to Channel Map Register for USB endpoint 11 Request */
-#define DRCMR36		0x40000190  /* Request to Channel Map Register for USB endpoint 12 Request */
-#define DRCMR37		0x40000194  /* Request to Channel Map Register for USB endpoint 13 Request */
-#define DRCMR38		0x40000198  /* Request to Channel Map Register for USB endpoint 14 Request */
-#define DRCMR39		0x4000019C  /* Reserved */
-
-#define DRCMR68		       0x40001110  /* Request to Channel Map Register for Camera FIFO 0 Request */
-#define DRCMR69		       0x40001114  /* Request to Channel Map Register for Camera FIFO 1 Request */
-#define DRCMR70		       0x40001118  /* Request to Channel Map Register for Camera FIFO 2 Request */
-
-#define DRCMRRXSADR	DRCMR2
-#define DRCMRTXSADR	DRCMR3
-#define DRCMRRXBTRBR	DRCMR4
-#define DRCMRTXBTTHR	DRCMR5
-#define DRCMRRXFFRBR	DRCMR6
-#define DRCMRTXFFTHR	DRCMR7
-#define DRCMRRXMCDR	DRCMR8
-#define DRCMRRXMODR	DRCMR9
-#define DRCMRTXMODR	DRCMR10
-#define DRCMRRXPCDR	DRCMR11
-#define DRCMRTXPCDR	DRCMR12
-#define DRCMRRXSSDR	DRCMR13
-#define DRCMRTXSSDR	DRCMR14
-#define DRCMRRXICDR	DRCMR17
-#define DRCMRTXICDR	DRCMR18
-#define DRCMRRXSTRBR	DRCMR19
-#define DRCMRTXSTTHR	DRCMR20
-#define DRCMRRXMMC	DRCMR21
-#define DRCMRTXMMC	DRCMR22
-
-#define DRCMR_MAPVLD	(1 << 7)	/* Map Valid (read / write) */
-#define DRCMR_CHLNUM	0x0f		/* mask for Channel Number (read / write) */
-
-#define DDADR0		0x40000200  /* DMA Descriptor Address Register Channel 0 */
-#define DSADR0		0x40000204  /* DMA Source Address Register Channel 0 */
-#define DTADR0		0x40000208  /* DMA Target Address Register Channel 0 */
-#define DCMD0		0x4000020c  /* DMA Command Address Register Channel 0 */
-#define DDADR1		0x40000210  /* DMA Descriptor Address Register Channel 1 */
-#define DSADR1		0x40000214  /* DMA Source Address Register Channel 1 */
-#define DTADR1		0x40000218  /* DMA Target Address Register Channel 1 */
-#define DCMD1		0x4000021c  /* DMA Command Address Register Channel 1 */
-#define DDADR2		0x40000220  /* DMA Descriptor Address Register Channel 2 */
-#define DSADR2		0x40000224  /* DMA Source Address Register Channel 2 */
-#define DTADR2		0x40000228  /* DMA Target Address Register Channel 2 */
-#define DCMD2		0x4000022c  /* DMA Command Address Register Channel 2 */
-#define DDADR3		0x40000230  /* DMA Descriptor Address Register Channel 3 */
-#define DSADR3		0x40000234  /* DMA Source Address Register Channel 3 */
-#define DTADR3		0x40000238  /* DMA Target Address Register Channel 3 */
-#define DCMD3		0x4000023c  /* DMA Command Address Register Channel 3 */
-#define DDADR4		0x40000240  /* DMA Descriptor Address Register Channel 4 */
-#define DSADR4		0x40000244  /* DMA Source Address Register Channel 4 */
-#define DTADR4		0x40000248  /* DMA Target Address Register Channel 4 */
-#define DCMD4		0x4000024c  /* DMA Command Address Register Channel 4 */
-#define DDADR5		0x40000250  /* DMA Descriptor Address Register Channel 5 */
-#define DSADR5		0x40000254  /* DMA Source Address Register Channel 5 */
-#define DTADR5		0x40000258  /* DMA Target Address Register Channel 5 */
-#define DCMD5		0x4000025c  /* DMA Command Address Register Channel 5 */
-#define DDADR6		0x40000260  /* DMA Descriptor Address Register Channel 6 */
-#define DSADR6		0x40000264  /* DMA Source Address Register Channel 6 */
-#define DTADR6		0x40000268  /* DMA Target Address Register Channel 6 */
-#define DCMD6		0x4000026c  /* DMA Command Address Register Channel 6 */
-#define DDADR7		0x40000270  /* DMA Descriptor Address Register Channel 7 */
-#define DSADR7		0x40000274  /* DMA Source Address Register Channel 7 */
-#define DTADR7		0x40000278  /* DMA Target Address Register Channel 7 */
-#define DCMD7		0x4000027c  /* DMA Command Address Register Channel 7 */
-#define DDADR8		0x40000280  /* DMA Descriptor Address Register Channel 8 */
-#define DSADR8		0x40000284  /* DMA Source Address Register Channel 8 */
-#define DTADR8		0x40000288  /* DMA Target Address Register Channel 8 */
-#define DCMD8		0x4000028c  /* DMA Command Address Register Channel 8 */
-#define DDADR9		0x40000290  /* DMA Descriptor Address Register Channel 9 */
-#define DSADR9		0x40000294  /* DMA Source Address Register Channel 9 */
-#define DTADR9		0x40000298  /* DMA Target Address Register Channel 9 */
-#define DCMD9		0x4000029c  /* DMA Command Address Register Channel 9 */
-#define DDADR10		0x400002a0  /* DMA Descriptor Address Register Channel 10 */
-#define DSADR10		0x400002a4  /* DMA Source Address Register Channel 10 */
-#define DTADR10		0x400002a8  /* DMA Target Address Register Channel 10 */
-#define DCMD10		0x400002ac  /* DMA Command Address Register Channel 10 */
-#define DDADR11		0x400002b0  /* DMA Descriptor Address Register Channel 11 */
-#define DSADR11		0x400002b4  /* DMA Source Address Register Channel 11 */
-#define DTADR11		0x400002b8  /* DMA Target Address Register Channel 11 */
-#define DCMD11		0x400002bc  /* DMA Command Address Register Channel 11 */
-#define DDADR12		0x400002c0  /* DMA Descriptor Address Register Channel 12 */
-#define DSADR12		0x400002c4  /* DMA Source Address Register Channel 12 */
-#define DTADR12		0x400002c8  /* DMA Target Address Register Channel 12 */
-#define DCMD12		0x400002cc  /* DMA Command Address Register Channel 12 */
-#define DDADR13		0x400002d0  /* DMA Descriptor Address Register Channel 13 */
-#define DSADR13		0x400002d4  /* DMA Source Address Register Channel 13 */
-#define DTADR13		0x400002d8  /* DMA Target Address Register Channel 13 */
-#define DCMD13		0x400002dc  /* DMA Command Address Register Channel 13 */
-#define DDADR14		0x400002e0  /* DMA Descriptor Address Register Channel 14 */
-#define DSADR14		0x400002e4  /* DMA Source Address Register Channel 14 */
-#define DTADR14		0x400002e8  /* DMA Target Address Register Channel 14 */
-#define DCMD14		0x400002ec  /* DMA Command Address Register Channel 14 */
-#define DDADR15		0x400002f0  /* DMA Descriptor Address Register Channel 15 */
-#define DSADR15		0x400002f4  /* DMA Source Address Register Channel 15 */
-#define DTADR15		0x400002f8  /* DMA Target Address Register Channel 15 */
-#define DCMD15		0x400002fc  /* DMA Command Address Register Channel 15 */
-
-#define DDADR(x)	(0x40000200 | ((x) << 4))
-#define DSADR(x)	(0x40000204 | ((x) << 4))
-#define DTADR(x)	(0x40000208 | ((x) << 4))
-#define DCMD(x)		(0x4000020c | ((x) << 4))
-
-#define DDADR_DESCADDR	0xfffffff0	/* Address of next descriptor (mask) */
-#define DDADR_STOP	(1 << 0)	/* Stop (read / write) */
-
-#define DCMD_INCSRCADDR (1 << 31)	/* Source Address Increment Setting. */
-#define DCMD_INCTRGADDR (1 << 30)	/* Target Address Increment Setting. */
-#define DCMD_FLOWSRC	(1 << 29)	/* Flow Control by the source. */
-#define DCMD_FLOWTRG	(1 << 28)	/* Flow Control by the target. */
-#define DCMD_STARTIRQEN (1 << 22)	/* Start Interrupt Enable */
-#define DCMD_ENDIRQEN	(1 << 21)	/* End Interrupt Enable */
-#define DCMD_ENDIAN	(1 << 18)	/* Device Endian-ness. */
-#define DCMD_BURST8	(1 << 16)	/* 8 byte burst */
-#define DCMD_BURST16	(2 << 16)	/* 16 byte burst */
-#define DCMD_BURST32	(3 << 16)	/* 32 byte burst */
-#define DCMD_WIDTH1	(1 << 14)	/* 1 byte width */
-#define DCMD_WIDTH2	(2 << 14)	/* 2 byte width (HalfWord) */
-#define DCMD_WIDTH4	(3 << 14)	/* 4 byte width (Word) */
-#define DCMD_LENGTH	0x01fff		/* length mask (max = 8K - 1) */
-
-/* default combinations */
-#define DCMD_RXPCDR	(DCMD_INCTRGADDR|DCMD_FLOWSRC|DCMD_BURST32|DCMD_WIDTH4)
-#define DCMD_RXMCDR	(DCMD_INCTRGADDR|DCMD_FLOWSRC|DCMD_BURST32|DCMD_WIDTH4)
-#define DCMD_TXPCDR	(DCMD_INCSRCADDR|DCMD_FLOWTRG|DCMD_BURST32|DCMD_WIDTH4)
-
-/******************************************************************************/
-/*
- * UARTs
- */
-/* Full Function UART (FFUART) */
-#define FFUART		FFRBR
-#define FFRBR		0x40100000  /* Receive Buffer Register (read only) */
-#define FFTHR		0x40100000  /* Transmit Holding Register (write only) */
-#define FFIER		0x40100004  /* Interrupt Enable Register (read/write) */
-#define FFIIR		0x40100008  /* Interrupt ID Register (read only) */
-#define FFFCR		0x40100008  /* FIFO Control Register (write only) */
-#define FFLCR		0x4010000C  /* Line Control Register (read/write) */
-#define FFMCR		0x40100010  /* Modem Control Register (read/write) */
-#define FFLSR		0x40100014  /* Line Status Register (read only) */
-#define FFMSR		0x40100018  /* Modem Status Register (read only) */
-#define FFSPR		0x4010001C  /* Scratch Pad Register (read/write) */
-#define FFISR		0x40100020  /* Infrared Selection Register (read/write) */
-#define FFDLL		0x40100000  /* Divisor Latch Low Register (DLAB = 1) (read/write) */
-#define FFDLH		0x40100004  /* Divisor Latch High Register (DLAB = 1) (read/write) */
-
-/* Bluetooth UART (BTUART) */
-#define BTUART		BTRBR
-#define BTRBR		0x40200000  /* Receive Buffer Register (read only) */
-#define BTTHR		0x40200000  /* Transmit Holding Register (write only) */
-#define BTIER		0x40200004  /* Interrupt Enable Register (read/write) */
-#define BTIIR		0x40200008  /* Interrupt ID Register (read only) */
-#define BTFCR		0x40200008  /* FIFO Control Register (write only) */
-#define BTLCR		0x4020000C  /* Line Control Register (read/write) */
-#define BTMCR		0x40200010  /* Modem Control Register (read/write) */
-#define BTLSR		0x40200014  /* Line Status Register (read only) */
-#define BTMSR		0x40200018  /* Modem Status Register (read only) */
-#define BTSPR		0x4020001C  /* Scratch Pad Register (read/write) */
-#define BTISR		0x40200020  /* Infrared Selection Register (read/write) */
-#define BTDLL		0x40200000  /* Divisor Latch Low Register (DLAB = 1) (read/write) */
-#define BTDLH		0x40200004  /* Divisor Latch High Register (DLAB = 1) (read/write) */
-
-/* Standard UART (STUART) */
-#define STUART		STRBR
-#define STRBR		0x40700000  /* Receive Buffer Register (read only) */
-#define STTHR		0x40700000  /* Transmit Holding Register (write only) */
-#define STIER		0x40700004  /* Interrupt Enable Register (read/write) */
-#define STIIR		0x40700008  /* Interrupt ID Register (read only) */
-#define STFCR		0x40700008  /* FIFO Control Register (write only) */
-#define STLCR		0x4070000C  /* Line Control Register (read/write) */
-#define STMCR		0x40700010  /* Modem Control Register (read/write) */
-#define STLSR		0x40700014  /* Line Status Register (read only) */
-#define STMSR		0x40700018  /* Reserved */
-#define STSPR		0x4070001C  /* Scratch Pad Register (read/write) */
-#define STISR		0x40700020  /* Infrared Selection Register (read/write) */
-#define STDLL		0x40700000  /* Divisor Latch Low Register (DLAB = 1) (read/write) */
-#define STDLH		0x40700004  /* Divisor Latch High Register (DLAB = 1) (read/write) */
-
-#define IER_DMAE	(1 << 7)	/* DMA Requests Enable */
-#define IER_UUE		(1 << 6)	/* UART Unit Enable */
-#define IER_NRZE	(1 << 5)	/* NRZ coding Enable */
-#define IER_RTIOE	(1 << 4)	/* Receiver Time Out Interrupt Enable */
-#define IER_MIE		(1 << 3)	/* Modem Interrupt Enable */
-#define IER_RLSE	(1 << 2)	/* Receiver Line Status Interrupt Enable */
-#define IER_TIE		(1 << 1)	/* Transmit Data request Interrupt Enable */
-#define IER_RAVIE	(1 << 0)	/* Receiver Data Available Interrupt Enable */
-
-#define IIR_FIFOES1	(1 << 7)	/* FIFO Mode Enable Status */
-#define IIR_FIFOES0	(1 << 6)	/* FIFO Mode Enable Status */
-#define IIR_TOD		(1 << 3)	/* Time Out Detected */
-#define IIR_IID2	(1 << 2)	/* Interrupt Source Encoded */
-#define IIR_IID1	(1 << 1)	/* Interrupt Source Encoded */
-#define IIR_IP		(1 << 0)	/* Interrupt Pending (active low) */
-
-#define FCR_ITL2	(1 << 7)	/* Interrupt Trigger Level */
-#define FCR_ITL1	(1 << 6)	/* Interrupt Trigger Level */
-#define FCR_RESETTF	(1 << 2)	/* Reset Transmitter FIFO */
-#define FCR_RESETRF	(1 << 1)	/* Reset Receiver FIFO */
-#define FCR_TRFIFOE	(1 << 0)	/* Transmit and Receive FIFO Enable */
-#define FCR_ITL_1	(0)
-#define FCR_ITL_8	(FCR_ITL1)
-#define FCR_ITL_16	(FCR_ITL2)
-#define FCR_ITL_32	(FCR_ITL2|FCR_ITL1)
-
-#define LCR_DLAB	(1 << 7)	/* Divisor Latch Access Bit */
-#define LCR_SB		(1 << 6)	/* Set Break */
-#define LCR_STKYP	(1 << 5)	/* Sticky Parity */
-#define LCR_EPS		(1 << 4)	/* Even Parity Select */
-#define LCR_PEN		(1 << 3)	/* Parity Enable */
-#define LCR_STB		(1 << 2)	/* Stop Bit */
-#define LCR_WLS1	(1 << 1)	/* Word Length Select */
-#define LCR_WLS0	(1 << 0)	/* Word Length Select */
-
-#define LSR_FIFOE	(1 << 7)	/* FIFO Error Status */
-#define LSR_TEMT	(1 << 6)	/* Transmitter Empty */
-#define LSR_TDRQ	(1 << 5)	/* Transmit Data Request */
-#define LSR_BI		(1 << 4)	/* Break Interrupt */
-#define LSR_FE		(1 << 3)	/* Framing Error */
-#define LSR_PE		(1 << 2)	/* Parity Error */
-#define LSR_OE		(1 << 1)	/* Overrun Error */
-#define LSR_DR		(1 << 0)	/* Data Ready */
-
-#define MCR_LOOP	(1 << 4)	/* */
-#define MCR_OUT2	(1 << 3)	/* force MSR_DCD in loopback mode */
-#define MCR_OUT1	(1 << 2)	/* force MSR_RI in loopback mode */
-#define MCR_RTS		(1 << 1)	/* Request to Send */
-#define MCR_DTR		(1 << 0)	/* Data Terminal Ready */
-
-#define MSR_DCD		(1 << 7)	/* Data Carrier Detect */
-#define MSR_RI		(1 << 6)	/* Ring Indicator */
-#define MSR_DSR		(1 << 5)	/* Data Set Ready */
-#define MSR_CTS		(1 << 4)	/* Clear To Send */
-#define MSR_DDCD	(1 << 3)	/* Delta Data Carrier Detect */
-#define MSR_TERI	(1 << 2)	/* Trailing Edge Ring Indicator */
-#define MSR_DDSR	(1 << 1)	/* Delta Data Set Ready */
-#define MSR_DCTS	(1 << 0)	/* Delta Clear To Send */
-
-/******************************************************************************/
-/*
- * IrSR (Infrared Selection Register)
- */
-#define IrSR_OFFSET 0x20
-
-#define IrSR_RXPL_NEG_IS_ZERO (1<<4)
-#define IrSR_RXPL_POS_IS_ZERO 0x0
-#define IrSR_TXPL_NEG_IS_ZERO (1<<3)
-#define IrSR_TXPL_POS_IS_ZERO 0x0
-#define IrSR_XMODE_PULSE_1_6  (1<<2)
-#define IrSR_XMODE_PULSE_3_16 0x0
-#define IrSR_RCVEIR_IR_MODE   (1<<1)
-#define IrSR_RCVEIR_UART_MODE 0x0
-#define IrSR_XMITIR_IR_MODE   (1<<0)
-#define IrSR_XMITIR_UART_MODE 0x0
-
-#define IrSR_IR_RECEIVE_ON (\
-		IrSR_RXPL_NEG_IS_ZERO | \
-		IrSR_TXPL_POS_IS_ZERO | \
-		IrSR_XMODE_PULSE_3_16 | \
-		IrSR_RCVEIR_IR_MODE   | \
-		IrSR_XMITIR_UART_MODE)
-
-#define IrSR_IR_TRANSMIT_ON (\
-		IrSR_RXPL_NEG_IS_ZERO | \
-		IrSR_TXPL_POS_IS_ZERO | \
-		IrSR_XMODE_PULSE_3_16 | \
-		IrSR_RCVEIR_UART_MODE | \
-		IrSR_XMITIR_IR_MODE)
-
-/*
- * I2C registers
- */
-#define IBMR		0x40301680  /* I2C Bus Monitor Register - IBMR */
-#define IDBR		0x40301688  /* I2C Data Buffer Register - IDBR */
-#define ICR		0x40301690  /* I2C Control Register - ICR */
-#define ISR		0x40301698  /* I2C Status Register - ISR */
-#define ISAR		0x403016A0  /* I2C Slave Address Register - ISAR */
-
-#ifdef CONFIG_CPU_MONAHANS
-#define PWRIBMR		0x40f500C0  /* Power I2C Bus Monitor Register-IBMR */
-#define PWRIDBR		0x40f500C4  /* Power I2C Data Buffer Register-IDBR */
-#define PWRICR		0x40f500C8  /* Power I2C Control Register - ICR */
-#define PWRISR		0x40f500CC  /* Power I2C Status Register - ISR */
-#define PWRISAR		0x40f500D0  /* Power I2C Slave Address Register-ISAR */
-#else
-#define PWRIBMR		0x40f00180  /* Power I2C Bus Monitor Register-IBMR */
-#define PWRIDBR		0x40f00188  /* Power I2C Data Buffer Register-IDBR */
-#define PWRICR		0x40f00190  /* Power I2C Control Register - ICR */
-#define PWRISR		0x40f00198  /* Power I2C Status Register - ISR */
-#define PWRISAR		0x40f001A0  /* Power I2C Slave Address Register-ISAR */
-#endif
-
-/* ----- Control register bits ---------------------------------------- */
-
-#define ICR_START	0x1		/* start bit */
-#define ICR_STOP	0x2		/* stop bit */
-#define ICR_ACKNAK	0x4		/* send ACK(0) or NAK(1) */
-#define ICR_TB		0x8		/* transfer byte bit */
-#define ICR_MA		0x10		/* master abort */
-#define ICR_SCLE	0x20		/* master clock enable, mona SCLEA */
-#define ICR_IUE		0x40		/* unit enable */
-#define ICR_GCD		0x80		/* general call disable */
-#define ICR_ITEIE	0x100		/* enable tx interrupts */
-#define ICR_IRFIE	0x200		/* enable rx interrupts, mona: DRFIE */
-#define ICR_BEIE	0x400		/* enable bus error ints */
-#define ICR_SSDIE	0x800		/* slave STOP detected int enable */
-#define ICR_ALDIE	0x1000		/* enable arbitration interrupt */
-#define ICR_SADIE	0x2000		/* slave address detected int enable */
-#define ICR_UR		0x4000		/* unit reset */
-#define ICR_FM		0x8000		/* Fast Mode */
-
-/* ----- Status register bits ----------------------------------------- */
-
-#define ISR_RWM		0x1		/* read/write mode */
-#define ISR_ACKNAK	0x2		/* ack/nak status */
-#define ISR_UB		0x4		/* unit busy */
-#define ISR_IBB		0x8		/* bus busy */
-#define ISR_SSD		0x10		/* slave stop detected */
-#define ISR_ALD		0x20		/* arbitration loss detected */
-#define ISR_ITE		0x40		/* tx buffer empty */
-#define ISR_IRF		0x80		/* rx buffer full */
-#define ISR_GCAD	0x100		/* general call address detected */
-#define ISR_SAD		0x200		/* slave address detected */
-#define ISR_BED		0x400		/* bus error no ACK/NAK */
-
-/*
- * Serial Audio Controller
- */
-/* FIXME the audio defines collide w/ the SA1111 defines.  I don't like these
- * short defines because there is too much chance of namespace collision
- */
-#define SACR0		0x40400000  /*  Global Control Register */
-#define SACR1		0x40400004  /*  Serial Audio I 2 S/MSB-Justified Control Register */
-#define SASR0		0x4040000C  /*  Serial Audio I 2 S/MSB-Justified Interface and FIFO Status Register */
-#define SAIMR		0x40400014  /*  Serial Audio Interrupt Mask Register */
-#define SAICR		0x40400018  /*  Serial Audio Interrupt Clear Register */
-#define SADIV		0x40400060  /*  Audio Clock Divider Register. */
-#define SADR		0x40400080  /*  Serial Audio Data Register (TX and RX FIFO access Register). */
-
-/*
- * AC97 Controller registers
- */
-#define POCR		0x40500000  /* PCM Out Control Register */
-#define POCR_FEIE	(1 << 3)	/* FIFO Error Interrupt Enable */
-
-#define PICR		0x40500004  /* PCM In Control Register */
-#define PICR_FEIE	(1 << 3)	/* FIFO Error Interrupt Enable */
-
-#define MCCR		0x40500008  /* Mic In Control Register */
-#define MCCR_FEIE	(1 << 3)	/* FIFO Error Interrupt Enable */
-
-#define GCR		0x4050000C  /* Global Control Register */
-#define GCR_CDONE_IE	(1 << 19)	/* Command Done Interrupt Enable */
-#define GCR_SDONE_IE	(1 << 18)	/* Status Done Interrupt Enable */
-#define GCR_SECRDY_IEN	(1 << 9)	/* Secondary Ready Interrupt Enable */
-#define GCR_PRIRDY_IEN	(1 << 8)	/* Primary Ready Interrupt Enable */
-#define GCR_SECRES_IEN	(1 << 5)	/* Secondary Resume Interrupt Enable */
-#define GCR_PRIRES_IEN	(1 << 4)	/* Primary Resume Interrupt Enable */
-#define GCR_ACLINK_OFF	(1 << 3)	/* AC-link Shut Off */
-#define GCR_WARM_RST	(1 << 2)	/* AC97 Warm Reset */
-#define GCR_COLD_RST	(1 << 1)	/* AC'97 Cold Reset (0 = active) */
-#define GCR_GIE		(1 << 0)	/* Codec GPI Interrupt Enable */
-
-#define POSR		0x40500010  /* PCM Out Status Register */
-#define POSR_FIFOE	(1 << 4)	/* FIFO error */
-
-#define PISR		0x40500014  /* PCM In Status Register */
-#define PISR_FIFOE	(1 << 4)	/* FIFO error */
-
-#define MCSR		0x40500018  /* Mic In Status Register */
-#define MCSR_FIFOE	(1 << 4)	/* FIFO error */
-
-#define GSR		0x4050001C  /* Global Status Register */
-#define GSR_CDONE	(1 << 19)	/* Command Done */
-#define GSR_SDONE	(1 << 18)	/* Status Done */
-#define GSR_RDCS	(1 << 15)	/* Read Completion Status */
-#define GSR_BIT3SLT12	(1 << 14)	/* Bit 3 of slot 12 */
-#define GSR_BIT2SLT12	(1 << 13)	/* Bit 2 of slot 12 */
-#define GSR_BIT1SLT12	(1 << 12)	/* Bit 1 of slot 12 */
-#define GSR_SECRES	(1 << 11)	/* Secondary Resume Interrupt */
-#define GSR_PRIRES	(1 << 10)	/* Primary Resume Interrupt */
-#define GSR_SCR		(1 << 9)	/* Secondary Codec Ready */
-#define GSR_PCR		(1 << 8)	/*  Primary Codec Ready */
-#define GSR_MINT	(1 << 7)	/* Mic In Interrupt */
-#define GSR_POINT	(1 << 6)	/* PCM Out Interrupt */
-#define GSR_PIINT	(1 << 5)	/* PCM In Interrupt */
-#define GSR_MOINT	(1 << 2)	/* Modem Out Interrupt */
-#define GSR_MIINT	(1 << 1)	/* Modem In Interrupt */
-#define GSR_GSCI	(1 << 0)	/* Codec GPI Status Change Interrupt */
-
-#define CAR		0x40500020  /* CODEC Access Register */
-#define CAR_CAIP	(1 << 0)	/* Codec Access In Progress */
-
-#define PCDR		0x40500040  /* PCM FIFO Data Register */
-#define MCDR		0x40500060  /* Mic-in FIFO Data Register */
-
-#define MOCR		0x40500100  /* Modem Out Control Register */
-#define MOCR_FEIE	(1 << 3)	/* FIFO Error */
-
-#define MICR		0x40500108  /* Modem In Control Register */
-#define MICR_FEIE	(1 << 3)	/* FIFO Error */
-
-#define MOSR		0x40500110  /* Modem Out Status Register */
-#define MOSR_FIFOE	(1 << 4)	/* FIFO error */
-
-#define MISR		0x40500118  /* Modem In Status Register */
-#define MISR_FIFOE	(1 << 4)	/* FIFO error */
-
-#define MODR		0x40500140  /* Modem FIFO Data Register */
-
-#define PAC_REG_BASE	0x40500200  /* Primary Audio Codec */
-#define SAC_REG_BASE	0x40500300  /* Secondary Audio Codec */
-#define PMC_REG_BASE	0x40500400  /* Primary Modem Codec */
-#define SMC_REG_BASE	0x40500500  /* Secondary Modem Codec */
-
-
-/*
- * USB Device Controller
- */
-#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
-
-#define UDCCR		0x40600000	/* UDC Control Register */
-#define UDCCR_UDE	(1 << 0)		/* UDC enable */
-#define UDCCR_UDA	(1 << 1)		/* UDC active */
-#define UDCCR_RSM	(1 << 2)		/* Device resume */
-#define UDCCR_EMCE	(1 << 3)		/* Endpoint Memory Configuration Error */
-#define UDCCR_SMAC	(1 << 4)		/* Switch Endpoint Memory to Active Configuration */
-#define UDCCR_RESIR	(1 << 29)		/* Resume interrupt request */
-#define UDCCR_SUSIR	(1 << 28)		/* Suspend interrupt request */
-#define UDCCR_SM	(1 << 28)		/* Suspend interrupt mask */
-#define UDCCR_RSTIR	(1 << 27)		/* Reset interrupt request */
-#define UDCCR_REM	(1 << 27)		/* Reset interrupt mask */
-#define UDCCR_RM	(1 << 29)		/* resume interrupt mask */
-#define UDCCR_SRM	(UDCCR_SM|UDCCR_RM)
-#define UDCCR_OEN	(1 << 31)		/* On-the-Go Enable */
-#define UDCCR_AALTHNP	(1 << 30)		/* A-device Alternate Host Negotiation Protocol Port Support */
-#define UDCCR_AHNP	(1 << 29)		/* A-device Host Negotiation Protocol Support */
-#define UDCCR_BHNP	(1 << 28)		/* B-device Host Negotiation Protocol Enable */
-#define UDCCR_DWRE	(1 << 16)		/* Device Remote Wake-up Enable */
-#define UDCCR_ACN	(0x03 << 11)		/* Active UDC configuration Number */
-#define UDCCR_ACN_S	11
-#define UDCCR_AIN	(0x07 << 8)		/* Active UDC interface Number */
-#define UDCCR_AIN_S	8
-#define UDCCR_AAISN	(0x07 << 5)		/* Active UDC Alternate Interface  Setting Number */
-#define UDCCR_AAISN_S	5
-
-#define UDCCS0		0x40600100	/* UDC Endpoint 0 Control/Status Register */
-#define UDCCS0_OPR	(1 << 0)		/* OUT packet ready */
-#define UDCCS0_IPR	(1 << 1)		/* IN packet ready */
-#define UDCCS0_FTF	(1 << 2)		/* Flush Tx FIFO */
-#define UDCCS0_DRWF	(1 << 16)		/* Device remote wakeup feature */
-#define UDCCS0_SST	(1 << 4)		/* Sent stall */
-#define UDCCS0_FST	(1 << 5)		/* Force stall */
-#define UDCCS0_RNE	(1 << 6)		/* Receive FIFO no empty */
-#define UDCCS0_SA	(1 << 7)		/* Setup active */
-
-/* Bulk IN - Endpoint 1,6,11 */
-#define UDCCS1		0x40600104  /* UDC Endpoint 1 (IN) Control/Status Register */
-#define UDCCS6		0x40600028  /* UDC Endpoint 6 (IN) Control/Status Register */
-#define UDCCS11		0x4060003C  /* UDC Endpoint 11 (IN) Control/Status Register */
-
-#define UDCCS_BI_TFS	(1 << 0)	/* Transmit FIFO service */
-#define UDCCS_BI_TPC	(1 << 1)	/* Transmit packet complete */
-#define UDCCS_BI_FTF	(1 << 8)	/* Flush Tx FIFO */
-#define UDCCS_BI_TUR	(1 << 3)	/* Transmit FIFO underrun */
-#define UDCCS_BI_SST	(1 << 4)	/* Sent stall */
-#define UDCCS_BI_FST	(1 << 5)	/* Force stall */
-#define UDCCS_BI_TSP	(1 << 7)	/* Transmit short packet */
-
-/* Bulk OUT - Endpoint 2,7,12 */
-#define UDCCS2		0x40600108  /* UDC Endpoint 2 (OUT) Control/Status Register */
-#define UDCCS7		0x4060002C  /* UDC Endpoint 7 (OUT) Control/Status Register */
-#define UDCCS12		0x40600040  /* UDC Endpoint 12 (OUT) Control/Status Register */
-
-#define UDCCS_BO_RFS	(1 << 0)	/* Receive FIFO service */
-#define UDCCS_BO_RPC	(1 << 1)	/* Receive packet complete */
-#define UDCCS_BO_DME	(1 << 3)	/* DMA enable */
-#define UDCCS_BO_SST	(1 << 4)	/* Sent stall */
-#define UDCCS_BO_FST	(1 << 5)	/* Force stall */
-#define UDCCS_BO_RNE	(1 << 6)	/* Receive FIFO not empty */
-#define UDCCS_BO_RSP	(1 << 7)	/* Receive short packet */
-
-/* Isochronous IN - Endpoint 3,8,13 */
-#define UDCCS3		0x4060001C  /* UDC Endpoint 3 (IN) Control/Status Register */
-#define UDCCS8		0x40600030  /* UDC Endpoint 8 (IN) Control/Status Register */
-#define UDCCS13		0x40600044  /* UDC Endpoint 13 (IN) Control/Status Register */
-
-#define UDCCS_II_TFS	(1 << 0)	/* Transmit FIFO service */
-#define UDCCS_II_TPC	(1 << 1)	/* Transmit packet complete */
-#define UDCCS_II_FTF	(1 << 2)	/* Flush Tx FIFO */
-#define UDCCS_II_TUR	(1 << 3)	/* Transmit FIFO underrun */
-#define UDCCS_II_TSP	(1 << 7)	/* Transmit short packet */
-
-/* Isochronous OUT - Endpoint 4,9,14 */
-#define UDCCS4		0x40600020  /* UDC Endpoint 4 (OUT) Control/Status Register */
-#define UDCCS9		0x40600034  /* UDC Endpoint 9 (OUT) Control/Status Register */
-#define UDCCS14		0x40600048  /* UDC Endpoint 14 (OUT) Control/Status Register */
-
-#define UDCCS_IO_RFS	(1 << 0)	/* Receive FIFO service */
-#define UDCCS_IO_RPC	(1 << 1)	/* Receive packet complete */
-#define UDCCS_IO_ROF	(1 << 3)	/* Receive overflow */
-#define UDCCS_IO_DME	(1 << 3)	/* DMA enable */
-#define UDCCS_IO_RNE	(1 << 6)	/* Receive FIFO not empty */
-#define UDCCS_IO_RSP	(1 << 7)	/* Receive short packet */
-
-/* Interrupt IN - Endpoint 5,10,15 */
-#define UDCCS5		0x40600024  /* UDC Endpoint 5 (Interrupt) Control/Status Register */
-#define UDCCS10		0x40600038  /* UDC Endpoint 10 (Interrupt) Control/Status Register */
-#define UDCCS15		0x4060004C  /* UDC Endpoint 15 (Interrupt) Control/Status Register */
-
-#define UDCCS_INT_TFS	(1 << 0)	/* Transmit FIFO service */
-#define UDCCS_INT_TPC	(1 << 1)	/* Transmit packet complete */
-#define UDCCS_INT_FTF	(1 << 2)	/* Flush Tx FIFO */
-#define UDCCS_INT_TUR	(1 << 3)	/* Transmit FIFO underrun */
-#define UDCCS_INT_SST	(1 << 4)	/* Sent stall */
-#define UDCCS_INT_FST	(1 << 5)	/* Force stall */
-#define UDCCS_INT_TSP	(1 << 7)	/* Transmit short packet */
-
-#define UFNRH		0x40600060  /* UDC Frame Number Register High */
-#define UFNRL		0x40600014  /* UDC Frame Number Register Low */
-#define UBCR2		0x40600208  /* UDC Byte Count Reg 2 */
-#define UBCR4		0x4060006c  /* UDC Byte Count Reg 4 */
-#define UBCR7		0x40600070  /* UDC Byte Count Reg 7 */
-#define UBCR9		0x40600074  /* UDC Byte Count Reg 9 */
-#define UBCR12		0x40600078  /* UDC Byte Count Reg 12 */
-#define UBCR14		0x4060007c  /* UDC Byte Count Reg 14 */
-#define UDDR0		0x40600300  /* UDC Endpoint 0 Data Register */
-#define UDDR1		0x40600304  /* UDC Endpoint 1 Data Register */
-#define UDDR2		0x40600308  /* UDC Endpoint 2 Data Register */
-#define UDDR3		0x40600200  /* UDC Endpoint 3 Data Register */
-#define UDDR4		0x40600400  /* UDC Endpoint 4 Data Register */
-#define UDDR5		0x406000A0  /* UDC Endpoint 5 Data Register */
-#define UDDR6		0x40600600  /* UDC Endpoint 6 Data Register */
-#define UDDR7		0x40600680  /* UDC Endpoint 7 Data Register */
-#define UDDR8		0x40600700  /* UDC Endpoint 8 Data Register */
-#define UDDR9		0x40600900  /* UDC Endpoint 9 Data Register */
-#define UDDR10		0x406000C0  /* UDC Endpoint 10 Data Register */
-#define UDDR11		0x40600B00  /* UDC Endpoint 11 Data Register */
-#define UDDR12		0x40600B80  /* UDC Endpoint 12 Data Register */
-#define UDDR13		0x40600C00  /* UDC Endpoint 13 Data Register */
-#define UDDR14		0x40600E00  /* UDC Endpoint 14 Data Register */
-#define UDDR15		0x406000E0  /* UDC Endpoint 15 Data Register */
-
-#define UICR0		0x40600004  /* UDC Interrupt Control Register 0 */
-
-#define UICR0_IM0	(1 << 0)	/* Interrupt mask ep 0 */
-#define UICR0_IM1	(1 << 1)	/* Interrupt mask ep 1 */
-#define UICR0_IM2	(1 << 2)	/* Interrupt mask ep 2 */
-#define UICR0_IM3	(1 << 3)	/* Interrupt mask ep 3 */
-#define UICR0_IM4	(1 << 4)	/* Interrupt mask ep 4 */
-#define UICR0_IM5	(1 << 5)	/* Interrupt mask ep 5 */
-#define UICR0_IM6	(1 << 6)	/* Interrupt mask ep 6 */
-#define UICR0_IM7	(1 << 7)	/* Interrupt mask ep 7 */
-
-#define UICR1		0x40600008  /* UDC Interrupt Control Register 1 */
-
-#define UICR1_IM8	(1 << 0)	/* Interrupt mask ep 8 */
-#define UICR1_IM9	(1 << 1)	/* Interrupt mask ep 9 */
-#define UICR1_IM10	(1 << 2)	/* Interrupt mask ep 10 */
-#define UICR1_IM11	(1 << 3)	/* Interrupt mask ep 11 */
-#define UICR1_IM12	(1 << 4)	/* Interrupt mask ep 12 */
-#define UICR1_IM13	(1 << 5)	/* Interrupt mask ep 13 */
-#define UICR1_IM14	(1 << 6)	/* Interrupt mask ep 14 */
-#define UICR1_IM15	(1 << 7)	/* Interrupt mask ep 15 */
-
-#define USIR0		0x4060000C  /* UDC Status Interrupt Register 0 */
-
-#define USIR0_IR0	(1 << 0)	/* Interrup request ep 0 */
-#define USIR0_IR1	(1 << 2)	/* Interrup request ep 1 */
-#define USIR0_IR2	(1 << 4)	/* Interrup request ep 2 */
-#define USIR0_IR3	(1 << 3)	/* Interrup request ep 3 */
-#define USIR0_IR4	(1 << 4)	/* Interrup request ep 4 */
-#define USIR0_IR5	(1 << 5)	/* Interrup request ep 5 */
-#define USIR0_IR6	(1 << 6)	/* Interrup request ep 6 */
-#define USIR0_IR7	(1 << 7)	/* Interrup request ep 7 */
-
-#define USIR1		0x40600010  /* UDC Status Interrupt Register 1 */
-
-#define USIR1_IR8	(1 << 0)	/* Interrup request ep 8 */
-#define USIR1_IR9	(1 << 1)	/* Interrup request ep 9 */
-#define USIR1_IR10	(1 << 2)	/* Interrup request ep 10 */
-#define USIR1_IR11	(1 << 3)	/* Interrup request ep 11 */
-#define USIR1_IR12	(1 << 4)	/* Interrup request ep 12 */
-#define USIR1_IR13	(1 << 5)	/* Interrup request ep 13 */
-#define USIR1_IR14	(1 << 6)	/* Interrup request ep 14 */
-#define USIR1_IR15	(1 << 7)	/* Interrup request ep 15 */
-
-
-#define UDCICR0         0x40600004	/* UDC Interrupt Control Register0 */
-#define UDCICR1         0x40600008	/* UDC Interrupt Control Register1 */
-#define UDCICR_FIFOERR	(1 << 1)			/* FIFO Error interrupt for EP */
-#define UDCICR_PKTCOMPL (1 << 0)			/* Packet Complete interrupt for EP */
-
-#define UDCICR_INT(n, intr) (((intr) & 0x03) << (((n) & 0x0F) * 2))
-#define UDCICR1_IECC	(1 << 31)	/* IntEn - Configuration Change */
-#define UDCICR1_IESOF	(1 << 30)	/* IntEn - Start of Frame */
-#define UDCICR1_IERU	(1 << 29)	/* IntEn - Resume */
-#define UDCICR1_IESU	(1 << 28)	/* IntEn - Suspend */
-#define UDCICR1_IERS	(1 << 27)	/* IntEn - Reset */
-
-#define UDCISR0         0x4060000C /* UDC Interrupt Status Register 0 */
-#define UDCISR1         0x40600010 /* UDC Interrupt Status Register 1 */
-#define UDCISR_INT(n, intr) (((intr) & 0x03) << (((n) & 0x0F) * 2))
-#define UDCISR1_IRCC	(1 << 31)	/* IntEn - Configuration Change */
-#define UDCISR1_IRSOF	(1 << 30)	/* IntEn - Start of Frame */
-#define UDCISR1_IRRU	(1 << 29)	/* IntEn - Resume */
-#define UDCISR1_IRSU	(1 << 28)	/* IntEn - Suspend */
-#define UDCISR1_IRRS	(1 << 27)	/* IntEn - Reset */
-
-
-#define UDCFNR			0x40600014 /* UDC Frame Number Register */
-#define UDCOTGICR		0x40600018 /* UDC On-The-Go interrupt control */
-#define UDCOTGICR_IESF		(1 << 24)	/* OTG SET_FEATURE command recvd */
-#define UDCOTGICR_IEXR		(1 << 17)	/* Extra Transciever Interrupt Rising Edge Interrupt Enable */
-#define UDCOTGICR_IEXF		(1 << 16)	/* Extra Transciever Interrupt Falling Edge Interrupt Enable */
-#define UDCOTGICR_IEVV40R	(1 << 9)	/* OTG Vbus Valid 4.0V Rising Edge Interrupt Enable */
-#define UDCOTGICR_IEVV40F	(1 << 8)	/* OTG Vbus Valid 4.0V Falling Edge Interrupt Enable */
-#define UDCOTGICR_IEVV44R	(1 << 7)	/* OTG Vbus Valid 4.4V Rising Edge  Interrupt Enable */
-#define UDCOTGICR_IEVV44F	(1 << 6)	/* OTG Vbus Valid 4.4V Falling Edge Interrupt Enable */
-#define UDCOTGICR_IESVR		(1 << 5)	/* OTG Session Valid Rising Edge Interrupt Enable */
-#define UDCOTGICR_IESVF		(1 << 4)	/* OTG Session Valid Falling Edge Interrupt Enable */
-#define UDCOTGICR_IESDR		(1 << 3)	/* OTG A-Device SRP Detect Rising Edge Interrupt Enable */
-#define UDCOTGICR_IESDF		(1 << 2)	/* OTG A-Device SRP Detect Falling  Edge Interrupt Enable */
-#define UDCOTGICR_IEIDR		(1 << 1)	/* OTG ID Change Rising Edge Interrupt Enable */
-#define UDCOTGICR_IEIDF		(1 << 0)	/* OTG ID Change Falling Edge Interrupt Enable */
-
-#define UDCCSN(x)	__REG2(0x40600100, (x) << 2)
-#define UDCCSR0		0x40600100 /* UDC Control/Status register - Endpoint 0 */
-
-#define UDCCSR0_SA	(1 << 7)	/* Setup Active */
-#define UDCCSR0_RNE	(1 << 6)	/* Receive FIFO Not Empty */
-#define UDCCSR0_FST	(1 << 5)	/* Force Stall */
-#define UDCCSR0_SST	(1 << 4)	/* Sent Stall */
-#define UDCCSR0_DME	(1 << 3)	/* DMA Enable */
-#define UDCCSR0_FTF	(1 << 2)	/* Flush Transmit FIFO */
-#define UDCCSR0_IPR	(1 << 1)	/* IN Packet Ready */
-#define UDCCSR0_OPC	(1 << 0)	/* OUT Packet Complete */
-
-#define UDCCSRA         0x40600104 /* UDC Control/Status register - Endpoint A */
-#define UDCCSRB         0x40600108 /* UDC Control/Status register - Endpoint B */
-#define UDCCSRC         0x4060010C /* UDC Control/Status register - Endpoint C */
-#define UDCCSRD         0x40600110 /* UDC Control/Status register - Endpoint D */
-#define UDCCSRE         0x40600114 /* UDC Control/Status register - Endpoint E */
-#define UDCCSRF         0x40600118 /* UDC Control/Status register - Endpoint F */
-#define UDCCSRG         0x4060011C /* UDC Control/Status register - Endpoint G */
-#define UDCCSRH         0x40600120 /* UDC Control/Status register - Endpoint H */
-#define UDCCSRI         0x40600124 /* UDC Control/Status register - Endpoint I */
-#define UDCCSRJ         0x40600128 /* UDC Control/Status register - Endpoint J */
-#define UDCCSRK         0x4060012C /* UDC Control/Status register - Endpoint K */
-#define UDCCSRL         0x40600130 /* UDC Control/Status register - Endpoint L */
-#define UDCCSRM         0x40600134 /* UDC Control/Status register - Endpoint M */
-#define UDCCSRN         0x40600138 /* UDC Control/Status register - Endpoint N */
-#define UDCCSRP         0x4060013C /* UDC Control/Status register - Endpoint P */
-#define UDCCSRQ         0x40600140 /* UDC Control/Status register - Endpoint Q */
-#define UDCCSRR         0x40600144 /* UDC Control/Status register - Endpoint R */
-#define UDCCSRS         0x40600148 /* UDC Control/Status register - Endpoint S */
-#define UDCCSRT         0x4060014C /* UDC Control/Status register - Endpoint T */
-#define UDCCSRU         0x40600150 /* UDC Control/Status register - Endpoint U */
-#define UDCCSRV         0x40600154 /* UDC Control/Status register - Endpoint V */
-#define UDCCSRW         0x40600158 /* UDC Control/Status register - Endpoint W */
-#define UDCCSRX         0x4060015C /* UDC Control/Status register - Endpoint X */
-
-#define UDCCSR_DPE	(1 << 9)	/* Data Packet Error */
-#define UDCCSR_FEF	(1 << 8)	/* Flush Endpoint FIFO */
-#define UDCCSR_SP	(1 << 7)	/* Short Packet Control/Status */
-#define UDCCSR_BNE	(1 << 6)	/* Buffer Not Empty (IN endpoints) */
-#define UDCCSR_BNF	(1 << 6)	/* Buffer Not Full (OUT endpoints) */
-#define UDCCSR_FST	(1 << 5)	/* Force STALL */
-#define UDCCSR_SST	(1 << 4)	/* Sent STALL */
-#define UDCCSR_DME	(1 << 3)	/* DMA Enable */
-#define UDCCSR_TRN	(1 << 2)	/* Tx/Rx NAK */
-#define UDCCSR_PC	(1 << 1)	/* Packet Complete */
-#define UDCCSR_FS	(1 << 0)	/* FIFO needs service */
-
-#define UDCBCN(x)	__REG2(0x40600200, (x)<<2)
-#define UDCBCR0         0x40600200 /* Byte Count Register - EP0 */
-#define UDCBCRA         0x40600204 /* Byte Count Register - EPA */
-#define UDCBCRB         0x40600208 /* Byte Count Register - EPB */
-#define UDCBCRC         0x4060020C /* Byte Count Register - EPC */
-#define UDCBCRD         0x40600210 /* Byte Count Register - EPD */
-#define UDCBCRE         0x40600214 /* Byte Count Register - EPE */
-#define UDCBCRF         0x40600218 /* Byte Count Register - EPF */
-#define UDCBCRG         0x4060021C /* Byte Count Register - EPG */
-#define UDCBCRH         0x40600220 /* Byte Count Register - EPH */
-#define UDCBCRI         0x40600224 /* Byte Count Register - EPI */
-#define UDCBCRJ         0x40600228 /* Byte Count Register - EPJ */
-#define UDCBCRK         0x4060022C /* Byte Count Register - EPK */
-#define UDCBCRL         0x40600230 /* Byte Count Register - EPL */
-#define UDCBCRM         0x40600234 /* Byte Count Register - EPM */
-#define UDCBCRN         0x40600238 /* Byte Count Register - EPN */
-#define UDCBCRP         0x4060023C /* Byte Count Register - EPP */
-#define UDCBCRQ         0x40600240 /* Byte Count Register - EPQ */
-#define UDCBCRR         0x40600244 /* Byte Count Register - EPR */
-#define UDCBCRS         0x40600248 /* Byte Count Register - EPS */
-#define UDCBCRT         0x4060024C /* Byte Count Register - EPT */
-#define UDCBCRU         0x40600250 /* Byte Count Register - EPU */
-#define UDCBCRV         0x40600254 /* Byte Count Register - EPV */
-#define UDCBCRW         0x40600258 /* Byte Count Register - EPW */
-#define UDCBCRX         0x4060025C /* Byte Count Register - EPX */
-
-#define UDCDN(x)	__REG2(0x40600300, (x)<<2)
-#define UDCDR0          0x40600300 /* Data Register - EP0 */
-#define UDCDRA          0x40600304 /* Data Register - EPA */
-#define UDCDRB          0x40600308 /* Data Register - EPB */
-#define UDCDRC          0x4060030C /* Data Register - EPC */
-#define UDCDRD          0x40600310 /* Data Register - EPD */
-#define UDCDRE          0x40600314 /* Data Register - EPE */
-#define UDCDRF          0x40600318 /* Data Register - EPF */
-#define UDCDRG          0x4060031C /* Data Register - EPG */
-#define UDCDRH          0x40600320 /* Data Register - EPH */
-#define UDCDRI          0x40600324 /* Data Register - EPI */
-#define UDCDRJ          0x40600328 /* Data Register - EPJ */
-#define UDCDRK          0x4060032C /* Data Register - EPK */
-#define UDCDRL          0x40600330 /* Data Register - EPL */
-#define UDCDRM          0x40600334 /* Data Register - EPM */
-#define UDCDRN          0x40600338 /* Data Register - EPN */
-#define UDCDRP          0x4060033C /* Data Register - EPP */
-#define UDCDRQ          0x40600340 /* Data Register - EPQ */
-#define UDCDRR          0x40600344 /* Data Register - EPR */
-#define UDCDRS          0x40600348 /* Data Register - EPS */
-#define UDCDRT          0x4060034C /* Data Register - EPT */
-#define UDCDRU          0x40600350 /* Data Register - EPU */
-#define UDCDRV          0x40600354 /* Data Register - EPV */
-#define UDCDRW          0x40600358 /* Data Register - EPW */
-#define UDCDRX          0x4060035C /* Data Register - EPX */
-
-#define UDCCN(x)	__REG2(0x40600400, (x)<<2)
-#define UDCCRA          0x40600404 /* Configuration register EPA */
-#define UDCCRB          0x40600408 /* Configuration register EPB */
-#define UDCCRC          0x4060040C /* Configuration register EPC */
-#define UDCCRD          0x40600410 /* Configuration register EPD */
-#define UDCCRE          0x40600414 /* Configuration register EPE */
-#define UDCCRF          0x40600418 /* Configuration register EPF */
-#define UDCCRG          0x4060041C /* Configuration register EPG */
-#define UDCCRH          0x40600420 /* Configuration register EPH */
-#define UDCCRI          0x40600424 /* Configuration register EPI */
-#define UDCCRJ          0x40600428 /* Configuration register EPJ */
-#define UDCCRK          0x4060042C /* Configuration register EPK */
-#define UDCCRL          0x40600430 /* Configuration register EPL */
-#define UDCCRM          0x40600434 /* Configuration register EPM */
-#define UDCCRN          0x40600438 /* Configuration register EPN */
-#define UDCCRP          0x4060043C /* Configuration register EPP */
-#define UDCCRQ          0x40600440 /* Configuration register EPQ */
-#define UDCCRR          0x40600444 /* Configuration register EPR */
-#define UDCCRS          0x40600448 /* Configuration register EPS */
-#define UDCCRT          0x4060044C /* Configuration register EPT */
-#define UDCCRU          0x40600450 /* Configuration register EPU */
-#define UDCCRV          0x40600454 /* Configuration register EPV */
-#define UDCCRW          0x40600458 /* Configuration register EPW */
-#define UDCCRX          0x4060045C /* Configuration register EPX */
-
-#define UDCCONR_CN	(0x03 << 25)	/* Configuration Number */
-#define UDCCONR_CN_S	(25)
-#define UDCCONR_IN	(0x07 << 22)	/* Interface Number */
-#define UDCCONR_IN_S	(22)
-#define UDCCONR_AISN	(0x07 << 19)	/* Alternate Interface Number */
-#define UDCCONR_AISN_S	(19)
-#define UDCCONR_EN	(0x0f << 15)	/* Endpoint Number */
-#define UDCCONR_EN_S	(15)
-#define UDCCONR_ET	(0x03 << 13)	/* Endpoint Type: */
-#define UDCCONR_ET_S	(13)
-#define UDCCONR_ET_INT	(0x03 << 13)	/* Interrupt */
-#define UDCCONR_ET_BULK	(0x02 << 13)	/* Bulk */
-#define UDCCONR_ET_ISO	(0x01 << 13)	/* Isochronous */
-#define UDCCONR_ET_NU	(0x00 << 13)	/* Not used */
-#define UDCCONR_ED	(1 << 12)	/* Endpoint Direction */
-#define UDCCONR_MPS	(0x3ff << 2)	/* Maximum Packet Size */
-#define UDCCONR_MPS_S	(2)
-#define UDCCONR_DE	(1 << 1)	/* Double Buffering Enable */
-#define UDCCONR_EE	(1 << 0)	/* Endpoint Enable */
-
-
-#define UDC_INT_FIFOERROR	(0x2)
-#define UDC_INT_PACKETCMP	(0x1)
-#define UDC_FNR_MASK		(0x7ff)
-#define UDCCSR_WR_MASK		(UDCCSR_DME|UDCCSR_FST)
-#define UDC_BCR_MASK		(0x3ff)
-
-#endif /* CONFIG_PXA27X */
-
-#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
-
-/******************************************************************************/
-/*
- * USB Host Controller
- */
-#define OHCI_REGS_BASE	0x4C000000	/* required for ohci driver */
-#define UHCREV		0x4C000000
-#define UHCHCON		0x4C000004
-#define UHCCOMS		0x4C000008
-#define UHCINTS		0x4C00000C
-#define UHCINTE		0x4C000010
-#define UHCINTD		0x4C000014
-#define UHCHCCA		0x4C000018
-#define UHCPCED		0x4C00001C
-#define UHCCHED		0x4C000020
-#define UHCCCED		0x4C000024
-#define UHCBHED		0x4C000028
-#define UHCBCED		0x4C00002C
-#define UHCDHEAD	0x4C000030
-#define UHCFMI		0x4C000034
-#define UHCFMR		0x4C000038
-#define UHCFMN		0x4C00003C
-#define UHCPERS		0x4C000040
-#define UHCLST		0x4C000044
-#define UHCRHDA		0x4C000048
-#define UHCRHDB		0x4C00004C
-#define UHCRHS		0x4C000050
-#define UHCRHPS1	0x4C000054
-#define UHCRHPS2	0x4C000058
-#define UHCRHPS3	0x4C00005C
-#define UHCSTAT		0x4C000060
-#define UHCHR		0x4C000064
-#define UHCHIE		0x4C000068
-#define UHCHIT		0x4C00006C
-
-#define UHCHR_FSBIR	(1<<0)
-#define UHCHR_FHR	(1<<1)
-#define UHCHR_CGR	(1<<2)
-#define UHCHR_SSDC	(1<<3)
-#define UHCHR_UIT	(1<<4)
-#define UHCHR_SSE	(1<<5)
-#define UHCHR_PSPL	(1<<6)
-#define UHCHR_PCPL	(1<<7)
-#define UHCHR_SSEP0	(1<<9)
-#define UHCHR_SSEP1	(1<<10)
-#define UHCHR_SSEP2	(1<<11)
-
-#define UHCHIE_UPRIE	(1<<13)
-#define UHCHIE_UPS2IE	(1<<12)
-#define UHCHIE_UPS1IE	(1<<11)
-#define UHCHIE_TAIE	(1<<10)
-#define UHCHIE_HBAIE	(1<<8)
-#define UHCHIE_RWIE	(1<<7)
-
-#define UP2OCR		0x40600020
-
-#define UP2OCR_HXOE	(1<<17)
-#define UP2OCR_HXS	(1<<16)
-#define UP2OCR_IDON	(1<<10)
-#define UP2OCR_EXSUS	(1<<9)
-#define UP2OCR_EXSP	(1<<8)
-#define UP2OCR_DMSTATE	(1<<7)
-#define UP2OCR_VPM	(1<<6)
-#define UP2OCR_DPSTATE	(1<<5)
-#define UP2OCR_DPPUE	(1<<4)
-#define UP2OCR_DMPDE	(1<<3)
-#define UP2OCR_DPPDE	(1<<2)
-#define UP2OCR_CPVPE	(1<<1)
-#define UP2OCR_CPVEN	(1<<0)
-
-#endif	/* CONFIG_PXA27X || CONFIG_CPU_MONAHANS */
-
-/******************************************************************************/
-/*
- * Fast Infrared Communication Port
- */
-#define ICCR0		0x40800000  /* ICP Control Register 0 */
-#define ICCR1		0x40800004  /* ICP Control Register 1 */
-#define ICCR2		0x40800008  /* ICP Control Register 2 */
-#define ICDR		0x4080000c  /* ICP Data Register */
-#define ICSR0		0x40800014  /* ICP Status Register 0 */
-#define ICSR1		0x40800018  /* ICP Status Register 1 */
-
-/*
- * Real Time Clock
- */
-#define RCNR		0x40900000  /* RTC Count Register */
-#define RTAR		0x40900004  /* RTC Alarm Register */
-#define RTSR		0x40900008  /* RTC Status Register */
-#define RTTR		0x4090000C  /* RTC Timer Trim Register */
-#define RDAR1		0x40900018  /* Wristwatch Day Alarm Reg 1 */
-#define RDAR2		0x40900020  /* Wristwatch Day Alarm Reg 2 */
-#define RYAR1		0x4090001C  /* Wristwatch Year Alarm Reg 1 */
-#define RYAR2		0x40900024  /* Wristwatch Year Alarm Reg 2 */
-#define SWAR1		0x4090002C  /* Stopwatch Alarm Register 1 */
-#define SWAR2		0x40900030  /* Stopwatch Alarm Register 2 */
-#define PIAR		0x40900038  /* Periodic Interrupt Alarm Register */
-#define RDCR		0x40900010  /* RTC Day Count Register. */
-#define RYCR		0x40900014  /* RTC Year Count Register. */
-#define SWCR		0x40900028  /* Stopwatch Count Register */
-#define RTCPICR		0x40900034  /* Periodic Interrupt Counter Register */
-
-#define RTSR_PICE	(1 << 15)	/* Peridoc interrupt count enable */
-#define RTSR_PIALE	(1 << 14)	/* Peridoc interrupt Alarm enable */
-#define RTSR_PIAL	(1 << 13)	/* Peridoc  interrupt Alarm status */
-#define RTSR_HZE	(1 << 3)	/* HZ interrupt enable */
-#define RTSR_ALE	(1 << 2)	/* RTC alarm interrupt enable */
-#define RTSR_HZ		(1 << 1)	/* HZ rising-edge detected */
-#define RTSR_AL		(1 << 0)	/* RTC alarm detected */
-
-/******************************************************************************/
-/*
- * OS Timer & Match Registers
- */
-#define OSMR0		0x40A00000  /* OS Timer Match Register 0 */
-#define OSMR1		0x40A00004  /* OS Timer Match Register 1 */
-#define OSMR2		0x40A00008  /* OS Timer Match Register 2 */
-#define OSMR3		0x40A0000C  /* OS Timer Match Register 3 */
-#define OSCR		0x40A00010  /* OS Timer Counter Register */
-#define OSSR		0x40A00014  /* OS Timer Status Register */
-#define OWER		0x40A00018  /* OS Timer Watchdog Enable Register */
-#define OIER		0x40A0001C  /* OS Timer Interrupt Enable Register */
-
-#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
-#define OSCR4		0x40A00040  /* OS Timer Counter Register 4 */
-#define OSCR5		0x40A00044  /* OS Timer Counter Register 5 */
-#define OSCR6		0x40A00048  /* OS Timer Counter Register 6 */
-#define OSCR7		0x40A0004C  /* OS Timer Counter Register 7 */
-#define OSCR8		0x40A00050  /* OS Timer Counter Register 8 */
-#define OSCR9		0x40A00054  /* OS Timer Counter Register 9 */
-#define OSCR10		0x40A00058  /* OS Timer Counter Register 10 */
-#define OSCR11		0x40A0005C  /* OS Timer Counter Register 11 */
-
-#define OSMR4		0x40A00080  /* OS Timer Match Register 4 */
-#define OSMR5		0x40A00084  /* OS Timer Match Register 5 */
-#define OSMR6		0x40A00088  /* OS Timer Match Register 6 */
-#define OSMR7		0x40A0008C  /* OS Timer Match Register 7 */
-#define OSMR8		0x40A00090  /* OS Timer Match Register 8 */
-#define OSMR9		0x40A00094  /* OS Timer Match Register 9 */
-#define OSMR10		0x40A00098  /* OS Timer Match Register 10 */
-#define OSMR11		0x40A0009C  /* OS Timer Match Register 11 */
-
-#define OMCR4		0x40A000C0  /* OS Match Control Register 4 */
-#define OMCR5		0x40A000C4  /* OS Match Control Register 5 */
-#define OMCR6		0x40A000C8  /* OS Match Control Register 6 */
-#define OMCR7		0x40A000CC  /* OS Match Control Register 7 */
-#define OMCR8		0x40A000D0  /* OS Match Control Register 8 */
-#define OMCR9		0x40A000D4  /* OS Match Control Register 9 */
-#define OMCR10		0x40A000D8  /* OS Match Control Register 10 */
-#define OMCR11		0x40A000DC  /* OS Match Control Register 11 */
-
-#endif /* CONFIG_PXA27X || CONFIG_CPU_MONAHANS */
-
-#define OSSR_M4		(1 << 4)	/* Match status channel 4 */
-#define OSSR_M3		(1 << 3)	/* Match status channel 3 */
-#define OSSR_M2		(1 << 2)	/* Match status channel 2 */
-#define OSSR_M1		(1 << 1)	/* Match status channel 1 */
-#define OSSR_M0		(1 << 0)	/* Match status channel 0 */
-
-#define OWER_WME	(1 << 0)	/* Watchdog Match Enable */
-
-#define OIER_E4		(1 << 4)	/* Interrupt enable channel 4 */
-#define OIER_E3		(1 << 3)	/* Interrupt enable channel 3 */
-#define OIER_E2		(1 << 2)	/* Interrupt enable channel 2 */
-#define OIER_E1		(1 << 1)	/* Interrupt enable channel 1 */
-#define OIER_E0		(1 << 0)	/* Interrupt enable channel 0 */
-
-#define	OSCR_CLK_FREQ	3250
-
-/******************************************************************************/
-/*
- * Core Clock
- */
-
-#if defined(CONFIG_CPU_MONAHANS)
-#define ACCR		0x41340000  /* Application Subsystem Clock Configuration Register */
-#define ACSR		0x41340004  /* Application Subsystem Clock Status Register */
-#define AICSR		0x41340008  /* Application Subsystem Interrupt Control/Status Register */
-#define CKENA		0x4134000C  /* A Clock Enable Register */
-#define CKENB		0x41340010  /* B Clock Enable Register */
-#define AC97_DIV	0x41340014  /* AC97 clock divisor value register */
-
-#define ACCR_SMC_MASK	0x03800000	/* Static Memory Controller Frequency Select */
-#define ACCR_SRAM_MASK	0x000c0000	/* SRAM Controller Frequency Select */
-#define ACCR_FC_MASK	0x00030000	/* Frequency Change Frequency Select */
-#define ACCR_HSIO_MASK	0x0000c000	/* High Speed IO Frequency Select */
-#define ACCR_DDR_MASK	0x00003000	/* DDR Memory Controller Frequency Select */
-#define ACCR_XN_MASK	0x00000700	/* Run Mode Frequency to Turbo Mode Frequency Multiplier */
-#define ACCR_XL_MASK	0x0000001f	/* Crystal Frequency to Memory Frequency Multiplier */
-#define ACCR_XPDIS	(1 << 31)
-#define ACCR_SPDIS	(1 << 30)
-#define ACCR_13MEND1	(1 << 27)
-#define ACCR_D0CS	(1 << 26)
-#define ACCR_13MEND2	(1 << 21)
-#define ACCR_PCCE	(1 << 11)
-
-#define CKENA_30_MSL0	(1 << 30)	/* MSL0 Interface Unit Clock Enable */
-#define CKENA_29_SSP4	(1 << 29)	/* SSP3 Unit Clock Enable */
-#define CKENA_28_SSP3	(1 << 28)	/* SSP2 Unit Clock Enable */
-#define CKENA_27_SSP2	(1 << 27)	/* SSP1 Unit Clock Enable */
-#define CKENA_26_SSP1	(1 << 26)	/* SSP0 Unit Clock Enable */
-#define CKENA_25_TSI	(1 << 25)	/* TSI Clock Enable */
-#define CKENA_24_AC97	(1 << 24)	/* AC97 Unit Clock Enable */
-#define CKENA_23_STUART	(1 << 23)	/* STUART Unit Clock Enable */
-#define CKENA_22_FFUART	(1 << 22)	/* FFUART Unit Clock Enable */
-#define CKENA_21_BTUART	(1 << 21)	/* BTUART Unit Clock Enable */
-#define CKENA_20_UDC	(1 << 20)	/* UDC Clock Enable */
-#define CKENA_19_TPM	(1 << 19)	/* TPM Unit Clock Enable */
-#define CKENA_18_USIM1	(1 << 18)	/* USIM1 Unit Clock Enable */
-#define CKENA_17_USIM0	(1 << 17)	/* USIM0 Unit Clock Enable */
-#define CKENA_15_CIR	(1 << 15)	/* Consumer IR Clock Enable */
-#define CKENA_14_KEY	(1 << 14)	/* Keypad Controller Clock Enable */
-#define CKENA_13_MMC1	(1 << 13)	/* MMC1 Clock Enable */
-#define CKENA_12_MMC0	(1 << 12)	/* MMC0 Clock Enable */
-#define CKENA_11_FLASH	(1 << 11)	/* Boot ROM Clock Enable */
-#define CKENA_10_SRAM	(1 << 10)	/* SRAM Controller Clock Enable */
-#define CKENA_9_SMC	(1 << 9)	/* Static Memory Controller */
-#define CKENA_8_DMC	(1 << 8)	/* Dynamic Memory Controller */
-#define CKENA_7_GRAPHICS (1 << 7)	/* 2D Graphics Clock Enable */
-#define CKENA_6_USBCLI	(1 << 6)	/* USB Client Unit Clock Enable */
-#define CKENA_4_NAND	(1 << 4)	/* NAND Flash Controller Clock Enable */
-#define CKENA_3_CAMERA	(1 << 3)	/* Camera Interface Clock Enable */
-#define CKENA_2_USBHOST	(1 << 2)	/* USB Host Unit Clock Enable */
-#define CKENA_1_LCD	(1 << 1)	/* LCD Unit Clock Enable */
-
-#define CKENB_9_SYSBUS2	(1 << 9)	/* System bus 2 */
-#define CKENB_8_1WIRE	(1 << 8)	/* One Wire Interface Unit Clock Enable */
-#define CKENB_7_GPIO	(1 << 7)	/* GPIO Clock Enable */
-#define CKENB_6_IRQ	(1 << 6)	/* Interrupt Controller Clock Enable */
-#define CKENB_4_I2C	(1 << 4)	/* I2C Unit Clock Enable */
-#define CKENB_1_PWM1	(1 << 1)	/* PWM2 & PWM3 Clock Enable */
-#define CKENB_0_PWM0	(1 << 0)	/* PWM0 & PWM1 Clock Enable */
-
-#else /* if defined CONFIG_CPU_MONAHANS */
-
-#define CCCR		0x41300000  /* Core Clock Configuration Register */
-#define CKEN		0x41300004  /* Clock Enable Register */
-#define OSCC		0x41300008  /* Oscillator Configuration Register */
-#define CCSR		0x4130000C /* Core Clock Status Register */
-
-#define CKEN23_SSP1	(1 << 23) /* SSP1 Unit Clock Enable */
-#define CKEN22_MEMC	(1 << 22) /* Memory Controler */
-#define CKEN21_MSHC	(1 << 21) /* Memery Stick Host Controller */
-#define CKEN20_IM	(1 << 20) /* Internal Memory Clock Enable */
-#define CKEN19_KEYPAD	(1 << 19) /* Keypad Interface Clock Enable */
-#define CKEN18_USIM	(1 << 18) /* USIM Unit Clock Enable */
-#define CKEN17_MSL	(1 << 17) /* MSL Interface Unit Clock Enable */
-#define CKEN15_PWR_I2C	(1 << 15) /* PWR_I2C Unit Clock Enable */
-#define CKEN9_OST	(1 << 9)  /* OS Timer Unit Clock Enable */
-#define CKEN4_SSP3	(1 << 4)  /* SSP3 Unit Clock Enable */
-
-#define CCCR_N_MASK	0x0380		/* Run Mode Frequency to Turbo Mode Frequency Multiplier */
-#if !defined(CONFIG_PXA27X)
-#define CCCR_M_MASK	0x0060		/* Memory Frequency to Run Mode Frequency Multiplier */
-#endif
-#define CCCR_L_MASK	0x001f		/* Crystal Frequency to Memory Frequency Multiplier */
-
-#define CKEN24_CAMERA	(1 << 24)	/* Camera Interface Clock Enable */
-#define CKEN23_SSP1	(1 << 23)	/* SSP1 Unit Clock Enable */
-#define CKEN22_MEMC	(1 << 22)	/* Memory Controller Clock Enable */
-#define CKEN21_MEMSTK	(1 << 21)	/* Memory Stick Host Controller */
-#define CKEN20_IM	(1 << 20)	/* Internal Memory Clock Enable */
-#define CKEN19_KEYPAD	(1 << 19)	/* Keypad Interface Clock Enable */
-#define CKEN18_USIM	(1 << 18)	/* USIM Unit Clock Enable */
-#define CKEN17_MSL	(1 << 17)	/* MSL Unit Clock Enable */
-#define CKEN16_LCD	(1 << 16)	/* LCD Unit Clock Enable */
-#define CKEN15_PWRI2C	(1 << 15)	/* PWR I2C Unit Clock Enable */
-#define CKEN14_I2C	(1 << 14)	/* I2C Unit Clock Enable */
-#define CKEN13_FICP	(1 << 13)	/* FICP Unit Clock Enable */
-#define CKEN12_MMC	(1 << 12)	/* MMC Unit Clock Enable */
-#define CKEN11_USB	(1 << 11)	/* USB Unit Clock Enable */
-#if defined(CONFIG_PXA27X)
-#define CKEN10_USBHOST	(1 << 10)	/* USB Host Unit Clock Enable */
-#define CKEN24_CAMERA	(1 << 24)	/* Camera Unit Clock Enable */
-#endif
-#define CKEN8_I2S	(1 << 8)	/* I2S Unit Clock Enable */
-#define CKEN7_BTUART	(1 << 7)	/* BTUART Unit Clock Enable */
-#define CKEN6_FFUART	(1 << 6)	/* FFUART Unit Clock Enable */
-#define CKEN5_STUART	(1 << 5)	/* STUART Unit Clock Enable */
-#define CKEN3_SSP	(1 << 3)	/* SSP Unit Clock Enable */
-#define CKEN2_AC97	(1 << 2)	/* AC97 Unit Clock Enable */
-#define CKEN1_PWM1	(1 << 1)	/* PWM1 Clock Enable */
-#define CKEN0_PWM0	(1 << 0)	/* PWM0 Clock Enable */
-
-#define OSCC_OON	(1 << 1)	/* 32.768kHz OON (write-once only bit) */
-#define OSCC_OOK	(1 << 0)	/* 32.768kHz OOK (read-only bit) */
-
-#if !defined(CONFIG_PXA27X)
-#define	 CCCR_L09      (0x1F)
-#define	 CCCR_L27      (0x1)
-#define	 CCCR_L32      (0x2)
-#define	 CCCR_L36      (0x3)
-#define	 CCCR_L40      (0x4)
-#define	 CCCR_L45      (0x5)
-
-#define	 CCCR_M1       (0x1 << 5)
-#define	 CCCR_M2       (0x2 << 5)
-#define	 CCCR_M4       (0x3 << 5)
-
-#define	 CCCR_N10      (0x2 << 7)
-#define	 CCCR_N15      (0x3 << 7)
-#define	 CCCR_N20      (0x4 << 7)
-#define	 CCCR_N25      (0x5 << 7)
-#define	 CCCR_N30      (0x6 << 7)
-#endif
-
-#endif /* CONFIG_CPU_MONAHANS */
-
-/******************************************************************************/
-/*
- * Pulse Width Modulator
- */
-#define PWM_CTRL0	0x40B00000  /* PWM 0 Control Register */
-#define PWM_PWDUTY0	0x40B00004  /* PWM 0 Duty Cycle Register */
-#define PWM_PERVAL0	0x40B00008  /* PWM 0 Period Control Register */
-
-#define PWM_CTRL1	0x40C00000  /* PWM 1 Control Register */
-#define PWM_PWDUTY1	0x40C00004  /* PWM 1 Duty Cycle Register */
-#define PWM_PERVAL1	0x40C00008  /* PWM 1 Period Control Register */
-
-#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
-#define PWM_CTRL2	0x40B00010  /* PWM 2 Control Register */
-#define PWM_PWDUTY2	0x40B00014  /* PWM 2 Duty Cycle Register */
-#define PWM_PERVAL2	0x40B00018  /* PWM 2 Period Control Register */
-
-#define PWM_CTRL3	0x40C00010  /* PWM 3 Control Register */
-#define PWM_PWDUTY3	0x40C00014  /* PWM 3 Duty Cycle Register */
-#define PWM_PERVAL3	0x40C00018  /* PWM 3 Period Control Register */
-#endif /* CONFIG_PXA27X || CONFIG_CPU_MONAHANS */
-
-/*
- * Interrupt Controller
- */
-#define ICIP		0x40D00000  /* Interrupt Controller IRQ Pending Register */
-#define ICMR		0x40D00004  /* Interrupt Controller Mask Register */
-#define ICLR		0x40D00008  /* Interrupt Controller Level Register */
-#define ICFP		0x40D0000C  /* Interrupt Controller FIQ Pending Register */
-#define ICPR		0x40D00010  /* Interrupt Controller Pending Register */
-#define ICCR		0x40D00014  /* Interrupt Controller Control Register */
-
-#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
-#define ICHP		0x40D00018  /* Interrupt Controller Highest Priority Register */
-#define ICIP2		0x40D0009C  /* Interrupt Controller IRQ Pending Register 2 */
-#define ICMR2		0x40D000A0  /* Interrupt Controller Mask Register 2 */
-#define ICLR2		0x40D000A4  /* Interrupt Controller Level Register 2 */
-#define ICFP2		0x40D000A8  /* Interrupt Controller FIQ Pending Register 2 */
-#define ICPR2		0x40D000AC  /* Interrupt Controller Pending Register 2 */
-#endif /* CONFIG_PXA27X || CONFIG_CPU_MONAHANS */
-
-/******************************************************************************/
-/*
- * General Purpose I/O
- */
-#define GPLR0		0x40E00000  /* GPIO Pin-Level Register GPIO<31:0> */
-#define GPLR1		0x40E00004  /* GPIO Pin-Level Register GPIO<63:32> */
-#define GPLR2		0x40E00008  /* GPIO Pin-Level Register GPIO<80:64> */
-
-#define GPDR0		0x40E0000C  /* GPIO Pin Direction Register GPIO<31:0> */
-#define GPDR1		0x40E00010  /* GPIO Pin Direction Register GPIO<63:32> */
-#define GPDR2		0x40E00014  /* GPIO Pin Direction Register GPIO<80:64> */
-
-#define GPSR0		0x40E00018  /* GPIO Pin Output Set Register GPIO<31:0> */
-#define GPSR1		0x40E0001C  /* GPIO Pin Output Set Register GPIO<63:32> */
-#define GPSR2		0x40E00020  /* GPIO Pin Output Set Register GPIO<80:64> */
-
-#define GPCR0		0x40E00024  /* GPIO Pin Output Clear Register GPIO<31:0> */
-#define GPCR1		0x40E00028  /* GPIO Pin Output Clear Register GPIO <63:32> */
-#define GPCR2		0x40E0002C  /* GPIO Pin Output Clear Register GPIO <80:64> */
-
-#define GRER0		0x40E00030  /* GPIO Rising-Edge Detect Register GPIO<31:0> */
-#define GRER1		0x40E00034  /* GPIO Rising-Edge Detect Register GPIO<63:32> */
-#define GRER2		0x40E00038  /* GPIO Rising-Edge Detect Register GPIO<80:64> */
-
-#define GFER0		0x40E0003C  /* GPIO Falling-Edge Detect Register GPIO<31:0> */
-#define GFER1		0x40E00040  /* GPIO Falling-Edge Detect Register GPIO<63:32> */
-#define GFER2		0x40E00044  /* GPIO Falling-Edge Detect Register GPIO<80:64> */
-
-#define GEDR0		0x40E00048  /* GPIO Edge Detect Status Register GPIO<31:0> */
-#define GEDR1		0x40E0004C  /* GPIO Edge Detect Status Register GPIO<63:32> */
-#define GEDR2		0x40E00050  /* GPIO Edge Detect Status Register GPIO<80:64> */
-
-#define GAFR0_L		0x40E00054  /* GPIO Alternate Function Select Register GPIO<15:0> */
-#define GAFR0_U		0x40E00058  /* GPIO Alternate Function Select Register GPIO<31:16> */
-#define GAFR1_L		0x40E0005C  /* GPIO Alternate Function Select Register GPIO<47:32> */
-#define GAFR1_U		0x40E00060  /* GPIO Alternate Function Select Register GPIO<63:48> */
-#define GAFR2_L		0x40E00064  /* GPIO Alternate Function Select Register GPIO<79:64> */
-#define GAFR2_U		0x40E00068  /* GPIO Alternate Function Select Register GPIO 80 */
-
-#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
-#define GPLR3		0x40E00100  /* GPIO Pin-Level Register GPIO<127:96> */
-#define GPDR3		0x40E0010C  /* GPIO Pin Direction Register GPIO<127:96> */
-#define GPSR3		0x40E00118  /* GPIO Pin Output Set Register GPIO<127:96> */
-#define GPCR3		0x40E00124  /* GPIO Pin Output Clear Register GPIO<127:96> */
-#define GRER3		0x40E00130  /* GPIO Rising-Edge Detect Register GPIO<127:96> */
-#define GFER3		0x40E0013C  /* GPIO Falling-Edge Detect Register GPIO<127:96> */
-#define GEDR3		0x40E00148  /* GPIO Edge Detect Status Register GPIO<127:96> */
-#define GAFR3_L		0x40E0006C  /* GPIO Alternate Function Select Register GPIO<111:96> */
-#define GAFR3_U		0x40E00070  /* GPIO Alternate Function Select Register GPIO<127:112> */
-#endif /* CONFIG_PXA27X || CONFIG_CPU_MONAHANS */
-
-#ifdef CONFIG_CPU_MONAHANS
-#define GSDR0		0x40E00400 /* Bit-wise Set of GPDR[31:0] */
-#define GSDR1		0x40E00404 /* Bit-wise Set of GPDR[63:32] */
-#define GSDR2		0x40E00408 /* Bit-wise Set of GPDR[95:64] */
-#define GSDR3		0x40E0040C /* Bit-wise Set of GPDR[127:96] */
-
-#define GCDR0		0x40E00420 /* Bit-wise Clear of GPDR[31:0] */
-#define GCDR1		0x40E00424 /* Bit-wise Clear of GPDR[63:32] */
-#define GCDR2		0x40E00428 /* Bit-wise Clear of GPDR[95:64] */
-#define GCDR3		0x40E0042C /* Bit-wise Clear of GPDR[127:96] */
-
-#define GSRER0		0x40E00440 /* Set Rising Edge Det. Enable [31:0] */
-#define GSRER1		0x40E00444 /* Set Rising Edge Det. Enable [63:32] */
-#define GSRER2		0x40E00448 /* Set Rising Edge Det. Enable [95:64] */
-#define GSRER3		0x40E0044C /* Set Rising Edge Det. Enable [127:96] */
-
-#define GCRER0		0x40E00460 /* Clear Rising Edge Det. Enable [31:0] */
-#define GCRER1		0x40E00464 /* Clear Rising Edge Det. Enable [63:32] */
-#define GCRER2		0x40E00468 /* Clear Rising Edge Det. Enable [95:64] */
-#define GCRER3		0x40E0046C /* Clear Rising Edge Det. Enable[127:96] */
-
-#define GSFER0		0x40E00480 /* Set Falling Edge Det. Enable [31:0] */
-#define GSFER1		0x40E00484 /* Set Falling Edge Det. Enable [63:32] */
-#define GSFER2		0x40E00488 /* Set Falling Edge Det. Enable [95:64] */
-#define GSFER3		0x40E0048C /* Set Falling Edge Det. Enable[127:96] */
-
-#define GCFER0		0x40E004A0 /* Clr Falling Edge Det. Enable [31:0] */
-#define GCFER1		0x40E004A4 /* Clr Falling Edge Det. Enable [63:32] */
-#define GCFER2		0x40E004A8 /* Clr Falling Edge Det. Enable [95:64] */
-#define GCFER3		0x40E004AC /* Clr Falling Edge Det. Enable[127:96] */
-
-#define GSDR(x)		(0x40E00400 | ((x) & 0x60) >> 3)
-#define GCDR(x)		(0x40E00420 | ((x) & 0x60) >> 3)
-#endif
-
-#define _GPLR(x)	(0x40E00000 + (((x) & 0x60) >> 3))
-#define _GPDR(x)	(0x40E0000C + (((x) & 0x60) >> 3))
-#define _GPSR(x)	(0x40E00018 + (((x) & 0x60) >> 3))
-#define _GPCR(x)	(0x40E00024 + (((x) & 0x60) >> 3))
-#define _GRER(x)	(0x40E00030 + (((x) & 0x60) >> 3))
-#define _GFER(x)	(0x40E0003C + (((x) & 0x60) >> 3))
-#define _GEDR(x)	(0x40E00048 + (((x) & 0x60) >> 3))
-#define _GAFR(x)	(0x40E00054 + (((x) & 0x70) >> 2))
-
-#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
-#define GPLR(x)		(((((x) & 0x7f) < 96) ? _GPLR(x) : GPLR3))
-#define GPDR(x)		(((((x) & 0x7f) < 96) ? _GPDR(x) : GPDR3))
-#define GPSR(x)		(((((x) & 0x7f) < 96) ? _GPSR(x) : GPSR3))
-#define GPCR(x)		(((((x) & 0x7f) < 96) ? _GPCR(x) : GPCR3))
-#define GRER(x)		(((((x) & 0x7f) < 96) ? _GRER(x) : GRER3))
-#define GFER(x)		(((((x) & 0x7f) < 96) ? _GFER(x) : GFER3))
-#define GEDR(x)		(((((x) & 0x7f) < 96) ? _GEDR(x) : GEDR3))
-#define GAFR(x)		(((((x) & 0x7f) < 96) ? _GAFR(x) : \
-			((((x) & 0x7f) < 112) ? GAFR3_L : GAFR3_U)))
-#else
-#define GPLR(x)		_GPLR(x)
-#define GPDR(x)		_GPDR(x)
-#define GPSR(x)		_GPSR(x)
-#define GPCR(x)		_GPCR(x)
-#define GRER(x)		_GRER(x)
-#define GFER(x)		_GFER(x)
-#define GEDR(x)		_GEDR(x)
-#define GAFR(x)		_GAFR(x)
-#endif
-
-#define GPIO_bit(x)	(1 << ((x) & 0x1f))
-
-/******************************************************************************/
-/*
- * Multi-function Pin Registers:
- */
-/* PXA320 */
-#if defined(CONFIG_CPU_PXA320)
-#define	DF_IO0		0x40e1024c
-#define	DF_IO1		0x40e10254
-#define	DF_IO2		0x40e1025c
-#define	DF_IO3		0x40e10264
-#define	DF_IO4		0x40e1026c
-#define	DF_IO5		0x40e10274
-#define	DF_IO6		0x40e1027c
-#define	DF_IO7		0x40e10284
-#define	DF_IO8		0x40e10250
-#define	DF_IO9		0x40e10258
-#define	DF_IO10		0x40e10260
-#define	DF_IO11		0x40e10268
-#define	DF_IO12		0x40e10270
-#define	DF_IO13		0x40e10278
-#define	DF_IO14		0x40e10280
-#define	DF_IO15		0x40e10288
-#define	DF_CLE_nOE	0x40e10204
-#define	DF_ALE_nWE1	0x40e10208
-#define	DF_ALE_nWE2	0x40e1021c
-#define	DF_SCLK_E	0x40e10210
-#define	DF_nCS0		0x40e10224
-#define	DF_nCS1		0x40e10228
-#define	nBE0		0x40e10214
-#define	nBE1		0x40e10218
-#define	nLUA		0x40e10234
-#define	nLLA		0x40e10238
-#define	DF_ADDR0	0x40e1023c
-#define	DF_ADDR1	0x40e10240
-#define	DF_ADDR2	0x40e10244
-#define	DF_ADDR3	0x40e10248
-#define	DF_INT_RnB	0x40e10220
-#define	DF_nCS0		0x40e10224
-#define	DF_nCS1		0x40e10228
-#define	DF_nWE		0x40e1022c
-#define	DF_nRE		0x40e10230
-
-#define	nXCVREN		0x40e10138
-
-#define	GPIO0		0x40e10124
-#define	GPIO1		0x40e10128
-#define	GPIO2		0x40e1012c
-#define	GPIO3		0x40e10130
-#define	GPIO4		0x40e10134
-#define	GPIO5		0x40e1028c
-#define	GPIO6		0x40e10290
-#define	GPIO7		0x40e10294
-#define	GPIO8		0x40e10298
-#define	GPIO9		0x40e1029c
-#define	GPIO10		0x40e10458
-#define	GPIO11		0x40e102a0
-#define	GPIO12		0x40e102a4
-#define	GPIO13		0x40e102a8
-#define	GPIO14		0x40e102ac
-#define	GPIO15		0x40e102b0
-#define	GPIO16		0x40e102b4
-#define	GPIO17		0x40e102b8
-#define	GPIO18		0x40e102bc
-#define	GPIO19		0x40e102c0
-#define	GPIO20		0x40e102c4
-#define	GPIO21		0x40e102c8
-#define	GPIO22		0x40e102cc
-#define	GPIO23		0x40e102d0
-#define	GPIO24		0x40e102d4
-#define	GPIO25		0x40e102d8
-#define	GPIO26		0x40e102dc
-
-#define	GPIO27		0x40e10400
-#define	GPIO28		0x40e10404
-#define	GPIO29		0x40e10408
-#define	GPIO30		0x40e1040c
-#define	GPIO31		0x40e10410
-#define	GPIO32		0x40e10414
-#define	GPIO33		0x40e10418
-#define	GPIO34		0x40e1041c
-#define	GPIO35		0x40e10420
-#define	GPIO36		0x40e10424
-#define	GPIO37		0x40e10428
-#define	GPIO38		0x40e1042c
-#define	GPIO39		0x40e10430
-#define	GPIO40		0x40e10434
-#define	GPIO41		0x40e10438
-#define	GPIO42		0x40e1043c
-#define	GPIO43		0x40e10440
-#define	GPIO44		0x40e10444
-#define	GPIO45		0x40e10448
-#define	GPIO46		0x40e1044c
-#define	GPIO47		0x40e10450
-#define	GPIO48		0x40e10454
-#define	GPIO49		0x40e1045c
-#define	GPIO50		0x40e10460
-#define	GPIO51		0x40e10464
-#define	GPIO52		0x40e10468
-#define	GPIO53		0x40e1046c
-#define	GPIO54		0x40e10470
-#define	GPIO55		0x40e10474
-#define	GPIO56		0x40e10478
-#define	GPIO57		0x40e1047c
-#define	GPIO58		0x40e10480
-#define	GPIO59		0x40e10484
-#define	GPIO60		0x40e10488
-#define	GPIO61		0x40e1048c
-#define	GPIO62		0x40e10490
-
-#define	GPIO6_2		0x40e10494
-#define	GPIO7_2		0x40e10498
-#define	GPIO8_2		0x40e1049c
-#define	GPIO9_2		0x40e104a0
-#define	GPIO10_2	0x40e104a4
-#define	GPIO11_2	0x40e104a8
-#define	GPIO12_2	0x40e104ac
-#define	GPIO13_2	0x40e104b0
-
-#define	GPIO63		0x40e104b4
-#define	GPIO64		0x40e104b8
-#define	GPIO65		0x40e104bc
-#define	GPIO66		0x40e104c0
-#define	GPIO67		0x40e104c4
-#define	GPIO68		0x40e104c8
-#define	GPIO69		0x40e104cc
-#define	GPIO70		0x40e104d0
-#define	GPIO71		0x40e104d4
-#define	GPIO72		0x40e104d8
-#define	GPIO73		0x40e104dc
-
-#define	GPIO14_2	0x40e104e0
-#define	GPIO15_2	0x40e104e4
-#define	GPIO16_2	0x40e104e8
-#define	GPIO17_2	0x40e104ec
-
-#define	GPIO74		0x40e104f0
-#define	GPIO75		0x40e104f4
-#define	GPIO76		0x40e104f8
-#define	GPIO77		0x40e104fc
-#define	GPIO78		0x40e10500
-#define	GPIO79		0x40e10504
-#define	GPIO80		0x40e10508
-#define	GPIO81		0x40e1050c
-#define	GPIO82		0x40e10510
-#define	GPIO83		0x40e10514
-#define	GPIO84		0x40e10518
-#define	GPIO85		0x40e1051c
-#define	GPIO86		0x40e10520
-#define	GPIO87		0x40e10524
-#define	GPIO88		0x40e10528
-#define	GPIO89		0x40e1052c
-#define	GPIO90		0x40e10530
-#define	GPIO91		0x40e10534
-#define	GPIO92		0x40e10538
-#define	GPIO93		0x40e1053c
-#define	GPIO94		0x40e10540
-#define	GPIO95		0x40e10544
-#define	GPIO96		0x40e10548
-#define	GPIO97		0x40e1054c
-#define	GPIO98		0x40e10550
-
-#define	GPIO99		0x40e10600
-#define	GPIO100		0x40e10604
-#define	GPIO101		0x40e10608
-#define	GPIO102		0x40e1060c
-#define	GPIO103		0x40e10610
-#define	GPIO104		0x40e10614
-#define	GPIO105		0x40e10618
-#define	GPIO106		0x40e1061c
-#define	GPIO107		0x40e10620
-#define	GPIO108		0x40e10624
-#define	GPIO109		0x40e10628
-#define	GPIO110		0x40e1062c
-#define	GPIO111		0x40e10630
-#define	GPIO112		0x40e10634
-
-#define	GPIO113		0x40e10638
-#define	GPIO114		0x40e1063c
-#define	GPIO115		0x40e10640
-#define	GPIO116		0x40e10644
-#define	GPIO117		0x40e10648
-#define	GPIO118		0x40e1064c
-#define	GPIO119		0x40e10650
-#define	GPIO120		0x40e10654
-#define	GPIO121		0x40e10658
-#define	GPIO122		0x40e1065c
-#define	GPIO123		0x40e10660
-#define	GPIO124		0x40e10664
-#define	GPIO125		0x40e10668
-#define	GPIO126		0x40e1066c
-#define	GPIO127		0x40e10670
-
-#define	GPIO0_2		0x40e10674
-#define	GPIO1_2		0x40e10678
-#define	GPIO2_2		0x40e1067c
-#define	GPIO3_2		0x40e10680
-#define	GPIO4_2		0x40e10684
-#define	GPIO5_2		0x40e10688
-
-/* PXA300 and PXA310 */
-#elif	defined(CONFIG_CPU_PXA300) || defined(CONFIG_CPU_PXA310)
-#define	DF_IO0		0x40e10220
-#define	DF_IO1		0x40e10228
-#define	DF_IO2		0x40e10230
-#define	DF_IO3		0x40e10238
-#define	DF_IO4		0x40e10258
-#define	DF_IO5		0x40e10260
-#define	DF_IO7		0x40e10270
-#define	DF_IO6		0x40e10268
-#define	DF_IO8		0x40e10224
-#define	DF_IO9		0x40e1022c
-#define	DF_IO10		0x40e10234
-#define	DF_IO11		0x40e1023c
-#define	DF_IO12		0x40e1025c
-#define	DF_IO13		0x40e10264
-#define	DF_IO14		0x40e1026c
-#define	DF_IO15		0x40e10274
-#define	DF_CLE_NOE	0x40e10240
-#define	DF_ALE_nWE	0x40e1020c
-#define	DF_SCLK_E	0x40e10250
-#define	nCS0		0x40e100c4
-#define	nCS1		0x40e100c0
-#define	nBE0		0x40e10204
-#define	nBE1		0x40e10208
-#define	nLUA		0x40e10244
-#define	nLLA		0x40e10254
-#define	DF_ADDR0	0x40e10210
-#define	DF_ADDR1	0x40e10214
-#define	DF_ADDR2	0x40e10218
-#define	DF_ADDR3	0x40e1021c
-#define	DF_INT_RnB	0x40e100c8
-#define	DF_nCS0		0x40e10248
-#define	DF_nCS1		0x40e10278
-#define	DF_nWE		0x40e100cc
-#define	DF_nRE		0x40e10200
-
-#define	GPIO0		0x40e100b4
-#define	GPIO1		0x40e100b8
-#define	GPIO2		0x40e100bc
-#define	GPIO3		0x40e1027c
-#define	GPIO4		0x40e10280
-
-#define	GPIO5		0x40e10284
-#define	GPIO6		0x40e10288
-#define	GPIO7		0x40e1028c
-#define	GPIO8		0x40e10290
-#define	GPIO9		0x40e10294
-#define	GPIO10		0x40e10298
-#define	GPIO11		0x40e1029c
-#define	GPIO12		0x40e102a0
-#define	GPIO13		0x40e102a4
-#define	GPIO14		0x40e102a8
-#define	GPIO15		0x40e102ac
-#define	GPIO16		0x40e102b0
-#define	GPIO17		0x40e102b4
-#define	GPIO18		0x40e102b8
-#define	GPIO19		0x40e102bc
-#define	GPIO20		0x40e102c0
-#define	GPIO21		0x40e102c4
-#define	GPIO22		0x40e102c8
-#define	GPIO23		0x40e102cc
-#define	GPIO24		0x40e102d0
-#define	GPIO25		0x40e102d4
-#define	GPIO26		0x40e102d8
-
-#define	GPIO27		0x40e10400
-#define	GPIO28		0x40e10404
-#define	GPIO29		0x40e10408
-#define	ULPI_STP	0x40e1040c
-#define	ULPI_NXT	0x40e10410
-#define	ULPI_DIR	0x40e10414
-#define	GPIO30		0x40e10418
-#define	GPIO31		0x40e1041c
-#define	GPIO32		0x40e10420
-#define	GPIO33		0x40e10424
-#define	GPIO34		0x40e10428
-#define	GPIO35		0x40e1042c
-#define	GPIO36		0x40e10430
-#define	GPIO37		0x40e10434
-#define	GPIO38		0x40e10438
-#define	GPIO39		0x40e1043c
-#define	GPIO40		0x40e10440
-#define	GPIO41		0x40e10444
-#define	GPIO42		0x40e10448
-#define	GPIO43		0x40e1044c
-#define	GPIO44		0x40e10450
-#define	GPIO45		0x40e10454
-#define	GPIO46		0x40e10458
-#define	GPIO47		0x40e1045c
-#define	GPIO48		0x40e10460
-
-#define	GPIO49		0x40e10464
-#define	GPIO50		0x40e10468
-#define	GPIO51		0x40e1046c
-#define	GPIO52		0x40e10470
-#define	GPIO53		0x40e10474
-#define	GPIO54		0x40e10478
-#define	GPIO55		0x40e1047c
-#define	GPIO56		0x40e10480
-#define	GPIO57		0x40e10484
-#define	GPIO58		0x40e10488
-#define	GPIO59		0x40e1048c
-#define	GPIO60		0x40e10490
-#define	GPIO61		0x40e10494
-#define	GPIO62		0x40e10498
-#define	GPIO63		0x40e1049c
-#define	GPIO64		0x40e104a0
-#define	GPIO65		0x40e104a4
-#define	GPIO66		0x40e104a8
-#define	GPIO67		0x40e104ac
-#define	GPIO68		0x40e104b0
-#define	GPIO69		0x40e104b4
-#define	GPIO70		0x40e104b8
-#define	GPIO71		0x40e104bc
-#define	GPIO72		0x40e104c0
-#define	GPIO73		0x40e104c4
-#define	GPIO74		0x40e104c8
-#define	GPIO75		0x40e104cc
-#define	GPIO76		0x40e104d0
-#define	GPIO77		0x40e104d4
-#define	GPIO78		0x40e104d8
-#define	GPIO79		0x40e104dc
-#define	GPIO80		0x40e104e0
-#define	GPIO81		0x40e104e4
-#define	GPIO82		0x40e104e8
-#define	GPIO83		0x40e104ec
-#define	GPIO84		0x40e104f0
-#define	GPIO85		0x40e104f4
-#define	GPIO86		0x40e104f8
-#define	GPIO87		0x40e104fc
-#define	GPIO88		0x40e10500
-#define	GPIO89		0x40e10504
-#define	GPIO90		0x40e10508
-#define	GPIO91		0x40e1050c
-#define	GPIO92		0x40e10510
-#define	GPIO93		0x40e10514
-#define	GPIO94		0x40e10518
-#define	GPIO95		0x40e1051c
-#define	GPIO96		0x40e10520
-#define	GPIO97		0x40e10524
-#define	GPIO98		0x40e10528
-
-#define	GPIO99		0x40e10600
-#define	GPIO100		0x40e10604
-#define	GPIO101		0x40e10608
-#define	GPIO102		0x40e1060c
-#define	GPIO103		0x40e10610
-#define	GPIO104		0x40e10614
-#define	GPIO105		0x40e10618
-#define	GPIO106		0x40e1061c
-#define	GPIO107		0x40e10620
-#define	GPIO108		0x40e10624
-#define	GPIO109		0x40e10628
-#define	GPIO110		0x40e1062c
-#define	GPIO111		0x40e10630
-#define	GPIO112		0x40e10634
-
-#define	GPIO113		0x40e10638
-#define	GPIO114		0x40e1063c
-#define	GPIO115		0x40e10640
-#define	GPIO116		0x40e10644
-#define	GPIO117		0x40e10648
-#define	GPIO118		0x40e1064c
-#define	GPIO119		0x40e10650
-#define	GPIO120		0x40e10654
-#define	GPIO121		0x40e10658
-#define	GPIO122		0x40e1065c
-#define	GPIO123		0x40e10660
-#define	GPIO124		0x40e10664
-#define	GPIO125		0x40e10668
-#define	GPIO126		0x40e1066c
-#define	GPIO127		0x40e10670
-
-#define	GPIO0_2		0x40e10674
-#define	GPIO1_2		0x40e10678
-#define	GPIO2_2		0x40e102dc
-#define	GPIO3_2		0x40e102e0
-#define	GPIO4_2		0x40e102e4
-#define	GPIO5_2		0x40e102e8
-#define	GPIO6_2		0x40e102ec
-
-#ifndef	CONFIG_CPU_PXA300	/* PXA310 only */
-#define	GPIO7_2		0x40e1052c
-#define	GPIO8_2		0x40e10530
-#define	GPIO9_2		0x40e10534
-#define	GPIO10_2	0x40e10538
-#endif
-#endif
-
-#ifdef CONFIG_CPU_MONAHANS
-/* MFPR Bit Definitions, see 4-10, Vol. 1 */
-#define PULL_SEL	0x8000
-#define PULLUP_EN	0x4000
-#define PULLDOWN_EN	0x2000
-
-#define DRIVE_FAST_1mA	0x0
-#define DRIVE_FAST_2mA	0x400
-#define DRIVE_FAST_3mA	0x800
-#define DRIVE_FAST_4mA	0xC00
-#define DRIVE_SLOW_6mA	0x1000
-#define DRIVE_FAST_6mA	0x1400
-#define DRIVE_SLOW_10mA	0x1800
-#define DRIVE_FAST_10mA	0x1C00
-
-#define SLEEP_SEL	0x200
-#define SLEEP_DATA	0x100
-#define SLEEP_OE_N	0x80
-#define EDGE_CLEAR	0x40
-#define EDGE_FALL_EN	0x20
-#define EDGE_RISE_EN	0x10
-
-#define AF_SEL_0	0x0	/* Alternate function 0 (reset state) */
-#define AF_SEL_1	0x1	/* Alternate function 1 */
-#define AF_SEL_2	0x2	/* Alternate function 2 */
-#define AF_SEL_3	0x3	/* Alternate function 3 */
-#define AF_SEL_4	0x4	/* Alternate function 4 */
-#define AF_SEL_5	0x5	/* Alternate function 5 */
-#define AF_SEL_6	0x6	/* Alternate function 6 */
-#define AF_SEL_7	0x7	/* Alternate function 7 */
-
-#endif /* CONFIG_CPU_MONAHANS */
-
-/* GPIO alternate function assignments */
-
-#define GPIO1_RST		1	/* reset */
-#define GPIO6_MMCCLK		6	/* MMC Clock */
-#define GPIO8_48MHz		7	/* 48 MHz clock output */
-#define GPIO8_MMCCS0		8	/* MMC Chip Select 0 */
-#define GPIO9_MMCCS1		9	/* MMC Chip Select 1 */
-#define GPIO10_RTCCLK		10	/* real time clock (1 Hz) */
-#define GPIO11_3_6MHz		11	/* 3.6 MHz oscillator out */
-#define GPIO12_32KHz		12	/* 32 kHz out */
-#define GPIO13_MBGNT		13	/* memory controller grant */
-#define GPIO14_MBREQ		14	/* alternate bus master request */
-#define GPIO15_nCS_1		15	/* chip select 1 */
-#define GPIO16_PWM0		16	/* PWM0 output */
-#define GPIO17_PWM1		17	/* PWM1 output */
-#define GPIO18_RDY		18	/* Ext. Bus Ready */
-#define GPIO19_DREQ1		19	/* External DMA Request */
-#define GPIO20_DREQ0		20	/* External DMA Request */
-#define GPIO23_SCLK		23	/* SSP clock */
-#define GPIO24_SFRM		24	/* SSP Frame */
-#define GPIO25_STXD		25	/* SSP transmit */
-#define GPIO26_SRXD		26	/* SSP receive */
-#define GPIO27_SEXTCLK		27	/* SSP ext_clk */
-#define GPIO28_BITCLK		28	/* AC97/I2S bit_clk */
-#define GPIO29_SDATA_IN		29	/* AC97 Sdata_in0 / I2S Sdata_in */
-#define GPIO30_SDATA_OUT	30	/* AC97/I2S Sdata_out */
-#define GPIO31_SYNC		31	/* AC97/I2S sync */
-#define GPIO32_SDATA_IN1	32	/* AC97 Sdata_in1 */
-#define GPIO33_nCS_5		33	/* chip select 5 */
-#define GPIO34_FFRXD		34	/* FFUART receive */
-#define GPIO34_MMCCS0		34	/* MMC Chip Select 0 */
-#define GPIO35_FFCTS		35	/* FFUART Clear to send */
-#define GPIO36_FFDCD		36	/* FFUART Data carrier detect */
-#define GPIO37_FFDSR		37	/* FFUART data set ready */
-#define GPIO38_FFRI		38	/* FFUART Ring Indicator */
-#define GPIO39_MMCCS1		39	/* MMC Chip Select 1 */
-#define GPIO39_FFTXD		39	/* FFUART transmit data */
-#define GPIO40_FFDTR		40	/* FFUART data terminal Ready */
-#define GPIO41_FFRTS		41	/* FFUART request to send */
-#define GPIO42_BTRXD		42	/* BTUART receive data */
-#define GPIO43_BTTXD		43	/* BTUART transmit data */
-#define GPIO44_BTCTS		44	/* BTUART clear to send */
-#define GPIO45_BTRTS		45	/* BTUART request to send */
-#define GPIO46_ICPRXD		46	/* ICP receive data */
-#define GPIO46_STRXD		46	/* STD_UART receive data */
-#define GPIO47_ICPTXD		47	/* ICP transmit data */
-#define GPIO47_STTXD		47	/* STD_UART transmit data */
-#define GPIO48_nPOE		48	/* Output Enable for Card Space */
-#define GPIO49_nPWE		49	/* Write Enable for Card Space */
-#define GPIO50_nPIOR		50	/* I/O Read for Card Space */
-#define GPIO51_nPIOW		51	/* I/O Write for Card Space */
-#define GPIO52_nPCE_1		52	/* Card Enable for Card Space */
-#define GPIO53_nPCE_2		53	/* Card Enable for Card Space */
-#define GPIO53_MMCCLK		53	/* MMC Clock */
-#define GPIO54_MMCCLK		54	/* MMC Clock */
-#define GPIO54_pSKTSEL		54	/* Socket Select for Card Space */
-#define GPIO55_nPREG		55	/* Card Address bit 26 */
-#define GPIO56_nPWAIT		56	/* Wait signal for Card Space */
-#define GPIO57_nIOIS16		57	/* Bus Width select for I/O Card Space */
-#define GPIO58_LDD_0		58	/* LCD data pin 0 */
-#define GPIO59_LDD_1		59	/* LCD data pin 1 */
-#define GPIO60_LDD_2		60	/* LCD data pin 2 */
-#define GPIO61_LDD_3		61	/* LCD data pin 3 */
-#define GPIO62_LDD_4		62	/* LCD data pin 4 */
-#define GPIO63_LDD_5		63	/* LCD data pin 5 */
-#define GPIO64_LDD_6		64	/* LCD data pin 6 */
-#define GPIO65_LDD_7		65	/* LCD data pin 7 */
-#define GPIO66_LDD_8		66	/* LCD data pin 8 */
-#define GPIO66_MBREQ		66	/* alternate bus master req */
-#define GPIO67_LDD_9		67	/* LCD data pin 9 */
-#define GPIO67_MMCCS0		67	/* MMC Chip Select 0 */
-#define GPIO68_LDD_10		68	/* LCD data pin 10 */
-#define GPIO68_MMCCS1		68	/* MMC Chip Select 1 */
-#define GPIO69_LDD_11		69	/* LCD data pin 11 */
-#define GPIO69_MMCCLK		69	/* MMC_CLK */
-#define GPIO70_LDD_12		70	/* LCD data pin 12 */
-#define GPIO70_RTCCLK		70	/* Real Time clock (1 Hz) */
-#define GPIO71_LDD_13		71	/* LCD data pin 13 */
-#define GPIO71_3_6MHz		71	/* 3.6 MHz Oscillator clock */
-#define GPIO72_LDD_14		72	/* LCD data pin 14 */
-#define GPIO72_32kHz		72	/* 32 kHz clock */
-#define GPIO73_LDD_15		73	/* LCD data pin 15 */
-#define GPIO73_MBGNT		73	/* Memory controller grant */
-#define GPIO74_LCD_FCLK		74	/* LCD Frame clock */
-#define GPIO75_LCD_LCLK		75	/* LCD line clock */
-#define GPIO76_LCD_PCLK		76	/* LCD Pixel clock */
-#define GPIO77_LCD_ACBIAS	77	/* LCD AC Bias */
-#define GPIO78_nCS_2		78	/* chip select 2 */
-#define GPIO79_nCS_3		79	/* chip select 3 */
-#define GPIO80_nCS_4		80	/* chip select 4 */
-
-/* GPIO alternate function mode & direction */
-
-#define GPIO_IN			0x000
-#define GPIO_OUT		0x080
-#define GPIO_ALT_FN_1_IN	0x100
-#define GPIO_ALT_FN_1_OUT	0x180
-#define GPIO_ALT_FN_2_IN	0x200
-#define GPIO_ALT_FN_2_OUT	0x280
-#define GPIO_ALT_FN_3_IN	0x300
-#define GPIO_ALT_FN_3_OUT	0x380
-#define GPIO_MD_MASK_NR		0x07f
-#define GPIO_MD_MASK_DIR	0x080
-#define GPIO_MD_MASK_FN		0x300
-
-#define GPIO1_RTS_MD		( 1 | GPIO_ALT_FN_1_IN)
-#define GPIO6_MMCCLK_MD		( 6 | GPIO_ALT_FN_1_OUT)
-#define GPIO8_48MHz_MD		( 8 | GPIO_ALT_FN_1_OUT)
-#define GPIO8_MMCCS0_MD		( 8 | GPIO_ALT_FN_1_OUT)
-#define GPIO9_MMCCS1_MD		( 9 | GPIO_ALT_FN_1_OUT)
-#define GPIO10_RTCCLK_MD	(10 | GPIO_ALT_FN_1_OUT)
-#define GPIO11_3_6MHz_MD	(11 | GPIO_ALT_FN_1_OUT)
-#define GPIO12_32KHz_MD		(12 | GPIO_ALT_FN_1_OUT)
-#define GPIO13_MBGNT_MD		(13 | GPIO_ALT_FN_2_OUT)
-#define GPIO14_MBREQ_MD		(14 | GPIO_ALT_FN_1_IN)
-#define GPIO15_nCS_1_MD		(15 | GPIO_ALT_FN_2_OUT)
-#define GPIO16_PWM0_MD		(16 | GPIO_ALT_FN_2_OUT)
-#define GPIO17_PWM1_MD		(17 | GPIO_ALT_FN_2_OUT)
-#define GPIO18_RDY_MD		(18 | GPIO_ALT_FN_1_IN)
-#define GPIO19_DREQ1_MD		(19 | GPIO_ALT_FN_1_IN)
-#define GPIO20_DREQ0_MD		(20 | GPIO_ALT_FN_1_IN)
-#define GPIO23_SCLK_md		(23 | GPIO_ALT_FN_2_OUT)
-#define GPIO24_SFRM_MD		(24 | GPIO_ALT_FN_2_OUT)
-#define GPIO25_STXD_MD		(25 | GPIO_ALT_FN_2_OUT)
-#define GPIO26_SRXD_MD		(26 | GPIO_ALT_FN_1_IN)
-#define GPIO27_SEXTCLK_MD	(27 | GPIO_ALT_FN_1_IN)
-#define GPIO28_BITCLK_AC97_MD	(28 | GPIO_ALT_FN_1_IN)
-#define GPIO28_BITCLK_I2S_MD	(28 | GPIO_ALT_FN_2_IN)
-#define GPIO29_SDATA_IN_AC97_MD (29 | GPIO_ALT_FN_1_IN)
-#define GPIO29_SDATA_IN_I2S_MD	(29 | GPIO_ALT_FN_2_IN)
-#define GPIO30_SDATA_OUT_AC97_MD	(30 | GPIO_ALT_FN_2_OUT)
-#define GPIO30_SDATA_OUT_I2S_MD (30 | GPIO_ALT_FN_1_OUT)
-#define GPIO31_SYNC_AC97_MD	(31 | GPIO_ALT_FN_2_OUT)
-#define GPIO31_SYNC_I2S_MD	(31 | GPIO_ALT_FN_1_OUT)
-#define GPIO32_SDATA_IN1_AC97_MD	(32 | GPIO_ALT_FN_1_IN)
-#define GPIO33_nCS_5_MD		(33 | GPIO_ALT_FN_2_OUT)
-#define GPIO34_FFRXD_MD		(34 | GPIO_ALT_FN_1_IN)
-#define GPIO34_MMCCS0_MD	(34 | GPIO_ALT_FN_2_OUT)
-#define GPIO35_FFCTS_MD		(35 | GPIO_ALT_FN_1_IN)
-#define GPIO36_FFDCD_MD		(36 | GPIO_ALT_FN_1_IN)
-#define GPIO37_FFDSR_MD		(37 | GPIO_ALT_FN_1_IN)
-#define GPIO38_FFRI_MD		(38 | GPIO_ALT_FN_1_IN)
-#define GPIO39_MMCCS1_MD	(39 | GPIO_ALT_FN_1_OUT)
-#define GPIO39_FFTXD_MD		(39 | GPIO_ALT_FN_2_OUT)
-#define GPIO40_FFDTR_MD		(40 | GPIO_ALT_FN_2_OUT)
-#define GPIO41_FFRTS_MD		(41 | GPIO_ALT_FN_2_OUT)
-#define GPIO42_BTRXD_MD		(42 | GPIO_ALT_FN_1_IN)
-#define GPIO43_BTTXD_MD		(43 | GPIO_ALT_FN_2_OUT)
-#define GPIO44_BTCTS_MD		(44 | GPIO_ALT_FN_1_IN)
-#define GPIO45_BTRTS_MD		(45 | GPIO_ALT_FN_2_OUT)
-#define GPIO46_ICPRXD_MD	(46 | GPIO_ALT_FN_1_IN)
-#define GPIO46_STRXD_MD		(46 | GPIO_ALT_FN_2_IN)
-#define GPIO47_ICPTXD_MD	(47 | GPIO_ALT_FN_2_OUT)
-#define GPIO47_STTXD_MD		(47 | GPIO_ALT_FN_1_OUT)
-#define GPIO48_nPOE_MD		(48 | GPIO_ALT_FN_2_OUT)
-#define GPIO49_nPWE_MD		(49 | GPIO_ALT_FN_2_OUT)
-#define GPIO50_nPIOR_MD		(50 | GPIO_ALT_FN_2_OUT)
-#define GPIO51_nPIOW_MD		(51 | GPIO_ALT_FN_2_OUT)
-#define GPIO52_nPCE_1_MD	(52 | GPIO_ALT_FN_2_OUT)
-#define GPIO53_nPCE_2_MD	(53 | GPIO_ALT_FN_2_OUT)
-#define GPIO53_MMCCLK_MD	(53 | GPIO_ALT_FN_1_OUT)
-#define GPIO54_MMCCLK_MD	(54 | GPIO_ALT_FN_1_OUT)
-#define GPIO54_pSKTSEL_MD	(54 | GPIO_ALT_FN_2_OUT)
-#define GPIO55_nPREG_MD		(55 | GPIO_ALT_FN_2_OUT)
-#define GPIO56_nPWAIT_MD	(56 | GPIO_ALT_FN_1_IN)
-#define GPIO57_nIOIS16_MD	(57 | GPIO_ALT_FN_1_IN)
-#define GPIO58_LDD_0_MD		(58 | GPIO_ALT_FN_2_OUT)
-#define GPIO59_LDD_1_MD		(59 | GPIO_ALT_FN_2_OUT)
-#define GPIO60_LDD_2_MD		(60 | GPIO_ALT_FN_2_OUT)
-#define GPIO61_LDD_3_MD		(61 | GPIO_ALT_FN_2_OUT)
-#define GPIO62_LDD_4_MD		(62 | GPIO_ALT_FN_2_OUT)
-#define GPIO63_LDD_5_MD		(63 | GPIO_ALT_FN_2_OUT)
-#define GPIO64_LDD_6_MD		(64 | GPIO_ALT_FN_2_OUT)
-#define GPIO65_LDD_7_MD		(65 | GPIO_ALT_FN_2_OUT)
-#define GPIO66_LDD_8_MD		(66 | GPIO_ALT_FN_2_OUT)
-#define GPIO66_MBREQ_MD		(66 | GPIO_ALT_FN_1_IN)
-#define GPIO67_LDD_9_MD		(67 | GPIO_ALT_FN_2_OUT)
-#define GPIO67_MMCCS0_MD	(67 | GPIO_ALT_FN_1_OUT)
-#define GPIO68_LDD_10_MD	(68 | GPIO_ALT_FN_2_OUT)
-#define GPIO68_MMCCS1_MD	(68 | GPIO_ALT_FN_1_OUT)
-#define GPIO69_LDD_11_MD	(69 | GPIO_ALT_FN_2_OUT)
-#define GPIO69_MMCCLK_MD	(69 | GPIO_ALT_FN_1_OUT)
-#define GPIO70_LDD_12_MD	(70 | GPIO_ALT_FN_2_OUT)
-#define GPIO70_RTCCLK_MD	(70 | GPIO_ALT_FN_1_OUT)
-#define GPIO71_LDD_13_MD	(71 | GPIO_ALT_FN_2_OUT)
-#define GPIO71_3_6MHz_MD	(71 | GPIO_ALT_FN_1_OUT)
-#define GPIO72_LDD_14_MD	(72 | GPIO_ALT_FN_2_OUT)
-#define GPIO72_32kHz_MD		(72 | GPIO_ALT_FN_1_OUT)
-#define GPIO73_LDD_15_MD	(73 | GPIO_ALT_FN_2_OUT)
-#define GPIO73_MBGNT_MD		(73 | GPIO_ALT_FN_1_OUT)
-#define GPIO74_LCD_FCLK_MD	(74 | GPIO_ALT_FN_2_OUT)
-#define GPIO75_LCD_LCLK_MD	(75 | GPIO_ALT_FN_2_OUT)
-#define GPIO76_LCD_PCLK_MD	(76 | GPIO_ALT_FN_2_OUT)
-#define GPIO77_LCD_ACBIAS_MD	(77 | GPIO_ALT_FN_2_OUT)
-#define GPIO78_nCS_2_MD		(78 | GPIO_ALT_FN_2_OUT)
-#define GPIO79_nCS_3_MD		(79 | GPIO_ALT_FN_2_OUT)
-#define GPIO80_nCS_4_MD		(80 | GPIO_ALT_FN_2_OUT)
-
-#define GPIO117_SCL		(117 | GPIO_ALT_FN_1_OUT)
-#define GPIO118_SDA		(118 | GPIO_ALT_FN_1_OUT)
-
-/*
- * Power Manager
- */
-#ifdef CONFIG_CPU_MONAHANS
-
-#define ASCR		0x40F40000  /* Application Subsystem Power Status/Control Register */
-#define ARSR		0x40F40004  /* Application Subsystem Reset Status Register */
-#define AD3ER		0x40F40008  /* Application Subsystem D3 state Wakeup Enable Register */
-#define AD3SR		0x40F4000C  /* Application Subsystem D3 state Wakeup Status Register */
-#define AD2D0ER		0x40F40010  /* Application Subsystem D2 to D0 state Wakeup Enable Register */
-#define AD2D0SR		0x40F40014  /* Application Subsystem D2 to D0 state Wakeup Status Register */
-#define AD2D1ER		0x40F40018  /* Application Subsystem D2 to D1 state Wakeup Enable Register */
-#define AD2D1SR		0x40F4001C  /* Application Subsystem D2 to D1 state Wakeup Status Register */
-#define AD1D0ER		0x40F40020  /* Application Subsystem D1 to D0 state Wakeup Enable Register */
-#define AD1D0SR		0x40F40024  /* Application Subsystem D1 to D0 state Wakeup Status Register */
-#define ASDCNT		0x40F40028  /* Application Subsystem SRAM Drowsy Count Register */
-#define AD3R		0x40F40030  /* Application Subsystem D3 State Configuration Register */
-#define AD2R		0x40F40034  /* Application Subsystem D2 State Configuration Register */
-#define AD1R		0x40F40038  /* Application Subsystem D1 State Configuration Register */
-
-#define PMCR		0x40F50000  /* Power Manager Control Register */
-#define PSR		0x40F50004  /* Power Manager S2 Status Register */
-#define PSPR		0x40F50008  /* Power Manager Scratch Pad Register */
-#define PCFR		0x40F5000C  /* Power Manager General Configuration Register */
-#define PWER		0x40F50010  /* Power Manager Wake-up Enable Register */
-#define PWSR		0x40F50014  /* Power Manager Wake-up Status Register */
-#define PECR		0x40F50018  /* Power Manager EXT_WAKEUP[1:0] Control Register */
-#define DCDCSR		0x40F50080  /* DC-DC Controller Status Register */
-#define PVCR		0x40F50100  /* Power Manager Voltage Change Control Register */
-#define    PCMD(x) (0x40F50110 + x*4)
-#define    PCMD0   (0x40F50110 + 0 * 4)
-#define    PCMD1   (0x40F50110 + 1 * 4)
-#define    PCMD2   (0x40F50110 + 2 * 4)
-#define    PCMD3   (0x40F50110 + 3 * 4)
-#define    PCMD4   (0x40F50110 + 4 * 4)
-#define    PCMD5   (0x40F50110 + 5 * 4)
-#define    PCMD6   (0x40F50110 + 6 * 4)
-#define    PCMD7   (0x40F50110 + 7 * 4)
-#define    PCMD8   (0x40F50110 + 8 * 4)
-#define    PCMD9   (0x40F50110 + 9 * 4)
-#define    PCMD10  (0x40F50110 + 10 * 4)
-#define    PCMD11  (0x40F50110 + 11 * 4)
-#define    PCMD12  (0x40F50110 + 12 * 4)
-#define    PCMD13  (0x40F50110 + 13 * 4)
-#define    PCMD14  (0x40F50110 + 14 * 4)
-#define    PCMD15  (0x40F50110 + 15 * 4)
-#define    PCMD16  (0x40F50110 + 16 * 4)
-#define    PCMD17  (0x40F50110 + 17 * 4)
-#define    PCMD18  (0x40F50110 + 18 * 4)
-#define    PCMD19  (0x40F50110 + 19 * 4)
-#define    PCMD20  (0x40F50110 + 20 * 4)
-#define    PCMD21  (0x40F50110 + 21 * 4)
-#define    PCMD22  (0x40F50110 + 22 * 4)
-#define    PCMD23  (0x40F50110 + 23 * 4)
-#define    PCMD24  (0x40F50110 + 24 * 4)
-#define    PCMD25  (0x40F50110 + 25 * 4)
-#define    PCMD26  (0x40F50110 + 26 * 4)
-#define    PCMD27  (0x40F50110 + 27 * 4)
-#define    PCMD28  (0x40F50110 + 28 * 4)
-#define    PCMD29  (0x40F50110 + 29 * 4)
-#define    PCMD30  (0x40F50110 + 30 * 4)
-#define    PCMD31  (0x40F50110 + 31 * 4)
-
-#define    PCMD_MBC    (1<<12)
-#define    PCMD_DCE    (1<<11)
-#define    PCMD_LC     (1<<10)
-#define    PCMD_SQC    (3<<8)  /* only 00 and 01 are valid */
-
-#define PVCR_FVC                   (0x1 << 28)
-#define PVCR_VCSA                  (0x1<<14)
-#define PVCR_CommandDelay          (0xf80)
-#define PVCR_ReadPointer           0x01f00000
-#define PVCR_SlaveAddress          (0x7f)
-
-#else /* ifdef CONFIG_CPU_MONAHANS */
-
-#define PMCR		0x40F00000  /* Power Manager Control Register */
-#define PSSR		0x40F00004  /* Power Manager Sleep Status Register */
-#define PSPR		0x40F00008  /* Power Manager Scratch Pad Register */
-#define PWER		0x40F0000C  /* Power Manager Wake-up Enable Register */
-#define PRER		0x40F00010  /* Power Manager GPIO Rising-Edge Detect Enable Register */
-#define PFER		0x40F00014  /* Power Manager GPIO Falling-Edge Detect Enable Register */
-#define PEDR		0x40F00018  /* Power Manager GPIO Edge Detect Status Register */
-#define PCFR		0x40F0001C  /* Power Manager General Configuration Register */
-#define PGSR0		0x40F00020  /* Power Manager GPIO Sleep State Register for GP[31-0] */
-#define PGSR1		0x40F00024  /* Power Manager GPIO Sleep State Register for GP[63-32] */
-#define PGSR2		0x40F00028  /* Power Manager GPIO Sleep State Register for GP[84-64] */
-#define PGSR3		0x40F0002C  /* Power Manager GPIO Sleep State Register for GP[118-96] */
-#define RCSR		0x40F00030  /* Reset Controller Status Register */
-
-#define	   PSLR	   0x40F00034	/* Power Manager Sleep Config Register */
-#define	   PSTR	   0x40F00038	/* Power Manager Standby Config Register */
-#define	   PSNR	   0x40F0003C	/* Power Manager Sense Config Register */
-#define	   PVCR	   0x40F00040	/* Power Manager VoltageControl Register */
-#define	   PKWR	   0x40F00050	/* Power Manager KB Wake-up Enable Reg */
-#define	   PKSR	   0x40F00054	/* Power Manager KB Level-Detect Register */
-#define	   PCMD(x) (0x40F00080 + x*4)
-#define	   PCMD0   (0x40F00080 + 0 * 4)
-#define	   PCMD1   (0x40F00080 + 1 * 4)
-#define	   PCMD2   (0x40F00080 + 2 * 4)
-#define	   PCMD3   (0x40F00080 + 3 * 4)
-#define	   PCMD4   (0x40F00080 + 4 * 4)
-#define	   PCMD5   (0x40F00080 + 5 * 4)
-#define	   PCMD6   (0x40F00080 + 6 * 4)
-#define	   PCMD7   (0x40F00080 + 7 * 4)
-#define	   PCMD8   (0x40F00080 + 8 * 4)
-#define	   PCMD9   (0x40F00080 + 9 * 4)
-#define	   PCMD10  (0x40F00080 + 10 * 4)
-#define	   PCMD11  (0x40F00080 + 11 * 4)
-#define	   PCMD12  (0x40F00080 + 12 * 4)
-#define	   PCMD13  (0x40F00080 + 13 * 4)
-#define	   PCMD14  (0x40F00080 + 14 * 4)
-#define	   PCMD15  (0x40F00080 + 15 * 4)
-#define	   PCMD16  (0x40F00080 + 16 * 4)
-#define	   PCMD17  (0x40F00080 + 17 * 4)
-#define	   PCMD18  (0x40F00080 + 18 * 4)
-#define	   PCMD19  (0x40F00080 + 19 * 4)
-#define	   PCMD20  (0x40F00080 + 20 * 4)
-#define	   PCMD21  (0x40F00080 + 21 * 4)
-#define	   PCMD22  (0x40F00080 + 22 * 4)
-#define	   PCMD23  (0x40F00080 + 23 * 4)
-#define	   PCMD24  (0x40F00080 + 24 * 4)
-#define	   PCMD25  (0x40F00080 + 25 * 4)
-#define	   PCMD26  (0x40F00080 + 26 * 4)
-#define	   PCMD27  (0x40F00080 + 27 * 4)
-#define	   PCMD28  (0x40F00080 + 28 * 4)
-#define	   PCMD29  (0x40F00080 + 29 * 4)
-#define	   PCMD30  (0x40F00080 + 30 * 4)
-#define	   PCMD31  (0x40F00080 + 31 * 4)
-
-#define	   PCMD_MBC    (1<<12)
-#define	   PCMD_DCE    (1<<11)
-#define	   PCMD_LC     (1<<10)
-/* FIXME:  PCMD_SQC need be checked.   */
-#define	   PCMD_SQC    (3<<8)  /* currently only bit 8 is changerable, */
-				/* bit 9 should be 0 all day. */
-#define PVCR_VCSA		   (0x1<<14)
-#define PVCR_CommandDelay	   (0xf80)
-/* define MACRO for Power Manager General Configuration Register (PCFR) */
-#define PCFR_FVC		   (0x1 << 10)
-#define PCFR_PI2C_EN		   (0x1 << 6)
-
-#define PSSR_OTGPH	(1 << 6)	/* OTG Peripheral control Hold */
-#define PSSR_RDH	(1 << 5)	/* Read Disable Hold */
-#define PSSR_PH		(1 << 4)	/* Peripheral Control Hold */
-#define PSSR_VFS	(1 << 2)	/* VDD Fault Status */
-#define PSSR_BFS	(1 << 1)	/* Battery Fault Status */
-#define PSSR_SSS	(1 << 0)	/* Software Sleep Status */
-
-#define PCFR_DS		(1 << 3)	/* Deep Sleep Mode */
-#define PCFR_FS		(1 << 2)	/* Float Static Chip Selects */
-#define PCFR_FP		(1 << 1)	/* Float PCMCIA controls */
-#define PCFR_OPDE	(1 << 0)	/* 3.6864 MHz oscillator power-down enable */
-
-#define RCSR_GPR	(1 << 3)	/* GPIO Reset */
-#define RCSR_SMR	(1 << 2)	/* Sleep Mode */
-#define RCSR_WDR	(1 << 1)	/* Watchdog Reset */
-#define RCSR_HWR	(1 << 0)	/* Hardware Reset */
-
-#endif /* CONFIG_CPU_MONAHANS */
-
-/*
- * SSP Serial Port Registers
- */
-#define SSCR0		0x41000000  /* SSP Control Register 0 */
-#define SSCR1		0x41000004  /* SSP Control Register 1 */
-#define SSSR		0x41000008  /* SSP Status Register */
-#define SSITR		0x4100000C  /* SSP Interrupt Test Register */
-#define SSDR		0x41000010  /* (Write / Read) SSP Data Write Register/SSP Data Read Register */
-
-/*
- * MultiMediaCard (MMC) controller
- */
-#define MMC_STRPCL	0x41100000  /* Control to start and stop MMC clock */
-#define MMC_STAT	0x41100004  /* MMC Status Register (read only) */
-#define MMC_CLKRT	0x41100008  /* MMC clock rate */
-#define MMC_SPI		0x4110000c  /* SPI mode control bits */
-#define MMC_CMDAT	0x41100010  /* Command/response/data sequence control */
-#define MMC_RESTO	0x41100014  /* Expected response time out */
-#define MMC_RDTO	0x41100018  /* Expected data read time out */
-#define MMC_BLKLEN	0x4110001c  /* Block length of data transaction */
-#define MMC_NOB		0x41100020  /* Number of blocks, for block mode */
-#define MMC_PRTBUF	0x41100024  /* Partial MMC_TXFIFO FIFO written */
-#define MMC_I_MASK	0x41100028  /* Interrupt Mask */
-#define MMC_I_REG	0x4110002c  /* Interrupt Register (read only) */
-#define MMC_CMD		0x41100030  /* Index of current command */
-#define MMC_ARGH	0x41100034  /* MSW part of the current command argument */
-#define MMC_ARGL	0x41100038  /* LSW part of the current command argument */
-#define MMC_RES		0x4110003c  /* Response FIFO (read only) */
-#define MMC_RXFIFO	0x41100040  /* Receive FIFO (read only) */
-#define MMC_TXFIFO	0x41100044  /* Transmit FIFO (write only) */
-
-
-/*
- * LCD
- */
-#define LCCR0		0x44000000  /* LCD Controller Control Register 0 */
-#define LCCR1		0x44000004  /* LCD Controller Control Register 1 */
-#define LCCR2		0x44000008  /* LCD Controller Control Register 2 */
-#define LCCR3		0x4400000C  /* LCD Controller Control Register 3 */
-#define DFBR0		0x44000020  /* DMA Channel 0 Frame Branch Register */
-#define DFBR1		0x44000024  /* DMA Channel 1 Frame Branch Register */
-#define LCSR0		0x44000038  /* LCD Controller Status Register */
-#define LCSR1		0x44000034  /* LCD Controller Status Register */
-#define LIIDR		0x4400003C  /* LCD Controller Interrupt ID Register */
-#define TMEDRGBR	0x44000040  /* TMED RGB Seed Register */
-#define TMEDCR		0x44000044  /* TMED Control Register */
-
-#define FDADR0		0x44000200  /* DMA Channel 0 Frame Descriptor Address Register */
-#define FSADR0		0x44000204  /* DMA Channel 0 Frame Source Address Register */
-#define FIDR0		0x44000208  /* DMA Channel 0 Frame ID Register */
-#define LDCMD0		0x4400020C  /* DMA Channel 0 Command Register */
-#define FDADR1		0x44000210  /* DMA Channel 1 Frame Descriptor Address Register */
-#define FSADR1		0x44000214  /* DMA Channel 1 Frame Source Address Register */
-#define FIDR1		0x44000218  /* DMA Channel 1 Frame ID Register */
-#define LDCMD1		0x4400021C  /* DMA Channel 1 Command Register */
-
-#define LCCR0_ENB	(1 << 0)	/* LCD Controller enable */
-#define LCCR0_CMS	(1 << 1)	/* Color = 0, Monochrome = 1 */
-#define LCCR0_SDS	(1 << 2)	/* Single Panel = 0, Dual Panel = 1 */
-#define LCCR0_LDM	(1 << 3)	/* LCD Disable Done Mask */
-#define LCCR0_SFM	(1 << 4)	/* Start of frame mask */
-#define LCCR0_IUM	(1 << 5)	/* Input FIFO underrun mask */
-#define LCCR0_EFM	(1 << 6)	/* End of Frame mask */
-#define LCCR0_PAS	(1 << 7)	/* Passive = 0, Active = 1 */
-#define LCCR0_BLE	(1 << 8)	/* Little Endian = 0, Big Endian = 1 */
-#define LCCR0_DPD	(1 << 9)	/* Double Pixel mode, 4 pixel value = 0, 8 pixle values = 1 */
-#define LCCR0_DIS	(1 << 10)	/* LCD Disable */
-#define LCCR0_QDM	(1 << 11)	/* LCD Quick Disable mask */
-#define LCCR0_PDD	(0xff << 12)	/* Palette DMA request delay */
-#define LCCR0_PDD_S	12
-#define LCCR0_BM	(1 << 20)	/* Branch mask */
-#define LCCR0_OUM	(1 << 21)	/* Output FIFO underrun mask */
-#if defined(CONFIG_PXA27X)
-#define LCCR0_LCDT	(1 << 22)	/* LCD Panel Type */
-#define LCCR0_RDSTM	(1 << 23)	/* Read Status Interrupt Mask */
-#define LCCR0_CMDIM	(1 << 24)	/* Command Interrupt Mask */
-#endif
-
-#define LCCR1_PPL	Fld (10, 0)	 /* Pixels Per Line - 1 */
-#define LCCR1_DisWdth(Pixel)		/* Display Width [1..800 pix.]	*/ \
-			(((Pixel) - 1) << FShft (LCCR1_PPL))
-
-#define LCCR1_HSW	Fld (6, 10)	/* Horizontal Synchronization	  */
-#define LCCR1_HorSnchWdth(Tpix)		/* Horizontal Synchronization	  */ \
-					/* pulse Width [1..64 Tpix]	  */ \
-			(((Tpix) - 1) << FShft (LCCR1_HSW))
-
-#define LCCR1_ELW	Fld (8, 16)	/* End-of-Line pixel clock Wait	   */
-					/* count - 1 [Tpix]		   */
-#define LCCR1_EndLnDel(Tpix)		/*  End-of-Line Delay		   */ \
-					/*  [1..256 Tpix]		   */ \
-			(((Tpix) - 1) << FShft (LCCR1_ELW))
-
-#define LCCR1_BLW	Fld (8, 24)	/* Beginning-of-Line pixel clock   */
-					/* Wait count - 1 [Tpix]	   */
-#define LCCR1_BegLnDel(Tpix)		/*  Beginning-of-Line Delay	   */ \
-					/*  [1..256 Tpix]		   */ \
-			(((Tpix) - 1) << FShft (LCCR1_BLW))
-
-
-#define LCCR2_LPP	Fld (10, 0)	/* Line Per Panel - 1		   */
-#define LCCR2_DisHght(Line)		/*  Display Height [1..1024 lines] */ \
-			(((Line) - 1) << FShft (LCCR2_LPP))
-
-#define LCCR2_VSW	Fld (6, 10)	/* Vertical Synchronization pulse  */
-					/* Width - 1 [Tln] (L_FCLK)	   */
-#define LCCR2_VrtSnchWdth(Tln)		/*  Vertical Synchronization pulse */ \
-					/*  Width [1..64 Tln]		   */ \
-			(((Tln) - 1) << FShft (LCCR2_VSW))
-
-#define LCCR2_EFW	Fld (8, 16)	/* End-of-Frame line clock Wait	   */
-					/* count [Tln]			   */
-#define LCCR2_EndFrmDel(Tln)		/*  End-of-Frame Delay		   */ \
-					/*  [0..255 Tln]		   */ \
-			((Tln) << FShft (LCCR2_EFW))
-
-#define LCCR2_BFW	Fld (8, 24)	/* Beginning-of-Frame line clock   */
-					/* Wait count [Tln]		   */
-#define LCCR2_BegFrmDel(Tln)		/*  Beginning-of-Frame Delay	   */ \
-					/*  [0..255 Tln]		   */ \
-			((Tln) << FShft (LCCR2_BFW))
-
-#define LCCR3_API	(0xf << 16)	/* AC Bias pin trasitions per interrupt */
-#define LCCR3_API_S	16
-#define LCCR3_VSP	(1 << 20)	/* vertical sync polarity */
-#define LCCR3_HSP	(1 << 21)	/* horizontal sync polarity */
-#define LCCR3_PCP	(1 << 22)	/* pixel clock polarity */
-#define LCCR3_OEP	(1 << 23)	/* output enable polarity */
-#define LCCR3_DPC	(1 << 27)	/* double pixel clock mode */
-
-#define LCCR3_PDFOR_0	 (0 << 30)
-#define LCCR3_PDFOR_1	 (1 << 30)
-#define LCCR3_PDFOR_2	 (2 << 30)
-#define LCCR3_PDFOR_3	 (3 << 30)
-
-
-#define LCCR3_PCD	Fld (8, 0)	/* Pixel Clock Divisor */
-#define LCCR3_PixClkDiv(Div)		/* Pixel Clock Divisor */ \
-			(((Div) << FShft (LCCR3_PCD)))
-
-
-#define LCCR3_BPP	Fld (3, 24)	/* Bit Per Pixel */
-#define LCCR3_Bpp(Bpp)			/* Bit Per Pixel */ \
-			((((Bpp&0x7) << FShft (LCCR3_BPP)))|(((Bpp&0x8)<<26)))
-
-#define LCCR3_ACB	Fld (8, 8)	/* AC Bias */
-#define LCCR3_Acb(Acb)			/* BAC Bias */ \
-			(((Acb) << FShft (LCCR3_ACB)))
-
-#define LCCR3_HorSnchH	(LCCR3_HSP*0)	/*  Horizontal Synchronization	   */
-					/*  pulse active High		   */
-#define LCCR3_HorSnchL	(LCCR3_HSP*1)	/*  Horizontal Synchronization	   */
-
-#define LCCR3_VrtSnchH	(LCCR3_VSP*0)	/*  Vertical Synchronization pulse */
-					/*  active High			   */
-#define LCCR3_VrtSnchL	(LCCR3_VSP*1)	/*  Vertical Synchronization pulse */
-					/*  active Low			   */
-
-#define LCSR0_LDD	(1 << 0)	/* LCD Disable Done */
-#define LCSR0_SOF	(1 << 1)	/* Start of frame */
-#define LCSR0_BER	(1 << 2)	/* Bus error */
-#define LCSR0_ABC	(1 << 3)	/* AC Bias count */
-#define LCSR0_IUL	(1 << 4)	/* input FIFO underrun Lower panel */
-#define LCSR0_IUU	(1 << 5)	/* input FIFO underrun Upper panel */
-#define LCSR0_OU	(1 << 6)	/* output FIFO underrun */
-#define LCSR0_QD	(1 << 7)	/* quick disable */
-#define LCSR0_EOF0	(1 << 8)	/* end of frame */
-#define LCSR0_BS	(1 << 9)	/* branch status */
-#define LCSR0_SINT	(1 << 10)	/* subsequent interrupt */
-
-#define LCSR1_SOF1	(1 << 0)
-#define LCSR1_SOF2	(1 << 1)
-#define LCSR1_SOF3	(1 << 2)
-#define LCSR1_SOF4	(1 << 3)
-#define LCSR1_SOF5	(1 << 4)
-#define LCSR1_SOF6	(1 << 5)
-
-#define LCSR1_EOF1	(1 << 8)
-#define LCSR1_EOF2	(1 << 9)
-#define LCSR1_EOF3	(1 << 10)
-#define LCSR1_EOF4	(1 << 11)
-#define LCSR1_EOF5	(1 << 12)
-#define LCSR1_EOF6	(1 << 13)
-
-#define LCSR1_BS1	(1 << 16)
-#define LCSR1_BS2	(1 << 17)
-#define LCSR1_BS3	(1 << 18)
-#define LCSR1_BS4	(1 << 19)
-#define LCSR1_BS5	(1 << 20)
-#define LCSR1_BS6	(1 << 21)
-
-#define LCSR1_IU2	(1 << 25)
-#define LCSR1_IU3	(1 << 26)
-#define LCSR1_IU4	(1 << 27)
-#define LCSR1_IU5	(1 << 28)
-#define LCSR1_IU6	(1 << 29)
-
-#define LDCMD_PAL	(1 << 26)	/* instructs DMA to load palette buffer */
-#if defined(CONFIG_PXA27X)
-#define LDCMD_SOFINT	(1 << 22)
-#define LDCMD_EOFINT	(1 << 21)
-#endif
-
-/*
- * Memory controller
- */
-
-#ifdef CONFIG_CPU_MONAHANS
-
-/* PXA3xx */
-
-/* Static Memory Controller Registers */
-#define	MSC0		0x4A000008 /* Static Memory Control Register 0 */
-#define	MSC1		0x4A00000C /* Static Memory Control Register 1 */
-#define	MECR		0x4A000014 /* Expansion Memory (PCMCIA/Compact Flash) Bus Configuration */
-#define	SXCNFG		0x4A00001C /* Synchronous Static Memory Control Register */
-#define	MCMEM0		0x4A000028 /* Card interface Common Memory Space Socket 0 Timing */
-#define	MCATT0		0x4A000030 /* Card interface Attribute Space Socket 0 Timing Configuration */
-#define	MCIO0		0x4A000038 /* Card interface I/O Space Socket 0 Timing Configuration */
-#define	MEMCLKCFG	0x4A000068 /* SCLK speed configuration */
-#define	CSADRCFG0	0x4A000080 /* Address Configuration for chip select 0 */
-#define	CSADRCFG1	0x4A000084 /* Address Configuration for chip select 1 */
-#define	CSADRCFG2	0x4A000088 /* Address Configuration for chip select 2 */
-#define	CSADRCFG3	0x4A00008C /* Address Configuration for chip select 3 */
-#define	CSADRCFG_P	0x4A000090 /* Address Configuration for pcmcia card interface */
-#define	CSMSADRCFG	0x4A0000A0 /* Master Address Configuration Register */
-#define	CLK_RET_DEL	0x4A0000B0 /* Delay line and mux selects for return data latching for sync. flash */
-#define	ADV_RET_DEL	0x4A0000B4 /* Delay line and mux selects for return data latching for sync. flash */
-
-/* Dynamic Memory Controller Registers */
-#define	MDCNFG		0x48100000 /* SDRAM Configuration Register 0 */
-#define	MDREFR		0x48100004 /* SDRAM Refresh Control Register */
-#define	FLYCNFG		0x48100020 /* Fly-by DMA DVAL[1:0] polarities */
-#define	MDMRS		0x48100040 /* MRS value to be written to SDRAM */
-#define	DDR_SCAL	0x48100050 /* Software Delay Line Calibration/Configuration for external DDR memory. */
-#define	DDR_HCAL	0x48100060 /* Hardware Delay Line Calibration/Configuration for external DDR memory. */
-#define	DDR_WCAL	0x48100068 /* DDR Write Strobe Calibration Register */
-#define	DMCIER		0x48100070 /* Dynamic MC Interrupt Enable Register. */
-#define	DMCISR		0x48100078 /* Dynamic MC Interrupt Status Register. */
-#define	DDR_DLS		0x48100080 /* DDR Delay Line Value Status register for external DDR memory. */
-#define	EMPI		0x48100090 /* EMPI Control Register */
-#define	RCOMP		0x48100100
-#define	PAD_MA		0x48100110
-#define	PAD_MDMSB	0x48100114
-#define	PAD_MDLSB	0x48100118
-#define	PAD_DMEM	0x4810011c
-#define	PAD_SDCLK	0x48100120
-#define	PAD_SDCS	0x48100124
-#define	PAD_SMEM	0x48100128
-#define	PAD_SCLK	0x4810012C
-#define	TAI		0x48100F00 /* TAI Tavor Address Isolation Register */
-
-/* Some frequently used bits */
-#define MDCNFG_DMAP	0x80000000	/* SDRAM 1GB Memory Map Enable */
-#define MDCNFG_DMCEN	0x40000000	/* Enable Dynamic Memory Controller */
-#define MDCNFG_HWFREQ	0x20000000	/* Hardware Frequency Change Calibration */
-#define MDCNFG_DTYPE	0x400		/* SDRAM Type: 1=DDR SDRAM */
-
-#define MDCNFG_DTC_0	0x0		/* Timing Category of SDRAM */
-#define MDCNFG_DTC_1	0x100
-#define MDCNFG_DTC_2	0x200
-#define MDCNFG_DTC_3	0x300
-
-#define MDCNFG_DRAC_12	0x0		/* Number of Row Access Bits */
-#define MDCNFG_DRAC_13	0x20
-#define MDCNFG_DRAC_14	0x40
-
-#define MDCNFG_DCAC_9	0x0		/* Number of Column Acess Bits */
-#define MDCNFG_DCAC_10	0x08
-#define MDCNFG_DCAC_11	0x10
-
-#define MDCNFG_DBW_16	0x4		/* SDRAM Data Bus width 16bit */
-#define MDCNFG_DCSE1	0x2		/* SDRAM CS 1 Enable */
-#define MDCNFG_DCSE0	0x1		/* SDRAM CS 0 Enable */
-
-
-/* Data Flash Controller Registers */
-
-#define NDCR		0x43100000  /* Data Flash Control register */
-#define NDTR0CS0	0x43100004  /* Data Controller Timing Parameter 0 Register for ND_nCS0 */
-/* #define NDTR0CS1	0x43100008  /\* Data Controller Timing Parameter 0 Register for ND_nCS1 *\/ */
-#define NDTR1CS0	0x4310000C  /* Data Controller Timing Parameter 1 Register for ND_nCS0 */
-/* #define NDTR1CS1	0x43100010  /\* Data Controller Timing Parameter 1 Register for ND_nCS1 *\/ */
-#define NDSR		0x43100014  /* Data Controller Status Register */
-#define NDPCR		0x43100018  /* Data Controller Page Count Register */
-#define NDBDR0		0x4310001C  /* Data Controller Bad Block Register 0 */
-#define NDBDR1		0x43100020  /* Data Controller Bad Block Register 1 */
-#define NDDB		0x43100040  /* Data Controller Data Buffer */
-#define NDCB0		0x43100048  /* Data Controller Command Buffer0 */
-#define NDCB1		0x4310004C  /* Data Controller Command Buffer1 */
-#define NDCB2		0x43100050  /* Data Controller Command Buffer2 */
-
-#define NDCR_SPARE_EN	(0x1<<31)
-#define NDCR_ECC_EN	(0x1<<30)
-#define NDCR_DMA_EN	(0x1<<29)
-#define NDCR_ND_RUN	(0x1<<28)
-#define NDCR_DWIDTH_C	(0x1<<27)
-#define NDCR_DWIDTH_M	(0x1<<26)
-#define NDCR_PAGE_SZ	(0x3<<24)
-#define NDCR_NCSX	(0x1<<23)
-#define NDCR_ND_STOP	(0x1<<22)
-/* reserved:
- * #define NDCR_ND_MODE	(0x3<<21)
- * #define NDCR_NAND_MODE   0x0 */
-#define NDCR_CLR_PG_CNT	(0x1<<20)
-#define NDCR_CLR_ECC	(0x1<<19)
-#define NDCR_RD_ID_CNT	(0x7<<16)
-#define NDCR_RA_START	(0x1<<15)
-#define NDCR_PG_PER_BLK	(0x1<<14)
-#define NDCR_ND_ARB_EN	(0x1<<12)
-#define NDCR_RDYM	(0x1<<11)
-#define NDCR_CS0_PAGEDM	(0x1<<10)
-#define NDCR_CS1_PAGEDM	(0x1<<9)
-#define NDCR_CS0_CMDDM	(0x1<<8)
-#define NDCR_CS1_CMDDM	(0x1<<7)
-#define NDCR_CS0_BBDM	(0x1<<6)
-#define NDCR_CS1_BBDM	(0x1<<5)
-#define NDCR_DBERRM	(0x1<<4)
-#define NDCR_SBERRM	(0x1<<3)
-#define NDCR_WRDREQM	(0x1<<2)
-#define NDCR_RDDREQM	(0x1<<1)
-#define NDCR_WRCMDREQM	(0x1)
-
-#define NDSR_RDY	(0x1<<11)
-#define NDSR_CS0_PAGED	(0x1<<10)
-#define NDSR_CS1_PAGED	(0x1<<9)
-#define NDSR_CS0_CMDD	(0x1<<8)
-#define NDSR_CS1_CMDD	(0x1<<7)
-#define NDSR_CS0_BBD	(0x1<<6)
-#define NDSR_CS1_BBD	(0x1<<5)
-#define NDSR_DBERR	(0x1<<4)
-#define NDSR_SBERR	(0x1<<3)
-#define NDSR_WRDREQ	(0x1<<2)
-#define NDSR_RDDREQ	(0x1<<1)
-#define NDSR_WRCMDREQ	(0x1)
-
-#define NDCB0_AUTO_RS	(0x1<<25)
-#define NDCB0_CSEL	(0x1<<24)
-#define NDCB0_CMD_TYPE	(0x7<<21)
-#define NDCB0_NC	(0x1<<20)
-#define NDCB0_DBC	(0x1<<19)
-#define NDCB0_ADDR_CYC	(0x7<<16)
-#define NDCB0_CMD2	(0xff<<8)
-#define NDCB0_CMD1	(0xff)
-#define MCMEM(s) MCMEM0
-#define MCATT(s) MCATT0
-#define MCIO(s) MCIO0
-#define MECR_CIT	(1 << 1)/* Card Is There: 0 -> no card, 1 -> card inserted */
-
-/* Maximum values for NAND Interface Timing Registers in DFC clock
- * periods */
-#define DFC_MAX_tCH	7
-#define DFC_MAX_tCS	7
-#define DFC_MAX_tWH	7
-#define DFC_MAX_tWP	7
-#define DFC_MAX_tRH	7
-#define DFC_MAX_tRP	15
-#define DFC_MAX_tR	65535
-#define DFC_MAX_tWHR	15
-#define DFC_MAX_tAR	15
-
-#define DFC_CLOCK	104		/* DFC Clock is 104 MHz */
-#define DFC_CLK_PER_US	DFC_CLOCK/1000	/* clock period in ns */
-
-#else /* CONFIG_CPU_MONAHANS */
-
-/* PXA2xx */
-
-#define MEMC_BASE	0x48000000  /* Base of Memory Controller */
-#define MDCNFG_OFFSET	0x0
-#define MDREFR_OFFSET	0x4
-#define MSC0_OFFSET	0x8
-#define MSC1_OFFSET	0xC
-#define MSC2_OFFSET	0x10
-#define MECR_OFFSET	0x14
-#define SXLCR_OFFSET	0x18
-#define SXCNFG_OFFSET	0x1C
-#define FLYCNFG_OFFSET	0x20
-#define SXMRS_OFFSET	0x24
-#define MCMEM0_OFFSET	0x28
-#define MCMEM1_OFFSET	0x2C
-#define MCATT0_OFFSET	0x30
-#define MCATT1_OFFSET	0x34
-#define MCIO0_OFFSET	0x38
-#define MCIO1_OFFSET	0x3C
-#define MDMRS_OFFSET	0x40
-
-#define MDCNFG		0x48000000  /* SDRAM Configuration Register 0 */
-#define MDCNFG_DE0	0x00000001
-#define MDCNFG_DE1	0x00000002
-#define MDCNFG_DE2	0x00010000
-#define MDCNFG_DE3	0x00020000
-#define MDCNFG_DWID0	0x00000004
-
-#define MDREFR		0x48000004  /* SDRAM Refresh Control Register */
-#define MSC0		0x48000008  /* Static Memory Control Register 0 */
-#define MSC1		0x4800000C  /* Static Memory Control Register 1 */
-#define MSC2		0x48000010  /* Static Memory Control Register 2 */
-#define MECR		0x48000014  /* Expansion Memory (PCMCIA/Compact Flash) Bus Configuration */
-#define SXLCR		0x48000018  /* LCR value to be written to SDRAM-Timing Synchronous Flash */
-#define SXCNFG		0x4800001C  /* Synchronous Static Memory Control Register */
-#define FLYCNFG		0x48000020
-#define SXMRS		0x48000024  /* MRS value to be written to Synchronous Flash or SMROM */
-#define MCMEM0		0x48000028  /* Card interface Common Memory Space Socket 0 Timing */
-#define MCMEM1		0x4800002C  /* Card interface Common Memory Space Socket 1 Timing */
-#define MCATT0		0x48000030  /* Card interface Attribute Space Socket 0 Timing Configuration */
-#define MCATT1		0x48000034  /* Card interface Attribute Space Socket 1 Timing Configuration */
-#define MCIO0		0x48000038  /* Card interface I/O Space Socket 0 Timing Configuration */
-#define MCIO1		0x4800003C  /* Card interface I/O Space Socket 1 Timing Configuration */
-#define MDMRS		0x48000040  /* MRS value to be written to SDRAM */
-#define BOOT_DEF	0x48000044  /* Read-Only Boot-Time Register. Contains BOOT_SEL and PKG_SEL */
-
-#define MDREFR_ALTREFA	(1 << 31)	/* Exiting Alternate Bus Master Mode Refresh Control */
-#define MDREFR_ALTREFB	(1 << 30)	/* Entering Alternate Bus Master Mode Refresh Control */
-#define MDREFR_K0DB4	(1 << 29)	/* SDCLK0 Divide by 4 Control/Status */
-#define MDREFR_K2FREE	(1 << 25)	/* SDRAM Free-Running Control */
-#define MDREFR_K1FREE	(1 << 24)	/* SDRAM Free-Running Control */
-#define MDREFR_K0FREE	(1 << 23)	/* SDRAM Free-Running Control */
-#define MDREFR_SLFRSH	(1 << 22)	/* SDRAM Self-Refresh Control/Status */
-#define MDREFR_APD	(1 << 20)	/* SDRAM/SSRAM Auto-Power-Down Enable */
-#define MDREFR_K2DB2	(1 << 19)	/* SDCLK2 Divide by 2 Control/Status */
-#define MDREFR_K2RUN	(1 << 18)	/* SDCLK2 Run Control/Status */
-#define MDREFR_K1DB2	(1 << 17)	/* SDCLK1 Divide by 2 Control/Status */
-#define MDREFR_K1RUN	(1 << 16)	/* SDCLK1 Run Control/Status */
-#define MDREFR_E1PIN	(1 << 15)	/* SDCKE1 Level Control/Status */
-#define MDREFR_K0DB2	(1 << 14)	/* SDCLK0 Divide by 2 Control/Status */
-#define MDREFR_K0RUN	(1 << 13)	/* SDCLK0 Run Control/Status */
-#define MDREFR_E0PIN	(1 << 12)	/* SDCKE0 Level Control/Status */
-
-#if defined(CONFIG_PXA27X)
-
-#define ARB_CNTRL	0x48000048  /* Arbiter Control Register */
-
-#define ARB_DMA_SLV_PARK	(1<<31)	   /* Be parked with DMA slave when idle */
-#define ARB_CI_PARK		(1<<30)	   /* Be parked with Camera Interface when idle */
-#define ARB_EX_MEM_PARK		(1<<29)	   /* Be parked with external MEMC when idle */
-#define ARB_INT_MEM_PARK	(1<<28)	   /* Be parked with internal MEMC when idle */
-#define ARB_USB_PARK		(1<<27)	   /* Be parked with USB when idle */
-#define ARB_LCD_PARK		(1<<26)	   /* Be parked with LCD when idle */
-#define ARB_DMA_PARK		(1<<25)	   /* Be parked with DMA when idle */
-#define ARB_CORE_PARK		(1<<24)	   /* Be parked with core when idle */
-#define ARB_LOCK_FLAG		(1<<23)	   /* Only Locking masters gain access to the bus */
-
-#endif /* CONFIG_PXA27X */
-
-/* LCD registers */
-#define LCCR4		0x44000010  /* LCD Controller Control Register 4 */
-#define LCCR5		0x44000014  /* LCD Controller Control Register 5 */
-#define FBR0		0x44000020  /* DMA Channel 0 Frame Branch Register */
-#define FBR1		0x44000024  /* DMA Channel 1 Frame Branch Register */
-#define FBR2		0x44000028  /* DMA Channel 2 Frame Branch Register */
-#define FBR3		0x4400002C  /* DMA Channel 3 Frame Branch Register */
-#define FBR4		0x44000030  /* DMA Channel 4 Frame Branch Register */
-#define FDADR2		0x44000220  /* DMA Channel 2 Frame Descriptor Address Register */
-#define FSADR2		0x44000224  /* DMA Channel 2 Frame Source Address Register */
-#define FIDR2		0x44000228  /* DMA Channel 2 Frame ID Register */
-#define LDCMD2		0x4400022C  /* DMA Channel 2 Command Register */
-#define FDADR3		0x44000230  /* DMA Channel 3 Frame Descriptor Address Register */
-#define FSADR3		0x44000234  /* DMA Channel 3 Frame Source Address Register */
-#define FIDR3		0x44000238  /* DMA Channel 3 Frame ID Register */
-#define LDCMD3		0x4400023C  /* DMA Channel 3 Command Register */
-#define FDADR4		0x44000240  /* DMA Channel 4 Frame Descriptor Address Register */
-#define FSADR4		0x44000244  /* DMA Channel 4 Frame Source Address Register */
-#define FIDR4		0x44000248  /* DMA Channel 4 Frame ID Register */
-#define LDCMD4		0x4400024C  /* DMA Channel 4 Command Register */
-#define FDADR5		0x44000250  /* DMA Channel 5 Frame Descriptor Address Register */
-#define FSADR5		0x44000254  /* DMA Channel 5 Frame Source Address Register */
-#define FIDR5		0x44000258  /* DMA Channel 5 Frame ID Register */
-#define LDCMD5		0x4400025C  /* DMA Channel 5 Command Register */
-
-#define OVL1C1		0x44000050  /* Overlay 1 Control Register 1 */
-#define OVL1C2		0x44000060  /* Overlay 1 Control Register 2 */
-#define OVL2C1		0x44000070  /* Overlay 2 Control Register 1 */
-#define OVL2C2		0x44000080  /* Overlay 2 Control Register 2 */
-#define CCR		0x44000090  /* Cursor Control Register */
-
-#define FBR5		0x44000110  /* DMA Channel 5 Frame Branch Register */
-#define FBR6		0x44000114  /* DMA Channel 6 Frame Branch Register */
-
-#define LCCR0_LDDALT	(1<<26)		/* LDD Alternate mapping bit when base pixel is RGBT16 */
-#define LCCR0_OUC	(1<<25)		/* Overlay Underlay Control Bit */
-
-#define LCCR5_SOFM1	(1<<0)		/* Start Of Frame Mask for Overlay 1 (channel 1) */
-#define LCCR5_SOFM2	(1<<1)		/* Start Of Frame Mask for Overlay 2 (channel 2) */
-#define LCCR5_SOFM3	(1<<2)		/* Start Of Frame Mask for Overlay 2 (channel 3) */
-#define LCCR5_SOFM4	(1<<3)		/* Start Of Frame Mask for Overlay 2 (channel 4) */
-#define LCCR5_SOFM5	(1<<4)		/* Start Of Frame Mask for cursor (channel 5) */
-#define LCCR5_SOFM6	(1<<5)		/* Start Of Frame Mask for command data (channel 6) */
-
-#define LCCR5_EOFM1	(1<<8)		/* End Of Frame Mask for Overlay 1 (channel 1) */
-#define LCCR5_EOFM2	(1<<9)		/* End Of Frame Mask for Overlay 2 (channel 2) */
-#define LCCR5_EOFM3	(1<<10)		/* End Of Frame Mask for Overlay 2 (channel 3) */
-#define LCCR5_EOFM4	(1<<11)		/* End Of Frame Mask for Overlay 2 (channel 4) */
-#define LCCR5_EOFM5	(1<<12)		/* End Of Frame Mask for cursor (channel 5) */
-#define LCCR5_EOFM6	(1<<13)		/* End Of Frame Mask for command data (channel 6) */
-
-#define LCCR5_BSM1	(1<<16)		/* Branch mask for Overlay 1 (channel 1) */
-#define LCCR5_BSM2	(1<<17)		/* Branch mask for Overlay 2 (channel 2) */
-#define LCCR5_BSM3	(1<<18)		/* Branch mask for Overlay 2 (channel 3) */
-#define LCCR5_BSM4	(1<<19)		/* Branch mask for Overlay 2 (channel 4) */
-#define LCCR5_BSM5	(1<<20)		/* Branch mask for cursor (channel 5) */
-#define LCCR5_BSM6	(1<<21)		/* Branch mask for data command	 (channel 6) */
-
-#define LCCR5_IUM1	(1<<24)		/* Input FIFO Underrun Mask for Overlay 1  */
-#define LCCR5_IUM2	(1<<25)		/* Input FIFO Underrun Mask for Overlay 2  */
-#define LCCR5_IUM3	(1<<26)		/* Input FIFO Underrun Mask for Overlay 2  */
-#define LCCR5_IUM4	(1<<27)		/* Input FIFO Underrun Mask for Overlay 2  */
-#define LCCR5_IUM5	(1<<28)		/* Input FIFO Underrun Mask for cursor */
-#define LCCR5_IUM6	(1<<29)		/* Input FIFO Underrun Mask for data command */
-
-#define OVL1C1_O1EN	(1<<31)		/* Enable bit for Overlay 1 */
-#define OVL2C1_O2EN	(1<<31)		/* Enable bit for Overlay 2 */
-#define CCR_CEN		(1<<31)		/* Enable bit for Cursor */
-
-/* Keypad controller */
-
-#define KPC		0x41500000 /* Keypad Interface Control register */
-#define KPDK		0x41500008 /* Keypad Interface Direct Key register */
-#define KPREC		0x41500010 /* Keypad Intefcace Rotary Encoder register */
-#define KPMK		0x41500018 /* Keypad Intefcace Matrix Key register */
-#define KPAS		0x41500020 /* Keypad Interface Automatic Scan register */
-#define KPASMKP0	0x41500028 /* Keypad Interface Automatic Scan Multiple Key Presser register 0 */
-#define KPASMKP1	0x41500030 /* Keypad Interface Automatic Scan Multiple Key Presser register 1 */
-#define KPASMKP2	0x41500038 /* Keypad Interface Automatic Scan Multiple Key Presser register 2 */
-#define KPASMKP3	0x41500040 /* Keypad Interface Automatic Scan Multiple Key Presser register 3 */
-#define KPKDI		0x41500048 /* Keypad Interface Key Debounce Interval register */
-
-#define KPC_AS		(0x1 << 30)  /* Automatic Scan bit */
-#define KPC_ASACT	(0x1 << 29)  /* Automatic Scan on Activity */
-#define KPC_MI		(0x1 << 22)  /* Matrix interrupt bit */
-#define KPC_IMKP	(0x1 << 21)  /* Ignore Multiple Key Press */
-#define KPC_MS7		(0x1 << 20)  /* Matrix scan line 7 */
-#define KPC_MS6		(0x1 << 19)  /* Matrix scan line 6 */
-#define KPC_MS5		(0x1 << 18)  /* Matrix scan line 5 */
-#define KPC_MS4		(0x1 << 17)  /* Matrix scan line 4 */
-#define KPC_MS3		(0x1 << 16)  /* Matrix scan line 3 */
-#define KPC_MS2		(0x1 << 15)  /* Matrix scan line 2 */
-#define KPC_MS1		(0x1 << 14)  /* Matrix scan line 1 */
-#define KPC_MS0		(0x1 << 13)  /* Matrix scan line 0 */
-#define KPC_ME		(0x1 << 12)  /* Matrix Keypad Enable */
-#define KPC_MIE		(0x1 << 11)  /* Matrix Interrupt Enable */
-#define KPC_DK_DEB_SEL	(0x1 <<	 9)  /* Direct Key Debounce select */
-#define KPC_DI		(0x1 <<	 5)  /* Direct key interrupt bit */
-#define KPC_DEE0	(0x1 <<	 2)  /* Rotary Encoder 0 Enable */
-#define KPC_DE		(0x1 <<	 1)  /* Direct Keypad Enable */
-#define KPC_DIE		(0x1 <<	 0)  /* Direct Keypad interrupt Enable */
-
-#define KPDK_DKP	(0x1 << 31)
-#define KPDK_DK7	(0x1 <<	 7)
-#define KPDK_DK6	(0x1 <<	 6)
-#define KPDK_DK5	(0x1 <<	 5)
-#define KPDK_DK4	(0x1 <<	 4)
-#define KPDK_DK3	(0x1 <<	 3)
-#define KPDK_DK2	(0x1 <<	 2)
-#define KPDK_DK1	(0x1 <<	 1)
-#define KPDK_DK0	(0x1 <<	 0)
-
-#define KPREC_OF1	(0x1 << 31)
-#define kPREC_UF1	(0x1 << 30)
-#define KPREC_OF0	(0x1 << 15)
-#define KPREC_UF0	(0x1 << 14)
-
-#define KPMK_MKP	(0x1 << 31)
-#define KPAS_SO		(0x1 << 31)
-#define KPASMKPx_SO	(0x1 << 31)
-
-#define GPIO113_BIT	(1 << 17)/* GPIO113 in GPSR, GPCR, bit 17 */
-#define PSLR		0x40F00034
-#define PSTR		0x40F00038  /* Power Manager Standby Configuration Reg */
-#define PSNR		0x40F0003C  /* Power Manager Sense Configuration Reg */
-#define PVCR		0x40F00040  /* Power Manager Voltage Change Control Reg */
-#define PKWR		0x40F00050  /* Power Manager KB Wake-Up Enable Reg */
-#define PKSR		0x40F00054  /* Power Manager KB Level-Detect Status Reg */
-#define OSMR4		0x40A00080  /* */
-#define OSCR4		0x40A00040  /* OS Timer Counter Register */
-#define OMCR4		0x40A000C0  /* */
-
-#endif	/* CONFIG_PXA27X */
-
-#endif	/* _PXA_REGS_H_ */
diff --git a/arch/arm/include/asm/arch-s3c24x0/memory.h b/arch/arm/include/asm/arch-s3c24x0/memory.h
deleted file mode 100644
index 61d6270..0000000
--- a/arch/arm/include/asm/arch-s3c24x0/memory.h
+++ /dev/null
@@ -1,162 +0,0 @@
-/*
- * linux/include/asm-arm/arch-s3c2400/memory.h by garyj@denx.de
- * based on
- * linux/include/asm-arm/arch-sa1100/memory.h
- *
- * Copyright (c) 1999 Nicolas Pitre <nico@visuaide.com>
- */
-
-#ifndef __ASM_ARCH_MEMORY_H
-#define __ASM_ARCH_MEMORY_H
-
-
-/*
- * Task size: 3GB
- */
-#define TASK_SIZE       (0xc0000000UL)
-#define TASK_SIZE_26	(0x04000000UL)
-
-/*
- * This decides where the kernel will search for a free chunk of vm
- * space during mmap's.
- */
-#define TASK_UNMAPPED_BASE (TASK_SIZE / 3)
-
-/*
- * Page offset: 3GB
- */
-#define PAGE_OFFSET     (0xc0000000UL)
-
-/*
- * Physical DRAM offset is 0x0c000000 on the S3C2400
- */
-#define PHYS_OFFSET	(0x0c000000UL)
-
-#include <linux/config.h>
-
-
-/* Modified for S3C2400, by chc, 20010509 */
-#define RAM_IN_BANK_0  32*1024*1024
-#define RAM_IN_BANK_1  0
-#define RAM_IN_BANK_2  0
-#define RAM_IN_BANK_3  0
-
-#define MEM_SIZE  (RAM_IN_BANK_0+RAM_IN_BANK_1+RAM_IN_BANK_2+RAM_IN_BANK_3)
-
-
-/* translation macros */
-#define __virt_to_phys__is_a_macro
-#define __phys_to_virt__is_a_macro
-
-#if (RAM_IN_BANK_1 + RAM_IN_BANK_2 + RAM_IN_BANK_3 == 0)
-
-#define __virt_to_phys(x) ( (x) - PAGE_OFFSET + 0x0c000000 )
-#define __phys_to_virt(x) ( (x) - 0x0c000000 + PAGE_OFFSET )
-
-#elif (RAM_IN_BANK_0 == RAM_IN_BANK_1) && \
-      (RAM_IN_BANK_2 + RAM_IN_BANK_3 == 0)
-
-/* Two identical banks */
-#define __virt_to_phys(x) \
-	  ( ((x) < PAGE_OFFSET+RAM_IN_BANK_0) ? \
-	    ((x) - PAGE_OFFSET + _DRAMBnk0) : \
-	    ((x) - PAGE_OFFSET - RAM_IN_BANK_0 + _DRAMBnk1) )
-#define __phys_to_virt(x) \
-	  ( ((x)&0x07ffffff) + \
-	    (((x)&0x08000000) ? PAGE_OFFSET+RAM_IN_BANK_0 : PAGE_OFFSET) )
-#else
-
-/* It's more efficient for all other cases to use the function call */
-#undef __virt_to_phys__is_a_macro
-#undef __phys_to_virt__is_a_macro
-extern unsigned long __virt_to_phys(unsigned long vpage);
-extern unsigned long __phys_to_virt(unsigned long ppage);
-
-#endif
-
-/*
- * Virtual view <-> DMA view memory address translations
- * virt_to_bus: Used to translate the virtual address to an
- *              address suitable to be passed to set_dma_addr
- * bus_to_virt: Used to convert an address for DMA operations
- *              to an address that the kernel can use.
- *
- * On the SA1100, bus addresses are equivalent to physical addresses.
- */
-#define __virt_to_bus__is_a_macro
-#define __virt_to_bus(x)        __virt_to_phys(x)
-#define __bus_to_virt__is_a_macro
-#define __bus_to_virt(x)        __phys_to_virt(x)
-
-
-#ifdef CONFIG_DISCONTIGMEM
-#error "CONFIG_DISCONTIGMEM will not work on S3C2400"
-/*
- * Because of the wide memory address space between physical RAM banks on the
- * SA1100, it's much more convenient to use Linux's NUMA support to implement
- * our memory map representation.  Assuming all memory nodes have equal access
- * characteristics, we then have generic discontiguous memory support.
- *
- * Of course, all this isn't mandatory for SA1100 implementations with only
- * one used memory bank.  For those, simply undefine CONFIG_DISCONTIGMEM.
- *
- * The nodes are matched with the physical memory bank addresses which are
- * incidentally the same as virtual addresses.
- *
- *	node 0:  0xc0000000 - 0xc7ffffff
- *	node 1:  0xc8000000 - 0xcfffffff
- *	node 2:  0xd0000000 - 0xd7ffffff
- *	node 3:  0xd8000000 - 0xdfffffff
- */
-
-#define NR_NODES	4
-
-/*
- * Given a kernel address, find the home node of the underlying memory.
- */
-#define KVADDR_TO_NID(addr) \
-		(((unsigned long)(addr) - 0xc0000000) >> 27)
-
-/*
- * Given a physical address, convert it to a node id.
- */
-#define PHYS_TO_NID(addr) KVADDR_TO_NID(__phys_to_virt(addr))
-
-/*
- * Given a kaddr, ADDR_TO_MAPBASE finds the owning node of the memory
- * and returns the mem_map of that node.
- */
-#define ADDR_TO_MAPBASE(kaddr) \
-			NODE_MEM_MAP(KVADDR_TO_NID((unsigned long)(kaddr)))
-
-/*
- * Given a kaddr, LOCAL_MEM_MAP finds the owning node of the memory
- * and returns the index corresponding to the appropriate page in the
- * node's mem_map.
- */
-#define LOCAL_MAP_NR(kvaddr) \
-	(((unsigned long)(kvaddr) & 0x07ffffff) >> PAGE_SHIFT)
-
-/*
- * Given a kaddr, virt_to_page returns a pointer to the corresponding
- * mem_map entry.
- */
-#define virt_to_page(kaddr) \
-	(ADDR_TO_MAPBASE(kaddr) + LOCAL_MAP_NR(kaddr))
-
-/*
- * VALID_PAGE returns a non-zero value if given page pointer is valid.
- * This assumes all node's mem_maps are stored within the node they refer to.
- */
-#define VALID_PAGE(page) \
-({ unsigned int node = KVADDR_TO_NID(page); \
-   ( (node < NR_NODES) && \
-     ((unsigned)((page) - NODE_MEM_MAP(node)) < NODE_DATA(node)->node_size) ); \
-})
-
-#else
-
-#define PHYS_TO_NID(addr)	(0)
-
-#endif
-#endif /* __ASM_ARCH_MEMORY_H */
diff --git a/arch/arm/include/asm/arch-s3c24x0/s3c2400.h b/arch/arm/include/asm/arch-s3c24x0/s3c2400.h
deleted file mode 100644
index 2678be1..0000000
--- a/arch/arm/include/asm/arch-s3c24x0/s3c2400.h
+++ /dev/null
@@ -1,152 +0,0 @@
-/*
- * (C) Copyright 2003
- * David Müller ELSOFT AG Switzerland. d.mueller@elsoft.ch
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/************************************************
- * NAME	    : s3c2400.h
- * Version  : 31.3.2003
- *
- * Based on S3C2400X User's manual Rev 1.1
- ************************************************/
-
-#ifndef __S3C2400_H__
-#define __S3C2400_H__
-
-#define S3C24X0_UART_CHANNELS	2
-#define S3C24X0_SPI_CHANNELS	1
-#define PALETTE			(0x14A00400)	/* SJS */
-
-enum s3c24x0_uarts_nr {
-	S3C24X0_UART0,
-	S3C24X0_UART1,
-};
-
-/*S3C2400 device base addresses */
-#define S3C24X0_MEMCTL_BASE		0x14000000
-#define S3C24X0_USB_HOST_BASE		0x14200000
-#define S3C24X0_INTERRUPT_BASE		0x14400000
-#define S3C24X0_DMA_BASE		0x14600000
-#define S3C24X0_CLOCK_POWER_BASE	0x14800000
-#define S3C24X0_LCD_BASE		0x14A00000
-#define S3C24X0_UART_BASE		0x15000000
-#define S3C24X0_TIMER_BASE		0x15100000
-#define S3C24X0_USB_DEVICE_BASE		0x15200140
-#define S3C24X0_WATCHDOG_BASE		0x15300000
-#define S3C24X0_I2C_BASE		0x15400000
-#define S3C24X0_I2S_BASE		0x15508000
-#define S3C24X0_GPIO_BASE		0x15600000
-#define S3C24X0_RTC_BASE		0x15700000
-#define S3C24X0_ADC_BASE		0x15800000
-#define S3C24X0_SPI_BASE		0x15900000
-#define S3C2400_MMC_BASE		0x15A00000
-
-/* include common stuff */
-#include <asm/arch/s3c24x0.h>
-
-
-static inline struct s3c24x0_memctl *s3c24x0_get_base_memctl(void)
-{
-	return (struct s3c24x0_memctl *)S3C24X0_MEMCTL_BASE;
-}
-
-static inline struct s3c24x0_usb_host *s3c24x0_get_base_usb_host(void)
-{
-	return (struct s3c24x0_usb_host *)S3C24X0_USB_HOST_BASE;
-}
-
-static inline struct s3c24x0_interrupt *s3c24x0_get_base_interrupt(void)
-{
-	return (struct s3c24x0_interrupt *)S3C24X0_INTERRUPT_BASE;
-}
-
-static inline struct s3c24x0_dmas *s3c24x0_get_base_dmas(void)
-{
-	return (struct s3c24x0_dmas *)S3C24X0_DMA_BASE;
-}
-
-static inline struct s3c24x0_clock_power *s3c24x0_get_base_clock_power(void)
-{
-	return (struct s3c24x0_clock_power *)S3C24X0_CLOCK_POWER_BASE;
-}
-
-static inline struct s3c24x0_lcd *s3c24x0_get_base_lcd(void)
-{
-	return (struct s3c24x0_lcd *)S3C24X0_LCD_BASE;
-}
-
-static inline struct s3c24x0_uart
-	*s3c24x0_get_base_uart(enum s3c24x0_uarts_nr n)
-{
-	return (struct s3c24x0_uart *)(S3C24X0_UART_BASE + (n * 0x4000));
-}
-
-static inline struct s3c24x0_timers *s3c24x0_get_base_timers(void)
-{
-	return (struct s3c24x0_timers *)S3C24X0_TIMER_BASE;
-}
-
-static inline struct s3c24x0_usb_device *s3c24x0_get_base_usb_device(void)
-{
-	return (struct s3c24x0_usb_device *)S3C24X0_USB_DEVICE_BASE;
-}
-
-static inline struct s3c24x0_watchdog *s3c24x0_get_base_watchdog(void)
-{
-	return (struct s3c24x0_watchdog *)S3C24X0_WATCHDOG_BASE;
-}
-
-static inline struct s3c24x0_i2c *s3c24x0_get_base_i2c(void)
-{
-	return (struct s3c24x0_i2c *)S3C24X0_I2C_BASE;
-}
-
-static inline struct s3c24x0_i2s *s3c24x0_get_base_i2s(void)
-{
-	return (struct s3c24x0_i2s *)S3C24X0_I2S_BASE;
-}
-
-static inline struct s3c24x0_gpio *s3c24x0_get_base_gpio(void)
-{
-	return (struct s3c24x0_gpio *)S3C24X0_GPIO_BASE;
-}
-
-static inline struct s3c24x0_rtc *s3c24x0_get_base_rtc(void)
-{
-	return (struct s3c24x0_rtc *)S3C24X0_RTC_BASE;
-}
-
-static inline struct s3c2400_adc *s3c2400_get_base_adc(void)
-{
-	return (struct s3c2400_adc *)S3C24X0_ADC_BASE;
-}
-
-static inline struct s3c24x0_spi *s3c24x0_get_base_spi(void)
-{
-	return (struct s3c24x0_spi *)S3C24X0_SPI_BASE;
-}
-
-static inline struct s3c2400_mmc *s3c2400_get_base_mmc(void)
-{
-	return (struct s3c2400_mmc *)S3C2400_MMC_BASE;
-}
-
-#endif /*__S3C2400_H__*/
diff --git a/arch/arm/include/asm/arch-s3c24x0/s3c2410.h b/arch/arm/include/asm/arch-s3c24x0/s3c2410.h
deleted file mode 100644
index 0543fe1..0000000
--- a/arch/arm/include/asm/arch-s3c24x0/s3c2410.h
+++ /dev/null
@@ -1,163 +0,0 @@
-/*
- * (C) Copyright 2003
- * David Müller ELSOFT AG Switzerland. d.mueller@elsoft.ch
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/************************************************
- * NAME	    : s3c2410.h
- * Version  : 31.3.2003
- *
- * Based on S3C2410X User's manual Rev 1.1
- ************************************************/
-
-#ifndef __S3C2410_H__
-#define __S3C2410_H__
-
-#define S3C24X0_UART_CHANNELS	3
-#define S3C24X0_SPI_CHANNELS	2
-
-/* S3C2410 only supports 512 Byte HW ECC */
-#define S3C2410_ECCSIZE		512
-#define S3C2410_ECCBYTES	3
-
-enum s3c24x0_uarts_nr {
-	S3C24X0_UART0,
-	S3C24X0_UART1,
-	S3C24X0_UART2
-};
-
-/* S3C2410 device base addresses */
-#define S3C24X0_MEMCTL_BASE		0x48000000
-#define S3C24X0_USB_HOST_BASE		0x49000000
-#define S3C24X0_INTERRUPT_BASE		0x4A000000
-#define S3C24X0_DMA_BASE		0x4B000000
-#define S3C24X0_CLOCK_POWER_BASE	0x4C000000
-#define S3C24X0_LCD_BASE		0x4D000000
-#define S3C2410_NAND_BASE		0x4E000000
-#define S3C24X0_UART_BASE		0x50000000
-#define S3C24X0_TIMER_BASE		0x51000000
-#define S3C24X0_USB_DEVICE_BASE		0x52000140
-#define S3C24X0_WATCHDOG_BASE		0x53000000
-#define S3C24X0_I2C_BASE		0x54000000
-#define S3C24X0_I2S_BASE		0x55000000
-#define S3C24X0_GPIO_BASE		0x56000000
-#define S3C24X0_RTC_BASE		0x57000000
-#define S3C2410_ADC_BASE		0x58000000
-#define S3C24X0_SPI_BASE		0x59000000
-#define S3C2410_SDI_BASE		0x5A000000
-
-
-/* include common stuff */
-#include <asm/arch/s3c24x0.h>
-
-
-static inline struct s3c24x0_memctl *s3c24x0_get_base_memctl(void)
-{
-	return (struct s3c24x0_memctl *)S3C24X0_MEMCTL_BASE;
-}
-
-static inline struct s3c24x0_usb_host *s3c24x0_get_base_usb_host(void)
-{
-	return (struct s3c24x0_usb_host *)S3C24X0_USB_HOST_BASE;
-}
-
-static inline struct s3c24x0_interrupt *s3c24x0_get_base_interrupt(void)
-{
-	return (struct s3c24x0_interrupt *)S3C24X0_INTERRUPT_BASE;
-}
-
-static inline struct s3c24x0_dmas *s3c24x0_get_base_dmas(void)
-{
-	return (struct s3c24x0_dmas *)S3C24X0_DMA_BASE;
-}
-
-static inline struct s3c24x0_clock_power *s3c24x0_get_base_clock_power(void)
-{
-	return (struct s3c24x0_clock_power *)S3C24X0_CLOCK_POWER_BASE;
-}
-
-static inline struct s3c24x0_lcd *s3c24x0_get_base_lcd(void)
-{
-	return (struct s3c24x0_lcd *)S3C24X0_LCD_BASE;
-}
-
-static inline struct s3c2410_nand *s3c2410_get_base_nand(void)
-{
-	return (struct s3c2410_nand *)S3C2410_NAND_BASE;
-}
-
-static inline struct s3c24x0_uart
-	*s3c24x0_get_base_uart(enum s3c24x0_uarts_nr n)
-{
-	return (struct s3c24x0_uart *)(S3C24X0_UART_BASE + (n * 0x4000));
-}
-
-static inline struct s3c24x0_timers *s3c24x0_get_base_timers(void)
-{
-	return (struct s3c24x0_timers *)S3C24X0_TIMER_BASE;
-}
-
-static inline struct s3c24x0_usb_device *s3c24x0_get_base_usb_device(void)
-{
-	return (struct s3c24x0_usb_device *)S3C24X0_USB_DEVICE_BASE;
-}
-
-static inline struct s3c24x0_watchdog *s3c24x0_get_base_watchdog(void)
-{
-	return (struct s3c24x0_watchdog *)S3C24X0_WATCHDOG_BASE;
-}
-
-static inline struct s3c24x0_i2c *s3c24x0_get_base_i2c(void)
-{
-	return (struct s3c24x0_i2c *)S3C24X0_I2C_BASE;
-}
-
-static inline struct s3c24x0_i2s *s3c24x0_get_base_i2s(void)
-{
-	return (struct s3c24x0_i2s *)S3C24X0_I2S_BASE;
-}
-
-static inline struct s3c24x0_gpio *s3c24x0_get_base_gpio(void)
-{
-	return (struct s3c24x0_gpio *)S3C24X0_GPIO_BASE;
-}
-
-static inline struct s3c24x0_rtc *s3c24x0_get_base_rtc(void)
-{
-	return (struct s3c24x0_rtc *)S3C24X0_RTC_BASE;
-}
-
-static inline struct s3c2410_adc *s3c2410_get_base_adc(void)
-{
-	return (struct s3c2410_adc *)S3C2410_ADC_BASE;
-}
-
-static inline struct s3c24x0_spi *s3c24x0_get_base_spi(void)
-{
-	return (struct s3c24x0_spi *)S3C24X0_SPI_BASE;
-}
-
-static inline struct s3c2410_sdi *s3c2410_get_base_sdi(void)
-{
-	return (struct s3c2410_sdi *)S3C2410_SDI_BASE;
-}
-
-#endif /*__S3C2410_H__*/
diff --git a/arch/arm/include/asm/arch-s3c24x0/s3c2440.h b/arch/arm/include/asm/arch-s3c24x0/s3c2440.h
deleted file mode 100644
index 8c606e3..0000000
--- a/arch/arm/include/asm/arch-s3c24x0/s3c2440.h
+++ /dev/null
@@ -1,161 +0,0 @@
-/*
- * (C) Copyright 2003
- * David Mueller ELSOFT AG Switzerland. d.mueller@elsoft.ch
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/************************************************
- * NAME	    : s3c2440.h
- * Version  : 31.3.2003
- *
- * Based on S3C2440 User's manual Rev x.x
- ************************************************/
-
-#ifndef __S3C2440_H__
-#define __S3C2440_H__
-
-#define S3C24X0_UART_CHANNELS	3
-#define S3C24X0_SPI_CHANNELS	2
-
-/* S3C2440 only supports 512 Byte HW ECC */
-#define S3C2440_ECCSIZE		512
-#define S3C2440_ECCBYTES	3
-
-enum s3c24x0_uarts_nr {
-	S3C24X0_UART0,
-	S3C24X0_UART1,
-	S3C24X0_UART2
-};
-
-/* S3C2440 device base addresses */
-#define S3C24X0_MEMCTL_BASE		0x48000000
-#define S3C24X0_USB_HOST_BASE		0x49000000
-#define S3C24X0_INTERRUPT_BASE		0x4A000000
-#define S3C24X0_DMA_BASE		0x4B000000
-#define S3C24X0_CLOCK_POWER_BASE	0x4C000000
-#define S3C24X0_LCD_BASE		0x4D000000
-#define S3C2440_NAND_BASE		0x4E000000
-#define S3C24X0_UART_BASE		0x50000000
-#define S3C24X0_TIMER_BASE		0x51000000
-#define S3C24X0_USB_DEVICE_BASE		0x52000140
-#define S3C24X0_WATCHDOG_BASE		0x53000000
-#define S3C24X0_I2C_BASE		0x54000000
-#define S3C24X0_I2S_BASE		0x55000000
-#define S3C24X0_GPIO_BASE		0x56000000
-#define S3C24X0_RTC_BASE		0x57000000
-#define S3C2440_ADC_BASE		0x58000000
-#define S3C24X0_SPI_BASE		0x59000000
-#define S3C2440_SDI_BASE		0x5A000000
-
-/* include common stuff */
-#include <asm/arch/s3c24x0.h>
-
-static inline struct s3c24x0_memctl *s3c24x0_get_base_memctl(void)
-{
-	return (struct s3c24x0_memctl *)S3C24X0_MEMCTL_BASE;
-}
-
-static inline struct s3c24x0_usb_host *s3c24x0_get_base_usb_host(void)
-{
-	return (struct s3c24x0_usb_host *)S3C24X0_USB_HOST_BASE;
-}
-
-static inline struct s3c24x0_interrupt *s3c24x0_get_base_interrupt(void)
-{
-	return (struct s3c24x0_interrupt *)S3C24X0_INTERRUPT_BASE;
-}
-
-static inline struct s3c24x0_dmas *s3c24x0_get_base_dmas(void)
-{
-	return (struct s3c24x0_dmas *)S3C24X0_DMA_BASE;
-}
-
-static inline struct s3c24x0_clock_power *s3c24x0_get_base_clock_power(void)
-{
-	return (struct s3c24x0_clock_power *)S3C24X0_CLOCK_POWER_BASE;
-}
-
-static inline struct s3c24x0_lcd *s3c24x0_get_base_lcd(void)
-{
-	return (struct s3c24x0_lcd *)S3C24X0_LCD_BASE;
-}
-
-static inline struct s3c2440_nand *s3c2440_get_base_nand(void)
-{
-	return (struct s3c2440_nand *)S3C2440_NAND_BASE;
-}
-
-static inline struct s3c24x0_uart
-	*s3c24x0_get_base_uart(enum s3c24x0_uarts_nr n)
-{
-	return (struct s3c24x0_uart *)(S3C24X0_UART_BASE + (n * 0x4000));
-}
-
-static inline struct s3c24x0_timers *s3c24x0_get_base_timers(void)
-{
-	return (struct s3c24x0_timers *)S3C24X0_TIMER_BASE;
-}
-
-static inline struct s3c24x0_usb_device *s3c24x0_get_base_usb_device(void)
-{
-	return (struct s3c24x0_usb_device *)S3C24X0_USB_DEVICE_BASE;
-}
-
-static inline struct s3c24x0_watchdog *s3c24x0_get_base_watchdog(void)
-{
-	return (struct s3c24x0_watchdog *)S3C24X0_WATCHDOG_BASE;
-}
-
-static inline struct s3c24x0_i2c *s3c24x0_get_base_i2c(void)
-{
-	return (struct s3c24x0_i2c *)S3C24X0_I2C_BASE;
-}
-
-static inline struct s3c24x0_i2s *s3c24x0_get_base_i2s(void)
-{
-	return (struct s3c24x0_i2s *)S3C24X0_I2S_BASE;
-}
-
-static inline struct s3c24x0_gpio *s3c24x0_get_base_gpio(void)
-{
-	return (struct s3c24x0_gpio *)S3C24X0_GPIO_BASE;
-}
-
-static inline struct s3c24x0_rtc *s3c24x0_get_base_rtc(void)
-{
-	return (struct s3c24x0_rtc *)S3C24X0_RTC_BASE;
-}
-
-static inline struct s3c2440_adc *s3c2440_get_base_adc(void)
-{
-	return (struct s3c2440_adc *)S3C2440_ADC_BASE;
-}
-
-static inline struct s3c24x0_spi *s3c24x0_get_base_spi(void)
-{
-	return (struct s3c24x0_spi *)S3C24X0_SPI_BASE;
-}
-
-static inline struct s3c2440_sdi *s3c2440_get_base_sdi(void)
-{
-	return (struct s3c2440_sdi *)S3C2440_SDI_BASE;
-}
-
-#endif /*__S3C2440_H__*/
diff --git a/arch/arm/include/asm/arch-s3c24x0/s3c24x0.h b/arch/arm/include/asm/arch-s3c24x0/s3c24x0.h
deleted file mode 100644
index f634d11..0000000
--- a/arch/arm/include/asm/arch-s3c24x0/s3c24x0.h
+++ /dev/null
@@ -1,730 +0,0 @@
-/*
- * (C) Copyright 2003
- * David Müller ELSOFT AG Switzerland. d.mueller@elsoft.ch
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/************************************************
- * NAME	    : s3c24x0.h
- * Version  : 31.3.2003
- *
- * common stuff for SAMSUNG S3C24X0 SoC
- ************************************************/
-
-#ifndef __S3C24X0_H__
-#define __S3C24X0_H__
-
-/* Memory controller (see manual chapter 5) */
-struct s3c24x0_memctl {
-	u32	bwscon;
-	u32	bankcon[8];
-	u32	refresh;
-	u32	banksize;
-	u32	mrsrb6;
-	u32	mrsrb7;
-};
-
-
-/* USB HOST (see manual chapter 12) */
-struct s3c24x0_usb_host {
-	u32	HcRevision;
-	u32	HcControl;
-	u32	HcCommonStatus;
-	u32	HcInterruptStatus;
-	u32	HcInterruptEnable;
-	u32	HcInterruptDisable;
-	u32	HcHCCA;
-	u32	HcPeriodCuttendED;
-	u32	HcControlHeadED;
-	u32	HcControlCurrentED;
-	u32	HcBulkHeadED;
-	u32	HcBuldCurrentED;
-	u32	HcDoneHead;
-	u32	HcRmInterval;
-	u32	HcFmRemaining;
-	u32	HcFmNumber;
-	u32	HcPeriodicStart;
-	u32	HcLSThreshold;
-	u32	HcRhDescriptorA;
-	u32	HcRhDescriptorB;
-	u32	HcRhStatus;
-	u32	HcRhPortStatus1;
-	u32	HcRhPortStatus2;
-};
-
-
-/* INTERRUPT (see manual chapter 14) */
-struct s3c24x0_interrupt {
-	u32	srcpnd;
-	u32	intmod;
-	u32	intmsk;
-	u32	priority;
-	u32	intpnd;
-	u32	intoffset;
-#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)
-	u32	subsrcpnd;
-	u32	intsubmsk;
-#endif
-};
-
-
-/* DMAS (see manual chapter 8) */
-struct s3c24x0_dma {
-	u32	disrc;
-#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)
-	u32	disrcc;
-#endif
-	u32	didst;
-#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)
-	u32	didstc;
-#endif
-	u32	dcon;
-	u32	dstat;
-	u32	dcsrc;
-	u32	dcdst;
-	u32	dmasktrig;
-#if defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410) \
-		|| defined(CONFIG_S3C2440)
-	u32	res[1];
-#endif
-};
-
-struct s3c24x0_dmas {
-	struct s3c24x0_dma	dma[4];
-};
-
-
-/* CLOCK & POWER MANAGEMENT (see S3C2400 manual chapter 6) */
-/*                          (see S3C2410 manual chapter 7) */
-struct s3c24x0_clock_power {
-	u32	locktime;
-	u32	mpllcon;
-	u32	upllcon;
-	u32	clkcon;
-	u32	clkslow;
-	u32	clkdivn;
-#if defined(CONFIG_S3C2440)
-	u32	camdivn;
-#endif
-};
-
-
-/* LCD CONTROLLER (see manual chapter 15) */
-struct s3c24x0_lcd {
-	u32	lcdcon1;
-	u32	lcdcon2;
-	u32	lcdcon3;
-	u32	lcdcon4;
-	u32	lcdcon5;
-	u32	lcdsaddr1;
-	u32	lcdsaddr2;
-	u32	lcdsaddr3;
-	u32	redlut;
-	u32	greenlut;
-	u32	bluelut;
-	u32	res[8];
-	u32	dithmode;
-	u32	tpal;
-#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)
-	u32	lcdintpnd;
-	u32	lcdsrcpnd;
-	u32	lcdintmsk;
-	u32	lpcsel;
-#endif
-};
-
-
-#ifdef CONFIG_S3C2410
-/* NAND FLASH (see S3C2410 manual chapter 6) */
-struct s3c2410_nand {
-	u32	nfconf;
-	u32	nfcmd;
-	u32	nfaddr;
-	u32	nfdata;
-	u32	nfstat;
-	u32	nfecc;
-};
-#endif
-#ifdef CONFIG_S3C2440
-/* NAND FLASH (see S3C2440 manual chapter 6) */
-struct s3c2440_nand {
-	u32	nfconf;
-	u32	nfcont;
-	u32	nfcmd;
-	u32	nfaddr;
-	u32	nfdata;
-	u32	nfeccd0;
-	u32	nfeccd1;
-	u32	nfeccd;
-	u32	nfstat;
-	u32	nfstat0;
-	u32	nfstat1;
-};
-#endif
-
-
-/* UART (see manual chapter 11) */
-struct s3c24x0_uart {
-	u32	ulcon;
-	u32	ucon;
-	u32	ufcon;
-	u32	umcon;
-	u32	utrstat;
-	u32	uerstat;
-	u32	ufstat;
-	u32	umstat;
-#ifdef __BIG_ENDIAN
-	u8	res1[3];
-	u8	utxh;
-	u8	res2[3];
-	u8	urxh;
-#else /* Little Endian */
-	u8	utxh;
-	u8	res1[3];
-	u8	urxh;
-	u8	res2[3];
-#endif
-	u32	ubrdiv;
-};
-
-
-/* PWM TIMER (see manual chapter 10) */
-struct s3c24x0_timer {
-	u32	tcntb;
-	u32	tcmpb;
-	u32	tcnto;
-};
-
-struct s3c24x0_timers {
-	u32	tcfg0;
-	u32	tcfg1;
-	u32	tcon;
-	struct s3c24x0_timer	ch[4];
-	u32	tcntb4;
-	u32	tcnto4;
-};
-
-
-/* USB DEVICE (see manual chapter 13) */
-struct s3c24x0_usb_dev_fifos {
-#ifdef __BIG_ENDIAN
-	u8	res[3];
-	u8	ep_fifo_reg;
-#else /*  little endian */
-	u8	ep_fifo_reg;
-	u8	res[3];
-#endif
-};
-
-struct s3c24x0_usb_dev_dmas {
-#ifdef __BIG_ENDIAN
-	u8	res1[3];
-	u8	ep_dma_con;
-	u8	res2[3];
-	u8	ep_dma_unit;
-	u8	res3[3];
-	u8	ep_dma_fifo;
-	u8	res4[3];
-	u8	ep_dma_ttc_l;
-	u8	res5[3];
-	u8	ep_dma_ttc_m;
-	u8	res6[3];
-	u8	ep_dma_ttc_h;
-#else /*  little endian */
-	u8	ep_dma_con;
-	u8	res1[3];
-	u8	ep_dma_unit;
-	u8	res2[3];
-	u8	ep_dma_fifo;
-	u8	res3[3];
-	u8	ep_dma_ttc_l;
-	u8	res4[3];
-	u8	ep_dma_ttc_m;
-	u8	res5[3];
-	u8	ep_dma_ttc_h;
-	u8	res6[3];
-#endif
-};
-
-struct s3c24x0_usb_device {
-#ifdef __BIG_ENDIAN
-	u8	res1[3];
-	u8	func_addr_reg;
-	u8	res2[3];
-	u8	pwr_reg;
-	u8	res3[3];
-	u8	ep_int_reg;
-	u8	res4[15];
-	u8	usb_int_reg;
-	u8	res5[3];
-	u8	ep_int_en_reg;
-	u8	res6[15];
-	u8	usb_int_en_reg;
-	u8	res7[3];
-	u8	frame_num1_reg;
-	u8	res8[3];
-	u8	frame_num2_reg;
-	u8	res9[3];
-	u8	index_reg;
-	u8	res10[7];
-	u8	maxp_reg;
-	u8	res11[3];
-	u8	ep0_csr_in_csr1_reg;
-	u8	res12[3];
-	u8	in_csr2_reg;
-	u8	res13[7];
-	u8	out_csr1_reg;
-	u8	res14[3];
-	u8	out_csr2_reg;
-	u8	res15[3];
-	u8	out_fifo_cnt1_reg;
-	u8	res16[3];
-	u8	out_fifo_cnt2_reg;
-#else /*  little endian */
-	u8	func_addr_reg;
-	u8	res1[3];
-	u8	pwr_reg;
-	u8	res2[3];
-	u8	ep_int_reg;
-	u8	res3[15];
-	u8	usb_int_reg;
-	u8	res4[3];
-	u8	ep_int_en_reg;
-	u8	res5[15];
-	u8	usb_int_en_reg;
-	u8	res6[3];
-	u8	frame_num1_reg;
-	u8	res7[3];
-	u8	frame_num2_reg;
-	u8	res8[3];
-	u8	index_reg;
-	u8	res9[7];
-	u8	maxp_reg;
-	u8	res10[7];
-	u8	ep0_csr_in_csr1_reg;
-	u8	res11[3];
-	u8	in_csr2_reg;
-	u8	res12[3];
-	u8	out_csr1_reg;
-	u8	res13[7];
-	u8	out_csr2_reg;
-	u8	res14[3];
-	u8	out_fifo_cnt1_reg;
-	u8	res15[3];
-	u8	out_fifo_cnt2_reg;
-	u8	res16[3];
-#endif /*  __BIG_ENDIAN */
-	struct s3c24x0_usb_dev_fifos	fifo[5];
-	struct s3c24x0_usb_dev_dmas	dma[5];
-};
-
-
-/* WATCH DOG TIMER (see manual chapter 18) */
-struct s3c24x0_watchdog {
-	u32	wtcon;
-	u32	wtdat;
-	u32	wtcnt;
-};
-
-
-/* IIC (see manual chapter 20) */
-struct s3c24x0_i2c {
-	u32	iiccon;
-	u32	iicstat;
-	u32	iicadd;
-	u32	iicds;
-};
-
-
-/* IIS (see manual chapter 21) */
-struct s3c24x0_i2s {
-#ifdef __BIG_ENDIAN
-	u16	res1;
-	u16	iiscon;
-	u16	res2;
-	u16	iismod;
-	u16	res3;
-	u16	iispsr;
-	u16	res4;
-	u16	iisfcon;
-	u16	res5;
-	u16	iisfifo;
-#else /*  little endian */
-	u16	iiscon;
-	u16	res1;
-	u16	iismod;
-	u16	res2;
-	u16	iispsr;
-	u16	res3;
-	u16	iisfcon;
-	u16	res4;
-	u16	iisfifo;
-	u16	res5;
-#endif
-};
-
-
-/* I/O PORT (see manual chapter 9) */
-struct s3c24x0_gpio {
-#ifdef CONFIG_S3C2400
-	u32	pacon;
-	u32	padat;
-
-	u32	pbcon;
-	u32	pbdat;
-	u32	pbup;
-
-	u32	pccon;
-	u32	pcdat;
-	u32	pcup;
-
-	u32	pdcon;
-	u32	pddat;
-	u32	pdup;
-
-	u32	pecon;
-	u32	pedat;
-	u32	peup;
-
-	u32	pfcon;
-	u32	pfdat;
-	u32	pfup;
-
-	u32	pgcon;
-	u32	pgdat;
-	u32	pgup;
-
-	u32	opencr;
-
-	u32	misccr;
-	u32	extint;
-#endif
-#ifdef CONFIG_S3C2410
-	u32	gpacon;
-	u32	gpadat;
-	u32	res1[2];
-	u32	gpbcon;
-	u32	gpbdat;
-	u32	gpbup;
-	u32	res2;
-	u32	gpccon;
-	u32	gpcdat;
-	u32	gpcup;
-	u32	res3;
-	u32	gpdcon;
-	u32	gpddat;
-	u32	gpdup;
-	u32	res4;
-	u32	gpecon;
-	u32	gpedat;
-	u32	gpeup;
-	u32	res5;
-	u32	gpfcon;
-	u32	gpfdat;
-	u32	gpfup;
-	u32	res6;
-	u32	gpgcon;
-	u32	gpgdat;
-	u32	gpgup;
-	u32	res7;
-	u32	gphcon;
-	u32	gphdat;
-	u32	gphup;
-	u32	res8;
-
-	u32	misccr;
-	u32	dclkcon;
-	u32	extint0;
-	u32	extint1;
-	u32	extint2;
-	u32	eintflt0;
-	u32	eintflt1;
-	u32	eintflt2;
-	u32	eintflt3;
-	u32	eintmask;
-	u32	eintpend;
-	u32	gstatus0;
-	u32	gstatus1;
-	u32	gstatus2;
-	u32	gstatus3;
-	u32	gstatus4;
-#endif
-#if defined(CONFIG_S3C2440)
-	u32	gpacon;
-	u32	gpadat;
-	u32	res1[2];
-	u32	gpbcon;
-	u32	gpbdat;
-	u32	gpbup;
-	u32	res2;
-	u32	gpccon;
-	u32	gpcdat;
-	u32	gpcup;
-	u32	res3;
-	u32	gpdcon;
-	u32	gpddat;
-	u32	gpdup;
-	u32	res4;
-	u32	gpecon;
-	u32	gpedat;
-	u32	gpeup;
-	u32	res5;
-	u32	gpfcon;
-	u32	gpfdat;
-	u32	gpfup;
-	u32	res6;
-	u32	gpgcon;
-	u32	gpgdat;
-	u32	gpgup;
-	u32	res7;
-	u32	gphcon;
-	u32	gphdat;
-	u32	gphup;
-	u32	res8;
-
-	u32	misccr;
-	u32	dclkcon;
-	u32	extint0;
-	u32	extint1;
-	u32	extint2;
-	u32	eintflt0;
-	u32	eintflt1;
-	u32	eintflt2;
-	u32	eintflt3;
-	u32	eintmask;
-	u32	eintpend;
-	u32	gstatus0;
-	u32	gstatus1;
-	u32	gstatus2;
-	u32	gstatus3;
-	u32	gstatus4;
-
-	u32	res9;
-	u32	dsc0;
-	u32	dsc1;
-	u32	mslcon;
-	u32	gpjcon;
-	u32	gpjdat;
-	u32	gpjup;
-	u32	res10;
-#endif
-};
-
-
-/* RTC (see manual chapter 17) */
-struct s3c24x0_rtc {
-#ifdef __BIG_ENDIAN
-	u8	res1[67];
-	u8	rtccon;
-	u8	res2[3];
-	u8	ticnt;
-	u8	res3[11];
-	u8	rtcalm;
-	u8	res4[3];
-	u8	almsec;
-	u8	res5[3];
-	u8	almmin;
-	u8	res6[3];
-	u8	almhour;
-	u8	res7[3];
-	u8	almdate;
-	u8	res8[3];
-	u8	almmon;
-	u8	res9[3];
-	u8	almyear;
-	u8	res10[3];
-	u8	rtcrst;
-	u8	res11[3];
-	u8	bcdsec;
-	u8	res12[3];
-	u8	bcdmin;
-	u8	res13[3];
-	u8	bcdhour;
-	u8	res14[3];
-	u8	bcddate;
-	u8	res15[3];
-	u8	bcdday;
-	u8	res16[3];
-	u8	bcdmon;
-	u8	res17[3];
-	u8	bcdyear;
-#else /*  little endian */
-	u8	res0[64];
-	u8	rtccon;
-	u8	res1[3];
-	u8	ticnt;
-	u8	res2[11];
-	u8	rtcalm;
-	u8	res3[3];
-	u8	almsec;
-	u8	res4[3];
-	u8	almmin;
-	u8	res5[3];
-	u8	almhour;
-	u8	res6[3];
-	u8	almdate;
-	u8	res7[3];
-	u8	almmon;
-	u8	res8[3];
-	u8	almyear;
-	u8	res9[3];
-	u8	rtcrst;
-	u8	res10[3];
-	u8	bcdsec;
-	u8	res11[3];
-	u8	bcdmin;
-	u8	res12[3];
-	u8	bcdhour;
-	u8	res13[3];
-	u8	bcddate;
-	u8	res14[3];
-	u8	bcdday;
-	u8	res15[3];
-	u8	bcdmon;
-	u8	res16[3];
-	u8	bcdyear;
-	u8	res17[3];
-#endif
-};
-
-
-/* ADC (see manual chapter 16) */
-struct s3c2400_adc {
-	u32	adccon;
-	u32	adcdat;
-};
-
-
-/* ADC (see manual chapter 16) */
-struct s3c2410_adc {
-	u32	adccon;
-	u32	adctsc;
-	u32	adcdly;
-	u32	adcdat0;
-	u32	adcdat1;
-};
-
-
-/* SPI (see manual chapter 22) */
-struct s3c24x0_spi_channel {
-	u8	spcon;
-	u8	res1[3];
-	u8	spsta;
-	u8	res2[3];
-	u8	sppin;
-	u8	res3[3];
-	u8	sppre;
-	u8	res4[3];
-	u8	sptdat;
-	u8	res5[3];
-	u8	sprdat;
-	u8	res6[3];
-	u8	res7[16];
-};
-
-struct s3c24x0_spi {
-	struct s3c24x0_spi_channel	ch[S3C24X0_SPI_CHANNELS];
-};
-
-
-/* MMC INTERFACE (see S3C2400 manual chapter 19) */
-struct s3c2400_mmc {
-#ifdef __BIG_ENDIAN
-	u8	res1[3];
-	u8	mmcon;
-	u8	res2[3];
-	u8	mmcrr;
-	u8	res3[3];
-	u8	mmfcon;
-	u8	res4[3];
-	u8	mmsta;
-	u16	res5;
-	u16	mmfsta;
-	u8	res6[3];
-	u8	mmpre;
-	u16	res7;
-	u16	mmlen;
-	u8	res8[3];
-	u8	mmcr7;
-	u32	mmrsp[4];
-	u8	res9[3];
-	u8	mmcmd0;
-	u32	mmcmd1;
-	u16	res10;
-	u16	mmcr16;
-	u8	res11[3];
-	u8	mmdat;
-#else
-	u8	mmcon;
-	u8	res1[3];
-	u8	mmcrr;
-	u8	res2[3];
-	u8	mmfcon;
-	u8	res3[3];
-	u8	mmsta;
-	u8	res4[3];
-	u16	mmfsta;
-	u16	res5;
-	u8	mmpre;
-	u8	res6[3];
-	u16	mmlen;
-	u16	res7;
-	u8	mmcr7;
-	u8	res8[3];
-	u32	mmrsp[4];
-	u8	mmcmd0;
-	u8	res9[3];
-	u32	mmcmd1;
-	u16	mmcr16;
-	u16	res10;
-	u8	mmdat;
-	u8	res11[3];
-#endif
-};
-
-
-/* SD INTERFACE (see S3C2410 manual chapter 19) */
-struct s3c2410_sdi {
-	u32	sdicon;
-	u32	sdipre;
-	u32	sdicarg;
-	u32	sdiccon;
-	u32	sdicsta;
-	u32	sdirsp0;
-	u32	sdirsp1;
-	u32	sdirsp2;
-	u32	sdirsp3;
-	u32	sdidtimer;
-	u32	sdibsize;
-	u32	sdidcon;
-	u32	sdidcnt;
-	u32	sdidsta;
-	u32	sdifsta;
-#ifdef __BIG_ENDIAN
-	u8	res[3];
-	u8	sdidat;
-#else
-	u8	sdidat;
-	u8	res[3];
-#endif
-	u32	sdiimsk;
-};
-
-#endif /*__S3C24X0_H__*/
diff --git a/arch/arm/include/asm/arch-s3c24x0/s3c24x0_cpu.h b/arch/arm/include/asm/arch-s3c24x0/s3c24x0_cpu.h
deleted file mode 100644
index 54184c4..0000000
--- a/arch/arm/include/asm/arch-s3c24x0/s3c24x0_cpu.h
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- * (C) Copyright 2009
- * Kevin Morfitt, Fearnside Systems Ltd, <kevin.morfitt@fearnside-systems.co.uk>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifdef CONFIG_S3C2400
-	#include <asm/arch/s3c2400.h>
-#elif defined CONFIG_S3C2410
-	#include <asm/arch/s3c2410.h>
-#elif defined CONFIG_S3C2440
-	#include <asm/arch/s3c2440.h>
-#else
-	#error Please define the s3c24x0 cpu type
-#endif
diff --git a/arch/arm/include/asm/arch-s3c44b0/hardware.h b/arch/arm/include/asm/arch-s3c44b0/hardware.h
deleted file mode 100644
index 146e265..0000000
--- a/arch/arm/include/asm/arch-s3c44b0/hardware.h
+++ /dev/null
@@ -1,281 +0,0 @@
-/********************************************************/
-/*							*/
-/* Samsung S3C44B0					*/
-/* tpu <tapu@371.net>					*/
-/*							*/
-/********************************************************/
-#ifndef __ASM_ARCH_HARDWARE_H
-#define __ASM_ARCH_HARDWARE_H
-
-#define REGBASE		0x01c00000
-#define REGL(addr)	(*(volatile unsigned int *)(REGBASE+addr))
-#define REGW(addr)	(*(volatile unsigned short *)(REGBASE+addr))
-#define REGB(addr)	(*(volatile unsigned char *)(REGBASE+addr))
-
-
-/*****************************/
-/* CPU Wrapper Registers     */
-/*****************************/
-
-#define SYSCFG		REGL(0x000000)
-#define NCACHBE0	REGL(0x000004)
-#define NCACHBE1	REGL(0x000008)
-#define SBUSCON		REGL(0x040000)
-
-/************************************/
-/* Memory Controller Registers      */
-/************************************/
-
-#define BWSCON		REGL(0x080000)
-#define BANKCON0	REGL(0x080004)
-#define BANKCON1	REGL(0x080008)
-#define BANKCON2	REGL(0x08000c)
-#define BANKCON3	REGL(0x080010)
-#define BANKCON4	REGL(0x080014)
-#define BANKCON5	REGL(0x080018)
-#define BANKCON6	REGL(0x08001c)
-#define BANKCON7	REGL(0x080020)
-#define REFRESH		REGL(0x080024)
-#define BANKSIZE	REGL(0x080028)
-#define MRSRB6		REGL(0x08002c)
-#define MRSRB7		REGL(0x080030)
-
-/*********************/
-/* UART Registers    */
-/*********************/
-
-#define ULCON0		REGL(0x100000)
-#define ULCON1		REGL(0x104000)
-#define UCON0		REGL(0x100004)
-#define UCON1		REGL(0x104004)
-#define UFCON0		REGL(0x100008)
-#define UFCON1		REGL(0x104008)
-#define UMCON0		REGL(0x10000c)
-#define UMCON1		REGL(0x10400c)
-#define UTRSTAT0	REGL(0x100010)
-#define UTRSTAT1	REGL(0x104010)
-#define UERSTAT0	REGL(0x100014)
-#define UERSTAT1	REGL(0x104014)
-#define UFSTAT0		REGL(0x100018)
-#define UFSTAT1		REGL(0x104018)
-#define UMSTAT0		REGL(0x10001c)
-#define UMSTAT1		REGL(0x10401c)
-#define UTXH0		REGB(0x100020)
-#define UTXH1		REGB(0x104020)
-#define URXH0		REGB(0x100024)
-#define URXH1		REGB(0x104024)
-#define UBRDIV0		REGL(0x100028)
-#define UBRDIV1		REGL(0x104028)
-
-/*******************/
-/* SIO Registers   */
-/*******************/
-
-#define SIOCON		REGL(0x114000)
-#define SIODAT		REGL(0x114004)
-#define SBRDR		REGL(0x114008)
-#define ITVCNT		REGL(0x11400c)
-#define DCNTZ		REGL(0x114010)
-
-/********************/
-/* IIS Registers    */
-/********************/
-
-#define IISCON		REGL(0x118000)
-#define IISMOD		REGL(0x118004)
-#define IISPSR		REGL(0x118008)
-#define IISFIFCON	REGL(0x11800c)
-#define IISFIF		REGW(0x118010)
-
-/**************************/
-/* I/O Ports Registers    */
-/**************************/
-
-#define PCONA		REGL(0x120000)
-#define PDATA		REGL(0x120004)
-#define PCONB		REGL(0x120008)
-#define PDATB		REGL(0x12000c)
-#define PCONC		REGL(0x120010)
-#define PDATC		REGL(0x120014)
-#define PUPC		REGL(0x120018)
-#define PCOND		REGL(0x12001c)
-#define PDATD		REGL(0x120020)
-#define PUPD		REGL(0x120024)
-#define PCONE		REGL(0x120028)
-#define PDATE		REGL(0x12002c)
-#define PUPE		REGL(0x120030)
-#define PCONF		REGL(0x120034)
-#define PDATF		REGL(0x120038)
-#define PUPF		REGL(0x12003c)
-#define PCONG		REGL(0x120040)
-#define PDATG		REGL(0x120044)
-#define PUPG		REGL(0x120048)
-#define SPUCR		REGL(0x12004c)
-#define EXTINT		REGL(0x120050)
-#define EXTINTPND	REGL(0x120054)
-
-/*********************************/
-/* WatchDog Timers Registers     */
-/*********************************/
-
-#define WTCON		REGL(0x130000)
-#define WTDAT		REGL(0x130004)
-#define WTCNT		REGL(0x130008)
-
-/*********************************/
-/* A/D Converter Registers       */
-/*********************************/
-
-#define ADCCON		REGL(0x140000)
-#define ADCPSR		REGL(0x140004)
-#define ADCDAT		REGL(0x140008)
-
-/***************************/
-/* PWM Timer Registers     */
-/***************************/
-
-#define TCFG0		REGL(0x150000)
-#define TCFG1		REGL(0x150004)
-#define TCON		REGL(0x150008)
-#define TCNTB0		REGL(0x15000c)
-#define TCMPB0		REGL(0x150010)
-#define TCNTO0		REGL(0x150014)
-#define TCNTB1		REGL(0x150018)
-#define TCMPB1		REGL(0x15001c)
-#define TCNTO1		REGL(0x150020)
-#define TCNTB2		REGL(0x150024)
-#define TCMPB2		REGL(0x150028)
-#define TCNTO2		REGL(0x15002c)
-#define TCNTB3		REGL(0x150030)
-#define TCMPB3		REGL(0x150034)
-#define TCNTO3		REGL(0x150038)
-#define TCNTB4		REGL(0x15003c)
-#define TCMPB4		REGL(0x150040)
-#define TCNTO4		REGL(0x150044)
-#define TCNTB5		REGL(0x150048)
-#define TCNTO5		REGL(0x15004c)
-
-/*********************/
-/* IIC Registers     */
-/*********************/
-
-#define IICCON		REGL(0x160000)
-#define IICSTAT		REGL(0x160004)
-#define IICADD		REGL(0x160008)
-#define IICDS		REGL(0x16000c)
-
-/*********************/
-/* RTC Registers     */
-/*********************/
-
-#define RTCCON		REGB(0x170040)
-#define RTCALM		REGB(0x170050)
-#define ALMSEC		REGB(0x170054)
-#define ALMMIN		REGB(0x170058)
-#define ALMHOUR		REGB(0x17005c)
-#define ALMDAY		REGB(0x170060)
-#define ALMMON		REGB(0x170064)
-#define ALMYEAR		REGB(0x170068)
-#define RTCRST		REGB(0x17006c)
-#define BCDSEC		REGB(0x170070)
-#define BCDMIN		REGB(0x170074)
-#define BCDHOUR		REGB(0x170078)
-#define BCDDAY		REGB(0x17007c)
-#define BCDDATE		REGB(0x170080)
-#define BCDMON		REGB(0x170084)
-#define BCDYEAR		REGB(0x170088)
-#define TICINT		REGB(0x17008c)
-
-/*********************************/
-/* Clock & Power Registers       */
-/*********************************/
-
-#define PLLCON		REGL(0x180000)
-#define CLKCON		REGL(0x180004)
-#define CLKSLOW		REGL(0x180008)
-#define LOCKTIME	REGL(0x18000c)
-
-/**************************************/
-/* Interrupt Controller Registers     */
-/**************************************/
-
-#define INTCON		REGL(0x200000)
-#define INTPND		REGL(0x200004)
-#define INTMOD		REGL(0x200008)
-#define INTMSK		REGL(0x20000c)
-#define I_PSLV		REGL(0x200010)
-#define I_PMST		REGL(0x200014)
-#define I_CSLV		REGL(0x200018)
-#define I_CMST		REGL(0x20001c)
-#define I_ISPR		REGL(0x200020)
-#define I_ISPC		REGL(0x200024)
-#define F_ISPR		REGL(0x200038)
-#define F_ISPC		REGL(0x20003c)
-
-/********************************/
-/* LCD Controller Registers     */
-/********************************/
-
-#define LCDCON1		REGL(0x300000)
-#define LCDCON2		REGL(0x300004)
-#define LCDSADDR1	REGL(0x300008)
-#define LCDSADDR2	REGL(0x30000c)
-#define LCDSADDR3	REGL(0x300010)
-#define REDLUT		REGL(0x300014)
-#define GREENLUT	REGL(0x300018)
-#define BLUELUT		REGL(0x30001c)
-#define DP1_2		REGL(0x300020)
-#define DP4_7		REGL(0x300024)
-#define DP3_5		REGL(0x300028)
-#define DP2_3		REGL(0x30002c)
-#define DP5_7		REGL(0x300030)
-#define DP3_4		REGL(0x300034)
-#define DP4_5		REGL(0x300038)
-#define DP6_7		REGL(0x30003c)
-#define LCDCON3		REGL(0x300040)
-#define DITHMODE	REGL(0x300044)
-
-/*********************/
-/* DMA Registers     */
-/*********************/
-
-#define ZDCON0		REGL(0x280000)
-#define ZDISRC0		REGL(0x280004)
-#define ZDIDES0		REGL(0x280008)
-#define ZDICNT0		REGL(0x28000c)
-#define ZDCSRC0		REGL(0x280010)
-#define ZDCDES0		REGL(0x280014)
-#define ZDCCNT0		REGL(0x280018)
-
-#define ZDCON1		REGL(0x280020)
-#define ZDISRC1		REGL(0x280024)
-#define ZDIDES1		REGL(0x280028)
-#define ZDICNT1		REGL(0x28002c)
-#define ZDCSRC1		REGL(0x280030)
-#define ZDCDES1		REGL(0x280034)
-#define ZDCCNT1		REGL(0x280038)
-
-#define BDCON0		REGL(0x380000)
-#define BDISRC0		REGL(0x380004)
-#define BDIDES0		REGL(0x380008)
-#define BDICNT0		REGL(0x38000c)
-#define BDCSRC0		REGL(0x380010)
-#define BDCDES0		REGL(0x380014)
-#define BDCCNT0		REGL(0x380018)
-
-#define BDCON1		REGL(0x380020)
-#define BDISRC1		REGL(0x380024)
-#define BDIDES1		REGL(0x380028)
-#define BDICNT1		REGL(0x38002c)
-#define BDCSRC1		REGL(0x380030)
-#define BDCDES1		REGL(0x380034)
-#define BDCCNT1		REGL(0x380038)
-
-
-#define CLEAR_PEND_INT(n)       I_ISPC = (1<<(n))
-#define INT_ENABLE(n)		INTMSK &= ~(1<<(n))
-#define INT_DISABLE(n)		INTMSK |= (1<<(n))
-
-#define HARD_RESET_NOW()
-
-#endif /* __ASM_ARCH_HARDWARE_H */
diff --git a/arch/arm/include/asm/arch-s3c4510b/hardware.h b/arch/arm/include/asm/arch-s3c4510b/hardware.h
deleted file mode 100644
index 6b8c8ed..0000000
--- a/arch/arm/include/asm/arch-s3c4510b/hardware.h
+++ /dev/null
@@ -1,272 +0,0 @@
-#ifndef __HW_S3C4510_H
-#define __HW_S3C4510_H
-
-/*
- * Copyright (c) 2004	Cucy Systems (http://www.cucy.com)
- * Curt Brune <curt@cucy.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- * Description:   Samsung S3C4510B register layout
- */
-
-/*------------------------------------------------------------------------
- *	  ASIC Address Definition
- *----------------------------------------------------------------------*/
-
-/* L1 8KB on chip SRAM base address */
-#define SRAM_BASE       (0x03fe0000)
-
-/* Special Register Start Address After System Reset */
-#define REG_BASE	(0x03ff0000)
-#define SPSTR		(REG_BASE)
-
-/* *********************** */
-/* System Manager Register */
-/* *********************** */
-#define REG_SYSCFG	(REG_BASE+0x0000)
-
-#define REG_CLKCON      (REG_BASE+0x3000)
-#define REG_EXTACON0	(REG_BASE+0x3008)
-#define REG_EXTACON1	(REG_BASE+0x300c)
-#define REG_EXTDBWTH	(REG_BASE+0x3010)
-#define REG_ROMCON0	(REG_BASE+0x3014)
-#define REG_ROMCON1	(REG_BASE+0x3018)
-#define REG_ROMCON2	(REG_BASE+0x301c)
-#define REG_ROMCON3	(REG_BASE+0x3020)
-#define REG_ROMCON4	(REG_BASE+0x3024)
-#define REG_ROMCON5	(REG_BASE+0x3028)
-#define REG_DRAMCON0	(REG_BASE+0x302c)
-#define REG_DRAMCON1	(REG_BASE+0x3030)
-#define REG_DRAMCON2	(REG_BASE+0x3034)
-#define REG_DRAMCON3	(REG_BASE+0x3038)
-#define REG_REFEXTCON	(REG_BASE+0x303c)
-
-/* *********************** */
-/* Ethernet BDMA Register  */
-/* *********************** */
-#define REG_BDMATXCON	(REG_BASE+0x9000)
-#define REG_BDMARXCON	(REG_BASE+0x9004)
-#define REG_BDMATXPTR	(REG_BASE+0x9008)
-#define REG_BDMARXPTR	(REG_BASE+0x900c)
-#define REG_BDMARXLSZ	(REG_BASE+0x9010)
-#define REG_BDMASTAT	(REG_BASE+0x9014)
-
-/* Content Address Memory */
-#define REG_CAM_BASE	(REG_BASE+0x9100)
-
-#define REG_BDMATXBUF	(REG_BASE+0x9200)
-#define REG_BDMARXBUF	(REG_BASE+0x9800)
-
-/* *********************** */
-/* Ethernet MAC Register   */
-/* *********************** */
-#define REG_MACCON	(REG_BASE+0xa000)
-#define REG_CAMCON	(REG_BASE+0xa004)
-#define REG_MACTXCON	(REG_BASE+0xa008)
-#define REG_MACTXSTAT	(REG_BASE+0xa00c)
-#define REG_MACRXCON	(REG_BASE+0xa010)
-#define REG_MACRXSTAT	(REG_BASE+0xa014)
-#define REG_STADATA	(REG_BASE+0xa018)
-#define REG_STACON	(REG_BASE+0xa01c)
-#define REG_CAMEN	(REG_BASE+0xa028)
-#define REG_EMISSCNT	(REG_BASE+0xa03c)
-#define REG_EPZCNT	(REG_BASE+0xa040)
-#define REG_ERMPZCNT	(REG_BASE+0xa044)
-#define REG_ETXSTAT	(REG_BASE+0x9040)
-#define REG_MACRXDESTR	(REG_BASE+0xa064)
-#define REG_MACRXSTATEM	(REG_BASE+0xa090)
-#define REG_MACRXFIFO	(REG_BASE+0xa200)
-
-/********************/
-/* I2C Bus Register */
-/********************/
-#define REG_I2C_CON	(REG_BASE+0xf000)
-#define REG_I2C_BUF	(REG_BASE+0xf004)
-#define REG_I2C_PS	(REG_BASE+0xf008)
-#define REG_I2C_COUNT	(REG_BASE+0xf00c)
-
-/********************/
-/*    GDMA 0        */
-/********************/
-#define REG_GDMACON0	(REG_BASE+0xb000)
-#define REG_GDMA0_RUN_ENABLE (REG_BASE+0xb020)
-#define REG_GDMASRC0	(REG_BASE+0xb004)
-#define REG_GDMADST0	(REG_BASE+0xb008)
-#define REG_GDMACNT0	(REG_BASE+0xb00c)
-
-/********************/
-/*    GDMA 1        */
-/********************/
-#define REG_GDMACON1	(REG_BASE+0xc000)
-#define REG_GDMA1_RUN_ENABLE (REG_BASE+0xc020)
-#define REG_GDMASRC1	(REG_BASE+0xc004)
-#define REG_GDMADST1	(REG_BASE+0xc008)
-#define REG_GDMACNT1	(REG_BASE+0xc00c)
-
-/********************/
-/*      UART 0      */
-/********************/
-#define UART0_BASE       (REG_BASE+0xd000)
-#define REG_UART0_LCON   (REG_BASE+0xd000)
-#define REG_UART0_CTRL   (REG_BASE+0xd004)
-#define REG_UART0_STAT   (REG_BASE+0xd008)
-#define REG_UART0_TXB    (REG_BASE+0xd00c)
-#define REG_UART0_RXB    (REG_BASE+0xd010)
-#define REG_UART0_BAUD_DIV    (REG_BASE+0xd014)
-#define REG_UART0_BAUD_CNT    (REG_BASE+0xd018)
-#define REG_UART0_BAUD_CLK    (REG_BASE+0xd01C)
-
-/********************/
-/*     UART 1       */
-/********************/
-#define UART1_BASE       (REG_BASE+0xe000)
-#define REG_UART1_LCON   (REG_BASE+0xe000)
-#define REG_UART1_CTRL   (REG_BASE+0xe004)
-#define REG_UART1_STAT   (REG_BASE+0xe008)
-#define REG_UART1_TXB    (REG_BASE+0xe00c)
-#define REG_UART1_RXB    (REG_BASE+0xe010)
-#define REG_UART1_BAUD_DIV    (REG_BASE+0xe014)
-#define REG_UART1_BAUD_CNT    (REG_BASE+0xe018)
-#define REG_UART1_BAUD_CLK    (REG_BASE+0xe01C)
-
-/********************/
-/*  Timer Register  */
-/********************/
-#define REG_TMOD	(REG_BASE+0x6000)
-#define REG_TDATA0	(REG_BASE+0x6004)
-#define REG_TDATA1	(REG_BASE+0x6008)
-#define REG_TCNT0	(REG_BASE+0x600c)
-#define REG_TCNT1	(REG_BASE+0x6010)
-
-/**********************/
-/* I/O Port Interface */
-/**********************/
-#define REG_IOPMODE	(REG_BASE+0x5000)
-#define REG_IOPCON	(REG_BASE+0x5004)
-#define REG_IOPDATA	(REG_BASE+0x5008)
-
-/*********************************/
-/* Interrupt Controller Register */
-/*********************************/
-#define REG_INTMODE     (REG_BASE+0x4000)
-#define REG_INTPEND     (REG_BASE+0x4004)
-#define REG_INTMASK     (REG_BASE+0x4008)
-
-#define REG_INTPRI0     (REG_BASE+0x400c)
-#define REG_INTPRI1	(REG_BASE+0x4010)
-#define REG_INTPRI2	(REG_BASE+0x4014)
-#define REG_INTPRI3	(REG_BASE+0x4018)
-#define REG_INTPRI4	(REG_BASE+0x401c)
-#define REG_INTPRI5	(REG_BASE+0x4020)
-#define REG_INTOFFSET	(REG_BASE+0x4024)
-#define REG_INTPNDPRI	(REG_BASE+0x4028)
-#define REG_INTPNDTST	(REG_BASE+0x402C)
-
-/*********************************/
-/* CACHE CONTROL MASKS           */
-/*********************************/
-#define CACHE_STALL      (0x00000001)
-#define CACHE_ENABLE     (0x00000002)
-#define CACHE_WRITE_BUFF (0x00000004)
-#define CACHE_MODE       (0x00000030)
-#define CACHE_MODE_00    (0x00000000)
-#define CACHE_MODE_01    (0x00000010)
-#define CACHE_MODE_10    (0x00000020)
-
-/*********************************/
-/* CACHE RAM BASE ADDRESSES      */
-/*********************************/
-#define CACHE_SET0_RAM   (0x10000000)
-#define CACHE_SET1_RAM   (0x10800000)
-#define CACHE_TAG_RAM    (0x11000000)
-
-/*********************************/
-/* CACHE_DISABLE MASK            */
-/*********************************/
-#define CACHE_DISABLE_MASK (0x04000000)
-
-#define GET_REG(reg)       (*((volatile u32 *)(reg)))
-#define PUT_REG(reg, val)  (*((volatile u32 *)(reg)) = ((u32)(val)))
-#define SET_REG(reg, mask) (PUT_REG((reg), GET_REG((reg)) |  mask))
-#define CLR_REG(reg, mask) (PUT_REG((reg), GET_REG((reg)) & ~mask))
-#define PUT_U16(reg, val)  (*((volatile u16 *)(reg)) = ((u16)(val)))
-#define PUT__U8(reg, val)  (*((volatile u8  *)(reg)) = (( u8)((val)&0xFF)))
-#define GET__U8(reg)       (*((volatile u8  *)(reg)))
-
-#define PUT_LED(val)       (PUT_REG(REG_IOPDATA, (~val)&0xFF))
-#define GET_LED()          ((~GET_REG( REG_IOPDATA)) & 0xFF)
-#define SET_LED(val)       { u32 led = GET_LED(); led |= 1 << (val);  PUT_LED( led); }
-#define CLR_LED(val)       { u32 led = GET_LED(); led &= ~(1 << (val));  PUT_LED( led); }
-
-/***********************************/
-/* CLOCK CONSTANTS -- 50 MHz Clock */
-/***********************************/
-
-#define CLK_FREQ_MHZ       (50)
-#define t_data_us(t)       ((t)*CLK_FREQ_MHZ-1)   /* t is time tick,unit[us] */
-#define t_data_ms(t)       (t_data_us((t)*1000))  /* t is time tick,unit[ms] */
-
-/*********************************************************/
-/*	       TIMER MODE REGISTER                       */
-/*********************************************************/
-#define  TM0_RUN      0x01  /* Timer 0 enable */
-#define  TM0_TOGGLE   0x02  /* 0, interval mode */
-#define  TM0_OUT_1    0x04  /* Timer 0 Initial TOUT0 value */
-#define  TM1_RUN      0x08  /* Timer 1 enable */
-#define  TM1_TOGGLE   0x10  /* 0, interval mode */
-#define  TM1_OUT_1    0x20  /* Timer 0 Initial TOUT0 value */
-
-
-/*********************************/
-/* INTERRUPT SOURCES             */
-/*********************************/
-#define INT_EXTINT0	0
-#define INT_EXTINT1	1
-#define INT_EXTINT2	2
-#define INT_EXTINT3	3
-#define INT_UARTTX0	4
-#define INT_UARTRX0	5
-#define INT_UARTTX1	6
-#define INT_UARTRX1	7
-#define INT_GDMA0	8
-#define INT_GDMA1	9
-#define INT_TIMER0	10
-#define INT_TIMER1	11
-#define INT_HDLCTXA	12
-#define INT_HDLCRXA	13
-#define INT_HDLCTXB	14
-#define INT_HDLCRXB	15
-#define INT_BDMATX	16
-#define INT_BDMARX	17
-#define INT_MACTX	18
-#define INT_MACRX	19
-#define INT_IIC		20
-#define INT_GLOBAL	21
-#define N_IRQS         (21)
-
-#ifndef __ASSEMBLER__
-struct _irq_handler {
-	void                *m_data;
-	void (*m_func)( void *data);
-};
-
-#endif
-
-#endif /* __S3C4510_h */
diff --git a/arch/arm/include/asm/arch-s3c64xx/hardware.h b/arch/arm/include/asm/arch-s3c64xx/hardware.h
deleted file mode 100644
index 84d24c9..0000000
--- a/arch/arm/include/asm/arch-s3c64xx/hardware.h
+++ /dev/null
@@ -1,63 +0,0 @@
-/*
- * Originates from Samsung's u-boot 1.1.6 port to S3C6400 / SMDK6400
- *
- * (C) Copyright 2008
- * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef _ARCH_HARDWARE_H_
-#define _ARCH_HARDWARE_H_
-
-#include <asm/sizes.h>
-
-#ifndef __ASSEMBLY__
-#define UData(Data)	((unsigned long) (Data))
-
-#define __REG(x)	(*(vu_long *)(x))
-#define __REGl(x)	(*(vu_long *)(x))
-#define __REGw(x)	(*(vu_short *)(x))
-#define __REGb(x)	(*(vu_char *)(x))
-#define __REG2(x, y)	(*(vu_long *)((x) + (y)))
-#else
-#define UData(Data)	(Data)
-
-#define __REG(x)	(x)
-#define __REGl(x)	(x)
-#define __REGw(x)	(x)
-#define __REGb(x)	(x)
-#define __REG2(x, y)	((x) + (y))
-#endif
-
-#define Fld(Size, Shft)	(((Size) << 16) + (Shft))
-
-#define FSize(Field)	((Field) >> 16)
-#define FShft(Field)	((Field) & 0x0000FFFF)
-#define FMsk(Field)	(((UData (1) << FSize (Field)) - 1) << FShft (Field))
-#define FAlnMsk(Field)	((UData (1) << FSize (Field)) - 1)
-#define F1stBit(Field)	(UData (1) << FShft (Field))
-
-#define FClrBit(Data, Bit)	(Data = (Data & ~(Bit)))
-#define FClrFld(Data, Field)	(Data = (Data & ~FMsk(Field)))
-
-#define FInsrt(Value, Field) \
-			(UData (Value) << FShft (Field))
-
-#define FExtr(Data, Field) \
-			((UData (Data) >> FShft (Field)) & FAlnMsk (Field))
-
-#endif /* _ARCH_HARDWARE_H_ */
diff --git a/arch/arm/include/asm/arch-s3c64xx/s3c6400.h b/arch/arm/include/asm/arch-s3c64xx/s3c6400.h
deleted file mode 100644
index 10b3324..0000000
--- a/arch/arm/include/asm/arch-s3c64xx/s3c6400.h
+++ /dev/null
@@ -1,895 +0,0 @@
-/*
- * (C) Copyright 2007
- * Byungjae Lee, Samsung Erectronics, bjlee@samsung.com.
- *      - only support for S3C6400
- *
- * (C) Copyright 2008
- * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/************************************************
- * NAME	    : s3c6400.h
- *
- * Based on S3C6400 User's manual Rev 0.0
- ************************************************/
-
-#ifndef __S3C6400_H__
-#define __S3C6400_H__
-
-#define S3C64XX_UART_CHANNELS	3
-#define S3C64XX_SPI_CHANNELS	2
-
-#include <asm/hardware.h>
-
-#define ELFIN_CLOCK_POWER_BASE	0x7e00f000
-
-/* Clock & Power Controller for mDirac3*/
-#define APLL_LOCK_OFFSET	0x00
-#define MPLL_LOCK_OFFSET	0x04
-#define EPLL_LOCK_OFFSET	0x08
-#define APLL_CON_OFFSET		0x0C
-#define MPLL_CON_OFFSET		0x10
-#define EPLL_CON0_OFFSET	0x14
-#define EPLL_CON1_OFFSET	0x18
-#define CLK_SRC_OFFSET		0x1C
-#define CLK_DIV0_OFFSET		0x20
-#define CLK_DIV1_OFFSET		0x24
-#define CLK_DIV2_OFFSET		0x28
-#define CLK_OUT_OFFSET		0x2C
-#define HCLK_GATE_OFFSET	0x30
-#define PCLK_GATE_OFFSET	0x34
-#define SCLK_GATE_OFFSET	0x38
-#define AHB_CON0_OFFSET		0x100
-#define AHB_CON1_OFFSET		0x104
-#define AHB_CON2_OFFSET		0x108
-#define SELECT_DMA_OFFSET	0x110
-#define SW_RST_OFFSET		0x114
-#define SYS_ID_OFFSET		0x118
-#define MEM_SYS_CFG_OFFSET	0x120
-#define QOS_OVERRIDE0_OFFSET	0x124
-#define QOS_OVERRIDE1_OFFSET	0x128
-#define MEM_CFG_STAT_OFFSET	0x12C
-#define PWR_CFG_OFFSET		0x804
-#define EINT_MASK_OFFSET	0x808
-#define NOR_CFG_OFFSET		0x810
-#define STOP_CFG_OFFSET		0x814
-#define SLEEP_CFG_OFFSET	0x818
-#define OSC_FREQ_OFFSET		0x820
-#define OSC_STABLE_OFFSET	0x824
-#define PWR_STABLE_OFFSET	0x828
-#define FPC_STABLE_OFFSET	0x82C
-#define MTC_STABLE_OFFSET	0x830
-#define OTHERS_OFFSET		0x900
-#define RST_STAT_OFFSET		0x904
-#define WAKEUP_STAT_OFFSET	0x908
-#define BLK_PWR_STAT_OFFSET	0x90C
-#define INF_REG0_OFFSET		0xA00
-#define INF_REG1_OFFSET		0xA04
-#define INF_REG2_OFFSET		0xA08
-#define INF_REG3_OFFSET		0xA0C
-#define INF_REG4_OFFSET		0xA10
-#define INF_REG5_OFFSET		0xA14
-#define INF_REG6_OFFSET		0xA18
-#define INF_REG7_OFFSET		0xA1C
-
-#define OSC_CNT_VAL_OFFSET	0x824
-#define PWR_CNT_VAL_OFFSET	0x828
-#define FPC_CNT_VAL_OFFSET	0x82C
-#define MTC_CNT_VAL_OFFSET	0x830
-
-#define APLL_LOCK_REG		__REG(ELFIN_CLOCK_POWER_BASE + APLL_LOCK_OFFSET)
-#define MPLL_LOCK_REG		__REG(ELFIN_CLOCK_POWER_BASE + MPLL_LOCK_OFFSET)
-#define EPLL_LOCK_REG		__REG(ELFIN_CLOCK_POWER_BASE + EPLL_LOCK_OFFSET)
-#define APLL_CON_REG		__REG(ELFIN_CLOCK_POWER_BASE + APLL_CON_OFFSET)
-#define MPLL_CON_REG		__REG(ELFIN_CLOCK_POWER_BASE + MPLL_CON_OFFSET)
-#define EPLL_CON0_REG		__REG(ELFIN_CLOCK_POWER_BASE + EPLL_CON0_OFFSET)
-#define EPLL_CON1_REG		__REG(ELFIN_CLOCK_POWER_BASE + EPLL_CON1_OFFSET)
-#define CLK_SRC_REG		__REG(ELFIN_CLOCK_POWER_BASE + CLK_SRC_OFFSET)
-#define CLK_DIV0_REG		__REG(ELFIN_CLOCK_POWER_BASE + CLK_DIV0_OFFSET)
-#define CLK_DIV1_REG		__REG(ELFIN_CLOCK_POWER_BASE + CLK_DIV1_OFFSET)
-#define CLK_DIV2_REG		__REG(ELFIN_CLOCK_POWER_BASE + CLK_DIV2_OFFSET)
-#define CLK_OUT_REG		__REG(ELFIN_CLOCK_POWER_BASE + CLK_OUT_OFFSET)
-#define HCLK_GATE_REG		__REG(ELFIN_CLOCK_POWER_BASE + HCLK_GATE_OFFSET)
-#define PCLK_GATE_REG		__REG(ELFIN_CLOCK_POWER_BASE + PCLK_GATE_OFFSET)
-#define SCLK_GATE_REG		__REG(ELFIN_CLOCK_POWER_BASE + SCLK_GATE_OFFSET)
-#define AHB_CON0_REG		__REG(ELFIN_CLOCK_POWER_BASE + AHB_CON0_OFFSET)
-#define AHB_CON1_REG		__REG(ELFIN_CLOCK_POWER_BASE + AHB_CON1_OFFSET)
-#define AHB_CON2_REG		__REG(ELFIN_CLOCK_POWER_BASE + AHB_CON2_OFFSET)
-#define SELECT_DMA_REG		__REG(ELFIN_CLOCK_POWER_BASE + \
-				      SELECT_DMA_OFFSET)
-#define SW_RST_REG		__REG(ELFIN_CLOCK_POWER_BASE + SW_RST_OFFSET)
-#define SYS_ID_REG		__REG(ELFIN_CLOCK_POWER_BASE + SYS_ID_OFFSET)
-#define MEM_SYS_CFG_REG		__REG(ELFIN_CLOCK_POWER_BASE + \
-				      MEM_SYS_CFG_OFFSET)
-#define QOS_OVERRIDE0_REG	__REG(ELFIN_CLOCK_POWER_BASE + \
-				      QOS_OVERRIDE0_OFFSET)
-#define QOS_OVERRIDE1_REG	__REG(ELFIN_CLOCK_POWER_BASE + \
-				      QOS_OVERRIDE1_OFFSET)
-#define MEM_CFG_STAT_REG	__REG(ELFIN_CLOCK_POWER_BASE + \
-				      MEM_CFG_STAT_OFFSET)
-#define PWR_CFG_REG		__REG(ELFIN_CLOCK_POWER_BASE + PWR_CFG_OFFSET)
-#define EINT_MASK_REG		__REG(ELFIN_CLOCK_POWER_BASE + EINT_MASK_OFFSET)
-#define NOR_CFG_REG		__REG(ELFIN_CLOCK_POWER_BASE + NOR_CFG_OFFSET)
-#define STOP_CFG_REG		__REG(ELFIN_CLOCK_POWER_BASE + STOP_CFG_OFFSET)
-#define SLEEP_CFG_REG		__REG(ELFIN_CLOCK_POWER_BASE + SLEEP_CFG_OFFSET)
-#define OSC_FREQ_REG		__REG(ELFIN_CLOCK_POWER_BASE + OSC_FREQ_OFFSET)
-#define OSC_CNT_VAL_REG		__REG(ELFIN_CLOCK_POWER_BASE + \
-				      OSC_CNT_VAL_OFFSET)
-#define PWR_CNT_VAL_REG		__REG(ELFIN_CLOCK_POWER_BASE + \
-				      PWR_CNT_VAL_OFFSET)
-#define FPC_CNT_VAL_REG		__REG(ELFIN_CLOCK_POWER_BASE + \
-				      FPC_CNT_VAL_OFFSET)
-#define MTC_CNT_VAL_REG		__REG(ELFIN_CLOCK_POWER_BASE + \
-				      MTC_CNT_VAL_OFFSET)
-#define OTHERS_REG		__REG(ELFIN_CLOCK_POWER_BASE + OTHERS_OFFSET)
-#define RST_STAT_REG		__REG(ELFIN_CLOCK_POWER_BASE + RST_STAT_OFFSET)
-#define WAKEUP_STAT_REG		__REG(ELFIN_CLOCK_POWER_BASE + \
-				      WAKEUP_STAT_OFFSET)
-#define BLK_PWR_STAT_REG	__REG(ELFIN_CLOCK_POWER_BASE + \
-				      BLK_PWR_STAT_OFFSET)
-#define INF_REG0_REG		__REG(ELFIN_CLOCK_POWER_BASE + INF_REG0_OFFSET)
-#define INF_REG1_REG		__REG(ELFIN_CLOCK_POWER_BASE + INF_REG1_OFFSET)
-#define INF_REG2_REG		__REG(ELFIN_CLOCK_POWER_BASE + INF_REG2_OFFSET)
-#define INF_REG3_REG		__REG(ELFIN_CLOCK_POWER_BASE + INF_REG3_OFFSET)
-#define INF_REG4_REG		__REG(ELFIN_CLOCK_POWER_BASE + INF_REG4_OFFSET)
-#define INF_REG5_REG		__REG(ELFIN_CLOCK_POWER_BASE + INF_REG5_OFFSET)
-#define INF_REG6_REG		__REG(ELFIN_CLOCK_POWER_BASE + INF_REG6_OFFSET)
-#define INF_REG7_REG		__REG(ELFIN_CLOCK_POWER_BASE + INF_REG7_OFFSET)
-
-#define APLL_LOCK	(ELFIN_CLOCK_POWER_BASE + APLL_LOCK_OFFSET)
-#define MPLL_LOCK	(ELFIN_CLOCK_POWER_BASE + MPLL_LOCK_OFFSET)
-#define EPLL_LOCK	(ELFIN_CLOCK_POWER_BASE + EPLL_LOCK_OFFSET)
-#define APLL_CON	(ELFIN_CLOCK_POWER_BASE + APLL_CON_OFFSET)
-#define MPLL_CON	(ELFIN_CLOCK_POWER_BASE + MPLL_CON_OFFSET)
-#define EPLL_CON0	(ELFIN_CLOCK_POWER_BASE + EPLL_CON0_OFFSET)
-#define EPLL_CON1	(ELFIN_CLOCK_POWER_BASE + EPLL_CON1_OFFSET)
-#define CLK_SRC		(ELFIN_CLOCK_POWER_BASE + CLK_SRC_OFFSET)
-#define CLK_DIV0	(ELFIN_CLOCK_POWER_BASE + CLK_DIV0_OFFSET)
-#define CLK_DIV1	(ELFIN_CLOCK_POWER_BASE + CLK_DIV1_OFFSET)
-#define CLK_DIV2	(ELFIN_CLOCK_POWER_BASE + CLK_DIV2_OFFSET)
-#define CLK_OUT		(ELFIN_CLOCK_POWER_BASE + CLK_OUT_OFFSET)
-#define HCLK_GATE	(ELFIN_CLOCK_POWER_BASE + HCLK_GATE_OFFSET)
-#define PCLK_GATE	(ELFIN_CLOCK_POWER_BASE + PCLK_GATE_OFFSET)
-#define SCLK_GATE	(ELFIN_CLOCK_POWER_BASE + SCLK_GATE_OFFSET)
-#define AHB_CON0	(ELFIN_CLOCK_POWER_BASE + AHB_CON0_OFFSET)
-#define AHB_CON1	(ELFIN_CLOCK_POWER_BASE + AHB_CON1_OFFSET)
-#define AHB_CON2	(ELFIN_CLOCK_POWER_BASE + AHB_CON2_OFFSET)
-#define SELECT_DMA	(ELFIN_CLOCK_POWER_BASE + SELECT_DMA_OFFSET)
-#define SW_RST		(ELFIN_CLOCK_POWER_BASE + SW_RST_OFFSET)
-#define SYS_ID		(ELFIN_CLOCK_POWER_BASE + SYS_ID_OFFSET)
-#define MEM_SYS_CFG	(ELFIN_CLOCK_POWER_BASE + MEM_SYS_CFG_OFFSET)
-#define QOS_OVERRIDE0	(ELFIN_CLOCK_POWER_BASE + QOS_OVERRIDE0_OFFSET)
-#define QOS_OVERRIDE1	(ELFIN_CLOCK_POWER_BASE + QOS_OVERRIDE1_OFFSET)
-#define MEM_CFG_STAT	(ELFIN_CLOCK_POWER_BASE + MEM_CFG_STAT_OFFSET)
-#define PWR_CFG		(ELFIN_CLOCK_POWER_BASE + PWR_CFG_OFFSET)
-#define EINT_MASK	(ELFIN_CLOCK_POWER_BASE + EINT_MASK_OFFSET)
-#define NOR_CFG		(ELFIN_CLOCK_POWER_BASE + NOR_CFG_OFFSET)
-#define STOP_CFG	(ELFIN_CLOCK_POWER_BASE + STOP_CFG_OFFSET)
-#define SLEEP_CFG	(ELFIN_CLOCK_POWER_BASE + SLEEP_CFG_OFFSET)
-#define OSC_FREQ	(ELFIN_CLOCK_POWER_BASE + OSC_FREQ_OFFSET)
-#define OSC_CNT_VAL	(ELFIN_CLOCK_POWER_BASE + OSC_CNT_VAL_OFFSET)
-#define PWR_CNT_VAL	(ELFIN_CLOCK_POWER_BASE + PWR_CNT_VAL_OFFSET)
-#define FPC_CNT_VAL	(ELFIN_CLOCK_POWER_BASE + FPC_CNT_VAL_OFFSET)
-#define MTC_CNT_VAL	(ELFIN_CLOCK_POWER_BASE + MTC_CNT_VAL_OFFSET)
-#define OTHERS		(ELFIN_CLOCK_POWER_BASE + OTHERS_OFFSET)
-#define RST_STAT	(ELFIN_CLOCK_POWER_BASE + RST_STAT_OFFSET)
-#define WAKEUP_STAT	(ELFIN_CLOCK_POWER_BASE + WAKEUP_STAT_OFFSET)
-#define BLK_PWR_STAT	(ELFIN_CLOCK_POWER_BASE + BLK_PWR_STAT_OFFSET)
-#define INF_REG0	(ELFIN_CLOCK_POWER_BASE + INF_REG0_OFFSET)
-#define INF_REG1	(ELFIN_CLOCK_POWER_BASE + INF_REG1_OFFSET)
-#define INF_REG2	(ELFIN_CLOCK_POWER_BASE + INF_REG2_OFFSET)
-#define INF_REG3	(ELFIN_CLOCK_POWER_BASE + INF_REG3_OFFSET)
-#define INF_REG4	(ELFIN_CLOCK_POWER_BASE + INF_REG4_OFFSET)
-#define INF_REG5	(ELFIN_CLOCK_POWER_BASE + INF_REG5_OFFSET)
-#define INF_REG6	(ELFIN_CLOCK_POWER_BASE + INF_REG6_OFFSET)
-#define INF_REG7	(ELFIN_CLOCK_POWER_BASE + INF_REG7_OFFSET)
-
-
-/*
- * GPIO
- */
-#define ELFIN_GPIO_BASE		0x7f008000
-
-#define GPACON_OFFSET		0x00
-#define GPADAT_OFFSET		0x04
-#define GPAPUD_OFFSET		0x08
-#define GPACONSLP_OFFSET	0x0C
-#define GPAPUDSLP_OFFSET	0x10
-#define GPBCON_OFFSET		0x20
-#define GPBDAT_OFFSET		0x24
-#define GPBPUD_OFFSET		0x28
-#define GPBCONSLP_OFFSET	0x2C
-#define GPBPUDSLP_OFFSET	0x30
-#define GPCCON_OFFSET		0x40
-#define GPCDAT_OFFSET		0x44
-#define GPCPUD_OFFSET		0x48
-#define GPCCONSLP_OFFSET	0x4C
-#define GPCPUDSLP_OFFSET	0x50
-#define GPDCON_OFFSET		0x60
-#define GPDDAT_OFFSET		0x64
-#define GPDPUD_OFFSET		0x68
-#define GPDCONSLP_OFFSET	0x6C
-#define GPDPUDSLP_OFFSET	0x70
-#define GPECON_OFFSET		0x80
-#define GPEDAT_OFFSET		0x84
-#define GPEPUD_OFFSET		0x88
-#define GPECONSLP_OFFSET	0x8C
-#define GPEPUDSLP_OFFSET	0x90
-#define GPFCON_OFFSET		0xA0
-#define GPFDAT_OFFSET		0xA4
-#define GPFPUD_OFFSET		0xA8
-#define GPFCONSLP_OFFSET	0xAC
-#define GPFPUDSLP_OFFSET	0xB0
-#define GPGCON_OFFSET		0xC0
-#define GPGDAT_OFFSET		0xC4
-#define GPGPUD_OFFSET		0xC8
-#define GPGCONSLP_OFFSET	0xCC
-#define GPGPUDSLP_OFFSET	0xD0
-#define GPHCON0_OFFSET		0xE0
-#define GPHCON1_OFFSET		0xE4
-#define GPHDAT_OFFSET		0xE8
-#define GPHPUD_OFFSET		0xEC
-#define GPHCONSLP_OFFSET	0xF0
-#define GPHPUDSLP_OFFSET	0xF4
-#define GPICON_OFFSET		0x100
-#define GPIDAT_OFFSET		0x104
-#define GPIPUD_OFFSET		0x108
-#define GPICONSLP_OFFSET	0x10C
-#define GPIPUDSLP_OFFSET	0x110
-#define GPJCON_OFFSET		0x120
-#define GPJDAT_OFFSET		0x124
-#define GPJPUD_OFFSET		0x128
-#define GPJCONSLP_OFFSET	0x12C
-#define GPJPUDSLP_OFFSET	0x130
-#define MEM0DRVCON_OFFSET	0x1D0
-#define MEM1DRVCON_OFFSET	0x1D4
-#define GPKCON0_OFFSET		0x800
-#define GPKCON1_OFFSET		0x804
-#define GPKDAT_OFFSET		0x808
-#define GPKPUD_OFFSET		0x80C
-#define GPLCON0_OFFSET		0x810
-#define GPLCON1_OFFSET		0x814
-#define GPLDAT_OFFSET		0x818
-#define GPLPUD_OFFSET		0x81C
-#define GPMCON_OFFSET		0x820
-#define GPMDAT_OFFSET		0x824
-#define GPMPUD_OFFSET		0x828
-#define GPNCON_OFFSET		0x830
-#define GPNDAT_OFFSET		0x834
-#define GPNPUD_OFFSET		0x838
-#define GPOCON_OFFSET		0x140
-#define GPODAT_OFFSET		0x144
-#define GPOPUD_OFFSET		0x148
-#define GPOCONSLP_OFFSET	0x14C
-#define GPOPUDSLP_OFFSET	0x150
-#define GPPCON_OFFSET		0x160
-#define GPPDAT_OFFSET		0x164
-#define GPPPUD_OFFSET		0x168
-#define GPPCONSLP_OFFSET	0x16C
-#define GPPPUDSLP_OFFSET	0x170
-#define GPQCON_OFFSET		0x180
-#define GPQDAT_OFFSET		0x184
-#define GPQPUD_OFFSET		0x188
-#define GPQCONSLP_OFFSET	0x18C
-#define GPQPUDSLP_OFFSET	0x190
-
-#define EINTPEND_OFFSET		0x924
-
-#define GPACON_REG		__REG(ELFIN_GPIO_BASE + GPACON_OFFSET)
-#define GPADAT_REG		__REG(ELFIN_GPIO_BASE + GPADAT_OFFSET)
-#define GPAPUD_REG		__REG(ELFIN_GPIO_BASE + GPAPUD_OFFSET)
-#define GPACONSLP_REG		__REG(ELFIN_GPIO_BASE + GPACONSLP_OFFSET)
-#define GPAPUDSLP_REG		__REG(ELFIN_GPIO_BASE + GPAPUDSLP_OFFSET)
-#define GPBCON_REG		__REG(ELFIN_GPIO_BASE + GPBCON_OFFSET)
-#define GPBDAT_REG		__REG(ELFIN_GPIO_BASE + GPBDAT_OFFSET)
-#define GPBPUD_REG		__REG(ELFIN_GPIO_BASE + GPBPUD_OFFSET)
-#define GPBCONSLP_REG		__REG(ELFIN_GPIO_BASE + GPBCONSLP_OFFSET)
-#define GPBPUDSLP_REG		__REG(ELFIN_GPIO_BASE + GPBPUDSLP_OFFSET)
-#define GPCCON_REG		__REG(ELFIN_GPIO_BASE + GPCCON_OFFSET)
-#define GPCDAT_REG		__REG(ELFIN_GPIO_BASE + GPCDAT_OFFSET)
-#define GPCPUD_REG		__REG(ELFIN_GPIO_BASE + GPCPUD_OFFSET)
-#define GPCCONSLP_REG		__REG(ELFIN_GPIO_BASE + GPCCONSLP_OFFSET)
-#define GPCPUDSLP_REG		__REG(ELFIN_GPIO_BASE + GPCPUDSLP_OFFSET)
-#define GPDCON_REG		__REG(ELFIN_GPIO_BASE + GPDCON_OFFSET)
-#define GPDDAT_REG		__REG(ELFIN_GPIO_BASE + GPDDAT_OFFSET)
-#define GPDPUD_REG		__REG(ELFIN_GPIO_BASE + GPDPUD_OFFSET)
-#define GPDCONSLP_REG		__REG(ELFIN_GPIO_BASE + GPDCONSLP_OFFSET)
-#define GPDPUDSLP_REG		__REG(ELFIN_GPIO_BASE + GPDPUDSLP_OFFSET)
-#define GPECON_REG		__REG(ELFIN_GPIO_BASE + GPECON_OFFSET)
-#define GPEDAT_REG		__REG(ELFIN_GPIO_BASE + GPEDAT_OFFSET)
-#define GPEPUD_REG		__REG(ELFIN_GPIO_BASE + GPEPUD_OFFSET)
-#define GPECONSLP_REG		__REG(ELFIN_GPIO_BASE + GPECONSLP_OFFSET)
-#define GPEPUDSLP_REG		__REG(ELFIN_GPIO_BASE + GPEPUDSLP_OFFSET)
-#define GPFCON_REG		__REG(ELFIN_GPIO_BASE + GPFCON_OFFSET)
-#define GPFDAT_REG		__REG(ELFIN_GPIO_BASE + GPFDAT_OFFSET)
-#define GPFPUD_REG		__REG(ELFIN_GPIO_BASE + GPFPUD_OFFSET)
-#define GPFCONSLP_REG		__REG(ELFIN_GPIO_BASE + GPFCONSLP_OFFSET)
-#define GPFPUDSLP_REG		__REG(ELFIN_GPIO_BASE + GPFPUDSLP_OFFSET)
-#define GPGCON_REG		__REG(ELFIN_GPIO_BASE + GPGCON_OFFSET)
-#define GPGDAT_REG		__REG(ELFIN_GPIO_BASE + GPGDAT_OFFSET)
-#define GPGPUD_REG		__REG(ELFIN_GPIO_BASE + GPGPUD_OFFSET)
-#define GPGCONSLP_REG		__REG(ELFIN_GPIO_BASE + GPGCONSLP_OFFSET)
-#define GPGPUDSLP_REG		__REG(ELFIN_GPIO_BASE + GPGPUDSLP_OFFSET)
-#define GPHCON0_REG		__REG(ELFIN_GPIO_BASE + GPHCON0_OFFSET)
-#define GPHCON1_REG		__REG(ELFIN_GPIO_BASE + GPHCON1_OFFSET)
-#define GPHDAT_REG		__REG(ELFIN_GPIO_BASE + GPHDAT_OFFSET)
-#define GPHPUD_REG		__REG(ELFIN_GPIO_BASE + GPHPUD_OFFSET)
-#define GPHCONSLP_REG		__REG(ELFIN_GPIO_BASE + GPHCONSLP_OFFSET)
-#define GPHPUDSLP_REG		__REG(ELFIN_GPIO_BASE + GPHPUDSLP_OFFSET)
-#define GPICON_REG		__REG(ELFIN_GPIO_BASE + GPICON_OFFSET)
-#define GPIDAT_REG		__REG(ELFIN_GPIO_BASE + GPIDAT_OFFSET)
-#define GPIPUD_REG		__REG(ELFIN_GPIO_BASE + GPIPUD_OFFSET)
-#define GPICONSLP_REG		__REG(ELFIN_GPIO_BASE + GPICONSLP_OFFSET)
-#define GPIPUDSLP_REG		__REG(ELFIN_GPIO_BASE + GPIPUDSLP_OFFSET)
-#define GPJCON_REG		__REG(ELFIN_GPIO_BASE + GPJCON_OFFSET)
-#define GPJDAT_REG		__REG(ELFIN_GPIO_BASE + GPJDAT_OFFSET)
-#define GPJPUD_REG		__REG(ELFIN_GPIO_BASE + GPJPUD_OFFSET)
-#define GPJCONSLP_REG		__REG(ELFIN_GPIO_BASE + GPJCONSLP_OFFSET)
-#define GPJPUDSLP_REG		__REG(ELFIN_GPIO_BASE + GPJPUDSLP_OFFSET)
-#define GPKCON0_REG		__REG(ELFIN_GPIO_BASE + GPKCON0_OFFSET)
-#define GPKCON1_REG		__REG(ELFIN_GPIO_BASE + GPKCON1_OFFSET)
-#define GPKDAT_REG		__REG(ELFIN_GPIO_BASE + GPKDAT_OFFSET)
-#define GPKPUD_REG		__REG(ELFIN_GPIO_BASE + GPKPUD_OFFSET)
-#define GPLCON0_REG		__REG(ELFIN_GPIO_BASE + GPLCON0_OFFSET)
-#define GPLCON1_REG		__REG(ELFIN_GPIO_BASE + GPLCON1_OFFSET)
-#define GPLDAT_REG		__REG(ELFIN_GPIO_BASE + GPLDAT_OFFSET)
-#define GPLPUD_REG		__REG(ELFIN_GPIO_BASE + GPLPUD_OFFSET)
-#define GPMCON_REG		__REG(ELFIN_GPIO_BASE + GPMCON_OFFSET)
-#define GPMDAT_REG		__REG(ELFIN_GPIO_BASE + GPMDAT_OFFSET)
-#define GPMPUD_REG		__REG(ELFIN_GPIO_BASE + GPMPUD_OFFSET)
-#define GPNCON_REG		__REG(ELFIN_GPIO_BASE + GPNCON_OFFSET)
-#define GPNDAT_REG		__REG(ELFIN_GPIO_BASE + GPNDAT_OFFSET)
-#define GPNPUD_REG		__REG(ELFIN_GPIO_BASE + GPNPUD_OFFSET)
-#define GPOCON_REG		__REG(ELFIN_GPIO_BASE + GPOCON_OFFSET)
-#define GPODAT_REG		__REG(ELFIN_GPIO_BASE + GPODAT_OFFSET)
-#define GPOPUD_REG		__REG(ELFIN_GPIO_BASE + GPOPUD_OFFSET)
-#define GPOCONSLP_REG		__REG(ELFIN_GPIO_BASE + GPOCONSLP_OFFSET)
-#define GPOPUDSLP_REG		__REG(ELFIN_GPIO_BASE + GPOPUDSLP_OFFSET)
-#define GPPCON_REG		__REG(ELFIN_GPIO_BASE + GPPCON_OFFSET)
-#define GPPDAT_REG		__REG(ELFIN_GPIO_BASE + GPPDAT_OFFSET)
-#define GPPPUD_REG		__REG(ELFIN_GPIO_BASE + GPPPUD_OFFSET)
-#define GPPCONSLP_REG		__REG(ELFIN_GPIO_BASE + GPPCONSLP_OFFSET)
-#define GPPPUDSLP_REG		__REG(ELFIN_GPIO_BASE + GPPPUDSLP_OFFSET)
-#define GPQCON_REG		__REG(ELFIN_GPIO_BASE + GPQCON_OFFSET)
-#define GPQDAT_REG		__REG(ELFIN_GPIO_BASE + GPQDAT_OFFSET)
-#define GPQPUD_REG		__REG(ELFIN_GPIO_BASE + GPQPUD_OFFSET)
-#define GPQCONSLP_REG		__REG(ELFIN_GPIO_BASE + GPQCONSLP_OFFSET)
-#define GPQPUDSLP_REG		__REG(ELFIN_GPIO_BASE + GPQPUDSLP_OFFSET)
-
-/*
- * Bus Matrix
- */
-#define ELFIN_MEM_SYS_CFG	0x7e00f120
-
-#define S3C64XX_MEM_SYS_CFG_16BIT	(1 << 12)
-
-#define S3C64XX_MEM_SYS_CFG_NAND	0x0008
-#define S3C64XX_MEM_SYS_CFG_ONENAND	S3C64XX_MEM_SYS_CFG_16BIT
-
-#define GPACON		(ELFIN_GPIO_BASE + GPACON_OFFSET)
-#define GPADAT		(ELFIN_GPIO_BASE + GPADAT_OFFSET)
-#define GPAPUD		(ELFIN_GPIO_BASE + GPAPUD_OFFSET)
-#define GPACONSLP	(ELFIN_GPIO_BASE + GPACONSLP_OFFSET)
-#define GPAPUDSLP	(ELFIN_GPIO_BASE + GPAPUDSLP_OFFSET)
-#define GPBCON		(ELFIN_GPIO_BASE + GPBCON_OFFSET)
-#define GPBDAT		(ELFIN_GPIO_BASE + GPBDAT_OFFSET)
-#define GPBPUD		(ELFIN_GPIO_BASE + GPBPUD_OFFSET)
-#define GPBCONSLP	(ELFIN_GPIO_BASE + GPBCONSLP_OFFSET)
-#define GPBPUDSLP	(ELFIN_GPIO_BASE + GPBPUDSLP_OFFSET)
-#define GPCCON		(ELFIN_GPIO_BASE + GPCCON_OFFSET)
-#define GPCDAT		(ELFIN_GPIO_BASE + GPCDAT_OFFSET)
-#define GPCPUD		(ELFIN_GPIO_BASE + GPCPUD_OFFSET)
-#define GPCCONSLP	(ELFIN_GPIO_BASE + GPCCONSLP_OFFSET)
-#define GPCPUDSLP	(ELFIN_GPIO_BASE + GPCPUDSLP_OFFSET)
-#define GPDCON		(ELFIN_GPIO_BASE + GPDCON_OFFSET)
-#define GPDDAT		(ELFIN_GPIO_BASE + GPDDAT_OFFSET)
-#define GPDPUD		(ELFIN_GPIO_BASE + GPDPUD_OFFSET)
-#define GPDCONSLP	(ELFIN_GPIO_BASE + GPDCONSLP_OFFSET)
-#define GPDPUDSLP	(ELFIN_GPIO_BASE + GPDPUDSLP_OFFSET)
-#define GPECON		(ELFIN_GPIO_BASE + GPECON_OFFSET)
-#define GPEDAT		(ELFIN_GPIO_BASE + GPEDAT_OFFSET)
-#define GPEPUD		(ELFIN_GPIO_BASE + GPEPUD_OFFSET)
-#define GPECONSLP	(ELFIN_GPIO_BASE + GPECONSLP_OFFSET)
-#define GPEPUDSLP	(ELFIN_GPIO_BASE + GPEPUDSLP_OFFSET)
-#define GPFCON		(ELFIN_GPIO_BASE + GPFCON_OFFSET)
-#define GPFDAT		(ELFIN_GPIO_BASE + GPFDAT_OFFSET)
-#define GPFPUD		(ELFIN_GPIO_BASE + GPFPUD_OFFSET)
-#define GPFCONSLP	(ELFIN_GPIO_BASE + GPFCONSLP_OFFSET)
-#define GPFPUDSLP	(ELFIN_GPIO_BASE + GPFPUDSLP_OFFSET)
-#define GPGCON		(ELFIN_GPIO_BASE + GPGCON_OFFSET)
-#define GPGDAT		(ELFIN_GPIO_BASE + GPGDAT_OFFSET)
-#define GPGPUD		(ELFIN_GPIO_BASE + GPGPUD_OFFSET)
-#define GPGCONSLP	(ELFIN_GPIO_BASE + GPGCONSLP_OFFSET)
-#define GPGPUDSLP	(ELFIN_GPIO_BASE + GPGPUDSLP_OFFSET)
-#define GPHCON0		(ELFIN_GPIO_BASE + GPHCON0_OFFSET)
-#define GPHCON1		(ELFIN_GPIO_BASE + GPHCON1_OFFSET)
-#define GPHDAT		(ELFIN_GPIO_BASE + GPHDAT_OFFSET)
-#define GPHPUD		(ELFIN_GPIO_BASE + GPHPUD_OFFSET)
-#define GPHCONSLP	(ELFIN_GPIO_BASE + GPHCONSLP_OFFSET)
-#define GPHPUDSLP	(ELFIN_GPIO_BASE + GPHPUDSLP_OFFSET)
-#define GPICON		(ELFIN_GPIO_BASE + GPICON_OFFSET)
-#define GPIDAT		(ELFIN_GPIO_BASE + GPIDAT_OFFSET)
-#define GPIPUD		(ELFIN_GPIO_BASE + GPIPUD_OFFSET)
-#define GPICONSLP	(ELFIN_GPIO_BASE + GPICONSLP_OFFSET)
-#define GPIPUDSLP	(ELFIN_GPIO_BASE + GPIPUDSLP_OFFSET)
-#define GPJCON		(ELFIN_GPIO_BASE + GPJCON_OFFSET)
-#define GPJDAT		(ELFIN_GPIO_BASE + GPJDAT_OFFSET)
-#define GPJPUD		(ELFIN_GPIO_BASE + GPJPUD_OFFSET)
-#define GPJCONSLP	(ELFIN_GPIO_BASE + GPJCONSLP_OFFSET)
-#define GPJPUDSLP	(ELFIN_GPIO_BASE + GPJPUDSLP_OFFSET)
-#define GPKCON0		(ELFIN_GPIO_BASE + GPKCON0_OFFSET)
-#define GPKCON1		(ELFIN_GPIO_BASE + GPKCON1_OFFSET)
-#define GPKDAT		(ELFIN_GPIO_BASE + GPKDAT_OFFSET)
-#define GPKPUD		(ELFIN_GPIO_BASE + GPKPUD_OFFSET)
-#define GPLCON0		(ELFIN_GPIO_BASE + GPLCON0_OFFSET)
-#define GPLCON1		(ELFIN_GPIO_BASE + GPLCON1_OFFSET)
-#define GPLDAT		(ELFIN_GPIO_BASE + GPLDAT_OFFSET)
-#define GPLPUD		(ELFIN_GPIO_BASE + GPLPUD_OFFSET)
-#define GPMCON		(ELFIN_GPIO_BASE + GPMCON_OFFSET)
-#define GPMDAT		(ELFIN_GPIO_BASE + GPMDAT_OFFSET)
-#define GPMPUD		(ELFIN_GPIO_BASE + GPMPUD_OFFSET)
-#define GPNCON		(ELFIN_GPIO_BASE + GPNCON_OFFSET)
-#define GPNDAT		(ELFIN_GPIO_BASE + GPNDAT_OFFSET)
-#define GPNPUD		(ELFIN_GPIO_BASE + GPNPUD_OFFSET)
-#define GPOCON		(ELFIN_GPIO_BASE + GPOCON_OFFSET)
-#define GPODAT		(ELFIN_GPIO_BASE + GPODAT_OFFSET)
-#define GPOPUD		(ELFIN_GPIO_BASE + GPOPUD_OFFSET)
-#define GPOCONSLP	(ELFIN_GPIO_BASE + GPOCONSLP_OFFSET)
-#define GPOPUDSLP	(ELFIN_GPIO_BASE + GPOPUDSLP_OFFSET)
-#define GPPCON		(ELFIN_GPIO_BASE + GPPCON_OFFSET)
-#define GPPDAT		(ELFIN_GPIO_BASE + GPPDAT_OFFSET)
-#define GPPPUD		(ELFIN_GPIO_BASE + GPPPUD_OFFSET)
-#define GPPCONSLP	(ELFIN_GPIO_BASE + GPPCONSLP_OFFSET)
-#define GPPPUDSLP	(ELFIN_GPIO_BASE + GPPPUDSLP_OFFSET)
-#define GPQCON		(ELFIN_GPIO_BASE + GPQCON_OFFSET)
-#define GPQDAT		(ELFIN_GPIO_BASE + GPQDAT_OFFSET)
-#define GPQPUD		(ELFIN_GPIO_BASE + GPQPUD_OFFSET)
-#define GPQCONSLP	(ELFIN_GPIO_BASE + GPQCONSLP_OFFSET)
-#define GPQPUDSLP	(ELFIN_GPIO_BASE + GPQPUDSLP_OFFSET)
-
-/*
- * Memory controller
- */
-#define ELFIN_SROM_BASE		0x70000000
-
-#define SROM_BW_REG	__REG(ELFIN_SROM_BASE + 0x0)
-#define SROM_BC0_REG	__REG(ELFIN_SROM_BASE + 0x4)
-#define SROM_BC1_REG	__REG(ELFIN_SROM_BASE + 0x8)
-#define SROM_BC2_REG	__REG(ELFIN_SROM_BASE + 0xC)
-#define SROM_BC3_REG	__REG(ELFIN_SROM_BASE + 0x10)
-#define SROM_BC4_REG	__REG(ELFIN_SROM_BASE + 0x14)
-#define SROM_BC5_REG	__REG(ELFIN_SROM_BASE + 0x18)
-
-/*
- * SDRAM Controller
- */
-#define ELFIN_DMC0_BASE		0x7e000000
-#define ELFIN_DMC1_BASE		0x7e001000
-
-#define INDEX_DMC_MEMC_STATUS	0x00
-#define INDEX_DMC_MEMC_CMD	0x04
-#define INDEX_DMC_DIRECT_CMD	0x08
-#define INDEX_DMC_MEMORY_CFG	0x0C
-#define INDEX_DMC_REFRESH_PRD	0x10
-#define INDEX_DMC_CAS_LATENCY	0x14
-#define INDEX_DMC_T_DQSS	0x18
-#define INDEX_DMC_T_MRD		0x1C
-#define INDEX_DMC_T_RAS		0x20
-#define INDEX_DMC_T_RC		0x24
-#define INDEX_DMC_T_RCD		0x28
-#define INDEX_DMC_T_RFC		0x2C
-#define INDEX_DMC_T_RP		0x30
-#define INDEX_DMC_T_RRD		0x34
-#define INDEX_DMC_T_WR		0x38
-#define INDEX_DMC_T_WTR		0x3C
-#define INDEX_DMC_T_XP		0x40
-#define INDEX_DMC_T_XSR		0x44
-#define INDEX_DMC_T_ESR		0x48
-#define INDEX_DMC_MEMORY_CFG2	0x4C
-#define INDEX_DMC_CHIP_0_CFG	0x200
-#define INDEX_DMC_CHIP_1_CFG	0x204
-#define INDEX_DMC_CHIP_2_CFG	0x208
-#define INDEX_DMC_CHIP_3_CFG	0x20C
-#define INDEX_DMC_USER_STATUS	0x300
-#define INDEX_DMC_USER_CONFIG	0x304
-
-/*
- * Memory Chip direct command
- */
-#define DMC_NOP0	0x0c0000
-#define DMC_NOP1	0x1c0000
-#define DMC_PA0		0x000000	/* Precharge all */
-#define DMC_PA1		0x100000
-#define DMC_AR0		0x040000	/* Autorefresh */
-#define DMC_AR1		0x140000
-#define DMC_SDR_MR0	0x080032	/* MRS, CAS 3,  Burst Length 4 */
-#define DMC_SDR_MR1	0x180032
-#define DMC_DDR_MR0	0x080162
-#define DMC_DDR_MR1	0x180162
-#define DMC_mDDR_MR0	0x080032	/* CAS 3, Burst Length 4 */
-#define DMC_mDDR_MR1	0x180032
-#define DMC_mSDR_EMR0	0x0a0000	/* EMRS, DS:Full, PASR:Full Array */
-#define DMC_mSDR_EMR1	0x1a0000
-#define DMC_DDR_EMR0	0x090000
-#define DMC_DDR_EMR1	0x190000
-#define DMC_mDDR_EMR0	0x0a0000	/*  DS:Full, PASR:Full Array */
-#define DMC_mDDR_EMR1	0x1a0000
-
-/*
- * Definitions for memory configuration
- * Set memory configuration
- *	active_chips	= 1'b0 (1 chip)
- *	qos_master_chip	= 3'b000(ARID[3:0])
- *	memory burst	= 3'b010(burst 4)
- *	stop_mem_clock	= 1'b0(disable dynamical stop)
- *	auto_power_down	= 1'b0(disable auto power-down mode)
- *	power_down_prd	= 6'b00_0000(0 cycle for auto power-down)
- *	ap_bit		= 1'b0 (bit position of auto-precharge is 10)
- *	row_bits	= 3'b010(# row address 13)
- *	column_bits	= 3'b010(# column address 10 )
- *
- * Set user configuration
- *	2'b10=SDRAM/mSDRAM, 2'b11=DDR, 2'b01=mDDR
- *
- * Set chip select for chip [n]
- *	 row bank control, bank address 0x3000_0000 ~ 0x37ff_ffff
- *	 CHIP_[n]_CFG=0x30F8,  30: ADDR[31:24], F8: Mask[31:24]
- */
-
-/*
- * Nand flash controller
- */
-#define ELFIN_NAND_BASE		0x70200000
-
-#define NFCONF_OFFSET		0x00
-#define NFCONT_OFFSET		0x04
-#define NFCMMD_OFFSET		0x08
-#define NFADDR_OFFSET		0x0c
-#define NFDATA_OFFSET		0x10
-#define NFMECCDATA0_OFFSET	0x14
-#define NFMECCDATA1_OFFSET	0x18
-#define NFSECCDATA0_OFFSET	0x1c
-#define NFSBLK_OFFSET		0x20
-#define NFEBLK_OFFSET		0x24
-#define NFSTAT_OFFSET		0x28
-#define NFESTAT0_OFFSET		0x2c
-#define NFESTAT1_OFFSET		0x30
-#define NFMECC0_OFFSET		0x34
-#define NFMECC1_OFFSET		0x38
-#define NFSECC_OFFSET		0x3c
-#define NFMLCBITPT_OFFSET	0x40
-
-#define NFCONF			(ELFIN_NAND_BASE + NFCONF_OFFSET)
-#define NFCONT			(ELFIN_NAND_BASE + NFCONT_OFFSET)
-#define NFCMMD			(ELFIN_NAND_BASE + NFCMMD_OFFSET)
-#define NFADDR			(ELFIN_NAND_BASE + NFADDR_OFFSET)
-#define NFDATA			(ELFIN_NAND_BASE + NFDATA_OFFSET)
-#define NFMECCDATA0		(ELFIN_NAND_BASE + NFMECCDATA0_OFFSET)
-#define NFMECCDATA1		(ELFIN_NAND_BASE + NFMECCDATA1_OFFSET)
-#define NFSECCDATA0		(ELFIN_NAND_BASE + NFSECCDATA0_OFFSET)
-#define NFSBLK			(ELFIN_NAND_BASE + NFSBLK_OFFSET)
-#define NFEBLK			(ELFIN_NAND_BASE + NFEBLK_OFFSET)
-#define NFSTAT			(ELFIN_NAND_BASE + NFSTAT_OFFSET)
-#define NFESTAT0		(ELFIN_NAND_BASE + NFESTAT0_OFFSET)
-#define NFESTAT1		(ELFIN_NAND_BASE + NFESTAT1_OFFSET)
-#define NFMECC0			(ELFIN_NAND_BASE + NFMECC0_OFFSET)
-#define NFMECC1			(ELFIN_NAND_BASE + NFMECC1_OFFSET)
-#define NFSECC			(ELFIN_NAND_BASE + NFSECC_OFFSET)
-#define NFMLCBITPT		(ELFIN_NAND_BASE + NFMLCBITPT_OFFSET)
-
-#define NFCONF_REG		__REG(ELFIN_NAND_BASE + NFCONF_OFFSET)
-#define NFCONT_REG		__REG(ELFIN_NAND_BASE + NFCONT_OFFSET)
-#define NFCMD_REG		__REG(ELFIN_NAND_BASE + NFCMMD_OFFSET)
-#define NFADDR_REG		__REG(ELFIN_NAND_BASE + NFADDR_OFFSET)
-#define NFDATA_REG		__REG(ELFIN_NAND_BASE + NFDATA_OFFSET)
-#define NFDATA8_REG		__REGb(ELFIN_NAND_BASE + NFDATA_OFFSET)
-#define NFMECCDATA0_REG		__REG(ELFIN_NAND_BASE + NFMECCDATA0_OFFSET)
-#define NFMECCDATA1_REG		__REG(ELFIN_NAND_BASE + NFMECCDATA1_OFFSET)
-#define NFSECCDATA0_REG		__REG(ELFIN_NAND_BASE + NFSECCDATA0_OFFSET)
-#define NFSBLK_REG		__REG(ELFIN_NAND_BASE + NFSBLK_OFFSET)
-#define NFEBLK_REG		__REG(ELFIN_NAND_BASE + NFEBLK_OFFSET)
-#define NFSTAT_REG		__REG(ELFIN_NAND_BASE + NFSTAT_OFFSET)
-#define NFESTAT0_REG		__REG(ELFIN_NAND_BASE + NFESTAT0_OFFSET)
-#define NFESTAT1_REG		__REG(ELFIN_NAND_BASE + NFESTAT1_OFFSET)
-#define NFMECC0_REG		__REG(ELFIN_NAND_BASE + NFMECC0_OFFSET)
-#define NFMECC1_REG		__REG(ELFIN_NAND_BASE + NFMECC1_OFFSET)
-#define NFSECC_REG		__REG(ELFIN_NAND_BASE + NFSECC_OFFSET)
-#define NFMLCBITPT_REG		__REG(ELFIN_NAND_BASE + NFMLCBITPT_OFFSET)
-
-#define NFCONF_ECC_4BIT		(1<<24)
-
-#define NFCONT_ECC_ENC		(1<<18)
-#define NFCONT_WP		(1<<16)
-#define NFCONT_MECCLOCK		(1<<7)
-#define NFCONT_SECCLOCK		(1<<6)
-#define NFCONT_INITMECC		(1<<5)
-#define NFCONT_INITSECC		(1<<4)
-#define NFCONT_INITECC		(NFCONT_INITMECC | NFCONT_INITSECC)
-#define NFCONT_CS_ALT		(1<<2)
-#define NFCONT_CS		(1<<1)
-#define NFCONT_ENABLE		(1<<0)
-
-#define NFSTAT_ECCENCDONE	(1<<7)
-#define NFSTAT_ECCDECDONE	(1<<6)
-#define NFSTAT_RnB		(1<<0)
-
-#define NFESTAT0_ECCBUSY	(1<<31)
-
-/*
- * Interrupt
- */
-#define ELFIN_VIC0_BASE_ADDR	0x71200000
-#define ELFIN_VIC1_BASE_ADDR	0x71300000
-#define oINTMOD			0x0C	/* VIC INT SELECT (IRQ or FIQ) */
-#define oINTUNMSK		0x10	/* VIC INT EN (write 1 to unmask) */
-#define oINTMSK			0x14	/* VIC INT EN CLEAR (write 1 to mask) */
-#define oINTSUBMSK		0x1C	/* VIC SOFT INT CLEAR */
-#define oVECTADDR		0xF00 /* VIC ADDRESS */
-
-/*
- * Watchdog timer
- */
-#define ELFIN_WATCHDOG_BASE	0x7E004000
-
-#define WTCON_REG		__REG(0x7E004004)
-#define WTDAT_REG		__REG(0x7E004008)
-#define WTCNT_REG		__REG(0x7E00400C)
-
-
-/*
- * UART
- */
-#define ELFIN_UART_BASE		0x7F005000
-
-#define ELFIN_UART0_OFFSET	0x0000
-#define ELFIN_UART1_OFFSET	0x0400
-#define ELFIN_UART2_OFFSET	0x0800
-
-#define ULCON_OFFSET		0x00
-#define UCON_OFFSET		0x04
-#define UFCON_OFFSET		0x08
-#define UMCON_OFFSET		0x0C
-#define UTRSTAT_OFFSET		0x10
-#define UERSTAT_OFFSET		0x14
-#define UFSTAT_OFFSET		0x18
-#define UMSTAT_OFFSET		0x1C
-#define UTXH_OFFSET		0x20
-#define URXH_OFFSET		0x24
-#define UBRDIV_OFFSET		0x28
-#define UDIVSLOT_OFFSET		0x2C
-#define UINTP_OFFSET		0x30
-#define UINTSP_OFFSET		0x34
-#define UINTM_OFFSET		0x38
-
-#define ULCON0_REG		__REG(0x7F005000)
-#define UCON0_REG		__REG(0x7F005004)
-#define UFCON0_REG		__REG(0x7F005008)
-#define UMCON0_REG		__REG(0x7F00500C)
-#define UTRSTAT0_REG		__REG(0x7F005010)
-#define UERSTAT0_REG		__REG(0x7F005014)
-#define UFSTAT0_REG		__REG(0x7F005018)
-#define UMSTAT0_REG		__REG(0x7F00501c)
-#define UTXH0_REG		__REG(0x7F005020)
-#define URXH0_REG		__REG(0x7F005024)
-#define UBRDIV0_REG		__REG(0x7F005028)
-#define UDIVSLOT0_REG		__REG(0x7F00502c)
-#define UINTP0_REG		__REG(0x7F005030)
-#define UINTSP0_REG		__REG(0x7F005034)
-#define UINTM0_REG		__REG(0x7F005038)
-
-#define ULCON1_REG		__REG(0x7F005400)
-#define UCON1_REG		__REG(0x7F005404)
-#define UFCON1_REG		__REG(0x7F005408)
-#define UMCON1_REG		__REG(0x7F00540C)
-#define UTRSTAT1_REG		__REG(0x7F005410)
-#define UERSTAT1_REG		__REG(0x7F005414)
-#define UFSTAT1_REG		__REG(0x7F005418)
-#define UMSTAT1_REG		__REG(0x7F00541c)
-#define UTXH1_REG		__REG(0x7F005420)
-#define URXH1_REG		__REG(0x7F005424)
-#define UBRDIV1_REG		__REG(0x7F005428)
-#define UDIVSLOT1_REG		__REG(0x7F00542c)
-#define UINTP1_REG		__REG(0x7F005430)
-#define UINTSP1_REG		__REG(0x7F005434)
-#define UINTM1_REG		__REG(0x7F005438)
-
-#define UTRSTAT_TX_EMPTY	(1 << 2)
-#define UTRSTAT_RX_READY	(1 << 0)
-#define UART_ERR_MASK		0xF
-
-/*
- * PWM timer
- */
-#define ELFIN_TIMER_BASE	0x7F006000
-
-#define TCFG0_REG	__REG(0x7F006000)
-#define TCFG1_REG	__REG(0x7F006004)
-#define TCON_REG	__REG(0x7F006008)
-#define TCNTB0_REG	__REG(0x7F00600c)
-#define TCMPB0_REG	__REG(0x7F006010)
-#define TCNTO0_REG	__REG(0x7F006014)
-#define TCNTB1_REG	__REG(0x7F006018)
-#define TCMPB1_REG	__REG(0x7F00601c)
-#define TCNTO1_REG	__REG(0x7F006020)
-#define TCNTB2_REG	__REG(0x7F006024)
-#define TCMPB2_REG	__REG(0x7F006028)
-#define TCNTO2_REG	__REG(0x7F00602c)
-#define TCNTB3_REG	__REG(0x7F006030)
-#define TCMPB3_REG	__REG(0x7F006034)
-#define TCNTO3_REG	__REG(0x7F006038)
-#define TCNTB4_REG	__REG(0x7F00603c)
-#define TCNTO4_REG	__REG(0x7F006040)
-
-/* Fields */
-#define fTCFG0_DZONE		Fld(8, 16) /* the dead zone length (=timer 0) */
-#define fTCFG0_PRE1		Fld(8, 8)  /* prescaler value for time 2,3,4 */
-#define fTCFG0_PRE0		Fld(8, 0)  /* prescaler value for time 0,1 */
-#define fTCFG1_MUX4		Fld(4, 16)
-/* bits */
-#define TCFG0_DZONE(x)		FInsrt((x), fTCFG0_DZONE)
-#define TCFG0_PRE1(x)		FInsrt((x), fTCFG0_PRE1)
-#define TCFG0_PRE0(x)		FInsrt((x), fTCFG0_PRE0)
-#define TCON_4_AUTO		(1 << 22)  /* auto reload on/off for Timer 4 */
-#define TCON_4_UPDATE		(1 << 21)  /* manual Update TCNTB4 */
-#define TCON_4_ONOFF		(1 << 20)  /* 0: Stop, 1: start Timer 4 */
-#define COUNT_4_ON		(TCON_4_ONOFF * 1)
-#define COUNT_4_OFF		(TCON_4_ONOFF * 0)
-#define TCON_3_AUTO		(1 << 19)  /* auto reload on/off for Timer 3 */
-#define TIMER3_ATLOAD_ON	(TCON_3_AUTO * 1)
-#define TIMER3_ATLAOD_OFF	FClrBit(TCON, TCON_3_AUTO)
-#define TCON_3_INVERT		(1 << 18)  /* 1: Inverter on for TOUT3 */
-#define TIMER3_IVT_ON		(TCON_3_INVERT * 1)
-#define TIMER3_IVT_OFF		(FClrBit(TCON, TCON_3_INVERT))
-#define TCON_3_MAN		(1 << 17)  /* manual Update TCNTB3,TCMPB3 */
-#define TIMER3_MANUP		(TCON_3_MAN*1)
-#define TIMER3_NOP		(FClrBit(TCON, TCON_3_MAN))
-#define TCON_3_ONOFF		(1 << 16)  /* 0: Stop, 1: start Timer 3 */
-#define TIMER3_ON		(TCON_3_ONOFF * 1)
-#define TIMER3_OFF		(FClrBit(TCON, TCON_3_ONOFF))
-
-#if defined(CONFIG_CLK_400_100_50)
-#define STARTUP_AMDIV		400
-#define STARTUP_MDIV		400
-#define STARTUP_PDIV		6
-#define STARTUP_SDIV		1
-#elif defined(CONFIG_CLK_400_133_66)
-#define STARTUP_AMDIV		400
-#define STARTUP_MDIV		533
-#define STARTUP_PDIV		6
-#define STARTUP_SDIV		1
-#elif defined(CONFIG_CLK_533_133_66)
-#define STARTUP_AMDIV		533
-#define STARTUP_MDIV		533
-#define STARTUP_PDIV		6
-#define STARTUP_SDIV		1
-#elif defined(CONFIG_CLK_667_133_66)
-#define STARTUP_AMDIV		667
-#define STARTUP_MDIV		533
-#define STARTUP_PDIV		6
-#define STARTUP_SDIV		1
-#endif
-
-#define	STARTUP_PCLKDIV		3
-#define STARTUP_HCLKX2DIV	1
-#define STARTUP_HCLKDIV		1
-#define STARTUP_MPLLDIV		1
-#define STARTUP_APLLDIV		0
-
-#define CLK_DIV_VAL	((STARTUP_PCLKDIV << 12) | (STARTUP_HCLKX2DIV << 9) | \
-	(STARTUP_HCLKDIV << 8) | (STARTUP_MPLLDIV<<4) | STARTUP_APLLDIV)
-#define MPLL_VAL	((1 << 31) | (STARTUP_MDIV << 16) | \
-	(STARTUP_PDIV << 8) | STARTUP_SDIV)
-#define STARTUP_MPLL	(((CONFIG_SYS_CLK_FREQ >> STARTUP_SDIV) / \
-	STARTUP_PDIV) * STARTUP_MDIV)
-
-#if defined(CONFIG_SYNC_MODE)
-#define APLL_VAL	((1 << 31) | (STARTUP_MDIV << 16) | \
-	(STARTUP_PDIV << 8) | STARTUP_SDIV)
-#define STARTUP_APLL	(((CONFIG_SYS_CLK_FREQ >> STARTUP_SDIV) / \
-	STARTUP_PDIV) * STARTUP_MDIV)
-#define STARTUP_HCLK	(STARTUP_MPLL / (STARTUP_HCLKX2DIV + 1) / \
-	(STARTUP_HCLKDIV + 1))
-#else
-#define APLL_VAL	((1 << 31) | (STARTUP_AMDIV << 16) | \
-	(STARTUP_PDIV << 8) | STARTUP_SDIV)
-#define STARTUP_APLL	(((CONFIG_SYS_CLK_FREQ >> STARTUP_SDIV) / \
-	STARTUP_PDIV) * STARTUP_AMDIV)
-#define STARTUP_HCLK	(STARTUP_MPLL / (STARTUP_HCLKX2DIV + 1) / \
-	(STARTUP_HCLKDIV + 1))
-#endif
-
-
-/*-----------------------------------------------------------------------
- * Physical Memory Map
- */
-#define DMC1_MEM_CFG	0x00010012	/* burst 4, 13-bit row, 10-bit col */
-#define DMC1_MEM_CFG2	0xB45
-#define DMC1_CHIP0_CFG	0x150F8		/* 0x5000_0000~0x57ff_ffff (128 MiB) */
-#define DMC_DDR_32_CFG	0x0 		/* 32bit, DDR */
-
-/* Memory Parameters */
-/* DDR Parameters */
-#define DDR_tREFRESH		7800	/* ns */
-#define DDR_tRAS		45	/* ns (min: 45ns)*/
-#define DDR_tRC 		68	/* ns (min: 67.5ns)*/
-#define DDR_tRCD		23	/* ns (min: 22.5ns)*/
-#define DDR_tRFC		80	/* ns (min: 80ns)*/
-#define DDR_tRP 		23	/* ns (min: 22.5ns)*/
-#define DDR_tRRD		15	/* ns (min: 15ns)*/
-#define DDR_tWR 		15	/* ns (min: 15ns)*/
-#define DDR_tXSR		120	/* ns (min: 120ns)*/
-#define DDR_CASL		3	/* CAS Latency 3 */
-
-/*
- * mDDR memory configuration
- */
-
-#define NS_TO_CLK(t)		((STARTUP_HCLK / 1000 * (t) - 1) / 1000000)
-
-#define DMC_DDR_BA_EMRS 	2
-#define DMC_DDR_MEM_CASLAT	3
-/* 6   Set Cas Latency to 3 */
-#define DMC_DDR_CAS_LATENCY	(DDR_CASL << 1)
-/* Min 0.75 ~ 1.25 */
-#define DMC_DDR_t_DQSS		1
-/* Min 2 tck */
-#define DMC_DDR_t_MRD		2
-/* 7, Min 45ns */
-#define DMC_DDR_t_RAS		(NS_TO_CLK(DDR_tRAS) + 1)
-/* 10, Min 67.5ns */
-#define DMC_DDR_t_RC		(NS_TO_CLK(DDR_tRC) + 1)
-/* 4,5(TRM), Min 22.5ns */
-#define DMC_DDR_t_RCD		(NS_TO_CLK(DDR_tRCD) + 1)
-#define DMC_DDR_schedule_RCD	((DMC_DDR_t_RCD - 3) << 3)
-/* 11,18(TRM) Min 80ns */
-#define DMC_DDR_t_RFC		(NS_TO_CLK(DDR_tRFC) + 1)
-#define DMC_DDR_schedule_RFC	((DMC_DDR_t_RFC - 3) << 5)
-/* 4, 5(TRM) Min 22.5ns */
-#define DMC_DDR_t_RP		(NS_TO_CLK(DDR_tRP) + 1)
-#define DMC_DDR_schedule_RP	((DMC_DDR_t_RP - 3) << 3)
-/* 3, Min 15ns */
-#define DMC_DDR_t_RRD		(NS_TO_CLK(DDR_tRRD) + 1)
-/* Min 15ns */
-#define DMC_DDR_t_WR		(NS_TO_CLK(DDR_tWR) + 1)
-#define DMC_DDR_t_WTR		2
-/* 1tck + tIS(1.5ns) */
-#define DMC_DDR_t_XP		2
-/* 17, Min 120ns */
-#define DMC_DDR_t_XSR		(NS_TO_CLK(DDR_tXSR) + 1)
-#define DMC_DDR_t_ESR		DMC_DDR_t_XSR
-/* TRM 2656 */
-#define DMC_DDR_REFRESH_PRD	(NS_TO_CLK(DDR_tREFRESH))
-/* 2b01 : mDDR */
-#define DMC_DDR_USER_CONFIG	1
-
-#ifndef __ASSEMBLY__
-enum s3c64xx_uarts_nr {
-	S3C64XX_UART0,
-	S3C64XX_UART1,
-	S3C64XX_UART2,
-};
-
-#include "s3c64x0.h"
-
-static inline s3c64xx_uart *s3c64xx_get_base_uart(enum s3c64xx_uarts_nr nr)
-{
-	return (s3c64xx_uart *)(ELFIN_UART_BASE + (nr * 0x400));
-}
-#endif
-
-#endif /*__S3C6400_H__*/
diff --git a/arch/arm/include/asm/arch-s3c64xx/s3c64x0.h b/arch/arm/include/asm/arch-s3c64xx/s3c64x0.h
deleted file mode 100644
index 0bbf1d0..0000000
--- a/arch/arm/include/asm/arch-s3c64xx/s3c64x0.h
+++ /dev/null
@@ -1,90 +0,0 @@
-/*
- * (C) Copyright 2003
- * David MÃŒller ELSOFT AG Switzerland. d.mueller@elsoft.ch
- *
- * (C) Copyright 2008
- * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/************************************************
- * NAME	    : S3C64XX.h
- * Version  : 31.3.2003
- *
- * common stuff for SAMSUNG S3C64XX SoC
- ************************************************/
-
-#ifndef __S3C64XX_H__
-#define __S3C64XX_H__
-
-#if defined(CONFIG_SYNC_MODE) && defined(CONFIG_S3C6400)
-#error CONFIG_SYNC_MODE unavailable on S3C6400, please, fix your configuration!
-#endif
-
-#include <asm/types.h>
-
-/* UART (see manual chapter 11) */
-typedef struct {
-	volatile u32	ULCON;
-	volatile u32	UCON;
-	volatile u32	UFCON;
-	volatile u32	UMCON;
-	volatile u32	UTRSTAT;
-	volatile u32	UERSTAT;
-	volatile u32	UFSTAT;
-	volatile u32	UMSTAT;
-#ifdef __BIG_ENDIAN
-	volatile u8	res1[3];
-	volatile u8	UTXH;
-	volatile u8	res2[3];
-	volatile u8	URXH;
-#else /* Little Endian */
-	volatile u8	UTXH;
-	volatile u8	res1[3];
-	volatile u8	URXH;
-	volatile u8	res2[3];
-#endif
-	volatile u32	UBRDIV;
-#ifdef __BIG_ENDIAN
-	volatile u8	res3[2];
-	volatile u16	UDIVSLOT;
-#else
-	volatile u16	UDIVSLOT;
-	volatile u8	res3[2];
-#endif
-} s3c64xx_uart;
-
-/* PWM TIMER (see manual chapter 10) */
-typedef struct {
-	volatile u32	TCNTB;
-	volatile u32	TCMPB;
-	volatile u32	TCNTO;
-} s3c64xx_timer;
-
-typedef struct {
-	volatile u32	TCFG0;
-	volatile u32	TCFG1;
-	volatile u32	TCON;
-	s3c64xx_timer	ch[4];
-	volatile u32	TCNTB4;
-	volatile u32	TCNTO4;
-} s3c64xx_timers;
-
-#endif /*__S3C64XX_H__*/
diff --git a/arch/arm/include/asm/arch-s5pc1xx/clk.h b/arch/arm/include/asm/arch-s5pc1xx/clk.h
deleted file mode 100644
index 4c389c1..0000000
--- a/arch/arm/include/asm/arch-s5pc1xx/clk.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/*
- * (C) Copyright 2009 Samsung Electronics
- * Minkyu Kang <mk7.kang@samsung.com>
- * Heungjun Kim <riverful.kim@samsung.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- */
-
-#ifndef __ASM_ARM_ARCH_CLK_H_
-#define __ASM_ARM_ARCH_CLK_H_
-
-#define APLL	0
-#define MPLL	1
-#define EPLL	2
-#define HPLL	3
-#define VPLL	4
-
-unsigned long get_pll_clk(int pllreg);
-unsigned long get_arm_clk(void);
-unsigned long get_pwm_clk(void);
-unsigned long get_uart_clk(int dev_index);
-
-#endif
diff --git a/arch/arm/include/asm/arch-s5pc1xx/clock.h b/arch/arm/include/asm/arch-s5pc1xx/clock.h
deleted file mode 100644
index 7b4eb89..0000000
--- a/arch/arm/include/asm/arch-s5pc1xx/clock.h
+++ /dev/null
@@ -1,94 +0,0 @@
-/*
- * (C) Copyright 2009 Samsung Electronics
- * Minkyu Kang <mk7.kang@samsung.com>
- * Heungjun Kim <riverful.kim@samsung.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- */
-
-#ifndef __ASM_ARM_ARCH_CLOCK_H_
-#define __ASM_ARM_ARCH_CLOCK_H_
-
-#ifndef __ASSEMBLY__
-struct s5pc100_clock {
-	unsigned int	apll_lock;
-	unsigned int	mpll_lock;
-	unsigned int	epll_lock;
-	unsigned int	hpll_lock;
-	unsigned char	res1[0xf0];
-	unsigned int	apll_con;
-	unsigned int	mpll_con;
-	unsigned int	epll_con;
-	unsigned int	hpll_con;
-	unsigned char	res2[0xf0];
-	unsigned int	src0;
-	unsigned int	src1;
-	unsigned int	src2;
-	unsigned int	src3;
-	unsigned char	res3[0xf0];
-	unsigned int	div0;
-	unsigned int	div1;
-	unsigned int	div2;
-	unsigned int	div3;
-	unsigned int	div4;
-	unsigned char	res4[0x1ec];
-	unsigned int	gate_d00;
-	unsigned int	gate_d01;
-	unsigned int	gate_d02;
-	unsigned char	res5[0x54];
-	unsigned int	gate_sclk0;
-	unsigned int	gate_sclk1;
-};
-
-struct s5pc110_clock {
-	unsigned int	apll_lock;
-	unsigned char	res1[0x4];
-	unsigned int	mpll_lock;
-	unsigned char	res2[0x4];
-	unsigned int	epll_lock;
-	unsigned char	res3[0xc];
-	unsigned int	vpll_lock;
-	unsigned char	res4[0xdc];
-	unsigned int	apll_con;
-	unsigned char	res5[0x4];
-	unsigned int	mpll_con;
-	unsigned char	res6[0x4];
-	unsigned int	epll_con;
-	unsigned char	res7[0xc];
-	unsigned int	vpll_con;
-	unsigned char	res8[0xdc];
-	unsigned int	src0;
-	unsigned int	src1;
-	unsigned int	src2;
-	unsigned int	src3;
-	unsigned char	res9[0xf0];
-	unsigned int	div0;
-	unsigned int	div1;
-	unsigned int	div2;
-	unsigned int	div3;
-	unsigned int	div4;
-	unsigned char	res10[0x1ec];
-	unsigned int	gate_d00;
-	unsigned int	gate_d01;
-	unsigned int	gate_d02;
-	unsigned char	res11[0x54];
-	unsigned int	gate_sclk0;
-	unsigned int	gate_sclk1;
-};
-#endif
-
-#endif
diff --git a/arch/arm/include/asm/arch-s5pc1xx/cpu.h b/arch/arm/include/asm/arch-s5pc1xx/cpu.h
deleted file mode 100644
index e74959f..0000000
--- a/arch/arm/include/asm/arch-s5pc1xx/cpu.h
+++ /dev/null
@@ -1,99 +0,0 @@
-/*
- * (C) Copyright 2009 Samsung Electronics
- * Minkyu Kang <mk7.kang@samsung.com>
- * Heungjun Kim <riverful.kim@samsung.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- */
-
-#ifndef _S5PC1XX_CPU_H
-#define _S5PC1XX_CPU_H
-
-#define S5PC1XX_ADDR_BASE	0xE0000000
-
-/* S5PC100 */
-#define S5PC100_PRO_ID		0xE0000000
-#define S5PC100_CLOCK_BASE	0xE0100000
-#define S5PC100_GPIO_BASE	0xE0300000
-#define S5PC100_VIC0_BASE	0xE4000000
-#define S5PC100_VIC1_BASE	0xE4100000
-#define S5PC100_VIC2_BASE	0xE4200000
-#define S5PC100_DMC_BASE	0xE6000000
-#define S5PC100_SROMC_BASE	0xE7000000
-#define S5PC100_ONENAND_BASE	0xE7100000
-#define S5PC100_PWMTIMER_BASE	0xEA000000
-#define S5PC100_WATCHDOG_BASE	0xEA200000
-#define S5PC100_UART_BASE	0xEC000000
-#define S5PC100_MMC_BASE	0xED800000
-
-/* S5PC110 */
-#define S5PC110_PRO_ID		0xE0000000
-#define S5PC110_CLOCK_BASE	0xE0100000
-#define S5PC110_GPIO_BASE	0xE0200000
-#define S5PC110_PWMTIMER_BASE	0xE2500000
-#define S5PC110_WATCHDOG_BASE	0xE2700000
-#define S5PC110_UART_BASE	0xE2900000
-#define S5PC110_SROMC_BASE	0xE8000000
-#define S5PC110_MMC_BASE	0xEB000000
-#define S5PC110_DMC0_BASE	0xF0000000
-#define S5PC110_DMC1_BASE	0xF1400000
-#define S5PC110_VIC0_BASE	0xF2000000
-#define S5PC110_VIC1_BASE	0xF2100000
-#define S5PC110_VIC2_BASE	0xF2200000
-#define S5PC110_VIC3_BASE	0xF2300000
-
-#ifndef __ASSEMBLY__
-#include <asm/io.h>
-/* CPU detection macros */
-extern unsigned int s5p_cpu_id;
-
-static inline void s5p_set_cpu_id(void)
-{
-	s5p_cpu_id = readl(S5PC100_PRO_ID);
-	s5p_cpu_id = 0xC000 | ((s5p_cpu_id & 0x00FFF000) >> 12);
-}
-
-#define IS_SAMSUNG_TYPE(type, id)			\
-static inline int cpu_is_##type(void)			\
-{							\
-	return s5p_cpu_id == id ? 1 : 0;		\
-}
-
-IS_SAMSUNG_TYPE(s5pc100, 0xc100)
-IS_SAMSUNG_TYPE(s5pc110, 0xc110)
-
-#define SAMSUNG_BASE(device, base)				\
-static inline unsigned int samsung_get_base_##device(void)	\
-{								\
-	if (cpu_is_s5pc100())					\
-		return S5PC100_##base;				\
-	else if (cpu_is_s5pc110())				\
-		return S5PC110_##base;				\
-	else							\
-		return 0;					\
-}
-
-SAMSUNG_BASE(clock, CLOCK_BASE)
-SAMSUNG_BASE(gpio, GPIO_BASE)
-SAMSUNG_BASE(pro_id, PRO_ID)
-SAMSUNG_BASE(mmc, MMC_BASE)
-SAMSUNG_BASE(sromc, SROMC_BASE)
-SAMSUNG_BASE(timer, PWMTIMER_BASE)
-SAMSUNG_BASE(uart, UART_BASE)
-#endif
-
-#endif	/* _S5PC1XX_CPU_H */
diff --git a/arch/arm/include/asm/arch-s5pc1xx/gpio.h b/arch/arm/include/asm/arch-s5pc1xx/gpio.h
deleted file mode 100644
index 2df33a6..0000000
--- a/arch/arm/include/asm/arch-s5pc1xx/gpio.h
+++ /dev/null
@@ -1,158 +0,0 @@
-/*
- * (C) Copyright 2009 Samsung Electronics
- * Minkyu Kang <mk7.kang@samsung.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __ASM_ARCH_GPIO_H
-#define __ASM_ARCH_GPIO_H
-
-#ifndef __ASSEMBLY__
-struct s5p_gpio_bank {
-	unsigned int	con;
-	unsigned int	dat;
-	unsigned int	pull;
-	unsigned int	drv;
-	unsigned int	pdn_con;
-	unsigned int	pdn_pull;
-	unsigned char	res1[8];
-};
-
-struct s5pc100_gpio {
-	struct s5p_gpio_bank a0;
-	struct s5p_gpio_bank a1;
-	struct s5p_gpio_bank b;
-	struct s5p_gpio_bank c;
-	struct s5p_gpio_bank d;
-	struct s5p_gpio_bank e0;
-	struct s5p_gpio_bank e1;
-	struct s5p_gpio_bank f0;
-	struct s5p_gpio_bank f1;
-	struct s5p_gpio_bank f2;
-	struct s5p_gpio_bank f3;
-	struct s5p_gpio_bank g0;
-	struct s5p_gpio_bank g1;
-	struct s5p_gpio_bank g2;
-	struct s5p_gpio_bank g3;
-	struct s5p_gpio_bank i;
-	struct s5p_gpio_bank j0;
-	struct s5p_gpio_bank j1;
-	struct s5p_gpio_bank j2;
-	struct s5p_gpio_bank j3;
-	struct s5p_gpio_bank j4;
-	struct s5p_gpio_bank k0;
-	struct s5p_gpio_bank k1;
-	struct s5p_gpio_bank k2;
-	struct s5p_gpio_bank k3;
-	struct s5p_gpio_bank l0;
-	struct s5p_gpio_bank l1;
-	struct s5p_gpio_bank l2;
-	struct s5p_gpio_bank l3;
-	struct s5p_gpio_bank l4;
-	struct s5p_gpio_bank h0;
-	struct s5p_gpio_bank h1;
-	struct s5p_gpio_bank h2;
-	struct s5p_gpio_bank h3;
-};
-
-struct s5pc110_gpio {
-	struct s5p_gpio_bank a0;
-	struct s5p_gpio_bank a1;
-	struct s5p_gpio_bank b;
-	struct s5p_gpio_bank c0;
-	struct s5p_gpio_bank c1;
-	struct s5p_gpio_bank d0;
-	struct s5p_gpio_bank d1;
-	struct s5p_gpio_bank e0;
-	struct s5p_gpio_bank e1;
-	struct s5p_gpio_bank f0;
-	struct s5p_gpio_bank f1;
-	struct s5p_gpio_bank f2;
-	struct s5p_gpio_bank f3;
-	struct s5p_gpio_bank g0;
-	struct s5p_gpio_bank g1;
-	struct s5p_gpio_bank g2;
-	struct s5p_gpio_bank g3;
-	struct s5p_gpio_bank i;
-	struct s5p_gpio_bank j0;
-	struct s5p_gpio_bank j1;
-	struct s5p_gpio_bank j2;
-	struct s5p_gpio_bank j3;
-	struct s5p_gpio_bank j4;
-	struct s5p_gpio_bank mp0_1;
-	struct s5p_gpio_bank mp0_2;
-	struct s5p_gpio_bank mp0_3;
-	struct s5p_gpio_bank mp0_4;
-	struct s5p_gpio_bank mp0_5;
-	struct s5p_gpio_bank mp0_6;
-	struct s5p_gpio_bank mp0_7;
-	struct s5p_gpio_bank mp1_0;
-	struct s5p_gpio_bank mp1_1;
-	struct s5p_gpio_bank mp1_2;
-	struct s5p_gpio_bank mp1_3;
-	struct s5p_gpio_bank mp1_4;
-	struct s5p_gpio_bank mp1_5;
-	struct s5p_gpio_bank mp1_6;
-	struct s5p_gpio_bank mp1_7;
-	struct s5p_gpio_bank mp1_8;
-	struct s5p_gpio_bank mp2_0;
-	struct s5p_gpio_bank mp2_1;
-	struct s5p_gpio_bank mp2_2;
-	struct s5p_gpio_bank mp2_3;
-	struct s5p_gpio_bank mp2_4;
-	struct s5p_gpio_bank mp2_5;
-	struct s5p_gpio_bank mp2_6;
-	struct s5p_gpio_bank mp2_7;
-	struct s5p_gpio_bank mp2_8;
-	struct s5p_gpio_bank res1[48];
-	struct s5p_gpio_bank h0;
-	struct s5p_gpio_bank h1;
-	struct s5p_gpio_bank h2;
-	struct s5p_gpio_bank h3;
-};
-
-/* functions */
-void gpio_cfg_pin(struct s5p_gpio_bank *bank, int gpio, int cfg);
-void gpio_direction_output(struct s5p_gpio_bank *bank, int gpio, int en);
-void gpio_direction_input(struct s5p_gpio_bank *bank, int gpio);
-void gpio_set_value(struct s5p_gpio_bank *bank, int gpio, int en);
-unsigned int gpio_get_value(struct s5p_gpio_bank *bank, int gpio);
-void gpio_set_pull(struct s5p_gpio_bank *bank, int gpio, int mode);
-void gpio_set_drv(struct s5p_gpio_bank *bank, int gpio, int mode);
-void gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode);
-#endif
-
-/* Pin configurations */
-#define GPIO_INPUT	0x0
-#define GPIO_OUTPUT	0x1
-#define GPIO_IRQ	0xf
-#define GPIO_FUNC(x)	(x)
-
-/* Pull mode */
-#define GPIO_PULL_NONE	0x0
-#define GPIO_PULL_DOWN	0x1
-#define GPIO_PULL_UP	0x2
-
-/* Drive Strength level */
-#define GPIO_DRV_1X	0x0
-#define GPIO_DRV_2X	0x1
-#define GPIO_DRV_3X	0x2
-#define GPIO_DRV_4X	0x3
-#define GPIO_DRV_FAST	0x0
-#define GPIO_DRV_SLOW	0x1
-
-#endif
diff --git a/arch/arm/include/asm/arch-s5pc1xx/mmc.h b/arch/arm/include/asm/arch-s5pc1xx/mmc.h
deleted file mode 100644
index 48de64d..0000000
--- a/arch/arm/include/asm/arch-s5pc1xx/mmc.h
+++ /dev/null
@@ -1,71 +0,0 @@
-/*
- * (C) Copyright 2009 SAMSUNG Electronics
- * Minkyu Kang <mk7.kang@samsung.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- *
- */
-
-#ifndef __ASM_ARCH_MMC_H_
-#define __ASM_ARCH_MMC_H_
-
-#ifndef __ASSEMBLY__
-struct s5p_mmc {
-	unsigned int	sysad;
-	unsigned short	blksize;
-	unsigned short	blkcnt;
-	unsigned int	argument;
-	unsigned short	trnmod;
-	unsigned short	cmdreg;
-	unsigned int	rspreg0;
-	unsigned int	rspreg1;
-	unsigned int	rspreg2;
-	unsigned int	rspreg3;
-	unsigned int	bdata;
-	unsigned int	prnsts;
-	unsigned char	hostctl;
-	unsigned char	pwrcon;
-	unsigned char	blkgap;
-	unsigned char	wakcon;
-	unsigned short	clkcon;
-	unsigned char	timeoutcon;
-	unsigned char	swrst;
-	unsigned int	norintsts;	/* errintsts */
-	unsigned int	norintstsen;	/* errintstsen */
-	unsigned int	norintsigen;	/* errintsigen */
-	unsigned short	acmd12errsts;
-	unsigned char	res1[2];
-	unsigned int	capareg;
-	unsigned char	res2[4];
-	unsigned int	maxcurr;
-	unsigned char	res3[0x34];
-	unsigned int	control2;
-	unsigned int	control3;
-	unsigned int	control4;
-	unsigned char	res4[0x6e];
-	unsigned short	hcver;
-	unsigned char	res5[0xFFF02];
-};
-
-struct mmc_host {
-	struct s5p_mmc *reg;
-	unsigned int version;	/* SDHCI spec. version */
-	unsigned int clock;	/* Current clock (MHz) */
-};
-
-int s5p_mmc_init(int dev_index, int bus_width);
-
-#endif	/* __ASSEMBLY__ */
-#endif
diff --git a/arch/arm/include/asm/arch-s5pc1xx/power.h b/arch/arm/include/asm/arch-s5pc1xx/power.h
deleted file mode 100644
index 57e2a2b..0000000
--- a/arch/arm/include/asm/arch-s5pc1xx/power.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * Copyright (c) 2009 Samsung Electronics
- * Kyungmin Park <kyungmin.park@samsung.com>
- * Minkyu Kang <mk7.kang@samsung.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- */
-
-#ifndef __ASM_ARM_ARCH_POWER_H_
-#define __ASM_ARM_ARCH_POWER_H_
-
-/*
- * Power control
- */
-#define S5PC100_OTHERS			0xE0108200
-#define S5PC100_RST_STAT		0xE0108300
-#define S5PC100_SLEEP_WAKEUP		(1 << 3)
-#define S5PC100_WAKEUP_STAT		0xE0108304
-#define S5PC100_INFORM0			0xE0108400
-
-#define S5PC110_RST_STAT		0xE010A000
-#define S5PC110_SLEEP_WAKEUP		(1 << 3)
-#define S5PC110_WAKEUP_STAT		0xE010C200
-#define S5PC110_OTHERS			0xE010E000
-#define S5PC110_USB_PHY_CON		0xE010E80C
-#define S5PC110_INFORM0			0xE010F000
-
-#endif
diff --git a/arch/arm/include/asm/arch-s5pc1xx/pwm.h b/arch/arm/include/asm/arch-s5pc1xx/pwm.h
deleted file mode 100644
index 0369968..0000000
--- a/arch/arm/include/asm/arch-s5pc1xx/pwm.h
+++ /dev/null
@@ -1,55 +0,0 @@
-/*
- * Copyright (C) 2009 Samsung Electronics
- * Kyungmin Park <kyungmin.park@samsung.com>
- * Minkyu Kang <mk7.kang@samsung.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __ASM_ARM_ARCH_PWM_H_
-#define __ASM_ARM_ARCH_PWM_H_
-
-/* Interval mode(Auto Reload) of PWM Timer 4 */
-#define TCON4_AUTO_RELOAD	(1 << 22)
-/* Update TCNTB4 */
-#define TCON4_UPDATE		(1 << 21)
-/* start bit of PWM Timer 4 */
-#define TCON4_START		(1 << 20)
-
-#ifndef __ASSEMBLY__
-struct s5p_timer {
-	unsigned int	tcfg0;
-	unsigned int	tcfg1;
-	unsigned int	tcon;
-	unsigned int	tcntb0;
-	unsigned int	tcmpb0;
-	unsigned int	tcnto0;
-	unsigned int	tcntb1;
-	unsigned int	tcmpb1;
-	unsigned int	tcnto1;
-	unsigned int	tcntb2;
-	unsigned int	tcmpb2;
-	unsigned int	tcnto2;
-	unsigned int	tcntb3;
-	unsigned int	res1;
-	unsigned int	tcnto3;
-	unsigned int	tcntb4;
-	unsigned int	tcnto4;
-	unsigned int	tintcstat;
-};
-#endif	/* __ASSEMBLY__ */
-
-#endif
diff --git a/arch/arm/include/asm/arch-s5pc1xx/smc.h b/arch/arm/include/asm/arch-s5pc1xx/smc.h
deleted file mode 100644
index 88f4ffe..0000000
--- a/arch/arm/include/asm/arch-s5pc1xx/smc.h
+++ /dev/null
@@ -1,53 +0,0 @@
-/*
- * (C) Copyright 2010 Samsung Electronics
- * Naveen Krishna Ch <ch.naveen@samsung.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- * Note: This file contains the register description for Memory subsystem
- * 	 (SROM, NAND Flash, OneNand, DDR, OneDRAM) on S5PC1XX.
- *
- * 	 Only SROMC is defined as of now
- */
-
-#ifndef __ASM_ARCH_SMC_H_
-#define __ASM_ARCH_SMC_H_
-
-#define SMC_DATA16_WIDTH(x)    (1<<((x*4)+0))
-#define SMC_BYTE_ADDR_MODE(x)  (1<<((x*4)+1))  /* 0-> Half-word base address*/
-						/* 1-> Byte base address*/
-#define SMC_WAIT_ENABLE(x)     (1<<((x*4)+2))
-#define SMC_BYTE_ENABLE(x)     (1<<((x*4)+3))
-
-#define SMC_BC_TACS(x) (x << 28) /* 0clk     address set-up */
-#define SMC_BC_TCOS(x) (x << 24) /* 4clk     chip selection set-up */
-#define SMC_BC_TACC(x) (x << 16) /* 14clk    access cycle */
-#define SMC_BC_TCOH(x) (x << 12) /* 1clk     chip selection hold */
-#define SMC_BC_TAH(x)  (x << 8)  /* 4clk     address holding time */
-#define SMC_BC_TACP(x) (x << 4)  /* 6clk     page mode access cycle */
-#define SMC_BC_PMC(x)  (x << 0)  /* normal(1data)page mode configuration */
-
-#ifndef __ASSEMBLY__
-struct s5pc1xx_smc {
-	unsigned int	bw;
-	unsigned int	bc[6];
-};
-#endif	/* __ASSEMBLY__ */
-
-/* Configure the Band Width and Bank Control Regs for required SROMC Bank */
-void s5pc1xx_config_sromc(u32 srom_bank, u32 smc_bw_conf, u32 smc_bc_conf);
-
-#endif /* __ASM_ARCH_SMC_H_ */
diff --git a/arch/arm/include/asm/arch-s5pc1xx/sys_proto.h b/arch/arm/include/asm/arch-s5pc1xx/sys_proto.h
deleted file mode 100644
index 3078aaf..0000000
--- a/arch/arm/include/asm/arch-s5pc1xx/sys_proto.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/*
- * Copyright (C) 2009 Samsung Electrnoics
- * Minkyu Kang <mk7.kang@samsung.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef _SYS_PROTO_H_
-#define _SYS_PROTO_H_
-
-u32 get_device_type(void);
-void invalidate_dcache(u32);
-void l2_cache_disable(void);
-void l2_cache_enable(void);
-
-#endif
diff --git a/arch/arm/include/asm/arch-s5pc1xx/uart.h b/arch/arm/include/asm/arch-s5pc1xx/uart.h
deleted file mode 100644
index 1c56739..0000000
--- a/arch/arm/include/asm/arch-s5pc1xx/uart.h
+++ /dev/null
@@ -1,58 +0,0 @@
-/*
- * (C) Copyright 2009 Samsung Electronics
- * Minkyu Kang <mk7.kang@samsung.com>
- * Heungjun Kim <riverful.kim@samsung.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- */
-
-#ifndef __ASM_ARCH_UART_H_
-#define __ASM_ARCH_UART_H_
-
-#ifndef __ASSEMBLY__
-/* baudrate rest value */
-union br_rest {
-	unsigned short	slot;		/* udivslot */
-	unsigned char	value;		/* ufracval */
-};
-
-struct s5p_uart {
-	unsigned int	ulcon;
-	unsigned int	ucon;
-	unsigned int	ufcon;
-	unsigned int	umcon;
-	unsigned int	utrstat;
-	unsigned int	uerstat;
-	unsigned int	ufstat;
-	unsigned int	umstat;
-	unsigned char	utxh;
-	unsigned char	res1[3];
-	unsigned char	urxh;
-	unsigned char	res2[3];
-	unsigned int	ubrdiv;
-	union br_rest	rest;
-	unsigned char	res3[0x3d0];
-};
-
-static inline int s5p_uart_divslot(void)
-{
-	return 1;
-}
-
-#endif	/* __ASSEMBLY__ */
-
-#endif
diff --git a/arch/arm/include/asm/arch-s5pc2xx/adc.h b/arch/arm/include/asm/arch-s5pc2xx/adc.h
deleted file mode 100644
index c0aa580..0000000
--- a/arch/arm/include/asm/arch-s5pc2xx/adc.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- *  Copyright (C) 2010 Samsung Electronics
- *  Minkyu Kang <mk7.kang@samsung.com>
- *  MyungJoo Ham <myungjoo.ham@samsung.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __ASM_ARM_ARCH_ADC_H_
-#define __ASM_ARM_ARCH_ADC_H_
-
-#ifndef __ASSEMBLY__
-struct s5p_adc {
-	unsigned int adccon;
-	unsigned int adctsc;
-	unsigned int adcdly;
-	unsigned int adcdat0;
-	unsigned int adcdat1;
-	unsigned int adcupdn;
-	unsigned int adcclrint;
-	unsigned int adcmux;
-	unsigned int adcclrintpndnup;
-};
-#endif
-
-#endif /* __ASM_ARM_ARCH_ADC_H_ */
diff --git a/arch/arm/include/asm/arch-s5pc2xx/clk.h b/arch/arm/include/asm/arch-s5pc2xx/clk.h
deleted file mode 100644
index 5a1cdf1..0000000
--- a/arch/arm/include/asm/arch-s5pc2xx/clk.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/*
- * (C) Copyright 2010 Samsung Electronics
- * Minkyu Kang <mk7.kang@samsung.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- */
-
-#ifndef __ASM_ARM_ARCH_CLK_H_
-#define __ASM_ARM_ARCH_CLK_H_
-
-#define APLL	0
-#define MPLL	1
-#define EPLL	2
-#define HPLL	3
-#define VPLL	4
-
-unsigned long get_pll_clk(int pllreg);
-unsigned long get_arm_clk(void);
-unsigned long get_pwm_clk(void);
-unsigned long get_uart_clk(int dev_index);
-
-#endif
diff --git a/arch/arm/include/asm/arch-s5pc2xx/clock.h b/arch/arm/include/asm/arch-s5pc2xx/clock.h
deleted file mode 100644
index 0ff8cf8..0000000
--- a/arch/arm/include/asm/arch-s5pc2xx/clock.h
+++ /dev/null
@@ -1,255 +0,0 @@
-/*
- * (C) Copyright 2010 Samsung Electronics
- * Minkyu Kang <mk7.kang@samsung.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- */
-
-#ifndef __ASM_ARM_ARCH_CLOCK_H_
-#define __ASM_ARM_ARCH_CLOCK_H_
-
-#ifndef __ASSEMBLY__
-struct s5pc210_clock {
-	unsigned char	res1[0x4200];
-	unsigned int	src_leftbus;
-	unsigned char	res2[0x1fc];
-	unsigned int	mux_stat_leftbus;
-	unsigned char	res4[0xfc];
-	unsigned int	div_leftbus;
-	unsigned char	res5[0xfc];
-	unsigned int	div_stat_leftbus;
-	unsigned char	res6[0x1fc];
-	unsigned int	gate_ip_leftbus;
-	unsigned char	res7[0x1fc];
-	unsigned int	clkout_leftbus;
-	unsigned int	clkout_leftbus_div_stat;
-	unsigned char	res8[0x37f8];
-	unsigned int	src_rightbus;
-	unsigned char	res9[0x1fc];
-	unsigned int	mux_stat_rightbus;
-	unsigned char	res10[0xfc];
-	unsigned int	div_rightbus;
-	unsigned char	res11[0xfc];
-	unsigned int	div_stat_rightbus;
-	unsigned char	res12[0x1fc];
-	unsigned int	gate_ip_rightbus;
-	unsigned char	res13[0x1fc];
-	unsigned int	clkout_rightbus;
-	unsigned int	clkout_rightbus_div_stat;
-	unsigned char	res14[0x3608];
-	unsigned int	epll_lock;
-	unsigned char	res15[0xc];
-	unsigned int	vpll_lock;
-	unsigned char	res16[0xec];
-	unsigned int	epll_con0;
-	unsigned int	epll_con1;
-	unsigned char	res17[0x8];
-	unsigned int	vpll_con0;
-	unsigned int	vpll_con1;
-	unsigned char	res18[0xe8];
-	unsigned int	src_top0;
-	unsigned int	src_top1;
-	unsigned char	res19[0x8];
-	unsigned int	src_cam;
-	unsigned int	src_tv;
-	unsigned int	src_mfc;
-	unsigned int	src_g3d;
-	unsigned int	src_image;
-	unsigned int	src_lcd0;
-	unsigned int	src_lcd1;
-	unsigned int	src_maudio;
-	unsigned int	src_fsys;
-	unsigned char	res20[0xc];
-	unsigned int	src_peril0;
-	unsigned int	src_peril1;
-	unsigned char	res21[0xb8];
-	unsigned int	src_mask_top;
-	unsigned char	res22[0xc];
-	unsigned int	src_mask_cam;
-	unsigned int	src_mask_tv;
-	unsigned char	res23[0xc];
-	unsigned int	src_mask_lcd0;
-	unsigned int	src_mask_lcd1;
-	unsigned int	src_mask_maudio;
-	unsigned int	src_mask_fsys;
-	unsigned char	res24[0xc];
-	unsigned int	src_mask_peril0;
-	unsigned int	src_mask_peril1;
-	unsigned char	res25[0xb8];
-	unsigned int	mux_stat_top;
-	unsigned char	res26[0x14];
-	unsigned int	mux_stat_mfc;
-	unsigned int	mux_stat_g3d;
-	unsigned int	mux_stat_image;
-	unsigned char	res27[0xdc];
-	unsigned int	div_top;
-	unsigned char	res28[0xc];
-	unsigned int	div_cam;
-	unsigned int	div_tv;
-	unsigned int	div_mfc;
-	unsigned int	div_g3d;
-	unsigned int	div_image;
-	unsigned int	div_lcd0;
-	unsigned int	div_lcd1;
-	unsigned int	div_maudio;
-	unsigned int	div_fsys0;
-	unsigned int	div_fsys1;
-	unsigned int	div_fsys2;
-	unsigned int	div_fsys3;
-	unsigned int	div_peril0;
-	unsigned int	div_peril1;
-	unsigned int	div_peril2;
-	unsigned int	div_peril3;
-	unsigned int	div_peril4;
-	unsigned int	div_peril5;
-	unsigned char	res29[0x18];
-	unsigned int	div2_ratio;
-	unsigned char	res30[0x8c];
-	unsigned int	div_stat_top;
-	unsigned char	res31[0xc];
-	unsigned int	div_stat_cam;
-	unsigned int	div_stat_tv;
-	unsigned int	div_stat_mfc;
-	unsigned int	div_stat_g3d;
-	unsigned int	div_stat_image;
-	unsigned int	div_stat_lcd0;
-	unsigned int	div_stat_lcd1;
-	unsigned int	div_stat_maudio;
-	unsigned int	div_stat_fsys0;
-	unsigned int	div_stat_fsys1;
-	unsigned int	div_stat_fsys2;
-	unsigned int	div_stat_fsys3;
-	unsigned int	div_stat_peril0;
-	unsigned int	div_stat_peril1;
-	unsigned int	div_stat_peril2;
-	unsigned int	div_stat_peril3;
-	unsigned int	div_stat_peril4;
-	unsigned int	div_stat_peril5;
-	unsigned char	res32[0x18];
-	unsigned int	div2_stat;
-	unsigned char	res33[0x29c];
-	unsigned int	gate_ip_cam;
-	unsigned int	gate_ip_tv;
-	unsigned int	gate_ip_mfc;
-	unsigned int	gate_ip_g3d;
-	unsigned int	gate_ip_image;
-	unsigned int	gate_ip_lcd0;
-	unsigned int	gate_ip_lcd1;
-	unsigned char	res34[0x4];
-	unsigned int	gate_ip_fsys;
-	unsigned char	res35[0x8];
-	unsigned int	gate_ip_gps;
-	unsigned int	gate_ip_peril;
-	unsigned char	res36[0xc];
-	unsigned int	gate_ip_perir;
-	unsigned char	res37[0xc];
-	unsigned int	gate_block;
-	unsigned char	res38[0x8c];
-	unsigned int	clkout_cmu_top;
-	unsigned int	clkout_cmu_top_div_stat;
-	unsigned char	res39[0x37f8];
-	unsigned int	src_dmc;
-	unsigned char	res40[0xfc];
-	unsigned int	src_mask_dmc;
-	unsigned char	res41[0xfc];
-	unsigned int	mux_stat_dmc;
-	unsigned char	res42[0xfc];
-	unsigned int	div_dmc0;
-	unsigned int	div_dmc1;
-	unsigned char	res43[0xf8];
-	unsigned int	div_stat_dmc0;
-	unsigned int	div_stat_dmc1;
-	unsigned char	res44[0x2f8];
-	unsigned int	gate_ip_dmc;
-	unsigned char	res45[0xfc];
-	unsigned int	clkout_cmu_dmc;
-	unsigned int	clkout_cmu_dmc_div_stat;
-	unsigned char	res46[0x5f8];
-	unsigned int	dcgidx_map0;
-	unsigned int	dcgidx_map1;
-	unsigned int	dcgidx_map2;
-	unsigned char	res47[0x14];
-	unsigned int	dcgperf_map0;
-	unsigned int	dcgperf_map1;
-	unsigned char	res48[0x18];
-	unsigned int	dvcidx_map;
-	unsigned char	res49[0x1c];
-	unsigned int	freq_cpu;
-	unsigned int	freq_dpm;
-	unsigned char	res50[0x18];
-	unsigned int	dvsemclk_en;
-	unsigned int	maxperf;
-	unsigned char	res51[0x2f78];
-	unsigned int	apll_lock;
-	unsigned char	res52[0x4];
-	unsigned int	mpll_lock;
-	unsigned char	res53[0xf4];
-	unsigned int	apll_con0;
-	unsigned int	apll_con1;
-	unsigned int	mpll_con0;
-	unsigned int	mpll_con1;
-	unsigned char	res54[0xf0];
-	unsigned int	src_cpu;
-	unsigned char	res55[0x1fc];
-	unsigned int	mux_stat_cpu;
-	unsigned char	res56[0xfc];
-	unsigned int	div_cpu0;
-	unsigned int	div_cpu1;
-	unsigned char	res57[0xf8];
-	unsigned int	div_stat_cpu0;
-	unsigned int	div_stat_cpu1;
-	unsigned char	res58[0x3f8];
-	unsigned int	clkout_cmu_cpu;
-	unsigned int	clkout_cmu_cpu_div_stat;
-	unsigned char	res59[0x5f8];
-	unsigned int	armclk_stopctrl;
-	unsigned int	atclk_stopctrl;
-	unsigned char	res60[0x8];
-	unsigned int	parityfail_status;
-	unsigned int	parityfail_clear;
-	unsigned char	res61[0xe8];
-	unsigned int	apll_con0_l8;
-	unsigned int	apll_con0_l7;
-	unsigned int	apll_con0_l6;
-	unsigned int	apll_con0_l5;
-	unsigned int	apll_con0_l4;
-	unsigned int	apll_con0_l3;
-	unsigned int	apll_con0_l2;
-	unsigned int	apll_con0_l1;
-	unsigned int	iem_control;
-	unsigned char	res62[0xdc];
-	unsigned int	apll_con1_l8;
-	unsigned int	apll_con1_l7;
-	unsigned int	apll_con1_l6;
-	unsigned int	apll_con1_l5;
-	unsigned int	apll_con1_l4;
-	unsigned int	apll_con1_l3;
-	unsigned int	apll_con1_l2;
-	unsigned int	apll_con1_l1;
-	unsigned char	res63[0xe0];
-	unsigned int	div_iem_l8;
-	unsigned int	div_iem_l7;
-	unsigned int	div_iem_l6;
-	unsigned int	div_iem_l5;
-	unsigned int	div_iem_l4;
-	unsigned int	div_iem_l3;
-	unsigned int	div_iem_l2;
-	unsigned int	div_iem_l1;
-};
-#endif
-
-#endif
diff --git a/arch/arm/include/asm/arch-s5pc2xx/cpu.h b/arch/arm/include/asm/arch-s5pc2xx/cpu.h
deleted file mode 100644
index d56ee80..0000000
--- a/arch/arm/include/asm/arch-s5pc2xx/cpu.h
+++ /dev/null
@@ -1,103 +0,0 @@
-/*
- * (C) Copyright 2010 Samsung Electronics
- * Minkyu Kang <mk7.kang@samsung.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- */
-
-#ifndef _S5PC2XX_CPU_H
-#define _S5PC2XX_CPU_H
-
-#define S5PC2XX_ADDR_BASE	0x10000000
-
-/* S5PC210 */
-#define S5PC210_GPIO_PART3_BASE	0x03860000
-#define S5PC210_PRO_ID		0x10000000
-#define S5PC210_POWER_BASE	0x10020000
-#define S5PC210_SWRESET		0x10020400
-#define S5PC210_CLOCK_BASE	0x10030000
-#define S5PC210_SYSTIMER_BASE	0x10050000
-#define S5PC210_WATCHDOG_BASE	0x10060000
-#define S5PC210_MIU_BASE	0x10600000
-#define S5PC210_DMC0_BASE	0x10400000
-#define S5PC210_DMC1_BASE	0x10410000
-#define S5PC210_GPIO_PART2_BASE	0x11000000
-#define S5PC210_GPIO_PART1_BASE	0x11400000
-#define S5PC210_FIMD_BASE	0x11C00000
-#define S5PC210_USBOTG_BASE	0x12480000
-#define S5PC210_MMC_BASE	0x12510000
-#define S5PC210_SROMC_BASE	0x12570000
-#define S5PC210_USBPHY_BASE	0x125B0000
-#define S5PC210_UART_BASE	0x13800000
-#define S5PC210_ADC_BASE	0x13910000
-#define S5PC210_PWMTIMER_BASE	0x139D0000
-#define S5PC210_MODEM_BASE	0x13A00000
-
-#ifndef __ASSEMBLY__
-#include <asm/io.h>
-/* CPU detection macros */
-extern unsigned int s5p_cpu_id;
-
-static inline void s5p_set_cpu_id(void)
-{
-	s5p_cpu_id = readl(S5PC210_PRO_ID);
-	s5p_cpu_id = (0xC000 | ((s5p_cpu_id & 0x00FFF000) >> 12));
-
-	/*
-	 * 0xC200: S5PC210 EVT0
-	 * 0xC210: S5PC210 EVT1
-	 */
-	if (s5p_cpu_id == 0xC200)
-		s5p_cpu_id |= 0x10;
-}
-
-#define IS_SAMSUNG_TYPE(type, id)			\
-static inline int cpu_is_##type(void)			\
-{							\
-	return s5p_cpu_id == id ? 1 : 0;		\
-}
-
-IS_SAMSUNG_TYPE(s5pc210, 0xc210)
-
-#define SAMSUNG_BASE(device, base)				\
-static inline unsigned int samsung_get_base_##device(void)	\
-{								\
-	if (cpu_is_s5pc210())					\
-		return S5PC210_##base;				\
-	else							\
-		return 0;					\
-}
-
-SAMSUNG_BASE(adc, ADC_BASE)
-SAMSUNG_BASE(clock, CLOCK_BASE)
-SAMSUNG_BASE(fimd, FIMD_BASE)
-SAMSUNG_BASE(gpio_part1, GPIO_PART1_BASE)
-SAMSUNG_BASE(gpio_part2, GPIO_PART2_BASE)
-SAMSUNG_BASE(gpio_part3, GPIO_PART3_BASE)
-SAMSUNG_BASE(pro_id, PRO_ID)
-SAMSUNG_BASE(mmc, MMC_BASE)
-SAMSUNG_BASE(modem, MODEM_BASE)
-SAMSUNG_BASE(sromc, SROMC_BASE)
-SAMSUNG_BASE(swreset, SWRESET)
-SAMSUNG_BASE(timer, PWMTIMER_BASE)
-SAMSUNG_BASE(uart, UART_BASE)
-SAMSUNG_BASE(usb_phy, USBPHY_BASE)
-SAMSUNG_BASE(usb_otg, USBOTG_BASE)
-SAMSUNG_BASE(watchdog, WATCHDOG_BASE)
-#endif
-
-#endif	/* _S5PC2XX_CPU_H */
diff --git a/arch/arm/include/asm/arch-s5pc2xx/gpio.h b/arch/arm/include/asm/arch-s5pc2xx/gpio.h
deleted file mode 100644
index 05e5b3e..0000000
--- a/arch/arm/include/asm/arch-s5pc2xx/gpio.h
+++ /dev/null
@@ -1,112 +0,0 @@
-/*
- * (C) Copyright 2010 Samsung Electronics
- * Minkyu Kang <mk7.kang@samsung.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __ASM_ARCH_GPIO_H
-#define __ASM_ARCH_GPIO_H
-
-#ifndef __ASSEMBLY__
-struct s5p_gpio_bank {
-	unsigned int	con;
-	unsigned int	dat;
-	unsigned int	pull;
-	unsigned int	drv;
-	unsigned int	pdn_con;
-	unsigned int	pdn_pull;
-	unsigned char	res1[8];
-};
-
-struct s5pc210_gpio_part1 {
-	struct s5p_gpio_bank a0;
-	struct s5p_gpio_bank a1;
-	struct s5p_gpio_bank b;
-	struct s5p_gpio_bank c0;
-	struct s5p_gpio_bank c1;
-	struct s5p_gpio_bank d0;
-	struct s5p_gpio_bank d1;
-	struct s5p_gpio_bank e0;
-	struct s5p_gpio_bank e1;
-	struct s5p_gpio_bank e2;
-	struct s5p_gpio_bank e3;
-	struct s5p_gpio_bank e4;
-	struct s5p_gpio_bank f0;
-	struct s5p_gpio_bank f1;
-	struct s5p_gpio_bank f2;
-	struct s5p_gpio_bank f3;
-};
-
-struct s5pc210_gpio_part2 {
-	struct s5p_gpio_bank j0;
-	struct s5p_gpio_bank j1;
-	struct s5p_gpio_bank k0;
-	struct s5p_gpio_bank k1;
-	struct s5p_gpio_bank k2;
-	struct s5p_gpio_bank k3;
-	struct s5p_gpio_bank l0;
-	struct s5p_gpio_bank l1;
-	struct s5p_gpio_bank l2;
-	struct s5p_gpio_bank y0;
-	struct s5p_gpio_bank y1;
-	struct s5p_gpio_bank y2;
-	struct s5p_gpio_bank y3;
-	struct s5p_gpio_bank y4;
-	struct s5p_gpio_bank y5;
-	struct s5p_gpio_bank y6;
-	struct s5p_gpio_bank res1[80];
-	struct s5p_gpio_bank x0;
-	struct s5p_gpio_bank x1;
-	struct s5p_gpio_bank x2;
-	struct s5p_gpio_bank x3;
-};
-
-struct s5pc210_gpio_part3 {
-	struct s5p_gpio_bank z;
-};
-
-/* functions */
-void gpio_cfg_pin(struct s5p_gpio_bank *bank, int gpio, int cfg);
-void gpio_direction_output(struct s5p_gpio_bank *bank, int gpio, int en);
-void gpio_direction_input(struct s5p_gpio_bank *bank, int gpio);
-void gpio_set_value(struct s5p_gpio_bank *bank, int gpio, int en);
-unsigned int gpio_get_value(struct s5p_gpio_bank *bank, int gpio);
-void gpio_set_pull(struct s5p_gpio_bank *bank, int gpio, int mode);
-void gpio_set_drv(struct s5p_gpio_bank *bank, int gpio, int mode);
-void gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode);
-#endif
-
-/* Pin configurations */
-#define GPIO_INPUT	0x0
-#define GPIO_OUTPUT	0x1
-#define GPIO_IRQ	0xf
-#define GPIO_FUNC(x)	(x)
-
-/* Pull mode */
-#define GPIO_PULL_NONE	0x0
-#define GPIO_PULL_DOWN	0x1
-#define GPIO_PULL_UP	0x2
-
-/* Drive Strength level */
-#define GPIO_DRV_1X	0x0
-#define GPIO_DRV_2X	0x1
-#define GPIO_DRV_3X	0x2
-#define GPIO_DRV_4X	0x3
-#define GPIO_DRV_FAST	0x0
-#define GPIO_DRV_SLOW	0x1
-
-#endif
diff --git a/arch/arm/include/asm/arch-s5pc2xx/mmc.h b/arch/arm/include/asm/arch-s5pc2xx/mmc.h
deleted file mode 100644
index 528150d..0000000
--- a/arch/arm/include/asm/arch-s5pc2xx/mmc.h
+++ /dev/null
@@ -1,71 +0,0 @@
-/*
- * (C) Copyright 2009 SAMSUNG Electronics
- * Minkyu Kang <mk7.kang@samsung.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- *
- */
-
-#ifndef __ASM_ARCH_MMC_H_
-#define __ASM_ARCH_MMC_H_
-
-#ifndef __ASSEMBLY__
-struct s5p_mmc {
-	unsigned int	sysad;
-	unsigned short	blksize;
-	unsigned short	blkcnt;
-	unsigned int	argument;
-	unsigned short	trnmod;
-	unsigned short	cmdreg;
-	unsigned int	rspreg0;
-	unsigned int	rspreg1;
-	unsigned int	rspreg2;
-	unsigned int	rspreg3;
-	unsigned int	bdata;
-	unsigned int	prnsts;
-	unsigned char	hostctl;
-	unsigned char	pwrcon;
-	unsigned char	blkgap;
-	unsigned char	wakcon;
-	unsigned short	clkcon;
-	unsigned char	timeoutcon;
-	unsigned char	swrst;
-	unsigned int	norintsts;	/* errintsts */
-	unsigned int	norintstsen;	/* errintstsen */
-	unsigned int	norintsigen;	/* errintsigen */
-	unsigned short	acmd12errsts;
-	unsigned char	res1[2];
-	unsigned int	capareg;
-	unsigned char	res2[4];
-	unsigned int	maxcurr;
-	unsigned char	res3[0x34];
-	unsigned int	control2;
-	unsigned int	control3;
-	unsigned int	control4;
-	unsigned char	res4[0x6e];
-	unsigned short	hcver;
-	unsigned char	res5[0xFF02];
-};
-
-struct mmc_host {
-	struct s5p_mmc *reg;
-	unsigned int version;	/* SDHCI spec. version */
-	unsigned int clock;	/* Current clock (MHz) */
-};
-
-int s5p_mmc_init(int dev_index, int bus_width);
-
-#endif	/* __ASSEMBLY__ */
-#endif
diff --git a/arch/arm/include/asm/arch-s5pc2xx/pwm.h b/arch/arm/include/asm/arch-s5pc2xx/pwm.h
deleted file mode 100644
index 0369968..0000000
--- a/arch/arm/include/asm/arch-s5pc2xx/pwm.h
+++ /dev/null
@@ -1,55 +0,0 @@
-/*
- * Copyright (C) 2009 Samsung Electronics
- * Kyungmin Park <kyungmin.park@samsung.com>
- * Minkyu Kang <mk7.kang@samsung.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __ASM_ARM_ARCH_PWM_H_
-#define __ASM_ARM_ARCH_PWM_H_
-
-/* Interval mode(Auto Reload) of PWM Timer 4 */
-#define TCON4_AUTO_RELOAD	(1 << 22)
-/* Update TCNTB4 */
-#define TCON4_UPDATE		(1 << 21)
-/* start bit of PWM Timer 4 */
-#define TCON4_START		(1 << 20)
-
-#ifndef __ASSEMBLY__
-struct s5p_timer {
-	unsigned int	tcfg0;
-	unsigned int	tcfg1;
-	unsigned int	tcon;
-	unsigned int	tcntb0;
-	unsigned int	tcmpb0;
-	unsigned int	tcnto0;
-	unsigned int	tcntb1;
-	unsigned int	tcmpb1;
-	unsigned int	tcnto1;
-	unsigned int	tcntb2;
-	unsigned int	tcmpb2;
-	unsigned int	tcnto2;
-	unsigned int	tcntb3;
-	unsigned int	res1;
-	unsigned int	tcnto3;
-	unsigned int	tcntb4;
-	unsigned int	tcnto4;
-	unsigned int	tintcstat;
-};
-#endif	/* __ASSEMBLY__ */
-
-#endif
diff --git a/arch/arm/include/asm/arch-s5pc2xx/sys_proto.h b/arch/arm/include/asm/arch-s5pc2xx/sys_proto.h
deleted file mode 100644
index 11f1636..0000000
--- a/arch/arm/include/asm/arch-s5pc2xx/sys_proto.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/*
- * Copyright (C) 2010 Samsung Electrnoics
- * Minkyu Kang <mk7.kang@samsung.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef _SYS_PROTO_H_
-#define _SYS_PROTO_H_
-
-u32 get_device_type(void);
-void invalidate_dcache(u32);
-void l2_cache_disable(void);
-void l2_cache_enable(void);
-
-#endif
diff --git a/arch/arm/include/asm/arch-s5pc2xx/uart.h b/arch/arm/include/asm/arch-s5pc2xx/uart.h
deleted file mode 100644
index 6cc68df..0000000
--- a/arch/arm/include/asm/arch-s5pc2xx/uart.h
+++ /dev/null
@@ -1,58 +0,0 @@
-/*
- * (C) Copyright 2009 Samsung Electronics
- * Minkyu Kang <mk7.kang@samsung.com>
- * Heungjun Kim <riverful.kim@samsung.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- */
-
-#ifndef __ASM_ARCH_UART_H_
-#define __ASM_ARCH_UART_H_
-
-#ifndef __ASSEMBLY__
-/* baudrate rest value */
-union br_rest {
-	unsigned short	slot;		/* udivslot */
-	unsigned char	value;		/* ufracval */
-};
-
-struct s5p_uart {
-	unsigned int	ulcon;
-	unsigned int	ucon;
-	unsigned int	ufcon;
-	unsigned int	umcon;
-	unsigned int	utrstat;
-	unsigned int	uerstat;
-	unsigned int	ufstat;
-	unsigned int	umstat;
-	unsigned char	utxh;
-	unsigned char	res1[3];
-	unsigned char	urxh;
-	unsigned char	res2[3];
-	unsigned int	ubrdiv;
-	union br_rest	rest;
-	unsigned char	res3[0xffd0];
-};
-
-static inline int s5p_uart_divslot(void)
-{
-	return 0;
-}
-
-#endif	/* __ASSEMBLY__ */
-
-#endif
diff --git a/arch/arm/include/asm/arch-sa1100/bitfield.h b/arch/arm/include/asm/arch-sa1100/bitfield.h
deleted file mode 100644
index 104a21c..0000000
--- a/arch/arm/include/asm/arch-sa1100/bitfield.h
+++ /dev/null
@@ -1,112 +0,0 @@
-/*
- *	FILE		bitfield.h
- *
- *	Version		1.1
- *	Author		Copyright (c) Marc A. Viredaz, 1998
- *			DEC Western Research Laboratory, Palo Alto, CA
- *	Date		April 1998 (April 1997)
- *	System		Advanced RISC Machine (ARM)
- *	Language	C or ARM Assembly
- *	Purpose		Definition of macros to operate on bit fields.
- */
-
-
-#ifndef __BITFIELD_H
-#define __BITFIELD_H
-
-#ifndef __ASSEMBLY__
-#define UData(Data)	((unsigned long) (Data))
-#else
-#define UData(Data)	(Data)
-#endif
-
-
-/*
- * MACRO: Fld
- *
- * Purpose
- *    The macro "Fld" encodes a bit field, given its size and its shift value
- *    with respect to bit 0.
- *
- * Note
- *    A more intuitive way to encode bit fields would have been to use their
- *    mask. However, extracting size and shift value information from a bit
- *    field's mask is cumbersome and might break the assembler (255-character
- *    line-size limit).
- *
- * Input
- *    Size		Size of the bit field, in number of bits.
- *    Shft		Shift value of the bit field with respect to bit 0.
- *
- * Output
- *    Fld		Encoded bit field.
- */
-
-#define Fld(Size, Shft)	(((Size) << 16) + (Shft))
-
-
-/*
- * MACROS: FSize, FShft, FMsk, FAlnMsk, F1stBit
- *
- * Purpose
- *    The macros "FSize", "FShft", "FMsk", "FAlnMsk", and "F1stBit" return
- *    the size, shift value, mask, aligned mask, and first bit of a
- *    bit field.
- *
- * Input
- *    Field		Encoded bit field (using the macro "Fld").
- *
- * Output
- *    FSize		Size of the bit field, in number of bits.
- *    FShft		Shift value of the bit field with respect to bit 0.
- *    FMsk		Mask for the bit field.
- *    FAlnMsk		Mask for the bit field, aligned on bit 0.
- *    F1stBit		First bit of the bit field.
- */
-
-#define FSize(Field)	((Field) >> 16)
-#define FShft(Field)	((Field) & 0x0000FFFF)
-#define FMsk(Field)	(((UData (1) << FSize (Field)) - 1) << FShft (Field))
-#define FAlnMsk(Field)	((UData (1) << FSize (Field)) - 1)
-#define F1stBit(Field)	(UData (1) << FShft (Field))
-
-
-/*
- * MACRO: FInsrt
- *
- * Purpose
- *    The macro "FInsrt" inserts a value into a bit field by shifting the
- *    former appropriately.
- *
- * Input
- *    Value		Bit-field value.
- *    Field		Encoded bit field (using the macro "Fld").
- *
- * Output
- *    FInsrt		Bit-field value positioned appropriately.
- */
-
-#define FInsrt(Value, Field) \
-			(UData (Value) << FShft (Field))
-
-
-/*
- * MACRO: FExtr
- *
- * Purpose
- *    The macro "FExtr" extracts the value of a bit field by masking and
- *    shifting it appropriately.
- *
- * Input
- *    Data		Data containing the bit-field to be extracted.
- *    Field		Encoded bit field (using the macro "Fld").
- *
- * Output
- *    FExtr		Bit-field value.
- */
-
-#define FExtr(Data, Field) \
-			((UData (Data) >> FShft (Field)) & FAlnMsk (Field))
-
-
-#endif /* __BITFIELD_H */
diff --git a/arch/arm/include/asm/arch-spear/hardware.h b/arch/arm/include/asm/arch-spear/hardware.h
deleted file mode 100644
index 818f36c..0000000
--- a/arch/arm/include/asm/arch-spear/hardware.h
+++ /dev/null
@@ -1,66 +0,0 @@
-/*
- * (C) Copyright 2009
- * Vipin Kumar, STMicroelectronics, <vipin.kumar@st.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef _ASM_ARCH_HARDWARE_H
-#define _ASM_ARCH_HARDWARE_H
-
-#define CONFIG_SYS_USBD_BASE			(0xE1100000)
-#define CONFIG_SYS_PLUG_BASE			(0xE1200000)
-#define CONFIG_SYS_FIFO_BASE			(0xE1000800)
-#define CONFIG_SYS_SMI_BASE			(0xFC000000)
-#define CONFIG_SPEAR_SYSCNTLBASE		(0xFCA00000)
-#define CONFIG_SPEAR_TIMERBASE			(0xFC800000)
-#define CONFIG_SPEAR_MISCBASE			(0xFCA80000)
-
-#define CONFIG_SYS_NAND_CLE			(1 << 16)
-#define CONFIG_SYS_NAND_ALE			(1 << 17)
-
-#if defined(CONFIG_SPEAR600)
-#define CONFIG_SYS_I2C_BASE			(0xD0200000)
-#define CONFIG_SPEAR_FSMCBASE			(0xD1800000)
-
-#elif defined(CONFIG_SPEAR300)
-#define CONFIG_SYS_I2C_BASE			(0xD0180000)
-#define CONFIG_SPEAR_FSMCBASE			(0x94000000)
-
-#elif defined(CONFIG_SPEAR310)
-#define CONFIG_SYS_I2C_BASE			(0xD0180000)
-#define CONFIG_SPEAR_FSMCBASE			(0x44000000)
-
-#undef CONFIG_SYS_NAND_CLE
-#undef CONFIG_SYS_NAND_ALE
-#define CONFIG_SYS_NAND_CLE			(1 << 17)
-#define CONFIG_SYS_NAND_ALE			(1 << 16)
-
-#define CONFIG_SPEAR_EMIBASE			(0x4F000000)
-#define CONFIG_SPEAR_RASBASE			(0xB4000000)
-
-#elif defined(CONFIG_SPEAR320)
-#define CONFIG_SYS_I2C_BASE			(0xD0180000)
-#define CONFIG_SPEAR_FSMCBASE			(0x4C000000)
-
-#define CONFIG_SPEAR_EMIBASE			(0x40000000)
-#define CONFIG_SPEAR_RASBASE			(0xB3000000)
-
-#endif
-#endif /* _ASM_ARCH_HARDWARE_H */
diff --git a/arch/arm/include/asm/arch-spear/spr_defs.h b/arch/arm/include/asm/arch-spear/spr_defs.h
deleted file mode 100644
index fa8412c..0000000
--- a/arch/arm/include/asm/arch-spear/spr_defs.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/*
- * (C) Copyright 2009
- * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __SPR_DEFS_H__
-#define __SPR_DEFS_H__
-
-extern int spear_board_init(ulong);
-extern void setfreq(unsigned int, unsigned int);
-extern unsigned int setfreq_sz;
-
-struct chip_data {
-	int cpufreq;
-	int dramfreq;
-	int dramtype;
-	uchar version[32];
-};
-
-/* HW mac id in i2c memory definitions */
-#define MAGIC_OFF	0x0
-#define MAGIC_LEN	0x2
-#define MAGIC_BYTE0	0x55
-#define MAGIC_BYTE1	0xAA
-#define MAC_OFF		0x2
-#define MAC_LEN		0x6
-
-#endif
diff --git a/arch/arm/include/asm/arch-spear/spr_emi.h b/arch/arm/include/asm/arch-spear/spr_emi.h
deleted file mode 100644
index c1f1c2a..0000000
--- a/arch/arm/include/asm/arch-spear/spr_emi.h
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * (C) Copyright 2009
- * Ryan CHEN, ST Micoelectronics, ryan.chen@st.com
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __SPEAR_EMI_H__
-#define __SPEAR_EMI_H__
-
-#ifdef CONFIG_SPEAR_EMI
-
-struct emi_bank_regs {
-	u32 tap;
-	u32 tsdp;
-	u32 tdpw;
-	u32 tdpr;
-	u32 tdcs;
-	u32 control;
-};
-
-struct emi_regs {
-	struct emi_bank_regs bank_regs[CONFIG_SYS_MAX_FLASH_BANKS];
-	u32 tout;
-	u32 ack;
-	u32 irq;
-};
-
-#define EMI_ACKMSK		0x40
-
-/* control register definitions */
-#define EMI_CNTL_ENBBYTEW	(1 << 2)
-#define EMI_CNTL_ENBBYTER	(1 << 3)
-#define EMI_CNTL_ENBBYTERW	(EMI_CNTL_ENBBYTER | EMI_CNTL_ENBBYTEW)
-
-#endif
-
-#endif
diff --git a/arch/arm/include/asm/arch-spear/spr_gpt.h b/arch/arm/include/asm/arch-spear/spr_gpt.h
deleted file mode 100644
index 965b5ab..0000000
--- a/arch/arm/include/asm/arch-spear/spr_gpt.h
+++ /dev/null
@@ -1,85 +0,0 @@
-/*
- * (C) Copyright 2009
- * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef _SPR_GPT_H
-#define _SPR_GPT_H
-
-struct gpt_regs {
-	u8 reserved[0x80];
-	u32 control;
-	u32 status;
-	u32 compare;
-	u32 count;
-	u32 capture_re;
-	u32 capture_fe;
-};
-
-/*
- * TIMER_CONTROL register settings
- */
-
-#define GPT_PRESCALER_MASK		0x000F
-#define GPT_PRESCALER_1			0x0000
-#define GPT_PRESCALER_2 		0x0001
-#define GPT_PRESCALER_4 		0x0002
-#define GPT_PRESCALER_8 		0x0003
-#define GPT_PRESCALER_16		0x0004
-#define GPT_PRESCALER_32		0x0005
-#define GPT_PRESCALER_64		0x0006
-#define GPT_PRESCALER_128		0x0007
-#define GPT_PRESCALER_256		0x0008
-
-#define GPT_MODE_SINGLE_SHOT		0x0010
-#define GPT_MODE_AUTO_RELOAD		0x0000
-
-#define GPT_ENABLE			0x0020
-
-#define GPT_CAPT_MODE_MASK		0x00C0
-#define GPT_CAPT_MODE_NONE		0x0000
-#define GPT_CAPT_MODE_RE		0x0040
-#define GPT_CAPT_MODE_FE		0x0080
-#define GPT_CAPT_MODE_BOTH		0x00C0
-
-#define GPT_INT_MATCH			0x0100
-#define GPT_INT_FE			0x0200
-#define GPT_INT_RE			0x0400
-
-/*
- * TIMER_STATUS register settings
- */
-
-#define GPT_STS_MATCH			0x0001
-#define GPT_STS_FE			0x0002
-#define GPT_STS_RE			0x0004
-
-/*
- * TIMER_COMPARE register settings
- */
-
-#define GPT_FREE_RUNNING		0xFFFF
-
-/* Timer, HZ specific defines */
-#define CONFIG_SPEAR_HZ			(1000)
-#define CONFIG_SPEAR_HZ_CLOCK		(8300000)
-
-#endif
diff --git a/arch/arm/include/asm/arch-spear/spr_i2c.h b/arch/arm/include/asm/arch-spear/spr_i2c.h
deleted file mode 100644
index 7521ebc..0000000
--- a/arch/arm/include/asm/arch-spear/spr_i2c.h
+++ /dev/null
@@ -1,146 +0,0 @@
-/*
- * (C) Copyright 2009
- * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __SPR_I2C_H_
-#define __SPR_I2C_H_
-
-struct i2c_regs {
-	u32 ic_con;
-	u32 ic_tar;
-	u32 ic_sar;
-	u32 ic_hs_maddr;
-	u32 ic_cmd_data;
-	u32 ic_ss_scl_hcnt;
-	u32 ic_ss_scl_lcnt;
-	u32 ic_fs_scl_hcnt;
-	u32 ic_fs_scl_lcnt;
-	u32 ic_hs_scl_hcnt;
-	u32 ic_hs_scl_lcnt;
-	u32 ic_intr_stat;
-	u32 ic_intr_mask;
-	u32 ic_raw_intr_stat;
-	u32 ic_rx_tl;
-	u32 ic_tx_tl;
-	u32 ic_clr_intr;
-	u32 ic_clr_rx_under;
-	u32 ic_clr_rx_over;
-	u32 ic_clr_tx_over;
-	u32 ic_clr_rd_req;
-	u32 ic_clr_tx_abrt;
-	u32 ic_clr_rx_done;
-	u32 ic_clr_activity;
-	u32 ic_clr_stop_det;
-	u32 ic_clr_start_det;
-	u32 ic_clr_gen_call;
-	u32 ic_enable;
-	u32 ic_status;
-	u32 ic_txflr;
-	u32 ix_rxflr;
-	u32 reserved_1;
-	u32 ic_tx_abrt_source;
-};
-
-#define IC_CLK			166
-#define NANO_TO_MICRO		1000
-
-/* High and low times in different speed modes (in ns) */
-#define MIN_SS_SCL_HIGHTIME	4000
-#define MIN_SS_SCL_LOWTIME	5000
-#define MIN_FS_SCL_HIGHTIME	800
-#define MIN_FS_SCL_LOWTIME	1700
-#define MIN_HS_SCL_HIGHTIME	60
-#define MIN_HS_SCL_LOWTIME	160
-
-/* Worst case timeout for 1 byte is kept as 2ms */
-#define I2C_BYTE_TO		(CONFIG_SYS_HZ/500)
-#define I2C_STOPDET_TO		(CONFIG_SYS_HZ/500)
-#define I2C_BYTE_TO_BB		(I2C_BYTE_TO * 16)
-
-/* i2c control register definitions */
-#define IC_CON_SD		0x0040
-#define IC_CON_RE		0x0020
-#define IC_CON_10BITADDRMASTER	0x0010
-#define IC_CON_10BITADDR_SLAVE	0x0008
-#define IC_CON_SPD_MSK		0x0006
-#define IC_CON_SPD_SS		0x0002
-#define IC_CON_SPD_FS		0x0004
-#define IC_CON_SPD_HS		0x0006
-#define IC_CON_MM		0x0001
-
-/* i2c target address register definitions */
-#define TAR_ADDR		0x0050
-
-/* i2c slave address register definitions */
-#define IC_SLAVE_ADDR		0x0002
-
-/* i2c data buffer and command register definitions */
-#define IC_CMD			0x0100
-
-/* i2c interrupt status register definitions */
-#define IC_GEN_CALL		0x0800
-#define IC_START_DET		0x0400
-#define IC_STOP_DET		0x0200
-#define IC_ACTIVITY		0x0100
-#define IC_RX_DONE		0x0080
-#define IC_TX_ABRT		0x0040
-#define IC_RD_REQ		0x0020
-#define IC_TX_EMPTY		0x0010
-#define IC_TX_OVER		0x0008
-#define IC_RX_FULL		0x0004
-#define IC_RX_OVER 		0x0002
-#define IC_RX_UNDER		0x0001
-
-/* fifo threshold register definitions */
-#define IC_TL0			0x00
-#define IC_TL1			0x01
-#define IC_TL2			0x02
-#define IC_TL3			0x03
-#define IC_TL4			0x04
-#define IC_TL5			0x05
-#define IC_TL6			0x06
-#define IC_TL7			0x07
-#define IC_RX_TL		IC_TL0
-#define IC_TX_TL		IC_TL0
-
-/* i2c enable register definitions */
-#define IC_ENABLE_0B		0x0001
-
-/* i2c status register  definitions */
-#define IC_STATUS_SA		0x0040
-#define IC_STATUS_MA		0x0020
-#define IC_STATUS_RFF		0x0010
-#define IC_STATUS_RFNE		0x0008
-#define IC_STATUS_TFE		0x0004
-#define IC_STATUS_TFNF		0x0002
-#define IC_STATUS_ACT		0x0001
-
-/* Speed Selection */
-#define IC_SPEED_MODE_STANDARD	1
-#define IC_SPEED_MODE_FAST	2
-#define IC_SPEED_MODE_MAX	3
-
-#define I2C_MAX_SPEED		3400000
-#define I2C_FAST_SPEED		400000
-#define I2C_STANDARD_SPEED	100000
-
-#endif /* __SPR_I2C_H_ */
diff --git a/arch/arm/include/asm/arch-spear/spr_misc.h b/arch/arm/include/asm/arch-spear/spr_misc.h
deleted file mode 100644
index 8b96d9b..0000000
--- a/arch/arm/include/asm/arch-spear/spr_misc.h
+++ /dev/null
@@ -1,130 +0,0 @@
-/*
- * (C) Copyright 2009
- * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef _SPR_MISC_H
-#define _SPR_MISC_H
-
-struct misc_regs {
-	u32 auto_cfg_reg;	/* 0x0 */
-	u32 armdbg_ctr_reg;	/* 0x4 */
-	u32 pll1_cntl;		/* 0x8 */
-	u32 pll1_frq;		/* 0xc */
-	u32 pll1_mod;		/* 0x10 */
-	u32 pll2_cntl;		/* 0x14 */
-	u32 pll2_frq;		/* 0x18 */
-	u32 pll2_mod;		/* 0x1C */
-	u32 pll_ctr_reg;	/* 0x20 */
-	u32 amba_clk_cfg;	/* 0x24 */
-	u32 periph_clk_cfg;	/* 0x28 */
-	u32 periph1_clken;	/* 0x2C */
-	u32 periph2_clken;	/* 0x30 */
-	u32 ras_clken;		/* 0x34 */
-	u32 periph1_rst;	/* 0x38 */
-	u32 periph2_rst;	/* 0x3C */
-	u32 ras_rst;		/* 0x40 */
-	u32 prsc1_clk_cfg;	/* 0x44 */
-	u32 prsc2_clk_cfg;	/* 0x48 */
-	u32 prsc3_clk_cfg;	/* 0x4C */
-	u32 amem_cfg_ctrl;	/* 0x50 */
-	u32 port_cfg_ctrl;	/* 0x54 */
-	u32 reserved_1;		/* 0x58 */
-	u32 clcd_synth_clk;	/* 0x5C */
-	u32 irda_synth_clk;	/* 0x60 */
-	u32 uart_synth_clk;	/* 0x64 */
-	u32 gmac_synth_clk;	/* 0x68 */
-	u32 ras_synth1_clk;	/* 0x6C */
-	u32 ras_synth2_clk;	/* 0x70 */
-	u32 ras_synth3_clk;	/* 0x74 */
-	u32 ras_synth4_clk;	/* 0x78 */
-	u32 arb_icm_ml1;	/* 0x7C */
-	u32 arb_icm_ml2;	/* 0x80 */
-	u32 arb_icm_ml3;	/* 0x84 */
-	u32 arb_icm_ml4;	/* 0x88 */
-	u32 arb_icm_ml5;	/* 0x8C */
-	u32 arb_icm_ml6;	/* 0x90 */
-	u32 arb_icm_ml7;	/* 0x94 */
-	u32 arb_icm_ml8;	/* 0x98 */
-	u32 arb_icm_ml9;	/* 0x9C */
-	u32 dma_src_sel;	/* 0xA0 */
-	u32 uphy_ctr_reg;	/* 0xA4 */
-	u32 gmac_ctr_reg;	/* 0xA8 */
-	u32 port_bridge_ctrl;	/* 0xAC */
-	u32 reserved_2[4];	/* 0xB0--0xBC */
-	u32 prc1_ilck_ctrl_reg;	/* 0xC0 */
-	u32 prc2_ilck_ctrl_reg;	/* 0xC4 */
-	u32 prc3_ilck_ctrl_reg;	/* 0xC8 */
-	u32 prc4_ilck_ctrl_reg;	/* 0xCC */
-	u32 prc1_intr_ctrl_reg;	/* 0xD0 */
-	u32 prc2_intr_ctrl_reg;	/* 0xD4 */
-	u32 prc3_intr_ctrl_reg;	/* 0xD8 */
-	u32 prc4_intr_ctrl_reg;	/* 0xDC */
-	u32 powerdown_cfg_reg;	/* 0xE0 */
-	u32 ddr_1v8_compensation;	/* 0xE4  */
-	u32 ddr_2v5_compensation;	/* 0xE8 */
-	u32 core_3v3_compensation;	/* 0xEC */
-	u32 ddr_pad;		/* 0xF0 */
-	u32 bist1_ctr_reg;	/* 0xF4 */
-	u32 bist2_ctr_reg;	/* 0xF8 */
-	u32 bist3_ctr_reg;	/* 0xFC */
-	u32 bist4_ctr_reg;	/* 0x100 */
-	u32 bist5_ctr_reg;	/* 0x104 */
-	u32 bist1_rslt_reg;	/* 0x108 */
-	u32 bist2_rslt_reg;	/* 0x10C */
-	u32 bist3_rslt_reg;	/* 0x110 */
-	u32 bist4_rslt_reg;	/* 0x114 */
-	u32 bist5_rslt_reg;	/* 0x118 */
-	u32 syst_error_reg;	/* 0x11C */
-	u32 reserved_3[0x1FB8];	/* 0x120--0x7FFC */
-	u32 ras_gpp1_in;	/* 0x8000 */
-	u32 ras_gpp2_in;	/* 0x8004 */
-	u32 ras_gpp1_out;	/* 0x8008 */
-	u32 ras_gpp2_out;	/* 0x800C */
-};
-
-/* AUTO_CFG_REG value */
-#define MISC_SOCCFGMSK                  0x0000003F
-#define MISC_SOCCFG30                   0x0000000C
-#define MISC_SOCCFG31                   0x0000000D
-#define MISC_NANDDIS			0x00020000
-
-/* PERIPH_CLK_CFG value */
-#define MISC_GPT3SYNTH			0x00000400
-#define MISC_GPT4SYNTH			0x00000800
-
-/* PRSC_CLK_CFG value */
-/*
- * Fout = Fin / (2^(N+1) * (M + 1))
- */
-#define MISC_PRSC_N_1			0x00001000
-#define MISC_PRSC_M_9			0x00000009
-#define MISC_PRSC_N_4			0x00004000
-#define MISC_PRSC_M_399			0x0000018F
-#define MISC_PRSC_N_6			0x00006000
-#define MISC_PRSC_M_2593		0x00000A21
-#define MISC_PRSC_M_124			0x0000007C
-#define MISC_PRSC_CFG			(MISC_PRSC_N_1 | MISC_PRSC_M_9)
-
-/* PERIPH1_CLKEN, PERIPH1_RST value */
-#define MISC_USBDENB			0x01000000
-
-#endif
diff --git a/arch/arm/include/asm/arch-spear/spr_nand.h b/arch/arm/include/asm/arch-spear/spr_nand.h
deleted file mode 100644
index 2b63dc7..0000000
--- a/arch/arm/include/asm/arch-spear/spr_nand.h
+++ /dev/null
@@ -1,57 +0,0 @@
-/*
- * (C) Copyright 2009
- * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __SPR_NAND_H__
-#define __SPR_NAND_H__
-
-struct fsmc_regs {
-	u32 reserved_1[0x10];
-	u32 genmemctrl_pc;
-	u32 reserved_2;
-	u32 genmemctrl_comm;
-	u32 genmemctrl_attrib;
-	u32 reserved_3;
-	u32 genmemctrl_ecc;
-};
-
-/* genmemctrl_pc register definitions */
-#define FSMC_RESET		(1 << 0)
-#define FSMC_WAITON		(1 << 1)
-#define FSMC_ENABLE		(1 << 2)
-#define FSMC_DEVTYPE_NAND	(1 << 3)
-#define FSMC_DEVWID_8		(0 << 4)
-#define FSMC_DEVWID_16		(1 << 4)
-#define FSMC_ECCEN		(1 << 6)
-#define FSMC_ECCPLEN_512	(0 << 7)
-#define FSMC_ECCPLEN_256	(1 << 7)
-#define FSMC_TCLR_1		(1 << 9)
-#define FSMC_TAR_1		(1 << 13)
-
-/* genmemctrl_comm register definitions */
-#define FSMC_TSET_0		(0 << 0)
-#define FSMC_TWAIT_6		(6 << 8)
-#define FSMC_THOLD_4		(4 << 16)
-#define FSMC_THIZ_1		(1 << 24)
-
-extern int spear_nand_init(struct nand_chip *nand);
-#endif
diff --git a/arch/arm/include/asm/arch-spear/spr_smi.h b/arch/arm/include/asm/arch-spear/spr_smi.h
deleted file mode 100644
index 06df745..0000000
--- a/arch/arm/include/asm/arch-spear/spr_smi.h
+++ /dev/null
@@ -1,115 +0,0 @@
-/*
- * (C) Copyright 2009
- * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef SPR_SMI_H
-#define SPR_SMI_H
-
-/* 0xF800.0000 . 0xFBFF.FFFF	64MB	SMI (Serial Flash Mem) */
-/* 0xFC00.0000 . 0xFC1F.FFFF	2MB	SMI (Serial Flash Reg.) */
-
-#define FLASH_START_ADDRESS	CONFIG_SYS_FLASH_BASE
-#define FLASH_BANK_SIZE		CONFIG_SYS_FLASH_BANK_SIZE
-
-#define SMIBANK0_BASE		(FLASH_START_ADDRESS)
-#define SMIBANK1_BASE		(SMIBANK0_BASE + FLASH_BANK_SIZE)
-#define SMIBANK2_BASE		(SMIBANK1_BASE + FLASH_BANK_SIZE)
-#define SMIBANK3_BASE		(SMIBANK2_BASE + FLASH_BANK_SIZE)
-
-#define BANK0			0
-#define BANK1			1
-#define BANK2			2
-#define BANK3			3
-
-struct smi_regs {
-	u32 smi_cr1;
-	u32 smi_cr2;
-	u32 smi_sr;
-	u32 smi_tr;
-	u32 smi_rr;
-};
-
-/* CONTROL REG 1 */
-#define BANK_EN			0x0000000F	/* enables all banks */
-#define DSEL_TIME		0x00000060	/* Deselect time */
-#define PRESCAL5		0x00000500	/* AHB_CK prescaling value */
-#define PRESCALA		0x00000A00	/* AHB_CK prescaling value */
-#define PRESCAL3		0x00000300	/* AHB_CK prescaling value */
-#define PRESCAL4		0x00000400	/* AHB_CK prescaling value */
-#define SW_MODE			0x10000000	/* enables SW Mode */
-#define WB_MODE			0x20000000	/* Write Burst Mode */
-#define FAST_MODE		0x00008000	/* Fast Mode */
-#define HOLD1			0x00010000
-
-/* CONTROL REG 2 */
-#define RD_STATUS_REG		0x00000400	/* reads status reg */
-#define WE			0x00000800	/* Write Enable */
-#define BANK0_SEL		0x00000000	/* Select Banck0 */
-#define BANK1_SEL		0x00001000	/* Select Banck1 */
-#define BANK2_SEL		0x00002000	/* Select Banck2 */
-#define BANK3_SEL		0x00003000	/* Select Banck3 */
-#define BANKSEL_SHIFT		12
-#define SEND			0x00000080	/* Send data */
-#define TX_LEN_1		0x00000001	/* data length = 1 byte */
-#define TX_LEN_2		0x00000002	/* data length = 2 byte */
-#define TX_LEN_3		0x00000003	/* data length = 3 byte */
-#define TX_LEN_4		0x00000004	/* data length = 4 byte */
-#define RX_LEN_1		0x00000010	/* data length = 1 byte */
-#define RX_LEN_2		0x00000020	/* data length = 2 byte */
-#define RX_LEN_3		0x00000030	/* data length = 3 byte */
-#define RX_LEN_4		0x00000040	/* data length = 4 byte */
-#define TFIE			0x00000100	/* Tx Flag Interrupt Enable */
-#define WCIE			0x00000200	/* WCF Interrupt Enable */
-
-/* STATUS_REG */
-#define INT_WCF_CLR		0xFFFFFDFF	/* clear: WCF clear */
-#define INT_TFF_CLR		0xFFFFFEFF	/* clear: TFF clear */
-#define WIP_BIT			0x00000001	/* WIP Bit of SPI SR */
-#define WEL_BIT			0x00000002	/* WEL Bit of SPI SR */
-#define RSR			0x00000005	/* Read Status regiser */
-#define TFF			0x00000100	/* Transfer Finished FLag */
-#define WCF			0x00000200	/* Transfer Finished FLag */
-#define ERF1			0x00000400	/* Error Flag 1 */
-#define ERF2			0x00000800	/* Error Flag 2 */
-#define WM0			0x00001000	/* WM Bank 0 */
-#define WM1			0x00002000	/* WM Bank 1 */
-#define WM2			0x00004000	/* WM Bank 2 */
-#define WM3			0x00008000	/* WM Bank 3 */
-#define WM_SHIFT		12
-
-/* TR REG */
-#define READ_ID			0x0000009F	/* Read Identification */
-#define BULK_ERASE		0x000000C7	/* BULK erase */
-#define SECTOR_ERASE		0x000000D8	/* SECTOR erase */
-#define WRITE_ENABLE		0x00000006	/* Wenable command to FLASH */
-
-struct flash_dev {
-	u32 density;
-	ulong size;
-	ushort sector_count;
-};
-
-#define SFLASH_PAGE_SIZE	0x100	/* flash page size */
-#define XFER_FINISH_TOUT	2	/* xfer finish timeout */
-#define WMODE_TOUT		2	/* write enable timeout */
-
-#endif
diff --git a/arch/arm/include/asm/arch-spear/spr_syscntl.h b/arch/arm/include/asm/arch-spear/spr_syscntl.h
deleted file mode 100644
index 3c92f09..0000000
--- a/arch/arm/include/asm/arch-spear/spr_syscntl.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- * (C) Copyright 2009
- * Ryan CHEN, ST Micoelectronics, ryan.chen@st.com
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-struct syscntl_regs {
-	u32 scctrl;
-	u32 scsysstat;
-	u32 scimctrl;
-	u32 scimsysstat;
-	u32 scxtalctrl;
-	u32 scpllctrl;
-	u32 scpllfctrl;
-	u32 scperctrl0;
-	u32 scperctrl1;
-	u32 scperen;
-	u32 scperdis;
-	const u32 scperclken;
-	const u32 scperstat;
-};
diff --git a/arch/arm/include/asm/arch-spear/spr_xloader_table.h b/arch/arm/include/asm/arch-spear/spr_xloader_table.h
deleted file mode 100644
index 7e3da18..0000000
--- a/arch/arm/include/asm/arch-spear/spr_xloader_table.h
+++ /dev/null
@@ -1,67 +0,0 @@
-/*
- * (C) Copyright 2009
- * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef _SPR_XLOADER_TABLE_H
-#define _SPR_XLOADER_TABLE_H
-
-#define XLOADER_TABLE_VERSION_1_1	2
-#define XLOADER_TABLE_VERSION_1_2	3
-
-#define XLOADER_TABLE_ADDRESS		0xD2801FF0
-
-#define DDRMOBILE	1
-#define DDR2		2
-
-#define REV_BA		1
-#define REV_AA		2
-#define REV_AB		3
-
-struct xloader_table_1_1 {
-	unsigned short ddrfreq;
-	unsigned char ddrsize;
-	unsigned char ddrtype;
-
-	unsigned char soc_rev;
-} __attribute__ ((packed));
-
-struct xloader_table_1_2 {
-	unsigned const char *version;
-
-	unsigned short ddrfreq;
-	unsigned char ddrsize;
-	unsigned char ddrtype;
-
-	unsigned char soc_rev;
-} __attribute__ ((packed));
-
-union table_contents {
-	struct xloader_table_1_1 table_1_1;
-	struct xloader_table_1_2 table_1_2;
-};
-
-struct xloader_table {
-	unsigned char table_version;
-	union table_contents table;
-} __attribute__ ((packed));
-
-#endif
diff --git a/arch/arm/include/asm/arch-tegra2/clk_rst.h b/arch/arm/include/asm/arch-tegra2/clk_rst.h
deleted file mode 100644
index 6d573bf..0000000
--- a/arch/arm/include/asm/arch-tegra2/clk_rst.h
+++ /dev/null
@@ -1,165 +0,0 @@
-/*
- *  (C) Copyright 2010,2011
- *  NVIDIA Corporation <www.nvidia.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef _CLK_RST_H_
-#define _CLK_RST_H_
-
-/* Clock/Reset Controller (CLK_RST_CONTROLLER_) regs */
-struct clk_rst_ctlr {
-	uint crc_rst_src;		/* _RST_SOURCE_0,	0x00 */
-	uint crc_rst_dev_l;		/* _RST_DEVICES_L_0,	0x04 */
-	uint crc_rst_dev_h;		/* _RST_DEVICES_H_0,	0x08 */
-	uint crc_rst_dev_u;		/* _RST_DEVICES_U_0,	0x0C */
-	uint crc_clk_out_enb_l;		/* _CLK_OUT_ENB_L_0,	0x10 */
-	uint crc_clk_out_enb_h;		/* _CLK_OUT_ENB_H_0,	0x14 */
-	uint crc_clk_out_enb_u;		/* _CLK_OUT_ENB_U_0,	0x18 */
-	uint crc_reserved0;		/* reserved_0,		0x1C */
-	uint crc_cclk_brst_pol;		/* _CCLK_BURST_POLICY_0,0x20 */
-	uint crc_super_cclk_div;	/* _SUPER_CCLK_DIVIDER_0,0x24 */
-	uint crc_sclk_brst_pol;		/* _SCLK_BURST_POLICY_0, 0x28 */
-	uint crc_super_sclk_div;	/* _SUPER_SCLK_DIVIDER_0,0x2C */
-	uint crc_clk_sys_rate;		/* _CLK_SYSTEM_RATE_0,	0x30 */
-	uint crc_prog_dly_clk;		/* _PROG_DLY_CLK_0,	0x34 */
-	uint crc_aud_sync_clk_rate;	/* _AUDIO_SYNC_CLK_RATE_0,0x38 */
-	uint crc_reserved1;		/* reserved_1,		0x3C */
-	uint crc_cop_clk_skip_plcy;	/* _COP_CLK_SKIP_POLICY_0,0x40 */
-	uint crc_clk_mask_arm;		/* _CLK_MASK_ARM_0,	0x44 */
-	uint crc_misc_clk_enb;		/* _MISC_CLK_ENB_0,	0x48 */
-	uint crc_clk_cpu_cmplx;		/* _CLK_CPU_CMPLX_0,	0x4C */
-	uint crc_osc_ctrl;		/* _OSC_CTRL_0,		0x50 */
-	uint crc_pll_lfsr;		/* _PLL_LFSR_0,		0x54 */
-	uint crc_osc_freq_det;		/* _OSC_FREQ_DET_0,	0x58 */
-	uint crc_osc_freq_det_stat;	/* _OSC_FREQ_DET_STATUS_0,0x5C */
-	uint crc_reserved2[8];		/* reserved_2[8],	0x60-7C */
-
-	uint crc_pllc_base;		/* _PLLC_BASE_0,	0x80 */
-	uint crc_pllc_out;		/* _PLLC_OUT_0,		0x84 */
-	uint crc_reserved3;		/* reserved_3,		0x88 */
-	uint crc_pllc_misc;		/* _PLLC_MISC_0,	0x8C */
-
-	uint crc_pllm_base;		/* _PLLM_BASE_0,	0x90 */
-	uint crc_pllm_out;		/* _PLLM_OUT_0,		0x94 */
-	uint crc_reserved4;		/* reserved_4,		0x98 */
-	uint crc_pllm_misc;		/* _PLLM_MISC_0,	0x9C */
-
-	uint crc_pllp_base;		/* _PLLP_BASE_0,	0xA0 */
-	uint crc_pllp_outa;		/* _PLLP_OUTA_0,	0xA4 */
-	uint crc_pllp_outb;		/* _PLLP_OUTB_0,	0xA8 */
-	uint crc_pllp_misc;		/* _PLLP_MISC_0,	0xAC */
-
-	uint crc_plla_base;		/* _PLLA_BASE_0,	0xB0 */
-	uint crc_plla_out;		/* _PLLA_OUT_0,		0xB4 */
-	uint crc_reserved5;		/* reserved_5,		0xB8 */
-	uint crc_plla_misc;		/* _PLLA_MISC_0,	0xBC */
-
-	uint crc_pllu_base;		/* _PLLU_BASE_0,	0xC0 */
-	uint crc_reserved6;		/* _reserved_6,		0xC4 */
-	uint crc_reserved7;		/* _reserved_7,		0xC8 */
-	uint crc_pllu_misc;		/* _PLLU_MISC_0,	0xCC */
-
-	uint crc_plld_base;		/* _PLLD_BASE_0,	0xD0 */
-	uint crc_reserved8;		/* _reserved_8,		0xD4 */
-	uint crc_reserved9;		/* _reserved_9,		0xD8 */
-	uint crc_plld_misc;		/* _PLLD_MISC_0,	0xDC */
-
-	uint crc_pllx_base;		/* _PLLX_BASE_0,	0xE0 */
-	uint crc_pllx_misc;		/* _PLLX_MISC_0,	0xE4 */
-
-	uint crc_plle_base;		/* _PLLE_BASE_0,	0xE8 */
-	uint crc_plle_misc;		/* _PLLE_MISC_0,	0xEC */
-
-	uint crc_plls_base;		/* _PLLS_BASE_0,	0xF0 */
-	uint crc_plls_misc;		/* _PLLS_MISC_0,	0xF4 */
-	uint crc_reserved10;		/* _reserved_10,	0xF8 */
-	uint crc_reserved11;		/* _reserved_11,	0xFC */
-
-	uint crc_clk_src_i2s1;		/*_I2S1_0,		0x100 */
-	uint crc_clk_src_i2s2;		/*_I2S2_0,		0x104 */
-	uint crc_clk_src_spdif_out;	/*_SPDIF_OUT_0,		0x108 */
-	uint crc_clk_src_spdif_in;	/*_SPDIF_IN_0,		0x10C */
-	uint crc_clk_src_pwm;		/*_PWM_0,		0x110 */
-	uint crc_clk_src_spi1;		/*_SPI1_0,		0x114 */
-	uint crc_clk_src_sbc2;		/*_SBC2_0,		0x118 */
-	uint crc_clk_src_sbc3;		/*_SBC3_0,		0x11C */
-	uint crc_clk_src_xio;		/*_XIO_0,		0x120 */
-	uint crc_clk_src_i2c1;		/*_I2C1_0,		0x124 */
-	uint crc_clk_src_dvc_i2c;	/*_DVC_I2C_0,		0x128 */
-	uint crc_clk_src_twc;		/*_TWC_0,		0x12C */
-	uint crc_reserved12;		/*			0x130 */
-	uint crc_clk_src_sbc1;		/*_SBC1_0,		0x134 */
-	uint crc_clk_src_disp1;		/*_DISP1_0,		0x138 */
-	uint crc_clk_src_disp2;		/*_DISP2_0,		0x13C */
-	uint crc_clk_src_cve;		/*_CVE_0,		0x140 */
-	uint crc_clk_src_ide;		/*_IDE_0,		0x144 */
-	uint crc_clk_src_vi;		/*_VI_0,		0x148 */
-	uint crc_reserved13;		/*			0x14C */
-	uint crc_clk_src_sdmmc1;	/*_SDMMC1_0,		0x150 */
-	uint crc_clk_src_sdmmc2;	/*_SDMMC2_0,		0x154 */
-	uint crc_clk_src_g3d;		/*_G3D_0,		0x158 */
-	uint crc_clk_src_g2d;		/*_G2D_0,		0x15C */
-	uint crc_clk_src_ndflash;	/*_NDFLASH_0,		0x160 */
-	uint crc_clk_src_sdmmc4;	/*_SDMMC4_0,		0x164 */
-	uint crc_clk_src_vfir;		/*_VFIR_0,		0x168 */
-	uint crc_clk_src_epp;		/*_EPP_0,		0x16C */
-	uint crc_clk_src_mp3;		/*_MPE_0,		0x170 */
-	uint crc_clk_src_mipi;		/*_MIPI_0,		0x174 */
-	uint crc_clk_src_uarta;		/*_UARTA_0,		0x178 */
-	uint crc_clk_src_uartb;		/*_UARTB_0,		0x17C */
-	uint crc_clk_src_host1x;	/*_HOST1X_0,		0x180 */
-	uint crc_reserved14;		/*			0x184 */
-	uint crc_clk_src_tvo;		/*_TVO_0,		0x188 */
-	uint crc_clk_src_hdmi;		/*_HDMI_0,		0x18C */
-	uint crc_reserved15;		/*			0x190 */
-	uint crc_clk_src_tvdac;		/*_TVDAC_0,		0x194 */
-	uint crc_clk_src_i2c2;		/*_I2C2_0,		0x198 */
-	uint crc_clk_src_emc;		/*_EMC_0,		0x19C */
-	uint crc_clk_src_uartc;		/*_UARTC_0,		0x1A0 */
-	uint crc_reserved16;		/*			0x1A4 */
-	uint crc_clk_src_vi_sensor;	/*_VI_SENSOR_0,		0x1A8 */
-	uint crc_reserved17;		/*			0x1AC */
-	uint crc_reserved18;		/*			0x1B0 */
-	uint crc_clk_src_sbc4;		/*_SBC4_0,		0x1B4 */
-	uint crc_clk_src_i2c3;		/*_I2C3_0,		0x1B8 */
-	uint crc_clk_src_sdmmc3;	/*_SDMMC3_0,		0x1BC */
-	uint crc_clk_src_uartd;		/*_UARTD_0,		0x1C0 */
-	uint crc_clk_src_uarte;		/*_UARTE_0,		0x1C4 */
-	uint crc_clk_src_vde;		/*_VDE_0,		0x1C8 */
-	uint crc_clk_src_owr;		/*_OWR_0,		0x1CC */
-	uint crc_clk_src_nor;		/*_NOR_0,		0x1D0 */
-	uint crc_clk_src_csite;		/*_CSITE_0,		0x1D4 */
-	uint crc_reserved19[9];		/*			0x1D8-1F8 */
-	uint crc_clk_src_osc;		/*_OSC_0,		0x1FC */
-};
-
-#define PLL_BYPASS		(1 << 31)
-#define PLL_ENABLE		(1 << 30)
-#define PLL_BASE_OVRRIDE	(1 << 28)
-#define PLL_DIVP		(1 << 20)	/* post divider, b22:20 */
-#define PLL_DIVM		0x0C		/* input divider, b4:0 */
-
-#define SWR_UARTD_RST		(1 << 2)
-#define CLK_ENB_UARTD		(1 << 2)
-#define SWR_UARTA_RST		(1 << 6)
-#define CLK_ENB_UARTA		(1 << 6)
-
-#endif	/* CLK_RST_H */
diff --git a/arch/arm/include/asm/arch-tegra2/pinmux.h b/arch/arm/include/asm/arch-tegra2/pinmux.h
deleted file mode 100644
index 8b4bd8d..0000000
--- a/arch/arm/include/asm/arch-tegra2/pinmux.h
+++ /dev/null
@@ -1,55 +0,0 @@
-/*
- *  (C) Copyright 2010,2011
- *  NVIDIA Corporation <www.nvidia.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef _PINMUX_H_
-#define _PINMUX_H_
-
-/* APB MISC Pin Mux and Tristate (APB_MISC_PP_) registers */
-struct pmux_tri_ctlr {
-	uint pmt_reserved0;		/* ABP_MISC_PP_ reserved offset 00 */
-	uint pmt_reserved1;		/* ABP_MISC_PP_ reserved offset 04 */
-	uint pmt_strap_opt_a;		/* _STRAPPING_OPT_A_0, offset 08 */
-	uint pmt_reserved2;		/* ABP_MISC_PP_ reserved offset 0C */
-	uint pmt_reserved3;		/* ABP_MISC_PP_ reserved offset 10 */
-	uint pmt_tri_a;			/* _TRI_STATE_REG_A_0, offset 14 */
-	uint pmt_tri_b;			/* _TRI_STATE_REG_B_0, offset 18 */
-	uint pmt_tri_c;			/* _TRI_STATE_REG_C_0, offset 1C */
-	uint pmt_tri_d;			/* _TRI_STATE_REG_D_0, offset 20 */
-	uint pmt_cfg_ctl;		/* _CONFIG_CTL_0, offset 24 */
-
-	uint pmt_reserved[22];		/* ABP_MISC_PP_ reserved offs 28-7C */
-
-	uint pmt_ctl_a;			/* _PIN_MUX_CTL_A_0, offset 80 */
-	uint pmt_ctl_b;			/* _PIN_MUX_CTL_B_0, offset 84 */
-	uint pmt_ctl_c;			/* _PIN_MUX_CTL_C_0, offset 88 */
-	uint pmt_ctl_d;			/* _PIN_MUX_CTL_D_0, offset 8C */
-	uint pmt_ctl_e;			/* _PIN_MUX_CTL_E_0, offset 90 */
-	uint pmt_ctl_f;			/* _PIN_MUX_CTL_F_0, offset 94 */
-	uint pmt_ctl_g;			/* _PIN_MUX_CTL_G_0, offset 98 */
-};
-
-#define Z_GMC			(1 << 29)
-#define Z_IRRX			(1 << 20)
-#define Z_IRTX			(1 << 19)
-
-#endif	/* PINMUX_H */
diff --git a/arch/arm/include/asm/arch-tegra2/pmc.h b/arch/arm/include/asm/arch-tegra2/pmc.h
deleted file mode 100644
index 7ec9eeb..0000000
--- a/arch/arm/include/asm/arch-tegra2/pmc.h
+++ /dev/null
@@ -1,124 +0,0 @@
-/*
- *  (C) Copyright 2010,2011
- *  NVIDIA Corporation <www.nvidia.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef _PMC_H_
-#define _PMC_H_
-
-/* Power Management Controller (APBDEV_PMC_) registers */
-struct pmc_ctlr {
-	uint pmc_cntrl;			/* _CNTRL_0, offset 00 */
-	uint pmc_sec_disable;		/* _SEC_DISABLE_0, offset 04 */
-	uint pmc_pmc_swrst;		/* _PMC_SWRST_0, offset 08 */
-	uint pmc_wake_mask;		/* _WAKE_MASK_0, offset 0C */
-	uint pmc_wake_lvl;		/* _WAKE_LVL_0, offset 10 */
-	uint pmc_wake_status;		/* _WAKE_STATUS_0, offset 14 */
-	uint pmc_sw_wake_status;	/* _SW_WAKE_STATUS_0, offset 18 */
-	uint pmc_dpd_pads_oride;	/* _DPD_PADS_ORIDE_0, offset 1C */
-	uint pmc_dpd_sample;		/* _DPD_PADS_SAMPLE_0, offset 20 */
-	uint pmc_dpd_enable;		/* _DPD_PADS_ENABLE_0, offset 24 */
-	uint pmc_pwrgate_timer_off;	/* _PWRGATE_TIMER_OFF_0, offset 28 */
-	uint pmc_pwrgate_timer_on;	/* _PWRGATE_TIMER_ON_0, offset 2C */
-	uint pmc_pwrgate_toggle;	/* _PWRGATE_TOGGLE_0, offset 30 */
-	uint pmc_remove_clamping;	/* _REMOVE_CLAMPING_CMD_0, offset 34 */
-	uint pmc_pwrgate_status;	/* _PWRGATE_STATUS_0, offset 38 */
-	uint pmc_pwrgood_timer;		/* _PWRGOOD_TIMER_0, offset 3C */
-	uint pmc_blink_timer;		/* _BLINK_TIMER_0, offset 40 */
-	uint pmc_no_iopower;		/* _NO_IOPOWER_0, offset 44 */
-	uint pmc_pwr_det;		/* _PWR_DET_0, offset 48 */
-	uint pmc_pwr_det_latch;		/* _PWR_DET_LATCH_0, offset 4C */
-
-	uint pmc_scratch0;		/* _SCRATCH0_0, offset 50 */
-	uint pmc_scratch1;		/* _SCRATCH1_0, offset 54 */
-	uint pmc_scratch2;		/* _SCRATCH2_0, offset 58 */
-	uint pmc_scratch3;		/* _SCRATCH3_0, offset 5C */
-	uint pmc_scratch4;		/* _SCRATCH4_0, offset 60 */
-	uint pmc_scratch5;		/* _SCRATCH5_0, offset 64 */
-	uint pmc_scratch6;		/* _SCRATCH6_0, offset 68 */
-	uint pmc_scratch7;		/* _SCRATCH7_0, offset 6C */
-	uint pmc_scratch8;		/* _SCRATCH8_0, offset 70 */
-	uint pmc_scratch9;		/* _SCRATCH9_0, offset 74 */
-	uint pmc_scratch10;		/* _SCRATCH10_0, offset 78 */
-	uint pmc_scratch11;		/* _SCRATCH11_0, offset 7C */
-	uint pmc_scratch12;		/* _SCRATCH12_0, offset 80 */
-	uint pmc_scratch13;		/* _SCRATCH13_0, offset 84 */
-	uint pmc_scratch14;		/* _SCRATCH14_0, offset 88 */
-	uint pmc_scratch15;		/* _SCRATCH15_0, offset 8C */
-	uint pmc_scratch16;		/* _SCRATCH16_0, offset 90 */
-	uint pmc_scratch17;		/* _SCRATCH17_0, offset 94 */
-	uint pmc_scratch18;		/* _SCRATCH18_0, offset 98 */
-	uint pmc_scratch19;		/* _SCRATCH19_0, offset 9C */
-	uint pmc_scratch20;		/* _SCRATCH20_0, offset A0 */
-	uint pmc_scratch21;		/* _SCRATCH21_0, offset A4 */
-	uint pmc_scratch22;		/* _SCRATCH22_0, offset A8 */
-	uint pmc_scratch23;		/* _SCRATCH23_0, offset AC */
-
-	uint pmc_secure_scratch0;	/* _SECURE_SCRATCH0_0, offset B0 */
-	uint pmc_secure_scratch1;	/* _SECURE_SCRATCH1_0, offset B4 */
-	uint pmc_secure_scratch2;	/* _SECURE_SCRATCH2_0, offset B8 */
-	uint pmc_secure_scratch3;	/* _SECURE_SCRATCH3_0, offset BC */
-	uint pmc_secure_scratch4;	/* _SECURE_SCRATCH4_0, offset C0 */
-	uint pmc_secure_scratch5;	/* _SECURE_SCRATCH5_0, offset C4 */
-
-	uint pmc_cpupwrgood_timer;	/* _CPUPWRGOOD_TIMER_0, offset C8 */
-	uint pmc_cpupwroff_timer;	/* _CPUPWROFF_TIMER_0, offset CC */
-	uint pmc_pg_mask;		/* _PG_MASK_0, offset D0 */
-	uint pmc_pg_mask_1;		/* _PG_MASK_1_0, offset D4 */
-	uint pmc_auto_wake_lvl;		/* _AUTO_WAKE_LVL_0, offset D8 */
-	uint pmc_auto_wake_lvl_mask;	/* _AUTO_WAKE_LVL_MASK_0, offset DC */
-	uint pmc_wake_delay;		/* _WAKE_DELAY_0, offset E0 */
-	uint pmc_pwr_det_val;		/* _PWR_DET_VAL_0, offset E4 */
-	uint pmc_ddr_pwr;		/* _DDR_PWR_0, offset E8 */
-	uint pmc_usb_debounce_del;	/* _USB_DEBOUNCE_DEL_0, offset EC */
-	uint pmc_usb_ao;		/* _USB_AO_0, offset F0 */
-	uint pmc_crypto_op;		/* _CRYPTO_OP__0, offset F4 */
-	uint pmc_pllp_wb0_override;	/* _PLLP_WB0_OVERRIDE_0, offset F8 */
-
-	uint pmc_scratch24;		/* _SCRATCH24_0, offset FC */
-	uint pmc_scratch25;		/* _SCRATCH24_0, offset 100 */
-	uint pmc_scratch26;		/* _SCRATCH24_0, offset 104 */
-	uint pmc_scratch27;		/* _SCRATCH24_0, offset 108 */
-	uint pmc_scratch28;		/* _SCRATCH24_0, offset 10C */
-	uint pmc_scratch29;		/* _SCRATCH24_0, offset 110 */
-	uint pmc_scratch30;		/* _SCRATCH24_0, offset 114 */
-	uint pmc_scratch31;		/* _SCRATCH24_0, offset 118 */
-	uint pmc_scratch32;		/* _SCRATCH24_0, offset 11C */
-	uint pmc_scratch33;		/* _SCRATCH24_0, offset 120 */
-	uint pmc_scratch34;		/* _SCRATCH24_0, offset 124 */
-	uint pmc_scratch35;		/* _SCRATCH24_0, offset 128 */
-	uint pmc_scratch36;		/* _SCRATCH24_0, offset 12C */
-	uint pmc_scratch37;		/* _SCRATCH24_0, offset 130 */
-	uint pmc_scratch38;		/* _SCRATCH24_0, offset 134 */
-	uint pmc_scratch39;		/* _SCRATCH24_0, offset 138 */
-	uint pmc_scratch40;		/* _SCRATCH24_0, offset 13C */
-	uint pmc_scratch41;		/* _SCRATCH24_0, offset 140 */
-	uint pmc_scratch42;		/* _SCRATCH24_0, offset 144 */
-
-	uint pmc_bo_mirror0;		/* _BOUNDOUT_MIRROR0_0, offset 148 */
-	uint pmc_bo_mirror1;		/* _BOUNDOUT_MIRROR1_0, offset 14C */
-	uint pmc_bo_mirror2;		/* _BOUNDOUT_MIRROR2_0, offset 150 */
-	uint pmc_sys_33v_en;		/* _SYS_33V_EN_0, offset 154 */
-	uint pmc_bo_mirror_access;	/* _BOUNDOUT_MIRROR_ACCESS_0, off158 */
-	uint pmc_gate;			/* _GATE_0, offset 15C */
-};
-
-#endif	/* PMC_H */
diff --git a/arch/arm/include/asm/arch-tegra2/sys_proto.h b/arch/arm/include/asm/arch-tegra2/sys_proto.h
deleted file mode 100644
index c11534e..0000000
--- a/arch/arm/include/asm/arch-tegra2/sys_proto.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- * (C) Copyright 2010,2011
- * NVIDIA Corporation <www.nvidia.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef _SYS_PROTO_H_
-#define _SYS_PROTO_H_
-
-struct tegra2_sysinfo {
-	char *board_string;
-};
-
-void invalidate_dcache(void);
-
-extern const struct tegra2_sysinfo sysinfo;
-
-#endif
diff --git a/arch/arm/include/asm/arch-tegra2/tegra2.h b/arch/arm/include/asm/arch-tegra2/tegra2.h
deleted file mode 100644
index 9001b68..0000000
--- a/arch/arm/include/asm/arch-tegra2/tegra2.h
+++ /dev/null
@@ -1,49 +0,0 @@
-/*
- * (C) Copyright 2010,2011
- * NVIDIA Corporation <www.nvidia.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef _TEGRA2_H_
-#define _TEGRA2_H_
-
-#define NV_PA_SDRAM_BASE	0x00000000
-#define NV_PA_TMRUS_BASE	0x60005010
-#define NV_PA_CLK_RST_BASE	0x60006000
-#define NV_PA_APB_MISC_BASE	0x70000000
-#define NV_PA_APB_UARTA_BASE	(NV_PA_APB_MISC_BASE + 0x6000)
-#define NV_PA_APB_UARTB_BASE	(NV_PA_APB_MISC_BASE + 0x6040)
-#define NV_PA_APB_UARTC_BASE	(NV_PA_APB_MISC_BASE + 0x6200)
-#define NV_PA_APB_UARTD_BASE	(NV_PA_APB_MISC_BASE + 0x6300)
-#define NV_PA_APB_UARTE_BASE	(NV_PA_APB_MISC_BASE + 0x6400)
-#define NV_PA_PMC_BASE		0x7000E400
-
-#define TEGRA2_SDRC_CS0		NV_PA_SDRAM_BASE
-#define LOW_LEVEL_SRAM_STACK	0x4000FFFC
-
-#ifndef __ASSEMBLY__
-struct timerus {
-	unsigned int cntr_1us;
-};
-#else  /* __ASSEMBLY__ */
-#define PRM_RSTCTRL		NV_PA_PMC_BASE
-#endif
-
-#endif	/* TEGRA2_H */
diff --git a/arch/arm/include/asm/arch-tegra2/uart.h b/arch/arm/include/asm/arch-tegra2/uart.h
deleted file mode 100644
index aea29a7..0000000
--- a/arch/arm/include/asm/arch-tegra2/uart.h
+++ /dev/null
@@ -1,47 +0,0 @@
-/*
- *  (C) Copyright 2010,2011
- *  NVIDIA Corporation <www.nvidia.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef _UART_H_
-#define _UART_H_
-
-/* UART registers */
-struct uart_ctlr {
-	uint uart_thr_dlab_0;		/* UART_THR_DLAB_0_0, offset 00 */
-	uint uart_ier_dlab_0;		/* UART_IER_DLAB_0_0, offset 04 */
-	uint uart_iir_fcr;		/* UART_IIR_FCR_0, offset 08 */
-	uint uart_lcr;			/* UART_LCR_0, offset 0C */
-	uint uart_mcr;			/* UART_MCR_0, offset 10 */
-	uint uart_lsr;			/* UART_LSR_0, offset 14 */
-	uint uart_msr;			/* UART_MSR_0, offset 18 */
-	uint uart_spr;			/* UART_SPR_0, offset 1C */
-	uint uart_irda_csr;		/* UART_IRDA_CSR_0, offset 20 */
-	uint uart_reserved[6];		/* Reserved, unused, offset 24-38*/
-	uint uart_asr;			/* UART_ASR_0, offset 3C */
-};
-
-#define NVRM_PLLP_FIXED_FREQ_KHZ	216000
-#define NV_DEFAULT_DEBUG_BAUD		115200
-
-#define UART_FCR_TRIGGER_3	0x30	/* Mask for trigger set at 3 */
-
-#endif	/* UART_H */
diff --git a/arch/arm/include/asm/arch-tnetv107x/clock.h b/arch/arm/include/asm/arch-tnetv107x/clock.h
deleted file mode 100644
index 097f825..0000000
--- a/arch/arm/include/asm/arch-tnetv107x/clock.h
+++ /dev/null
@@ -1,68 +0,0 @@
-/*
- * TNETV107X: Clock APIs
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#ifndef __ASM_ARCH_CLOCK_H
-#define __ASM_ARCH_CLOCK_H
-
-#define PSC_MDCTL_NEXT_SWRSTDISABLE	0x0
-#define PSC_MDCTL_NEXT_SYNCRST		0x1
-#define PSC_MDCTL_NEXT_DISABLE		0x2
-#define PSC_MDCTL_NEXT_ENABLE		0x3
-
-#define CONFIG_SYS_INT_OSC_FREQ		24000000
-
-#ifndef __ASSEMBLY__
-
-/* PLL identifiers */
-enum pll_type_e {
-	SYS_PLL,
-	TDM_PLL,
-	ETH_PLL
-};
-
-/* PLL configuration data */
-struct pll_init_data {
-	int pll;
-	int internal_osc;
-	unsigned long pll_freq;
-	unsigned long div_freq[10];
-};
-
-void init_plls(int num_pll, struct pll_init_data *config);
-int  lpsc_status(unsigned int mod);
-void lpsc_control(int mod, unsigned long state, int lrstz);
-unsigned long clk_get_rate(unsigned int clk);
-unsigned long clk_round_rate(unsigned int clk, unsigned long hz);
-int clk_set_rate(unsigned int clk, unsigned long hz);
-
-static inline void clk_enable(unsigned int mod)
-{
-	lpsc_control(mod, PSC_MDCTL_NEXT_ENABLE, -1);
-}
-
-static inline void clk_disable(unsigned int mod)
-{
-	lpsc_control(mod, PSC_MDCTL_NEXT_DISABLE, -1);
-}
-
-#endif
-
-#endif
diff --git a/arch/arm/include/asm/arch-tnetv107x/emif_defs.h b/arch/arm/include/asm/arch-tnetv107x/emif_defs.h
deleted file mode 100644
index 9969a01..0000000
--- a/arch/arm/include/asm/arch-tnetv107x/emif_defs.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm/arch-davinci/emif_defs.h>
diff --git a/arch/arm/include/asm/arch-tnetv107x/hardware.h b/arch/arm/include/asm/arch-tnetv107x/hardware.h
deleted file mode 100644
index 94a94f9..0000000
--- a/arch/arm/include/asm/arch-tnetv107x/hardware.h
+++ /dev/null
@@ -1,173 +0,0 @@
-/*
- * TNETV107X: Hardware information
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#ifndef __ASM_ARCH_HARDWARE_H
-#define __ASM_ARCH_HARDWARE_H
-
-#ifndef __ASSEMBLY__
-
-#include <asm/sizes.h>
-
-#define ASYNC_EMIF_NUM_CS		4
-#define ASYNC_EMIF_MODE_NOR		0
-#define ASYNC_EMIF_MODE_NAND		1
-#define ASYNC_EMIF_MODE_ONENAND		2
-#define ASYNC_EMIF_PRESERVE		-1
-
-struct async_emif_config {
-	unsigned mode;
-	unsigned select_strobe;
-	unsigned extend_wait;
-	unsigned wr_setup;
-	unsigned wr_strobe;
-	unsigned wr_hold;
-	unsigned rd_setup;
-	unsigned rd_strobe;
-	unsigned rd_hold;
-	unsigned turn_around;
-	enum {
-		ASYNC_EMIF_8	= 0,
-		ASYNC_EMIF_16	= 1,
-		ASYNC_EMIF_32	= 2,
-	} width;
-};
-
-void init_async_emif(int num_cs, struct async_emif_config *config);
-
-int wdt_start(unsigned long msecs);
-int wdt_stop(void);
-int wdt_kick(void);
-
-#endif
-
-/* Chip configuration unlock codes and registers */
-#define TNETV107X_KICK0		(TNETV107X_CHIP_CONFIG_SYS_BASE+0x38)
-#define TNETV107X_KICK1		(TNETV107X_CHIP_CONFIG_SYS_BASE+0x3c)
-#define TNETV107X_PINMUX(n)	(TNETV107X_CHIP_CONFIG_SYS_BASE+0x150+(n)*4)
-#define TNETV107X_KICK0_MAGIC	0x83e70b13
-#define TNETV107X_KICK1_MAGIC	0x95a4f1e0
-
-/* Module base addresses */
-#define TNETV107X_TPCC_BASE			0x01C00000
-#define TNETV107X_TPTC0_BASE			0x01C10000
-#define TNETV107X_TPTC1_BASE			0x01C10400
-#define TNETV107X_INTC_BASE			0x03000000
-#define TNETV107X_LCD_CONTROLLER_BASE		0x08030000
-#define TNETV107X_INTD_BASE			0x08038000
-#define TNETV107X_INTD_IPC_BASE			0x08038000
-#define TNETV107X_INTD_FAST_BASE		0x08039000
-#define TNETV107X_INTD_ASYNC_BASE		0x0803A000
-#define TNETV107X_INTD_SLOW_BASE		0x0803B000
-#define TNETV107X_PKA_BASE			0x08040000
-#define TNETV107X_RNG_BASE			0x08044000
-#define TNETV107X_TIMER0_BASE			0x08086500
-#define TNETV107X_TIMER1_BASE			0x08086600
-#define TNETV107X_WDT0_ARM_BASE			0x08086700
-#define TNETV107X_WDT1_DSP_BASE			0x08086800
-#define TNETV107X_CHIP_CONFIG_SYS_BASE		0x08087000
-#define TNETV107X_GPIO_BASE			0x08088000
-#define TNETV107X_UART1_BASE			0x08088400
-#define TNETV107X_TOUCHSCREEN_BASE		0x08088500
-#define TNETV107X_SDIO0_BASE			0x08088700
-#define TNETV107X_SDIO1_BASE			0x08088800
-#define TNETV107X_MDIO_BASE			0x08088900
-#define TNETV107X_KEYPAD_BASE			0x08088A00
-#define TNETV107X_SSP_BASE			0x08088C00
-#define TNETV107X_CLOCK_CONTROL_BASE		0x0808A000
-#define TNETV107X_PSC_BASE			0x0808B000
-#define TNETV107X_TDM0_BASE			0x08100000
-#define TNETV107X_TDM1_BASE			0x08100100
-#define TNETV107X_MCDMA_BASE			0x08108000
-#define TNETV107X_UART0_DMA_BASE		0x08108200
-#define TNETV107X_USBSS_BASE			0x08120000
-#define TNETV107X_VLYNQ_CONTROL_BASE		0x0810D000
-#define TNETV107X_ASYNC_EMIF_CNTRL_BASE		0x08200000
-#define TNETV107X_VLYNQ_MEM_MAP_BASE		0x0C000000
-#define TNETV107X_IMCOP_BASE			0x01CC0000
-#define TNETV107X_MBX_LITE_BASE			0x07000000
-#define TNETV107X_ETHSS_BASE			0x0803C000
-#define TNETV107X_CPSW_BASE			0x0803C000
-#define TNETV107X_SPF_BASE			0x0803C800
-#define TNETV107X_IOPU_ETHSS_BASE		0x0803D000
-#define TNETV107X_VTP_CNTRL_0			0x0803D800
-#define TNETV107X_VTP_CNTRL_1			0x0803D900
-#define TNETV107X_UART2_DMA_BASE		0x08108400
-#define TNETV107X_INTERNAL_MEMORY		0x20000000
-#define TNETV107X_ASYNC_EMIF_DATA_CE0_BASE	0x30000000
-#define TNETV107X_ASYNC_EMIF_DATA_CE1_BASE	0x40000000
-#define TNETV107X_ASYNC_EMIF_DATA_CE2_BASE	0x44000000
-#define TNETV107X_ASYNC_EMIF_DATA_CE3_BASE	0x48000000
-#define TNETV107X_DDR_EMIF_DATA_BASE		0x80000000
-#define TNETV107X_DDR_EMIF_CONTROL_BASE		0x90000000
-
-/* LPSC module definitions */
-#define TNETV107X_LPSC_ARM			0
-#define TNETV107X_LPSC_GEM			1
-#define TNETV107X_LPSC_DDR2_PHY			2
-#define TNETV107X_LPSC_TPCC			3
-#define TNETV107X_LPSC_TPTC0			4
-#define TNETV107X_LPSC_TPTC1			5
-#define TNETV107X_LPSC_RAM			6
-#define TNETV107X_LPSC_MBX_LITE			7
-#define TNETV107X_LPSC_LCD			8
-#define TNETV107X_LPSC_ETHSS			9
-#define TNETV107X_LPSC_AEMIF			10
-#define TNETV107X_LPSC_CHIP_CFG			11
-#define TNETV107X_LPSC_TSC			12
-#define TNETV107X_LPSC_ROM			13
-#define TNETV107X_LPSC_UART2			14
-#define TNETV107X_LPSC_PKTSEC			15
-#define TNETV107X_LPSC_SECCTL			16
-#define TNETV107X_LPSC_KEYMGR			17
-#define TNETV107X_LPSC_KEYPAD			18
-#define TNETV107X_LPSC_GPIO			19
-#define TNETV107X_LPSC_MDIO			20
-#define TNETV107X_LPSC_SDIO0			21
-#define TNETV107X_LPSC_UART0			22
-#define TNETV107X_LPSC_UART1			23
-#define TNETV107X_LPSC_TIMER0			24
-#define TNETV107X_LPSC_TIMER1			25
-#define TNETV107X_LPSC_WDT_ARM			26
-#define TNETV107X_LPSC_WDT_DSP			27
-#define TNETV107X_LPSC_SSP			28
-#define TNETV107X_LPSC_TDM0			29
-#define TNETV107X_LPSC_VLYNQ			30
-#define TNETV107X_LPSC_MCDMA			31
-#define TNETV107X_LPSC_USB0			32
-#define TNETV107X_LPSC_TDM1			33
-#define TNETV107X_LPSC_DEBUGSS			34
-#define TNETV107X_LPSC_ETHSS_RGMII		35
-#define TNETV107X_LPSC_SYSTEM			36
-#define TNETV107X_LPSC_IMCOP			37
-#define TNETV107X_LPSC_SPARE			38
-#define TNETV107X_LPSC_SDIO1			39
-#define TNETV107X_LPSC_USB1			40
-#define TNETV107X_LPSC_USBSS			41
-#define TNETV107X_LPSC_DDR2_EMIF1_VRST		42
-#define TNETV107X_LPSC_DDR2_EMIF2_VCTL_RST	43
-#define TNETV107X_LPSC_MAX			44
-
-/* Interrupt controller */
-#define INTC_GLB_EN			(TNETV107X_INTC_BASE + 0x10)
-#define INTC_HINT_EN			(TNETV107X_INTC_BASE + 0x1500)
-#define INTC_EN_CLR0			(TNETV107X_INTC_BASE + 0x380)
-
-#endif /* __ASM_ARCH_HARDWARE_H */
diff --git a/arch/arm/include/asm/arch-tnetv107x/mux.h b/arch/arm/include/asm/arch-tnetv107x/mux.h
deleted file mode 100644
index f16bc99..0000000
--- a/arch/arm/include/asm/arch-tnetv107x/mux.h
+++ /dev/null
@@ -1,306 +0,0 @@
-/*
- * TNETV107X: Pinmux APIs
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#ifndef __ASM_ARCH_MUX_H
-#define __ASM_ARCH_MUX_H
-
-struct pin_config {
-	unsigned char reg_index;
-	unsigned char mask_offset;
-	unsigned char mode;
-};
-
-#define TNETV107X_MUX_CFG(reg, offset, mux_mode) \
-			{ reg, offset, mux_mode }
-
-int mux_select_pin(short index);
-int mux_select_pins(const short *pins);
-
-enum tnetv107x_pin_mux_index {
-	TNETV107X_PIN_ASR_A00,
-	TNETV107X_PIN_GPIO32,
-	TNETV107X_PIN_ASR_A01,
-	TNETV107X_PIN_GPIO33,
-	TNETV107X_PIN_ASR_A02,
-	TNETV107X_PIN_GPIO34,
-	TNETV107X_PIN_ASR_A03,
-	TNETV107X_PIN_GPIO35,
-	TNETV107X_PIN_ASR_A04,
-	TNETV107X_PIN_GPIO36,
-	TNETV107X_PIN_ASR_A05,
-	TNETV107X_PIN_GPIO37,
-	TNETV107X_PIN_ASR_A06,
-	TNETV107X_PIN_GPIO38,
-	TNETV107X_PIN_ASR_A07,
-	TNETV107X_PIN_GPIO39,
-	TNETV107X_PIN_ASR_A08,
-	TNETV107X_PIN_GPIO40,
-	TNETV107X_PIN_ASR_A09,
-	TNETV107X_PIN_GPIO41,
-	TNETV107X_PIN_ASR_A10,
-	TNETV107X_PIN_GPIO42,
-	TNETV107X_PIN_ASR_A11,
-	TNETV107X_PIN_BOOT_STRP_0,
-	TNETV107X_PIN_ASR_A12,
-	TNETV107X_PIN_BOOT_STRP_1,
-	TNETV107X_PIN_ASR_A13,
-	TNETV107X_PIN_GPIO43,
-	TNETV107X_PIN_ASR_A14,
-	TNETV107X_PIN_GPIO44,
-	TNETV107X_PIN_ASR_A15,
-	TNETV107X_PIN_GPIO45,
-	TNETV107X_PIN_ASR_A16,
-	TNETV107X_PIN_GPIO46,
-	TNETV107X_PIN_ASR_A17,
-	TNETV107X_PIN_GPIO47,
-	TNETV107X_PIN_ASR_A18,
-	TNETV107X_PIN_GPIO48,
-	TNETV107X_PIN_SDIO1_DATA3_0,
-	TNETV107X_PIN_ASR_A19,
-	TNETV107X_PIN_GPIO49,
-	TNETV107X_PIN_SDIO1_DATA2_0,
-	TNETV107X_PIN_ASR_A20,
-	TNETV107X_PIN_GPIO50,
-	TNETV107X_PIN_SDIO1_DATA1_0,
-	TNETV107X_PIN_ASR_A21,
-	TNETV107X_PIN_GPIO51,
-	TNETV107X_PIN_SDIO1_DATA0_0,
-	TNETV107X_PIN_ASR_A22,
-	TNETV107X_PIN_GPIO52,
-	TNETV107X_PIN_SDIO1_CMD_0,
-	TNETV107X_PIN_ASR_A23,
-	TNETV107X_PIN_GPIO53,
-	TNETV107X_PIN_SDIO1_CLK_0,
-	TNETV107X_PIN_ASR_BA_1,
-	TNETV107X_PIN_GPIO54,
-	TNETV107X_PIN_SYS_PLL_CLK,
-	TNETV107X_PIN_ASR_CS0,
-	TNETV107X_PIN_ASR_CS1,
-	TNETV107X_PIN_ASR_CS2,
-	TNETV107X_PIN_TDM_PLL_CLK,
-	TNETV107X_PIN_ASR_CS3,
-	TNETV107X_PIN_ETH_PHY_CLK,
-	TNETV107X_PIN_ASR_D00,
-	TNETV107X_PIN_GPIO55,
-	TNETV107X_PIN_ASR_D01,
-	TNETV107X_PIN_GPIO56,
-	TNETV107X_PIN_ASR_D02,
-	TNETV107X_PIN_GPIO57,
-	TNETV107X_PIN_ASR_D03,
-	TNETV107X_PIN_GPIO58,
-	TNETV107X_PIN_ASR_D04,
-	TNETV107X_PIN_GPIO59_0,
-	TNETV107X_PIN_ASR_D05,
-	TNETV107X_PIN_GPIO60_0,
-	TNETV107X_PIN_ASR_D06,
-	TNETV107X_PIN_GPIO61_0,
-	TNETV107X_PIN_ASR_D07,
-	TNETV107X_PIN_GPIO62_0,
-	TNETV107X_PIN_ASR_D08,
-	TNETV107X_PIN_GPIO63_0,
-	TNETV107X_PIN_ASR_D09,
-	TNETV107X_PIN_GPIO64_0,
-	TNETV107X_PIN_ASR_D10,
-	TNETV107X_PIN_SDIO1_DATA3_1,
-	TNETV107X_PIN_ASR_D11,
-	TNETV107X_PIN_SDIO1_DATA2_1,
-	TNETV107X_PIN_ASR_D12,
-	TNETV107X_PIN_SDIO1_DATA1_1,
-	TNETV107X_PIN_ASR_D13,
-	TNETV107X_PIN_SDIO1_DATA0_1,
-	TNETV107X_PIN_ASR_D14,
-	TNETV107X_PIN_SDIO1_CMD_1,
-	TNETV107X_PIN_ASR_D15,
-	TNETV107X_PIN_SDIO1_CLK_1,
-	TNETV107X_PIN_ASR_OE,
-	TNETV107X_PIN_BOOT_STRP_2,
-	TNETV107X_PIN_ASR_RNW,
-	TNETV107X_PIN_GPIO29_0,
-	TNETV107X_PIN_ASR_WAIT,
-	TNETV107X_PIN_GPIO30_0,
-	TNETV107X_PIN_ASR_WE,
-	TNETV107X_PIN_BOOT_STRP_3,
-	TNETV107X_PIN_ASR_WE_DQM0,
-	TNETV107X_PIN_GPIO31,
-	TNETV107X_PIN_LCD_PD17_0,
-	TNETV107X_PIN_ASR_WE_DQM1,
-	TNETV107X_PIN_ASR_BA0_0,
-	TNETV107X_PIN_VLYNQ_CLK,
-	TNETV107X_PIN_GPIO14,
-	TNETV107X_PIN_LCD_PD19_0,
-	TNETV107X_PIN_VLYNQ_RXD0,
-	TNETV107X_PIN_GPIO15,
-	TNETV107X_PIN_LCD_PD20_0,
-	TNETV107X_PIN_VLYNQ_RXD1,
-	TNETV107X_PIN_GPIO16,
-	TNETV107X_PIN_LCD_PD21_0,
-	TNETV107X_PIN_VLYNQ_TXD0,
-	TNETV107X_PIN_GPIO17,
-	TNETV107X_PIN_LCD_PD22_0,
-	TNETV107X_PIN_VLYNQ_TXD1,
-	TNETV107X_PIN_GPIO18,
-	TNETV107X_PIN_LCD_PD23_0,
-	TNETV107X_PIN_SDIO0_CLK,
-	TNETV107X_PIN_GPIO19,
-	TNETV107X_PIN_SDIO0_CMD,
-	TNETV107X_PIN_GPIO20,
-	TNETV107X_PIN_SDIO0_DATA0,
-	TNETV107X_PIN_GPIO21,
-	TNETV107X_PIN_SDIO0_DATA1,
-	TNETV107X_PIN_GPIO22,
-	TNETV107X_PIN_SDIO0_DATA2,
-	TNETV107X_PIN_GPIO23,
-	TNETV107X_PIN_SDIO0_DATA3,
-	TNETV107X_PIN_GPIO24,
-	TNETV107X_PIN_EMU0,
-	TNETV107X_PIN_EMU1,
-	TNETV107X_PIN_RTCK,
-	TNETV107X_PIN_TRST_N,
-	TNETV107X_PIN_TCK,
-	TNETV107X_PIN_TDI,
-	TNETV107X_PIN_TDO,
-	TNETV107X_PIN_TMS,
-	TNETV107X_PIN_TDM1_CLK,
-	TNETV107X_PIN_TDM1_RX,
-	TNETV107X_PIN_TDM1_TX,
-	TNETV107X_PIN_TDM1_FS,
-	TNETV107X_PIN_KEYPAD_R0,
-	TNETV107X_PIN_KEYPAD_R1,
-	TNETV107X_PIN_KEYPAD_R2,
-	TNETV107X_PIN_KEYPAD_R3,
-	TNETV107X_PIN_KEYPAD_R4,
-	TNETV107X_PIN_KEYPAD_R5,
-	TNETV107X_PIN_KEYPAD_R6,
-	TNETV107X_PIN_GPIO12,
-	TNETV107X_PIN_KEYPAD_R7,
-	TNETV107X_PIN_GPIO10,
-	TNETV107X_PIN_KEYPAD_C0,
-	TNETV107X_PIN_KEYPAD_C1,
-	TNETV107X_PIN_KEYPAD_C2,
-	TNETV107X_PIN_KEYPAD_C3,
-	TNETV107X_PIN_KEYPAD_C4,
-	TNETV107X_PIN_KEYPAD_C5,
-	TNETV107X_PIN_KEYPAD_C6,
-	TNETV107X_PIN_GPIO13,
-	TNETV107X_PIN_TEST_CLK_IN,
-	TNETV107X_PIN_KEYPAD_C7,
-	TNETV107X_PIN_GPIO11,
-	TNETV107X_PIN_SSP0_0,
-	TNETV107X_PIN_SCC_DCLK,
-	TNETV107X_PIN_LCD_PD20_1,
-	TNETV107X_PIN_SSP0_1,
-	TNETV107X_PIN_SCC_CS_N,
-	TNETV107X_PIN_LCD_PD21_1,
-	TNETV107X_PIN_SSP0_2,
-	TNETV107X_PIN_SCC_D,
-	TNETV107X_PIN_LCD_PD22_1,
-	TNETV107X_PIN_SSP0_3,
-	TNETV107X_PIN_SCC_RESETN,
-	TNETV107X_PIN_LCD_PD23_1,
-	TNETV107X_PIN_SSP1_0,
-	TNETV107X_PIN_GPIO25,
-	TNETV107X_PIN_UART2_CTS,
-	TNETV107X_PIN_SSP1_1,
-	TNETV107X_PIN_GPIO26,
-	TNETV107X_PIN_UART2_RD,
-	TNETV107X_PIN_SSP1_2,
-	TNETV107X_PIN_GPIO27,
-	TNETV107X_PIN_UART2_RTS,
-	TNETV107X_PIN_SSP1_3,
-	TNETV107X_PIN_GPIO28,
-	TNETV107X_PIN_UART2_TD,
-	TNETV107X_PIN_UART0_CTS,
-	TNETV107X_PIN_UART0_RD,
-	TNETV107X_PIN_UART0_RTS,
-	TNETV107X_PIN_UART0_TD,
-	TNETV107X_PIN_UART1_RD,
-	TNETV107X_PIN_UART1_TD,
-	TNETV107X_PIN_LCD_AC_NCS,
-	TNETV107X_PIN_LCD_HSYNC_RNW,
-	TNETV107X_PIN_LCD_VSYNC_A0,
-	TNETV107X_PIN_LCD_MCLK,
-	TNETV107X_PIN_LCD_PD16_0,
-	TNETV107X_PIN_LCD_PCLK_E,
-	TNETV107X_PIN_LCD_PD00,
-	TNETV107X_PIN_LCD_PD01,
-	TNETV107X_PIN_LCD_PD02,
-	TNETV107X_PIN_LCD_PD03,
-	TNETV107X_PIN_LCD_PD04,
-	TNETV107X_PIN_LCD_PD05,
-	TNETV107X_PIN_LCD_PD06,
-	TNETV107X_PIN_LCD_PD07,
-	TNETV107X_PIN_LCD_PD08,
-	TNETV107X_PIN_GPIO59_1,
-	TNETV107X_PIN_LCD_PD09,
-	TNETV107X_PIN_GPIO60_1,
-	TNETV107X_PIN_LCD_PD10,
-	TNETV107X_PIN_ASR_BA0_1,
-	TNETV107X_PIN_GPIO61_1,
-	TNETV107X_PIN_LCD_PD11,
-	TNETV107X_PIN_GPIO62_1,
-	TNETV107X_PIN_LCD_PD12,
-	TNETV107X_PIN_GPIO63_1,
-	TNETV107X_PIN_LCD_PD13,
-	TNETV107X_PIN_GPIO64_1,
-	TNETV107X_PIN_LCD_PD14,
-	TNETV107X_PIN_GPIO29_1,
-	TNETV107X_PIN_LCD_PD15,
-	TNETV107X_PIN_GPIO30_1,
-	TNETV107X_PIN_EINT0,
-	TNETV107X_PIN_GPIO08,
-	TNETV107X_PIN_EINT1,
-	TNETV107X_PIN_GPIO09,
-	TNETV107X_PIN_GPIO00,
-	TNETV107X_PIN_LCD_PD20_2,
-	TNETV107X_PIN_TDM_CLK_IN_2,
-	TNETV107X_PIN_GPIO01,
-	TNETV107X_PIN_LCD_PD21_2,
-	TNETV107X_PIN_24M_CLK_OUT_1,
-	TNETV107X_PIN_GPIO02,
-	TNETV107X_PIN_LCD_PD22_2,
-	TNETV107X_PIN_GPIO03,
-	TNETV107X_PIN_LCD_PD23_2,
-	TNETV107X_PIN_GPIO04,
-	TNETV107X_PIN_LCD_PD16_1,
-	TNETV107X_PIN_USB0_RXERR,
-	TNETV107X_PIN_GPIO05,
-	TNETV107X_PIN_LCD_PD17_1,
-	TNETV107X_PIN_TDM_CLK_IN_1,
-	TNETV107X_PIN_GPIO06,
-	TNETV107X_PIN_LCD_PD18,
-	TNETV107X_PIN_24M_CLK_OUT_2,
-	TNETV107X_PIN_GPIO07,
-	TNETV107X_PIN_LCD_PD19_1,
-	TNETV107X_PIN_USB1_RXERR,
-	TNETV107X_PIN_ETH_PLL_CLK,
-	TNETV107X_PIN_MDIO,
-	TNETV107X_PIN_MDC,
-	TNETV107X_PIN_AIC_MUTE_STAT_N,
-	TNETV107X_PIN_TDM0_CLK,
-	TNETV107X_PIN_AIC_HNS_EN_N,
-	TNETV107X_PIN_TDM0_FS,
-	TNETV107X_PIN_AIC_HDS_EN_STAT_N,
-	TNETV107X_PIN_TDM0_TX,
-	TNETV107X_PIN_AIC_HNF_EN_STAT_N,
-	TNETV107X_PIN_TDM0_RX,
-};
-
-#endif
diff --git a/arch/arm/include/asm/arch-tnetv107x/nand_defs.h b/arch/arm/include/asm/arch-tnetv107x/nand_defs.h
deleted file mode 100644
index 961b710..0000000
--- a/arch/arm/include/asm/arch-tnetv107x/nand_defs.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- * TNETV107X: NAND definitions
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-#ifndef _NAND_DEFS_H_
-#define _NAND_DEFS_H_
-
-#include <asm/arch/hardware.h>
-#include <asm/arch/emif_defs.h>
-
-#define DAVINCI_ASYNC_EMIF_CNTRL_BASE	TNETV107X_ASYNC_EMIF_CNTRL_BASE
-
-#define	MASK_CLE		0x4000
-#define	MASK_ALE		0x2000
-
-#define NAND_READ_START		0x00
-#define NAND_READ_END		0x30
-#define NAND_STATUS		0x70
-
-extern void davinci_nand_init(struct nand_chip *nand);
-
-#endif
diff --git a/arch/arm/include/asm/atomic.h b/arch/arm/include/asm/atomic.h
deleted file mode 100644
index ba9e4b7..0000000
--- a/arch/arm/include/asm/atomic.h
+++ /dev/null
@@ -1,113 +0,0 @@
-/*
- *  linux/include/asm-arm/atomic.h
- *
- *  Copyright (c) 1996 Russell King.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- *  Changelog:
- *   27-06-1996	RMK	Created
- *   13-04-1997	RMK	Made functions atomic!
- *   07-12-1997	RMK	Upgraded for v2.1.
- *   26-08-1998	PJB	Added #ifdef __KERNEL__
- */
-#ifndef __ASM_ARM_ATOMIC_H
-#define __ASM_ARM_ATOMIC_H
-
-#include <linux/config.h>
-
-#ifdef CONFIG_SMP
-#error SMP not supported
-#endif
-
-typedef struct { volatile int counter; } atomic_t;
-
-#define ATOMIC_INIT(i)	{ (i) }
-
-#ifdef __KERNEL__
-#include <asm/proc/system.h>
-
-#define atomic_read(v)	((v)->counter)
-#define atomic_set(v,i)	(((v)->counter) = (i))
-
-static inline void atomic_add(int i, volatile atomic_t *v)
-{
-	unsigned long flags;
-
-	local_irq_save(flags);
-	v->counter += i;
-	local_irq_restore(flags);
-}
-
-static inline void atomic_sub(int i, volatile atomic_t *v)
-{
-	unsigned long flags;
-
-	local_irq_save(flags);
-	v->counter -= i;
-	local_irq_restore(flags);
-}
-
-static inline void atomic_inc(volatile atomic_t *v)
-{
-	unsigned long flags;
-
-	local_irq_save(flags);
-	v->counter += 1;
-	local_irq_restore(flags);
-}
-
-static inline void atomic_dec(volatile atomic_t *v)
-{
-	unsigned long flags;
-
-	local_irq_save(flags);
-	v->counter -= 1;
-	local_irq_restore(flags);
-}
-
-static inline int atomic_dec_and_test(volatile atomic_t *v)
-{
-	unsigned long flags;
-	int val;
-
-	local_irq_save(flags);
-	val = v->counter;
-	v->counter = val -= 1;
-	local_irq_restore(flags);
-
-	return val == 0;
-}
-
-static inline int atomic_add_negative(int i, volatile atomic_t *v)
-{
-	unsigned long flags;
-	int val;
-
-	local_irq_save(flags);
-	val = v->counter;
-	v->counter = val += i;
-	local_irq_restore(flags);
-
-	return val < 0;
-}
-
-static inline void atomic_clear_mask(unsigned long mask, unsigned long *addr)
-{
-	unsigned long flags;
-
-	local_irq_save(flags);
-	*addr &= ~mask;
-	local_irq_restore(flags);
-}
-
-/* Atomic operations are already serializing on ARM */
-#define smp_mb__before_atomic_dec()	barrier()
-#define smp_mb__after_atomic_dec()	barrier()
-#define smp_mb__before_atomic_inc()	barrier()
-#define smp_mb__after_atomic_inc()	barrier()
-
-#endif
-#endif
diff --git a/arch/arm/include/asm/bitops.h b/arch/arm/include/asm/bitops.h
deleted file mode 100644
index 270f163..0000000
--- a/arch/arm/include/asm/bitops.h
+++ /dev/null
@@ -1,151 +0,0 @@
-/*
- * Copyright 1995, Russell King.
- * Various bits and pieces copyrights include:
- *  Linus Torvalds (test_bit).
- *
- * bit 0 is the LSB of addr; bit 32 is the LSB of (addr+1).
- *
- * Please note that the code in this file should never be included
- * from user space.  Many of these are not implemented in assembler
- * since they would be too costly.  Also, they require priviledged
- * instructions (which are not available from user mode) to ensure
- * that they are atomic.
- */
-
-#ifndef __ASM_ARM_BITOPS_H
-#define __ASM_ARM_BITOPS_H
-
-#ifdef __KERNEL__
-
-#include <asm/proc/system.h>
-
-#define smp_mb__before_clear_bit()	do { } while (0)
-#define smp_mb__after_clear_bit()	do { } while (0)
-
-/*
- * Function prototypes to keep gcc -Wall happy.
- */
-extern void set_bit(int nr, volatile void * addr);
-
-extern void clear_bit(int nr, volatile void * addr);
-
-extern void change_bit(int nr, volatile void * addr);
-
-static inline void __change_bit(int nr, volatile void *addr)
-{
-	unsigned long mask = BIT_MASK(nr);
-	unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
-
-	*p ^= mask;
-}
-
-static inline int __test_and_set_bit(int nr, volatile void *addr)
-{
-	unsigned long mask = BIT_MASK(nr);
-	unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
-	unsigned long old = *p;
-
-	*p = old | mask;
-	return (old & mask) != 0;
-}
-
-static inline int test_and_set_bit(int nr, volatile void * addr)
-{
-	unsigned long flags;
-	int out;
-
-	local_irq_save(flags);
-	out = __test_and_set_bit(nr, addr);
-	local_irq_restore(flags);
-
-	return out;
-}
-
-static inline int __test_and_clear_bit(int nr, volatile void *addr)
-{
-	unsigned long mask = BIT_MASK(nr);
-	unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
-	unsigned long old = *p;
-
-	*p = old & ~mask;
-	return (old & mask) != 0;
-}
-
-static inline int test_and_clear_bit(int nr, volatile void * addr)
-{
-	unsigned long flags;
-	int out;
-
-	local_irq_save(flags);
-	out = __test_and_clear_bit(nr, addr);
-	local_irq_restore(flags);
-
-	return out;
-}
-
-extern int test_and_change_bit(int nr, volatile void * addr);
-
-static inline int __test_and_change_bit(int nr, volatile void *addr)
-{
-	unsigned long mask = BIT_MASK(nr);
-	unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
-	unsigned long old = *p;
-
-	*p = old ^ mask;
-	return (old & mask) != 0;
-}
-
-extern int find_first_zero_bit(void * addr, unsigned size);
-extern int find_next_zero_bit(void * addr, int size, int offset);
-
-/*
- * This routine doesn't need to be atomic.
- */
-static inline int test_bit(int nr, const void * addr)
-{
-    return ((unsigned char *) addr)[nr >> 3] & (1U << (nr & 7));
-}
-
-/*
- * ffz = Find First Zero in word. Undefined if no zero exists,
- * so code should check against ~0UL first..
- */
-static inline unsigned long ffz(unsigned long word)
-{
-	int k;
-
-	word = ~word;
-	k = 31;
-	if (word & 0x0000ffff) { k -= 16; word <<= 16; }
-	if (word & 0x00ff0000) { k -= 8;  word <<= 8;  }
-	if (word & 0x0f000000) { k -= 4;  word <<= 4;  }
-	if (word & 0x30000000) { k -= 2;  word <<= 2;  }
-	if (word & 0x40000000) { k -= 1; }
-	return k;
-}
-
-/*
- * hweightN: returns the hamming weight (i.e. the number
- * of bits set) of a N-bit word
- */
-
-#define hweight32(x) generic_hweight32(x)
-#define hweight16(x) generic_hweight16(x)
-#define hweight8(x) generic_hweight8(x)
-
-#define ext2_set_bit			test_and_set_bit
-#define ext2_clear_bit			test_and_clear_bit
-#define ext2_test_bit			test_bit
-#define ext2_find_first_zero_bit	find_first_zero_bit
-#define ext2_find_next_zero_bit		find_next_zero_bit
-
-/* Bitmap functions for the minix filesystem. */
-#define minix_test_and_set_bit(nr,addr)	test_and_set_bit(nr,addr)
-#define minix_set_bit(nr,addr)		set_bit(nr,addr)
-#define minix_test_and_clear_bit(nr,addr)	test_and_clear_bit(nr,addr)
-#define minix_test_bit(nr,addr)		test_bit(nr,addr)
-#define minix_find_first_zero_bit(addr,size)	find_first_zero_bit(addr,size)
-
-#endif /* __KERNEL__ */
-
-#endif /* _ARM_BITOPS_H */
diff --git a/arch/arm/include/asm/byteorder.h b/arch/arm/include/asm/byteorder.h
deleted file mode 100644
index c3489f1..0000000
--- a/arch/arm/include/asm/byteorder.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/*
- *  linux/include/asm-arm/byteorder.h
- *
- * ARM Endian-ness.  In little endian mode, the data bus is connected such
- * that byte accesses appear as:
- *  0 = d0...d7, 1 = d8...d15, 2 = d16...d23, 3 = d24...d31
- * and word accesses (data or instruction) appear as:
- *  d0...d31
- *
- * When in big endian mode, byte accesses appear as:
- *  0 = d24...d31, 1 = d16...d23, 2 = d8...d15, 3 = d0...d7
- * and word accesses (data or instruction) appear as:
- *  d0...d31
- */
-#ifndef __ASM_ARM_BYTEORDER_H
-#define __ASM_ARM_BYTEORDER_H
-
-
-#include <asm/types.h>
-
-#if !defined(__STRICT_ANSI__) || defined(__KERNEL__)
-#  define __BYTEORDER_HAS_U64__
-#  define __SWAB_64_THRU_32__
-#endif
-
-#ifdef __ARMEB__
-#include <linux/byteorder/big_endian.h>
-#else
-#include <linux/byteorder/little_endian.h>
-#endif
-
-#endif
diff --git a/arch/arm/include/asm/cache.h b/arch/arm/include/asm/cache.h
deleted file mode 100644
index d0518be..0000000
--- a/arch/arm/include/asm/cache.h
+++ /dev/null
@@ -1,45 +0,0 @@
-/*
- * (C) Copyright 2009
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-#ifndef _ASM_CACHE_H
-#define _ASM_CACHE_H
-
-#include <asm/system.h>
-
-/*
- * Invalidate L2 Cache using co-proc instruction
- */
-static inline void invalidate_l2_cache(void)
-{
-	unsigned int val=0;
-
-	asm volatile("mcr p15, 1, %0, c15, c11, 0 @ invl l2 cache"
-		: : "r" (val) : "cc");
-	isb();
-}
-
-void l2_cache_enable(void);
-void l2_cache_disable(void);
-
-#endif /* _ASM_CACHE_H */
diff --git a/arch/arm/include/asm/config.h b/arch/arm/include/asm/config.h
deleted file mode 100644
index c60dba2..0000000
--- a/arch/arm/include/asm/config.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * Copyright 2009 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- */
-
-#ifndef _ASM_CONFIG_H_
-#define _ASM_CONFIG_H_
-
-#define CONFIG_LMB
-#define CONFIG_SYS_BOOT_RAMDISK_HIGH
-#endif
diff --git a/arch/arm/include/asm/dma-mapping.h b/arch/arm/include/asm/dma-mapping.h
deleted file mode 100644
index 501ce0e..0000000
--- a/arch/arm/include/asm/dma-mapping.h
+++ /dev/null
@@ -1,50 +0,0 @@
-/*
- * (C) Copyright 2007
- * Stelian Pop <stelian.pop@leadtechdesign.com>
- * Lead Tech Design <www.leadtechdesign.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-#ifndef __ASM_ARM_DMA_MAPPING_H
-#define __ASM_ARM_DMA_MAPPING_H
-
-enum dma_data_direction {
-	DMA_BIDIRECTIONAL	= 0,
-	DMA_TO_DEVICE		= 1,
-	DMA_FROM_DEVICE		= 2,
-};
-
-static void *dma_alloc_coherent(size_t len, unsigned long *handle)
-{
-	*handle = (unsigned long)malloc(len);
-	return (void *)*handle;
-}
-
-static inline unsigned long dma_map_single(volatile void *vaddr, size_t len,
-					   enum dma_data_direction dir)
-{
-	return (unsigned long)vaddr;
-}
-
-static inline void dma_unmap_single(volatile void *vaddr, size_t len,
-				    unsigned long paddr)
-{
-}
-
-#endif /* __ASM_ARM_DMA_MAPPING_H */
diff --git a/arch/arm/include/asm/errno.h b/arch/arm/include/asm/errno.h
deleted file mode 100644
index 4c82b50..0000000
--- a/arch/arm/include/asm/errno.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/errno.h>
diff --git a/arch/arm/include/asm/global_data.h b/arch/arm/include/asm/global_data.h
deleted file mode 100644
index 2a84d27..0000000
--- a/arch/arm/include/asm/global_data.h
+++ /dev/null
@@ -1,94 +0,0 @@
-/*
- * (C) Copyright 2002-2010
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef	__ASM_GBL_DATA_H
-#define __ASM_GBL_DATA_H
-/*
- * The following data structure is placed in some memory wich is
- * available very early after boot (like DPRAM on MPC8xx/MPC82xx, or
- * some locked parts of the data cache) to allow for a minimum set of
- * global variables during system initialization (until we have set
- * up the memory controller so that we can use RAM).
- *
- * Keep it *SMALL* and remember to set GENERATED_GBL_DATA_SIZE > sizeof(gd_t)
- */
-
-typedef	struct	global_data {
-	bd_t		*bd;
-	unsigned long	flags;
-	unsigned long	baudrate;
-	unsigned long	have_console;	/* serial_init() was called */
-	unsigned long	env_addr;	/* Address  of Environment struct */
-	unsigned long	env_valid;	/* Checksum of Environment valid? */
-	unsigned long	fb_base;	/* base address of frame buffer */
-#ifdef CONFIG_VFD
-	unsigned char	vfd_type;	/* display type */
-#endif
-#ifdef CONFIG_FSL_ESDHC
-	unsigned long	sdhc_clk;
-#endif
-#ifdef CONFIG_AT91FAMILY
-	/* "static data" needed by at91's clock.c */
-	unsigned long	cpu_clk_rate_hz;
-	unsigned long	main_clk_rate_hz;
-	unsigned long	mck_rate_hz;
-	unsigned long	plla_rate_hz;
-	unsigned long	pllb_rate_hz;
-	unsigned long	at91_pllb_usb_init;
-#endif
-#ifdef CONFIG_ARM
-	/* "static data" needed by most of timer.c on ARM platforms */
-	unsigned long	timer_rate_hz;
-	unsigned long	tbl;
-	unsigned long	tbu;
-	unsigned long long	timer_reset_value;
-	unsigned long	lastinc;
-#endif
-	unsigned long	relocaddr;	/* Start address of U-Boot in RAM */
-	phys_size_t	ram_size;	/* RAM size */
-	unsigned long	mon_len;	/* monitor len */
-	unsigned long	irq_sp;		/* irq stack pointer */
-	unsigned long	start_addr_sp;	/* start_addr_stackpointer */
-	unsigned long	reloc_off;
-#if !(defined(CONFIG_SYS_NO_ICACHE) && defined(CONFIG_SYS_NO_DCACHE))
-	unsigned long	tlb_addr;
-#endif
-	void		**jt;		/* jump table */
-	char		env_buf[32];	/* buffer for getenv() before reloc. */
-} gd_t;
-
-/*
- * Global Data Flags
- */
-#define	GD_FLG_RELOC		0x00001	/* Code was relocated to RAM		*/
-#define	GD_FLG_DEVINIT		0x00002	/* Devices have been initialized	*/
-#define	GD_FLG_SILENT		0x00004	/* Silent mode				*/
-#define	GD_FLG_POSTFAIL		0x00008	/* Critical POST test failed		*/
-#define	GD_FLG_POSTSTOP		0x00010	/* POST seqeunce aborted		*/
-#define	GD_FLG_LOGINIT		0x00020	/* Log Buffer has been initialized	*/
-#define GD_FLG_DISABLE_CONSOLE	0x00040	/* Disable console (in & out)		*/
-#define GD_FLG_ENV_READY	0x00080	/* Environment imported into hash table	*/
-
-#define DECLARE_GLOBAL_DATA_PTR     register volatile gd_t *gd asm ("r8")
-
-#endif /* __ASM_GBL_DATA_H */
diff --git a/arch/arm/include/asm/hardware.h b/arch/arm/include/asm/hardware.h
deleted file mode 100644
index 1fd1a5b..0000000
--- a/arch/arm/include/asm/hardware.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/*
- *  linux/include/asm-arm/hardware.h
- *
- *  Copyright (C) 1996 Russell King
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- *  Common hardware definitions
- */
-
-#ifndef __ASM_HARDWARE_H
-#define __ASM_HARDWARE_H
-
-#include <asm/arch/hardware.h>
-
-#endif
diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h
deleted file mode 100644
index 1fbc531..0000000
--- a/arch/arm/include/asm/io.h
+++ /dev/null
@@ -1,437 +0,0 @@
-/*
- *  linux/include/asm-arm/io.h
- *
- *  Copyright (C) 1996-2000 Russell King
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * Modifications:
- *  16-Sep-1996	RMK	Inlined the inx/outx functions & optimised for both
- *			constant addresses and variable addresses.
- *  04-Dec-1997	RMK	Moved a lot of this stuff to the new architecture
- *			specific IO header files.
- *  27-Mar-1999	PJB	Second parameter of memcpy_toio is const..
- *  04-Apr-1999	PJB	Added check_signature.
- *  12-Dec-1999	RMK	More cleanups
- *  18-Jun-2000 RMK	Removed virt_to_* and friends definitions
- */
-#ifndef __ASM_ARM_IO_H
-#define __ASM_ARM_IO_H
-
-#ifdef __KERNEL__
-
-#include <linux/types.h>
-#include <asm/byteorder.h>
-#include <asm/memory.h>
-#if 0	/* XXX###XXX */
-#include <asm/arch/hardware.h>
-#endif	/* XXX###XXX */
-
-static inline void sync(void)
-{
-}
-
-/*
- * Given a physical address and a length, return a virtual address
- * that can be used to access the memory range with the caching
- * properties specified by "flags".
- */
-#define MAP_NOCACHE	(0)
-#define MAP_WRCOMBINE	(0)
-#define MAP_WRBACK	(0)
-#define MAP_WRTHROUGH	(0)
-
-static inline void *
-map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags)
-{
-	return (void *)paddr;
-}
-
-/*
- * Take down a mapping set up by map_physmem().
- */
-static inline void unmap_physmem(void *vaddr, unsigned long flags)
-{
-
-}
-
-static inline phys_addr_t virt_to_phys(void * vaddr)
-{
-	return (phys_addr_t)(vaddr);
-}
-
-/*
- * Generic virtual read/write.  Note that we don't support half-word
- * read/writes.  We define __arch_*[bl] here, and leave __arch_*w
- * to the architecture specific code.
- */
-#define __arch_getb(a)			(*(volatile unsigned char *)(a))
-#define __arch_getw(a)			(*(volatile unsigned short *)(a))
-#define __arch_getl(a)			(*(volatile unsigned int *)(a))
-
-#define __arch_putb(v,a)		(*(volatile unsigned char *)(a) = (v))
-#define __arch_putw(v,a)		(*(volatile unsigned short *)(a) = (v))
-#define __arch_putl(v,a)		(*(volatile unsigned int *)(a) = (v))
-
-extern inline void __raw_writesb(unsigned int addr, const void *data, int bytelen)
-{
-	uint8_t *buf = (uint8_t *)data;
-	while(bytelen--)
-		__arch_putb(*buf++, addr);
-}
-
-extern inline void __raw_writesw(unsigned int addr, const void *data, int wordlen)
-{
-	uint16_t *buf = (uint16_t *)data;
-	while(wordlen--)
-		__arch_putw(*buf++, addr);
-}
-
-extern inline void __raw_writesl(unsigned int addr, const void *data, int longlen)
-{
-	uint32_t *buf = (uint32_t *)data;
-	while(longlen--)
-		__arch_putl(*buf++, addr);
-}
-
-extern inline void __raw_readsb(unsigned int addr, void *data, int bytelen)
-{
-	uint8_t *buf = (uint8_t *)data;
-	while(bytelen--)
-		*buf++ = __arch_getb(addr);
-}
-
-extern inline void __raw_readsw(unsigned int addr, void *data, int wordlen)
-{
-	uint16_t *buf = (uint16_t *)data;
-	while(wordlen--)
-		*buf++ = __arch_getw(addr);
-}
-
-extern inline void __raw_readsl(unsigned int addr, void *data, int longlen)
-{
-	uint32_t *buf = (uint32_t *)data;
-	while(longlen--)
-		*buf++ = __arch_getl(addr);
-}
-
-#define __raw_writeb(v,a)	__arch_putb(v,a)
-#define __raw_writew(v,a)	__arch_putw(v,a)
-#define __raw_writel(v,a)	__arch_putl(v,a)
-
-#define __raw_readb(a)		__arch_getb(a)
-#define __raw_readw(a)		__arch_getw(a)
-#define __raw_readl(a)		__arch_getl(a)
-
-/*
- * TODO: The kernel offers some more advanced versions of barriers, it might
- * have some advantages to use them instead of the simple one here.
- */
-#define dmb()		__asm__ __volatile__ ("" : : : "memory")
-#define __iormb()	dmb()
-#define __iowmb()	dmb()
-
-#define writeb(v,c)	({ u8  __v = v; __iowmb(); __arch_putb(__v,c); __v; })
-#define writew(v,c)	({ u16 __v = v; __iowmb(); __arch_putw(__v,c); __v; })
-#define writel(v,c)	({ u32 __v = v; __iowmb(); __arch_putl(__v,c); __v; })
-
-#define readb(c)	({ u8  __v = __arch_getb(c); __iormb(); __v; })
-#define readw(c)	({ u16 __v = __arch_getw(c); __iormb(); __v; })
-#define readl(c)	({ u32 __v = __arch_getl(c); __iormb(); __v; })
-
-/*
- * The compiler seems to be incapable of optimising constants
- * properly.  Spell it out to the compiler in some cases.
- * These are only valid for small values of "off" (< 1<<12)
- */
-#define __raw_base_writeb(val,base,off)	__arch_base_putb(val,base,off)
-#define __raw_base_writew(val,base,off)	__arch_base_putw(val,base,off)
-#define __raw_base_writel(val,base,off)	__arch_base_putl(val,base,off)
-
-#define __raw_base_readb(base,off)	__arch_base_getb(base,off)
-#define __raw_base_readw(base,off)	__arch_base_getw(base,off)
-#define __raw_base_readl(base,off)	__arch_base_getl(base,off)
-
-/*
- * Clear and set bits in one shot. These macros can be used to clear and
- * set multiple bits in a register using a single call. These macros can
- * also be used to set a multiple-bit bit pattern using a mask, by
- * specifying the mask in the 'clear' parameter and the new bit pattern
- * in the 'set' parameter.
- */
-
-#define out_arch(type,endian,a,v)	__raw_write##type(cpu_to_##endian(v),a)
-#define in_arch(type,endian,a)		endian##_to_cpu(__raw_read##type(a))
-
-#define out_le32(a,v)	out_arch(l,le32,a,v)
-#define out_le16(a,v)	out_arch(w,le16,a,v)
-
-#define in_le32(a)	in_arch(l,le32,a)
-#define in_le16(a)	in_arch(w,le16,a)
-
-#define out_be32(a,v)	out_arch(l,be32,a,v)
-#define out_be16(a,v)	out_arch(w,be16,a,v)
-
-#define in_be32(a)	in_arch(l,be32,a)
-#define in_be16(a)	in_arch(w,be16,a)
-
-#define out_8(a,v)	__raw_writeb(v,a)
-#define in_8(a)		__raw_readb(a)
-
-#define clrbits(type, addr, clear) \
-	out_##type((addr), in_##type(addr) & ~(clear))
-
-#define setbits(type, addr, set) \
-	out_##type((addr), in_##type(addr) | (set))
-
-#define clrsetbits(type, addr, clear, set) \
-	out_##type((addr), (in_##type(addr) & ~(clear)) | (set))
-
-#define clrbits_be32(addr, clear) clrbits(be32, addr, clear)
-#define setbits_be32(addr, set) setbits(be32, addr, set)
-#define clrsetbits_be32(addr, clear, set) clrsetbits(be32, addr, clear, set)
-
-#define clrbits_le32(addr, clear) clrbits(le32, addr, clear)
-#define setbits_le32(addr, set) setbits(le32, addr, set)
-#define clrsetbits_le32(addr, clear, set) clrsetbits(le32, addr, clear, set)
-
-#define clrbits_be16(addr, clear) clrbits(be16, addr, clear)
-#define setbits_be16(addr, set) setbits(be16, addr, set)
-#define clrsetbits_be16(addr, clear, set) clrsetbits(be16, addr, clear, set)
-
-#define clrbits_le16(addr, clear) clrbits(le16, addr, clear)
-#define setbits_le16(addr, set) setbits(le16, addr, set)
-#define clrsetbits_le16(addr, clear, set) clrsetbits(le16, addr, clear, set)
-
-#define clrbits_8(addr, clear) clrbits(8, addr, clear)
-#define setbits_8(addr, set) setbits(8, addr, set)
-#define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set)
-
-/*
- * Now, pick up the machine-defined IO definitions
- */
-#if 0	/* XXX###XXX */
-#include <asm/arch/io.h>
-#endif	/* XXX###XXX */
-
-/*
- *  IO port access primitives
- *  -------------------------
- *
- * The ARM doesn't have special IO access instructions; all IO is memory
- * mapped.  Note that these are defined to perform little endian accesses
- * only.  Their primary purpose is to access PCI and ISA peripherals.
- *
- * Note that for a big endian machine, this implies that the following
- * big endian mode connectivity is in place, as described by numerous
- * ARM documents:
- *
- *    PCI:  D0-D7   D8-D15 D16-D23 D24-D31
- *    ARM: D24-D31 D16-D23  D8-D15  D0-D7
- *
- * The machine specific io.h include defines __io to translate an "IO"
- * address to a memory address.
- *
- * Note that we prevent GCC re-ordering or caching values in expressions
- * by introducing sequence points into the in*() definitions.  Note that
- * __raw_* do not guarantee this behaviour.
- *
- * The {in,out}[bwl] macros are for emulating x86-style PCI/ISA IO space.
- */
-#ifdef __io
-#define outb(v,p)			__raw_writeb(v,__io(p))
-#define outw(v,p)			__raw_writew(cpu_to_le16(v),__io(p))
-#define outl(v,p)			__raw_writel(cpu_to_le32(v),__io(p))
-
-#define inb(p)	({ unsigned int __v = __raw_readb(__io(p)); __v; })
-#define inw(p)	({ unsigned int __v = le16_to_cpu(__raw_readw(__io(p))); __v; })
-#define inl(p)	({ unsigned int __v = le32_to_cpu(__raw_readl(__io(p))); __v; })
-
-#define outsb(p,d,l)			__raw_writesb(__io(p),d,l)
-#define outsw(p,d,l)			__raw_writesw(__io(p),d,l)
-#define outsl(p,d,l)			__raw_writesl(__io(p),d,l)
-
-#define insb(p,d,l)			__raw_readsb(__io(p),d,l)
-#define insw(p,d,l)			__raw_readsw(__io(p),d,l)
-#define insl(p,d,l)			__raw_readsl(__io(p),d,l)
-#endif
-
-#define outb_p(val,port)		outb((val),(port))
-#define outw_p(val,port)		outw((val),(port))
-#define outl_p(val,port)		outl((val),(port))
-#define inb_p(port)			inb((port))
-#define inw_p(port)			inw((port))
-#define inl_p(port)			inl((port))
-
-#define outsb_p(port,from,len)		outsb(port,from,len)
-#define outsw_p(port,from,len)		outsw(port,from,len)
-#define outsl_p(port,from,len)		outsl(port,from,len)
-#define insb_p(port,to,len)		insb(port,to,len)
-#define insw_p(port,to,len)		insw(port,to,len)
-#define insl_p(port,to,len)		insl(port,to,len)
-
-/*
- * ioremap and friends.
- *
- * ioremap takes a PCI memory address, as specified in
- * linux/Documentation/IO-mapping.txt.  If you want a
- * physical address, use __ioremap instead.
- */
-extern void * __ioremap(unsigned long offset, size_t size, unsigned long flags);
-extern void __iounmap(void *addr);
-
-/*
- * Generic ioremap support.
- *
- * Define:
- *  iomem_valid_addr(off,size)
- *  iomem_to_phys(off)
- */
-#ifdef iomem_valid_addr
-#define __arch_ioremap(off,sz,nocache)					\
- ({									\
-	unsigned long _off = (off), _size = (sz);			\
-	void *_ret = (void *)0;						\
-	if (iomem_valid_addr(_off, _size))				\
-		_ret = __ioremap(iomem_to_phys(_off),_size,nocache);	\
-	_ret;								\
- })
-
-#define __arch_iounmap __iounmap
-#endif
-
-#define ioremap(off,sz)			__arch_ioremap((off),(sz),0)
-#define ioremap_nocache(off,sz)		__arch_ioremap((off),(sz),1)
-#define iounmap(_addr)			__arch_iounmap(_addr)
-
-/*
- * DMA-consistent mapping functions.  These allocate/free a region of
- * uncached, unwrite-buffered mapped memory space for use with DMA
- * devices.  This is the "generic" version.  The PCI specific version
- * is in pci.h
- */
-extern void *consistent_alloc(int gfp, size_t size, dma_addr_t *handle);
-extern void consistent_free(void *vaddr, size_t size, dma_addr_t handle);
-extern void consistent_sync(void *vaddr, size_t size, int rw);
-
-/*
- * String version of IO memory access ops:
- */
-extern void _memcpy_fromio(void *, unsigned long, size_t);
-extern void _memcpy_toio(unsigned long, const void *, size_t);
-extern void _memset_io(unsigned long, int, size_t);
-
-extern void __readwrite_bug(const char *fn);
-
-/*
- * If this architecture has PCI memory IO, then define the read/write
- * macros.  These should only be used with the cookie passed from
- * ioremap.
- */
-#ifdef __mem_pci
-
-#define readb(c) ({ unsigned int __v = __raw_readb(__mem_pci(c)); __v; })
-#define readw(c) ({ unsigned int __v = le16_to_cpu(__raw_readw(__mem_pci(c))); __v; })
-#define readl(c) ({ unsigned int __v = le32_to_cpu(__raw_readl(__mem_pci(c))); __v; })
-
-#define writeb(v,c)		__raw_writeb(v,__mem_pci(c))
-#define writew(v,c)		__raw_writew(cpu_to_le16(v),__mem_pci(c))
-#define writel(v,c)		__raw_writel(cpu_to_le32(v),__mem_pci(c))
-
-#define memset_io(c,v,l)		_memset_io(__mem_pci(c),(v),(l))
-#define memcpy_fromio(a,c,l)		_memcpy_fromio((a),__mem_pci(c),(l))
-#define memcpy_toio(c,a,l)		_memcpy_toio(__mem_pci(c),(a),(l))
-
-#define eth_io_copy_and_sum(s,c,l,b) \
-				eth_copy_and_sum((s),__mem_pci(c),(l),(b))
-
-static inline int
-check_signature(unsigned long io_addr, const unsigned char *signature,
-		int length)
-{
-	int retval = 0;
-	do {
-		if (readb(io_addr) != *signature)
-			goto out;
-		io_addr++;
-		signature++;
-		length--;
-	} while (length);
-	retval = 1;
-out:
-	return retval;
-}
-
-#elif !defined(readb)
-
-#define readb(addr)			(__readwrite_bug("readb"),0)
-#define readw(addr)			(__readwrite_bug("readw"),0)
-#define readl(addr)			(__readwrite_bug("readl"),0)
-#define writeb(v,addr)			__readwrite_bug("writeb")
-#define writew(v,addr)			__readwrite_bug("writew")
-#define writel(v,addr)			__readwrite_bug("writel")
-
-#define eth_io_copy_and_sum(a,b,c,d)	__readwrite_bug("eth_io_copy_and_sum")
-
-#define check_signature(io,sig,len)	(0)
-
-#endif	/* __mem_pci */
-
-/*
- * If this architecture has ISA IO, then define the isa_read/isa_write
- * macros.
- */
-#ifdef __mem_isa
-
-#define isa_readb(addr)			__raw_readb(__mem_isa(addr))
-#define isa_readw(addr)			__raw_readw(__mem_isa(addr))
-#define isa_readl(addr)			__raw_readl(__mem_isa(addr))
-#define isa_writeb(val,addr)		__raw_writeb(val,__mem_isa(addr))
-#define isa_writew(val,addr)		__raw_writew(val,__mem_isa(addr))
-#define isa_writel(val,addr)		__raw_writel(val,__mem_isa(addr))
-#define isa_memset_io(a,b,c)		_memset_io(__mem_isa(a),(b),(c))
-#define isa_memcpy_fromio(a,b,c)	_memcpy_fromio((a),__mem_isa(b),(c))
-#define isa_memcpy_toio(a,b,c)		_memcpy_toio(__mem_isa((a)),(b),(c))
-
-#define isa_eth_io_copy_and_sum(a,b,c,d) \
-				eth_copy_and_sum((a),__mem_isa(b),(c),(d))
-
-static inline int
-isa_check_signature(unsigned long io_addr, const unsigned char *signature,
-		    int length)
-{
-	int retval = 0;
-	do {
-		if (isa_readb(io_addr) != *signature)
-			goto out;
-		io_addr++;
-		signature++;
-		length--;
-	} while (length);
-	retval = 1;
-out:
-	return retval;
-}
-
-#else	/* __mem_isa */
-
-#define isa_readb(addr)			(__readwrite_bug("isa_readb"),0)
-#define isa_readw(addr)			(__readwrite_bug("isa_readw"),0)
-#define isa_readl(addr)			(__readwrite_bug("isa_readl"),0)
-#define isa_writeb(val,addr)		__readwrite_bug("isa_writeb")
-#define isa_writew(val,addr)		__readwrite_bug("isa_writew")
-#define isa_writel(val,addr)		__readwrite_bug("isa_writel")
-#define isa_memset_io(a,b,c)		__readwrite_bug("isa_memset_io")
-#define isa_memcpy_fromio(a,b,c)	__readwrite_bug("isa_memcpy_fromio")
-#define isa_memcpy_toio(a,b,c)		__readwrite_bug("isa_memcpy_toio")
-
-#define isa_eth_io_copy_and_sum(a,b,c,d) \
-				__readwrite_bug("isa_eth_io_copy_and_sum")
-
-#define isa_check_signature(io,sig,len)	(0)
-
-#endif	/* __mem_isa */
-#endif	/* __KERNEL__ */
-#endif	/* __ASM_ARM_IO_H */
diff --git a/arch/arm/include/asm/mach-types.h b/arch/arm/include/asm/mach-types.h
deleted file mode 100644
index a1fd03a..0000000
--- a/arch/arm/include/asm/mach-types.h
+++ /dev/null
@@ -1,42924 +0,0 @@
-/*
- * This was automagically generated from arch/arm/tools/mach-types!
- * Do NOT edit
- */
-
-#ifndef __ASM_ARM_MACH_TYPE_H
-#define __ASM_ARM_MACH_TYPE_H
-
-#ifndef __ASSEMBLY__
-/* The type of machine we're running on */
-extern unsigned int __machine_arch_type;
-#endif
-
-/* see arch/arm/kernel/arch.c for a description of these */
-#define MACH_TYPE_EBSA110              0
-#define MACH_TYPE_RISCPC               1
-#define MACH_TYPE_NEXUSPCI             3
-#define MACH_TYPE_EBSA285              4
-#define MACH_TYPE_NETWINDER            5
-#define MACH_TYPE_CATS                 6
-#define MACH_TYPE_TBOX                 7
-#define MACH_TYPE_CO285                8
-#define MACH_TYPE_CLPS7110             9
-#define MACH_TYPE_ARCHIMEDES           10
-#define MACH_TYPE_A5K                  11
-#define MACH_TYPE_ETOILE               12
-#define MACH_TYPE_LACIE_NAS            13
-#define MACH_TYPE_CLPS7500             14
-#define MACH_TYPE_SHARK                15
-#define MACH_TYPE_BRUTUS               16
-#define MACH_TYPE_PERSONAL_SERVER      17
-#define MACH_TYPE_ITSY                 18
-#define MACH_TYPE_L7200                19
-#define MACH_TYPE_PLEB                 20
-#define MACH_TYPE_INTEGRATOR           21
-#define MACH_TYPE_H3600                22
-#define MACH_TYPE_IXP1200              23
-#define MACH_TYPE_P720T                24
-#define MACH_TYPE_ASSABET              25
-#define MACH_TYPE_VICTOR               26
-#define MACH_TYPE_LART                 27
-#define MACH_TYPE_RANGER               28
-#define MACH_TYPE_GRAPHICSCLIENT       29
-#define MACH_TYPE_XP860                30
-#define MACH_TYPE_CERF                 31
-#define MACH_TYPE_NANOENGINE           32
-#define MACH_TYPE_FPIC                 33
-#define MACH_TYPE_EXTENEX1             34
-#define MACH_TYPE_SHERMAN              35
-#define MACH_TYPE_ACCELENT_SA          36
-#define MACH_TYPE_ACCELENT_L7200       37
-#define MACH_TYPE_NETPORT              38
-#define MACH_TYPE_PANGOLIN             39
-#define MACH_TYPE_YOPY                 40
-#define MACH_TYPE_COOLIDGE             41
-#define MACH_TYPE_HUW_WEBPANEL         42
-#define MACH_TYPE_SPOTME               43
-#define MACH_TYPE_FREEBIRD             44
-#define MACH_TYPE_TI925                45
-#define MACH_TYPE_RISCSTATION          46
-#define MACH_TYPE_CAVY                 47
-#define MACH_TYPE_JORNADA720           48
-#define MACH_TYPE_OMNIMETER            49
-#define MACH_TYPE_EDB7211              50
-#define MACH_TYPE_CITYGO               51
-#define MACH_TYPE_PFS168               52
-#define MACH_TYPE_SPOT                 53
-#define MACH_TYPE_FLEXANET             54
-#define MACH_TYPE_WEBPAL               55
-#define MACH_TYPE_LINPDA               56
-#define MACH_TYPE_ANAKIN               57
-#define MACH_TYPE_MVI                  58
-#define MACH_TYPE_JUPITER              59
-#define MACH_TYPE_PSIONW               60
-#define MACH_TYPE_ALN                  61
-#define MACH_TYPE_CAMELOT              62
-#define MACH_TYPE_GDS2200              63
-#define MACH_TYPE_PSION_SERIES7        64
-#define MACH_TYPE_XFILE                65
-#define MACH_TYPE_ACCELENT_EP9312      66
-#define MACH_TYPE_IC200                67
-#define MACH_TYPE_CREDITLART           68
-#define MACH_TYPE_HTM                  69
-#define MACH_TYPE_IQ80310              70
-#define MACH_TYPE_FREEBOT              71
-#define MACH_TYPE_ENTEL                72
-#define MACH_TYPE_ENP3510              73
-#define MACH_TYPE_TRIZEPS              74
-#define MACH_TYPE_NESA                 75
-#define MACH_TYPE_VENUS                76
-#define MACH_TYPE_TARDIS               77
-#define MACH_TYPE_MERCURY              78
-#define MACH_TYPE_EMPEG                79
-#define MACH_TYPE_I80200FCC            80
-#define MACH_TYPE_ITT_CPB              81
-#define MACH_TYPE_SVC                  82
-#define MACH_TYPE_ALPHA2               84
-#define MACH_TYPE_ALPHA1               85
-#define MACH_TYPE_NETARM               86
-#define MACH_TYPE_SIMPAD               87
-#define MACH_TYPE_PDA1                 88
-#define MACH_TYPE_LUBBOCK              89
-#define MACH_TYPE_ANIKO                90
-#define MACH_TYPE_CLEP7212             91
-#define MACH_TYPE_CS89712              92
-#define MACH_TYPE_WEARARM              93
-#define MACH_TYPE_POSSIO_PX            94
-#define MACH_TYPE_SIDEARM              95
-#define MACH_TYPE_STORK                96
-#define MACH_TYPE_SHANNON              97
-#define MACH_TYPE_ACE                  98
-#define MACH_TYPE_BALLYARM             99
-#define MACH_TYPE_SIMPUTER             100
-#define MACH_TYPE_NEXTERM              101
-#define MACH_TYPE_SA1100_ELF           102
-#define MACH_TYPE_GATOR                103
-#define MACH_TYPE_GRANITE              104
-#define MACH_TYPE_CONSUS               105
-#define MACH_TYPE_AAED2000             106
-#define MACH_TYPE_CDB89712             107
-#define MACH_TYPE_GRAPHICSMASTER       108
-#define MACH_TYPE_ADSBITSY             109
-#define MACH_TYPE_PXA_IDP              110
-#define MACH_TYPE_PLCE                 111
-#define MACH_TYPE_PT_SYSTEM3           112
-#define MACH_TYPE_MEDALB               113
-#define MACH_TYPE_EAGLE                114
-#define MACH_TYPE_DSC21                115
-#define MACH_TYPE_DSC24                116
-#define MACH_TYPE_TI5472               117
-#define MACH_TYPE_AUTCPU12             118
-#define MACH_TYPE_UENGINE              119
-#define MACH_TYPE_BLUESTEM             120
-#define MACH_TYPE_XINGU8               121
-#define MACH_TYPE_BUSHSTB              122
-#define MACH_TYPE_EPSILON1             123
-#define MACH_TYPE_BALLOON              124
-#define MACH_TYPE_PUPPY                125
-#define MACH_TYPE_ELROY                126
-#define MACH_TYPE_GMS720               127
-#define MACH_TYPE_S24X                 128
-#define MACH_TYPE_JTEL_CLEP7312        129
-#define MACH_TYPE_CX821XX              130
-#define MACH_TYPE_EDB7312              131
-#define MACH_TYPE_BSA1110              132
-#define MACH_TYPE_POWERPIN             133
-#define MACH_TYPE_OPENARM              134
-#define MACH_TYPE_WHITECHAPEL          135
-#define MACH_TYPE_H3100                136
-#define MACH_TYPE_H3800                137
-#define MACH_TYPE_BLUE_V1              138
-#define MACH_TYPE_PXA_CERF             139
-#define MACH_TYPE_ARM7TEVB             140
-#define MACH_TYPE_D7400                141
-#define MACH_TYPE_PIRANHA              142
-#define MACH_TYPE_SBCAMELOT            143
-#define MACH_TYPE_KINGS                144
-#define MACH_TYPE_SMDK2400             145
-#define MACH_TYPE_COLLIE               146
-#define MACH_TYPE_IDR                  147
-#define MACH_TYPE_BADGE4               148
-#define MACH_TYPE_WEBNET               149
-#define MACH_TYPE_D7300                150
-#define MACH_TYPE_CEP                  151
-#define MACH_TYPE_FORTUNET             152
-#define MACH_TYPE_VC547X               153
-#define MACH_TYPE_FILEWALKER           154
-#define MACH_TYPE_NETGATEWAY           155
-#define MACH_TYPE_SYMBOL2800           156
-#define MACH_TYPE_SUNS                 157
-#define MACH_TYPE_FRODO                158
-#define MACH_TYPE_MACH_TYTE_MS301      159
-#define MACH_TYPE_MX1ADS               160
-#define MACH_TYPE_H7201                161
-#define MACH_TYPE_H7202                162
-#define MACH_TYPE_AMICO                163
-#define MACH_TYPE_IAM                  164
-#define MACH_TYPE_TT530                165
-#define MACH_TYPE_SAM2400              166
-#define MACH_TYPE_JORNADA56X           167
-#define MACH_TYPE_ACTIVE               168
-#define MACH_TYPE_IQ80321              169
-#define MACH_TYPE_WID                  170
-#define MACH_TYPE_SABINAL              171
-#define MACH_TYPE_IXP425_MATACUMBE     172
-#define MACH_TYPE_MINIPRINT            173
-#define MACH_TYPE_ADM510X              174
-#define MACH_TYPE_SVS200               175
-#define MACH_TYPE_ATG_TCU              176
-#define MACH_TYPE_JORNADA820           177
-#define MACH_TYPE_S3C44B0              178
-#define MACH_TYPE_MARGIS2              179
-#define MACH_TYPE_KS8695               180
-#define MACH_TYPE_BRH                  181
-#define MACH_TYPE_S3C2410              182
-#define MACH_TYPE_POSSIO_PX30          183
-#define MACH_TYPE_S3C2800              184
-#define MACH_TYPE_FLEETWOOD            185
-#define MACH_TYPE_OMAHA                186
-#define MACH_TYPE_TA7                  187
-#define MACH_TYPE_NOVA                 188
-#define MACH_TYPE_HMK                  189
-#define MACH_TYPE_KARO                 190
-#define MACH_TYPE_FESTER               191
-#define MACH_TYPE_GPI                  192
-#define MACH_TYPE_SMDK2410             193
-#define MACH_TYPE_I519                 194
-#define MACH_TYPE_NEXIO                195
-#define MACH_TYPE_BITBOX               196
-#define MACH_TYPE_G200                 197
-#define MACH_TYPE_GILL                 198
-#define MACH_TYPE_PXA_MERCURY          199
-#define MACH_TYPE_CEIVA                200
-#define MACH_TYPE_FRET                 201
-#define MACH_TYPE_EMAILPHONE           202
-#define MACH_TYPE_H3900                203
-#define MACH_TYPE_PXA1                 204
-#define MACH_TYPE_KOAN369              205
-#define MACH_TYPE_COGENT               206
-#define MACH_TYPE_ESL_SIMPUTER         207
-#define MACH_TYPE_ESL_SIMPUTER_CLR     208
-#define MACH_TYPE_ESL_SIMPUTER_BW      209
-#define MACH_TYPE_HHP_CRADLE           210
-#define MACH_TYPE_HE500                211
-#define MACH_TYPE_INHANDELF2           212
-#define MACH_TYPE_INHANDFTIP           213
-#define MACH_TYPE_DNP1110              214
-#define MACH_TYPE_PNP1110              215
-#define MACH_TYPE_CSB226               216
-#define MACH_TYPE_ARNOLD               217
-#define MACH_TYPE_VOICEBLUE            218
-#define MACH_TYPE_JZ8028               219
-#define MACH_TYPE_H5400                220
-#define MACH_TYPE_FORTE                221
-#define MACH_TYPE_ACAM                 222
-#define MACH_TYPE_ABOX                 223
-#define MACH_TYPE_ATMEL                224
-#define MACH_TYPE_SITSANG              225
-#define MACH_TYPE_CPU1110LCDNET        226
-#define MACH_TYPE_MPL_VCMA9            227
-#define MACH_TYPE_OPUS_A1              228
-#define MACH_TYPE_DAYTONA              229
-#define MACH_TYPE_KILLBEAR             230
-#define MACH_TYPE_YOHO                 231
-#define MACH_TYPE_JASPER               232
-#define MACH_TYPE_DSC25                233
-#define MACH_TYPE_OMAP_INNOVATOR       234
-#define MACH_TYPE_RAMSES               235
-#define MACH_TYPE_S28X                 236
-#define MACH_TYPE_MPORT3               237
-#define MACH_TYPE_PXA_EAGLE250         238
-#define MACH_TYPE_PDB                  239
-#define MACH_TYPE_BLUE_2G              240
-#define MACH_TYPE_BLUEARCH             241
-#define MACH_TYPE_IXDP2400             242
-#define MACH_TYPE_IXDP2800             243
-#define MACH_TYPE_EXPLORER             244
-#define MACH_TYPE_IXDP425              245
-#define MACH_TYPE_CHIMP                246
-#define MACH_TYPE_STORK_NEST           247
-#define MACH_TYPE_STORK_EGG            248
-#define MACH_TYPE_WISMO                249
-#define MACH_TYPE_EZLINX               250
-#define MACH_TYPE_AT91RM9200           251
-#define MACH_TYPE_ADTECH_ORION         252
-#define MACH_TYPE_NEPTUNE              253
-#define MACH_TYPE_HACKKIT              254
-#define MACH_TYPE_PXA_WINS30           255
-#define MACH_TYPE_LAVINNA              256
-#define MACH_TYPE_PXA_UENGINE          257
-#define MACH_TYPE_INNOKOM              258
-#define MACH_TYPE_BMS                  259
-#define MACH_TYPE_IXCDP1100            260
-#define MACH_TYPE_PRPMC1100            261
-#define MACH_TYPE_AT91RM9200DK         262
-#define MACH_TYPE_ARMSTICK             263
-#define MACH_TYPE_ARMONIE              264
-#define MACH_TYPE_MPORT1               265
-#define MACH_TYPE_S3C5410              266
-#define MACH_TYPE_ZCP320A              267
-#define MACH_TYPE_I_BOX                268
-#define MACH_TYPE_STLC1502             269
-#define MACH_TYPE_SIREN                270
-#define MACH_TYPE_GREENLAKE            271
-#define MACH_TYPE_ARGUS                272
-#define MACH_TYPE_COMBADGE             273
-#define MACH_TYPE_ROKEPXA              274
-#define MACH_TYPE_CINTEGRATOR          275
-#define MACH_TYPE_GUIDEA07             276
-#define MACH_TYPE_TAT257               277
-#define MACH_TYPE_IGP2425              278
-#define MACH_TYPE_BLUEGRAMMA           279
-#define MACH_TYPE_IPOD                 280
-#define MACH_TYPE_ADSBITSYX            281
-#define MACH_TYPE_TRIZEPS2             282
-#define MACH_TYPE_VIPER                283
-#define MACH_TYPE_ADSBITSYPLUS         284
-#define MACH_TYPE_ADSAGC               285
-#define MACH_TYPE_STP7312              286
-#define MACH_TYPE_NX_PHNX              287
-#define MACH_TYPE_WEP_EP250            288
-#define MACH_TYPE_INHANDELF3           289
-#define MACH_TYPE_ADI_COYOTE           290
-#define MACH_TYPE_IYONIX               291
-#define MACH_TYPE_DAMICAM_SA1110       292
-#define MACH_TYPE_MEG03                293
-#define MACH_TYPE_PXA_WHITECHAPEL      294
-#define MACH_TYPE_NWSC                 295
-#define MACH_TYPE_NWLARM               296
-#define MACH_TYPE_IXP425_MGUARD        297
-#define MACH_TYPE_PXA_NETDCU4          298
-#define MACH_TYPE_IXDP2401             299
-#define MACH_TYPE_IXDP2801             300
-#define MACH_TYPE_ZODIAC               301
-#define MACH_TYPE_ARMMODUL             302
-#define MACH_TYPE_KETOP                303
-#define MACH_TYPE_AV7200               304
-#define MACH_TYPE_ARCH_TI925           305
-#define MACH_TYPE_ACQ200               306
-#define MACH_TYPE_PT_DAFIT             307
-#define MACH_TYPE_IHBA                 308
-#define MACH_TYPE_QUINQUE              309
-#define MACH_TYPE_NIMBRAONE            310
-#define MACH_TYPE_NIMBRA29X            311
-#define MACH_TYPE_NIMBRA210            312
-#define MACH_TYPE_HHP_D95XX            313
-#define MACH_TYPE_LABARM               314
-#define MACH_TYPE_M825XX               315
-#define MACH_TYPE_M7100                316
-#define MACH_TYPE_NIPC2                317
-#define MACH_TYPE_FU7202               318
-#define MACH_TYPE_ADSAGX               319
-#define MACH_TYPE_PXA_POOH             320
-#define MACH_TYPE_BANDON               321
-#define MACH_TYPE_PCM7210              322
-#define MACH_TYPE_NMS9200              323
-#define MACH_TYPE_LOGODL               324
-#define MACH_TYPE_M7140                325
-#define MACH_TYPE_KOREBOT              326
-#define MACH_TYPE_IQ31244              327
-#define MACH_TYPE_KOAN393              328
-#define MACH_TYPE_INHANDFTIP3          329
-#define MACH_TYPE_GONZO                330
-#define MACH_TYPE_BAST                 331
-#define MACH_TYPE_SCANPASS             332
-#define MACH_TYPE_EP7312_POOH          333
-#define MACH_TYPE_TA7S                 334
-#define MACH_TYPE_TA7V                 335
-#define MACH_TYPE_ICARUS               336
-#define MACH_TYPE_H1900                337
-#define MACH_TYPE_GEMINI               338
-#define MACH_TYPE_AXIM                 339
-#define MACH_TYPE_AUDIOTRON            340
-#define MACH_TYPE_H2200                341
-#define MACH_TYPE_LOOX600              342
-#define MACH_TYPE_NIOP                 343
-#define MACH_TYPE_DM310                344
-#define MACH_TYPE_SEEDPXA_C2           345
-#define MACH_TYPE_IXP4XX_MGUARD_PCI    346
-#define MACH_TYPE_H1940                347
-#define MACH_TYPE_SCORPIO              348
-#define MACH_TYPE_VIVA                 349
-#define MACH_TYPE_PXA_XCARD            350
-#define MACH_TYPE_CSB335               351
-#define MACH_TYPE_IXRD425              352
-#define MACH_TYPE_IQ80315              353
-#define MACH_TYPE_NMP7312              354
-#define MACH_TYPE_CX861XX              355
-#define MACH_TYPE_ENP2611              356
-#define MACH_TYPE_XDA                  357
-#define MACH_TYPE_CSIR_IMS             358
-#define MACH_TYPE_IXP421_DNAEETH       359
-#define MACH_TYPE_POCKETSERV9200       360
-#define MACH_TYPE_TOTO                 361
-#define MACH_TYPE_S3C2440              362
-#define MACH_TYPE_KS8695P              363
-#define MACH_TYPE_SE4000               364
-#define MACH_TYPE_QUADRICEPS           365
-#define MACH_TYPE_BRONCO               366
-#define MACH_TYPE_ESL_WIRELESS_TAB     367
-#define MACH_TYPE_ESL_SOFCOMP          368
-#define MACH_TYPE_S5C7375              369
-#define MACH_TYPE_SPEARHEAD            370
-#define MACH_TYPE_PANTERA              371
-#define MACH_TYPE_PRAYOGLITE           372
-#define MACH_TYPE_GUMSTIX              373
-#define MACH_TYPE_RCUBE                374
-#define MACH_TYPE_REA_OLV              375
-#define MACH_TYPE_PXA_IPHONE           376
-#define MACH_TYPE_S3C3410              377
-#define MACH_TYPE_ESPD_4510B           378
-#define MACH_TYPE_MP1X                 379
-#define MACH_TYPE_AT91RM9200TB         380
-#define MACH_TYPE_ADSVGX               381
-#define MACH_TYPE_OMAP_H2              382
-#define MACH_TYPE_PELEE                383
-#define MACH_TYPE_E740                 384
-#define MACH_TYPE_IQ80331              385
-#define MACH_TYPE_VERSATILE_PB         387
-#define MACH_TYPE_KEV7A400             388
-#define MACH_TYPE_LPD7A400             389
-#define MACH_TYPE_LPD7A404             390
-#define MACH_TYPE_FUJITSU_CAMELOT      391
-#define MACH_TYPE_JANUS2M              392
-#define MACH_TYPE_EMBTF                393
-#define MACH_TYPE_HPM                  394
-#define MACH_TYPE_SMDK2410TK           395
-#define MACH_TYPE_SMDK2410AJ           396
-#define MACH_TYPE_STREETRACER          397
-#define MACH_TYPE_EFRAME               398
-#define MACH_TYPE_CSB337               399
-#define MACH_TYPE_PXA_LARK             400
-#define MACH_TYPE_PNP2110              401
-#define MACH_TYPE_TCC72X               402
-#define MACH_TYPE_ALTAIR               403
-#define MACH_TYPE_KC3                  404
-#define MACH_TYPE_SINTEFTD             405
-#define MACH_TYPE_MAINSTONE            406
-#define MACH_TYPE_ADAY4X               407
-#define MACH_TYPE_LITE300              408
-#define MACH_TYPE_S5C7376              409
-#define MACH_TYPE_MT02                 410
-#define MACH_TYPE_MPORT3S              411
-#define MACH_TYPE_RA_ALPHA             412
-#define MACH_TYPE_XCEP                 413
-#define MACH_TYPE_ARCOM_VULCAN         414
-#define MACH_TYPE_STARGATE             415
-#define MACH_TYPE_ARMADILLOJ           416
-#define MACH_TYPE_ELROY_JACK           417
-#define MACH_TYPE_BACKEND              418
-#define MACH_TYPE_S5LINBOX             419
-#define MACH_TYPE_NOMADIK              420
-#define MACH_TYPE_IA_CPU_9200          421
-#define MACH_TYPE_AT91_BJA1            422
-#define MACH_TYPE_CORGI                423
-#define MACH_TYPE_POODLE               424
-#define MACH_TYPE_TEN                  425
-#define MACH_TYPE_ROVERP5P             426
-#define MACH_TYPE_SC2700               427
-#define MACH_TYPE_EX_EAGLE             428
-#define MACH_TYPE_NX_PXA12             429
-#define MACH_TYPE_NX_PXA5              430
-#define MACH_TYPE_BLACKBOARD2          431
-#define MACH_TYPE_I819                 432
-#define MACH_TYPE_IXMB995E             433
-#define MACH_TYPE_SKYRIDER             434
-#define MACH_TYPE_SKYHAWK              435
-#define MACH_TYPE_ENTERPRISE           436
-#define MACH_TYPE_DEP2410              437
-#define MACH_TYPE_ARMCORE              438
-#define MACH_TYPE_HOBBIT               439
-#define MACH_TYPE_H7210                440
-#define MACH_TYPE_PXA_NETDCU5          441
-#define MACH_TYPE_ACC                  442
-#define MACH_TYPE_ESL_SARVA            443
-#define MACH_TYPE_XM250                444
-#define MACH_TYPE_T6TC1XB              445
-#define MACH_TYPE_ESS710               446
-#define MACH_TYPE_MX31ADS              447
-#define MACH_TYPE_HIMALAYA             448
-#define MACH_TYPE_BOLFENK              449
-#define MACH_TYPE_AT91RM9200KR         450
-#define MACH_TYPE_EDB9312              451
-#define MACH_TYPE_OMAP_GENERIC         452
-#define MACH_TYPE_AXIMX3               453
-#define MACH_TYPE_EB67XDIP             454
-#define MACH_TYPE_WEBTXS               455
-#define MACH_TYPE_HAWK                 456
-#define MACH_TYPE_CCAT91SBC001         457
-#define MACH_TYPE_EXPRESSO             458
-#define MACH_TYPE_H4000                459
-#define MACH_TYPE_DINO                 460
-#define MACH_TYPE_ML675K               461
-#define MACH_TYPE_EDB9301              462
-#define MACH_TYPE_EDB9315              463
-#define MACH_TYPE_RECIVA_TT            464
-#define MACH_TYPE_CSTCB01              465
-#define MACH_TYPE_CSTCB1               466
-#define MACH_TYPE_SHADWELL             467
-#define MACH_TYPE_GOEPEL263            468
-#define MACH_TYPE_ACQ100               469
-#define MACH_TYPE_MX1FS2               470
-#define MACH_TYPE_HIPTOP_G1            471
-#define MACH_TYPE_SPARKY               472
-#define MACH_TYPE_NS9750               473
-#define MACH_TYPE_PHOENIX              474
-#define MACH_TYPE_VR1000               475
-#define MACH_TYPE_DEISTERPXA           476
-#define MACH_TYPE_BCM1160              477
-#define MACH_TYPE_PCM022               478
-#define MACH_TYPE_ADSGCX               479
-#define MACH_TYPE_DREADNAUGHT          480
-#define MACH_TYPE_DM320                481
-#define MACH_TYPE_MARKOV               482
-#define MACH_TYPE_COS7A400             483
-#define MACH_TYPE_MILANO               484
-#define MACH_TYPE_UE9328               485
-#define MACH_TYPE_UEX255               486
-#define MACH_TYPE_UE2410               487
-#define MACH_TYPE_A620                 488
-#define MACH_TYPE_OCELOT               489
-#define MACH_TYPE_CHEETAH              490
-#define MACH_TYPE_OMAP_PERSEUS2        491
-#define MACH_TYPE_ZVUE                 492
-#define MACH_TYPE_ROVERP1              493
-#define MACH_TYPE_ASIDIAL2             494
-#define MACH_TYPE_S3C24A0              495
-#define MACH_TYPE_E800                 496
-#define MACH_TYPE_E750                 497
-#define MACH_TYPE_S3C5500              498
-#define MACH_TYPE_SMDK5500             499
-#define MACH_TYPE_SIGNALSYNC           500
-#define MACH_TYPE_NBC                  501
-#define MACH_TYPE_KODIAK               502
-#define MACH_TYPE_NETBOOKPRO           503
-#define MACH_TYPE_HW90200              504
-#define MACH_TYPE_CONDOR               505
-#define MACH_TYPE_CUP                  506
-#define MACH_TYPE_KITE                 507
-#define MACH_TYPE_SCB9328              508
-#define MACH_TYPE_OMAP_H3              509
-#define MACH_TYPE_OMAP_H4              510
-#define MACH_TYPE_N10                  511
-#define MACH_TYPE_MONTAJADE            512
-#define MACH_TYPE_SG560                513
-#define MACH_TYPE_DP1000               514
-#define MACH_TYPE_OMAP_OSK             515
-#define MACH_TYPE_RG100V3              516
-#define MACH_TYPE_MX2ADS               517
-#define MACH_TYPE_PXA_KILO             518
-#define MACH_TYPE_IXP4XX_EAGLE         519
-#define MACH_TYPE_TOSA                 520
-#define MACH_TYPE_MB2520F              521
-#define MACH_TYPE_EMC1000              522
-#define MACH_TYPE_TIDSC25              523
-#define MACH_TYPE_AKCPMXL              524
-#define MACH_TYPE_AV3XX                525
-#define MACH_TYPE_AVILA                526
-#define MACH_TYPE_PXA_MPM10            527
-#define MACH_TYPE_PXA_KYANITE          528
-#define MACH_TYPE_SGOLD                529
-#define MACH_TYPE_OSCAR                530
-#define MACH_TYPE_EPXA4USB2            531
-#define MACH_TYPE_XSENGINE             532
-#define MACH_TYPE_IP600                533
-#define MACH_TYPE_MCAN2                534
-#define MACH_TYPE_DDI_BLUERIDGE        535
-#define MACH_TYPE_SKYMINDER            536
-#define MACH_TYPE_LPD79520             537
-#define MACH_TYPE_EDB9302              538
-#define MACH_TYPE_HW90340              539
-#define MACH_TYPE_CIP_BOX              540
-#define MACH_TYPE_IVPN                 541
-#define MACH_TYPE_RSOC2                542
-#define MACH_TYPE_HUSKY                543
-#define MACH_TYPE_BOXER                544
-#define MACH_TYPE_SHEPHERD             545
-#define MACH_TYPE_AML42800AA           546
-#define MACH_TYPE_LPC2294              548
-#define MACH_TYPE_SWITCHGRASS          549
-#define MACH_TYPE_ENS_CMU              550
-#define MACH_TYPE_MM6_SDB              551
-#define MACH_TYPE_SATURN               552
-#define MACH_TYPE_I30030EVB            553
-#define MACH_TYPE_MXC27530EVB          554
-#define MACH_TYPE_SMDK2800             555
-#define MACH_TYPE_MTWILSON             556
-#define MACH_TYPE_ZITI                 557
-#define MACH_TYPE_GRANDFATHER          558
-#define MACH_TYPE_TENGINE              559
-#define MACH_TYPE_S3C2460              560
-#define MACH_TYPE_PDM                  561
-#define MACH_TYPE_H4700                562
-#define MACH_TYPE_H6300                563
-#define MACH_TYPE_RZ1700               564
-#define MACH_TYPE_A716                 565
-#define MACH_TYPE_ESTK2440A            566
-#define MACH_TYPE_ATWIXP425            567
-#define MACH_TYPE_CSB336               568
-#define MACH_TYPE_RIRM2                569
-#define MACH_TYPE_CX23518              570
-#define MACH_TYPE_CX2351X              571
-#define MACH_TYPE_COMPUTIME            572
-#define MACH_TYPE_IZARUS               573
-#define MACH_TYPE_RTS                  574
-#define MACH_TYPE_SE5100               575
-#define MACH_TYPE_S3C2510              576
-#define MACH_TYPE_CSB437TL             577
-#define MACH_TYPE_SLAUSON              578
-#define MACH_TYPE_PEARLRIVER           579
-#define MACH_TYPE_TDC_P210             580
-#define MACH_TYPE_SG580                581
-#define MACH_TYPE_WRSBCARM7            582
-#define MACH_TYPE_IPD                  583
-#define MACH_TYPE_PXA_DNP2110          584
-#define MACH_TYPE_XAENIAX              585
-#define MACH_TYPE_SOMN4250             586
-#define MACH_TYPE_PLEB2                587
-#define MACH_TYPE_CORNWALLIS           588
-#define MACH_TYPE_GURNEY_DRV           589
-#define MACH_TYPE_CHAFFEE              590
-#define MACH_TYPE_RMS101               591
-#define MACH_TYPE_RX3715               592
-#define MACH_TYPE_SWIFT                593
-#define MACH_TYPE_ROVERP7              594
-#define MACH_TYPE_PR818S               595
-#define MACH_TYPE_TRXPRO               596
-#define MACH_TYPE_NSLU2                597
-#define MACH_TYPE_E400                 598
-#define MACH_TYPE_TRAB                 599
-#define MACH_TYPE_CMC_PU2              600
-#define MACH_TYPE_FULCRUM              601
-#define MACH_TYPE_NETGATE42X           602
-#define MACH_TYPE_STR710               603
-#define MACH_TYPE_IXDPG425             604
-#define MACH_TYPE_TOMTOMGO             605
-#define MACH_TYPE_VERSATILE_AB         606
-#define MACH_TYPE_EDB9307              607
-#define MACH_TYPE_SG565                608
-#define MACH_TYPE_LPD79524             609
-#define MACH_TYPE_LPD79525             610
-#define MACH_TYPE_RMS100               611
-#define MACH_TYPE_KB9200               612
-#define MACH_TYPE_SX1                  613
-#define MACH_TYPE_HMS39C7092           614
-#define MACH_TYPE_ARMADILLO            615
-#define MACH_TYPE_IPCU                 616
-#define MACH_TYPE_LOOX720              617
-#define MACH_TYPE_IXDP465              618
-#define MACH_TYPE_IXDP2351             619
-#define MACH_TYPE_ADSVIX               620
-#define MACH_TYPE_DM270                621
-#define MACH_TYPE_SOCLTPLUS            622
-#define MACH_TYPE_ECIA                 623
-#define MACH_TYPE_CM4008               624
-#define MACH_TYPE_P2001                625
-#define MACH_TYPE_TWISTER              626
-#define MACH_TYPE_MUDSHARK             627
-#define MACH_TYPE_HB2                  628
-#define MACH_TYPE_IQ80332              629
-#define MACH_TYPE_SENDT                630
-#define MACH_TYPE_MX2JAZZ              631
-#define MACH_TYPE_MULTIIO              632
-#define MACH_TYPE_HRDISPLAY            633
-#define MACH_TYPE_MXC27530ADS          634
-#define MACH_TYPE_TRIZEPS3             635
-#define MACH_TYPE_ZEFEERDZA            636
-#define MACH_TYPE_ZEFEERDZB            637
-#define MACH_TYPE_ZEFEERDZG            638
-#define MACH_TYPE_ZEFEERDZN            639
-#define MACH_TYPE_ZEFEERDZQ            640
-#define MACH_TYPE_GTWX5715             641
-#define MACH_TYPE_ASTRO_JACK           643
-#define MACH_TYPE_TIP03                644
-#define MACH_TYPE_A9200EC              645
-#define MACH_TYPE_PNX0105              646
-#define MACH_TYPE_ADCPOECPU            647
-#define MACH_TYPE_CSB637               648
-#define MACH_TYPE_MB9200               650
-#define MACH_TYPE_KULUN                651
-#define MACH_TYPE_SNAPPER              652
-#define MACH_TYPE_OPTIMA               653
-#define MACH_TYPE_DLHSBC               654
-#define MACH_TYPE_X30                  655
-#define MACH_TYPE_N30                  656
-#define MACH_TYPE_MANGA_KS8695         657
-#define MACH_TYPE_AJAX                 658
-#define MACH_TYPE_NEC_MP900            659
-#define MACH_TYPE_VVTK1000             661
-#define MACH_TYPE_KAFA                 662
-#define MACH_TYPE_VVTK3000             663
-#define MACH_TYPE_PIMX1                664
-#define MACH_TYPE_OLLIE                665
-#define MACH_TYPE_SKYMAX               666
-#define MACH_TYPE_JAZZ                 667
-#define MACH_TYPE_TEL_T3               668
-#define MACH_TYPE_AISINO_FCR255        669
-#define MACH_TYPE_BTWEB                670
-#define MACH_TYPE_DBG_LH79520          671
-#define MACH_TYPE_CM41XX               672
-#define MACH_TYPE_TS72XX               673
-#define MACH_TYPE_NGGPXA               674
-#define MACH_TYPE_CSB535               675
-#define MACH_TYPE_CSB536               676
-#define MACH_TYPE_PXA_TRAKPOD          677
-#define MACH_TYPE_PRAXIS               678
-#define MACH_TYPE_LH75411              679
-#define MACH_TYPE_OTOM                 680
-#define MACH_TYPE_NEXCODER_2440        681
-#define MACH_TYPE_LOOX410              682
-#define MACH_TYPE_WESTLAKE             683
-#define MACH_TYPE_NSB                  684
-#define MACH_TYPE_ESL_SARVA_STN        685
-#define MACH_TYPE_ESL_SARVA_TFT        686
-#define MACH_TYPE_ESL_SARVA_IAD        687
-#define MACH_TYPE_ESL_SARVA_ACC        688
-#define MACH_TYPE_TYPHOON              689
-#define MACH_TYPE_CNAV                 690
-#define MACH_TYPE_A730                 691
-#define MACH_TYPE_NETSTAR              692
-#define MACH_TYPE_PHASEFALE_SUPERCON   693
-#define MACH_TYPE_SHIVA1100            694
-#define MACH_TYPE_ETEXSC               695
-#define MACH_TYPE_IXDPG465             696
-#define MACH_TYPE_A9M2410              697
-#define MACH_TYPE_A9M2440              698
-#define MACH_TYPE_A9M9750              699
-#define MACH_TYPE_A9M9360              700
-#define MACH_TYPE_UNC90                701
-#define MACH_TYPE_ECO920               702
-#define MACH_TYPE_SATVIEW              703
-#define MACH_TYPE_ROADRUNNER           704
-#define MACH_TYPE_AT91RM9200EK         705
-#define MACH_TYPE_GP32                 706
-#define MACH_TYPE_GEM                  707
-#define MACH_TYPE_I858                 708
-#define MACH_TYPE_HX2750               709
-#define MACH_TYPE_MXC91131EVB          710
-#define MACH_TYPE_P700                 711
-#define MACH_TYPE_CPE                  712
-#define MACH_TYPE_SPITZ                713
-#define MACH_TYPE_NIMBRA340            714
-#define MACH_TYPE_LPC22XX              715
-#define MACH_TYPE_COMET3               716
-#define MACH_TYPE_COMET4               717
-#define MACH_TYPE_CSB625               718
-#define MACH_TYPE_FORTUNET2            719
-#define MACH_TYPE_S5H2200              720
-#define MACH_TYPE_OPTORM920            721
-#define MACH_TYPE_ADSBITSYXB           722
-#define MACH_TYPE_ADSSPHERE            723
-#define MACH_TYPE_ADSPORTAL            724
-#define MACH_TYPE_LN2410SBC            725
-#define MACH_TYPE_CB3RUFC              726
-#define MACH_TYPE_MP2USB               727
-#define MACH_TYPE_NTNP425C             728
-#define MACH_TYPE_COLIBRI              729
-#define MACH_TYPE_PCM7220              730
-#define MACH_TYPE_GATEWAY7001          731
-#define MACH_TYPE_PCM027               732
-#define MACH_TYPE_CMPXA                733
-#define MACH_TYPE_ANUBIS               734
-#define MACH_TYPE_ITE8152              735
-#define MACH_TYPE_LPC3XXX              736
-#define MACH_TYPE_PUPPETEER            737
-#define MACH_TYPE_E570                 739
-#define MACH_TYPE_X50                  740
-#define MACH_TYPE_RECON                741
-#define MACH_TYPE_XBOARDGP8            742
-#define MACH_TYPE_FPIC2                743
-#define MACH_TYPE_AKITA                744
-#define MACH_TYPE_A81                  745
-#define MACH_TYPE_SVM_SC25X            746
-#define MACH_TYPE_VADATECH020          747
-#define MACH_TYPE_TLI                  748
-#define MACH_TYPE_EDB9315LC            749
-#define MACH_TYPE_PASSEC               750
-#define MACH_TYPE_DS_TIGER             751
-#define MACH_TYPE_E310                 752
-#define MACH_TYPE_E330                 753
-#define MACH_TYPE_RT3000               754
-#define MACH_TYPE_NOKIA770             755
-#define MACH_TYPE_PNX0106              756
-#define MACH_TYPE_HX21XX               757
-#define MACH_TYPE_FARADAY              758
-#define MACH_TYPE_SBC9312              759
-#define MACH_TYPE_BATMAN               760
-#define MACH_TYPE_JPD201               761
-#define MACH_TYPE_MIPSA                762
-#define MACH_TYPE_KACOM                763
-#define MACH_TYPE_SWARCOCPU            764
-#define MACH_TYPE_SWARCODSL            765
-#define MACH_TYPE_BLUEANGEL            766
-#define MACH_TYPE_HAIRYGRAMA           767
-#define MACH_TYPE_BANFF                768
-#define MACH_TYPE_CARMEVA              769
-#define MACH_TYPE_SAM255               770
-#define MACH_TYPE_PPM10                771
-#define MACH_TYPE_EDB9315A             772
-#define MACH_TYPE_SUNSET               773
-#define MACH_TYPE_STARGATE2            774
-#define MACH_TYPE_INTELMOTE2           775
-#define MACH_TYPE_TRIZEPS4             776
-#define MACH_TYPE_MAINSTONE2           777
-#define MACH_TYPE_EZ_IXP42X            778
-#define MACH_TYPE_TAPWAVE_ZODIAC       779
-#define MACH_TYPE_UNIVERSALMETER       780
-#define MACH_TYPE_HICOARM9             781
-#define MACH_TYPE_PNX4008              782
-#define MACH_TYPE_KWS6000              783
-#define MACH_TYPE_PORTUX920T           784
-#define MACH_TYPE_EZ_X5                785
-#define MACH_TYPE_OMAP_RUDOLPH         786
-#define MACH_TYPE_CPUAT91              787
-#define MACH_TYPE_REA9200              788
-#define MACH_TYPE_ACTS_PUNE_SA1110     789
-#define MACH_TYPE_IXP425               790
-#define MACH_TYPE_I30030ADS            791
-#define MACH_TYPE_PERCH                792
-#define MACH_TYPE_EIS05R1              793
-#define MACH_TYPE_PEPPERPAD            794
-#define MACH_TYPE_SB3010               795
-#define MACH_TYPE_RM9200               796
-#define MACH_TYPE_DMA03                797
-#define MACH_TYPE_ROAD_S101            798
-#define MACH_TYPE_IQ81340SC            799
-#define MACH_TYPE_IQ_NEXTGEN_B         800
-#define MACH_TYPE_IQ81340MC            801
-#define MACH_TYPE_IQ_NEXTGEN_D         802
-#define MACH_TYPE_IQ_NEXTGEN_E         803
-#define MACH_TYPE_MALLOW_AT91          804
-#define MACH_TYPE_CYBERTRACKER_I       805
-#define MACH_TYPE_GESBC931X            806
-#define MACH_TYPE_CENTIPAD             807
-#define MACH_TYPE_ARMSOC               808
-#define MACH_TYPE_SE4200               809
-#define MACH_TYPE_EMS197A              810
-#define MACH_TYPE_MICRO9               811
-#define MACH_TYPE_MICRO9L              812
-#define MACH_TYPE_UC5471DSP            813
-#define MACH_TYPE_SJ5471ENG            814
-#define MACH_TYPE_CMPXA26X             815
-#define MACH_TYPE_NC                   816
-#define MACH_TYPE_OMAP_PALMTE          817
-#define MACH_TYPE_AJAX52X              818
-#define MACH_TYPE_SIRIUSTAR            819
-#define MACH_TYPE_IODATA_HDLG          820
-#define MACH_TYPE_AT91RM9200UTL        821
-#define MACH_TYPE_BIOSAFE              822
-#define MACH_TYPE_MP1000               823
-#define MACH_TYPE_PARSY                824
-#define MACH_TYPE_CCXP                 825
-#define MACH_TYPE_OMAP_GSAMPLE         826
-#define MACH_TYPE_REALVIEW_EB          827
-#define MACH_TYPE_SAMOA                828
-#define MACH_TYPE_PALMT3               829
-#define MACH_TYPE_I878                 830
-#define MACH_TYPE_BORZOI               831
-#define MACH_TYPE_GECKO                832
-#define MACH_TYPE_DS101                833
-#define MACH_TYPE_OMAP_PALMTT2         834
-#define MACH_TYPE_PALMLD               835
-#define MACH_TYPE_CC9C                 836
-#define MACH_TYPE_SBC1670              837
-#define MACH_TYPE_IXDP28X5             838
-#define MACH_TYPE_OMAP_PALMTT          839
-#define MACH_TYPE_ML696K               840
-#define MACH_TYPE_ARCOM_ZEUS           841
-#define MACH_TYPE_OSIRIS               842
-#define MACH_TYPE_MAESTRO              843
-#define MACH_TYPE_PALMTE2              844
-#define MACH_TYPE_IXBBM                845
-#define MACH_TYPE_MX27ADS              846
-#define MACH_TYPE_AX8004               847
-#define MACH_TYPE_AT91SAM9261EK        848
-#define MACH_TYPE_LOFT                 849
-#define MACH_TYPE_MAGPIE               850
-#define MACH_TYPE_MX21ADS              851
-#define MACH_TYPE_MB87M3400            852
-#define MACH_TYPE_MGUARD_DELTA         853
-#define MACH_TYPE_DAVINCI_DVDP         854
-#define MACH_TYPE_HTCUNIVERSAL         855
-#define MACH_TYPE_TPAD                 856
-#define MACH_TYPE_ROVERP3              857
-#define MACH_TYPE_JORNADA928           858
-#define MACH_TYPE_MV88FXX81            859
-#define MACH_TYPE_STMP36XX             860
-#define MACH_TYPE_SXNI79524            861
-#define MACH_TYPE_AMS_DELTA            862
-#define MACH_TYPE_URANIUM              863
-#define MACH_TYPE_UCON                 864
-#define MACH_TYPE_NAS100D              865
-#define MACH_TYPE_L083_1000            866
-#define MACH_TYPE_EZX                  867
-#define MACH_TYPE_PNX5220              868
-#define MACH_TYPE_BUTTE                869
-#define MACH_TYPE_SRM2                 870
-#define MACH_TYPE_DSBR                 871
-#define MACH_TYPE_CRYSTALBALL          872
-#define MACH_TYPE_TINYPXA27X           873
-#define MACH_TYPE_HERBIE               874
-#define MACH_TYPE_MAGICIAN             875
-#define MACH_TYPE_CM4002               876
-#define MACH_TYPE_B4                   877
-#define MACH_TYPE_MAUI                 878
-#define MACH_TYPE_CYBERTRACKER_G       879
-#define MACH_TYPE_NXDKN                880
-#define MACH_TYPE_MIO8390              881
-#define MACH_TYPE_OMI_BOARD            882
-#define MACH_TYPE_MX21CIV              883
-#define MACH_TYPE_MAHI_CDAC            884
-#define MACH_TYPE_PALMTX               885
-#define MACH_TYPE_S3C2413              887
-#define MACH_TYPE_SAMSYS_EP0           888
-#define MACH_TYPE_WG302V1              889
-#define MACH_TYPE_WG302V2              890
-#define MACH_TYPE_EB42X                891
-#define MACH_TYPE_IQ331ES              892
-#define MACH_TYPE_COSYDSP              893
-#define MACH_TYPE_UPLAT7D              894
-#define MACH_TYPE_PTDAVINCI            895
-#define MACH_TYPE_MBUS                 896
-#define MACH_TYPE_NADIA2VB             897
-#define MACH_TYPE_R1000                898
-#define MACH_TYPE_HW90250              899
-#define MACH_TYPE_OMAP_2430SDP         900
-#define MACH_TYPE_DAVINCI_EVM          901
-#define MACH_TYPE_OMAP_TORNADO         902
-#define MACH_TYPE_OLOCREEK             903
-#define MACH_TYPE_PALMZ72              904
-#define MACH_TYPE_NXDB500              905
-#define MACH_TYPE_APF9328              906
-#define MACH_TYPE_OMAP_WIPOQ           907
-#define MACH_TYPE_OMAP_TWIP            908
-#define MACH_TYPE_TREO650              909
-#define MACH_TYPE_ACUMEN               910
-#define MACH_TYPE_XP100                911
-#define MACH_TYPE_FS2410               912
-#define MACH_TYPE_PXA270_CERF          913
-#define MACH_TYPE_SQ2FTLPALM           914
-#define MACH_TYPE_BSEMSERVER           915
-#define MACH_TYPE_NETCLIENT            916
-#define MACH_TYPE_PALMT5               917
-#define MACH_TYPE_PALMTC               918
-#define MACH_TYPE_OMAP_APOLLON         919
-#define MACH_TYPE_MXC30030EVB          920
-#define MACH_TYPE_REA_2D               921
-#define MACH_TYPE_TI3E524              922
-#define MACH_TYPE_ATEB9200             923
-#define MACH_TYPE_AUCKLAND             924
-#define MACH_TYPE_AK3320M              925
-#define MACH_TYPE_DURAMAX              926
-#define MACH_TYPE_N35                  927
-#define MACH_TYPE_PRONGHORN            928
-#define MACH_TYPE_FUNDY                929
-#define MACH_TYPE_LOGICPD_PXA270       930
-#define MACH_TYPE_CPU777               931
-#define MACH_TYPE_SIMICON9201          932
-#define MACH_TYPE_LEAP2_HPM            933
-#define MACH_TYPE_CM922TXA10           934
-#define MACH_TYPE_PXA                  935
-#define MACH_TYPE_SANDGATE2            936
-#define MACH_TYPE_SANDGATE2G           937
-#define MACH_TYPE_SANDGATE2P           938
-#define MACH_TYPE_FRED_JACK            939
-#define MACH_TYPE_TTG_COLOR1           940
-#define MACH_TYPE_NXEB500HMI           941
-#define MACH_TYPE_NETDCU8              942
-#define MACH_TYPE_NG_FVX538            944
-#define MACH_TYPE_NG_FVS338            945
-#define MACH_TYPE_PNX4103              946
-#define MACH_TYPE_HESDB                947
-#define MACH_TYPE_XSILO                948
-#define MACH_TYPE_ESPRESSO             949
-#define MACH_TYPE_EMLC                 950
-#define MACH_TYPE_SISTERON             951
-#define MACH_TYPE_RX1950               952
-#define MACH_TYPE_TSC_VENUS            953
-#define MACH_TYPE_DS101J               954
-#define MACH_TYPE_MXC30030ADS          955
-#define MACH_TYPE_FUJITSU_WIMAXSOC     956
-#define MACH_TYPE_DUALPCMODEM          957
-#define MACH_TYPE_GESBC9312            958
-#define MACH_TYPE_HTCAPACHE            959
-#define MACH_TYPE_IXDP435              960
-#define MACH_TYPE_CATPROVT100          961
-#define MACH_TYPE_PICOTUX1XX           962
-#define MACH_TYPE_PICOTUX2XX           963
-#define MACH_TYPE_DSMG600              964
-#define MACH_TYPE_EMPC2                965
-#define MACH_TYPE_VENTURA              966
-#define MACH_TYPE_PHIDGET_SBC          967
-#define MACH_TYPE_IJ3K                 968
-#define MACH_TYPE_PISGAH               969
-#define MACH_TYPE_OMAP_FSAMPLE         970
-#define MACH_TYPE_SG720                971
-#define MACH_TYPE_REDFOX               972
-#define MACH_TYPE_MYSH_EP9315_1        973
-#define MACH_TYPE_TPF106               974
-#define MACH_TYPE_AT91RM9200KG         975
-#define MACH_TYPE_SLEDB                976
-#define MACH_TYPE_ONTRACK              977
-#define MACH_TYPE_PM1200               978
-#define MACH_TYPE_ESS24XXX             979
-#define MACH_TYPE_COREMP7              980
-#define MACH_TYPE_NEXCODER_6446        981
-#define MACH_TYPE_STVC8380             982
-#define MACH_TYPE_TEKLYNX              983
-#define MACH_TYPE_CARBONADO            984
-#define MACH_TYPE_SYSMOS_MP730         985
-#define MACH_TYPE_SNAPPER_CL15         986
-#define MACH_TYPE_PGIGIM               987
-#define MACH_TYPE_PTX9160P2            988
-#define MACH_TYPE_DCORE1               989
-#define MACH_TYPE_VICTORPXA            990
-#define MACH_TYPE_MX2DTB               991
-#define MACH_TYPE_PXA_IREX_ER0100      992
-#define MACH_TYPE_OMAP_PALMZ71         993
-#define MACH_TYPE_BARTEC_DEG           994
-#define MACH_TYPE_HW50251              995
-#define MACH_TYPE_IBOX                 996
-#define MACH_TYPE_ATLASLH7A404         997
-#define MACH_TYPE_PT2026               998
-#define MACH_TYPE_HTCALPINE            999
-#define MACH_TYPE_BARTEC_VTU           1000
-#define MACH_TYPE_VCOREII              1001
-#define MACH_TYPE_PDNB3                1002
-#define MACH_TYPE_HTCBEETLES           1003
-#define MACH_TYPE_S3C6400              1004
-#define MACH_TYPE_S3C2443              1005
-#define MACH_TYPE_OMAP_LDK             1006
-#define MACH_TYPE_SMDK2460             1007
-#define MACH_TYPE_SMDK2440             1008
-#define MACH_TYPE_SMDK2412             1009
-#define MACH_TYPE_WEBBOX               1010
-#define MACH_TYPE_CWWNDP               1011
-#define MACH_TYPE_DRAGON               1012
-#define MACH_TYPE_OPENDO_CPU_BOARD     1013
-#define MACH_TYPE_CCM2200              1014
-#define MACH_TYPE_ETWARM               1015
-#define MACH_TYPE_M93030               1016
-#define MACH_TYPE_CC7U                 1017
-#define MACH_TYPE_MTT_RANGER           1018
-#define MACH_TYPE_NEXUS                1019
-#define MACH_TYPE_DESMAN               1020
-#define MACH_TYPE_BKDE303              1021
-#define MACH_TYPE_SMDK2413             1022
-#define MACH_TYPE_AML_M7200            1023
-#define MACH_TYPE_AML_M5900            1024
-#define MACH_TYPE_SG640                1025
-#define MACH_TYPE_EDG79524             1026
-#define MACH_TYPE_AI2410               1027
-#define MACH_TYPE_IXP465               1028
-#define MACH_TYPE_BALLOON3             1029
-#define MACH_TYPE_HEINS                1030
-#define MACH_TYPE_MPLUSEVA             1031
-#define MACH_TYPE_RT042                1032
-#define MACH_TYPE_CWIEM                1033
-#define MACH_TYPE_CM_X270              1034
-#define MACH_TYPE_CM_X255              1035
-#define MACH_TYPE_ESH_AT91             1036
-#define MACH_TYPE_SANDGATE3            1037
-#define MACH_TYPE_PRIMO                1038
-#define MACH_TYPE_GEMSTONE             1039
-#define MACH_TYPE_PRONGHORNMETRO       1040
-#define MACH_TYPE_SIDEWINDER           1041
-#define MACH_TYPE_PICOMOD1             1042
-#define MACH_TYPE_SG590                1043
-#define MACH_TYPE_AKAI9307             1044
-#define MACH_TYPE_FONTAINE             1045
-#define MACH_TYPE_WOMBAT               1046
-#define MACH_TYPE_ACQ300               1047
-#define MACH_TYPE_MOD_270              1048
-#define MACH_TYPE_VC0820               1049
-#define MACH_TYPE_ANI_AIM              1050
-#define MACH_TYPE_JELLYFISH            1051
-#define MACH_TYPE_AMANITA              1052
-#define MACH_TYPE_VLINK                1053
-#define MACH_TYPE_DEXFLEX              1054
-#define MACH_TYPE_EIGEN_TTQ            1055
-#define MACH_TYPE_ARCOM_TITAN          1056
-#define MACH_TYPE_TABLA                1057
-#define MACH_TYPE_MDIRAC3              1058
-#define MACH_TYPE_MRHFBP2              1059
-#define MACH_TYPE_AT91RM9200RB         1060
-#define MACH_TYPE_ANI_APM              1061
-#define MACH_TYPE_ELLA1                1062
-#define MACH_TYPE_INHAND_PXA27X        1063
-#define MACH_TYPE_INHAND_PXA25X        1064
-#define MACH_TYPE_EMPOS_XM             1065
-#define MACH_TYPE_EMPOS                1066
-#define MACH_TYPE_EMPOS_TINY           1067
-#define MACH_TYPE_EMPOS_SM             1068
-#define MACH_TYPE_EGRET                1069
-#define MACH_TYPE_OSTRICH              1070
-#define MACH_TYPE_N50                  1071
-#define MACH_TYPE_ECBAT91              1072
-#define MACH_TYPE_STAREAST             1073
-#define MACH_TYPE_DSPG_DW              1074
-#define MACH_TYPE_ONEARM               1075
-#define MACH_TYPE_MRG110_6             1076
-#define MACH_TYPE_WRT300NV2            1077
-#define MACH_TYPE_XM_BULVERDE          1078
-#define MACH_TYPE_MSM6100              1079
-#define MACH_TYPE_ETI_B1               1080
-#define MACH_TYPE_ZILOG_ZA9L           1081
-#define MACH_TYPE_BIT2440              1082
-#define MACH_TYPE_NBI                  1083
-#define MACH_TYPE_SMDK2443             1084
-#define MACH_TYPE_VDAVINCI             1085
-#define MACH_TYPE_ATC6                 1086
-#define MACH_TYPE_MULTMDW              1087
-#define MACH_TYPE_MBA2440              1088
-#define MACH_TYPE_ECSD                 1089
-#define MACH_TYPE_PALMZ31              1090
-#define MACH_TYPE_FSG                  1091
-#define MACH_TYPE_RAZOR101             1092
-#define MACH_TYPE_OPERA_TDM            1093
-#define MACH_TYPE_COMCERTO             1094
-#define MACH_TYPE_TB0319               1095
-#define MACH_TYPE_KWS8000              1096
-#define MACH_TYPE_B2                   1097
-#define MACH_TYPE_LCL54                1098
-#define MACH_TYPE_AT91SAM9260EK        1099
-#define MACH_TYPE_GLANTANK             1100
-#define MACH_TYPE_N2100                1101
-#define MACH_TYPE_N4100                1102
-#define MACH_TYPE_VERTICAL_RSC4        1103
-#define MACH_TYPE_SG8100               1104
-#define MACH_TYPE_IM42XX               1105
-#define MACH_TYPE_FTXX                 1106
-#define MACH_TYPE_LWFUSION             1107
-#define MACH_TYPE_QT2410               1108
-#define MACH_TYPE_KIXRP435             1109
-#define MACH_TYPE_CCW9C                1110
-#define MACH_TYPE_DABHS                1111
-#define MACH_TYPE_GZMX                 1112
-#define MACH_TYPE_IPNW100AP            1113
-#define MACH_TYPE_CC9P9360DEV          1114
-#define MACH_TYPE_CC9P9750DEV          1115
-#define MACH_TYPE_CC9P9360VAL          1116
-#define MACH_TYPE_CC9P9750VAL          1117
-#define MACH_TYPE_NX70V                1118
-#define MACH_TYPE_AT91RM9200DF         1119
-#define MACH_TYPE_SE_PILOT2            1120
-#define MACH_TYPE_MTCN_T800            1121
-#define MACH_TYPE_VCMX212              1122
-#define MACH_TYPE_LYNX                 1123
-#define MACH_TYPE_AT91SAM9260ID        1124
-#define MACH_TYPE_HW86052              1125
-#define MACH_TYPE_PILZ_PMI3            1126
-#define MACH_TYPE_EDB9302A             1127
-#define MACH_TYPE_EDB9307A             1128
-#define MACH_TYPE_CT_DFS               1129
-#define MACH_TYPE_PILZ_PMI4            1130
-#define MACH_TYPE_XCEEDNP_IXP          1131
-#define MACH_TYPE_SMDK2442B            1132
-#define MACH_TYPE_XNODE                1133
-#define MACH_TYPE_AIDX270              1134
-#define MACH_TYPE_REMA                 1135
-#define MACH_TYPE_BPS1000              1136
-#define MACH_TYPE_HW90350              1137
-#define MACH_TYPE_OMAP_3430SDP         1138
-#define MACH_TYPE_BLUETOUCH            1139
-#define MACH_TYPE_VSTMS                1140
-#define MACH_TYPE_XSBASE270            1141
-#define MACH_TYPE_AT91SAM9260EK_CN     1142
-#define MACH_TYPE_ADSTURBOXB           1143
-#define MACH_TYPE_OTI4110              1144
-#define MACH_TYPE_HME_PXA              1145
-#define MACH_TYPE_DEISTERDCA           1146
-#define MACH_TYPE_CES_SSEM2            1147
-#define MACH_TYPE_CES_MTR              1148
-#define MACH_TYPE_TDS_AVNG_SBC         1149
-#define MACH_TYPE_EVEREST              1150
-#define MACH_TYPE_PNX4010              1151
-#define MACH_TYPE_OXNAS                1152
-#define MACH_TYPE_FIORI                1153
-#define MACH_TYPE_ML1200               1154
-#define MACH_TYPE_PECOS                1155
-#define MACH_TYPE_NB2XXX               1156
-#define MACH_TYPE_HW6900               1157
-#define MACH_TYPE_CDCS_QUOLL           1158
-#define MACH_TYPE_QUICKSILVER          1159
-#define MACH_TYPE_UPLAT926             1160
-#define MACH_TYPE_DEP2410_THOMAS       1161
-#define MACH_TYPE_DTK2410              1162
-#define MACH_TYPE_CHILI                1163
-#define MACH_TYPE_DEMETER              1164
-#define MACH_TYPE_DIONYSUS             1165
-#define MACH_TYPE_AS352X               1166
-#define MACH_TYPE_SERVICE              1167
-#define MACH_TYPE_CS_E9301             1168
-#define MACH_TYPE_MICRO9M              1169
-#define MACH_TYPE_IA_MOSPCK            1170
-#define MACH_TYPE_QL201B               1171
-#define MACH_TYPE_BBM                  1174
-#define MACH_TYPE_EXXX                 1175
-#define MACH_TYPE_WMA11B               1176
-#define MACH_TYPE_PELCO_ATLAS          1177
-#define MACH_TYPE_G500                 1178
-#define MACH_TYPE_BUG                  1179
-#define MACH_TYPE_MX33ADS              1180
-#define MACH_TYPE_CHUB                 1181
-#define MACH_TYPE_NEO1973_GTA01        1182
-#define MACH_TYPE_W90N740              1183
-#define MACH_TYPE_MEDALLION_SA2410     1184
-#define MACH_TYPE_IA_CPU_9200_2        1185
-#define MACH_TYPE_DIMMRM9200           1186
-#define MACH_TYPE_PM9261               1187
-#define MACH_TYPE_ML7304               1189
-#define MACH_TYPE_UCP250               1190
-#define MACH_TYPE_INTBOARD             1191
-#define MACH_TYPE_GULFSTREAM           1192
-#define MACH_TYPE_LABQUEST             1193
-#define MACH_TYPE_VCMX313              1194
-#define MACH_TYPE_URG200               1195
-#define MACH_TYPE_CPUX255LCDNET        1196
-#define MACH_TYPE_NETDCU9              1197
-#define MACH_TYPE_NETDCU10             1198
-#define MACH_TYPE_DSPG_DGA             1199
-#define MACH_TYPE_DSPG_DVW             1200
-#define MACH_TYPE_SOLOS                1201
-#define MACH_TYPE_AT91SAM9263EK        1202
-#define MACH_TYPE_OSSTBOX              1203
-#define MACH_TYPE_KBAT9261             1204
-#define MACH_TYPE_CT1100               1205
-#define MACH_TYPE_AKCPPXA              1206
-#define MACH_TYPE_OCHAYA1020           1207
-#define MACH_TYPE_HITRACK              1208
-#define MACH_TYPE_SYME1                1209
-#define MACH_TYPE_SYHL1                1210
-#define MACH_TYPE_EMPCA400             1211
-#define MACH_TYPE_EM7210               1212
-#define MACH_TYPE_HTCHERMES            1213
-#define MACH_TYPE_ETI_C1               1214
-#define MACH_TYPE_AC100                1216
-#define MACH_TYPE_SNEETCH              1217
-#define MACH_TYPE_STUDENTMATE          1218
-#define MACH_TYPE_ZIR2410              1219
-#define MACH_TYPE_ZIR2413              1220
-#define MACH_TYPE_DLONIP3              1221
-#define MACH_TYPE_INSTREAM             1222
-#define MACH_TYPE_AMBARELLA            1223
-#define MACH_TYPE_NEVIS                1224
-#define MACH_TYPE_HTC_TRINITY          1225
-#define MACH_TYPE_QL202B               1226
-#define MACH_TYPE_VPAC270              1227
-#define MACH_TYPE_RD129                1228
-#define MACH_TYPE_HTCWIZARD            1229
-#define MACH_TYPE_TREO680              1230
-#define MACH_TYPE_TECON_TMEZON         1231
-#define MACH_TYPE_ZYLONITE             1233
-#define MACH_TYPE_GENE1270             1234
-#define MACH_TYPE_ZIR2412              1235
-#define MACH_TYPE_MX31LITE             1236
-#define MACH_TYPE_T700WX               1237
-#define MACH_TYPE_VF100                1238
-#define MACH_TYPE_NSB2                 1239
-#define MACH_TYPE_NXHMI_BB             1240
-#define MACH_TYPE_NXHMI_RE             1241
-#define MACH_TYPE_N4100PRO             1242
-#define MACH_TYPE_SAM9260              1243
-#define MACH_TYPE_OMAP_TREO600         1244
-#define MACH_TYPE_INDY2410             1245
-#define MACH_TYPE_NELT_A               1246
-#define MACH_TYPE_N311                 1248
-#define MACH_TYPE_AT91SAM9260VGK       1249
-#define MACH_TYPE_AT91LEPPE            1250
-#define MACH_TYPE_AT91LEPCCN           1251
-#define MACH_TYPE_APC7100              1252
-#define MACH_TYPE_STARGAZER            1253
-#define MACH_TYPE_SONATA               1254
-#define MACH_TYPE_SCHMOOGIE            1255
-#define MACH_TYPE_AZTOOL               1256
-#define MACH_TYPE_MIOA701              1257
-#define MACH_TYPE_SXNI9260             1258
-#define MACH_TYPE_MXC27520EVB          1259
-#define MACH_TYPE_ARMADILLO5X0         1260
-#define MACH_TYPE_MB9260               1261
-#define MACH_TYPE_MB9263               1262
-#define MACH_TYPE_IPAC9302             1263
-#define MACH_TYPE_CC9P9360JS           1264
-#define MACH_TYPE_GALLIUM              1265
-#define MACH_TYPE_MSC2410              1266
-#define MACH_TYPE_GHI270               1267
-#define MACH_TYPE_DAVINCI_LEONARDO     1268
-#define MACH_TYPE_OIAB                 1269
-#define MACH_TYPE_SMDK6400             1270
-#define MACH_TYPE_NOKIA_N800           1271
-#define MACH_TYPE_GREENPHONE           1272
-#define MACH_TYPE_COMPEXWP18           1273
-#define MACH_TYPE_XMATE                1274
-#define MACH_TYPE_ENERGIZER            1275
-#define MACH_TYPE_IME1                 1276
-#define MACH_TYPE_SWEDATMS             1277
-#define MACH_TYPE_NTNP435C             1278
-#define MACH_TYPE_SPECTRO2             1279
-#define MACH_TYPE_H6039                1280
-#define MACH_TYPE_EP80219              1281
-#define MACH_TYPE_SAMOA_II             1282
-#define MACH_TYPE_CWMXL                1283
-#define MACH_TYPE_AS9200               1284
-#define MACH_TYPE_SFX1149              1285
-#define MACH_TYPE_NAVI010              1286
-#define MACH_TYPE_MULTMDP              1287
-#define MACH_TYPE_SCB9520              1288
-#define MACH_TYPE_HTCATHENA            1289
-#define MACH_TYPE_XP179                1290
-#define MACH_TYPE_H4300                1291
-#define MACH_TYPE_GORAMO_MLR           1292
-#define MACH_TYPE_MXC30020EVB          1293
-#define MACH_TYPE_ADSBITSYG5           1294
-#define MACH_TYPE_ADSPORTALPLUS        1295
-#define MACH_TYPE_MMSP2PLUS            1296
-#define MACH_TYPE_EM_X270              1297
-#define MACH_TYPE_TPP302               1298
-#define MACH_TYPE_TPM104               1299
-#define MACH_TYPE_TPM102               1300
-#define MACH_TYPE_TPM109               1301
-#define MACH_TYPE_FBXO1                1302
-#define MACH_TYPE_HXD8                 1303
-#define MACH_TYPE_NEO1973_GTA02        1304
-#define MACH_TYPE_EMTEST               1305
-#define MACH_TYPE_AD6900               1306
-#define MACH_TYPE_EUROPA               1307
-#define MACH_TYPE_METROCONNECT         1308
-#define MACH_TYPE_EZ_S2410             1309
-#define MACH_TYPE_EZ_S2440             1310
-#define MACH_TYPE_EZ_EP9312            1311
-#define MACH_TYPE_EZ_EP9315            1312
-#define MACH_TYPE_EZ_X7                1313
-#define MACH_TYPE_GODOTDB              1314
-#define MACH_TYPE_MISTRAL              1315
-#define MACH_TYPE_MSM                  1316
-#define MACH_TYPE_CT5910               1317
-#define MACH_TYPE_CT5912               1318
-#define MACH_TYPE_HYNET_INE            1319
-#define MACH_TYPE_HYNET_APP            1320
-#define MACH_TYPE_MSM7200              1321
-#define MACH_TYPE_MSM7600              1322
-#define MACH_TYPE_CEB255               1323
-#define MACH_TYPE_CIEL                 1324
-#define MACH_TYPE_SLM5650              1325
-#define MACH_TYPE_AT91SAM9RLEK         1326
-#define MACH_TYPE_COMTECH_ROUTER       1327
-#define MACH_TYPE_SBC2410X             1328
-#define MACH_TYPE_AT4X0BD              1329
-#define MACH_TYPE_CBIFR                1330
-#define MACH_TYPE_ARCOM_QUANTUM        1331
-#define MACH_TYPE_MATRIX520            1332
-#define MACH_TYPE_MATRIX510            1333
-#define MACH_TYPE_MATRIX500            1334
-#define MACH_TYPE_M501                 1335
-#define MACH_TYPE_AAEON1270            1336
-#define MACH_TYPE_MATRIX500EV          1337
-#define MACH_TYPE_PAC500               1338
-#define MACH_TYPE_PNX8181              1339
-#define MACH_TYPE_COLIBRI320           1340
-#define MACH_TYPE_AZTOOLBB             1341
-#define MACH_TYPE_AZTOOLG2             1342
-#define MACH_TYPE_DVLHOST              1343
-#define MACH_TYPE_ZIR9200              1344
-#define MACH_TYPE_ZIR9260              1345
-#define MACH_TYPE_COCOPAH              1346
-#define MACH_TYPE_NDS                  1347
-#define MACH_TYPE_ROSENCRANTZ          1348
-#define MACH_TYPE_FTTX_ODSC            1349
-#define MACH_TYPE_CLASSE_R6904         1350
-#define MACH_TYPE_CAM60                1351
-#define MACH_TYPE_MXC30031ADS          1352
-#define MACH_TYPE_DATACALL             1353
-#define MACH_TYPE_AT91EB01             1354
-#define MACH_TYPE_RTY                  1355
-#define MACH_TYPE_DWL2100              1356
-#define MACH_TYPE_VINSI                1357
-#define MACH_TYPE_DB88F5281            1358
-#define MACH_TYPE_CSB726               1359
-#define MACH_TYPE_TIK27                1360
-#define MACH_TYPE_MX_UC7420            1361
-#define MACH_TYPE_RIRM3                1362
-#define MACH_TYPE_PELCO_ODYSSEY        1363
-#define MACH_TYPE_ADX_ABOX             1365
-#define MACH_TYPE_ADX_TPID             1366
-#define MACH_TYPE_MINICHECK            1367
-#define MACH_TYPE_IDAM                 1368
-#define MACH_TYPE_MARIO_MX             1369
-#define MACH_TYPE_VI1888               1370
-#define MACH_TYPE_ZR4230               1371
-#define MACH_TYPE_T1_IX_BLUE           1372
-#define MACH_TYPE_SYHQ2                1373
-#define MACH_TYPE_COMPUTIME_R3         1374
-#define MACH_TYPE_ORATIS               1375
-#define MACH_TYPE_MIKKO                1376
-#define MACH_TYPE_HOLON                1377
-#define MACH_TYPE_OLIP8                1378
-#define MACH_TYPE_GHI270HG             1379
-#define MACH_TYPE_DAVINCI_DM6467_EVM   1380
-#define MACH_TYPE_DAVINCI_DM355_EVM    1381
-#define MACH_TYPE_BLACKRIVER           1383
-#define MACH_TYPE_SANDGATEWP           1384
-#define MACH_TYPE_CDOTBWSG             1385
-#define MACH_TYPE_QUARK963             1386
-#define MACH_TYPE_CSB735               1387
-#define MACH_TYPE_LITTLETON            1388
-#define MACH_TYPE_MIO_P550             1389
-#define MACH_TYPE_MOTION2440           1390
-#define MACH_TYPE_IMM500               1391
-#define MACH_TYPE_HOMEMATIC            1392
-#define MACH_TYPE_ERMINE               1393
-#define MACH_TYPE_KB9202B              1394
-#define MACH_TYPE_HS1XX                1395
-#define MACH_TYPE_STUDENTMATE2440      1396
-#define MACH_TYPE_ARVOO_L1_Z1          1397
-#define MACH_TYPE_DEP2410K             1398
-#define MACH_TYPE_XXSVIDEO             1399
-#define MACH_TYPE_IM4004               1400
-#define MACH_TYPE_OCHAYA1050           1401
-#define MACH_TYPE_LEP9261              1402
-#define MACH_TYPE_SVENMEB              1403
-#define MACH_TYPE_FORTUNET2NE          1404
-#define MACH_TYPE_NXHX                 1406
-#define MACH_TYPE_REALVIEW_PB11MP      1407
-#define MACH_TYPE_IDS500               1408
-#define MACH_TYPE_ORS_N725             1409
-#define MACH_TYPE_HSDARM               1410
-#define MACH_TYPE_SHA_PON003           1411
-#define MACH_TYPE_SHA_PON004           1412
-#define MACH_TYPE_SHA_PON007           1413
-#define MACH_TYPE_SHA_PON011           1414
-#define MACH_TYPE_H6042                1415
-#define MACH_TYPE_H6043                1416
-#define MACH_TYPE_LOOXC550             1417
-#define MACH_TYPE_CNTY_TITAN           1418
-#define MACH_TYPE_APP3XX               1419
-#define MACH_TYPE_SIDEOATSGRAMA        1420
-#define MACH_TYPE_TREO700P             1421
-#define MACH_TYPE_TREO700W             1422
-#define MACH_TYPE_TREO750              1423
-#define MACH_TYPE_TREO755P             1424
-#define MACH_TYPE_EZREGANUT9200        1425
-#define MACH_TYPE_SARGE                1426
-#define MACH_TYPE_A696                 1427
-#define MACH_TYPE_TURTLE               1428
-#define MACH_TYPE_MX27_3DS             1430
-#define MACH_TYPE_BISHOP               1431
-#define MACH_TYPE_PXX                  1432
-#define MACH_TYPE_REDWOOD              1433
-#define MACH_TYPE_OMAP_2430DLP         1436
-#define MACH_TYPE_OMAP_2430OSK         1437
-#define MACH_TYPE_SARDINE              1438
-#define MACH_TYPE_HALIBUT              1439
-#define MACH_TYPE_TROUT                1440
-#define MACH_TYPE_GOLDFISH             1441
-#define MACH_TYPE_GESBC2440            1442
-#define MACH_TYPE_NOMAD                1443
-#define MACH_TYPE_ROSALIND             1444
-#define MACH_TYPE_CC9P9215             1445
-#define MACH_TYPE_CC9P9210             1446
-#define MACH_TYPE_CC9P9215JS           1447
-#define MACH_TYPE_CC9P9210JS           1448
-#define MACH_TYPE_NASFFE               1449
-#define MACH_TYPE_TN2X0BD              1450
-#define MACH_TYPE_GWMPXA               1451
-#define MACH_TYPE_EXYPLUS              1452
-#define MACH_TYPE_JADOO21              1453
-#define MACH_TYPE_LOOXN560             1454
-#define MACH_TYPE_BONSAI               1455
-#define MACH_TYPE_ADSMILGATO           1456
-#define MACH_TYPE_GBA                  1457
-#define MACH_TYPE_H6044                1458
-#define MACH_TYPE_APP                  1459
-#define MACH_TYPE_TCT_HAMMER           1460
-#define MACH_TYPE_HERALD               1461
-#define MACH_TYPE_ARTEMIS              1462
-#define MACH_TYPE_HTCTITAN             1463
-#define MACH_TYPE_QRANIUM              1464
-#define MACH_TYPE_ADX_WSC2             1465
-#define MACH_TYPE_ADX_MEDCOM           1466
-#define MACH_TYPE_BBOARD               1467
-#define MACH_TYPE_CAMBRIA              1468
-#define MACH_TYPE_MT7XXX               1469
-#define MACH_TYPE_MATRIX512            1470
-#define MACH_TYPE_MATRIX522            1471
-#define MACH_TYPE_IPAC5010             1472
-#define MACH_TYPE_SAKURA               1473
-#define MACH_TYPE_GROCX                1474
-#define MACH_TYPE_PM9263               1475
-#define MACH_TYPE_SIM_ONE              1476
-#define MACH_TYPE_ACQ132               1477
-#define MACH_TYPE_DATR                 1478
-#define MACH_TYPE_ACTUX1               1479
-#define MACH_TYPE_ACTUX2               1480
-#define MACH_TYPE_ACTUX3               1481
-#define MACH_TYPE_FLEXIT               1482
-#define MACH_TYPE_BH2X0BD              1483
-#define MACH_TYPE_ATB2002              1484
-#define MACH_TYPE_XENON                1485
-#define MACH_TYPE_FM607                1486
-#define MACH_TYPE_MATRIX514            1487
-#define MACH_TYPE_MATRIX524            1488
-#define MACH_TYPE_INPOD                1489
-#define MACH_TYPE_JIVE                 1490
-#define MACH_TYPE_TLL_MX21             1491
-#define MACH_TYPE_SBC2800              1492
-#define MACH_TYPE_CC7UCAMRY            1493
-#define MACH_TYPE_UBISYS_P9_SC15       1494
-#define MACH_TYPE_UBISYS_P9_SSC2D10    1495
-#define MACH_TYPE_UBISYS_P9_RCU3       1496
-#define MACH_TYPE_AML_M8000            1497
-#define MACH_TYPE_SNAPPER_270          1498
-#define MACH_TYPE_OMAP_BBX             1499
-#define MACH_TYPE_UCN2410              1500
-#define MACH_TYPE_SAM9_L9260           1501
-#define MACH_TYPE_ETI_C2               1502
-#define MACH_TYPE_AVALANCHE            1503
-#define MACH_TYPE_REALVIEW_PB1176      1504
-#define MACH_TYPE_DP1500               1505
-#define MACH_TYPE_APPLE_IPHONE         1506
-#define MACH_TYPE_YL9200               1507
-#define MACH_TYPE_RD88F5182            1508
-#define MACH_TYPE_KUROBOX_PRO          1509
-#define MACH_TYPE_SE_POET              1510
-#define MACH_TYPE_MX31_3DS             1511
-#define MACH_TYPE_R270                 1512
-#define MACH_TYPE_ARMOUR21             1513
-#define MACH_TYPE_DT2                  1514
-#define MACH_TYPE_VT4                  1515
-#define MACH_TYPE_TYCO320              1516
-#define MACH_TYPE_ADMA                 1517
-#define MACH_TYPE_WP188                1518
-#define MACH_TYPE_CORSICA              1519
-#define MACH_TYPE_BIGEYE               1520
-#define MACH_TYPE_TLL5000              1522
-#define MACH_TYPE_BEBOT                1523
-#define MACH_TYPE_QONG                 1524
-#define MACH_TYPE_TCOMPACT             1525
-#define MACH_TYPE_PUMA5                1526
-#define MACH_TYPE_ELARA                1527
-#define MACH_TYPE_ELLINGTON            1528
-#define MACH_TYPE_XDA_ATOM             1529
-#define MACH_TYPE_ENERGIZER2           1530
-#define MACH_TYPE_ODIN                 1531
-#define MACH_TYPE_ACTUX4               1532
-#define MACH_TYPE_ESL_OMAP             1533
-#define MACH_TYPE_OMAP2EVM             1534
-#define MACH_TYPE_OMAP3EVM             1535
-#define MACH_TYPE_ADX_PCU57            1536
-#define MACH_TYPE_MONACO               1537
-#define MACH_TYPE_LEVANTE              1538
-#define MACH_TYPE_TMXIPX425            1539
-#define MACH_TYPE_LEEP                 1540
-#define MACH_TYPE_RAAD                 1541
-#define MACH_TYPE_DNS323               1542
-#define MACH_TYPE_AP1000               1543
-#define MACH_TYPE_A9SAM6432            1544
-#define MACH_TYPE_SHINY                1545
-#define MACH_TYPE_OMAP3_BEAGLE         1546
-#define MACH_TYPE_CSR_BDB2             1547
-#define MACH_TYPE_NOKIA_N810           1548
-#define MACH_TYPE_C270                 1549
-#define MACH_TYPE_SENTRY               1550
-#define MACH_TYPE_PCM038               1551
-#define MACH_TYPE_ANC300               1552
-#define MACH_TYPE_HTCKAISER            1553
-#define MACH_TYPE_SBAT100              1554
-#define MACH_TYPE_MODUNORM             1555
-#define MACH_TYPE_PELOS_TWARM          1556
-#define MACH_TYPE_FLANK                1557
-#define MACH_TYPE_SIRLOIN              1558
-#define MACH_TYPE_BRISKET              1559
-#define MACH_TYPE_CHUCK                1560
-#define MACH_TYPE_OTTER                1561
-#define MACH_TYPE_DAVINCI_LDK          1562
-#define MACH_TYPE_PHREEDOM             1563
-#define MACH_TYPE_SG310                1564
-#define MACH_TYPE_TS209                1565
-#define MACH_TYPE_AT91CAP9ADK          1566
-#define MACH_TYPE_TION9315             1567
-#define MACH_TYPE_MAST                 1568
-#define MACH_TYPE_PFW                  1569
-#define MACH_TYPE_YL_P2440             1570
-#define MACH_TYPE_ZSBC32               1571
-#define MACH_TYPE_OMAP_PACE2           1572
-#define MACH_TYPE_IMX_PACE2            1573
-#define MACH_TYPE_MX31MOBOARD          1574
-#define MACH_TYPE_MX37_3DS             1575
-#define MACH_TYPE_RCC                  1576
-#define MACH_TYPE_ARM9                 1577
-#define MACH_TYPE_VISION_EP9307        1578
-#define MACH_TYPE_SCLY1000             1579
-#define MACH_TYPE_FONTEL_EP            1580
-#define MACH_TYPE_VOICEBLUE3G          1581
-#define MACH_TYPE_TT9200               1582
-#define MACH_TYPE_DIGI2410             1583
-#define MACH_TYPE_TERASTATION_PRO2     1584
-#define MACH_TYPE_LINKSTATION_PRO      1585
-#define MACH_TYPE_MOTOROLA_A780        1587
-#define MACH_TYPE_MOTOROLA_E6          1588
-#define MACH_TYPE_MOTOROLA_E2          1589
-#define MACH_TYPE_MOTOROLA_E680        1590
-#define MACH_TYPE_UR2410               1591
-#define MACH_TYPE_TAS9261              1592
-#define MACH_TYPE_HERMES_HD            1593
-#define MACH_TYPE_PERSEO_HD            1594
-#define MACH_TYPE_STARGAZER2           1595
-#define MACH_TYPE_E350                 1596
-#define MACH_TYPE_WPCM450              1597
-#define MACH_TYPE_CARTESIO             1598
-#define MACH_TYPE_TOYBOX               1599
-#define MACH_TYPE_TX27                 1600
-#define MACH_TYPE_TS409                1601
-#define MACH_TYPE_P300                 1602
-#define MACH_TYPE_XDACOMET             1603
-#define MACH_TYPE_DEXFLEX2             1604
-#define MACH_TYPE_OW                   1605
-#define MACH_TYPE_ARMEBS3              1606
-#define MACH_TYPE_U3                   1607
-#define MACH_TYPE_SMDK2450             1608
-#define MACH_TYPE_RSI_EWS              1609
-#define MACH_TYPE_TNB                  1610
-#define MACH_TYPE_TOEPATH              1611
-#define MACH_TYPE_KB9263               1612
-#define MACH_TYPE_MT7108               1613
-#define MACH_TYPE_SMTR2440             1614
-#define MACH_TYPE_MANAO                1615
-#define MACH_TYPE_CM_X300              1616
-#define MACH_TYPE_GULFSTREAM_KP        1617
-#define MACH_TYPE_LANREADYFN522        1618
-#define MACH_TYPE_ARMA37               1619
-#define MACH_TYPE_MENDEL               1620
-#define MACH_TYPE_PELCO_ILIAD          1621
-#define MACH_TYPE_UNIT2P               1622
-#define MACH_TYPE_INC20OTTER           1623
-#define MACH_TYPE_AT91SAM9G20EK        1624
-#define MACH_TYPE_STORCENTER           1625
-#define MACH_TYPE_SMDK6410             1626
-#define MACH_TYPE_U300                 1627
-#define MACH_TYPE_U500                 1628
-#define MACH_TYPE_DS9260               1629
-#define MACH_TYPE_RIVERROCK            1630
-#define MACH_TYPE_SCIBATH              1631
-#define MACH_TYPE_AT91SAM7SE512EK      1632
-#define MACH_TYPE_WRT350N_V2           1633
-#define MACH_TYPE_MULTIMEDIA           1634
-#define MACH_TYPE_MARVIN               1635
-#define MACH_TYPE_X500                 1636
-#define MACH_TYPE_AWLUG4LCU            1637
-#define MACH_TYPE_PALERMOC             1638
-#define MACH_TYPE_OMAP_LDP             1639
-#define MACH_TYPE_IP500                1640
-#define MACH_TYPE_ASE2                 1642
-#define MACH_TYPE_MX35EVB              1643
-#define MACH_TYPE_AML_M8050            1644
-#define MACH_TYPE_MX35_3DS             1645
-#define MACH_TYPE_MARS                 1646
-#define MACH_TYPE_NEUROS_OSD2          1647
-#define MACH_TYPE_BADGER               1648
-#define MACH_TYPE_TRIZEPS4WL           1649
-#define MACH_TYPE_TRIZEPS5             1650
-#define MACH_TYPE_MARLIN               1651
-#define MACH_TYPE_TS78XX               1652
-#define MACH_TYPE_HPIPAQ214            1653
-#define MACH_TYPE_AT572D940DCM         1654
-#define MACH_TYPE_NE1BOARD             1655
-#define MACH_TYPE_ZANTE                1656
-#define MACH_TYPE_SFFSDR               1657
-#define MACH_TYPE_TW2662               1658
-#define MACH_TYPE_VF10XX               1659
-#define MACH_TYPE_ZORAN43XX            1660
-#define MACH_TYPE_SONIX926             1661
-#define MACH_TYPE_CELESTIALSEMI        1662
-#define MACH_TYPE_CC9M2443JS           1663
-#define MACH_TYPE_TW5334               1664
-#define MACH_TYPE_HTCARTEMIS           1665
-#define MACH_TYPE_NAL_HLITE            1666
-#define MACH_TYPE_HTCVOGUE             1667
-#define MACH_TYPE_SMARTWEB             1668
-#define MACH_TYPE_MV86XX               1669
-#define MACH_TYPE_MV87XX               1670
-#define MACH_TYPE_SONGYOUNGHO          1671
-#define MACH_TYPE_YOUNGHOTEMA          1672
-#define MACH_TYPE_PCM037               1673
-#define MACH_TYPE_MMVP                 1674
-#define MACH_TYPE_MMAP                 1675
-#define MACH_TYPE_PTID2410             1676
-#define MACH_TYPE_JAMES_926            1677
-#define MACH_TYPE_FM6000               1678
-#define MACH_TYPE_DB88F6281_BP         1680
-#define MACH_TYPE_RD88F6192_NAS        1681
-#define MACH_TYPE_RD88F6281            1682
-#define MACH_TYPE_DB78X00_BP           1683
-#define MACH_TYPE_SMDK2416             1685
-#define MACH_TYPE_OCE_SPIDER_SI        1686
-#define MACH_TYPE_OCE_SPIDER_SK        1687
-#define MACH_TYPE_ROVERN6              1688
-#define MACH_TYPE_PELCO_EVOLUTION      1689
-#define MACH_TYPE_WBD111               1690
-#define MACH_TYPE_ELARACPE             1691
-#define MACH_TYPE_MABV3                1692
-#define MACH_TYPE_MV2120               1693
-#define MACH_TYPE_CSB737               1695
-#define MACH_TYPE_MX51_3DS             1696
-#define MACH_TYPE_G900                 1697
-#define MACH_TYPE_APF27                1698
-#define MACH_TYPE_GGUS2000             1699
-#define MACH_TYPE_OMAP_2430_MIMIC      1700
-#define MACH_TYPE_IMX27LITE            1701
-#define MACH_TYPE_ALMEX                1702
-#define MACH_TYPE_CONTROL              1703
-#define MACH_TYPE_MBA2410              1704
-#define MACH_TYPE_VOLCANO              1705
-#define MACH_TYPE_ZENITH               1706
-#define MACH_TYPE_MUCHIP               1707
-#define MACH_TYPE_MAGELLAN             1708
-#define MACH_TYPE_USB_A9260            1709
-#define MACH_TYPE_USB_A9263            1710
-#define MACH_TYPE_QIL_A9260            1711
-#define MACH_TYPE_CME9210              1712
-#define MACH_TYPE_HCZH4                1713
-#define MACH_TYPE_SPEARBASIC           1714
-#define MACH_TYPE_DEP2440              1715
-#define MACH_TYPE_HDL_GXR              1716
-#define MACH_TYPE_HDL_GT               1717
-#define MACH_TYPE_HDL_4G               1718
-#define MACH_TYPE_S3C6000              1719
-#define MACH_TYPE_MMSP2_MDK            1720
-#define MACH_TYPE_MPX220               1721
-#define MACH_TYPE_KZM_ARM11_01         1722
-#define MACH_TYPE_HTC_POLARIS          1723
-#define MACH_TYPE_HTC_KAISER           1724
-#define MACH_TYPE_LG_KS20              1725
-#define MACH_TYPE_HHGPS                1726
-#define MACH_TYPE_NOKIA_N810_WIMAX     1727
-#define MACH_TYPE_INSIGHT              1728
-#define MACH_TYPE_SAPPHIRE             1729
-#define MACH_TYPE_CSB637XO             1730
-#define MACH_TYPE_EVISIONG             1731
-#define MACH_TYPE_STMP37XX             1732
-#define MACH_TYPE_STMP378X             1733
-#define MACH_TYPE_TNT                  1734
-#define MACH_TYPE_TBXT                 1735
-#define MACH_TYPE_PLAYMATE             1736
-#define MACH_TYPE_PNS10                1737
-#define MACH_TYPE_EZNAVI               1738
-#define MACH_TYPE_PS4000               1739
-#define MACH_TYPE_EZX_A780             1740
-#define MACH_TYPE_EZX_E680             1741
-#define MACH_TYPE_EZX_A1200            1742
-#define MACH_TYPE_EZX_E6               1743
-#define MACH_TYPE_EZX_E2               1744
-#define MACH_TYPE_EZX_A910             1745
-#define MACH_TYPE_CWMX31               1746
-#define MACH_TYPE_SL2312               1747
-#define MACH_TYPE_BLENNY               1748
-#define MACH_TYPE_DS107                1749
-#define MACH_TYPE_DSX07                1750
-#define MACH_TYPE_PICOCOM1             1751
-#define MACH_TYPE_LYNX_WOLVERINE       1752
-#define MACH_TYPE_UBISYS_P9_SC19       1753
-#define MACH_TYPE_KRATOS_LOW           1754
-#define MACH_TYPE_M700                 1755
-#define MACH_TYPE_EDMINI_V2            1756
-#define MACH_TYPE_ZIPIT2               1757
-#define MACH_TYPE_HSLFEMTOCELL         1758
-#define MACH_TYPE_DAINTREE_AT91        1759
-#define MACH_TYPE_SG560USB             1760
-#define MACH_TYPE_OMAP3_PANDORA        1761
-#define MACH_TYPE_USR8200              1762
-#define MACH_TYPE_S1S65K               1763
-#define MACH_TYPE_S2S65A               1764
-#define MACH_TYPE_ICORE                1765
-#define MACH_TYPE_MSS2                 1766
-#define MACH_TYPE_BELMONT              1767
-#define MACH_TYPE_ASUSP525             1768
-#define MACH_TYPE_LB88RC8480           1769
-#define MACH_TYPE_HIPXA                1770
-#define MACH_TYPE_MX25_3DS             1771
-#define MACH_TYPE_M800                 1772
-#define MACH_TYPE_OMAP3530_LV_SOM      1773
-#define MACH_TYPE_PRIMA_EVB            1774
-#define MACH_TYPE_MX31BT1              1775
-#define MACH_TYPE_ATLAS4_EVB           1776
-#define MACH_TYPE_MX31CICADA           1777
-#define MACH_TYPE_MI424WR              1778
-#define MACH_TYPE_AXS_ULTRAX           1779
-#define MACH_TYPE_AT572D940DEB         1780
-#define MACH_TYPE_DAVINCI_DA830_EVM    1781
-#define MACH_TYPE_EP9302               1782
-#define MACH_TYPE_AT572D940HFEB        1783
-#define MACH_TYPE_CYBOOK3              1784
-#define MACH_TYPE_WDG002               1785
-#define MACH_TYPE_SG560ADSL            1786
-#define MACH_TYPE_NEXTIO_N2800_ICA     1787
-#define MACH_TYPE_DOVE_DB              1788
-#define MACH_TYPE_MARVELL_NEWDB        1789
-#define MACH_TYPE_VANDIHUD             1790
-#define MACH_TYPE_MAGX_E8              1791
-#define MACH_TYPE_MAGX_Z6              1792
-#define MACH_TYPE_MAGX_V8              1793
-#define MACH_TYPE_MAGX_U9              1794
-#define MACH_TYPE_TOUGHCF08            1795
-#define MACH_TYPE_ZW4400               1796
-#define MACH_TYPE_MARAT91              1797
-#define MACH_TYPE_OVERO                1798
-#define MACH_TYPE_AT2440EVB            1799
-#define MACH_TYPE_NEOCORE926           1800
-#define MACH_TYPE_WNR854T              1801
-#define MACH_TYPE_IMX27                1802
-#define MACH_TYPE_MOOSE_DB             1803
-#define MACH_TYPE_FAB4                 1804
-#define MACH_TYPE_HTCDIAMOND           1805
-#define MACH_TYPE_FIONA                1806
-#define MACH_TYPE_MXC30030_X           1807
-#define MACH_TYPE_BMP1000              1808
-#define MACH_TYPE_LOGI9200             1809
-#define MACH_TYPE_TQMA31               1810
-#define MACH_TYPE_CCW9P9215JS          1811
-#define MACH_TYPE_RD88F5181L_GE        1812
-#define MACH_TYPE_SIFMAIN              1813
-#define MACH_TYPE_SAM9_L9261           1814
-#define MACH_TYPE_CC9M2443             1815
-#define MACH_TYPE_XARIA300             1816
-#define MACH_TYPE_IT9200               1817
-#define MACH_TYPE_RD88F5181L_FXO       1818
-#define MACH_TYPE_KRISS_SENSOR         1819
-#define MACH_TYPE_PILZ_PMI5            1820
-#define MACH_TYPE_JADE                 1821
-#define MACH_TYPE_KS8695_SOFTPLC       1822
-#define MACH_TYPE_GPRISC3              1823
-#define MACH_TYPE_STAMP9G20            1824
-#define MACH_TYPE_SMDK6430             1825
-#define MACH_TYPE_SMDKC100             1826
-#define MACH_TYPE_TAVOREVB             1827
-#define MACH_TYPE_SAAR                 1828
-#define MACH_TYPE_DEISTER_EYECAM       1829
-#define MACH_TYPE_AT91SAM9M10G45EK     1830
-#define MACH_TYPE_LINKSTATION_PRODUO   1831
-#define MACH_TYPE_HIT_B0               1832
-#define MACH_TYPE_ADX_RMU              1833
-#define MACH_TYPE_XG_CPE_MAIN          1834
-#define MACH_TYPE_EDB9407A             1835
-#define MACH_TYPE_DTB9608              1836
-#define MACH_TYPE_EM104V1              1837
-#define MACH_TYPE_DEMO                 1838
-#define MACH_TYPE_LOGI9260             1839
-#define MACH_TYPE_MX31_EXM32           1840
-#define MACH_TYPE_USB_A9G20            1841
-#define MACH_TYPE_PICPROJE2008         1842
-#define MACH_TYPE_CS_E9315             1843
-#define MACH_TYPE_QIL_A9G20            1844
-#define MACH_TYPE_SHA_PON020           1845
-#define MACH_TYPE_NAD                  1846
-#define MACH_TYPE_SBC35_A9260          1847
-#define MACH_TYPE_SBC35_A9G20          1848
-#define MACH_TYPE_DAVINCI_BEGINNING    1849
-#define MACH_TYPE_UWC                  1850
-#define MACH_TYPE_MXLADS               1851
-#define MACH_TYPE_HTCNIKE              1852
-#define MACH_TYPE_DEISTER_PXA270       1853
-#define MACH_TYPE_CME9210JS            1854
-#define MACH_TYPE_CC9P9360             1855
-#define MACH_TYPE_MOCHA                1856
-#define MACH_TYPE_WAPD170AG            1857
-#define MACH_TYPE_LINKSTATION_MINI     1858
-#define MACH_TYPE_AFEB9260             1859
-#define MACH_TYPE_W90X900              1860
-#define MACH_TYPE_W90X700              1861
-#define MACH_TYPE_KT300IP              1862
-#define MACH_TYPE_KT300IP_G20          1863
-#define MACH_TYPE_SRCM                 1864
-#define MACH_TYPE_WLNX_9260            1865
-#define MACH_TYPE_OPENMOKO_GTA03       1866
-#define MACH_TYPE_OSPREY2              1867
-#define MACH_TYPE_KBIO9260             1868
-#define MACH_TYPE_GINZA                1869
-#define MACH_TYPE_A636N                1870
-#define MACH_TYPE_IMX27IPCAM           1871
-#define MACH_TYPE_NEMOC                1872
-#define MACH_TYPE_GENEVA               1873
-#define MACH_TYPE_HTCPHAROS            1874
-#define MACH_TYPE_NEONC                1875
-#define MACH_TYPE_NAS7100              1876
-#define MACH_TYPE_TEUPHONE             1877
-#define MACH_TYPE_ANNAX_ETH2           1878
-#define MACH_TYPE_CSB733               1879
-#define MACH_TYPE_BK3                  1880
-#define MACH_TYPE_OMAP_EM32            1881
-#define MACH_TYPE_ET9261CP             1882
-#define MACH_TYPE_JASPERC              1883
-#define MACH_TYPE_ISSI_ARM9            1884
-#define MACH_TYPE_UED                  1885
-#define MACH_TYPE_ESIBLADE             1886
-#define MACH_TYPE_EYE02                1887
-#define MACH_TYPE_IMX27KBD             1888
-#define MACH_TYPE_SST61VC010_FPGA      1889
-#define MACH_TYPE_KIXVP435             1890
-#define MACH_TYPE_KIXNP435             1891
-#define MACH_TYPE_AFRICA               1892
-#define MACH_TYPE_NH233                1893
-#define MACH_TYPE_RD88F6183AP_GE       1894
-#define MACH_TYPE_BCM4760              1895
-#define MACH_TYPE_EDDY_V2              1896
-#define MACH_TYPE_REALVIEW_PBA8        1897
-#define MACH_TYPE_HID_A7               1898
-#define MACH_TYPE_HERO                 1899
-#define MACH_TYPE_OMAP_POSEIDON        1900
-#define MACH_TYPE_REALVIEW_PBX         1901
-#define MACH_TYPE_MICRO9S              1902
-#define MACH_TYPE_MAKO                 1903
-#define MACH_TYPE_XDAFLAME             1904
-#define MACH_TYPE_PHIDGET_SBC2         1905
-#define MACH_TYPE_LIMESTONE            1906
-#define MACH_TYPE_IPROBE_C32           1907
-#define MACH_TYPE_RUT100               1908
-#define MACH_TYPE_ASUSP535             1909
-#define MACH_TYPE_HTCRAPHAEL           1910
-#define MACH_TYPE_SYGDG1               1911
-#define MACH_TYPE_SYGDG2               1912
-#define MACH_TYPE_SEOUL                1913
-#define MACH_TYPE_SALERNO              1914
-#define MACH_TYPE_UCN_S3C64XX          1915
-#define MACH_TYPE_MSM7201A             1916
-#define MACH_TYPE_LPR1                 1917
-#define MACH_TYPE_ARMADILLO500FX       1918
-#define MACH_TYPE_G3EVM                1919
-#define MACH_TYPE_Z3_DM355             1920
-#define MACH_TYPE_W90P910EVB           1921
-#define MACH_TYPE_W90P920EVB           1922
-#define MACH_TYPE_W90P950EVB           1923
-#define MACH_TYPE_W90N960EVB           1924
-#define MACH_TYPE_CAMHD                1925
-#define MACH_TYPE_MVC100               1926
-#define MACH_TYPE_ELECTRUM_200         1927
-#define MACH_TYPE_HTCJADE              1928
-#define MACH_TYPE_MEMPHIS              1929
-#define MACH_TYPE_IMX27SBC             1930
-#define MACH_TYPE_LEXTAR               1931
-#define MACH_TYPE_MV88F6281GTW_GE      1932
-#define MACH_TYPE_NCP                  1933
-#define MACH_TYPE_Z32AN                1934
-#define MACH_TYPE_TMQ_CAPD             1935
-#define MACH_TYPE_OMAP3_WL             1936
-#define MACH_TYPE_CHUMBY               1937
-#define MACH_TYPE_ATSARM9              1938
-#define MACH_TYPE_DAVINCI_DM365_EVM    1939
-#define MACH_TYPE_BAHAMAS              1940
-#define MACH_TYPE_DAS                  1941
-#define MACH_TYPE_MINIDAS              1942
-#define MACH_TYPE_VK1000               1943
-#define MACH_TYPE_CENTRO               1944
-#define MACH_TYPE_CTERA_2BAY           1945
-#define MACH_TYPE_EDGECONNECT          1946
-#define MACH_TYPE_ND27000              1947
-#define MACH_TYPE_GEMALTO_COBRA        1948
-#define MACH_TYPE_INGELABS_COMET       1949
-#define MACH_TYPE_POLLUX_WIZ           1950
-#define MACH_TYPE_BLACKSTONE           1951
-#define MACH_TYPE_TOPAZ                1952
-#define MACH_TYPE_AIXLE                1953
-#define MACH_TYPE_MW998                1954
-#define MACH_TYPE_NOKIA_RX51           1955
-#define MACH_TYPE_VSC5605EV            1956
-#define MACH_TYPE_NT98700DK            1957
-#define MACH_TYPE_ICONTACT             1958
-#define MACH_TYPE_SWARCO_FRCPU         1959
-#define MACH_TYPE_SWARCO_SCPU          1960
-#define MACH_TYPE_BBOX_P16             1961
-#define MACH_TYPE_BSTD                 1962
-#define MACH_TYPE_SBC2440II            1963
-#define MACH_TYPE_PCM034               1964
-#define MACH_TYPE_NESO                 1965
-#define MACH_TYPE_WLNX_9G20            1966
-#define MACH_TYPE_OMAP_ZOOM2           1967
-#define MACH_TYPE_TOTEMNOVA            1968
-#define MACH_TYPE_C5000                1969
-#define MACH_TYPE_UNIPO_AT91SAM9263    1970
-#define MACH_TYPE_ETHERNUT5            1971
-#define MACH_TYPE_ARM11                1972
-#define MACH_TYPE_CPUAT9260            1973
-#define MACH_TYPE_CPUPXA255            1974
-#define MACH_TYPE_CPUIMX27             1975
-#define MACH_TYPE_CHEFLUX              1976
-#define MACH_TYPE_EB_CPUX9K2           1977
-#define MACH_TYPE_OPCOTEC              1978
-#define MACH_TYPE_YT                   1979
-#define MACH_TYPE_MOTOQ                1980
-#define MACH_TYPE_BSB1                 1981
-#define MACH_TYPE_ACS5K                1982
-#define MACH_TYPE_MILAN                1983
-#define MACH_TYPE_QUARTZV2             1984
-#define MACH_TYPE_RSVP                 1985
-#define MACH_TYPE_RMP200               1986
-#define MACH_TYPE_SNAPPER_9260         1987
-#define MACH_TYPE_DSM320               1988
-#define MACH_TYPE_ADSGCM               1989
-#define MACH_TYPE_ASE2_400             1990
-#define MACH_TYPE_PIZZA                1991
-#define MACH_TYPE_SPOT_NGPL            1992
-#define MACH_TYPE_ARMATA               1993
-#define MACH_TYPE_EXEDA                1994
-#define MACH_TYPE_MX31SF005            1995
-#define MACH_TYPE_F5D8231_4_V2         1996
-#define MACH_TYPE_Q2440                1997
-#define MACH_TYPE_QQ2440               1998
-#define MACH_TYPE_MINI2440             1999
-#define MACH_TYPE_COLIBRI300           2000
-#define MACH_TYPE_JADES                2001
-#define MACH_TYPE_SPARK                2002
-#define MACH_TYPE_BENZINA              2003
-#define MACH_TYPE_BLAZE                2004
-#define MACH_TYPE_LINKSTATION_LS_HGL   2005
-#define MACH_TYPE_HTCKOVSKY            2006
-#define MACH_TYPE_SONY_PRS505          2007
-#define MACH_TYPE_HANLIN_V3            2008
-#define MACH_TYPE_SAPPHIRA             2009
-#define MACH_TYPE_DACK_SDA_01          2010
-#define MACH_TYPE_ARMBOX               2011
-#define MACH_TYPE_HARRIS_RVP           2012
-#define MACH_TYPE_RIBALDO              2013
-#define MACH_TYPE_AGORA                2014
-#define MACH_TYPE_OMAP3_MINI           2015
-#define MACH_TYPE_A9SAM6432_B          2016
-#define MACH_TYPE_USG2410              2017
-#define MACH_TYPE_PC72052_I10_REVB     2018
-#define MACH_TYPE_MX35_EXM32           2019
-#define MACH_TYPE_TOPAS910             2020
-#define MACH_TYPE_HYENA                2021
-#define MACH_TYPE_POSPAX               2022
-#define MACH_TYPE_HDL_GX               2023
-#define MACH_TYPE_CTERA_4BAY           2024
-#define MACH_TYPE_CTERA_PLUG_C         2025
-#define MACH_TYPE_CRWEA_PLUG_I         2026
-#define MACH_TYPE_EGAUGE2              2027
-#define MACH_TYPE_DIDJ                 2028
-#define MACH_TYPE_MEISTER              2029
-#define MACH_TYPE_HTCBLACKSTONE        2030
-#define MACH_TYPE_CPUAT9G20            2031
-#define MACH_TYPE_SMDK6440             2032
-#define MACH_TYPE_OMAP_35XX_MVP        2033
-#define MACH_TYPE_CTERA_PLUG_I         2034
-#define MACH_TYPE_PVG610               2035
-#define MACH_TYPE_HPRW6815             2036
-#define MACH_TYPE_OMAP3_OSWALD         2037
-#define MACH_TYPE_NAS4220B             2038
-#define MACH_TYPE_HTCRAPHAEL_CDMA      2039
-#define MACH_TYPE_HTCDIAMOND_CDMA      2040
-#define MACH_TYPE_SCALER               2041
-#define MACH_TYPE_ZYLONITE2            2042
-#define MACH_TYPE_ASPENITE             2043
-#define MACH_TYPE_TETON                2044
-#define MACH_TYPE_TTC_DKB              2045
-#define MACH_TYPE_BISHOP2              2046
-#define MACH_TYPE_IPPV5                2047
-#define MACH_TYPE_FARM926              2048
-#define MACH_TYPE_MMCCPU               2049
-#define MACH_TYPE_SGMSFL               2050
-#define MACH_TYPE_TT8000               2051
-#define MACH_TYPE_ZRN4300LP            2052
-#define MACH_TYPE_MPTC                 2053
-#define MACH_TYPE_H6051                2054
-#define MACH_TYPE_PVG610_101           2055
-#define MACH_TYPE_STAMP9261_PC_EVB     2056
-#define MACH_TYPE_PELCO_ODYSSEUS       2057
-#define MACH_TYPE_TNY_A9260            2058
-#define MACH_TYPE_TNY_A9G20            2059
-#define MACH_TYPE_AESOP_MP2530F        2060
-#define MACH_TYPE_DX900                2061
-#define MACH_TYPE_CPODC2               2062
-#define MACH_TYPE_TILT_8925            2063
-#define MACH_TYPE_DAVINCI_DM357_EVM    2064
-#define MACH_TYPE_SWORDFISH            2065
-#define MACH_TYPE_CORVUS               2066
-#define MACH_TYPE_TAURUS               2067
-#define MACH_TYPE_AXM                  2068
-#define MACH_TYPE_AXC                  2069
-#define MACH_TYPE_BABY                 2070
-#define MACH_TYPE_MP200                2071
-#define MACH_TYPE_PCM043               2072
-#define MACH_TYPE_HANLIN_V3C           2073
-#define MACH_TYPE_KBK9G20              2074
-#define MACH_TYPE_ADSTURBOG5           2075
-#define MACH_TYPE_AVENGER_LITE1        2076
-#define MACH_TYPE_SUC                  2077
-#define MACH_TYPE_AT91SAM7S256         2078
-#define MACH_TYPE_MENDOZA              2079
-#define MACH_TYPE_KIRA                 2080
-#define MACH_TYPE_MX1HBM               2081
-#define MACH_TYPE_QUATRO43XX           2082
-#define MACH_TYPE_QUATRO4230           2083
-#define MACH_TYPE_NSB400               2084
-#define MACH_TYPE_DRP255               2085
-#define MACH_TYPE_THOTH                2086
-#define MACH_TYPE_FIRESTONE            2087
-#define MACH_TYPE_ASUSP750             2088
-#define MACH_TYPE_CTERA_DL             2089
-#define MACH_TYPE_SOCR                 2090
-#define MACH_TYPE_HTCOXYGEN            2091
-#define MACH_TYPE_HEROC                2092
-#define MACH_TYPE_ZENO6800             2093
-#define MACH_TYPE_SC2MCS               2094
-#define MACH_TYPE_GENE100              2095
-#define MACH_TYPE_AS353X               2096
-#define MACH_TYPE_SHEEVAPLUG           2097
-#define MACH_TYPE_AT91SAM9G20          2098
-#define MACH_TYPE_MV88F6192GTW_FE      2099
-#define MACH_TYPE_CC9200               2100
-#define MACH_TYPE_SM9200               2101
-#define MACH_TYPE_TP9200               2102
-#define MACH_TYPE_SNAPPERDV            2103
-#define MACH_TYPE_AVENGERS_LITE        2104
-#define MACH_TYPE_AVENGERS_LITE1       2105
-#define MACH_TYPE_OMAP3AXON            2106
-#define MACH_TYPE_MA8XX                2107
-#define MACH_TYPE_MP201EK              2108
-#define MACH_TYPE_DAVINCI_TUX          2109
-#define MACH_TYPE_MPA1600              2110
-#define MACH_TYPE_PELCO_TROY           2111
-#define MACH_TYPE_NSB667               2112
-#define MACH_TYPE_ROVERS5_4MPIX        2113
-#define MACH_TYPE_TWOCOM               2114
-#define MACH_TYPE_UBISYS_P9_RCU3R2     2115
-#define MACH_TYPE_HERO_ESPRESSO        2116
-#define MACH_TYPE_AFEUSB               2117
-#define MACH_TYPE_T830                 2118
-#define MACH_TYPE_SPD8020_CC           2119
-#define MACH_TYPE_OM_3D7K              2120
-#define MACH_TYPE_PICOCOM2             2121
-#define MACH_TYPE_UWG4MX27             2122
-#define MACH_TYPE_UWG4MX31             2123
-#define MACH_TYPE_CHERRY               2124
-#define MACH_TYPE_MX51_BABBAGE         2125
-#define MACH_TYPE_S3C2440TURKIYE       2126
-#define MACH_TYPE_TX37                 2127
-#define MACH_TYPE_SBC2800_9G20         2128
-#define MACH_TYPE_BENZGLB              2129
-#define MACH_TYPE_BENZTD               2130
-#define MACH_TYPE_CARTESIO_PLUS        2131
-#define MACH_TYPE_SOLRAD_G20           2132
-#define MACH_TYPE_MX27WALLACE          2133
-#define MACH_TYPE_FMZWEBMODUL          2134
-#define MACH_TYPE_RD78X00_MASA         2135
-#define MACH_TYPE_SMALLOGGER           2136
-#define MACH_TYPE_CCW9P9215            2137
-#define MACH_TYPE_DM355_LEOPARD        2138
-#define MACH_TYPE_TS219                2139
-#define MACH_TYPE_TNY_A9263            2140
-#define MACH_TYPE_APOLLO               2141
-#define MACH_TYPE_AT91CAP9STK          2142
-#define MACH_TYPE_SPC300               2143
-#define MACH_TYPE_EKO                  2144
-#define MACH_TYPE_CCW9M2443            2145
-#define MACH_TYPE_CCW9M2443JS          2146
-#define MACH_TYPE_M2M_ROUTER_DEVICE    2147
-#define MACH_TYPE_STAR9104NAS          2148
-#define MACH_TYPE_PCA100               2149
-#define MACH_TYPE_Z3_DM365_MOD_01      2150
-#define MACH_TYPE_HIPOX                2151
-#define MACH_TYPE_OMAP3_PITEDS         2152
-#define MACH_TYPE_BM150R               2153
-#define MACH_TYPE_TBONE                2154
-#define MACH_TYPE_MERLIN               2155
-#define MACH_TYPE_FALCON               2156
-#define MACH_TYPE_DAVINCI_DA850_EVM    2157
-#define MACH_TYPE_S5P6440              2158
-#define MACH_TYPE_AT91SAM9G10EK        2159
-#define MACH_TYPE_OMAP_4430SDP         2160
-#define MACH_TYPE_LPC313X              2161
-#define MACH_TYPE_MAGX_ZN5             2162
-#define MACH_TYPE_MAGX_EM30            2163
-#define MACH_TYPE_MAGX_VE66            2164
-#define MACH_TYPE_MEESC                2165
-#define MACH_TYPE_OTC570               2166
-#define MACH_TYPE_BCU2412              2167
-#define MACH_TYPE_BEACON               2168
-#define MACH_TYPE_ACTIA_TGW            2169
-#define MACH_TYPE_E4430                2170
-#define MACH_TYPE_QL300                2171
-#define MACH_TYPE_BTMAVB101            2172
-#define MACH_TYPE_BTMAWB101            2173
-#define MACH_TYPE_SQ201                2174
-#define MACH_TYPE_QUATRO45XX           2175
-#define MACH_TYPE_OPENPAD              2176
-#define MACH_TYPE_TX25                 2177
-#define MACH_TYPE_OMAP3_TORPEDO        2178
-#define MACH_TYPE_HTCRAPHAEL_K         2179
-#define MACH_TYPE_LAL43                2181
-#define MACH_TYPE_HTCRAPHAEL_CDMA500   2182
-#define MACH_TYPE_ANW6410              2183
-#define MACH_TYPE_HTCPROPHET           2185
-#define MACH_TYPE_CFA_10022            2186
-#define MACH_TYPE_IMX27_VISSTRIM_M10   2187
-#define MACH_TYPE_PX2IMX27             2188
-#define MACH_TYPE_STM3210E_EVAL        2189
-#define MACH_TYPE_DVS10                2190
-#define MACH_TYPE_PORTUXG20            2191
-#define MACH_TYPE_ARM_SPV              2192
-#define MACH_TYPE_SMDKC110             2193
-#define MACH_TYPE_CABESPRESSO          2194
-#define MACH_TYPE_HMC800               2195
-#define MACH_TYPE_SHOLES               2196
-#define MACH_TYPE_BTMXC31              2197
-#define MACH_TYPE_DT501                2198
-#define MACH_TYPE_KTX                  2199
-#define MACH_TYPE_OMAP3517EVM          2200
-#define MACH_TYPE_NETSPACE_V2          2201
-#define MACH_TYPE_NETSPACE_MAX_V2      2202
-#define MACH_TYPE_D2NET_V2             2203
-#define MACH_TYPE_NET2BIG_V2           2204
-#define MACH_TYPE_NET4BIG_V2           2205
-#define MACH_TYPE_NET5BIG_V2           2206
-#define MACH_TYPE_ENDB2443             2207
-#define MACH_TYPE_INETSPACE_V2         2208
-#define MACH_TYPE_TROS                 2209
-#define MACH_TYPE_PELCO_HOMER          2210
-#define MACH_TYPE_OFSP8                2211
-#define MACH_TYPE_AT91SAM9G45EKES      2212
-#define MACH_TYPE_GUF_CUPID            2213
-#define MACH_TYPE_EAB1R                2214
-#define MACH_TYPE_DESIREC              2215
-#define MACH_TYPE_CORDOBA              2216
-#define MACH_TYPE_IRVINE               2217
-#define MACH_TYPE_SFF772               2218
-#define MACH_TYPE_PELCO_MILANO         2219
-#define MACH_TYPE_PC7302               2220
-#define MACH_TYPE_BIP6000              2221
-#define MACH_TYPE_SILVERMOON           2222
-#define MACH_TYPE_VC0830               2223
-#define MACH_TYPE_DT430                2224
-#define MACH_TYPE_JI42PF               2225
-#define MACH_TYPE_GNET_KSM             2226
-#define MACH_TYPE_GNET_SGM             2227
-#define MACH_TYPE_GNET_SGR             2228
-#define MACH_TYPE_OMAP3_ICETEKEVM      2229
-#define MACH_TYPE_PNP                  2230
-#define MACH_TYPE_CTERA_2BAY_K         2231
-#define MACH_TYPE_CTERA_2BAY_U         2232
-#define MACH_TYPE_SAS_C                2233
-#define MACH_TYPE_VMA2315              2234
-#define MACH_TYPE_VCS                  2235
-#define MACH_TYPE_SPEAR600             2236
-#define MACH_TYPE_SPEAR300             2237
-#define MACH_TYPE_SPEAR1300            2238
-#define MACH_TYPE_LILLY1131            2239
-#define MACH_TYPE_ARVOO_AX301          2240
-#define MACH_TYPE_MAPPHONE             2241
-#define MACH_TYPE_LEGEND               2242
-#define MACH_TYPE_SALSA                2243
-#define MACH_TYPE_LOUNGE               2244
-#define MACH_TYPE_VISION               2245
-#define MACH_TYPE_VMB20                2246
-#define MACH_TYPE_HY2410               2247
-#define MACH_TYPE_HY9315               2248
-#define MACH_TYPE_BULLWINKLE           2249
-#define MACH_TYPE_ARM_ULTIMATOR2       2250
-#define MACH_TYPE_VS_V210              2252
-#define MACH_TYPE_VS_V212              2253
-#define MACH_TYPE_HMT                  2254
-#define MACH_TYPE_KM_KIRKWOOD          2255
-#define MACH_TYPE_VESPER               2256
-#define MACH_TYPE_STR9                 2257
-#define MACH_TYPE_OMAP3_WL_FF          2258
-#define MACH_TYPE_SIMCOM               2259
-#define MACH_TYPE_MCWEBIO              2260
-#define MACH_TYPE_OMAP3_PHRAZER        2261
-#define MACH_TYPE_DARWIN               2262
-#define MACH_TYPE_ORATISCOMU           2263
-#define MACH_TYPE_RTSBC20              2264
-#define MACH_TYPE_I780                 2265
-#define MACH_TYPE_GEMINI324            2266
-#define MACH_TYPE_ORATISLAN            2267
-#define MACH_TYPE_ORATISALOG           2268
-#define MACH_TYPE_ORATISMADI           2269
-#define MACH_TYPE_ORATISOT16           2270
-#define MACH_TYPE_ORATISDESK           2271
-#define MACH_TYPE_VEXPRESS             2272
-#define MACH_TYPE_SINTEXO              2273
-#define MACH_TYPE_CM3389               2274
-#define MACH_TYPE_OMAP3_CIO            2275
-#define MACH_TYPE_SGH_I900             2276
-#define MACH_TYPE_BST100               2277
-#define MACH_TYPE_PASSION              2278
-#define MACH_TYPE_INDESIGN_AT91SAM     2279
-#define MACH_TYPE_C4_BADGER            2280
-#define MACH_TYPE_C4_VIPER             2281
-#define MACH_TYPE_D2NET                2282
-#define MACH_TYPE_BIGDISK              2283
-#define MACH_TYPE_NOTALVISION          2284
-#define MACH_TYPE_OMAP3_KBOC           2285
-#define MACH_TYPE_CYCLONE              2286
-#define MACH_TYPE_NINJA                2287
-#define MACH_TYPE_AT91SAM9G20EK_2MMC   2288
-#define MACH_TYPE_BCMRING              2289
-#define MACH_TYPE_RESOL_DL2            2290
-#define MACH_TYPE_IFOSW                2291
-#define MACH_TYPE_HTCRHODIUM           2292
-#define MACH_TYPE_HTCTOPAZ             2293
-#define MACH_TYPE_MATRIX504            2294
-#define MACH_TYPE_MRFSA                2295
-#define MACH_TYPE_SC_P270              2296
-#define MACH_TYPE_ATLAS5_EVB           2297
-#define MACH_TYPE_PELCO_LOBOX          2298
-#define MACH_TYPE_DILAX_PCU200         2299
-#define MACH_TYPE_LEONARDO             2300
-#define MACH_TYPE_ZORAN_APPROACH7      2301
-#define MACH_TYPE_DP6XX                2302
-#define MACH_TYPE_BCM2153_VESPER       2303
-#define MACH_TYPE_MAHIMAHI             2304
-#define MACH_TYPE_CLICKC               2305
-#define MACH_TYPE_ZB_GATEWAY           2306
-#define MACH_TYPE_TAZCARD              2307
-#define MACH_TYPE_TAZDEV               2308
-#define MACH_TYPE_ANNAX_CB_ARM         2309
-#define MACH_TYPE_ANNAX_DM3            2310
-#define MACH_TYPE_CEREBRIC             2311
-#define MACH_TYPE_ORCA                 2312
-#define MACH_TYPE_PC9260               2313
-#define MACH_TYPE_EMS285A              2314
-#define MACH_TYPE_GEC2410              2315
-#define MACH_TYPE_GEC2440              2316
-#define MACH_TYPE_ARCH_MW903           2317
-#define MACH_TYPE_MW2440               2318
-#define MACH_TYPE_ECAC2378             2319
-#define MACH_TYPE_TAZKIOSK             2320
-#define MACH_TYPE_WHITERABBIT_MCH      2321
-#define MACH_TYPE_SBOX9263             2322
-#define MACH_TYPE_OREO                 2323
-#define MACH_TYPE_SMDK6442             2324
-#define MACH_TYPE_OPENRD_BASE          2325
-#define MACH_TYPE_INCREDIBLE           2326
-#define MACH_TYPE_INCREDIBLEC          2327
-#define MACH_TYPE_HEROCT               2328
-#define MACH_TYPE_MMNET1000            2329
-#define MACH_TYPE_DEVKIT8000           2330
-#define MACH_TYPE_DEVKIT9000           2331
-#define MACH_TYPE_MX31TXTR             2332
-#define MACH_TYPE_U380                 2333
-#define MACH_TYPE_HUALU_BOARD          2334
-#define MACH_TYPE_NPCMX50              2335
-#define MACH_TYPE_MX51_EFIKAMX         2336
-#define MACH_TYPE_MX51_LANGE52         2337
-#define MACH_TYPE_RIOM                 2338
-#define MACH_TYPE_COMCAS               2339
-#define MACH_TYPE_WSI_MX27             2340
-#define MACH_TYPE_CM_T35               2341
-#define MACH_TYPE_NET2BIG              2342
-#define MACH_TYPE_MOTOROLA_A1600       2343
-#define MACH_TYPE_IGEP0020             2344
-#define MACH_TYPE_IGEP0010             2345
-#define MACH_TYPE_MV6281GTWGE2         2346
-#define MACH_TYPE_SCAT100              2347
-#define MACH_TYPE_SANMINA              2348
-#define MACH_TYPE_MOMENTO              2349
-#define MACH_TYPE_NUC9XX               2350
-#define MACH_TYPE_NUC910EVB            2351
-#define MACH_TYPE_NUC920EVB            2352
-#define MACH_TYPE_NUC950EVB            2353
-#define MACH_TYPE_NUC945EVB            2354
-#define MACH_TYPE_NUC960EVB            2355
-#define MACH_TYPE_NUC932EVB            2356
-#define MACH_TYPE_NUC900               2357
-#define MACH_TYPE_SD1SOC               2358
-#define MACH_TYPE_LN2440BC             2359
-#define MACH_TYPE_RSBC                 2360
-#define MACH_TYPE_OPENRD_CLIENT        2361
-#define MACH_TYPE_HPIPAQ11X            2362
-#define MACH_TYPE_WAYLAND              2363
-#define MACH_TYPE_ACNBSX102            2364
-#define MACH_TYPE_HWAT91               2365
-#define MACH_TYPE_AT91SAM9263CS        2366
-#define MACH_TYPE_CSB732               2367
-#define MACH_TYPE_U8500                2368
-#define MACH_TYPE_HUQIU                2369
-#define MACH_TYPE_MX51_EFIKASB         2370
-#define MACH_TYPE_PMT1G                2371
-#define MACH_TYPE_HTCELF               2372
-#define MACH_TYPE_ARMADILLO420         2373
-#define MACH_TYPE_ARMADILLO440         2374
-#define MACH_TYPE_U_CHIP_DUAL_ARM      2375
-#define MACH_TYPE_CSR_BDB3             2376
-#define MACH_TYPE_DOLBY_CAT1018        2377
-#define MACH_TYPE_HY9307               2378
-#define MACH_TYPE_A_ES                 2379
-#define MACH_TYPE_DAVINCI_IRIF         2380
-#define MACH_TYPE_AGAMA9263            2381
-#define MACH_TYPE_MARVELL_JASPER       2382
-#define MACH_TYPE_FLINT                2383
-#define MACH_TYPE_TAVOREVB3            2384
-#define MACH_TYPE_SCH_M490             2386
-#define MACH_TYPE_RBL01                2387
-#define MACH_TYPE_OMNIFI               2388
-#define MACH_TYPE_OTAVALO              2389
-#define MACH_TYPE_SIENNA               2390
-#define MACH_TYPE_HTC_EXCALIBUR_S620   2391
-#define MACH_TYPE_HTC_OPAL             2392
-#define MACH_TYPE_TOUCHBOOK            2393
-#define MACH_TYPE_LATTE                2394
-#define MACH_TYPE_XA200                2395
-#define MACH_TYPE_NIMROD               2396
-#define MACH_TYPE_CC9P9215_3G          2397
-#define MACH_TYPE_CC9P9215_3GJS        2398
-#define MACH_TYPE_TK71                 2399
-#define MACH_TYPE_COMHAM3525           2400
-#define MACH_TYPE_MX31EREBUS           2401
-#define MACH_TYPE_MCARDMX27            2402
-#define MACH_TYPE_PARADISE             2403
-#define MACH_TYPE_TIDE                 2404
-#define MACH_TYPE_WZL2440              2405
-#define MACH_TYPE_SDRDEMO              2406
-#define MACH_TYPE_ETHERCAN2            2407
-#define MACH_TYPE_ECMIMG20             2408
-#define MACH_TYPE_OMAP_DRAGON          2409
-#define MACH_TYPE_HALO                 2410
-#define MACH_TYPE_HUANGSHAN            2411
-#define MACH_TYPE_VL_MA2SC             2412
-#define MACH_TYPE_RAUMFELD_RC          2413
-#define MACH_TYPE_RAUMFELD_CONNECTOR   2414
-#define MACH_TYPE_RAUMFELD_SPEAKER     2415
-#define MACH_TYPE_MULTIBUS_MASTER      2416
-#define MACH_TYPE_MULTIBUS_PBK         2417
-#define MACH_TYPE_TNETV107X            2418
-#define MACH_TYPE_SNAKE                2419
-#define MACH_TYPE_CWMX27               2420
-#define MACH_TYPE_SCH_M480             2421
-#define MACH_TYPE_PLATYPUS             2422
-#define MACH_TYPE_PSS2                 2423
-#define MACH_TYPE_DAVINCI_APM150       2424
-#define MACH_TYPE_STR9100              2425
-#define MACH_TYPE_NET5BIG              2426
-#define MACH_TYPE_SEABED9263           2427
-#define MACH_TYPE_MX51_M2ID            2428
-#define MACH_TYPE_OCTVOCPLUS_EB        2429
-#define MACH_TYPE_KLK_FIREFOX          2430
-#define MACH_TYPE_KLK_WIRMA_MODULE     2431
-#define MACH_TYPE_KLK_WIRMA_MMI        2432
-#define MACH_TYPE_SUPERSONIC           2433
-#define MACH_TYPE_LIBERTY              2434
-#define MACH_TYPE_MH355                2435
-#define MACH_TYPE_PC7802               2436
-#define MACH_TYPE_GNET_SGC             2437
-#define MACH_TYPE_EINSTEIN15           2438
-#define MACH_TYPE_CMPD                 2439
-#define MACH_TYPE_DAVINCI_HASE1        2440
-#define MACH_TYPE_LGEINCITEPHONE       2441
-#define MACH_TYPE_EA313X               2442
-#define MACH_TYPE_FWBD_39064           2443
-#define MACH_TYPE_FWBD_390128          2444
-#define MACH_TYPE_PELCO_MOE            2445
-#define MACH_TYPE_MINIMIX27            2446
-#define MACH_TYPE_OMAP3_THUNDER        2447
-#define MACH_TYPE_PASSIONC             2448
-#define MACH_TYPE_MX27AMATA            2449
-#define MACH_TYPE_BGAT1                2450
-#define MACH_TYPE_BUZZ                 2451
-#define MACH_TYPE_MB9G20               2452
-#define MACH_TYPE_YUSHAN               2453
-#define MACH_TYPE_LIZARD               2454
-#define MACH_TYPE_OMAP3POLYCOM         2455
-#define MACH_TYPE_SMDKV210             2456
-#define MACH_TYPE_BRAVO                2457
-#define MACH_TYPE_SIOGENTOO1           2458
-#define MACH_TYPE_SIOGENTOO2           2459
-#define MACH_TYPE_SM3K                 2460
-#define MACH_TYPE_ACER_TEMPO_F900      2461
-#define MACH_TYPE_SST61VC010_DEV       2462
-#define MACH_TYPE_GLITTERTIND          2463
-#define MACH_TYPE_OMAP_ZOOM3           2464
-#define MACH_TYPE_OMAP_3630SDP         2465
-#define MACH_TYPE_CYBOOK2440           2466
-#define MACH_TYPE_TORINO_S             2467
-#define MACH_TYPE_HAVANA               2468
-#define MACH_TYPE_BEAUMONT_11          2469
-#define MACH_TYPE_VANGUARD             2470
-#define MACH_TYPE_S5PC110_DRACO        2471
-#define MACH_TYPE_CARTESIO_TWO         2472
-#define MACH_TYPE_ASTER                2473
-#define MACH_TYPE_VOGUESV210           2474
-#define MACH_TYPE_ACM500X              2475
-#define MACH_TYPE_KM9260               2476
-#define MACH_TYPE_NIDEFLEXG1           2477
-#define MACH_TYPE_CTERA_PLUG_IO        2478
-#define MACH_TYPE_SMARTQ7              2479
-#define MACH_TYPE_AT91SAM9G10EK2       2480
-#define MACH_TYPE_ASUSP527             2481
-#define MACH_TYPE_AT91SAM9G20MPM2      2482
-#define MACH_TYPE_TOPASA900            2483
-#define MACH_TYPE_ELECTRUM_100         2484
-#define MACH_TYPE_MX51GRB              2485
-#define MACH_TYPE_XEA300               2486
-#define MACH_TYPE_HTCSTARTREK          2487
-#define MACH_TYPE_LIMA                 2488
-#define MACH_TYPE_CSB740               2489
-#define MACH_TYPE_USB_S8815            2490
-#define MACH_TYPE_WATSON_EFM_PLUGIN    2491
-#define MACH_TYPE_MILKYWAY             2492
-#define MACH_TYPE_G4EVM                2493
-#define MACH_TYPE_PICOMOD6             2494
-#define MACH_TYPE_OMAPL138_HAWKBOARD   2495
-#define MACH_TYPE_IP6000               2496
-#define MACH_TYPE_IP6010               2497
-#define MACH_TYPE_UTM400               2498
-#define MACH_TYPE_OMAP3_ZYBEX          2499
-#define MACH_TYPE_WIRELESS_SPACE       2500
-#define MACH_TYPE_SX560                2501
-#define MACH_TYPE_TS41X                2502
-#define MACH_TYPE_ELPHEL10373          2503
-#define MACH_TYPE_RHOBOT               2504
-#define MACH_TYPE_MX51_REFRESH         2505
-#define MACH_TYPE_LS9260               2506
-#define MACH_TYPE_SHANK                2507
-#define MACH_TYPE_QSD8X50_ST1          2508
-#define MACH_TYPE_AT91SAM9M10EKES      2509
-#define MACH_TYPE_HIRAM                2510
-#define MACH_TYPE_PHY3250              2511
-#define MACH_TYPE_EA3250               2512
-#define MACH_TYPE_FDI3250              2513
-#define MACH_TYPE_WHITESTONE           2514
-#define MACH_TYPE_AT91SAM9263NIT       2515
-#define MACH_TYPE_CCMX51               2516
-#define MACH_TYPE_CCMX51JS             2517
-#define MACH_TYPE_CCWMX51              2518
-#define MACH_TYPE_CCWMX51JS            2519
-#define MACH_TYPE_MINI6410             2520
-#define MACH_TYPE_TINY6410             2521
-#define MACH_TYPE_NANO6410             2522
-#define MACH_TYPE_AT572D940HFNLDB      2523
-#define MACH_TYPE_HTCLEO               2524
-#define MACH_TYPE_AVP13                2525
-#define MACH_TYPE_XXSVIDEOD            2526
-#define MACH_TYPE_VPNEXT               2527
-#define MACH_TYPE_SWARCO_ITC3          2528
-#define MACH_TYPE_TX51                 2529
-#define MACH_TYPE_DOLBY_CAT1021        2530
-#define MACH_TYPE_MX28EVK              2531
-#define MACH_TYPE_PHOENIX260           2532
-#define MACH_TYPE_UVACA_STORK          2533
-#define MACH_TYPE_SMARTQ5              2534
-#define MACH_TYPE_ALL3078              2535
-#define MACH_TYPE_CTERA_2BAY_DS        2536
-#define MACH_TYPE_SIOGENTOO3           2537
-#define MACH_TYPE_EPB5000              2538
-#define MACH_TYPE_HY9263               2539
-#define MACH_TYPE_ACER_TEMPO_M900      2540
-#define MACH_TYPE_ACER_TEMPO_DX900     2541
-#define MACH_TYPE_ACER_TEMPO_X960      2542
-#define MACH_TYPE_ACER_ETEN_V900       2543
-#define MACH_TYPE_ACER_ETEN_X900       2544
-#define MACH_TYPE_BONNELL              2545
-#define MACH_TYPE_OHT_MX27             2546
-#define MACH_TYPE_HTCQUARTZ            2547
-#define MACH_TYPE_DAVINCI_DM6467TEVM   2548
-#define MACH_TYPE_C3AX03               2549
-#define MACH_TYPE_MXT_TD60             2550
-#define MACH_TYPE_ESYX                 2551
-#define MACH_TYPE_DOVE_DB2             2552
-#define MACH_TYPE_BULLDOG              2553
-#define MACH_TYPE_DERELL_ME2000        2554
-#define MACH_TYPE_BCMRING_BASE         2555
-#define MACH_TYPE_BCMRING_EVM          2556
-#define MACH_TYPE_BCMRING_EVM_JAZZ     2557
-#define MACH_TYPE_BCMRING_SP           2558
-#define MACH_TYPE_BCMRING_SV           2559
-#define MACH_TYPE_BCMRING_SV_JAZZ      2560
-#define MACH_TYPE_BCMRING_TABLET       2561
-#define MACH_TYPE_BCMRING_VP           2562
-#define MACH_TYPE_BCMRING_EVM_SEIKOR   2563
-#define MACH_TYPE_BCMRING_SP_WQVGA     2564
-#define MACH_TYPE_BCMRING_CUSTOM       2565
-#define MACH_TYPE_ACER_S200            2566
-#define MACH_TYPE_BT270                2567
-#define MACH_TYPE_ISEO                 2568
-#define MACH_TYPE_CEZANNE              2569
-#define MACH_TYPE_LUCCA                2570
-#define MACH_TYPE_SUPERSMART           2571
-#define MACH_TYPE_CS_MISANO            2572
-#define MACH_TYPE_MAGNOLIA2            2573
-#define MACH_TYPE_EMXX                 2574
-#define MACH_TYPE_OUTLAW               2575
-#define MACH_TYPE_RIOT_BEI2            2576
-#define MACH_TYPE_RIOT_VOX             2577
-#define MACH_TYPE_RIOT_X37             2578
-#define MACH_TYPE_MEGA25MX             2579
-#define MACH_TYPE_BENZINA2             2580
-#define MACH_TYPE_IGNITE               2581
-#define MACH_TYPE_FOGGIA               2582
-#define MACH_TYPE_AREZZO               2583
-#define MACH_TYPE_LEICA_SKYWALKER      2584
-#define MACH_TYPE_JACINTO2_JAMR        2585
-#define MACH_TYPE_GTS_NOVA             2586
-#define MACH_TYPE_P3600                2587
-#define MACH_TYPE_DLT2                 2588
-#define MACH_TYPE_DF3120               2589
-#define MACH_TYPE_ECUCORE_9G20         2590
-#define MACH_TYPE_NAUTEL_LPC3240       2591
-#define MACH_TYPE_GLACIER              2592
-#define MACH_TYPE_PHRAZER_BULLDOG      2593
-#define MACH_TYPE_OMAP3_BULLDOG        2594
-#define MACH_TYPE_PCA101               2595
-#define MACH_TYPE_BUZZC                2596
-#define MACH_TYPE_SASIE2               2597
-#define MACH_TYPE_DAVINCI_CIO          2598
-#define MACH_TYPE_SMARTMETER_DL        2599
-#define MACH_TYPE_WZL6410              2600
-#define MACH_TYPE_WZL6410M             2601
-#define MACH_TYPE_WZL6410F             2602
-#define MACH_TYPE_WZL6410I             2603
-#define MACH_TYPE_SPACECOM1            2604
-#define MACH_TYPE_PINGU920             2605
-#define MACH_TYPE_BRAVOC               2606
-#define MACH_TYPE_CYBO2440             2607
-#define MACH_TYPE_VDSSW                2608
-#define MACH_TYPE_ROMULUS              2609
-#define MACH_TYPE_OMAP_MAGIC           2610
-#define MACH_TYPE_ELTD100              2611
-#define MACH_TYPE_CAPC7117             2612
-#define MACH_TYPE_SWAN                 2613
-#define MACH_TYPE_VEU                  2614
-#define MACH_TYPE_RM2                  2615
-#define MACH_TYPE_TT2100               2616
-#define MACH_TYPE_VENICE               2617
-#define MACH_TYPE_PC7323               2618
-#define MACH_TYPE_MASP                 2619
-#define MACH_TYPE_FUJITSU_TVSTBSOC     2620
-#define MACH_TYPE_FUJITSU_TVSTBSOC1    2621
-#define MACH_TYPE_LEXIKON              2622
-#define MACH_TYPE_MINI2440V2           2623
-#define MACH_TYPE_ICONTROL             2624
-#define MACH_TYPE_SHEEVAD              2625
-#define MACH_TYPE_QSD8X50A_ST1_1       2626
-#define MACH_TYPE_QSD8X50A_ST1_5       2627
-#define MACH_TYPE_BEE                  2628
-#define MACH_TYPE_MX23EVK              2629
-#define MACH_TYPE_AP4EVB               2630
-#define MACH_TYPE_STOCKHOLM            2631
-#define MACH_TYPE_LPC_H3131            2632
-#define MACH_TYPE_STINGRAY             2633
-#define MACH_TYPE_KRAKEN               2634
-#define MACH_TYPE_GW2388               2635
-#define MACH_TYPE_JADECPU              2636
-#define MACH_TYPE_CARLISLE             2637
-#define MACH_TYPE_LUX_SF9              2638
-#define MACH_TYPE_NEMID_TB             2639
-#define MACH_TYPE_TERRIER              2640
-#define MACH_TYPE_TURBOT               2641
-#define MACH_TYPE_SANDDAB              2642
-#define MACH_TYPE_MX35_CICADA          2643
-#define MACH_TYPE_GHI2703D             2644
-#define MACH_TYPE_LUX_SFX9             2645
-#define MACH_TYPE_LUX_SF9G             2646
-#define MACH_TYPE_LUX_EDK9             2647
-#define MACH_TYPE_HW90240              2648
-#define MACH_TYPE_DM365_LEOPARD        2649
-#define MACH_TYPE_MITYOMAPL138         2650
-#define MACH_TYPE_SCAT110              2651
-#define MACH_TYPE_ACER_A1              2652
-#define MACH_TYPE_CMCONTROL            2653
-#define MACH_TYPE_PELCO_LAMAR          2654
-#define MACH_TYPE_RFP43                2655
-#define MACH_TYPE_SK86R0301            2656
-#define MACH_TYPE_CTPXA                2657
-#define MACH_TYPE_EPB_ARM9_A           2658
-#define MACH_TYPE_GURUPLUG             2659
-#define MACH_TYPE_SPEAR310             2660
-#define MACH_TYPE_SPEAR320             2661
-#define MACH_TYPE_ROBOTX               2662
-#define MACH_TYPE_LSXHL                2663
-#define MACH_TYPE_SMARTLITE            2664
-#define MACH_TYPE_CWS2                 2665
-#define MACH_TYPE_M619                 2666
-#define MACH_TYPE_SMARTVIEW            2667
-#define MACH_TYPE_LSA_SALSA            2668
-#define MACH_TYPE_KIZBOX               2669
-#define MACH_TYPE_HTCCHARMER           2670
-#define MACH_TYPE_GUF_NESO_LT          2671
-#define MACH_TYPE_PM9G45               2672
-#define MACH_TYPE_HTCPANTHER           2673
-#define MACH_TYPE_HTCPANTHER_CDMA      2674
-#define MACH_TYPE_REB01                2675
-#define MACH_TYPE_AQUILA               2676
-#define MACH_TYPE_SPARK_SLS_HW2        2677
-#define MACH_TYPE_ESATA_SHEEVAPLUG     2678
-#define MACH_TYPE_MSM7X30_SURF         2679
-#define MACH_TYPE_MICRO2440            2680
-#define MACH_TYPE_AM2440               2681
-#define MACH_TYPE_TQ2440               2682
-#define MACH_TYPE_LPC2478OEM           2683
-#define MACH_TYPE_AK880X               2684
-#define MACH_TYPE_COBRA3530            2685
-#define MACH_TYPE_PMPPB                2686
-#define MACH_TYPE_U6715                2687
-#define MACH_TYPE_AXAR1500_SENDER      2688
-#define MACH_TYPE_G30_DVB              2689
-#define MACH_TYPE_VC088X               2690
-#define MACH_TYPE_MIOA702              2691
-#define MACH_TYPE_HPMIN                2692
-#define MACH_TYPE_AK880XAK             2693
-#define MACH_TYPE_ARM926TOMAP850       2694
-#define MACH_TYPE_LKEVM                2695
-#define MACH_TYPE_MW6410               2696
-#define MACH_TYPE_TERASTATION_WXL      2697
-#define MACH_TYPE_CPU8000E             2698
-#define MACH_TYPE_CATANIA              2699
-#define MACH_TYPE_TOKYO                2700
-#define MACH_TYPE_MSM7201A_SURF        2701
-#define MACH_TYPE_MSM7201A_FFA         2702
-#define MACH_TYPE_MSM7X25_SURF         2703
-#define MACH_TYPE_MSM7X25_FFA          2704
-#define MACH_TYPE_MSM7X27_SURF         2705
-#define MACH_TYPE_MSM7X27_FFA          2706
-#define MACH_TYPE_MSM7X30_FFA          2707
-#define MACH_TYPE_QSD8X50_SURF         2708
-#define MACH_TYPE_QSD8X50_COMET        2709
-#define MACH_TYPE_QSD8X50_FFA          2710
-#define MACH_TYPE_QSD8X50A_SURF        2711
-#define MACH_TYPE_QSD8X50A_FFA         2712
-#define MACH_TYPE_ADX_XGCP10           2713
-#define MACH_TYPE_MCGWUMTS2A           2714
-#define MACH_TYPE_MOBIKT               2715
-#define MACH_TYPE_MX53_EVK             2716
-#define MACH_TYPE_IGEP0030             2717
-#define MACH_TYPE_AXELL_H40_H50_CTRL   2718
-#define MACH_TYPE_DTCOMMOD             2719
-#define MACH_TYPE_GOULD                2720
-#define MACH_TYPE_SIBERIA              2721
-#define MACH_TYPE_SBC3530              2722
-#define MACH_TYPE_QARM                 2723
-#define MACH_TYPE_MIPS                 2724
-#define MACH_TYPE_MX27GRB              2725
-#define MACH_TYPE_SBC8100              2726
-#define MACH_TYPE_SAARB                2727
-#define MACH_TYPE_OMAP3MINI            2728
-#define MACH_TYPE_CNMBOOK7SE           2729
-#define MACH_TYPE_CATAN                2730
-#define MACH_TYPE_HARMONY              2731
-#define MACH_TYPE_TONGA                2732
-#define MACH_TYPE_CYBOOK_ORIZON        2733
-#define MACH_TYPE_HTCRHODIUMCDMA       2734
-#define MACH_TYPE_EPC_G45              2735
-#define MACH_TYPE_EPC_LPC3250          2736
-#define MACH_TYPE_MXC91341EVB          2737
-#define MACH_TYPE_RTW1000              2738
-#define MACH_TYPE_BOBCAT               2739
-#define MACH_TYPE_TRIZEPS6             2740
-#define MACH_TYPE_MSM7X30_FLUID        2741
-#define MACH_TYPE_NEDAP9263            2742
-#define MACH_TYPE_NETGEAR_MS2110       2743
-#define MACH_TYPE_BMX                  2744
-#define MACH_TYPE_NETSTREAM            2745
-#define MACH_TYPE_VPNEXT_RCU           2746
-#define MACH_TYPE_VPNEXT_MPU           2747
-#define MACH_TYPE_BCMRING_TABLET_V1    2748
-#define MACH_TYPE_SGARM10              2749
-#define MACH_TYPE_CM_T3517             2750
-#define MACH_TYPE_OMAP3_CPS            2751
-#define MACH_TYPE_AXAR1500_RECEIVER    2752
-#define MACH_TYPE_WBD222               2753
-#define MACH_TYPE_MT65XX               2754
-#define MACH_TYPE_MSM8X60_SURF         2755
-#define MACH_TYPE_MSM8X60_SIM          2756
-#define MACH_TYPE_VMC300               2757
-#define MACH_TYPE_TCC8000_SDK          2758
-#define MACH_TYPE_NANOS                2759
-#define MACH_TYPE_STAMP9G10            2760
-#define MACH_TYPE_STAMP9G45            2761
-#define MACH_TYPE_H6053                2762
-#define MACH_TYPE_SMINT01              2763
-#define MACH_TYPE_PRTLVT2              2764
-#define MACH_TYPE_AP420                2765
-#define MACH_TYPE_HTCSHIFT             2766
-#define MACH_TYPE_DAVINCI_DM365_FC     2767
-#define MACH_TYPE_MSM8X55_SURF         2768
-#define MACH_TYPE_MSM8X55_FFA          2769
-#define MACH_TYPE_ESL_VAMANA           2770
-#define MACH_TYPE_SBC35                2771
-#define MACH_TYPE_MPX6446              2772
-#define MACH_TYPE_OREO_CONTROLLER      2773
-#define MACH_TYPE_KOPIN_MODELS         2774
-#define MACH_TYPE_TTC_VISION2          2775
-#define MACH_TYPE_CNS3420VB            2776
-#define MACH_TYPE_LPC2                 2777
-#define MACH_TYPE_OLYMPUS              2778
-#define MACH_TYPE_VORTEX               2779
-#define MACH_TYPE_S5PC200              2780
-#define MACH_TYPE_ECUCORE_9263         2781
-#define MACH_TYPE_SMDKC200             2782
-#define MACH_TYPE_EMSISO_SX27          2783
-#define MACH_TYPE_APX_SOM9G45_EK       2784
-#define MACH_TYPE_SONGSHAN             2785
-#define MACH_TYPE_TIANSHAN             2786
-#define MACH_TYPE_VPX500               2787
-#define MACH_TYPE_AM3517SAM            2788
-#define MACH_TYPE_SKAT91_SIM508        2789
-#define MACH_TYPE_SKAT91_S3E           2790
-#define MACH_TYPE_OMAP4_PANDA          2791
-#define MACH_TYPE_DF7220               2792
-#define MACH_TYPE_NEMINI               2793
-#define MACH_TYPE_T8200                2794
-#define MACH_TYPE_APF51                2795
-#define MACH_TYPE_DR_RC_UNIT           2796
-#define MACH_TYPE_BORDEAUX             2797
-#define MACH_TYPE_CATANIA_B            2798
-#define MACH_TYPE_MX51_OCEAN           2799
-#define MACH_TYPE_TI8168EVM            2800
-#define MACH_TYPE_NEOCOREOMAP          2801
-#define MACH_TYPE_WITHINGS_WBP         2802
-#define MACH_TYPE_DBPS                 2803
-#define MACH_TYPE_SBC9261              2804
-#define MACH_TYPE_PCBFP0001            2805
-#define MACH_TYPE_SPEEDY               2806
-#define MACH_TYPE_CHRYSAOR             2807
-#define MACH_TYPE_TANGO                2808
-#define MACH_TYPE_SYNOLOGY_DSX11       2809
-#define MACH_TYPE_HANLIN_V3EXT         2810
-#define MACH_TYPE_HANLIN_V5            2811
-#define MACH_TYPE_HANLIN_V3PLUS        2812
-#define MACH_TYPE_IRIVER_STORY         2813
-#define MACH_TYPE_IREX_ILIAD           2814
-#define MACH_TYPE_IREX_DR1000          2815
-#define MACH_TYPE_TETON_BGA            2816
-#define MACH_TYPE_SNAPPER9G45          2817
-#define MACH_TYPE_TAM3517              2818
-#define MACH_TYPE_PDC100               2819
-#define MACH_TYPE_EUKREA_CPUIMX25      2820
-#define MACH_TYPE_EUKREA_CPUIMX35      2821
-#define MACH_TYPE_EUKREA_CPUIMX51SD    2822
-#define MACH_TYPE_EUKREA_CPUIMX51      2823
-#define MACH_TYPE_P565                 2824
-#define MACH_TYPE_ACER_A4              2825
-#define MACH_TYPE_DAVINCI_DM368_BIP    2826
-#define MACH_TYPE_ESHARE               2827
-#define MACH_TYPE_HW_OMAPL138_EUROPA   2828
-#define MACH_TYPE_WLBARGN              2829
-#define MACH_TYPE_BM170                2830
-#define MACH_TYPE_NETSPACE_MINI_V2     2831
-#define MACH_TYPE_NETSPACE_PLUG_V2     2832
-#define MACH_TYPE_SIEMENS_L1           2833
-#define MACH_TYPE_ELV_LCU1             2834
-#define MACH_TYPE_MCU1                 2835
-#define MACH_TYPE_OMAP3_TAO3530        2836
-#define MACH_TYPE_OMAP3_PCUTOUCH       2837
-#define MACH_TYPE_SMDKC210             2838
-#define MACH_TYPE_OMAP3_BRAILLO        2839
-#define MACH_TYPE_SPYPLUG              2840
-#define MACH_TYPE_GINGER               2841
-#define MACH_TYPE_TNY_T3530            2842
-#define MACH_TYPE_PCA102               2843
-#define MACH_TYPE_SPADE                2844
-#define MACH_TYPE_MXC25_TOPAZ          2845
-#define MACH_TYPE_T5325                2846
-#define MACH_TYPE_GW2361               2847
-#define MACH_TYPE_ELOG                 2848
-#define MACH_TYPE_INCOME               2849
-#define MACH_TYPE_BCM589X              2850
-#define MACH_TYPE_ETNA                 2851
-#define MACH_TYPE_HAWKS                2852
-#define MACH_TYPE_MESON                2853
-#define MACH_TYPE_XSBASE255            2854
-#define MACH_TYPE_PVM2030              2855
-#define MACH_TYPE_MIOA502              2856
-#define MACH_TYPE_VVBOX_SDORIG2        2857
-#define MACH_TYPE_VVBOX_SDLITE2        2858
-#define MACH_TYPE_VVBOX_SDPRO4         2859
-#define MACH_TYPE_HTC_SPV_M700         2860
-#define MACH_TYPE_MX257SX              2861
-#define MACH_TYPE_GONI                 2862
-#define MACH_TYPE_MSM8X55_SVLTE_FFA    2863
-#define MACH_TYPE_MSM8X55_SVLTE_SURF   2864
-#define MACH_TYPE_QUICKSTEP            2865
-#define MACH_TYPE_DMW96                2866
-#define MACH_TYPE_HAMMERHEAD           2867
-#define MACH_TYPE_TRIDENT              2868
-#define MACH_TYPE_LIGHTNING            2869
-#define MACH_TYPE_ICONNECT             2870
-#define MACH_TYPE_AUTOBOT              2871
-#define MACH_TYPE_COCONUT              2872
-#define MACH_TYPE_DURIAN               2873
-#define MACH_TYPE_CAYENNE              2874
-#define MACH_TYPE_FUJI                 2875
-#define MACH_TYPE_SYNOLOGY_6282        2876
-#define MACH_TYPE_EM1SY                2877
-#define MACH_TYPE_M502                 2878
-#define MACH_TYPE_MATRIX518            2879
-#define MACH_TYPE_TINY_GURNARD         2880
-#define MACH_TYPE_SPEAR1310            2881
-#define MACH_TYPE_BV07                 2882
-#define MACH_TYPE_MXT_TD61             2883
-#define MACH_TYPE_OPENRD_ULTIMATE      2884
-#define MACH_TYPE_DEVIXP               2885
-#define MACH_TYPE_MICCPT               2886
-#define MACH_TYPE_MIC256               2887
-#define MACH_TYPE_AS1167               2888
-#define MACH_TYPE_OMAP3_IBIZA          2889
-#define MACH_TYPE_U5500                2890
-#define MACH_TYPE_DAVINCI_PICTO        2891
-#define MACH_TYPE_MECHA                2892
-#define MACH_TYPE_BUBBA3               2893
-#define MACH_TYPE_PUPITRE              2894
-#define MACH_TYPE_TEGRA_HARMONY        2895
-#define MACH_TYPE_TEGRA_VOGUE          2896
-#define MACH_TYPE_TEGRA_E1165          2897
-#define MACH_TYPE_SIMPLENET            2898
-#define MACH_TYPE_EC4350TBM            2899
-#define MACH_TYPE_PEC_TC               2900
-#define MACH_TYPE_PEC_HC2              2901
-#define MACH_TYPE_ESL_MOBILIS_A        2902
-#define MACH_TYPE_ESL_MOBILIS_B        2903
-#define MACH_TYPE_ESL_WAVE_A           2904
-#define MACH_TYPE_ESL_WAVE_B           2905
-#define MACH_TYPE_UNISENSE_MMM         2906
-#define MACH_TYPE_BLUESHARK            2907
-#define MACH_TYPE_E10                  2908
-#define MACH_TYPE_APP3K_ROBIN          2909
-#define MACH_TYPE_POV15HD              2910
-#define MACH_TYPE_STELLA               2911
-#define MACH_TYPE_LINKSTATION_LSCHL    2913
-#define MACH_TYPE_NETWALKER            2914
-#define MACH_TYPE_ACSX106              2915
-#define MACH_TYPE_ATLAS5_C1            2916
-#define MACH_TYPE_NSB3AST              2917
-#define MACH_TYPE_GNET_SLC             2918
-#define MACH_TYPE_AF4000               2919
-#define MACH_TYPE_ARK9431              2920
-#define MACH_TYPE_FS_S5PC100           2921
-#define MACH_TYPE_OMAP3505NOVA8        2922
-#define MACH_TYPE_OMAP3621_EDP1        2923
-#define MACH_TYPE_ORATISAES            2924
-#define MACH_TYPE_SMDKV310             2925
-#define MACH_TYPE_SIEMENS_L0           2926
-#define MACH_TYPE_VENTANA              2927
-#define MACH_TYPE_WM8505_7IN_NETBOOK   2928
-#define MACH_TYPE_EC4350SDB            2929
-#define MACH_TYPE_MIMAS                2930
-#define MACH_TYPE_TITAN                2931
-#define MACH_TYPE_CRANEBOARD           2932
-#define MACH_TYPE_ES2440               2933
-#define MACH_TYPE_NAJAY_A9263          2934
-#define MACH_TYPE_HTCTORNADO           2935
-#define MACH_TYPE_DIMM_MX257           2936
-#define MACH_TYPE_JIGEN                2937
-#define MACH_TYPE_SMDK6450             2938
-#define MACH_TYPE_MENO_QNG             2939
-#define MACH_TYPE_NS2416               2940
-#define MACH_TYPE_RPC353               2941
-#define MACH_TYPE_TQ6410               2942
-#define MACH_TYPE_SKY6410              2943
-#define MACH_TYPE_DYNASTY              2944
-#define MACH_TYPE_VIVO                 2945
-#define MACH_TYPE_BURY_BL7582          2946
-#define MACH_TYPE_BURY_BPS5270         2947
-#define MACH_TYPE_BASI                 2948
-#define MACH_TYPE_TN200                2949
-#define MACH_TYPE_C2MMI                2950
-#define MACH_TYPE_MESON_6236M          2951
-#define MACH_TYPE_MESON_8626M          2952
-#define MACH_TYPE_TUBE                 2953
-#define MACH_TYPE_MESSINA              2954
-#define MACH_TYPE_MX50_ARM2            2955
-#define MACH_TYPE_CETUS9263            2956
-#define MACH_TYPE_BROWNSTONE           2957
-#define MACH_TYPE_VMX25                2958
-#define MACH_TYPE_VMX51                2959
-#define MACH_TYPE_ABACUS               2960
-#define MACH_TYPE_CM4745               2961
-#define MACH_TYPE_ORATISLINK           2962
-#define MACH_TYPE_DAVINCI_DM365_DVR    2963
-#define MACH_TYPE_NETVIZ               2964
-#define MACH_TYPE_FLEXIBITY            2965
-#define MACH_TYPE_WLAN_COMPUTER        2966
-#define MACH_TYPE_LPC24XX              2967
-#define MACH_TYPE_SPICA                2968
-#define MACH_TYPE_GPSDISPLAY           2969
-#define MACH_TYPE_BIPNET               2970
-#define MACH_TYPE_OVERO_CTU_INERTIAL   2971
-#define MACH_TYPE_DAVINCI_DM355_MMM    2972
-#define MACH_TYPE_PC9260_V2            2973
-#define MACH_TYPE_PTX7545              2974
-#define MACH_TYPE_TM_EFDC              2975
-#define MACH_TYPE_OMAP3_WALDO1         2977
-#define MACH_TYPE_FLYER                2978
-#define MACH_TYPE_TORNADO3240          2979
-#define MACH_TYPE_SOLI_01              2980
-#define MACH_TYPE_OMAPL138_EUROPALC    2981
-#define MACH_TYPE_HELIOS_V1            2982
-#define MACH_TYPE_NETSPACE_LITE_V2     2983
-#define MACH_TYPE_SSC                  2984
-#define MACH_TYPE_PREMIERWAVE_EN       2985
-#define MACH_TYPE_WASABI               2986
-#define MACH_TYPE_VIVOW                2987
-#define MACH_TYPE_MX50_RDP             2988
-#define MACH_TYPE_UNIVERSAL_C210       2989
-#define MACH_TYPE_REAL6410             2990
-#define MACH_TYPE_SPX_SAKURA           2991
-#define MACH_TYPE_IJ3K_2440            2992
-#define MACH_TYPE_OMAP3_BC10           2993
-#define MACH_TYPE_THEBE                2994
-#define MACH_TYPE_RV082                2995
-#define MACH_TYPE_ARMLGUEST            2996
-#define MACH_TYPE_TJINC1000            2997
-#define MACH_TYPE_DOCKSTAR             2998
-#define MACH_TYPE_AX8008               2999
-#define MACH_TYPE_GNET_SGCE            3000
-#define MACH_TYPE_PXWNAS_500_1000      3001
-#define MACH_TYPE_EA20                 3002
-#define MACH_TYPE_AWM2                 3003
-#define MACH_TYPE_TI8148EVM            3004
-#define MACH_TYPE_SEABOARD             3005
-#define MACH_TYPE_LINKSTATION_CHLV2    3006
-#define MACH_TYPE_TERA_PRO2_RACK       3007
-#define MACH_TYPE_RUBYS                3008
-#define MACH_TYPE_AQUARIUS             3009
-#define MACH_TYPE_MX53_ARD             3010
-#define MACH_TYPE_MX53_SMD             3011
-#define MACH_TYPE_LSWXL                3012
-#define MACH_TYPE_DOVE_AVNG_V3         3013
-#define MACH_TYPE_SDI_ESS_9263         3014
-#define MACH_TYPE_JOCPU550             3015
-#define MACH_TYPE_MSM8X60_RUMI3        3016
-#define MACH_TYPE_MSM8X60_FFA          3017
-#define MACH_TYPE_YANOMAMI             3018
-#define MACH_TYPE_GTA04                3019
-#define MACH_TYPE_CM_A510              3020
-#define MACH_TYPE_OMAP3_RFS200         3021
-#define MACH_TYPE_KX33XX               3022
-#define MACH_TYPE_PTX7510              3023
-#define MACH_TYPE_TOP9000              3024
-#define MACH_TYPE_TEENOTE              3025
-#define MACH_TYPE_TS3                  3026
-#define MACH_TYPE_A0                   3027
-#define MACH_TYPE_FSM9XXX_SURF         3028
-#define MACH_TYPE_FSM9XXX_FFA          3029
-#define MACH_TYPE_FRRHWCDMA60W         3030
-#define MACH_TYPE_REMUS                3031
-#define MACH_TYPE_AT91CAP7XDK          3032
-#define MACH_TYPE_AT91CAP7STK          3033
-#define MACH_TYPE_KT_SBC_SAM9_1        3034
-#define MACH_TYPE_ORATISROUTER         3035
-#define MACH_TYPE_ARMADA_XP_DB         3036
-#define MACH_TYPE_SPDM                 3037
-#define MACH_TYPE_GTIB                 3038
-#define MACH_TYPE_DGM3240              3039
-#define MACH_TYPE_ATLAS_I_LPE          3040
-#define MACH_TYPE_HTCMEGA              3041
-#define MACH_TYPE_TRICORDER            3042
-#define MACH_TYPE_TX28                 3043
-#define MACH_TYPE_BSTBRD               3044
-#define MACH_TYPE_PWB3090              3045
-#define MACH_TYPE_IDEA6410             3046
-#define MACH_TYPE_QBC9263              3047
-#define MACH_TYPE_BORABORA             3048
-#define MACH_TYPE_VALDEZ               3049
-#define MACH_TYPE_LS9G20               3050
-#define MACH_TYPE_MIOS_V1              3051
-#define MACH_TYPE_S5PC110_CRESPO       3052
-#define MACH_TYPE_CONTROLTEK9G20       3053
-#define MACH_TYPE_TIN307               3054
-#define MACH_TYPE_TIN510               3055
-#define MACH_TYPE_BLUECHEESE           3057
-#define MACH_TYPE_TEM3X30              3058
-#define MACH_TYPE_HARVEST_DESOTO       3059
-#define MACH_TYPE_MSM8X60_QRDC         3060
-#define MACH_TYPE_SPEAR900             3061
-#define MACH_TYPE_PCONTROL_G20         3062
-#define MACH_TYPE_RDSTOR               3063
-#define MACH_TYPE_USDLOADER            3064
-#define MACH_TYPE_TSOPLOADER           3065
-#define MACH_TYPE_KRONOS               3066
-#define MACH_TYPE_FFCORE               3067
-#define MACH_TYPE_MONE                 3068
-#define MACH_TYPE_UNIT2S               3069
-#define MACH_TYPE_ACER_A5              3070
-#define MACH_TYPE_ETHERPRO_ISP         3071
-#define MACH_TYPE_STRETCHS7000         3072
-#define MACH_TYPE_P87_SMARTSIM         3073
-#define MACH_TYPE_TULIP                3074
-#define MACH_TYPE_SUNFLOWER            3075
-#define MACH_TYPE_RIB                  3076
-#define MACH_TYPE_CLOD                 3077
-#define MACH_TYPE_RUMP                 3078
-#define MACH_TYPE_TENDERLOIN           3079
-#define MACH_TYPE_SHORTLOIN            3080
-#define MACH_TYPE_CRESPO               3081
-#define MACH_TYPE_ANTARES              3082
-#define MACH_TYPE_WB40N                3083
-#define MACH_TYPE_HERRING              3084
-#define MACH_TYPE_NAXY400              3085
-#define MACH_TYPE_NAXY1200             3086
-#define MACH_TYPE_VPR200               3087
-#define MACH_TYPE_BUG20                3088
-#define MACH_TYPE_GOFLEXNET            3089
-#define MACH_TYPE_TORBRECK             3090
-#define MACH_TYPE_SAARB_MG1            3091
-#define MACH_TYPE_CALLISTO             3092
-#define MACH_TYPE_MULTHSU              3093
-#define MACH_TYPE_SALUDA               3094
-#define MACH_TYPE_PEMP_OMAP3_APOLLO    3095
-#define MACH_TYPE_VC0718               3096
-#define MACH_TYPE_MVBLX                3097
-#define MACH_TYPE_INHAND_APEIRON       3098
-#define MACH_TYPE_INHAND_FURY          3099
-#define MACH_TYPE_INHAND_SIREN         3100
-#define MACH_TYPE_HDNVP                3101
-#define MACH_TYPE_SOFTWINNER           3102
-#define MACH_TYPE_PRIMA2_EVB           3103
-#define MACH_TYPE_NAS6210              3104
-#define MACH_TYPE_UNISDEV              3105
-#define MACH_TYPE_SBCA11               3106
-#define MACH_TYPE_SAGA                 3107
-#define MACH_TYPE_NS_K330              3108
-#define MACH_TYPE_TANNA                3109
-#define MACH_TYPE_IMATE8502            3110
-#define MACH_TYPE_ASPEN                3111
-#define MACH_TYPE_DAINTREE_CWAC        3112
-#define MACH_TYPE_ZMX25                3113
-#define MACH_TYPE_MAPLE1               3114
-#define MACH_TYPE_QSD8X72_SURF         3115
-#define MACH_TYPE_QSD8X72_FFA          3116
-#define MACH_TYPE_ABILENE              3117
-#define MACH_TYPE_EIGEN_TTR            3118
-#define MACH_TYPE_IOMEGA_IX2_200       3119
-#define MACH_TYPE_CORETEC_VCX7400      3120
-#define MACH_TYPE_SANTIAGO             3121
-#define MACH_TYPE_MX257SOL             3122
-#define MACH_TYPE_STRASBOURG           3123
-#define MACH_TYPE_MSM8X60_FLUID        3124
-#define MACH_TYPE_SMARTQV5             3125
-#define MACH_TYPE_SMARTQV3             3126
-#define MACH_TYPE_SMARTQV7             3127
-#define MACH_TYPE_PAZ00                3128
-#define MACH_TYPE_ACMENETUSFOXG20      3129
-#define MACH_TYPE_HTCWILLOW            3130
-#define MACH_TYPE_FWBD_0404            3131
-#define MACH_TYPE_HDGU                 3132
-#define MACH_TYPE_PYRAMID              3133
-#define MACH_TYPE_EPIPHAN              3134
-#define MACH_TYPE_OMAP_BENDER          3135
-#define MACH_TYPE_GURNARD              3136
-#define MACH_TYPE_GTL_IT5100           3137
-#define MACH_TYPE_BCM2708              3138
-#define MACH_TYPE_MX51_GGC             3139
-#define MACH_TYPE_SHARESPACE           3140
-#define MACH_TYPE_HABA_KNX_EXPLORER    3141
-#define MACH_TYPE_SIMTEC_KIRKMOD       3142
-#define MACH_TYPE_CRUX                 3143
-#define MACH_TYPE_MX51_BRAVO           3144
-#define MACH_TYPE_CHARON               3145
-#define MACH_TYPE_PICOCOM3             3146
-#define MACH_TYPE_PICOCOM4             3147
-#define MACH_TYPE_SERRANO              3148
-#define MACH_TYPE_DOUBLESHOT           3149
-#define MACH_TYPE_EVSY                 3150
-#define MACH_TYPE_HUASHAN              3151
-#define MACH_TYPE_LAUSANNE             3152
-#define MACH_TYPE_EMERALD              3153
-#define MACH_TYPE_TQMA35               3154
-#define MACH_TYPE_MARVEL               3155
-#define MACH_TYPE_MANUAE               3156
-#define MACH_TYPE_CHACHA               3157
-#define MACH_TYPE_LEMON                3158
-#define MACH_TYPE_CSC                  3159
-#define MACH_TYPE_GIRA_KNXIP_ROUTER    3160
-#define MACH_TYPE_T20                  3161
-#define MACH_TYPE_HDMINI               3162
-#define MACH_TYPE_SCIPHONE_G2          3163
-#define MACH_TYPE_EXPRESS              3164
-#define MACH_TYPE_EXPRESS_KT           3165
-#define MACH_TYPE_MAXIMASP             3166
-#define MACH_TYPE_NITROGEN_IMX51       3167
-#define MACH_TYPE_NITROGEN_IMX53       3168
-#define MACH_TYPE_SUNFIRE              3169
-#define MACH_TYPE_AROWANA              3170
-#define MACH_TYPE_TEGRA_DAYTONA        3171
-#define MACH_TYPE_TEGRA_SWORDFISH      3172
-#define MACH_TYPE_EDISON               3173
-#define MACH_TYPE_SVP8500V1            3174
-#define MACH_TYPE_SVP8500V2            3175
-#define MACH_TYPE_SVP5500              3176
-#define MACH_TYPE_B5500                3177
-#define MACH_TYPE_S5500                3178
-#define MACH_TYPE_ICON                 3179
-#define MACH_TYPE_ELEPHANT             3180
-#define MACH_TYPE_MSM8X60_FUSION       3181
-#define MACH_TYPE_SHOOTER              3182
-#define MACH_TYPE_SPADE_LTE            3183
-#define MACH_TYPE_PHILHWANI            3184
-#define MACH_TYPE_GSNCOMM              3185
-#define MACH_TYPE_STRASBOURG_A2        3186
-#define MACH_TYPE_MMM                  3187
-#define MACH_TYPE_DAVINCI_DM365_BV     3188
-#define MACH_TYPE_AG5EVM               3189
-#define MACH_TYPE_SC575PLC             3190
-#define MACH_TYPE_SC575IPC             3191
-#define MACH_TYPE_OMAP3_TDM3730        3192
-#define MACH_TYPE_G7                   3193
-#define MACH_TYPE_TOP9000_EVAL         3194
-#define MACH_TYPE_TOP9000_SU           3195
-#define MACH_TYPE_UTM300               3196
-#define MACH_TYPE_TSUNAGI              3197
-#define MACH_TYPE_TS75XX               3198
-#define MACH_TYPE_MSM8X60_FUSN_FFA     3199
-#define MACH_TYPE_TS47XX               3200
-#define MACH_TYPE_DA850_K5             3201
-#define MACH_TYPE_AX502                3202
-#define MACH_TYPE_IGEP0032             3203
-#define MACH_TYPE_ANTERO               3204
-#define MACH_TYPE_SYNERGY              3205
-#define MACH_TYPE_ICS_IF_VOIP          3206
-#define MACH_TYPE_WLF_CRAGG_6410       3207
-#define MACH_TYPE_PUNICA               3208
-#define MACH_TYPE_TRIMSLICE            3209
-#define MACH_TYPE_MX27_WMULTRA         3210
-#define MACH_TYPE_MACKEREL             3211
-#define MACH_TYPE_FA9X27               3213
-#define MACH_TYPE_NS2816TB             3214
-#define MACH_TYPE_NS2816_NTPAD         3215
-#define MACH_TYPE_NS2816_NTNB          3216
-#define MACH_TYPE_KAEN                 3217
-#define MACH_TYPE_NV1000               3218
-#define MACH_TYPE_NUC950TS             3219
-#define MACH_TYPE_NOKIA_RM680          3220
-#define MACH_TYPE_AST2200              3221
-#define MACH_TYPE_LEAD                 3222
-#define MACH_TYPE_UNINO1               3223
-#define MACH_TYPE_GREECO               3224
-#define MACH_TYPE_VERDI                3225
-#define MACH_TYPE_DM6446_ADBOX         3226
-#define MACH_TYPE_QUAD_SALSA           3227
-#define MACH_TYPE_ABB_GMA_1_1          3228
-#define MACH_TYPE_SVCID                3229
-#define MACH_TYPE_MSM8960_SIM          3230
-#define MACH_TYPE_MSM8960_RUMI3        3231
-#define MACH_TYPE_ICON_G               3232
-#define MACH_TYPE_MB3                  3233
-#define MACH_TYPE_GSIA18S              3234
-#define MACH_TYPE_PIVICC               3235
-#define MACH_TYPE_PCM048               3236
-#define MACH_TYPE_DDS                  3237
-#define MACH_TYPE_CHALTEN_XA1          3238
-#define MACH_TYPE_TS48XX               3239
-#define MACH_TYPE_TONGA2_TFTTIMER      3240
-#define MACH_TYPE_WHISTLER             3241
-#define MACH_TYPE_ASL_PHOENIX          3242
-#define MACH_TYPE_AT91SAM9263OTLITE    3243
-#define MACH_TYPE_DDPLUG               3244
-#define MACH_TYPE_D2PLUG               3245
-#define MACH_TYPE_KZM9D                3246
-#define MACH_TYPE_VERDI_LTE            3247
-#define MACH_TYPE_NANOZOOM             3248
-#define MACH_TYPE_DM3730_SOM_LV        3249
-#define MACH_TYPE_DM3730_TORPEDO       3250
-#define MACH_TYPE_ANCHOVY              3251
-#define MACH_TYPE_RE2REV20             3253
-#define MACH_TYPE_RE2REV21             3254
-#define MACH_TYPE_CNS21XX              3255
-#define MACH_TYPE_RIDER                3257
-#define MACH_TYPE_NSK330               3258
-#define MACH_TYPE_CNS2133EVB           3259
-#define MACH_TYPE_Z3_816X_MOD          3260
-#define MACH_TYPE_Z3_814X_MOD          3261
-#define MACH_TYPE_BEECT                3262
-#define MACH_TYPE_DMA_THUNDERBUG       3263
-#define MACH_TYPE_OMN_AT91SAM9G20      3264
-#define MACH_TYPE_MX25_E2S_UC          3265
-#define MACH_TYPE_MIONE                3266
-#define MACH_TYPE_TOP9000_TCU          3267
-#define MACH_TYPE_TOP9000_BSL          3268
-#define MACH_TYPE_KINGDOM              3269
-#define MACH_TYPE_ARMADILLO460         3270
-#define MACH_TYPE_LQ2                  3271
-#define MACH_TYPE_SWEDA_TMS2           3272
-#define MACH_TYPE_MX53_LOCO            3273
-#define MACH_TYPE_ACER_A8              3275
-#define MACH_TYPE_ACER_GAUGUIN         3276
-#define MACH_TYPE_GUPPY                3277
-#define MACH_TYPE_MX61_ARD             3278
-#define MACH_TYPE_TX53                 3279
-#define MACH_TYPE_OMAPL138_CASE_A3     3280
-#define MACH_TYPE_UEMD                 3281
-#define MACH_TYPE_CCWMX51MUT           3282
-#define MACH_TYPE_ROCKHOPPER           3283
-#define MACH_TYPE_NOOKCOLOR            3284
-#define MACH_TYPE_HKDKC100             3285
-#define MACH_TYPE_TS42XX               3286
-#define MACH_TYPE_AEBL                 3287
-#define MACH_TYPE_WARIO                3288
-#define MACH_TYPE_GFS_SPM              3289
-#define MACH_TYPE_CM_T3730             3290
-#define MACH_TYPE_ISC3                 3291
-#define MACH_TYPE_RASCAL               3292
-#define MACH_TYPE_HREFV60              3293
-#define MACH_TYPE_TPT_2_0              3294
-#define MACH_TYPE_PYRAMID_TD           3295
-#define MACH_TYPE_SPLENDOR             3296
-#define MACH_TYPE_GUF_PLANET           3297
-#define MACH_TYPE_MSM8X60_QT           3298
-#define MACH_TYPE_HTC_HD_MINI          3299
-#define MACH_TYPE_ATHENE               3300
-#define MACH_TYPE_DEEP_R_EK_1          3301
-#define MACH_TYPE_VIVOW_CT             3302
-#define MACH_TYPE_NERY_1000            3303
-#define MACH_TYPE_RFL109145_SSRV       3304
-#define MACH_TYPE_NMH                  3305
-#define MACH_TYPE_WN802T               3306
-#define MACH_TYPE_DRAGONET             3307
-#define MACH_TYPE_GENEVA_B             3308
-#define MACH_TYPE_AT91SAM9263DESK16L   3309
-#define MACH_TYPE_BCMHANA_SV           3310
-#define MACH_TYPE_BCMHANA_TABLET       3311
-#define MACH_TYPE_KOI                  3312
-#define MACH_TYPE_TS4800               3313
-#define MACH_TYPE_TQMA9263             3314
-#define MACH_TYPE_HOLIDAY              3315
-#define MACH_TYPE_DMA6410              3316
-#define MACH_TYPE_PCATS_OVERLAY        3317
-#define MACH_TYPE_HWGW6410             3318
-#define MACH_TYPE_SHENZHOU             3319
-#define MACH_TYPE_CWME9210             3320
-#define MACH_TYPE_CWME9210JS           3321
-#define MACH_TYPE_PGS_SITARA           3322
-#define MACH_TYPE_COLIBRI_TEGRA2       3323
-#define MACH_TYPE_W21                  3324
-#define MACH_TYPE_POLYSAT1             3325
-#define MACH_TYPE_DATAWAY              3326
-#define MACH_TYPE_COBRAL138            3327
-#define MACH_TYPE_ROVERPCS8            3328
-#define MACH_TYPE_MARVELC              3329
-#define MACH_TYPE_NAVEFIHID            3330
-#define MACH_TYPE_DM365_CV100          3331
-#define MACH_TYPE_ABLE                 3332
-#define MACH_TYPE_LEGACY               3333
-#define MACH_TYPE_ICONG                3334
-#define MACH_TYPE_ROVER_G8             3335
-#define MACH_TYPE_T5388P               3336
-#define MACH_TYPE_DINGO                3337
-#define MACH_TYPE_GOFLEXHOME           3338
-
-#ifdef CONFIG_ARCH_EBSA110
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_EBSA110
-# endif
-# define machine_is_ebsa110()	(machine_arch_type == MACH_TYPE_EBSA110)
-#else
-# define machine_is_ebsa110()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_RPC
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_RISCPC
-# endif
-# define machine_is_riscpc()	(machine_arch_type == MACH_TYPE_RISCPC)
-#else
-# define machine_is_riscpc()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_NEXUSPCI
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_NEXUSPCI
-# endif
-# define machine_is_nexuspci()	(machine_arch_type == MACH_TYPE_NEXUSPCI)
-#else
-# define machine_is_nexuspci()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_EBSA285
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_EBSA285
-# endif
-# define machine_is_ebsa285()	(machine_arch_type == MACH_TYPE_EBSA285)
-#else
-# define machine_is_ebsa285()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_NETWINDER
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_NETWINDER
-# endif
-# define machine_is_netwinder()	(machine_arch_type == MACH_TYPE_NETWINDER)
-#else
-# define machine_is_netwinder()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_CATS
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CATS
-# endif
-# define machine_is_cats()	(machine_arch_type == MACH_TYPE_CATS)
-#else
-# define machine_is_cats()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_TBOX
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TBOX
-# endif
-# define machine_is_tbox()	(machine_arch_type == MACH_TYPE_TBOX)
-#else
-# define machine_is_tbox()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_CO285
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CO285
-# endif
-# define machine_is_co285()	(machine_arch_type == MACH_TYPE_CO285)
-#else
-# define machine_is_co285()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_CLPS7110
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CLPS7110
-# endif
-# define machine_is_clps7110()	(machine_arch_type == MACH_TYPE_CLPS7110)
-#else
-# define machine_is_clps7110()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_ARC
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ARCHIMEDES
-# endif
-# define machine_is_archimedes()	(machine_arch_type == MACH_TYPE_ARCHIMEDES)
-#else
-# define machine_is_archimedes()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_A5K
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_A5K
-# endif
-# define machine_is_a5k()	(machine_arch_type == MACH_TYPE_A5K)
-#else
-# define machine_is_a5k()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_ETOILE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ETOILE
-# endif
-# define machine_is_etoile()	(machine_arch_type == MACH_TYPE_ETOILE)
-#else
-# define machine_is_etoile()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_LACIE_NAS
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_LACIE_NAS
-# endif
-# define machine_is_lacie_nas()	(machine_arch_type == MACH_TYPE_LACIE_NAS)
-#else
-# define machine_is_lacie_nas()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_CLPS7500
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CLPS7500
-# endif
-# define machine_is_clps7500()	(machine_arch_type == MACH_TYPE_CLPS7500)
-#else
-# define machine_is_clps7500()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_SHARK
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SHARK
-# endif
-# define machine_is_shark()	(machine_arch_type == MACH_TYPE_SHARK)
-#else
-# define machine_is_shark()	(0)
-#endif
-
-#ifdef CONFIG_SA1100_BRUTUS
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_BRUTUS
-# endif
-# define machine_is_brutus()	(machine_arch_type == MACH_TYPE_BRUTUS)
-#else
-# define machine_is_brutus()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_PERSONAL_SERVER
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PERSONAL_SERVER
-# endif
-# define machine_is_personal_server()	(machine_arch_type == MACH_TYPE_PERSONAL_SERVER)
-#else
-# define machine_is_personal_server()	(0)
-#endif
-
-#ifdef CONFIG_SA1100_ITSY
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ITSY
-# endif
-# define machine_is_itsy()	(machine_arch_type == MACH_TYPE_ITSY)
-#else
-# define machine_is_itsy()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_L7200
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_L7200
-# endif
-# define machine_is_l7200()	(machine_arch_type == MACH_TYPE_L7200)
-#else
-# define machine_is_l7200()	(0)
-#endif
-
-#ifdef CONFIG_SA1100_PLEB
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PLEB
-# endif
-# define machine_is_pleb()	(machine_arch_type == MACH_TYPE_PLEB)
-#else
-# define machine_is_pleb()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_INTEGRATOR
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_INTEGRATOR
-# endif
-# define machine_is_integrator()	(machine_arch_type == MACH_TYPE_INTEGRATOR)
-#else
-# define machine_is_integrator()	(0)
-#endif
-
-#ifdef CONFIG_SA1100_H3600
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_H3600
-# endif
-# define machine_is_h3600()	(machine_arch_type == MACH_TYPE_H3600)
-#else
-# define machine_is_h3600()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_IXP1200
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_IXP1200
-# endif
-# define machine_is_ixp1200()	(machine_arch_type == MACH_TYPE_IXP1200)
-#else
-# define machine_is_ixp1200()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_P720T
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_P720T
-# endif
-# define machine_is_p720t()	(machine_arch_type == MACH_TYPE_P720T)
-#else
-# define machine_is_p720t()	(0)
-#endif
-
-#ifdef CONFIG_SA1100_ASSABET
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ASSABET
-# endif
-# define machine_is_assabet()	(machine_arch_type == MACH_TYPE_ASSABET)
-#else
-# define machine_is_assabet()	(0)
-#endif
-
-#ifdef CONFIG_SA1100_VICTOR
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_VICTOR
-# endif
-# define machine_is_victor()	(machine_arch_type == MACH_TYPE_VICTOR)
-#else
-# define machine_is_victor()	(0)
-#endif
-
-#ifdef CONFIG_SA1100_LART
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_LART
-# endif
-# define machine_is_lart()	(machine_arch_type == MACH_TYPE_LART)
-#else
-# define machine_is_lart()	(0)
-#endif
-
-#ifdef CONFIG_SA1100_RANGER
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_RANGER
-# endif
-# define machine_is_ranger()	(machine_arch_type == MACH_TYPE_RANGER)
-#else
-# define machine_is_ranger()	(0)
-#endif
-
-#ifdef CONFIG_SA1100_GRAPHICSCLIENT
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_GRAPHICSCLIENT
-# endif
-# define machine_is_graphicsclient()	(machine_arch_type == MACH_TYPE_GRAPHICSCLIENT)
-#else
-# define machine_is_graphicsclient()	(0)
-#endif
-
-#ifdef CONFIG_SA1100_XP860
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_XP860
-# endif
-# define machine_is_xp860()	(machine_arch_type == MACH_TYPE_XP860)
-#else
-# define machine_is_xp860()	(0)
-#endif
-
-#ifdef CONFIG_SA1100_CERF
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CERF
-# endif
-# define machine_is_cerf()	(machine_arch_type == MACH_TYPE_CERF)
-#else
-# define machine_is_cerf()	(0)
-#endif
-
-#ifdef CONFIG_SA1100_NANOENGINE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_NANOENGINE
-# endif
-# define machine_is_nanoengine()	(machine_arch_type == MACH_TYPE_NANOENGINE)
-#else
-# define machine_is_nanoengine()	(0)
-#endif
-
-#ifdef CONFIG_SA1100_FPIC
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_FPIC
-# endif
-# define machine_is_fpic()	(machine_arch_type == MACH_TYPE_FPIC)
-#else
-# define machine_is_fpic()	(0)
-#endif
-
-#ifdef CONFIG_SA1100_EXTENEX1
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_EXTENEX1
-# endif
-# define machine_is_extenex1()	(machine_arch_type == MACH_TYPE_EXTENEX1)
-#else
-# define machine_is_extenex1()	(0)
-#endif
-
-#ifdef CONFIG_SA1100_SHERMAN
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SHERMAN
-# endif
-# define machine_is_sherman()	(machine_arch_type == MACH_TYPE_SHERMAN)
-#else
-# define machine_is_sherman()	(0)
-#endif
-
-#ifdef CONFIG_SA1100_ACCELENT
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ACCELENT_SA
-# endif
-# define machine_is_accelent_sa()	(machine_arch_type == MACH_TYPE_ACCELENT_SA)
-#else
-# define machine_is_accelent_sa()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_L7200_ACCELENT
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ACCELENT_L7200
-# endif
-# define machine_is_accelent_l7200()	(machine_arch_type == MACH_TYPE_ACCELENT_L7200)
-#else
-# define machine_is_accelent_l7200()	(0)
-#endif
-
-#ifdef CONFIG_SA1100_NETPORT
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_NETPORT
-# endif
-# define machine_is_netport()	(machine_arch_type == MACH_TYPE_NETPORT)
-#else
-# define machine_is_netport()	(0)
-#endif
-
-#ifdef CONFIG_SA1100_PANGOLIN
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PANGOLIN
-# endif
-# define machine_is_pangolin()	(machine_arch_type == MACH_TYPE_PANGOLIN)
-#else
-# define machine_is_pangolin()	(0)
-#endif
-
-#ifdef CONFIG_SA1100_YOPY
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_YOPY
-# endif
-# define machine_is_yopy()	(machine_arch_type == MACH_TYPE_YOPY)
-#else
-# define machine_is_yopy()	(0)
-#endif
-
-#ifdef CONFIG_SA1100_COOLIDGE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_COOLIDGE
-# endif
-# define machine_is_coolidge()	(machine_arch_type == MACH_TYPE_COOLIDGE)
-#else
-# define machine_is_coolidge()	(0)
-#endif
-
-#ifdef CONFIG_SA1100_HUW_WEBPANEL
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_HUW_WEBPANEL
-# endif
-# define machine_is_huw_webpanel()	(machine_arch_type == MACH_TYPE_HUW_WEBPANEL)
-#else
-# define machine_is_huw_webpanel()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_SPOTME
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SPOTME
-# endif
-# define machine_is_spotme()	(machine_arch_type == MACH_TYPE_SPOTME)
-#else
-# define machine_is_spotme()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_FREEBIRD
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_FREEBIRD
-# endif
-# define machine_is_freebird()	(machine_arch_type == MACH_TYPE_FREEBIRD)
-#else
-# define machine_is_freebird()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_TI925
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TI925
-# endif
-# define machine_is_ti925()	(machine_arch_type == MACH_TYPE_TI925)
-#else
-# define machine_is_ti925()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_RISCSTATION
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_RISCSTATION
-# endif
-# define machine_is_riscstation()	(machine_arch_type == MACH_TYPE_RISCSTATION)
-#else
-# define machine_is_riscstation()	(0)
-#endif
-
-#ifdef CONFIG_SA1100_CAVY
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CAVY
-# endif
-# define machine_is_cavy()	(machine_arch_type == MACH_TYPE_CAVY)
-#else
-# define machine_is_cavy()	(0)
-#endif
-
-#ifdef CONFIG_SA1100_JORNADA720
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_JORNADA720
-# endif
-# define machine_is_jornada720()	(machine_arch_type == MACH_TYPE_JORNADA720)
-#else
-# define machine_is_jornada720()	(0)
-#endif
-
-#ifdef CONFIG_SA1100_OMNIMETER
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_OMNIMETER
-# endif
-# define machine_is_omnimeter()	(machine_arch_type == MACH_TYPE_OMNIMETER)
-#else
-# define machine_is_omnimeter()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_EDB7211
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_EDB7211
-# endif
-# define machine_is_edb7211()	(machine_arch_type == MACH_TYPE_EDB7211)
-#else
-# define machine_is_edb7211()	(0)
-#endif
-
-#ifdef CONFIG_SA1100_CITYGO
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CITYGO
-# endif
-# define machine_is_citygo()	(machine_arch_type == MACH_TYPE_CITYGO)
-#else
-# define machine_is_citygo()	(0)
-#endif
-
-#ifdef CONFIG_SA1100_PFS168
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PFS168
-# endif
-# define machine_is_pfs168()	(machine_arch_type == MACH_TYPE_PFS168)
-#else
-# define machine_is_pfs168()	(0)
-#endif
-
-#ifdef CONFIG_SA1100_SPOT
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SPOT
-# endif
-# define machine_is_spot()	(machine_arch_type == MACH_TYPE_SPOT)
-#else
-# define machine_is_spot()	(0)
-#endif
-
-#ifdef CONFIG_SA1100_FLEXANET
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_FLEXANET
-# endif
-# define machine_is_flexanet()	(machine_arch_type == MACH_TYPE_FLEXANET)
-#else
-# define machine_is_flexanet()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_WEBPAL
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_WEBPAL
-# endif
-# define machine_is_webpal()	(machine_arch_type == MACH_TYPE_WEBPAL)
-#else
-# define machine_is_webpal()	(0)
-#endif
-
-#ifdef CONFIG_SA1100_LINPDA
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_LINPDA
-# endif
-# define machine_is_linpda()	(machine_arch_type == MACH_TYPE_LINPDA)
-#else
-# define machine_is_linpda()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_ANAKIN
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ANAKIN
-# endif
-# define machine_is_anakin()	(machine_arch_type == MACH_TYPE_ANAKIN)
-#else
-# define machine_is_anakin()	(0)
-#endif
-
-#ifdef CONFIG_SA1100_MVI
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MVI
-# endif
-# define machine_is_mvi()	(machine_arch_type == MACH_TYPE_MVI)
-#else
-# define machine_is_mvi()	(0)
-#endif
-
-#ifdef CONFIG_SA1100_JUPITER
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_JUPITER
-# endif
-# define machine_is_jupiter()	(machine_arch_type == MACH_TYPE_JUPITER)
-#else
-# define machine_is_jupiter()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_PSIONW
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PSIONW
-# endif
-# define machine_is_psionw()	(machine_arch_type == MACH_TYPE_PSIONW)
-#else
-# define machine_is_psionw()	(0)
-#endif
-
-#ifdef CONFIG_SA1100_ALN
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ALN
-# endif
-# define machine_is_aln()	(machine_arch_type == MACH_TYPE_ALN)
-#else
-# define machine_is_aln()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_CAMELOT
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CAMELOT
-# endif
-# define machine_is_epxa()	(machine_arch_type == MACH_TYPE_CAMELOT)
-#else
-# define machine_is_epxa()	(0)
-#endif
-
-#ifdef CONFIG_SA1100_GDS2200
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_GDS2200
-# endif
-# define machine_is_gds2200()	(machine_arch_type == MACH_TYPE_GDS2200)
-#else
-# define machine_is_gds2200()	(0)
-#endif
-
-#ifdef CONFIG_SA1100_PSION_SERIES7
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PSION_SERIES7
-# endif
-# define machine_is_netbook()	(machine_arch_type == MACH_TYPE_PSION_SERIES7)
-#else
-# define machine_is_netbook()	(0)
-#endif
-
-#ifdef CONFIG_SA1100_XFILE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_XFILE
-# endif
-# define machine_is_xfile()	(machine_arch_type == MACH_TYPE_XFILE)
-#else
-# define machine_is_xfile()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_ACCELENT_EP9312
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ACCELENT_EP9312
-# endif
-# define machine_is_accelent_ep9312()	(machine_arch_type == MACH_TYPE_ACCELENT_EP9312)
-#else
-# define machine_is_accelent_ep9312()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_IC200
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_IC200
-# endif
-# define machine_is_ic200()	(machine_arch_type == MACH_TYPE_IC200)
-#else
-# define machine_is_ic200()	(0)
-#endif
-
-#ifdef CONFIG_SA1100_CREDITLART
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CREDITLART
-# endif
-# define machine_is_creditlart()	(machine_arch_type == MACH_TYPE_CREDITLART)
-#else
-# define machine_is_creditlart()	(0)
-#endif
-
-#ifdef CONFIG_SA1100_HTM
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_HTM
-# endif
-# define machine_is_htm()	(machine_arch_type == MACH_TYPE_HTM)
-#else
-# define machine_is_htm()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_IQ80310
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_IQ80310
-# endif
-# define machine_is_iq80310()	(machine_arch_type == MACH_TYPE_IQ80310)
-#else
-# define machine_is_iq80310()	(0)
-#endif
-
-#ifdef CONFIG_SA1100_FREEBOT
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_FREEBOT
-# endif
-# define machine_is_freebot()	(machine_arch_type == MACH_TYPE_FREEBOT)
-#else
-# define machine_is_freebot()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_ENTEL
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ENTEL
-# endif
-# define machine_is_entel()	(machine_arch_type == MACH_TYPE_ENTEL)
-#else
-# define machine_is_entel()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_ENP3510
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ENP3510
-# endif
-# define machine_is_enp3510()	(machine_arch_type == MACH_TYPE_ENP3510)
-#else
-# define machine_is_enp3510()	(0)
-#endif
-
-#ifdef CONFIG_SA1100_TRIZEPS
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TRIZEPS
-# endif
-# define machine_is_trizeps()	(machine_arch_type == MACH_TYPE_TRIZEPS)
-#else
-# define machine_is_trizeps()	(0)
-#endif
-
-#ifdef CONFIG_SA1100_NESA
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_NESA
-# endif
-# define machine_is_nesa()	(machine_arch_type == MACH_TYPE_NESA)
-#else
-# define machine_is_nesa()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_VENUS
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_VENUS
-# endif
-# define machine_is_venus()	(machine_arch_type == MACH_TYPE_VENUS)
-#else
-# define machine_is_venus()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_TARDIS
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TARDIS
-# endif
-# define machine_is_tardis()	(machine_arch_type == MACH_TYPE_TARDIS)
-#else
-# define machine_is_tardis()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_MERCURY
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MERCURY
-# endif
-# define machine_is_mercury()	(machine_arch_type == MACH_TYPE_MERCURY)
-#else
-# define machine_is_mercury()	(0)
-#endif
-
-#ifdef CONFIG_SA1100_EMPEG
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_EMPEG
-# endif
-# define machine_is_empeg()	(machine_arch_type == MACH_TYPE_EMPEG)
-#else
-# define machine_is_empeg()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_I80200FCC
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_I80200FCC
-# endif
-# define machine_is_adi_evb()	(machine_arch_type == MACH_TYPE_I80200FCC)
-#else
-# define machine_is_adi_evb()	(0)
-#endif
-
-#ifdef CONFIG_SA1100_ITT_CPB
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ITT_CPB
-# endif
-# define machine_is_itt_cpb()	(machine_arch_type == MACH_TYPE_ITT_CPB)
-#else
-# define machine_is_itt_cpb()	(0)
-#endif
-
-#ifdef CONFIG_SA1100_SVC
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SVC
-# endif
-# define machine_is_svc()	(machine_arch_type == MACH_TYPE_SVC)
-#else
-# define machine_is_svc()	(0)
-#endif
-
-#ifdef CONFIG_SA1100_ALPHA2
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ALPHA2
-# endif
-# define machine_is_alpha2()	(machine_arch_type == MACH_TYPE_ALPHA2)
-#else
-# define machine_is_alpha2()	(0)
-#endif
-
-#ifdef CONFIG_SA1100_ALPHA1
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ALPHA1
-# endif
-# define machine_is_alpha1()	(machine_arch_type == MACH_TYPE_ALPHA1)
-#else
-# define machine_is_alpha1()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_NETARM
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_NETARM
-# endif
-# define machine_is_netarm()	(machine_arch_type == MACH_TYPE_NETARM)
-#else
-# define machine_is_netarm()	(0)
-#endif
-
-#ifdef CONFIG_SA1100_SIMPAD
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SIMPAD
-# endif
-# define machine_is_simpad()	(machine_arch_type == MACH_TYPE_SIMPAD)
-#else
-# define machine_is_simpad()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_PDA1
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PDA1
-# endif
-# define machine_is_pda1()	(machine_arch_type == MACH_TYPE_PDA1)
-#else
-# define machine_is_pda1()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_LUBBOCK
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_LUBBOCK
-# endif
-# define machine_is_lubbock()	(machine_arch_type == MACH_TYPE_LUBBOCK)
-#else
-# define machine_is_lubbock()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_ANIKO
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ANIKO
-# endif
-# define machine_is_aniko()	(machine_arch_type == MACH_TYPE_ANIKO)
-#else
-# define machine_is_aniko()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_CLEP7212
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CLEP7212
-# endif
-# define machine_is_clep7212()	(machine_arch_type == MACH_TYPE_CLEP7212)
-#else
-# define machine_is_clep7212()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_CS89712
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CS89712
-# endif
-# define machine_is_cs89712()	(machine_arch_type == MACH_TYPE_CS89712)
-#else
-# define machine_is_cs89712()	(0)
-#endif
-
-#ifdef CONFIG_SA1100_WEARARM
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_WEARARM
-# endif
-# define machine_is_weararm()	(machine_arch_type == MACH_TYPE_WEARARM)
-#else
-# define machine_is_weararm()	(0)
-#endif
-
-#ifdef CONFIG_SA1100_POSSIO_PX
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_POSSIO_PX
-# endif
-# define machine_is_possio_px()	(machine_arch_type == MACH_TYPE_POSSIO_PX)
-#else
-# define machine_is_possio_px()	(0)
-#endif
-
-#ifdef CONFIG_SA1100_SIDEARM
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SIDEARM
-# endif
-# define machine_is_sidearm()	(machine_arch_type == MACH_TYPE_SIDEARM)
-#else
-# define machine_is_sidearm()	(0)
-#endif
-
-#ifdef CONFIG_SA1100_STORK
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_STORK
-# endif
-# define machine_is_stork()	(machine_arch_type == MACH_TYPE_STORK)
-#else
-# define machine_is_stork()	(0)
-#endif
-
-#ifdef CONFIG_SA1100_SHANNON
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SHANNON
-# endif
-# define machine_is_shannon()	(machine_arch_type == MACH_TYPE_SHANNON)
-#else
-# define machine_is_shannon()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_ACE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ACE
-# endif
-# define machine_is_ace()	(machine_arch_type == MACH_TYPE_ACE)
-#else
-# define machine_is_ace()	(0)
-#endif
-
-#ifdef CONFIG_SA1100_BALLYARM
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_BALLYARM
-# endif
-# define machine_is_ballyarm()	(machine_arch_type == MACH_TYPE_BALLYARM)
-#else
-# define machine_is_ballyarm()	(0)
-#endif
-
-#ifdef CONFIG_SA1100_SIMPUTER
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SIMPUTER
-# endif
-# define machine_is_simputer()	(machine_arch_type == MACH_TYPE_SIMPUTER)
-#else
-# define machine_is_simputer()	(0)
-#endif
-
-#ifdef CONFIG_SA1100_NEXTERM
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_NEXTERM
-# endif
-# define machine_is_nexterm()	(machine_arch_type == MACH_TYPE_NEXTERM)
-#else
-# define machine_is_nexterm()	(0)
-#endif
-
-#ifdef CONFIG_SA1100_SA1100_ELF
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SA1100_ELF
-# endif
-# define machine_is_sa1100_elf()	(machine_arch_type == MACH_TYPE_SA1100_ELF)
-#else
-# define machine_is_sa1100_elf()	(0)
-#endif
-
-#ifdef CONFIG_SA1100_GATOR
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_GATOR
-# endif
-# define machine_is_gator()	(machine_arch_type == MACH_TYPE_GATOR)
-#else
-# define machine_is_gator()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_GRANITE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_GRANITE
-# endif
-# define machine_is_granite()	(machine_arch_type == MACH_TYPE_GRANITE)
-#else
-# define machine_is_granite()	(0)
-#endif
-
-#ifdef CONFIG_SA1100_CONSUS
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CONSUS
-# endif
-# define machine_is_consus()	(machine_arch_type == MACH_TYPE_CONSUS)
-#else
-# define machine_is_consus()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_AAED2000
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_AAED2000
-# endif
-# define machine_is_aaed2000()	(machine_arch_type == MACH_TYPE_AAED2000)
-#else
-# define machine_is_aaed2000()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_CDB89712
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CDB89712
-# endif
-# define machine_is_cdb89712()	(machine_arch_type == MACH_TYPE_CDB89712)
-#else
-# define machine_is_cdb89712()	(0)
-#endif
-
-#ifdef CONFIG_SA1100_GRAPHICSMASTER
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_GRAPHICSMASTER
-# endif
-# define machine_is_graphicsmaster()	(machine_arch_type == MACH_TYPE_GRAPHICSMASTER)
-#else
-# define machine_is_graphicsmaster()	(0)
-#endif
-
-#ifdef CONFIG_SA1100_ADSBITSY
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ADSBITSY
-# endif
-# define machine_is_adsbitsy()	(machine_arch_type == MACH_TYPE_ADSBITSY)
-#else
-# define machine_is_adsbitsy()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_PXA_IDP
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PXA_IDP
-# endif
-# define machine_is_pxa_idp()	(machine_arch_type == MACH_TYPE_PXA_IDP)
-#else
-# define machine_is_pxa_idp()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_PLCE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PLCE
-# endif
-# define machine_is_plce()	(machine_arch_type == MACH_TYPE_PLCE)
-#else
-# define machine_is_plce()	(0)
-#endif
-
-#ifdef CONFIG_SA1100_PT_SYSTEM3
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PT_SYSTEM3
-# endif
-# define machine_is_pt_system3()	(machine_arch_type == MACH_TYPE_PT_SYSTEM3)
-#else
-# define machine_is_pt_system3()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_MEDALB
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MEDALB
-# endif
-# define machine_is_murphy()	(machine_arch_type == MACH_TYPE_MEDALB)
-#else
-# define machine_is_murphy()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_EAGLE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_EAGLE
-# endif
-# define machine_is_eagle()	(machine_arch_type == MACH_TYPE_EAGLE)
-#else
-# define machine_is_eagle()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_DSC21
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_DSC21
-# endif
-# define machine_is_dsc21()	(machine_arch_type == MACH_TYPE_DSC21)
-#else
-# define machine_is_dsc21()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_DSC24
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_DSC24
-# endif
-# define machine_is_dsc24()	(machine_arch_type == MACH_TYPE_DSC24)
-#else
-# define machine_is_dsc24()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_TI5472
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TI5472
-# endif
-# define machine_is_ti5472()	(machine_arch_type == MACH_TYPE_TI5472)
-#else
-# define machine_is_ti5472()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_AUTCPU12
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_AUTCPU12
-# endif
-# define machine_is_autcpu12()	(machine_arch_type == MACH_TYPE_AUTCPU12)
-#else
-# define machine_is_autcpu12()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_UENGINE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_UENGINE
-# endif
-# define machine_is_uengine()	(machine_arch_type == MACH_TYPE_UENGINE)
-#else
-# define machine_is_uengine()	(0)
-#endif
-
-#ifdef CONFIG_SA1100_BLUESTEM
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_BLUESTEM
-# endif
-# define machine_is_bluestem()	(machine_arch_type == MACH_TYPE_BLUESTEM)
-#else
-# define machine_is_bluestem()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_XINGU8
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_XINGU8
-# endif
-# define machine_is_xingu8()	(machine_arch_type == MACH_TYPE_XINGU8)
-#else
-# define machine_is_xingu8()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_BUSHSTB
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_BUSHSTB
-# endif
-# define machine_is_bushstb()	(machine_arch_type == MACH_TYPE_BUSHSTB)
-#else
-# define machine_is_bushstb()	(0)
-#endif
-
-#ifdef CONFIG_SA1100_EPSILON1
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_EPSILON1
-# endif
-# define machine_is_epsilon1()	(machine_arch_type == MACH_TYPE_EPSILON1)
-#else
-# define machine_is_epsilon1()	(0)
-#endif
-
-#ifdef CONFIG_SA1100_BALLOON
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_BALLOON
-# endif
-# define machine_is_balloon()	(machine_arch_type == MACH_TYPE_BALLOON)
-#else
-# define machine_is_balloon()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_PUPPY
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PUPPY
-# endif
-# define machine_is_puppy()	(machine_arch_type == MACH_TYPE_PUPPY)
-#else
-# define machine_is_puppy()	(0)
-#endif
-
-#ifdef CONFIG_SA1100_ELROY
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ELROY
-# endif
-# define machine_is_elroy()	(machine_arch_type == MACH_TYPE_ELROY)
-#else
-# define machine_is_elroy()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_GMS720
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_GMS720
-# endif
-# define machine_is_gms720()	(machine_arch_type == MACH_TYPE_GMS720)
-#else
-# define machine_is_gms720()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_S24X
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_S24X
-# endif
-# define machine_is_s24x()	(machine_arch_type == MACH_TYPE_S24X)
-#else
-# define machine_is_s24x()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_JTEL_CLEP7312
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_JTEL_CLEP7312
-# endif
-# define machine_is_jtel_clep7312()	(machine_arch_type == MACH_TYPE_JTEL_CLEP7312)
-#else
-# define machine_is_jtel_clep7312()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_CX821XX
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CX821XX
-# endif
-# define machine_is_cx821xx()	(machine_arch_type == MACH_TYPE_CX821XX)
-#else
-# define machine_is_cx821xx()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_EDB7312
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_EDB7312
-# endif
-# define machine_is_edb7312()	(machine_arch_type == MACH_TYPE_EDB7312)
-#else
-# define machine_is_edb7312()	(0)
-#endif
-
-#ifdef CONFIG_SA1100_BSA1110
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_BSA1110
-# endif
-# define machine_is_bsa1110()	(machine_arch_type == MACH_TYPE_BSA1110)
-#else
-# define machine_is_bsa1110()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_POWERPIN
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_POWERPIN
-# endif
-# define machine_is_powerpin()	(machine_arch_type == MACH_TYPE_POWERPIN)
-#else
-# define machine_is_powerpin()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_OPENARM
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_OPENARM
-# endif
-# define machine_is_openarm()	(machine_arch_type == MACH_TYPE_OPENARM)
-#else
-# define machine_is_openarm()	(0)
-#endif
-
-#ifdef CONFIG_SA1100_WHITECHAPEL
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_WHITECHAPEL
-# endif
-# define machine_is_whitechapel()	(machine_arch_type == MACH_TYPE_WHITECHAPEL)
-#else
-# define machine_is_whitechapel()	(0)
-#endif
-
-#ifdef CONFIG_SA1100_H3100
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_H3100
-# endif
-# define machine_is_h3100()	(machine_arch_type == MACH_TYPE_H3100)
-#else
-# define machine_is_h3100()	(0)
-#endif
-
-#ifdef CONFIG_SA1100_H3800
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_H3800
-# endif
-# define machine_is_h3800()	(machine_arch_type == MACH_TYPE_H3800)
-#else
-# define machine_is_h3800()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_BLUE_V1
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_BLUE_V1
-# endif
-# define machine_is_blue_v1()	(machine_arch_type == MACH_TYPE_BLUE_V1)
-#else
-# define machine_is_blue_v1()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_PXA_CERF
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PXA_CERF
-# endif
-# define machine_is_pxa_cerf()	(machine_arch_type == MACH_TYPE_PXA_CERF)
-#else
-# define machine_is_pxa_cerf()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_ARM7TEVB
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ARM7TEVB
-# endif
-# define machine_is_arm7tevb()	(machine_arch_type == MACH_TYPE_ARM7TEVB)
-#else
-# define machine_is_arm7tevb()	(0)
-#endif
-
-#ifdef CONFIG_SA1100_D7400
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_D7400
-# endif
-# define machine_is_d7400()	(machine_arch_type == MACH_TYPE_D7400)
-#else
-# define machine_is_d7400()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_PIRANHA
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PIRANHA
-# endif
-# define machine_is_piranha()	(machine_arch_type == MACH_TYPE_PIRANHA)
-#else
-# define machine_is_piranha()	(0)
-#endif
-
-#ifdef CONFIG_SA1100_SBCAMELOT
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SBCAMELOT
-# endif
-# define machine_is_sbcamelot()	(machine_arch_type == MACH_TYPE_SBCAMELOT)
-#else
-# define machine_is_sbcamelot()	(0)
-#endif
-
-#ifdef CONFIG_SA1100_KINGS
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_KINGS
-# endif
-# define machine_is_kings()	(machine_arch_type == MACH_TYPE_KINGS)
-#else
-# define machine_is_kings()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_SMDK2400
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SMDK2400
-# endif
-# define machine_is_smdk2400()	(machine_arch_type == MACH_TYPE_SMDK2400)
-#else
-# define machine_is_smdk2400()	(0)
-#endif
-
-#ifdef CONFIG_SA1100_COLLIE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_COLLIE
-# endif
-# define machine_is_collie()	(machine_arch_type == MACH_TYPE_COLLIE)
-#else
-# define machine_is_collie()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_IDR
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_IDR
-# endif
-# define machine_is_idr()	(machine_arch_type == MACH_TYPE_IDR)
-#else
-# define machine_is_idr()	(0)
-#endif
-
-#ifdef CONFIG_SA1100_BADGE4
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_BADGE4
-# endif
-# define machine_is_badge4()	(machine_arch_type == MACH_TYPE_BADGE4)
-#else
-# define machine_is_badge4()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_WEBNET
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_WEBNET
-# endif
-# define machine_is_webnet()	(machine_arch_type == MACH_TYPE_WEBNET)
-#else
-# define machine_is_webnet()	(0)
-#endif
-
-#ifdef CONFIG_SA1100_D7300
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_D7300
-# endif
-# define machine_is_d7300()	(machine_arch_type == MACH_TYPE_D7300)
-#else
-# define machine_is_d7300()	(0)
-#endif
-
-#ifdef CONFIG_SA1100_CEP
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CEP
-# endif
-# define machine_is_cep()	(machine_arch_type == MACH_TYPE_CEP)
-#else
-# define machine_is_cep()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_FORTUNET
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_FORTUNET
-# endif
-# define machine_is_fortunet()	(machine_arch_type == MACH_TYPE_FORTUNET)
-#else
-# define machine_is_fortunet()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_VC547X
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_VC547X
-# endif
-# define machine_is_vc547x()	(machine_arch_type == MACH_TYPE_VC547X)
-#else
-# define machine_is_vc547x()	(0)
-#endif
-
-#ifdef CONFIG_SA1100_FILEWALKER
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_FILEWALKER
-# endif
-# define machine_is_filewalker()	(machine_arch_type == MACH_TYPE_FILEWALKER)
-#else
-# define machine_is_filewalker()	(0)
-#endif
-
-#ifdef CONFIG_SA1100_NETGATEWAY
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_NETGATEWAY
-# endif
-# define machine_is_netgateway()	(machine_arch_type == MACH_TYPE_NETGATEWAY)
-#else
-# define machine_is_netgateway()	(0)
-#endif
-
-#ifdef CONFIG_SA1100_SYMBOL2800
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SYMBOL2800
-# endif
-# define machine_is_symbol2800()	(machine_arch_type == MACH_TYPE_SYMBOL2800)
-#else
-# define machine_is_symbol2800()	(0)
-#endif
-
-#ifdef CONFIG_SA1100_SUNS
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SUNS
-# endif
-# define machine_is_suns()	(machine_arch_type == MACH_TYPE_SUNS)
-#else
-# define machine_is_suns()	(0)
-#endif
-
-#ifdef CONFIG_SA1100_FRODO
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_FRODO
-# endif
-# define machine_is_frodo()	(machine_arch_type == MACH_TYPE_FRODO)
-#else
-# define machine_is_frodo()	(0)
-#endif
-
-#ifdef CONFIG_SA1100_MACH_TYTE_MS301
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MACH_TYTE_MS301
-# endif
-# define machine_is_ms301()	(machine_arch_type == MACH_TYPE_MACH_TYTE_MS301)
-#else
-# define machine_is_ms301()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_MX1ADS
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MX1ADS
-# endif
-# define machine_is_mx1ads()	(machine_arch_type == MACH_TYPE_MX1ADS)
-#else
-# define machine_is_mx1ads()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_H7201
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_H7201
-# endif
-# define machine_is_h7201()	(machine_arch_type == MACH_TYPE_H7201)
-#else
-# define machine_is_h7201()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_H7202
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_H7202
-# endif
-# define machine_is_h7202()	(machine_arch_type == MACH_TYPE_H7202)
-#else
-# define machine_is_h7202()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_AMICO
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_AMICO
-# endif
-# define machine_is_amico()	(machine_arch_type == MACH_TYPE_AMICO)
-#else
-# define machine_is_amico()	(0)
-#endif
-
-#ifdef CONFIG_SA1100_IAM
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_IAM
-# endif
-# define machine_is_iam()	(machine_arch_type == MACH_TYPE_IAM)
-#else
-# define machine_is_iam()	(0)
-#endif
-
-#ifdef CONFIG_SA1100_TT530
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TT530
-# endif
-# define machine_is_tt530()	(machine_arch_type == MACH_TYPE_TT530)
-#else
-# define machine_is_tt530()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_SAM2400
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SAM2400
-# endif
-# define machine_is_sam2400()	(machine_arch_type == MACH_TYPE_SAM2400)
-#else
-# define machine_is_sam2400()	(0)
-#endif
-
-#ifdef CONFIG_SA1100_JORNADA56X
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_JORNADA56X
-# endif
-# define machine_is_jornada56x()	(machine_arch_type == MACH_TYPE_JORNADA56X)
-#else
-# define machine_is_jornada56x()	(0)
-#endif
-
-#ifdef CONFIG_SA1100_ACTIVE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ACTIVE
-# endif
-# define machine_is_active()	(machine_arch_type == MACH_TYPE_ACTIVE)
-#else
-# define machine_is_active()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_IQ80321
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_IQ80321
-# endif
-# define machine_is_iq80321()	(machine_arch_type == MACH_TYPE_IQ80321)
-#else
-# define machine_is_iq80321()	(0)
-#endif
-
-#ifdef CONFIG_SA1100_WID
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_WID
-# endif
-# define machine_is_wid()	(machine_arch_type == MACH_TYPE_WID)
-#else
-# define machine_is_wid()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_SABINAL
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SABINAL
-# endif
-# define machine_is_sabinal()	(machine_arch_type == MACH_TYPE_SABINAL)
-#else
-# define machine_is_sabinal()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_IXP425_MATACUMBE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_IXP425_MATACUMBE
-# endif
-# define machine_is_ixp425_matacumbe()	(machine_arch_type == MACH_TYPE_IXP425_MATACUMBE)
-#else
-# define machine_is_ixp425_matacumbe()	(0)
-#endif
-
-#ifdef CONFIG_SA1100_MINIPRINT
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MINIPRINT
-# endif
-# define machine_is_miniprint()	(machine_arch_type == MACH_TYPE_MINIPRINT)
-#else
-# define machine_is_miniprint()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_ADM510X
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ADM510X
-# endif
-# define machine_is_adm510x()	(machine_arch_type == MACH_TYPE_ADM510X)
-#else
-# define machine_is_adm510x()	(0)
-#endif
-
-#ifdef CONFIG_SA1100_SVS200
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SVS200
-# endif
-# define machine_is_svs200()	(machine_arch_type == MACH_TYPE_SVS200)
-#else
-# define machine_is_svs200()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_ATG_TCU
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ATG_TCU
-# endif
-# define machine_is_atg_tcu()	(machine_arch_type == MACH_TYPE_ATG_TCU)
-#else
-# define machine_is_atg_tcu()	(0)
-#endif
-
-#ifdef CONFIG_SA1100_JORNADA820
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_JORNADA820
-# endif
-# define machine_is_jornada820()	(machine_arch_type == MACH_TYPE_JORNADA820)
-#else
-# define machine_is_jornada820()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_S3C44B0
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_S3C44B0
-# endif
-# define machine_is_s3c44b0()	(machine_arch_type == MACH_TYPE_S3C44B0)
-#else
-# define machine_is_s3c44b0()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_MARGIS2
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MARGIS2
-# endif
-# define machine_is_margis2()	(machine_arch_type == MACH_TYPE_MARGIS2)
-#else
-# define machine_is_margis2()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_KS8695
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_KS8695
-# endif
-# define machine_is_ks8695()	(machine_arch_type == MACH_TYPE_KS8695)
-#else
-# define machine_is_ks8695()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_BRH
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_BRH
-# endif
-# define machine_is_brh()	(machine_arch_type == MACH_TYPE_BRH)
-#else
-# define machine_is_brh()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_S3C2410
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_S3C2410
-# endif
-# define machine_is_s3c2410()	(machine_arch_type == MACH_TYPE_S3C2410)
-#else
-# define machine_is_s3c2410()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_POSSIO_PX30
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_POSSIO_PX30
-# endif
-# define machine_is_possio_px30()	(machine_arch_type == MACH_TYPE_POSSIO_PX30)
-#else
-# define machine_is_possio_px30()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_S3C2800
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_S3C2800
-# endif
-# define machine_is_s3c2800()	(machine_arch_type == MACH_TYPE_S3C2800)
-#else
-# define machine_is_s3c2800()	(0)
-#endif
-
-#ifdef CONFIG_SA1100_FLEETWOOD
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_FLEETWOOD
-# endif
-# define machine_is_fleetwood()	(machine_arch_type == MACH_TYPE_FLEETWOOD)
-#else
-# define machine_is_fleetwood()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_OMAHA
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_OMAHA
-# endif
-# define machine_is_omaha()	(machine_arch_type == MACH_TYPE_OMAHA)
-#else
-# define machine_is_omaha()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_TA7
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TA7
-# endif
-# define machine_is_ta7()	(machine_arch_type == MACH_TYPE_TA7)
-#else
-# define machine_is_ta7()	(0)
-#endif
-
-#ifdef CONFIG_SA1100_NOVA
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_NOVA
-# endif
-# define machine_is_nova()	(machine_arch_type == MACH_TYPE_NOVA)
-#else
-# define machine_is_nova()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_HMK
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_HMK
-# endif
-# define machine_is_hmk()	(machine_arch_type == MACH_TYPE_HMK)
-#else
-# define machine_is_hmk()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_KARO
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_KARO
-# endif
-# define machine_is_karo()	(machine_arch_type == MACH_TYPE_KARO)
-#else
-# define machine_is_karo()	(0)
-#endif
-
-#ifdef CONFIG_SA1100_FESTER
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_FESTER
-# endif
-# define machine_is_fester()	(machine_arch_type == MACH_TYPE_FESTER)
-#else
-# define machine_is_fester()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_GPI
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_GPI
-# endif
-# define machine_is_gpi()	(machine_arch_type == MACH_TYPE_GPI)
-#else
-# define machine_is_gpi()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_SMDK2410
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SMDK2410
-# endif
-# define machine_is_smdk2410()	(machine_arch_type == MACH_TYPE_SMDK2410)
-#else
-# define machine_is_smdk2410()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_I519
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_I519
-# endif
-# define machine_is_i519()	(machine_arch_type == MACH_TYPE_I519)
-#else
-# define machine_is_i519()	(0)
-#endif
-
-#ifdef CONFIG_SA1100_NEXIO
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_NEXIO
-# endif
-# define machine_is_nexio()	(machine_arch_type == MACH_TYPE_NEXIO)
-#else
-# define machine_is_nexio()	(0)
-#endif
-
-#ifdef CONFIG_SA1100_BITBOX
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_BITBOX
-# endif
-# define machine_is_bitbox()	(machine_arch_type == MACH_TYPE_BITBOX)
-#else
-# define machine_is_bitbox()	(0)
-#endif
-
-#ifdef CONFIG_SA1100_G200
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_G200
-# endif
-# define machine_is_g200()	(machine_arch_type == MACH_TYPE_G200)
-#else
-# define machine_is_g200()	(0)
-#endif
-
-#ifdef CONFIG_SA1100_GILL
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_GILL
-# endif
-# define machine_is_gill()	(machine_arch_type == MACH_TYPE_GILL)
-#else
-# define machine_is_gill()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_PXA_MERCURY
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PXA_MERCURY
-# endif
-# define machine_is_pxa_mercury()	(machine_arch_type == MACH_TYPE_PXA_MERCURY)
-#else
-# define machine_is_pxa_mercury()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_CEIVA
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CEIVA
-# endif
-# define machine_is_ceiva()	(machine_arch_type == MACH_TYPE_CEIVA)
-#else
-# define machine_is_ceiva()	(0)
-#endif
-
-#ifdef CONFIG_SA1100_FRET
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_FRET
-# endif
-# define machine_is_fret()	(machine_arch_type == MACH_TYPE_FRET)
-#else
-# define machine_is_fret()	(0)
-#endif
-
-#ifdef CONFIG_SA1100_EMAILPHONE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_EMAILPHONE
-# endif
-# define machine_is_emailphone()	(machine_arch_type == MACH_TYPE_EMAILPHONE)
-#else
-# define machine_is_emailphone()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_H3900
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_H3900
-# endif
-# define machine_is_h3900()	(machine_arch_type == MACH_TYPE_H3900)
-#else
-# define machine_is_h3900()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_PXA1
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PXA1
-# endif
-# define machine_is_pxa1()	(machine_arch_type == MACH_TYPE_PXA1)
-#else
-# define machine_is_pxa1()	(0)
-#endif
-
-#ifdef CONFIG_SA1100_KOAN369
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_KOAN369
-# endif
-# define machine_is_koan369()	(machine_arch_type == MACH_TYPE_KOAN369)
-#else
-# define machine_is_koan369()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_COGENT
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_COGENT
-# endif
-# define machine_is_cogent()	(machine_arch_type == MACH_TYPE_COGENT)
-#else
-# define machine_is_cogent()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_ESL_SIMPUTER
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ESL_SIMPUTER
-# endif
-# define machine_is_esl_simputer()	(machine_arch_type == MACH_TYPE_ESL_SIMPUTER)
-#else
-# define machine_is_esl_simputer()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_ESL_SIMPUTER_CLR
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ESL_SIMPUTER_CLR
-# endif
-# define machine_is_esl_simputer_clr()	(machine_arch_type == MACH_TYPE_ESL_SIMPUTER_CLR)
-#else
-# define machine_is_esl_simputer_clr()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_ESL_SIMPUTER_BW
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ESL_SIMPUTER_BW
-# endif
-# define machine_is_esl_simputer_bw()	(machine_arch_type == MACH_TYPE_ESL_SIMPUTER_BW)
-#else
-# define machine_is_esl_simputer_bw()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_HHP_CRADLE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_HHP_CRADLE
-# endif
-# define machine_is_hhp_cradle()	(machine_arch_type == MACH_TYPE_HHP_CRADLE)
-#else
-# define machine_is_hhp_cradle()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_HE500
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_HE500
-# endif
-# define machine_is_he500()	(machine_arch_type == MACH_TYPE_HE500)
-#else
-# define machine_is_he500()	(0)
-#endif
-
-#ifdef CONFIG_SA1100_INHANDELF2
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_INHANDELF2
-# endif
-# define machine_is_inhandelf2()	(machine_arch_type == MACH_TYPE_INHANDELF2)
-#else
-# define machine_is_inhandelf2()	(0)
-#endif
-
-#ifdef CONFIG_SA1100_INHANDFTIP
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_INHANDFTIP
-# endif
-# define machine_is_inhandftip()	(machine_arch_type == MACH_TYPE_INHANDFTIP)
-#else
-# define machine_is_inhandftip()	(0)
-#endif
-
-#ifdef CONFIG_SA1100_DNP1110
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_DNP1110
-# endif
-# define machine_is_dnp1110()	(machine_arch_type == MACH_TYPE_DNP1110)
-#else
-# define machine_is_dnp1110()	(0)
-#endif
-
-#ifdef CONFIG_SA1100_PNP1110
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PNP1110
-# endif
-# define machine_is_pnp1110()	(machine_arch_type == MACH_TYPE_PNP1110)
-#else
-# define machine_is_pnp1110()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_CSB226
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CSB226
-# endif
-# define machine_is_csb226()	(machine_arch_type == MACH_TYPE_CSB226)
-#else
-# define machine_is_csb226()	(0)
-#endif
-
-#ifdef CONFIG_SA1100_ARNOLD
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ARNOLD
-# endif
-# define machine_is_arnold()	(machine_arch_type == MACH_TYPE_ARNOLD)
-#else
-# define machine_is_arnold()	(0)
-#endif
-
-#ifdef CONFIG_MACH_VOICEBLUE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_VOICEBLUE
-# endif
-# define machine_is_voiceblue()	(machine_arch_type == MACH_TYPE_VOICEBLUE)
-#else
-# define machine_is_voiceblue()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_JZ8028
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_JZ8028
-# endif
-# define machine_is_jz8028()	(machine_arch_type == MACH_TYPE_JZ8028)
-#else
-# define machine_is_jz8028()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_H5400
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_H5400
-# endif
-# define machine_is_h5400()	(machine_arch_type == MACH_TYPE_H5400)
-#else
-# define machine_is_h5400()	(0)
-#endif
-
-#ifdef CONFIG_SA1100_FORTE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_FORTE
-# endif
-# define machine_is_forte()	(machine_arch_type == MACH_TYPE_FORTE)
-#else
-# define machine_is_forte()	(0)
-#endif
-
-#ifdef CONFIG_SA1100_ACAM
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ACAM
-# endif
-# define machine_is_acam()	(machine_arch_type == MACH_TYPE_ACAM)
-#else
-# define machine_is_acam()	(0)
-#endif
-
-#ifdef CONFIG_SA1100_ABOX
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ABOX
-# endif
-# define machine_is_abox()	(machine_arch_type == MACH_TYPE_ABOX)
-#else
-# define machine_is_abox()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_ATMEL
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ATMEL
-# endif
-# define machine_is_atmel()	(machine_arch_type == MACH_TYPE_ATMEL)
-#else
-# define machine_is_atmel()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_SITSANG
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SITSANG
-# endif
-# define machine_is_sitsang()	(machine_arch_type == MACH_TYPE_SITSANG)
-#else
-# define machine_is_sitsang()	(0)
-#endif
-
-#ifdef CONFIG_SA1100_CPU1110LCDNET
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CPU1110LCDNET
-# endif
-# define machine_is_cpu1110lcdnet()	(machine_arch_type == MACH_TYPE_CPU1110LCDNET)
-#else
-# define machine_is_cpu1110lcdnet()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_MPL_VCMA9
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MPL_VCMA9
-# endif
-# define machine_is_mpl_vcma9()	(machine_arch_type == MACH_TYPE_MPL_VCMA9)
-#else
-# define machine_is_mpl_vcma9()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_OPUS_A1
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_OPUS_A1
-# endif
-# define machine_is_opus_a1()	(machine_arch_type == MACH_TYPE_OPUS_A1)
-#else
-# define machine_is_opus_a1()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_DAYTONA
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_DAYTONA
-# endif
-# define machine_is_daytona()	(machine_arch_type == MACH_TYPE_DAYTONA)
-#else
-# define machine_is_daytona()	(0)
-#endif
-
-#ifdef CONFIG_SA1100_KILLBEAR
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_KILLBEAR
-# endif
-# define machine_is_killbear()	(machine_arch_type == MACH_TYPE_KILLBEAR)
-#else
-# define machine_is_killbear()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_YOHO
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_YOHO
-# endif
-# define machine_is_yoho()	(machine_arch_type == MACH_TYPE_YOHO)
-#else
-# define machine_is_yoho()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_JASPER
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_JASPER
-# endif
-# define machine_is_jasper()	(machine_arch_type == MACH_TYPE_JASPER)
-#else
-# define machine_is_jasper()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_DSC25
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_DSC25
-# endif
-# define machine_is_dsc25()	(machine_arch_type == MACH_TYPE_DSC25)
-#else
-# define machine_is_dsc25()	(0)
-#endif
-
-#ifdef CONFIG_MACH_OMAP_INNOVATOR
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_OMAP_INNOVATOR
-# endif
-# define machine_is_omap_innovator()	(machine_arch_type == MACH_TYPE_OMAP_INNOVATOR)
-#else
-# define machine_is_omap_innovator()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_RAMSES
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_RAMSES
-# endif
-# define machine_is_mnci()	(machine_arch_type == MACH_TYPE_RAMSES)
-#else
-# define machine_is_mnci()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_S28X
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_S28X
-# endif
-# define machine_is_s28x()	(machine_arch_type == MACH_TYPE_S28X)
-#else
-# define machine_is_s28x()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_MPORT3
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MPORT3
-# endif
-# define machine_is_mport3()	(machine_arch_type == MACH_TYPE_MPORT3)
-#else
-# define machine_is_mport3()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_PXA_EAGLE250
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PXA_EAGLE250
-# endif
-# define machine_is_pxa_eagle250()	(machine_arch_type == MACH_TYPE_PXA_EAGLE250)
-#else
-# define machine_is_pxa_eagle250()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_PDB
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PDB
-# endif
-# define machine_is_pdb()	(machine_arch_type == MACH_TYPE_PDB)
-#else
-# define machine_is_pdb()	(0)
-#endif
-
-#ifdef CONFIG_SA1100_BLUE_2G
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_BLUE_2G
-# endif
-# define machine_is_blue_2g()	(machine_arch_type == MACH_TYPE_BLUE_2G)
-#else
-# define machine_is_blue_2g()	(0)
-#endif
-
-#ifdef CONFIG_SA1100_BLUEARCH
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_BLUEARCH
-# endif
-# define machine_is_bluearch()	(machine_arch_type == MACH_TYPE_BLUEARCH)
-#else
-# define machine_is_bluearch()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_IXDP2400
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_IXDP2400
-# endif
-# define machine_is_ixdp2400()	(machine_arch_type == MACH_TYPE_IXDP2400)
-#else
-# define machine_is_ixdp2400()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_IXDP2800
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_IXDP2800
-# endif
-# define machine_is_ixdp2800()	(machine_arch_type == MACH_TYPE_IXDP2800)
-#else
-# define machine_is_ixdp2800()	(0)
-#endif
-
-#ifdef CONFIG_SA1100_EXPLORER
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_EXPLORER
-# endif
-# define machine_is_explorer()	(machine_arch_type == MACH_TYPE_EXPLORER)
-#else
-# define machine_is_explorer()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_IXDP425
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_IXDP425
-# endif
-# define machine_is_ixdp425()	(machine_arch_type == MACH_TYPE_IXDP425)
-#else
-# define machine_is_ixdp425()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_CHIMP
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CHIMP
-# endif
-# define machine_is_chimp()	(machine_arch_type == MACH_TYPE_CHIMP)
-#else
-# define machine_is_chimp()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_STORK_NEST
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_STORK_NEST
-# endif
-# define machine_is_stork_nest()	(machine_arch_type == MACH_TYPE_STORK_NEST)
-#else
-# define machine_is_stork_nest()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_STORK_EGG
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_STORK_EGG
-# endif
-# define machine_is_stork_egg()	(machine_arch_type == MACH_TYPE_STORK_EGG)
-#else
-# define machine_is_stork_egg()	(0)
-#endif
-
-#ifdef CONFIG_SA1100_WISMO
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_WISMO
-# endif
-# define machine_is_wismo()	(machine_arch_type == MACH_TYPE_WISMO)
-#else
-# define machine_is_wismo()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_EZLINX
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_EZLINX
-# endif
-# define machine_is_ezlinx()	(machine_arch_type == MACH_TYPE_EZLINX)
-#else
-# define machine_is_ezlinx()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_AT91RM9200
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_AT91RM9200
-# endif
-# define machine_is_at91rm9200()	(machine_arch_type == MACH_TYPE_AT91RM9200)
-#else
-# define machine_is_at91rm9200()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_ADTECH_ORION
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ADTECH_ORION
-# endif
-# define machine_is_adtech_orion()	(machine_arch_type == MACH_TYPE_ADTECH_ORION)
-#else
-# define machine_is_adtech_orion()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_NEPTUNE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_NEPTUNE
-# endif
-# define machine_is_neptune()	(machine_arch_type == MACH_TYPE_NEPTUNE)
-#else
-# define machine_is_neptune()	(0)
-#endif
-
-#ifdef CONFIG_SA1100_HACKKIT
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_HACKKIT
-# endif
-# define machine_is_hackkit()	(machine_arch_type == MACH_TYPE_HACKKIT)
-#else
-# define machine_is_hackkit()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_PXA_WINS30
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PXA_WINS30
-# endif
-# define machine_is_pxa_wins30()	(machine_arch_type == MACH_TYPE_PXA_WINS30)
-#else
-# define machine_is_pxa_wins30()	(0)
-#endif
-
-#ifdef CONFIG_SA1100_LAVINNA
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_LAVINNA
-# endif
-# define machine_is_lavinna()	(machine_arch_type == MACH_TYPE_LAVINNA)
-#else
-# define machine_is_lavinna()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_PXA_UENGINE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PXA_UENGINE
-# endif
-# define machine_is_pxa_uengine()	(machine_arch_type == MACH_TYPE_PXA_UENGINE)
-#else
-# define machine_is_pxa_uengine()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_INNOKOM
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_INNOKOM
-# endif
-# define machine_is_innokom()	(machine_arch_type == MACH_TYPE_INNOKOM)
-#else
-# define machine_is_innokom()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_BMS
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_BMS
-# endif
-# define machine_is_bms()	(machine_arch_type == MACH_TYPE_BMS)
-#else
-# define machine_is_bms()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_IXCDP1100
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_IXCDP1100
-# endif
-# define machine_is_ixcdp1100()	(machine_arch_type == MACH_TYPE_IXCDP1100)
-#else
-# define machine_is_ixcdp1100()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_PRPMC1100
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PRPMC1100
-# endif
-# define machine_is_prpmc1100()	(machine_arch_type == MACH_TYPE_PRPMC1100)
-#else
-# define machine_is_prpmc1100()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_AT91RM9200DK
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_AT91RM9200DK
-# endif
-# define machine_is_at91rm9200dk()	(machine_arch_type == MACH_TYPE_AT91RM9200DK)
-#else
-# define machine_is_at91rm9200dk()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_ARMSTICK
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ARMSTICK
-# endif
-# define machine_is_armstick()	(machine_arch_type == MACH_TYPE_ARMSTICK)
-#else
-# define machine_is_armstick()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_ARMONIE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ARMONIE
-# endif
-# define machine_is_armonie()	(machine_arch_type == MACH_TYPE_ARMONIE)
-#else
-# define machine_is_armonie()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_MPORT1
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MPORT1
-# endif
-# define machine_is_mport1()	(machine_arch_type == MACH_TYPE_MPORT1)
-#else
-# define machine_is_mport1()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_S3C5410
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_S3C5410
-# endif
-# define machine_is_s3c5410()	(machine_arch_type == MACH_TYPE_S3C5410)
-#else
-# define machine_is_s3c5410()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_ZCP320A
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ZCP320A
-# endif
-# define machine_is_zcp320a()	(machine_arch_type == MACH_TYPE_ZCP320A)
-#else
-# define machine_is_zcp320a()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_I_BOX
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_I_BOX
-# endif
-# define machine_is_i_box()	(machine_arch_type == MACH_TYPE_I_BOX)
-#else
-# define machine_is_i_box()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_STLC1502
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_STLC1502
-# endif
-# define machine_is_stlc1502()	(machine_arch_type == MACH_TYPE_STLC1502)
-#else
-# define machine_is_stlc1502()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_SIREN
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SIREN
-# endif
-# define machine_is_siren()	(machine_arch_type == MACH_TYPE_SIREN)
-#else
-# define machine_is_siren()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_GREENLAKE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_GREENLAKE
-# endif
-# define machine_is_greenlake()	(machine_arch_type == MACH_TYPE_GREENLAKE)
-#else
-# define machine_is_greenlake()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_ARGUS
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ARGUS
-# endif
-# define machine_is_argus()	(machine_arch_type == MACH_TYPE_ARGUS)
-#else
-# define machine_is_argus()	(0)
-#endif
-
-#ifdef CONFIG_SA1100_COMBADGE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_COMBADGE
-# endif
-# define machine_is_combadge()	(machine_arch_type == MACH_TYPE_COMBADGE)
-#else
-# define machine_is_combadge()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_ROKEPXA
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ROKEPXA
-# endif
-# define machine_is_rokepxa()	(machine_arch_type == MACH_TYPE_ROKEPXA)
-#else
-# define machine_is_rokepxa()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_CINTEGRATOR
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CINTEGRATOR
-# endif
-# define machine_is_cintegrator()	(machine_arch_type == MACH_TYPE_CINTEGRATOR)
-#else
-# define machine_is_cintegrator()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_GUIDEA07
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_GUIDEA07
-# endif
-# define machine_is_guidea07()	(machine_arch_type == MACH_TYPE_GUIDEA07)
-#else
-# define machine_is_guidea07()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_TAT257
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TAT257
-# endif
-# define machine_is_tat257()	(machine_arch_type == MACH_TYPE_TAT257)
-#else
-# define machine_is_tat257()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_IGP2425
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_IGP2425
-# endif
-# define machine_is_igp2425()	(machine_arch_type == MACH_TYPE_IGP2425)
-#else
-# define machine_is_igp2425()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_BLUEGRAMMA
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_BLUEGRAMMA
-# endif
-# define machine_is_bluegrama()	(machine_arch_type == MACH_TYPE_BLUEGRAMMA)
-#else
-# define machine_is_bluegrama()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_IPOD
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_IPOD
-# endif
-# define machine_is_ipod()	(machine_arch_type == MACH_TYPE_IPOD)
-#else
-# define machine_is_ipod()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_ADSBITSYX
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ADSBITSYX
-# endif
-# define machine_is_adsbitsyx()	(machine_arch_type == MACH_TYPE_ADSBITSYX)
-#else
-# define machine_is_adsbitsyx()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_TRIZEPS2
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TRIZEPS2
-# endif
-# define machine_is_trizeps2()	(machine_arch_type == MACH_TYPE_TRIZEPS2)
-#else
-# define machine_is_trizeps2()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_VIPER
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_VIPER
-# endif
-# define machine_is_viper()	(machine_arch_type == MACH_TYPE_VIPER)
-#else
-# define machine_is_viper()	(0)
-#endif
-
-#ifdef CONFIG_SA1100_ADSBITSYPLUS
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ADSBITSYPLUS
-# endif
-# define machine_is_adsbitsyplus()	(machine_arch_type == MACH_TYPE_ADSBITSYPLUS)
-#else
-# define machine_is_adsbitsyplus()	(0)
-#endif
-
-#ifdef CONFIG_SA1100_ADSAGC
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ADSAGC
-# endif
-# define machine_is_adsagc()	(machine_arch_type == MACH_TYPE_ADSAGC)
-#else
-# define machine_is_adsagc()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_STP7312
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_STP7312
-# endif
-# define machine_is_stp7312()	(machine_arch_type == MACH_TYPE_STP7312)
-#else
-# define machine_is_stp7312()	(0)
-#endif
-
-#ifdef CONFIG_MACH_NX_PHNX
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_NX_PHNX
-# endif
-# define machine_is_nx_phnx()	(machine_arch_type == MACH_TYPE_NX_PHNX)
-#else
-# define machine_is_nx_phnx()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_WEP_EP250
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_WEP_EP250
-# endif
-# define machine_is_wep_ep250()	(machine_arch_type == MACH_TYPE_WEP_EP250)
-#else
-# define machine_is_wep_ep250()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_INHANDELF3
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_INHANDELF3
-# endif
-# define machine_is_inhandelf3()	(machine_arch_type == MACH_TYPE_INHANDELF3)
-#else
-# define machine_is_inhandelf3()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_ADI_COYOTE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ADI_COYOTE
-# endif
-# define machine_is_adi_coyote()	(machine_arch_type == MACH_TYPE_ADI_COYOTE)
-#else
-# define machine_is_adi_coyote()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_IYONIX
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_IYONIX
-# endif
-# define machine_is_iyonix()	(machine_arch_type == MACH_TYPE_IYONIX)
-#else
-# define machine_is_iyonix()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_DAMICAM_SA1110
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_DAMICAM_SA1110
-# endif
-# define machine_is_damicam1()	(machine_arch_type == MACH_TYPE_DAMICAM_SA1110)
-#else
-# define machine_is_damicam1()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_MEG03
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MEG03
-# endif
-# define machine_is_meg03()	(machine_arch_type == MACH_TYPE_MEG03)
-#else
-# define machine_is_meg03()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_PXA_WHITECHAPEL
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PXA_WHITECHAPEL
-# endif
-# define machine_is_pxa_whitechapel()	(machine_arch_type == MACH_TYPE_PXA_WHITECHAPEL)
-#else
-# define machine_is_pxa_whitechapel()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_NWSC
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_NWSC
-# endif
-# define machine_is_nwsc()	(machine_arch_type == MACH_TYPE_NWSC)
-#else
-# define machine_is_nwsc()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_NWLARM
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_NWLARM
-# endif
-# define machine_is_nwlarm()	(machine_arch_type == MACH_TYPE_NWLARM)
-#else
-# define machine_is_nwlarm()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_IXP425_MGUARD
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_IXP425_MGUARD
-# endif
-# define machine_is_ixp425_mguard()	(machine_arch_type == MACH_TYPE_IXP425_MGUARD)
-#else
-# define machine_is_ixp425_mguard()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_PXA_NETDCU4
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PXA_NETDCU4
-# endif
-# define machine_is_pxa_netdcu4()	(machine_arch_type == MACH_TYPE_PXA_NETDCU4)
-#else
-# define machine_is_pxa_netdcu4()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_IXDP2401
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_IXDP2401
-# endif
-# define machine_is_ixdp2401()	(machine_arch_type == MACH_TYPE_IXDP2401)
-#else
-# define machine_is_ixdp2401()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_IXDP2801
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_IXDP2801
-# endif
-# define machine_is_ixdp2801()	(machine_arch_type == MACH_TYPE_IXDP2801)
-#else
-# define machine_is_ixdp2801()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_ZODIAC
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ZODIAC
-# endif
-# define machine_is_zodiac()	(machine_arch_type == MACH_TYPE_ZODIAC)
-#else
-# define machine_is_zodiac()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_ARMMODUL
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ARMMODUL
-# endif
-# define machine_is_armmodul()	(machine_arch_type == MACH_TYPE_ARMMODUL)
-#else
-# define machine_is_armmodul()	(0)
-#endif
-
-#ifdef CONFIG_SA1100_KETOP
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_KETOP
-# endif
-# define machine_is_ketop()	(machine_arch_type == MACH_TYPE_KETOP)
-#else
-# define machine_is_ketop()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_AV7200
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_AV7200
-# endif
-# define machine_is_av7200()	(machine_arch_type == MACH_TYPE_AV7200)
-#else
-# define machine_is_av7200()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_ARCH_TI925
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ARCH_TI925
-# endif
-# define machine_is_arch_ti925()	(machine_arch_type == MACH_TYPE_ARCH_TI925)
-#else
-# define machine_is_arch_ti925()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_ACQ200
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ACQ200
-# endif
-# define machine_is_acq200()	(machine_arch_type == MACH_TYPE_ACQ200)
-#else
-# define machine_is_acq200()	(0)
-#endif
-
-#ifdef CONFIG_SA1100_PT_DAFIT
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PT_DAFIT
-# endif
-# define machine_is_pt_dafit()	(machine_arch_type == MACH_TYPE_PT_DAFIT)
-#else
-# define machine_is_pt_dafit()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_IHBA
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_IHBA
-# endif
-# define machine_is_ihba()	(machine_arch_type == MACH_TYPE_IHBA)
-#else
-# define machine_is_ihba()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_QUINQUE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_QUINQUE
-# endif
-# define machine_is_quinque()	(machine_arch_type == MACH_TYPE_QUINQUE)
-#else
-# define machine_is_quinque()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_NIMBRAONE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_NIMBRAONE
-# endif
-# define machine_is_nimbraone()	(machine_arch_type == MACH_TYPE_NIMBRAONE)
-#else
-# define machine_is_nimbraone()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_NIMBRA29X
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_NIMBRA29X
-# endif
-# define machine_is_nimbra29x()	(machine_arch_type == MACH_TYPE_NIMBRA29X)
-#else
-# define machine_is_nimbra29x()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_NIMBRA210
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_NIMBRA210
-# endif
-# define machine_is_nimbra210()	(machine_arch_type == MACH_TYPE_NIMBRA210)
-#else
-# define machine_is_nimbra210()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_HHP_D95XX
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_HHP_D95XX
-# endif
-# define machine_is_hhp_d95xx()	(machine_arch_type == MACH_TYPE_HHP_D95XX)
-#else
-# define machine_is_hhp_d95xx()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_LABARM
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_LABARM
-# endif
-# define machine_is_labarm()	(machine_arch_type == MACH_TYPE_LABARM)
-#else
-# define machine_is_labarm()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_M825XX
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_M825XX
-# endif
-# define machine_is_m825xx()	(machine_arch_type == MACH_TYPE_M825XX)
-#else
-# define machine_is_m825xx()	(0)
-#endif
-
-#ifdef CONFIG_SA1100_M7100
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_M7100
-# endif
-# define machine_is_m7100()	(machine_arch_type == MACH_TYPE_M7100)
-#else
-# define machine_is_m7100()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_NIPC2
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_NIPC2
-# endif
-# define machine_is_nipc2()	(machine_arch_type == MACH_TYPE_NIPC2)
-#else
-# define machine_is_nipc2()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_FU7202
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_FU7202
-# endif
-# define machine_is_fu7202()	(machine_arch_type == MACH_TYPE_FU7202)
-#else
-# define machine_is_fu7202()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_ADSAGX
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ADSAGX
-# endif
-# define machine_is_adsagx()	(machine_arch_type == MACH_TYPE_ADSAGX)
-#else
-# define machine_is_adsagx()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_PXA_POOH
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PXA_POOH
-# endif
-# define machine_is_pxa_pooh()	(machine_arch_type == MACH_TYPE_PXA_POOH)
-#else
-# define machine_is_pxa_pooh()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_BANDON
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_BANDON
-# endif
-# define machine_is_bandon()	(machine_arch_type == MACH_TYPE_BANDON)
-#else
-# define machine_is_bandon()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_PCM7210
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PCM7210
-# endif
-# define machine_is_pcm7210()	(machine_arch_type == MACH_TYPE_PCM7210)
-#else
-# define machine_is_pcm7210()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_NMS9200
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_NMS9200
-# endif
-# define machine_is_nms9200()	(machine_arch_type == MACH_TYPE_NMS9200)
-#else
-# define machine_is_nms9200()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_LOGODL
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_LOGODL
-# endif
-# define machine_is_logodl()	(machine_arch_type == MACH_TYPE_LOGODL)
-#else
-# define machine_is_logodl()	(0)
-#endif
-
-#ifdef CONFIG_SA1100_M7140
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_M7140
-# endif
-# define machine_is_m7140()	(machine_arch_type == MACH_TYPE_M7140)
-#else
-# define machine_is_m7140()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_KOREBOT
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_KOREBOT
-# endif
-# define machine_is_korebot()	(machine_arch_type == MACH_TYPE_KOREBOT)
-#else
-# define machine_is_korebot()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_IQ31244
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_IQ31244
-# endif
-# define machine_is_iq31244()	(machine_arch_type == MACH_TYPE_IQ31244)
-#else
-# define machine_is_iq31244()	(0)
-#endif
-
-#ifdef CONFIG_SA1100_KOAN393
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_KOAN393
-# endif
-# define machine_is_koan393()	(machine_arch_type == MACH_TYPE_KOAN393)
-#else
-# define machine_is_koan393()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_INHANDFTIP3
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_INHANDFTIP3
-# endif
-# define machine_is_inhandftip3()	(machine_arch_type == MACH_TYPE_INHANDFTIP3)
-#else
-# define machine_is_inhandftip3()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_GONZO
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_GONZO
-# endif
-# define machine_is_gonzo()	(machine_arch_type == MACH_TYPE_GONZO)
-#else
-# define machine_is_gonzo()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_BAST
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_BAST
-# endif
-# define machine_is_bast()	(machine_arch_type == MACH_TYPE_BAST)
-#else
-# define machine_is_bast()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_SCANPASS
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SCANPASS
-# endif
-# define machine_is_scanpass()	(machine_arch_type == MACH_TYPE_SCANPASS)
-#else
-# define machine_is_scanpass()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_EP7312_POOH
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_EP7312_POOH
-# endif
-# define machine_is_ep7312_pooh()	(machine_arch_type == MACH_TYPE_EP7312_POOH)
-#else
-# define machine_is_ep7312_pooh()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_TA7S
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TA7S
-# endif
-# define machine_is_ta7s()	(machine_arch_type == MACH_TYPE_TA7S)
-#else
-# define machine_is_ta7s()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_TA7V
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TA7V
-# endif
-# define machine_is_ta7v()	(machine_arch_type == MACH_TYPE_TA7V)
-#else
-# define machine_is_ta7v()	(0)
-#endif
-
-#ifdef CONFIG_SA1100_ICARUS
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ICARUS
-# endif
-# define machine_is_icarus()	(machine_arch_type == MACH_TYPE_ICARUS)
-#else
-# define machine_is_icarus()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_H1900
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_H1900
-# endif
-# define machine_is_h1900()	(machine_arch_type == MACH_TYPE_H1900)
-#else
-# define machine_is_h1900()	(0)
-#endif
-
-#ifdef CONFIG_SA1100_GEMINI
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_GEMINI
-# endif
-# define machine_is_gemini()	(machine_arch_type == MACH_TYPE_GEMINI)
-#else
-# define machine_is_gemini()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_AXIM
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_AXIM
-# endif
-# define machine_is_axim()	(machine_arch_type == MACH_TYPE_AXIM)
-#else
-# define machine_is_axim()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_AUDIOTRON
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_AUDIOTRON
-# endif
-# define machine_is_audiotron()	(machine_arch_type == MACH_TYPE_AUDIOTRON)
-#else
-# define machine_is_audiotron()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_H2200
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_H2200
-# endif
-# define machine_is_h2200()	(machine_arch_type == MACH_TYPE_H2200)
-#else
-# define machine_is_h2200()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_LOOX600
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_LOOX600
-# endif
-# define machine_is_loox600()	(machine_arch_type == MACH_TYPE_LOOX600)
-#else
-# define machine_is_loox600()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_NIOP
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_NIOP
-# endif
-# define machine_is_niop()	(machine_arch_type == MACH_TYPE_NIOP)
-#else
-# define machine_is_niop()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_DM310
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_DM310
-# endif
-# define machine_is_dm310()	(machine_arch_type == MACH_TYPE_DM310)
-#else
-# define machine_is_dm310()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_SEEDPXA_C2
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SEEDPXA_C2
-# endif
-# define machine_is_seedpxa_c2()	(machine_arch_type == MACH_TYPE_SEEDPXA_C2)
-#else
-# define machine_is_seedpxa_c2()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_IXP4XX_MGUARD_PCI
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_IXP4XX_MGUARD_PCI
-# endif
-# define machine_is_ixp4xx_mguardpci()	(machine_arch_type == MACH_TYPE_IXP4XX_MGUARD_PCI)
-#else
-# define machine_is_ixp4xx_mguardpci()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_H1940
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_H1940
-# endif
-# define machine_is_h1940()	(machine_arch_type == MACH_TYPE_H1940)
-#else
-# define machine_is_h1940()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_SCORPIO
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SCORPIO
-# endif
-# define machine_is_scorpio()	(machine_arch_type == MACH_TYPE_SCORPIO)
-#else
-# define machine_is_scorpio()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_VIVA
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_VIVA
-# endif
-# define machine_is_viva()	(machine_arch_type == MACH_TYPE_VIVA)
-#else
-# define machine_is_viva()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_PXA_XCARD
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PXA_XCARD
-# endif
-# define machine_is_pxa_xcard()	(machine_arch_type == MACH_TYPE_PXA_XCARD)
-#else
-# define machine_is_pxa_xcard()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_CSB335
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CSB335
-# endif
-# define machine_is_csb335()	(machine_arch_type == MACH_TYPE_CSB335)
-#else
-# define machine_is_csb335()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_IXRD425
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_IXRD425
-# endif
-# define machine_is_ixrd425()	(machine_arch_type == MACH_TYPE_IXRD425)
-#else
-# define machine_is_ixrd425()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_IQ80315
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_IQ80315
-# endif
-# define machine_is_iq80315()	(machine_arch_type == MACH_TYPE_IQ80315)
-#else
-# define machine_is_iq80315()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_NMP7312
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_NMP7312
-# endif
-# define machine_is_nmp7312()	(machine_arch_type == MACH_TYPE_NMP7312)
-#else
-# define machine_is_nmp7312()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_CX861XX
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CX861XX
-# endif
-# define machine_is_cx861xx()	(machine_arch_type == MACH_TYPE_CX861XX)
-#else
-# define machine_is_cx861xx()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_ENP2611
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ENP2611
-# endif
-# define machine_is_enp2611()	(machine_arch_type == MACH_TYPE_ENP2611)
-#else
-# define machine_is_enp2611()	(0)
-#endif
-
-#ifdef CONFIG_SA1100_XDA
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_XDA
-# endif
-# define machine_is_xda()	(machine_arch_type == MACH_TYPE_XDA)
-#else
-# define machine_is_xda()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_CSIR_IMS
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CSIR_IMS
-# endif
-# define machine_is_csir_ims()	(machine_arch_type == MACH_TYPE_CSIR_IMS)
-#else
-# define machine_is_csir_ims()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_IXP421_DNAEETH
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_IXP421_DNAEETH
-# endif
-# define machine_is_ixp421_dnaeeth()	(machine_arch_type == MACH_TYPE_IXP421_DNAEETH)
-#else
-# define machine_is_ixp421_dnaeeth()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_POCKETSERV9200
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_POCKETSERV9200
-# endif
-# define machine_is_pocketserv9200()	(machine_arch_type == MACH_TYPE_POCKETSERV9200)
-#else
-# define machine_is_pocketserv9200()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_TOTO
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TOTO
-# endif
-# define machine_is_toto()	(machine_arch_type == MACH_TYPE_TOTO)
-#else
-# define machine_is_toto()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_S3C2440
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_S3C2440
-# endif
-# define machine_is_s3c2440()	(machine_arch_type == MACH_TYPE_S3C2440)
-#else
-# define machine_is_s3c2440()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_KS8695P
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_KS8695P
-# endif
-# define machine_is_ks8695p()	(machine_arch_type == MACH_TYPE_KS8695P)
-#else
-# define machine_is_ks8695p()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_SE4000
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SE4000
-# endif
-# define machine_is_se4000()	(machine_arch_type == MACH_TYPE_SE4000)
-#else
-# define machine_is_se4000()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_QUADRICEPS
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_QUADRICEPS
-# endif
-# define machine_is_quadriceps()	(machine_arch_type == MACH_TYPE_QUADRICEPS)
-#else
-# define machine_is_quadriceps()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_BRONCO
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_BRONCO
-# endif
-# define machine_is_bronco()	(machine_arch_type == MACH_TYPE_BRONCO)
-#else
-# define machine_is_bronco()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_ESL_WIRELESS_TAB
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ESL_WIRELESS_TAB
-# endif
-# define machine_is_esl_wireless_tab()	(machine_arch_type == MACH_TYPE_ESL_WIRELESS_TAB)
-#else
-# define machine_is_esl_wireless_tab()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_ESL_SOFCOMP
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ESL_SOFCOMP
-# endif
-# define machine_is_esl_sofcomp()	(machine_arch_type == MACH_TYPE_ESL_SOFCOMP)
-#else
-# define machine_is_esl_sofcomp()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_S5C7375
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_S5C7375
-# endif
-# define machine_is_s5c7375()	(machine_arch_type == MACH_TYPE_S5C7375)
-#else
-# define machine_is_s5c7375()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_SPEARHEAD
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SPEARHEAD
-# endif
-# define machine_is_spearhead()	(machine_arch_type == MACH_TYPE_SPEARHEAD)
-#else
-# define machine_is_spearhead()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_PANTERA
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PANTERA
-# endif
-# define machine_is_pantera()	(machine_arch_type == MACH_TYPE_PANTERA)
-#else
-# define machine_is_pantera()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_PRAYOGLITE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PRAYOGLITE
-# endif
-# define machine_is_prayoglite()	(machine_arch_type == MACH_TYPE_PRAYOGLITE)
-#else
-# define machine_is_prayoglite()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_GUMSTIX
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_GUMSTIX
-# endif
-# define machine_is_gumstix()	(machine_arch_type == MACH_TYPE_GUMSTIX)
-#else
-# define machine_is_gumstix()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_RCUBE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_RCUBE
-# endif
-# define machine_is_rcube()	(machine_arch_type == MACH_TYPE_RCUBE)
-#else
-# define machine_is_rcube()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_REA_OLV
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_REA_OLV
-# endif
-# define machine_is_rea_olv()	(machine_arch_type == MACH_TYPE_REA_OLV)
-#else
-# define machine_is_rea_olv()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_PXA_IPHONE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PXA_IPHONE
-# endif
-# define machine_is_pxa_iphone()	(machine_arch_type == MACH_TYPE_PXA_IPHONE)
-#else
-# define machine_is_pxa_iphone()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_S3C3410
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_S3C3410
-# endif
-# define machine_is_s3c3410()	(machine_arch_type == MACH_TYPE_S3C3410)
-#else
-# define machine_is_s3c3410()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_ESPD_4510B
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ESPD_4510B
-# endif
-# define machine_is_espd_4510b()	(machine_arch_type == MACH_TYPE_ESPD_4510B)
-#else
-# define machine_is_espd_4510b()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_MP1X
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MP1X
-# endif
-# define machine_is_mp1x()	(machine_arch_type == MACH_TYPE_MP1X)
-#else
-# define machine_is_mp1x()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_AT91RM9200TB
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_AT91RM9200TB
-# endif
-# define machine_is_at91rm9200tb()	(machine_arch_type == MACH_TYPE_AT91RM9200TB)
-#else
-# define machine_is_at91rm9200tb()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_ADSVGX
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ADSVGX
-# endif
-# define machine_is_adsvgx()	(machine_arch_type == MACH_TYPE_ADSVGX)
-#else
-# define machine_is_adsvgx()	(0)
-#endif
-
-#ifdef CONFIG_MACH_OMAP_H2
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_OMAP_H2
-# endif
-# define machine_is_omap_h2()	(machine_arch_type == MACH_TYPE_OMAP_H2)
-#else
-# define machine_is_omap_h2()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_PELEE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PELEE
-# endif
-# define machine_is_pelee()	(machine_arch_type == MACH_TYPE_PELEE)
-#else
-# define machine_is_pelee()	(0)
-#endif
-
-#ifdef CONFIG_MACH_E740
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_E740
-# endif
-# define machine_is_e740()	(machine_arch_type == MACH_TYPE_E740)
-#else
-# define machine_is_e740()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_IQ80331
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_IQ80331
-# endif
-# define machine_is_iq80331()	(machine_arch_type == MACH_TYPE_IQ80331)
-#else
-# define machine_is_iq80331()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_VERSATILE_PB
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_VERSATILE_PB
-# endif
-# define machine_is_versatile_pb()	(machine_arch_type == MACH_TYPE_VERSATILE_PB)
-#else
-# define machine_is_versatile_pb()	(0)
-#endif
-
-#ifdef CONFIG_MACH_KEV7A400
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_KEV7A400
-# endif
-# define machine_is_kev7a400()	(machine_arch_type == MACH_TYPE_KEV7A400)
-#else
-# define machine_is_kev7a400()	(0)
-#endif
-
-#ifdef CONFIG_MACH_LPD7A400
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_LPD7A400
-# endif
-# define machine_is_lpd7a400()	(machine_arch_type == MACH_TYPE_LPD7A400)
-#else
-# define machine_is_lpd7a400()	(0)
-#endif
-
-#ifdef CONFIG_MACH_LPD7A404
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_LPD7A404
-# endif
-# define machine_is_lpd7a404()	(machine_arch_type == MACH_TYPE_LPD7A404)
-#else
-# define machine_is_lpd7a404()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_FUJITSU_CAMELOT
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_FUJITSU_CAMELOT
-# endif
-# define machine_is_fujitsu_camelot()	(machine_arch_type == MACH_TYPE_FUJITSU_CAMELOT)
-#else
-# define machine_is_fujitsu_camelot()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_JANUS2M
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_JANUS2M
-# endif
-# define machine_is_janus2m()	(machine_arch_type == MACH_TYPE_JANUS2M)
-#else
-# define machine_is_janus2m()	(0)
-#endif
-
-#ifdef CONFIG_MACH_EMBTF
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_EMBTF
-# endif
-# define machine_is_embtf()	(machine_arch_type == MACH_TYPE_EMBTF)
-#else
-# define machine_is_embtf()	(0)
-#endif
-
-#ifdef CONFIG_MACH_HPM
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_HPM
-# endif
-# define machine_is_hpm()	(machine_arch_type == MACH_TYPE_HPM)
-#else
-# define machine_is_hpm()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SMDK2410TK
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SMDK2410TK
-# endif
-# define machine_is_smdk2410tk()	(machine_arch_type == MACH_TYPE_SMDK2410TK)
-#else
-# define machine_is_smdk2410tk()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SMDK2410AJ
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SMDK2410AJ
-# endif
-# define machine_is_smdk2410aj()	(machine_arch_type == MACH_TYPE_SMDK2410AJ)
-#else
-# define machine_is_smdk2410aj()	(0)
-#endif
-
-#ifdef CONFIG_MACH_STREETRACER
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_STREETRACER
-# endif
-# define machine_is_streetracer()	(machine_arch_type == MACH_TYPE_STREETRACER)
-#else
-# define machine_is_streetracer()	(0)
-#endif
-
-#ifdef CONFIG_MACH_EFRAME
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_EFRAME
-# endif
-# define machine_is_eframe()	(machine_arch_type == MACH_TYPE_EFRAME)
-#else
-# define machine_is_eframe()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CSB337
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CSB337
-# endif
-# define machine_is_csb337()	(machine_arch_type == MACH_TYPE_CSB337)
-#else
-# define machine_is_csb337()	(0)
-#endif
-
-#ifdef CONFIG_MACH_PXA_LARK
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PXA_LARK
-# endif
-# define machine_is_pxa_lark()	(machine_arch_type == MACH_TYPE_PXA_LARK)
-#else
-# define machine_is_pxa_lark()	(0)
-#endif
-
-#ifdef CONFIG_MACH_PNP2110
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PNP2110
-# endif
-# define machine_is_pxa_pnp2110()	(machine_arch_type == MACH_TYPE_PNP2110)
-#else
-# define machine_is_pxa_pnp2110()	(0)
-#endif
-
-#ifdef CONFIG_MACH_TCC72X
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TCC72X
-# endif
-# define machine_is_tcc72x()	(machine_arch_type == MACH_TYPE_TCC72X)
-#else
-# define machine_is_tcc72x()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ALTAIR
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ALTAIR
-# endif
-# define machine_is_altair()	(machine_arch_type == MACH_TYPE_ALTAIR)
-#else
-# define machine_is_altair()	(0)
-#endif
-
-#ifdef CONFIG_MACH_KC3
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_KC3
-# endif
-# define machine_is_kc3()	(machine_arch_type == MACH_TYPE_KC3)
-#else
-# define machine_is_kc3()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SINTEFTD
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SINTEFTD
-# endif
-# define machine_is_sinteftd()	(machine_arch_type == MACH_TYPE_SINTEFTD)
-#else
-# define machine_is_sinteftd()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MAINSTONE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MAINSTONE
-# endif
-# define machine_is_mainstone()	(machine_arch_type == MACH_TYPE_MAINSTONE)
-#else
-# define machine_is_mainstone()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ADAY4X
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ADAY4X
-# endif
-# define machine_is_aday4x()	(machine_arch_type == MACH_TYPE_ADAY4X)
-#else
-# define machine_is_aday4x()	(0)
-#endif
-
-#ifdef CONFIG_MACH_LITE300
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_LITE300
-# endif
-# define machine_is_lite300()	(machine_arch_type == MACH_TYPE_LITE300)
-#else
-# define machine_is_lite300()	(0)
-#endif
-
-#ifdef CONFIG_MACH_S5C7376
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_S5C7376
-# endif
-# define machine_is_s5c7376()	(machine_arch_type == MACH_TYPE_S5C7376)
-#else
-# define machine_is_s5c7376()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MT02
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MT02
-# endif
-# define machine_is_mt02()	(machine_arch_type == MACH_TYPE_MT02)
-#else
-# define machine_is_mt02()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MPORT3S
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MPORT3S
-# endif
-# define machine_is_mport3s()	(machine_arch_type == MACH_TYPE_MPORT3S)
-#else
-# define machine_is_mport3s()	(0)
-#endif
-
-#ifdef CONFIG_MACH_RA_ALPHA
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_RA_ALPHA
-# endif
-# define machine_is_ra_alpha()	(machine_arch_type == MACH_TYPE_RA_ALPHA)
-#else
-# define machine_is_ra_alpha()	(0)
-#endif
-
-#ifdef CONFIG_MACH_XCEP
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_XCEP
-# endif
-# define machine_is_xcep()	(machine_arch_type == MACH_TYPE_XCEP)
-#else
-# define machine_is_xcep()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ARCOM_VULCAN
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ARCOM_VULCAN
-# endif
-# define machine_is_arcom_vulcan()	(machine_arch_type == MACH_TYPE_ARCOM_VULCAN)
-#else
-# define machine_is_arcom_vulcan()	(0)
-#endif
-
-#ifdef CONFIG_MACH_STARGATE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_STARGATE
-# endif
-# define machine_is_stargate()	(machine_arch_type == MACH_TYPE_STARGATE)
-#else
-# define machine_is_stargate()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ARMADILLOJ
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ARMADILLOJ
-# endif
-# define machine_is_armadilloj()	(machine_arch_type == MACH_TYPE_ARMADILLOJ)
-#else
-# define machine_is_armadilloj()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ELROY_JACK
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ELROY_JACK
-# endif
-# define machine_is_elroy_jack()	(machine_arch_type == MACH_TYPE_ELROY_JACK)
-#else
-# define machine_is_elroy_jack()	(0)
-#endif
-
-#ifdef CONFIG_MACH_BACKEND
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_BACKEND
-# endif
-# define machine_is_backend()	(machine_arch_type == MACH_TYPE_BACKEND)
-#else
-# define machine_is_backend()	(0)
-#endif
-
-#ifdef CONFIG_MACH_S5LINBOX
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_S5LINBOX
-# endif
-# define machine_is_s5linbox()	(machine_arch_type == MACH_TYPE_S5LINBOX)
-#else
-# define machine_is_s5linbox()	(0)
-#endif
-
-#ifdef CONFIG_MACH_NOMADIK
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_NOMADIK
-# endif
-# define machine_is_nomadik()	(machine_arch_type == MACH_TYPE_NOMADIK)
-#else
-# define machine_is_nomadik()	(0)
-#endif
-
-#ifdef CONFIG_MACH_IA_CPU_9200
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_IA_CPU_9200
-# endif
-# define machine_is_ia_cpu_9200()	(machine_arch_type == MACH_TYPE_IA_CPU_9200)
-#else
-# define machine_is_ia_cpu_9200()	(0)
-#endif
-
-#ifdef CONFIG_MACH_AT91_BJA1
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_AT91_BJA1
-# endif
-# define machine_is_at91_bja1()	(machine_arch_type == MACH_TYPE_AT91_BJA1)
-#else
-# define machine_is_at91_bja1()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CORGI
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CORGI
-# endif
-# define machine_is_corgi()	(machine_arch_type == MACH_TYPE_CORGI)
-#else
-# define machine_is_corgi()	(0)
-#endif
-
-#ifdef CONFIG_MACH_POODLE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_POODLE
-# endif
-# define machine_is_poodle()	(machine_arch_type == MACH_TYPE_POODLE)
-#else
-# define machine_is_poodle()	(0)
-#endif
-
-#ifdef CONFIG_MACH_TEN
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TEN
-# endif
-# define machine_is_ten()	(machine_arch_type == MACH_TYPE_TEN)
-#else
-# define machine_is_ten()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ROVERP5P
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ROVERP5P
-# endif
-# define machine_is_roverp5p()	(machine_arch_type == MACH_TYPE_ROVERP5P)
-#else
-# define machine_is_roverp5p()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SC2700
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SC2700
-# endif
-# define machine_is_sc2700()	(machine_arch_type == MACH_TYPE_SC2700)
-#else
-# define machine_is_sc2700()	(0)
-#endif
-
-#ifdef CONFIG_MACH_EX_EAGLE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_EX_EAGLE
-# endif
-# define machine_is_ex_eagle()	(machine_arch_type == MACH_TYPE_EX_EAGLE)
-#else
-# define machine_is_ex_eagle()	(0)
-#endif
-
-#ifdef CONFIG_MACH_NX_PXA12
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_NX_PXA12
-# endif
-# define machine_is_nx_pxa12()	(machine_arch_type == MACH_TYPE_NX_PXA12)
-#else
-# define machine_is_nx_pxa12()	(0)
-#endif
-
-#ifdef CONFIG_MACH_NX_PXA5
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_NX_PXA5
-# endif
-# define machine_is_nx_pxa5()	(machine_arch_type == MACH_TYPE_NX_PXA5)
-#else
-# define machine_is_nx_pxa5()	(0)
-#endif
-
-#ifdef CONFIG_MACH_BLACKBOARD2
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_BLACKBOARD2
-# endif
-# define machine_is_blackboard2()	(machine_arch_type == MACH_TYPE_BLACKBOARD2)
-#else
-# define machine_is_blackboard2()	(0)
-#endif
-
-#ifdef CONFIG_MACH_I819
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_I819
-# endif
-# define machine_is_i819()	(machine_arch_type == MACH_TYPE_I819)
-#else
-# define machine_is_i819()	(0)
-#endif
-
-#ifdef CONFIG_MACH_IXMB995E
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_IXMB995E
-# endif
-# define machine_is_ixmb995e()	(machine_arch_type == MACH_TYPE_IXMB995E)
-#else
-# define machine_is_ixmb995e()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SKYRIDER
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SKYRIDER
-# endif
-# define machine_is_skyrider()	(machine_arch_type == MACH_TYPE_SKYRIDER)
-#else
-# define machine_is_skyrider()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SKYHAWK
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SKYHAWK
-# endif
-# define machine_is_skyhawk()	(machine_arch_type == MACH_TYPE_SKYHAWK)
-#else
-# define machine_is_skyhawk()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ENTERPRISE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ENTERPRISE
-# endif
-# define machine_is_enterprise()	(machine_arch_type == MACH_TYPE_ENTERPRISE)
-#else
-# define machine_is_enterprise()	(0)
-#endif
-
-#ifdef CONFIG_MACH_DEP2410
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_DEP2410
-# endif
-# define machine_is_dep2410()	(machine_arch_type == MACH_TYPE_DEP2410)
-#else
-# define machine_is_dep2410()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ARMCORE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ARMCORE
-# endif
-# define machine_is_armcore()	(machine_arch_type == MACH_TYPE_ARMCORE)
-#else
-# define machine_is_armcore()	(0)
-#endif
-
-#ifdef CONFIG_MACH_HOBBIT
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_HOBBIT
-# endif
-# define machine_is_hobbit()	(machine_arch_type == MACH_TYPE_HOBBIT)
-#else
-# define machine_is_hobbit()	(0)
-#endif
-
-#ifdef CONFIG_MACH_H7210
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_H7210
-# endif
-# define machine_is_h7210()	(machine_arch_type == MACH_TYPE_H7210)
-#else
-# define machine_is_h7210()	(0)
-#endif
-
-#ifdef CONFIG_MACH_PXA_NETDCU5
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PXA_NETDCU5
-# endif
-# define machine_is_pxa_netdcu5()	(machine_arch_type == MACH_TYPE_PXA_NETDCU5)
-#else
-# define machine_is_pxa_netdcu5()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ACC
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ACC
-# endif
-# define machine_is_acc()	(machine_arch_type == MACH_TYPE_ACC)
-#else
-# define machine_is_acc()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ESL_SARVA
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ESL_SARVA
-# endif
-# define machine_is_esl_sarva()	(machine_arch_type == MACH_TYPE_ESL_SARVA)
-#else
-# define machine_is_esl_sarva()	(0)
-#endif
-
-#ifdef CONFIG_MACH_XM250
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_XM250
-# endif
-# define machine_is_xm250()	(machine_arch_type == MACH_TYPE_XM250)
-#else
-# define machine_is_xm250()	(0)
-#endif
-
-#ifdef CONFIG_MACH_T6TC1XB
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_T6TC1XB
-# endif
-# define machine_is_t6tc1xb()	(machine_arch_type == MACH_TYPE_T6TC1XB)
-#else
-# define machine_is_t6tc1xb()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ESS710
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ESS710
-# endif
-# define machine_is_ess710()	(machine_arch_type == MACH_TYPE_ESS710)
-#else
-# define machine_is_ess710()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MX31ADS
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MX31ADS
-# endif
-# define machine_is_mx31ads()	(machine_arch_type == MACH_TYPE_MX31ADS)
-#else
-# define machine_is_mx31ads()	(0)
-#endif
-
-#ifdef CONFIG_MACH_HIMALAYA
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_HIMALAYA
-# endif
-# define machine_is_himalaya()	(machine_arch_type == MACH_TYPE_HIMALAYA)
-#else
-# define machine_is_himalaya()	(0)
-#endif
-
-#ifdef CONFIG_MACH_BOLFENK
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_BOLFENK
-# endif
-# define machine_is_bolfenk()	(machine_arch_type == MACH_TYPE_BOLFENK)
-#else
-# define machine_is_bolfenk()	(0)
-#endif
-
-#ifdef CONFIG_MACH_AT91RM9200KR
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_AT91RM9200KR
-# endif
-# define machine_is_at91rm9200kr()	(machine_arch_type == MACH_TYPE_AT91RM9200KR)
-#else
-# define machine_is_at91rm9200kr()	(0)
-#endif
-
-#ifdef CONFIG_MACH_EDB9312
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_EDB9312
-# endif
-# define machine_is_edb9312()	(machine_arch_type == MACH_TYPE_EDB9312)
-#else
-# define machine_is_edb9312()	(0)
-#endif
-
-#ifdef CONFIG_MACH_OMAP_GENERIC
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_OMAP_GENERIC
-# endif
-# define machine_is_omap_generic()	(machine_arch_type == MACH_TYPE_OMAP_GENERIC)
-#else
-# define machine_is_omap_generic()	(0)
-#endif
-
-#ifdef CONFIG_MACH_AXIMX3
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_AXIMX3
-# endif
-# define machine_is_aximx3()	(machine_arch_type == MACH_TYPE_AXIMX3)
-#else
-# define machine_is_aximx3()	(0)
-#endif
-
-#ifdef CONFIG_MACH_EB67XDIP
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_EB67XDIP
-# endif
-# define machine_is_eb67xdip()	(machine_arch_type == MACH_TYPE_EB67XDIP)
-#else
-# define machine_is_eb67xdip()	(0)
-#endif
-
-#ifdef CONFIG_MACH_WEBTXS
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_WEBTXS
-# endif
-# define machine_is_webtxs()	(machine_arch_type == MACH_TYPE_WEBTXS)
-#else
-# define machine_is_webtxs()	(0)
-#endif
-
-#ifdef CONFIG_MACH_HAWK
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_HAWK
-# endif
-# define machine_is_hawk()	(machine_arch_type == MACH_TYPE_HAWK)
-#else
-# define machine_is_hawk()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CCAT91SBC001
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CCAT91SBC001
-# endif
-# define machine_is_ccat91sbc001()	(machine_arch_type == MACH_TYPE_CCAT91SBC001)
-#else
-# define machine_is_ccat91sbc001()	(0)
-#endif
-
-#ifdef CONFIG_MACH_EXPRESSO
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_EXPRESSO
-# endif
-# define machine_is_expresso()	(machine_arch_type == MACH_TYPE_EXPRESSO)
-#else
-# define machine_is_expresso()	(0)
-#endif
-
-#ifdef CONFIG_MACH_H4000
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_H4000
-# endif
-# define machine_is_h4000()	(machine_arch_type == MACH_TYPE_H4000)
-#else
-# define machine_is_h4000()	(0)
-#endif
-
-#ifdef CONFIG_MACH_DINO
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_DINO
-# endif
-# define machine_is_dino()	(machine_arch_type == MACH_TYPE_DINO)
-#else
-# define machine_is_dino()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ML675K
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ML675K
-# endif
-# define machine_is_ml675k()	(machine_arch_type == MACH_TYPE_ML675K)
-#else
-# define machine_is_ml675k()	(0)
-#endif
-
-#ifdef CONFIG_MACH_EDB9301
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_EDB9301
-# endif
-# define machine_is_edb9301()	(machine_arch_type == MACH_TYPE_EDB9301)
-#else
-# define machine_is_edb9301()	(0)
-#endif
-
-#ifdef CONFIG_MACH_EDB9315
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_EDB9315
-# endif
-# define machine_is_edb9315()	(machine_arch_type == MACH_TYPE_EDB9315)
-#else
-# define machine_is_edb9315()	(0)
-#endif
-
-#ifdef CONFIG_MACH_RECIVA_TT
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_RECIVA_TT
-# endif
-# define machine_is_reciva_tt()	(machine_arch_type == MACH_TYPE_RECIVA_TT)
-#else
-# define machine_is_reciva_tt()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CSTCB01
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CSTCB01
-# endif
-# define machine_is_cstcb01()	(machine_arch_type == MACH_TYPE_CSTCB01)
-#else
-# define machine_is_cstcb01()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CSTCB1
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CSTCB1
-# endif
-# define machine_is_cstcb1()	(machine_arch_type == MACH_TYPE_CSTCB1)
-#else
-# define machine_is_cstcb1()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SHADWELL
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SHADWELL
-# endif
-# define machine_is_shadwell()	(machine_arch_type == MACH_TYPE_SHADWELL)
-#else
-# define machine_is_shadwell()	(0)
-#endif
-
-#ifdef CONFIG_MACH_GOEPEL263
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_GOEPEL263
-# endif
-# define machine_is_goepel263()	(machine_arch_type == MACH_TYPE_GOEPEL263)
-#else
-# define machine_is_goepel263()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ACQ100
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ACQ100
-# endif
-# define machine_is_acq100()	(machine_arch_type == MACH_TYPE_ACQ100)
-#else
-# define machine_is_acq100()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MX1FS2
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MX1FS2
-# endif
-# define machine_is_mx1fs2()	(machine_arch_type == MACH_TYPE_MX1FS2)
-#else
-# define machine_is_mx1fs2()	(0)
-#endif
-
-#ifdef CONFIG_MACH_HIPTOP_G1
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_HIPTOP_G1
-# endif
-# define machine_is_hiptop_g1()	(machine_arch_type == MACH_TYPE_HIPTOP_G1)
-#else
-# define machine_is_hiptop_g1()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SPARKY
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SPARKY
-# endif
-# define machine_is_sparky()	(machine_arch_type == MACH_TYPE_SPARKY)
-#else
-# define machine_is_sparky()	(0)
-#endif
-
-#ifdef CONFIG_MACH_NS9750
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_NS9750
-# endif
-# define machine_is_ns9750()	(machine_arch_type == MACH_TYPE_NS9750)
-#else
-# define machine_is_ns9750()	(0)
-#endif
-
-#ifdef CONFIG_MACH_PHOENIX
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PHOENIX
-# endif
-# define machine_is_phoenix()	(machine_arch_type == MACH_TYPE_PHOENIX)
-#else
-# define machine_is_phoenix()	(0)
-#endif
-
-#ifdef CONFIG_MACH_VR1000
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_VR1000
-# endif
-# define machine_is_vr1000()	(machine_arch_type == MACH_TYPE_VR1000)
-#else
-# define machine_is_vr1000()	(0)
-#endif
-
-#ifdef CONFIG_MACH_DEISTERPXA
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_DEISTERPXA
-# endif
-# define machine_is_deisterpxa()	(machine_arch_type == MACH_TYPE_DEISTERPXA)
-#else
-# define machine_is_deisterpxa()	(0)
-#endif
-
-#ifdef CONFIG_MACH_BCM1160
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_BCM1160
-# endif
-# define machine_is_bcm1160()	(machine_arch_type == MACH_TYPE_BCM1160)
-#else
-# define machine_is_bcm1160()	(0)
-#endif
-
-#ifdef CONFIG_MACH_PCM022
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PCM022
-# endif
-# define machine_is_pcm022()	(machine_arch_type == MACH_TYPE_PCM022)
-#else
-# define machine_is_pcm022()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ADSGCX
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ADSGCX
-# endif
-# define machine_is_adsgcx()	(machine_arch_type == MACH_TYPE_ADSGCX)
-#else
-# define machine_is_adsgcx()	(0)
-#endif
-
-#ifdef CONFIG_MACH_DREADNAUGHT
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_DREADNAUGHT
-# endif
-# define machine_is_dreadnaught()	(machine_arch_type == MACH_TYPE_DREADNAUGHT)
-#else
-# define machine_is_dreadnaught()	(0)
-#endif
-
-#ifdef CONFIG_MACH_DM320
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_DM320
-# endif
-# define machine_is_dm320()	(machine_arch_type == MACH_TYPE_DM320)
-#else
-# define machine_is_dm320()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MARKOV
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MARKOV
-# endif
-# define machine_is_markov()	(machine_arch_type == MACH_TYPE_MARKOV)
-#else
-# define machine_is_markov()	(0)
-#endif
-
-#ifdef CONFIG_MACH_COS7A400
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_COS7A400
-# endif
-# define machine_is_cos7a400()	(machine_arch_type == MACH_TYPE_COS7A400)
-#else
-# define machine_is_cos7a400()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MILANO
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MILANO
-# endif
-# define machine_is_milano()	(machine_arch_type == MACH_TYPE_MILANO)
-#else
-# define machine_is_milano()	(0)
-#endif
-
-#ifdef CONFIG_MACH_UE9328
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_UE9328
-# endif
-# define machine_is_ue9328()	(machine_arch_type == MACH_TYPE_UE9328)
-#else
-# define machine_is_ue9328()	(0)
-#endif
-
-#ifdef CONFIG_MACH_UEX255
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_UEX255
-# endif
-# define machine_is_uex255()	(machine_arch_type == MACH_TYPE_UEX255)
-#else
-# define machine_is_uex255()	(0)
-#endif
-
-#ifdef CONFIG_MACH_UE2410
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_UE2410
-# endif
-# define machine_is_ue2410()	(machine_arch_type == MACH_TYPE_UE2410)
-#else
-# define machine_is_ue2410()	(0)
-#endif
-
-#ifdef CONFIG_MACH_A620
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_A620
-# endif
-# define machine_is_a620()	(machine_arch_type == MACH_TYPE_A620)
-#else
-# define machine_is_a620()	(0)
-#endif
-
-#ifdef CONFIG_MACH_OCELOT
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_OCELOT
-# endif
-# define machine_is_ocelot()	(machine_arch_type == MACH_TYPE_OCELOT)
-#else
-# define machine_is_ocelot()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CHEETAH
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CHEETAH
-# endif
-# define machine_is_cheetah()	(machine_arch_type == MACH_TYPE_CHEETAH)
-#else
-# define machine_is_cheetah()	(0)
-#endif
-
-#ifdef CONFIG_MACH_OMAP_PERSEUS2
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_OMAP_PERSEUS2
-# endif
-# define machine_is_omap_perseus2()	(machine_arch_type == MACH_TYPE_OMAP_PERSEUS2)
-#else
-# define machine_is_omap_perseus2()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ZVUE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ZVUE
-# endif
-# define machine_is_zvue()	(machine_arch_type == MACH_TYPE_ZVUE)
-#else
-# define machine_is_zvue()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ROVERP1
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ROVERP1
-# endif
-# define machine_is_roverp1()	(machine_arch_type == MACH_TYPE_ROVERP1)
-#else
-# define machine_is_roverp1()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ASIDIAL2
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ASIDIAL2
-# endif
-# define machine_is_asidial2()	(machine_arch_type == MACH_TYPE_ASIDIAL2)
-#else
-# define machine_is_asidial2()	(0)
-#endif
-
-#ifdef CONFIG_MACH_S3C24A0
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_S3C24A0
-# endif
-# define machine_is_s3c24a0()	(machine_arch_type == MACH_TYPE_S3C24A0)
-#else
-# define machine_is_s3c24a0()	(0)
-#endif
-
-#ifdef CONFIG_MACH_E800
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_E800
-# endif
-# define machine_is_e800()	(machine_arch_type == MACH_TYPE_E800)
-#else
-# define machine_is_e800()	(0)
-#endif
-
-#ifdef CONFIG_MACH_E750
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_E750
-# endif
-# define machine_is_e750()	(machine_arch_type == MACH_TYPE_E750)
-#else
-# define machine_is_e750()	(0)
-#endif
-
-#ifdef CONFIG_MACH_S3C5500
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_S3C5500
-# endif
-# define machine_is_s3c5500()	(machine_arch_type == MACH_TYPE_S3C5500)
-#else
-# define machine_is_s3c5500()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SMDK5500
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SMDK5500
-# endif
-# define machine_is_smdk5500()	(machine_arch_type == MACH_TYPE_SMDK5500)
-#else
-# define machine_is_smdk5500()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SIGNALSYNC
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SIGNALSYNC
-# endif
-# define machine_is_signalsync()	(machine_arch_type == MACH_TYPE_SIGNALSYNC)
-#else
-# define machine_is_signalsync()	(0)
-#endif
-
-#ifdef CONFIG_MACH_NBC
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_NBC
-# endif
-# define machine_is_nbc()	(machine_arch_type == MACH_TYPE_NBC)
-#else
-# define machine_is_nbc()	(0)
-#endif
-
-#ifdef CONFIG_MACH_KODIAK
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_KODIAK
-# endif
-# define machine_is_kodiak()	(machine_arch_type == MACH_TYPE_KODIAK)
-#else
-# define machine_is_kodiak()	(0)
-#endif
-
-#ifdef CONFIG_MACH_NETBOOKPRO
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_NETBOOKPRO
-# endif
-# define machine_is_netbookpro()	(machine_arch_type == MACH_TYPE_NETBOOKPRO)
-#else
-# define machine_is_netbookpro()	(0)
-#endif
-
-#ifdef CONFIG_MACH_HW90200
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_HW90200
-# endif
-# define machine_is_hw90200()	(machine_arch_type == MACH_TYPE_HW90200)
-#else
-# define machine_is_hw90200()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CONDOR
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CONDOR
-# endif
-# define machine_is_condor()	(machine_arch_type == MACH_TYPE_CONDOR)
-#else
-# define machine_is_condor()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CUP
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CUP
-# endif
-# define machine_is_cup()	(machine_arch_type == MACH_TYPE_CUP)
-#else
-# define machine_is_cup()	(0)
-#endif
-
-#ifdef CONFIG_MACH_KITE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_KITE
-# endif
-# define machine_is_kite()	(machine_arch_type == MACH_TYPE_KITE)
-#else
-# define machine_is_kite()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SCB9328
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SCB9328
-# endif
-# define machine_is_scb9328()	(machine_arch_type == MACH_TYPE_SCB9328)
-#else
-# define machine_is_scb9328()	(0)
-#endif
-
-#ifdef CONFIG_MACH_OMAP_H3
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_OMAP_H3
-# endif
-# define machine_is_omap_h3()	(machine_arch_type == MACH_TYPE_OMAP_H3)
-#else
-# define machine_is_omap_h3()	(0)
-#endif
-
-#ifdef CONFIG_MACH_OMAP_H4
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_OMAP_H4
-# endif
-# define machine_is_omap_h4()	(machine_arch_type == MACH_TYPE_OMAP_H4)
-#else
-# define machine_is_omap_h4()	(0)
-#endif
-
-#ifdef CONFIG_MACH_N10
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_N10
-# endif
-# define machine_is_n10()	(machine_arch_type == MACH_TYPE_N10)
-#else
-# define machine_is_n10()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MONTAJADE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MONTAJADE
-# endif
-# define machine_is_montejade()	(machine_arch_type == MACH_TYPE_MONTAJADE)
-#else
-# define machine_is_montejade()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SG560
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SG560
-# endif
-# define machine_is_sg560()	(machine_arch_type == MACH_TYPE_SG560)
-#else
-# define machine_is_sg560()	(0)
-#endif
-
-#ifdef CONFIG_MACH_DP1000
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_DP1000
-# endif
-# define machine_is_dp1000()	(machine_arch_type == MACH_TYPE_DP1000)
-#else
-# define machine_is_dp1000()	(0)
-#endif
-
-#ifdef CONFIG_MACH_OMAP_OSK
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_OMAP_OSK
-# endif
-# define machine_is_omap_osk()	(machine_arch_type == MACH_TYPE_OMAP_OSK)
-#else
-# define machine_is_omap_osk()	(0)
-#endif
-
-#ifdef CONFIG_MACH_RG100V3
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_RG100V3
-# endif
-# define machine_is_rg100v3()	(machine_arch_type == MACH_TYPE_RG100V3)
-#else
-# define machine_is_rg100v3()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MX2ADS
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MX2ADS
-# endif
-# define machine_is_mx2ads()	(machine_arch_type == MACH_TYPE_MX2ADS)
-#else
-# define machine_is_mx2ads()	(0)
-#endif
-
-#ifdef CONFIG_MACH_PXA_KILO
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PXA_KILO
-# endif
-# define machine_is_pxa_kilo()	(machine_arch_type == MACH_TYPE_PXA_KILO)
-#else
-# define machine_is_pxa_kilo()	(0)
-#endif
-
-#ifdef CONFIG_MACH_IXP4XX_EAGLE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_IXP4XX_EAGLE
-# endif
-# define machine_is_ixp4xx_eagle()	(machine_arch_type == MACH_TYPE_IXP4XX_EAGLE)
-#else
-# define machine_is_ixp4xx_eagle()	(0)
-#endif
-
-#ifdef CONFIG_MACH_TOSA
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TOSA
-# endif
-# define machine_is_tosa()	(machine_arch_type == MACH_TYPE_TOSA)
-#else
-# define machine_is_tosa()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MB2520F
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MB2520F
-# endif
-# define machine_is_mb2520f()	(machine_arch_type == MACH_TYPE_MB2520F)
-#else
-# define machine_is_mb2520f()	(0)
-#endif
-
-#ifdef CONFIG_MACH_EMC1000
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_EMC1000
-# endif
-# define machine_is_emc1000()	(machine_arch_type == MACH_TYPE_EMC1000)
-#else
-# define machine_is_emc1000()	(0)
-#endif
-
-#ifdef CONFIG_MACH_TIDSC25
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TIDSC25
-# endif
-# define machine_is_tidsc25()	(machine_arch_type == MACH_TYPE_TIDSC25)
-#else
-# define machine_is_tidsc25()	(0)
-#endif
-
-#ifdef CONFIG_MACH_AKCPMXL
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_AKCPMXL
-# endif
-# define machine_is_akcpmxl()	(machine_arch_type == MACH_TYPE_AKCPMXL)
-#else
-# define machine_is_akcpmxl()	(0)
-#endif
-
-#ifdef CONFIG_MACH_AV3XX
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_AV3XX
-# endif
-# define machine_is_av3xx()	(machine_arch_type == MACH_TYPE_AV3XX)
-#else
-# define machine_is_av3xx()	(0)
-#endif
-
-#ifdef CONFIG_MACH_AVILA
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_AVILA
-# endif
-# define machine_is_avila()	(machine_arch_type == MACH_TYPE_AVILA)
-#else
-# define machine_is_avila()	(0)
-#endif
-
-#ifdef CONFIG_MACH_PXA_MPM10
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PXA_MPM10
-# endif
-# define machine_is_pxa_mpm10()	(machine_arch_type == MACH_TYPE_PXA_MPM10)
-#else
-# define machine_is_pxa_mpm10()	(0)
-#endif
-
-#ifdef CONFIG_MACH_PXA_KYANITE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PXA_KYANITE
-# endif
-# define machine_is_pxa_kyanite()	(machine_arch_type == MACH_TYPE_PXA_KYANITE)
-#else
-# define machine_is_pxa_kyanite()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SGOLD
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SGOLD
-# endif
-# define machine_is_sgold()	(machine_arch_type == MACH_TYPE_SGOLD)
-#else
-# define machine_is_sgold()	(0)
-#endif
-
-#ifdef CONFIG_MACH_OSCAR
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_OSCAR
-# endif
-# define machine_is_oscar()	(machine_arch_type == MACH_TYPE_OSCAR)
-#else
-# define machine_is_oscar()	(0)
-#endif
-
-#ifdef CONFIG_MACH_EPXA4USB2
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_EPXA4USB2
-# endif
-# define machine_is_epxa4usb2()	(machine_arch_type == MACH_TYPE_EPXA4USB2)
-#else
-# define machine_is_epxa4usb2()	(0)
-#endif
-
-#ifdef CONFIG_MACH_XSENGINE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_XSENGINE
-# endif
-# define machine_is_xsengine()	(machine_arch_type == MACH_TYPE_XSENGINE)
-#else
-# define machine_is_xsengine()	(0)
-#endif
-
-#ifdef CONFIG_MACH_IP600
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_IP600
-# endif
-# define machine_is_ip600()	(machine_arch_type == MACH_TYPE_IP600)
-#else
-# define machine_is_ip600()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MCAN2
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MCAN2
-# endif
-# define machine_is_mcan2()	(machine_arch_type == MACH_TYPE_MCAN2)
-#else
-# define machine_is_mcan2()	(0)
-#endif
-
-#ifdef CONFIG_MACH_DDI_BLUERIDGE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_DDI_BLUERIDGE
-# endif
-# define machine_is_ddi_blueridge()	(machine_arch_type == MACH_TYPE_DDI_BLUERIDGE)
-#else
-# define machine_is_ddi_blueridge()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SKYMINDER
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SKYMINDER
-# endif
-# define machine_is_skyminder()	(machine_arch_type == MACH_TYPE_SKYMINDER)
-#else
-# define machine_is_skyminder()	(0)
-#endif
-
-#ifdef CONFIG_MACH_LPD79520
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_LPD79520
-# endif
-# define machine_is_lpd79520()	(machine_arch_type == MACH_TYPE_LPD79520)
-#else
-# define machine_is_lpd79520()	(0)
-#endif
-
-#ifdef CONFIG_MACH_EDB9302
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_EDB9302
-# endif
-# define machine_is_edb9302()	(machine_arch_type == MACH_TYPE_EDB9302)
-#else
-# define machine_is_edb9302()	(0)
-#endif
-
-#ifdef CONFIG_MACH_HW90340
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_HW90340
-# endif
-# define machine_is_hw90340()	(machine_arch_type == MACH_TYPE_HW90340)
-#else
-# define machine_is_hw90340()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CIP_BOX
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CIP_BOX
-# endif
-# define machine_is_cip_box()	(machine_arch_type == MACH_TYPE_CIP_BOX)
-#else
-# define machine_is_cip_box()	(0)
-#endif
-
-#ifdef CONFIG_MACH_IVPN
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_IVPN
-# endif
-# define machine_is_ivpn()	(machine_arch_type == MACH_TYPE_IVPN)
-#else
-# define machine_is_ivpn()	(0)
-#endif
-
-#ifdef CONFIG_MACH_RSOC2
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_RSOC2
-# endif
-# define machine_is_rsoc2()	(machine_arch_type == MACH_TYPE_RSOC2)
-#else
-# define machine_is_rsoc2()	(0)
-#endif
-
-#ifdef CONFIG_MACH_HUSKY
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_HUSKY
-# endif
-# define machine_is_husky()	(machine_arch_type == MACH_TYPE_HUSKY)
-#else
-# define machine_is_husky()	(0)
-#endif
-
-#ifdef CONFIG_MACH_BOXER
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_BOXER
-# endif
-# define machine_is_boxer()	(machine_arch_type == MACH_TYPE_BOXER)
-#else
-# define machine_is_boxer()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SHEPHERD
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SHEPHERD
-# endif
-# define machine_is_shepherd()	(machine_arch_type == MACH_TYPE_SHEPHERD)
-#else
-# define machine_is_shepherd()	(0)
-#endif
-
-#ifdef CONFIG_MACH_AML42800AA
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_AML42800AA
-# endif
-# define machine_is_aml42800aa()	(machine_arch_type == MACH_TYPE_AML42800AA)
-#else
-# define machine_is_aml42800aa()	(0)
-#endif
-
-#ifdef CONFIG_MACH_LPC2294
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_LPC2294
-# endif
-# define machine_is_lpc2294()	(machine_arch_type == MACH_TYPE_LPC2294)
-#else
-# define machine_is_lpc2294()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SWITCHGRASS
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SWITCHGRASS
-# endif
-# define machine_is_switchgrass()	(machine_arch_type == MACH_TYPE_SWITCHGRASS)
-#else
-# define machine_is_switchgrass()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ENS_CMU
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ENS_CMU
-# endif
-# define machine_is_ens_cmu()	(machine_arch_type == MACH_TYPE_ENS_CMU)
-#else
-# define machine_is_ens_cmu()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MM6_SDB
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MM6_SDB
-# endif
-# define machine_is_mm6_sdb()	(machine_arch_type == MACH_TYPE_MM6_SDB)
-#else
-# define machine_is_mm6_sdb()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SATURN
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SATURN
-# endif
-# define machine_is_saturn()	(machine_arch_type == MACH_TYPE_SATURN)
-#else
-# define machine_is_saturn()	(0)
-#endif
-
-#ifdef CONFIG_MACH_I30030EVB
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_I30030EVB
-# endif
-# define machine_is_i30030evb()	(machine_arch_type == MACH_TYPE_I30030EVB)
-#else
-# define machine_is_i30030evb()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MXC27530EVB
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MXC27530EVB
-# endif
-# define machine_is_mxc27530evb()	(machine_arch_type == MACH_TYPE_MXC27530EVB)
-#else
-# define machine_is_mxc27530evb()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SMDK2800
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SMDK2800
-# endif
-# define machine_is_smdk2800()	(machine_arch_type == MACH_TYPE_SMDK2800)
-#else
-# define machine_is_smdk2800()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MTWILSON
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MTWILSON
-# endif
-# define machine_is_mtwilson()	(machine_arch_type == MACH_TYPE_MTWILSON)
-#else
-# define machine_is_mtwilson()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ZITI
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ZITI
-# endif
-# define machine_is_ziti()	(machine_arch_type == MACH_TYPE_ZITI)
-#else
-# define machine_is_ziti()	(0)
-#endif
-
-#ifdef CONFIG_MACH_GRANDFATHER
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_GRANDFATHER
-# endif
-# define machine_is_grandfather()	(machine_arch_type == MACH_TYPE_GRANDFATHER)
-#else
-# define machine_is_grandfather()	(0)
-#endif
-
-#ifdef CONFIG_MACH_TENGINE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TENGINE
-# endif
-# define machine_is_tengine()	(machine_arch_type == MACH_TYPE_TENGINE)
-#else
-# define machine_is_tengine()	(0)
-#endif
-
-#ifdef CONFIG_MACH_S3C2460
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_S3C2460
-# endif
-# define machine_is_s3c2460()	(machine_arch_type == MACH_TYPE_S3C2460)
-#else
-# define machine_is_s3c2460()	(0)
-#endif
-
-#ifdef CONFIG_MACH_PDM
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PDM
-# endif
-# define machine_is_pdm()	(machine_arch_type == MACH_TYPE_PDM)
-#else
-# define machine_is_pdm()	(0)
-#endif
-
-#ifdef CONFIG_MACH_H4700
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_H4700
-# endif
-# define machine_is_h4700()	(machine_arch_type == MACH_TYPE_H4700)
-#else
-# define machine_is_h4700()	(0)
-#endif
-
-#ifdef CONFIG_MACH_H6300
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_H6300
-# endif
-# define machine_is_h6300()	(machine_arch_type == MACH_TYPE_H6300)
-#else
-# define machine_is_h6300()	(0)
-#endif
-
-#ifdef CONFIG_MACH_RZ1700
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_RZ1700
-# endif
-# define machine_is_rz1700()	(machine_arch_type == MACH_TYPE_RZ1700)
-#else
-# define machine_is_rz1700()	(0)
-#endif
-
-#ifdef CONFIG_MACH_A716
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_A716
-# endif
-# define machine_is_a716()	(machine_arch_type == MACH_TYPE_A716)
-#else
-# define machine_is_a716()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ESTK2440A
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ESTK2440A
-# endif
-# define machine_is_estk2440a()	(machine_arch_type == MACH_TYPE_ESTK2440A)
-#else
-# define machine_is_estk2440a()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ATWIXP425
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ATWIXP425
-# endif
-# define machine_is_atwixp425()	(machine_arch_type == MACH_TYPE_ATWIXP425)
-#else
-# define machine_is_atwixp425()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CSB336
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CSB336
-# endif
-# define machine_is_csb336()	(machine_arch_type == MACH_TYPE_CSB336)
-#else
-# define machine_is_csb336()	(0)
-#endif
-
-#ifdef CONFIG_MACH_RIRM2
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_RIRM2
-# endif
-# define machine_is_rirm2()	(machine_arch_type == MACH_TYPE_RIRM2)
-#else
-# define machine_is_rirm2()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CX23518
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CX23518
-# endif
-# define machine_is_cx23518()	(machine_arch_type == MACH_TYPE_CX23518)
-#else
-# define machine_is_cx23518()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CX2351X
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CX2351X
-# endif
-# define machine_is_cx2351x()	(machine_arch_type == MACH_TYPE_CX2351X)
-#else
-# define machine_is_cx2351x()	(0)
-#endif
-
-#ifdef CONFIG_MACH_COMPUTIME
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_COMPUTIME
-# endif
-# define machine_is_computime()	(machine_arch_type == MACH_TYPE_COMPUTIME)
-#else
-# define machine_is_computime()	(0)
-#endif
-
-#ifdef CONFIG_MACH_IZARUS
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_IZARUS
-# endif
-# define machine_is_izarus()	(machine_arch_type == MACH_TYPE_IZARUS)
-#else
-# define machine_is_izarus()	(0)
-#endif
-
-#ifdef CONFIG_MACH_RTS
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_RTS
-# endif
-# define machine_is_pxa_rts()	(machine_arch_type == MACH_TYPE_RTS)
-#else
-# define machine_is_pxa_rts()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SE5100
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SE5100
-# endif
-# define machine_is_se5100()	(machine_arch_type == MACH_TYPE_SE5100)
-#else
-# define machine_is_se5100()	(0)
-#endif
-
-#ifdef CONFIG_MACH_S3C2510
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_S3C2510
-# endif
-# define machine_is_s3c2510()	(machine_arch_type == MACH_TYPE_S3C2510)
-#else
-# define machine_is_s3c2510()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CSB437TL
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CSB437TL
-# endif
-# define machine_is_csb437tl()	(machine_arch_type == MACH_TYPE_CSB437TL)
-#else
-# define machine_is_csb437tl()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SLAUSON
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SLAUSON
-# endif
-# define machine_is_slauson()	(machine_arch_type == MACH_TYPE_SLAUSON)
-#else
-# define machine_is_slauson()	(0)
-#endif
-
-#ifdef CONFIG_MACH_PEARLRIVER
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PEARLRIVER
-# endif
-# define machine_is_pearlriver()	(machine_arch_type == MACH_TYPE_PEARLRIVER)
-#else
-# define machine_is_pearlriver()	(0)
-#endif
-
-#ifdef CONFIG_MACH_TDC_P210
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TDC_P210
-# endif
-# define machine_is_tdc_p210()	(machine_arch_type == MACH_TYPE_TDC_P210)
-#else
-# define machine_is_tdc_p210()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SG580
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SG580
-# endif
-# define machine_is_sg580()	(machine_arch_type == MACH_TYPE_SG580)
-#else
-# define machine_is_sg580()	(0)
-#endif
-
-#ifdef CONFIG_MACH_WRSBCARM7
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_WRSBCARM7
-# endif
-# define machine_is_wrsbcarm7()	(machine_arch_type == MACH_TYPE_WRSBCARM7)
-#else
-# define machine_is_wrsbcarm7()	(0)
-#endif
-
-#ifdef CONFIG_MACH_IPD
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_IPD
-# endif
-# define machine_is_ipd()	(machine_arch_type == MACH_TYPE_IPD)
-#else
-# define machine_is_ipd()	(0)
-#endif
-
-#ifdef CONFIG_MACH_PXA_DNP2110
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PXA_DNP2110
-# endif
-# define machine_is_pxa_dnp2110()	(machine_arch_type == MACH_TYPE_PXA_DNP2110)
-#else
-# define machine_is_pxa_dnp2110()	(0)
-#endif
-
-#ifdef CONFIG_MACH_XAENIAX
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_XAENIAX
-# endif
-# define machine_is_xaeniax()	(machine_arch_type == MACH_TYPE_XAENIAX)
-#else
-# define machine_is_xaeniax()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SOMN4250
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SOMN4250
-# endif
-# define machine_is_somn4250()	(machine_arch_type == MACH_TYPE_SOMN4250)
-#else
-# define machine_is_somn4250()	(0)
-#endif
-
-#ifdef CONFIG_MACH_PLEB2
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PLEB2
-# endif
-# define machine_is_pleb2()	(machine_arch_type == MACH_TYPE_PLEB2)
-#else
-# define machine_is_pleb2()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CORNWALLIS
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CORNWALLIS
-# endif
-# define machine_is_cornwallis()	(machine_arch_type == MACH_TYPE_CORNWALLIS)
-#else
-# define machine_is_cornwallis()	(0)
-#endif
-
-#ifdef CONFIG_MACH_GURNEY_DRV
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_GURNEY_DRV
-# endif
-# define machine_is_gurney_drv()	(machine_arch_type == MACH_TYPE_GURNEY_DRV)
-#else
-# define machine_is_gurney_drv()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CHAFFEE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CHAFFEE
-# endif
-# define machine_is_chaffee()	(machine_arch_type == MACH_TYPE_CHAFFEE)
-#else
-# define machine_is_chaffee()	(0)
-#endif
-
-#ifdef CONFIG_MACH_RMS101
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_RMS101
-# endif
-# define machine_is_rms101()	(machine_arch_type == MACH_TYPE_RMS101)
-#else
-# define machine_is_rms101()	(0)
-#endif
-
-#ifdef CONFIG_MACH_RX3715
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_RX3715
-# endif
-# define machine_is_rx3715()	(machine_arch_type == MACH_TYPE_RX3715)
-#else
-# define machine_is_rx3715()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SWIFT
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SWIFT
-# endif
-# define machine_is_swift()	(machine_arch_type == MACH_TYPE_SWIFT)
-#else
-# define machine_is_swift()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ROVERP7
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ROVERP7
-# endif
-# define machine_is_roverp7()	(machine_arch_type == MACH_TYPE_ROVERP7)
-#else
-# define machine_is_roverp7()	(0)
-#endif
-
-#ifdef CONFIG_MACH_PR818S
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PR818S
-# endif
-# define machine_is_pr818s()	(machine_arch_type == MACH_TYPE_PR818S)
-#else
-# define machine_is_pr818s()	(0)
-#endif
-
-#ifdef CONFIG_MACH_TRXPRO
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TRXPRO
-# endif
-# define machine_is_trxpro()	(machine_arch_type == MACH_TYPE_TRXPRO)
-#else
-# define machine_is_trxpro()	(0)
-#endif
-
-#ifdef CONFIG_MACH_NSLU2
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_NSLU2
-# endif
-# define machine_is_nslu2()	(machine_arch_type == MACH_TYPE_NSLU2)
-#else
-# define machine_is_nslu2()	(0)
-#endif
-
-#ifdef CONFIG_MACH_E400
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_E400
-# endif
-# define machine_is_e400()	(machine_arch_type == MACH_TYPE_E400)
-#else
-# define machine_is_e400()	(0)
-#endif
-
-#ifdef CONFIG_MACH_TRAB
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TRAB
-# endif
-# define machine_is_trab()	(machine_arch_type == MACH_TYPE_TRAB)
-#else
-# define machine_is_trab()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CMC_PU2
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CMC_PU2
-# endif
-# define machine_is_cmc_pu2()	(machine_arch_type == MACH_TYPE_CMC_PU2)
-#else
-# define machine_is_cmc_pu2()	(0)
-#endif
-
-#ifdef CONFIG_MACH_FULCRUM
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_FULCRUM
-# endif
-# define machine_is_fulcrum()	(machine_arch_type == MACH_TYPE_FULCRUM)
-#else
-# define machine_is_fulcrum()	(0)
-#endif
-
-#ifdef CONFIG_MACH_NETGATE42X
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_NETGATE42X
-# endif
-# define machine_is_netgate42x()	(machine_arch_type == MACH_TYPE_NETGATE42X)
-#else
-# define machine_is_netgate42x()	(0)
-#endif
-
-#ifdef CONFIG_MACH_STR710
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_STR710
-# endif
-# define machine_is_str710()	(machine_arch_type == MACH_TYPE_STR710)
-#else
-# define machine_is_str710()	(0)
-#endif
-
-#ifdef CONFIG_MACH_IXDPG425
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_IXDPG425
-# endif
-# define machine_is_ixdpg425()	(machine_arch_type == MACH_TYPE_IXDPG425)
-#else
-# define machine_is_ixdpg425()	(0)
-#endif
-
-#ifdef CONFIG_MACH_TOMTOMGO
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TOMTOMGO
-# endif
-# define machine_is_tomtomgo()	(machine_arch_type == MACH_TYPE_TOMTOMGO)
-#else
-# define machine_is_tomtomgo()	(0)
-#endif
-
-#ifdef CONFIG_MACH_VERSATILE_AB
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_VERSATILE_AB
-# endif
-# define machine_is_versatile_ab()	(machine_arch_type == MACH_TYPE_VERSATILE_AB)
-#else
-# define machine_is_versatile_ab()	(0)
-#endif
-
-#ifdef CONFIG_MACH_EDB9307
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_EDB9307
-# endif
-# define machine_is_edb9307()	(machine_arch_type == MACH_TYPE_EDB9307)
-#else
-# define machine_is_edb9307()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SG565
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SG565
-# endif
-# define machine_is_sg565()	(machine_arch_type == MACH_TYPE_SG565)
-#else
-# define machine_is_sg565()	(0)
-#endif
-
-#ifdef CONFIG_MACH_LPD79524
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_LPD79524
-# endif
-# define machine_is_lpd79524()	(machine_arch_type == MACH_TYPE_LPD79524)
-#else
-# define machine_is_lpd79524()	(0)
-#endif
-
-#ifdef CONFIG_MACH_LPD79525
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_LPD79525
-# endif
-# define machine_is_lpd79525()	(machine_arch_type == MACH_TYPE_LPD79525)
-#else
-# define machine_is_lpd79525()	(0)
-#endif
-
-#ifdef CONFIG_MACH_RMS100
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_RMS100
-# endif
-# define machine_is_rms100()	(machine_arch_type == MACH_TYPE_RMS100)
-#else
-# define machine_is_rms100()	(0)
-#endif
-
-#ifdef CONFIG_MACH_KB9200
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_KB9200
-# endif
-# define machine_is_kb9200()	(machine_arch_type == MACH_TYPE_KB9200)
-#else
-# define machine_is_kb9200()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SX1
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SX1
-# endif
-# define machine_is_sx1()	(machine_arch_type == MACH_TYPE_SX1)
-#else
-# define machine_is_sx1()	(0)
-#endif
-
-#ifdef CONFIG_MACH_HMS39C7092
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_HMS39C7092
-# endif
-# define machine_is_hms39c7092()	(machine_arch_type == MACH_TYPE_HMS39C7092)
-#else
-# define machine_is_hms39c7092()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ARMADILLO
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ARMADILLO
-# endif
-# define machine_is_armadillo()	(machine_arch_type == MACH_TYPE_ARMADILLO)
-#else
-# define machine_is_armadillo()	(0)
-#endif
-
-#ifdef CONFIG_MACH_IPCU
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_IPCU
-# endif
-# define machine_is_ipcu()	(machine_arch_type == MACH_TYPE_IPCU)
-#else
-# define machine_is_ipcu()	(0)
-#endif
-
-#ifdef CONFIG_MACH_LOOX720
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_LOOX720
-# endif
-# define machine_is_loox720()	(machine_arch_type == MACH_TYPE_LOOX720)
-#else
-# define machine_is_loox720()	(0)
-#endif
-
-#ifdef CONFIG_MACH_IXDP465
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_IXDP465
-# endif
-# define machine_is_ixdp465()	(machine_arch_type == MACH_TYPE_IXDP465)
-#else
-# define machine_is_ixdp465()	(0)
-#endif
-
-#ifdef CONFIG_MACH_IXDP2351
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_IXDP2351
-# endif
-# define machine_is_ixdp2351()	(machine_arch_type == MACH_TYPE_IXDP2351)
-#else
-# define machine_is_ixdp2351()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ADSVIX
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ADSVIX
-# endif
-# define machine_is_adsvix()	(machine_arch_type == MACH_TYPE_ADSVIX)
-#else
-# define machine_is_adsvix()	(0)
-#endif
-
-#ifdef CONFIG_MACH_DM270
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_DM270
-# endif
-# define machine_is_dm270()	(machine_arch_type == MACH_TYPE_DM270)
-#else
-# define machine_is_dm270()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SOCLTPLUS
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SOCLTPLUS
-# endif
-# define machine_is_socltplus()	(machine_arch_type == MACH_TYPE_SOCLTPLUS)
-#else
-# define machine_is_socltplus()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ECIA
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ECIA
-# endif
-# define machine_is_ecia()	(machine_arch_type == MACH_TYPE_ECIA)
-#else
-# define machine_is_ecia()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CM4008
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CM4008
-# endif
-# define machine_is_cm4008()	(machine_arch_type == MACH_TYPE_CM4008)
-#else
-# define machine_is_cm4008()	(0)
-#endif
-
-#ifdef CONFIG_MACH_P2001
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_P2001
-# endif
-# define machine_is_p2001()	(machine_arch_type == MACH_TYPE_P2001)
-#else
-# define machine_is_p2001()	(0)
-#endif
-
-#ifdef CONFIG_MACH_TWISTER
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TWISTER
-# endif
-# define machine_is_twister()	(machine_arch_type == MACH_TYPE_TWISTER)
-#else
-# define machine_is_twister()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MUDSHARK
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MUDSHARK
-# endif
-# define machine_is_mudshark()	(machine_arch_type == MACH_TYPE_MUDSHARK)
-#else
-# define machine_is_mudshark()	(0)
-#endif
-
-#ifdef CONFIG_MACH_HB2
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_HB2
-# endif
-# define machine_is_hb2()	(machine_arch_type == MACH_TYPE_HB2)
-#else
-# define machine_is_hb2()	(0)
-#endif
-
-#ifdef CONFIG_MACH_IQ80332
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_IQ80332
-# endif
-# define machine_is_iq80332()	(machine_arch_type == MACH_TYPE_IQ80332)
-#else
-# define machine_is_iq80332()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SENDT
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SENDT
-# endif
-# define machine_is_sendt()	(machine_arch_type == MACH_TYPE_SENDT)
-#else
-# define machine_is_sendt()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MX2JAZZ
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MX2JAZZ
-# endif
-# define machine_is_mx2jazz()	(machine_arch_type == MACH_TYPE_MX2JAZZ)
-#else
-# define machine_is_mx2jazz()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MULTIIO
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MULTIIO
-# endif
-# define machine_is_multiio()	(machine_arch_type == MACH_TYPE_MULTIIO)
-#else
-# define machine_is_multiio()	(0)
-#endif
-
-#ifdef CONFIG_MACH_HRDISPLAY
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_HRDISPLAY
-# endif
-# define machine_is_hrdisplay()	(machine_arch_type == MACH_TYPE_HRDISPLAY)
-#else
-# define machine_is_hrdisplay()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MXC27530ADS
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MXC27530ADS
-# endif
-# define machine_is_mxc27530ads()	(machine_arch_type == MACH_TYPE_MXC27530ADS)
-#else
-# define machine_is_mxc27530ads()	(0)
-#endif
-
-#ifdef CONFIG_MACH_TRIZEPS3
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TRIZEPS3
-# endif
-# define machine_is_trizeps3()	(machine_arch_type == MACH_TYPE_TRIZEPS3)
-#else
-# define machine_is_trizeps3()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ZEFEERDZA
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ZEFEERDZA
-# endif
-# define machine_is_zefeerdza()	(machine_arch_type == MACH_TYPE_ZEFEERDZA)
-#else
-# define machine_is_zefeerdza()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ZEFEERDZB
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ZEFEERDZB
-# endif
-# define machine_is_zefeerdzb()	(machine_arch_type == MACH_TYPE_ZEFEERDZB)
-#else
-# define machine_is_zefeerdzb()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ZEFEERDZG
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ZEFEERDZG
-# endif
-# define machine_is_zefeerdzg()	(machine_arch_type == MACH_TYPE_ZEFEERDZG)
-#else
-# define machine_is_zefeerdzg()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ZEFEERDZN
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ZEFEERDZN
-# endif
-# define machine_is_zefeerdzn()	(machine_arch_type == MACH_TYPE_ZEFEERDZN)
-#else
-# define machine_is_zefeerdzn()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ZEFEERDZQ
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ZEFEERDZQ
-# endif
-# define machine_is_zefeerdzq()	(machine_arch_type == MACH_TYPE_ZEFEERDZQ)
-#else
-# define machine_is_zefeerdzq()	(0)
-#endif
-
-#ifdef CONFIG_MACH_GTWX5715
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_GTWX5715
-# endif
-# define machine_is_gtwx5715()	(machine_arch_type == MACH_TYPE_GTWX5715)
-#else
-# define machine_is_gtwx5715()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ASTRO_JACK
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ASTRO_JACK
-# endif
-# define machine_is_astro_jack()	(machine_arch_type == MACH_TYPE_ASTRO_JACK)
-#else
-# define machine_is_astro_jack()	(0)
-#endif
-
-#ifdef CONFIG_MACH_TIP03
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TIP03
-# endif
-# define machine_is_tip03()	(machine_arch_type == MACH_TYPE_TIP03)
-#else
-# define machine_is_tip03()	(0)
-#endif
-
-#ifdef CONFIG_MACH_A9200EC
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_A9200EC
-# endif
-# define machine_is_a9200ec()	(machine_arch_type == MACH_TYPE_A9200EC)
-#else
-# define machine_is_a9200ec()	(0)
-#endif
-
-#ifdef CONFIG_MACH_PNX0105
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PNX0105
-# endif
-# define machine_is_pnx0105()	(machine_arch_type == MACH_TYPE_PNX0105)
-#else
-# define machine_is_pnx0105()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ADCPOECPU
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ADCPOECPU
-# endif
-# define machine_is_adcpoecpu()	(machine_arch_type == MACH_TYPE_ADCPOECPU)
-#else
-# define machine_is_adcpoecpu()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CSB637
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CSB637
-# endif
-# define machine_is_csb637()	(machine_arch_type == MACH_TYPE_CSB637)
-#else
-# define machine_is_csb637()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MB9200
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MB9200
-# endif
-# define machine_is_mb9200()	(machine_arch_type == MACH_TYPE_MB9200)
-#else
-# define machine_is_mb9200()	(0)
-#endif
-
-#ifdef CONFIG_MACH_KULUN
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_KULUN
-# endif
-# define machine_is_kulun()	(machine_arch_type == MACH_TYPE_KULUN)
-#else
-# define machine_is_kulun()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SNAPPER
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SNAPPER
-# endif
-# define machine_is_snapper()	(machine_arch_type == MACH_TYPE_SNAPPER)
-#else
-# define machine_is_snapper()	(0)
-#endif
-
-#ifdef CONFIG_MACH_OPTIMA
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_OPTIMA
-# endif
-# define machine_is_optima()	(machine_arch_type == MACH_TYPE_OPTIMA)
-#else
-# define machine_is_optima()	(0)
-#endif
-
-#ifdef CONFIG_MACH_DLHSBC
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_DLHSBC
-# endif
-# define machine_is_dlhsbc()	(machine_arch_type == MACH_TYPE_DLHSBC)
-#else
-# define machine_is_dlhsbc()	(0)
-#endif
-
-#ifdef CONFIG_MACH_X30
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_X30
-# endif
-# define machine_is_x30()	(machine_arch_type == MACH_TYPE_X30)
-#else
-# define machine_is_x30()	(0)
-#endif
-
-#ifdef CONFIG_MACH_N30
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_N30
-# endif
-# define machine_is_n30()	(machine_arch_type == MACH_TYPE_N30)
-#else
-# define machine_is_n30()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MANGA_KS8695
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MANGA_KS8695
-# endif
-# define machine_is_manga_ks8695()	(machine_arch_type == MACH_TYPE_MANGA_KS8695)
-#else
-# define machine_is_manga_ks8695()	(0)
-#endif
-
-#ifdef CONFIG_MACH_AJAX
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_AJAX
-# endif
-# define machine_is_ajax()	(machine_arch_type == MACH_TYPE_AJAX)
-#else
-# define machine_is_ajax()	(0)
-#endif
-
-#ifdef CONFIG_MACH_NEC_MP900
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_NEC_MP900
-# endif
-# define machine_is_nec_mp900()	(machine_arch_type == MACH_TYPE_NEC_MP900)
-#else
-# define machine_is_nec_mp900()	(0)
-#endif
-
-#ifdef CONFIG_MACH_VVTK1000
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_VVTK1000
-# endif
-# define machine_is_vvtk1000()	(machine_arch_type == MACH_TYPE_VVTK1000)
-#else
-# define machine_is_vvtk1000()	(0)
-#endif
-
-#ifdef CONFIG_MACH_KAFA
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_KAFA
-# endif
-# define machine_is_kafa()	(machine_arch_type == MACH_TYPE_KAFA)
-#else
-# define machine_is_kafa()	(0)
-#endif
-
-#ifdef CONFIG_MACH_VVTK3000
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_VVTK3000
-# endif
-# define machine_is_vvtk3000()	(machine_arch_type == MACH_TYPE_VVTK3000)
-#else
-# define machine_is_vvtk3000()	(0)
-#endif
-
-#ifdef CONFIG_MACH_PIMX1
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PIMX1
-# endif
-# define machine_is_pimx1()	(machine_arch_type == MACH_TYPE_PIMX1)
-#else
-# define machine_is_pimx1()	(0)
-#endif
-
-#ifdef CONFIG_MACH_OLLIE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_OLLIE
-# endif
-# define machine_is_ollie()	(machine_arch_type == MACH_TYPE_OLLIE)
-#else
-# define machine_is_ollie()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SKYMAX
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SKYMAX
-# endif
-# define machine_is_skymax()	(machine_arch_type == MACH_TYPE_SKYMAX)
-#else
-# define machine_is_skymax()	(0)
-#endif
-
-#ifdef CONFIG_MACH_JAZZ
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_JAZZ
-# endif
-# define machine_is_jazz()	(machine_arch_type == MACH_TYPE_JAZZ)
-#else
-# define machine_is_jazz()	(0)
-#endif
-
-#ifdef CONFIG_MACH_TEL_T3
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TEL_T3
-# endif
-# define machine_is_tel_t3()	(machine_arch_type == MACH_TYPE_TEL_T3)
-#else
-# define machine_is_tel_t3()	(0)
-#endif
-
-#ifdef CONFIG_MACH_AISINO_FCR255
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_AISINO_FCR255
-# endif
-# define machine_is_aisino_fcr255()	(machine_arch_type == MACH_TYPE_AISINO_FCR255)
-#else
-# define machine_is_aisino_fcr255()	(0)
-#endif
-
-#ifdef CONFIG_MACH_BTWEB
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_BTWEB
-# endif
-# define machine_is_btweb()	(machine_arch_type == MACH_TYPE_BTWEB)
-#else
-# define machine_is_btweb()	(0)
-#endif
-
-#ifdef CONFIG_MACH_DBG_LH79520
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_DBG_LH79520
-# endif
-# define machine_is_dbg_lh79520()	(machine_arch_type == MACH_TYPE_DBG_LH79520)
-#else
-# define machine_is_dbg_lh79520()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CM41XX
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CM41XX
-# endif
-# define machine_is_cm41xx()	(machine_arch_type == MACH_TYPE_CM41XX)
-#else
-# define machine_is_cm41xx()	(0)
-#endif
-
-#ifdef CONFIG_MACH_TS72XX
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TS72XX
-# endif
-# define machine_is_ts72xx()	(machine_arch_type == MACH_TYPE_TS72XX)
-#else
-# define machine_is_ts72xx()	(0)
-#endif
-
-#ifdef CONFIG_MACH_NGGPXA
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_NGGPXA
-# endif
-# define machine_is_nggpxa()	(machine_arch_type == MACH_TYPE_NGGPXA)
-#else
-# define machine_is_nggpxa()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CSB535
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CSB535
-# endif
-# define machine_is_csb535()	(machine_arch_type == MACH_TYPE_CSB535)
-#else
-# define machine_is_csb535()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CSB536
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CSB536
-# endif
-# define machine_is_csb536()	(machine_arch_type == MACH_TYPE_CSB536)
-#else
-# define machine_is_csb536()	(0)
-#endif
-
-#ifdef CONFIG_MACH_PXA_TRAKPOD
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PXA_TRAKPOD
-# endif
-# define machine_is_pxa_trakpod()	(machine_arch_type == MACH_TYPE_PXA_TRAKPOD)
-#else
-# define machine_is_pxa_trakpod()	(0)
-#endif
-
-#ifdef CONFIG_MACH_PRAXIS
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PRAXIS
-# endif
-# define machine_is_praxis()	(machine_arch_type == MACH_TYPE_PRAXIS)
-#else
-# define machine_is_praxis()	(0)
-#endif
-
-#ifdef CONFIG_MACH_LH75411
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_LH75411
-# endif
-# define machine_is_lh75411()	(machine_arch_type == MACH_TYPE_LH75411)
-#else
-# define machine_is_lh75411()	(0)
-#endif
-
-#ifdef CONFIG_MACH_OTOM
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_OTOM
-# endif
-# define machine_is_otom()	(machine_arch_type == MACH_TYPE_OTOM)
-#else
-# define machine_is_otom()	(0)
-#endif
-
-#ifdef CONFIG_MACH_NEXCODER_2440
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_NEXCODER_2440
-# endif
-# define machine_is_nexcoder_2440()	(machine_arch_type == MACH_TYPE_NEXCODER_2440)
-#else
-# define machine_is_nexcoder_2440()	(0)
-#endif
-
-#ifdef CONFIG_MACH_LOOX410
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_LOOX410
-# endif
-# define machine_is_loox410()	(machine_arch_type == MACH_TYPE_LOOX410)
-#else
-# define machine_is_loox410()	(0)
-#endif
-
-#ifdef CONFIG_MACH_WESTLAKE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_WESTLAKE
-# endif
-# define machine_is_westlake()	(machine_arch_type == MACH_TYPE_WESTLAKE)
-#else
-# define machine_is_westlake()	(0)
-#endif
-
-#ifdef CONFIG_MACH_NSB
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_NSB
-# endif
-# define machine_is_nsb()	(machine_arch_type == MACH_TYPE_NSB)
-#else
-# define machine_is_nsb()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ESL_SARVA_STN
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ESL_SARVA_STN
-# endif
-# define machine_is_esl_sarva_stn()	(machine_arch_type == MACH_TYPE_ESL_SARVA_STN)
-#else
-# define machine_is_esl_sarva_stn()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ESL_SARVA_TFT
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ESL_SARVA_TFT
-# endif
-# define machine_is_esl_sarva_tft()	(machine_arch_type == MACH_TYPE_ESL_SARVA_TFT)
-#else
-# define machine_is_esl_sarva_tft()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ESL_SARVA_IAD
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ESL_SARVA_IAD
-# endif
-# define machine_is_esl_sarva_iad()	(machine_arch_type == MACH_TYPE_ESL_SARVA_IAD)
-#else
-# define machine_is_esl_sarva_iad()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ESL_SARVA_ACC
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ESL_SARVA_ACC
-# endif
-# define machine_is_esl_sarva_acc()	(machine_arch_type == MACH_TYPE_ESL_SARVA_ACC)
-#else
-# define machine_is_esl_sarva_acc()	(0)
-#endif
-
-#ifdef CONFIG_MACH_TYPHOON
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TYPHOON
-# endif
-# define machine_is_typhoon()	(machine_arch_type == MACH_TYPE_TYPHOON)
-#else
-# define machine_is_typhoon()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CNAV
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CNAV
-# endif
-# define machine_is_cnav()	(machine_arch_type == MACH_TYPE_CNAV)
-#else
-# define machine_is_cnav()	(0)
-#endif
-
-#ifdef CONFIG_MACH_A730
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_A730
-# endif
-# define machine_is_a730()	(machine_arch_type == MACH_TYPE_A730)
-#else
-# define machine_is_a730()	(0)
-#endif
-
-#ifdef CONFIG_MACH_NETSTAR
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_NETSTAR
-# endif
-# define machine_is_netstar()	(machine_arch_type == MACH_TYPE_NETSTAR)
-#else
-# define machine_is_netstar()	(0)
-#endif
-
-#ifdef CONFIG_MACH_PHASEFALE_SUPERCON
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PHASEFALE_SUPERCON
-# endif
-# define machine_is_supercon()	(machine_arch_type == MACH_TYPE_PHASEFALE_SUPERCON)
-#else
-# define machine_is_supercon()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SHIVA1100
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SHIVA1100
-# endif
-# define machine_is_shiva1100()	(machine_arch_type == MACH_TYPE_SHIVA1100)
-#else
-# define machine_is_shiva1100()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ETEXSC
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ETEXSC
-# endif
-# define machine_is_etexsc()	(machine_arch_type == MACH_TYPE_ETEXSC)
-#else
-# define machine_is_etexsc()	(0)
-#endif
-
-#ifdef CONFIG_MACH_IXDPG465
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_IXDPG465
-# endif
-# define machine_is_ixdpg465()	(machine_arch_type == MACH_TYPE_IXDPG465)
-#else
-# define machine_is_ixdpg465()	(0)
-#endif
-
-#ifdef CONFIG_MACH_A9M2410
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_A9M2410
-# endif
-# define machine_is_a9m2410()	(machine_arch_type == MACH_TYPE_A9M2410)
-#else
-# define machine_is_a9m2410()	(0)
-#endif
-
-#ifdef CONFIG_MACH_A9M2440
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_A9M2440
-# endif
-# define machine_is_a9m2440()	(machine_arch_type == MACH_TYPE_A9M2440)
-#else
-# define machine_is_a9m2440()	(0)
-#endif
-
-#ifdef CONFIG_MACH_A9M9750
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_A9M9750
-# endif
-# define machine_is_a9m9750()	(machine_arch_type == MACH_TYPE_A9M9750)
-#else
-# define machine_is_a9m9750()	(0)
-#endif
-
-#ifdef CONFIG_MACH_A9M9360
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_A9M9360
-# endif
-# define machine_is_a9m9360()	(machine_arch_type == MACH_TYPE_A9M9360)
-#else
-# define machine_is_a9m9360()	(0)
-#endif
-
-#ifdef CONFIG_MACH_UNC90
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_UNC90
-# endif
-# define machine_is_unc90()	(machine_arch_type == MACH_TYPE_UNC90)
-#else
-# define machine_is_unc90()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ECO920
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ECO920
-# endif
-# define machine_is_eco920()	(machine_arch_type == MACH_TYPE_ECO920)
-#else
-# define machine_is_eco920()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SATVIEW
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SATVIEW
-# endif
-# define machine_is_satview()	(machine_arch_type == MACH_TYPE_SATVIEW)
-#else
-# define machine_is_satview()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ROADRUNNER
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ROADRUNNER
-# endif
-# define machine_is_roadrunner()	(machine_arch_type == MACH_TYPE_ROADRUNNER)
-#else
-# define machine_is_roadrunner()	(0)
-#endif
-
-#ifdef CONFIG_MACH_AT91RM9200EK
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_AT91RM9200EK
-# endif
-# define machine_is_at91rm9200ek()	(machine_arch_type == MACH_TYPE_AT91RM9200EK)
-#else
-# define machine_is_at91rm9200ek()	(0)
-#endif
-
-#ifdef CONFIG_MACH_GP32
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_GP32
-# endif
-# define machine_is_gp32()	(machine_arch_type == MACH_TYPE_GP32)
-#else
-# define machine_is_gp32()	(0)
-#endif
-
-#ifdef CONFIG_MACH_GEM
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_GEM
-# endif
-# define machine_is_gem()	(machine_arch_type == MACH_TYPE_GEM)
-#else
-# define machine_is_gem()	(0)
-#endif
-
-#ifdef CONFIG_MACH_I858
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_I858
-# endif
-# define machine_is_i858()	(machine_arch_type == MACH_TYPE_I858)
-#else
-# define machine_is_i858()	(0)
-#endif
-
-#ifdef CONFIG_MACH_HX2750
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_HX2750
-# endif
-# define machine_is_hx2750()	(machine_arch_type == MACH_TYPE_HX2750)
-#else
-# define machine_is_hx2750()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MXC91131EVB
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MXC91131EVB
-# endif
-# define machine_is_mxc91131evb()	(machine_arch_type == MACH_TYPE_MXC91131EVB)
-#else
-# define machine_is_mxc91131evb()	(0)
-#endif
-
-#ifdef CONFIG_MACH_P700
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_P700
-# endif
-# define machine_is_p700()	(machine_arch_type == MACH_TYPE_P700)
-#else
-# define machine_is_p700()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CPE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CPE
-# endif
-# define machine_is_cpe()	(machine_arch_type == MACH_TYPE_CPE)
-#else
-# define machine_is_cpe()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SPITZ
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SPITZ
-# endif
-# define machine_is_spitz()	(machine_arch_type == MACH_TYPE_SPITZ)
-#else
-# define machine_is_spitz()	(0)
-#endif
-
-#ifdef CONFIG_MACH_NIMBRA340
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_NIMBRA340
-# endif
-# define machine_is_nimbra340()	(machine_arch_type == MACH_TYPE_NIMBRA340)
-#else
-# define machine_is_nimbra340()	(0)
-#endif
-
-#ifdef CONFIG_MACH_LPC22XX
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_LPC22XX
-# endif
-# define machine_is_lpc22xx()	(machine_arch_type == MACH_TYPE_LPC22XX)
-#else
-# define machine_is_lpc22xx()	(0)
-#endif
-
-#ifdef CONFIG_MACH_COMET3
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_COMET3
-# endif
-# define machine_is_omap_comet3()	(machine_arch_type == MACH_TYPE_COMET3)
-#else
-# define machine_is_omap_comet3()	(0)
-#endif
-
-#ifdef CONFIG_MACH_COMET4
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_COMET4
-# endif
-# define machine_is_omap_comet4()	(machine_arch_type == MACH_TYPE_COMET4)
-#else
-# define machine_is_omap_comet4()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CSB625
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CSB625
-# endif
-# define machine_is_csb625()	(machine_arch_type == MACH_TYPE_CSB625)
-#else
-# define machine_is_csb625()	(0)
-#endif
-
-#ifdef CONFIG_MACH_FORTUNET2
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_FORTUNET2
-# endif
-# define machine_is_fortunet2()	(machine_arch_type == MACH_TYPE_FORTUNET2)
-#else
-# define machine_is_fortunet2()	(0)
-#endif
-
-#ifdef CONFIG_MACH_S5H2200
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_S5H2200
-# endif
-# define machine_is_s5h2200()	(machine_arch_type == MACH_TYPE_S5H2200)
-#else
-# define machine_is_s5h2200()	(0)
-#endif
-
-#ifdef CONFIG_MACH_OPTORM920
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_OPTORM920
-# endif
-# define machine_is_optorm920()	(machine_arch_type == MACH_TYPE_OPTORM920)
-#else
-# define machine_is_optorm920()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ADSBITSYXB
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ADSBITSYXB
-# endif
-# define machine_is_adsbitsyxb()	(machine_arch_type == MACH_TYPE_ADSBITSYXB)
-#else
-# define machine_is_adsbitsyxb()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ADSSPHERE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ADSSPHERE
-# endif
-# define machine_is_adssphere()	(machine_arch_type == MACH_TYPE_ADSSPHERE)
-#else
-# define machine_is_adssphere()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ADSPORTAL
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ADSPORTAL
-# endif
-# define machine_is_adsportal()	(machine_arch_type == MACH_TYPE_ADSPORTAL)
-#else
-# define machine_is_adsportal()	(0)
-#endif
-
-#ifdef CONFIG_MACH_LN2410SBC
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_LN2410SBC
-# endif
-# define machine_is_ln2410sbc()	(machine_arch_type == MACH_TYPE_LN2410SBC)
-#else
-# define machine_is_ln2410sbc()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CB3RUFC
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CB3RUFC
-# endif
-# define machine_is_cb3rufc()	(machine_arch_type == MACH_TYPE_CB3RUFC)
-#else
-# define machine_is_cb3rufc()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MP2USB
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MP2USB
-# endif
-# define machine_is_mp2usb()	(machine_arch_type == MACH_TYPE_MP2USB)
-#else
-# define machine_is_mp2usb()	(0)
-#endif
-
-#ifdef CONFIG_MACH_NTNP425C
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_NTNP425C
-# endif
-# define machine_is_ntnp425c()	(machine_arch_type == MACH_TYPE_NTNP425C)
-#else
-# define machine_is_ntnp425c()	(0)
-#endif
-
-#ifdef CONFIG_MACH_COLIBRI
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_COLIBRI
-# endif
-# define machine_is_colibri()	(machine_arch_type == MACH_TYPE_COLIBRI)
-#else
-# define machine_is_colibri()	(0)
-#endif
-
-#ifdef CONFIG_MACH_PCM7220
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PCM7220
-# endif
-# define machine_is_pcm7220()	(machine_arch_type == MACH_TYPE_PCM7220)
-#else
-# define machine_is_pcm7220()	(0)
-#endif
-
-#ifdef CONFIG_MACH_GATEWAY7001
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_GATEWAY7001
-# endif
-# define machine_is_gateway7001()	(machine_arch_type == MACH_TYPE_GATEWAY7001)
-#else
-# define machine_is_gateway7001()	(0)
-#endif
-
-#ifdef CONFIG_MACH_PCM027
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PCM027
-# endif
-# define machine_is_pcm027()	(machine_arch_type == MACH_TYPE_PCM027)
-#else
-# define machine_is_pcm027()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CMPXA
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CMPXA
-# endif
-# define machine_is_cmpxa()	(machine_arch_type == MACH_TYPE_CMPXA)
-#else
-# define machine_is_cmpxa()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ANUBIS
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ANUBIS
-# endif
-# define machine_is_anubis()	(machine_arch_type == MACH_TYPE_ANUBIS)
-#else
-# define machine_is_anubis()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ITE8152
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ITE8152
-# endif
-# define machine_is_ite8152()	(machine_arch_type == MACH_TYPE_ITE8152)
-#else
-# define machine_is_ite8152()	(0)
-#endif
-
-#ifdef CONFIG_MACH_LPC3XXX
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_LPC3XXX
-# endif
-# define machine_is_lpc3xxx()	(machine_arch_type == MACH_TYPE_LPC3XXX)
-#else
-# define machine_is_lpc3xxx()	(0)
-#endif
-
-#ifdef CONFIG_MACH_PUPPETEER
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PUPPETEER
-# endif
-# define machine_is_puppeteer()	(machine_arch_type == MACH_TYPE_PUPPETEER)
-#else
-# define machine_is_puppeteer()	(0)
-#endif
-
-#ifdef CONFIG_MACH_E570
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_E570
-# endif
-# define machine_is_e570()	(machine_arch_type == MACH_TYPE_E570)
-#else
-# define machine_is_e570()	(0)
-#endif
-
-#ifdef CONFIG_MACH_X50
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_X50
-# endif
-# define machine_is_x50()	(machine_arch_type == MACH_TYPE_X50)
-#else
-# define machine_is_x50()	(0)
-#endif
-
-#ifdef CONFIG_MACH_RECON
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_RECON
-# endif
-# define machine_is_recon()	(machine_arch_type == MACH_TYPE_RECON)
-#else
-# define machine_is_recon()	(0)
-#endif
-
-#ifdef CONFIG_MACH_XBOARDGP8
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_XBOARDGP8
-# endif
-# define machine_is_xboardgp8()	(machine_arch_type == MACH_TYPE_XBOARDGP8)
-#else
-# define machine_is_xboardgp8()	(0)
-#endif
-
-#ifdef CONFIG_MACH_FPIC2
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_FPIC2
-# endif
-# define machine_is_fpic2()	(machine_arch_type == MACH_TYPE_FPIC2)
-#else
-# define machine_is_fpic2()	(0)
-#endif
-
-#ifdef CONFIG_MACH_AKITA
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_AKITA
-# endif
-# define machine_is_akita()	(machine_arch_type == MACH_TYPE_AKITA)
-#else
-# define machine_is_akita()	(0)
-#endif
-
-#ifdef CONFIG_MACH_A81
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_A81
-# endif
-# define machine_is_a81()	(machine_arch_type == MACH_TYPE_A81)
-#else
-# define machine_is_a81()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SVM_SC25X
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SVM_SC25X
-# endif
-# define machine_is_svm_sc25x()	(machine_arch_type == MACH_TYPE_SVM_SC25X)
-#else
-# define machine_is_svm_sc25x()	(0)
-#endif
-
-#ifdef CONFIG_MACH_VADATECH020
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_VADATECH020
-# endif
-# define machine_is_vt020()	(machine_arch_type == MACH_TYPE_VADATECH020)
-#else
-# define machine_is_vt020()	(0)
-#endif
-
-#ifdef CONFIG_MACH_TLI
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TLI
-# endif
-# define machine_is_tli()	(machine_arch_type == MACH_TYPE_TLI)
-#else
-# define machine_is_tli()	(0)
-#endif
-
-#ifdef CONFIG_MACH_EDB9315LC
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_EDB9315LC
-# endif
-# define machine_is_edb9315lc()	(machine_arch_type == MACH_TYPE_EDB9315LC)
-#else
-# define machine_is_edb9315lc()	(0)
-#endif
-
-#ifdef CONFIG_MACH_PASSEC
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PASSEC
-# endif
-# define machine_is_passec()	(machine_arch_type == MACH_TYPE_PASSEC)
-#else
-# define machine_is_passec()	(0)
-#endif
-
-#ifdef CONFIG_MACH_DS_TIGER
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_DS_TIGER
-# endif
-# define machine_is_ds_tiger()	(machine_arch_type == MACH_TYPE_DS_TIGER)
-#else
-# define machine_is_ds_tiger()	(0)
-#endif
-
-#ifdef CONFIG_MACH_E310
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_E310
-# endif
-# define machine_is_e310()	(machine_arch_type == MACH_TYPE_E310)
-#else
-# define machine_is_e310()	(0)
-#endif
-
-#ifdef CONFIG_MACH_E330
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_E330
-# endif
-# define machine_is_e330()	(machine_arch_type == MACH_TYPE_E330)
-#else
-# define machine_is_e330()	(0)
-#endif
-
-#ifdef CONFIG_MACH_RT3000
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_RT3000
-# endif
-# define machine_is_rt3000()	(machine_arch_type == MACH_TYPE_RT3000)
-#else
-# define machine_is_rt3000()	(0)
-#endif
-
-#ifdef CONFIG_MACH_NOKIA770
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_NOKIA770
-# endif
-# define machine_is_nokia770()	(machine_arch_type == MACH_TYPE_NOKIA770)
-#else
-# define machine_is_nokia770()	(0)
-#endif
-
-#ifdef CONFIG_MACH_PNX0106
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PNX0106
-# endif
-# define machine_is_pnx0106()	(machine_arch_type == MACH_TYPE_PNX0106)
-#else
-# define machine_is_pnx0106()	(0)
-#endif
-
-#ifdef CONFIG_MACH_HX21XX
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_HX21XX
-# endif
-# define machine_is_hx21xx()	(machine_arch_type == MACH_TYPE_HX21XX)
-#else
-# define machine_is_hx21xx()	(0)
-#endif
-
-#ifdef CONFIG_MACH_FARADAY
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_FARADAY
-# endif
-# define machine_is_faraday()	(machine_arch_type == MACH_TYPE_FARADAY)
-#else
-# define machine_is_faraday()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SBC9312
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SBC9312
-# endif
-# define machine_is_sbc9312()	(machine_arch_type == MACH_TYPE_SBC9312)
-#else
-# define machine_is_sbc9312()	(0)
-#endif
-
-#ifdef CONFIG_MACH_BATMAN
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_BATMAN
-# endif
-# define machine_is_batman()	(machine_arch_type == MACH_TYPE_BATMAN)
-#else
-# define machine_is_batman()	(0)
-#endif
-
-#ifdef CONFIG_MACH_JPD201
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_JPD201
-# endif
-# define machine_is_jpd201()	(machine_arch_type == MACH_TYPE_JPD201)
-#else
-# define machine_is_jpd201()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MIPSA
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MIPSA
-# endif
-# define machine_is_mipsa()	(machine_arch_type == MACH_TYPE_MIPSA)
-#else
-# define machine_is_mipsa()	(0)
-#endif
-
-#ifdef CONFIG_MACH_KACOM
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_KACOM
-# endif
-# define machine_is_kacom()	(machine_arch_type == MACH_TYPE_KACOM)
-#else
-# define machine_is_kacom()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SWARCOCPU
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SWARCOCPU
-# endif
-# define machine_is_swarcocpu()	(machine_arch_type == MACH_TYPE_SWARCOCPU)
-#else
-# define machine_is_swarcocpu()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SWARCODSL
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SWARCODSL
-# endif
-# define machine_is_swarcodsl()	(machine_arch_type == MACH_TYPE_SWARCODSL)
-#else
-# define machine_is_swarcodsl()	(0)
-#endif
-
-#ifdef CONFIG_MACH_BLUEANGEL
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_BLUEANGEL
-# endif
-# define machine_is_blueangel()	(machine_arch_type == MACH_TYPE_BLUEANGEL)
-#else
-# define machine_is_blueangel()	(0)
-#endif
-
-#ifdef CONFIG_MACH_HAIRYGRAMA
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_HAIRYGRAMA
-# endif
-# define machine_is_hairygrama()	(machine_arch_type == MACH_TYPE_HAIRYGRAMA)
-#else
-# define machine_is_hairygrama()	(0)
-#endif
-
-#ifdef CONFIG_MACH_BANFF
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_BANFF
-# endif
-# define machine_is_banff()	(machine_arch_type == MACH_TYPE_BANFF)
-#else
-# define machine_is_banff()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CARMEVA
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CARMEVA
-# endif
-# define machine_is_carmeva()	(machine_arch_type == MACH_TYPE_CARMEVA)
-#else
-# define machine_is_carmeva()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SAM255
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SAM255
-# endif
-# define machine_is_sam255()	(machine_arch_type == MACH_TYPE_SAM255)
-#else
-# define machine_is_sam255()	(0)
-#endif
-
-#ifdef CONFIG_MACH_PPM10
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PPM10
-# endif
-# define machine_is_ppm10()	(machine_arch_type == MACH_TYPE_PPM10)
-#else
-# define machine_is_ppm10()	(0)
-#endif
-
-#ifdef CONFIG_MACH_EDB9315A
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_EDB9315A
-# endif
-# define machine_is_edb9315a()	(machine_arch_type == MACH_TYPE_EDB9315A)
-#else
-# define machine_is_edb9315a()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SUNSET
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SUNSET
-# endif
-# define machine_is_sunset()	(machine_arch_type == MACH_TYPE_SUNSET)
-#else
-# define machine_is_sunset()	(0)
-#endif
-
-#ifdef CONFIG_MACH_STARGATE2
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_STARGATE2
-# endif
-# define machine_is_stargate2()	(machine_arch_type == MACH_TYPE_STARGATE2)
-#else
-# define machine_is_stargate2()	(0)
-#endif
-
-#ifdef CONFIG_MACH_INTELMOTE2
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_INTELMOTE2
-# endif
-# define machine_is_intelmote2()	(machine_arch_type == MACH_TYPE_INTELMOTE2)
-#else
-# define machine_is_intelmote2()	(0)
-#endif
-
-#ifdef CONFIG_MACH_TRIZEPS4
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TRIZEPS4
-# endif
-# define machine_is_trizeps4()	(machine_arch_type == MACH_TYPE_TRIZEPS4)
-#else
-# define machine_is_trizeps4()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MAINSTONE2
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MAINSTONE2
-# endif
-# define machine_is_mainstone2()	(machine_arch_type == MACH_TYPE_MAINSTONE2)
-#else
-# define machine_is_mainstone2()	(0)
-#endif
-
-#ifdef CONFIG_MACH_EZ_IXP42X
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_EZ_IXP42X
-# endif
-# define machine_is_ez_ixp42x()	(machine_arch_type == MACH_TYPE_EZ_IXP42X)
-#else
-# define machine_is_ez_ixp42x()	(0)
-#endif
-
-#ifdef CONFIG_MACH_TAPWAVE_ZODIAC
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TAPWAVE_ZODIAC
-# endif
-# define machine_is_tapwave_zodiac()	(machine_arch_type == MACH_TYPE_TAPWAVE_ZODIAC)
-#else
-# define machine_is_tapwave_zodiac()	(0)
-#endif
-
-#ifdef CONFIG_MACH_UNIVERSALMETER
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_UNIVERSALMETER
-# endif
-# define machine_is_universalmeter()	(machine_arch_type == MACH_TYPE_UNIVERSALMETER)
-#else
-# define machine_is_universalmeter()	(0)
-#endif
-
-#ifdef CONFIG_MACH_HICOARM9
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_HICOARM9
-# endif
-# define machine_is_hicoarm9()	(machine_arch_type == MACH_TYPE_HICOARM9)
-#else
-# define machine_is_hicoarm9()	(0)
-#endif
-
-#ifdef CONFIG_MACH_PNX4008
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PNX4008
-# endif
-# define machine_is_pnx4008()	(machine_arch_type == MACH_TYPE_PNX4008)
-#else
-# define machine_is_pnx4008()	(0)
-#endif
-
-#ifdef CONFIG_MACH_KWS6000
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_KWS6000
-# endif
-# define machine_is_kws6000()	(machine_arch_type == MACH_TYPE_KWS6000)
-#else
-# define machine_is_kws6000()	(0)
-#endif
-
-#ifdef CONFIG_MACH_PORTUX920T
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PORTUX920T
-# endif
-# define machine_is_portux920t()	(machine_arch_type == MACH_TYPE_PORTUX920T)
-#else
-# define machine_is_portux920t()	(0)
-#endif
-
-#ifdef CONFIG_MACH_EZ_X5
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_EZ_X5
-# endif
-# define machine_is_ez_x5()	(machine_arch_type == MACH_TYPE_EZ_X5)
-#else
-# define machine_is_ez_x5()	(0)
-#endif
-
-#ifdef CONFIG_MACH_OMAP_RUDOLPH
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_OMAP_RUDOLPH
-# endif
-# define machine_is_omap_rudolph()	(machine_arch_type == MACH_TYPE_OMAP_RUDOLPH)
-#else
-# define machine_is_omap_rudolph()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CPUAT91
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CPUAT91
-# endif
-# define machine_is_cpuat91()	(machine_arch_type == MACH_TYPE_CPUAT91)
-#else
-# define machine_is_cpuat91()	(0)
-#endif
-
-#ifdef CONFIG_MACH_REA9200
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_REA9200
-# endif
-# define machine_is_rea9200()	(machine_arch_type == MACH_TYPE_REA9200)
-#else
-# define machine_is_rea9200()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ACTS_PUNE_SA1110
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ACTS_PUNE_SA1110
-# endif
-# define machine_is_acts_pune_sa1110()	(machine_arch_type == MACH_TYPE_ACTS_PUNE_SA1110)
-#else
-# define machine_is_acts_pune_sa1110()	(0)
-#endif
-
-#ifdef CONFIG_MACH_IXP425
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_IXP425
-# endif
-# define machine_is_ixp425()	(machine_arch_type == MACH_TYPE_IXP425)
-#else
-# define machine_is_ixp425()	(0)
-#endif
-
-#ifdef CONFIG_MACH_I30030ADS
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_I30030ADS
-# endif
-# define machine_is_i30030ads()	(machine_arch_type == MACH_TYPE_I30030ADS)
-#else
-# define machine_is_i30030ads()	(0)
-#endif
-
-#ifdef CONFIG_MACH_PERCH
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PERCH
-# endif
-# define machine_is_perch()	(machine_arch_type == MACH_TYPE_PERCH)
-#else
-# define machine_is_perch()	(0)
-#endif
-
-#ifdef CONFIG_MACH_EIS05R1
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_EIS05R1
-# endif
-# define machine_is_eis05r1()	(machine_arch_type == MACH_TYPE_EIS05R1)
-#else
-# define machine_is_eis05r1()	(0)
-#endif
-
-#ifdef CONFIG_MACH_PEPPERPAD
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PEPPERPAD
-# endif
-# define machine_is_pepperpad()	(machine_arch_type == MACH_TYPE_PEPPERPAD)
-#else
-# define machine_is_pepperpad()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SB3010
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SB3010
-# endif
-# define machine_is_sb3010()	(machine_arch_type == MACH_TYPE_SB3010)
-#else
-# define machine_is_sb3010()	(0)
-#endif
-
-#ifdef CONFIG_MACH_RM9200
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_RM9200
-# endif
-# define machine_is_rm9200()	(machine_arch_type == MACH_TYPE_RM9200)
-#else
-# define machine_is_rm9200()	(0)
-#endif
-
-#ifdef CONFIG_MACH_DMA03
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_DMA03
-# endif
-# define machine_is_dma03()	(machine_arch_type == MACH_TYPE_DMA03)
-#else
-# define machine_is_dma03()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ROAD_S101
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ROAD_S101
-# endif
-# define machine_is_road_s101()	(machine_arch_type == MACH_TYPE_ROAD_S101)
-#else
-# define machine_is_road_s101()	(0)
-#endif
-
-#ifdef CONFIG_MACH_IQ81340SC
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_IQ81340SC
-# endif
-# define machine_is_iq81340sc()	(machine_arch_type == MACH_TYPE_IQ81340SC)
-#else
-# define machine_is_iq81340sc()	(0)
-#endif
-
-#ifdef CONFIG_MACH_IQ_NEXTGEN_B
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_IQ_NEXTGEN_B
-# endif
-# define machine_is_iq_nextgen_b()	(machine_arch_type == MACH_TYPE_IQ_NEXTGEN_B)
-#else
-# define machine_is_iq_nextgen_b()	(0)
-#endif
-
-#ifdef CONFIG_MACH_IQ81340MC
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_IQ81340MC
-# endif
-# define machine_is_iq81340mc()	(machine_arch_type == MACH_TYPE_IQ81340MC)
-#else
-# define machine_is_iq81340mc()	(0)
-#endif
-
-#ifdef CONFIG_MACH_IQ_NEXTGEN_D
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_IQ_NEXTGEN_D
-# endif
-# define machine_is_iq_nextgen_d()	(machine_arch_type == MACH_TYPE_IQ_NEXTGEN_D)
-#else
-# define machine_is_iq_nextgen_d()	(0)
-#endif
-
-#ifdef CONFIG_MACH_IQ_NEXTGEN_E
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_IQ_NEXTGEN_E
-# endif
-# define machine_is_iq_nextgen_e()	(machine_arch_type == MACH_TYPE_IQ_NEXTGEN_E)
-#else
-# define machine_is_iq_nextgen_e()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MALLOW_AT91
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MALLOW_AT91
-# endif
-# define machine_is_mallow_at91()	(machine_arch_type == MACH_TYPE_MALLOW_AT91)
-#else
-# define machine_is_mallow_at91()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CYBERTRACKER_I
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CYBERTRACKER_I
-# endif
-# define machine_is_cybertracker_i()	(machine_arch_type == MACH_TYPE_CYBERTRACKER_I)
-#else
-# define machine_is_cybertracker_i()	(0)
-#endif
-
-#ifdef CONFIG_MACH_GESBC931X
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_GESBC931X
-# endif
-# define machine_is_gesbc931x()	(machine_arch_type == MACH_TYPE_GESBC931X)
-#else
-# define machine_is_gesbc931x()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CENTIPAD
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CENTIPAD
-# endif
-# define machine_is_centipad()	(machine_arch_type == MACH_TYPE_CENTIPAD)
-#else
-# define machine_is_centipad()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ARMSOC
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ARMSOC
-# endif
-# define machine_is_armsoc()	(machine_arch_type == MACH_TYPE_ARMSOC)
-#else
-# define machine_is_armsoc()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SE4200
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SE4200
-# endif
-# define machine_is_se4200()	(machine_arch_type == MACH_TYPE_SE4200)
-#else
-# define machine_is_se4200()	(0)
-#endif
-
-#ifdef CONFIG_MACH_EMS197A
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_EMS197A
-# endif
-# define machine_is_ems197a()	(machine_arch_type == MACH_TYPE_EMS197A)
-#else
-# define machine_is_ems197a()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MICRO9
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MICRO9
-# endif
-# define machine_is_micro9()	(machine_arch_type == MACH_TYPE_MICRO9)
-#else
-# define machine_is_micro9()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MICRO9L
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MICRO9L
-# endif
-# define machine_is_micro9l()	(machine_arch_type == MACH_TYPE_MICRO9L)
-#else
-# define machine_is_micro9l()	(0)
-#endif
-
-#ifdef CONFIG_MACH_UC5471DSP
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_UC5471DSP
-# endif
-# define machine_is_uc5471dsp()	(machine_arch_type == MACH_TYPE_UC5471DSP)
-#else
-# define machine_is_uc5471dsp()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SJ5471ENG
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SJ5471ENG
-# endif
-# define machine_is_sj5471eng()	(machine_arch_type == MACH_TYPE_SJ5471ENG)
-#else
-# define machine_is_sj5471eng()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CMPXA26X
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CMPXA26X
-# endif
-# define machine_is_none()	(machine_arch_type == MACH_TYPE_CMPXA26X)
-#else
-# define machine_is_none()	(0)
-#endif
-
-#ifdef CONFIG_MACH_NC
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_NC
-# endif
-# define machine_is_nc1()	(machine_arch_type == MACH_TYPE_NC)
-#else
-# define machine_is_nc1()	(0)
-#endif
-
-#ifdef CONFIG_MACH_OMAP_PALMTE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_OMAP_PALMTE
-# endif
-# define machine_is_omap_palmte()	(machine_arch_type == MACH_TYPE_OMAP_PALMTE)
-#else
-# define machine_is_omap_palmte()	(0)
-#endif
-
-#ifdef CONFIG_MACH_AJAX52X
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_AJAX52X
-# endif
-# define machine_is_ajax52x()	(machine_arch_type == MACH_TYPE_AJAX52X)
-#else
-# define machine_is_ajax52x()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SIRIUSTAR
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SIRIUSTAR
-# endif
-# define machine_is_siriustar()	(machine_arch_type == MACH_TYPE_SIRIUSTAR)
-#else
-# define machine_is_siriustar()	(0)
-#endif
-
-#ifdef CONFIG_MACH_IODATA_HDLG
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_IODATA_HDLG
-# endif
-# define machine_is_iodata_hdlg()	(machine_arch_type == MACH_TYPE_IODATA_HDLG)
-#else
-# define machine_is_iodata_hdlg()	(0)
-#endif
-
-#ifdef CONFIG_MACH_AT91RM9200UTL
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_AT91RM9200UTL
-# endif
-# define machine_is_at91rm9200utl()	(machine_arch_type == MACH_TYPE_AT91RM9200UTL)
-#else
-# define machine_is_at91rm9200utl()	(0)
-#endif
-
-#ifdef CONFIG_MACH_BIOSAFE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_BIOSAFE
-# endif
-# define machine_is_biosafe()	(machine_arch_type == MACH_TYPE_BIOSAFE)
-#else
-# define machine_is_biosafe()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MP1000
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MP1000
-# endif
-# define machine_is_mp1000()	(machine_arch_type == MACH_TYPE_MP1000)
-#else
-# define machine_is_mp1000()	(0)
-#endif
-
-#ifdef CONFIG_MACH_PARSY
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PARSY
-# endif
-# define machine_is_parsy()	(machine_arch_type == MACH_TYPE_PARSY)
-#else
-# define machine_is_parsy()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CCXP
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CCXP
-# endif
-# define machine_is_ccxp270()	(machine_arch_type == MACH_TYPE_CCXP)
-#else
-# define machine_is_ccxp270()	(0)
-#endif
-
-#ifdef CONFIG_MACH_OMAP_GSAMPLE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_OMAP_GSAMPLE
-# endif
-# define machine_is_omap_gsample()	(machine_arch_type == MACH_TYPE_OMAP_GSAMPLE)
-#else
-# define machine_is_omap_gsample()	(0)
-#endif
-
-#ifdef CONFIG_MACH_REALVIEW_EB
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_REALVIEW_EB
-# endif
-# define machine_is_realview_eb()	(machine_arch_type == MACH_TYPE_REALVIEW_EB)
-#else
-# define machine_is_realview_eb()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SAMOA
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SAMOA
-# endif
-# define machine_is_samoa()	(machine_arch_type == MACH_TYPE_SAMOA)
-#else
-# define machine_is_samoa()	(0)
-#endif
-
-#ifdef CONFIG_MACH_PALMT3
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PALMT3
-# endif
-# define machine_is_palmt3()	(machine_arch_type == MACH_TYPE_PALMT3)
-#else
-# define machine_is_palmt3()	(0)
-#endif
-
-#ifdef CONFIG_MACH_I878
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_I878
-# endif
-# define machine_is_i878()	(machine_arch_type == MACH_TYPE_I878)
-#else
-# define machine_is_i878()	(0)
-#endif
-
-#ifdef CONFIG_MACH_BORZOI
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_BORZOI
-# endif
-# define machine_is_borzoi()	(machine_arch_type == MACH_TYPE_BORZOI)
-#else
-# define machine_is_borzoi()	(0)
-#endif
-
-#ifdef CONFIG_MACH_GECKO
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_GECKO
-# endif
-# define machine_is_gecko()	(machine_arch_type == MACH_TYPE_GECKO)
-#else
-# define machine_is_gecko()	(0)
-#endif
-
-#ifdef CONFIG_MACH_DS101
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_DS101
-# endif
-# define machine_is_ds101()	(machine_arch_type == MACH_TYPE_DS101)
-#else
-# define machine_is_ds101()	(0)
-#endif
-
-#ifdef CONFIG_MACH_OMAP_PALMTT2
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_OMAP_PALMTT2
-# endif
-# define machine_is_omap_palmtt2()	(machine_arch_type == MACH_TYPE_OMAP_PALMTT2)
-#else
-# define machine_is_omap_palmtt2()	(0)
-#endif
-
-#ifdef CONFIG_MACH_PALMLD
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PALMLD
-# endif
-# define machine_is_palmld()	(machine_arch_type == MACH_TYPE_PALMLD)
-#else
-# define machine_is_palmld()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CC9C
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CC9C
-# endif
-# define machine_is_cc9c()	(machine_arch_type == MACH_TYPE_CC9C)
-#else
-# define machine_is_cc9c()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SBC1670
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SBC1670
-# endif
-# define machine_is_sbc1670()	(machine_arch_type == MACH_TYPE_SBC1670)
-#else
-# define machine_is_sbc1670()	(0)
-#endif
-
-#ifdef CONFIG_MACH_IXDP28X5
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_IXDP28X5
-# endif
-# define machine_is_ixdp28x5()	(machine_arch_type == MACH_TYPE_IXDP28X5)
-#else
-# define machine_is_ixdp28x5()	(0)
-#endif
-
-#ifdef CONFIG_MACH_OMAP_PALMTT
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_OMAP_PALMTT
-# endif
-# define machine_is_omap_palmtt()	(machine_arch_type == MACH_TYPE_OMAP_PALMTT)
-#else
-# define machine_is_omap_palmtt()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ML696K
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ML696K
-# endif
-# define machine_is_ml696k()	(machine_arch_type == MACH_TYPE_ML696K)
-#else
-# define machine_is_ml696k()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ARCOM_ZEUS
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ARCOM_ZEUS
-# endif
-# define machine_is_arcom_zeus()	(machine_arch_type == MACH_TYPE_ARCOM_ZEUS)
-#else
-# define machine_is_arcom_zeus()	(0)
-#endif
-
-#ifdef CONFIG_MACH_OSIRIS
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_OSIRIS
-# endif
-# define machine_is_osiris()	(machine_arch_type == MACH_TYPE_OSIRIS)
-#else
-# define machine_is_osiris()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MAESTRO
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MAESTRO
-# endif
-# define machine_is_maestro()	(machine_arch_type == MACH_TYPE_MAESTRO)
-#else
-# define machine_is_maestro()	(0)
-#endif
-
-#ifdef CONFIG_MACH_PALMTE2
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PALMTE2
-# endif
-# define machine_is_palmte2()	(machine_arch_type == MACH_TYPE_PALMTE2)
-#else
-# define machine_is_palmte2()	(0)
-#endif
-
-#ifdef CONFIG_MACH_IXBBM
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_IXBBM
-# endif
-# define machine_is_ixbbm()	(machine_arch_type == MACH_TYPE_IXBBM)
-#else
-# define machine_is_ixbbm()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MX27ADS
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MX27ADS
-# endif
-# define machine_is_mx27ads()	(machine_arch_type == MACH_TYPE_MX27ADS)
-#else
-# define machine_is_mx27ads()	(0)
-#endif
-
-#ifdef CONFIG_MACH_AX8004
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_AX8004
-# endif
-# define machine_is_ax8004()	(machine_arch_type == MACH_TYPE_AX8004)
-#else
-# define machine_is_ax8004()	(0)
-#endif
-
-#ifdef CONFIG_MACH_AT91SAM9261EK
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_AT91SAM9261EK
-# endif
-# define machine_is_at91sam9261ek()	(machine_arch_type == MACH_TYPE_AT91SAM9261EK)
-#else
-# define machine_is_at91sam9261ek()	(0)
-#endif
-
-#ifdef CONFIG_MACH_LOFT
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_LOFT
-# endif
-# define machine_is_loft()	(machine_arch_type == MACH_TYPE_LOFT)
-#else
-# define machine_is_loft()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MAGPIE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MAGPIE
-# endif
-# define machine_is_magpie()	(machine_arch_type == MACH_TYPE_MAGPIE)
-#else
-# define machine_is_magpie()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MX21ADS
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MX21ADS
-# endif
-# define machine_is_mx21ads()	(machine_arch_type == MACH_TYPE_MX21ADS)
-#else
-# define machine_is_mx21ads()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MB87M3400
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MB87M3400
-# endif
-# define machine_is_mb87m3400()	(machine_arch_type == MACH_TYPE_MB87M3400)
-#else
-# define machine_is_mb87m3400()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MGUARD_DELTA
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MGUARD_DELTA
-# endif
-# define machine_is_mguard_delta()	(machine_arch_type == MACH_TYPE_MGUARD_DELTA)
-#else
-# define machine_is_mguard_delta()	(0)
-#endif
-
-#ifdef CONFIG_MACH_DAVINCI_DVDP
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_DAVINCI_DVDP
-# endif
-# define machine_is_davinci_dvdp()	(machine_arch_type == MACH_TYPE_DAVINCI_DVDP)
-#else
-# define machine_is_davinci_dvdp()	(0)
-#endif
-
-#ifdef CONFIG_MACH_HTCUNIVERSAL
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_HTCUNIVERSAL
-# endif
-# define machine_is_htcuniversal()	(machine_arch_type == MACH_TYPE_HTCUNIVERSAL)
-#else
-# define machine_is_htcuniversal()	(0)
-#endif
-
-#ifdef CONFIG_MACH_TPAD
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TPAD
-# endif
-# define machine_is_tpad()	(machine_arch_type == MACH_TYPE_TPAD)
-#else
-# define machine_is_tpad()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ROVERP3
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ROVERP3
-# endif
-# define machine_is_roverp3()	(machine_arch_type == MACH_TYPE_ROVERP3)
-#else
-# define machine_is_roverp3()	(0)
-#endif
-
-#ifdef CONFIG_MACH_JORNADA928
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_JORNADA928
-# endif
-# define machine_is_jornada928()	(machine_arch_type == MACH_TYPE_JORNADA928)
-#else
-# define machine_is_jornada928()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MV88FXX81
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MV88FXX81
-# endif
-# define machine_is_mv88fxx81()	(machine_arch_type == MACH_TYPE_MV88FXX81)
-#else
-# define machine_is_mv88fxx81()	(0)
-#endif
-
-#ifdef CONFIG_MACH_STMP36XX
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_STMP36XX
-# endif
-# define machine_is_stmp36xx()	(machine_arch_type == MACH_TYPE_STMP36XX)
-#else
-# define machine_is_stmp36xx()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SXNI79524
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SXNI79524
-# endif
-# define machine_is_sxni79524()	(machine_arch_type == MACH_TYPE_SXNI79524)
-#else
-# define machine_is_sxni79524()	(0)
-#endif
-
-#ifdef CONFIG_MACH_AMS_DELTA
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_AMS_DELTA
-# endif
-# define machine_is_ams_delta()	(machine_arch_type == MACH_TYPE_AMS_DELTA)
-#else
-# define machine_is_ams_delta()	(0)
-#endif
-
-#ifdef CONFIG_MACH_URANIUM
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_URANIUM
-# endif
-# define machine_is_uranium()	(machine_arch_type == MACH_TYPE_URANIUM)
-#else
-# define machine_is_uranium()	(0)
-#endif
-
-#ifdef CONFIG_MACH_UCON
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_UCON
-# endif
-# define machine_is_ucon()	(machine_arch_type == MACH_TYPE_UCON)
-#else
-# define machine_is_ucon()	(0)
-#endif
-
-#ifdef CONFIG_MACH_NAS100D
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_NAS100D
-# endif
-# define machine_is_nas100d()	(machine_arch_type == MACH_TYPE_NAS100D)
-#else
-# define machine_is_nas100d()	(0)
-#endif
-
-#ifdef CONFIG_MACH_L083_1000
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_L083_1000
-# endif
-# define machine_is_l083()	(machine_arch_type == MACH_TYPE_L083_1000)
-#else
-# define machine_is_l083()	(0)
-#endif
-
-#ifdef CONFIG_MACH_EZX
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_EZX
-# endif
-# define machine_is_ezx()	(machine_arch_type == MACH_TYPE_EZX)
-#else
-# define machine_is_ezx()	(0)
-#endif
-
-#ifdef CONFIG_MACH_PNX5220
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PNX5220
-# endif
-# define machine_is_pnx5220()	(machine_arch_type == MACH_TYPE_PNX5220)
-#else
-# define machine_is_pnx5220()	(0)
-#endif
-
-#ifdef CONFIG_MACH_BUTTE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_BUTTE
-# endif
-# define machine_is_butte()	(machine_arch_type == MACH_TYPE_BUTTE)
-#else
-# define machine_is_butte()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SRM2
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SRM2
-# endif
-# define machine_is_srm2()	(machine_arch_type == MACH_TYPE_SRM2)
-#else
-# define machine_is_srm2()	(0)
-#endif
-
-#ifdef CONFIG_MACH_DSBR
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_DSBR
-# endif
-# define machine_is_dsbr()	(machine_arch_type == MACH_TYPE_DSBR)
-#else
-# define machine_is_dsbr()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CRYSTALBALL
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CRYSTALBALL
-# endif
-# define machine_is_crystalball()	(machine_arch_type == MACH_TYPE_CRYSTALBALL)
-#else
-# define machine_is_crystalball()	(0)
-#endif
-
-#ifdef CONFIG_MACH_TINYPXA27X
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TINYPXA27X
-# endif
-# define machine_is_tinypxa27x()	(machine_arch_type == MACH_TYPE_TINYPXA27X)
-#else
-# define machine_is_tinypxa27x()	(0)
-#endif
-
-#ifdef CONFIG_MACH_HERBIE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_HERBIE
-# endif
-# define machine_is_herbie()	(machine_arch_type == MACH_TYPE_HERBIE)
-#else
-# define machine_is_herbie()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MAGICIAN
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MAGICIAN
-# endif
-# define machine_is_magician()	(machine_arch_type == MACH_TYPE_MAGICIAN)
-#else
-# define machine_is_magician()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CM4002
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CM4002
-# endif
-# define machine_is_cm4002()	(machine_arch_type == MACH_TYPE_CM4002)
-#else
-# define machine_is_cm4002()	(0)
-#endif
-
-#ifdef CONFIG_MACH_B4
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_B4
-# endif
-# define machine_is_b4()	(machine_arch_type == MACH_TYPE_B4)
-#else
-# define machine_is_b4()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MAUI
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MAUI
-# endif
-# define machine_is_maui()	(machine_arch_type == MACH_TYPE_MAUI)
-#else
-# define machine_is_maui()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CYBERTRACKER_G
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CYBERTRACKER_G
-# endif
-# define machine_is_cybertracker_g()	(machine_arch_type == MACH_TYPE_CYBERTRACKER_G)
-#else
-# define machine_is_cybertracker_g()	(0)
-#endif
-
-#ifdef CONFIG_MACH_NXDKN
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_NXDKN
-# endif
-# define machine_is_nxdkn()	(machine_arch_type == MACH_TYPE_NXDKN)
-#else
-# define machine_is_nxdkn()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MIO8390
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MIO8390
-# endif
-# define machine_is_mio8390()	(machine_arch_type == MACH_TYPE_MIO8390)
-#else
-# define machine_is_mio8390()	(0)
-#endif
-
-#ifdef CONFIG_MACH_OMI_BOARD
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_OMI_BOARD
-# endif
-# define machine_is_omi_board()	(machine_arch_type == MACH_TYPE_OMI_BOARD)
-#else
-# define machine_is_omi_board()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MX21CIV
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MX21CIV
-# endif
-# define machine_is_mx21civ()	(machine_arch_type == MACH_TYPE_MX21CIV)
-#else
-# define machine_is_mx21civ()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MAHI_CDAC
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MAHI_CDAC
-# endif
-# define machine_is_mahi_cdac()	(machine_arch_type == MACH_TYPE_MAHI_CDAC)
-#else
-# define machine_is_mahi_cdac()	(0)
-#endif
-
-#ifdef CONFIG_MACH_PALMTX
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PALMTX
-# endif
-# define machine_is_palmtx()	(machine_arch_type == MACH_TYPE_PALMTX)
-#else
-# define machine_is_palmtx()	(0)
-#endif
-
-#ifdef CONFIG_MACH_S3C2413
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_S3C2413
-# endif
-# define machine_is_s3c2413()	(machine_arch_type == MACH_TYPE_S3C2413)
-#else
-# define machine_is_s3c2413()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SAMSYS_EP0
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SAMSYS_EP0
-# endif
-# define machine_is_samsys_ep0()	(machine_arch_type == MACH_TYPE_SAMSYS_EP0)
-#else
-# define machine_is_samsys_ep0()	(0)
-#endif
-
-#ifdef CONFIG_MACH_WG302V1
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_WG302V1
-# endif
-# define machine_is_wg302v1()	(machine_arch_type == MACH_TYPE_WG302V1)
-#else
-# define machine_is_wg302v1()	(0)
-#endif
-
-#ifdef CONFIG_MACH_WG302V2
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_WG302V2
-# endif
-# define machine_is_wg302v2()	(machine_arch_type == MACH_TYPE_WG302V2)
-#else
-# define machine_is_wg302v2()	(0)
-#endif
-
-#ifdef CONFIG_MACH_EB42X
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_EB42X
-# endif
-# define machine_is_eb42x()	(machine_arch_type == MACH_TYPE_EB42X)
-#else
-# define machine_is_eb42x()	(0)
-#endif
-
-#ifdef CONFIG_MACH_IQ331ES
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_IQ331ES
-# endif
-# define machine_is_iq331es()	(machine_arch_type == MACH_TYPE_IQ331ES)
-#else
-# define machine_is_iq331es()	(0)
-#endif
-
-#ifdef CONFIG_MACH_COSYDSP
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_COSYDSP
-# endif
-# define machine_is_cosydsp()	(machine_arch_type == MACH_TYPE_COSYDSP)
-#else
-# define machine_is_cosydsp()	(0)
-#endif
-
-#ifdef CONFIG_MACH_UPLAT7D
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_UPLAT7D
-# endif
-# define machine_is_uplat7d_proto()	(machine_arch_type == MACH_TYPE_UPLAT7D)
-#else
-# define machine_is_uplat7d_proto()	(0)
-#endif
-
-#ifdef CONFIG_MACH_PTDAVINCI
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PTDAVINCI
-# endif
-# define machine_is_ptdavinci()	(machine_arch_type == MACH_TYPE_PTDAVINCI)
-#else
-# define machine_is_ptdavinci()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MBUS
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MBUS
-# endif
-# define machine_is_mbus()	(machine_arch_type == MACH_TYPE_MBUS)
-#else
-# define machine_is_mbus()	(0)
-#endif
-
-#ifdef CONFIG_MACH_NADIA2VB
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_NADIA2VB
-# endif
-# define machine_is_nadia2vb()	(machine_arch_type == MACH_TYPE_NADIA2VB)
-#else
-# define machine_is_nadia2vb()	(0)
-#endif
-
-#ifdef CONFIG_MACH_R1000
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_R1000
-# endif
-# define machine_is_r1000()	(machine_arch_type == MACH_TYPE_R1000)
-#else
-# define machine_is_r1000()	(0)
-#endif
-
-#ifdef CONFIG_MACH_HW90250
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_HW90250
-# endif
-# define machine_is_hw90250()	(machine_arch_type == MACH_TYPE_HW90250)
-#else
-# define machine_is_hw90250()	(0)
-#endif
-
-#ifdef CONFIG_MACH_OMAP_2430SDP
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_OMAP_2430SDP
-# endif
-# define machine_is_omap_2430sdp()	(machine_arch_type == MACH_TYPE_OMAP_2430SDP)
-#else
-# define machine_is_omap_2430sdp()	(0)
-#endif
-
-#ifdef CONFIG_MACH_DAVINCI_EVM
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_DAVINCI_EVM
-# endif
-# define machine_is_davinci_evm()	(machine_arch_type == MACH_TYPE_DAVINCI_EVM)
-#else
-# define machine_is_davinci_evm()	(0)
-#endif
-
-#ifdef CONFIG_MACH_OMAP_TORNADO
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_OMAP_TORNADO
-# endif
-# define machine_is_omap_tornado()	(machine_arch_type == MACH_TYPE_OMAP_TORNADO)
-#else
-# define machine_is_omap_tornado()	(0)
-#endif
-
-#ifdef CONFIG_MACH_OLOCREEK
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_OLOCREEK
-# endif
-# define machine_is_olocreek()	(machine_arch_type == MACH_TYPE_OLOCREEK)
-#else
-# define machine_is_olocreek()	(0)
-#endif
-
-#ifdef CONFIG_MACH_PALMZ72
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PALMZ72
-# endif
-# define machine_is_palmz72()	(machine_arch_type == MACH_TYPE_PALMZ72)
-#else
-# define machine_is_palmz72()	(0)
-#endif
-
-#ifdef CONFIG_MACH_NXDB500
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_NXDB500
-# endif
-# define machine_is_nxdb500()	(machine_arch_type == MACH_TYPE_NXDB500)
-#else
-# define machine_is_nxdb500()	(0)
-#endif
-
-#ifdef CONFIG_MACH_APF9328
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_APF9328
-# endif
-# define machine_is_apf9328()	(machine_arch_type == MACH_TYPE_APF9328)
-#else
-# define machine_is_apf9328()	(0)
-#endif
-
-#ifdef CONFIG_MACH_OMAP_WIPOQ
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_OMAP_WIPOQ
-# endif
-# define machine_is_omap_wipoq()	(machine_arch_type == MACH_TYPE_OMAP_WIPOQ)
-#else
-# define machine_is_omap_wipoq()	(0)
-#endif
-
-#ifdef CONFIG_MACH_OMAP_TWIP
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_OMAP_TWIP
-# endif
-# define machine_is_omap_twip()	(machine_arch_type == MACH_TYPE_OMAP_TWIP)
-#else
-# define machine_is_omap_twip()	(0)
-#endif
-
-#ifdef CONFIG_MACH_TREO650
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TREO650
-# endif
-# define machine_is_treo650()	(machine_arch_type == MACH_TYPE_TREO650)
-#else
-# define machine_is_treo650()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ACUMEN
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ACUMEN
-# endif
-# define machine_is_acumen()	(machine_arch_type == MACH_TYPE_ACUMEN)
-#else
-# define machine_is_acumen()	(0)
-#endif
-
-#ifdef CONFIG_MACH_XP100
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_XP100
-# endif
-# define machine_is_xp100()	(machine_arch_type == MACH_TYPE_XP100)
-#else
-# define machine_is_xp100()	(0)
-#endif
-
-#ifdef CONFIG_MACH_FS2410
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_FS2410
-# endif
-# define machine_is_fs2410()	(machine_arch_type == MACH_TYPE_FS2410)
-#else
-# define machine_is_fs2410()	(0)
-#endif
-
-#ifdef CONFIG_MACH_PXA270_CERF
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PXA270_CERF
-# endif
-# define machine_is_pxa270_cerf()	(machine_arch_type == MACH_TYPE_PXA270_CERF)
-#else
-# define machine_is_pxa270_cerf()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SQ2FTLPALM
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SQ2FTLPALM
-# endif
-# define machine_is_sq2ftlpalm()	(machine_arch_type == MACH_TYPE_SQ2FTLPALM)
-#else
-# define machine_is_sq2ftlpalm()	(0)
-#endif
-
-#ifdef CONFIG_MACH_BSEMSERVER
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_BSEMSERVER
-# endif
-# define machine_is_bsemserver()	(machine_arch_type == MACH_TYPE_BSEMSERVER)
-#else
-# define machine_is_bsemserver()	(0)
-#endif
-
-#ifdef CONFIG_MACH_NETCLIENT
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_NETCLIENT
-# endif
-# define machine_is_netclient()	(machine_arch_type == MACH_TYPE_NETCLIENT)
-#else
-# define machine_is_netclient()	(0)
-#endif
-
-#ifdef CONFIG_MACH_PALMT5
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PALMT5
-# endif
-# define machine_is_palmt5()	(machine_arch_type == MACH_TYPE_PALMT5)
-#else
-# define machine_is_palmt5()	(0)
-#endif
-
-#ifdef CONFIG_MACH_PALMTC
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PALMTC
-# endif
-# define machine_is_palmtc()	(machine_arch_type == MACH_TYPE_PALMTC)
-#else
-# define machine_is_palmtc()	(0)
-#endif
-
-#ifdef CONFIG_MACH_OMAP_APOLLON
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_OMAP_APOLLON
-# endif
-# define machine_is_omap_apollon()	(machine_arch_type == MACH_TYPE_OMAP_APOLLON)
-#else
-# define machine_is_omap_apollon()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MXC30030EVB
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MXC30030EVB
-# endif
-# define machine_is_mxc30030evb()	(machine_arch_type == MACH_TYPE_MXC30030EVB)
-#else
-# define machine_is_mxc30030evb()	(0)
-#endif
-
-#ifdef CONFIG_MACH_REA_2D
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_REA_2D
-# endif
-# define machine_is_rea_cpu2()	(machine_arch_type == MACH_TYPE_REA_2D)
-#else
-# define machine_is_rea_cpu2()	(0)
-#endif
-
-#ifdef CONFIG_MACH_TI3E524
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TI3E524
-# endif
-# define machine_is_eti3e524()	(machine_arch_type == MACH_TYPE_TI3E524)
-#else
-# define machine_is_eti3e524()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ATEB9200
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ATEB9200
-# endif
-# define machine_is_ateb9200()	(machine_arch_type == MACH_TYPE_ATEB9200)
-#else
-# define machine_is_ateb9200()	(0)
-#endif
-
-#ifdef CONFIG_MACH_AUCKLAND
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_AUCKLAND
-# endif
-# define machine_is_auckland()	(machine_arch_type == MACH_TYPE_AUCKLAND)
-#else
-# define machine_is_auckland()	(0)
-#endif
-
-#ifdef CONFIG_MACH_AK3320M
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_AK3320M
-# endif
-# define machine_is_ak3220m()	(machine_arch_type == MACH_TYPE_AK3320M)
-#else
-# define machine_is_ak3220m()	(0)
-#endif
-
-#ifdef CONFIG_MACH_DURAMAX
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_DURAMAX
-# endif
-# define machine_is_duramax()	(machine_arch_type == MACH_TYPE_DURAMAX)
-#else
-# define machine_is_duramax()	(0)
-#endif
-
-#ifdef CONFIG_MACH_N35
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_N35
-# endif
-# define machine_is_n35()	(machine_arch_type == MACH_TYPE_N35)
-#else
-# define machine_is_n35()	(0)
-#endif
-
-#ifdef CONFIG_MACH_PRONGHORN
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PRONGHORN
-# endif
-# define machine_is_pronghorn()	(machine_arch_type == MACH_TYPE_PRONGHORN)
-#else
-# define machine_is_pronghorn()	(0)
-#endif
-
-#ifdef CONFIG_MACH_FUNDY
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_FUNDY
-# endif
-# define machine_is_fundy()	(machine_arch_type == MACH_TYPE_FUNDY)
-#else
-# define machine_is_fundy()	(0)
-#endif
-
-#ifdef CONFIG_MACH_LOGICPD_PXA270
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_LOGICPD_PXA270
-# endif
-# define machine_is_logicpd_pxa270()	(machine_arch_type == MACH_TYPE_LOGICPD_PXA270)
-#else
-# define machine_is_logicpd_pxa270()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CPU777
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CPU777
-# endif
-# define machine_is_cpu777()	(machine_arch_type == MACH_TYPE_CPU777)
-#else
-# define machine_is_cpu777()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SIMICON9201
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SIMICON9201
-# endif
-# define machine_is_simicon9201()	(machine_arch_type == MACH_TYPE_SIMICON9201)
-#else
-# define machine_is_simicon9201()	(0)
-#endif
-
-#ifdef CONFIG_MACH_LEAP2_HPM
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_LEAP2_HPM
-# endif
-# define machine_is_leap2_hpm()	(machine_arch_type == MACH_TYPE_LEAP2_HPM)
-#else
-# define machine_is_leap2_hpm()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CM922TXA10
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CM922TXA10
-# endif
-# define machine_is_cm922txa10()	(machine_arch_type == MACH_TYPE_CM922TXA10)
-#else
-# define machine_is_cm922txa10()	(0)
-#endif
-
-#ifdef CONFIG_MACH_PXA
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PXA
-# endif
-# define machine_is_sandgate()	(machine_arch_type == MACH_TYPE_PXA)
-#else
-# define machine_is_sandgate()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SANDGATE2
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SANDGATE2
-# endif
-# define machine_is_sandgate2()	(machine_arch_type == MACH_TYPE_SANDGATE2)
-#else
-# define machine_is_sandgate2()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SANDGATE2G
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SANDGATE2G
-# endif
-# define machine_is_sandgate2g()	(machine_arch_type == MACH_TYPE_SANDGATE2G)
-#else
-# define machine_is_sandgate2g()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SANDGATE2P
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SANDGATE2P
-# endif
-# define machine_is_sandgate2p()	(machine_arch_type == MACH_TYPE_SANDGATE2P)
-#else
-# define machine_is_sandgate2p()	(0)
-#endif
-
-#ifdef CONFIG_MACH_FRED_JACK
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_FRED_JACK
-# endif
-# define machine_is_fred_jack()	(machine_arch_type == MACH_TYPE_FRED_JACK)
-#else
-# define machine_is_fred_jack()	(0)
-#endif
-
-#ifdef CONFIG_MACH_TTG_COLOR1
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TTG_COLOR1
-# endif
-# define machine_is_ttg_color1()	(machine_arch_type == MACH_TYPE_TTG_COLOR1)
-#else
-# define machine_is_ttg_color1()	(0)
-#endif
-
-#ifdef CONFIG_MACH_NXEB500HMI
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_NXEB500HMI
-# endif
-# define machine_is_nxeb500hmi()	(machine_arch_type == MACH_TYPE_NXEB500HMI)
-#else
-# define machine_is_nxeb500hmi()	(0)
-#endif
-
-#ifdef CONFIG_MACH_NETDCU8
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_NETDCU8
-# endif
-# define machine_is_netdcu8()	(machine_arch_type == MACH_TYPE_NETDCU8)
-#else
-# define machine_is_netdcu8()	(0)
-#endif
-
-#ifdef CONFIG_MACH_NG_FVX538
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_NG_FVX538
-# endif
-# define machine_is_ng_fvx538()	(machine_arch_type == MACH_TYPE_NG_FVX538)
-#else
-# define machine_is_ng_fvx538()	(0)
-#endif
-
-#ifdef CONFIG_MACH_NG_FVS338
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_NG_FVS338
-# endif
-# define machine_is_ng_fvs338()	(machine_arch_type == MACH_TYPE_NG_FVS338)
-#else
-# define machine_is_ng_fvs338()	(0)
-#endif
-
-#ifdef CONFIG_MACH_PNX4103
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PNX4103
-# endif
-# define machine_is_pnx4103()	(machine_arch_type == MACH_TYPE_PNX4103)
-#else
-# define machine_is_pnx4103()	(0)
-#endif
-
-#ifdef CONFIG_MACH_HESDB
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_HESDB
-# endif
-# define machine_is_hesdb()	(machine_arch_type == MACH_TYPE_HESDB)
-#else
-# define machine_is_hesdb()	(0)
-#endif
-
-#ifdef CONFIG_MACH_XSILO
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_XSILO
-# endif
-# define machine_is_xsilo()	(machine_arch_type == MACH_TYPE_XSILO)
-#else
-# define machine_is_xsilo()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ESPRESSO
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ESPRESSO
-# endif
-# define machine_is_espresso()	(machine_arch_type == MACH_TYPE_ESPRESSO)
-#else
-# define machine_is_espresso()	(0)
-#endif
-
-#ifdef CONFIG_MACH_EMLC
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_EMLC
-# endif
-# define machine_is_emlc()	(machine_arch_type == MACH_TYPE_EMLC)
-#else
-# define machine_is_emlc()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SISTERON
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SISTERON
-# endif
-# define machine_is_sisteron()	(machine_arch_type == MACH_TYPE_SISTERON)
-#else
-# define machine_is_sisteron()	(0)
-#endif
-
-#ifdef CONFIG_MACH_RX1950
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_RX1950
-# endif
-# define machine_is_rx1950()	(machine_arch_type == MACH_TYPE_RX1950)
-#else
-# define machine_is_rx1950()	(0)
-#endif
-
-#ifdef CONFIG_MACH_TSC_VENUS
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TSC_VENUS
-# endif
-# define machine_is_tsc_venus()	(machine_arch_type == MACH_TYPE_TSC_VENUS)
-#else
-# define machine_is_tsc_venus()	(0)
-#endif
-
-#ifdef CONFIG_MACH_DS101J
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_DS101J
-# endif
-# define machine_is_ds101j()	(machine_arch_type == MACH_TYPE_DS101J)
-#else
-# define machine_is_ds101j()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MXC30030ADS
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MXC30030ADS
-# endif
-# define machine_is_mxc30030ads()	(machine_arch_type == MACH_TYPE_MXC30030ADS)
-#else
-# define machine_is_mxc30030ads()	(0)
-#endif
-
-#ifdef CONFIG_MACH_FUJITSU_WIMAXSOC
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_FUJITSU_WIMAXSOC
-# endif
-# define machine_is_fujitsu_wimaxsoc()	(machine_arch_type == MACH_TYPE_FUJITSU_WIMAXSOC)
-#else
-# define machine_is_fujitsu_wimaxsoc()	(0)
-#endif
-
-#ifdef CONFIG_MACH_DUALPCMODEM
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_DUALPCMODEM
-# endif
-# define machine_is_dualpcmodem()	(machine_arch_type == MACH_TYPE_DUALPCMODEM)
-#else
-# define machine_is_dualpcmodem()	(0)
-#endif
-
-#ifdef CONFIG_MACH_GESBC9312
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_GESBC9312
-# endif
-# define machine_is_gesbc9312()	(machine_arch_type == MACH_TYPE_GESBC9312)
-#else
-# define machine_is_gesbc9312()	(0)
-#endif
-
-#ifdef CONFIG_MACH_HTCAPACHE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_HTCAPACHE
-# endif
-# define machine_is_htcapache()	(machine_arch_type == MACH_TYPE_HTCAPACHE)
-#else
-# define machine_is_htcapache()	(0)
-#endif
-
-#ifdef CONFIG_MACH_IXDP435
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_IXDP435
-# endif
-# define machine_is_ixdp435()	(machine_arch_type == MACH_TYPE_IXDP435)
-#else
-# define machine_is_ixdp435()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CATPROVT100
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CATPROVT100
-# endif
-# define machine_is_catprovt100()	(machine_arch_type == MACH_TYPE_CATPROVT100)
-#else
-# define machine_is_catprovt100()	(0)
-#endif
-
-#ifdef CONFIG_MACH_PICOTUX1XX
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PICOTUX1XX
-# endif
-# define machine_is_picotux1xx()	(machine_arch_type == MACH_TYPE_PICOTUX1XX)
-#else
-# define machine_is_picotux1xx()	(0)
-#endif
-
-#ifdef CONFIG_MACH_PICOTUX2XX
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PICOTUX2XX
-# endif
-# define machine_is_picotux2xx()	(machine_arch_type == MACH_TYPE_PICOTUX2XX)
-#else
-# define machine_is_picotux2xx()	(0)
-#endif
-
-#ifdef CONFIG_MACH_DSMG600
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_DSMG600
-# endif
-# define machine_is_dsmg600()	(machine_arch_type == MACH_TYPE_DSMG600)
-#else
-# define machine_is_dsmg600()	(0)
-#endif
-
-#ifdef CONFIG_MACH_EMPC2
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_EMPC2
-# endif
-# define machine_is_empc2()	(machine_arch_type == MACH_TYPE_EMPC2)
-#else
-# define machine_is_empc2()	(0)
-#endif
-
-#ifdef CONFIG_MACH_VENTURA
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_VENTURA
-# endif
-# define machine_is_ventura()	(machine_arch_type == MACH_TYPE_VENTURA)
-#else
-# define machine_is_ventura()	(0)
-#endif
-
-#ifdef CONFIG_MACH_PHIDGET_SBC
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PHIDGET_SBC
-# endif
-# define machine_is_phidget_sbc()	(machine_arch_type == MACH_TYPE_PHIDGET_SBC)
-#else
-# define machine_is_phidget_sbc()	(0)
-#endif
-
-#ifdef CONFIG_MACH_IJ3K
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_IJ3K
-# endif
-# define machine_is_ij3k()	(machine_arch_type == MACH_TYPE_IJ3K)
-#else
-# define machine_is_ij3k()	(0)
-#endif
-
-#ifdef CONFIG_MACH_PISGAH
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PISGAH
-# endif
-# define machine_is_pisgah()	(machine_arch_type == MACH_TYPE_PISGAH)
-#else
-# define machine_is_pisgah()	(0)
-#endif
-
-#ifdef CONFIG_MACH_OMAP_FSAMPLE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_OMAP_FSAMPLE
-# endif
-# define machine_is_omap_fsample()	(machine_arch_type == MACH_TYPE_OMAP_FSAMPLE)
-#else
-# define machine_is_omap_fsample()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SG720
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SG720
-# endif
-# define machine_is_sg720()	(machine_arch_type == MACH_TYPE_SG720)
-#else
-# define machine_is_sg720()	(0)
-#endif
-
-#ifdef CONFIG_MACH_REDFOX
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_REDFOX
-# endif
-# define machine_is_redfox()	(machine_arch_type == MACH_TYPE_REDFOX)
-#else
-# define machine_is_redfox()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MYSH_EP9315_1
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MYSH_EP9315_1
-# endif
-# define machine_is_mysh_ep9315_1()	(machine_arch_type == MACH_TYPE_MYSH_EP9315_1)
-#else
-# define machine_is_mysh_ep9315_1()	(0)
-#endif
-
-#ifdef CONFIG_MACH_TPF106
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TPF106
-# endif
-# define machine_is_tpf106()	(machine_arch_type == MACH_TYPE_TPF106)
-#else
-# define machine_is_tpf106()	(0)
-#endif
-
-#ifdef CONFIG_MACH_AT91RM9200KG
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_AT91RM9200KG
-# endif
-# define machine_is_at91rm9200kg()	(machine_arch_type == MACH_TYPE_AT91RM9200KG)
-#else
-# define machine_is_at91rm9200kg()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SLEDB
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SLEDB
-# endif
-# define machine_is_rcmt2()	(machine_arch_type == MACH_TYPE_SLEDB)
-#else
-# define machine_is_rcmt2()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ONTRACK
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ONTRACK
-# endif
-# define machine_is_ontrack()	(machine_arch_type == MACH_TYPE_ONTRACK)
-#else
-# define machine_is_ontrack()	(0)
-#endif
-
-#ifdef CONFIG_MACH_PM1200
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PM1200
-# endif
-# define machine_is_pm1200()	(machine_arch_type == MACH_TYPE_PM1200)
-#else
-# define machine_is_pm1200()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ESS24XXX
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ESS24XXX
-# endif
-# define machine_is_ess24562()	(machine_arch_type == MACH_TYPE_ESS24XXX)
-#else
-# define machine_is_ess24562()	(0)
-#endif
-
-#ifdef CONFIG_MACH_COREMP7
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_COREMP7
-# endif
-# define machine_is_coremp7()	(machine_arch_type == MACH_TYPE_COREMP7)
-#else
-# define machine_is_coremp7()	(0)
-#endif
-
-#ifdef CONFIG_MACH_NEXCODER_6446
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_NEXCODER_6446
-# endif
-# define machine_is_nexcoder_6446()	(machine_arch_type == MACH_TYPE_NEXCODER_6446)
-#else
-# define machine_is_nexcoder_6446()	(0)
-#endif
-
-#ifdef CONFIG_MACH_STVC8380
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_STVC8380
-# endif
-# define machine_is_stvc8380()	(machine_arch_type == MACH_TYPE_STVC8380)
-#else
-# define machine_is_stvc8380()	(0)
-#endif
-
-#ifdef CONFIG_MACH_TEKLYNX
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TEKLYNX
-# endif
-# define machine_is_teklynx()	(machine_arch_type == MACH_TYPE_TEKLYNX)
-#else
-# define machine_is_teklynx()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CARBONADO
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CARBONADO
-# endif
-# define machine_is_carbonado()	(machine_arch_type == MACH_TYPE_CARBONADO)
-#else
-# define machine_is_carbonado()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SYSMOS_MP730
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SYSMOS_MP730
-# endif
-# define machine_is_sysmos_mp730()	(machine_arch_type == MACH_TYPE_SYSMOS_MP730)
-#else
-# define machine_is_sysmos_mp730()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SNAPPER_CL15
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SNAPPER_CL15
-# endif
-# define machine_is_snapper_cl15()	(machine_arch_type == MACH_TYPE_SNAPPER_CL15)
-#else
-# define machine_is_snapper_cl15()	(0)
-#endif
-
-#ifdef CONFIG_MACH_PGIGIM
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PGIGIM
-# endif
-# define machine_is_pgigim()	(machine_arch_type == MACH_TYPE_PGIGIM)
-#else
-# define machine_is_pgigim()	(0)
-#endif
-
-#ifdef CONFIG_MACH_PTX9160P2
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PTX9160P2
-# endif
-# define machine_is_ptx9160p2()	(machine_arch_type == MACH_TYPE_PTX9160P2)
-#else
-# define machine_is_ptx9160p2()	(0)
-#endif
-
-#ifdef CONFIG_MACH_DCORE1
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_DCORE1
-# endif
-# define machine_is_dcore1()	(machine_arch_type == MACH_TYPE_DCORE1)
-#else
-# define machine_is_dcore1()	(0)
-#endif
-
-#ifdef CONFIG_MACH_VICTORPXA
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_VICTORPXA
-# endif
-# define machine_is_victorpxa()	(machine_arch_type == MACH_TYPE_VICTORPXA)
-#else
-# define machine_is_victorpxa()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MX2DTB
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MX2DTB
-# endif
-# define machine_is_mx2dtb()	(machine_arch_type == MACH_TYPE_MX2DTB)
-#else
-# define machine_is_mx2dtb()	(0)
-#endif
-
-#ifdef CONFIG_MACH_PXA_IREX_ER0100
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PXA_IREX_ER0100
-# endif
-# define machine_is_pxa_irex_er0100()	(machine_arch_type == MACH_TYPE_PXA_IREX_ER0100)
-#else
-# define machine_is_pxa_irex_er0100()	(0)
-#endif
-
-#ifdef CONFIG_MACH_OMAP_PALMZ71
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_OMAP_PALMZ71
-# endif
-# define machine_is_omap_palmz71()	(machine_arch_type == MACH_TYPE_OMAP_PALMZ71)
-#else
-# define machine_is_omap_palmz71()	(0)
-#endif
-
-#ifdef CONFIG_MACH_BARTEC_DEG
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_BARTEC_DEG
-# endif
-# define machine_is_bartec_deg()	(machine_arch_type == MACH_TYPE_BARTEC_DEG)
-#else
-# define machine_is_bartec_deg()	(0)
-#endif
-
-#ifdef CONFIG_MACH_HW50251
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_HW50251
-# endif
-# define machine_is_hw50251()	(machine_arch_type == MACH_TYPE_HW50251)
-#else
-# define machine_is_hw50251()	(0)
-#endif
-
-#ifdef CONFIG_MACH_IBOX
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_IBOX
-# endif
-# define machine_is_ibox()	(machine_arch_type == MACH_TYPE_IBOX)
-#else
-# define machine_is_ibox()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ATLASLH7A404
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ATLASLH7A404
-# endif
-# define machine_is_atlaslh7a404()	(machine_arch_type == MACH_TYPE_ATLASLH7A404)
-#else
-# define machine_is_atlaslh7a404()	(0)
-#endif
-
-#ifdef CONFIG_MACH_PT2026
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PT2026
-# endif
-# define machine_is_pt2026()	(machine_arch_type == MACH_TYPE_PT2026)
-#else
-# define machine_is_pt2026()	(0)
-#endif
-
-#ifdef CONFIG_MACH_HTCALPINE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_HTCALPINE
-# endif
-# define machine_is_htcalpine()	(machine_arch_type == MACH_TYPE_HTCALPINE)
-#else
-# define machine_is_htcalpine()	(0)
-#endif
-
-#ifdef CONFIG_MACH_BARTEC_VTU
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_BARTEC_VTU
-# endif
-# define machine_is_bartec_vtu()	(machine_arch_type == MACH_TYPE_BARTEC_VTU)
-#else
-# define machine_is_bartec_vtu()	(0)
-#endif
-
-#ifdef CONFIG_MACH_VCOREII
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_VCOREII
-# endif
-# define machine_is_vcoreii()	(machine_arch_type == MACH_TYPE_VCOREII)
-#else
-# define machine_is_vcoreii()	(0)
-#endif
-
-#ifdef CONFIG_MACH_PDNB3
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PDNB3
-# endif
-# define machine_is_pdnb3()	(machine_arch_type == MACH_TYPE_PDNB3)
-#else
-# define machine_is_pdnb3()	(0)
-#endif
-
-#ifdef CONFIG_MACH_HTCBEETLES
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_HTCBEETLES
-# endif
-# define machine_is_htcbeetles()	(machine_arch_type == MACH_TYPE_HTCBEETLES)
-#else
-# define machine_is_htcbeetles()	(0)
-#endif
-
-#ifdef CONFIG_MACH_S3C6400
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_S3C6400
-# endif
-# define machine_is_s3c6400()	(machine_arch_type == MACH_TYPE_S3C6400)
-#else
-# define machine_is_s3c6400()	(0)
-#endif
-
-#ifdef CONFIG_MACH_S3C2443
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_S3C2443
-# endif
-# define machine_is_s3c2443()	(machine_arch_type == MACH_TYPE_S3C2443)
-#else
-# define machine_is_s3c2443()	(0)
-#endif
-
-#ifdef CONFIG_MACH_OMAP_LDK
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_OMAP_LDK
-# endif
-# define machine_is_omap_ldk()	(machine_arch_type == MACH_TYPE_OMAP_LDK)
-#else
-# define machine_is_omap_ldk()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SMDK2460
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SMDK2460
-# endif
-# define machine_is_smdk2460()	(machine_arch_type == MACH_TYPE_SMDK2460)
-#else
-# define machine_is_smdk2460()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SMDK2440
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SMDK2440
-# endif
-# define machine_is_smdk2440()	(machine_arch_type == MACH_TYPE_SMDK2440)
-#else
-# define machine_is_smdk2440()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SMDK2412
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SMDK2412
-# endif
-# define machine_is_smdk2412()	(machine_arch_type == MACH_TYPE_SMDK2412)
-#else
-# define machine_is_smdk2412()	(0)
-#endif
-
-#ifdef CONFIG_MACH_WEBBOX
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_WEBBOX
-# endif
-# define machine_is_webbox()	(machine_arch_type == MACH_TYPE_WEBBOX)
-#else
-# define machine_is_webbox()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CWWNDP
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CWWNDP
-# endif
-# define machine_is_cwwndp()	(machine_arch_type == MACH_TYPE_CWWNDP)
-#else
-# define machine_is_cwwndp()	(0)
-#endif
-
-#ifdef CONFIG_MACH_DRAGON
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_DRAGON
-# endif
-# define machine_is_i839()	(machine_arch_type == MACH_TYPE_DRAGON)
-#else
-# define machine_is_i839()	(0)
-#endif
-
-#ifdef CONFIG_MACH_OPENDO_CPU_BOARD
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_OPENDO_CPU_BOARD
-# endif
-# define machine_is_opendo_cpu_board()	(machine_arch_type == MACH_TYPE_OPENDO_CPU_BOARD)
-#else
-# define machine_is_opendo_cpu_board()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CCM2200
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CCM2200
-# endif
-# define machine_is_ccm2200()	(machine_arch_type == MACH_TYPE_CCM2200)
-#else
-# define machine_is_ccm2200()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ETWARM
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ETWARM
-# endif
-# define machine_is_etwarm()	(machine_arch_type == MACH_TYPE_ETWARM)
-#else
-# define machine_is_etwarm()	(0)
-#endif
-
-#ifdef CONFIG_MACH_M93030
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_M93030
-# endif
-# define machine_is_m93030()	(machine_arch_type == MACH_TYPE_M93030)
-#else
-# define machine_is_m93030()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CC7U
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CC7U
-# endif
-# define machine_is_cc7u()	(machine_arch_type == MACH_TYPE_CC7U)
-#else
-# define machine_is_cc7u()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MTT_RANGER
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MTT_RANGER
-# endif
-# define machine_is_mtt_ranger()	(machine_arch_type == MACH_TYPE_MTT_RANGER)
-#else
-# define machine_is_mtt_ranger()	(0)
-#endif
-
-#ifdef CONFIG_MACH_NEXUS
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_NEXUS
-# endif
-# define machine_is_nexus()	(machine_arch_type == MACH_TYPE_NEXUS)
-#else
-# define machine_is_nexus()	(0)
-#endif
-
-#ifdef CONFIG_MACH_DESMAN
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_DESMAN
-# endif
-# define machine_is_desman()	(machine_arch_type == MACH_TYPE_DESMAN)
-#else
-# define machine_is_desman()	(0)
-#endif
-
-#ifdef CONFIG_MACH_BKDE303
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_BKDE303
-# endif
-# define machine_is_bkde303()	(machine_arch_type == MACH_TYPE_BKDE303)
-#else
-# define machine_is_bkde303()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SMDK2413
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SMDK2413
-# endif
-# define machine_is_smdk2413()	(machine_arch_type == MACH_TYPE_SMDK2413)
-#else
-# define machine_is_smdk2413()	(0)
-#endif
-
-#ifdef CONFIG_MACH_AML_M7200
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_AML_M7200
-# endif
-# define machine_is_aml_m7200()	(machine_arch_type == MACH_TYPE_AML_M7200)
-#else
-# define machine_is_aml_m7200()	(0)
-#endif
-
-#ifdef CONFIG_MACH_AML_M5900
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_AML_M5900
-# endif
-# define machine_is_aml_m5900()	(machine_arch_type == MACH_TYPE_AML_M5900)
-#else
-# define machine_is_aml_m5900()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SG640
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SG640
-# endif
-# define machine_is_sg640()	(machine_arch_type == MACH_TYPE_SG640)
-#else
-# define machine_is_sg640()	(0)
-#endif
-
-#ifdef CONFIG_MACH_EDG79524
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_EDG79524
-# endif
-# define machine_is_edg79524()	(machine_arch_type == MACH_TYPE_EDG79524)
-#else
-# define machine_is_edg79524()	(0)
-#endif
-
-#ifdef CONFIG_MACH_AI2410
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_AI2410
-# endif
-# define machine_is_ai2410()	(machine_arch_type == MACH_TYPE_AI2410)
-#else
-# define machine_is_ai2410()	(0)
-#endif
-
-#ifdef CONFIG_MACH_IXP465
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_IXP465
-# endif
-# define machine_is_ixp465()	(machine_arch_type == MACH_TYPE_IXP465)
-#else
-# define machine_is_ixp465()	(0)
-#endif
-
-#ifdef CONFIG_MACH_BALLOON3
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_BALLOON3
-# endif
-# define machine_is_balloon3()	(machine_arch_type == MACH_TYPE_BALLOON3)
-#else
-# define machine_is_balloon3()	(0)
-#endif
-
-#ifdef CONFIG_MACH_HEINS
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_HEINS
-# endif
-# define machine_is_heins()	(machine_arch_type == MACH_TYPE_HEINS)
-#else
-# define machine_is_heins()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MPLUSEVA
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MPLUSEVA
-# endif
-# define machine_is_mpluseva()	(machine_arch_type == MACH_TYPE_MPLUSEVA)
-#else
-# define machine_is_mpluseva()	(0)
-#endif
-
-#ifdef CONFIG_MACH_RT042
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_RT042
-# endif
-# define machine_is_rt042()	(machine_arch_type == MACH_TYPE_RT042)
-#else
-# define machine_is_rt042()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CWIEM
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CWIEM
-# endif
-# define machine_is_cwiem()	(machine_arch_type == MACH_TYPE_CWIEM)
-#else
-# define machine_is_cwiem()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CM_X270
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CM_X270
-# endif
-# define machine_is_cm_x270()	(machine_arch_type == MACH_TYPE_CM_X270)
-#else
-# define machine_is_cm_x270()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CM_X255
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CM_X255
-# endif
-# define machine_is_cm_x255()	(machine_arch_type == MACH_TYPE_CM_X255)
-#else
-# define machine_is_cm_x255()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ESH_AT91
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ESH_AT91
-# endif
-# define machine_is_esh_at91()	(machine_arch_type == MACH_TYPE_ESH_AT91)
-#else
-# define machine_is_esh_at91()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SANDGATE3
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SANDGATE3
-# endif
-# define machine_is_sandgate3()	(machine_arch_type == MACH_TYPE_SANDGATE3)
-#else
-# define machine_is_sandgate3()	(0)
-#endif
-
-#ifdef CONFIG_MACH_PRIMO
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PRIMO
-# endif
-# define machine_is_primo()	(machine_arch_type == MACH_TYPE_PRIMO)
-#else
-# define machine_is_primo()	(0)
-#endif
-
-#ifdef CONFIG_MACH_GEMSTONE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_GEMSTONE
-# endif
-# define machine_is_gemstone()	(machine_arch_type == MACH_TYPE_GEMSTONE)
-#else
-# define machine_is_gemstone()	(0)
-#endif
-
-#ifdef CONFIG_MACH_PRONGHORNMETRO
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PRONGHORNMETRO
-# endif
-# define machine_is_pronghorn_metro()	(machine_arch_type == MACH_TYPE_PRONGHORNMETRO)
-#else
-# define machine_is_pronghorn_metro()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SIDEWINDER
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SIDEWINDER
-# endif
-# define machine_is_sidewinder()	(machine_arch_type == MACH_TYPE_SIDEWINDER)
-#else
-# define machine_is_sidewinder()	(0)
-#endif
-
-#ifdef CONFIG_MACH_PICOMOD1
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PICOMOD1
-# endif
-# define machine_is_picomod1()	(machine_arch_type == MACH_TYPE_PICOMOD1)
-#else
-# define machine_is_picomod1()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SG590
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SG590
-# endif
-# define machine_is_sg590()	(machine_arch_type == MACH_TYPE_SG590)
-#else
-# define machine_is_sg590()	(0)
-#endif
-
-#ifdef CONFIG_MACH_AKAI9307
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_AKAI9307
-# endif
-# define machine_is_akai9307()	(machine_arch_type == MACH_TYPE_AKAI9307)
-#else
-# define machine_is_akai9307()	(0)
-#endif
-
-#ifdef CONFIG_MACH_FONTAINE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_FONTAINE
-# endif
-# define machine_is_fontaine()	(machine_arch_type == MACH_TYPE_FONTAINE)
-#else
-# define machine_is_fontaine()	(0)
-#endif
-
-#ifdef CONFIG_MACH_WOMBAT
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_WOMBAT
-# endif
-# define machine_is_wombat()	(machine_arch_type == MACH_TYPE_WOMBAT)
-#else
-# define machine_is_wombat()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ACQ300
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ACQ300
-# endif
-# define machine_is_acq300()	(machine_arch_type == MACH_TYPE_ACQ300)
-#else
-# define machine_is_acq300()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MOD_270
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MOD_270
-# endif
-# define machine_is_mod272()	(machine_arch_type == MACH_TYPE_MOD_270)
-#else
-# define machine_is_mod272()	(0)
-#endif
-
-#ifdef CONFIG_MACH_VC0820
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_VC0820
-# endif
-# define machine_is_vmc_vc0820()	(machine_arch_type == MACH_TYPE_VC0820)
-#else
-# define machine_is_vmc_vc0820()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ANI_AIM
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ANI_AIM
-# endif
-# define machine_is_ani_aim()	(machine_arch_type == MACH_TYPE_ANI_AIM)
-#else
-# define machine_is_ani_aim()	(0)
-#endif
-
-#ifdef CONFIG_MACH_JELLYFISH
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_JELLYFISH
-# endif
-# define machine_is_jellyfish()	(machine_arch_type == MACH_TYPE_JELLYFISH)
-#else
-# define machine_is_jellyfish()	(0)
-#endif
-
-#ifdef CONFIG_MACH_AMANITA
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_AMANITA
-# endif
-# define machine_is_amanita()	(machine_arch_type == MACH_TYPE_AMANITA)
-#else
-# define machine_is_amanita()	(0)
-#endif
-
-#ifdef CONFIG_MACH_VLINK
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_VLINK
-# endif
-# define machine_is_vlink()	(machine_arch_type == MACH_TYPE_VLINK)
-#else
-# define machine_is_vlink()	(0)
-#endif
-
-#ifdef CONFIG_MACH_DEXFLEX
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_DEXFLEX
-# endif
-# define machine_is_dexflex()	(machine_arch_type == MACH_TYPE_DEXFLEX)
-#else
-# define machine_is_dexflex()	(0)
-#endif
-
-#ifdef CONFIG_MACH_EIGEN_TTQ
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_EIGEN_TTQ
-# endif
-# define machine_is_eigen_ttq()	(machine_arch_type == MACH_TYPE_EIGEN_TTQ)
-#else
-# define machine_is_eigen_ttq()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ARCOM_TITAN
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ARCOM_TITAN
-# endif
-# define machine_is_arcom_titan()	(machine_arch_type == MACH_TYPE_ARCOM_TITAN)
-#else
-# define machine_is_arcom_titan()	(0)
-#endif
-
-#ifdef CONFIG_MACH_TABLA
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TABLA
-# endif
-# define machine_is_tabla()	(machine_arch_type == MACH_TYPE_TABLA)
-#else
-# define machine_is_tabla()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MDIRAC3
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MDIRAC3
-# endif
-# define machine_is_mdirac3()	(machine_arch_type == MACH_TYPE_MDIRAC3)
-#else
-# define machine_is_mdirac3()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MRHFBP2
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MRHFBP2
-# endif
-# define machine_is_mrhfbp2()	(machine_arch_type == MACH_TYPE_MRHFBP2)
-#else
-# define machine_is_mrhfbp2()	(0)
-#endif
-
-#ifdef CONFIG_MACH_AT91RM9200RB
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_AT91RM9200RB
-# endif
-# define machine_is_at91rm9200rb()	(machine_arch_type == MACH_TYPE_AT91RM9200RB)
-#else
-# define machine_is_at91rm9200rb()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ANI_APM
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ANI_APM
-# endif
-# define machine_is_ani_apm()	(machine_arch_type == MACH_TYPE_ANI_APM)
-#else
-# define machine_is_ani_apm()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ELLA1
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ELLA1
-# endif
-# define machine_is_ella1()	(machine_arch_type == MACH_TYPE_ELLA1)
-#else
-# define machine_is_ella1()	(0)
-#endif
-
-#ifdef CONFIG_MACH_INHAND_PXA27X
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_INHAND_PXA27X
-# endif
-# define machine_is_inhand_pxa27x()	(machine_arch_type == MACH_TYPE_INHAND_PXA27X)
-#else
-# define machine_is_inhand_pxa27x()	(0)
-#endif
-
-#ifdef CONFIG_MACH_INHAND_PXA25X
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_INHAND_PXA25X
-# endif
-# define machine_is_inhand_pxa25x()	(machine_arch_type == MACH_TYPE_INHAND_PXA25X)
-#else
-# define machine_is_inhand_pxa25x()	(0)
-#endif
-
-#ifdef CONFIG_MACH_EMPOS_XM
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_EMPOS_XM
-# endif
-# define machine_is_empos_xm()	(machine_arch_type == MACH_TYPE_EMPOS_XM)
-#else
-# define machine_is_empos_xm()	(0)
-#endif
-
-#ifdef CONFIG_MACH_EMPOS
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_EMPOS
-# endif
-# define machine_is_empos()	(machine_arch_type == MACH_TYPE_EMPOS)
-#else
-# define machine_is_empos()	(0)
-#endif
-
-#ifdef CONFIG_MACH_EMPOS_TINY
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_EMPOS_TINY
-# endif
-# define machine_is_empos_tiny()	(machine_arch_type == MACH_TYPE_EMPOS_TINY)
-#else
-# define machine_is_empos_tiny()	(0)
-#endif
-
-#ifdef CONFIG_MACH_EMPOS_SM
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_EMPOS_SM
-# endif
-# define machine_is_empos_sm()	(machine_arch_type == MACH_TYPE_EMPOS_SM)
-#else
-# define machine_is_empos_sm()	(0)
-#endif
-
-#ifdef CONFIG_MACH_EGRET
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_EGRET
-# endif
-# define machine_is_egret()	(machine_arch_type == MACH_TYPE_EGRET)
-#else
-# define machine_is_egret()	(0)
-#endif
-
-#ifdef CONFIG_MACH_OSTRICH
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_OSTRICH
-# endif
-# define machine_is_ostrich()	(machine_arch_type == MACH_TYPE_OSTRICH)
-#else
-# define machine_is_ostrich()	(0)
-#endif
-
-#ifdef CONFIG_MACH_N50
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_N50
-# endif
-# define machine_is_n50()	(machine_arch_type == MACH_TYPE_N50)
-#else
-# define machine_is_n50()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ECBAT91
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ECBAT91
-# endif
-# define machine_is_ecbat91()	(machine_arch_type == MACH_TYPE_ECBAT91)
-#else
-# define machine_is_ecbat91()	(0)
-#endif
-
-#ifdef CONFIG_MACH_STAREAST
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_STAREAST
-# endif
-# define machine_is_stareast()	(machine_arch_type == MACH_TYPE_STAREAST)
-#else
-# define machine_is_stareast()	(0)
-#endif
-
-#ifdef CONFIG_MACH_DSPG_DW
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_DSPG_DW
-# endif
-# define machine_is_dspg_dw()	(machine_arch_type == MACH_TYPE_DSPG_DW)
-#else
-# define machine_is_dspg_dw()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ONEARM
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ONEARM
-# endif
-# define machine_is_onearm()	(machine_arch_type == MACH_TYPE_ONEARM)
-#else
-# define machine_is_onearm()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MRG110_6
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MRG110_6
-# endif
-# define machine_is_mrg110_6()	(machine_arch_type == MACH_TYPE_MRG110_6)
-#else
-# define machine_is_mrg110_6()	(0)
-#endif
-
-#ifdef CONFIG_MACH_WRT300NV2
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_WRT300NV2
-# endif
-# define machine_is_wrt300nv2()	(machine_arch_type == MACH_TYPE_WRT300NV2)
-#else
-# define machine_is_wrt300nv2()	(0)
-#endif
-
-#ifdef CONFIG_MACH_XM_BULVERDE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_XM_BULVERDE
-# endif
-# define machine_is_xm_bulverde()	(machine_arch_type == MACH_TYPE_XM_BULVERDE)
-#else
-# define machine_is_xm_bulverde()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MSM6100
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MSM6100
-# endif
-# define machine_is_msm6100()	(machine_arch_type == MACH_TYPE_MSM6100)
-#else
-# define machine_is_msm6100()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ETI_B1
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ETI_B1
-# endif
-# define machine_is_eti_b1()	(machine_arch_type == MACH_TYPE_ETI_B1)
-#else
-# define machine_is_eti_b1()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ZILOG_ZA9L
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ZILOG_ZA9L
-# endif
-# define machine_is_za9l_series()	(machine_arch_type == MACH_TYPE_ZILOG_ZA9L)
-#else
-# define machine_is_za9l_series()	(0)
-#endif
-
-#ifdef CONFIG_MACH_BIT2440
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_BIT2440
-# endif
-# define machine_is_bit2440()	(machine_arch_type == MACH_TYPE_BIT2440)
-#else
-# define machine_is_bit2440()	(0)
-#endif
-
-#ifdef CONFIG_MACH_NBI
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_NBI
-# endif
-# define machine_is_nbi()	(machine_arch_type == MACH_TYPE_NBI)
-#else
-# define machine_is_nbi()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SMDK2443
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SMDK2443
-# endif
-# define machine_is_smdk2443()	(machine_arch_type == MACH_TYPE_SMDK2443)
-#else
-# define machine_is_smdk2443()	(0)
-#endif
-
-#ifdef CONFIG_MACH_VDAVINCI
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_VDAVINCI
-# endif
-# define machine_is_vdavinci()	(machine_arch_type == MACH_TYPE_VDAVINCI)
-#else
-# define machine_is_vdavinci()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ATC6
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ATC6
-# endif
-# define machine_is_atc6()	(machine_arch_type == MACH_TYPE_ATC6)
-#else
-# define machine_is_atc6()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MULTMDW
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MULTMDW
-# endif
-# define machine_is_multmdw()	(machine_arch_type == MACH_TYPE_MULTMDW)
-#else
-# define machine_is_multmdw()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MBA2440
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MBA2440
-# endif
-# define machine_is_mba2440()	(machine_arch_type == MACH_TYPE_MBA2440)
-#else
-# define machine_is_mba2440()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ECSD
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ECSD
-# endif
-# define machine_is_ecsd()	(machine_arch_type == MACH_TYPE_ECSD)
-#else
-# define machine_is_ecsd()	(0)
-#endif
-
-#ifdef CONFIG_MACH_PALMZ31
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PALMZ31
-# endif
-# define machine_is_palmz31()	(machine_arch_type == MACH_TYPE_PALMZ31)
-#else
-# define machine_is_palmz31()	(0)
-#endif
-
-#ifdef CONFIG_MACH_FSG
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_FSG
-# endif
-# define machine_is_fsg()	(machine_arch_type == MACH_TYPE_FSG)
-#else
-# define machine_is_fsg()	(0)
-#endif
-
-#ifdef CONFIG_MACH_RAZOR101
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_RAZOR101
-# endif
-# define machine_is_razor101()	(machine_arch_type == MACH_TYPE_RAZOR101)
-#else
-# define machine_is_razor101()	(0)
-#endif
-
-#ifdef CONFIG_MACH_OPERA_TDM
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_OPERA_TDM
-# endif
-# define machine_is_opera_tdm()	(machine_arch_type == MACH_TYPE_OPERA_TDM)
-#else
-# define machine_is_opera_tdm()	(0)
-#endif
-
-#ifdef CONFIG_MACH_COMCERTO
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_COMCERTO
-# endif
-# define machine_is_comcerto()	(machine_arch_type == MACH_TYPE_COMCERTO)
-#else
-# define machine_is_comcerto()	(0)
-#endif
-
-#ifdef CONFIG_MACH_TB0319
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TB0319
-# endif
-# define machine_is_tb0319()	(machine_arch_type == MACH_TYPE_TB0319)
-#else
-# define machine_is_tb0319()	(0)
-#endif
-
-#ifdef CONFIG_MACH_KWS8000
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_KWS8000
-# endif
-# define machine_is_kws8000()	(machine_arch_type == MACH_TYPE_KWS8000)
-#else
-# define machine_is_kws8000()	(0)
-#endif
-
-#ifdef CONFIG_MACH_B2
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_B2
-# endif
-# define machine_is_b2()	(machine_arch_type == MACH_TYPE_B2)
-#else
-# define machine_is_b2()	(0)
-#endif
-
-#ifdef CONFIG_MACH_LCL54
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_LCL54
-# endif
-# define machine_is_lcl54()	(machine_arch_type == MACH_TYPE_LCL54)
-#else
-# define machine_is_lcl54()	(0)
-#endif
-
-#ifdef CONFIG_MACH_AT91SAM9260EK
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_AT91SAM9260EK
-# endif
-# define machine_is_at91sam9260ek()	(machine_arch_type == MACH_TYPE_AT91SAM9260EK)
-#else
-# define machine_is_at91sam9260ek()	(0)
-#endif
-
-#ifdef CONFIG_MACH_GLANTANK
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_GLANTANK
-# endif
-# define machine_is_glantank()	(machine_arch_type == MACH_TYPE_GLANTANK)
-#else
-# define machine_is_glantank()	(0)
-#endif
-
-#ifdef CONFIG_MACH_N2100
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_N2100
-# endif
-# define machine_is_n2100()	(machine_arch_type == MACH_TYPE_N2100)
-#else
-# define machine_is_n2100()	(0)
-#endif
-
-#ifdef CONFIG_MACH_N4100
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_N4100
-# endif
-# define machine_is_n4100()	(machine_arch_type == MACH_TYPE_N4100)
-#else
-# define machine_is_n4100()	(0)
-#endif
-
-#ifdef CONFIG_MACH_VERTICAL_RSC4
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_VERTICAL_RSC4
-# endif
-# define machine_is_rsc4()	(machine_arch_type == MACH_TYPE_VERTICAL_RSC4)
-#else
-# define machine_is_rsc4()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SG8100
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SG8100
-# endif
-# define machine_is_sg8100()	(machine_arch_type == MACH_TYPE_SG8100)
-#else
-# define machine_is_sg8100()	(0)
-#endif
-
-#ifdef CONFIG_MACH_IM42XX
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_IM42XX
-# endif
-# define machine_is_im42xx()	(machine_arch_type == MACH_TYPE_IM42XX)
-#else
-# define machine_is_im42xx()	(0)
-#endif
-
-#ifdef CONFIG_MACH_FTXX
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_FTXX
-# endif
-# define machine_is_ftxx()	(machine_arch_type == MACH_TYPE_FTXX)
-#else
-# define machine_is_ftxx()	(0)
-#endif
-
-#ifdef CONFIG_MACH_LWFUSION
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_LWFUSION
-# endif
-# define machine_is_lwfusion()	(machine_arch_type == MACH_TYPE_LWFUSION)
-#else
-# define machine_is_lwfusion()	(0)
-#endif
-
-#ifdef CONFIG_MACH_QT2410
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_QT2410
-# endif
-# define machine_is_qt2410()	(machine_arch_type == MACH_TYPE_QT2410)
-#else
-# define machine_is_qt2410()	(0)
-#endif
-
-#ifdef CONFIG_MACH_KIXRP435
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_KIXRP435
-# endif
-# define machine_is_kixrp435()	(machine_arch_type == MACH_TYPE_KIXRP435)
-#else
-# define machine_is_kixrp435()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CCW9C
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CCW9C
-# endif
-# define machine_is_ccw9c()	(machine_arch_type == MACH_TYPE_CCW9C)
-#else
-# define machine_is_ccw9c()	(0)
-#endif
-
-#ifdef CONFIG_MACH_DABHS
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_DABHS
-# endif
-# define machine_is_dabhs()	(machine_arch_type == MACH_TYPE_DABHS)
-#else
-# define machine_is_dabhs()	(0)
-#endif
-
-#ifdef CONFIG_MACH_GZMX
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_GZMX
-# endif
-# define machine_is_gzmx()	(machine_arch_type == MACH_TYPE_GZMX)
-#else
-# define machine_is_gzmx()	(0)
-#endif
-
-#ifdef CONFIG_MACH_IPNW100AP
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_IPNW100AP
-# endif
-# define machine_is_ipnw100ap()	(machine_arch_type == MACH_TYPE_IPNW100AP)
-#else
-# define machine_is_ipnw100ap()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CC9P9360DEV
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CC9P9360DEV
-# endif
-# define machine_is_cc9p9360dev()	(machine_arch_type == MACH_TYPE_CC9P9360DEV)
-#else
-# define machine_is_cc9p9360dev()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CC9P9750DEV
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CC9P9750DEV
-# endif
-# define machine_is_cc9p9750dev()	(machine_arch_type == MACH_TYPE_CC9P9750DEV)
-#else
-# define machine_is_cc9p9750dev()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CC9P9360VAL
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CC9P9360VAL
-# endif
-# define machine_is_cc9p9360val()	(machine_arch_type == MACH_TYPE_CC9P9360VAL)
-#else
-# define machine_is_cc9p9360val()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CC9P9750VAL
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CC9P9750VAL
-# endif
-# define machine_is_cc9p9750val()	(machine_arch_type == MACH_TYPE_CC9P9750VAL)
-#else
-# define machine_is_cc9p9750val()	(0)
-#endif
-
-#ifdef CONFIG_MACH_NX70V
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_NX70V
-# endif
-# define machine_is_nx70v()	(machine_arch_type == MACH_TYPE_NX70V)
-#else
-# define machine_is_nx70v()	(0)
-#endif
-
-#ifdef CONFIG_MACH_AT91RM9200DF
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_AT91RM9200DF
-# endif
-# define machine_is_at91rm9200df()	(machine_arch_type == MACH_TYPE_AT91RM9200DF)
-#else
-# define machine_is_at91rm9200df()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SE_PILOT2
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SE_PILOT2
-# endif
-# define machine_is_se_pilot2()	(machine_arch_type == MACH_TYPE_SE_PILOT2)
-#else
-# define machine_is_se_pilot2()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MTCN_T800
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MTCN_T800
-# endif
-# define machine_is_mtcn_t800()	(machine_arch_type == MACH_TYPE_MTCN_T800)
-#else
-# define machine_is_mtcn_t800()	(0)
-#endif
-
-#ifdef CONFIG_MACH_VCMX212
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_VCMX212
-# endif
-# define machine_is_vcmx212()	(machine_arch_type == MACH_TYPE_VCMX212)
-#else
-# define machine_is_vcmx212()	(0)
-#endif
-
-#ifdef CONFIG_MACH_LYNX
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_LYNX
-# endif
-# define machine_is_lynx()	(machine_arch_type == MACH_TYPE_LYNX)
-#else
-# define machine_is_lynx()	(0)
-#endif
-
-#ifdef CONFIG_MACH_AT91SAM9260ID
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_AT91SAM9260ID
-# endif
-# define machine_is_at91sam9260id()	(machine_arch_type == MACH_TYPE_AT91SAM9260ID)
-#else
-# define machine_is_at91sam9260id()	(0)
-#endif
-
-#ifdef CONFIG_MACH_HW86052
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_HW86052
-# endif
-# define machine_is_hw86052()	(machine_arch_type == MACH_TYPE_HW86052)
-#else
-# define machine_is_hw86052()	(0)
-#endif
-
-#ifdef CONFIG_MACH_PILZ_PMI3
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PILZ_PMI3
-# endif
-# define machine_is_pilz_pmi3()	(machine_arch_type == MACH_TYPE_PILZ_PMI3)
-#else
-# define machine_is_pilz_pmi3()	(0)
-#endif
-
-#ifdef CONFIG_MACH_EDB9302A
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_EDB9302A
-# endif
-# define machine_is_edb9302a()	(machine_arch_type == MACH_TYPE_EDB9302A)
-#else
-# define machine_is_edb9302a()	(0)
-#endif
-
-#ifdef CONFIG_MACH_EDB9307A
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_EDB9307A
-# endif
-# define machine_is_edb9307a()	(machine_arch_type == MACH_TYPE_EDB9307A)
-#else
-# define machine_is_edb9307a()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CT_DFS
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CT_DFS
-# endif
-# define machine_is_ct_dfs()	(machine_arch_type == MACH_TYPE_CT_DFS)
-#else
-# define machine_is_ct_dfs()	(0)
-#endif
-
-#ifdef CONFIG_MACH_PILZ_PMI4
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PILZ_PMI4
-# endif
-# define machine_is_pilz_pmi4()	(machine_arch_type == MACH_TYPE_PILZ_PMI4)
-#else
-# define machine_is_pilz_pmi4()	(0)
-#endif
-
-#ifdef CONFIG_MACH_XCEEDNP_IXP
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_XCEEDNP_IXP
-# endif
-# define machine_is_xceednp_ixp()	(machine_arch_type == MACH_TYPE_XCEEDNP_IXP)
-#else
-# define machine_is_xceednp_ixp()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SMDK2442B
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SMDK2442B
-# endif
-# define machine_is_smdk2442b()	(machine_arch_type == MACH_TYPE_SMDK2442B)
-#else
-# define machine_is_smdk2442b()	(0)
-#endif
-
-#ifdef CONFIG_MACH_XNODE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_XNODE
-# endif
-# define machine_is_xnode()	(machine_arch_type == MACH_TYPE_XNODE)
-#else
-# define machine_is_xnode()	(0)
-#endif
-
-#ifdef CONFIG_MACH_AIDX270
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_AIDX270
-# endif
-# define machine_is_aidx270()	(machine_arch_type == MACH_TYPE_AIDX270)
-#else
-# define machine_is_aidx270()	(0)
-#endif
-
-#ifdef CONFIG_MACH_REMA
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_REMA
-# endif
-# define machine_is_rema()	(machine_arch_type == MACH_TYPE_REMA)
-#else
-# define machine_is_rema()	(0)
-#endif
-
-#ifdef CONFIG_MACH_BPS1000
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_BPS1000
-# endif
-# define machine_is_bps1000()	(machine_arch_type == MACH_TYPE_BPS1000)
-#else
-# define machine_is_bps1000()	(0)
-#endif
-
-#ifdef CONFIG_MACH_HW90350
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_HW90350
-# endif
-# define machine_is_hw90350()	(machine_arch_type == MACH_TYPE_HW90350)
-#else
-# define machine_is_hw90350()	(0)
-#endif
-
-#ifdef CONFIG_MACH_OMAP_3430SDP
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_OMAP_3430SDP
-# endif
-# define machine_is_omap_3430sdp()	(machine_arch_type == MACH_TYPE_OMAP_3430SDP)
-#else
-# define machine_is_omap_3430sdp()	(0)
-#endif
-
-#ifdef CONFIG_MACH_BLUETOUCH
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_BLUETOUCH
-# endif
-# define machine_is_bluetouch()	(machine_arch_type == MACH_TYPE_BLUETOUCH)
-#else
-# define machine_is_bluetouch()	(0)
-#endif
-
-#ifdef CONFIG_MACH_VSTMS
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_VSTMS
-# endif
-# define machine_is_vstms()	(machine_arch_type == MACH_TYPE_VSTMS)
-#else
-# define machine_is_vstms()	(0)
-#endif
-
-#ifdef CONFIG_MACH_XSBASE270
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_XSBASE270
-# endif
-# define machine_is_xsbase270()	(machine_arch_type == MACH_TYPE_XSBASE270)
-#else
-# define machine_is_xsbase270()	(0)
-#endif
-
-#ifdef CONFIG_MACH_AT91SAM9260EK_CN
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_AT91SAM9260EK_CN
-# endif
-# define machine_is_at91sam9260ek_cn()	(machine_arch_type == MACH_TYPE_AT91SAM9260EK_CN)
-#else
-# define machine_is_at91sam9260ek_cn()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ADSTURBOXB
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ADSTURBOXB
-# endif
-# define machine_is_adsturboxb()	(machine_arch_type == MACH_TYPE_ADSTURBOXB)
-#else
-# define machine_is_adsturboxb()	(0)
-#endif
-
-#ifdef CONFIG_MACH_OTI4110
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_OTI4110
-# endif
-# define machine_is_oti4110()	(machine_arch_type == MACH_TYPE_OTI4110)
-#else
-# define machine_is_oti4110()	(0)
-#endif
-
-#ifdef CONFIG_MACH_HME_PXA
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_HME_PXA
-# endif
-# define machine_is_hme_pxa()	(machine_arch_type == MACH_TYPE_HME_PXA)
-#else
-# define machine_is_hme_pxa()	(0)
-#endif
-
-#ifdef CONFIG_MACH_DEISTERDCA
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_DEISTERDCA
-# endif
-# define machine_is_deisterdca()	(machine_arch_type == MACH_TYPE_DEISTERDCA)
-#else
-# define machine_is_deisterdca()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CES_SSEM2
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CES_SSEM2
-# endif
-# define machine_is_ces_ssem2()	(machine_arch_type == MACH_TYPE_CES_SSEM2)
-#else
-# define machine_is_ces_ssem2()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CES_MTR
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CES_MTR
-# endif
-# define machine_is_ces_mtr()	(machine_arch_type == MACH_TYPE_CES_MTR)
-#else
-# define machine_is_ces_mtr()	(0)
-#endif
-
-#ifdef CONFIG_MACH_TDS_AVNG_SBC
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TDS_AVNG_SBC
-# endif
-# define machine_is_tds_avng_sbc()	(machine_arch_type == MACH_TYPE_TDS_AVNG_SBC)
-#else
-# define machine_is_tds_avng_sbc()	(0)
-#endif
-
-#ifdef CONFIG_MACH_EVEREST
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_EVEREST
-# endif
-# define machine_is_everest()	(machine_arch_type == MACH_TYPE_EVEREST)
-#else
-# define machine_is_everest()	(0)
-#endif
-
-#ifdef CONFIG_MACH_PNX4010
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PNX4010
-# endif
-# define machine_is_pnx4010()	(machine_arch_type == MACH_TYPE_PNX4010)
-#else
-# define machine_is_pnx4010()	(0)
-#endif
-
-#ifdef CONFIG_MACH_OXNAS
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_OXNAS
-# endif
-# define machine_is_oxnas()	(machine_arch_type == MACH_TYPE_OXNAS)
-#else
-# define machine_is_oxnas()	(0)
-#endif
-
-#ifdef CONFIG_MACH_FIORI
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_FIORI
-# endif
-# define machine_is_fiori()	(machine_arch_type == MACH_TYPE_FIORI)
-#else
-# define machine_is_fiori()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ML1200
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ML1200
-# endif
-# define machine_is_ml1200()	(machine_arch_type == MACH_TYPE_ML1200)
-#else
-# define machine_is_ml1200()	(0)
-#endif
-
-#ifdef CONFIG_MACH_PECOS
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PECOS
-# endif
-# define machine_is_pecos()	(machine_arch_type == MACH_TYPE_PECOS)
-#else
-# define machine_is_pecos()	(0)
-#endif
-
-#ifdef CONFIG_MACH_NB2XXX
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_NB2XXX
-# endif
-# define machine_is_nb2xxx()	(machine_arch_type == MACH_TYPE_NB2XXX)
-#else
-# define machine_is_nb2xxx()	(0)
-#endif
-
-#ifdef CONFIG_MACH_HW6900
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_HW6900
-# endif
-# define machine_is_hw6900()	(machine_arch_type == MACH_TYPE_HW6900)
-#else
-# define machine_is_hw6900()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CDCS_QUOLL
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CDCS_QUOLL
-# endif
-# define machine_is_cdcs_quoll()	(machine_arch_type == MACH_TYPE_CDCS_QUOLL)
-#else
-# define machine_is_cdcs_quoll()	(0)
-#endif
-
-#ifdef CONFIG_MACH_QUICKSILVER
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_QUICKSILVER
-# endif
-# define machine_is_quicksilver()	(machine_arch_type == MACH_TYPE_QUICKSILVER)
-#else
-# define machine_is_quicksilver()	(0)
-#endif
-
-#ifdef CONFIG_MACH_UPLAT926
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_UPLAT926
-# endif
-# define machine_is_uplat926()	(machine_arch_type == MACH_TYPE_UPLAT926)
-#else
-# define machine_is_uplat926()	(0)
-#endif
-
-#ifdef CONFIG_MACH_DEP2410_THOMAS
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_DEP2410_THOMAS
-# endif
-# define machine_is_dep2410_dep2410()	(machine_arch_type == MACH_TYPE_DEP2410_THOMAS)
-#else
-# define machine_is_dep2410_dep2410()	(0)
-#endif
-
-#ifdef CONFIG_MACH_DTK2410
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_DTK2410
-# endif
-# define machine_is_dtk2410()	(machine_arch_type == MACH_TYPE_DTK2410)
-#else
-# define machine_is_dtk2410()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CHILI
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CHILI
-# endif
-# define machine_is_chili()	(machine_arch_type == MACH_TYPE_CHILI)
-#else
-# define machine_is_chili()	(0)
-#endif
-
-#ifdef CONFIG_MACH_DEMETER
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_DEMETER
-# endif
-# define machine_is_demeter()	(machine_arch_type == MACH_TYPE_DEMETER)
-#else
-# define machine_is_demeter()	(0)
-#endif
-
-#ifdef CONFIG_MACH_DIONYSUS
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_DIONYSUS
-# endif
-# define machine_is_dionysus()	(machine_arch_type == MACH_TYPE_DIONYSUS)
-#else
-# define machine_is_dionysus()	(0)
-#endif
-
-#ifdef CONFIG_MACH_AS352X
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_AS352X
-# endif
-# define machine_is_as352x()	(machine_arch_type == MACH_TYPE_AS352X)
-#else
-# define machine_is_as352x()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SERVICE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SERVICE
-# endif
-# define machine_is_service()	(machine_arch_type == MACH_TYPE_SERVICE)
-#else
-# define machine_is_service()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CS_E9301
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CS_E9301
-# endif
-# define machine_is_cs_e9301()	(machine_arch_type == MACH_TYPE_CS_E9301)
-#else
-# define machine_is_cs_e9301()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MICRO9M
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MICRO9M
-# endif
-# define machine_is_micro9m()	(machine_arch_type == MACH_TYPE_MICRO9M)
-#else
-# define machine_is_micro9m()	(0)
-#endif
-
-#ifdef CONFIG_MACH_IA_MOSPCK
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_IA_MOSPCK
-# endif
-# define machine_is_ia_mospck()	(machine_arch_type == MACH_TYPE_IA_MOSPCK)
-#else
-# define machine_is_ia_mospck()	(0)
-#endif
-
-#ifdef CONFIG_MACH_QL201B
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_QL201B
-# endif
-# define machine_is_ql201b()	(machine_arch_type == MACH_TYPE_QL201B)
-#else
-# define machine_is_ql201b()	(0)
-#endif
-
-#ifdef CONFIG_MACH_BBM
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_BBM
-# endif
-# define machine_is_bbm()	(machine_arch_type == MACH_TYPE_BBM)
-#else
-# define machine_is_bbm()	(0)
-#endif
-
-#ifdef CONFIG_MACH_EXXX
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_EXXX
-# endif
-# define machine_is_exxx()	(machine_arch_type == MACH_TYPE_EXXX)
-#else
-# define machine_is_exxx()	(0)
-#endif
-
-#ifdef CONFIG_MACH_WMA11B
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_WMA11B
-# endif
-# define machine_is_wma11b()	(machine_arch_type == MACH_TYPE_WMA11B)
-#else
-# define machine_is_wma11b()	(0)
-#endif
-
-#ifdef CONFIG_MACH_PELCO_ATLAS
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PELCO_ATLAS
-# endif
-# define machine_is_pelco_atlas()	(machine_arch_type == MACH_TYPE_PELCO_ATLAS)
-#else
-# define machine_is_pelco_atlas()	(0)
-#endif
-
-#ifdef CONFIG_MACH_G500
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_G500
-# endif
-# define machine_is_g500()	(machine_arch_type == MACH_TYPE_G500)
-#else
-# define machine_is_g500()	(0)
-#endif
-
-#ifdef CONFIG_MACH_BUG
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_BUG
-# endif
-# define machine_is_bug()	(machine_arch_type == MACH_TYPE_BUG)
-#else
-# define machine_is_bug()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MX33ADS
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MX33ADS
-# endif
-# define machine_is_mx33ads()	(machine_arch_type == MACH_TYPE_MX33ADS)
-#else
-# define machine_is_mx33ads()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CHUB
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CHUB
-# endif
-# define machine_is_chub()	(machine_arch_type == MACH_TYPE_CHUB)
-#else
-# define machine_is_chub()	(0)
-#endif
-
-#ifdef CONFIG_MACH_NEO1973_GTA01
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_NEO1973_GTA01
-# endif
-# define machine_is_neo1973_gta01()	(machine_arch_type == MACH_TYPE_NEO1973_GTA01)
-#else
-# define machine_is_neo1973_gta01()	(0)
-#endif
-
-#ifdef CONFIG_MACH_W90N740
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_W90N740
-# endif
-# define machine_is_w90n740()	(machine_arch_type == MACH_TYPE_W90N740)
-#else
-# define machine_is_w90n740()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MEDALLION_SA2410
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MEDALLION_SA2410
-# endif
-# define machine_is_medallion_sa2410()	(machine_arch_type == MACH_TYPE_MEDALLION_SA2410)
-#else
-# define machine_is_medallion_sa2410()	(0)
-#endif
-
-#ifdef CONFIG_MACH_IA_CPU_9200_2
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_IA_CPU_9200_2
-# endif
-# define machine_is_ia_cpu_9200_2()	(machine_arch_type == MACH_TYPE_IA_CPU_9200_2)
-#else
-# define machine_is_ia_cpu_9200_2()	(0)
-#endif
-
-#ifdef CONFIG_MACH_DIMMRM9200
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_DIMMRM9200
-# endif
-# define machine_is_dimmrm9200()	(machine_arch_type == MACH_TYPE_DIMMRM9200)
-#else
-# define machine_is_dimmrm9200()	(0)
-#endif
-
-#ifdef CONFIG_MACH_PM9261
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PM9261
-# endif
-# define machine_is_pm9261()	(machine_arch_type == MACH_TYPE_PM9261)
-#else
-# define machine_is_pm9261()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ML7304
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ML7304
-# endif
-# define machine_is_ml7304()	(machine_arch_type == MACH_TYPE_ML7304)
-#else
-# define machine_is_ml7304()	(0)
-#endif
-
-#ifdef CONFIG_MACH_UCP250
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_UCP250
-# endif
-# define machine_is_ucp250()	(machine_arch_type == MACH_TYPE_UCP250)
-#else
-# define machine_is_ucp250()	(0)
-#endif
-
-#ifdef CONFIG_MACH_INTBOARD
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_INTBOARD
-# endif
-# define machine_is_intboard()	(machine_arch_type == MACH_TYPE_INTBOARD)
-#else
-# define machine_is_intboard()	(0)
-#endif
-
-#ifdef CONFIG_MACH_GULFSTREAM
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_GULFSTREAM
-# endif
-# define machine_is_gulfstream()	(machine_arch_type == MACH_TYPE_GULFSTREAM)
-#else
-# define machine_is_gulfstream()	(0)
-#endif
-
-#ifdef CONFIG_MACH_LABQUEST
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_LABQUEST
-# endif
-# define machine_is_labquest()	(machine_arch_type == MACH_TYPE_LABQUEST)
-#else
-# define machine_is_labquest()	(0)
-#endif
-
-#ifdef CONFIG_MACH_VCMX313
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_VCMX313
-# endif
-# define machine_is_vcmx313()	(machine_arch_type == MACH_TYPE_VCMX313)
-#else
-# define machine_is_vcmx313()	(0)
-#endif
-
-#ifdef CONFIG_MACH_URG200
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_URG200
-# endif
-# define machine_is_urg200()	(machine_arch_type == MACH_TYPE_URG200)
-#else
-# define machine_is_urg200()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CPUX255LCDNET
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CPUX255LCDNET
-# endif
-# define machine_is_cpux255lcdnet()	(machine_arch_type == MACH_TYPE_CPUX255LCDNET)
-#else
-# define machine_is_cpux255lcdnet()	(0)
-#endif
-
-#ifdef CONFIG_MACH_NETDCU9
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_NETDCU9
-# endif
-# define machine_is_netdcu9()	(machine_arch_type == MACH_TYPE_NETDCU9)
-#else
-# define machine_is_netdcu9()	(0)
-#endif
-
-#ifdef CONFIG_MACH_NETDCU10
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_NETDCU10
-# endif
-# define machine_is_netdcu10()	(machine_arch_type == MACH_TYPE_NETDCU10)
-#else
-# define machine_is_netdcu10()	(0)
-#endif
-
-#ifdef CONFIG_MACH_DSPG_DGA
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_DSPG_DGA
-# endif
-# define machine_is_dspg_dga()	(machine_arch_type == MACH_TYPE_DSPG_DGA)
-#else
-# define machine_is_dspg_dga()	(0)
-#endif
-
-#ifdef CONFIG_MACH_DSPG_DVW
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_DSPG_DVW
-# endif
-# define machine_is_dspg_dvw()	(machine_arch_type == MACH_TYPE_DSPG_DVW)
-#else
-# define machine_is_dspg_dvw()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SOLOS
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SOLOS
-# endif
-# define machine_is_solos()	(machine_arch_type == MACH_TYPE_SOLOS)
-#else
-# define machine_is_solos()	(0)
-#endif
-
-#ifdef CONFIG_MACH_AT91SAM9263EK
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_AT91SAM9263EK
-# endif
-# define machine_is_at91sam9263ek()	(machine_arch_type == MACH_TYPE_AT91SAM9263EK)
-#else
-# define machine_is_at91sam9263ek()	(0)
-#endif
-
-#ifdef CONFIG_MACH_OSSTBOX
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_OSSTBOX
-# endif
-# define machine_is_osstbox()	(machine_arch_type == MACH_TYPE_OSSTBOX)
-#else
-# define machine_is_osstbox()	(0)
-#endif
-
-#ifdef CONFIG_MACH_KBAT9261
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_KBAT9261
-# endif
-# define machine_is_kbat9261()	(machine_arch_type == MACH_TYPE_KBAT9261)
-#else
-# define machine_is_kbat9261()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CT1100
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CT1100
-# endif
-# define machine_is_ct1100()	(machine_arch_type == MACH_TYPE_CT1100)
-#else
-# define machine_is_ct1100()	(0)
-#endif
-
-#ifdef CONFIG_MACH_AKCPPXA
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_AKCPPXA
-# endif
-# define machine_is_akcppxa()	(machine_arch_type == MACH_TYPE_AKCPPXA)
-#else
-# define machine_is_akcppxa()	(0)
-#endif
-
-#ifdef CONFIG_MACH_OCHAYA1020
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_OCHAYA1020
-# endif
-# define machine_is_ochaya1020()	(machine_arch_type == MACH_TYPE_OCHAYA1020)
-#else
-# define machine_is_ochaya1020()	(0)
-#endif
-
-#ifdef CONFIG_MACH_HITRACK
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_HITRACK
-# endif
-# define machine_is_hitrack()	(machine_arch_type == MACH_TYPE_HITRACK)
-#else
-# define machine_is_hitrack()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SYME1
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SYME1
-# endif
-# define machine_is_syme1()	(machine_arch_type == MACH_TYPE_SYME1)
-#else
-# define machine_is_syme1()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SYHL1
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SYHL1
-# endif
-# define machine_is_syhl1()	(machine_arch_type == MACH_TYPE_SYHL1)
-#else
-# define machine_is_syhl1()	(0)
-#endif
-
-#ifdef CONFIG_MACH_EMPCA400
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_EMPCA400
-# endif
-# define machine_is_empca400()	(machine_arch_type == MACH_TYPE_EMPCA400)
-#else
-# define machine_is_empca400()	(0)
-#endif
-
-#ifdef CONFIG_MACH_EM7210
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_EM7210
-# endif
-# define machine_is_em7210()	(machine_arch_type == MACH_TYPE_EM7210)
-#else
-# define machine_is_em7210()	(0)
-#endif
-
-#ifdef CONFIG_MACH_HTCHERMES
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_HTCHERMES
-# endif
-# define machine_is_htchermes()	(machine_arch_type == MACH_TYPE_HTCHERMES)
-#else
-# define machine_is_htchermes()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ETI_C1
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ETI_C1
-# endif
-# define machine_is_eti_c1()	(machine_arch_type == MACH_TYPE_ETI_C1)
-#else
-# define machine_is_eti_c1()	(0)
-#endif
-
-#ifdef CONFIG_MACH_AC100
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_AC100
-# endif
-# define machine_is_ac100()	(machine_arch_type == MACH_TYPE_AC100)
-#else
-# define machine_is_ac100()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SNEETCH
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SNEETCH
-# endif
-# define machine_is_sneetch()	(machine_arch_type == MACH_TYPE_SNEETCH)
-#else
-# define machine_is_sneetch()	(0)
-#endif
-
-#ifdef CONFIG_MACH_STUDENTMATE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_STUDENTMATE
-# endif
-# define machine_is_studentmate()	(machine_arch_type == MACH_TYPE_STUDENTMATE)
-#else
-# define machine_is_studentmate()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ZIR2410
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ZIR2410
-# endif
-# define machine_is_zir2410()	(machine_arch_type == MACH_TYPE_ZIR2410)
-#else
-# define machine_is_zir2410()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ZIR2413
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ZIR2413
-# endif
-# define machine_is_zir2413()	(machine_arch_type == MACH_TYPE_ZIR2413)
-#else
-# define machine_is_zir2413()	(0)
-#endif
-
-#ifdef CONFIG_MACH_DLONIP3
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_DLONIP3
-# endif
-# define machine_is_dlonip3()	(machine_arch_type == MACH_TYPE_DLONIP3)
-#else
-# define machine_is_dlonip3()	(0)
-#endif
-
-#ifdef CONFIG_MACH_INSTREAM
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_INSTREAM
-# endif
-# define machine_is_instream()	(machine_arch_type == MACH_TYPE_INSTREAM)
-#else
-# define machine_is_instream()	(0)
-#endif
-
-#ifdef CONFIG_MACH_AMBARELLA
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_AMBARELLA
-# endif
-# define machine_is_ambarella()	(machine_arch_type == MACH_TYPE_AMBARELLA)
-#else
-# define machine_is_ambarella()	(0)
-#endif
-
-#ifdef CONFIG_MACH_NEVIS
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_NEVIS
-# endif
-# define machine_is_nevis()	(machine_arch_type == MACH_TYPE_NEVIS)
-#else
-# define machine_is_nevis()	(0)
-#endif
-
-#ifdef CONFIG_MACH_HTC_TRINITY
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_HTC_TRINITY
-# endif
-# define machine_is_htc_trinity()	(machine_arch_type == MACH_TYPE_HTC_TRINITY)
-#else
-# define machine_is_htc_trinity()	(0)
-#endif
-
-#ifdef CONFIG_MACH_QL202B
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_QL202B
-# endif
-# define machine_is_ql202b()	(machine_arch_type == MACH_TYPE_QL202B)
-#else
-# define machine_is_ql202b()	(0)
-#endif
-
-#ifdef CONFIG_MACH_VPAC270
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_VPAC270
-# endif
-# define machine_is_vpac270()	(machine_arch_type == MACH_TYPE_VPAC270)
-#else
-# define machine_is_vpac270()	(0)
-#endif
-
-#ifdef CONFIG_MACH_RD129
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_RD129
-# endif
-# define machine_is_rd129()	(machine_arch_type == MACH_TYPE_RD129)
-#else
-# define machine_is_rd129()	(0)
-#endif
-
-#ifdef CONFIG_MACH_HTCWIZARD
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_HTCWIZARD
-# endif
-# define machine_is_htcwizard()	(machine_arch_type == MACH_TYPE_HTCWIZARD)
-#else
-# define machine_is_htcwizard()	(0)
-#endif
-
-#ifdef CONFIG_MACH_TREO680
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TREO680
-# endif
-# define machine_is_treo680()	(machine_arch_type == MACH_TYPE_TREO680)
-#else
-# define machine_is_treo680()	(0)
-#endif
-
-#ifdef CONFIG_MACH_TECON_TMEZON
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TECON_TMEZON
-# endif
-# define machine_is_tecon_tmezon()	(machine_arch_type == MACH_TYPE_TECON_TMEZON)
-#else
-# define machine_is_tecon_tmezon()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ZYLONITE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ZYLONITE
-# endif
-# define machine_is_zylonite()	(machine_arch_type == MACH_TYPE_ZYLONITE)
-#else
-# define machine_is_zylonite()	(0)
-#endif
-
-#ifdef CONFIG_MACH_GENE1270
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_GENE1270
-# endif
-# define machine_is_gene1270()	(machine_arch_type == MACH_TYPE_GENE1270)
-#else
-# define machine_is_gene1270()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ZIR2412
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ZIR2412
-# endif
-# define machine_is_zir2412()	(machine_arch_type == MACH_TYPE_ZIR2412)
-#else
-# define machine_is_zir2412()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MX31LITE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MX31LITE
-# endif
-# define machine_is_mx31lite()	(machine_arch_type == MACH_TYPE_MX31LITE)
-#else
-# define machine_is_mx31lite()	(0)
-#endif
-
-#ifdef CONFIG_MACH_T700WX
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_T700WX
-# endif
-# define machine_is_t700wx()	(machine_arch_type == MACH_TYPE_T700WX)
-#else
-# define machine_is_t700wx()	(0)
-#endif
-
-#ifdef CONFIG_MACH_VF100
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_VF100
-# endif
-# define machine_is_vf100()	(machine_arch_type == MACH_TYPE_VF100)
-#else
-# define machine_is_vf100()	(0)
-#endif
-
-#ifdef CONFIG_MACH_NSB2
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_NSB2
-# endif
-# define machine_is_nsb2()	(machine_arch_type == MACH_TYPE_NSB2)
-#else
-# define machine_is_nsb2()	(0)
-#endif
-
-#ifdef CONFIG_MACH_NXHMI_BB
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_NXHMI_BB
-# endif
-# define machine_is_nxhmi_bb()	(machine_arch_type == MACH_TYPE_NXHMI_BB)
-#else
-# define machine_is_nxhmi_bb()	(0)
-#endif
-
-#ifdef CONFIG_MACH_NXHMI_RE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_NXHMI_RE
-# endif
-# define machine_is_nxhmi_re()	(machine_arch_type == MACH_TYPE_NXHMI_RE)
-#else
-# define machine_is_nxhmi_re()	(0)
-#endif
-
-#ifdef CONFIG_MACH_N4100PRO
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_N4100PRO
-# endif
-# define machine_is_n4100pro()	(machine_arch_type == MACH_TYPE_N4100PRO)
-#else
-# define machine_is_n4100pro()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SAM9260
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SAM9260
-# endif
-# define machine_is_sam9260()	(machine_arch_type == MACH_TYPE_SAM9260)
-#else
-# define machine_is_sam9260()	(0)
-#endif
-
-#ifdef CONFIG_MACH_OMAP_TREO600
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_OMAP_TREO600
-# endif
-# define machine_is_omap_treo600()	(machine_arch_type == MACH_TYPE_OMAP_TREO600)
-#else
-# define machine_is_omap_treo600()	(0)
-#endif
-
-#ifdef CONFIG_MACH_INDY2410
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_INDY2410
-# endif
-# define machine_is_indy2410()	(machine_arch_type == MACH_TYPE_INDY2410)
-#else
-# define machine_is_indy2410()	(0)
-#endif
-
-#ifdef CONFIG_MACH_NELT_A
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_NELT_A
-# endif
-# define machine_is_nelt_a()	(machine_arch_type == MACH_TYPE_NELT_A)
-#else
-# define machine_is_nelt_a()	(0)
-#endif
-
-#ifdef CONFIG_MACH_N311
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_N311
-# endif
-# define machine_is_n311()	(machine_arch_type == MACH_TYPE_N311)
-#else
-# define machine_is_n311()	(0)
-#endif
-
-#ifdef CONFIG_MACH_AT91SAM9260VGK
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_AT91SAM9260VGK
-# endif
-# define machine_is_at91sam9260vgk()	(machine_arch_type == MACH_TYPE_AT91SAM9260VGK)
-#else
-# define machine_is_at91sam9260vgk()	(0)
-#endif
-
-#ifdef CONFIG_MACH_AT91LEPPE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_AT91LEPPE
-# endif
-# define machine_is_at91leppe()	(machine_arch_type == MACH_TYPE_AT91LEPPE)
-#else
-# define machine_is_at91leppe()	(0)
-#endif
-
-#ifdef CONFIG_MACH_AT91LEPCCN
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_AT91LEPCCN
-# endif
-# define machine_is_at91lepccn()	(machine_arch_type == MACH_TYPE_AT91LEPCCN)
-#else
-# define machine_is_at91lepccn()	(0)
-#endif
-
-#ifdef CONFIG_MACH_APC7100
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_APC7100
-# endif
-# define machine_is_apc7100()	(machine_arch_type == MACH_TYPE_APC7100)
-#else
-# define machine_is_apc7100()	(0)
-#endif
-
-#ifdef CONFIG_MACH_STARGAZER
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_STARGAZER
-# endif
-# define machine_is_stargazer()	(machine_arch_type == MACH_TYPE_STARGAZER)
-#else
-# define machine_is_stargazer()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SONATA
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SONATA
-# endif
-# define machine_is_sonata()	(machine_arch_type == MACH_TYPE_SONATA)
-#else
-# define machine_is_sonata()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SCHMOOGIE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SCHMOOGIE
-# endif
-# define machine_is_schmoogie()	(machine_arch_type == MACH_TYPE_SCHMOOGIE)
-#else
-# define machine_is_schmoogie()	(0)
-#endif
-
-#ifdef CONFIG_MACH_AZTOOL
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_AZTOOL
-# endif
-# define machine_is_aztool()	(machine_arch_type == MACH_TYPE_AZTOOL)
-#else
-# define machine_is_aztool()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MIOA701
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MIOA701
-# endif
-# define machine_is_mioa701()	(machine_arch_type == MACH_TYPE_MIOA701)
-#else
-# define machine_is_mioa701()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SXNI9260
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SXNI9260
-# endif
-# define machine_is_sxni9260()	(machine_arch_type == MACH_TYPE_SXNI9260)
-#else
-# define machine_is_sxni9260()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MXC27520EVB
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MXC27520EVB
-# endif
-# define machine_is_mxc27520evb()	(machine_arch_type == MACH_TYPE_MXC27520EVB)
-#else
-# define machine_is_mxc27520evb()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ARMADILLO5X0
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ARMADILLO5X0
-# endif
-# define machine_is_armadillo5x0()	(machine_arch_type == MACH_TYPE_ARMADILLO5X0)
-#else
-# define machine_is_armadillo5x0()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MB9260
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MB9260
-# endif
-# define machine_is_mb9260()	(machine_arch_type == MACH_TYPE_MB9260)
-#else
-# define machine_is_mb9260()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MB9263
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MB9263
-# endif
-# define machine_is_mb9263()	(machine_arch_type == MACH_TYPE_MB9263)
-#else
-# define machine_is_mb9263()	(0)
-#endif
-
-#ifdef CONFIG_MACH_IPAC9302
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_IPAC9302
-# endif
-# define machine_is_ipac9302()	(machine_arch_type == MACH_TYPE_IPAC9302)
-#else
-# define machine_is_ipac9302()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CC9P9360JS
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CC9P9360JS
-# endif
-# define machine_is_cc9p9360js()	(machine_arch_type == MACH_TYPE_CC9P9360JS)
-#else
-# define machine_is_cc9p9360js()	(0)
-#endif
-
-#ifdef CONFIG_MACH_GALLIUM
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_GALLIUM
-# endif
-# define machine_is_gallium()	(machine_arch_type == MACH_TYPE_GALLIUM)
-#else
-# define machine_is_gallium()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MSC2410
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MSC2410
-# endif
-# define machine_is_msc2410()	(machine_arch_type == MACH_TYPE_MSC2410)
-#else
-# define machine_is_msc2410()	(0)
-#endif
-
-#ifdef CONFIG_MACH_GHI270
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_GHI270
-# endif
-# define machine_is_ghi270()	(machine_arch_type == MACH_TYPE_GHI270)
-#else
-# define machine_is_ghi270()	(0)
-#endif
-
-#ifdef CONFIG_MACH_DAVINCI_LEONARDO
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_DAVINCI_LEONARDO
-# endif
-# define machine_is_davinci_leonardo()	(machine_arch_type == MACH_TYPE_DAVINCI_LEONARDO)
-#else
-# define machine_is_davinci_leonardo()	(0)
-#endif
-
-#ifdef CONFIG_MACH_OIAB
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_OIAB
-# endif
-# define machine_is_oiab()	(machine_arch_type == MACH_TYPE_OIAB)
-#else
-# define machine_is_oiab()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SMDK6400
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SMDK6400
-# endif
-# define machine_is_smdk6400()	(machine_arch_type == MACH_TYPE_SMDK6400)
-#else
-# define machine_is_smdk6400()	(0)
-#endif
-
-#ifdef CONFIG_MACH_NOKIA_N800
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_NOKIA_N800
-# endif
-# define machine_is_nokia_n800()	(machine_arch_type == MACH_TYPE_NOKIA_N800)
-#else
-# define machine_is_nokia_n800()	(0)
-#endif
-
-#ifdef CONFIG_MACH_GREENPHONE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_GREENPHONE
-# endif
-# define machine_is_greenphone()	(machine_arch_type == MACH_TYPE_GREENPHONE)
-#else
-# define machine_is_greenphone()	(0)
-#endif
-
-#ifdef CONFIG_MACH_COMPEXWP18
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_COMPEXWP18
-# endif
-# define machine_is_compex42x()	(machine_arch_type == MACH_TYPE_COMPEXWP18)
-#else
-# define machine_is_compex42x()	(0)
-#endif
-
-#ifdef CONFIG_MACH_XMATE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_XMATE
-# endif
-# define machine_is_xmate()	(machine_arch_type == MACH_TYPE_XMATE)
-#else
-# define machine_is_xmate()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ENERGIZER
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ENERGIZER
-# endif
-# define machine_is_energizer()	(machine_arch_type == MACH_TYPE_ENERGIZER)
-#else
-# define machine_is_energizer()	(0)
-#endif
-
-#ifdef CONFIG_MACH_IME1
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_IME1
-# endif
-# define machine_is_ime1()	(machine_arch_type == MACH_TYPE_IME1)
-#else
-# define machine_is_ime1()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SWEDATMS
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SWEDATMS
-# endif
-# define machine_is_sweda_tms()	(machine_arch_type == MACH_TYPE_SWEDATMS)
-#else
-# define machine_is_sweda_tms()	(0)
-#endif
-
-#ifdef CONFIG_MACH_NTNP435C
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_NTNP435C
-# endif
-# define machine_is_ntnp435c()	(machine_arch_type == MACH_TYPE_NTNP435C)
-#else
-# define machine_is_ntnp435c()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SPECTRO2
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SPECTRO2
-# endif
-# define machine_is_spectro2()	(machine_arch_type == MACH_TYPE_SPECTRO2)
-#else
-# define machine_is_spectro2()	(0)
-#endif
-
-#ifdef CONFIG_MACH_H6039
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_H6039
-# endif
-# define machine_is_h6039()	(machine_arch_type == MACH_TYPE_H6039)
-#else
-# define machine_is_h6039()	(0)
-#endif
-
-#ifdef CONFIG_MACH_EP80219
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_EP80219
-# endif
-# define machine_is_ep80219()	(machine_arch_type == MACH_TYPE_EP80219)
-#else
-# define machine_is_ep80219()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SAMOA_II
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SAMOA_II
-# endif
-# define machine_is_samoa_ii()	(machine_arch_type == MACH_TYPE_SAMOA_II)
-#else
-# define machine_is_samoa_ii()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CWMXL
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CWMXL
-# endif
-# define machine_is_cwmxl()	(machine_arch_type == MACH_TYPE_CWMXL)
-#else
-# define machine_is_cwmxl()	(0)
-#endif
-
-#ifdef CONFIG_MACH_AS9200
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_AS9200
-# endif
-# define machine_is_as9200()	(machine_arch_type == MACH_TYPE_AS9200)
-#else
-# define machine_is_as9200()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SFX1149
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SFX1149
-# endif
-# define machine_is_sfx1149()	(machine_arch_type == MACH_TYPE_SFX1149)
-#else
-# define machine_is_sfx1149()	(0)
-#endif
-
-#ifdef CONFIG_MACH_NAVI010
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_NAVI010
-# endif
-# define machine_is_navi010()	(machine_arch_type == MACH_TYPE_NAVI010)
-#else
-# define machine_is_navi010()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MULTMDP
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MULTMDP
-# endif
-# define machine_is_multmdp()	(machine_arch_type == MACH_TYPE_MULTMDP)
-#else
-# define machine_is_multmdp()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SCB9520
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SCB9520
-# endif
-# define machine_is_scb9520()	(machine_arch_type == MACH_TYPE_SCB9520)
-#else
-# define machine_is_scb9520()	(0)
-#endif
-
-#ifdef CONFIG_MACH_HTCATHENA
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_HTCATHENA
-# endif
-# define machine_is_htcathena()	(machine_arch_type == MACH_TYPE_HTCATHENA)
-#else
-# define machine_is_htcathena()	(0)
-#endif
-
-#ifdef CONFIG_MACH_XP179
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_XP179
-# endif
-# define machine_is_xp179()	(machine_arch_type == MACH_TYPE_XP179)
-#else
-# define machine_is_xp179()	(0)
-#endif
-
-#ifdef CONFIG_MACH_H4300
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_H4300
-# endif
-# define machine_is_h4300()	(machine_arch_type == MACH_TYPE_H4300)
-#else
-# define machine_is_h4300()	(0)
-#endif
-
-#ifdef CONFIG_MACH_GORAMO_MLR
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_GORAMO_MLR
-# endif
-# define machine_is_goramo_mlr()	(machine_arch_type == MACH_TYPE_GORAMO_MLR)
-#else
-# define machine_is_goramo_mlr()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MXC30020EVB
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MXC30020EVB
-# endif
-# define machine_is_mxc30020evb()	(machine_arch_type == MACH_TYPE_MXC30020EVB)
-#else
-# define machine_is_mxc30020evb()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ADSBITSYG5
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ADSBITSYG5
-# endif
-# define machine_is_adsbitsyg5()	(machine_arch_type == MACH_TYPE_ADSBITSYG5)
-#else
-# define machine_is_adsbitsyg5()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ADSPORTALPLUS
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ADSPORTALPLUS
-# endif
-# define machine_is_adsportalplus()	(machine_arch_type == MACH_TYPE_ADSPORTALPLUS)
-#else
-# define machine_is_adsportalplus()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MMSP2PLUS
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MMSP2PLUS
-# endif
-# define machine_is_mmsp2plus()	(machine_arch_type == MACH_TYPE_MMSP2PLUS)
-#else
-# define machine_is_mmsp2plus()	(0)
-#endif
-
-#ifdef CONFIG_MACH_EM_X270
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_EM_X270
-# endif
-# define machine_is_em_x270()	(machine_arch_type == MACH_TYPE_EM_X270)
-#else
-# define machine_is_em_x270()	(0)
-#endif
-
-#ifdef CONFIG_MACH_TPP302
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TPP302
-# endif
-# define machine_is_tpp302()	(machine_arch_type == MACH_TYPE_TPP302)
-#else
-# define machine_is_tpp302()	(0)
-#endif
-
-#ifdef CONFIG_MACH_TPM104
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TPM104
-# endif
-# define machine_is_tpp104()	(machine_arch_type == MACH_TYPE_TPM104)
-#else
-# define machine_is_tpp104()	(0)
-#endif
-
-#ifdef CONFIG_MACH_TPM102
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TPM102
-# endif
-# define machine_is_tpm102()	(machine_arch_type == MACH_TYPE_TPM102)
-#else
-# define machine_is_tpm102()	(0)
-#endif
-
-#ifdef CONFIG_MACH_TPM109
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TPM109
-# endif
-# define machine_is_tpm109()	(machine_arch_type == MACH_TYPE_TPM109)
-#else
-# define machine_is_tpm109()	(0)
-#endif
-
-#ifdef CONFIG_MACH_FBXO1
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_FBXO1
-# endif
-# define machine_is_fbxo1()	(machine_arch_type == MACH_TYPE_FBXO1)
-#else
-# define machine_is_fbxo1()	(0)
-#endif
-
-#ifdef CONFIG_MACH_HXD8
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_HXD8
-# endif
-# define machine_is_hxd8()	(machine_arch_type == MACH_TYPE_HXD8)
-#else
-# define machine_is_hxd8()	(0)
-#endif
-
-#ifdef CONFIG_MACH_NEO1973_GTA02
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_NEO1973_GTA02
-# endif
-# define machine_is_neo1973_gta02()	(machine_arch_type == MACH_TYPE_NEO1973_GTA02)
-#else
-# define machine_is_neo1973_gta02()	(0)
-#endif
-
-#ifdef CONFIG_MACH_EMTEST
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_EMTEST
-# endif
-# define machine_is_emtest()	(machine_arch_type == MACH_TYPE_EMTEST)
-#else
-# define machine_is_emtest()	(0)
-#endif
-
-#ifdef CONFIG_MACH_AD6900
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_AD6900
-# endif
-# define machine_is_ad6900()	(machine_arch_type == MACH_TYPE_AD6900)
-#else
-# define machine_is_ad6900()	(0)
-#endif
-
-#ifdef CONFIG_MACH_EUROPA
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_EUROPA
-# endif
-# define machine_is_europa()	(machine_arch_type == MACH_TYPE_EUROPA)
-#else
-# define machine_is_europa()	(0)
-#endif
-
-#ifdef CONFIG_MACH_METROCONNECT
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_METROCONNECT
-# endif
-# define machine_is_metroconnect()	(machine_arch_type == MACH_TYPE_METROCONNECT)
-#else
-# define machine_is_metroconnect()	(0)
-#endif
-
-#ifdef CONFIG_MACH_EZ_S2410
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_EZ_S2410
-# endif
-# define machine_is_ez_s2410()	(machine_arch_type == MACH_TYPE_EZ_S2410)
-#else
-# define machine_is_ez_s2410()	(0)
-#endif
-
-#ifdef CONFIG_MACH_EZ_S2440
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_EZ_S2440
-# endif
-# define machine_is_ez_s2440()	(machine_arch_type == MACH_TYPE_EZ_S2440)
-#else
-# define machine_is_ez_s2440()	(0)
-#endif
-
-#ifdef CONFIG_MACH_EZ_EP9312
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_EZ_EP9312
-# endif
-# define machine_is_ez_ep9312()	(machine_arch_type == MACH_TYPE_EZ_EP9312)
-#else
-# define machine_is_ez_ep9312()	(0)
-#endif
-
-#ifdef CONFIG_MACH_EZ_EP9315
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_EZ_EP9315
-# endif
-# define machine_is_ez_ep9315()	(machine_arch_type == MACH_TYPE_EZ_EP9315)
-#else
-# define machine_is_ez_ep9315()	(0)
-#endif
-
-#ifdef CONFIG_MACH_EZ_X7
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_EZ_X7
-# endif
-# define machine_is_ez_x7()	(machine_arch_type == MACH_TYPE_EZ_X7)
-#else
-# define machine_is_ez_x7()	(0)
-#endif
-
-#ifdef CONFIG_MACH_GODOTDB
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_GODOTDB
-# endif
-# define machine_is_godotdb()	(machine_arch_type == MACH_TYPE_GODOTDB)
-#else
-# define machine_is_godotdb()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MISTRAL
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MISTRAL
-# endif
-# define machine_is_mistral()	(machine_arch_type == MACH_TYPE_MISTRAL)
-#else
-# define machine_is_mistral()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MSM
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MSM
-# endif
-# define machine_is_msm()	(machine_arch_type == MACH_TYPE_MSM)
-#else
-# define machine_is_msm()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CT5910
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CT5910
-# endif
-# define machine_is_ct5910()	(machine_arch_type == MACH_TYPE_CT5910)
-#else
-# define machine_is_ct5910()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CT5912
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CT5912
-# endif
-# define machine_is_ct5912()	(machine_arch_type == MACH_TYPE_CT5912)
-#else
-# define machine_is_ct5912()	(0)
-#endif
-
-#ifdef CONFIG_MACH_HYNET_INE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_HYNET_INE
-# endif
-# define machine_is_hynet_ine()	(machine_arch_type == MACH_TYPE_HYNET_INE)
-#else
-# define machine_is_hynet_ine()	(0)
-#endif
-
-#ifdef CONFIG_MACH_HYNET_APP
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_HYNET_APP
-# endif
-# define machine_is_hynet_app()	(machine_arch_type == MACH_TYPE_HYNET_APP)
-#else
-# define machine_is_hynet_app()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MSM7200
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MSM7200
-# endif
-# define machine_is_msm7200()	(machine_arch_type == MACH_TYPE_MSM7200)
-#else
-# define machine_is_msm7200()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MSM7600
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MSM7600
-# endif
-# define machine_is_msm7600()	(machine_arch_type == MACH_TYPE_MSM7600)
-#else
-# define machine_is_msm7600()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CEB255
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CEB255
-# endif
-# define machine_is_ceb255()	(machine_arch_type == MACH_TYPE_CEB255)
-#else
-# define machine_is_ceb255()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CIEL
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CIEL
-# endif
-# define machine_is_ciel()	(machine_arch_type == MACH_TYPE_CIEL)
-#else
-# define machine_is_ciel()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SLM5650
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SLM5650
-# endif
-# define machine_is_slm5650()	(machine_arch_type == MACH_TYPE_SLM5650)
-#else
-# define machine_is_slm5650()	(0)
-#endif
-
-#ifdef CONFIG_MACH_AT91SAM9RLEK
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_AT91SAM9RLEK
-# endif
-# define machine_is_at91sam9rlek()	(machine_arch_type == MACH_TYPE_AT91SAM9RLEK)
-#else
-# define machine_is_at91sam9rlek()	(0)
-#endif
-
-#ifdef CONFIG_MACH_COMTECH_ROUTER
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_COMTECH_ROUTER
-# endif
-# define machine_is_comtech_router()	(machine_arch_type == MACH_TYPE_COMTECH_ROUTER)
-#else
-# define machine_is_comtech_router()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SBC2410X
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SBC2410X
-# endif
-# define machine_is_sbc2410x()	(machine_arch_type == MACH_TYPE_SBC2410X)
-#else
-# define machine_is_sbc2410x()	(0)
-#endif
-
-#ifdef CONFIG_MACH_AT4X0BD
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_AT4X0BD
-# endif
-# define machine_is_at4x0bd()	(machine_arch_type == MACH_TYPE_AT4X0BD)
-#else
-# define machine_is_at4x0bd()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CBIFR
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CBIFR
-# endif
-# define machine_is_cbifr()	(machine_arch_type == MACH_TYPE_CBIFR)
-#else
-# define machine_is_cbifr()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ARCOM_QUANTUM
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ARCOM_QUANTUM
-# endif
-# define machine_is_arcom_quantum()	(machine_arch_type == MACH_TYPE_ARCOM_QUANTUM)
-#else
-# define machine_is_arcom_quantum()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MATRIX520
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MATRIX520
-# endif
-# define machine_is_matrix520()	(machine_arch_type == MACH_TYPE_MATRIX520)
-#else
-# define machine_is_matrix520()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MATRIX510
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MATRIX510
-# endif
-# define machine_is_matrix510()	(machine_arch_type == MACH_TYPE_MATRIX510)
-#else
-# define machine_is_matrix510()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MATRIX500
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MATRIX500
-# endif
-# define machine_is_matrix500()	(machine_arch_type == MACH_TYPE_MATRIX500)
-#else
-# define machine_is_matrix500()	(0)
-#endif
-
-#ifdef CONFIG_MACH_M501
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_M501
-# endif
-# define machine_is_m501()	(machine_arch_type == MACH_TYPE_M501)
-#else
-# define machine_is_m501()	(0)
-#endif
-
-#ifdef CONFIG_MACH_AAEON1270
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_AAEON1270
-# endif
-# define machine_is_aaeon1270()	(machine_arch_type == MACH_TYPE_AAEON1270)
-#else
-# define machine_is_aaeon1270()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MATRIX500EV
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MATRIX500EV
-# endif
-# define machine_is_matrix500ev()	(machine_arch_type == MACH_TYPE_MATRIX500EV)
-#else
-# define machine_is_matrix500ev()	(0)
-#endif
-
-#ifdef CONFIG_MACH_PAC500
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PAC500
-# endif
-# define machine_is_pac500()	(machine_arch_type == MACH_TYPE_PAC500)
-#else
-# define machine_is_pac500()	(0)
-#endif
-
-#ifdef CONFIG_MACH_PNX8181
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PNX8181
-# endif
-# define machine_is_pnx8181()	(machine_arch_type == MACH_TYPE_PNX8181)
-#else
-# define machine_is_pnx8181()	(0)
-#endif
-
-#ifdef CONFIG_MACH_COLIBRI320
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_COLIBRI320
-# endif
-# define machine_is_colibri320()	(machine_arch_type == MACH_TYPE_COLIBRI320)
-#else
-# define machine_is_colibri320()	(0)
-#endif
-
-#ifdef CONFIG_MACH_AZTOOLBB
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_AZTOOLBB
-# endif
-# define machine_is_aztoolbb()	(machine_arch_type == MACH_TYPE_AZTOOLBB)
-#else
-# define machine_is_aztoolbb()	(0)
-#endif
-
-#ifdef CONFIG_MACH_AZTOOLG2
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_AZTOOLG2
-# endif
-# define machine_is_aztoolg2()	(machine_arch_type == MACH_TYPE_AZTOOLG2)
-#else
-# define machine_is_aztoolg2()	(0)
-#endif
-
-#ifdef CONFIG_MACH_DVLHOST
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_DVLHOST
-# endif
-# define machine_is_dvlhost()	(machine_arch_type == MACH_TYPE_DVLHOST)
-#else
-# define machine_is_dvlhost()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ZIR9200
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ZIR9200
-# endif
-# define machine_is_zir9200()	(machine_arch_type == MACH_TYPE_ZIR9200)
-#else
-# define machine_is_zir9200()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ZIR9260
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ZIR9260
-# endif
-# define machine_is_zir9260()	(machine_arch_type == MACH_TYPE_ZIR9260)
-#else
-# define machine_is_zir9260()	(0)
-#endif
-
-#ifdef CONFIG_MACH_COCOPAH
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_COCOPAH
-# endif
-# define machine_is_cocopah()	(machine_arch_type == MACH_TYPE_COCOPAH)
-#else
-# define machine_is_cocopah()	(0)
-#endif
-
-#ifdef CONFIG_MACH_NDS
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_NDS
-# endif
-# define machine_is_nds()	(machine_arch_type == MACH_TYPE_NDS)
-#else
-# define machine_is_nds()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ROSENCRANTZ
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ROSENCRANTZ
-# endif
-# define machine_is_rosencrantz()	(machine_arch_type == MACH_TYPE_ROSENCRANTZ)
-#else
-# define machine_is_rosencrantz()	(0)
-#endif
-
-#ifdef CONFIG_MACH_FTTX_ODSC
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_FTTX_ODSC
-# endif
-# define machine_is_fttx_odsc()	(machine_arch_type == MACH_TYPE_FTTX_ODSC)
-#else
-# define machine_is_fttx_odsc()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CLASSE_R6904
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CLASSE_R6904
-# endif
-# define machine_is_classe_r6904()	(machine_arch_type == MACH_TYPE_CLASSE_R6904)
-#else
-# define machine_is_classe_r6904()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CAM60
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CAM60
-# endif
-# define machine_is_cam60()	(machine_arch_type == MACH_TYPE_CAM60)
-#else
-# define machine_is_cam60()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MXC30031ADS
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MXC30031ADS
-# endif
-# define machine_is_mxc30031ads()	(machine_arch_type == MACH_TYPE_MXC30031ADS)
-#else
-# define machine_is_mxc30031ads()	(0)
-#endif
-
-#ifdef CONFIG_MACH_DATACALL
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_DATACALL
-# endif
-# define machine_is_datacall()	(machine_arch_type == MACH_TYPE_DATACALL)
-#else
-# define machine_is_datacall()	(0)
-#endif
-
-#ifdef CONFIG_MACH_AT91EB01
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_AT91EB01
-# endif
-# define machine_is_at91eb01()	(machine_arch_type == MACH_TYPE_AT91EB01)
-#else
-# define machine_is_at91eb01()	(0)
-#endif
-
-#ifdef CONFIG_MACH_RTY
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_RTY
-# endif
-# define machine_is_rty()	(machine_arch_type == MACH_TYPE_RTY)
-#else
-# define machine_is_rty()	(0)
-#endif
-
-#ifdef CONFIG_MACH_DWL2100
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_DWL2100
-# endif
-# define machine_is_dwl2100()	(machine_arch_type == MACH_TYPE_DWL2100)
-#else
-# define machine_is_dwl2100()	(0)
-#endif
-
-#ifdef CONFIG_MACH_VINSI
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_VINSI
-# endif
-# define machine_is_vinsi()	(machine_arch_type == MACH_TYPE_VINSI)
-#else
-# define machine_is_vinsi()	(0)
-#endif
-
-#ifdef CONFIG_MACH_DB88F5281
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_DB88F5281
-# endif
-# define machine_is_db88f5281()	(machine_arch_type == MACH_TYPE_DB88F5281)
-#else
-# define machine_is_db88f5281()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CSB726
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CSB726
-# endif
-# define machine_is_csb726()	(machine_arch_type == MACH_TYPE_CSB726)
-#else
-# define machine_is_csb726()	(0)
-#endif
-
-#ifdef CONFIG_MACH_TIK27
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TIK27
-# endif
-# define machine_is_tik27()	(machine_arch_type == MACH_TYPE_TIK27)
-#else
-# define machine_is_tik27()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MX_UC7420
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MX_UC7420
-# endif
-# define machine_is_mx_uc7420()	(machine_arch_type == MACH_TYPE_MX_UC7420)
-#else
-# define machine_is_mx_uc7420()	(0)
-#endif
-
-#ifdef CONFIG_MACH_RIRM3
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_RIRM3
-# endif
-# define machine_is_rirm3()	(machine_arch_type == MACH_TYPE_RIRM3)
-#else
-# define machine_is_rirm3()	(0)
-#endif
-
-#ifdef CONFIG_MACH_PELCO_ODYSSEY
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PELCO_ODYSSEY
-# endif
-# define machine_is_pelco_odyssey()	(machine_arch_type == MACH_TYPE_PELCO_ODYSSEY)
-#else
-# define machine_is_pelco_odyssey()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ADX_ABOX
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ADX_ABOX
-# endif
-# define machine_is_adx_abox()	(machine_arch_type == MACH_TYPE_ADX_ABOX)
-#else
-# define machine_is_adx_abox()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ADX_TPID
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ADX_TPID
-# endif
-# define machine_is_adx_tpid()	(machine_arch_type == MACH_TYPE_ADX_TPID)
-#else
-# define machine_is_adx_tpid()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MINICHECK
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MINICHECK
-# endif
-# define machine_is_minicheck()	(machine_arch_type == MACH_TYPE_MINICHECK)
-#else
-# define machine_is_minicheck()	(0)
-#endif
-
-#ifdef CONFIG_MACH_IDAM
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_IDAM
-# endif
-# define machine_is_idam()	(machine_arch_type == MACH_TYPE_IDAM)
-#else
-# define machine_is_idam()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MARIO_MX
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MARIO_MX
-# endif
-# define machine_is_mario_mx()	(machine_arch_type == MACH_TYPE_MARIO_MX)
-#else
-# define machine_is_mario_mx()	(0)
-#endif
-
-#ifdef CONFIG_MACH_VI1888
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_VI1888
-# endif
-# define machine_is_vi1888()	(machine_arch_type == MACH_TYPE_VI1888)
-#else
-# define machine_is_vi1888()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ZR4230
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ZR4230
-# endif
-# define machine_is_zr4230()	(machine_arch_type == MACH_TYPE_ZR4230)
-#else
-# define machine_is_zr4230()	(0)
-#endif
-
-#ifdef CONFIG_MACH_T1_IX_BLUE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_T1_IX_BLUE
-# endif
-# define machine_is_t1_ix_blue()	(machine_arch_type == MACH_TYPE_T1_IX_BLUE)
-#else
-# define machine_is_t1_ix_blue()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SYHQ2
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SYHQ2
-# endif
-# define machine_is_syhq2()	(machine_arch_type == MACH_TYPE_SYHQ2)
-#else
-# define machine_is_syhq2()	(0)
-#endif
-
-#ifdef CONFIG_MACH_COMPUTIME_R3
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_COMPUTIME_R3
-# endif
-# define machine_is_computime_r3()	(machine_arch_type == MACH_TYPE_COMPUTIME_R3)
-#else
-# define machine_is_computime_r3()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ORATIS
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ORATIS
-# endif
-# define machine_is_oratis()	(machine_arch_type == MACH_TYPE_ORATIS)
-#else
-# define machine_is_oratis()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MIKKO
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MIKKO
-# endif
-# define machine_is_mikko()	(machine_arch_type == MACH_TYPE_MIKKO)
-#else
-# define machine_is_mikko()	(0)
-#endif
-
-#ifdef CONFIG_MACH_HOLON
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_HOLON
-# endif
-# define machine_is_holon()	(machine_arch_type == MACH_TYPE_HOLON)
-#else
-# define machine_is_holon()	(0)
-#endif
-
-#ifdef CONFIG_MACH_OLIP8
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_OLIP8
-# endif
-# define machine_is_olip8()	(machine_arch_type == MACH_TYPE_OLIP8)
-#else
-# define machine_is_olip8()	(0)
-#endif
-
-#ifdef CONFIG_MACH_GHI270HG
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_GHI270HG
-# endif
-# define machine_is_ghi270hg()	(machine_arch_type == MACH_TYPE_GHI270HG)
-#else
-# define machine_is_ghi270hg()	(0)
-#endif
-
-#ifdef CONFIG_MACH_DAVINCI_DM6467_EVM
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_DAVINCI_DM6467_EVM
-# endif
-# define machine_is_davinci_dm6467_evm()	(machine_arch_type == MACH_TYPE_DAVINCI_DM6467_EVM)
-#else
-# define machine_is_davinci_dm6467_evm()	(0)
-#endif
-
-#ifdef CONFIG_MACH_DAVINCI_DM355_EVM
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_DAVINCI_DM355_EVM
-# endif
-# define machine_is_davinci_dm355_evm()	(machine_arch_type == MACH_TYPE_DAVINCI_DM355_EVM)
-#else
-# define machine_is_davinci_dm355_evm()	(0)
-#endif
-
-#ifdef CONFIG_MACH_BLACKRIVER
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_BLACKRIVER
-# endif
-# define machine_is_blackriver()	(machine_arch_type == MACH_TYPE_BLACKRIVER)
-#else
-# define machine_is_blackriver()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SANDGATEWP
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SANDGATEWP
-# endif
-# define machine_is_sandgate_wp()	(machine_arch_type == MACH_TYPE_SANDGATEWP)
-#else
-# define machine_is_sandgate_wp()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CDOTBWSG
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CDOTBWSG
-# endif
-# define machine_is_cdotbwsg()	(machine_arch_type == MACH_TYPE_CDOTBWSG)
-#else
-# define machine_is_cdotbwsg()	(0)
-#endif
-
-#ifdef CONFIG_MACH_QUARK963
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_QUARK963
-# endif
-# define machine_is_quark963()	(machine_arch_type == MACH_TYPE_QUARK963)
-#else
-# define machine_is_quark963()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CSB735
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CSB735
-# endif
-# define machine_is_csb735()	(machine_arch_type == MACH_TYPE_CSB735)
-#else
-# define machine_is_csb735()	(0)
-#endif
-
-#ifdef CONFIG_MACH_LITTLETON
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_LITTLETON
-# endif
-# define machine_is_littleton()	(machine_arch_type == MACH_TYPE_LITTLETON)
-#else
-# define machine_is_littleton()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MIO_P550
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MIO_P550
-# endif
-# define machine_is_mio_p550()	(machine_arch_type == MACH_TYPE_MIO_P550)
-#else
-# define machine_is_mio_p550()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MOTION2440
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MOTION2440
-# endif
-# define machine_is_motion2440()	(machine_arch_type == MACH_TYPE_MOTION2440)
-#else
-# define machine_is_motion2440()	(0)
-#endif
-
-#ifdef CONFIG_MACH_IMM500
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_IMM500
-# endif
-# define machine_is_imm500()	(machine_arch_type == MACH_TYPE_IMM500)
-#else
-# define machine_is_imm500()	(0)
-#endif
-
-#ifdef CONFIG_MACH_HOMEMATIC
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_HOMEMATIC
-# endif
-# define machine_is_homematic()	(machine_arch_type == MACH_TYPE_HOMEMATIC)
-#else
-# define machine_is_homematic()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ERMINE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ERMINE
-# endif
-# define machine_is_ermine()	(machine_arch_type == MACH_TYPE_ERMINE)
-#else
-# define machine_is_ermine()	(0)
-#endif
-
-#ifdef CONFIG_MACH_KB9202B
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_KB9202B
-# endif
-# define machine_is_kb9202b()	(machine_arch_type == MACH_TYPE_KB9202B)
-#else
-# define machine_is_kb9202b()	(0)
-#endif
-
-#ifdef CONFIG_MACH_HS1XX
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_HS1XX
-# endif
-# define machine_is_hs1xx()	(machine_arch_type == MACH_TYPE_HS1XX)
-#else
-# define machine_is_hs1xx()	(0)
-#endif
-
-#ifdef CONFIG_MACH_STUDENTMATE2440
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_STUDENTMATE2440
-# endif
-# define machine_is_studentmate2440()	(machine_arch_type == MACH_TYPE_STUDENTMATE2440)
-#else
-# define machine_is_studentmate2440()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ARVOO_L1_Z1
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ARVOO_L1_Z1
-# endif
-# define machine_is_arvoo_l1_z1()	(machine_arch_type == MACH_TYPE_ARVOO_L1_Z1)
-#else
-# define machine_is_arvoo_l1_z1()	(0)
-#endif
-
-#ifdef CONFIG_MACH_DEP2410K
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_DEP2410K
-# endif
-# define machine_is_dep2410k()	(machine_arch_type == MACH_TYPE_DEP2410K)
-#else
-# define machine_is_dep2410k()	(0)
-#endif
-
-#ifdef CONFIG_MACH_XXSVIDEO
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_XXSVIDEO
-# endif
-# define machine_is_xxsvideo()	(machine_arch_type == MACH_TYPE_XXSVIDEO)
-#else
-# define machine_is_xxsvideo()	(0)
-#endif
-
-#ifdef CONFIG_MACH_IM4004
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_IM4004
-# endif
-# define machine_is_im4004()	(machine_arch_type == MACH_TYPE_IM4004)
-#else
-# define machine_is_im4004()	(0)
-#endif
-
-#ifdef CONFIG_MACH_OCHAYA1050
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_OCHAYA1050
-# endif
-# define machine_is_ochaya1050()	(machine_arch_type == MACH_TYPE_OCHAYA1050)
-#else
-# define machine_is_ochaya1050()	(0)
-#endif
-
-#ifdef CONFIG_MACH_LEP9261
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_LEP9261
-# endif
-# define machine_is_lep9261()	(machine_arch_type == MACH_TYPE_LEP9261)
-#else
-# define machine_is_lep9261()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SVENMEB
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SVENMEB
-# endif
-# define machine_is_svenmeb()	(machine_arch_type == MACH_TYPE_SVENMEB)
-#else
-# define machine_is_svenmeb()	(0)
-#endif
-
-#ifdef CONFIG_MACH_FORTUNET2NE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_FORTUNET2NE
-# endif
-# define machine_is_fortunet2ne()	(machine_arch_type == MACH_TYPE_FORTUNET2NE)
-#else
-# define machine_is_fortunet2ne()	(0)
-#endif
-
-#ifdef CONFIG_MACH_NXHX
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_NXHX
-# endif
-# define machine_is_nxhx()	(machine_arch_type == MACH_TYPE_NXHX)
-#else
-# define machine_is_nxhx()	(0)
-#endif
-
-#ifdef CONFIG_MACH_REALVIEW_PB11MP
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_REALVIEW_PB11MP
-# endif
-# define machine_is_realview_pb11mp()	(machine_arch_type == MACH_TYPE_REALVIEW_PB11MP)
-#else
-# define machine_is_realview_pb11mp()	(0)
-#endif
-
-#ifdef CONFIG_MACH_IDS500
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_IDS500
-# endif
-# define machine_is_ids500()	(machine_arch_type == MACH_TYPE_IDS500)
-#else
-# define machine_is_ids500()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ORS_N725
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ORS_N725
-# endif
-# define machine_is_ors_n725()	(machine_arch_type == MACH_TYPE_ORS_N725)
-#else
-# define machine_is_ors_n725()	(0)
-#endif
-
-#ifdef CONFIG_MACH_HSDARM
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_HSDARM
-# endif
-# define machine_is_hsdarm()	(machine_arch_type == MACH_TYPE_HSDARM)
-#else
-# define machine_is_hsdarm()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SHA_PON003
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SHA_PON003
-# endif
-# define machine_is_sha_pon003()	(machine_arch_type == MACH_TYPE_SHA_PON003)
-#else
-# define machine_is_sha_pon003()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SHA_PON004
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SHA_PON004
-# endif
-# define machine_is_sha_pon004()	(machine_arch_type == MACH_TYPE_SHA_PON004)
-#else
-# define machine_is_sha_pon004()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SHA_PON007
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SHA_PON007
-# endif
-# define machine_is_sha_pon007()	(machine_arch_type == MACH_TYPE_SHA_PON007)
-#else
-# define machine_is_sha_pon007()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SHA_PON011
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SHA_PON011
-# endif
-# define machine_is_sha_pon011()	(machine_arch_type == MACH_TYPE_SHA_PON011)
-#else
-# define machine_is_sha_pon011()	(0)
-#endif
-
-#ifdef CONFIG_MACH_H6042
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_H6042
-# endif
-# define machine_is_h6042()	(machine_arch_type == MACH_TYPE_H6042)
-#else
-# define machine_is_h6042()	(0)
-#endif
-
-#ifdef CONFIG_MACH_H6043
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_H6043
-# endif
-# define machine_is_h6043()	(machine_arch_type == MACH_TYPE_H6043)
-#else
-# define machine_is_h6043()	(0)
-#endif
-
-#ifdef CONFIG_MACH_LOOXC550
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_LOOXC550
-# endif
-# define machine_is_looxc550()	(machine_arch_type == MACH_TYPE_LOOXC550)
-#else
-# define machine_is_looxc550()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CNTY_TITAN
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CNTY_TITAN
-# endif
-# define machine_is_cnty_titan()	(machine_arch_type == MACH_TYPE_CNTY_TITAN)
-#else
-# define machine_is_cnty_titan()	(0)
-#endif
-
-#ifdef CONFIG_MACH_APP3XX
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_APP3XX
-# endif
-# define machine_is_app3xx()	(machine_arch_type == MACH_TYPE_APP3XX)
-#else
-# define machine_is_app3xx()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SIDEOATSGRAMA
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SIDEOATSGRAMA
-# endif
-# define machine_is_sideoatsgrama()	(machine_arch_type == MACH_TYPE_SIDEOATSGRAMA)
-#else
-# define machine_is_sideoatsgrama()	(0)
-#endif
-
-#ifdef CONFIG_MACH_TREO700P
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TREO700P
-# endif
-# define machine_is_treo700p()	(machine_arch_type == MACH_TYPE_TREO700P)
-#else
-# define machine_is_treo700p()	(0)
-#endif
-
-#ifdef CONFIG_MACH_TREO700W
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TREO700W
-# endif
-# define machine_is_treo700w()	(machine_arch_type == MACH_TYPE_TREO700W)
-#else
-# define machine_is_treo700w()	(0)
-#endif
-
-#ifdef CONFIG_MACH_TREO750
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TREO750
-# endif
-# define machine_is_treo750()	(machine_arch_type == MACH_TYPE_TREO750)
-#else
-# define machine_is_treo750()	(0)
-#endif
-
-#ifdef CONFIG_MACH_TREO755P
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TREO755P
-# endif
-# define machine_is_treo755p()	(machine_arch_type == MACH_TYPE_TREO755P)
-#else
-# define machine_is_treo755p()	(0)
-#endif
-
-#ifdef CONFIG_MACH_EZREGANUT9200
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_EZREGANUT9200
-# endif
-# define machine_is_ezreganut9200()	(machine_arch_type == MACH_TYPE_EZREGANUT9200)
-#else
-# define machine_is_ezreganut9200()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SARGE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SARGE
-# endif
-# define machine_is_sarge()	(machine_arch_type == MACH_TYPE_SARGE)
-#else
-# define machine_is_sarge()	(0)
-#endif
-
-#ifdef CONFIG_MACH_A696
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_A696
-# endif
-# define machine_is_a696()	(machine_arch_type == MACH_TYPE_A696)
-#else
-# define machine_is_a696()	(0)
-#endif
-
-#ifdef CONFIG_MACH_TURTLE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TURTLE
-# endif
-# define machine_is_turtle1916()	(machine_arch_type == MACH_TYPE_TURTLE)
-#else
-# define machine_is_turtle1916()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MX27_3DS
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MX27_3DS
-# endif
-# define machine_is_mx27_3ds()	(machine_arch_type == MACH_TYPE_MX27_3DS)
-#else
-# define machine_is_mx27_3ds()	(0)
-#endif
-
-#ifdef CONFIG_MACH_BISHOP
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_BISHOP
-# endif
-# define machine_is_bishop()	(machine_arch_type == MACH_TYPE_BISHOP)
-#else
-# define machine_is_bishop()	(0)
-#endif
-
-#ifdef CONFIG_MACH_PXX
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PXX
-# endif
-# define machine_is_pxx()	(machine_arch_type == MACH_TYPE_PXX)
-#else
-# define machine_is_pxx()	(0)
-#endif
-
-#ifdef CONFIG_MACH_REDWOOD
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_REDWOOD
-# endif
-# define machine_is_redwood()	(machine_arch_type == MACH_TYPE_REDWOOD)
-#else
-# define machine_is_redwood()	(0)
-#endif
-
-#ifdef CONFIG_MACH_OMAP_2430DLP
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_OMAP_2430DLP
-# endif
-# define machine_is_omap_2430dlp()	(machine_arch_type == MACH_TYPE_OMAP_2430DLP)
-#else
-# define machine_is_omap_2430dlp()	(0)
-#endif
-
-#ifdef CONFIG_MACH_OMAP_2430OSK
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_OMAP_2430OSK
-# endif
-# define machine_is_omap_2430osk()	(machine_arch_type == MACH_TYPE_OMAP_2430OSK)
-#else
-# define machine_is_omap_2430osk()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SARDINE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SARDINE
-# endif
-# define machine_is_sardine()	(machine_arch_type == MACH_TYPE_SARDINE)
-#else
-# define machine_is_sardine()	(0)
-#endif
-
-#ifdef CONFIG_MACH_HALIBUT
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_HALIBUT
-# endif
-# define machine_is_halibut()	(machine_arch_type == MACH_TYPE_HALIBUT)
-#else
-# define machine_is_halibut()	(0)
-#endif
-
-#ifdef CONFIG_MACH_TROUT
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TROUT
-# endif
-# define machine_is_trout()	(machine_arch_type == MACH_TYPE_TROUT)
-#else
-# define machine_is_trout()	(0)
-#endif
-
-#ifdef CONFIG_MACH_GOLDFISH
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_GOLDFISH
-# endif
-# define machine_is_goldfish()	(machine_arch_type == MACH_TYPE_GOLDFISH)
-#else
-# define machine_is_goldfish()	(0)
-#endif
-
-#ifdef CONFIG_MACH_GESBC2440
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_GESBC2440
-# endif
-# define machine_is_gesbc2440()	(machine_arch_type == MACH_TYPE_GESBC2440)
-#else
-# define machine_is_gesbc2440()	(0)
-#endif
-
-#ifdef CONFIG_MACH_NOMAD
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_NOMAD
-# endif
-# define machine_is_nomad()	(machine_arch_type == MACH_TYPE_NOMAD)
-#else
-# define machine_is_nomad()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ROSALIND
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ROSALIND
-# endif
-# define machine_is_rosalind()	(machine_arch_type == MACH_TYPE_ROSALIND)
-#else
-# define machine_is_rosalind()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CC9P9215
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CC9P9215
-# endif
-# define machine_is_cc9p9215()	(machine_arch_type == MACH_TYPE_CC9P9215)
-#else
-# define machine_is_cc9p9215()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CC9P9210
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CC9P9210
-# endif
-# define machine_is_cc9p9210()	(machine_arch_type == MACH_TYPE_CC9P9210)
-#else
-# define machine_is_cc9p9210()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CC9P9215JS
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CC9P9215JS
-# endif
-# define machine_is_cc9p9215js()	(machine_arch_type == MACH_TYPE_CC9P9215JS)
-#else
-# define machine_is_cc9p9215js()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CC9P9210JS
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CC9P9210JS
-# endif
-# define machine_is_cc9p9210js()	(machine_arch_type == MACH_TYPE_CC9P9210JS)
-#else
-# define machine_is_cc9p9210js()	(0)
-#endif
-
-#ifdef CONFIG_MACH_NASFFE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_NASFFE
-# endif
-# define machine_is_nasffe()	(machine_arch_type == MACH_TYPE_NASFFE)
-#else
-# define machine_is_nasffe()	(0)
-#endif
-
-#ifdef CONFIG_MACH_TN2X0BD
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TN2X0BD
-# endif
-# define machine_is_tn2x0bd()	(machine_arch_type == MACH_TYPE_TN2X0BD)
-#else
-# define machine_is_tn2x0bd()	(0)
-#endif
-
-#ifdef CONFIG_MACH_GWMPXA
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_GWMPXA
-# endif
-# define machine_is_gwmpxa()	(machine_arch_type == MACH_TYPE_GWMPXA)
-#else
-# define machine_is_gwmpxa()	(0)
-#endif
-
-#ifdef CONFIG_MACH_EXYPLUS
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_EXYPLUS
-# endif
-# define machine_is_exyplus()	(machine_arch_type == MACH_TYPE_EXYPLUS)
-#else
-# define machine_is_exyplus()	(0)
-#endif
-
-#ifdef CONFIG_MACH_JADOO21
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_JADOO21
-# endif
-# define machine_is_jadoo21()	(machine_arch_type == MACH_TYPE_JADOO21)
-#else
-# define machine_is_jadoo21()	(0)
-#endif
-
-#ifdef CONFIG_MACH_LOOXN560
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_LOOXN560
-# endif
-# define machine_is_looxn560()	(machine_arch_type == MACH_TYPE_LOOXN560)
-#else
-# define machine_is_looxn560()	(0)
-#endif
-
-#ifdef CONFIG_MACH_BONSAI
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_BONSAI
-# endif
-# define machine_is_bonsai()	(machine_arch_type == MACH_TYPE_BONSAI)
-#else
-# define machine_is_bonsai()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ADSMILGATO
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ADSMILGATO
-# endif
-# define machine_is_adsmilgato()	(machine_arch_type == MACH_TYPE_ADSMILGATO)
-#else
-# define machine_is_adsmilgato()	(0)
-#endif
-
-#ifdef CONFIG_MACH_GBA
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_GBA
-# endif
-# define machine_is_gba()	(machine_arch_type == MACH_TYPE_GBA)
-#else
-# define machine_is_gba()	(0)
-#endif
-
-#ifdef CONFIG_MACH_H6044
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_H6044
-# endif
-# define machine_is_h6044()	(machine_arch_type == MACH_TYPE_H6044)
-#else
-# define machine_is_h6044()	(0)
-#endif
-
-#ifdef CONFIG_MACH_APP
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_APP
-# endif
-# define machine_is_app()	(machine_arch_type == MACH_TYPE_APP)
-#else
-# define machine_is_app()	(0)
-#endif
-
-#ifdef CONFIG_MACH_TCT_HAMMER
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TCT_HAMMER
-# endif
-# define machine_is_tct_hammer()	(machine_arch_type == MACH_TYPE_TCT_HAMMER)
-#else
-# define machine_is_tct_hammer()	(0)
-#endif
-
-#ifdef CONFIG_MACH_HERALD
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_HERALD
-# endif
-# define machine_is_herald()	(machine_arch_type == MACH_TYPE_HERALD)
-#else
-# define machine_is_herald()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ARTEMIS
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ARTEMIS
-# endif
-# define machine_is_artemis()	(machine_arch_type == MACH_TYPE_ARTEMIS)
-#else
-# define machine_is_artemis()	(0)
-#endif
-
-#ifdef CONFIG_MACH_HTCTITAN
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_HTCTITAN
-# endif
-# define machine_is_htctitan()	(machine_arch_type == MACH_TYPE_HTCTITAN)
-#else
-# define machine_is_htctitan()	(0)
-#endif
-
-#ifdef CONFIG_MACH_QRANIUM
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_QRANIUM
-# endif
-# define machine_is_qranium()	(machine_arch_type == MACH_TYPE_QRANIUM)
-#else
-# define machine_is_qranium()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ADX_WSC2
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ADX_WSC2
-# endif
-# define machine_is_adx_wsc2()	(machine_arch_type == MACH_TYPE_ADX_WSC2)
-#else
-# define machine_is_adx_wsc2()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ADX_MEDCOM
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ADX_MEDCOM
-# endif
-# define machine_is_adx_medcom()	(machine_arch_type == MACH_TYPE_ADX_MEDCOM)
-#else
-# define machine_is_adx_medcom()	(0)
-#endif
-
-#ifdef CONFIG_MACH_BBOARD
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_BBOARD
-# endif
-# define machine_is_bboard()	(machine_arch_type == MACH_TYPE_BBOARD)
-#else
-# define machine_is_bboard()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CAMBRIA
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CAMBRIA
-# endif
-# define machine_is_cambria()	(machine_arch_type == MACH_TYPE_CAMBRIA)
-#else
-# define machine_is_cambria()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MT7XXX
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MT7XXX
-# endif
-# define machine_is_mt7xxx()	(machine_arch_type == MACH_TYPE_MT7XXX)
-#else
-# define machine_is_mt7xxx()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MATRIX512
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MATRIX512
-# endif
-# define machine_is_matrix512()	(machine_arch_type == MACH_TYPE_MATRIX512)
-#else
-# define machine_is_matrix512()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MATRIX522
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MATRIX522
-# endif
-# define machine_is_matrix522()	(machine_arch_type == MACH_TYPE_MATRIX522)
-#else
-# define machine_is_matrix522()	(0)
-#endif
-
-#ifdef CONFIG_MACH_IPAC5010
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_IPAC5010
-# endif
-# define machine_is_ipac5010()	(machine_arch_type == MACH_TYPE_IPAC5010)
-#else
-# define machine_is_ipac5010()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SAKURA
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SAKURA
-# endif
-# define machine_is_sakura()	(machine_arch_type == MACH_TYPE_SAKURA)
-#else
-# define machine_is_sakura()	(0)
-#endif
-
-#ifdef CONFIG_MACH_GROCX
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_GROCX
-# endif
-# define machine_is_grocx()	(machine_arch_type == MACH_TYPE_GROCX)
-#else
-# define machine_is_grocx()	(0)
-#endif
-
-#ifdef CONFIG_MACH_PM9263
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PM9263
-# endif
-# define machine_is_pm9263()	(machine_arch_type == MACH_TYPE_PM9263)
-#else
-# define machine_is_pm9263()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SIM_ONE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SIM_ONE
-# endif
-# define machine_is_sim_one()	(machine_arch_type == MACH_TYPE_SIM_ONE)
-#else
-# define machine_is_sim_one()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ACQ132
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ACQ132
-# endif
-# define machine_is_acq132()	(machine_arch_type == MACH_TYPE_ACQ132)
-#else
-# define machine_is_acq132()	(0)
-#endif
-
-#ifdef CONFIG_MACH_DATR
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_DATR
-# endif
-# define machine_is_datr()	(machine_arch_type == MACH_TYPE_DATR)
-#else
-# define machine_is_datr()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ACTUX1
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ACTUX1
-# endif
-# define machine_is_actux1()	(machine_arch_type == MACH_TYPE_ACTUX1)
-#else
-# define machine_is_actux1()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ACTUX2
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ACTUX2
-# endif
-# define machine_is_actux2()	(machine_arch_type == MACH_TYPE_ACTUX2)
-#else
-# define machine_is_actux2()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ACTUX3
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ACTUX3
-# endif
-# define machine_is_actux3()	(machine_arch_type == MACH_TYPE_ACTUX3)
-#else
-# define machine_is_actux3()	(0)
-#endif
-
-#ifdef CONFIG_MACH_FLEXIT
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_FLEXIT
-# endif
-# define machine_is_flexit()	(machine_arch_type == MACH_TYPE_FLEXIT)
-#else
-# define machine_is_flexit()	(0)
-#endif
-
-#ifdef CONFIG_MACH_BH2X0BD
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_BH2X0BD
-# endif
-# define machine_is_bh2x0bd()	(machine_arch_type == MACH_TYPE_BH2X0BD)
-#else
-# define machine_is_bh2x0bd()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ATB2002
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ATB2002
-# endif
-# define machine_is_atb2002()	(machine_arch_type == MACH_TYPE_ATB2002)
-#else
-# define machine_is_atb2002()	(0)
-#endif
-
-#ifdef CONFIG_MACH_XENON
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_XENON
-# endif
-# define machine_is_xenon()	(machine_arch_type == MACH_TYPE_XENON)
-#else
-# define machine_is_xenon()	(0)
-#endif
-
-#ifdef CONFIG_MACH_FM607
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_FM607
-# endif
-# define machine_is_fm607()	(machine_arch_type == MACH_TYPE_FM607)
-#else
-# define machine_is_fm607()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MATRIX514
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MATRIX514
-# endif
-# define machine_is_matrix514()	(machine_arch_type == MACH_TYPE_MATRIX514)
-#else
-# define machine_is_matrix514()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MATRIX524
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MATRIX524
-# endif
-# define machine_is_matrix524()	(machine_arch_type == MACH_TYPE_MATRIX524)
-#else
-# define machine_is_matrix524()	(0)
-#endif
-
-#ifdef CONFIG_MACH_INPOD
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_INPOD
-# endif
-# define machine_is_inpod()	(machine_arch_type == MACH_TYPE_INPOD)
-#else
-# define machine_is_inpod()	(0)
-#endif
-
-#ifdef CONFIG_MACH_JIVE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_JIVE
-# endif
-# define machine_is_jive()	(machine_arch_type == MACH_TYPE_JIVE)
-#else
-# define machine_is_jive()	(0)
-#endif
-
-#ifdef CONFIG_MACH_TLL_MX21
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TLL_MX21
-# endif
-# define machine_is_tll_mx21()	(machine_arch_type == MACH_TYPE_TLL_MX21)
-#else
-# define machine_is_tll_mx21()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SBC2800
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SBC2800
-# endif
-# define machine_is_sbc2800()	(machine_arch_type == MACH_TYPE_SBC2800)
-#else
-# define machine_is_sbc2800()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CC7UCAMRY
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CC7UCAMRY
-# endif
-# define machine_is_cc7ucamry()	(machine_arch_type == MACH_TYPE_CC7UCAMRY)
-#else
-# define machine_is_cc7ucamry()	(0)
-#endif
-
-#ifdef CONFIG_MACH_UBISYS_P9_SC15
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_UBISYS_P9_SC15
-# endif
-# define machine_is_ubisys_p9_sc15()	(machine_arch_type == MACH_TYPE_UBISYS_P9_SC15)
-#else
-# define machine_is_ubisys_p9_sc15()	(0)
-#endif
-
-#ifdef CONFIG_MACH_UBISYS_P9_SSC2D10
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_UBISYS_P9_SSC2D10
-# endif
-# define machine_is_ubisys_p9_ssc2d10()	(machine_arch_type == MACH_TYPE_UBISYS_P9_SSC2D10)
-#else
-# define machine_is_ubisys_p9_ssc2d10()	(0)
-#endif
-
-#ifdef CONFIG_MACH_UBISYS_P9_RCU3
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_UBISYS_P9_RCU3
-# endif
-# define machine_is_ubisys_p9_rcu3()	(machine_arch_type == MACH_TYPE_UBISYS_P9_RCU3)
-#else
-# define machine_is_ubisys_p9_rcu3()	(0)
-#endif
-
-#ifdef CONFIG_MACH_AML_M8000
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_AML_M8000
-# endif
-# define machine_is_aml_m8000()	(machine_arch_type == MACH_TYPE_AML_M8000)
-#else
-# define machine_is_aml_m8000()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SNAPPER_270
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SNAPPER_270
-# endif
-# define machine_is_snapper_270()	(machine_arch_type == MACH_TYPE_SNAPPER_270)
-#else
-# define machine_is_snapper_270()	(0)
-#endif
-
-#ifdef CONFIG_MACH_OMAP_BBX
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_OMAP_BBX
-# endif
-# define machine_is_omap_bbx()	(machine_arch_type == MACH_TYPE_OMAP_BBX)
-#else
-# define machine_is_omap_bbx()	(0)
-#endif
-
-#ifdef CONFIG_MACH_UCN2410
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_UCN2410
-# endif
-# define machine_is_ucn2410()	(machine_arch_type == MACH_TYPE_UCN2410)
-#else
-# define machine_is_ucn2410()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SAM9_L9260
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SAM9_L9260
-# endif
-# define machine_is_sam9_l9260()	(machine_arch_type == MACH_TYPE_SAM9_L9260)
-#else
-# define machine_is_sam9_l9260()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ETI_C2
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ETI_C2
-# endif
-# define machine_is_eti_c2()	(machine_arch_type == MACH_TYPE_ETI_C2)
-#else
-# define machine_is_eti_c2()	(0)
-#endif
-
-#ifdef CONFIG_MACH_AVALANCHE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_AVALANCHE
-# endif
-# define machine_is_avalanche()	(machine_arch_type == MACH_TYPE_AVALANCHE)
-#else
-# define machine_is_avalanche()	(0)
-#endif
-
-#ifdef CONFIG_MACH_REALVIEW_PB1176
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_REALVIEW_PB1176
-# endif
-# define machine_is_realview_pb1176()	(machine_arch_type == MACH_TYPE_REALVIEW_PB1176)
-#else
-# define machine_is_realview_pb1176()	(0)
-#endif
-
-#ifdef CONFIG_MACH_DP1500
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_DP1500
-# endif
-# define machine_is_dp1500()	(machine_arch_type == MACH_TYPE_DP1500)
-#else
-# define machine_is_dp1500()	(0)
-#endif
-
-#ifdef CONFIG_MACH_APPLE_IPHONE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_APPLE_IPHONE
-# endif
-# define machine_is_apple_iphone()	(machine_arch_type == MACH_TYPE_APPLE_IPHONE)
-#else
-# define machine_is_apple_iphone()	(0)
-#endif
-
-#ifdef CONFIG_MACH_YL9200
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_YL9200
-# endif
-# define machine_is_yl9200()	(machine_arch_type == MACH_TYPE_YL9200)
-#else
-# define machine_is_yl9200()	(0)
-#endif
-
-#ifdef CONFIG_MACH_RD88F5182
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_RD88F5182
-# endif
-# define machine_is_rd88f5182()	(machine_arch_type == MACH_TYPE_RD88F5182)
-#else
-# define machine_is_rd88f5182()	(0)
-#endif
-
-#ifdef CONFIG_MACH_KUROBOX_PRO
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_KUROBOX_PRO
-# endif
-# define machine_is_kurobox_pro()	(machine_arch_type == MACH_TYPE_KUROBOX_PRO)
-#else
-# define machine_is_kurobox_pro()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SE_POET
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SE_POET
-# endif
-# define machine_is_se_poet()	(machine_arch_type == MACH_TYPE_SE_POET)
-#else
-# define machine_is_se_poet()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MX31_3DS
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MX31_3DS
-# endif
-# define machine_is_mx31_3ds()	(machine_arch_type == MACH_TYPE_MX31_3DS)
-#else
-# define machine_is_mx31_3ds()	(0)
-#endif
-
-#ifdef CONFIG_MACH_R270
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_R270
-# endif
-# define machine_is_r270()	(machine_arch_type == MACH_TYPE_R270)
-#else
-# define machine_is_r270()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ARMOUR21
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ARMOUR21
-# endif
-# define machine_is_armour21()	(machine_arch_type == MACH_TYPE_ARMOUR21)
-#else
-# define machine_is_armour21()	(0)
-#endif
-
-#ifdef CONFIG_MACH_DT2
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_DT2
-# endif
-# define machine_is_dt2()	(machine_arch_type == MACH_TYPE_DT2)
-#else
-# define machine_is_dt2()	(0)
-#endif
-
-#ifdef CONFIG_MACH_VT4
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_VT4
-# endif
-# define machine_is_vt4()	(machine_arch_type == MACH_TYPE_VT4)
-#else
-# define machine_is_vt4()	(0)
-#endif
-
-#ifdef CONFIG_MACH_TYCO320
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TYCO320
-# endif
-# define machine_is_tyco320()	(machine_arch_type == MACH_TYPE_TYCO320)
-#else
-# define machine_is_tyco320()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ADMA
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ADMA
-# endif
-# define machine_is_adma()	(machine_arch_type == MACH_TYPE_ADMA)
-#else
-# define machine_is_adma()	(0)
-#endif
-
-#ifdef CONFIG_MACH_WP188
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_WP188
-# endif
-# define machine_is_wp188()	(machine_arch_type == MACH_TYPE_WP188)
-#else
-# define machine_is_wp188()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CORSICA
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CORSICA
-# endif
-# define machine_is_corsica()	(machine_arch_type == MACH_TYPE_CORSICA)
-#else
-# define machine_is_corsica()	(0)
-#endif
-
-#ifdef CONFIG_MACH_BIGEYE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_BIGEYE
-# endif
-# define machine_is_bigeye()	(machine_arch_type == MACH_TYPE_BIGEYE)
-#else
-# define machine_is_bigeye()	(0)
-#endif
-
-#ifdef CONFIG_MACH_TLL5000
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TLL5000
-# endif
-# define machine_is_tll5000()	(machine_arch_type == MACH_TYPE_TLL5000)
-#else
-# define machine_is_tll5000()	(0)
-#endif
-
-#ifdef CONFIG_MACH_BEBOT
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_BEBOT
-# endif
-# define machine_is_bebot()	(machine_arch_type == MACH_TYPE_BEBOT)
-#else
-# define machine_is_bebot()	(0)
-#endif
-
-#ifdef CONFIG_MACH_QONG
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_QONG
-# endif
-# define machine_is_qong()	(machine_arch_type == MACH_TYPE_QONG)
-#else
-# define machine_is_qong()	(0)
-#endif
-
-#ifdef CONFIG_MACH_TCOMPACT
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TCOMPACT
-# endif
-# define machine_is_tcompact()	(machine_arch_type == MACH_TYPE_TCOMPACT)
-#else
-# define machine_is_tcompact()	(0)
-#endif
-
-#ifdef CONFIG_MACH_PUMA5
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PUMA5
-# endif
-# define machine_is_puma5()	(machine_arch_type == MACH_TYPE_PUMA5)
-#else
-# define machine_is_puma5()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ELARA
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ELARA
-# endif
-# define machine_is_elara()	(machine_arch_type == MACH_TYPE_ELARA)
-#else
-# define machine_is_elara()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ELLINGTON
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ELLINGTON
-# endif
-# define machine_is_ellington()	(machine_arch_type == MACH_TYPE_ELLINGTON)
-#else
-# define machine_is_ellington()	(0)
-#endif
-
-#ifdef CONFIG_MACH_XDA_ATOM
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_XDA_ATOM
-# endif
-# define machine_is_xda_atom()	(machine_arch_type == MACH_TYPE_XDA_ATOM)
-#else
-# define machine_is_xda_atom()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ENERGIZER2
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ENERGIZER2
-# endif
-# define machine_is_energizer2()	(machine_arch_type == MACH_TYPE_ENERGIZER2)
-#else
-# define machine_is_energizer2()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ODIN
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ODIN
-# endif
-# define machine_is_odin()	(machine_arch_type == MACH_TYPE_ODIN)
-#else
-# define machine_is_odin()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ACTUX4
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ACTUX4
-# endif
-# define machine_is_actux4()	(machine_arch_type == MACH_TYPE_ACTUX4)
-#else
-# define machine_is_actux4()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ESL_OMAP
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ESL_OMAP
-# endif
-# define machine_is_esl_omap()	(machine_arch_type == MACH_TYPE_ESL_OMAP)
-#else
-# define machine_is_esl_omap()	(0)
-#endif
-
-#ifdef CONFIG_MACH_OMAP2EVM
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_OMAP2EVM
-# endif
-# define machine_is_omap2evm()	(machine_arch_type == MACH_TYPE_OMAP2EVM)
-#else
-# define machine_is_omap2evm()	(0)
-#endif
-
-#ifdef CONFIG_MACH_OMAP3EVM
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_OMAP3EVM
-# endif
-# define machine_is_omap3evm()	(machine_arch_type == MACH_TYPE_OMAP3EVM)
-#else
-# define machine_is_omap3evm()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ADX_PCU57
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ADX_PCU57
-# endif
-# define machine_is_adx_pcu57()	(machine_arch_type == MACH_TYPE_ADX_PCU57)
-#else
-# define machine_is_adx_pcu57()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MONACO
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MONACO
-# endif
-# define machine_is_monaco()	(machine_arch_type == MACH_TYPE_MONACO)
-#else
-# define machine_is_monaco()	(0)
-#endif
-
-#ifdef CONFIG_MACH_LEVANTE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_LEVANTE
-# endif
-# define machine_is_levante()	(machine_arch_type == MACH_TYPE_LEVANTE)
-#else
-# define machine_is_levante()	(0)
-#endif
-
-#ifdef CONFIG_MACH_TMXIPX425
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TMXIPX425
-# endif
-# define machine_is_tmxipx425()	(machine_arch_type == MACH_TYPE_TMXIPX425)
-#else
-# define machine_is_tmxipx425()	(0)
-#endif
-
-#ifdef CONFIG_MACH_LEEP
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_LEEP
-# endif
-# define machine_is_leep()	(machine_arch_type == MACH_TYPE_LEEP)
-#else
-# define machine_is_leep()	(0)
-#endif
-
-#ifdef CONFIG_MACH_RAAD
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_RAAD
-# endif
-# define machine_is_raad()	(machine_arch_type == MACH_TYPE_RAAD)
-#else
-# define machine_is_raad()	(0)
-#endif
-
-#ifdef CONFIG_MACH_DNS323
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_DNS323
-# endif
-# define machine_is_dns323()	(machine_arch_type == MACH_TYPE_DNS323)
-#else
-# define machine_is_dns323()	(0)
-#endif
-
-#ifdef CONFIG_MACH_AP1000
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_AP1000
-# endif
-# define machine_is_ap1000()	(machine_arch_type == MACH_TYPE_AP1000)
-#else
-# define machine_is_ap1000()	(0)
-#endif
-
-#ifdef CONFIG_MACH_A9SAM6432
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_A9SAM6432
-# endif
-# define machine_is_a9sam6432()	(machine_arch_type == MACH_TYPE_A9SAM6432)
-#else
-# define machine_is_a9sam6432()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SHINY
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SHINY
-# endif
-# define machine_is_shiny()	(machine_arch_type == MACH_TYPE_SHINY)
-#else
-# define machine_is_shiny()	(0)
-#endif
-
-#ifdef CONFIG_MACH_OMAP3_BEAGLE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_OMAP3_BEAGLE
-# endif
-# define machine_is_omap3_beagle()	(machine_arch_type == MACH_TYPE_OMAP3_BEAGLE)
-#else
-# define machine_is_omap3_beagle()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CSR_BDB2
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CSR_BDB2
-# endif
-# define machine_is_csr_bdb2()	(machine_arch_type == MACH_TYPE_CSR_BDB2)
-#else
-# define machine_is_csr_bdb2()	(0)
-#endif
-
-#ifdef CONFIG_MACH_NOKIA_N810
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_NOKIA_N810
-# endif
-# define machine_is_nokia_n810()	(machine_arch_type == MACH_TYPE_NOKIA_N810)
-#else
-# define machine_is_nokia_n810()	(0)
-#endif
-
-#ifdef CONFIG_MACH_C270
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_C270
-# endif
-# define machine_is_c270()	(machine_arch_type == MACH_TYPE_C270)
-#else
-# define machine_is_c270()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SENTRY
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SENTRY
-# endif
-# define machine_is_sentry()	(machine_arch_type == MACH_TYPE_SENTRY)
-#else
-# define machine_is_sentry()	(0)
-#endif
-
-#ifdef CONFIG_MACH_PCM038
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PCM038
-# endif
-# define machine_is_pcm038()	(machine_arch_type == MACH_TYPE_PCM038)
-#else
-# define machine_is_pcm038()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ANC300
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ANC300
-# endif
-# define machine_is_anc300()	(machine_arch_type == MACH_TYPE_ANC300)
-#else
-# define machine_is_anc300()	(0)
-#endif
-
-#ifdef CONFIG_MACH_HTCKAISER
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_HTCKAISER
-# endif
-# define machine_is_htckaiser()	(machine_arch_type == MACH_TYPE_HTCKAISER)
-#else
-# define machine_is_htckaiser()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SBAT100
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SBAT100
-# endif
-# define machine_is_sbat100()	(machine_arch_type == MACH_TYPE_SBAT100)
-#else
-# define machine_is_sbat100()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MODUNORM
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MODUNORM
-# endif
-# define machine_is_modunorm()	(machine_arch_type == MACH_TYPE_MODUNORM)
-#else
-# define machine_is_modunorm()	(0)
-#endif
-
-#ifdef CONFIG_MACH_PELOS_TWARM
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PELOS_TWARM
-# endif
-# define machine_is_pelos_twarm()	(machine_arch_type == MACH_TYPE_PELOS_TWARM)
-#else
-# define machine_is_pelos_twarm()	(0)
-#endif
-
-#ifdef CONFIG_MACH_FLANK
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_FLANK
-# endif
-# define machine_is_flank()	(machine_arch_type == MACH_TYPE_FLANK)
-#else
-# define machine_is_flank()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SIRLOIN
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SIRLOIN
-# endif
-# define machine_is_sirloin()	(machine_arch_type == MACH_TYPE_SIRLOIN)
-#else
-# define machine_is_sirloin()	(0)
-#endif
-
-#ifdef CONFIG_MACH_BRISKET
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_BRISKET
-# endif
-# define machine_is_brisket()	(machine_arch_type == MACH_TYPE_BRISKET)
-#else
-# define machine_is_brisket()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CHUCK
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CHUCK
-# endif
-# define machine_is_chuck()	(machine_arch_type == MACH_TYPE_CHUCK)
-#else
-# define machine_is_chuck()	(0)
-#endif
-
-#ifdef CONFIG_MACH_OTTER
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_OTTER
-# endif
-# define machine_is_otter()	(machine_arch_type == MACH_TYPE_OTTER)
-#else
-# define machine_is_otter()	(0)
-#endif
-
-#ifdef CONFIG_MACH_DAVINCI_LDK
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_DAVINCI_LDK
-# endif
-# define machine_is_davinci_ldk()	(machine_arch_type == MACH_TYPE_DAVINCI_LDK)
-#else
-# define machine_is_davinci_ldk()	(0)
-#endif
-
-#ifdef CONFIG_MACH_PHREEDOM
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PHREEDOM
-# endif
-# define machine_is_phreedom()	(machine_arch_type == MACH_TYPE_PHREEDOM)
-#else
-# define machine_is_phreedom()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SG310
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SG310
-# endif
-# define machine_is_sg310()	(machine_arch_type == MACH_TYPE_SG310)
-#else
-# define machine_is_sg310()	(0)
-#endif
-
-#ifdef CONFIG_MACH_TS209
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TS209
-# endif
-# define machine_is_ts_x09()	(machine_arch_type == MACH_TYPE_TS209)
-#else
-# define machine_is_ts_x09()	(0)
-#endif
-
-#ifdef CONFIG_MACH_AT91CAP9ADK
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_AT91CAP9ADK
-# endif
-# define machine_is_at91cap9adk()	(machine_arch_type == MACH_TYPE_AT91CAP9ADK)
-#else
-# define machine_is_at91cap9adk()	(0)
-#endif
-
-#ifdef CONFIG_MACH_TION9315
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TION9315
-# endif
-# define machine_is_tion9315()	(machine_arch_type == MACH_TYPE_TION9315)
-#else
-# define machine_is_tion9315()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MAST
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MAST
-# endif
-# define machine_is_mast()	(machine_arch_type == MACH_TYPE_MAST)
-#else
-# define machine_is_mast()	(0)
-#endif
-
-#ifdef CONFIG_MACH_PFW
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PFW
-# endif
-# define machine_is_pfw()	(machine_arch_type == MACH_TYPE_PFW)
-#else
-# define machine_is_pfw()	(0)
-#endif
-
-#ifdef CONFIG_MACH_YL_P2440
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_YL_P2440
-# endif
-# define machine_is_yl_p2440()	(machine_arch_type == MACH_TYPE_YL_P2440)
-#else
-# define machine_is_yl_p2440()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ZSBC32
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ZSBC32
-# endif
-# define machine_is_zsbc32()	(machine_arch_type == MACH_TYPE_ZSBC32)
-#else
-# define machine_is_zsbc32()	(0)
-#endif
-
-#ifdef CONFIG_MACH_OMAP_PACE2
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_OMAP_PACE2
-# endif
-# define machine_is_omap_pace2()	(machine_arch_type == MACH_TYPE_OMAP_PACE2)
-#else
-# define machine_is_omap_pace2()	(0)
-#endif
-
-#ifdef CONFIG_MACH_IMX_PACE2
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_IMX_PACE2
-# endif
-# define machine_is_imx_pace2()	(machine_arch_type == MACH_TYPE_IMX_PACE2)
-#else
-# define machine_is_imx_pace2()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MX31MOBOARD
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MX31MOBOARD
-# endif
-# define machine_is_mx31moboard()	(machine_arch_type == MACH_TYPE_MX31MOBOARD)
-#else
-# define machine_is_mx31moboard()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MX37_3DS
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MX37_3DS
-# endif
-# define machine_is_mx37_3ds()	(machine_arch_type == MACH_TYPE_MX37_3DS)
-#else
-# define machine_is_mx37_3ds()	(0)
-#endif
-
-#ifdef CONFIG_MACH_RCC
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_RCC
-# endif
-# define machine_is_rcc()	(machine_arch_type == MACH_TYPE_RCC)
-#else
-# define machine_is_rcc()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ARM9
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ARM9
-# endif
-# define machine_is_dmp()	(machine_arch_type == MACH_TYPE_ARM9)
-#else
-# define machine_is_dmp()	(0)
-#endif
-
-#ifdef CONFIG_MACH_VISION_EP9307
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_VISION_EP9307
-# endif
-# define machine_is_vision_ep9307()	(machine_arch_type == MACH_TYPE_VISION_EP9307)
-#else
-# define machine_is_vision_ep9307()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SCLY1000
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SCLY1000
-# endif
-# define machine_is_scly1000()	(machine_arch_type == MACH_TYPE_SCLY1000)
-#else
-# define machine_is_scly1000()	(0)
-#endif
-
-#ifdef CONFIG_MACH_FONTEL_EP
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_FONTEL_EP
-# endif
-# define machine_is_fontel_ep()	(machine_arch_type == MACH_TYPE_FONTEL_EP)
-#else
-# define machine_is_fontel_ep()	(0)
-#endif
-
-#ifdef CONFIG_MACH_VOICEBLUE3G
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_VOICEBLUE3G
-# endif
-# define machine_is_voiceblue3g()	(machine_arch_type == MACH_TYPE_VOICEBLUE3G)
-#else
-# define machine_is_voiceblue3g()	(0)
-#endif
-
-#ifdef CONFIG_MACH_TT9200
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TT9200
-# endif
-# define machine_is_tt9200()	(machine_arch_type == MACH_TYPE_TT9200)
-#else
-# define machine_is_tt9200()	(0)
-#endif
-
-#ifdef CONFIG_MACH_DIGI2410
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_DIGI2410
-# endif
-# define machine_is_digi2410()	(machine_arch_type == MACH_TYPE_DIGI2410)
-#else
-# define machine_is_digi2410()	(0)
-#endif
-
-#ifdef CONFIG_MACH_TERASTATION_PRO2
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TERASTATION_PRO2
-# endif
-# define machine_is_terastation_pro2()	(machine_arch_type == MACH_TYPE_TERASTATION_PRO2)
-#else
-# define machine_is_terastation_pro2()	(0)
-#endif
-
-#ifdef CONFIG_MACH_LINKSTATION_PRO
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_LINKSTATION_PRO
-# endif
-# define machine_is_linkstation_pro()	(machine_arch_type == MACH_TYPE_LINKSTATION_PRO)
-#else
-# define machine_is_linkstation_pro()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MOTOROLA_A780
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MOTOROLA_A780
-# endif
-# define machine_is_motorola_a780()	(machine_arch_type == MACH_TYPE_MOTOROLA_A780)
-#else
-# define machine_is_motorola_a780()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MOTOROLA_E6
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MOTOROLA_E6
-# endif
-# define machine_is_motorola_e6()	(machine_arch_type == MACH_TYPE_MOTOROLA_E6)
-#else
-# define machine_is_motorola_e6()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MOTOROLA_E2
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MOTOROLA_E2
-# endif
-# define machine_is_motorola_e2()	(machine_arch_type == MACH_TYPE_MOTOROLA_E2)
-#else
-# define machine_is_motorola_e2()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MOTOROLA_E680
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MOTOROLA_E680
-# endif
-# define machine_is_motorola_e680()	(machine_arch_type == MACH_TYPE_MOTOROLA_E680)
-#else
-# define machine_is_motorola_e680()	(0)
-#endif
-
-#ifdef CONFIG_MACH_UR2410
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_UR2410
-# endif
-# define machine_is_ur2410()	(machine_arch_type == MACH_TYPE_UR2410)
-#else
-# define machine_is_ur2410()	(0)
-#endif
-
-#ifdef CONFIG_MACH_TAS9261
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TAS9261
-# endif
-# define machine_is_tas9261()	(machine_arch_type == MACH_TYPE_TAS9261)
-#else
-# define machine_is_tas9261()	(0)
-#endif
-
-#ifdef CONFIG_MACH_HERMES_HD
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_HERMES_HD
-# endif
-# define machine_is_davinci_hermes_hd()	(machine_arch_type == MACH_TYPE_HERMES_HD)
-#else
-# define machine_is_davinci_hermes_hd()	(0)
-#endif
-
-#ifdef CONFIG_MACH_PERSEO_HD
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PERSEO_HD
-# endif
-# define machine_is_davinci_perseo_hd()	(machine_arch_type == MACH_TYPE_PERSEO_HD)
-#else
-# define machine_is_davinci_perseo_hd()	(0)
-#endif
-
-#ifdef CONFIG_MACH_STARGAZER2
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_STARGAZER2
-# endif
-# define machine_is_stargazer2()	(machine_arch_type == MACH_TYPE_STARGAZER2)
-#else
-# define machine_is_stargazer2()	(0)
-#endif
-
-#ifdef CONFIG_MACH_E350
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_E350
-# endif
-# define machine_is_e350()	(machine_arch_type == MACH_TYPE_E350)
-#else
-# define machine_is_e350()	(0)
-#endif
-
-#ifdef CONFIG_MACH_WPCM450
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_WPCM450
-# endif
-# define machine_is_wpcm450()	(machine_arch_type == MACH_TYPE_WPCM450)
-#else
-# define machine_is_wpcm450()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CARTESIO
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CARTESIO
-# endif
-# define machine_is_cartesio()	(machine_arch_type == MACH_TYPE_CARTESIO)
-#else
-# define machine_is_cartesio()	(0)
-#endif
-
-#ifdef CONFIG_MACH_TOYBOX
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TOYBOX
-# endif
-# define machine_is_toybox()	(machine_arch_type == MACH_TYPE_TOYBOX)
-#else
-# define machine_is_toybox()	(0)
-#endif
-
-#ifdef CONFIG_MACH_TX27
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TX27
-# endif
-# define machine_is_tx27()	(machine_arch_type == MACH_TYPE_TX27)
-#else
-# define machine_is_tx27()	(0)
-#endif
-
-#ifdef CONFIG_MACH_TS409
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TS409
-# endif
-# define machine_is_ts409()	(machine_arch_type == MACH_TYPE_TS409)
-#else
-# define machine_is_ts409()	(0)
-#endif
-
-#ifdef CONFIG_MACH_P300
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_P300
-# endif
-# define machine_is_p300()	(machine_arch_type == MACH_TYPE_P300)
-#else
-# define machine_is_p300()	(0)
-#endif
-
-#ifdef CONFIG_MACH_XDACOMET
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_XDACOMET
-# endif
-# define machine_is_xdacomet()	(machine_arch_type == MACH_TYPE_XDACOMET)
-#else
-# define machine_is_xdacomet()	(0)
-#endif
-
-#ifdef CONFIG_MACH_DEXFLEX2
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_DEXFLEX2
-# endif
-# define machine_is_dexflex2()	(machine_arch_type == MACH_TYPE_DEXFLEX2)
-#else
-# define machine_is_dexflex2()	(0)
-#endif
-
-#ifdef CONFIG_MACH_OW
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_OW
-# endif
-# define machine_is_ow()	(machine_arch_type == MACH_TYPE_OW)
-#else
-# define machine_is_ow()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ARMEBS3
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ARMEBS3
-# endif
-# define machine_is_armebs3()	(machine_arch_type == MACH_TYPE_ARMEBS3)
-#else
-# define machine_is_armebs3()	(0)
-#endif
-
-#ifdef CONFIG_MACH_U3
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_U3
-# endif
-# define machine_is_u3()	(machine_arch_type == MACH_TYPE_U3)
-#else
-# define machine_is_u3()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SMDK2450
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SMDK2450
-# endif
-# define machine_is_smdk2450()	(machine_arch_type == MACH_TYPE_SMDK2450)
-#else
-# define machine_is_smdk2450()	(0)
-#endif
-
-#ifdef CONFIG_MACH_RSI_EWS
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_RSI_EWS
-# endif
-# define machine_is_rsi_ews()	(machine_arch_type == MACH_TYPE_RSI_EWS)
-#else
-# define machine_is_rsi_ews()	(0)
-#endif
-
-#ifdef CONFIG_MACH_TNB
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TNB
-# endif
-# define machine_is_tnb()	(machine_arch_type == MACH_TYPE_TNB)
-#else
-# define machine_is_tnb()	(0)
-#endif
-
-#ifdef CONFIG_MACH_TOEPATH
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TOEPATH
-# endif
-# define machine_is_toepath()	(machine_arch_type == MACH_TYPE_TOEPATH)
-#else
-# define machine_is_toepath()	(0)
-#endif
-
-#ifdef CONFIG_MACH_KB9263
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_KB9263
-# endif
-# define machine_is_kb9263()	(machine_arch_type == MACH_TYPE_KB9263)
-#else
-# define machine_is_kb9263()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MT7108
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MT7108
-# endif
-# define machine_is_mt7108()	(machine_arch_type == MACH_TYPE_MT7108)
-#else
-# define machine_is_mt7108()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SMTR2440
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SMTR2440
-# endif
-# define machine_is_smtr2440()	(machine_arch_type == MACH_TYPE_SMTR2440)
-#else
-# define machine_is_smtr2440()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MANAO
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MANAO
-# endif
-# define machine_is_manao()	(machine_arch_type == MACH_TYPE_MANAO)
-#else
-# define machine_is_manao()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CM_X300
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CM_X300
-# endif
-# define machine_is_cm_x300()	(machine_arch_type == MACH_TYPE_CM_X300)
-#else
-# define machine_is_cm_x300()	(0)
-#endif
-
-#ifdef CONFIG_MACH_GULFSTREAM_KP
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_GULFSTREAM_KP
-# endif
-# define machine_is_gulfstream_kp()	(machine_arch_type == MACH_TYPE_GULFSTREAM_KP)
-#else
-# define machine_is_gulfstream_kp()	(0)
-#endif
-
-#ifdef CONFIG_MACH_LANREADYFN522
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_LANREADYFN522
-# endif
-# define machine_is_lanreadyfn522()	(machine_arch_type == MACH_TYPE_LANREADYFN522)
-#else
-# define machine_is_lanreadyfn522()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ARMA37
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ARMA37
-# endif
-# define machine_is_arma37()	(machine_arch_type == MACH_TYPE_ARMA37)
-#else
-# define machine_is_arma37()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MENDEL
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MENDEL
-# endif
-# define machine_is_mendel()	(machine_arch_type == MACH_TYPE_MENDEL)
-#else
-# define machine_is_mendel()	(0)
-#endif
-
-#ifdef CONFIG_MACH_PELCO_ILIAD
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PELCO_ILIAD
-# endif
-# define machine_is_pelco_iliad()	(machine_arch_type == MACH_TYPE_PELCO_ILIAD)
-#else
-# define machine_is_pelco_iliad()	(0)
-#endif
-
-#ifdef CONFIG_MACH_UNIT2P
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_UNIT2P
-# endif
-# define machine_is_unit2p()	(machine_arch_type == MACH_TYPE_UNIT2P)
-#else
-# define machine_is_unit2p()	(0)
-#endif
-
-#ifdef CONFIG_MACH_INC20OTTER
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_INC20OTTER
-# endif
-# define machine_is_inc20otter()	(machine_arch_type == MACH_TYPE_INC20OTTER)
-#else
-# define machine_is_inc20otter()	(0)
-#endif
-
-#ifdef CONFIG_MACH_AT91SAM9G20EK
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_AT91SAM9G20EK
-# endif
-# define machine_is_at91sam9g20ek()	(machine_arch_type == MACH_TYPE_AT91SAM9G20EK)
-#else
-# define machine_is_at91sam9g20ek()	(0)
-#endif
-
-#ifdef CONFIG_MACH_STORCENTER
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_STORCENTER
-# endif
-# define machine_is_sc_ge2()	(machine_arch_type == MACH_TYPE_STORCENTER)
-#else
-# define machine_is_sc_ge2()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SMDK6410
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SMDK6410
-# endif
-# define machine_is_smdk6410()	(machine_arch_type == MACH_TYPE_SMDK6410)
-#else
-# define machine_is_smdk6410()	(0)
-#endif
-
-#ifdef CONFIG_MACH_U300
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_U300
-# endif
-# define machine_is_u300()	(machine_arch_type == MACH_TYPE_U300)
-#else
-# define machine_is_u300()	(0)
-#endif
-
-#ifdef CONFIG_MACH_U500
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_U500
-# endif
-# define machine_is_u500()	(machine_arch_type == MACH_TYPE_U500)
-#else
-# define machine_is_u500()	(0)
-#endif
-
-#ifdef CONFIG_MACH_DS9260
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_DS9260
-# endif
-# define machine_is_ds9260()	(machine_arch_type == MACH_TYPE_DS9260)
-#else
-# define machine_is_ds9260()	(0)
-#endif
-
-#ifdef CONFIG_MACH_RIVERROCK
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_RIVERROCK
-# endif
-# define machine_is_riverrock()	(machine_arch_type == MACH_TYPE_RIVERROCK)
-#else
-# define machine_is_riverrock()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SCIBATH
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SCIBATH
-# endif
-# define machine_is_scibath()	(machine_arch_type == MACH_TYPE_SCIBATH)
-#else
-# define machine_is_scibath()	(0)
-#endif
-
-#ifdef CONFIG_MACH_AT91SAM7SE512EK
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_AT91SAM7SE512EK
-# endif
-# define machine_is_at91sam7se()	(machine_arch_type == MACH_TYPE_AT91SAM7SE512EK)
-#else
-# define machine_is_at91sam7se()	(0)
-#endif
-
-#ifdef CONFIG_MACH_WRT350N_V2
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_WRT350N_V2
-# endif
-# define machine_is_wrt350n_v2()	(machine_arch_type == MACH_TYPE_WRT350N_V2)
-#else
-# define machine_is_wrt350n_v2()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MULTIMEDIA
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MULTIMEDIA
-# endif
-# define machine_is_multimedia()	(machine_arch_type == MACH_TYPE_MULTIMEDIA)
-#else
-# define machine_is_multimedia()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MARVIN
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MARVIN
-# endif
-# define machine_is_marvin()	(machine_arch_type == MACH_TYPE_MARVIN)
-#else
-# define machine_is_marvin()	(0)
-#endif
-
-#ifdef CONFIG_MACH_X500
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_X500
-# endif
-# define machine_is_x500()	(machine_arch_type == MACH_TYPE_X500)
-#else
-# define machine_is_x500()	(0)
-#endif
-
-#ifdef CONFIG_MACH_AWLUG4LCU
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_AWLUG4LCU
-# endif
-# define machine_is_awlug4lcu()	(machine_arch_type == MACH_TYPE_AWLUG4LCU)
-#else
-# define machine_is_awlug4lcu()	(0)
-#endif
-
-#ifdef CONFIG_MACH_PALERMOC
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PALERMOC
-# endif
-# define machine_is_palermoc()	(machine_arch_type == MACH_TYPE_PALERMOC)
-#else
-# define machine_is_palermoc()	(0)
-#endif
-
-#ifdef CONFIG_MACH_OMAP_LDP
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_OMAP_LDP
-# endif
-# define machine_is_omap_ldp()	(machine_arch_type == MACH_TYPE_OMAP_LDP)
-#else
-# define machine_is_omap_ldp()	(0)
-#endif
-
-#ifdef CONFIG_MACH_IP500
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_IP500
-# endif
-# define machine_is_ip500()	(machine_arch_type == MACH_TYPE_IP500)
-#else
-# define machine_is_ip500()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ASE2
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ASE2
-# endif
-# define machine_is_ase2()	(machine_arch_type == MACH_TYPE_ASE2)
-#else
-# define machine_is_ase2()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MX35EVB
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MX35EVB
-# endif
-# define machine_is_mx35evb()	(machine_arch_type == MACH_TYPE_MX35EVB)
-#else
-# define machine_is_mx35evb()	(0)
-#endif
-
-#ifdef CONFIG_MACH_AML_M8050
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_AML_M8050
-# endif
-# define machine_is_aml_m8050()	(machine_arch_type == MACH_TYPE_AML_M8050)
-#else
-# define machine_is_aml_m8050()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MX35_3DS
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MX35_3DS
-# endif
-# define machine_is_mx35_3ds()	(machine_arch_type == MACH_TYPE_MX35_3DS)
-#else
-# define machine_is_mx35_3ds()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MARS
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MARS
-# endif
-# define machine_is_mars()	(machine_arch_type == MACH_TYPE_MARS)
-#else
-# define machine_is_mars()	(0)
-#endif
-
-#ifdef CONFIG_MACH_NEUROS_OSD2
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_NEUROS_OSD2
-# endif
-# define machine_is_neuros_osd2()	(machine_arch_type == MACH_TYPE_NEUROS_OSD2)
-#else
-# define machine_is_neuros_osd2()	(0)
-#endif
-
-#ifdef CONFIG_MACH_BADGER
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_BADGER
-# endif
-# define machine_is_badger()	(machine_arch_type == MACH_TYPE_BADGER)
-#else
-# define machine_is_badger()	(0)
-#endif
-
-#ifdef CONFIG_MACH_TRIZEPS4WL
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TRIZEPS4WL
-# endif
-# define machine_is_trizeps4wl()	(machine_arch_type == MACH_TYPE_TRIZEPS4WL)
-#else
-# define machine_is_trizeps4wl()	(0)
-#endif
-
-#ifdef CONFIG_MACH_TRIZEPS5
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TRIZEPS5
-# endif
-# define machine_is_trizeps5()	(machine_arch_type == MACH_TYPE_TRIZEPS5)
-#else
-# define machine_is_trizeps5()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MARLIN
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MARLIN
-# endif
-# define machine_is_marlin()	(machine_arch_type == MACH_TYPE_MARLIN)
-#else
-# define machine_is_marlin()	(0)
-#endif
-
-#ifdef CONFIG_MACH_TS78XX
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TS78XX
-# endif
-# define machine_is_ts78xx()	(machine_arch_type == MACH_TYPE_TS78XX)
-#else
-# define machine_is_ts78xx()	(0)
-#endif
-
-#ifdef CONFIG_MACH_HPIPAQ214
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_HPIPAQ214
-# endif
-# define machine_is_hpipaq214()	(machine_arch_type == MACH_TYPE_HPIPAQ214)
-#else
-# define machine_is_hpipaq214()	(0)
-#endif
-
-#ifdef CONFIG_MACH_AT572D940DCM
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_AT572D940DCM
-# endif
-# define machine_is_at572d940dcm()	(machine_arch_type == MACH_TYPE_AT572D940DCM)
-#else
-# define machine_is_at572d940dcm()	(0)
-#endif
-
-#ifdef CONFIG_MACH_NE1BOARD
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_NE1BOARD
-# endif
-# define machine_is_ne1board()	(machine_arch_type == MACH_TYPE_NE1BOARD)
-#else
-# define machine_is_ne1board()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ZANTE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ZANTE
-# endif
-# define machine_is_zante()	(machine_arch_type == MACH_TYPE_ZANTE)
-#else
-# define machine_is_zante()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SFFSDR
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SFFSDR
-# endif
-# define machine_is_sffsdr()	(machine_arch_type == MACH_TYPE_SFFSDR)
-#else
-# define machine_is_sffsdr()	(0)
-#endif
-
-#ifdef CONFIG_MACH_TW2662
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TW2662
-# endif
-# define machine_is_tw2662()	(machine_arch_type == MACH_TYPE_TW2662)
-#else
-# define machine_is_tw2662()	(0)
-#endif
-
-#ifdef CONFIG_MACH_VF10XX
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_VF10XX
-# endif
-# define machine_is_vf10xx()	(machine_arch_type == MACH_TYPE_VF10XX)
-#else
-# define machine_is_vf10xx()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ZORAN43XX
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ZORAN43XX
-# endif
-# define machine_is_zoran43xx()	(machine_arch_type == MACH_TYPE_ZORAN43XX)
-#else
-# define machine_is_zoran43xx()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SONIX926
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SONIX926
-# endif
-# define machine_is_sonix926()	(machine_arch_type == MACH_TYPE_SONIX926)
-#else
-# define machine_is_sonix926()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CELESTIALSEMI
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CELESTIALSEMI
-# endif
-# define machine_is_celestialsemi()	(machine_arch_type == MACH_TYPE_CELESTIALSEMI)
-#else
-# define machine_is_celestialsemi()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CC9M2443JS
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CC9M2443JS
-# endif
-# define machine_is_cc9m2443js()	(machine_arch_type == MACH_TYPE_CC9M2443JS)
-#else
-# define machine_is_cc9m2443js()	(0)
-#endif
-
-#ifdef CONFIG_MACH_TW5334
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TW5334
-# endif
-# define machine_is_tw5334()	(machine_arch_type == MACH_TYPE_TW5334)
-#else
-# define machine_is_tw5334()	(0)
-#endif
-
-#ifdef CONFIG_MACH_HTCARTEMIS
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_HTCARTEMIS
-# endif
-# define machine_is_omap_htcartemis()	(machine_arch_type == MACH_TYPE_HTCARTEMIS)
-#else
-# define machine_is_omap_htcartemis()	(0)
-#endif
-
-#ifdef CONFIG_MACH_NAL_HLITE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_NAL_HLITE
-# endif
-# define machine_is_nal_hlite()	(machine_arch_type == MACH_TYPE_NAL_HLITE)
-#else
-# define machine_is_nal_hlite()	(0)
-#endif
-
-#ifdef CONFIG_MACH_HTCVOGUE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_HTCVOGUE
-# endif
-# define machine_is_htcvogue()	(machine_arch_type == MACH_TYPE_HTCVOGUE)
-#else
-# define machine_is_htcvogue()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SMARTWEB
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SMARTWEB
-# endif
-# define machine_is_smartweb()	(machine_arch_type == MACH_TYPE_SMARTWEB)
-#else
-# define machine_is_smartweb()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MV86XX
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MV86XX
-# endif
-# define machine_is_mv86xx()	(machine_arch_type == MACH_TYPE_MV86XX)
-#else
-# define machine_is_mv86xx()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MV87XX
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MV87XX
-# endif
-# define machine_is_mv87xx()	(machine_arch_type == MACH_TYPE_MV87XX)
-#else
-# define machine_is_mv87xx()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SONGYOUNGHO
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SONGYOUNGHO
-# endif
-# define machine_is_songyoungho()	(machine_arch_type == MACH_TYPE_SONGYOUNGHO)
-#else
-# define machine_is_songyoungho()	(0)
-#endif
-
-#ifdef CONFIG_MACH_YOUNGHOTEMA
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_YOUNGHOTEMA
-# endif
-# define machine_is_younghotema()	(machine_arch_type == MACH_TYPE_YOUNGHOTEMA)
-#else
-# define machine_is_younghotema()	(0)
-#endif
-
-#ifdef CONFIG_MACH_PCM037
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PCM037
-# endif
-# define machine_is_pcm037()	(machine_arch_type == MACH_TYPE_PCM037)
-#else
-# define machine_is_pcm037()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MMVP
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MMVP
-# endif
-# define machine_is_mmvp()	(machine_arch_type == MACH_TYPE_MMVP)
-#else
-# define machine_is_mmvp()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MMAP
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MMAP
-# endif
-# define machine_is_mmap()	(machine_arch_type == MACH_TYPE_MMAP)
-#else
-# define machine_is_mmap()	(0)
-#endif
-
-#ifdef CONFIG_MACH_PTID2410
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PTID2410
-# endif
-# define machine_is_ptid2410()	(machine_arch_type == MACH_TYPE_PTID2410)
-#else
-# define machine_is_ptid2410()	(0)
-#endif
-
-#ifdef CONFIG_MACH_JAMES_926
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_JAMES_926
-# endif
-# define machine_is_james_926()	(machine_arch_type == MACH_TYPE_JAMES_926)
-#else
-# define machine_is_james_926()	(0)
-#endif
-
-#ifdef CONFIG_MACH_FM6000
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_FM6000
-# endif
-# define machine_is_fm6000()	(machine_arch_type == MACH_TYPE_FM6000)
-#else
-# define machine_is_fm6000()	(0)
-#endif
-
-#ifdef CONFIG_MACH_DB88F6281_BP
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_DB88F6281_BP
-# endif
-# define machine_is_db88f6281_bp()	(machine_arch_type == MACH_TYPE_DB88F6281_BP)
-#else
-# define machine_is_db88f6281_bp()	(0)
-#endif
-
-#ifdef CONFIG_MACH_RD88F6192_NAS
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_RD88F6192_NAS
-# endif
-# define machine_is_rd88f6192_nas()	(machine_arch_type == MACH_TYPE_RD88F6192_NAS)
-#else
-# define machine_is_rd88f6192_nas()	(0)
-#endif
-
-#ifdef CONFIG_MACH_RD88F6281
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_RD88F6281
-# endif
-# define machine_is_rd88f6281()	(machine_arch_type == MACH_TYPE_RD88F6281)
-#else
-# define machine_is_rd88f6281()	(0)
-#endif
-
-#ifdef CONFIG_MACH_DB78X00_BP
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_DB78X00_BP
-# endif
-# define machine_is_db78x00_bp()	(machine_arch_type == MACH_TYPE_DB78X00_BP)
-#else
-# define machine_is_db78x00_bp()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SMDK2416
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SMDK2416
-# endif
-# define machine_is_smdk2416()	(machine_arch_type == MACH_TYPE_SMDK2416)
-#else
-# define machine_is_smdk2416()	(0)
-#endif
-
-#ifdef CONFIG_MACH_OCE_SPIDER_SI
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_OCE_SPIDER_SI
-# endif
-# define machine_is_oce_spider_si()	(machine_arch_type == MACH_TYPE_OCE_SPIDER_SI)
-#else
-# define machine_is_oce_spider_si()	(0)
-#endif
-
-#ifdef CONFIG_MACH_OCE_SPIDER_SK
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_OCE_SPIDER_SK
-# endif
-# define machine_is_oce_spider_sk()	(machine_arch_type == MACH_TYPE_OCE_SPIDER_SK)
-#else
-# define machine_is_oce_spider_sk()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ROVERN6
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ROVERN6
-# endif
-# define machine_is_rovern6()	(machine_arch_type == MACH_TYPE_ROVERN6)
-#else
-# define machine_is_rovern6()	(0)
-#endif
-
-#ifdef CONFIG_MACH_PELCO_EVOLUTION
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PELCO_EVOLUTION
-# endif
-# define machine_is_pelco_evolution()	(machine_arch_type == MACH_TYPE_PELCO_EVOLUTION)
-#else
-# define machine_is_pelco_evolution()	(0)
-#endif
-
-#ifdef CONFIG_MACH_WBD111
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_WBD111
-# endif
-# define machine_is_wbd111()	(machine_arch_type == MACH_TYPE_WBD111)
-#else
-# define machine_is_wbd111()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ELARACPE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ELARACPE
-# endif
-# define machine_is_elaracpe()	(machine_arch_type == MACH_TYPE_ELARACPE)
-#else
-# define machine_is_elaracpe()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MABV3
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MABV3
-# endif
-# define machine_is_mabv3()	(machine_arch_type == MACH_TYPE_MABV3)
-#else
-# define machine_is_mabv3()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MV2120
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MV2120
-# endif
-# define machine_is_mv2120()	(machine_arch_type == MACH_TYPE_MV2120)
-#else
-# define machine_is_mv2120()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CSB737
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CSB737
-# endif
-# define machine_is_csb737()	(machine_arch_type == MACH_TYPE_CSB737)
-#else
-# define machine_is_csb737()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MX51_3DS
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MX51_3DS
-# endif
-# define machine_is_mx51_3ds()	(machine_arch_type == MACH_TYPE_MX51_3DS)
-#else
-# define machine_is_mx51_3ds()	(0)
-#endif
-
-#ifdef CONFIG_MACH_G900
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_G900
-# endif
-# define machine_is_g900()	(machine_arch_type == MACH_TYPE_G900)
-#else
-# define machine_is_g900()	(0)
-#endif
-
-#ifdef CONFIG_MACH_APF27
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_APF27
-# endif
-# define machine_is_apf27()	(machine_arch_type == MACH_TYPE_APF27)
-#else
-# define machine_is_apf27()	(0)
-#endif
-
-#ifdef CONFIG_MACH_GGUS2000
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_GGUS2000
-# endif
-# define machine_is_ggus2000()	(machine_arch_type == MACH_TYPE_GGUS2000)
-#else
-# define machine_is_ggus2000()	(0)
-#endif
-
-#ifdef CONFIG_MACH_OMAP_2430_MIMIC
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_OMAP_2430_MIMIC
-# endif
-# define machine_is_omap_2430_mimic()	(machine_arch_type == MACH_TYPE_OMAP_2430_MIMIC)
-#else
-# define machine_is_omap_2430_mimic()	(0)
-#endif
-
-#ifdef CONFIG_MACH_IMX27LITE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_IMX27LITE
-# endif
-# define machine_is_imx27lite()	(machine_arch_type == MACH_TYPE_IMX27LITE)
-#else
-# define machine_is_imx27lite()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ALMEX
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ALMEX
-# endif
-# define machine_is_almex()	(machine_arch_type == MACH_TYPE_ALMEX)
-#else
-# define machine_is_almex()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CONTROL
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CONTROL
-# endif
-# define machine_is_control()	(machine_arch_type == MACH_TYPE_CONTROL)
-#else
-# define machine_is_control()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MBA2410
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MBA2410
-# endif
-# define machine_is_mba2410()	(machine_arch_type == MACH_TYPE_MBA2410)
-#else
-# define machine_is_mba2410()	(0)
-#endif
-
-#ifdef CONFIG_MACH_VOLCANO
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_VOLCANO
-# endif
-# define machine_is_volcano()	(machine_arch_type == MACH_TYPE_VOLCANO)
-#else
-# define machine_is_volcano()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ZENITH
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ZENITH
-# endif
-# define machine_is_zenith()	(machine_arch_type == MACH_TYPE_ZENITH)
-#else
-# define machine_is_zenith()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MUCHIP
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MUCHIP
-# endif
-# define machine_is_muchip()	(machine_arch_type == MACH_TYPE_MUCHIP)
-#else
-# define machine_is_muchip()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MAGELLAN
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MAGELLAN
-# endif
-# define machine_is_magellan()	(machine_arch_type == MACH_TYPE_MAGELLAN)
-#else
-# define machine_is_magellan()	(0)
-#endif
-
-#ifdef CONFIG_MACH_USB_A9260
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_USB_A9260
-# endif
-# define machine_is_usb_a9260()	(machine_arch_type == MACH_TYPE_USB_A9260)
-#else
-# define machine_is_usb_a9260()	(0)
-#endif
-
-#ifdef CONFIG_MACH_USB_A9263
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_USB_A9263
-# endif
-# define machine_is_usb_a9263()	(machine_arch_type == MACH_TYPE_USB_A9263)
-#else
-# define machine_is_usb_a9263()	(0)
-#endif
-
-#ifdef CONFIG_MACH_QIL_A9260
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_QIL_A9260
-# endif
-# define machine_is_qil_a9260()	(machine_arch_type == MACH_TYPE_QIL_A9260)
-#else
-# define machine_is_qil_a9260()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CME9210
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CME9210
-# endif
-# define machine_is_cme9210()	(machine_arch_type == MACH_TYPE_CME9210)
-#else
-# define machine_is_cme9210()	(0)
-#endif
-
-#ifdef CONFIG_MACH_HCZH4
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_HCZH4
-# endif
-# define machine_is_hczh4()	(machine_arch_type == MACH_TYPE_HCZH4)
-#else
-# define machine_is_hczh4()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SPEARBASIC
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SPEARBASIC
-# endif
-# define machine_is_spearbasic()	(machine_arch_type == MACH_TYPE_SPEARBASIC)
-#else
-# define machine_is_spearbasic()	(0)
-#endif
-
-#ifdef CONFIG_MACH_DEP2440
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_DEP2440
-# endif
-# define machine_is_dep2440()	(machine_arch_type == MACH_TYPE_DEP2440)
-#else
-# define machine_is_dep2440()	(0)
-#endif
-
-#ifdef CONFIG_MACH_HDL_GXR
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_HDL_GXR
-# endif
-# define machine_is_hdl_gxr()	(machine_arch_type == MACH_TYPE_HDL_GXR)
-#else
-# define machine_is_hdl_gxr()	(0)
-#endif
-
-#ifdef CONFIG_MACH_HDL_GT
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_HDL_GT
-# endif
-# define machine_is_hdl_gt()	(machine_arch_type == MACH_TYPE_HDL_GT)
-#else
-# define machine_is_hdl_gt()	(0)
-#endif
-
-#ifdef CONFIG_MACH_HDL_4G
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_HDL_4G
-# endif
-# define machine_is_hdl_4g()	(machine_arch_type == MACH_TYPE_HDL_4G)
-#else
-# define machine_is_hdl_4g()	(0)
-#endif
-
-#ifdef CONFIG_MACH_S3C6000
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_S3C6000
-# endif
-# define machine_is_s3c6000()	(machine_arch_type == MACH_TYPE_S3C6000)
-#else
-# define machine_is_s3c6000()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MMSP2_MDK
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MMSP2_MDK
-# endif
-# define machine_is_mmsp2_mdk()	(machine_arch_type == MACH_TYPE_MMSP2_MDK)
-#else
-# define machine_is_mmsp2_mdk()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MPX220
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MPX220
-# endif
-# define machine_is_mpx220()	(machine_arch_type == MACH_TYPE_MPX220)
-#else
-# define machine_is_mpx220()	(0)
-#endif
-
-#ifdef CONFIG_MACH_KZM_ARM11_01
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_KZM_ARM11_01
-# endif
-# define machine_is_kzm_arm11_01()	(machine_arch_type == MACH_TYPE_KZM_ARM11_01)
-#else
-# define machine_is_kzm_arm11_01()	(0)
-#endif
-
-#ifdef CONFIG_MACH_HTC_POLARIS
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_HTC_POLARIS
-# endif
-# define machine_is_htc_polaris()	(machine_arch_type == MACH_TYPE_HTC_POLARIS)
-#else
-# define machine_is_htc_polaris()	(0)
-#endif
-
-#ifdef CONFIG_MACH_HTC_KAISER
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_HTC_KAISER
-# endif
-# define machine_is_htc_kaiser()	(machine_arch_type == MACH_TYPE_HTC_KAISER)
-#else
-# define machine_is_htc_kaiser()	(0)
-#endif
-
-#ifdef CONFIG_MACH_LG_KS20
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_LG_KS20
-# endif
-# define machine_is_lg_ks20()	(machine_arch_type == MACH_TYPE_LG_KS20)
-#else
-# define machine_is_lg_ks20()	(0)
-#endif
-
-#ifdef CONFIG_MACH_HHGPS
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_HHGPS
-# endif
-# define machine_is_hhgps()	(machine_arch_type == MACH_TYPE_HHGPS)
-#else
-# define machine_is_hhgps()	(0)
-#endif
-
-#ifdef CONFIG_MACH_NOKIA_N810_WIMAX
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_NOKIA_N810_WIMAX
-# endif
-# define machine_is_nokia_n810_wimax()	(machine_arch_type == MACH_TYPE_NOKIA_N810_WIMAX)
-#else
-# define machine_is_nokia_n810_wimax()	(0)
-#endif
-
-#ifdef CONFIG_MACH_INSIGHT
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_INSIGHT
-# endif
-# define machine_is_insight()	(machine_arch_type == MACH_TYPE_INSIGHT)
-#else
-# define machine_is_insight()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SAPPHIRE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SAPPHIRE
-# endif
-# define machine_is_sapphire()	(machine_arch_type == MACH_TYPE_SAPPHIRE)
-#else
-# define machine_is_sapphire()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CSB637XO
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CSB637XO
-# endif
-# define machine_is_csb637xo()	(machine_arch_type == MACH_TYPE_CSB637XO)
-#else
-# define machine_is_csb637xo()	(0)
-#endif
-
-#ifdef CONFIG_MACH_EVISIONG
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_EVISIONG
-# endif
-# define machine_is_evisiong()	(machine_arch_type == MACH_TYPE_EVISIONG)
-#else
-# define machine_is_evisiong()	(0)
-#endif
-
-#ifdef CONFIG_MACH_STMP37XX
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_STMP37XX
-# endif
-# define machine_is_stmp37xx()	(machine_arch_type == MACH_TYPE_STMP37XX)
-#else
-# define machine_is_stmp37xx()	(0)
-#endif
-
-#ifdef CONFIG_MACH_STMP378X
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_STMP378X
-# endif
-# define machine_is_stmp378x()	(machine_arch_type == MACH_TYPE_STMP378X)
-#else
-# define machine_is_stmp378x()	(0)
-#endif
-
-#ifdef CONFIG_MACH_TNT
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TNT
-# endif
-# define machine_is_tnt()	(machine_arch_type == MACH_TYPE_TNT)
-#else
-# define machine_is_tnt()	(0)
-#endif
-
-#ifdef CONFIG_MACH_TBXT
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TBXT
-# endif
-# define machine_is_tbxt()	(machine_arch_type == MACH_TYPE_TBXT)
-#else
-# define machine_is_tbxt()	(0)
-#endif
-
-#ifdef CONFIG_MACH_PLAYMATE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PLAYMATE
-# endif
-# define machine_is_playmate()	(machine_arch_type == MACH_TYPE_PLAYMATE)
-#else
-# define machine_is_playmate()	(0)
-#endif
-
-#ifdef CONFIG_MACH_PNS10
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PNS10
-# endif
-# define machine_is_pns10()	(machine_arch_type == MACH_TYPE_PNS10)
-#else
-# define machine_is_pns10()	(0)
-#endif
-
-#ifdef CONFIG_MACH_EZNAVI
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_EZNAVI
-# endif
-# define machine_is_eznavi()	(machine_arch_type == MACH_TYPE_EZNAVI)
-#else
-# define machine_is_eznavi()	(0)
-#endif
-
-#ifdef CONFIG_MACH_PS4000
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PS4000
-# endif
-# define machine_is_ps4000()	(machine_arch_type == MACH_TYPE_PS4000)
-#else
-# define machine_is_ps4000()	(0)
-#endif
-
-#ifdef CONFIG_MACH_EZX_A780
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_EZX_A780
-# endif
-# define machine_is_ezx_a780()	(machine_arch_type == MACH_TYPE_EZX_A780)
-#else
-# define machine_is_ezx_a780()	(0)
-#endif
-
-#ifdef CONFIG_MACH_EZX_E680
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_EZX_E680
-# endif
-# define machine_is_ezx_e680()	(machine_arch_type == MACH_TYPE_EZX_E680)
-#else
-# define machine_is_ezx_e680()	(0)
-#endif
-
-#ifdef CONFIG_MACH_EZX_A1200
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_EZX_A1200
-# endif
-# define machine_is_ezx_a1200()	(machine_arch_type == MACH_TYPE_EZX_A1200)
-#else
-# define machine_is_ezx_a1200()	(0)
-#endif
-
-#ifdef CONFIG_MACH_EZX_E6
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_EZX_E6
-# endif
-# define machine_is_ezx_e6()	(machine_arch_type == MACH_TYPE_EZX_E6)
-#else
-# define machine_is_ezx_e6()	(0)
-#endif
-
-#ifdef CONFIG_MACH_EZX_E2
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_EZX_E2
-# endif
-# define machine_is_ezx_e2()	(machine_arch_type == MACH_TYPE_EZX_E2)
-#else
-# define machine_is_ezx_e2()	(0)
-#endif
-
-#ifdef CONFIG_MACH_EZX_A910
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_EZX_A910
-# endif
-# define machine_is_ezx_a910()	(machine_arch_type == MACH_TYPE_EZX_A910)
-#else
-# define machine_is_ezx_a910()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CWMX31
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CWMX31
-# endif
-# define machine_is_cwmx31()	(machine_arch_type == MACH_TYPE_CWMX31)
-#else
-# define machine_is_cwmx31()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SL2312
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SL2312
-# endif
-# define machine_is_sl2312()	(machine_arch_type == MACH_TYPE_SL2312)
-#else
-# define machine_is_sl2312()	(0)
-#endif
-
-#ifdef CONFIG_MACH_BLENNY
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_BLENNY
-# endif
-# define machine_is_blenny()	(machine_arch_type == MACH_TYPE_BLENNY)
-#else
-# define machine_is_blenny()	(0)
-#endif
-
-#ifdef CONFIG_MACH_DS107
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_DS107
-# endif
-# define machine_is_ds107()	(machine_arch_type == MACH_TYPE_DS107)
-#else
-# define machine_is_ds107()	(0)
-#endif
-
-#ifdef CONFIG_MACH_DSX07
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_DSX07
-# endif
-# define machine_is_dsx07()	(machine_arch_type == MACH_TYPE_DSX07)
-#else
-# define machine_is_dsx07()	(0)
-#endif
-
-#ifdef CONFIG_MACH_PICOCOM1
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PICOCOM1
-# endif
-# define machine_is_picocom1()	(machine_arch_type == MACH_TYPE_PICOCOM1)
-#else
-# define machine_is_picocom1()	(0)
-#endif
-
-#ifdef CONFIG_MACH_LYNX_WOLVERINE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_LYNX_WOLVERINE
-# endif
-# define machine_is_lynx_wolverine()	(machine_arch_type == MACH_TYPE_LYNX_WOLVERINE)
-#else
-# define machine_is_lynx_wolverine()	(0)
-#endif
-
-#ifdef CONFIG_MACH_UBISYS_P9_SC19
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_UBISYS_P9_SC19
-# endif
-# define machine_is_ubisys_p9_sc19()	(machine_arch_type == MACH_TYPE_UBISYS_P9_SC19)
-#else
-# define machine_is_ubisys_p9_sc19()	(0)
-#endif
-
-#ifdef CONFIG_MACH_KRATOS_LOW
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_KRATOS_LOW
-# endif
-# define machine_is_kratos_low()	(machine_arch_type == MACH_TYPE_KRATOS_LOW)
-#else
-# define machine_is_kratos_low()	(0)
-#endif
-
-#ifdef CONFIG_MACH_M700
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_M700
-# endif
-# define machine_is_m700()	(machine_arch_type == MACH_TYPE_M700)
-#else
-# define machine_is_m700()	(0)
-#endif
-
-#ifdef CONFIG_MACH_EDMINI_V2
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_EDMINI_V2
-# endif
-# define machine_is_edmini_v2()	(machine_arch_type == MACH_TYPE_EDMINI_V2)
-#else
-# define machine_is_edmini_v2()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ZIPIT2
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ZIPIT2
-# endif
-# define machine_is_zipit2()	(machine_arch_type == MACH_TYPE_ZIPIT2)
-#else
-# define machine_is_zipit2()	(0)
-#endif
-
-#ifdef CONFIG_MACH_HSLFEMTOCELL
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_HSLFEMTOCELL
-# endif
-# define machine_is_hslfemtocell()	(machine_arch_type == MACH_TYPE_HSLFEMTOCELL)
-#else
-# define machine_is_hslfemtocell()	(0)
-#endif
-
-#ifdef CONFIG_MACH_DAINTREE_AT91
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_DAINTREE_AT91
-# endif
-# define machine_is_daintree_at91()	(machine_arch_type == MACH_TYPE_DAINTREE_AT91)
-#else
-# define machine_is_daintree_at91()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SG560USB
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SG560USB
-# endif
-# define machine_is_sg560usb()	(machine_arch_type == MACH_TYPE_SG560USB)
-#else
-# define machine_is_sg560usb()	(0)
-#endif
-
-#ifdef CONFIG_MACH_OMAP3_PANDORA
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_OMAP3_PANDORA
-# endif
-# define machine_is_omap3_pandora()	(machine_arch_type == MACH_TYPE_OMAP3_PANDORA)
-#else
-# define machine_is_omap3_pandora()	(0)
-#endif
-
-#ifdef CONFIG_MACH_USR8200
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_USR8200
-# endif
-# define machine_is_usr8200()	(machine_arch_type == MACH_TYPE_USR8200)
-#else
-# define machine_is_usr8200()	(0)
-#endif
-
-#ifdef CONFIG_MACH_S1S65K
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_S1S65K
-# endif
-# define machine_is_s1s65k()	(machine_arch_type == MACH_TYPE_S1S65K)
-#else
-# define machine_is_s1s65k()	(0)
-#endif
-
-#ifdef CONFIG_MACH_S2S65A
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_S2S65A
-# endif
-# define machine_is_s2s65a()	(machine_arch_type == MACH_TYPE_S2S65A)
-#else
-# define machine_is_s2s65a()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ICORE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ICORE
-# endif
-# define machine_is_icore()	(machine_arch_type == MACH_TYPE_ICORE)
-#else
-# define machine_is_icore()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MSS2
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MSS2
-# endif
-# define machine_is_mss2()	(machine_arch_type == MACH_TYPE_MSS2)
-#else
-# define machine_is_mss2()	(0)
-#endif
-
-#ifdef CONFIG_MACH_BELMONT
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_BELMONT
-# endif
-# define machine_is_belmont()	(machine_arch_type == MACH_TYPE_BELMONT)
-#else
-# define machine_is_belmont()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ASUSP525
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ASUSP525
-# endif
-# define machine_is_asusp525()	(machine_arch_type == MACH_TYPE_ASUSP525)
-#else
-# define machine_is_asusp525()	(0)
-#endif
-
-#ifdef CONFIG_MACH_LB88RC8480
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_LB88RC8480
-# endif
-# define machine_is_lb88rc8480()	(machine_arch_type == MACH_TYPE_LB88RC8480)
-#else
-# define machine_is_lb88rc8480()	(0)
-#endif
-
-#ifdef CONFIG_MACH_HIPXA
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_HIPXA
-# endif
-# define machine_is_hipxa()	(machine_arch_type == MACH_TYPE_HIPXA)
-#else
-# define machine_is_hipxa()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MX25_3DS
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MX25_3DS
-# endif
-# define machine_is_mx25_3ds()	(machine_arch_type == MACH_TYPE_MX25_3DS)
-#else
-# define machine_is_mx25_3ds()	(0)
-#endif
-
-#ifdef CONFIG_MACH_M800
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_M800
-# endif
-# define machine_is_m800()	(machine_arch_type == MACH_TYPE_M800)
-#else
-# define machine_is_m800()	(0)
-#endif
-
-#ifdef CONFIG_MACH_OMAP3530_LV_SOM
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_OMAP3530_LV_SOM
-# endif
-# define machine_is_omap3530_lv_som()	(machine_arch_type == MACH_TYPE_OMAP3530_LV_SOM)
-#else
-# define machine_is_omap3530_lv_som()	(0)
-#endif
-
-#ifdef CONFIG_MACH_PRIMA_EVB
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PRIMA_EVB
-# endif
-# define machine_is_prima_evb()	(machine_arch_type == MACH_TYPE_PRIMA_EVB)
-#else
-# define machine_is_prima_evb()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MX31BT1
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MX31BT1
-# endif
-# define machine_is_mx31bt1()	(machine_arch_type == MACH_TYPE_MX31BT1)
-#else
-# define machine_is_mx31bt1()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ATLAS4_EVB
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ATLAS4_EVB
-# endif
-# define machine_is_atlas4_evb()	(machine_arch_type == MACH_TYPE_ATLAS4_EVB)
-#else
-# define machine_is_atlas4_evb()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MX31CICADA
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MX31CICADA
-# endif
-# define machine_is_mx31cicada()	(machine_arch_type == MACH_TYPE_MX31CICADA)
-#else
-# define machine_is_mx31cicada()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MI424WR
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MI424WR
-# endif
-# define machine_is_mi424wr()	(machine_arch_type == MACH_TYPE_MI424WR)
-#else
-# define machine_is_mi424wr()	(0)
-#endif
-
-#ifdef CONFIG_MACH_AXS_ULTRAX
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_AXS_ULTRAX
-# endif
-# define machine_is_axs_ultrax()	(machine_arch_type == MACH_TYPE_AXS_ULTRAX)
-#else
-# define machine_is_axs_ultrax()	(0)
-#endif
-
-#ifdef CONFIG_MACH_AT572D940DEB
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_AT572D940DEB
-# endif
-# define machine_is_at572d940deb()	(machine_arch_type == MACH_TYPE_AT572D940DEB)
-#else
-# define machine_is_at572d940deb()	(0)
-#endif
-
-#ifdef CONFIG_MACH_DAVINCI_DA830_EVM
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_DAVINCI_DA830_EVM
-# endif
-# define machine_is_davinci_da830_evm()	(machine_arch_type == MACH_TYPE_DAVINCI_DA830_EVM)
-#else
-# define machine_is_davinci_da830_evm()	(0)
-#endif
-
-#ifdef CONFIG_MACH_EP9302
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_EP9302
-# endif
-# define machine_is_ep9302()	(machine_arch_type == MACH_TYPE_EP9302)
-#else
-# define machine_is_ep9302()	(0)
-#endif
-
-#ifdef CONFIG_MACH_AT572D940HFEB
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_AT572D940HFEB
-# endif
-# define machine_is_at572d940hfek()	(machine_arch_type == MACH_TYPE_AT572D940HFEB)
-#else
-# define machine_is_at572d940hfek()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CYBOOK3
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CYBOOK3
-# endif
-# define machine_is_cybook3()	(machine_arch_type == MACH_TYPE_CYBOOK3)
-#else
-# define machine_is_cybook3()	(0)
-#endif
-
-#ifdef CONFIG_MACH_WDG002
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_WDG002
-# endif
-# define machine_is_wdg002()	(machine_arch_type == MACH_TYPE_WDG002)
-#else
-# define machine_is_wdg002()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SG560ADSL
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SG560ADSL
-# endif
-# define machine_is_sg560adsl()	(machine_arch_type == MACH_TYPE_SG560ADSL)
-#else
-# define machine_is_sg560adsl()	(0)
-#endif
-
-#ifdef CONFIG_MACH_NEXTIO_N2800_ICA
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_NEXTIO_N2800_ICA
-# endif
-# define machine_is_nextio_n2800_ica()	(machine_arch_type == MACH_TYPE_NEXTIO_N2800_ICA)
-#else
-# define machine_is_nextio_n2800_ica()	(0)
-#endif
-
-#ifdef CONFIG_MACH_DOVE_DB
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_DOVE_DB
-# endif
-# define machine_is_dove_db()	(machine_arch_type == MACH_TYPE_DOVE_DB)
-#else
-# define machine_is_dove_db()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MARVELL_NEWDB
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MARVELL_NEWDB
-# endif
-# define machine_is_marvell_newdb()	(machine_arch_type == MACH_TYPE_MARVELL_NEWDB)
-#else
-# define machine_is_marvell_newdb()	(0)
-#endif
-
-#ifdef CONFIG_MACH_VANDIHUD
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_VANDIHUD
-# endif
-# define machine_is_vandihud()	(machine_arch_type == MACH_TYPE_VANDIHUD)
-#else
-# define machine_is_vandihud()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MAGX_E8
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MAGX_E8
-# endif
-# define machine_is_magx_e8()	(machine_arch_type == MACH_TYPE_MAGX_E8)
-#else
-# define machine_is_magx_e8()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MAGX_Z6
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MAGX_Z6
-# endif
-# define machine_is_magx_z6()	(machine_arch_type == MACH_TYPE_MAGX_Z6)
-#else
-# define machine_is_magx_z6()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MAGX_V8
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MAGX_V8
-# endif
-# define machine_is_magx_v8()	(machine_arch_type == MACH_TYPE_MAGX_V8)
-#else
-# define machine_is_magx_v8()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MAGX_U9
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MAGX_U9
-# endif
-# define machine_is_magx_u9()	(machine_arch_type == MACH_TYPE_MAGX_U9)
-#else
-# define machine_is_magx_u9()	(0)
-#endif
-
-#ifdef CONFIG_MACH_TOUGHCF08
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TOUGHCF08
-# endif
-# define machine_is_toughcf08()	(machine_arch_type == MACH_TYPE_TOUGHCF08)
-#else
-# define machine_is_toughcf08()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ZW4400
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ZW4400
-# endif
-# define machine_is_zw4400()	(machine_arch_type == MACH_TYPE_ZW4400)
-#else
-# define machine_is_zw4400()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MARAT91
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MARAT91
-# endif
-# define machine_is_marat91()	(machine_arch_type == MACH_TYPE_MARAT91)
-#else
-# define machine_is_marat91()	(0)
-#endif
-
-#ifdef CONFIG_MACH_OVERO
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_OVERO
-# endif
-# define machine_is_overo()	(machine_arch_type == MACH_TYPE_OVERO)
-#else
-# define machine_is_overo()	(0)
-#endif
-
-#ifdef CONFIG_MACH_AT2440EVB
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_AT2440EVB
-# endif
-# define machine_is_at2440evb()	(machine_arch_type == MACH_TYPE_AT2440EVB)
-#else
-# define machine_is_at2440evb()	(0)
-#endif
-
-#ifdef CONFIG_MACH_NEOCORE926
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_NEOCORE926
-# endif
-# define machine_is_neocore926()	(machine_arch_type == MACH_TYPE_NEOCORE926)
-#else
-# define machine_is_neocore926()	(0)
-#endif
-
-#ifdef CONFIG_MACH_WNR854T
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_WNR854T
-# endif
-# define machine_is_wnr854t()	(machine_arch_type == MACH_TYPE_WNR854T)
-#else
-# define machine_is_wnr854t()	(0)
-#endif
-
-#ifdef CONFIG_MACH_IMX27
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_IMX27
-# endif
-# define machine_is_imx27()	(machine_arch_type == MACH_TYPE_IMX27)
-#else
-# define machine_is_imx27()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MOOSE_DB
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MOOSE_DB
-# endif
-# define machine_is_moose_db()	(machine_arch_type == MACH_TYPE_MOOSE_DB)
-#else
-# define machine_is_moose_db()	(0)
-#endif
-
-#ifdef CONFIG_MACH_FAB4
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_FAB4
-# endif
-# define machine_is_fab4()	(machine_arch_type == MACH_TYPE_FAB4)
-#else
-# define machine_is_fab4()	(0)
-#endif
-
-#ifdef CONFIG_MACH_HTCDIAMOND
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_HTCDIAMOND
-# endif
-# define machine_is_htcdiamond()	(machine_arch_type == MACH_TYPE_HTCDIAMOND)
-#else
-# define machine_is_htcdiamond()	(0)
-#endif
-
-#ifdef CONFIG_MACH_FIONA
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_FIONA
-# endif
-# define machine_is_fiona()	(machine_arch_type == MACH_TYPE_FIONA)
-#else
-# define machine_is_fiona()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MXC30030_X
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MXC30030_X
-# endif
-# define machine_is_mxc30030_x()	(machine_arch_type == MACH_TYPE_MXC30030_X)
-#else
-# define machine_is_mxc30030_x()	(0)
-#endif
-
-#ifdef CONFIG_MACH_BMP1000
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_BMP1000
-# endif
-# define machine_is_bmp1000()	(machine_arch_type == MACH_TYPE_BMP1000)
-#else
-# define machine_is_bmp1000()	(0)
-#endif
-
-#ifdef CONFIG_MACH_LOGI9200
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_LOGI9200
-# endif
-# define machine_is_logi9200()	(machine_arch_type == MACH_TYPE_LOGI9200)
-#else
-# define machine_is_logi9200()	(0)
-#endif
-
-#ifdef CONFIG_MACH_TQMA31
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TQMA31
-# endif
-# define machine_is_tqma31()	(machine_arch_type == MACH_TYPE_TQMA31)
-#else
-# define machine_is_tqma31()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CCW9P9215JS
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CCW9P9215JS
-# endif
-# define machine_is_ccw9p9215js()	(machine_arch_type == MACH_TYPE_CCW9P9215JS)
-#else
-# define machine_is_ccw9p9215js()	(0)
-#endif
-
-#ifdef CONFIG_MACH_RD88F5181L_GE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_RD88F5181L_GE
-# endif
-# define machine_is_rd88f5181l_ge()	(machine_arch_type == MACH_TYPE_RD88F5181L_GE)
-#else
-# define machine_is_rd88f5181l_ge()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SIFMAIN
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SIFMAIN
-# endif
-# define machine_is_sifmain()	(machine_arch_type == MACH_TYPE_SIFMAIN)
-#else
-# define machine_is_sifmain()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SAM9_L9261
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SAM9_L9261
-# endif
-# define machine_is_sam9_l9261()	(machine_arch_type == MACH_TYPE_SAM9_L9261)
-#else
-# define machine_is_sam9_l9261()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CC9M2443
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CC9M2443
-# endif
-# define machine_is_cc9m2443()	(machine_arch_type == MACH_TYPE_CC9M2443)
-#else
-# define machine_is_cc9m2443()	(0)
-#endif
-
-#ifdef CONFIG_MACH_XARIA300
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_XARIA300
-# endif
-# define machine_is_xaria300()	(machine_arch_type == MACH_TYPE_XARIA300)
-#else
-# define machine_is_xaria300()	(0)
-#endif
-
-#ifdef CONFIG_MACH_IT9200
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_IT9200
-# endif
-# define machine_is_it9200()	(machine_arch_type == MACH_TYPE_IT9200)
-#else
-# define machine_is_it9200()	(0)
-#endif
-
-#ifdef CONFIG_MACH_RD88F5181L_FXO
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_RD88F5181L_FXO
-# endif
-# define machine_is_rd88f5181l_fxo()	(machine_arch_type == MACH_TYPE_RD88F5181L_FXO)
-#else
-# define machine_is_rd88f5181l_fxo()	(0)
-#endif
-
-#ifdef CONFIG_MACH_KRISS_SENSOR
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_KRISS_SENSOR
-# endif
-# define machine_is_kriss_sensor()	(machine_arch_type == MACH_TYPE_KRISS_SENSOR)
-#else
-# define machine_is_kriss_sensor()	(0)
-#endif
-
-#ifdef CONFIG_MACH_PILZ_PMI5
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PILZ_PMI5
-# endif
-# define machine_is_pilz_pmi5()	(machine_arch_type == MACH_TYPE_PILZ_PMI5)
-#else
-# define machine_is_pilz_pmi5()	(0)
-#endif
-
-#ifdef CONFIG_MACH_JADE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_JADE
-# endif
-# define machine_is_jade()	(machine_arch_type == MACH_TYPE_JADE)
-#else
-# define machine_is_jade()	(0)
-#endif
-
-#ifdef CONFIG_MACH_KS8695_SOFTPLC
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_KS8695_SOFTPLC
-# endif
-# define machine_is_ks8695_softplc()	(machine_arch_type == MACH_TYPE_KS8695_SOFTPLC)
-#else
-# define machine_is_ks8695_softplc()	(0)
-#endif
-
-#ifdef CONFIG_MACH_GPRISC3
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_GPRISC3
-# endif
-# define machine_is_gprisc3()	(machine_arch_type == MACH_TYPE_GPRISC3)
-#else
-# define machine_is_gprisc3()	(0)
-#endif
-
-#ifdef CONFIG_MACH_STAMP9G20
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_STAMP9G20
-# endif
-# define machine_is_stamp9g20()	(machine_arch_type == MACH_TYPE_STAMP9G20)
-#else
-# define machine_is_stamp9g20()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SMDK6430
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SMDK6430
-# endif
-# define machine_is_smdk6430()	(machine_arch_type == MACH_TYPE_SMDK6430)
-#else
-# define machine_is_smdk6430()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SMDKC100
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SMDKC100
-# endif
-# define machine_is_smdkc100()	(machine_arch_type == MACH_TYPE_SMDKC100)
-#else
-# define machine_is_smdkc100()	(0)
-#endif
-
-#ifdef CONFIG_MACH_TAVOREVB
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TAVOREVB
-# endif
-# define machine_is_tavorevb()	(machine_arch_type == MACH_TYPE_TAVOREVB)
-#else
-# define machine_is_tavorevb()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SAAR
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SAAR
-# endif
-# define machine_is_saar()	(machine_arch_type == MACH_TYPE_SAAR)
-#else
-# define machine_is_saar()	(0)
-#endif
-
-#ifdef CONFIG_MACH_DEISTER_EYECAM
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_DEISTER_EYECAM
-# endif
-# define machine_is_deister_eyecam()	(machine_arch_type == MACH_TYPE_DEISTER_EYECAM)
-#else
-# define machine_is_deister_eyecam()	(0)
-#endif
-
-#ifdef CONFIG_MACH_AT91SAM9M10G45EK
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_AT91SAM9M10G45EK
-# endif
-# define machine_is_at91sam9m10g45ek()	(machine_arch_type == MACH_TYPE_AT91SAM9M10G45EK)
-#else
-# define machine_is_at91sam9m10g45ek()	(0)
-#endif
-
-#ifdef CONFIG_MACH_LINKSTATION_PRODUO
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_LINKSTATION_PRODUO
-# endif
-# define machine_is_linkstation_produo()	(machine_arch_type == MACH_TYPE_LINKSTATION_PRODUO)
-#else
-# define machine_is_linkstation_produo()	(0)
-#endif
-
-#ifdef CONFIG_MACH_HIT_B0
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_HIT_B0
-# endif
-# define machine_is_hit_b0()	(machine_arch_type == MACH_TYPE_HIT_B0)
-#else
-# define machine_is_hit_b0()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ADX_RMU
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ADX_RMU
-# endif
-# define machine_is_adx_rmu()	(machine_arch_type == MACH_TYPE_ADX_RMU)
-#else
-# define machine_is_adx_rmu()	(0)
-#endif
-
-#ifdef CONFIG_MACH_XG_CPE_MAIN
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_XG_CPE_MAIN
-# endif
-# define machine_is_xg_cpe_main()	(machine_arch_type == MACH_TYPE_XG_CPE_MAIN)
-#else
-# define machine_is_xg_cpe_main()	(0)
-#endif
-
-#ifdef CONFIG_MACH_EDB9407A
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_EDB9407A
-# endif
-# define machine_is_edb9407a()	(machine_arch_type == MACH_TYPE_EDB9407A)
-#else
-# define machine_is_edb9407a()	(0)
-#endif
-
-#ifdef CONFIG_MACH_DTB9608
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_DTB9608
-# endif
-# define machine_is_dtb9608()	(machine_arch_type == MACH_TYPE_DTB9608)
-#else
-# define machine_is_dtb9608()	(0)
-#endif
-
-#ifdef CONFIG_MACH_EM104V1
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_EM104V1
-# endif
-# define machine_is_em104v1()	(machine_arch_type == MACH_TYPE_EM104V1)
-#else
-# define machine_is_em104v1()	(0)
-#endif
-
-#ifdef CONFIG_MACH_DEMO
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_DEMO
-# endif
-# define machine_is_demo()	(machine_arch_type == MACH_TYPE_DEMO)
-#else
-# define machine_is_demo()	(0)
-#endif
-
-#ifdef CONFIG_MACH_LOGI9260
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_LOGI9260
-# endif
-# define machine_is_logi9260()	(machine_arch_type == MACH_TYPE_LOGI9260)
-#else
-# define machine_is_logi9260()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MX31_EXM32
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MX31_EXM32
-# endif
-# define machine_is_mx31_exm32()	(machine_arch_type == MACH_TYPE_MX31_EXM32)
-#else
-# define machine_is_mx31_exm32()	(0)
-#endif
-
-#ifdef CONFIG_MACH_USB_A9G20
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_USB_A9G20
-# endif
-# define machine_is_usb_a9g20()	(machine_arch_type == MACH_TYPE_USB_A9G20)
-#else
-# define machine_is_usb_a9g20()	(0)
-#endif
-
-#ifdef CONFIG_MACH_PICPROJE2008
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PICPROJE2008
-# endif
-# define machine_is_picproje2008()	(machine_arch_type == MACH_TYPE_PICPROJE2008)
-#else
-# define machine_is_picproje2008()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CS_E9315
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CS_E9315
-# endif
-# define machine_is_cs_e9315()	(machine_arch_type == MACH_TYPE_CS_E9315)
-#else
-# define machine_is_cs_e9315()	(0)
-#endif
-
-#ifdef CONFIG_MACH_QIL_A9G20
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_QIL_A9G20
-# endif
-# define machine_is_qil_a9g20()	(machine_arch_type == MACH_TYPE_QIL_A9G20)
-#else
-# define machine_is_qil_a9g20()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SHA_PON020
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SHA_PON020
-# endif
-# define machine_is_sha_pon020()	(machine_arch_type == MACH_TYPE_SHA_PON020)
-#else
-# define machine_is_sha_pon020()	(0)
-#endif
-
-#ifdef CONFIG_MACH_NAD
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_NAD
-# endif
-# define machine_is_nad()	(machine_arch_type == MACH_TYPE_NAD)
-#else
-# define machine_is_nad()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SBC35_A9260
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SBC35_A9260
-# endif
-# define machine_is_sbc35_a9260()	(machine_arch_type == MACH_TYPE_SBC35_A9260)
-#else
-# define machine_is_sbc35_a9260()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SBC35_A9G20
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SBC35_A9G20
-# endif
-# define machine_is_sbc35_a9g20()	(machine_arch_type == MACH_TYPE_SBC35_A9G20)
-#else
-# define machine_is_sbc35_a9g20()	(0)
-#endif
-
-#ifdef CONFIG_MACH_DAVINCI_BEGINNING
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_DAVINCI_BEGINNING
-# endif
-# define machine_is_davinci_beginning()	(machine_arch_type == MACH_TYPE_DAVINCI_BEGINNING)
-#else
-# define machine_is_davinci_beginning()	(0)
-#endif
-
-#ifdef CONFIG_MACH_UWC
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_UWC
-# endif
-# define machine_is_uwc()	(machine_arch_type == MACH_TYPE_UWC)
-#else
-# define machine_is_uwc()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MXLADS
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MXLADS
-# endif
-# define machine_is_mxlads()	(machine_arch_type == MACH_TYPE_MXLADS)
-#else
-# define machine_is_mxlads()	(0)
-#endif
-
-#ifdef CONFIG_MACH_HTCNIKE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_HTCNIKE
-# endif
-# define machine_is_htcnike()	(machine_arch_type == MACH_TYPE_HTCNIKE)
-#else
-# define machine_is_htcnike()	(0)
-#endif
-
-#ifdef CONFIG_MACH_DEISTER_PXA270
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_DEISTER_PXA270
-# endif
-# define machine_is_deister_pxa270()	(machine_arch_type == MACH_TYPE_DEISTER_PXA270)
-#else
-# define machine_is_deister_pxa270()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CME9210JS
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CME9210JS
-# endif
-# define machine_is_cme9210js()	(machine_arch_type == MACH_TYPE_CME9210JS)
-#else
-# define machine_is_cme9210js()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CC9P9360
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CC9P9360
-# endif
-# define machine_is_cc9p9360()	(machine_arch_type == MACH_TYPE_CC9P9360)
-#else
-# define machine_is_cc9p9360()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MOCHA
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MOCHA
-# endif
-# define machine_is_mocha()	(machine_arch_type == MACH_TYPE_MOCHA)
-#else
-# define machine_is_mocha()	(0)
-#endif
-
-#ifdef CONFIG_MACH_WAPD170AG
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_WAPD170AG
-# endif
-# define machine_is_wapd170ag()	(machine_arch_type == MACH_TYPE_WAPD170AG)
-#else
-# define machine_is_wapd170ag()	(0)
-#endif
-
-#ifdef CONFIG_MACH_LINKSTATION_MINI
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_LINKSTATION_MINI
-# endif
-# define machine_is_linkstation_mini()	(machine_arch_type == MACH_TYPE_LINKSTATION_MINI)
-#else
-# define machine_is_linkstation_mini()	(0)
-#endif
-
-#ifdef CONFIG_MACH_AFEB9260
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_AFEB9260
-# endif
-# define machine_is_afeb9260()	(machine_arch_type == MACH_TYPE_AFEB9260)
-#else
-# define machine_is_afeb9260()	(0)
-#endif
-
-#ifdef CONFIG_MACH_W90X900
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_W90X900
-# endif
-# define machine_is_w90x900()	(machine_arch_type == MACH_TYPE_W90X900)
-#else
-# define machine_is_w90x900()	(0)
-#endif
-
-#ifdef CONFIG_MACH_W90X700
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_W90X700
-# endif
-# define machine_is_w90x700()	(machine_arch_type == MACH_TYPE_W90X700)
-#else
-# define machine_is_w90x700()	(0)
-#endif
-
-#ifdef CONFIG_MACH_KT300IP
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_KT300IP
-# endif
-# define machine_is_kt300ip()	(machine_arch_type == MACH_TYPE_KT300IP)
-#else
-# define machine_is_kt300ip()	(0)
-#endif
-
-#ifdef CONFIG_MACH_KT300IP_G20
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_KT300IP_G20
-# endif
-# define machine_is_kt300ip_g20()	(machine_arch_type == MACH_TYPE_KT300IP_G20)
-#else
-# define machine_is_kt300ip_g20()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SRCM
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SRCM
-# endif
-# define machine_is_srcm()	(machine_arch_type == MACH_TYPE_SRCM)
-#else
-# define machine_is_srcm()	(0)
-#endif
-
-#ifdef CONFIG_MACH_WLNX_9260
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_WLNX_9260
-# endif
-# define machine_is_wlnx_9260()	(machine_arch_type == MACH_TYPE_WLNX_9260)
-#else
-# define machine_is_wlnx_9260()	(0)
-#endif
-
-#ifdef CONFIG_MACH_OPENMOKO_GTA03
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_OPENMOKO_GTA03
-# endif
-# define machine_is_openmoko_gta03()	(machine_arch_type == MACH_TYPE_OPENMOKO_GTA03)
-#else
-# define machine_is_openmoko_gta03()	(0)
-#endif
-
-#ifdef CONFIG_MACH_OSPREY2
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_OSPREY2
-# endif
-# define machine_is_osprey2()	(machine_arch_type == MACH_TYPE_OSPREY2)
-#else
-# define machine_is_osprey2()	(0)
-#endif
-
-#ifdef CONFIG_MACH_KBIO9260
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_KBIO9260
-# endif
-# define machine_is_kbio9260()	(machine_arch_type == MACH_TYPE_KBIO9260)
-#else
-# define machine_is_kbio9260()	(0)
-#endif
-
-#ifdef CONFIG_MACH_GINZA
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_GINZA
-# endif
-# define machine_is_ginza()	(machine_arch_type == MACH_TYPE_GINZA)
-#else
-# define machine_is_ginza()	(0)
-#endif
-
-#ifdef CONFIG_MACH_A636N
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_A636N
-# endif
-# define machine_is_a636n()	(machine_arch_type == MACH_TYPE_A636N)
-#else
-# define machine_is_a636n()	(0)
-#endif
-
-#ifdef CONFIG_MACH_IMX27IPCAM
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_IMX27IPCAM
-# endif
-# define machine_is_imx27ipcam()	(machine_arch_type == MACH_TYPE_IMX27IPCAM)
-#else
-# define machine_is_imx27ipcam()	(0)
-#endif
-
-#ifdef CONFIG_MACH_NEMOC
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_NEMOC
-# endif
-# define machine_is_nemoc()	(machine_arch_type == MACH_TYPE_NEMOC)
-#else
-# define machine_is_nemoc()	(0)
-#endif
-
-#ifdef CONFIG_MACH_GENEVA
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_GENEVA
-# endif
-# define machine_is_geneva()	(machine_arch_type == MACH_TYPE_GENEVA)
-#else
-# define machine_is_geneva()	(0)
-#endif
-
-#ifdef CONFIG_MACH_HTCPHAROS
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_HTCPHAROS
-# endif
-# define machine_is_htcpharos()	(machine_arch_type == MACH_TYPE_HTCPHAROS)
-#else
-# define machine_is_htcpharos()	(0)
-#endif
-
-#ifdef CONFIG_MACH_NEONC
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_NEONC
-# endif
-# define machine_is_neonc()	(machine_arch_type == MACH_TYPE_NEONC)
-#else
-# define machine_is_neonc()	(0)
-#endif
-
-#ifdef CONFIG_MACH_NAS7100
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_NAS7100
-# endif
-# define machine_is_nas7100()	(machine_arch_type == MACH_TYPE_NAS7100)
-#else
-# define machine_is_nas7100()	(0)
-#endif
-
-#ifdef CONFIG_MACH_TEUPHONE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TEUPHONE
-# endif
-# define machine_is_teuphone()	(machine_arch_type == MACH_TYPE_TEUPHONE)
-#else
-# define machine_is_teuphone()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ANNAX_ETH2
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ANNAX_ETH2
-# endif
-# define machine_is_annax_eth2()	(machine_arch_type == MACH_TYPE_ANNAX_ETH2)
-#else
-# define machine_is_annax_eth2()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CSB733
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CSB733
-# endif
-# define machine_is_csb733()	(machine_arch_type == MACH_TYPE_CSB733)
-#else
-# define machine_is_csb733()	(0)
-#endif
-
-#ifdef CONFIG_MACH_BK3
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_BK3
-# endif
-# define machine_is_bk3()	(machine_arch_type == MACH_TYPE_BK3)
-#else
-# define machine_is_bk3()	(0)
-#endif
-
-#ifdef CONFIG_MACH_OMAP_EM32
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_OMAP_EM32
-# endif
-# define machine_is_omap_em32()	(machine_arch_type == MACH_TYPE_OMAP_EM32)
-#else
-# define machine_is_omap_em32()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ET9261CP
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ET9261CP
-# endif
-# define machine_is_et9261cp()	(machine_arch_type == MACH_TYPE_ET9261CP)
-#else
-# define machine_is_et9261cp()	(0)
-#endif
-
-#ifdef CONFIG_MACH_JASPERC
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_JASPERC
-# endif
-# define machine_is_jasperc()	(machine_arch_type == MACH_TYPE_JASPERC)
-#else
-# define machine_is_jasperc()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ISSI_ARM9
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ISSI_ARM9
-# endif
-# define machine_is_issi_arm9()	(machine_arch_type == MACH_TYPE_ISSI_ARM9)
-#else
-# define machine_is_issi_arm9()	(0)
-#endif
-
-#ifdef CONFIG_MACH_UED
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_UED
-# endif
-# define machine_is_ued()	(machine_arch_type == MACH_TYPE_UED)
-#else
-# define machine_is_ued()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ESIBLADE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ESIBLADE
-# endif
-# define machine_is_esiblade()	(machine_arch_type == MACH_TYPE_ESIBLADE)
-#else
-# define machine_is_esiblade()	(0)
-#endif
-
-#ifdef CONFIG_MACH_EYE02
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_EYE02
-# endif
-# define machine_is_eye02()	(machine_arch_type == MACH_TYPE_EYE02)
-#else
-# define machine_is_eye02()	(0)
-#endif
-
-#ifdef CONFIG_MACH_IMX27KBD
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_IMX27KBD
-# endif
-# define machine_is_imx27kbd()	(machine_arch_type == MACH_TYPE_IMX27KBD)
-#else
-# define machine_is_imx27kbd()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SST61VC010_FPGA
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SST61VC010_FPGA
-# endif
-# define machine_is_sst61vc010_fpga()	(machine_arch_type == MACH_TYPE_SST61VC010_FPGA)
-#else
-# define machine_is_sst61vc010_fpga()	(0)
-#endif
-
-#ifdef CONFIG_MACH_KIXVP435
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_KIXVP435
-# endif
-# define machine_is_kixvp435()	(machine_arch_type == MACH_TYPE_KIXVP435)
-#else
-# define machine_is_kixvp435()	(0)
-#endif
-
-#ifdef CONFIG_MACH_KIXNP435
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_KIXNP435
-# endif
-# define machine_is_kixnp435()	(machine_arch_type == MACH_TYPE_KIXNP435)
-#else
-# define machine_is_kixnp435()	(0)
-#endif
-
-#ifdef CONFIG_MACH_AFRICA
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_AFRICA
-# endif
-# define machine_is_africa()	(machine_arch_type == MACH_TYPE_AFRICA)
-#else
-# define machine_is_africa()	(0)
-#endif
-
-#ifdef CONFIG_MACH_NH233
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_NH233
-# endif
-# define machine_is_nh233()	(machine_arch_type == MACH_TYPE_NH233)
-#else
-# define machine_is_nh233()	(0)
-#endif
-
-#ifdef CONFIG_MACH_RD88F6183AP_GE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_RD88F6183AP_GE
-# endif
-# define machine_is_rd88f6183ap_ge()	(machine_arch_type == MACH_TYPE_RD88F6183AP_GE)
-#else
-# define machine_is_rd88f6183ap_ge()	(0)
-#endif
-
-#ifdef CONFIG_MACH_BCM4760
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_BCM4760
-# endif
-# define machine_is_bcm4760()	(machine_arch_type == MACH_TYPE_BCM4760)
-#else
-# define machine_is_bcm4760()	(0)
-#endif
-
-#ifdef CONFIG_MACH_EDDY_V2
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_EDDY_V2
-# endif
-# define machine_is_eddy_v2()	(machine_arch_type == MACH_TYPE_EDDY_V2)
-#else
-# define machine_is_eddy_v2()	(0)
-#endif
-
-#ifdef CONFIG_MACH_REALVIEW_PBA8
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_REALVIEW_PBA8
-# endif
-# define machine_is_realview_pba8()	(machine_arch_type == MACH_TYPE_REALVIEW_PBA8)
-#else
-# define machine_is_realview_pba8()	(0)
-#endif
-
-#ifdef CONFIG_MACH_HID_A7
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_HID_A7
-# endif
-# define machine_is_hid_a7()	(machine_arch_type == MACH_TYPE_HID_A7)
-#else
-# define machine_is_hid_a7()	(0)
-#endif
-
-#ifdef CONFIG_MACH_HERO
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_HERO
-# endif
-# define machine_is_hero()	(machine_arch_type == MACH_TYPE_HERO)
-#else
-# define machine_is_hero()	(0)
-#endif
-
-#ifdef CONFIG_MACH_OMAP_POSEIDON
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_OMAP_POSEIDON
-# endif
-# define machine_is_omap_poseidon()	(machine_arch_type == MACH_TYPE_OMAP_POSEIDON)
-#else
-# define machine_is_omap_poseidon()	(0)
-#endif
-
-#ifdef CONFIG_MACH_REALVIEW_PBX
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_REALVIEW_PBX
-# endif
-# define machine_is_realview_pbx()	(machine_arch_type == MACH_TYPE_REALVIEW_PBX)
-#else
-# define machine_is_realview_pbx()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MICRO9S
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MICRO9S
-# endif
-# define machine_is_micro9s()	(machine_arch_type == MACH_TYPE_MICRO9S)
-#else
-# define machine_is_micro9s()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MAKO
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MAKO
-# endif
-# define machine_is_mako()	(machine_arch_type == MACH_TYPE_MAKO)
-#else
-# define machine_is_mako()	(0)
-#endif
-
-#ifdef CONFIG_MACH_XDAFLAME
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_XDAFLAME
-# endif
-# define machine_is_xdaflame()	(machine_arch_type == MACH_TYPE_XDAFLAME)
-#else
-# define machine_is_xdaflame()	(0)
-#endif
-
-#ifdef CONFIG_MACH_PHIDGET_SBC2
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PHIDGET_SBC2
-# endif
-# define machine_is_phidget_sbc2()	(machine_arch_type == MACH_TYPE_PHIDGET_SBC2)
-#else
-# define machine_is_phidget_sbc2()	(0)
-#endif
-
-#ifdef CONFIG_MACH_LIMESTONE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_LIMESTONE
-# endif
-# define machine_is_limestone()	(machine_arch_type == MACH_TYPE_LIMESTONE)
-#else
-# define machine_is_limestone()	(0)
-#endif
-
-#ifdef CONFIG_MACH_IPROBE_C32
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_IPROBE_C32
-# endif
-# define machine_is_iprobe_c32()	(machine_arch_type == MACH_TYPE_IPROBE_C32)
-#else
-# define machine_is_iprobe_c32()	(0)
-#endif
-
-#ifdef CONFIG_MACH_RUT100
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_RUT100
-# endif
-# define machine_is_rut100()	(machine_arch_type == MACH_TYPE_RUT100)
-#else
-# define machine_is_rut100()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ASUSP535
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ASUSP535
-# endif
-# define machine_is_asusp535()	(machine_arch_type == MACH_TYPE_ASUSP535)
-#else
-# define machine_is_asusp535()	(0)
-#endif
-
-#ifdef CONFIG_MACH_HTCRAPHAEL
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_HTCRAPHAEL
-# endif
-# define machine_is_htcraphael()	(machine_arch_type == MACH_TYPE_HTCRAPHAEL)
-#else
-# define machine_is_htcraphael()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SYGDG1
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SYGDG1
-# endif
-# define machine_is_sygdg1()	(machine_arch_type == MACH_TYPE_SYGDG1)
-#else
-# define machine_is_sygdg1()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SYGDG2
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SYGDG2
-# endif
-# define machine_is_sygdg2()	(machine_arch_type == MACH_TYPE_SYGDG2)
-#else
-# define machine_is_sygdg2()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SEOUL
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SEOUL
-# endif
-# define machine_is_seoul()	(machine_arch_type == MACH_TYPE_SEOUL)
-#else
-# define machine_is_seoul()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SALERNO
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SALERNO
-# endif
-# define machine_is_salerno()	(machine_arch_type == MACH_TYPE_SALERNO)
-#else
-# define machine_is_salerno()	(0)
-#endif
-
-#ifdef CONFIG_MACH_UCN_S3C64XX
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_UCN_S3C64XX
-# endif
-# define machine_is_ucn_s3c64xx()	(machine_arch_type == MACH_TYPE_UCN_S3C64XX)
-#else
-# define machine_is_ucn_s3c64xx()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MSM7201A
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MSM7201A
-# endif
-# define machine_is_msm7201a()	(machine_arch_type == MACH_TYPE_MSM7201A)
-#else
-# define machine_is_msm7201a()	(0)
-#endif
-
-#ifdef CONFIG_MACH_LPR1
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_LPR1
-# endif
-# define machine_is_lpr1()	(machine_arch_type == MACH_TYPE_LPR1)
-#else
-# define machine_is_lpr1()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ARMADILLO500FX
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ARMADILLO500FX
-# endif
-# define machine_is_armadillo500fx()	(machine_arch_type == MACH_TYPE_ARMADILLO500FX)
-#else
-# define machine_is_armadillo500fx()	(0)
-#endif
-
-#ifdef CONFIG_MACH_G3EVM
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_G3EVM
-# endif
-# define machine_is_g3evm()	(machine_arch_type == MACH_TYPE_G3EVM)
-#else
-# define machine_is_g3evm()	(0)
-#endif
-
-#ifdef CONFIG_MACH_Z3_DM355
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_Z3_DM355
-# endif
-# define machine_is_z3_dm355()	(machine_arch_type == MACH_TYPE_Z3_DM355)
-#else
-# define machine_is_z3_dm355()	(0)
-#endif
-
-#ifdef CONFIG_MACH_W90P910EVB
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_W90P910EVB
-# endif
-# define machine_is_w90p910evb()	(machine_arch_type == MACH_TYPE_W90P910EVB)
-#else
-# define machine_is_w90p910evb()	(0)
-#endif
-
-#ifdef CONFIG_MACH_W90P920EVB
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_W90P920EVB
-# endif
-# define machine_is_w90p920evb()	(machine_arch_type == MACH_TYPE_W90P920EVB)
-#else
-# define machine_is_w90p920evb()	(0)
-#endif
-
-#ifdef CONFIG_MACH_W90P950EVB
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_W90P950EVB
-# endif
-# define machine_is_w90p950evb()	(machine_arch_type == MACH_TYPE_W90P950EVB)
-#else
-# define machine_is_w90p950evb()	(0)
-#endif
-
-#ifdef CONFIG_MACH_W90N960EVB
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_W90N960EVB
-# endif
-# define machine_is_w90n960evb()	(machine_arch_type == MACH_TYPE_W90N960EVB)
-#else
-# define machine_is_w90n960evb()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CAMHD
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CAMHD
-# endif
-# define machine_is_camhd()	(machine_arch_type == MACH_TYPE_CAMHD)
-#else
-# define machine_is_camhd()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MVC100
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MVC100
-# endif
-# define machine_is_mvc100()	(machine_arch_type == MACH_TYPE_MVC100)
-#else
-# define machine_is_mvc100()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ELECTRUM_200
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ELECTRUM_200
-# endif
-# define machine_is_electrum_200()	(machine_arch_type == MACH_TYPE_ELECTRUM_200)
-#else
-# define machine_is_electrum_200()	(0)
-#endif
-
-#ifdef CONFIG_MACH_HTCJADE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_HTCJADE
-# endif
-# define machine_is_htcjade()	(machine_arch_type == MACH_TYPE_HTCJADE)
-#else
-# define machine_is_htcjade()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MEMPHIS
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MEMPHIS
-# endif
-# define machine_is_memphis()	(machine_arch_type == MACH_TYPE_MEMPHIS)
-#else
-# define machine_is_memphis()	(0)
-#endif
-
-#ifdef CONFIG_MACH_IMX27SBC
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_IMX27SBC
-# endif
-# define machine_is_imx27sbc()	(machine_arch_type == MACH_TYPE_IMX27SBC)
-#else
-# define machine_is_imx27sbc()	(0)
-#endif
-
-#ifdef CONFIG_MACH_LEXTAR
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_LEXTAR
-# endif
-# define machine_is_lextar()	(machine_arch_type == MACH_TYPE_LEXTAR)
-#else
-# define machine_is_lextar()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MV88F6281GTW_GE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MV88F6281GTW_GE
-# endif
-# define machine_is_mv88f6281gtw_ge()	(machine_arch_type == MACH_TYPE_MV88F6281GTW_GE)
-#else
-# define machine_is_mv88f6281gtw_ge()	(0)
-#endif
-
-#ifdef CONFIG_MACH_NCP
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_NCP
-# endif
-# define machine_is_ncp()	(machine_arch_type == MACH_TYPE_NCP)
-#else
-# define machine_is_ncp()	(0)
-#endif
-
-#ifdef CONFIG_MACH_Z32AN
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_Z32AN
-# endif
-# define machine_is_z32an_series()	(machine_arch_type == MACH_TYPE_Z32AN)
-#else
-# define machine_is_z32an_series()	(0)
-#endif
-
-#ifdef CONFIG_MACH_TMQ_CAPD
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TMQ_CAPD
-# endif
-# define machine_is_tmq_capd()	(machine_arch_type == MACH_TYPE_TMQ_CAPD)
-#else
-# define machine_is_tmq_capd()	(0)
-#endif
-
-#ifdef CONFIG_MACH_OMAP3_WL
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_OMAP3_WL
-# endif
-# define machine_is_omap3_wl()	(machine_arch_type == MACH_TYPE_OMAP3_WL)
-#else
-# define machine_is_omap3_wl()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CHUMBY
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CHUMBY
-# endif
-# define machine_is_chumby()	(machine_arch_type == MACH_TYPE_CHUMBY)
-#else
-# define machine_is_chumby()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ATSARM9
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ATSARM9
-# endif
-# define machine_is_atsarm9()	(machine_arch_type == MACH_TYPE_ATSARM9)
-#else
-# define machine_is_atsarm9()	(0)
-#endif
-
-#ifdef CONFIG_MACH_DAVINCI_DM365_EVM
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_DAVINCI_DM365_EVM
-# endif
-# define machine_is_davinci_dm365_evm()	(machine_arch_type == MACH_TYPE_DAVINCI_DM365_EVM)
-#else
-# define machine_is_davinci_dm365_evm()	(0)
-#endif
-
-#ifdef CONFIG_MACH_BAHAMAS
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_BAHAMAS
-# endif
-# define machine_is_bahamas()	(machine_arch_type == MACH_TYPE_BAHAMAS)
-#else
-# define machine_is_bahamas()	(0)
-#endif
-
-#ifdef CONFIG_MACH_DAS
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_DAS
-# endif
-# define machine_is_das()	(machine_arch_type == MACH_TYPE_DAS)
-#else
-# define machine_is_das()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MINIDAS
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MINIDAS
-# endif
-# define machine_is_minidas()	(machine_arch_type == MACH_TYPE_MINIDAS)
-#else
-# define machine_is_minidas()	(0)
-#endif
-
-#ifdef CONFIG_MACH_VK1000
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_VK1000
-# endif
-# define machine_is_vk1000()	(machine_arch_type == MACH_TYPE_VK1000)
-#else
-# define machine_is_vk1000()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CENTRO
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CENTRO
-# endif
-# define machine_is_centro()	(machine_arch_type == MACH_TYPE_CENTRO)
-#else
-# define machine_is_centro()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CTERA_2BAY
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CTERA_2BAY
-# endif
-# define machine_is_ctera_2bay()	(machine_arch_type == MACH_TYPE_CTERA_2BAY)
-#else
-# define machine_is_ctera_2bay()	(0)
-#endif
-
-#ifdef CONFIG_MACH_EDGECONNECT
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_EDGECONNECT
-# endif
-# define machine_is_edgeconnect()	(machine_arch_type == MACH_TYPE_EDGECONNECT)
-#else
-# define machine_is_edgeconnect()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ND27000
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ND27000
-# endif
-# define machine_is_nd27000()	(machine_arch_type == MACH_TYPE_ND27000)
-#else
-# define machine_is_nd27000()	(0)
-#endif
-
-#ifdef CONFIG_MACH_GEMALTO_COBRA
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_GEMALTO_COBRA
-# endif
-# define machine_is_cobra()	(machine_arch_type == MACH_TYPE_GEMALTO_COBRA)
-#else
-# define machine_is_cobra()	(0)
-#endif
-
-#ifdef CONFIG_MACH_INGELABS_COMET
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_INGELABS_COMET
-# endif
-# define machine_is_ingelabs_comet()	(machine_arch_type == MACH_TYPE_INGELABS_COMET)
-#else
-# define machine_is_ingelabs_comet()	(0)
-#endif
-
-#ifdef CONFIG_MACH_POLLUX_WIZ
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_POLLUX_WIZ
-# endif
-# define machine_is_pollux_wiz()	(machine_arch_type == MACH_TYPE_POLLUX_WIZ)
-#else
-# define machine_is_pollux_wiz()	(0)
-#endif
-
-#ifdef CONFIG_MACH_BLACKSTONE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_BLACKSTONE
-# endif
-# define machine_is_blackstone()	(machine_arch_type == MACH_TYPE_BLACKSTONE)
-#else
-# define machine_is_blackstone()	(0)
-#endif
-
-#ifdef CONFIG_MACH_TOPAZ
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TOPAZ
-# endif
-# define machine_is_topaz()	(machine_arch_type == MACH_TYPE_TOPAZ)
-#else
-# define machine_is_topaz()	(0)
-#endif
-
-#ifdef CONFIG_MACH_AIXLE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_AIXLE
-# endif
-# define machine_is_aixle()	(machine_arch_type == MACH_TYPE_AIXLE)
-#else
-# define machine_is_aixle()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MW998
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MW998
-# endif
-# define machine_is_mw998()	(machine_arch_type == MACH_TYPE_MW998)
-#else
-# define machine_is_mw998()	(0)
-#endif
-
-#ifdef CONFIG_MACH_NOKIA_RX51
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_NOKIA_RX51
-# endif
-# define machine_is_nokia_rx51()	(machine_arch_type == MACH_TYPE_NOKIA_RX51)
-#else
-# define machine_is_nokia_rx51()	(0)
-#endif
-
-#ifdef CONFIG_MACH_VSC5605EV
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_VSC5605EV
-# endif
-# define machine_is_vsc5605ev()	(machine_arch_type == MACH_TYPE_VSC5605EV)
-#else
-# define machine_is_vsc5605ev()	(0)
-#endif
-
-#ifdef CONFIG_MACH_NT98700DK
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_NT98700DK
-# endif
-# define machine_is_nt98700dk()	(machine_arch_type == MACH_TYPE_NT98700DK)
-#else
-# define machine_is_nt98700dk()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ICONTACT
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ICONTACT
-# endif
-# define machine_is_icontact()	(machine_arch_type == MACH_TYPE_ICONTACT)
-#else
-# define machine_is_icontact()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SWARCO_FRCPU
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SWARCO_FRCPU
-# endif
-# define machine_is_swarco_frcpu()	(machine_arch_type == MACH_TYPE_SWARCO_FRCPU)
-#else
-# define machine_is_swarco_frcpu()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SWARCO_SCPU
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SWARCO_SCPU
-# endif
-# define machine_is_swarco_scpu()	(machine_arch_type == MACH_TYPE_SWARCO_SCPU)
-#else
-# define machine_is_swarco_scpu()	(0)
-#endif
-
-#ifdef CONFIG_MACH_BBOX_P16
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_BBOX_P16
-# endif
-# define machine_is_bbox_p16()	(machine_arch_type == MACH_TYPE_BBOX_P16)
-#else
-# define machine_is_bbox_p16()	(0)
-#endif
-
-#ifdef CONFIG_MACH_BSTD
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_BSTD
-# endif
-# define machine_is_bstd()	(machine_arch_type == MACH_TYPE_BSTD)
-#else
-# define machine_is_bstd()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SBC2440II
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SBC2440II
-# endif
-# define machine_is_sbc2440ii()	(machine_arch_type == MACH_TYPE_SBC2440II)
-#else
-# define machine_is_sbc2440ii()	(0)
-#endif
-
-#ifdef CONFIG_MACH_PCM034
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PCM034
-# endif
-# define machine_is_pcm034()	(machine_arch_type == MACH_TYPE_PCM034)
-#else
-# define machine_is_pcm034()	(0)
-#endif
-
-#ifdef CONFIG_MACH_NESO
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_NESO
-# endif
-# define machine_is_neso()	(machine_arch_type == MACH_TYPE_NESO)
-#else
-# define machine_is_neso()	(0)
-#endif
-
-#ifdef CONFIG_MACH_WLNX_9G20
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_WLNX_9G20
-# endif
-# define machine_is_wlnx_9g20()	(machine_arch_type == MACH_TYPE_WLNX_9G20)
-#else
-# define machine_is_wlnx_9g20()	(0)
-#endif
-
-#ifdef CONFIG_MACH_OMAP_ZOOM2
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_OMAP_ZOOM2
-# endif
-# define machine_is_omap_zoom2()	(machine_arch_type == MACH_TYPE_OMAP_ZOOM2)
-#else
-# define machine_is_omap_zoom2()	(0)
-#endif
-
-#ifdef CONFIG_MACH_TOTEMNOVA
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TOTEMNOVA
-# endif
-# define machine_is_totemnova()	(machine_arch_type == MACH_TYPE_TOTEMNOVA)
-#else
-# define machine_is_totemnova()	(0)
-#endif
-
-#ifdef CONFIG_MACH_C5000
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_C5000
-# endif
-# define machine_is_c5000()	(machine_arch_type == MACH_TYPE_C5000)
-#else
-# define machine_is_c5000()	(0)
-#endif
-
-#ifdef CONFIG_MACH_UNIPO_AT91SAM9263
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_UNIPO_AT91SAM9263
-# endif
-# define machine_is_unipo_at91sam9263()	(machine_arch_type == MACH_TYPE_UNIPO_AT91SAM9263)
-#else
-# define machine_is_unipo_at91sam9263()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ETHERNUT5
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ETHERNUT5
-# endif
-# define machine_is_ethernut5()	(machine_arch_type == MACH_TYPE_ETHERNUT5)
-#else
-# define machine_is_ethernut5()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ARM11
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ARM11
-# endif
-# define machine_is_arm11()	(machine_arch_type == MACH_TYPE_ARM11)
-#else
-# define machine_is_arm11()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CPUAT9260
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CPUAT9260
-# endif
-# define machine_is_cpuat9260()	(machine_arch_type == MACH_TYPE_CPUAT9260)
-#else
-# define machine_is_cpuat9260()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CPUPXA255
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CPUPXA255
-# endif
-# define machine_is_cpupxa255()	(machine_arch_type == MACH_TYPE_CPUPXA255)
-#else
-# define machine_is_cpupxa255()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CPUIMX27
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CPUIMX27
-# endif
-# define machine_is_eukrea_cpuimx27()	(machine_arch_type == MACH_TYPE_CPUIMX27)
-#else
-# define machine_is_eukrea_cpuimx27()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CHEFLUX
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CHEFLUX
-# endif
-# define machine_is_cheflux()	(machine_arch_type == MACH_TYPE_CHEFLUX)
-#else
-# define machine_is_cheflux()	(0)
-#endif
-
-#ifdef CONFIG_MACH_EB_CPUX9K2
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_EB_CPUX9K2
-# endif
-# define machine_is_eb_cpux9k2()	(machine_arch_type == MACH_TYPE_EB_CPUX9K2)
-#else
-# define machine_is_eb_cpux9k2()	(0)
-#endif
-
-#ifdef CONFIG_MACH_OPCOTEC
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_OPCOTEC
-# endif
-# define machine_is_opcotec()	(machine_arch_type == MACH_TYPE_OPCOTEC)
-#else
-# define machine_is_opcotec()	(0)
-#endif
-
-#ifdef CONFIG_MACH_YT
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_YT
-# endif
-# define machine_is_yt()	(machine_arch_type == MACH_TYPE_YT)
-#else
-# define machine_is_yt()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MOTOQ
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MOTOQ
-# endif
-# define machine_is_motoq()	(machine_arch_type == MACH_TYPE_MOTOQ)
-#else
-# define machine_is_motoq()	(0)
-#endif
-
-#ifdef CONFIG_MACH_BSB1
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_BSB1
-# endif
-# define machine_is_bsb1()	(machine_arch_type == MACH_TYPE_BSB1)
-#else
-# define machine_is_bsb1()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ACS5K
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ACS5K
-# endif
-# define machine_is_acs5k()	(machine_arch_type == MACH_TYPE_ACS5K)
-#else
-# define machine_is_acs5k()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MILAN
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MILAN
-# endif
-# define machine_is_milan()	(machine_arch_type == MACH_TYPE_MILAN)
-#else
-# define machine_is_milan()	(0)
-#endif
-
-#ifdef CONFIG_MACH_QUARTZV2
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_QUARTZV2
-# endif
-# define machine_is_quartzv2()	(machine_arch_type == MACH_TYPE_QUARTZV2)
-#else
-# define machine_is_quartzv2()	(0)
-#endif
-
-#ifdef CONFIG_MACH_RSVP
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_RSVP
-# endif
-# define machine_is_rsvp()	(machine_arch_type == MACH_TYPE_RSVP)
-#else
-# define machine_is_rsvp()	(0)
-#endif
-
-#ifdef CONFIG_MACH_RMP200
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_RMP200
-# endif
-# define machine_is_rmp200()	(machine_arch_type == MACH_TYPE_RMP200)
-#else
-# define machine_is_rmp200()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SNAPPER_9260
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SNAPPER_9260
-# endif
-# define machine_is_snapper_9260()	(machine_arch_type == MACH_TYPE_SNAPPER_9260)
-#else
-# define machine_is_snapper_9260()	(0)
-#endif
-
-#ifdef CONFIG_MACH_DSM320
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_DSM320
-# endif
-# define machine_is_dsm320()	(machine_arch_type == MACH_TYPE_DSM320)
-#else
-# define machine_is_dsm320()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ADSGCM
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ADSGCM
-# endif
-# define machine_is_adsgcm()	(machine_arch_type == MACH_TYPE_ADSGCM)
-#else
-# define machine_is_adsgcm()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ASE2_400
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ASE2_400
-# endif
-# define machine_is_ase2_400()	(machine_arch_type == MACH_TYPE_ASE2_400)
-#else
-# define machine_is_ase2_400()	(0)
-#endif
-
-#ifdef CONFIG_MACH_PIZZA
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PIZZA
-# endif
-# define machine_is_pizza()	(machine_arch_type == MACH_TYPE_PIZZA)
-#else
-# define machine_is_pizza()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SPOT_NGPL
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SPOT_NGPL
-# endif
-# define machine_is_spot_ngpl()	(machine_arch_type == MACH_TYPE_SPOT_NGPL)
-#else
-# define machine_is_spot_ngpl()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ARMATA
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ARMATA
-# endif
-# define machine_is_armata()	(machine_arch_type == MACH_TYPE_ARMATA)
-#else
-# define machine_is_armata()	(0)
-#endif
-
-#ifdef CONFIG_MACH_EXEDA
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_EXEDA
-# endif
-# define machine_is_exeda()	(machine_arch_type == MACH_TYPE_EXEDA)
-#else
-# define machine_is_exeda()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MX31SF005
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MX31SF005
-# endif
-# define machine_is_mx31sf005()	(machine_arch_type == MACH_TYPE_MX31SF005)
-#else
-# define machine_is_mx31sf005()	(0)
-#endif
-
-#ifdef CONFIG_MACH_F5D8231_4_V2
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_F5D8231_4_V2
-# endif
-# define machine_is_f5d8231_4_v2()	(machine_arch_type == MACH_TYPE_F5D8231_4_V2)
-#else
-# define machine_is_f5d8231_4_v2()	(0)
-#endif
-
-#ifdef CONFIG_MACH_Q2440
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_Q2440
-# endif
-# define machine_is_q2440()	(machine_arch_type == MACH_TYPE_Q2440)
-#else
-# define machine_is_q2440()	(0)
-#endif
-
-#ifdef CONFIG_MACH_QQ2440
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_QQ2440
-# endif
-# define machine_is_qq2440()	(machine_arch_type == MACH_TYPE_QQ2440)
-#else
-# define machine_is_qq2440()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MINI2440
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MINI2440
-# endif
-# define machine_is_mini2440()	(machine_arch_type == MACH_TYPE_MINI2440)
-#else
-# define machine_is_mini2440()	(0)
-#endif
-
-#ifdef CONFIG_MACH_COLIBRI300
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_COLIBRI300
-# endif
-# define machine_is_colibri300()	(machine_arch_type == MACH_TYPE_COLIBRI300)
-#else
-# define machine_is_colibri300()	(0)
-#endif
-
-#ifdef CONFIG_MACH_JADES
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_JADES
-# endif
-# define machine_is_jades()	(machine_arch_type == MACH_TYPE_JADES)
-#else
-# define machine_is_jades()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SPARK
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SPARK
-# endif
-# define machine_is_spark()	(machine_arch_type == MACH_TYPE_SPARK)
-#else
-# define machine_is_spark()	(0)
-#endif
-
-#ifdef CONFIG_MACH_BENZINA
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_BENZINA
-# endif
-# define machine_is_benzina()	(machine_arch_type == MACH_TYPE_BENZINA)
-#else
-# define machine_is_benzina()	(0)
-#endif
-
-#ifdef CONFIG_MACH_BLAZE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_BLAZE
-# endif
-# define machine_is_blaze()	(machine_arch_type == MACH_TYPE_BLAZE)
-#else
-# define machine_is_blaze()	(0)
-#endif
-
-#ifdef CONFIG_MACH_LINKSTATION_LS_HGL
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_LINKSTATION_LS_HGL
-# endif
-# define machine_is_linkstation_ls_hgl()	(machine_arch_type == MACH_TYPE_LINKSTATION_LS_HGL)
-#else
-# define machine_is_linkstation_ls_hgl()	(0)
-#endif
-
-#ifdef CONFIG_MACH_HTCKOVSKY
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_HTCKOVSKY
-# endif
-# define machine_is_htckovsky()	(machine_arch_type == MACH_TYPE_HTCKOVSKY)
-#else
-# define machine_is_htckovsky()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SONY_PRS505
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SONY_PRS505
-# endif
-# define machine_is_sony_prs505()	(machine_arch_type == MACH_TYPE_SONY_PRS505)
-#else
-# define machine_is_sony_prs505()	(0)
-#endif
-
-#ifdef CONFIG_MACH_HANLIN_V3
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_HANLIN_V3
-# endif
-# define machine_is_hanlin_v3()	(machine_arch_type == MACH_TYPE_HANLIN_V3)
-#else
-# define machine_is_hanlin_v3()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SAPPHIRA
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SAPPHIRA
-# endif
-# define machine_is_sapphira()	(machine_arch_type == MACH_TYPE_SAPPHIRA)
-#else
-# define machine_is_sapphira()	(0)
-#endif
-
-#ifdef CONFIG_MACH_DACK_SDA_01
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_DACK_SDA_01
-# endif
-# define machine_is_dack_sda_01()	(machine_arch_type == MACH_TYPE_DACK_SDA_01)
-#else
-# define machine_is_dack_sda_01()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ARMBOX
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ARMBOX
-# endif
-# define machine_is_armbox()	(machine_arch_type == MACH_TYPE_ARMBOX)
-#else
-# define machine_is_armbox()	(0)
-#endif
-
-#ifdef CONFIG_MACH_HARRIS_RVP
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_HARRIS_RVP
-# endif
-# define machine_is_harris_rvp()	(machine_arch_type == MACH_TYPE_HARRIS_RVP)
-#else
-# define machine_is_harris_rvp()	(0)
-#endif
-
-#ifdef CONFIG_MACH_RIBALDO
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_RIBALDO
-# endif
-# define machine_is_ribaldo()	(machine_arch_type == MACH_TYPE_RIBALDO)
-#else
-# define machine_is_ribaldo()	(0)
-#endif
-
-#ifdef CONFIG_MACH_AGORA
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_AGORA
-# endif
-# define machine_is_agora()	(machine_arch_type == MACH_TYPE_AGORA)
-#else
-# define machine_is_agora()	(0)
-#endif
-
-#ifdef CONFIG_MACH_OMAP3_MINI
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_OMAP3_MINI
-# endif
-# define machine_is_omap3_mini()	(machine_arch_type == MACH_TYPE_OMAP3_MINI)
-#else
-# define machine_is_omap3_mini()	(0)
-#endif
-
-#ifdef CONFIG_MACH_A9SAM6432_B
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_A9SAM6432_B
-# endif
-# define machine_is_a9sam6432_b()	(machine_arch_type == MACH_TYPE_A9SAM6432_B)
-#else
-# define machine_is_a9sam6432_b()	(0)
-#endif
-
-#ifdef CONFIG_MACH_USG2410
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_USG2410
-# endif
-# define machine_is_usg2410()	(machine_arch_type == MACH_TYPE_USG2410)
-#else
-# define machine_is_usg2410()	(0)
-#endif
-
-#ifdef CONFIG_MACH_PC72052_I10_REVB
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PC72052_I10_REVB
-# endif
-# define machine_is_pc72052_i10_revb()	(machine_arch_type == MACH_TYPE_PC72052_I10_REVB)
-#else
-# define machine_is_pc72052_i10_revb()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MX35_EXM32
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MX35_EXM32
-# endif
-# define machine_is_mx35_exm32()	(machine_arch_type == MACH_TYPE_MX35_EXM32)
-#else
-# define machine_is_mx35_exm32()	(0)
-#endif
-
-#ifdef CONFIG_MACH_TOPAS910
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TOPAS910
-# endif
-# define machine_is_topas910()	(machine_arch_type == MACH_TYPE_TOPAS910)
-#else
-# define machine_is_topas910()	(0)
-#endif
-
-#ifdef CONFIG_MACH_HYENA
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_HYENA
-# endif
-# define machine_is_hyena()	(machine_arch_type == MACH_TYPE_HYENA)
-#else
-# define machine_is_hyena()	(0)
-#endif
-
-#ifdef CONFIG_MACH_POSPAX
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_POSPAX
-# endif
-# define machine_is_pospax()	(machine_arch_type == MACH_TYPE_POSPAX)
-#else
-# define machine_is_pospax()	(0)
-#endif
-
-#ifdef CONFIG_MACH_HDL_GX
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_HDL_GX
-# endif
-# define machine_is_hdl_gx()	(machine_arch_type == MACH_TYPE_HDL_GX)
-#else
-# define machine_is_hdl_gx()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CTERA_4BAY
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CTERA_4BAY
-# endif
-# define machine_is_ctera_4bay()	(machine_arch_type == MACH_TYPE_CTERA_4BAY)
-#else
-# define machine_is_ctera_4bay()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CTERA_PLUG_C
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CTERA_PLUG_C
-# endif
-# define machine_is_ctera_plug_c()	(machine_arch_type == MACH_TYPE_CTERA_PLUG_C)
-#else
-# define machine_is_ctera_plug_c()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CRWEA_PLUG_I
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CRWEA_PLUG_I
-# endif
-# define machine_is_crwea_plug_i()	(machine_arch_type == MACH_TYPE_CRWEA_PLUG_I)
-#else
-# define machine_is_crwea_plug_i()	(0)
-#endif
-
-#ifdef CONFIG_MACH_EGAUGE2
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_EGAUGE2
-# endif
-# define machine_is_egauge2()	(machine_arch_type == MACH_TYPE_EGAUGE2)
-#else
-# define machine_is_egauge2()	(0)
-#endif
-
-#ifdef CONFIG_MACH_DIDJ
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_DIDJ
-# endif
-# define machine_is_didj()	(machine_arch_type == MACH_TYPE_DIDJ)
-#else
-# define machine_is_didj()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MEISTER
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MEISTER
-# endif
-# define machine_is_m_s3c2443()	(machine_arch_type == MACH_TYPE_MEISTER)
-#else
-# define machine_is_m_s3c2443()	(0)
-#endif
-
-#ifdef CONFIG_MACH_HTCBLACKSTONE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_HTCBLACKSTONE
-# endif
-# define machine_is_htcblackstone()	(machine_arch_type == MACH_TYPE_HTCBLACKSTONE)
-#else
-# define machine_is_htcblackstone()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CPUAT9G20
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CPUAT9G20
-# endif
-# define machine_is_cpuat9g20()	(machine_arch_type == MACH_TYPE_CPUAT9G20)
-#else
-# define machine_is_cpuat9g20()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SMDK6440
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SMDK6440
-# endif
-# define machine_is_smdk6440()	(machine_arch_type == MACH_TYPE_SMDK6440)
-#else
-# define machine_is_smdk6440()	(0)
-#endif
-
-#ifdef CONFIG_MACH_OMAP_35XX_MVP
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_OMAP_35XX_MVP
-# endif
-# define machine_is_omap_35xx_mvp()	(machine_arch_type == MACH_TYPE_OMAP_35XX_MVP)
-#else
-# define machine_is_omap_35xx_mvp()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CTERA_PLUG_I
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CTERA_PLUG_I
-# endif
-# define machine_is_ctera_plug_i()	(machine_arch_type == MACH_TYPE_CTERA_PLUG_I)
-#else
-# define machine_is_ctera_plug_i()	(0)
-#endif
-
-#ifdef CONFIG_MACH_PVG610
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PVG610
-# endif
-# define machine_is_pvg610_100()	(machine_arch_type == MACH_TYPE_PVG610)
-#else
-# define machine_is_pvg610_100()	(0)
-#endif
-
-#ifdef CONFIG_MACH_HPRW6815
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_HPRW6815
-# endif
-# define machine_is_hprw6815()	(machine_arch_type == MACH_TYPE_HPRW6815)
-#else
-# define machine_is_hprw6815()	(0)
-#endif
-
-#ifdef CONFIG_MACH_OMAP3_OSWALD
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_OMAP3_OSWALD
-# endif
-# define machine_is_omap3_oswald()	(machine_arch_type == MACH_TYPE_OMAP3_OSWALD)
-#else
-# define machine_is_omap3_oswald()	(0)
-#endif
-
-#ifdef CONFIG_MACH_NAS4220B
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_NAS4220B
-# endif
-# define machine_is_nas4220b()	(machine_arch_type == MACH_TYPE_NAS4220B)
-#else
-# define machine_is_nas4220b()	(0)
-#endif
-
-#ifdef CONFIG_MACH_HTCRAPHAEL_CDMA
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_HTCRAPHAEL_CDMA
-# endif
-# define machine_is_htcraphael_cdma()	(machine_arch_type == MACH_TYPE_HTCRAPHAEL_CDMA)
-#else
-# define machine_is_htcraphael_cdma()	(0)
-#endif
-
-#ifdef CONFIG_MACH_HTCDIAMOND_CDMA
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_HTCDIAMOND_CDMA
-# endif
-# define machine_is_htcdiamond_cdma()	(machine_arch_type == MACH_TYPE_HTCDIAMOND_CDMA)
-#else
-# define machine_is_htcdiamond_cdma()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SCALER
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SCALER
-# endif
-# define machine_is_scaler()	(machine_arch_type == MACH_TYPE_SCALER)
-#else
-# define machine_is_scaler()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ZYLONITE2
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ZYLONITE2
-# endif
-# define machine_is_zylonite2()	(machine_arch_type == MACH_TYPE_ZYLONITE2)
-#else
-# define machine_is_zylonite2()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ASPENITE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ASPENITE
-# endif
-# define machine_is_aspenite()	(machine_arch_type == MACH_TYPE_ASPENITE)
-#else
-# define machine_is_aspenite()	(0)
-#endif
-
-#ifdef CONFIG_MACH_TETON
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TETON
-# endif
-# define machine_is_teton()	(machine_arch_type == MACH_TYPE_TETON)
-#else
-# define machine_is_teton()	(0)
-#endif
-
-#ifdef CONFIG_MACH_TTC_DKB
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TTC_DKB
-# endif
-# define machine_is_ttc_dkb()	(machine_arch_type == MACH_TYPE_TTC_DKB)
-#else
-# define machine_is_ttc_dkb()	(0)
-#endif
-
-#ifdef CONFIG_MACH_BISHOP2
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_BISHOP2
-# endif
-# define machine_is_bishop2()	(machine_arch_type == MACH_TYPE_BISHOP2)
-#else
-# define machine_is_bishop2()	(0)
-#endif
-
-#ifdef CONFIG_MACH_IPPV5
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_IPPV5
-# endif
-# define machine_is_ippv5()	(machine_arch_type == MACH_TYPE_IPPV5)
-#else
-# define machine_is_ippv5()	(0)
-#endif
-
-#ifdef CONFIG_MACH_FARM926
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_FARM926
-# endif
-# define machine_is_farm926()	(machine_arch_type == MACH_TYPE_FARM926)
-#else
-# define machine_is_farm926()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MMCCPU
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MMCCPU
-# endif
-# define machine_is_mmccpu()	(machine_arch_type == MACH_TYPE_MMCCPU)
-#else
-# define machine_is_mmccpu()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SGMSFL
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SGMSFL
-# endif
-# define machine_is_sgmsfl()	(machine_arch_type == MACH_TYPE_SGMSFL)
-#else
-# define machine_is_sgmsfl()	(0)
-#endif
-
-#ifdef CONFIG_MACH_TT8000
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TT8000
-# endif
-# define machine_is_tt8000()	(machine_arch_type == MACH_TYPE_TT8000)
-#else
-# define machine_is_tt8000()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ZRN4300LP
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ZRN4300LP
-# endif
-# define machine_is_zrn4300lp()	(machine_arch_type == MACH_TYPE_ZRN4300LP)
-#else
-# define machine_is_zrn4300lp()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MPTC
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MPTC
-# endif
-# define machine_is_mptc()	(machine_arch_type == MACH_TYPE_MPTC)
-#else
-# define machine_is_mptc()	(0)
-#endif
-
-#ifdef CONFIG_MACH_H6051
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_H6051
-# endif
-# define machine_is_h6051()	(machine_arch_type == MACH_TYPE_H6051)
-#else
-# define machine_is_h6051()	(0)
-#endif
-
-#ifdef CONFIG_MACH_PVG610_101
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PVG610_101
-# endif
-# define machine_is_pvg610_101()	(machine_arch_type == MACH_TYPE_PVG610_101)
-#else
-# define machine_is_pvg610_101()	(0)
-#endif
-
-#ifdef CONFIG_MACH_STAMP9261_PC_EVB
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_STAMP9261_PC_EVB
-# endif
-# define machine_is_stamp9261_pc_evb()	(machine_arch_type == MACH_TYPE_STAMP9261_PC_EVB)
-#else
-# define machine_is_stamp9261_pc_evb()	(0)
-#endif
-
-#ifdef CONFIG_MACH_PELCO_ODYSSEUS
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PELCO_ODYSSEUS
-# endif
-# define machine_is_pelco_odysseus()	(machine_arch_type == MACH_TYPE_PELCO_ODYSSEUS)
-#else
-# define machine_is_pelco_odysseus()	(0)
-#endif
-
-#ifdef CONFIG_MACH_TNY_A9260
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TNY_A9260
-# endif
-# define machine_is_tny_a9260()	(machine_arch_type == MACH_TYPE_TNY_A9260)
-#else
-# define machine_is_tny_a9260()	(0)
-#endif
-
-#ifdef CONFIG_MACH_TNY_A9G20
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TNY_A9G20
-# endif
-# define machine_is_tny_a9g20()	(machine_arch_type == MACH_TYPE_TNY_A9G20)
-#else
-# define machine_is_tny_a9g20()	(0)
-#endif
-
-#ifdef CONFIG_MACH_AESOP_MP2530F
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_AESOP_MP2530F
-# endif
-# define machine_is_aesop_mp2530f()	(machine_arch_type == MACH_TYPE_AESOP_MP2530F)
-#else
-# define machine_is_aesop_mp2530f()	(0)
-#endif
-
-#ifdef CONFIG_MACH_DX900
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_DX900
-# endif
-# define machine_is_dx900()	(machine_arch_type == MACH_TYPE_DX900)
-#else
-# define machine_is_dx900()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CPODC2
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CPODC2
-# endif
-# define machine_is_cpodc2()	(machine_arch_type == MACH_TYPE_CPODC2)
-#else
-# define machine_is_cpodc2()	(0)
-#endif
-
-#ifdef CONFIG_MACH_TILT_8925
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TILT_8925
-# endif
-# define machine_is_tilt_8925()	(machine_arch_type == MACH_TYPE_TILT_8925)
-#else
-# define machine_is_tilt_8925()	(0)
-#endif
-
-#ifdef CONFIG_MACH_DAVINCI_DM357_EVM
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_DAVINCI_DM357_EVM
-# endif
-# define machine_is_davinci_dm357_evm()	(machine_arch_type == MACH_TYPE_DAVINCI_DM357_EVM)
-#else
-# define machine_is_davinci_dm357_evm()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SWORDFISH
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SWORDFISH
-# endif
-# define machine_is_swordfish()	(machine_arch_type == MACH_TYPE_SWORDFISH)
-#else
-# define machine_is_swordfish()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CORVUS
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CORVUS
-# endif
-# define machine_is_corvus()	(machine_arch_type == MACH_TYPE_CORVUS)
-#else
-# define machine_is_corvus()	(0)
-#endif
-
-#ifdef CONFIG_MACH_TAURUS
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TAURUS
-# endif
-# define machine_is_taurus()	(machine_arch_type == MACH_TYPE_TAURUS)
-#else
-# define machine_is_taurus()	(0)
-#endif
-
-#ifdef CONFIG_MACH_AXM
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_AXM
-# endif
-# define machine_is_axm()	(machine_arch_type == MACH_TYPE_AXM)
-#else
-# define machine_is_axm()	(0)
-#endif
-
-#ifdef CONFIG_MACH_AXC
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_AXC
-# endif
-# define machine_is_axc()	(machine_arch_type == MACH_TYPE_AXC)
-#else
-# define machine_is_axc()	(0)
-#endif
-
-#ifdef CONFIG_MACH_BABY
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_BABY
-# endif
-# define machine_is_baby()	(machine_arch_type == MACH_TYPE_BABY)
-#else
-# define machine_is_baby()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MP200
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MP200
-# endif
-# define machine_is_mp200()	(machine_arch_type == MACH_TYPE_MP200)
-#else
-# define machine_is_mp200()	(0)
-#endif
-
-#ifdef CONFIG_MACH_PCM043
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PCM043
-# endif
-# define machine_is_pcm043()	(machine_arch_type == MACH_TYPE_PCM043)
-#else
-# define machine_is_pcm043()	(0)
-#endif
-
-#ifdef CONFIG_MACH_HANLIN_V3C
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_HANLIN_V3C
-# endif
-# define machine_is_hanlin_v3c()	(machine_arch_type == MACH_TYPE_HANLIN_V3C)
-#else
-# define machine_is_hanlin_v3c()	(0)
-#endif
-
-#ifdef CONFIG_MACH_KBK9G20
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_KBK9G20
-# endif
-# define machine_is_kbk9g20()	(machine_arch_type == MACH_TYPE_KBK9G20)
-#else
-# define machine_is_kbk9g20()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ADSTURBOG5
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ADSTURBOG5
-# endif
-# define machine_is_adsturbog5()	(machine_arch_type == MACH_TYPE_ADSTURBOG5)
-#else
-# define machine_is_adsturbog5()	(0)
-#endif
-
-#ifdef CONFIG_MACH_AVENGER_LITE1
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_AVENGER_LITE1
-# endif
-# define machine_is_avenger_lite1()	(machine_arch_type == MACH_TYPE_AVENGER_LITE1)
-#else
-# define machine_is_avenger_lite1()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SUC
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SUC
-# endif
-# define machine_is_suc82x()	(machine_arch_type == MACH_TYPE_SUC)
-#else
-# define machine_is_suc82x()	(0)
-#endif
-
-#ifdef CONFIG_MACH_AT91SAM7S256
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_AT91SAM7S256
-# endif
-# define machine_is_at91sam7s256()	(machine_arch_type == MACH_TYPE_AT91SAM7S256)
-#else
-# define machine_is_at91sam7s256()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MENDOZA
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MENDOZA
-# endif
-# define machine_is_mendoza()	(machine_arch_type == MACH_TYPE_MENDOZA)
-#else
-# define machine_is_mendoza()	(0)
-#endif
-
-#ifdef CONFIG_MACH_KIRA
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_KIRA
-# endif
-# define machine_is_kira()	(machine_arch_type == MACH_TYPE_KIRA)
-#else
-# define machine_is_kira()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MX1HBM
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MX1HBM
-# endif
-# define machine_is_mx1hbm()	(machine_arch_type == MACH_TYPE_MX1HBM)
-#else
-# define machine_is_mx1hbm()	(0)
-#endif
-
-#ifdef CONFIG_MACH_QUATRO43XX
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_QUATRO43XX
-# endif
-# define machine_is_quatro43xx()	(machine_arch_type == MACH_TYPE_QUATRO43XX)
-#else
-# define machine_is_quatro43xx()	(0)
-#endif
-
-#ifdef CONFIG_MACH_QUATRO4230
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_QUATRO4230
-# endif
-# define machine_is_quatro4230()	(machine_arch_type == MACH_TYPE_QUATRO4230)
-#else
-# define machine_is_quatro4230()	(0)
-#endif
-
-#ifdef CONFIG_MACH_NSB400
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_NSB400
-# endif
-# define machine_is_nsb400()	(machine_arch_type == MACH_TYPE_NSB400)
-#else
-# define machine_is_nsb400()	(0)
-#endif
-
-#ifdef CONFIG_MACH_DRP255
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_DRP255
-# endif
-# define machine_is_drp255()	(machine_arch_type == MACH_TYPE_DRP255)
-#else
-# define machine_is_drp255()	(0)
-#endif
-
-#ifdef CONFIG_MACH_THOTH
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_THOTH
-# endif
-# define machine_is_thoth()	(machine_arch_type == MACH_TYPE_THOTH)
-#else
-# define machine_is_thoth()	(0)
-#endif
-
-#ifdef CONFIG_MACH_FIRESTONE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_FIRESTONE
-# endif
-# define machine_is_firestone()	(machine_arch_type == MACH_TYPE_FIRESTONE)
-#else
-# define machine_is_firestone()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ASUSP750
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ASUSP750
-# endif
-# define machine_is_asusp750()	(machine_arch_type == MACH_TYPE_ASUSP750)
-#else
-# define machine_is_asusp750()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CTERA_DL
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CTERA_DL
-# endif
-# define machine_is_ctera_dl()	(machine_arch_type == MACH_TYPE_CTERA_DL)
-#else
-# define machine_is_ctera_dl()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SOCR
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SOCR
-# endif
-# define machine_is_socr()	(machine_arch_type == MACH_TYPE_SOCR)
-#else
-# define machine_is_socr()	(0)
-#endif
-
-#ifdef CONFIG_MACH_HTCOXYGEN
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_HTCOXYGEN
-# endif
-# define machine_is_htcoxygen()	(machine_arch_type == MACH_TYPE_HTCOXYGEN)
-#else
-# define machine_is_htcoxygen()	(0)
-#endif
-
-#ifdef CONFIG_MACH_HEROC
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_HEROC
-# endif
-# define machine_is_heroc()	(machine_arch_type == MACH_TYPE_HEROC)
-#else
-# define machine_is_heroc()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ZENO6800
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ZENO6800
-# endif
-# define machine_is_zeno6800()	(machine_arch_type == MACH_TYPE_ZENO6800)
-#else
-# define machine_is_zeno6800()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SC2MCS
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SC2MCS
-# endif
-# define machine_is_sc2mcs()	(machine_arch_type == MACH_TYPE_SC2MCS)
-#else
-# define machine_is_sc2mcs()	(0)
-#endif
-
-#ifdef CONFIG_MACH_GENE100
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_GENE100
-# endif
-# define machine_is_gene100()	(machine_arch_type == MACH_TYPE_GENE100)
-#else
-# define machine_is_gene100()	(0)
-#endif
-
-#ifdef CONFIG_MACH_AS353X
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_AS353X
-# endif
-# define machine_is_as353x()	(machine_arch_type == MACH_TYPE_AS353X)
-#else
-# define machine_is_as353x()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SHEEVAPLUG
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SHEEVAPLUG
-# endif
-# define machine_is_sheevaplug()	(machine_arch_type == MACH_TYPE_SHEEVAPLUG)
-#else
-# define machine_is_sheevaplug()	(0)
-#endif
-
-#ifdef CONFIG_MACH_AT91SAM9G20
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_AT91SAM9G20
-# endif
-# define machine_is_at91sam9g20()	(machine_arch_type == MACH_TYPE_AT91SAM9G20)
-#else
-# define machine_is_at91sam9g20()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MV88F6192GTW_FE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MV88F6192GTW_FE
-# endif
-# define machine_is_mv88f6192gtw_fe()	(machine_arch_type == MACH_TYPE_MV88F6192GTW_FE)
-#else
-# define machine_is_mv88f6192gtw_fe()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CC9200
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CC9200
-# endif
-# define machine_is_cc9200()	(machine_arch_type == MACH_TYPE_CC9200)
-#else
-# define machine_is_cc9200()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SM9200
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SM9200
-# endif
-# define machine_is_sm9200()	(machine_arch_type == MACH_TYPE_SM9200)
-#else
-# define machine_is_sm9200()	(0)
-#endif
-
-#ifdef CONFIG_MACH_TP9200
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TP9200
-# endif
-# define machine_is_tp9200()	(machine_arch_type == MACH_TYPE_TP9200)
-#else
-# define machine_is_tp9200()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SNAPPERDV
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SNAPPERDV
-# endif
-# define machine_is_snapperdv()	(machine_arch_type == MACH_TYPE_SNAPPERDV)
-#else
-# define machine_is_snapperdv()	(0)
-#endif
-
-#ifdef CONFIG_MACH_AVENGERS_LITE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_AVENGERS_LITE
-# endif
-# define machine_is_avengers_lite()	(machine_arch_type == MACH_TYPE_AVENGERS_LITE)
-#else
-# define machine_is_avengers_lite()	(0)
-#endif
-
-#ifdef CONFIG_MACH_AVENGERS_LITE1
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_AVENGERS_LITE1
-# endif
-# define machine_is_avengers_lite1()	(machine_arch_type == MACH_TYPE_AVENGERS_LITE1)
-#else
-# define machine_is_avengers_lite1()	(0)
-#endif
-
-#ifdef CONFIG_MACH_OMAP3AXON
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_OMAP3AXON
-# endif
-# define machine_is_omap3axon()	(machine_arch_type == MACH_TYPE_OMAP3AXON)
-#else
-# define machine_is_omap3axon()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MA8XX
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MA8XX
-# endif
-# define machine_is_ma8xx()	(machine_arch_type == MACH_TYPE_MA8XX)
-#else
-# define machine_is_ma8xx()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MP201EK
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MP201EK
-# endif
-# define machine_is_mp201ek()	(machine_arch_type == MACH_TYPE_MP201EK)
-#else
-# define machine_is_mp201ek()	(0)
-#endif
-
-#ifdef CONFIG_MACH_DAVINCI_TUX
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_DAVINCI_TUX
-# endif
-# define machine_is_davinci_tux()	(machine_arch_type == MACH_TYPE_DAVINCI_TUX)
-#else
-# define machine_is_davinci_tux()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MPA1600
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MPA1600
-# endif
-# define machine_is_mpa1600()	(machine_arch_type == MACH_TYPE_MPA1600)
-#else
-# define machine_is_mpa1600()	(0)
-#endif
-
-#ifdef CONFIG_MACH_PELCO_TROY
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PELCO_TROY
-# endif
-# define machine_is_pelco_troy()	(machine_arch_type == MACH_TYPE_PELCO_TROY)
-#else
-# define machine_is_pelco_troy()	(0)
-#endif
-
-#ifdef CONFIG_MACH_NSB667
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_NSB667
-# endif
-# define machine_is_nsb667()	(machine_arch_type == MACH_TYPE_NSB667)
-#else
-# define machine_is_nsb667()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ROVERS5_4MPIX
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ROVERS5_4MPIX
-# endif
-# define machine_is_rovers5_4mpix()	(machine_arch_type == MACH_TYPE_ROVERS5_4MPIX)
-#else
-# define machine_is_rovers5_4mpix()	(0)
-#endif
-
-#ifdef CONFIG_MACH_TWOCOM
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TWOCOM
-# endif
-# define machine_is_twocom()	(machine_arch_type == MACH_TYPE_TWOCOM)
-#else
-# define machine_is_twocom()	(0)
-#endif
-
-#ifdef CONFIG_MACH_UBISYS_P9_RCU3R2
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_UBISYS_P9_RCU3R2
-# endif
-# define machine_is_ubisys_p9_rcu3r2()	(machine_arch_type == MACH_TYPE_UBISYS_P9_RCU3R2)
-#else
-# define machine_is_ubisys_p9_rcu3r2()	(0)
-#endif
-
-#ifdef CONFIG_MACH_HERO_ESPRESSO
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_HERO_ESPRESSO
-# endif
-# define machine_is_hero_espresso()	(machine_arch_type == MACH_TYPE_HERO_ESPRESSO)
-#else
-# define machine_is_hero_espresso()	(0)
-#endif
-
-#ifdef CONFIG_MACH_AFEUSB
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_AFEUSB
-# endif
-# define machine_is_afeusb()	(machine_arch_type == MACH_TYPE_AFEUSB)
-#else
-# define machine_is_afeusb()	(0)
-#endif
-
-#ifdef CONFIG_MACH_T830
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_T830
-# endif
-# define machine_is_t830()	(machine_arch_type == MACH_TYPE_T830)
-#else
-# define machine_is_t830()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SPD8020_CC
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SPD8020_CC
-# endif
-# define machine_is_spd8020_cc()	(machine_arch_type == MACH_TYPE_SPD8020_CC)
-#else
-# define machine_is_spd8020_cc()	(0)
-#endif
-
-#ifdef CONFIG_MACH_OM_3D7K
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_OM_3D7K
-# endif
-# define machine_is_om_3d7k()	(machine_arch_type == MACH_TYPE_OM_3D7K)
-#else
-# define machine_is_om_3d7k()	(0)
-#endif
-
-#ifdef CONFIG_MACH_PICOCOM2
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PICOCOM2
-# endif
-# define machine_is_picocom2()	(machine_arch_type == MACH_TYPE_PICOCOM2)
-#else
-# define machine_is_picocom2()	(0)
-#endif
-
-#ifdef CONFIG_MACH_UWG4MX27
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_UWG4MX27
-# endif
-# define machine_is_uwg4mx27()	(machine_arch_type == MACH_TYPE_UWG4MX27)
-#else
-# define machine_is_uwg4mx27()	(0)
-#endif
-
-#ifdef CONFIG_MACH_UWG4MX31
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_UWG4MX31
-# endif
-# define machine_is_uwg4mx31()	(machine_arch_type == MACH_TYPE_UWG4MX31)
-#else
-# define machine_is_uwg4mx31()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CHERRY
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CHERRY
-# endif
-# define machine_is_cherry()	(machine_arch_type == MACH_TYPE_CHERRY)
-#else
-# define machine_is_cherry()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MX51_BABBAGE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MX51_BABBAGE
-# endif
-# define machine_is_mx51_babbage()	(machine_arch_type == MACH_TYPE_MX51_BABBAGE)
-#else
-# define machine_is_mx51_babbage()	(0)
-#endif
-
-#ifdef CONFIG_MACH_S3C2440TURKIYE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_S3C2440TURKIYE
-# endif
-# define machine_is_s3c2440turkiye()	(machine_arch_type == MACH_TYPE_S3C2440TURKIYE)
-#else
-# define machine_is_s3c2440turkiye()	(0)
-#endif
-
-#ifdef CONFIG_MACH_TX37
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TX37
-# endif
-# define machine_is_tx37()	(machine_arch_type == MACH_TYPE_TX37)
-#else
-# define machine_is_tx37()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SBC2800_9G20
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SBC2800_9G20
-# endif
-# define machine_is_sbc2800_9g20()	(machine_arch_type == MACH_TYPE_SBC2800_9G20)
-#else
-# define machine_is_sbc2800_9g20()	(0)
-#endif
-
-#ifdef CONFIG_MACH_BENZGLB
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_BENZGLB
-# endif
-# define machine_is_benzglb()	(machine_arch_type == MACH_TYPE_BENZGLB)
-#else
-# define machine_is_benzglb()	(0)
-#endif
-
-#ifdef CONFIG_MACH_BENZTD
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_BENZTD
-# endif
-# define machine_is_benztd()	(machine_arch_type == MACH_TYPE_BENZTD)
-#else
-# define machine_is_benztd()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CARTESIO_PLUS
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CARTESIO_PLUS
-# endif
-# define machine_is_cartesio_plus()	(machine_arch_type == MACH_TYPE_CARTESIO_PLUS)
-#else
-# define machine_is_cartesio_plus()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SOLRAD_G20
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SOLRAD_G20
-# endif
-# define machine_is_solrad_g20()	(machine_arch_type == MACH_TYPE_SOLRAD_G20)
-#else
-# define machine_is_solrad_g20()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MX27WALLACE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MX27WALLACE
-# endif
-# define machine_is_mx27wallace()	(machine_arch_type == MACH_TYPE_MX27WALLACE)
-#else
-# define machine_is_mx27wallace()	(0)
-#endif
-
-#ifdef CONFIG_MACH_FMZWEBMODUL
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_FMZWEBMODUL
-# endif
-# define machine_is_fmzwebmodul()	(machine_arch_type == MACH_TYPE_FMZWEBMODUL)
-#else
-# define machine_is_fmzwebmodul()	(0)
-#endif
-
-#ifdef CONFIG_MACH_RD78X00_MASA
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_RD78X00_MASA
-# endif
-# define machine_is_rd78x00_masa()	(machine_arch_type == MACH_TYPE_RD78X00_MASA)
-#else
-# define machine_is_rd78x00_masa()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SMALLOGGER
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SMALLOGGER
-# endif
-# define machine_is_smallogger()	(machine_arch_type == MACH_TYPE_SMALLOGGER)
-#else
-# define machine_is_smallogger()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CCW9P9215
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CCW9P9215
-# endif
-# define machine_is_ccw9p9215()	(machine_arch_type == MACH_TYPE_CCW9P9215)
-#else
-# define machine_is_ccw9p9215()	(0)
-#endif
-
-#ifdef CONFIG_MACH_DM355_LEOPARD
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_DM355_LEOPARD
-# endif
-# define machine_is_dm355_leopard()	(machine_arch_type == MACH_TYPE_DM355_LEOPARD)
-#else
-# define machine_is_dm355_leopard()	(0)
-#endif
-
-#ifdef CONFIG_MACH_TS219
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TS219
-# endif
-# define machine_is_ts219()	(machine_arch_type == MACH_TYPE_TS219)
-#else
-# define machine_is_ts219()	(0)
-#endif
-
-#ifdef CONFIG_MACH_TNY_A9263
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TNY_A9263
-# endif
-# define machine_is_tny_a9263()	(machine_arch_type == MACH_TYPE_TNY_A9263)
-#else
-# define machine_is_tny_a9263()	(0)
-#endif
-
-#ifdef CONFIG_MACH_APOLLO
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_APOLLO
-# endif
-# define machine_is_apollo()	(machine_arch_type == MACH_TYPE_APOLLO)
-#else
-# define machine_is_apollo()	(0)
-#endif
-
-#ifdef CONFIG_MACH_AT91CAP9STK
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_AT91CAP9STK
-# endif
-# define machine_is_at91cap9stk()	(machine_arch_type == MACH_TYPE_AT91CAP9STK)
-#else
-# define machine_is_at91cap9stk()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SPC300
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SPC300
-# endif
-# define machine_is_spc300()	(machine_arch_type == MACH_TYPE_SPC300)
-#else
-# define machine_is_spc300()	(0)
-#endif
-
-#ifdef CONFIG_MACH_EKO
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_EKO
-# endif
-# define machine_is_eko()	(machine_arch_type == MACH_TYPE_EKO)
-#else
-# define machine_is_eko()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CCW9M2443
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CCW9M2443
-# endif
-# define machine_is_ccw9m2443()	(machine_arch_type == MACH_TYPE_CCW9M2443)
-#else
-# define machine_is_ccw9m2443()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CCW9M2443JS
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CCW9M2443JS
-# endif
-# define machine_is_ccw9m2443js()	(machine_arch_type == MACH_TYPE_CCW9M2443JS)
-#else
-# define machine_is_ccw9m2443js()	(0)
-#endif
-
-#ifdef CONFIG_MACH_M2M_ROUTER_DEVICE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_M2M_ROUTER_DEVICE
-# endif
-# define machine_is_m2m_router_device()	(machine_arch_type == MACH_TYPE_M2M_ROUTER_DEVICE)
-#else
-# define machine_is_m2m_router_device()	(0)
-#endif
-
-#ifdef CONFIG_MACH_STAR9104NAS
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_STAR9104NAS
-# endif
-# define machine_is_str9104nas()	(machine_arch_type == MACH_TYPE_STAR9104NAS)
-#else
-# define machine_is_str9104nas()	(0)
-#endif
-
-#ifdef CONFIG_MACH_PCA100
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PCA100
-# endif
-# define machine_is_pca100()	(machine_arch_type == MACH_TYPE_PCA100)
-#else
-# define machine_is_pca100()	(0)
-#endif
-
-#ifdef CONFIG_MACH_Z3_DM365_MOD_01
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_Z3_DM365_MOD_01
-# endif
-# define machine_is_z3_dm365_mod_01()	(machine_arch_type == MACH_TYPE_Z3_DM365_MOD_01)
-#else
-# define machine_is_z3_dm365_mod_01()	(0)
-#endif
-
-#ifdef CONFIG_MACH_HIPOX
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_HIPOX
-# endif
-# define machine_is_hipox()	(machine_arch_type == MACH_TYPE_HIPOX)
-#else
-# define machine_is_hipox()	(0)
-#endif
-
-#ifdef CONFIG_MACH_OMAP3_PITEDS
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_OMAP3_PITEDS
-# endif
-# define machine_is_omap3_piteds()	(machine_arch_type == MACH_TYPE_OMAP3_PITEDS)
-#else
-# define machine_is_omap3_piteds()	(0)
-#endif
-
-#ifdef CONFIG_MACH_BM150R
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_BM150R
-# endif
-# define machine_is_bm150r()	(machine_arch_type == MACH_TYPE_BM150R)
-#else
-# define machine_is_bm150r()	(0)
-#endif
-
-#ifdef CONFIG_MACH_TBONE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TBONE
-# endif
-# define machine_is_tbone()	(machine_arch_type == MACH_TYPE_TBONE)
-#else
-# define machine_is_tbone()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MERLIN
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MERLIN
-# endif
-# define machine_is_merlin()	(machine_arch_type == MACH_TYPE_MERLIN)
-#else
-# define machine_is_merlin()	(0)
-#endif
-
-#ifdef CONFIG_MACH_FALCON
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_FALCON
-# endif
-# define machine_is_falcon()	(machine_arch_type == MACH_TYPE_FALCON)
-#else
-# define machine_is_falcon()	(0)
-#endif
-
-#ifdef CONFIG_MACH_DAVINCI_DA850_EVM
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_DAVINCI_DA850_EVM
-# endif
-# define machine_is_davinci_da850_evm()	(machine_arch_type == MACH_TYPE_DAVINCI_DA850_EVM)
-#else
-# define machine_is_davinci_da850_evm()	(0)
-#endif
-
-#ifdef CONFIG_MACH_S5P6440
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_S5P6440
-# endif
-# define machine_is_s5p6440()	(machine_arch_type == MACH_TYPE_S5P6440)
-#else
-# define machine_is_s5p6440()	(0)
-#endif
-
-#ifdef CONFIG_MACH_AT91SAM9G10EK
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_AT91SAM9G10EK
-# endif
-# define machine_is_at91sam9g10ek()	(machine_arch_type == MACH_TYPE_AT91SAM9G10EK)
-#else
-# define machine_is_at91sam9g10ek()	(0)
-#endif
-
-#ifdef CONFIG_MACH_OMAP_4430SDP
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_OMAP_4430SDP
-# endif
-# define machine_is_omap_4430sdp()	(machine_arch_type == MACH_TYPE_OMAP_4430SDP)
-#else
-# define machine_is_omap_4430sdp()	(0)
-#endif
-
-#ifdef CONFIG_MACH_LPC313X
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_LPC313X
-# endif
-# define machine_is_lpc313x()	(machine_arch_type == MACH_TYPE_LPC313X)
-#else
-# define machine_is_lpc313x()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MAGX_ZN5
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MAGX_ZN5
-# endif
-# define machine_is_magx_zn5()	(machine_arch_type == MACH_TYPE_MAGX_ZN5)
-#else
-# define machine_is_magx_zn5()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MAGX_EM30
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MAGX_EM30
-# endif
-# define machine_is_magx_em30()	(machine_arch_type == MACH_TYPE_MAGX_EM30)
-#else
-# define machine_is_magx_em30()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MAGX_VE66
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MAGX_VE66
-# endif
-# define machine_is_magx_ve66()	(machine_arch_type == MACH_TYPE_MAGX_VE66)
-#else
-# define machine_is_magx_ve66()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MEESC
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MEESC
-# endif
-# define machine_is_meesc()	(machine_arch_type == MACH_TYPE_MEESC)
-#else
-# define machine_is_meesc()	(0)
-#endif
-
-#ifdef CONFIG_MACH_OTC570
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_OTC570
-# endif
-# define machine_is_otc570()	(machine_arch_type == MACH_TYPE_OTC570)
-#else
-# define machine_is_otc570()	(0)
-#endif
-
-#ifdef CONFIG_MACH_BCU2412
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_BCU2412
-# endif
-# define machine_is_bcu2412()	(machine_arch_type == MACH_TYPE_BCU2412)
-#else
-# define machine_is_bcu2412()	(0)
-#endif
-
-#ifdef CONFIG_MACH_BEACON
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_BEACON
-# endif
-# define machine_is_beacon()	(machine_arch_type == MACH_TYPE_BEACON)
-#else
-# define machine_is_beacon()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ACTIA_TGW
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ACTIA_TGW
-# endif
-# define machine_is_actia_tgw()	(machine_arch_type == MACH_TYPE_ACTIA_TGW)
-#else
-# define machine_is_actia_tgw()	(0)
-#endif
-
-#ifdef CONFIG_MACH_E4430
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_E4430
-# endif
-# define machine_is_e4430()	(machine_arch_type == MACH_TYPE_E4430)
-#else
-# define machine_is_e4430()	(0)
-#endif
-
-#ifdef CONFIG_MACH_QL300
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_QL300
-# endif
-# define machine_is_ql300()	(machine_arch_type == MACH_TYPE_QL300)
-#else
-# define machine_is_ql300()	(0)
-#endif
-
-#ifdef CONFIG_MACH_BTMAVB101
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_BTMAVB101
-# endif
-# define machine_is_btmavb101()	(machine_arch_type == MACH_TYPE_BTMAVB101)
-#else
-# define machine_is_btmavb101()	(0)
-#endif
-
-#ifdef CONFIG_MACH_BTMAWB101
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_BTMAWB101
-# endif
-# define machine_is_btmawb101()	(machine_arch_type == MACH_TYPE_BTMAWB101)
-#else
-# define machine_is_btmawb101()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SQ201
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SQ201
-# endif
-# define machine_is_sq201()	(machine_arch_type == MACH_TYPE_SQ201)
-#else
-# define machine_is_sq201()	(0)
-#endif
-
-#ifdef CONFIG_MACH_QUATRO45XX
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_QUATRO45XX
-# endif
-# define machine_is_quatro45xx()	(machine_arch_type == MACH_TYPE_QUATRO45XX)
-#else
-# define machine_is_quatro45xx()	(0)
-#endif
-
-#ifdef CONFIG_MACH_OPENPAD
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_OPENPAD
-# endif
-# define machine_is_openpad()	(machine_arch_type == MACH_TYPE_OPENPAD)
-#else
-# define machine_is_openpad()	(0)
-#endif
-
-#ifdef CONFIG_MACH_TX25
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TX25
-# endif
-# define machine_is_tx25()	(machine_arch_type == MACH_TYPE_TX25)
-#else
-# define machine_is_tx25()	(0)
-#endif
-
-#ifdef CONFIG_MACH_OMAP3_TORPEDO
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_OMAP3_TORPEDO
-# endif
-# define machine_is_omap3_torpedo()	(machine_arch_type == MACH_TYPE_OMAP3_TORPEDO)
-#else
-# define machine_is_omap3_torpedo()	(0)
-#endif
-
-#ifdef CONFIG_MACH_HTCRAPHAEL_K
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_HTCRAPHAEL_K
-# endif
-# define machine_is_htcraphael_k()	(machine_arch_type == MACH_TYPE_HTCRAPHAEL_K)
-#else
-# define machine_is_htcraphael_k()	(0)
-#endif
-
-#ifdef CONFIG_MACH_LAL43
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_LAL43
-# endif
-# define machine_is_lal43()	(machine_arch_type == MACH_TYPE_LAL43)
-#else
-# define machine_is_lal43()	(0)
-#endif
-
-#ifdef CONFIG_MACH_HTCRAPHAEL_CDMA500
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_HTCRAPHAEL_CDMA500
-# endif
-# define machine_is_htcraphael_cdma500()	(machine_arch_type == MACH_TYPE_HTCRAPHAEL_CDMA500)
-#else
-# define machine_is_htcraphael_cdma500()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ANW6410
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ANW6410
-# endif
-# define machine_is_anw6410()	(machine_arch_type == MACH_TYPE_ANW6410)
-#else
-# define machine_is_anw6410()	(0)
-#endif
-
-#ifdef CONFIG_MACH_HTCPROPHET
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_HTCPROPHET
-# endif
-# define machine_is_htcprophet()	(machine_arch_type == MACH_TYPE_HTCPROPHET)
-#else
-# define machine_is_htcprophet()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CFA_10022
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CFA_10022
-# endif
-# define machine_is_cfa_10022()	(machine_arch_type == MACH_TYPE_CFA_10022)
-#else
-# define machine_is_cfa_10022()	(0)
-#endif
-
-#ifdef CONFIG_MACH_IMX27_VISSTRIM_M10
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_IMX27_VISSTRIM_M10
-# endif
-# define machine_is_imx27_visstrim_m10()	(machine_arch_type == MACH_TYPE_IMX27_VISSTRIM_M10)
-#else
-# define machine_is_imx27_visstrim_m10()	(0)
-#endif
-
-#ifdef CONFIG_MACH_PX2IMX27
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PX2IMX27
-# endif
-# define machine_is_px2imx27()	(machine_arch_type == MACH_TYPE_PX2IMX27)
-#else
-# define machine_is_px2imx27()	(0)
-#endif
-
-#ifdef CONFIG_MACH_STM3210E_EVAL
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_STM3210E_EVAL
-# endif
-# define machine_is_stm3210e_eval()	(machine_arch_type == MACH_TYPE_STM3210E_EVAL)
-#else
-# define machine_is_stm3210e_eval()	(0)
-#endif
-
-#ifdef CONFIG_MACH_DVS10
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_DVS10
-# endif
-# define machine_is_dvs10()	(machine_arch_type == MACH_TYPE_DVS10)
-#else
-# define machine_is_dvs10()	(0)
-#endif
-
-#ifdef CONFIG_MACH_PORTUXG20
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PORTUXG20
-# endif
-# define machine_is_portuxg20()	(machine_arch_type == MACH_TYPE_PORTUXG20)
-#else
-# define machine_is_portuxg20()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ARM_SPV
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ARM_SPV
-# endif
-# define machine_is_arm_spv()	(machine_arch_type == MACH_TYPE_ARM_SPV)
-#else
-# define machine_is_arm_spv()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SMDKC110
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SMDKC110
-# endif
-# define machine_is_smdkc110()	(machine_arch_type == MACH_TYPE_SMDKC110)
-#else
-# define machine_is_smdkc110()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CABESPRESSO
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CABESPRESSO
-# endif
-# define machine_is_cabespresso()	(machine_arch_type == MACH_TYPE_CABESPRESSO)
-#else
-# define machine_is_cabespresso()	(0)
-#endif
-
-#ifdef CONFIG_MACH_HMC800
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_HMC800
-# endif
-# define machine_is_hmc800()	(machine_arch_type == MACH_TYPE_HMC800)
-#else
-# define machine_is_hmc800()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SHOLES
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SHOLES
-# endif
-# define machine_is_sholes()	(machine_arch_type == MACH_TYPE_SHOLES)
-#else
-# define machine_is_sholes()	(0)
-#endif
-
-#ifdef CONFIG_MACH_BTMXC31
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_BTMXC31
-# endif
-# define machine_is_btmxc31()	(machine_arch_type == MACH_TYPE_BTMXC31)
-#else
-# define machine_is_btmxc31()	(0)
-#endif
-
-#ifdef CONFIG_MACH_DT501
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_DT501
-# endif
-# define machine_is_dt501()	(machine_arch_type == MACH_TYPE_DT501)
-#else
-# define machine_is_dt501()	(0)
-#endif
-
-#ifdef CONFIG_MACH_KTX
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_KTX
-# endif
-# define machine_is_ktx()	(machine_arch_type == MACH_TYPE_KTX)
-#else
-# define machine_is_ktx()	(0)
-#endif
-
-#ifdef CONFIG_MACH_OMAP3517EVM
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_OMAP3517EVM
-# endif
-# define machine_is_omap3517evm()	(machine_arch_type == MACH_TYPE_OMAP3517EVM)
-#else
-# define machine_is_omap3517evm()	(0)
-#endif
-
-#ifdef CONFIG_MACH_NETSPACE_V2
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_NETSPACE_V2
-# endif
-# define machine_is_netspace_v2()	(machine_arch_type == MACH_TYPE_NETSPACE_V2)
-#else
-# define machine_is_netspace_v2()	(0)
-#endif
-
-#ifdef CONFIG_MACH_NETSPACE_MAX_V2
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_NETSPACE_MAX_V2
-# endif
-# define machine_is_netspace_max_v2()	(machine_arch_type == MACH_TYPE_NETSPACE_MAX_V2)
-#else
-# define machine_is_netspace_max_v2()	(0)
-#endif
-
-#ifdef CONFIG_MACH_D2NET_V2
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_D2NET_V2
-# endif
-# define machine_is_d2net_v2()	(machine_arch_type == MACH_TYPE_D2NET_V2)
-#else
-# define machine_is_d2net_v2()	(0)
-#endif
-
-#ifdef CONFIG_MACH_NET2BIG_V2
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_NET2BIG_V2
-# endif
-# define machine_is_net2big_v2()	(machine_arch_type == MACH_TYPE_NET2BIG_V2)
-#else
-# define machine_is_net2big_v2()	(0)
-#endif
-
-#ifdef CONFIG_MACH_NET4BIG_V2
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_NET4BIG_V2
-# endif
-# define machine_is_net4big_v2()	(machine_arch_type == MACH_TYPE_NET4BIG_V2)
-#else
-# define machine_is_net4big_v2()	(0)
-#endif
-
-#ifdef CONFIG_MACH_NET5BIG_V2
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_NET5BIG_V2
-# endif
-# define machine_is_net5big_v2()	(machine_arch_type == MACH_TYPE_NET5BIG_V2)
-#else
-# define machine_is_net5big_v2()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ENDB2443
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ENDB2443
-# endif
-# define machine_is_endb2443()	(machine_arch_type == MACH_TYPE_ENDB2443)
-#else
-# define machine_is_endb2443()	(0)
-#endif
-
-#ifdef CONFIG_MACH_INETSPACE_V2
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_INETSPACE_V2
-# endif
-# define machine_is_inetspace_v2()	(machine_arch_type == MACH_TYPE_INETSPACE_V2)
-#else
-# define machine_is_inetspace_v2()	(0)
-#endif
-
-#ifdef CONFIG_MACH_TROS
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TROS
-# endif
-# define machine_is_tros()	(machine_arch_type == MACH_TYPE_TROS)
-#else
-# define machine_is_tros()	(0)
-#endif
-
-#ifdef CONFIG_MACH_PELCO_HOMER
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PELCO_HOMER
-# endif
-# define machine_is_pelco_homer()	(machine_arch_type == MACH_TYPE_PELCO_HOMER)
-#else
-# define machine_is_pelco_homer()	(0)
-#endif
-
-#ifdef CONFIG_MACH_OFSP8
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_OFSP8
-# endif
-# define machine_is_ofsp8()	(machine_arch_type == MACH_TYPE_OFSP8)
-#else
-# define machine_is_ofsp8()	(0)
-#endif
-
-#ifdef CONFIG_MACH_AT91SAM9G45EKES
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_AT91SAM9G45EKES
-# endif
-# define machine_is_at91sam9g45ekes()	(machine_arch_type == MACH_TYPE_AT91SAM9G45EKES)
-#else
-# define machine_is_at91sam9g45ekes()	(0)
-#endif
-
-#ifdef CONFIG_MACH_GUF_CUPID
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_GUF_CUPID
-# endif
-# define machine_is_guf_cupid()	(machine_arch_type == MACH_TYPE_GUF_CUPID)
-#else
-# define machine_is_guf_cupid()	(0)
-#endif
-
-#ifdef CONFIG_MACH_EAB1R
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_EAB1R
-# endif
-# define machine_is_eab1r()	(machine_arch_type == MACH_TYPE_EAB1R)
-#else
-# define machine_is_eab1r()	(0)
-#endif
-
-#ifdef CONFIG_MACH_DESIREC
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_DESIREC
-# endif
-# define machine_is_desirec()	(machine_arch_type == MACH_TYPE_DESIREC)
-#else
-# define machine_is_desirec()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CORDOBA
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CORDOBA
-# endif
-# define machine_is_cordoba()	(machine_arch_type == MACH_TYPE_CORDOBA)
-#else
-# define machine_is_cordoba()	(0)
-#endif
-
-#ifdef CONFIG_MACH_IRVINE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_IRVINE
-# endif
-# define machine_is_irvine()	(machine_arch_type == MACH_TYPE_IRVINE)
-#else
-# define machine_is_irvine()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SFF772
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SFF772
-# endif
-# define machine_is_sff772()	(machine_arch_type == MACH_TYPE_SFF772)
-#else
-# define machine_is_sff772()	(0)
-#endif
-
-#ifdef CONFIG_MACH_PELCO_MILANO
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PELCO_MILANO
-# endif
-# define machine_is_pelco_milano()	(machine_arch_type == MACH_TYPE_PELCO_MILANO)
-#else
-# define machine_is_pelco_milano()	(0)
-#endif
-
-#ifdef CONFIG_MACH_PC7302
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PC7302
-# endif
-# define machine_is_pc7302()	(machine_arch_type == MACH_TYPE_PC7302)
-#else
-# define machine_is_pc7302()	(0)
-#endif
-
-#ifdef CONFIG_MACH_BIP6000
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_BIP6000
-# endif
-# define machine_is_bip6000()	(machine_arch_type == MACH_TYPE_BIP6000)
-#else
-# define machine_is_bip6000()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SILVERMOON
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SILVERMOON
-# endif
-# define machine_is_silvermoon()	(machine_arch_type == MACH_TYPE_SILVERMOON)
-#else
-# define machine_is_silvermoon()	(0)
-#endif
-
-#ifdef CONFIG_MACH_VC0830
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_VC0830
-# endif
-# define machine_is_vc0830()	(machine_arch_type == MACH_TYPE_VC0830)
-#else
-# define machine_is_vc0830()	(0)
-#endif
-
-#ifdef CONFIG_MACH_DT430
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_DT430
-# endif
-# define machine_is_dt430()	(machine_arch_type == MACH_TYPE_DT430)
-#else
-# define machine_is_dt430()	(0)
-#endif
-
-#ifdef CONFIG_MACH_JI42PF
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_JI42PF
-# endif
-# define machine_is_ji42pf()	(machine_arch_type == MACH_TYPE_JI42PF)
-#else
-# define machine_is_ji42pf()	(0)
-#endif
-
-#ifdef CONFIG_MACH_GNET_KSM
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_GNET_KSM
-# endif
-# define machine_is_gnet_ksm()	(machine_arch_type == MACH_TYPE_GNET_KSM)
-#else
-# define machine_is_gnet_ksm()	(0)
-#endif
-
-#ifdef CONFIG_MACH_GNET_SGM
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_GNET_SGM
-# endif
-# define machine_is_gnet_sgm()	(machine_arch_type == MACH_TYPE_GNET_SGM)
-#else
-# define machine_is_gnet_sgm()	(0)
-#endif
-
-#ifdef CONFIG_MACH_GNET_SGR
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_GNET_SGR
-# endif
-# define machine_is_gnet_sgr()	(machine_arch_type == MACH_TYPE_GNET_SGR)
-#else
-# define machine_is_gnet_sgr()	(0)
-#endif
-
-#ifdef CONFIG_MACH_OMAP3_ICETEKEVM
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_OMAP3_ICETEKEVM
-# endif
-# define machine_is_omap3_icetekevm()	(machine_arch_type == MACH_TYPE_OMAP3_ICETEKEVM)
-#else
-# define machine_is_omap3_icetekevm()	(0)
-#endif
-
-#ifdef CONFIG_MACH_PNP
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PNP
-# endif
-# define machine_is_pnp()	(machine_arch_type == MACH_TYPE_PNP)
-#else
-# define machine_is_pnp()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CTERA_2BAY_K
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CTERA_2BAY_K
-# endif
-# define machine_is_ctera_2bay_k()	(machine_arch_type == MACH_TYPE_CTERA_2BAY_K)
-#else
-# define machine_is_ctera_2bay_k()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CTERA_2BAY_U
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CTERA_2BAY_U
-# endif
-# define machine_is_ctera_2bay_u()	(machine_arch_type == MACH_TYPE_CTERA_2BAY_U)
-#else
-# define machine_is_ctera_2bay_u()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SAS_C
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SAS_C
-# endif
-# define machine_is_sas_c()	(machine_arch_type == MACH_TYPE_SAS_C)
-#else
-# define machine_is_sas_c()	(0)
-#endif
-
-#ifdef CONFIG_MACH_VMA2315
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_VMA2315
-# endif
-# define machine_is_vma2315()	(machine_arch_type == MACH_TYPE_VMA2315)
-#else
-# define machine_is_vma2315()	(0)
-#endif
-
-#ifdef CONFIG_MACH_VCS
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_VCS
-# endif
-# define machine_is_vcs()	(machine_arch_type == MACH_TYPE_VCS)
-#else
-# define machine_is_vcs()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SPEAR600
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SPEAR600
-# endif
-# define machine_is_spear600()	(machine_arch_type == MACH_TYPE_SPEAR600)
-#else
-# define machine_is_spear600()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SPEAR300
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SPEAR300
-# endif
-# define machine_is_spear300()	(machine_arch_type == MACH_TYPE_SPEAR300)
-#else
-# define machine_is_spear300()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SPEAR1300
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SPEAR1300
-# endif
-# define machine_is_spear1300()	(machine_arch_type == MACH_TYPE_SPEAR1300)
-#else
-# define machine_is_spear1300()	(0)
-#endif
-
-#ifdef CONFIG_MACH_LILLY1131
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_LILLY1131
-# endif
-# define machine_is_lilly1131()	(machine_arch_type == MACH_TYPE_LILLY1131)
-#else
-# define machine_is_lilly1131()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ARVOO_AX301
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ARVOO_AX301
-# endif
-# define machine_is_arvoo_ax301()	(machine_arch_type == MACH_TYPE_ARVOO_AX301)
-#else
-# define machine_is_arvoo_ax301()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MAPPHONE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MAPPHONE
-# endif
-# define machine_is_mapphone()	(machine_arch_type == MACH_TYPE_MAPPHONE)
-#else
-# define machine_is_mapphone()	(0)
-#endif
-
-#ifdef CONFIG_MACH_LEGEND
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_LEGEND
-# endif
-# define machine_is_legend()	(machine_arch_type == MACH_TYPE_LEGEND)
-#else
-# define machine_is_legend()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SALSA
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SALSA
-# endif
-# define machine_is_salsa()	(machine_arch_type == MACH_TYPE_SALSA)
-#else
-# define machine_is_salsa()	(0)
-#endif
-
-#ifdef CONFIG_MACH_LOUNGE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_LOUNGE
-# endif
-# define machine_is_lounge()	(machine_arch_type == MACH_TYPE_LOUNGE)
-#else
-# define machine_is_lounge()	(0)
-#endif
-
-#ifdef CONFIG_MACH_VISION
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_VISION
-# endif
-# define machine_is_vision()	(machine_arch_type == MACH_TYPE_VISION)
-#else
-# define machine_is_vision()	(0)
-#endif
-
-#ifdef CONFIG_MACH_VMB20
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_VMB20
-# endif
-# define machine_is_vmb20()	(machine_arch_type == MACH_TYPE_VMB20)
-#else
-# define machine_is_vmb20()	(0)
-#endif
-
-#ifdef CONFIG_MACH_HY2410
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_HY2410
-# endif
-# define machine_is_hy2410()	(machine_arch_type == MACH_TYPE_HY2410)
-#else
-# define machine_is_hy2410()	(0)
-#endif
-
-#ifdef CONFIG_MACH_HY9315
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_HY9315
-# endif
-# define machine_is_hy9315()	(machine_arch_type == MACH_TYPE_HY9315)
-#else
-# define machine_is_hy9315()	(0)
-#endif
-
-#ifdef CONFIG_MACH_BULLWINKLE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_BULLWINKLE
-# endif
-# define machine_is_bullwinkle()	(machine_arch_type == MACH_TYPE_BULLWINKLE)
-#else
-# define machine_is_bullwinkle()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ARM_ULTIMATOR2
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ARM_ULTIMATOR2
-# endif
-# define machine_is_arm_ultimator2()	(machine_arch_type == MACH_TYPE_ARM_ULTIMATOR2)
-#else
-# define machine_is_arm_ultimator2()	(0)
-#endif
-
-#ifdef CONFIG_MACH_VS_V210
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_VS_V210
-# endif
-# define machine_is_vs_v210()	(machine_arch_type == MACH_TYPE_VS_V210)
-#else
-# define machine_is_vs_v210()	(0)
-#endif
-
-#ifdef CONFIG_MACH_VS_V212
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_VS_V212
-# endif
-# define machine_is_vs_v212()	(machine_arch_type == MACH_TYPE_VS_V212)
-#else
-# define machine_is_vs_v212()	(0)
-#endif
-
-#ifdef CONFIG_MACH_HMT
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_HMT
-# endif
-# define machine_is_hmt()	(machine_arch_type == MACH_TYPE_HMT)
-#else
-# define machine_is_hmt()	(0)
-#endif
-
-#ifdef CONFIG_MACH_KM_KIRKWOOD
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_KM_KIRKWOOD
-# endif
-# define machine_is_km_kirkwood()	(machine_arch_type == MACH_TYPE_KM_KIRKWOOD)
-#else
-# define machine_is_km_kirkwood()	(0)
-#endif
-
-#ifdef CONFIG_MACH_VESPER
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_VESPER
-# endif
-# define machine_is_vesper()	(machine_arch_type == MACH_TYPE_VESPER)
-#else
-# define machine_is_vesper()	(0)
-#endif
-
-#ifdef CONFIG_MACH_STR9
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_STR9
-# endif
-# define machine_is_str9()	(machine_arch_type == MACH_TYPE_STR9)
-#else
-# define machine_is_str9()	(0)
-#endif
-
-#ifdef CONFIG_MACH_OMAP3_WL_FF
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_OMAP3_WL_FF
-# endif
-# define machine_is_omap3_wl_ff()	(machine_arch_type == MACH_TYPE_OMAP3_WL_FF)
-#else
-# define machine_is_omap3_wl_ff()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SIMCOM
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SIMCOM
-# endif
-# define machine_is_simcom()	(machine_arch_type == MACH_TYPE_SIMCOM)
-#else
-# define machine_is_simcom()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MCWEBIO
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MCWEBIO
-# endif
-# define machine_is_mcwebio()	(machine_arch_type == MACH_TYPE_MCWEBIO)
-#else
-# define machine_is_mcwebio()	(0)
-#endif
-
-#ifdef CONFIG_MACH_OMAP3_PHRAZER
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_OMAP3_PHRAZER
-# endif
-# define machine_is_omap3_phrazer()	(machine_arch_type == MACH_TYPE_OMAP3_PHRAZER)
-#else
-# define machine_is_omap3_phrazer()	(0)
-#endif
-
-#ifdef CONFIG_MACH_DARWIN
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_DARWIN
-# endif
-# define machine_is_darwin()	(machine_arch_type == MACH_TYPE_DARWIN)
-#else
-# define machine_is_darwin()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ORATISCOMU
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ORATISCOMU
-# endif
-# define machine_is_oratiscomu()	(machine_arch_type == MACH_TYPE_ORATISCOMU)
-#else
-# define machine_is_oratiscomu()	(0)
-#endif
-
-#ifdef CONFIG_MACH_RTSBC20
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_RTSBC20
-# endif
-# define machine_is_rtsbc20()	(machine_arch_type == MACH_TYPE_RTSBC20)
-#else
-# define machine_is_rtsbc20()	(0)
-#endif
-
-#ifdef CONFIG_MACH_I780
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_I780
-# endif
-# define machine_is_sgh_i780()	(machine_arch_type == MACH_TYPE_I780)
-#else
-# define machine_is_sgh_i780()	(0)
-#endif
-
-#ifdef CONFIG_MACH_GEMINI324
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_GEMINI324
-# endif
-# define machine_is_gemini324()	(machine_arch_type == MACH_TYPE_GEMINI324)
-#else
-# define machine_is_gemini324()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ORATISLAN
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ORATISLAN
-# endif
-# define machine_is_oratislan()	(machine_arch_type == MACH_TYPE_ORATISLAN)
-#else
-# define machine_is_oratislan()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ORATISALOG
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ORATISALOG
-# endif
-# define machine_is_oratisalog()	(machine_arch_type == MACH_TYPE_ORATISALOG)
-#else
-# define machine_is_oratisalog()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ORATISMADI
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ORATISMADI
-# endif
-# define machine_is_oratismadi()	(machine_arch_type == MACH_TYPE_ORATISMADI)
-#else
-# define machine_is_oratismadi()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ORATISOT16
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ORATISOT16
-# endif
-# define machine_is_oratisot16()	(machine_arch_type == MACH_TYPE_ORATISOT16)
-#else
-# define machine_is_oratisot16()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ORATISDESK
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ORATISDESK
-# endif
-# define machine_is_oratisdesk()	(machine_arch_type == MACH_TYPE_ORATISDESK)
-#else
-# define machine_is_oratisdesk()	(0)
-#endif
-
-#ifdef CONFIG_MACH_VEXPRESS
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_VEXPRESS
-# endif
-# define machine_is_vexpress()	(machine_arch_type == MACH_TYPE_VEXPRESS)
-#else
-# define machine_is_vexpress()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SINTEXO
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SINTEXO
-# endif
-# define machine_is_sintexo()	(machine_arch_type == MACH_TYPE_SINTEXO)
-#else
-# define machine_is_sintexo()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CM3389
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CM3389
-# endif
-# define machine_is_cm3389()	(machine_arch_type == MACH_TYPE_CM3389)
-#else
-# define machine_is_cm3389()	(0)
-#endif
-
-#ifdef CONFIG_MACH_OMAP3_CIO
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_OMAP3_CIO
-# endif
-# define machine_is_omap3_cio()	(machine_arch_type == MACH_TYPE_OMAP3_CIO)
-#else
-# define machine_is_omap3_cio()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SGH_I900
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SGH_I900
-# endif
-# define machine_is_sgh_i900()	(machine_arch_type == MACH_TYPE_SGH_I900)
-#else
-# define machine_is_sgh_i900()	(0)
-#endif
-
-#ifdef CONFIG_MACH_BST100
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_BST100
-# endif
-# define machine_is_bst100()	(machine_arch_type == MACH_TYPE_BST100)
-#else
-# define machine_is_bst100()	(0)
-#endif
-
-#ifdef CONFIG_MACH_PASSION
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PASSION
-# endif
-# define machine_is_passion()	(machine_arch_type == MACH_TYPE_PASSION)
-#else
-# define machine_is_passion()	(0)
-#endif
-
-#ifdef CONFIG_MACH_INDESIGN_AT91SAM
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_INDESIGN_AT91SAM
-# endif
-# define machine_is_indesign_at91sam()	(machine_arch_type == MACH_TYPE_INDESIGN_AT91SAM)
-#else
-# define machine_is_indesign_at91sam()	(0)
-#endif
-
-#ifdef CONFIG_MACH_C4_BADGER
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_C4_BADGER
-# endif
-# define machine_is_c4_badger()	(machine_arch_type == MACH_TYPE_C4_BADGER)
-#else
-# define machine_is_c4_badger()	(0)
-#endif
-
-#ifdef CONFIG_MACH_C4_VIPER
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_C4_VIPER
-# endif
-# define machine_is_c4_viper()	(machine_arch_type == MACH_TYPE_C4_VIPER)
-#else
-# define machine_is_c4_viper()	(0)
-#endif
-
-#ifdef CONFIG_MACH_D2NET
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_D2NET
-# endif
-# define machine_is_d2net()	(machine_arch_type == MACH_TYPE_D2NET)
-#else
-# define machine_is_d2net()	(0)
-#endif
-
-#ifdef CONFIG_MACH_BIGDISK
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_BIGDISK
-# endif
-# define machine_is_bigdisk()	(machine_arch_type == MACH_TYPE_BIGDISK)
-#else
-# define machine_is_bigdisk()	(0)
-#endif
-
-#ifdef CONFIG_MACH_NOTALVISION
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_NOTALVISION
-# endif
-# define machine_is_notalvision()	(machine_arch_type == MACH_TYPE_NOTALVISION)
-#else
-# define machine_is_notalvision()	(0)
-#endif
-
-#ifdef CONFIG_MACH_OMAP3_KBOC
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_OMAP3_KBOC
-# endif
-# define machine_is_omap3_kboc()	(machine_arch_type == MACH_TYPE_OMAP3_KBOC)
-#else
-# define machine_is_omap3_kboc()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CYCLONE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CYCLONE
-# endif
-# define machine_is_cyclone()	(machine_arch_type == MACH_TYPE_CYCLONE)
-#else
-# define machine_is_cyclone()	(0)
-#endif
-
-#ifdef CONFIG_MACH_NINJA
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_NINJA
-# endif
-# define machine_is_ninja()	(machine_arch_type == MACH_TYPE_NINJA)
-#else
-# define machine_is_ninja()	(0)
-#endif
-
-#ifdef CONFIG_MACH_AT91SAM9G20EK_2MMC
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_AT91SAM9G20EK_2MMC
-# endif
-# define machine_is_at91sam9g20ek_2mmc()	(machine_arch_type == MACH_TYPE_AT91SAM9G20EK_2MMC)
-#else
-# define machine_is_at91sam9g20ek_2mmc()	(0)
-#endif
-
-#ifdef CONFIG_MACH_BCMRING
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_BCMRING
-# endif
-# define machine_is_bcmring()	(machine_arch_type == MACH_TYPE_BCMRING)
-#else
-# define machine_is_bcmring()	(0)
-#endif
-
-#ifdef CONFIG_MACH_RESOL_DL2
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_RESOL_DL2
-# endif
-# define machine_is_resol_dl2()	(machine_arch_type == MACH_TYPE_RESOL_DL2)
-#else
-# define machine_is_resol_dl2()	(0)
-#endif
-
-#ifdef CONFIG_MACH_IFOSW
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_IFOSW
-# endif
-# define machine_is_ifosw()	(machine_arch_type == MACH_TYPE_IFOSW)
-#else
-# define machine_is_ifosw()	(0)
-#endif
-
-#ifdef CONFIG_MACH_HTCRHODIUM
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_HTCRHODIUM
-# endif
-# define machine_is_htcrhodium()	(machine_arch_type == MACH_TYPE_HTCRHODIUM)
-#else
-# define machine_is_htcrhodium()	(0)
-#endif
-
-#ifdef CONFIG_MACH_HTCTOPAZ
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_HTCTOPAZ
-# endif
-# define machine_is_htctopaz()	(machine_arch_type == MACH_TYPE_HTCTOPAZ)
-#else
-# define machine_is_htctopaz()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MATRIX504
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MATRIX504
-# endif
-# define machine_is_matrix504()	(machine_arch_type == MACH_TYPE_MATRIX504)
-#else
-# define machine_is_matrix504()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MRFSA
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MRFSA
-# endif
-# define machine_is_mrfsa()	(machine_arch_type == MACH_TYPE_MRFSA)
-#else
-# define machine_is_mrfsa()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SC_P270
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SC_P270
-# endif
-# define machine_is_sc_p270()	(machine_arch_type == MACH_TYPE_SC_P270)
-#else
-# define machine_is_sc_p270()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ATLAS5_EVB
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ATLAS5_EVB
-# endif
-# define machine_is_atlas5_evb()	(machine_arch_type == MACH_TYPE_ATLAS5_EVB)
-#else
-# define machine_is_atlas5_evb()	(0)
-#endif
-
-#ifdef CONFIG_MACH_PELCO_LOBOX
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PELCO_LOBOX
-# endif
-# define machine_is_pelco_lobox()	(machine_arch_type == MACH_TYPE_PELCO_LOBOX)
-#else
-# define machine_is_pelco_lobox()	(0)
-#endif
-
-#ifdef CONFIG_MACH_DILAX_PCU200
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_DILAX_PCU200
-# endif
-# define machine_is_dilax_pcu200()	(machine_arch_type == MACH_TYPE_DILAX_PCU200)
-#else
-# define machine_is_dilax_pcu200()	(0)
-#endif
-
-#ifdef CONFIG_MACH_LEONARDO
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_LEONARDO
-# endif
-# define machine_is_leonardo()	(machine_arch_type == MACH_TYPE_LEONARDO)
-#else
-# define machine_is_leonardo()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ZORAN_APPROACH7
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ZORAN_APPROACH7
-# endif
-# define machine_is_zoran_approach7()	(machine_arch_type == MACH_TYPE_ZORAN_APPROACH7)
-#else
-# define machine_is_zoran_approach7()	(0)
-#endif
-
-#ifdef CONFIG_MACH_DP6XX
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_DP6XX
-# endif
-# define machine_is_dp6xx()	(machine_arch_type == MACH_TYPE_DP6XX)
-#else
-# define machine_is_dp6xx()	(0)
-#endif
-
-#ifdef CONFIG_MACH_BCM2153_VESPER
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_BCM2153_VESPER
-# endif
-# define machine_is_bcm2153_vesper()	(machine_arch_type == MACH_TYPE_BCM2153_VESPER)
-#else
-# define machine_is_bcm2153_vesper()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MAHIMAHI
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MAHIMAHI
-# endif
-# define machine_is_mahimahi()	(machine_arch_type == MACH_TYPE_MAHIMAHI)
-#else
-# define machine_is_mahimahi()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CLICKC
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CLICKC
-# endif
-# define machine_is_clickc()	(machine_arch_type == MACH_TYPE_CLICKC)
-#else
-# define machine_is_clickc()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ZB_GATEWAY
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ZB_GATEWAY
-# endif
-# define machine_is_zb_gateway()	(machine_arch_type == MACH_TYPE_ZB_GATEWAY)
-#else
-# define machine_is_zb_gateway()	(0)
-#endif
-
-#ifdef CONFIG_MACH_TAZCARD
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TAZCARD
-# endif
-# define machine_is_tazcard()	(machine_arch_type == MACH_TYPE_TAZCARD)
-#else
-# define machine_is_tazcard()	(0)
-#endif
-
-#ifdef CONFIG_MACH_TAZDEV
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TAZDEV
-# endif
-# define machine_is_tazdev()	(machine_arch_type == MACH_TYPE_TAZDEV)
-#else
-# define machine_is_tazdev()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ANNAX_CB_ARM
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ANNAX_CB_ARM
-# endif
-# define machine_is_annax_cb_arm()	(machine_arch_type == MACH_TYPE_ANNAX_CB_ARM)
-#else
-# define machine_is_annax_cb_arm()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ANNAX_DM3
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ANNAX_DM3
-# endif
-# define machine_is_annax_dm3()	(machine_arch_type == MACH_TYPE_ANNAX_DM3)
-#else
-# define machine_is_annax_dm3()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CEREBRIC
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CEREBRIC
-# endif
-# define machine_is_cerebric()	(machine_arch_type == MACH_TYPE_CEREBRIC)
-#else
-# define machine_is_cerebric()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ORCA
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ORCA
-# endif
-# define machine_is_orca()	(machine_arch_type == MACH_TYPE_ORCA)
-#else
-# define machine_is_orca()	(0)
-#endif
-
-#ifdef CONFIG_MACH_PC9260
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PC9260
-# endif
-# define machine_is_pc9260()	(machine_arch_type == MACH_TYPE_PC9260)
-#else
-# define machine_is_pc9260()	(0)
-#endif
-
-#ifdef CONFIG_MACH_EMS285A
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_EMS285A
-# endif
-# define machine_is_ems285a()	(machine_arch_type == MACH_TYPE_EMS285A)
-#else
-# define machine_is_ems285a()	(0)
-#endif
-
-#ifdef CONFIG_MACH_GEC2410
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_GEC2410
-# endif
-# define machine_is_gec2410()	(machine_arch_type == MACH_TYPE_GEC2410)
-#else
-# define machine_is_gec2410()	(0)
-#endif
-
-#ifdef CONFIG_MACH_GEC2440
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_GEC2440
-# endif
-# define machine_is_gec2440()	(machine_arch_type == MACH_TYPE_GEC2440)
-#else
-# define machine_is_gec2440()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ARCH_MW903
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ARCH_MW903
-# endif
-# define machine_is_mw903()	(machine_arch_type == MACH_TYPE_ARCH_MW903)
-#else
-# define machine_is_mw903()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MW2440
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MW2440
-# endif
-# define machine_is_mw2440()	(machine_arch_type == MACH_TYPE_MW2440)
-#else
-# define machine_is_mw2440()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ECAC2378
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ECAC2378
-# endif
-# define machine_is_ecac2378()	(machine_arch_type == MACH_TYPE_ECAC2378)
-#else
-# define machine_is_ecac2378()	(0)
-#endif
-
-#ifdef CONFIG_MACH_TAZKIOSK
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TAZKIOSK
-# endif
-# define machine_is_tazkiosk()	(machine_arch_type == MACH_TYPE_TAZKIOSK)
-#else
-# define machine_is_tazkiosk()	(0)
-#endif
-
-#ifdef CONFIG_MACH_WHITERABBIT_MCH
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_WHITERABBIT_MCH
-# endif
-# define machine_is_whiterabbit_mch()	(machine_arch_type == MACH_TYPE_WHITERABBIT_MCH)
-#else
-# define machine_is_whiterabbit_mch()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SBOX9263
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SBOX9263
-# endif
-# define machine_is_sbox9263()	(machine_arch_type == MACH_TYPE_SBOX9263)
-#else
-# define machine_is_sbox9263()	(0)
-#endif
-
-#ifdef CONFIG_MACH_OREO
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_OREO
-# endif
-# define machine_is_oreo()	(machine_arch_type == MACH_TYPE_OREO)
-#else
-# define machine_is_oreo()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SMDK6442
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SMDK6442
-# endif
-# define machine_is_smdk6442()	(machine_arch_type == MACH_TYPE_SMDK6442)
-#else
-# define machine_is_smdk6442()	(0)
-#endif
-
-#ifdef CONFIG_MACH_OPENRD_BASE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_OPENRD_BASE
-# endif
-# define machine_is_openrd_base()	(machine_arch_type == MACH_TYPE_OPENRD_BASE)
-#else
-# define machine_is_openrd_base()	(0)
-#endif
-
-#ifdef CONFIG_MACH_INCREDIBLE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_INCREDIBLE
-# endif
-# define machine_is_incredible()	(machine_arch_type == MACH_TYPE_INCREDIBLE)
-#else
-# define machine_is_incredible()	(0)
-#endif
-
-#ifdef CONFIG_MACH_INCREDIBLEC
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_INCREDIBLEC
-# endif
-# define machine_is_incrediblec()	(machine_arch_type == MACH_TYPE_INCREDIBLEC)
-#else
-# define machine_is_incrediblec()	(0)
-#endif
-
-#ifdef CONFIG_MACH_HEROCT
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_HEROCT
-# endif
-# define machine_is_heroct()	(machine_arch_type == MACH_TYPE_HEROCT)
-#else
-# define machine_is_heroct()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MMNET1000
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MMNET1000
-# endif
-# define machine_is_mmnet1000()	(machine_arch_type == MACH_TYPE_MMNET1000)
-#else
-# define machine_is_mmnet1000()	(0)
-#endif
-
-#ifdef CONFIG_MACH_DEVKIT8000
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_DEVKIT8000
-# endif
-# define machine_is_devkit8000()	(machine_arch_type == MACH_TYPE_DEVKIT8000)
-#else
-# define machine_is_devkit8000()	(0)
-#endif
-
-#ifdef CONFIG_MACH_DEVKIT9000
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_DEVKIT9000
-# endif
-# define machine_is_devkit9000()	(machine_arch_type == MACH_TYPE_DEVKIT9000)
-#else
-# define machine_is_devkit9000()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MX31TXTR
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MX31TXTR
-# endif
-# define machine_is_mx31txtr()	(machine_arch_type == MACH_TYPE_MX31TXTR)
-#else
-# define machine_is_mx31txtr()	(0)
-#endif
-
-#ifdef CONFIG_MACH_U380
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_U380
-# endif
-# define machine_is_u380()	(machine_arch_type == MACH_TYPE_U380)
-#else
-# define machine_is_u380()	(0)
-#endif
-
-#ifdef CONFIG_MACH_HUALU_BOARD
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_HUALU_BOARD
-# endif
-# define machine_is_oamp3_hualu()	(machine_arch_type == MACH_TYPE_HUALU_BOARD)
-#else
-# define machine_is_oamp3_hualu()	(0)
-#endif
-
-#ifdef CONFIG_MACH_NPCMX50
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_NPCMX50
-# endif
-# define machine_is_npcmx50()	(machine_arch_type == MACH_TYPE_NPCMX50)
-#else
-# define machine_is_npcmx50()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MX51_EFIKAMX
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MX51_EFIKAMX
-# endif
-# define machine_is_mx51_efikamx()	(machine_arch_type == MACH_TYPE_MX51_EFIKAMX)
-#else
-# define machine_is_mx51_efikamx()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MX51_LANGE52
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MX51_LANGE52
-# endif
-# define machine_is_mx51_lange52()	(machine_arch_type == MACH_TYPE_MX51_LANGE52)
-#else
-# define machine_is_mx51_lange52()	(0)
-#endif
-
-#ifdef CONFIG_MACH_RIOM
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_RIOM
-# endif
-# define machine_is_riom()	(machine_arch_type == MACH_TYPE_RIOM)
-#else
-# define machine_is_riom()	(0)
-#endif
-
-#ifdef CONFIG_MACH_COMCAS
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_COMCAS
-# endif
-# define machine_is_comcas()	(machine_arch_type == MACH_TYPE_COMCAS)
-#else
-# define machine_is_comcas()	(0)
-#endif
-
-#ifdef CONFIG_MACH_WSI_MX27
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_WSI_MX27
-# endif
-# define machine_is_wsi_mx27()	(machine_arch_type == MACH_TYPE_WSI_MX27)
-#else
-# define machine_is_wsi_mx27()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CM_T35
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CM_T35
-# endif
-# define machine_is_cm_t35()	(machine_arch_type == MACH_TYPE_CM_T35)
-#else
-# define machine_is_cm_t35()	(0)
-#endif
-
-#ifdef CONFIG_MACH_NET2BIG
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_NET2BIG
-# endif
-# define machine_is_net2big()	(machine_arch_type == MACH_TYPE_NET2BIG)
-#else
-# define machine_is_net2big()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MOTOROLA_A1600
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MOTOROLA_A1600
-# endif
-# define machine_is_motorola_a1600()	(machine_arch_type == MACH_TYPE_MOTOROLA_A1600)
-#else
-# define machine_is_motorola_a1600()	(0)
-#endif
-
-#ifdef CONFIG_MACH_IGEP0020
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_IGEP0020
-# endif
-# define machine_is_igep0020()	(machine_arch_type == MACH_TYPE_IGEP0020)
-#else
-# define machine_is_igep0020()	(0)
-#endif
-
-#ifdef CONFIG_MACH_IGEP0010
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_IGEP0010
-# endif
-# define machine_is_igep0010()	(machine_arch_type == MACH_TYPE_IGEP0010)
-#else
-# define machine_is_igep0010()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MV6281GTWGE2
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MV6281GTWGE2
-# endif
-# define machine_is_mv6281gtwge2()	(machine_arch_type == MACH_TYPE_MV6281GTWGE2)
-#else
-# define machine_is_mv6281gtwge2()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SCAT100
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SCAT100
-# endif
-# define machine_is_scat100()	(machine_arch_type == MACH_TYPE_SCAT100)
-#else
-# define machine_is_scat100()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SANMINA
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SANMINA
-# endif
-# define machine_is_sanmina()	(machine_arch_type == MACH_TYPE_SANMINA)
-#else
-# define machine_is_sanmina()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MOMENTO
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MOMENTO
-# endif
-# define machine_is_momento()	(machine_arch_type == MACH_TYPE_MOMENTO)
-#else
-# define machine_is_momento()	(0)
-#endif
-
-#ifdef CONFIG_MACH_NUC9XX
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_NUC9XX
-# endif
-# define machine_is_nuc9xx()	(machine_arch_type == MACH_TYPE_NUC9XX)
-#else
-# define machine_is_nuc9xx()	(0)
-#endif
-
-#ifdef CONFIG_MACH_NUC910EVB
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_NUC910EVB
-# endif
-# define machine_is_nuc910evb()	(machine_arch_type == MACH_TYPE_NUC910EVB)
-#else
-# define machine_is_nuc910evb()	(0)
-#endif
-
-#ifdef CONFIG_MACH_NUC920EVB
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_NUC920EVB
-# endif
-# define machine_is_nuc920evb()	(machine_arch_type == MACH_TYPE_NUC920EVB)
-#else
-# define machine_is_nuc920evb()	(0)
-#endif
-
-#ifdef CONFIG_MACH_NUC950EVB
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_NUC950EVB
-# endif
-# define machine_is_nuc950evb()	(machine_arch_type == MACH_TYPE_NUC950EVB)
-#else
-# define machine_is_nuc950evb()	(0)
-#endif
-
-#ifdef CONFIG_MACH_NUC945EVB
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_NUC945EVB
-# endif
-# define machine_is_nuc945evb()	(machine_arch_type == MACH_TYPE_NUC945EVB)
-#else
-# define machine_is_nuc945evb()	(0)
-#endif
-
-#ifdef CONFIG_MACH_NUC960EVB
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_NUC960EVB
-# endif
-# define machine_is_nuc960evb()	(machine_arch_type == MACH_TYPE_NUC960EVB)
-#else
-# define machine_is_nuc960evb()	(0)
-#endif
-
-#ifdef CONFIG_MACH_NUC932EVB
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_NUC932EVB
-# endif
-# define machine_is_nuc932evb()	(machine_arch_type == MACH_TYPE_NUC932EVB)
-#else
-# define machine_is_nuc932evb()	(0)
-#endif
-
-#ifdef CONFIG_MACH_NUC900
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_NUC900
-# endif
-# define machine_is_nuc900()	(machine_arch_type == MACH_TYPE_NUC900)
-#else
-# define machine_is_nuc900()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SD1SOC
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SD1SOC
-# endif
-# define machine_is_sd1soc()	(machine_arch_type == MACH_TYPE_SD1SOC)
-#else
-# define machine_is_sd1soc()	(0)
-#endif
-
-#ifdef CONFIG_MACH_LN2440BC
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_LN2440BC
-# endif
-# define machine_is_ln2440bc()	(machine_arch_type == MACH_TYPE_LN2440BC)
-#else
-# define machine_is_ln2440bc()	(0)
-#endif
-
-#ifdef CONFIG_MACH_RSBC
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_RSBC
-# endif
-# define machine_is_rsbc()	(machine_arch_type == MACH_TYPE_RSBC)
-#else
-# define machine_is_rsbc()	(0)
-#endif
-
-#ifdef CONFIG_MACH_OPENRD_CLIENT
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_OPENRD_CLIENT
-# endif
-# define machine_is_openrd_client()	(machine_arch_type == MACH_TYPE_OPENRD_CLIENT)
-#else
-# define machine_is_openrd_client()	(0)
-#endif
-
-#ifdef CONFIG_MACH_HPIPAQ11X
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_HPIPAQ11X
-# endif
-# define machine_is_hpipaq11x()	(machine_arch_type == MACH_TYPE_HPIPAQ11X)
-#else
-# define machine_is_hpipaq11x()	(0)
-#endif
-
-#ifdef CONFIG_MACH_WAYLAND
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_WAYLAND
-# endif
-# define machine_is_wayland()	(machine_arch_type == MACH_TYPE_WAYLAND)
-#else
-# define machine_is_wayland()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ACNBSX102
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ACNBSX102
-# endif
-# define machine_is_acnbsx102()	(machine_arch_type == MACH_TYPE_ACNBSX102)
-#else
-# define machine_is_acnbsx102()	(0)
-#endif
-
-#ifdef CONFIG_MACH_HWAT91
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_HWAT91
-# endif
-# define machine_is_hwat91()	(machine_arch_type == MACH_TYPE_HWAT91)
-#else
-# define machine_is_hwat91()	(0)
-#endif
-
-#ifdef CONFIG_MACH_AT91SAM9263CS
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_AT91SAM9263CS
-# endif
-# define machine_is_at91sam9263cs()	(machine_arch_type == MACH_TYPE_AT91SAM9263CS)
-#else
-# define machine_is_at91sam9263cs()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CSB732
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CSB732
-# endif
-# define machine_is_csb732()	(machine_arch_type == MACH_TYPE_CSB732)
-#else
-# define machine_is_csb732()	(0)
-#endif
-
-#ifdef CONFIG_MACH_U8500
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_U8500
-# endif
-# define machine_is_u8500()	(machine_arch_type == MACH_TYPE_U8500)
-#else
-# define machine_is_u8500()	(0)
-#endif
-
-#ifdef CONFIG_MACH_HUQIU
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_HUQIU
-# endif
-# define machine_is_huqiu()	(machine_arch_type == MACH_TYPE_HUQIU)
-#else
-# define machine_is_huqiu()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MX51_EFIKASB
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MX51_EFIKASB
-# endif
-# define machine_is_mx51_efikasb()	(machine_arch_type == MACH_TYPE_MX51_EFIKASB)
-#else
-# define machine_is_mx51_efikasb()	(0)
-#endif
-
-#ifdef CONFIG_MACH_PMT1G
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PMT1G
-# endif
-# define machine_is_pmt1g()	(machine_arch_type == MACH_TYPE_PMT1G)
-#else
-# define machine_is_pmt1g()	(0)
-#endif
-
-#ifdef CONFIG_MACH_HTCELF
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_HTCELF
-# endif
-# define machine_is_htcelf()	(machine_arch_type == MACH_TYPE_HTCELF)
-#else
-# define machine_is_htcelf()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ARMADILLO420
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ARMADILLO420
-# endif
-# define machine_is_armadillo420()	(machine_arch_type == MACH_TYPE_ARMADILLO420)
-#else
-# define machine_is_armadillo420()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ARMADILLO440
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ARMADILLO440
-# endif
-# define machine_is_armadillo440()	(machine_arch_type == MACH_TYPE_ARMADILLO440)
-#else
-# define machine_is_armadillo440()	(0)
-#endif
-
-#ifdef CONFIG_MACH_U_CHIP_DUAL_ARM
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_U_CHIP_DUAL_ARM
-# endif
-# define machine_is_u_chip_dual_arm()	(machine_arch_type == MACH_TYPE_U_CHIP_DUAL_ARM)
-#else
-# define machine_is_u_chip_dual_arm()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CSR_BDB3
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CSR_BDB3
-# endif
-# define machine_is_csr_bdb3()	(machine_arch_type == MACH_TYPE_CSR_BDB3)
-#else
-# define machine_is_csr_bdb3()	(0)
-#endif
-
-#ifdef CONFIG_MACH_DOLBY_CAT1018
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_DOLBY_CAT1018
-# endif
-# define machine_is_dolby_cat1018()	(machine_arch_type == MACH_TYPE_DOLBY_CAT1018)
-#else
-# define machine_is_dolby_cat1018()	(0)
-#endif
-
-#ifdef CONFIG_MACH_HY9307
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_HY9307
-# endif
-# define machine_is_hy9307()	(machine_arch_type == MACH_TYPE_HY9307)
-#else
-# define machine_is_hy9307()	(0)
-#endif
-
-#ifdef CONFIG_MACH_A_ES
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_A_ES
-# endif
-# define machine_is_aspire_easystore()	(machine_arch_type == MACH_TYPE_A_ES)
-#else
-# define machine_is_aspire_easystore()	(0)
-#endif
-
-#ifdef CONFIG_MACH_DAVINCI_IRIF
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_DAVINCI_IRIF
-# endif
-# define machine_is_davinci_irif()	(machine_arch_type == MACH_TYPE_DAVINCI_IRIF)
-#else
-# define machine_is_davinci_irif()	(0)
-#endif
-
-#ifdef CONFIG_MACH_AGAMA9263
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_AGAMA9263
-# endif
-# define machine_is_agama9263()	(machine_arch_type == MACH_TYPE_AGAMA9263)
-#else
-# define machine_is_agama9263()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MARVELL_JASPER
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MARVELL_JASPER
-# endif
-# define machine_is_marvell_jasper()	(machine_arch_type == MACH_TYPE_MARVELL_JASPER)
-#else
-# define machine_is_marvell_jasper()	(0)
-#endif
-
-#ifdef CONFIG_MACH_FLINT
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_FLINT
-# endif
-# define machine_is_flint()	(machine_arch_type == MACH_TYPE_FLINT)
-#else
-# define machine_is_flint()	(0)
-#endif
-
-#ifdef CONFIG_MACH_TAVOREVB3
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TAVOREVB3
-# endif
-# define machine_is_tavorevb3()	(machine_arch_type == MACH_TYPE_TAVOREVB3)
-#else
-# define machine_is_tavorevb3()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SCH_M490
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SCH_M490
-# endif
-# define machine_is_sch_m490()	(machine_arch_type == MACH_TYPE_SCH_M490)
-#else
-# define machine_is_sch_m490()	(0)
-#endif
-
-#ifdef CONFIG_MACH_RBL01
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_RBL01
-# endif
-# define machine_is_rbl01()	(machine_arch_type == MACH_TYPE_RBL01)
-#else
-# define machine_is_rbl01()	(0)
-#endif
-
-#ifdef CONFIG_MACH_OMNIFI
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_OMNIFI
-# endif
-# define machine_is_omnifi()	(machine_arch_type == MACH_TYPE_OMNIFI)
-#else
-# define machine_is_omnifi()	(0)
-#endif
-
-#ifdef CONFIG_MACH_OTAVALO
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_OTAVALO
-# endif
-# define machine_is_otavalo()	(machine_arch_type == MACH_TYPE_OTAVALO)
-#else
-# define machine_is_otavalo()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SIENNA
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SIENNA
-# endif
-# define machine_is_sienna()	(machine_arch_type == MACH_TYPE_SIENNA)
-#else
-# define machine_is_sienna()	(0)
-#endif
-
-#ifdef CONFIG_MACH_HTC_EXCALIBUR_S620
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_HTC_EXCALIBUR_S620
-# endif
-# define machine_is_htc_excalibur_s620()	(machine_arch_type == MACH_TYPE_HTC_EXCALIBUR_S620)
-#else
-# define machine_is_htc_excalibur_s620()	(0)
-#endif
-
-#ifdef CONFIG_MACH_HTC_OPAL
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_HTC_OPAL
-# endif
-# define machine_is_htc_opal()	(machine_arch_type == MACH_TYPE_HTC_OPAL)
-#else
-# define machine_is_htc_opal()	(0)
-#endif
-
-#ifdef CONFIG_MACH_TOUCHBOOK
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TOUCHBOOK
-# endif
-# define machine_is_touchbook()	(machine_arch_type == MACH_TYPE_TOUCHBOOK)
-#else
-# define machine_is_touchbook()	(0)
-#endif
-
-#ifdef CONFIG_MACH_LATTE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_LATTE
-# endif
-# define machine_is_latte()	(machine_arch_type == MACH_TYPE_LATTE)
-#else
-# define machine_is_latte()	(0)
-#endif
-
-#ifdef CONFIG_MACH_XA200
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_XA200
-# endif
-# define machine_is_xa200()	(machine_arch_type == MACH_TYPE_XA200)
-#else
-# define machine_is_xa200()	(0)
-#endif
-
-#ifdef CONFIG_MACH_NIMROD
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_NIMROD
-# endif
-# define machine_is_nimrod()	(machine_arch_type == MACH_TYPE_NIMROD)
-#else
-# define machine_is_nimrod()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CC9P9215_3G
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CC9P9215_3G
-# endif
-# define machine_is_cc9p9215_3g()	(machine_arch_type == MACH_TYPE_CC9P9215_3G)
-#else
-# define machine_is_cc9p9215_3g()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CC9P9215_3GJS
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CC9P9215_3GJS
-# endif
-# define machine_is_cc9p9215_3gjs()	(machine_arch_type == MACH_TYPE_CC9P9215_3GJS)
-#else
-# define machine_is_cc9p9215_3gjs()	(0)
-#endif
-
-#ifdef CONFIG_MACH_TK71
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TK71
-# endif
-# define machine_is_tk71()	(machine_arch_type == MACH_TYPE_TK71)
-#else
-# define machine_is_tk71()	(0)
-#endif
-
-#ifdef CONFIG_MACH_COMHAM3525
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_COMHAM3525
-# endif
-# define machine_is_comham3525()	(machine_arch_type == MACH_TYPE_COMHAM3525)
-#else
-# define machine_is_comham3525()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MX31EREBUS
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MX31EREBUS
-# endif
-# define machine_is_mx31erebus()	(machine_arch_type == MACH_TYPE_MX31EREBUS)
-#else
-# define machine_is_mx31erebus()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MCARDMX27
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MCARDMX27
-# endif
-# define machine_is_mcardmx27()	(machine_arch_type == MACH_TYPE_MCARDMX27)
-#else
-# define machine_is_mcardmx27()	(0)
-#endif
-
-#ifdef CONFIG_MACH_PARADISE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PARADISE
-# endif
-# define machine_is_paradise()	(machine_arch_type == MACH_TYPE_PARADISE)
-#else
-# define machine_is_paradise()	(0)
-#endif
-
-#ifdef CONFIG_MACH_TIDE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TIDE
-# endif
-# define machine_is_tide()	(machine_arch_type == MACH_TYPE_TIDE)
-#else
-# define machine_is_tide()	(0)
-#endif
-
-#ifdef CONFIG_MACH_WZL2440
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_WZL2440
-# endif
-# define machine_is_wzl2440()	(machine_arch_type == MACH_TYPE_WZL2440)
-#else
-# define machine_is_wzl2440()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SDRDEMO
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SDRDEMO
-# endif
-# define machine_is_sdrdemo()	(machine_arch_type == MACH_TYPE_SDRDEMO)
-#else
-# define machine_is_sdrdemo()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ETHERCAN2
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ETHERCAN2
-# endif
-# define machine_is_ethercan2()	(machine_arch_type == MACH_TYPE_ETHERCAN2)
-#else
-# define machine_is_ethercan2()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ECMIMG20
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ECMIMG20
-# endif
-# define machine_is_ecmimg20()	(machine_arch_type == MACH_TYPE_ECMIMG20)
-#else
-# define machine_is_ecmimg20()	(0)
-#endif
-
-#ifdef CONFIG_MACH_OMAP_DRAGON
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_OMAP_DRAGON
-# endif
-# define machine_is_omap_dragon()	(machine_arch_type == MACH_TYPE_OMAP_DRAGON)
-#else
-# define machine_is_omap_dragon()	(0)
-#endif
-
-#ifdef CONFIG_MACH_HALO
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_HALO
-# endif
-# define machine_is_halo()	(machine_arch_type == MACH_TYPE_HALO)
-#else
-# define machine_is_halo()	(0)
-#endif
-
-#ifdef CONFIG_MACH_HUANGSHAN
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_HUANGSHAN
-# endif
-# define machine_is_huangshan()	(machine_arch_type == MACH_TYPE_HUANGSHAN)
-#else
-# define machine_is_huangshan()	(0)
-#endif
-
-#ifdef CONFIG_MACH_VL_MA2SC
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_VL_MA2SC
-# endif
-# define machine_is_vl_ma2sc()	(machine_arch_type == MACH_TYPE_VL_MA2SC)
-#else
-# define machine_is_vl_ma2sc()	(0)
-#endif
-
-#ifdef CONFIG_MACH_RAUMFELD_RC
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_RAUMFELD_RC
-# endif
-# define machine_is_raumfeld_rc()	(machine_arch_type == MACH_TYPE_RAUMFELD_RC)
-#else
-# define machine_is_raumfeld_rc()	(0)
-#endif
-
-#ifdef CONFIG_MACH_RAUMFELD_CONNECTOR
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_RAUMFELD_CONNECTOR
-# endif
-# define machine_is_raumfeld_connector()	(machine_arch_type == MACH_TYPE_RAUMFELD_CONNECTOR)
-#else
-# define machine_is_raumfeld_connector()	(0)
-#endif
-
-#ifdef CONFIG_MACH_RAUMFELD_SPEAKER
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_RAUMFELD_SPEAKER
-# endif
-# define machine_is_raumfeld_speaker()	(machine_arch_type == MACH_TYPE_RAUMFELD_SPEAKER)
-#else
-# define machine_is_raumfeld_speaker()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MULTIBUS_MASTER
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MULTIBUS_MASTER
-# endif
-# define machine_is_multibus_master()	(machine_arch_type == MACH_TYPE_MULTIBUS_MASTER)
-#else
-# define machine_is_multibus_master()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MULTIBUS_PBK
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MULTIBUS_PBK
-# endif
-# define machine_is_multibus_pbk()	(machine_arch_type == MACH_TYPE_MULTIBUS_PBK)
-#else
-# define machine_is_multibus_pbk()	(0)
-#endif
-
-#ifdef CONFIG_MACH_TNETV107X
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TNETV107X
-# endif
-# define machine_is_tnetv107x()	(machine_arch_type == MACH_TYPE_TNETV107X)
-#else
-# define machine_is_tnetv107x()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SNAKE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SNAKE
-# endif
-# define machine_is_snake()	(machine_arch_type == MACH_TYPE_SNAKE)
-#else
-# define machine_is_snake()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CWMX27
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CWMX27
-# endif
-# define machine_is_cwmx27()	(machine_arch_type == MACH_TYPE_CWMX27)
-#else
-# define machine_is_cwmx27()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SCH_M480
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SCH_M480
-# endif
-# define machine_is_sch_m480()	(machine_arch_type == MACH_TYPE_SCH_M480)
-#else
-# define machine_is_sch_m480()	(0)
-#endif
-
-#ifdef CONFIG_MACH_PLATYPUS
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PLATYPUS
-# endif
-# define machine_is_platypus()	(machine_arch_type == MACH_TYPE_PLATYPUS)
-#else
-# define machine_is_platypus()	(0)
-#endif
-
-#ifdef CONFIG_MACH_PSS2
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PSS2
-# endif
-# define machine_is_pss2()	(machine_arch_type == MACH_TYPE_PSS2)
-#else
-# define machine_is_pss2()	(0)
-#endif
-
-#ifdef CONFIG_MACH_DAVINCI_APM150
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_DAVINCI_APM150
-# endif
-# define machine_is_davinci_apm150()	(machine_arch_type == MACH_TYPE_DAVINCI_APM150)
-#else
-# define machine_is_davinci_apm150()	(0)
-#endif
-
-#ifdef CONFIG_MACH_STR9100
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_STR9100
-# endif
-# define machine_is_str9100()	(machine_arch_type == MACH_TYPE_STR9100)
-#else
-# define machine_is_str9100()	(0)
-#endif
-
-#ifdef CONFIG_MACH_NET5BIG
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_NET5BIG
-# endif
-# define machine_is_net5big()	(machine_arch_type == MACH_TYPE_NET5BIG)
-#else
-# define machine_is_net5big()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SEABED9263
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SEABED9263
-# endif
-# define machine_is_seabed9263()	(machine_arch_type == MACH_TYPE_SEABED9263)
-#else
-# define machine_is_seabed9263()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MX51_M2ID
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MX51_M2ID
-# endif
-# define machine_is_mx51_m2id()	(machine_arch_type == MACH_TYPE_MX51_M2ID)
-#else
-# define machine_is_mx51_m2id()	(0)
-#endif
-
-#ifdef CONFIG_MACH_OCTVOCPLUS_EB
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_OCTVOCPLUS_EB
-# endif
-# define machine_is_octvocplus_eb()	(machine_arch_type == MACH_TYPE_OCTVOCPLUS_EB)
-#else
-# define machine_is_octvocplus_eb()	(0)
-#endif
-
-#ifdef CONFIG_MACH_KLK_FIREFOX
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_KLK_FIREFOX
-# endif
-# define machine_is_klk_firefox()	(machine_arch_type == MACH_TYPE_KLK_FIREFOX)
-#else
-# define machine_is_klk_firefox()	(0)
-#endif
-
-#ifdef CONFIG_MACH_KLK_WIRMA_MODULE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_KLK_WIRMA_MODULE
-# endif
-# define machine_is_klk_wirma_module()	(machine_arch_type == MACH_TYPE_KLK_WIRMA_MODULE)
-#else
-# define machine_is_klk_wirma_module()	(0)
-#endif
-
-#ifdef CONFIG_MACH_KLK_WIRMA_MMI
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_KLK_WIRMA_MMI
-# endif
-# define machine_is_klk_wirma_mmi()	(machine_arch_type == MACH_TYPE_KLK_WIRMA_MMI)
-#else
-# define machine_is_klk_wirma_mmi()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SUPERSONIC
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SUPERSONIC
-# endif
-# define machine_is_supersonic()	(machine_arch_type == MACH_TYPE_SUPERSONIC)
-#else
-# define machine_is_supersonic()	(0)
-#endif
-
-#ifdef CONFIG_MACH_LIBERTY
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_LIBERTY
-# endif
-# define machine_is_liberty()	(machine_arch_type == MACH_TYPE_LIBERTY)
-#else
-# define machine_is_liberty()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MH355
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MH355
-# endif
-# define machine_is_mh355()	(machine_arch_type == MACH_TYPE_MH355)
-#else
-# define machine_is_mh355()	(0)
-#endif
-
-#ifdef CONFIG_MACH_PC7802
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PC7802
-# endif
-# define machine_is_pc7802()	(machine_arch_type == MACH_TYPE_PC7802)
-#else
-# define machine_is_pc7802()	(0)
-#endif
-
-#ifdef CONFIG_MACH_GNET_SGC
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_GNET_SGC
-# endif
-# define machine_is_gnet_sgc()	(machine_arch_type == MACH_TYPE_GNET_SGC)
-#else
-# define machine_is_gnet_sgc()	(0)
-#endif
-
-#ifdef CONFIG_MACH_EINSTEIN15
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_EINSTEIN15
-# endif
-# define machine_is_einstein15()	(machine_arch_type == MACH_TYPE_EINSTEIN15)
-#else
-# define machine_is_einstein15()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CMPD
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CMPD
-# endif
-# define machine_is_cmpd()	(machine_arch_type == MACH_TYPE_CMPD)
-#else
-# define machine_is_cmpd()	(0)
-#endif
-
-#ifdef CONFIG_MACH_DAVINCI_HASE1
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_DAVINCI_HASE1
-# endif
-# define machine_is_davinci_hase1()	(machine_arch_type == MACH_TYPE_DAVINCI_HASE1)
-#else
-# define machine_is_davinci_hase1()	(0)
-#endif
-
-#ifdef CONFIG_MACH_LGEINCITEPHONE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_LGEINCITEPHONE
-# endif
-# define machine_is_lgeincitephone()	(machine_arch_type == MACH_TYPE_LGEINCITEPHONE)
-#else
-# define machine_is_lgeincitephone()	(0)
-#endif
-
-#ifdef CONFIG_MACH_EA313X
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_EA313X
-# endif
-# define machine_is_ea313x()	(machine_arch_type == MACH_TYPE_EA313X)
-#else
-# define machine_is_ea313x()	(0)
-#endif
-
-#ifdef CONFIG_MACH_FWBD_39064
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_FWBD_39064
-# endif
-# define machine_is_fwbd_39064()	(machine_arch_type == MACH_TYPE_FWBD_39064)
-#else
-# define machine_is_fwbd_39064()	(0)
-#endif
-
-#ifdef CONFIG_MACH_FWBD_390128
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_FWBD_390128
-# endif
-# define machine_is_fwbd_390128()	(machine_arch_type == MACH_TYPE_FWBD_390128)
-#else
-# define machine_is_fwbd_390128()	(0)
-#endif
-
-#ifdef CONFIG_MACH_PELCO_MOE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PELCO_MOE
-# endif
-# define machine_is_pelco_moe()	(machine_arch_type == MACH_TYPE_PELCO_MOE)
-#else
-# define machine_is_pelco_moe()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MINIMIX27
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MINIMIX27
-# endif
-# define machine_is_minimix27()	(machine_arch_type == MACH_TYPE_MINIMIX27)
-#else
-# define machine_is_minimix27()	(0)
-#endif
-
-#ifdef CONFIG_MACH_OMAP3_THUNDER
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_OMAP3_THUNDER
-# endif
-# define machine_is_omap3_thunder()	(machine_arch_type == MACH_TYPE_OMAP3_THUNDER)
-#else
-# define machine_is_omap3_thunder()	(0)
-#endif
-
-#ifdef CONFIG_MACH_PASSIONC
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PASSIONC
-# endif
-# define machine_is_passionc()	(machine_arch_type == MACH_TYPE_PASSIONC)
-#else
-# define machine_is_passionc()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MX27AMATA
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MX27AMATA
-# endif
-# define machine_is_mx27amata()	(machine_arch_type == MACH_TYPE_MX27AMATA)
-#else
-# define machine_is_mx27amata()	(0)
-#endif
-
-#ifdef CONFIG_MACH_BGAT1
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_BGAT1
-# endif
-# define machine_is_bgat1()	(machine_arch_type == MACH_TYPE_BGAT1)
-#else
-# define machine_is_bgat1()	(0)
-#endif
-
-#ifdef CONFIG_MACH_BUZZ
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_BUZZ
-# endif
-# define machine_is_buzz()	(machine_arch_type == MACH_TYPE_BUZZ)
-#else
-# define machine_is_buzz()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MB9G20
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MB9G20
-# endif
-# define machine_is_mb9g20()	(machine_arch_type == MACH_TYPE_MB9G20)
-#else
-# define machine_is_mb9g20()	(0)
-#endif
-
-#ifdef CONFIG_MACH_YUSHAN
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_YUSHAN
-# endif
-# define machine_is_yushan()	(machine_arch_type == MACH_TYPE_YUSHAN)
-#else
-# define machine_is_yushan()	(0)
-#endif
-
-#ifdef CONFIG_MACH_LIZARD
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_LIZARD
-# endif
-# define machine_is_lizard()	(machine_arch_type == MACH_TYPE_LIZARD)
-#else
-# define machine_is_lizard()	(0)
-#endif
-
-#ifdef CONFIG_MACH_OMAP3POLYCOM
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_OMAP3POLYCOM
-# endif
-# define machine_is_omap3polycom()	(machine_arch_type == MACH_TYPE_OMAP3POLYCOM)
-#else
-# define machine_is_omap3polycom()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SMDKV210
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SMDKV210
-# endif
-# define machine_is_smdkv210()	(machine_arch_type == MACH_TYPE_SMDKV210)
-#else
-# define machine_is_smdkv210()	(0)
-#endif
-
-#ifdef CONFIG_MACH_BRAVO
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_BRAVO
-# endif
-# define machine_is_bravo()	(machine_arch_type == MACH_TYPE_BRAVO)
-#else
-# define machine_is_bravo()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SIOGENTOO1
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SIOGENTOO1
-# endif
-# define machine_is_siogentoo1()	(machine_arch_type == MACH_TYPE_SIOGENTOO1)
-#else
-# define machine_is_siogentoo1()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SIOGENTOO2
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SIOGENTOO2
-# endif
-# define machine_is_siogentoo2()	(machine_arch_type == MACH_TYPE_SIOGENTOO2)
-#else
-# define machine_is_siogentoo2()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SM3K
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SM3K
-# endif
-# define machine_is_sm3k()	(machine_arch_type == MACH_TYPE_SM3K)
-#else
-# define machine_is_sm3k()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ACER_TEMPO_F900
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ACER_TEMPO_F900
-# endif
-# define machine_is_acer_tempo_f900()	(machine_arch_type == MACH_TYPE_ACER_TEMPO_F900)
-#else
-# define machine_is_acer_tempo_f900()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SST61VC010_DEV
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SST61VC010_DEV
-# endif
-# define machine_is_sst61vc010_dev()	(machine_arch_type == MACH_TYPE_SST61VC010_DEV)
-#else
-# define machine_is_sst61vc010_dev()	(0)
-#endif
-
-#ifdef CONFIG_MACH_GLITTERTIND
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_GLITTERTIND
-# endif
-# define machine_is_glittertind()	(machine_arch_type == MACH_TYPE_GLITTERTIND)
-#else
-# define machine_is_glittertind()	(0)
-#endif
-
-#ifdef CONFIG_MACH_OMAP_ZOOM3
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_OMAP_ZOOM3
-# endif
-# define machine_is_omap_zoom3()	(machine_arch_type == MACH_TYPE_OMAP_ZOOM3)
-#else
-# define machine_is_omap_zoom3()	(0)
-#endif
-
-#ifdef CONFIG_MACH_OMAP_3630SDP
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_OMAP_3630SDP
-# endif
-# define machine_is_omap_3630sdp()	(machine_arch_type == MACH_TYPE_OMAP_3630SDP)
-#else
-# define machine_is_omap_3630sdp()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CYBOOK2440
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CYBOOK2440
-# endif
-# define machine_is_cybook2440()	(machine_arch_type == MACH_TYPE_CYBOOK2440)
-#else
-# define machine_is_cybook2440()	(0)
-#endif
-
-#ifdef CONFIG_MACH_TORINO_S
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TORINO_S
-# endif
-# define machine_is_torino_s()	(machine_arch_type == MACH_TYPE_TORINO_S)
-#else
-# define machine_is_torino_s()	(0)
-#endif
-
-#ifdef CONFIG_MACH_HAVANA
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_HAVANA
-# endif
-# define machine_is_havana()	(machine_arch_type == MACH_TYPE_HAVANA)
-#else
-# define machine_is_havana()	(0)
-#endif
-
-#ifdef CONFIG_MACH_BEAUMONT_11
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_BEAUMONT_11
-# endif
-# define machine_is_beaumont_11()	(machine_arch_type == MACH_TYPE_BEAUMONT_11)
-#else
-# define machine_is_beaumont_11()	(0)
-#endif
-
-#ifdef CONFIG_MACH_VANGUARD
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_VANGUARD
-# endif
-# define machine_is_vanguard()	(machine_arch_type == MACH_TYPE_VANGUARD)
-#else
-# define machine_is_vanguard()	(0)
-#endif
-
-#ifdef CONFIG_MACH_S5PC110_DRACO
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_S5PC110_DRACO
-# endif
-# define machine_is_s5pc110_draco()	(machine_arch_type == MACH_TYPE_S5PC110_DRACO)
-#else
-# define machine_is_s5pc110_draco()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CARTESIO_TWO
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CARTESIO_TWO
-# endif
-# define machine_is_cartesio_two()	(machine_arch_type == MACH_TYPE_CARTESIO_TWO)
-#else
-# define machine_is_cartesio_two()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ASTER
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ASTER
-# endif
-# define machine_is_aster()	(machine_arch_type == MACH_TYPE_ASTER)
-#else
-# define machine_is_aster()	(0)
-#endif
-
-#ifdef CONFIG_MACH_VOGUESV210
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_VOGUESV210
-# endif
-# define machine_is_voguesv210()	(machine_arch_type == MACH_TYPE_VOGUESV210)
-#else
-# define machine_is_voguesv210()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ACM500X
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ACM500X
-# endif
-# define machine_is_acm500x()	(machine_arch_type == MACH_TYPE_ACM500X)
-#else
-# define machine_is_acm500x()	(0)
-#endif
-
-#ifdef CONFIG_MACH_KM9260
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_KM9260
-# endif
-# define machine_is_km9260()	(machine_arch_type == MACH_TYPE_KM9260)
-#else
-# define machine_is_km9260()	(0)
-#endif
-
-#ifdef CONFIG_MACH_NIDEFLEXG1
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_NIDEFLEXG1
-# endif
-# define machine_is_nideflexg1()	(machine_arch_type == MACH_TYPE_NIDEFLEXG1)
-#else
-# define machine_is_nideflexg1()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CTERA_PLUG_IO
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CTERA_PLUG_IO
-# endif
-# define machine_is_ctera_plug_io()	(machine_arch_type == MACH_TYPE_CTERA_PLUG_IO)
-#else
-# define machine_is_ctera_plug_io()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SMARTQ7
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SMARTQ7
-# endif
-# define machine_is_smartq7()	(machine_arch_type == MACH_TYPE_SMARTQ7)
-#else
-# define machine_is_smartq7()	(0)
-#endif
-
-#ifdef CONFIG_MACH_AT91SAM9G10EK2
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_AT91SAM9G10EK2
-# endif
-# define machine_is_at91sam9g10ek2()	(machine_arch_type == MACH_TYPE_AT91SAM9G10EK2)
-#else
-# define machine_is_at91sam9g10ek2()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ASUSP527
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ASUSP527
-# endif
-# define machine_is_asusp527()	(machine_arch_type == MACH_TYPE_ASUSP527)
-#else
-# define machine_is_asusp527()	(0)
-#endif
-
-#ifdef CONFIG_MACH_AT91SAM9G20MPM2
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_AT91SAM9G20MPM2
-# endif
-# define machine_is_at91sam9g20mpm2()	(machine_arch_type == MACH_TYPE_AT91SAM9G20MPM2)
-#else
-# define machine_is_at91sam9g20mpm2()	(0)
-#endif
-
-#ifdef CONFIG_MACH_TOPASA900
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TOPASA900
-# endif
-# define machine_is_topasa900()	(machine_arch_type == MACH_TYPE_TOPASA900)
-#else
-# define machine_is_topasa900()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ELECTRUM_100
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ELECTRUM_100
-# endif
-# define machine_is_electrum_100()	(machine_arch_type == MACH_TYPE_ELECTRUM_100)
-#else
-# define machine_is_electrum_100()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MX51GRB
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MX51GRB
-# endif
-# define machine_is_mx51grb()	(machine_arch_type == MACH_TYPE_MX51GRB)
-#else
-# define machine_is_mx51grb()	(0)
-#endif
-
-#ifdef CONFIG_MACH_XEA300
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_XEA300
-# endif
-# define machine_is_xea300()	(machine_arch_type == MACH_TYPE_XEA300)
-#else
-# define machine_is_xea300()	(0)
-#endif
-
-#ifdef CONFIG_MACH_HTCSTARTREK
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_HTCSTARTREK
-# endif
-# define machine_is_htcstartrek()	(machine_arch_type == MACH_TYPE_HTCSTARTREK)
-#else
-# define machine_is_htcstartrek()	(0)
-#endif
-
-#ifdef CONFIG_MACH_LIMA
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_LIMA
-# endif
-# define machine_is_lima()	(machine_arch_type == MACH_TYPE_LIMA)
-#else
-# define machine_is_lima()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CSB740
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CSB740
-# endif
-# define machine_is_csb740()	(machine_arch_type == MACH_TYPE_CSB740)
-#else
-# define machine_is_csb740()	(0)
-#endif
-
-#ifdef CONFIG_MACH_USB_S8815
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_USB_S8815
-# endif
-# define machine_is_usb_s8815()	(machine_arch_type == MACH_TYPE_USB_S8815)
-#else
-# define machine_is_usb_s8815()	(0)
-#endif
-
-#ifdef CONFIG_MACH_WATSON_EFM_PLUGIN
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_WATSON_EFM_PLUGIN
-# endif
-# define machine_is_watson_efm_plugin()	(machine_arch_type == MACH_TYPE_WATSON_EFM_PLUGIN)
-#else
-# define machine_is_watson_efm_plugin()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MILKYWAY
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MILKYWAY
-# endif
-# define machine_is_milkyway()	(machine_arch_type == MACH_TYPE_MILKYWAY)
-#else
-# define machine_is_milkyway()	(0)
-#endif
-
-#ifdef CONFIG_MACH_G4EVM
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_G4EVM
-# endif
-# define machine_is_g4evm()	(machine_arch_type == MACH_TYPE_G4EVM)
-#else
-# define machine_is_g4evm()	(0)
-#endif
-
-#ifdef CONFIG_MACH_PICOMOD6
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PICOMOD6
-# endif
-# define machine_is_picomod6()	(machine_arch_type == MACH_TYPE_PICOMOD6)
-#else
-# define machine_is_picomod6()	(0)
-#endif
-
-#ifdef CONFIG_MACH_OMAPL138_HAWKBOARD
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_OMAPL138_HAWKBOARD
-# endif
-# define machine_is_omapl138_hawkboard()	(machine_arch_type == MACH_TYPE_OMAPL138_HAWKBOARD)
-#else
-# define machine_is_omapl138_hawkboard()	(0)
-#endif
-
-#ifdef CONFIG_MACH_IP6000
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_IP6000
-# endif
-# define machine_is_ip6000()	(machine_arch_type == MACH_TYPE_IP6000)
-#else
-# define machine_is_ip6000()	(0)
-#endif
-
-#ifdef CONFIG_MACH_IP6010
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_IP6010
-# endif
-# define machine_is_ip6010()	(machine_arch_type == MACH_TYPE_IP6010)
-#else
-# define machine_is_ip6010()	(0)
-#endif
-
-#ifdef CONFIG_MACH_UTM400
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_UTM400
-# endif
-# define machine_is_utm400()	(machine_arch_type == MACH_TYPE_UTM400)
-#else
-# define machine_is_utm400()	(0)
-#endif
-
-#ifdef CONFIG_MACH_OMAP3_ZYBEX
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_OMAP3_ZYBEX
-# endif
-# define machine_is_omap3_zybex()	(machine_arch_type == MACH_TYPE_OMAP3_ZYBEX)
-#else
-# define machine_is_omap3_zybex()	(0)
-#endif
-
-#ifdef CONFIG_MACH_WIRELESS_SPACE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_WIRELESS_SPACE
-# endif
-# define machine_is_wireless_space()	(machine_arch_type == MACH_TYPE_WIRELESS_SPACE)
-#else
-# define machine_is_wireless_space()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SX560
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SX560
-# endif
-# define machine_is_sx560()	(machine_arch_type == MACH_TYPE_SX560)
-#else
-# define machine_is_sx560()	(0)
-#endif
-
-#ifdef CONFIG_MACH_TS41X
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TS41X
-# endif
-# define machine_is_ts41x()	(machine_arch_type == MACH_TYPE_TS41X)
-#else
-# define machine_is_ts41x()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ELPHEL10373
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ELPHEL10373
-# endif
-# define machine_is_elphel10373()	(machine_arch_type == MACH_TYPE_ELPHEL10373)
-#else
-# define machine_is_elphel10373()	(0)
-#endif
-
-#ifdef CONFIG_MACH_RHOBOT
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_RHOBOT
-# endif
-# define machine_is_rhobot()	(machine_arch_type == MACH_TYPE_RHOBOT)
-#else
-# define machine_is_rhobot()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MX51_REFRESH
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MX51_REFRESH
-# endif
-# define machine_is_mx51_refresh()	(machine_arch_type == MACH_TYPE_MX51_REFRESH)
-#else
-# define machine_is_mx51_refresh()	(0)
-#endif
-
-#ifdef CONFIG_MACH_LS9260
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_LS9260
-# endif
-# define machine_is_ls9260()	(machine_arch_type == MACH_TYPE_LS9260)
-#else
-# define machine_is_ls9260()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SHANK
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SHANK
-# endif
-# define machine_is_shank()	(machine_arch_type == MACH_TYPE_SHANK)
-#else
-# define machine_is_shank()	(0)
-#endif
-
-#ifdef CONFIG_MACH_QSD8X50_ST1
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_QSD8X50_ST1
-# endif
-# define machine_is_qsd8x50_st1()	(machine_arch_type == MACH_TYPE_QSD8X50_ST1)
-#else
-# define machine_is_qsd8x50_st1()	(0)
-#endif
-
-#ifdef CONFIG_MACH_AT91SAM9M10EKES
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_AT91SAM9M10EKES
-# endif
-# define machine_is_at91sam9m10ekes()	(machine_arch_type == MACH_TYPE_AT91SAM9M10EKES)
-#else
-# define machine_is_at91sam9m10ekes()	(0)
-#endif
-
-#ifdef CONFIG_MACH_HIRAM
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_HIRAM
-# endif
-# define machine_is_hiram()	(machine_arch_type == MACH_TYPE_HIRAM)
-#else
-# define machine_is_hiram()	(0)
-#endif
-
-#ifdef CONFIG_MACH_PHY3250
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PHY3250
-# endif
-# define machine_is_phy3250()	(machine_arch_type == MACH_TYPE_PHY3250)
-#else
-# define machine_is_phy3250()	(0)
-#endif
-
-#ifdef CONFIG_MACH_EA3250
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_EA3250
-# endif
-# define machine_is_ea3250()	(machine_arch_type == MACH_TYPE_EA3250)
-#else
-# define machine_is_ea3250()	(0)
-#endif
-
-#ifdef CONFIG_MACH_FDI3250
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_FDI3250
-# endif
-# define machine_is_fdi3250()	(machine_arch_type == MACH_TYPE_FDI3250)
-#else
-# define machine_is_fdi3250()	(0)
-#endif
-
-#ifdef CONFIG_MACH_WHITESTONE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_WHITESTONE
-# endif
-# define machine_is_whitestone()	(machine_arch_type == MACH_TYPE_WHITESTONE)
-#else
-# define machine_is_whitestone()	(0)
-#endif
-
-#ifdef CONFIG_MACH_AT91SAM9263NIT
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_AT91SAM9263NIT
-# endif
-# define machine_is_at91sam9263nit()	(machine_arch_type == MACH_TYPE_AT91SAM9263NIT)
-#else
-# define machine_is_at91sam9263nit()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CCMX51
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CCMX51
-# endif
-# define machine_is_ccmx51()	(machine_arch_type == MACH_TYPE_CCMX51)
-#else
-# define machine_is_ccmx51()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CCMX51JS
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CCMX51JS
-# endif
-# define machine_is_ccmx51js()	(machine_arch_type == MACH_TYPE_CCMX51JS)
-#else
-# define machine_is_ccmx51js()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CCWMX51
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CCWMX51
-# endif
-# define machine_is_ccwmx51()	(machine_arch_type == MACH_TYPE_CCWMX51)
-#else
-# define machine_is_ccwmx51()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CCWMX51JS
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CCWMX51JS
-# endif
-# define machine_is_ccwmx51js()	(machine_arch_type == MACH_TYPE_CCWMX51JS)
-#else
-# define machine_is_ccwmx51js()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MINI6410
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MINI6410
-# endif
-# define machine_is_mini6410()	(machine_arch_type == MACH_TYPE_MINI6410)
-#else
-# define machine_is_mini6410()	(0)
-#endif
-
-#ifdef CONFIG_MACH_TINY6410
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TINY6410
-# endif
-# define machine_is_tiny6410()	(machine_arch_type == MACH_TYPE_TINY6410)
-#else
-# define machine_is_tiny6410()	(0)
-#endif
-
-#ifdef CONFIG_MACH_NANO6410
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_NANO6410
-# endif
-# define machine_is_nano6410()	(machine_arch_type == MACH_TYPE_NANO6410)
-#else
-# define machine_is_nano6410()	(0)
-#endif
-
-#ifdef CONFIG_MACH_AT572D940HFNLDB
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_AT572D940HFNLDB
-# endif
-# define machine_is_at572d940hfnldb()	(machine_arch_type == MACH_TYPE_AT572D940HFNLDB)
-#else
-# define machine_is_at572d940hfnldb()	(0)
-#endif
-
-#ifdef CONFIG_MACH_HTCLEO
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_HTCLEO
-# endif
-# define machine_is_htcleo()	(machine_arch_type == MACH_TYPE_HTCLEO)
-#else
-# define machine_is_htcleo()	(0)
-#endif
-
-#ifdef CONFIG_MACH_AVP13
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_AVP13
-# endif
-# define machine_is_avp13()	(machine_arch_type == MACH_TYPE_AVP13)
-#else
-# define machine_is_avp13()	(0)
-#endif
-
-#ifdef CONFIG_MACH_XXSVIDEOD
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_XXSVIDEOD
-# endif
-# define machine_is_xxsvideod()	(machine_arch_type == MACH_TYPE_XXSVIDEOD)
-#else
-# define machine_is_xxsvideod()	(0)
-#endif
-
-#ifdef CONFIG_MACH_VPNEXT
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_VPNEXT
-# endif
-# define machine_is_vpnext()	(machine_arch_type == MACH_TYPE_VPNEXT)
-#else
-# define machine_is_vpnext()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SWARCO_ITC3
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SWARCO_ITC3
-# endif
-# define machine_is_swarco_itc3()	(machine_arch_type == MACH_TYPE_SWARCO_ITC3)
-#else
-# define machine_is_swarco_itc3()	(0)
-#endif
-
-#ifdef CONFIG_MACH_TX51
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TX51
-# endif
-# define machine_is_tx51()	(machine_arch_type == MACH_TYPE_TX51)
-#else
-# define machine_is_tx51()	(0)
-#endif
-
-#ifdef CONFIG_MACH_DOLBY_CAT1021
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_DOLBY_CAT1021
-# endif
-# define machine_is_dolby_cat1021()	(machine_arch_type == MACH_TYPE_DOLBY_CAT1021)
-#else
-# define machine_is_dolby_cat1021()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MX28EVK
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MX28EVK
-# endif
-# define machine_is_mx28evk()	(machine_arch_type == MACH_TYPE_MX28EVK)
-#else
-# define machine_is_mx28evk()	(0)
-#endif
-
-#ifdef CONFIG_MACH_PHOENIX260
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PHOENIX260
-# endif
-# define machine_is_phoenix260()	(machine_arch_type == MACH_TYPE_PHOENIX260)
-#else
-# define machine_is_phoenix260()	(0)
-#endif
-
-#ifdef CONFIG_MACH_UVACA_STORK
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_UVACA_STORK
-# endif
-# define machine_is_uvaca_stork()	(machine_arch_type == MACH_TYPE_UVACA_STORK)
-#else
-# define machine_is_uvaca_stork()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SMARTQ5
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SMARTQ5
-# endif
-# define machine_is_smartq5()	(machine_arch_type == MACH_TYPE_SMARTQ5)
-#else
-# define machine_is_smartq5()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ALL3078
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ALL3078
-# endif
-# define machine_is_all3078()	(machine_arch_type == MACH_TYPE_ALL3078)
-#else
-# define machine_is_all3078()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CTERA_2BAY_DS
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CTERA_2BAY_DS
-# endif
-# define machine_is_ctera_2bay_ds()	(machine_arch_type == MACH_TYPE_CTERA_2BAY_DS)
-#else
-# define machine_is_ctera_2bay_ds()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SIOGENTOO3
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SIOGENTOO3
-# endif
-# define machine_is_siogentoo3()	(machine_arch_type == MACH_TYPE_SIOGENTOO3)
-#else
-# define machine_is_siogentoo3()	(0)
-#endif
-
-#ifdef CONFIG_MACH_EPB5000
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_EPB5000
-# endif
-# define machine_is_epb5000()	(machine_arch_type == MACH_TYPE_EPB5000)
-#else
-# define machine_is_epb5000()	(0)
-#endif
-
-#ifdef CONFIG_MACH_HY9263
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_HY9263
-# endif
-# define machine_is_hy9263()	(machine_arch_type == MACH_TYPE_HY9263)
-#else
-# define machine_is_hy9263()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ACER_TEMPO_M900
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ACER_TEMPO_M900
-# endif
-# define machine_is_acer_tempo_m900()	(machine_arch_type == MACH_TYPE_ACER_TEMPO_M900)
-#else
-# define machine_is_acer_tempo_m900()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ACER_TEMPO_DX900
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ACER_TEMPO_DX900
-# endif
-# define machine_is_acer_tempo_dx650()	(machine_arch_type == MACH_TYPE_ACER_TEMPO_DX900)
-#else
-# define machine_is_acer_tempo_dx650()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ACER_TEMPO_X960
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ACER_TEMPO_X960
-# endif
-# define machine_is_acer_tempo_x960()	(machine_arch_type == MACH_TYPE_ACER_TEMPO_X960)
-#else
-# define machine_is_acer_tempo_x960()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ACER_ETEN_V900
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ACER_ETEN_V900
-# endif
-# define machine_is_acer_eten_v900()	(machine_arch_type == MACH_TYPE_ACER_ETEN_V900)
-#else
-# define machine_is_acer_eten_v900()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ACER_ETEN_X900
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ACER_ETEN_X900
-# endif
-# define machine_is_acer_eten_x900()	(machine_arch_type == MACH_TYPE_ACER_ETEN_X900)
-#else
-# define machine_is_acer_eten_x900()	(0)
-#endif
-
-#ifdef CONFIG_MACH_BONNELL
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_BONNELL
-# endif
-# define machine_is_bonnell()	(machine_arch_type == MACH_TYPE_BONNELL)
-#else
-# define machine_is_bonnell()	(0)
-#endif
-
-#ifdef CONFIG_MACH_OHT_MX27
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_OHT_MX27
-# endif
-# define machine_is_oht_mx27()	(machine_arch_type == MACH_TYPE_OHT_MX27)
-#else
-# define machine_is_oht_mx27()	(0)
-#endif
-
-#ifdef CONFIG_MACH_HTCQUARTZ
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_HTCQUARTZ
-# endif
-# define machine_is_htcquartz()	(machine_arch_type == MACH_TYPE_HTCQUARTZ)
-#else
-# define machine_is_htcquartz()	(0)
-#endif
-
-#ifdef CONFIG_MACH_DAVINCI_DM6467TEVM
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_DAVINCI_DM6467TEVM
-# endif
-# define machine_is_davinci_dm6467tevm()	(machine_arch_type == MACH_TYPE_DAVINCI_DM6467TEVM)
-#else
-# define machine_is_davinci_dm6467tevm()	(0)
-#endif
-
-#ifdef CONFIG_MACH_C3AX03
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_C3AX03
-# endif
-# define machine_is_c3ax03()	(machine_arch_type == MACH_TYPE_C3AX03)
-#else
-# define machine_is_c3ax03()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MXT_TD60
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MXT_TD60
-# endif
-# define machine_is_mxt_td60()	(machine_arch_type == MACH_TYPE_MXT_TD60)
-#else
-# define machine_is_mxt_td60()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ESYX
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ESYX
-# endif
-# define machine_is_esyx()	(machine_arch_type == MACH_TYPE_ESYX)
-#else
-# define machine_is_esyx()	(0)
-#endif
-
-#ifdef CONFIG_MACH_DOVE_DB2
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_DOVE_DB2
-# endif
-# define machine_is_dove_db2()	(machine_arch_type == MACH_TYPE_DOVE_DB2)
-#else
-# define machine_is_dove_db2()	(0)
-#endif
-
-#ifdef CONFIG_MACH_BULLDOG
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_BULLDOG
-# endif
-# define machine_is_bulldog()	(machine_arch_type == MACH_TYPE_BULLDOG)
-#else
-# define machine_is_bulldog()	(0)
-#endif
-
-#ifdef CONFIG_MACH_DERELL_ME2000
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_DERELL_ME2000
-# endif
-# define machine_is_derell_me2000()	(machine_arch_type == MACH_TYPE_DERELL_ME2000)
-#else
-# define machine_is_derell_me2000()	(0)
-#endif
-
-#ifdef CONFIG_MACH_BCMRING_BASE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_BCMRING_BASE
-# endif
-# define machine_is_bcmring_base()	(machine_arch_type == MACH_TYPE_BCMRING_BASE)
-#else
-# define machine_is_bcmring_base()	(0)
-#endif
-
-#ifdef CONFIG_MACH_BCMRING_EVM
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_BCMRING_EVM
-# endif
-# define machine_is_bcmring_evm()	(machine_arch_type == MACH_TYPE_BCMRING_EVM)
-#else
-# define machine_is_bcmring_evm()	(0)
-#endif
-
-#ifdef CONFIG_MACH_BCMRING_EVM_JAZZ
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_BCMRING_EVM_JAZZ
-# endif
-# define machine_is_bcmring_evm_jazz()	(machine_arch_type == MACH_TYPE_BCMRING_EVM_JAZZ)
-#else
-# define machine_is_bcmring_evm_jazz()	(0)
-#endif
-
-#ifdef CONFIG_MACH_BCMRING_SP
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_BCMRING_SP
-# endif
-# define machine_is_bcmring_sp()	(machine_arch_type == MACH_TYPE_BCMRING_SP)
-#else
-# define machine_is_bcmring_sp()	(0)
-#endif
-
-#ifdef CONFIG_MACH_BCMRING_SV
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_BCMRING_SV
-# endif
-# define machine_is_bcmring_sv()	(machine_arch_type == MACH_TYPE_BCMRING_SV)
-#else
-# define machine_is_bcmring_sv()	(0)
-#endif
-
-#ifdef CONFIG_MACH_BCMRING_SV_JAZZ
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_BCMRING_SV_JAZZ
-# endif
-# define machine_is_bcmring_sv_jazz()	(machine_arch_type == MACH_TYPE_BCMRING_SV_JAZZ)
-#else
-# define machine_is_bcmring_sv_jazz()	(0)
-#endif
-
-#ifdef CONFIG_MACH_BCMRING_TABLET
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_BCMRING_TABLET
-# endif
-# define machine_is_bcmring_tablet()	(machine_arch_type == MACH_TYPE_BCMRING_TABLET)
-#else
-# define machine_is_bcmring_tablet()	(0)
-#endif
-
-#ifdef CONFIG_MACH_BCMRING_VP
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_BCMRING_VP
-# endif
-# define machine_is_bcmring_vp()	(machine_arch_type == MACH_TYPE_BCMRING_VP)
-#else
-# define machine_is_bcmring_vp()	(0)
-#endif
-
-#ifdef CONFIG_MACH_BCMRING_EVM_SEIKOR
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_BCMRING_EVM_SEIKOR
-# endif
-# define machine_is_bcmring_evm_seikor()	(machine_arch_type == MACH_TYPE_BCMRING_EVM_SEIKOR)
-#else
-# define machine_is_bcmring_evm_seikor()	(0)
-#endif
-
-#ifdef CONFIG_MACH_BCMRING_SP_WQVGA
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_BCMRING_SP_WQVGA
-# endif
-# define machine_is_bcmring_sp_wqvga()	(machine_arch_type == MACH_TYPE_BCMRING_SP_WQVGA)
-#else
-# define machine_is_bcmring_sp_wqvga()	(0)
-#endif
-
-#ifdef CONFIG_MACH_BCMRING_CUSTOM
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_BCMRING_CUSTOM
-# endif
-# define machine_is_bcmring_custom()	(machine_arch_type == MACH_TYPE_BCMRING_CUSTOM)
-#else
-# define machine_is_bcmring_custom()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ACER_S200
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ACER_S200
-# endif
-# define machine_is_acer_s200()	(machine_arch_type == MACH_TYPE_ACER_S200)
-#else
-# define machine_is_acer_s200()	(0)
-#endif
-
-#ifdef CONFIG_MACH_BT270
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_BT270
-# endif
-# define machine_is_bt270()	(machine_arch_type == MACH_TYPE_BT270)
-#else
-# define machine_is_bt270()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ISEO
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ISEO
-# endif
-# define machine_is_iseo()	(machine_arch_type == MACH_TYPE_ISEO)
-#else
-# define machine_is_iseo()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CEZANNE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CEZANNE
-# endif
-# define machine_is_cezanne()	(machine_arch_type == MACH_TYPE_CEZANNE)
-#else
-# define machine_is_cezanne()	(0)
-#endif
-
-#ifdef CONFIG_MACH_LUCCA
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_LUCCA
-# endif
-# define machine_is_lucca()	(machine_arch_type == MACH_TYPE_LUCCA)
-#else
-# define machine_is_lucca()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SUPERSMART
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SUPERSMART
-# endif
-# define machine_is_supersmart()	(machine_arch_type == MACH_TYPE_SUPERSMART)
-#else
-# define machine_is_supersmart()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CS_MISANO
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CS_MISANO
-# endif
-# define machine_is_arm11_board()	(machine_arch_type == MACH_TYPE_CS_MISANO)
-#else
-# define machine_is_arm11_board()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MAGNOLIA2
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MAGNOLIA2
-# endif
-# define machine_is_magnolia2()	(machine_arch_type == MACH_TYPE_MAGNOLIA2)
-#else
-# define machine_is_magnolia2()	(0)
-#endif
-
-#ifdef CONFIG_MACH_EMXX
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_EMXX
-# endif
-# define machine_is_emxx()	(machine_arch_type == MACH_TYPE_EMXX)
-#else
-# define machine_is_emxx()	(0)
-#endif
-
-#ifdef CONFIG_MACH_OUTLAW
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_OUTLAW
-# endif
-# define machine_is_outlaw()	(machine_arch_type == MACH_TYPE_OUTLAW)
-#else
-# define machine_is_outlaw()	(0)
-#endif
-
-#ifdef CONFIG_MACH_RIOT_BEI2
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_RIOT_BEI2
-# endif
-# define machine_is_riot_bei2()	(machine_arch_type == MACH_TYPE_RIOT_BEI2)
-#else
-# define machine_is_riot_bei2()	(0)
-#endif
-
-#ifdef CONFIG_MACH_RIOT_VOX
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_RIOT_VOX
-# endif
-# define machine_is_riot_vox()	(machine_arch_type == MACH_TYPE_RIOT_VOX)
-#else
-# define machine_is_riot_vox()	(0)
-#endif
-
-#ifdef CONFIG_MACH_RIOT_X37
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_RIOT_X37
-# endif
-# define machine_is_riot_x37()	(machine_arch_type == MACH_TYPE_RIOT_X37)
-#else
-# define machine_is_riot_x37()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MEGA25MX
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MEGA25MX
-# endif
-# define machine_is_mega25mx()	(machine_arch_type == MACH_TYPE_MEGA25MX)
-#else
-# define machine_is_mega25mx()	(0)
-#endif
-
-#ifdef CONFIG_MACH_BENZINA2
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_BENZINA2
-# endif
-# define machine_is_benzina2()	(machine_arch_type == MACH_TYPE_BENZINA2)
-#else
-# define machine_is_benzina2()	(0)
-#endif
-
-#ifdef CONFIG_MACH_IGNITE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_IGNITE
-# endif
-# define machine_is_ignite()	(machine_arch_type == MACH_TYPE_IGNITE)
-#else
-# define machine_is_ignite()	(0)
-#endif
-
-#ifdef CONFIG_MACH_FOGGIA
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_FOGGIA
-# endif
-# define machine_is_foggia()	(machine_arch_type == MACH_TYPE_FOGGIA)
-#else
-# define machine_is_foggia()	(0)
-#endif
-
-#ifdef CONFIG_MACH_AREZZO
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_AREZZO
-# endif
-# define machine_is_arezzo()	(machine_arch_type == MACH_TYPE_AREZZO)
-#else
-# define machine_is_arezzo()	(0)
-#endif
-
-#ifdef CONFIG_MACH_LEICA_SKYWALKER
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_LEICA_SKYWALKER
-# endif
-# define machine_is_leica_skywalker()	(machine_arch_type == MACH_TYPE_LEICA_SKYWALKER)
-#else
-# define machine_is_leica_skywalker()	(0)
-#endif
-
-#ifdef CONFIG_MACH_JACINTO2_JAMR
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_JACINTO2_JAMR
-# endif
-# define machine_is_jacinto2_jamr()	(machine_arch_type == MACH_TYPE_JACINTO2_JAMR)
-#else
-# define machine_is_jacinto2_jamr()	(0)
-#endif
-
-#ifdef CONFIG_MACH_GTS_NOVA
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_GTS_NOVA
-# endif
-# define machine_is_gts_nova()	(machine_arch_type == MACH_TYPE_GTS_NOVA)
-#else
-# define machine_is_gts_nova()	(0)
-#endif
-
-#ifdef CONFIG_MACH_P3600
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_P3600
-# endif
-# define machine_is_p3600()	(machine_arch_type == MACH_TYPE_P3600)
-#else
-# define machine_is_p3600()	(0)
-#endif
-
-#ifdef CONFIG_MACH_DLT2
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_DLT2
-# endif
-# define machine_is_dlt2()	(machine_arch_type == MACH_TYPE_DLT2)
-#else
-# define machine_is_dlt2()	(0)
-#endif
-
-#ifdef CONFIG_MACH_DF3120
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_DF3120
-# endif
-# define machine_is_df3120()	(machine_arch_type == MACH_TYPE_DF3120)
-#else
-# define machine_is_df3120()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ECUCORE_9G20
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ECUCORE_9G20
-# endif
-# define machine_is_ecucore_9g20()	(machine_arch_type == MACH_TYPE_ECUCORE_9G20)
-#else
-# define machine_is_ecucore_9g20()	(0)
-#endif
-
-#ifdef CONFIG_MACH_NAUTEL_LPC3240
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_NAUTEL_LPC3240
-# endif
-# define machine_is_nautel_lpc3240()	(machine_arch_type == MACH_TYPE_NAUTEL_LPC3240)
-#else
-# define machine_is_nautel_lpc3240()	(0)
-#endif
-
-#ifdef CONFIG_MACH_GLACIER
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_GLACIER
-# endif
-# define machine_is_glacier()	(machine_arch_type == MACH_TYPE_GLACIER)
-#else
-# define machine_is_glacier()	(0)
-#endif
-
-#ifdef CONFIG_MACH_PHRAZER_BULLDOG
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PHRAZER_BULLDOG
-# endif
-# define machine_is_phrazer_bulldog()	(machine_arch_type == MACH_TYPE_PHRAZER_BULLDOG)
-#else
-# define machine_is_phrazer_bulldog()	(0)
-#endif
-
-#ifdef CONFIG_MACH_OMAP3_BULLDOG
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_OMAP3_BULLDOG
-# endif
-# define machine_is_omap3_bulldog()	(machine_arch_type == MACH_TYPE_OMAP3_BULLDOG)
-#else
-# define machine_is_omap3_bulldog()	(0)
-#endif
-
-#ifdef CONFIG_MACH_PCA101
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PCA101
-# endif
-# define machine_is_pca101()	(machine_arch_type == MACH_TYPE_PCA101)
-#else
-# define machine_is_pca101()	(0)
-#endif
-
-#ifdef CONFIG_MACH_BUZZC
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_BUZZC
-# endif
-# define machine_is_buzzc()	(machine_arch_type == MACH_TYPE_BUZZC)
-#else
-# define machine_is_buzzc()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SASIE2
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SASIE2
-# endif
-# define machine_is_sasie2()	(machine_arch_type == MACH_TYPE_SASIE2)
-#else
-# define machine_is_sasie2()	(0)
-#endif
-
-#ifdef CONFIG_MACH_DAVINCI_CIO
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_DAVINCI_CIO
-# endif
-# define machine_is_davinci_cio()	(machine_arch_type == MACH_TYPE_DAVINCI_CIO)
-#else
-# define machine_is_davinci_cio()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SMARTMETER_DL
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SMARTMETER_DL
-# endif
-# define machine_is_smartmeter_dl()	(machine_arch_type == MACH_TYPE_SMARTMETER_DL)
-#else
-# define machine_is_smartmeter_dl()	(0)
-#endif
-
-#ifdef CONFIG_MACH_WZL6410
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_WZL6410
-# endif
-# define machine_is_wzl6410()	(machine_arch_type == MACH_TYPE_WZL6410)
-#else
-# define machine_is_wzl6410()	(0)
-#endif
-
-#ifdef CONFIG_MACH_WZL6410M
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_WZL6410M
-# endif
-# define machine_is_wzl6410m()	(machine_arch_type == MACH_TYPE_WZL6410M)
-#else
-# define machine_is_wzl6410m()	(0)
-#endif
-
-#ifdef CONFIG_MACH_WZL6410F
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_WZL6410F
-# endif
-# define machine_is_wzl6410f()	(machine_arch_type == MACH_TYPE_WZL6410F)
-#else
-# define machine_is_wzl6410f()	(0)
-#endif
-
-#ifdef CONFIG_MACH_WZL6410I
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_WZL6410I
-# endif
-# define machine_is_wzl6410i()	(machine_arch_type == MACH_TYPE_WZL6410I)
-#else
-# define machine_is_wzl6410i()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SPACECOM1
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SPACECOM1
-# endif
-# define machine_is_spacecom1()	(machine_arch_type == MACH_TYPE_SPACECOM1)
-#else
-# define machine_is_spacecom1()	(0)
-#endif
-
-#ifdef CONFIG_MACH_PINGU920
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PINGU920
-# endif
-# define machine_is_pingu920()	(machine_arch_type == MACH_TYPE_PINGU920)
-#else
-# define machine_is_pingu920()	(0)
-#endif
-
-#ifdef CONFIG_MACH_BRAVOC
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_BRAVOC
-# endif
-# define machine_is_bravoc()	(machine_arch_type == MACH_TYPE_BRAVOC)
-#else
-# define machine_is_bravoc()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CYBO2440
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CYBO2440
-# endif
-# define machine_is_cybo2440()	(machine_arch_type == MACH_TYPE_CYBO2440)
-#else
-# define machine_is_cybo2440()	(0)
-#endif
-
-#ifdef CONFIG_MACH_VDSSW
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_VDSSW
-# endif
-# define machine_is_vdssw()	(machine_arch_type == MACH_TYPE_VDSSW)
-#else
-# define machine_is_vdssw()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ROMULUS
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ROMULUS
-# endif
-# define machine_is_romulus()	(machine_arch_type == MACH_TYPE_ROMULUS)
-#else
-# define machine_is_romulus()	(0)
-#endif
-
-#ifdef CONFIG_MACH_OMAP_MAGIC
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_OMAP_MAGIC
-# endif
-# define machine_is_omap_magic()	(machine_arch_type == MACH_TYPE_OMAP_MAGIC)
-#else
-# define machine_is_omap_magic()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ELTD100
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ELTD100
-# endif
-# define machine_is_eltd100()	(machine_arch_type == MACH_TYPE_ELTD100)
-#else
-# define machine_is_eltd100()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CAPC7117
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CAPC7117
-# endif
-# define machine_is_capc7117()	(machine_arch_type == MACH_TYPE_CAPC7117)
-#else
-# define machine_is_capc7117()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SWAN
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SWAN
-# endif
-# define machine_is_swan()	(machine_arch_type == MACH_TYPE_SWAN)
-#else
-# define machine_is_swan()	(0)
-#endif
-
-#ifdef CONFIG_MACH_VEU
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_VEU
-# endif
-# define machine_is_veu()	(machine_arch_type == MACH_TYPE_VEU)
-#else
-# define machine_is_veu()	(0)
-#endif
-
-#ifdef CONFIG_MACH_RM2
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_RM2
-# endif
-# define machine_is_rm2()	(machine_arch_type == MACH_TYPE_RM2)
-#else
-# define machine_is_rm2()	(0)
-#endif
-
-#ifdef CONFIG_MACH_TT2100
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TT2100
-# endif
-# define machine_is_tt2100()	(machine_arch_type == MACH_TYPE_TT2100)
-#else
-# define machine_is_tt2100()	(0)
-#endif
-
-#ifdef CONFIG_MACH_VENICE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_VENICE
-# endif
-# define machine_is_venice()	(machine_arch_type == MACH_TYPE_VENICE)
-#else
-# define machine_is_venice()	(0)
-#endif
-
-#ifdef CONFIG_MACH_PC7323
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PC7323
-# endif
-# define machine_is_pc7323()	(machine_arch_type == MACH_TYPE_PC7323)
-#else
-# define machine_is_pc7323()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MASP
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MASP
-# endif
-# define machine_is_masp()	(machine_arch_type == MACH_TYPE_MASP)
-#else
-# define machine_is_masp()	(0)
-#endif
-
-#ifdef CONFIG_MACH_FUJITSU_TVSTBSOC
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_FUJITSU_TVSTBSOC
-# endif
-# define machine_is_fujitsu_tvstbsoc0()	(machine_arch_type == MACH_TYPE_FUJITSU_TVSTBSOC)
-#else
-# define machine_is_fujitsu_tvstbsoc0()	(0)
-#endif
-
-#ifdef CONFIG_MACH_FUJITSU_TVSTBSOC1
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_FUJITSU_TVSTBSOC1
-# endif
-# define machine_is_fujitsu_tvstbsoc1()	(machine_arch_type == MACH_TYPE_FUJITSU_TVSTBSOC1)
-#else
-# define machine_is_fujitsu_tvstbsoc1()	(0)
-#endif
-
-#ifdef CONFIG_MACH_LEXIKON
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_LEXIKON
-# endif
-# define machine_is_lexikon()	(machine_arch_type == MACH_TYPE_LEXIKON)
-#else
-# define machine_is_lexikon()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MINI2440V2
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MINI2440V2
-# endif
-# define machine_is_mini2440v2()	(machine_arch_type == MACH_TYPE_MINI2440V2)
-#else
-# define machine_is_mini2440v2()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ICONTROL
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ICONTROL
-# endif
-# define machine_is_icontrol()	(machine_arch_type == MACH_TYPE_ICONTROL)
-#else
-# define machine_is_icontrol()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SHEEVAD
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SHEEVAD
-# endif
-# define machine_is_gplugd()	(machine_arch_type == MACH_TYPE_SHEEVAD)
-#else
-# define machine_is_gplugd()	(0)
-#endif
-
-#ifdef CONFIG_MACH_QSD8X50A_ST1_1
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_QSD8X50A_ST1_1
-# endif
-# define machine_is_qsd8x50a_st1_1()	(machine_arch_type == MACH_TYPE_QSD8X50A_ST1_1)
-#else
-# define machine_is_qsd8x50a_st1_1()	(0)
-#endif
-
-#ifdef CONFIG_MACH_QSD8X50A_ST1_5
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_QSD8X50A_ST1_5
-# endif
-# define machine_is_qsd8x50a_st1_5()	(machine_arch_type == MACH_TYPE_QSD8X50A_ST1_5)
-#else
-# define machine_is_qsd8x50a_st1_5()	(0)
-#endif
-
-#ifdef CONFIG_MACH_BEE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_BEE
-# endif
-# define machine_is_bee()	(machine_arch_type == MACH_TYPE_BEE)
-#else
-# define machine_is_bee()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MX23EVK
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MX23EVK
-# endif
-# define machine_is_mx23evk()	(machine_arch_type == MACH_TYPE_MX23EVK)
-#else
-# define machine_is_mx23evk()	(0)
-#endif
-
-#ifdef CONFIG_MACH_AP4EVB
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_AP4EVB
-# endif
-# define machine_is_ap4evb()	(machine_arch_type == MACH_TYPE_AP4EVB)
-#else
-# define machine_is_ap4evb()	(0)
-#endif
-
-#ifdef CONFIG_MACH_STOCKHOLM
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_STOCKHOLM
-# endif
-# define machine_is_stockholm()	(machine_arch_type == MACH_TYPE_STOCKHOLM)
-#else
-# define machine_is_stockholm()	(0)
-#endif
-
-#ifdef CONFIG_MACH_LPC_H3131
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_LPC_H3131
-# endif
-# define machine_is_lpc_h3131()	(machine_arch_type == MACH_TYPE_LPC_H3131)
-#else
-# define machine_is_lpc_h3131()	(0)
-#endif
-
-#ifdef CONFIG_MACH_STINGRAY
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_STINGRAY
-# endif
-# define machine_is_stingray()	(machine_arch_type == MACH_TYPE_STINGRAY)
-#else
-# define machine_is_stingray()	(0)
-#endif
-
-#ifdef CONFIG_MACH_KRAKEN
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_KRAKEN
-# endif
-# define machine_is_kraken()	(machine_arch_type == MACH_TYPE_KRAKEN)
-#else
-# define machine_is_kraken()	(0)
-#endif
-
-#ifdef CONFIG_MACH_GW2388
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_GW2388
-# endif
-# define machine_is_gw2388()	(machine_arch_type == MACH_TYPE_GW2388)
-#else
-# define machine_is_gw2388()	(0)
-#endif
-
-#ifdef CONFIG_MACH_JADECPU
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_JADECPU
-# endif
-# define machine_is_jadecpu()	(machine_arch_type == MACH_TYPE_JADECPU)
-#else
-# define machine_is_jadecpu()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CARLISLE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CARLISLE
-# endif
-# define machine_is_carlisle()	(machine_arch_type == MACH_TYPE_CARLISLE)
-#else
-# define machine_is_carlisle()	(0)
-#endif
-
-#ifdef CONFIG_MACH_LUX_SF9
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_LUX_SF9
-# endif
-# define machine_is_lux_sf9()	(machine_arch_type == MACH_TYPE_LUX_SF9)
-#else
-# define machine_is_lux_sf9()	(0)
-#endif
-
-#ifdef CONFIG_MACH_NEMID_TB
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_NEMID_TB
-# endif
-# define machine_is_nemid_tb()	(machine_arch_type == MACH_TYPE_NEMID_TB)
-#else
-# define machine_is_nemid_tb()	(0)
-#endif
-
-#ifdef CONFIG_MACH_TERRIER
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TERRIER
-# endif
-# define machine_is_terrier()	(machine_arch_type == MACH_TYPE_TERRIER)
-#else
-# define machine_is_terrier()	(0)
-#endif
-
-#ifdef CONFIG_MACH_TURBOT
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TURBOT
-# endif
-# define machine_is_turbot()	(machine_arch_type == MACH_TYPE_TURBOT)
-#else
-# define machine_is_turbot()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SANDDAB
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SANDDAB
-# endif
-# define machine_is_sanddab()	(machine_arch_type == MACH_TYPE_SANDDAB)
-#else
-# define machine_is_sanddab()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MX35_CICADA
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MX35_CICADA
-# endif
-# define machine_is_mx35_cicada()	(machine_arch_type == MACH_TYPE_MX35_CICADA)
-#else
-# define machine_is_mx35_cicada()	(0)
-#endif
-
-#ifdef CONFIG_MACH_GHI2703D
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_GHI2703D
-# endif
-# define machine_is_ghi2703d()	(machine_arch_type == MACH_TYPE_GHI2703D)
-#else
-# define machine_is_ghi2703d()	(0)
-#endif
-
-#ifdef CONFIG_MACH_LUX_SFX9
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_LUX_SFX9
-# endif
-# define machine_is_lux_sfx9()	(machine_arch_type == MACH_TYPE_LUX_SFX9)
-#else
-# define machine_is_lux_sfx9()	(0)
-#endif
-
-#ifdef CONFIG_MACH_LUX_SF9G
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_LUX_SF9G
-# endif
-# define machine_is_lux_sf9g()	(machine_arch_type == MACH_TYPE_LUX_SF9G)
-#else
-# define machine_is_lux_sf9g()	(0)
-#endif
-
-#ifdef CONFIG_MACH_LUX_EDK9
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_LUX_EDK9
-# endif
-# define machine_is_lux_edk9()	(machine_arch_type == MACH_TYPE_LUX_EDK9)
-#else
-# define machine_is_lux_edk9()	(0)
-#endif
-
-#ifdef CONFIG_MACH_HW90240
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_HW90240
-# endif
-# define machine_is_hw90240()	(machine_arch_type == MACH_TYPE_HW90240)
-#else
-# define machine_is_hw90240()	(0)
-#endif
-
-#ifdef CONFIG_MACH_DM365_LEOPARD
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_DM365_LEOPARD
-# endif
-# define machine_is_dm365_leopard()	(machine_arch_type == MACH_TYPE_DM365_LEOPARD)
-#else
-# define machine_is_dm365_leopard()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MITYOMAPL138
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MITYOMAPL138
-# endif
-# define machine_is_mityomapl138()	(machine_arch_type == MACH_TYPE_MITYOMAPL138)
-#else
-# define machine_is_mityomapl138()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SCAT110
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SCAT110
-# endif
-# define machine_is_scat110()	(machine_arch_type == MACH_TYPE_SCAT110)
-#else
-# define machine_is_scat110()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ACER_A1
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ACER_A1
-# endif
-# define machine_is_acer_a1()	(machine_arch_type == MACH_TYPE_ACER_A1)
-#else
-# define machine_is_acer_a1()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CMCONTROL
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CMCONTROL
-# endif
-# define machine_is_cmcontrol()	(machine_arch_type == MACH_TYPE_CMCONTROL)
-#else
-# define machine_is_cmcontrol()	(0)
-#endif
-
-#ifdef CONFIG_MACH_PELCO_LAMAR
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PELCO_LAMAR
-# endif
-# define machine_is_pelco_lamar()	(machine_arch_type == MACH_TYPE_PELCO_LAMAR)
-#else
-# define machine_is_pelco_lamar()	(0)
-#endif
-
-#ifdef CONFIG_MACH_RFP43
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_RFP43
-# endif
-# define machine_is_rfp43()	(machine_arch_type == MACH_TYPE_RFP43)
-#else
-# define machine_is_rfp43()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SK86R0301
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SK86R0301
-# endif
-# define machine_is_sk86r0301()	(machine_arch_type == MACH_TYPE_SK86R0301)
-#else
-# define machine_is_sk86r0301()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CTPXA
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CTPXA
-# endif
-# define machine_is_ctpxa()	(machine_arch_type == MACH_TYPE_CTPXA)
-#else
-# define machine_is_ctpxa()	(0)
-#endif
-
-#ifdef CONFIG_MACH_EPB_ARM9_A
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_EPB_ARM9_A
-# endif
-# define machine_is_epb_arm9_a()	(machine_arch_type == MACH_TYPE_EPB_ARM9_A)
-#else
-# define machine_is_epb_arm9_a()	(0)
-#endif
-
-#ifdef CONFIG_MACH_GURUPLUG
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_GURUPLUG
-# endif
-# define machine_is_guruplug()	(machine_arch_type == MACH_TYPE_GURUPLUG)
-#else
-# define machine_is_guruplug()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SPEAR310
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SPEAR310
-# endif
-# define machine_is_spear310()	(machine_arch_type == MACH_TYPE_SPEAR310)
-#else
-# define machine_is_spear310()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SPEAR320
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SPEAR320
-# endif
-# define machine_is_spear320()	(machine_arch_type == MACH_TYPE_SPEAR320)
-#else
-# define machine_is_spear320()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ROBOTX
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ROBOTX
-# endif
-# define machine_is_robotx()	(machine_arch_type == MACH_TYPE_ROBOTX)
-#else
-# define machine_is_robotx()	(0)
-#endif
-
-#ifdef CONFIG_MACH_LSXHL
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_LSXHL
-# endif
-# define machine_is_lsxhl()	(machine_arch_type == MACH_TYPE_LSXHL)
-#else
-# define machine_is_lsxhl()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SMARTLITE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SMARTLITE
-# endif
-# define machine_is_smartlite()	(machine_arch_type == MACH_TYPE_SMARTLITE)
-#else
-# define machine_is_smartlite()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CWS2
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CWS2
-# endif
-# define machine_is_cws2()	(machine_arch_type == MACH_TYPE_CWS2)
-#else
-# define machine_is_cws2()	(0)
-#endif
-
-#ifdef CONFIG_MACH_M619
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_M619
-# endif
-# define machine_is_m619()	(machine_arch_type == MACH_TYPE_M619)
-#else
-# define machine_is_m619()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SMARTVIEW
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SMARTVIEW
-# endif
-# define machine_is_smartview()	(machine_arch_type == MACH_TYPE_SMARTVIEW)
-#else
-# define machine_is_smartview()	(0)
-#endif
-
-#ifdef CONFIG_MACH_LSA_SALSA
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_LSA_SALSA
-# endif
-# define machine_is_lsa_salsa()	(machine_arch_type == MACH_TYPE_LSA_SALSA)
-#else
-# define machine_is_lsa_salsa()	(0)
-#endif
-
-#ifdef CONFIG_MACH_KIZBOX
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_KIZBOX
-# endif
-# define machine_is_kizbox()	(machine_arch_type == MACH_TYPE_KIZBOX)
-#else
-# define machine_is_kizbox()	(0)
-#endif
-
-#ifdef CONFIG_MACH_HTCCHARMER
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_HTCCHARMER
-# endif
-# define machine_is_htccharmer()	(machine_arch_type == MACH_TYPE_HTCCHARMER)
-#else
-# define machine_is_htccharmer()	(0)
-#endif
-
-#ifdef CONFIG_MACH_GUF_NESO_LT
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_GUF_NESO_LT
-# endif
-# define machine_is_guf_neso_lt()	(machine_arch_type == MACH_TYPE_GUF_NESO_LT)
-#else
-# define machine_is_guf_neso_lt()	(0)
-#endif
-
-#ifdef CONFIG_MACH_PM9G45
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PM9G45
-# endif
-# define machine_is_pm9g45()	(machine_arch_type == MACH_TYPE_PM9G45)
-#else
-# define machine_is_pm9g45()	(0)
-#endif
-
-#ifdef CONFIG_MACH_HTCPANTHER
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_HTCPANTHER
-# endif
-# define machine_is_htcpanther()	(machine_arch_type == MACH_TYPE_HTCPANTHER)
-#else
-# define machine_is_htcpanther()	(0)
-#endif
-
-#ifdef CONFIG_MACH_HTCPANTHER_CDMA
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_HTCPANTHER_CDMA
-# endif
-# define machine_is_htcpanther_cdma()	(machine_arch_type == MACH_TYPE_HTCPANTHER_CDMA)
-#else
-# define machine_is_htcpanther_cdma()	(0)
-#endif
-
-#ifdef CONFIG_MACH_REB01
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_REB01
-# endif
-# define machine_is_reb01()	(machine_arch_type == MACH_TYPE_REB01)
-#else
-# define machine_is_reb01()	(0)
-#endif
-
-#ifdef CONFIG_MACH_AQUILA
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_AQUILA
-# endif
-# define machine_is_aquila()	(machine_arch_type == MACH_TYPE_AQUILA)
-#else
-# define machine_is_aquila()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SPARK_SLS_HW2
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SPARK_SLS_HW2
-# endif
-# define machine_is_spark_sls_hw2()	(machine_arch_type == MACH_TYPE_SPARK_SLS_HW2)
-#else
-# define machine_is_spark_sls_hw2()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ESATA_SHEEVAPLUG
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ESATA_SHEEVAPLUG
-# endif
-# define machine_is_sheeva_esata()	(machine_arch_type == MACH_TYPE_ESATA_SHEEVAPLUG)
-#else
-# define machine_is_sheeva_esata()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MSM7X30_SURF
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MSM7X30_SURF
-# endif
-# define machine_is_msm7x30_surf()	(machine_arch_type == MACH_TYPE_MSM7X30_SURF)
-#else
-# define machine_is_msm7x30_surf()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MICRO2440
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MICRO2440
-# endif
-# define machine_is_micro2440()	(machine_arch_type == MACH_TYPE_MICRO2440)
-#else
-# define machine_is_micro2440()	(0)
-#endif
-
-#ifdef CONFIG_MACH_AM2440
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_AM2440
-# endif
-# define machine_is_am2440()	(machine_arch_type == MACH_TYPE_AM2440)
-#else
-# define machine_is_am2440()	(0)
-#endif
-
-#ifdef CONFIG_MACH_TQ2440
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TQ2440
-# endif
-# define machine_is_tq2440()	(machine_arch_type == MACH_TYPE_TQ2440)
-#else
-# define machine_is_tq2440()	(0)
-#endif
-
-#ifdef CONFIG_MACH_LPC2478OEM
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_LPC2478OEM
-# endif
-# define machine_is_lpc2478oem()	(machine_arch_type == MACH_TYPE_LPC2478OEM)
-#else
-# define machine_is_lpc2478oem()	(0)
-#endif
-
-#ifdef CONFIG_MACH_AK880X
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_AK880X
-# endif
-# define machine_is_ak880x()	(machine_arch_type == MACH_TYPE_AK880X)
-#else
-# define machine_is_ak880x()	(0)
-#endif
-
-#ifdef CONFIG_MACH_COBRA3530
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_COBRA3530
-# endif
-# define machine_is_cobra3530()	(machine_arch_type == MACH_TYPE_COBRA3530)
-#else
-# define machine_is_cobra3530()	(0)
-#endif
-
-#ifdef CONFIG_MACH_PMPPB
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PMPPB
-# endif
-# define machine_is_pmppb()	(machine_arch_type == MACH_TYPE_PMPPB)
-#else
-# define machine_is_pmppb()	(0)
-#endif
-
-#ifdef CONFIG_MACH_U6715
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_U6715
-# endif
-# define machine_is_u6715()	(machine_arch_type == MACH_TYPE_U6715)
-#else
-# define machine_is_u6715()	(0)
-#endif
-
-#ifdef CONFIG_MACH_AXAR1500_SENDER
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_AXAR1500_SENDER
-# endif
-# define machine_is_axar1500_sender()	(machine_arch_type == MACH_TYPE_AXAR1500_SENDER)
-#else
-# define machine_is_axar1500_sender()	(0)
-#endif
-
-#ifdef CONFIG_MACH_G30_DVB
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_G30_DVB
-# endif
-# define machine_is_g30_dvb()	(machine_arch_type == MACH_TYPE_G30_DVB)
-#else
-# define machine_is_g30_dvb()	(0)
-#endif
-
-#ifdef CONFIG_MACH_VC088X
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_VC088X
-# endif
-# define machine_is_vc088x()	(machine_arch_type == MACH_TYPE_VC088X)
-#else
-# define machine_is_vc088x()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MIOA702
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MIOA702
-# endif
-# define machine_is_mioa702()	(machine_arch_type == MACH_TYPE_MIOA702)
-#else
-# define machine_is_mioa702()	(0)
-#endif
-
-#ifdef CONFIG_MACH_HPMIN
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_HPMIN
-# endif
-# define machine_is_hpmin()	(machine_arch_type == MACH_TYPE_HPMIN)
-#else
-# define machine_is_hpmin()	(0)
-#endif
-
-#ifdef CONFIG_MACH_AK880XAK
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_AK880XAK
-# endif
-# define machine_is_ak880xak()	(machine_arch_type == MACH_TYPE_AK880XAK)
-#else
-# define machine_is_ak880xak()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ARM926TOMAP850
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ARM926TOMAP850
-# endif
-# define machine_is_arm926tomap850()	(machine_arch_type == MACH_TYPE_ARM926TOMAP850)
-#else
-# define machine_is_arm926tomap850()	(0)
-#endif
-
-#ifdef CONFIG_MACH_LKEVM
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_LKEVM
-# endif
-# define machine_is_lkevm()	(machine_arch_type == MACH_TYPE_LKEVM)
-#else
-# define machine_is_lkevm()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MW6410
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MW6410
-# endif
-# define machine_is_mw6410()	(machine_arch_type == MACH_TYPE_MW6410)
-#else
-# define machine_is_mw6410()	(0)
-#endif
-
-#ifdef CONFIG_MACH_TERASTATION_WXL
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TERASTATION_WXL
-# endif
-# define machine_is_terastation_wxl()	(machine_arch_type == MACH_TYPE_TERASTATION_WXL)
-#else
-# define machine_is_terastation_wxl()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CPU8000E
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CPU8000E
-# endif
-# define machine_is_cpu8000e()	(machine_arch_type == MACH_TYPE_CPU8000E)
-#else
-# define machine_is_cpu8000e()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CATANIA
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CATANIA
-# endif
-# define machine_is_catania()	(machine_arch_type == MACH_TYPE_CATANIA)
-#else
-# define machine_is_catania()	(0)
-#endif
-
-#ifdef CONFIG_MACH_TOKYO
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TOKYO
-# endif
-# define machine_is_tokyo()	(machine_arch_type == MACH_TYPE_TOKYO)
-#else
-# define machine_is_tokyo()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MSM7201A_SURF
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MSM7201A_SURF
-# endif
-# define machine_is_msm7201a_surf()	(machine_arch_type == MACH_TYPE_MSM7201A_SURF)
-#else
-# define machine_is_msm7201a_surf()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MSM7201A_FFA
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MSM7201A_FFA
-# endif
-# define machine_is_msm7201a_ffa()	(machine_arch_type == MACH_TYPE_MSM7201A_FFA)
-#else
-# define machine_is_msm7201a_ffa()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MSM7X25_SURF
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MSM7X25_SURF
-# endif
-# define machine_is_msm7x25_surf()	(machine_arch_type == MACH_TYPE_MSM7X25_SURF)
-#else
-# define machine_is_msm7x25_surf()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MSM7X25_FFA
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MSM7X25_FFA
-# endif
-# define machine_is_msm7x25_ffa()	(machine_arch_type == MACH_TYPE_MSM7X25_FFA)
-#else
-# define machine_is_msm7x25_ffa()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MSM7X27_SURF
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MSM7X27_SURF
-# endif
-# define machine_is_msm7x27_surf()	(machine_arch_type == MACH_TYPE_MSM7X27_SURF)
-#else
-# define machine_is_msm7x27_surf()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MSM7X27_FFA
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MSM7X27_FFA
-# endif
-# define machine_is_msm7x27_ffa()	(machine_arch_type == MACH_TYPE_MSM7X27_FFA)
-#else
-# define machine_is_msm7x27_ffa()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MSM7X30_FFA
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MSM7X30_FFA
-# endif
-# define machine_is_msm7x30_ffa()	(machine_arch_type == MACH_TYPE_MSM7X30_FFA)
-#else
-# define machine_is_msm7x30_ffa()	(0)
-#endif
-
-#ifdef CONFIG_MACH_QSD8X50_SURF
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_QSD8X50_SURF
-# endif
-# define machine_is_qsd8x50_surf()	(machine_arch_type == MACH_TYPE_QSD8X50_SURF)
-#else
-# define machine_is_qsd8x50_surf()	(0)
-#endif
-
-#ifdef CONFIG_MACH_QSD8X50_COMET
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_QSD8X50_COMET
-# endif
-# define machine_is_qsd8x50_comet()	(machine_arch_type == MACH_TYPE_QSD8X50_COMET)
-#else
-# define machine_is_qsd8x50_comet()	(0)
-#endif
-
-#ifdef CONFIG_MACH_QSD8X50_FFA
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_QSD8X50_FFA
-# endif
-# define machine_is_qsd8x50_ffa()	(machine_arch_type == MACH_TYPE_QSD8X50_FFA)
-#else
-# define machine_is_qsd8x50_ffa()	(0)
-#endif
-
-#ifdef CONFIG_MACH_QSD8X50A_SURF
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_QSD8X50A_SURF
-# endif
-# define machine_is_qsd8x50a_surf()	(machine_arch_type == MACH_TYPE_QSD8X50A_SURF)
-#else
-# define machine_is_qsd8x50a_surf()	(0)
-#endif
-
-#ifdef CONFIG_MACH_QSD8X50A_FFA
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_QSD8X50A_FFA
-# endif
-# define machine_is_qsd8x50a_ffa()	(machine_arch_type == MACH_TYPE_QSD8X50A_FFA)
-#else
-# define machine_is_qsd8x50a_ffa()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ADX_XGCP10
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ADX_XGCP10
-# endif
-# define machine_is_adx_xgcp10()	(machine_arch_type == MACH_TYPE_ADX_XGCP10)
-#else
-# define machine_is_adx_xgcp10()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MCGWUMTS2A
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MCGWUMTS2A
-# endif
-# define machine_is_mcgwumts2a()	(machine_arch_type == MACH_TYPE_MCGWUMTS2A)
-#else
-# define machine_is_mcgwumts2a()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MOBIKT
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MOBIKT
-# endif
-# define machine_is_mobikt()	(machine_arch_type == MACH_TYPE_MOBIKT)
-#else
-# define machine_is_mobikt()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MX53_EVK
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MX53_EVK
-# endif
-# define machine_is_mx53_evk()	(machine_arch_type == MACH_TYPE_MX53_EVK)
-#else
-# define machine_is_mx53_evk()	(0)
-#endif
-
-#ifdef CONFIG_MACH_IGEP0030
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_IGEP0030
-# endif
-# define machine_is_igep0030()	(machine_arch_type == MACH_TYPE_IGEP0030)
-#else
-# define machine_is_igep0030()	(0)
-#endif
-
-#ifdef CONFIG_MACH_AXELL_H40_H50_CTRL
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_AXELL_H40_H50_CTRL
-# endif
-# define machine_is_axell_h40_h50_ctrl()	(machine_arch_type == MACH_TYPE_AXELL_H40_H50_CTRL)
-#else
-# define machine_is_axell_h40_h50_ctrl()	(0)
-#endif
-
-#ifdef CONFIG_MACH_DTCOMMOD
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_DTCOMMOD
-# endif
-# define machine_is_dtcommod()	(machine_arch_type == MACH_TYPE_DTCOMMOD)
-#else
-# define machine_is_dtcommod()	(0)
-#endif
-
-#ifdef CONFIG_MACH_GOULD
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_GOULD
-# endif
-# define machine_is_gould()	(machine_arch_type == MACH_TYPE_GOULD)
-#else
-# define machine_is_gould()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SIBERIA
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SIBERIA
-# endif
-# define machine_is_siberia()	(machine_arch_type == MACH_TYPE_SIBERIA)
-#else
-# define machine_is_siberia()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SBC3530
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SBC3530
-# endif
-# define machine_is_sbc3530()	(machine_arch_type == MACH_TYPE_SBC3530)
-#else
-# define machine_is_sbc3530()	(0)
-#endif
-
-#ifdef CONFIG_MACH_QARM
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_QARM
-# endif
-# define machine_is_qarm()	(machine_arch_type == MACH_TYPE_QARM)
-#else
-# define machine_is_qarm()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MIPS
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MIPS
-# endif
-# define machine_is_mips()	(machine_arch_type == MACH_TYPE_MIPS)
-#else
-# define machine_is_mips()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MX27GRB
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MX27GRB
-# endif
-# define machine_is_mx27grb()	(machine_arch_type == MACH_TYPE_MX27GRB)
-#else
-# define machine_is_mx27grb()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SBC8100
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SBC8100
-# endif
-# define machine_is_sbc8100()	(machine_arch_type == MACH_TYPE_SBC8100)
-#else
-# define machine_is_sbc8100()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SAARB
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SAARB
-# endif
-# define machine_is_saarb()	(machine_arch_type == MACH_TYPE_SAARB)
-#else
-# define machine_is_saarb()	(0)
-#endif
-
-#ifdef CONFIG_MACH_OMAP3MINI
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_OMAP3MINI
-# endif
-# define machine_is_omap3mini()	(machine_arch_type == MACH_TYPE_OMAP3MINI)
-#else
-# define machine_is_omap3mini()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CNMBOOK7SE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CNMBOOK7SE
-# endif
-# define machine_is_cnmbook7se()	(machine_arch_type == MACH_TYPE_CNMBOOK7SE)
-#else
-# define machine_is_cnmbook7se()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CATAN
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CATAN
-# endif
-# define machine_is_catan()	(machine_arch_type == MACH_TYPE_CATAN)
-#else
-# define machine_is_catan()	(0)
-#endif
-
-#ifdef CONFIG_MACH_HARMONY
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_HARMONY
-# endif
-# define machine_is_harmony()	(machine_arch_type == MACH_TYPE_HARMONY)
-#else
-# define machine_is_harmony()	(0)
-#endif
-
-#ifdef CONFIG_MACH_TONGA
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TONGA
-# endif
-# define machine_is_tonga()	(machine_arch_type == MACH_TYPE_TONGA)
-#else
-# define machine_is_tonga()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CYBOOK_ORIZON
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CYBOOK_ORIZON
-# endif
-# define machine_is_cybook_orizon()	(machine_arch_type == MACH_TYPE_CYBOOK_ORIZON)
-#else
-# define machine_is_cybook_orizon()	(0)
-#endif
-
-#ifdef CONFIG_MACH_HTCRHODIUMCDMA
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_HTCRHODIUMCDMA
-# endif
-# define machine_is_htcrhodiumcdma()	(machine_arch_type == MACH_TYPE_HTCRHODIUMCDMA)
-#else
-# define machine_is_htcrhodiumcdma()	(0)
-#endif
-
-#ifdef CONFIG_MACH_EPC_G45
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_EPC_G45
-# endif
-# define machine_is_epc_g45()	(machine_arch_type == MACH_TYPE_EPC_G45)
-#else
-# define machine_is_epc_g45()	(0)
-#endif
-
-#ifdef CONFIG_MACH_EPC_LPC3250
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_EPC_LPC3250
-# endif
-# define machine_is_epc_lpc3250()	(machine_arch_type == MACH_TYPE_EPC_LPC3250)
-#else
-# define machine_is_epc_lpc3250()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MXC91341EVB
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MXC91341EVB
-# endif
-# define machine_is_mxc91341evb()	(machine_arch_type == MACH_TYPE_MXC91341EVB)
-#else
-# define machine_is_mxc91341evb()	(0)
-#endif
-
-#ifdef CONFIG_MACH_RTW1000
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_RTW1000
-# endif
-# define machine_is_rtw1000()	(machine_arch_type == MACH_TYPE_RTW1000)
-#else
-# define machine_is_rtw1000()	(0)
-#endif
-
-#ifdef CONFIG_MACH_BOBCAT
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_BOBCAT
-# endif
-# define machine_is_bobcat()	(machine_arch_type == MACH_TYPE_BOBCAT)
-#else
-# define machine_is_bobcat()	(0)
-#endif
-
-#ifdef CONFIG_MACH_TRIZEPS6
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TRIZEPS6
-# endif
-# define machine_is_trizeps6()	(machine_arch_type == MACH_TYPE_TRIZEPS6)
-#else
-# define machine_is_trizeps6()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MSM7X30_FLUID
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MSM7X30_FLUID
-# endif
-# define machine_is_msm7x30_fluid()	(machine_arch_type == MACH_TYPE_MSM7X30_FLUID)
-#else
-# define machine_is_msm7x30_fluid()	(0)
-#endif
-
-#ifdef CONFIG_MACH_NEDAP9263
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_NEDAP9263
-# endif
-# define machine_is_nedap9263()	(machine_arch_type == MACH_TYPE_NEDAP9263)
-#else
-# define machine_is_nedap9263()	(0)
-#endif
-
-#ifdef CONFIG_MACH_NETGEAR_MS2110
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_NETGEAR_MS2110
-# endif
-# define machine_is_netgear_ms2110()	(machine_arch_type == MACH_TYPE_NETGEAR_MS2110)
-#else
-# define machine_is_netgear_ms2110()	(0)
-#endif
-
-#ifdef CONFIG_MACH_BMX
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_BMX
-# endif
-# define machine_is_bmx()	(machine_arch_type == MACH_TYPE_BMX)
-#else
-# define machine_is_bmx()	(0)
-#endif
-
-#ifdef CONFIG_MACH_NETSTREAM
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_NETSTREAM
-# endif
-# define machine_is_netstream()	(machine_arch_type == MACH_TYPE_NETSTREAM)
-#else
-# define machine_is_netstream()	(0)
-#endif
-
-#ifdef CONFIG_MACH_VPNEXT_RCU
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_VPNEXT_RCU
-# endif
-# define machine_is_vpnext_rcu()	(machine_arch_type == MACH_TYPE_VPNEXT_RCU)
-#else
-# define machine_is_vpnext_rcu()	(0)
-#endif
-
-#ifdef CONFIG_MACH_VPNEXT_MPU
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_VPNEXT_MPU
-# endif
-# define machine_is_vpnext_mpu()	(machine_arch_type == MACH_TYPE_VPNEXT_MPU)
-#else
-# define machine_is_vpnext_mpu()	(0)
-#endif
-
-#ifdef CONFIG_MACH_BCMRING_TABLET_V1
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_BCMRING_TABLET_V1
-# endif
-# define machine_is_bcmring_tablet_v1()	(machine_arch_type == MACH_TYPE_BCMRING_TABLET_V1)
-#else
-# define machine_is_bcmring_tablet_v1()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SGARM10
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SGARM10
-# endif
-# define machine_is_sgarm10()	(machine_arch_type == MACH_TYPE_SGARM10)
-#else
-# define machine_is_sgarm10()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CM_T3517
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CM_T3517
-# endif
-# define machine_is_cm_t3517()	(machine_arch_type == MACH_TYPE_CM_T3517)
-#else
-# define machine_is_cm_t3517()	(0)
-#endif
-
-#ifdef CONFIG_MACH_OMAP3_CPS
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_OMAP3_CPS
-# endif
-# define machine_is_omap3_cps()	(machine_arch_type == MACH_TYPE_OMAP3_CPS)
-#else
-# define machine_is_omap3_cps()	(0)
-#endif
-
-#ifdef CONFIG_MACH_AXAR1500_RECEIVER
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_AXAR1500_RECEIVER
-# endif
-# define machine_is_axar1500_receiver()	(machine_arch_type == MACH_TYPE_AXAR1500_RECEIVER)
-#else
-# define machine_is_axar1500_receiver()	(0)
-#endif
-
-#ifdef CONFIG_MACH_WBD222
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_WBD222
-# endif
-# define machine_is_wbd222()	(machine_arch_type == MACH_TYPE_WBD222)
-#else
-# define machine_is_wbd222()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MT65XX
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MT65XX
-# endif
-# define machine_is_mt65xx()	(machine_arch_type == MACH_TYPE_MT65XX)
-#else
-# define machine_is_mt65xx()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MSM8X60_SURF
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MSM8X60_SURF
-# endif
-# define machine_is_msm8x60_surf()	(machine_arch_type == MACH_TYPE_MSM8X60_SURF)
-#else
-# define machine_is_msm8x60_surf()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MSM8X60_SIM
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MSM8X60_SIM
-# endif
-# define machine_is_msm8x60_sim()	(machine_arch_type == MACH_TYPE_MSM8X60_SIM)
-#else
-# define machine_is_msm8x60_sim()	(0)
-#endif
-
-#ifdef CONFIG_MACH_VMC300
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_VMC300
-# endif
-# define machine_is_vmc300()	(machine_arch_type == MACH_TYPE_VMC300)
-#else
-# define machine_is_vmc300()	(0)
-#endif
-
-#ifdef CONFIG_MACH_TCC8000_SDK
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TCC8000_SDK
-# endif
-# define machine_is_tcc8000_sdk()	(machine_arch_type == MACH_TYPE_TCC8000_SDK)
-#else
-# define machine_is_tcc8000_sdk()	(0)
-#endif
-
-#ifdef CONFIG_MACH_NANOS
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_NANOS
-# endif
-# define machine_is_nanos()	(machine_arch_type == MACH_TYPE_NANOS)
-#else
-# define machine_is_nanos()	(0)
-#endif
-
-#ifdef CONFIG_MACH_STAMP9G10
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_STAMP9G10
-# endif
-# define machine_is_stamp9g10()	(machine_arch_type == MACH_TYPE_STAMP9G10)
-#else
-# define machine_is_stamp9g10()	(0)
-#endif
-
-#ifdef CONFIG_MACH_STAMP9G45
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_STAMP9G45
-# endif
-# define machine_is_stamp9g45()	(machine_arch_type == MACH_TYPE_STAMP9G45)
-#else
-# define machine_is_stamp9g45()	(0)
-#endif
-
-#ifdef CONFIG_MACH_H6053
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_H6053
-# endif
-# define machine_is_h6053()	(machine_arch_type == MACH_TYPE_H6053)
-#else
-# define machine_is_h6053()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SMINT01
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SMINT01
-# endif
-# define machine_is_smint01()	(machine_arch_type == MACH_TYPE_SMINT01)
-#else
-# define machine_is_smint01()	(0)
-#endif
-
-#ifdef CONFIG_MACH_PRTLVT2
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PRTLVT2
-# endif
-# define machine_is_prtlvt2()	(machine_arch_type == MACH_TYPE_PRTLVT2)
-#else
-# define machine_is_prtlvt2()	(0)
-#endif
-
-#ifdef CONFIG_MACH_AP420
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_AP420
-# endif
-# define machine_is_ap420()	(machine_arch_type == MACH_TYPE_AP420)
-#else
-# define machine_is_ap420()	(0)
-#endif
-
-#ifdef CONFIG_MACH_HTCSHIFT
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_HTCSHIFT
-# endif
-# define machine_is_htcshift()	(machine_arch_type == MACH_TYPE_HTCSHIFT)
-#else
-# define machine_is_htcshift()	(0)
-#endif
-
-#ifdef CONFIG_MACH_DAVINCI_DM365_FC
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_DAVINCI_DM365_FC
-# endif
-# define machine_is_davinci_dm365_fc()	(machine_arch_type == MACH_TYPE_DAVINCI_DM365_FC)
-#else
-# define machine_is_davinci_dm365_fc()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MSM8X55_SURF
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MSM8X55_SURF
-# endif
-# define machine_is_msm8x55_surf()	(machine_arch_type == MACH_TYPE_MSM8X55_SURF)
-#else
-# define machine_is_msm8x55_surf()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MSM8X55_FFA
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MSM8X55_FFA
-# endif
-# define machine_is_msm8x55_ffa()	(machine_arch_type == MACH_TYPE_MSM8X55_FFA)
-#else
-# define machine_is_msm8x55_ffa()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ESL_VAMANA
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ESL_VAMANA
-# endif
-# define machine_is_esl_vamana()	(machine_arch_type == MACH_TYPE_ESL_VAMANA)
-#else
-# define machine_is_esl_vamana()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SBC35
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SBC35
-# endif
-# define machine_is_sbc35()	(machine_arch_type == MACH_TYPE_SBC35)
-#else
-# define machine_is_sbc35()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MPX6446
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MPX6446
-# endif
-# define machine_is_mpx6446()	(machine_arch_type == MACH_TYPE_MPX6446)
-#else
-# define machine_is_mpx6446()	(0)
-#endif
-
-#ifdef CONFIG_MACH_OREO_CONTROLLER
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_OREO_CONTROLLER
-# endif
-# define machine_is_oreo_controller()	(machine_arch_type == MACH_TYPE_OREO_CONTROLLER)
-#else
-# define machine_is_oreo_controller()	(0)
-#endif
-
-#ifdef CONFIG_MACH_KOPIN_MODELS
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_KOPIN_MODELS
-# endif
-# define machine_is_kopin_models()	(machine_arch_type == MACH_TYPE_KOPIN_MODELS)
-#else
-# define machine_is_kopin_models()	(0)
-#endif
-
-#ifdef CONFIG_MACH_TTC_VISION2
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TTC_VISION2
-# endif
-# define machine_is_ttc_vision2()	(machine_arch_type == MACH_TYPE_TTC_VISION2)
-#else
-# define machine_is_ttc_vision2()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CNS3420VB
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CNS3420VB
-# endif
-# define machine_is_cns3420vb()	(machine_arch_type == MACH_TYPE_CNS3420VB)
-#else
-# define machine_is_cns3420vb()	(0)
-#endif
-
-#ifdef CONFIG_MACH_LPC2
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_LPC2
-# endif
-# define machine_is_lpc2()	(machine_arch_type == MACH_TYPE_LPC2)
-#else
-# define machine_is_lpc2()	(0)
-#endif
-
-#ifdef CONFIG_MACH_OLYMPUS
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_OLYMPUS
-# endif
-# define machine_is_olympus()	(machine_arch_type == MACH_TYPE_OLYMPUS)
-#else
-# define machine_is_olympus()	(0)
-#endif
-
-#ifdef CONFIG_MACH_VORTEX
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_VORTEX
-# endif
-# define machine_is_vortex()	(machine_arch_type == MACH_TYPE_VORTEX)
-#else
-# define machine_is_vortex()	(0)
-#endif
-
-#ifdef CONFIG_MACH_S5PC200
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_S5PC200
-# endif
-# define machine_is_s5pc200()	(machine_arch_type == MACH_TYPE_S5PC200)
-#else
-# define machine_is_s5pc200()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ECUCORE_9263
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ECUCORE_9263
-# endif
-# define machine_is_ecucore_9263()	(machine_arch_type == MACH_TYPE_ECUCORE_9263)
-#else
-# define machine_is_ecucore_9263()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SMDKC200
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SMDKC200
-# endif
-# define machine_is_smdkc200()	(machine_arch_type == MACH_TYPE_SMDKC200)
-#else
-# define machine_is_smdkc200()	(0)
-#endif
-
-#ifdef CONFIG_MACH_EMSISO_SX27
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_EMSISO_SX27
-# endif
-# define machine_is_emsiso_sx27()	(machine_arch_type == MACH_TYPE_EMSISO_SX27)
-#else
-# define machine_is_emsiso_sx27()	(0)
-#endif
-
-#ifdef CONFIG_MACH_APX_SOM9G45_EK
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_APX_SOM9G45_EK
-# endif
-# define machine_is_apx_som9g45_ek()	(machine_arch_type == MACH_TYPE_APX_SOM9G45_EK)
-#else
-# define machine_is_apx_som9g45_ek()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SONGSHAN
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SONGSHAN
-# endif
-# define machine_is_songshan()	(machine_arch_type == MACH_TYPE_SONGSHAN)
-#else
-# define machine_is_songshan()	(0)
-#endif
-
-#ifdef CONFIG_MACH_TIANSHAN
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TIANSHAN
-# endif
-# define machine_is_tianshan()	(machine_arch_type == MACH_TYPE_TIANSHAN)
-#else
-# define machine_is_tianshan()	(0)
-#endif
-
-#ifdef CONFIG_MACH_VPX500
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_VPX500
-# endif
-# define machine_is_vpx500()	(machine_arch_type == MACH_TYPE_VPX500)
-#else
-# define machine_is_vpx500()	(0)
-#endif
-
-#ifdef CONFIG_MACH_AM3517SAM
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_AM3517SAM
-# endif
-# define machine_is_am3517sam()	(machine_arch_type == MACH_TYPE_AM3517SAM)
-#else
-# define machine_is_am3517sam()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SKAT91_SIM508
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SKAT91_SIM508
-# endif
-# define machine_is_skat91_sim508()	(machine_arch_type == MACH_TYPE_SKAT91_SIM508)
-#else
-# define machine_is_skat91_sim508()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SKAT91_S3E
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SKAT91_S3E
-# endif
-# define machine_is_skat91_s3e()	(machine_arch_type == MACH_TYPE_SKAT91_S3E)
-#else
-# define machine_is_skat91_s3e()	(0)
-#endif
-
-#ifdef CONFIG_MACH_OMAP4_PANDA
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_OMAP4_PANDA
-# endif
-# define machine_is_omap4_panda()	(machine_arch_type == MACH_TYPE_OMAP4_PANDA)
-#else
-# define machine_is_omap4_panda()	(0)
-#endif
-
-#ifdef CONFIG_MACH_DF7220
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_DF7220
-# endif
-# define machine_is_df7220()	(machine_arch_type == MACH_TYPE_DF7220)
-#else
-# define machine_is_df7220()	(0)
-#endif
-
-#ifdef CONFIG_MACH_NEMINI
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_NEMINI
-# endif
-# define machine_is_nemini()	(machine_arch_type == MACH_TYPE_NEMINI)
-#else
-# define machine_is_nemini()	(0)
-#endif
-
-#ifdef CONFIG_MACH_T8200
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_T8200
-# endif
-# define machine_is_t8200()	(machine_arch_type == MACH_TYPE_T8200)
-#else
-# define machine_is_t8200()	(0)
-#endif
-
-#ifdef CONFIG_MACH_APF51
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_APF51
-# endif
-# define machine_is_apf51()	(machine_arch_type == MACH_TYPE_APF51)
-#else
-# define machine_is_apf51()	(0)
-#endif
-
-#ifdef CONFIG_MACH_DR_RC_UNIT
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_DR_RC_UNIT
-# endif
-# define machine_is_dr_rc_unit()	(machine_arch_type == MACH_TYPE_DR_RC_UNIT)
-#else
-# define machine_is_dr_rc_unit()	(0)
-#endif
-
-#ifdef CONFIG_MACH_BORDEAUX
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_BORDEAUX
-# endif
-# define machine_is_bordeaux()	(machine_arch_type == MACH_TYPE_BORDEAUX)
-#else
-# define machine_is_bordeaux()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CATANIA_B
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CATANIA_B
-# endif
-# define machine_is_catania_b()	(machine_arch_type == MACH_TYPE_CATANIA_B)
-#else
-# define machine_is_catania_b()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MX51_OCEAN
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MX51_OCEAN
-# endif
-# define machine_is_mx51_ocean()	(machine_arch_type == MACH_TYPE_MX51_OCEAN)
-#else
-# define machine_is_mx51_ocean()	(0)
-#endif
-
-#ifdef CONFIG_MACH_TI8168EVM
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TI8168EVM
-# endif
-# define machine_is_ti8168evm()	(machine_arch_type == MACH_TYPE_TI8168EVM)
-#else
-# define machine_is_ti8168evm()	(0)
-#endif
-
-#ifdef CONFIG_MACH_NEOCOREOMAP
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_NEOCOREOMAP
-# endif
-# define machine_is_neocoreomap()	(machine_arch_type == MACH_TYPE_NEOCOREOMAP)
-#else
-# define machine_is_neocoreomap()	(0)
-#endif
-
-#ifdef CONFIG_MACH_WITHINGS_WBP
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_WITHINGS_WBP
-# endif
-# define machine_is_withings_wbp()	(machine_arch_type == MACH_TYPE_WITHINGS_WBP)
-#else
-# define machine_is_withings_wbp()	(0)
-#endif
-
-#ifdef CONFIG_MACH_DBPS
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_DBPS
-# endif
-# define machine_is_dbps()	(machine_arch_type == MACH_TYPE_DBPS)
-#else
-# define machine_is_dbps()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SBC9261
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SBC9261
-# endif
-# define machine_is_sbc9261()	(machine_arch_type == MACH_TYPE_SBC9261)
-#else
-# define machine_is_sbc9261()	(0)
-#endif
-
-#ifdef CONFIG_MACH_PCBFP0001
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PCBFP0001
-# endif
-# define machine_is_pcbfp0001()	(machine_arch_type == MACH_TYPE_PCBFP0001)
-#else
-# define machine_is_pcbfp0001()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SPEEDY
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SPEEDY
-# endif
-# define machine_is_speedy()	(machine_arch_type == MACH_TYPE_SPEEDY)
-#else
-# define machine_is_speedy()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CHRYSAOR
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CHRYSAOR
-# endif
-# define machine_is_chrysaor()	(machine_arch_type == MACH_TYPE_CHRYSAOR)
-#else
-# define machine_is_chrysaor()	(0)
-#endif
-
-#ifdef CONFIG_MACH_TANGO
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TANGO
-# endif
-# define machine_is_tango()	(machine_arch_type == MACH_TYPE_TANGO)
-#else
-# define machine_is_tango()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SYNOLOGY_DSX11
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SYNOLOGY_DSX11
-# endif
-# define machine_is_synology_dsx11()	(machine_arch_type == MACH_TYPE_SYNOLOGY_DSX11)
-#else
-# define machine_is_synology_dsx11()	(0)
-#endif
-
-#ifdef CONFIG_MACH_HANLIN_V3EXT
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_HANLIN_V3EXT
-# endif
-# define machine_is_hanlin_v3ext()	(machine_arch_type == MACH_TYPE_HANLIN_V3EXT)
-#else
-# define machine_is_hanlin_v3ext()	(0)
-#endif
-
-#ifdef CONFIG_MACH_HANLIN_V5
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_HANLIN_V5
-# endif
-# define machine_is_hanlin_v5()	(machine_arch_type == MACH_TYPE_HANLIN_V5)
-#else
-# define machine_is_hanlin_v5()	(0)
-#endif
-
-#ifdef CONFIG_MACH_HANLIN_V3PLUS
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_HANLIN_V3PLUS
-# endif
-# define machine_is_hanlin_v3plus()	(machine_arch_type == MACH_TYPE_HANLIN_V3PLUS)
-#else
-# define machine_is_hanlin_v3plus()	(0)
-#endif
-
-#ifdef CONFIG_MACH_IRIVER_STORY
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_IRIVER_STORY
-# endif
-# define machine_is_iriver_story()	(machine_arch_type == MACH_TYPE_IRIVER_STORY)
-#else
-# define machine_is_iriver_story()	(0)
-#endif
-
-#ifdef CONFIG_MACH_IREX_ILIAD
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_IREX_ILIAD
-# endif
-# define machine_is_irex_iliad()	(machine_arch_type == MACH_TYPE_IREX_ILIAD)
-#else
-# define machine_is_irex_iliad()	(0)
-#endif
-
-#ifdef CONFIG_MACH_IREX_DR1000
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_IREX_DR1000
-# endif
-# define machine_is_irex_dr1000()	(machine_arch_type == MACH_TYPE_IREX_DR1000)
-#else
-# define machine_is_irex_dr1000()	(0)
-#endif
-
-#ifdef CONFIG_MACH_TETON_BGA
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TETON_BGA
-# endif
-# define machine_is_teton_bga()	(machine_arch_type == MACH_TYPE_TETON_BGA)
-#else
-# define machine_is_teton_bga()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SNAPPER9G45
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SNAPPER9G45
-# endif
-# define machine_is_snapper9g45()	(machine_arch_type == MACH_TYPE_SNAPPER9G45)
-#else
-# define machine_is_snapper9g45()	(0)
-#endif
-
-#ifdef CONFIG_MACH_TAM3517
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TAM3517
-# endif
-# define machine_is_tam3517()	(machine_arch_type == MACH_TYPE_TAM3517)
-#else
-# define machine_is_tam3517()	(0)
-#endif
-
-#ifdef CONFIG_MACH_PDC100
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PDC100
-# endif
-# define machine_is_pdc100()	(machine_arch_type == MACH_TYPE_PDC100)
-#else
-# define machine_is_pdc100()	(0)
-#endif
-
-#ifdef CONFIG_MACH_EUKREA_CPUIMX25
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_EUKREA_CPUIMX25
-# endif
-# define machine_is_eukrea_cpuimx25sd()	(machine_arch_type == MACH_TYPE_EUKREA_CPUIMX25)
-#else
-# define machine_is_eukrea_cpuimx25sd()	(0)
-#endif
-
-#ifdef CONFIG_MACH_EUKREA_CPUIMX35
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_EUKREA_CPUIMX35
-# endif
-# define machine_is_eukrea_cpuimx35sd()	(machine_arch_type == MACH_TYPE_EUKREA_CPUIMX35)
-#else
-# define machine_is_eukrea_cpuimx35sd()	(0)
-#endif
-
-#ifdef CONFIG_MACH_EUKREA_CPUIMX51SD
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_EUKREA_CPUIMX51SD
-# endif
-# define machine_is_eukrea_cpuimx51sd()	(machine_arch_type == MACH_TYPE_EUKREA_CPUIMX51SD)
-#else
-# define machine_is_eukrea_cpuimx51sd()	(0)
-#endif
-
-#ifdef CONFIG_MACH_EUKREA_CPUIMX51
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_EUKREA_CPUIMX51
-# endif
-# define machine_is_eukrea_cpuimx51()	(machine_arch_type == MACH_TYPE_EUKREA_CPUIMX51)
-#else
-# define machine_is_eukrea_cpuimx51()	(0)
-#endif
-
-#ifdef CONFIG_MACH_P565
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_P565
-# endif
-# define machine_is_p565()	(machine_arch_type == MACH_TYPE_P565)
-#else
-# define machine_is_p565()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ACER_A4
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ACER_A4
-# endif
-# define machine_is_acer_a4()	(machine_arch_type == MACH_TYPE_ACER_A4)
-#else
-# define machine_is_acer_a4()	(0)
-#endif
-
-#ifdef CONFIG_MACH_DAVINCI_DM368_BIP
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_DAVINCI_DM368_BIP
-# endif
-# define machine_is_davinci_dm368_bip()	(machine_arch_type == MACH_TYPE_DAVINCI_DM368_BIP)
-#else
-# define machine_is_davinci_dm368_bip()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ESHARE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ESHARE
-# endif
-# define machine_is_eshare()	(machine_arch_type == MACH_TYPE_ESHARE)
-#else
-# define machine_is_eshare()	(0)
-#endif
-
-#ifdef CONFIG_MACH_HW_OMAPL138_EUROPA
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_HW_OMAPL138_EUROPA
-# endif
-# define machine_is_hw_omapl138_europa()	(machine_arch_type == MACH_TYPE_HW_OMAPL138_EUROPA)
-#else
-# define machine_is_hw_omapl138_europa()	(0)
-#endif
-
-#ifdef CONFIG_MACH_WLBARGN
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_WLBARGN
-# endif
-# define machine_is_wlbargn()	(machine_arch_type == MACH_TYPE_WLBARGN)
-#else
-# define machine_is_wlbargn()	(0)
-#endif
-
-#ifdef CONFIG_MACH_BM170
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_BM170
-# endif
-# define machine_is_bm170()	(machine_arch_type == MACH_TYPE_BM170)
-#else
-# define machine_is_bm170()	(0)
-#endif
-
-#ifdef CONFIG_MACH_NETSPACE_MINI_V2
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_NETSPACE_MINI_V2
-# endif
-# define machine_is_netspace_mini_v2()	(machine_arch_type == MACH_TYPE_NETSPACE_MINI_V2)
-#else
-# define machine_is_netspace_mini_v2()	(0)
-#endif
-
-#ifdef CONFIG_MACH_NETSPACE_PLUG_V2
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_NETSPACE_PLUG_V2
-# endif
-# define machine_is_netspace_plug_v2()	(machine_arch_type == MACH_TYPE_NETSPACE_PLUG_V2)
-#else
-# define machine_is_netspace_plug_v2()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SIEMENS_L1
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SIEMENS_L1
-# endif
-# define machine_is_siemens_l1()	(machine_arch_type == MACH_TYPE_SIEMENS_L1)
-#else
-# define machine_is_siemens_l1()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ELV_LCU1
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ELV_LCU1
-# endif
-# define machine_is_elv_lcu1()	(machine_arch_type == MACH_TYPE_ELV_LCU1)
-#else
-# define machine_is_elv_lcu1()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MCU1
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MCU1
-# endif
-# define machine_is_mcu1()	(machine_arch_type == MACH_TYPE_MCU1)
-#else
-# define machine_is_mcu1()	(0)
-#endif
-
-#ifdef CONFIG_MACH_OMAP3_TAO3530
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_OMAP3_TAO3530
-# endif
-# define machine_is_omap3_tao3530()	(machine_arch_type == MACH_TYPE_OMAP3_TAO3530)
-#else
-# define machine_is_omap3_tao3530()	(0)
-#endif
-
-#ifdef CONFIG_MACH_OMAP3_PCUTOUCH
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_OMAP3_PCUTOUCH
-# endif
-# define machine_is_omap3_pcutouch()	(machine_arch_type == MACH_TYPE_OMAP3_PCUTOUCH)
-#else
-# define machine_is_omap3_pcutouch()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SMDKC210
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SMDKC210
-# endif
-# define machine_is_smdkc210()	(machine_arch_type == MACH_TYPE_SMDKC210)
-#else
-# define machine_is_smdkc210()	(0)
-#endif
-
-#ifdef CONFIG_MACH_OMAP3_BRAILLO
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_OMAP3_BRAILLO
-# endif
-# define machine_is_omap3_braillo()	(machine_arch_type == MACH_TYPE_OMAP3_BRAILLO)
-#else
-# define machine_is_omap3_braillo()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SPYPLUG
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SPYPLUG
-# endif
-# define machine_is_spyplug()	(machine_arch_type == MACH_TYPE_SPYPLUG)
-#else
-# define machine_is_spyplug()	(0)
-#endif
-
-#ifdef CONFIG_MACH_GINGER
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_GINGER
-# endif
-# define machine_is_ginger()	(machine_arch_type == MACH_TYPE_GINGER)
-#else
-# define machine_is_ginger()	(0)
-#endif
-
-#ifdef CONFIG_MACH_TNY_T3530
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TNY_T3530
-# endif
-# define machine_is_tny_t3530()	(machine_arch_type == MACH_TYPE_TNY_T3530)
-#else
-# define machine_is_tny_t3530()	(0)
-#endif
-
-#ifdef CONFIG_MACH_PCA102
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PCA102
-# endif
-# define machine_is_pca102()	(machine_arch_type == MACH_TYPE_PCA102)
-#else
-# define machine_is_pca102()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SPADE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SPADE
-# endif
-# define machine_is_spade()	(machine_arch_type == MACH_TYPE_SPADE)
-#else
-# define machine_is_spade()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MXC25_TOPAZ
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MXC25_TOPAZ
-# endif
-# define machine_is_mxc25_topaz()	(machine_arch_type == MACH_TYPE_MXC25_TOPAZ)
-#else
-# define machine_is_mxc25_topaz()	(0)
-#endif
-
-#ifdef CONFIG_MACH_T5325
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_T5325
-# endif
-# define machine_is_t5325()	(machine_arch_type == MACH_TYPE_T5325)
-#else
-# define machine_is_t5325()	(0)
-#endif
-
-#ifdef CONFIG_MACH_GW2361
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_GW2361
-# endif
-# define machine_is_gw2361()	(machine_arch_type == MACH_TYPE_GW2361)
-#else
-# define machine_is_gw2361()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ELOG
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ELOG
-# endif
-# define machine_is_elog()	(machine_arch_type == MACH_TYPE_ELOG)
-#else
-# define machine_is_elog()	(0)
-#endif
-
-#ifdef CONFIG_MACH_INCOME
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_INCOME
-# endif
-# define machine_is_income()	(machine_arch_type == MACH_TYPE_INCOME)
-#else
-# define machine_is_income()	(0)
-#endif
-
-#ifdef CONFIG_MACH_BCM589X
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_BCM589X
-# endif
-# define machine_is_bcm589x()	(machine_arch_type == MACH_TYPE_BCM589X)
-#else
-# define machine_is_bcm589x()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ETNA
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ETNA
-# endif
-# define machine_is_etna()	(machine_arch_type == MACH_TYPE_ETNA)
-#else
-# define machine_is_etna()	(0)
-#endif
-
-#ifdef CONFIG_MACH_HAWKS
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_HAWKS
-# endif
-# define machine_is_hawks()	(machine_arch_type == MACH_TYPE_HAWKS)
-#else
-# define machine_is_hawks()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MESON
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MESON
-# endif
-# define machine_is_meson()	(machine_arch_type == MACH_TYPE_MESON)
-#else
-# define machine_is_meson()	(0)
-#endif
-
-#ifdef CONFIG_MACH_XSBASE255
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_XSBASE255
-# endif
-# define machine_is_xsbase255()	(machine_arch_type == MACH_TYPE_XSBASE255)
-#else
-# define machine_is_xsbase255()	(0)
-#endif
-
-#ifdef CONFIG_MACH_PVM2030
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PVM2030
-# endif
-# define machine_is_pvm2030()	(machine_arch_type == MACH_TYPE_PVM2030)
-#else
-# define machine_is_pvm2030()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MIOA502
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MIOA502
-# endif
-# define machine_is_mioa502()	(machine_arch_type == MACH_TYPE_MIOA502)
-#else
-# define machine_is_mioa502()	(0)
-#endif
-
-#ifdef CONFIG_MACH_VVBOX_SDORIG2
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_VVBOX_SDORIG2
-# endif
-# define machine_is_vvbox_sdorig2()	(machine_arch_type == MACH_TYPE_VVBOX_SDORIG2)
-#else
-# define machine_is_vvbox_sdorig2()	(0)
-#endif
-
-#ifdef CONFIG_MACH_VVBOX_SDLITE2
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_VVBOX_SDLITE2
-# endif
-# define machine_is_vvbox_sdlite2()	(machine_arch_type == MACH_TYPE_VVBOX_SDLITE2)
-#else
-# define machine_is_vvbox_sdlite2()	(0)
-#endif
-
-#ifdef CONFIG_MACH_VVBOX_SDPRO4
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_VVBOX_SDPRO4
-# endif
-# define machine_is_vvbox_sdpro4()	(machine_arch_type == MACH_TYPE_VVBOX_SDPRO4)
-#else
-# define machine_is_vvbox_sdpro4()	(0)
-#endif
-
-#ifdef CONFIG_MACH_HTC_SPV_M700
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_HTC_SPV_M700
-# endif
-# define machine_is_htc_spv_m700()	(machine_arch_type == MACH_TYPE_HTC_SPV_M700)
-#else
-# define machine_is_htc_spv_m700()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MX257SX
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MX257SX
-# endif
-# define machine_is_mx257sx()	(machine_arch_type == MACH_TYPE_MX257SX)
-#else
-# define machine_is_mx257sx()	(0)
-#endif
-
-#ifdef CONFIG_MACH_GONI
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_GONI
-# endif
-# define machine_is_goni()	(machine_arch_type == MACH_TYPE_GONI)
-#else
-# define machine_is_goni()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MSM8X55_SVLTE_FFA
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MSM8X55_SVLTE_FFA
-# endif
-# define machine_is_msm8x55_svlte_ffa()	(machine_arch_type == MACH_TYPE_MSM8X55_SVLTE_FFA)
-#else
-# define machine_is_msm8x55_svlte_ffa()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MSM8X55_SVLTE_SURF
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MSM8X55_SVLTE_SURF
-# endif
-# define machine_is_msm8x55_svlte_surf()	(machine_arch_type == MACH_TYPE_MSM8X55_SVLTE_SURF)
-#else
-# define machine_is_msm8x55_svlte_surf()	(0)
-#endif
-
-#ifdef CONFIG_MACH_QUICKSTEP
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_QUICKSTEP
-# endif
-# define machine_is_quickstep()	(machine_arch_type == MACH_TYPE_QUICKSTEP)
-#else
-# define machine_is_quickstep()	(0)
-#endif
-
-#ifdef CONFIG_MACH_DMW96
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_DMW96
-# endif
-# define machine_is_dmw96()	(machine_arch_type == MACH_TYPE_DMW96)
-#else
-# define machine_is_dmw96()	(0)
-#endif
-
-#ifdef CONFIG_MACH_HAMMERHEAD
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_HAMMERHEAD
-# endif
-# define machine_is_hammerhead()	(machine_arch_type == MACH_TYPE_HAMMERHEAD)
-#else
-# define machine_is_hammerhead()	(0)
-#endif
-
-#ifdef CONFIG_MACH_TRIDENT
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TRIDENT
-# endif
-# define machine_is_trident()	(machine_arch_type == MACH_TYPE_TRIDENT)
-#else
-# define machine_is_trident()	(0)
-#endif
-
-#ifdef CONFIG_MACH_LIGHTNING
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_LIGHTNING
-# endif
-# define machine_is_lightning()	(machine_arch_type == MACH_TYPE_LIGHTNING)
-#else
-# define machine_is_lightning()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ICONNECT
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ICONNECT
-# endif
-# define machine_is_iconnect()	(machine_arch_type == MACH_TYPE_ICONNECT)
-#else
-# define machine_is_iconnect()	(0)
-#endif
-
-#ifdef CONFIG_MACH_AUTOBOT
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_AUTOBOT
-# endif
-# define machine_is_autobot()	(machine_arch_type == MACH_TYPE_AUTOBOT)
-#else
-# define machine_is_autobot()	(0)
-#endif
-
-#ifdef CONFIG_MACH_COCONUT
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_COCONUT
-# endif
-# define machine_is_coconut()	(machine_arch_type == MACH_TYPE_COCONUT)
-#else
-# define machine_is_coconut()	(0)
-#endif
-
-#ifdef CONFIG_MACH_DURIAN
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_DURIAN
-# endif
-# define machine_is_durian()	(machine_arch_type == MACH_TYPE_DURIAN)
-#else
-# define machine_is_durian()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CAYENNE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CAYENNE
-# endif
-# define machine_is_cayenne()	(machine_arch_type == MACH_TYPE_CAYENNE)
-#else
-# define machine_is_cayenne()	(0)
-#endif
-
-#ifdef CONFIG_MACH_FUJI
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_FUJI
-# endif
-# define machine_is_fuji()	(machine_arch_type == MACH_TYPE_FUJI)
-#else
-# define machine_is_fuji()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SYNOLOGY_6282
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SYNOLOGY_6282
-# endif
-# define machine_is_synology_6282()	(machine_arch_type == MACH_TYPE_SYNOLOGY_6282)
-#else
-# define machine_is_synology_6282()	(0)
-#endif
-
-#ifdef CONFIG_MACH_EM1SY
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_EM1SY
-# endif
-# define machine_is_em1sy()	(machine_arch_type == MACH_TYPE_EM1SY)
-#else
-# define machine_is_em1sy()	(0)
-#endif
-
-#ifdef CONFIG_MACH_M502
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_M502
-# endif
-# define machine_is_m502()	(machine_arch_type == MACH_TYPE_M502)
-#else
-# define machine_is_m502()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MATRIX518
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MATRIX518
-# endif
-# define machine_is_matrix518()	(machine_arch_type == MACH_TYPE_MATRIX518)
-#else
-# define machine_is_matrix518()	(0)
-#endif
-
-#ifdef CONFIG_MACH_TINY_GURNARD
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TINY_GURNARD
-# endif
-# define machine_is_tiny_gurnard()	(machine_arch_type == MACH_TYPE_TINY_GURNARD)
-#else
-# define machine_is_tiny_gurnard()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SPEAR1310
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SPEAR1310
-# endif
-# define machine_is_spear1310()	(machine_arch_type == MACH_TYPE_SPEAR1310)
-#else
-# define machine_is_spear1310()	(0)
-#endif
-
-#ifdef CONFIG_MACH_BV07
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_BV07
-# endif
-# define machine_is_bv07()	(machine_arch_type == MACH_TYPE_BV07)
-#else
-# define machine_is_bv07()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MXT_TD61
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MXT_TD61
-# endif
-# define machine_is_mxt_td61()	(machine_arch_type == MACH_TYPE_MXT_TD61)
-#else
-# define machine_is_mxt_td61()	(0)
-#endif
-
-#ifdef CONFIG_MACH_OPENRD_ULTIMATE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_OPENRD_ULTIMATE
-# endif
-# define machine_is_openrd_ultimate()	(machine_arch_type == MACH_TYPE_OPENRD_ULTIMATE)
-#else
-# define machine_is_openrd_ultimate()	(0)
-#endif
-
-#ifdef CONFIG_MACH_DEVIXP
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_DEVIXP
-# endif
-# define machine_is_devixp()	(machine_arch_type == MACH_TYPE_DEVIXP)
-#else
-# define machine_is_devixp()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MICCPT
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MICCPT
-# endif
-# define machine_is_miccpt()	(machine_arch_type == MACH_TYPE_MICCPT)
-#else
-# define machine_is_miccpt()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MIC256
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MIC256
-# endif
-# define machine_is_mic256()	(machine_arch_type == MACH_TYPE_MIC256)
-#else
-# define machine_is_mic256()	(0)
-#endif
-
-#ifdef CONFIG_MACH_AS1167
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_AS1167
-# endif
-# define machine_is_as1167()	(machine_arch_type == MACH_TYPE_AS1167)
-#else
-# define machine_is_as1167()	(0)
-#endif
-
-#ifdef CONFIG_MACH_OMAP3_IBIZA
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_OMAP3_IBIZA
-# endif
-# define machine_is_omap3_ibiza()	(machine_arch_type == MACH_TYPE_OMAP3_IBIZA)
-#else
-# define machine_is_omap3_ibiza()	(0)
-#endif
-
-#ifdef CONFIG_MACH_U5500
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_U5500
-# endif
-# define machine_is_u5500()	(machine_arch_type == MACH_TYPE_U5500)
-#else
-# define machine_is_u5500()	(0)
-#endif
-
-#ifdef CONFIG_MACH_DAVINCI_PICTO
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_DAVINCI_PICTO
-# endif
-# define machine_is_davinci_picto()	(machine_arch_type == MACH_TYPE_DAVINCI_PICTO)
-#else
-# define machine_is_davinci_picto()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MECHA
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MECHA
-# endif
-# define machine_is_mecha()	(machine_arch_type == MACH_TYPE_MECHA)
-#else
-# define machine_is_mecha()	(0)
-#endif
-
-#ifdef CONFIG_MACH_BUBBA3
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_BUBBA3
-# endif
-# define machine_is_bubba3()	(machine_arch_type == MACH_TYPE_BUBBA3)
-#else
-# define machine_is_bubba3()	(0)
-#endif
-
-#ifdef CONFIG_MACH_PUPITRE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PUPITRE
-# endif
-# define machine_is_pupitre()	(machine_arch_type == MACH_TYPE_PUPITRE)
-#else
-# define machine_is_pupitre()	(0)
-#endif
-
-#ifdef CONFIG_MACH_TEGRA_HARMONY
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TEGRA_HARMONY
-# endif
-# define machine_is_tegra_harmony()	(machine_arch_type == MACH_TYPE_TEGRA_HARMONY)
-#else
-# define machine_is_tegra_harmony()	(0)
-#endif
-
-#ifdef CONFIG_MACH_TEGRA_VOGUE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TEGRA_VOGUE
-# endif
-# define machine_is_tegra_vogue()	(machine_arch_type == MACH_TYPE_TEGRA_VOGUE)
-#else
-# define machine_is_tegra_vogue()	(0)
-#endif
-
-#ifdef CONFIG_MACH_TEGRA_E1165
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TEGRA_E1165
-# endif
-# define machine_is_tegra_e1165()	(machine_arch_type == MACH_TYPE_TEGRA_E1165)
-#else
-# define machine_is_tegra_e1165()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SIMPLENET
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SIMPLENET
-# endif
-# define machine_is_simplenet()	(machine_arch_type == MACH_TYPE_SIMPLENET)
-#else
-# define machine_is_simplenet()	(0)
-#endif
-
-#ifdef CONFIG_MACH_EC4350TBM
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_EC4350TBM
-# endif
-# define machine_is_ec4350tbm()	(machine_arch_type == MACH_TYPE_EC4350TBM)
-#else
-# define machine_is_ec4350tbm()	(0)
-#endif
-
-#ifdef CONFIG_MACH_PEC_TC
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PEC_TC
-# endif
-# define machine_is_pec_tc()	(machine_arch_type == MACH_TYPE_PEC_TC)
-#else
-# define machine_is_pec_tc()	(0)
-#endif
-
-#ifdef CONFIG_MACH_PEC_HC2
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PEC_HC2
-# endif
-# define machine_is_pec_hc2()	(machine_arch_type == MACH_TYPE_PEC_HC2)
-#else
-# define machine_is_pec_hc2()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ESL_MOBILIS_A
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ESL_MOBILIS_A
-# endif
-# define machine_is_esl_mobilis_a()	(machine_arch_type == MACH_TYPE_ESL_MOBILIS_A)
-#else
-# define machine_is_esl_mobilis_a()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ESL_MOBILIS_B
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ESL_MOBILIS_B
-# endif
-# define machine_is_esl_mobilis_b()	(machine_arch_type == MACH_TYPE_ESL_MOBILIS_B)
-#else
-# define machine_is_esl_mobilis_b()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ESL_WAVE_A
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ESL_WAVE_A
-# endif
-# define machine_is_esl_wave_a()	(machine_arch_type == MACH_TYPE_ESL_WAVE_A)
-#else
-# define machine_is_esl_wave_a()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ESL_WAVE_B
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ESL_WAVE_B
-# endif
-# define machine_is_esl_wave_b()	(machine_arch_type == MACH_TYPE_ESL_WAVE_B)
-#else
-# define machine_is_esl_wave_b()	(0)
-#endif
-
-#ifdef CONFIG_MACH_UNISENSE_MMM
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_UNISENSE_MMM
-# endif
-# define machine_is_unisense_mmm()	(machine_arch_type == MACH_TYPE_UNISENSE_MMM)
-#else
-# define machine_is_unisense_mmm()	(0)
-#endif
-
-#ifdef CONFIG_MACH_BLUESHARK
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_BLUESHARK
-# endif
-# define machine_is_blueshark()	(machine_arch_type == MACH_TYPE_BLUESHARK)
-#else
-# define machine_is_blueshark()	(0)
-#endif
-
-#ifdef CONFIG_MACH_E10
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_E10
-# endif
-# define machine_is_e10()	(machine_arch_type == MACH_TYPE_E10)
-#else
-# define machine_is_e10()	(0)
-#endif
-
-#ifdef CONFIG_MACH_APP3K_ROBIN
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_APP3K_ROBIN
-# endif
-# define machine_is_app3k_robin()	(machine_arch_type == MACH_TYPE_APP3K_ROBIN)
-#else
-# define machine_is_app3k_robin()	(0)
-#endif
-
-#ifdef CONFIG_MACH_POV15HD
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_POV15HD
-# endif
-# define machine_is_pov15hd()	(machine_arch_type == MACH_TYPE_POV15HD)
-#else
-# define machine_is_pov15hd()	(0)
-#endif
-
-#ifdef CONFIG_MACH_STELLA
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_STELLA
-# endif
-# define machine_is_stella()	(machine_arch_type == MACH_TYPE_STELLA)
-#else
-# define machine_is_stella()	(0)
-#endif
-
-#ifdef CONFIG_MACH_LINKSTATION_LSCHL
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_LINKSTATION_LSCHL
-# endif
-# define machine_is_linkstation_lschl()	(machine_arch_type == MACH_TYPE_LINKSTATION_LSCHL)
-#else
-# define machine_is_linkstation_lschl()	(0)
-#endif
-
-#ifdef CONFIG_MACH_NETWALKER
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_NETWALKER
-# endif
-# define machine_is_netwalker()	(machine_arch_type == MACH_TYPE_NETWALKER)
-#else
-# define machine_is_netwalker()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ACSX106
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ACSX106
-# endif
-# define machine_is_acsx106()	(machine_arch_type == MACH_TYPE_ACSX106)
-#else
-# define machine_is_acsx106()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ATLAS5_C1
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ATLAS5_C1
-# endif
-# define machine_is_atlas5_c1()	(machine_arch_type == MACH_TYPE_ATLAS5_C1)
-#else
-# define machine_is_atlas5_c1()	(0)
-#endif
-
-#ifdef CONFIG_MACH_NSB3AST
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_NSB3AST
-# endif
-# define machine_is_nsb3ast()	(machine_arch_type == MACH_TYPE_NSB3AST)
-#else
-# define machine_is_nsb3ast()	(0)
-#endif
-
-#ifdef CONFIG_MACH_GNET_SLC
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_GNET_SLC
-# endif
-# define machine_is_gnet_slc()	(machine_arch_type == MACH_TYPE_GNET_SLC)
-#else
-# define machine_is_gnet_slc()	(0)
-#endif
-
-#ifdef CONFIG_MACH_AF4000
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_AF4000
-# endif
-# define machine_is_af4000()	(machine_arch_type == MACH_TYPE_AF4000)
-#else
-# define machine_is_af4000()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ARK9431
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ARK9431
-# endif
-# define machine_is_ark9431()	(machine_arch_type == MACH_TYPE_ARK9431)
-#else
-# define machine_is_ark9431()	(0)
-#endif
-
-#ifdef CONFIG_MACH_FS_S5PC100
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_FS_S5PC100
-# endif
-# define machine_is_fs_s5pc100()	(machine_arch_type == MACH_TYPE_FS_S5PC100)
-#else
-# define machine_is_fs_s5pc100()	(0)
-#endif
-
-#ifdef CONFIG_MACH_OMAP3505NOVA8
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_OMAP3505NOVA8
-# endif
-# define machine_is_omap3505nova8()	(machine_arch_type == MACH_TYPE_OMAP3505NOVA8)
-#else
-# define machine_is_omap3505nova8()	(0)
-#endif
-
-#ifdef CONFIG_MACH_OMAP3621_EDP1
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_OMAP3621_EDP1
-# endif
-# define machine_is_omap3621_edp1()	(machine_arch_type == MACH_TYPE_OMAP3621_EDP1)
-#else
-# define machine_is_omap3621_edp1()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ORATISAES
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ORATISAES
-# endif
-# define machine_is_oratisaes()	(machine_arch_type == MACH_TYPE_ORATISAES)
-#else
-# define machine_is_oratisaes()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SMDKV310
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SMDKV310
-# endif
-# define machine_is_smdkv310()	(machine_arch_type == MACH_TYPE_SMDKV310)
-#else
-# define machine_is_smdkv310()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SIEMENS_L0
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SIEMENS_L0
-# endif
-# define machine_is_siemens_l0()	(machine_arch_type == MACH_TYPE_SIEMENS_L0)
-#else
-# define machine_is_siemens_l0()	(0)
-#endif
-
-#ifdef CONFIG_MACH_VENTANA
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_VENTANA
-# endif
-# define machine_is_ventana()	(machine_arch_type == MACH_TYPE_VENTANA)
-#else
-# define machine_is_ventana()	(0)
-#endif
-
-#ifdef CONFIG_MACH_WM8505_7IN_NETBOOK
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_WM8505_7IN_NETBOOK
-# endif
-# define machine_is_wm8505_7in_netbook()	(machine_arch_type == MACH_TYPE_WM8505_7IN_NETBOOK)
-#else
-# define machine_is_wm8505_7in_netbook()	(0)
-#endif
-
-#ifdef CONFIG_MACH_EC4350SDB
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_EC4350SDB
-# endif
-# define machine_is_ec4350sdb()	(machine_arch_type == MACH_TYPE_EC4350SDB)
-#else
-# define machine_is_ec4350sdb()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MIMAS
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MIMAS
-# endif
-# define machine_is_mimas()	(machine_arch_type == MACH_TYPE_MIMAS)
-#else
-# define machine_is_mimas()	(0)
-#endif
-
-#ifdef CONFIG_MACH_TITAN
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TITAN
-# endif
-# define machine_is_titan()	(machine_arch_type == MACH_TYPE_TITAN)
-#else
-# define machine_is_titan()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CRANEBOARD
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CRANEBOARD
-# endif
-# define machine_is_craneboard()	(machine_arch_type == MACH_TYPE_CRANEBOARD)
-#else
-# define machine_is_craneboard()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ES2440
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ES2440
-# endif
-# define machine_is_es2440()	(machine_arch_type == MACH_TYPE_ES2440)
-#else
-# define machine_is_es2440()	(0)
-#endif
-
-#ifdef CONFIG_MACH_NAJAY_A9263
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_NAJAY_A9263
-# endif
-# define machine_is_najay_a9263()	(machine_arch_type == MACH_TYPE_NAJAY_A9263)
-#else
-# define machine_is_najay_a9263()	(0)
-#endif
-
-#ifdef CONFIG_MACH_HTCTORNADO
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_HTCTORNADO
-# endif
-# define machine_is_htctornado()	(machine_arch_type == MACH_TYPE_HTCTORNADO)
-#else
-# define machine_is_htctornado()	(0)
-#endif
-
-#ifdef CONFIG_MACH_DIMM_MX257
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_DIMM_MX257
-# endif
-# define machine_is_dimm_mx257()	(machine_arch_type == MACH_TYPE_DIMM_MX257)
-#else
-# define machine_is_dimm_mx257()	(0)
-#endif
-
-#ifdef CONFIG_MACH_JIGEN
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_JIGEN
-# endif
-# define machine_is_jigen301()	(machine_arch_type == MACH_TYPE_JIGEN)
-#else
-# define machine_is_jigen301()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SMDK6450
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SMDK6450
-# endif
-# define machine_is_smdk6450()	(machine_arch_type == MACH_TYPE_SMDK6450)
-#else
-# define machine_is_smdk6450()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MENO_QNG
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MENO_QNG
-# endif
-# define machine_is_meno_qng()	(machine_arch_type == MACH_TYPE_MENO_QNG)
-#else
-# define machine_is_meno_qng()	(0)
-#endif
-
-#ifdef CONFIG_MACH_NS2416
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_NS2416
-# endif
-# define machine_is_ns2416()	(machine_arch_type == MACH_TYPE_NS2416)
-#else
-# define machine_is_ns2416()	(0)
-#endif
-
-#ifdef CONFIG_MACH_RPC353
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_RPC353
-# endif
-# define machine_is_rpc353()	(machine_arch_type == MACH_TYPE_RPC353)
-#else
-# define machine_is_rpc353()	(0)
-#endif
-
-#ifdef CONFIG_MACH_TQ6410
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TQ6410
-# endif
-# define machine_is_tq6410()	(machine_arch_type == MACH_TYPE_TQ6410)
-#else
-# define machine_is_tq6410()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SKY6410
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SKY6410
-# endif
-# define machine_is_sky6410()	(machine_arch_type == MACH_TYPE_SKY6410)
-#else
-# define machine_is_sky6410()	(0)
-#endif
-
-#ifdef CONFIG_MACH_DYNASTY
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_DYNASTY
-# endif
-# define machine_is_dynasty()	(machine_arch_type == MACH_TYPE_DYNASTY)
-#else
-# define machine_is_dynasty()	(0)
-#endif
-
-#ifdef CONFIG_MACH_VIVO
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_VIVO
-# endif
-# define machine_is_vivo()	(machine_arch_type == MACH_TYPE_VIVO)
-#else
-# define machine_is_vivo()	(0)
-#endif
-
-#ifdef CONFIG_MACH_BURY_BL7582
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_BURY_BL7582
-# endif
-# define machine_is_bury_bl7582()	(machine_arch_type == MACH_TYPE_BURY_BL7582)
-#else
-# define machine_is_bury_bl7582()	(0)
-#endif
-
-#ifdef CONFIG_MACH_BURY_BPS5270
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_BURY_BPS5270
-# endif
-# define machine_is_bury_bps5270()	(machine_arch_type == MACH_TYPE_BURY_BPS5270)
-#else
-# define machine_is_bury_bps5270()	(0)
-#endif
-
-#ifdef CONFIG_MACH_BASI
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_BASI
-# endif
-# define machine_is_basi()	(machine_arch_type == MACH_TYPE_BASI)
-#else
-# define machine_is_basi()	(0)
-#endif
-
-#ifdef CONFIG_MACH_TN200
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TN200
-# endif
-# define machine_is_tn200()	(machine_arch_type == MACH_TYPE_TN200)
-#else
-# define machine_is_tn200()	(0)
-#endif
-
-#ifdef CONFIG_MACH_C2MMI
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_C2MMI
-# endif
-# define machine_is_c2mmi()	(machine_arch_type == MACH_TYPE_C2MMI)
-#else
-# define machine_is_c2mmi()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MESON_6236M
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MESON_6236M
-# endif
-# define machine_is_meson_6236m()	(machine_arch_type == MACH_TYPE_MESON_6236M)
-#else
-# define machine_is_meson_6236m()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MESON_8626M
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MESON_8626M
-# endif
-# define machine_is_meson_8626m()	(machine_arch_type == MACH_TYPE_MESON_8626M)
-#else
-# define machine_is_meson_8626m()	(0)
-#endif
-
-#ifdef CONFIG_MACH_TUBE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TUBE
-# endif
-# define machine_is_tube()	(machine_arch_type == MACH_TYPE_TUBE)
-#else
-# define machine_is_tube()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MESSINA
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MESSINA
-# endif
-# define machine_is_messina()	(machine_arch_type == MACH_TYPE_MESSINA)
-#else
-# define machine_is_messina()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MX50_ARM2
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MX50_ARM2
-# endif
-# define machine_is_mx50_arm2()	(machine_arch_type == MACH_TYPE_MX50_ARM2)
-#else
-# define machine_is_mx50_arm2()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CETUS9263
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CETUS9263
-# endif
-# define machine_is_cetus9263()	(machine_arch_type == MACH_TYPE_CETUS9263)
-#else
-# define machine_is_cetus9263()	(0)
-#endif
-
-#ifdef CONFIG_MACH_BROWNSTONE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_BROWNSTONE
-# endif
-# define machine_is_brownstone()	(machine_arch_type == MACH_TYPE_BROWNSTONE)
-#else
-# define machine_is_brownstone()	(0)
-#endif
-
-#ifdef CONFIG_MACH_VMX25
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_VMX25
-# endif
-# define machine_is_vmx25()	(machine_arch_type == MACH_TYPE_VMX25)
-#else
-# define machine_is_vmx25()	(0)
-#endif
-
-#ifdef CONFIG_MACH_VMX51
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_VMX51
-# endif
-# define machine_is_vmx51()	(machine_arch_type == MACH_TYPE_VMX51)
-#else
-# define machine_is_vmx51()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ABACUS
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ABACUS
-# endif
-# define machine_is_abacus()	(machine_arch_type == MACH_TYPE_ABACUS)
-#else
-# define machine_is_abacus()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CM4745
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CM4745
-# endif
-# define machine_is_cm4745()	(machine_arch_type == MACH_TYPE_CM4745)
-#else
-# define machine_is_cm4745()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ORATISLINK
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ORATISLINK
-# endif
-# define machine_is_oratislink()	(machine_arch_type == MACH_TYPE_ORATISLINK)
-#else
-# define machine_is_oratislink()	(0)
-#endif
-
-#ifdef CONFIG_MACH_DAVINCI_DM365_DVR
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_DAVINCI_DM365_DVR
-# endif
-# define machine_is_davinci_dm365_dvr()	(machine_arch_type == MACH_TYPE_DAVINCI_DM365_DVR)
-#else
-# define machine_is_davinci_dm365_dvr()	(0)
-#endif
-
-#ifdef CONFIG_MACH_NETVIZ
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_NETVIZ
-# endif
-# define machine_is_netviz()	(machine_arch_type == MACH_TYPE_NETVIZ)
-#else
-# define machine_is_netviz()	(0)
-#endif
-
-#ifdef CONFIG_MACH_FLEXIBITY
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_FLEXIBITY
-# endif
-# define machine_is_flexibity()	(machine_arch_type == MACH_TYPE_FLEXIBITY)
-#else
-# define machine_is_flexibity()	(0)
-#endif
-
-#ifdef CONFIG_MACH_WLAN_COMPUTER
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_WLAN_COMPUTER
-# endif
-# define machine_is_wlan_computer()	(machine_arch_type == MACH_TYPE_WLAN_COMPUTER)
-#else
-# define machine_is_wlan_computer()	(0)
-#endif
-
-#ifdef CONFIG_MACH_LPC24XX
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_LPC24XX
-# endif
-# define machine_is_lpc24xx()	(machine_arch_type == MACH_TYPE_LPC24XX)
-#else
-# define machine_is_lpc24xx()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SPICA
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SPICA
-# endif
-# define machine_is_spica()	(machine_arch_type == MACH_TYPE_SPICA)
-#else
-# define machine_is_spica()	(0)
-#endif
-
-#ifdef CONFIG_MACH_GPSDISPLAY
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_GPSDISPLAY
-# endif
-# define machine_is_gpsdisplay()	(machine_arch_type == MACH_TYPE_GPSDISPLAY)
-#else
-# define machine_is_gpsdisplay()	(0)
-#endif
-
-#ifdef CONFIG_MACH_BIPNET
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_BIPNET
-# endif
-# define machine_is_bipnet()	(machine_arch_type == MACH_TYPE_BIPNET)
-#else
-# define machine_is_bipnet()	(0)
-#endif
-
-#ifdef CONFIG_MACH_OVERO_CTU_INERTIAL
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_OVERO_CTU_INERTIAL
-# endif
-# define machine_is_overo_ctu_inertial()	(machine_arch_type == MACH_TYPE_OVERO_CTU_INERTIAL)
-#else
-# define machine_is_overo_ctu_inertial()	(0)
-#endif
-
-#ifdef CONFIG_MACH_DAVINCI_DM355_MMM
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_DAVINCI_DM355_MMM
-# endif
-# define machine_is_davinci_dm355_mmm()	(machine_arch_type == MACH_TYPE_DAVINCI_DM355_MMM)
-#else
-# define machine_is_davinci_dm355_mmm()	(0)
-#endif
-
-#ifdef CONFIG_MACH_PC9260_V2
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PC9260_V2
-# endif
-# define machine_is_pc9260_v2()	(machine_arch_type == MACH_TYPE_PC9260_V2)
-#else
-# define machine_is_pc9260_v2()	(0)
-#endif
-
-#ifdef CONFIG_MACH_PTX7545
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PTX7545
-# endif
-# define machine_is_ptx7545()	(machine_arch_type == MACH_TYPE_PTX7545)
-#else
-# define machine_is_ptx7545()	(0)
-#endif
-
-#ifdef CONFIG_MACH_TM_EFDC
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TM_EFDC
-# endif
-# define machine_is_tm_efdc()	(machine_arch_type == MACH_TYPE_TM_EFDC)
-#else
-# define machine_is_tm_efdc()	(0)
-#endif
-
-#ifdef CONFIG_MACH_OMAP3_WALDO1
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_OMAP3_WALDO1
-# endif
-# define machine_is_omap3_waldo1()	(machine_arch_type == MACH_TYPE_OMAP3_WALDO1)
-#else
-# define machine_is_omap3_waldo1()	(0)
-#endif
-
-#ifdef CONFIG_MACH_FLYER
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_FLYER
-# endif
-# define machine_is_flyer()	(machine_arch_type == MACH_TYPE_FLYER)
-#else
-# define machine_is_flyer()	(0)
-#endif
-
-#ifdef CONFIG_MACH_TORNADO3240
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TORNADO3240
-# endif
-# define machine_is_tornado3240()	(machine_arch_type == MACH_TYPE_TORNADO3240)
-#else
-# define machine_is_tornado3240()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SOLI_01
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SOLI_01
-# endif
-# define machine_is_soli_01()	(machine_arch_type == MACH_TYPE_SOLI_01)
-#else
-# define machine_is_soli_01()	(0)
-#endif
-
-#ifdef CONFIG_MACH_OMAPL138_EUROPALC
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_OMAPL138_EUROPALC
-# endif
-# define machine_is_omapl138_europalc()	(machine_arch_type == MACH_TYPE_OMAPL138_EUROPALC)
-#else
-# define machine_is_omapl138_europalc()	(0)
-#endif
-
-#ifdef CONFIG_MACH_HELIOS_V1
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_HELIOS_V1
-# endif
-# define machine_is_helios_v1()	(machine_arch_type == MACH_TYPE_HELIOS_V1)
-#else
-# define machine_is_helios_v1()	(0)
-#endif
-
-#ifdef CONFIG_MACH_NETSPACE_LITE_V2
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_NETSPACE_LITE_V2
-# endif
-# define machine_is_netspace_lite_v2()	(machine_arch_type == MACH_TYPE_NETSPACE_LITE_V2)
-#else
-# define machine_is_netspace_lite_v2()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SSC
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SSC
-# endif
-# define machine_is_ssc()	(machine_arch_type == MACH_TYPE_SSC)
-#else
-# define machine_is_ssc()	(0)
-#endif
-
-#ifdef CONFIG_MACH_PREMIERWAVE_EN
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PREMIERWAVE_EN
-# endif
-# define machine_is_premierwave_en()	(machine_arch_type == MACH_TYPE_PREMIERWAVE_EN)
-#else
-# define machine_is_premierwave_en()	(0)
-#endif
-
-#ifdef CONFIG_MACH_WASABI
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_WASABI
-# endif
-# define machine_is_wasabi()	(machine_arch_type == MACH_TYPE_WASABI)
-#else
-# define machine_is_wasabi()	(0)
-#endif
-
-#ifdef CONFIG_MACH_VIVOW
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_VIVOW
-# endif
-# define machine_is_vivow()	(machine_arch_type == MACH_TYPE_VIVOW)
-#else
-# define machine_is_vivow()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MX50_RDP
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MX50_RDP
-# endif
-# define machine_is_mx50_rdp()	(machine_arch_type == MACH_TYPE_MX50_RDP)
-#else
-# define machine_is_mx50_rdp()	(0)
-#endif
-
-#ifdef CONFIG_MACH_UNIVERSAL_C210
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_UNIVERSAL_C210
-# endif
-# define machine_is_universal_c210()	(machine_arch_type == MACH_TYPE_UNIVERSAL_C210)
-#else
-# define machine_is_universal_c210()	(0)
-#endif
-
-#ifdef CONFIG_MACH_REAL6410
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_REAL6410
-# endif
-# define machine_is_real6410()	(machine_arch_type == MACH_TYPE_REAL6410)
-#else
-# define machine_is_real6410()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SPX_SAKURA
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SPX_SAKURA
-# endif
-# define machine_is_spx_sakura()	(machine_arch_type == MACH_TYPE_SPX_SAKURA)
-#else
-# define machine_is_spx_sakura()	(0)
-#endif
-
-#ifdef CONFIG_MACH_IJ3K_2440
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_IJ3K_2440
-# endif
-# define machine_is_ij3k_2440()	(machine_arch_type == MACH_TYPE_IJ3K_2440)
-#else
-# define machine_is_ij3k_2440()	(0)
-#endif
-
-#ifdef CONFIG_MACH_OMAP3_BC10
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_OMAP3_BC10
-# endif
-# define machine_is_omap3_bc10()	(machine_arch_type == MACH_TYPE_OMAP3_BC10)
-#else
-# define machine_is_omap3_bc10()	(0)
-#endif
-
-#ifdef CONFIG_MACH_THEBE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_THEBE
-# endif
-# define machine_is_thebe()	(machine_arch_type == MACH_TYPE_THEBE)
-#else
-# define machine_is_thebe()	(0)
-#endif
-
-#ifdef CONFIG_MACH_RV082
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_RV082
-# endif
-# define machine_is_rv082()	(machine_arch_type == MACH_TYPE_RV082)
-#else
-# define machine_is_rv082()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ARMLGUEST
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ARMLGUEST
-# endif
-# define machine_is_armlguest()	(machine_arch_type == MACH_TYPE_ARMLGUEST)
-#else
-# define machine_is_armlguest()	(0)
-#endif
-
-#ifdef CONFIG_MACH_TJINC1000
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TJINC1000
-# endif
-# define machine_is_tjinc1000()	(machine_arch_type == MACH_TYPE_TJINC1000)
-#else
-# define machine_is_tjinc1000()	(0)
-#endif
-
-#ifdef CONFIG_MACH_DOCKSTAR
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_DOCKSTAR
-# endif
-# define machine_is_dockstar()	(machine_arch_type == MACH_TYPE_DOCKSTAR)
-#else
-# define machine_is_dockstar()	(0)
-#endif
-
-#ifdef CONFIG_MACH_AX8008
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_AX8008
-# endif
-# define machine_is_ax8008()	(machine_arch_type == MACH_TYPE_AX8008)
-#else
-# define machine_is_ax8008()	(0)
-#endif
-
-#ifdef CONFIG_MACH_GNET_SGCE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_GNET_SGCE
-# endif
-# define machine_is_gnet_sgce()	(machine_arch_type == MACH_TYPE_GNET_SGCE)
-#else
-# define machine_is_gnet_sgce()	(0)
-#endif
-
-#ifdef CONFIG_MACH_PXWNAS_500_1000
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PXWNAS_500_1000
-# endif
-# define machine_is_pxwnas_500_1000()	(machine_arch_type == MACH_TYPE_PXWNAS_500_1000)
-#else
-# define machine_is_pxwnas_500_1000()	(0)
-#endif
-
-#ifdef CONFIG_MACH_EA20
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_EA20
-# endif
-# define machine_is_ea20()	(machine_arch_type == MACH_TYPE_EA20)
-#else
-# define machine_is_ea20()	(0)
-#endif
-
-#ifdef CONFIG_MACH_AWM2
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_AWM2
-# endif
-# define machine_is_awm2()	(machine_arch_type == MACH_TYPE_AWM2)
-#else
-# define machine_is_awm2()	(0)
-#endif
-
-#ifdef CONFIG_MACH_TI8148EVM
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TI8148EVM
-# endif
-# define machine_is_ti8148evm()	(machine_arch_type == MACH_TYPE_TI8148EVM)
-#else
-# define machine_is_ti8148evm()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SEABOARD
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SEABOARD
-# endif
-# define machine_is_seaboard()	(machine_arch_type == MACH_TYPE_SEABOARD)
-#else
-# define machine_is_seaboard()	(0)
-#endif
-
-#ifdef CONFIG_MACH_LINKSTATION_CHLV2
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_LINKSTATION_CHLV2
-# endif
-# define machine_is_linkstation_chlv2()	(machine_arch_type == MACH_TYPE_LINKSTATION_CHLV2)
-#else
-# define machine_is_linkstation_chlv2()	(0)
-#endif
-
-#ifdef CONFIG_MACH_TERA_PRO2_RACK
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TERA_PRO2_RACK
-# endif
-# define machine_is_tera_pro2_rack()	(machine_arch_type == MACH_TYPE_TERA_PRO2_RACK)
-#else
-# define machine_is_tera_pro2_rack()	(0)
-#endif
-
-#ifdef CONFIG_MACH_RUBYS
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_RUBYS
-# endif
-# define machine_is_rubys()	(machine_arch_type == MACH_TYPE_RUBYS)
-#else
-# define machine_is_rubys()	(0)
-#endif
-
-#ifdef CONFIG_MACH_AQUARIUS
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_AQUARIUS
-# endif
-# define machine_is_aquarius()	(machine_arch_type == MACH_TYPE_AQUARIUS)
-#else
-# define machine_is_aquarius()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MX53_ARD
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MX53_ARD
-# endif
-# define machine_is_mx53_ard()	(machine_arch_type == MACH_TYPE_MX53_ARD)
-#else
-# define machine_is_mx53_ard()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MX53_SMD
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MX53_SMD
-# endif
-# define machine_is_mx53_smd()	(machine_arch_type == MACH_TYPE_MX53_SMD)
-#else
-# define machine_is_mx53_smd()	(0)
-#endif
-
-#ifdef CONFIG_MACH_LSWXL
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_LSWXL
-# endif
-# define machine_is_lswxl()	(machine_arch_type == MACH_TYPE_LSWXL)
-#else
-# define machine_is_lswxl()	(0)
-#endif
-
-#ifdef CONFIG_MACH_DOVE_AVNG_V3
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_DOVE_AVNG_V3
-# endif
-# define machine_is_dove_avng_v3()	(machine_arch_type == MACH_TYPE_DOVE_AVNG_V3)
-#else
-# define machine_is_dove_avng_v3()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SDI_ESS_9263
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SDI_ESS_9263
-# endif
-# define machine_is_sdi_ess_9263()	(machine_arch_type == MACH_TYPE_SDI_ESS_9263)
-#else
-# define machine_is_sdi_ess_9263()	(0)
-#endif
-
-#ifdef CONFIG_MACH_JOCPU550
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_JOCPU550
-# endif
-# define machine_is_jocpu550()	(machine_arch_type == MACH_TYPE_JOCPU550)
-#else
-# define machine_is_jocpu550()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MSM8X60_RUMI3
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MSM8X60_RUMI3
-# endif
-# define machine_is_msm8x60_rumi3()	(machine_arch_type == MACH_TYPE_MSM8X60_RUMI3)
-#else
-# define machine_is_msm8x60_rumi3()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MSM8X60_FFA
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MSM8X60_FFA
-# endif
-# define machine_is_msm8x60_ffa()	(machine_arch_type == MACH_TYPE_MSM8X60_FFA)
-#else
-# define machine_is_msm8x60_ffa()	(0)
-#endif
-
-#ifdef CONFIG_MACH_YANOMAMI
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_YANOMAMI
-# endif
-# define machine_is_yanomami()	(machine_arch_type == MACH_TYPE_YANOMAMI)
-#else
-# define machine_is_yanomami()	(0)
-#endif
-
-#ifdef CONFIG_MACH_GTA04
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_GTA04
-# endif
-# define machine_is_gta04()	(machine_arch_type == MACH_TYPE_GTA04)
-#else
-# define machine_is_gta04()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CM_A510
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CM_A510
-# endif
-# define machine_is_cm_a510()	(machine_arch_type == MACH_TYPE_CM_A510)
-#else
-# define machine_is_cm_a510()	(0)
-#endif
-
-#ifdef CONFIG_MACH_OMAP3_RFS200
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_OMAP3_RFS200
-# endif
-# define machine_is_omap3_rfs200()	(machine_arch_type == MACH_TYPE_OMAP3_RFS200)
-#else
-# define machine_is_omap3_rfs200()	(0)
-#endif
-
-#ifdef CONFIG_MACH_KX33XX
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_KX33XX
-# endif
-# define machine_is_kx33xx()	(machine_arch_type == MACH_TYPE_KX33XX)
-#else
-# define machine_is_kx33xx()	(0)
-#endif
-
-#ifdef CONFIG_MACH_PTX7510
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PTX7510
-# endif
-# define machine_is_ptx7510()	(machine_arch_type == MACH_TYPE_PTX7510)
-#else
-# define machine_is_ptx7510()	(0)
-#endif
-
-#ifdef CONFIG_MACH_TOP9000
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TOP9000
-# endif
-# define machine_is_top9000()	(machine_arch_type == MACH_TYPE_TOP9000)
-#else
-# define machine_is_top9000()	(0)
-#endif
-
-#ifdef CONFIG_MACH_TEENOTE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TEENOTE
-# endif
-# define machine_is_teenote()	(machine_arch_type == MACH_TYPE_TEENOTE)
-#else
-# define machine_is_teenote()	(0)
-#endif
-
-#ifdef CONFIG_MACH_TS3
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TS3
-# endif
-# define machine_is_ts3()	(machine_arch_type == MACH_TYPE_TS3)
-#else
-# define machine_is_ts3()	(0)
-#endif
-
-#ifdef CONFIG_MACH_A0
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_A0
-# endif
-# define machine_is_a0()	(machine_arch_type == MACH_TYPE_A0)
-#else
-# define machine_is_a0()	(0)
-#endif
-
-#ifdef CONFIG_MACH_FSM9XXX_SURF
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_FSM9XXX_SURF
-# endif
-# define machine_is_fsm9xxx_surf()	(machine_arch_type == MACH_TYPE_FSM9XXX_SURF)
-#else
-# define machine_is_fsm9xxx_surf()	(0)
-#endif
-
-#ifdef CONFIG_MACH_FSM9XXX_FFA
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_FSM9XXX_FFA
-# endif
-# define machine_is_fsm9xxx_ffa()	(machine_arch_type == MACH_TYPE_FSM9XXX_FFA)
-#else
-# define machine_is_fsm9xxx_ffa()	(0)
-#endif
-
-#ifdef CONFIG_MACH_FRRHWCDMA60W
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_FRRHWCDMA60W
-# endif
-# define machine_is_frrhwcdma60w()	(machine_arch_type == MACH_TYPE_FRRHWCDMA60W)
-#else
-# define machine_is_frrhwcdma60w()	(0)
-#endif
-
-#ifdef CONFIG_MACH_REMUS
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_REMUS
-# endif
-# define machine_is_remus()	(machine_arch_type == MACH_TYPE_REMUS)
-#else
-# define machine_is_remus()	(0)
-#endif
-
-#ifdef CONFIG_MACH_AT91CAP7XDK
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_AT91CAP7XDK
-# endif
-# define machine_is_at91cap7xdk()	(machine_arch_type == MACH_TYPE_AT91CAP7XDK)
-#else
-# define machine_is_at91cap7xdk()	(0)
-#endif
-
-#ifdef CONFIG_MACH_AT91CAP7STK
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_AT91CAP7STK
-# endif
-# define machine_is_at91cap7stk()	(machine_arch_type == MACH_TYPE_AT91CAP7STK)
-#else
-# define machine_is_at91cap7stk()	(0)
-#endif
-
-#ifdef CONFIG_MACH_KT_SBC_SAM9_1
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_KT_SBC_SAM9_1
-# endif
-# define machine_is_kt_sbc_sam9_1()	(machine_arch_type == MACH_TYPE_KT_SBC_SAM9_1)
-#else
-# define machine_is_kt_sbc_sam9_1()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ORATISROUTER
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ORATISROUTER
-# endif
-# define machine_is_oratisrouter()	(machine_arch_type == MACH_TYPE_ORATISROUTER)
-#else
-# define machine_is_oratisrouter()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ARMADA_XP_DB
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ARMADA_XP_DB
-# endif
-# define machine_is_armada_xp_db()	(machine_arch_type == MACH_TYPE_ARMADA_XP_DB)
-#else
-# define machine_is_armada_xp_db()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SPDM
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SPDM
-# endif
-# define machine_is_spdm()	(machine_arch_type == MACH_TYPE_SPDM)
-#else
-# define machine_is_spdm()	(0)
-#endif
-
-#ifdef CONFIG_MACH_GTIB
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_GTIB
-# endif
-# define machine_is_gtib()	(machine_arch_type == MACH_TYPE_GTIB)
-#else
-# define machine_is_gtib()	(0)
-#endif
-
-#ifdef CONFIG_MACH_DGM3240
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_DGM3240
-# endif
-# define machine_is_dgm3240()	(machine_arch_type == MACH_TYPE_DGM3240)
-#else
-# define machine_is_dgm3240()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ATLAS_I_LPE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ATLAS_I_LPE
-# endif
-# define machine_is_atlas_i_lpe()	(machine_arch_type == MACH_TYPE_ATLAS_I_LPE)
-#else
-# define machine_is_atlas_i_lpe()	(0)
-#endif
-
-#ifdef CONFIG_MACH_HTCMEGA
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_HTCMEGA
-# endif
-# define machine_is_htcmega()	(machine_arch_type == MACH_TYPE_HTCMEGA)
-#else
-# define machine_is_htcmega()	(0)
-#endif
-
-#ifdef CONFIG_MACH_TRICORDER
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TRICORDER
-# endif
-# define machine_is_tricorder()	(machine_arch_type == MACH_TYPE_TRICORDER)
-#else
-# define machine_is_tricorder()	(0)
-#endif
-
-#ifdef CONFIG_MACH_TX28
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TX28
-# endif
-# define machine_is_tx28()	(machine_arch_type == MACH_TYPE_TX28)
-#else
-# define machine_is_tx28()	(0)
-#endif
-
-#ifdef CONFIG_MACH_BSTBRD
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_BSTBRD
-# endif
-# define machine_is_bstbrd()	(machine_arch_type == MACH_TYPE_BSTBRD)
-#else
-# define machine_is_bstbrd()	(0)
-#endif
-
-#ifdef CONFIG_MACH_PWB3090
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PWB3090
-# endif
-# define machine_is_pwb3090()	(machine_arch_type == MACH_TYPE_PWB3090)
-#else
-# define machine_is_pwb3090()	(0)
-#endif
-
-#ifdef CONFIG_MACH_IDEA6410
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_IDEA6410
-# endif
-# define machine_is_idea6410()	(machine_arch_type == MACH_TYPE_IDEA6410)
-#else
-# define machine_is_idea6410()	(0)
-#endif
-
-#ifdef CONFIG_MACH_QBC9263
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_QBC9263
-# endif
-# define machine_is_qbc9263()	(machine_arch_type == MACH_TYPE_QBC9263)
-#else
-# define machine_is_qbc9263()	(0)
-#endif
-
-#ifdef CONFIG_MACH_BORABORA
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_BORABORA
-# endif
-# define machine_is_borabora()	(machine_arch_type == MACH_TYPE_BORABORA)
-#else
-# define machine_is_borabora()	(0)
-#endif
-
-#ifdef CONFIG_MACH_VALDEZ
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_VALDEZ
-# endif
-# define machine_is_valdez()	(machine_arch_type == MACH_TYPE_VALDEZ)
-#else
-# define machine_is_valdez()	(0)
-#endif
-
-#ifdef CONFIG_MACH_LS9G20
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_LS9G20
-# endif
-# define machine_is_ls9g20()	(machine_arch_type == MACH_TYPE_LS9G20)
-#else
-# define machine_is_ls9g20()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MIOS_V1
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MIOS_V1
-# endif
-# define machine_is_mios_v1()	(machine_arch_type == MACH_TYPE_MIOS_V1)
-#else
-# define machine_is_mios_v1()	(0)
-#endif
-
-#ifdef CONFIG_MACH_S5PC110_CRESPO
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_S5PC110_CRESPO
-# endif
-# define machine_is_s5pc110_crespo()	(machine_arch_type == MACH_TYPE_S5PC110_CRESPO)
-#else
-# define machine_is_s5pc110_crespo()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CONTROLTEK9G20
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CONTROLTEK9G20
-# endif
-# define machine_is_controltek9g20()	(machine_arch_type == MACH_TYPE_CONTROLTEK9G20)
-#else
-# define machine_is_controltek9g20()	(0)
-#endif
-
-#ifdef CONFIG_MACH_TIN307
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TIN307
-# endif
-# define machine_is_tin307()	(machine_arch_type == MACH_TYPE_TIN307)
-#else
-# define machine_is_tin307()	(0)
-#endif
-
-#ifdef CONFIG_MACH_TIN510
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TIN510
-# endif
-# define machine_is_tin510()	(machine_arch_type == MACH_TYPE_TIN510)
-#else
-# define machine_is_tin510()	(0)
-#endif
-
-#ifdef CONFIG_MACH_BLUECHEESE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_BLUECHEESE
-# endif
-# define machine_is_bluecheese()	(machine_arch_type == MACH_TYPE_BLUECHEESE)
-#else
-# define machine_is_bluecheese()	(0)
-#endif
-
-#ifdef CONFIG_MACH_TEM3X30
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TEM3X30
-# endif
-# define machine_is_tem3x30()	(machine_arch_type == MACH_TYPE_TEM3X30)
-#else
-# define machine_is_tem3x30()	(0)
-#endif
-
-#ifdef CONFIG_MACH_HARVEST_DESOTO
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_HARVEST_DESOTO
-# endif
-# define machine_is_harvest_desoto()	(machine_arch_type == MACH_TYPE_HARVEST_DESOTO)
-#else
-# define machine_is_harvest_desoto()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MSM8X60_QRDC
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MSM8X60_QRDC
-# endif
-# define machine_is_msm8x60_qrdc()	(machine_arch_type == MACH_TYPE_MSM8X60_QRDC)
-#else
-# define machine_is_msm8x60_qrdc()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SPEAR900
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SPEAR900
-# endif
-# define machine_is_spear900()	(machine_arch_type == MACH_TYPE_SPEAR900)
-#else
-# define machine_is_spear900()	(0)
-#endif
-
-#ifdef CONFIG_MACH_PCONTROL_G20
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PCONTROL_G20
-# endif
-# define machine_is_pcontrol_g20()	(machine_arch_type == MACH_TYPE_PCONTROL_G20)
-#else
-# define machine_is_pcontrol_g20()	(0)
-#endif
-
-#ifdef CONFIG_MACH_RDSTOR
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_RDSTOR
-# endif
-# define machine_is_rdstor()	(machine_arch_type == MACH_TYPE_RDSTOR)
-#else
-# define machine_is_rdstor()	(0)
-#endif
-
-#ifdef CONFIG_MACH_USDLOADER
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_USDLOADER
-# endif
-# define machine_is_usdloader()	(machine_arch_type == MACH_TYPE_USDLOADER)
-#else
-# define machine_is_usdloader()	(0)
-#endif
-
-#ifdef CONFIG_MACH_TSOPLOADER
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TSOPLOADER
-# endif
-# define machine_is_tsoploader()	(machine_arch_type == MACH_TYPE_TSOPLOADER)
-#else
-# define machine_is_tsoploader()	(0)
-#endif
-
-#ifdef CONFIG_MACH_KRONOS
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_KRONOS
-# endif
-# define machine_is_kronos()	(machine_arch_type == MACH_TYPE_KRONOS)
-#else
-# define machine_is_kronos()	(0)
-#endif
-
-#ifdef CONFIG_MACH_FFCORE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_FFCORE
-# endif
-# define machine_is_ffcore()	(machine_arch_type == MACH_TYPE_FFCORE)
-#else
-# define machine_is_ffcore()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MONE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MONE
-# endif
-# define machine_is_mone()	(machine_arch_type == MACH_TYPE_MONE)
-#else
-# define machine_is_mone()	(0)
-#endif
-
-#ifdef CONFIG_MACH_UNIT2S
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_UNIT2S
-# endif
-# define machine_is_unit2s()	(machine_arch_type == MACH_TYPE_UNIT2S)
-#else
-# define machine_is_unit2s()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ACER_A5
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ACER_A5
-# endif
-# define machine_is_acer_a5()	(machine_arch_type == MACH_TYPE_ACER_A5)
-#else
-# define machine_is_acer_a5()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ETHERPRO_ISP
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ETHERPRO_ISP
-# endif
-# define machine_is_etherpro_isp()	(machine_arch_type == MACH_TYPE_ETHERPRO_ISP)
-#else
-# define machine_is_etherpro_isp()	(0)
-#endif
-
-#ifdef CONFIG_MACH_STRETCHS7000
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_STRETCHS7000
-# endif
-# define machine_is_stretchs7000()	(machine_arch_type == MACH_TYPE_STRETCHS7000)
-#else
-# define machine_is_stretchs7000()	(0)
-#endif
-
-#ifdef CONFIG_MACH_P87_SMARTSIM
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_P87_SMARTSIM
-# endif
-# define machine_is_p87_smartsim()	(machine_arch_type == MACH_TYPE_P87_SMARTSIM)
-#else
-# define machine_is_p87_smartsim()	(0)
-#endif
-
-#ifdef CONFIG_MACH_TULIP
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TULIP
-# endif
-# define machine_is_tulip()	(machine_arch_type == MACH_TYPE_TULIP)
-#else
-# define machine_is_tulip()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SUNFLOWER
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SUNFLOWER
-# endif
-# define machine_is_sunflower()	(machine_arch_type == MACH_TYPE_SUNFLOWER)
-#else
-# define machine_is_sunflower()	(0)
-#endif
-
-#ifdef CONFIG_MACH_RIB
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_RIB
-# endif
-# define machine_is_rib()	(machine_arch_type == MACH_TYPE_RIB)
-#else
-# define machine_is_rib()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CLOD
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CLOD
-# endif
-# define machine_is_clod()	(machine_arch_type == MACH_TYPE_CLOD)
-#else
-# define machine_is_clod()	(0)
-#endif
-
-#ifdef CONFIG_MACH_RUMP
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_RUMP
-# endif
-# define machine_is_rump()	(machine_arch_type == MACH_TYPE_RUMP)
-#else
-# define machine_is_rump()	(0)
-#endif
-
-#ifdef CONFIG_MACH_TENDERLOIN
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TENDERLOIN
-# endif
-# define machine_is_tenderloin()	(machine_arch_type == MACH_TYPE_TENDERLOIN)
-#else
-# define machine_is_tenderloin()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SHORTLOIN
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SHORTLOIN
-# endif
-# define machine_is_shortloin()	(machine_arch_type == MACH_TYPE_SHORTLOIN)
-#else
-# define machine_is_shortloin()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CRESPO
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CRESPO
-# endif
-# define machine_is_crespo()	(machine_arch_type == MACH_TYPE_CRESPO)
-#else
-# define machine_is_crespo()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ANTARES
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ANTARES
-# endif
-# define machine_is_antares()	(machine_arch_type == MACH_TYPE_ANTARES)
-#else
-# define machine_is_antares()	(0)
-#endif
-
-#ifdef CONFIG_MACH_WB40N
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_WB40N
-# endif
-# define machine_is_wb40n()	(machine_arch_type == MACH_TYPE_WB40N)
-#else
-# define machine_is_wb40n()	(0)
-#endif
-
-#ifdef CONFIG_MACH_HERRING
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_HERRING
-# endif
-# define machine_is_herring()	(machine_arch_type == MACH_TYPE_HERRING)
-#else
-# define machine_is_herring()	(0)
-#endif
-
-#ifdef CONFIG_MACH_NAXY400
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_NAXY400
-# endif
-# define machine_is_naxy400()	(machine_arch_type == MACH_TYPE_NAXY400)
-#else
-# define machine_is_naxy400()	(0)
-#endif
-
-#ifdef CONFIG_MACH_NAXY1200
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_NAXY1200
-# endif
-# define machine_is_naxy1200()	(machine_arch_type == MACH_TYPE_NAXY1200)
-#else
-# define machine_is_naxy1200()	(0)
-#endif
-
-#ifdef CONFIG_MACH_VPR200
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_VPR200
-# endif
-# define machine_is_vpr200()	(machine_arch_type == MACH_TYPE_VPR200)
-#else
-# define machine_is_vpr200()	(0)
-#endif
-
-#ifdef CONFIG_MACH_BUG20
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_BUG20
-# endif
-# define machine_is_bug20()	(machine_arch_type == MACH_TYPE_BUG20)
-#else
-# define machine_is_bug20()	(0)
-#endif
-
-#ifdef CONFIG_MACH_GOFLEXNET
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_GOFLEXNET
-# endif
-# define machine_is_goflexnet()	(machine_arch_type == MACH_TYPE_GOFLEXNET)
-#else
-# define machine_is_goflexnet()	(0)
-#endif
-
-#ifdef CONFIG_MACH_TORBRECK
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TORBRECK
-# endif
-# define machine_is_torbreck()	(machine_arch_type == MACH_TYPE_TORBRECK)
-#else
-# define machine_is_torbreck()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SAARB_MG1
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SAARB_MG1
-# endif
-# define machine_is_saarb_mg1()	(machine_arch_type == MACH_TYPE_SAARB_MG1)
-#else
-# define machine_is_saarb_mg1()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CALLISTO
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CALLISTO
-# endif
-# define machine_is_callisto()	(machine_arch_type == MACH_TYPE_CALLISTO)
-#else
-# define machine_is_callisto()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MULTHSU
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MULTHSU
-# endif
-# define machine_is_multhsu()	(machine_arch_type == MACH_TYPE_MULTHSU)
-#else
-# define machine_is_multhsu()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SALUDA
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SALUDA
-# endif
-# define machine_is_saluda()	(machine_arch_type == MACH_TYPE_SALUDA)
-#else
-# define machine_is_saluda()	(0)
-#endif
-
-#ifdef CONFIG_MACH_PEMP_OMAP3_APOLLO
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PEMP_OMAP3_APOLLO
-# endif
-# define machine_is_pemp_omap3_apollo()	(machine_arch_type == MACH_TYPE_PEMP_OMAP3_APOLLO)
-#else
-# define machine_is_pemp_omap3_apollo()	(0)
-#endif
-
-#ifdef CONFIG_MACH_VC0718
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_VC0718
-# endif
-# define machine_is_vc0718()	(machine_arch_type == MACH_TYPE_VC0718)
-#else
-# define machine_is_vc0718()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MVBLX
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MVBLX
-# endif
-# define machine_is_mvblx()	(machine_arch_type == MACH_TYPE_MVBLX)
-#else
-# define machine_is_mvblx()	(0)
-#endif
-
-#ifdef CONFIG_MACH_INHAND_APEIRON
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_INHAND_APEIRON
-# endif
-# define machine_is_inhand_apeiron()	(machine_arch_type == MACH_TYPE_INHAND_APEIRON)
-#else
-# define machine_is_inhand_apeiron()	(0)
-#endif
-
-#ifdef CONFIG_MACH_INHAND_FURY
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_INHAND_FURY
-# endif
-# define machine_is_inhand_fury()	(machine_arch_type == MACH_TYPE_INHAND_FURY)
-#else
-# define machine_is_inhand_fury()	(0)
-#endif
-
-#ifdef CONFIG_MACH_INHAND_SIREN
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_INHAND_SIREN
-# endif
-# define machine_is_inhand_siren()	(machine_arch_type == MACH_TYPE_INHAND_SIREN)
-#else
-# define machine_is_inhand_siren()	(0)
-#endif
-
-#ifdef CONFIG_MACH_HDNVP
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_HDNVP
-# endif
-# define machine_is_hdnvp()	(machine_arch_type == MACH_TYPE_HDNVP)
-#else
-# define machine_is_hdnvp()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SOFTWINNER
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SOFTWINNER
-# endif
-# define machine_is_softwinner()	(machine_arch_type == MACH_TYPE_SOFTWINNER)
-#else
-# define machine_is_softwinner()	(0)
-#endif
-
-#ifdef CONFIG_MACH_PRIMA2_EVB
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PRIMA2_EVB
-# endif
-# define machine_is_prima2_evb()	(machine_arch_type == MACH_TYPE_PRIMA2_EVB)
-#else
-# define machine_is_prima2_evb()	(0)
-#endif
-
-#ifdef CONFIG_MACH_NAS6210
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_NAS6210
-# endif
-# define machine_is_nas6210()	(machine_arch_type == MACH_TYPE_NAS6210)
-#else
-# define machine_is_nas6210()	(0)
-#endif
-
-#ifdef CONFIG_MACH_UNISDEV
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_UNISDEV
-# endif
-# define machine_is_unisdev()	(machine_arch_type == MACH_TYPE_UNISDEV)
-#else
-# define machine_is_unisdev()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SBCA11
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SBCA11
-# endif
-# define machine_is_sbca11()	(machine_arch_type == MACH_TYPE_SBCA11)
-#else
-# define machine_is_sbca11()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SAGA
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SAGA
-# endif
-# define machine_is_saga()	(machine_arch_type == MACH_TYPE_SAGA)
-#else
-# define machine_is_saga()	(0)
-#endif
-
-#ifdef CONFIG_MACH_NS_K330
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_NS_K330
-# endif
-# define machine_is_ns_k330()	(machine_arch_type == MACH_TYPE_NS_K330)
-#else
-# define machine_is_ns_k330()	(0)
-#endif
-
-#ifdef CONFIG_MACH_TANNA
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TANNA
-# endif
-# define machine_is_tanna()	(machine_arch_type == MACH_TYPE_TANNA)
-#else
-# define machine_is_tanna()	(0)
-#endif
-
-#ifdef CONFIG_MACH_IMATE8502
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_IMATE8502
-# endif
-# define machine_is_imate8502()	(machine_arch_type == MACH_TYPE_IMATE8502)
-#else
-# define machine_is_imate8502()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ASPEN
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ASPEN
-# endif
-# define machine_is_aspen()	(machine_arch_type == MACH_TYPE_ASPEN)
-#else
-# define machine_is_aspen()	(0)
-#endif
-
-#ifdef CONFIG_MACH_DAINTREE_CWAC
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_DAINTREE_CWAC
-# endif
-# define machine_is_daintree_cwac()	(machine_arch_type == MACH_TYPE_DAINTREE_CWAC)
-#else
-# define machine_is_daintree_cwac()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ZMX25
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ZMX25
-# endif
-# define machine_is_zmx25()	(machine_arch_type == MACH_TYPE_ZMX25)
-#else
-# define machine_is_zmx25()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MAPLE1
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MAPLE1
-# endif
-# define machine_is_maple1()	(machine_arch_type == MACH_TYPE_MAPLE1)
-#else
-# define machine_is_maple1()	(0)
-#endif
-
-#ifdef CONFIG_MACH_QSD8X72_SURF
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_QSD8X72_SURF
-# endif
-# define machine_is_qsd8x72_surf()	(machine_arch_type == MACH_TYPE_QSD8X72_SURF)
-#else
-# define machine_is_qsd8x72_surf()	(0)
-#endif
-
-#ifdef CONFIG_MACH_QSD8X72_FFA
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_QSD8X72_FFA
-# endif
-# define machine_is_qsd8x72_ffa()	(machine_arch_type == MACH_TYPE_QSD8X72_FFA)
-#else
-# define machine_is_qsd8x72_ffa()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ABILENE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ABILENE
-# endif
-# define machine_is_abilene()	(machine_arch_type == MACH_TYPE_ABILENE)
-#else
-# define machine_is_abilene()	(0)
-#endif
-
-#ifdef CONFIG_MACH_EIGEN_TTR
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_EIGEN_TTR
-# endif
-# define machine_is_eigen_ttr()	(machine_arch_type == MACH_TYPE_EIGEN_TTR)
-#else
-# define machine_is_eigen_ttr()	(0)
-#endif
-
-#ifdef CONFIG_MACH_IOMEGA_IX2_200
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_IOMEGA_IX2_200
-# endif
-# define machine_is_iomega_ix2_200()	(machine_arch_type == MACH_TYPE_IOMEGA_IX2_200)
-#else
-# define machine_is_iomega_ix2_200()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CORETEC_VCX7400
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CORETEC_VCX7400
-# endif
-# define machine_is_coretec_vcx7400()	(machine_arch_type == MACH_TYPE_CORETEC_VCX7400)
-#else
-# define machine_is_coretec_vcx7400()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SANTIAGO
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SANTIAGO
-# endif
-# define machine_is_santiago()	(machine_arch_type == MACH_TYPE_SANTIAGO)
-#else
-# define machine_is_santiago()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MX257SOL
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MX257SOL
-# endif
-# define machine_is_mx257sol()	(machine_arch_type == MACH_TYPE_MX257SOL)
-#else
-# define machine_is_mx257sol()	(0)
-#endif
-
-#ifdef CONFIG_MACH_STRASBOURG
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_STRASBOURG
-# endif
-# define machine_is_strasbourg()	(machine_arch_type == MACH_TYPE_STRASBOURG)
-#else
-# define machine_is_strasbourg()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MSM8X60_FLUID
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MSM8X60_FLUID
-# endif
-# define machine_is_msm8x60_fluid()	(machine_arch_type == MACH_TYPE_MSM8X60_FLUID)
-#else
-# define machine_is_msm8x60_fluid()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SMARTQV5
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SMARTQV5
-# endif
-# define machine_is_smartqv5()	(machine_arch_type == MACH_TYPE_SMARTQV5)
-#else
-# define machine_is_smartqv5()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SMARTQV3
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SMARTQV3
-# endif
-# define machine_is_smartqv3()	(machine_arch_type == MACH_TYPE_SMARTQV3)
-#else
-# define machine_is_smartqv3()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SMARTQV7
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SMARTQV7
-# endif
-# define machine_is_smartqv7()	(machine_arch_type == MACH_TYPE_SMARTQV7)
-#else
-# define machine_is_smartqv7()	(0)
-#endif
-
-#ifdef CONFIG_MACH_PAZ00
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PAZ00
-# endif
-# define machine_is_paz00()	(machine_arch_type == MACH_TYPE_PAZ00)
-#else
-# define machine_is_paz00()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ACMENETUSFOXG20
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ACMENETUSFOXG20
-# endif
-# define machine_is_acmenetusfoxg20()	(machine_arch_type == MACH_TYPE_ACMENETUSFOXG20)
-#else
-# define machine_is_acmenetusfoxg20()	(0)
-#endif
-
-#ifdef CONFIG_MACH_HTCWILLOW
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_HTCWILLOW
-# endif
-# define machine_is_htcwillow()	(machine_arch_type == MACH_TYPE_HTCWILLOW)
-#else
-# define machine_is_htcwillow()	(0)
-#endif
-
-#ifdef CONFIG_MACH_FWBD_0404
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_FWBD_0404
-# endif
-# define machine_is_fwbd_0404()	(machine_arch_type == MACH_TYPE_FWBD_0404)
-#else
-# define machine_is_fwbd_0404()	(0)
-#endif
-
-#ifdef CONFIG_MACH_HDGU
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_HDGU
-# endif
-# define machine_is_hdgu()	(machine_arch_type == MACH_TYPE_HDGU)
-#else
-# define machine_is_hdgu()	(0)
-#endif
-
-#ifdef CONFIG_MACH_PYRAMID
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PYRAMID
-# endif
-# define machine_is_pyramid()	(machine_arch_type == MACH_TYPE_PYRAMID)
-#else
-# define machine_is_pyramid()	(0)
-#endif
-
-#ifdef CONFIG_MACH_EPIPHAN
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_EPIPHAN
-# endif
-# define machine_is_epiphan()	(machine_arch_type == MACH_TYPE_EPIPHAN)
-#else
-# define machine_is_epiphan()	(0)
-#endif
-
-#ifdef CONFIG_MACH_OMAP_BENDER
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_OMAP_BENDER
-# endif
-# define machine_is_omap_bender()	(machine_arch_type == MACH_TYPE_OMAP_BENDER)
-#else
-# define machine_is_omap_bender()	(0)
-#endif
-
-#ifdef CONFIG_MACH_GURNARD
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_GURNARD
-# endif
-# define machine_is_gurnard()	(machine_arch_type == MACH_TYPE_GURNARD)
-#else
-# define machine_is_gurnard()	(0)
-#endif
-
-#ifdef CONFIG_MACH_GTL_IT5100
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_GTL_IT5100
-# endif
-# define machine_is_gtl_it5100()	(machine_arch_type == MACH_TYPE_GTL_IT5100)
-#else
-# define machine_is_gtl_it5100()	(0)
-#endif
-
-#ifdef CONFIG_MACH_BCM2708
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_BCM2708
-# endif
-# define machine_is_bcm2708()	(machine_arch_type == MACH_TYPE_BCM2708)
-#else
-# define machine_is_bcm2708()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MX51_GGC
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MX51_GGC
-# endif
-# define machine_is_mx51_ggc()	(machine_arch_type == MACH_TYPE_MX51_GGC)
-#else
-# define machine_is_mx51_ggc()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SHARESPACE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SHARESPACE
-# endif
-# define machine_is_sharespace()	(machine_arch_type == MACH_TYPE_SHARESPACE)
-#else
-# define machine_is_sharespace()	(0)
-#endif
-
-#ifdef CONFIG_MACH_HABA_KNX_EXPLORER
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_HABA_KNX_EXPLORER
-# endif
-# define machine_is_haba_knx_explorer()	(machine_arch_type == MACH_TYPE_HABA_KNX_EXPLORER)
-#else
-# define machine_is_haba_knx_explorer()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SIMTEC_KIRKMOD
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SIMTEC_KIRKMOD
-# endif
-# define machine_is_simtec_kirkmod()	(machine_arch_type == MACH_TYPE_SIMTEC_KIRKMOD)
-#else
-# define machine_is_simtec_kirkmod()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CRUX
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CRUX
-# endif
-# define machine_is_crux()	(machine_arch_type == MACH_TYPE_CRUX)
-#else
-# define machine_is_crux()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MX51_BRAVO
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MX51_BRAVO
-# endif
-# define machine_is_mx51_bravo()	(machine_arch_type == MACH_TYPE_MX51_BRAVO)
-#else
-# define machine_is_mx51_bravo()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CHARON
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CHARON
-# endif
-# define machine_is_charon()	(machine_arch_type == MACH_TYPE_CHARON)
-#else
-# define machine_is_charon()	(0)
-#endif
-
-#ifdef CONFIG_MACH_PICOCOM3
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PICOCOM3
-# endif
-# define machine_is_picocom3()	(machine_arch_type == MACH_TYPE_PICOCOM3)
-#else
-# define machine_is_picocom3()	(0)
-#endif
-
-#ifdef CONFIG_MACH_PICOCOM4
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PICOCOM4
-# endif
-# define machine_is_picocom4()	(machine_arch_type == MACH_TYPE_PICOCOM4)
-#else
-# define machine_is_picocom4()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SERRANO
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SERRANO
-# endif
-# define machine_is_serrano()	(machine_arch_type == MACH_TYPE_SERRANO)
-#else
-# define machine_is_serrano()	(0)
-#endif
-
-#ifdef CONFIG_MACH_DOUBLESHOT
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_DOUBLESHOT
-# endif
-# define machine_is_doubleshot()	(machine_arch_type == MACH_TYPE_DOUBLESHOT)
-#else
-# define machine_is_doubleshot()	(0)
-#endif
-
-#ifdef CONFIG_MACH_EVSY
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_EVSY
-# endif
-# define machine_is_evsy()	(machine_arch_type == MACH_TYPE_EVSY)
-#else
-# define machine_is_evsy()	(0)
-#endif
-
-#ifdef CONFIG_MACH_HUASHAN
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_HUASHAN
-# endif
-# define machine_is_huashan()	(machine_arch_type == MACH_TYPE_HUASHAN)
-#else
-# define machine_is_huashan()	(0)
-#endif
-
-#ifdef CONFIG_MACH_LAUSANNE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_LAUSANNE
-# endif
-# define machine_is_lausanne()	(machine_arch_type == MACH_TYPE_LAUSANNE)
-#else
-# define machine_is_lausanne()	(0)
-#endif
-
-#ifdef CONFIG_MACH_EMERALD
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_EMERALD
-# endif
-# define machine_is_emerald()	(machine_arch_type == MACH_TYPE_EMERALD)
-#else
-# define machine_is_emerald()	(0)
-#endif
-
-#ifdef CONFIG_MACH_TQMA35
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TQMA35
-# endif
-# define machine_is_tqma35()	(machine_arch_type == MACH_TYPE_TQMA35)
-#else
-# define machine_is_tqma35()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MARVEL
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MARVEL
-# endif
-# define machine_is_marvel()	(machine_arch_type == MACH_TYPE_MARVEL)
-#else
-# define machine_is_marvel()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MANUAE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MANUAE
-# endif
-# define machine_is_manuae()	(machine_arch_type == MACH_TYPE_MANUAE)
-#else
-# define machine_is_manuae()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CHACHA
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CHACHA
-# endif
-# define machine_is_chacha()	(machine_arch_type == MACH_TYPE_CHACHA)
-#else
-# define machine_is_chacha()	(0)
-#endif
-
-#ifdef CONFIG_MACH_LEMON
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_LEMON
-# endif
-# define machine_is_lemon()	(machine_arch_type == MACH_TYPE_LEMON)
-#else
-# define machine_is_lemon()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CSC
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CSC
-# endif
-# define machine_is_csc()	(machine_arch_type == MACH_TYPE_CSC)
-#else
-# define machine_is_csc()	(0)
-#endif
-
-#ifdef CONFIG_MACH_GIRA_KNXIP_ROUTER
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_GIRA_KNXIP_ROUTER
-# endif
-# define machine_is_gira_knxip_router()	(machine_arch_type == MACH_TYPE_GIRA_KNXIP_ROUTER)
-#else
-# define machine_is_gira_knxip_router()	(0)
-#endif
-
-#ifdef CONFIG_MACH_T20
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_T20
-# endif
-# define machine_is_t20()	(machine_arch_type == MACH_TYPE_T20)
-#else
-# define machine_is_t20()	(0)
-#endif
-
-#ifdef CONFIG_MACH_HDMINI
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_HDMINI
-# endif
-# define machine_is_hdmini()	(machine_arch_type == MACH_TYPE_HDMINI)
-#else
-# define machine_is_hdmini()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SCIPHONE_G2
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SCIPHONE_G2
-# endif
-# define machine_is_sciphone_g2()	(machine_arch_type == MACH_TYPE_SCIPHONE_G2)
-#else
-# define machine_is_sciphone_g2()	(0)
-#endif
-
-#ifdef CONFIG_MACH_EXPRESS
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_EXPRESS
-# endif
-# define machine_is_express()	(machine_arch_type == MACH_TYPE_EXPRESS)
-#else
-# define machine_is_express()	(0)
-#endif
-
-#ifdef CONFIG_MACH_EXPRESS_KT
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_EXPRESS_KT
-# endif
-# define machine_is_express_kt()	(machine_arch_type == MACH_TYPE_EXPRESS_KT)
-#else
-# define machine_is_express_kt()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MAXIMASP
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MAXIMASP
-# endif
-# define machine_is_maximasp()	(machine_arch_type == MACH_TYPE_MAXIMASP)
-#else
-# define machine_is_maximasp()	(0)
-#endif
-
-#ifdef CONFIG_MACH_NITROGEN_IMX51
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_NITROGEN_IMX51
-# endif
-# define machine_is_nitrogen_imx51()	(machine_arch_type == MACH_TYPE_NITROGEN_IMX51)
-#else
-# define machine_is_nitrogen_imx51()	(0)
-#endif
-
-#ifdef CONFIG_MACH_NITROGEN_IMX53
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_NITROGEN_IMX53
-# endif
-# define machine_is_nitrogen_imx53()	(machine_arch_type == MACH_TYPE_NITROGEN_IMX53)
-#else
-# define machine_is_nitrogen_imx53()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SUNFIRE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SUNFIRE
-# endif
-# define machine_is_sunfire()	(machine_arch_type == MACH_TYPE_SUNFIRE)
-#else
-# define machine_is_sunfire()	(0)
-#endif
-
-#ifdef CONFIG_MACH_AROWANA
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_AROWANA
-# endif
-# define machine_is_arowana()	(machine_arch_type == MACH_TYPE_AROWANA)
-#else
-# define machine_is_arowana()	(0)
-#endif
-
-#ifdef CONFIG_MACH_TEGRA_DAYTONA
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TEGRA_DAYTONA
-# endif
-# define machine_is_tegra_daytona()	(machine_arch_type == MACH_TYPE_TEGRA_DAYTONA)
-#else
-# define machine_is_tegra_daytona()	(0)
-#endif
-
-#ifdef CONFIG_MACH_TEGRA_SWORDFISH
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TEGRA_SWORDFISH
-# endif
-# define machine_is_tegra_swordfish()	(machine_arch_type == MACH_TYPE_TEGRA_SWORDFISH)
-#else
-# define machine_is_tegra_swordfish()	(0)
-#endif
-
-#ifdef CONFIG_MACH_EDISON
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_EDISON
-# endif
-# define machine_is_edison()	(machine_arch_type == MACH_TYPE_EDISON)
-#else
-# define machine_is_edison()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SVP8500V1
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SVP8500V1
-# endif
-# define machine_is_svp8500v1()	(machine_arch_type == MACH_TYPE_SVP8500V1)
-#else
-# define machine_is_svp8500v1()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SVP8500V2
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SVP8500V2
-# endif
-# define machine_is_svp8500v2()	(machine_arch_type == MACH_TYPE_SVP8500V2)
-#else
-# define machine_is_svp8500v2()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SVP5500
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SVP5500
-# endif
-# define machine_is_svp5500()	(machine_arch_type == MACH_TYPE_SVP5500)
-#else
-# define machine_is_svp5500()	(0)
-#endif
-
-#ifdef CONFIG_MACH_B5500
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_B5500
-# endif
-# define machine_is_b5500()	(machine_arch_type == MACH_TYPE_B5500)
-#else
-# define machine_is_b5500()	(0)
-#endif
-
-#ifdef CONFIG_MACH_S5500
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_S5500
-# endif
-# define machine_is_s5500()	(machine_arch_type == MACH_TYPE_S5500)
-#else
-# define machine_is_s5500()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ICON
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ICON
-# endif
-# define machine_is_icon()	(machine_arch_type == MACH_TYPE_ICON)
-#else
-# define machine_is_icon()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ELEPHANT
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ELEPHANT
-# endif
-# define machine_is_elephant()	(machine_arch_type == MACH_TYPE_ELEPHANT)
-#else
-# define machine_is_elephant()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MSM8X60_FUSION
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MSM8X60_FUSION
-# endif
-# define machine_is_msm8x60_fusion()	(machine_arch_type == MACH_TYPE_MSM8X60_FUSION)
-#else
-# define machine_is_msm8x60_fusion()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SHOOTER
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SHOOTER
-# endif
-# define machine_is_shooter()	(machine_arch_type == MACH_TYPE_SHOOTER)
-#else
-# define machine_is_shooter()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SPADE_LTE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SPADE_LTE
-# endif
-# define machine_is_spade_lte()	(machine_arch_type == MACH_TYPE_SPADE_LTE)
-#else
-# define machine_is_spade_lte()	(0)
-#endif
-
-#ifdef CONFIG_MACH_PHILHWANI
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PHILHWANI
-# endif
-# define machine_is_philhwani()	(machine_arch_type == MACH_TYPE_PHILHWANI)
-#else
-# define machine_is_philhwani()	(0)
-#endif
-
-#ifdef CONFIG_MACH_GSNCOMM
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_GSNCOMM
-# endif
-# define machine_is_gsncomm()	(machine_arch_type == MACH_TYPE_GSNCOMM)
-#else
-# define machine_is_gsncomm()	(0)
-#endif
-
-#ifdef CONFIG_MACH_STRASBOURG_A2
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_STRASBOURG_A2
-# endif
-# define machine_is_strasbourg_a2()	(machine_arch_type == MACH_TYPE_STRASBOURG_A2)
-#else
-# define machine_is_strasbourg_a2()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MMM
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MMM
-# endif
-# define machine_is_mmm()	(machine_arch_type == MACH_TYPE_MMM)
-#else
-# define machine_is_mmm()	(0)
-#endif
-
-#ifdef CONFIG_MACH_DAVINCI_DM365_BV
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_DAVINCI_DM365_BV
-# endif
-# define machine_is_davinci_dm365_bv()	(machine_arch_type == MACH_TYPE_DAVINCI_DM365_BV)
-#else
-# define machine_is_davinci_dm365_bv()	(0)
-#endif
-
-#ifdef CONFIG_MACH_AG5EVM
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_AG5EVM
-# endif
-# define machine_is_ag5evm()	(machine_arch_type == MACH_TYPE_AG5EVM)
-#else
-# define machine_is_ag5evm()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SC575PLC
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SC575PLC
-# endif
-# define machine_is_sc575plc()	(machine_arch_type == MACH_TYPE_SC575PLC)
-#else
-# define machine_is_sc575plc()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SC575IPC
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SC575IPC
-# endif
-# define machine_is_sc575hmi()	(machine_arch_type == MACH_TYPE_SC575IPC)
-#else
-# define machine_is_sc575hmi()	(0)
-#endif
-
-#ifdef CONFIG_MACH_OMAP3_TDM3730
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_OMAP3_TDM3730
-# endif
-# define machine_is_omap3_tdm3730()	(machine_arch_type == MACH_TYPE_OMAP3_TDM3730)
-#else
-# define machine_is_omap3_tdm3730()	(0)
-#endif
-
-#ifdef CONFIG_MACH_G7
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_G7
-# endif
-# define machine_is_g7()	(machine_arch_type == MACH_TYPE_G7)
-#else
-# define machine_is_g7()	(0)
-#endif
-
-#ifdef CONFIG_MACH_TOP9000_EVAL
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TOP9000_EVAL
-# endif
-# define machine_is_top9000_eval()	(machine_arch_type == MACH_TYPE_TOP9000_EVAL)
-#else
-# define machine_is_top9000_eval()	(0)
-#endif
-
-#ifdef CONFIG_MACH_TOP9000_SU
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TOP9000_SU
-# endif
-# define machine_is_top9000_su()	(machine_arch_type == MACH_TYPE_TOP9000_SU)
-#else
-# define machine_is_top9000_su()	(0)
-#endif
-
-#ifdef CONFIG_MACH_UTM300
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_UTM300
-# endif
-# define machine_is_utm300()	(machine_arch_type == MACH_TYPE_UTM300)
-#else
-# define machine_is_utm300()	(0)
-#endif
-
-#ifdef CONFIG_MACH_TSUNAGI
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TSUNAGI
-# endif
-# define machine_is_tsunagi()	(machine_arch_type == MACH_TYPE_TSUNAGI)
-#else
-# define machine_is_tsunagi()	(0)
-#endif
-
-#ifdef CONFIG_MACH_TS75XX
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TS75XX
-# endif
-# define machine_is_ts75xx()	(machine_arch_type == MACH_TYPE_TS75XX)
-#else
-# define machine_is_ts75xx()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MSM8X60_FUSN_FFA
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MSM8X60_FUSN_FFA
-# endif
-# define machine_is_msm8x60_fusn_ffa()	(machine_arch_type == MACH_TYPE_MSM8X60_FUSN_FFA)
-#else
-# define machine_is_msm8x60_fusn_ffa()	(0)
-#endif
-
-#ifdef CONFIG_MACH_TS47XX
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TS47XX
-# endif
-# define machine_is_ts47xx()	(machine_arch_type == MACH_TYPE_TS47XX)
-#else
-# define machine_is_ts47xx()	(0)
-#endif
-
-#ifdef CONFIG_MACH_DA850_K5
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_DA850_K5
-# endif
-# define machine_is_da850_k5()	(machine_arch_type == MACH_TYPE_DA850_K5)
-#else
-# define machine_is_da850_k5()	(0)
-#endif
-
-#ifdef CONFIG_MACH_AX502
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_AX502
-# endif
-# define machine_is_ax502()	(machine_arch_type == MACH_TYPE_AX502)
-#else
-# define machine_is_ax502()	(0)
-#endif
-
-#ifdef CONFIG_MACH_IGEP0032
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_IGEP0032
-# endif
-# define machine_is_igep0032()	(machine_arch_type == MACH_TYPE_IGEP0032)
-#else
-# define machine_is_igep0032()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ANTERO
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ANTERO
-# endif
-# define machine_is_antero()	(machine_arch_type == MACH_TYPE_ANTERO)
-#else
-# define machine_is_antero()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SYNERGY
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SYNERGY
-# endif
-# define machine_is_synergy()	(machine_arch_type == MACH_TYPE_SYNERGY)
-#else
-# define machine_is_synergy()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ICS_IF_VOIP
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ICS_IF_VOIP
-# endif
-# define machine_is_ics_if_voip()	(machine_arch_type == MACH_TYPE_ICS_IF_VOIP)
-#else
-# define machine_is_ics_if_voip()	(0)
-#endif
-
-#ifdef CONFIG_MACH_WLF_CRAGG_6410
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_WLF_CRAGG_6410
-# endif
-# define machine_is_wlf_cragg_6410()	(machine_arch_type == MACH_TYPE_WLF_CRAGG_6410)
-#else
-# define machine_is_wlf_cragg_6410()	(0)
-#endif
-
-#ifdef CONFIG_MACH_PUNICA
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PUNICA
-# endif
-# define machine_is_punica()	(machine_arch_type == MACH_TYPE_PUNICA)
-#else
-# define machine_is_punica()	(0)
-#endif
-
-#ifdef CONFIG_MACH_TRIMSLICE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TRIMSLICE
-# endif
-# define machine_is_trimslice()	(machine_arch_type == MACH_TYPE_TRIMSLICE)
-#else
-# define machine_is_trimslice()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MX27_WMULTRA
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MX27_WMULTRA
-# endif
-# define machine_is_mx27_wmultra()	(machine_arch_type == MACH_TYPE_MX27_WMULTRA)
-#else
-# define machine_is_mx27_wmultra()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MACKEREL
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MACKEREL
-# endif
-# define machine_is_mackerel()	(machine_arch_type == MACH_TYPE_MACKEREL)
-#else
-# define machine_is_mackerel()	(0)
-#endif
-
-#ifdef CONFIG_MACH_FA9X27
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_FA9X27
-# endif
-# define machine_is_fa9x27()	(machine_arch_type == MACH_TYPE_FA9X27)
-#else
-# define machine_is_fa9x27()	(0)
-#endif
-
-#ifdef CONFIG_MACH_NS2816TB
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_NS2816TB
-# endif
-# define machine_is_ns2816tb()	(machine_arch_type == MACH_TYPE_NS2816TB)
-#else
-# define machine_is_ns2816tb()	(0)
-#endif
-
-#ifdef CONFIG_MACH_NS2816_NTPAD
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_NS2816_NTPAD
-# endif
-# define machine_is_ns2816_ntpad()	(machine_arch_type == MACH_TYPE_NS2816_NTPAD)
-#else
-# define machine_is_ns2816_ntpad()	(0)
-#endif
-
-#ifdef CONFIG_MACH_NS2816_NTNB
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_NS2816_NTNB
-# endif
-# define machine_is_ns2816_ntnb()	(machine_arch_type == MACH_TYPE_NS2816_NTNB)
-#else
-# define machine_is_ns2816_ntnb()	(0)
-#endif
-
-#ifdef CONFIG_MACH_KAEN
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_KAEN
-# endif
-# define machine_is_kaen()	(machine_arch_type == MACH_TYPE_KAEN)
-#else
-# define machine_is_kaen()	(0)
-#endif
-
-#ifdef CONFIG_MACH_NV1000
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_NV1000
-# endif
-# define machine_is_nv1000()	(machine_arch_type == MACH_TYPE_NV1000)
-#else
-# define machine_is_nv1000()	(0)
-#endif
-
-#ifdef CONFIG_MACH_NUC950TS
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_NUC950TS
-# endif
-# define machine_is_nuc950ts()	(machine_arch_type == MACH_TYPE_NUC950TS)
-#else
-# define machine_is_nuc950ts()	(0)
-#endif
-
-#ifdef CONFIG_MACH_NOKIA_RM680
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_NOKIA_RM680
-# endif
-# define machine_is_nokia_rm680()	(machine_arch_type == MACH_TYPE_NOKIA_RM680)
-#else
-# define machine_is_nokia_rm680()	(0)
-#endif
-
-#ifdef CONFIG_MACH_AST2200
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_AST2200
-# endif
-# define machine_is_ast2200()	(machine_arch_type == MACH_TYPE_AST2200)
-#else
-# define machine_is_ast2200()	(0)
-#endif
-
-#ifdef CONFIG_MACH_LEAD
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_LEAD
-# endif
-# define machine_is_lead()	(machine_arch_type == MACH_TYPE_LEAD)
-#else
-# define machine_is_lead()	(0)
-#endif
-
-#ifdef CONFIG_MACH_UNINO1
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_UNINO1
-# endif
-# define machine_is_unino1()	(machine_arch_type == MACH_TYPE_UNINO1)
-#else
-# define machine_is_unino1()	(0)
-#endif
-
-#ifdef CONFIG_MACH_GREECO
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_GREECO
-# endif
-# define machine_is_greeco()	(machine_arch_type == MACH_TYPE_GREECO)
-#else
-# define machine_is_greeco()	(0)
-#endif
-
-#ifdef CONFIG_MACH_VERDI
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_VERDI
-# endif
-# define machine_is_verdi()	(machine_arch_type == MACH_TYPE_VERDI)
-#else
-# define machine_is_verdi()	(0)
-#endif
-
-#ifdef CONFIG_MACH_DM6446_ADBOX
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_DM6446_ADBOX
-# endif
-# define machine_is_dm6446_adbox()	(machine_arch_type == MACH_TYPE_DM6446_ADBOX)
-#else
-# define machine_is_dm6446_adbox()	(0)
-#endif
-
-#ifdef CONFIG_MACH_QUAD_SALSA
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_QUAD_SALSA
-# endif
-# define machine_is_quad_salsa()	(machine_arch_type == MACH_TYPE_QUAD_SALSA)
-#else
-# define machine_is_quad_salsa()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ABB_GMA_1_1
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ABB_GMA_1_1
-# endif
-# define machine_is_abb_gma_1_1()	(machine_arch_type == MACH_TYPE_ABB_GMA_1_1)
-#else
-# define machine_is_abb_gma_1_1()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SVCID
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SVCID
-# endif
-# define machine_is_svcid()	(machine_arch_type == MACH_TYPE_SVCID)
-#else
-# define machine_is_svcid()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MSM8960_SIM
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MSM8960_SIM
-# endif
-# define machine_is_msm8960_sim()	(machine_arch_type == MACH_TYPE_MSM8960_SIM)
-#else
-# define machine_is_msm8960_sim()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MSM8960_RUMI3
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MSM8960_RUMI3
-# endif
-# define machine_is_msm8960_rumi3()	(machine_arch_type == MACH_TYPE_MSM8960_RUMI3)
-#else
-# define machine_is_msm8960_rumi3()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ICON_G
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ICON_G
-# endif
-# define machine_is_icon_g()	(machine_arch_type == MACH_TYPE_ICON_G)
-#else
-# define machine_is_icon_g()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MB3
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MB3
-# endif
-# define machine_is_mb3()	(machine_arch_type == MACH_TYPE_MB3)
-#else
-# define machine_is_mb3()	(0)
-#endif
-
-#ifdef CONFIG_MACH_GSIA18S
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_GSIA18S
-# endif
-# define machine_is_gsia18s()	(machine_arch_type == MACH_TYPE_GSIA18S)
-#else
-# define machine_is_gsia18s()	(0)
-#endif
-
-#ifdef CONFIG_MACH_PIVICC
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PIVICC
-# endif
-# define machine_is_pivicc()	(machine_arch_type == MACH_TYPE_PIVICC)
-#else
-# define machine_is_pivicc()	(0)
-#endif
-
-#ifdef CONFIG_MACH_PCM048
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PCM048
-# endif
-# define machine_is_pcm048()	(machine_arch_type == MACH_TYPE_PCM048)
-#else
-# define machine_is_pcm048()	(0)
-#endif
-
-#ifdef CONFIG_MACH_DDS
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_DDS
-# endif
-# define machine_is_dds()	(machine_arch_type == MACH_TYPE_DDS)
-#else
-# define machine_is_dds()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CHALTEN_XA1
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CHALTEN_XA1
-# endif
-# define machine_is_chalten_xa1()	(machine_arch_type == MACH_TYPE_CHALTEN_XA1)
-#else
-# define machine_is_chalten_xa1()	(0)
-#endif
-
-#ifdef CONFIG_MACH_TS48XX
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TS48XX
-# endif
-# define machine_is_ts48xx()	(machine_arch_type == MACH_TYPE_TS48XX)
-#else
-# define machine_is_ts48xx()	(0)
-#endif
-
-#ifdef CONFIG_MACH_TONGA2_TFTTIMER
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TONGA2_TFTTIMER
-# endif
-# define machine_is_tonga2_tfttimer()	(machine_arch_type == MACH_TYPE_TONGA2_TFTTIMER)
-#else
-# define machine_is_tonga2_tfttimer()	(0)
-#endif
-
-#ifdef CONFIG_MACH_WHISTLER
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_WHISTLER
-# endif
-# define machine_is_whistler()	(machine_arch_type == MACH_TYPE_WHISTLER)
-#else
-# define machine_is_whistler()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ASL_PHOENIX
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ASL_PHOENIX
-# endif
-# define machine_is_asl_phoenix()	(machine_arch_type == MACH_TYPE_ASL_PHOENIX)
-#else
-# define machine_is_asl_phoenix()	(0)
-#endif
-
-#ifdef CONFIG_MACH_AT91SAM9263OTLITE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_AT91SAM9263OTLITE
-# endif
-# define machine_is_at91sam9263otlite()	(machine_arch_type == MACH_TYPE_AT91SAM9263OTLITE)
-#else
-# define machine_is_at91sam9263otlite()	(0)
-#endif
-
-#ifdef CONFIG_MACH_DDPLUG
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_DDPLUG
-# endif
-# define machine_is_ddplug()	(machine_arch_type == MACH_TYPE_DDPLUG)
-#else
-# define machine_is_ddplug()	(0)
-#endif
-
-#ifdef CONFIG_MACH_D2PLUG
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_D2PLUG
-# endif
-# define machine_is_d2plug()	(machine_arch_type == MACH_TYPE_D2PLUG)
-#else
-# define machine_is_d2plug()	(0)
-#endif
-
-#ifdef CONFIG_MACH_KZM9D
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_KZM9D
-# endif
-# define machine_is_kzm9d()	(machine_arch_type == MACH_TYPE_KZM9D)
-#else
-# define machine_is_kzm9d()	(0)
-#endif
-
-#ifdef CONFIG_MACH_VERDI_LTE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_VERDI_LTE
-# endif
-# define machine_is_verdi_lte()	(machine_arch_type == MACH_TYPE_VERDI_LTE)
-#else
-# define machine_is_verdi_lte()	(0)
-#endif
-
-#ifdef CONFIG_MACH_NANOZOOM
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_NANOZOOM
-# endif
-# define machine_is_nanozoom()	(machine_arch_type == MACH_TYPE_NANOZOOM)
-#else
-# define machine_is_nanozoom()	(0)
-#endif
-
-#ifdef CONFIG_MACH_DM3730_SOM_LV
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_DM3730_SOM_LV
-# endif
-# define machine_is_dm3730_som_lv()	(machine_arch_type == MACH_TYPE_DM3730_SOM_LV)
-#else
-# define machine_is_dm3730_som_lv()	(0)
-#endif
-
-#ifdef CONFIG_MACH_DM3730_TORPEDO
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_DM3730_TORPEDO
-# endif
-# define machine_is_dm3730_torpedo()	(machine_arch_type == MACH_TYPE_DM3730_TORPEDO)
-#else
-# define machine_is_dm3730_torpedo()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ANCHOVY
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ANCHOVY
-# endif
-# define machine_is_anchovy()	(machine_arch_type == MACH_TYPE_ANCHOVY)
-#else
-# define machine_is_anchovy()	(0)
-#endif
-
-#ifdef CONFIG_MACH_RE2REV20
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_RE2REV20
-# endif
-# define machine_is_re2rev20()	(machine_arch_type == MACH_TYPE_RE2REV20)
-#else
-# define machine_is_re2rev20()	(0)
-#endif
-
-#ifdef CONFIG_MACH_RE2REV21
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_RE2REV21
-# endif
-# define machine_is_re2rev21()	(machine_arch_type == MACH_TYPE_RE2REV21)
-#else
-# define machine_is_re2rev21()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CNS21XX
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CNS21XX
-# endif
-# define machine_is_cns21xx()	(machine_arch_type == MACH_TYPE_CNS21XX)
-#else
-# define machine_is_cns21xx()	(0)
-#endif
-
-#ifdef CONFIG_MACH_RIDER
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_RIDER
-# endif
-# define machine_is_rider()	(machine_arch_type == MACH_TYPE_RIDER)
-#else
-# define machine_is_rider()	(0)
-#endif
-
-#ifdef CONFIG_MACH_NSK330
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_NSK330
-# endif
-# define machine_is_nsk330()	(machine_arch_type == MACH_TYPE_NSK330)
-#else
-# define machine_is_nsk330()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CNS2133EVB
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CNS2133EVB
-# endif
-# define machine_is_cns2133evb()	(machine_arch_type == MACH_TYPE_CNS2133EVB)
-#else
-# define machine_is_cns2133evb()	(0)
-#endif
-
-#ifdef CONFIG_MACH_Z3_816X_MOD
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_Z3_816X_MOD
-# endif
-# define machine_is_z3_816x_mod()	(machine_arch_type == MACH_TYPE_Z3_816X_MOD)
-#else
-# define machine_is_z3_816x_mod()	(0)
-#endif
-
-#ifdef CONFIG_MACH_Z3_814X_MOD
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_Z3_814X_MOD
-# endif
-# define machine_is_z3_814x_mod()	(machine_arch_type == MACH_TYPE_Z3_814X_MOD)
-#else
-# define machine_is_z3_814x_mod()	(0)
-#endif
-
-#ifdef CONFIG_MACH_BEECT
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_BEECT
-# endif
-# define machine_is_beect()	(machine_arch_type == MACH_TYPE_BEECT)
-#else
-# define machine_is_beect()	(0)
-#endif
-
-#ifdef CONFIG_MACH_DMA_THUNDERBUG
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_DMA_THUNDERBUG
-# endif
-# define machine_is_dma_thunderbug()	(machine_arch_type == MACH_TYPE_DMA_THUNDERBUG)
-#else
-# define machine_is_dma_thunderbug()	(0)
-#endif
-
-#ifdef CONFIG_MACH_OMN_AT91SAM9G20
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_OMN_AT91SAM9G20
-# endif
-# define machine_is_omn_at91sam9g20()	(machine_arch_type == MACH_TYPE_OMN_AT91SAM9G20)
-#else
-# define machine_is_omn_at91sam9g20()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MX25_E2S_UC
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MX25_E2S_UC
-# endif
-# define machine_is_mx25_e2s_uc()	(machine_arch_type == MACH_TYPE_MX25_E2S_UC)
-#else
-# define machine_is_mx25_e2s_uc()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MIONE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MIONE
-# endif
-# define machine_is_mione()	(machine_arch_type == MACH_TYPE_MIONE)
-#else
-# define machine_is_mione()	(0)
-#endif
-
-#ifdef CONFIG_MACH_TOP9000_TCU
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TOP9000_TCU
-# endif
-# define machine_is_top9000_tcu()	(machine_arch_type == MACH_TYPE_TOP9000_TCU)
-#else
-# define machine_is_top9000_tcu()	(0)
-#endif
-
-#ifdef CONFIG_MACH_TOP9000_BSL
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TOP9000_BSL
-# endif
-# define machine_is_top9000_bsl()	(machine_arch_type == MACH_TYPE_TOP9000_BSL)
-#else
-# define machine_is_top9000_bsl()	(0)
-#endif
-
-#ifdef CONFIG_MACH_KINGDOM
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_KINGDOM
-# endif
-# define machine_is_kingdom()	(machine_arch_type == MACH_TYPE_KINGDOM)
-#else
-# define machine_is_kingdom()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ARMADILLO460
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ARMADILLO460
-# endif
-# define machine_is_armadillo460()	(machine_arch_type == MACH_TYPE_ARMADILLO460)
-#else
-# define machine_is_armadillo460()	(0)
-#endif
-
-#ifdef CONFIG_MACH_LQ2
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_LQ2
-# endif
-# define machine_is_lq2()	(machine_arch_type == MACH_TYPE_LQ2)
-#else
-# define machine_is_lq2()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SWEDA_TMS2
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SWEDA_TMS2
-# endif
-# define machine_is_sweda_tms2()	(machine_arch_type == MACH_TYPE_SWEDA_TMS2)
-#else
-# define machine_is_sweda_tms2()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MX53_LOCO
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MX53_LOCO
-# endif
-# define machine_is_mx53_loco()	(machine_arch_type == MACH_TYPE_MX53_LOCO)
-#else
-# define machine_is_mx53_loco()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ACER_A8
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ACER_A8
-# endif
-# define machine_is_acer_a8()	(machine_arch_type == MACH_TYPE_ACER_A8)
-#else
-# define machine_is_acer_a8()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ACER_GAUGUIN
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ACER_GAUGUIN
-# endif
-# define machine_is_acer_gauguin()	(machine_arch_type == MACH_TYPE_ACER_GAUGUIN)
-#else
-# define machine_is_acer_gauguin()	(0)
-#endif
-
-#ifdef CONFIG_MACH_GUPPY
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_GUPPY
-# endif
-# define machine_is_guppy()	(machine_arch_type == MACH_TYPE_GUPPY)
-#else
-# define machine_is_guppy()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MX61_ARD
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MX61_ARD
-# endif
-# define machine_is_mx61_ard()	(machine_arch_type == MACH_TYPE_MX61_ARD)
-#else
-# define machine_is_mx61_ard()	(0)
-#endif
-
-#ifdef CONFIG_MACH_TX53
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TX53
-# endif
-# define machine_is_tx53()	(machine_arch_type == MACH_TYPE_TX53)
-#else
-# define machine_is_tx53()	(0)
-#endif
-
-#ifdef CONFIG_MACH_OMAPL138_CASE_A3
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_OMAPL138_CASE_A3
-# endif
-# define machine_is_omapl138_case_a3()	(machine_arch_type == MACH_TYPE_OMAPL138_CASE_A3)
-#else
-# define machine_is_omapl138_case_a3()	(0)
-#endif
-
-#ifdef CONFIG_MACH_UEMD
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_UEMD
-# endif
-# define machine_is_uemd()	(machine_arch_type == MACH_TYPE_UEMD)
-#else
-# define machine_is_uemd()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CCWMX51MUT
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CCWMX51MUT
-# endif
-# define machine_is_ccwmx51mut()	(machine_arch_type == MACH_TYPE_CCWMX51MUT)
-#else
-# define machine_is_ccwmx51mut()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ROCKHOPPER
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ROCKHOPPER
-# endif
-# define machine_is_rockhopper()	(machine_arch_type == MACH_TYPE_ROCKHOPPER)
-#else
-# define machine_is_rockhopper()	(0)
-#endif
-
-#ifdef CONFIG_MACH_NOOKCOLOR
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_NOOKCOLOR
-# endif
-# define machine_is_nookcolor()	(machine_arch_type == MACH_TYPE_NOOKCOLOR)
-#else
-# define machine_is_nookcolor()	(0)
-#endif
-
-#ifdef CONFIG_MACH_HKDKC100
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_HKDKC100
-# endif
-# define machine_is_hkdkc100()	(machine_arch_type == MACH_TYPE_HKDKC100)
-#else
-# define machine_is_hkdkc100()	(0)
-#endif
-
-#ifdef CONFIG_MACH_TS42XX
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TS42XX
-# endif
-# define machine_is_ts42xx()	(machine_arch_type == MACH_TYPE_TS42XX)
-#else
-# define machine_is_ts42xx()	(0)
-#endif
-
-#ifdef CONFIG_MACH_AEBL
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_AEBL
-# endif
-# define machine_is_aebl()	(machine_arch_type == MACH_TYPE_AEBL)
-#else
-# define machine_is_aebl()	(0)
-#endif
-
-#ifdef CONFIG_MACH_WARIO
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_WARIO
-# endif
-# define machine_is_wario()	(machine_arch_type == MACH_TYPE_WARIO)
-#else
-# define machine_is_wario()	(0)
-#endif
-
-#ifdef CONFIG_MACH_GFS_SPM
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_GFS_SPM
-# endif
-# define machine_is_gfs_spm()	(machine_arch_type == MACH_TYPE_GFS_SPM)
-#else
-# define machine_is_gfs_spm()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CM_T3730
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CM_T3730
-# endif
-# define machine_is_cm_t3730()	(machine_arch_type == MACH_TYPE_CM_T3730)
-#else
-# define machine_is_cm_t3730()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ISC3
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ISC3
-# endif
-# define machine_is_isc3()	(machine_arch_type == MACH_TYPE_ISC3)
-#else
-# define machine_is_isc3()	(0)
-#endif
-
-#ifdef CONFIG_MACH_RASCAL
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_RASCAL
-# endif
-# define machine_is_rascal()	(machine_arch_type == MACH_TYPE_RASCAL)
-#else
-# define machine_is_rascal()	(0)
-#endif
-
-#ifdef CONFIG_MACH_HREFV60
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_HREFV60
-# endif
-# define machine_is_hrefv60()	(machine_arch_type == MACH_TYPE_HREFV60)
-#else
-# define machine_is_hrefv60()	(0)
-#endif
-
-#ifdef CONFIG_MACH_TPT_2_0
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TPT_2_0
-# endif
-# define machine_is_tpt_2_0()	(machine_arch_type == MACH_TYPE_TPT_2_0)
-#else
-# define machine_is_tpt_2_0()	(0)
-#endif
-
-#ifdef CONFIG_MACH_PYRAMID_TD
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PYRAMID_TD
-# endif
-# define machine_is_pyramid_td()	(machine_arch_type == MACH_TYPE_PYRAMID_TD)
-#else
-# define machine_is_pyramid_td()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SPLENDOR
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SPLENDOR
-# endif
-# define machine_is_splendor()	(machine_arch_type == MACH_TYPE_SPLENDOR)
-#else
-# define machine_is_splendor()	(0)
-#endif
-
-#ifdef CONFIG_MACH_GUF_PLANET
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_GUF_PLANET
-# endif
-# define machine_is_guf_planet()	(machine_arch_type == MACH_TYPE_GUF_PLANET)
-#else
-# define machine_is_guf_planet()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MSM8X60_QT
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MSM8X60_QT
-# endif
-# define machine_is_msm8x60_qt()	(machine_arch_type == MACH_TYPE_MSM8X60_QT)
-#else
-# define machine_is_msm8x60_qt()	(0)
-#endif
-
-#ifdef CONFIG_MACH_HTC_HD_MINI
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_HTC_HD_MINI
-# endif
-# define machine_is_htc_hd_mini()	(machine_arch_type == MACH_TYPE_HTC_HD_MINI)
-#else
-# define machine_is_htc_hd_mini()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ATHENE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ATHENE
-# endif
-# define machine_is_athene()	(machine_arch_type == MACH_TYPE_ATHENE)
-#else
-# define machine_is_athene()	(0)
-#endif
-
-#ifdef CONFIG_MACH_DEEP_R_EK_1
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_DEEP_R_EK_1
-# endif
-# define machine_is_deep_r_ek_1()	(machine_arch_type == MACH_TYPE_DEEP_R_EK_1)
-#else
-# define machine_is_deep_r_ek_1()	(0)
-#endif
-
-#ifdef CONFIG_MACH_VIVOW_CT
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_VIVOW_CT
-# endif
-# define machine_is_vivow_ct()	(machine_arch_type == MACH_TYPE_VIVOW_CT)
-#else
-# define machine_is_vivow_ct()	(0)
-#endif
-
-#ifdef CONFIG_MACH_NERY_1000
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_NERY_1000
-# endif
-# define machine_is_nery_1000()	(machine_arch_type == MACH_TYPE_NERY_1000)
-#else
-# define machine_is_nery_1000()	(0)
-#endif
-
-#ifdef CONFIG_MACH_RFL109145_SSRV
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_RFL109145_SSRV
-# endif
-# define machine_is_rfl109145_ssrv()	(machine_arch_type == MACH_TYPE_RFL109145_SSRV)
-#else
-# define machine_is_rfl109145_ssrv()	(0)
-#endif
-
-#ifdef CONFIG_MACH_NMH
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_NMH
-# endif
-# define machine_is_nmh()	(machine_arch_type == MACH_TYPE_NMH)
-#else
-# define machine_is_nmh()	(0)
-#endif
-
-#ifdef CONFIG_MACH_WN802T
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_WN802T
-# endif
-# define machine_is_wn802t()	(machine_arch_type == MACH_TYPE_WN802T)
-#else
-# define machine_is_wn802t()	(0)
-#endif
-
-#ifdef CONFIG_MACH_DRAGONET
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_DRAGONET
-# endif
-# define machine_is_dragonet()	(machine_arch_type == MACH_TYPE_DRAGONET)
-#else
-# define machine_is_dragonet()	(0)
-#endif
-
-#ifdef CONFIG_MACH_GENEVA_B
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_GENEVA_B
-# endif
-# define machine_is_geneva_b()	(machine_arch_type == MACH_TYPE_GENEVA_B)
-#else
-# define machine_is_geneva_b()	(0)
-#endif
-
-#ifdef CONFIG_MACH_AT91SAM9263DESK16L
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_AT91SAM9263DESK16L
-# endif
-# define machine_is_at91sam9263desk16l()	(machine_arch_type == MACH_TYPE_AT91SAM9263DESK16L)
-#else
-# define machine_is_at91sam9263desk16l()	(0)
-#endif
-
-#ifdef CONFIG_MACH_BCMHANA_SV
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_BCMHANA_SV
-# endif
-# define machine_is_bcmhana_sv()	(machine_arch_type == MACH_TYPE_BCMHANA_SV)
-#else
-# define machine_is_bcmhana_sv()	(0)
-#endif
-
-#ifdef CONFIG_MACH_BCMHANA_TABLET
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_BCMHANA_TABLET
-# endif
-# define machine_is_bcmhana_tablet()	(machine_arch_type == MACH_TYPE_BCMHANA_TABLET)
-#else
-# define machine_is_bcmhana_tablet()	(0)
-#endif
-
-#ifdef CONFIG_MACH_KOI
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_KOI
-# endif
-# define machine_is_koi()	(machine_arch_type == MACH_TYPE_KOI)
-#else
-# define machine_is_koi()	(0)
-#endif
-
-#ifdef CONFIG_MACH_TS4800
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TS4800
-# endif
-# define machine_is_ts4800()	(machine_arch_type == MACH_TYPE_TS4800)
-#else
-# define machine_is_ts4800()	(0)
-#endif
-
-#ifdef CONFIG_MACH_TQMA9263
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_TQMA9263
-# endif
-# define machine_is_tqma9263()	(machine_arch_type == MACH_TYPE_TQMA9263)
-#else
-# define machine_is_tqma9263()	(0)
-#endif
-
-#ifdef CONFIG_MACH_HOLIDAY
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_HOLIDAY
-# endif
-# define machine_is_holiday()	(machine_arch_type == MACH_TYPE_HOLIDAY)
-#else
-# define machine_is_holiday()	(0)
-#endif
-
-#ifdef CONFIG_MACH_DMA6410
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_DMA6410
-# endif
-# define machine_is_dma_6410()	(machine_arch_type == MACH_TYPE_DMA6410)
-#else
-# define machine_is_dma_6410()	(0)
-#endif
-
-#ifdef CONFIG_MACH_PCATS_OVERLAY
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PCATS_OVERLAY
-# endif
-# define machine_is_pcats_overlay()	(machine_arch_type == MACH_TYPE_PCATS_OVERLAY)
-#else
-# define machine_is_pcats_overlay()	(0)
-#endif
-
-#ifdef CONFIG_MACH_HWGW6410
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_HWGW6410
-# endif
-# define machine_is_hwgw6410()	(machine_arch_type == MACH_TYPE_HWGW6410)
-#else
-# define machine_is_hwgw6410()	(0)
-#endif
-
-#ifdef CONFIG_MACH_SHENZHOU
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_SHENZHOU
-# endif
-# define machine_is_shenzhou()	(machine_arch_type == MACH_TYPE_SHENZHOU)
-#else
-# define machine_is_shenzhou()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CWME9210
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CWME9210
-# endif
-# define machine_is_cwme9210()	(machine_arch_type == MACH_TYPE_CWME9210)
-#else
-# define machine_is_cwme9210()	(0)
-#endif
-
-#ifdef CONFIG_MACH_CWME9210JS
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_CWME9210JS
-# endif
-# define machine_is_cwme9210js()	(machine_arch_type == MACH_TYPE_CWME9210JS)
-#else
-# define machine_is_cwme9210js()	(0)
-#endif
-
-#ifdef CONFIG_MACH_PGS_SITARA
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_PGS_SITARA
-# endif
-# define machine_is_pgs_v1()	(machine_arch_type == MACH_TYPE_PGS_SITARA)
-#else
-# define machine_is_pgs_v1()	(0)
-#endif
-
-#ifdef CONFIG_MACH_COLIBRI_TEGRA2
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_COLIBRI_TEGRA2
-# endif
-# define machine_is_colibri_tegra2()	(machine_arch_type == MACH_TYPE_COLIBRI_TEGRA2)
-#else
-# define machine_is_colibri_tegra2()	(0)
-#endif
-
-#ifdef CONFIG_MACH_W21
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_W21
-# endif
-# define machine_is_w21()	(machine_arch_type == MACH_TYPE_W21)
-#else
-# define machine_is_w21()	(0)
-#endif
-
-#ifdef CONFIG_MACH_POLYSAT1
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_POLYSAT1
-# endif
-# define machine_is_polysat1()	(machine_arch_type == MACH_TYPE_POLYSAT1)
-#else
-# define machine_is_polysat1()	(0)
-#endif
-
-#ifdef CONFIG_MACH_DATAWAY
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_DATAWAY
-# endif
-# define machine_is_dataway()	(machine_arch_type == MACH_TYPE_DATAWAY)
-#else
-# define machine_is_dataway()	(0)
-#endif
-
-#ifdef CONFIG_MACH_COBRAL138
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_COBRAL138
-# endif
-# define machine_is_cobral138()	(machine_arch_type == MACH_TYPE_COBRAL138)
-#else
-# define machine_is_cobral138()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ROVERPCS8
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ROVERPCS8
-# endif
-# define machine_is_roverpcs8()	(machine_arch_type == MACH_TYPE_ROVERPCS8)
-#else
-# define machine_is_roverpcs8()	(0)
-#endif
-
-#ifdef CONFIG_MACH_MARVELC
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_MARVELC
-# endif
-# define machine_is_marvelc()	(machine_arch_type == MACH_TYPE_MARVELC)
-#else
-# define machine_is_marvelc()	(0)
-#endif
-
-#ifdef CONFIG_MACH_NAVEFIHID
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_NAVEFIHID
-# endif
-# define machine_is_navefihid()	(machine_arch_type == MACH_TYPE_NAVEFIHID)
-#else
-# define machine_is_navefihid()	(0)
-#endif
-
-#ifdef CONFIG_MACH_DM365_CV100
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_DM365_CV100
-# endif
-# define machine_is_dm365_cv100()	(machine_arch_type == MACH_TYPE_DM365_CV100)
-#else
-# define machine_is_dm365_cv100()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ABLE
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ABLE
-# endif
-# define machine_is_able()	(machine_arch_type == MACH_TYPE_ABLE)
-#else
-# define machine_is_able()	(0)
-#endif
-
-#ifdef CONFIG_MACH_LEGACY
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_LEGACY
-# endif
-# define machine_is_legacy()	(machine_arch_type == MACH_TYPE_LEGACY)
-#else
-# define machine_is_legacy()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ICONG
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ICONG
-# endif
-# define machine_is_icong()	(machine_arch_type == MACH_TYPE_ICONG)
-#else
-# define machine_is_icong()	(0)
-#endif
-
-#ifdef CONFIG_MACH_ROVER_G8
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_ROVER_G8
-# endif
-# define machine_is_rover_g8()	(machine_arch_type == MACH_TYPE_ROVER_G8)
-#else
-# define machine_is_rover_g8()	(0)
-#endif
-
-#ifdef CONFIG_MACH_T5388P
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_T5388P
-# endif
-# define machine_is_t5388p()	(machine_arch_type == MACH_TYPE_T5388P)
-#else
-# define machine_is_t5388p()	(0)
-#endif
-
-#ifdef CONFIG_MACH_DINGO
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_DINGO
-# endif
-# define machine_is_dingo()	(machine_arch_type == MACH_TYPE_DINGO)
-#else
-# define machine_is_dingo()	(0)
-#endif
-
-#ifdef CONFIG_MACH_GOFLEXHOME
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type	__machine_arch_type
-# else
-#  define machine_arch_type	MACH_TYPE_GOFLEXHOME
-# endif
-# define machine_is_goflexhome()	(machine_arch_type == MACH_TYPE_GOFLEXHOME)
-#else
-# define machine_is_goflexhome()	(0)
-#endif
-
-/*
- * These have not yet been registered
- */
-
-#ifndef machine_arch_type
-#define machine_arch_type	__machine_arch_type
-#endif
-
-#endif
diff --git a/arch/arm/include/asm/macro.h b/arch/arm/include/asm/macro.h
deleted file mode 100644
index 57b5260..0000000
--- a/arch/arm/include/asm/macro.h
+++ /dev/null
@@ -1,74 +0,0 @@
-/*
- * include/asm-arm/macro.h
- *
- * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __ASM_ARM_MACRO_H__
-#define __ASM_ARM_MACRO_H__
-#ifdef __ASSEMBLY__
-
-/*
- * These macros provide a convenient way to write 8, 16 and 32 bit data
- * to any address.
- * Registers r4 and r5 are used, any data in these registers are
- * overwritten by the macros.
- * The macros are valid for any ARM architecture, they do not implement
- * any memory barriers so caution is recommended when using these when the
- * caches are enabled or on a multi-core system.
- */
-
-.macro	write32, addr, data
-	ldr	r4, =\addr
-	ldr	r5, =\data
-	str	r5, [r4]
-.endm
-
-.macro	write16, addr, data
-	ldr	r4, =\addr
-	ldrh	r5, =\data
-	strh	r5, [r4]
-.endm
-
-.macro	write8, addr, data
-	ldr	r4, =\addr
-	ldrb	r5, =\data
-	strb	r5, [r4]
-.endm
-
-/*
- * This macro generates a loop that can be used for delays in the code.
- * Register r4 is used, any data in this register is overwritten by the
- * macro.
- * The macro is valid for any ARM architeture. The actual time spent in the
- * loop will vary from CPU to CPU though.
- */
-
-.macro	wait_timer, time
-	ldr	r4, =\time
-1:
-	nop
-	subs	r4, r4, #1
-	bcs	1b
-.endm
-
-#endif /* __ASSEMBLY__ */
-#endif /* __ASM_ARM_MACRO_H__ */
diff --git a/arch/arm/include/asm/memory.h b/arch/arm/include/asm/memory.h
deleted file mode 100644
index c3b2afd..0000000
--- a/arch/arm/include/asm/memory.h
+++ /dev/null
@@ -1,137 +0,0 @@
-/*
- *  linux/include/asm-arm/memory.h
- *
- *  Copyright (C) 2000-2002 Russell King
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- *  Note: this file should not be included by non-asm/.h files
- */
-#ifndef __ASM_ARM_MEMORY_H
-#define __ASM_ARM_MEMORY_H
-
-#if 0	/* XXX###XXX */
-
-#include <linux/config.h>
-#include <asm/arch/memory.h>
-
-/*
- * PFNs are used to describe any physical page; this means
- * PFN 0 == physical address 0.
- *
- * This is the PFN of the first RAM page in the kernel
- * direct-mapped view.  We assume this is the first page
- * of RAM in the mem_map as well.
- */
-#define PHYS_PFN_OFFSET	(PHYS_OFFSET >> PAGE_SHIFT)
-
-/*
- * These are *only* valid on the kernel direct mapped RAM memory.
- */
-static inline unsigned long virt_to_phys(void *x)
-{
-	return __virt_to_phys((unsigned long)(x));
-}
-
-static inline void *phys_to_virt(unsigned long x)
-{
-	return (void *)(__phys_to_virt((unsigned long)(x)));
-}
-
-#define __pa(x)			__virt_to_phys((unsigned long)(x))
-#define __va(x)			((void *)__phys_to_virt((unsigned long)(x)))
-
-/*
- * Virtual <-> DMA view memory address translations
- * Again, these are *only* valid on the kernel direct mapped RAM
- * memory.  Use of these is *depreciated*.
- */
-#define virt_to_bus(x)		(__virt_to_bus((unsigned long)(x)))
-#define bus_to_virt(x)		((void *)(__bus_to_virt((unsigned long)(x))))
-
-/*
- * Conversion between a struct page and a physical address.
- *
- * Note: when converting an unknown physical address to a
- * struct page, the resulting pointer must be validated
- * using VALID_PAGE().  It must return an invalid struct page
- * for any physical address not corresponding to a system
- * RAM address.
- *
- *  page_to_pfn(page)	convert a struct page * to a PFN number
- *  pfn_to_page(pfn)	convert a _valid_ PFN number to struct page *
- *  pfn_valid(pfn)	indicates whether a PFN number is valid
- *
- *  virt_to_page(k)	convert a _valid_ virtual address to struct page *
- *  virt_addr_valid(k)	indicates whether a virtual address is valid
- */
-#ifndef CONFIG_DISCONTIGMEM
-
-#define page_to_pfn(page)	(((page) - mem_map) + PHYS_PFN_OFFSET)
-#define pfn_to_page(pfn)	((mem_map + (pfn)) - PHYS_PFN_OFFSET)
-#define pfn_valid(pfn)		((pfn) >= PHYS_PFN_OFFSET && (pfn) < (PHYS_PFN_OFFSET + max_mapnr))
-
-#define virt_to_page(kaddr)	(pfn_to_page(__pa(kaddr) >> PAGE_SHIFT))
-#define virt_addr_valid(kaddr)	((kaddr) >= PAGE_OFFSET && (kaddr) < (unsigned long)high_memory)
-
-#define PHYS_TO_NID(addr)	(0)
-
-#define VALID_PAGE(page)	((page - mem_map) < max_mapnr)
-
-#else
-
-/*
- * This is more complex.  We have a set of mem_map arrays spread
- * around in memory.
- */
-#define page_to_pfn(page)					\
-	(((page) - page_zone(page)->zone_mem_map)		\
-	  + (page_zone(page)->zone_start_paddr >> PAGE_SHIFT))
-
-#define pfn_to_page(pfn)					\
-	(PFN_TO_MAPBASE(pfn) + LOCAL_MAP_NR((pfn) << PAGE_SHIFT))
-
-#define pfn_valid(pfn)						\
-  ({								\
-	unsigned int node = PFN_TO_NID(pfn);			\
-	struct pglist_data *nd = NODE_DATA(node);		\
-	((node < NR_NODES) &&					\
-	 ((pfn - (nd->node_start_paddr >> PAGE_SHIFT)) < nd->node_size));\
-   })
-
-#define virt_to_page(kaddr)					\
-	(ADDR_TO_MAPBASE(kaddr) + LOCAL_MAP_NR(kaddr))
-
-#define virt_addr_valid(kaddr)	(KVADDR_TO_NID(kaddr) < NR_NODES)
-
-/*
- * Common discontigmem stuff.
- *  PHYS_TO_NID is used by the ARM kernel/setup.c
- */
-#define PHYS_TO_NID(addr)	PFN_TO_NID((addr) >> PAGE_SHIFT)
-
-/*
- * 2.4 compatibility
- *
- * VALID_PAGE returns a non-zero value if given page pointer is valid.
- * This assumes all node's mem_maps are stored within the node they
- * refer to.  This is actually inherently buggy.
- */
-#define VALID_PAGE(page) \
-({ unsigned int node = KVADDR_TO_NID(page); \
-   ((node < NR_NODES) && \
-     ((unsigned)((page) - NODE_MEM_MAP(node)) < NODE_DATA(node)->node_size)); \
-})
-
-#endif
-
-/*
- * We should really eliminate virt_to_bus() here - it's depreciated.
- */
-#define page_to_bus(page)	(virt_to_bus(page_address(page)))
-
-#endif	/* XXX###XXX */
-
-#endif	/* __ASM_ARM_MEMORY_H */
diff --git a/arch/arm/include/asm/posix_types.h b/arch/arm/include/asm/posix_types.h
deleted file mode 100644
index c412486..0000000
--- a/arch/arm/include/asm/posix_types.h
+++ /dev/null
@@ -1,79 +0,0 @@
-/*
- *  linux/include/asm-arm/posix_types.h
- *
- *  Copyright (C) 1996-1998 Russell King.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- *  Changelog:
- *   27-06-1996	RMK	Created
- */
-#ifndef __ARCH_ARM_POSIX_TYPES_H
-#define __ARCH_ARM_POSIX_TYPES_H
-
-/*
- * This file is generally used by user-level software, so you need to
- * be a little careful about namespace pollution etc.  Also, we cannot
- * assume GCC is being used.
- */
-
-typedef unsigned short		__kernel_dev_t;
-typedef unsigned long		__kernel_ino_t;
-typedef unsigned short		__kernel_mode_t;
-typedef unsigned short		__kernel_nlink_t;
-typedef long			__kernel_off_t;
-typedef int			__kernel_pid_t;
-typedef unsigned short		__kernel_ipc_pid_t;
-typedef unsigned short		__kernel_uid_t;
-typedef unsigned short		__kernel_gid_t;
-typedef unsigned int		__kernel_size_t;
-typedef int			__kernel_ssize_t;
-typedef int			__kernel_ptrdiff_t;
-typedef long			__kernel_time_t;
-typedef long			__kernel_suseconds_t;
-typedef long			__kernel_clock_t;
-typedef int			__kernel_daddr_t;
-typedef char *			__kernel_caddr_t;
-typedef unsigned short		__kernel_uid16_t;
-typedef unsigned short		__kernel_gid16_t;
-typedef unsigned int		__kernel_uid32_t;
-typedef unsigned int		__kernel_gid32_t;
-
-typedef unsigned short		__kernel_old_uid_t;
-typedef unsigned short		__kernel_old_gid_t;
-
-#ifdef __GNUC__
-typedef long long		__kernel_loff_t;
-#endif
-
-typedef struct {
-#if defined(__KERNEL__) || defined(__USE_ALL)
-	int	val[2];
-#else /* !defined(__KERNEL__) && !defined(__USE_ALL) */
-	int	__val[2];
-#endif /* !defined(__KERNEL__) && !defined(__USE_ALL) */
-} __kernel_fsid_t;
-
-#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2)
-
-#undef	__FD_SET
-#define __FD_SET(fd, fdsetp) \
-		(((fd_set *)fdsetp)->fds_bits[fd >> 5] |= (1<<(fd & 31)))
-
-#undef	__FD_CLR
-#define __FD_CLR(fd, fdsetp) \
-		(((fd_set *)fdsetp)->fds_bits[fd >> 5] &= ~(1<<(fd & 31)))
-
-#undef	__FD_ISSET
-#define __FD_ISSET(fd, fdsetp) \
-		((((fd_set *)fdsetp)->fds_bits[fd >> 5] & (1<<(fd & 31))) != 0)
-
-#undef	__FD_ZERO
-#define __FD_ZERO(fdsetp) \
-		(memset (fdsetp, 0, sizeof (*(fd_set *)fdsetp)))
-
-#endif
-
-#endif
diff --git a/arch/arm/include/asm/proc-armv/domain.h b/arch/arm/include/asm/proc-armv/domain.h
deleted file mode 100644
index aadc831..0000000
--- a/arch/arm/include/asm/proc-armv/domain.h
+++ /dev/null
@@ -1,50 +0,0 @@
-/*
- *  linux/include/asm-arm/proc-armv/domain.h
- *
- *  Copyright (C) 1999 Russell King.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#ifndef __ASM_PROC_DOMAIN_H
-#define __ASM_PROC_DOMAIN_H
-
-/*
- * Domain numbers
- *
- *  DOMAIN_IO     - domain 2 includes all IO only
- *  DOMAIN_KERNEL - domain 1 includes all kernel memory only
- *  DOMAIN_USER   - domain 0 includes all user memory only
- */
-#define DOMAIN_USER	0
-#define DOMAIN_KERNEL	1
-#define DOMAIN_TABLE	1
-#define DOMAIN_IO	2
-
-/*
- * Domain types
- */
-#define DOMAIN_NOACCESS	0
-#define DOMAIN_CLIENT	1
-#define DOMAIN_MANAGER	3
-
-#define domain_val(dom,type)	((type) << 2*(dom))
-
-#define set_domain(x)					\
-	do {						\
-	__asm__ __volatile__(				\
-	"mcr	p15, 0, %0, c3, c0	@ set domain"	\
-	  : : "r" (x));					\
-	} while (0)
-
-#define modify_domain(dom,type)				\
-	do {						\
-	unsigned int domain = current->thread.domain;	\
-	domain &= ~domain_val(dom, DOMAIN_MANAGER);	\
-	domain |= domain_val(dom, type);		\
-	current->thread.domain = domain;		\
-	set_domain(current->thread.domain);		\
-	} while (0)
-
-#endif
diff --git a/arch/arm/include/asm/proc-armv/processor.h b/arch/arm/include/asm/proc-armv/processor.h
deleted file mode 100644
index 5bfab7f..0000000
--- a/arch/arm/include/asm/proc-armv/processor.h
+++ /dev/null
@@ -1,74 +0,0 @@
-/*
- *  linux/include/asm-arm/proc-armv/processor.h
- *
- *  Copyright (C) 1996-1999 Russell King.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- *  Changelog:
- *   20-09-1996	RMK	Created
- *   26-09-1996	RMK	Added 'EXTRA_THREAD_STRUCT*'
- *   28-09-1996	RMK	Moved start_thread into the processor dependencies
- *   09-09-1998	PJB	Delete redundant `wp_works_ok'
- *   30-05-1999	PJB	Save sl across context switches
- *   31-07-1999	RMK	Added 'domain' stuff
- */
-#ifndef __ASM_PROC_PROCESSOR_H
-#define __ASM_PROC_PROCESSOR_H
-
-#include <asm/proc/domain.h>
-
-#define KERNEL_STACK_SIZE	PAGE_SIZE
-
-struct context_save_struct {
-	unsigned long cpsr;
-	unsigned long r4;
-	unsigned long r5;
-	unsigned long r6;
-	unsigned long r7;
-	unsigned long r8;
-	unsigned long r9;
-	unsigned long sl;
-	unsigned long fp;
-	unsigned long pc;
-};
-
-#define INIT_CSS (struct context_save_struct){ SVC_MODE, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
-
-#define EXTRA_THREAD_STRUCT						\
-	unsigned int	domain;
-
-#define EXTRA_THREAD_STRUCT_INIT					\
-	domain:	  domain_val(DOMAIN_USER, DOMAIN_CLIENT) |		\
-		  domain_val(DOMAIN_KERNEL, DOMAIN_MANAGER) |		\
-		  domain_val(DOMAIN_IO, DOMAIN_CLIENT)
-
-#define start_thread(regs,pc,sp)					\
-({									\
-	unsigned long *stack = (unsigned long *)sp;			\
-	set_fs(USER_DS);						\
-	memzero(regs->uregs, sizeof(regs->uregs));			\
-	if (current->personality & ADDR_LIMIT_32BIT)			\
-		regs->ARM_cpsr = USR_MODE;				\
-	else								\
-		regs->ARM_cpsr = USR26_MODE;				\
-	regs->ARM_pc = pc;		/* pc */			\
-	regs->ARM_sp = sp;		/* sp */			\
-	regs->ARM_r2 = stack[2];	/* r2 (envp) */			\
-	regs->ARM_r1 = stack[1];	/* r1 (argv) */			\
-	regs->ARM_r0 = stack[0];	/* r0 (argc) */			\
-})
-
-#define KSTK_EIP(tsk)	(((unsigned long *)(4096+(unsigned long)(tsk)))[1019])
-#define KSTK_ESP(tsk)	(((unsigned long *)(4096+(unsigned long)(tsk)))[1017])
-
-/* Allocation and freeing of basic task resources. */
-/*
- * NOTE! The task struct and the stack go together
- */
-#define ll_alloc_task_struct() ((struct task_struct *) __get_free_pages(GFP_KERNEL,1))
-#define ll_free_task_struct(p) free_pages((unsigned long)(p),1)
-
-#endif
diff --git a/arch/arm/include/asm/proc-armv/ptrace.h b/arch/arm/include/asm/proc-armv/ptrace.h
deleted file mode 100644
index 79cc644..0000000
--- a/arch/arm/include/asm/proc-armv/ptrace.h
+++ /dev/null
@@ -1,109 +0,0 @@
-/*
- *  linux/include/asm-arm/proc-armv/ptrace.h
- *
- *  Copyright (C) 1996-1999 Russell King
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#ifndef __ASM_PROC_PTRACE_H
-#define __ASM_PROC_PTRACE_H
-
-#include <linux/config.h>
-
-#define USR26_MODE	0x00
-#define FIQ26_MODE	0x01
-#define IRQ26_MODE	0x02
-#define SVC26_MODE	0x03
-#define USR_MODE	0x10
-#define FIQ_MODE	0x11
-#define IRQ_MODE	0x12
-#define SVC_MODE	0x13
-#define ABT_MODE	0x17
-#define UND_MODE	0x1b
-#define SYSTEM_MODE	0x1f
-#define MODE_MASK	0x1f
-#define T_BIT		0x20
-#define F_BIT		0x40
-#define I_BIT		0x80
-#define CC_V_BIT	(1 << 28)
-#define CC_C_BIT	(1 << 29)
-#define CC_Z_BIT	(1 << 30)
-#define CC_N_BIT	(1 << 31)
-#define PCMASK		0
-
-#ifndef __ASSEMBLY__
-
-/* this struct defines the way the registers are stored on the
-   stack during a system call. */
-
-struct pt_regs {
-	long uregs[18];
-};
-
-#define ARM_cpsr	uregs[16]
-#define ARM_pc		uregs[15]
-#define ARM_lr		uregs[14]
-#define ARM_sp		uregs[13]
-#define ARM_ip		uregs[12]
-#define ARM_fp		uregs[11]
-#define ARM_r10		uregs[10]
-#define ARM_r9		uregs[9]
-#define ARM_r8		uregs[8]
-#define ARM_r7		uregs[7]
-#define ARM_r6		uregs[6]
-#define ARM_r5		uregs[5]
-#define ARM_r4		uregs[4]
-#define ARM_r3		uregs[3]
-#define ARM_r2		uregs[2]
-#define ARM_r1		uregs[1]
-#define ARM_r0		uregs[0]
-#define ARM_ORIG_r0	uregs[17]
-
-#ifdef __KERNEL__
-
-#define user_mode(regs)	\
-	(((regs)->ARM_cpsr & 0xf) == 0)
-
-#ifdef CONFIG_ARM_THUMB
-#define thumb_mode(regs) \
-	(((regs)->ARM_cpsr & T_BIT))
-#else
-#define thumb_mode(regs) (0)
-#endif
-
-#define processor_mode(regs) \
-	((regs)->ARM_cpsr & MODE_MASK)
-
-#define interrupts_enabled(regs) \
-	(!((regs)->ARM_cpsr & I_BIT))
-
-#define fast_interrupts_enabled(regs) \
-	(!((regs)->ARM_cpsr & F_BIT))
-
-#define condition_codes(regs) \
-	((regs)->ARM_cpsr & (CC_V_BIT|CC_C_BIT|CC_Z_BIT|CC_N_BIT))
-
-/* Are the current registers suitable for user mode?
- * (used to maintain security in signal handlers)
- */
-static inline int valid_user_regs(struct pt_regs *regs)
-{
-	if ((regs->ARM_cpsr & 0xf) == 0 &&
-	    (regs->ARM_cpsr & (F_BIT|I_BIT)) == 0)
-		return 1;
-
-	/*
-	 * Force CPSR to something logical...
-	 */
-	regs->ARM_cpsr &= (CC_V_BIT|CC_C_BIT|CC_Z_BIT|CC_N_BIT|0x10);
-
-	return 0;
-}
-
-#endif	/* __KERNEL__ */
-
-#endif	/* __ASSEMBLY__ */
-
-#endif
diff --git a/arch/arm/include/asm/proc-armv/system.h b/arch/arm/include/asm/proc-armv/system.h
deleted file mode 100644
index b4cfa68..0000000
--- a/arch/arm/include/asm/proc-armv/system.h
+++ /dev/null
@@ -1,169 +0,0 @@
-/*
- *  linux/include/asm-arm/proc-armv/system.h
- *
- *  Copyright (C) 1996 Russell King
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#ifndef __ASM_PROC_SYSTEM_H
-#define __ASM_PROC_SYSTEM_H
-
-#include <linux/config.h>
-
-/*
- * Save the current interrupt enable state & disable IRQs
- */
-#define local_irq_save(x)					\
-	({							\
-		unsigned long temp;				\
-	__asm__ __volatile__(					\
-	"mrs	%0, cpsr		@ local_irq_save\n"	\
-"	orr	%1, %0, #128\n"					\
-"	msr	cpsr_c, %1"					\
-	: "=r" (x), "=r" (temp)					\
-	:							\
-	: "memory");						\
-	})
-
-/*
- * Enable IRQs
- */
-#define local_irq_enable()					\
-	({							\
-		unsigned long temp;				\
-	__asm__ __volatile__(					\
-	"mrs	%0, cpsr		@ local_irq_enable\n"	\
-"	bic	%0, %0, #128\n"					\
-"	msr	cpsr_c, %0"					\
-	: "=r" (temp)						\
-	:							\
-	: "memory");						\
-	})
-
-/*
- * Disable IRQs
- */
-#define local_irq_disable()					\
-	({							\
-		unsigned long temp;				\
-	__asm__ __volatile__(					\
-	"mrs	%0, cpsr		@ local_irq_disable\n"	\
-"	orr	%0, %0, #128\n"					\
-"	msr	cpsr_c, %0"					\
-	: "=r" (temp)						\
-	:							\
-	: "memory");						\
-	})
-
-/*
- * Enable FIQs
- */
-#define __stf()							\
-	({							\
-		unsigned long temp;				\
-	__asm__ __volatile__(					\
-	"mrs	%0, cpsr		@ stf\n"		\
-"	bic	%0, %0, #64\n"					\
-"	msr	cpsr_c, %0"					\
-	: "=r" (temp)						\
-	:							\
-	: "memory");						\
-	})
-
-/*
- * Disable FIQs
- */
-#define __clf()							\
-	({							\
-		unsigned long temp;				\
-	__asm__ __volatile__(					\
-	"mrs	%0, cpsr		@ clf\n"		\
-"	orr	%0, %0, #64\n"					\
-"	msr	cpsr_c, %0"					\
-	: "=r" (temp)						\
-	:							\
-	: "memory");						\
-	})
-
-/*
- * Save the current interrupt enable state.
- */
-#define local_save_flags(x)					\
-	({							\
-	__asm__ __volatile__(					\
-	"mrs	%0, cpsr		@ local_save_flags\n"	\
-	  : "=r" (x)						\
-	  :							\
-	  : "memory");						\
-	})
-
-/*
- * restore saved IRQ & FIQ state
- */
-#define local_irq_restore(x)					\
-	__asm__ __volatile__(					\
-	"msr	cpsr_c, %0		@ local_irq_restore\n"	\
-	:							\
-	: "r" (x)						\
-	: "memory")
-
-#if defined(CONFIG_CPU_SA1100) || defined(CONFIG_CPU_SA110)
-/*
- * On the StrongARM, "swp" is terminally broken since it bypasses the
- * cache totally.  This means that the cache becomes inconsistent, and,
- * since we use normal loads/stores as well, this is really bad.
- * Typically, this causes oopsen in filp_close, but could have other,
- * more disasterous effects.  There are two work-arounds:
- *  1. Disable interrupts and emulate the atomic swap
- *  2. Clean the cache, perform atomic swap, flush the cache
- *
- * We choose (1) since its the "easiest" to achieve here and is not
- * dependent on the processor type.
- */
-#define swp_is_buggy
-#endif
-
-static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size)
-{
-	extern void __bad_xchg(volatile void *, int);
-	unsigned long ret;
-#ifdef swp_is_buggy
-	unsigned long flags;
-#endif
-
-	switch (size) {
-#ifdef swp_is_buggy
-		case 1:
-			local_irq_save(flags);
-			ret = *(volatile unsigned char *)ptr;
-			*(volatile unsigned char *)ptr = x;
-			local_irq_restore(flags);
-			break;
-
-		case 4:
-			local_irq_save(flags);
-			ret = *(volatile unsigned long *)ptr;
-			*(volatile unsigned long *)ptr = x;
-			local_irq_restore(flags);
-			break;
-#else
-		case 1:	__asm__ __volatile__ ("swpb %0, %1, [%2]"
-					: "=&r" (ret)
-					: "r" (x), "r" (ptr)
-					: "memory");
-			break;
-		case 4:	__asm__ __volatile__ ("swp %0, %1, [%2]"
-					: "=&r" (ret)
-					: "r" (x), "r" (ptr)
-					: "memory");
-			break;
-#endif
-		default: __bad_xchg(ptr, size), ret = 0;
-	}
-
-	return ret;
-}
-
-#endif
diff --git a/arch/arm/include/asm/processor.h b/arch/arm/include/asm/processor.h
deleted file mode 100644
index 445d449..0000000
--- a/arch/arm/include/asm/processor.h
+++ /dev/null
@@ -1,134 +0,0 @@
-/*
- *  linux/include/asm-arm/processor.h
- *
- *  Copyright (C) 1995-2002 Russell King
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __ASM_ARM_PROCESSOR_H
-#define __ASM_ARM_PROCESSOR_H
-
-/*
- * Default implementation of macro that returns current
- * instruction pointer ("program counter").
- */
-#define current_text_addr() ({ __label__ _l; _l: &&_l;})
-
-#define FP_SIZE 35
-
-struct fp_hard_struct {
-	unsigned int save[FP_SIZE];		/* as yet undefined */
-};
-
-struct fp_soft_struct {
-	unsigned int save[FP_SIZE];		/* undefined information */
-};
-
-union fp_state {
-	struct fp_hard_struct	hard;
-	struct fp_soft_struct	soft;
-};
-
-typedef unsigned long mm_segment_t;		/* domain register	*/
-
-#ifdef __KERNEL__
-
-#define EISA_bus 0
-#define MCA_bus 0
-#define MCA_bus__is_a_macro
-
-#include <asm/atomic.h>
-#include <asm/ptrace.h>
-#if 0	/* XXX###XXX */
-#include <asm/arch/memory.h>
-#endif	/* XXX###XXX */
-#include <asm/proc/processor.h>
-#include <asm/types.h>
-
-union debug_insn {
-	u32	arm;
-	u16	thumb;
-};
-
-struct debug_entry {
-	u32			address;
-	union debug_insn	insn;
-};
-
-struct debug_info {
-	int			nsaved;
-	struct debug_entry	bp[2];
-};
-
-struct thread_struct {
-	atomic_t			refcount;
-							/* fault info	  */
-	unsigned long			address;
-	unsigned long			trap_no;
-	unsigned long			error_code;
-							/* floating point */
-	union fp_state			fpstate;
-							/* debugging	  */
-	struct debug_info		debug;
-							/* context info	  */
-	struct context_save_struct	*save;
-	EXTRA_THREAD_STRUCT
-};
-
-#define INIT_THREAD  {					\
-	refcount:	ATOMIC_INIT(1),			\
-	EXTRA_THREAD_STRUCT_INIT			\
-}
-
-/*
- * Return saved PC of a blocked thread.
- */
-static inline unsigned long thread_saved_pc(struct thread_struct *t)
-{
-	return t->save ? pc_pointer(t->save->pc) : 0;
-}
-
-static inline unsigned long thread_saved_fp(struct thread_struct *t)
-{
-	return t->save ? t->save->fp : 0;
-}
-
-/* Forward declaration, a strange C thing */
-struct task_struct;
-
-/* Free all resources held by a thread. */
-extern void release_thread(struct task_struct *);
-
-/* Copy and release all segment info associated with a VM */
-#define copy_segments(tsk, mm)		do { } while (0)
-#define release_segments(mm)		do { } while (0)
-
-unsigned long get_wchan(struct task_struct *p);
-
-#define THREAD_SIZE	(8192)
-
-extern struct task_struct *alloc_task_struct(void);
-extern void __free_task_struct(struct task_struct *);
-#define get_task_struct(p)	atomic_inc(&(p)->thread.refcount)
-#define free_task_struct(p)					\
- do {								\
-	if (atomic_dec_and_test(&(p)->thread.refcount))		\
-		__free_task_struct((p));			\
- } while (0)
-
-#define init_task	(init_task_union.task)
-#define init_stack	(init_task_union.stack)
-
-#define cpu_relax()	barrier()
-
-/*
- * Create a new kernel thread
- */
-extern int arch_kernel_thread(int (*fn)(void *), void *arg, unsigned long flags);
-
-#endif
-
-#endif /* __ASM_ARM_PROCESSOR_H */
diff --git a/arch/arm/include/asm/ptrace.h b/arch/arm/include/asm/ptrace.h
deleted file mode 100644
index 73c9087..0000000
--- a/arch/arm/include/asm/ptrace.h
+++ /dev/null
@@ -1,33 +0,0 @@
-#ifndef __ASM_ARM_PTRACE_H
-#define __ASM_ARM_PTRACE_H
-
-#define PTRACE_GETREGS		12
-#define PTRACE_SETREGS		13
-#define PTRACE_GETFPREGS	14
-#define PTRACE_SETFPREGS	15
-
-#define PTRACE_SETOPTIONS	21
-
-/* options set using PTRACE_SETOPTIONS */
-#define PTRACE_O_TRACESYSGOOD	0x00000001
-
-#include <asm/proc/ptrace.h>
-
-#ifndef __ASSEMBLY__
-#define pc_pointer(v) \
-	((v) & ~PCMASK)
-
-#define instruction_pointer(regs) \
-	(pc_pointer((regs)->ARM_pc))
-
-#ifdef __KERNEL__
-extern void show_regs(struct pt_regs *);
-
-#define predicate(x)	(x & 0xf0000000)
-#define PREDICATE_ALWAYS	0xe0000000
-
-#endif
-
-#endif /* __ASSEMBLY__ */
-
-#endif
diff --git a/arch/arm/include/asm/setup.h b/arch/arm/include/asm/setup.h
deleted file mode 100644
index 89df4dc..0000000
--- a/arch/arm/include/asm/setup.h
+++ /dev/null
@@ -1,269 +0,0 @@
-/*
- *  linux/include/asm/setup.h
- *
- *  Copyright (C) 1997-1999 Russell King
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- *  Structure passed to kernel to tell it about the
- *  hardware it's running on.  See linux/Documentation/arm/Setup
- *  for more info.
- *
- * NOTE:
- *  This file contains two ways to pass information from the boot
- *  loader to the kernel. The old struct param_struct is deprecated,
- *  but it will be kept in the kernel for 5 years from now
- *  (2001). This will allow boot loaders to convert to the new struct
- *  tag way.
- */
-#ifndef __ASMARM_SETUP_H
-#define __ASMARM_SETUP_H
-
-/*
- * Usage:
- *  - do not go blindly adding fields, add them at the end
- *  - when adding fields, don't rely on the address until
- *    a patch from me has been released
- *  - unused fields should be zero (for future expansion)
- *  - this structure is relatively short-lived - only
- *    guaranteed to contain useful data in setup_arch()
- */
-#define COMMAND_LINE_SIZE 1024
-
-/* This is the old deprecated way to pass parameters to the kernel */
-struct param_struct {
-    union {
-	struct {
-	    unsigned long page_size;		/*  0 */
-	    unsigned long nr_pages;		/*  4 */
-	    unsigned long ramdisk_size;		/*  8 */
-	    unsigned long flags;		/* 12 */
-#define FLAG_READONLY	1
-#define FLAG_RDLOAD	4
-#define FLAG_RDPROMPT	8
-	    unsigned long rootdev;		/* 16 */
-	    unsigned long video_num_cols;	/* 20 */
-	    unsigned long video_num_rows;	/* 24 */
-	    unsigned long video_x;		/* 28 */
-	    unsigned long video_y;		/* 32 */
-	    unsigned long memc_control_reg;	/* 36 */
-	    unsigned char sounddefault;		/* 40 */
-	    unsigned char adfsdrives;		/* 41 */
-	    unsigned char bytes_per_char_h;	/* 42 */
-	    unsigned char bytes_per_char_v;	/* 43 */
-	    unsigned long pages_in_bank[4];	/* 44 */
-	    unsigned long pages_in_vram;	/* 60 */
-	    unsigned long initrd_start;		/* 64 */
-	    unsigned long initrd_size;		/* 68 */
-	    unsigned long rd_start;		/* 72 */
-	    unsigned long system_rev;		/* 76 */
-	    unsigned long system_serial_low;	/* 80 */
-	    unsigned long system_serial_high;	/* 84 */
-	    unsigned long mem_fclk_21285;       /* 88 */
-	} s;
-	char unused[256];
-    } u1;
-    union {
-	char paths[8][128];
-	struct {
-	    unsigned long magic;
-	    char n[1024 - sizeof(unsigned long)];
-	} s;
-    } u2;
-    char commandline[COMMAND_LINE_SIZE];
-};
-
-
-/*
- * The new way of passing information: a list of tagged entries
- */
-
-/* The list ends with an ATAG_NONE node. */
-#define ATAG_NONE	0x00000000
-
-struct tag_header {
-	u32 size;
-	u32 tag;
-};
-
-/* The list must start with an ATAG_CORE node */
-#define ATAG_CORE	0x54410001
-
-struct tag_core {
-	u32 flags;		/* bit 0 = read-only */
-	u32 pagesize;
-	u32 rootdev;
-};
-
-/* it is allowed to have multiple ATAG_MEM nodes */
-#define ATAG_MEM	0x54410002
-
-struct tag_mem32 {
-	u32	size;
-	u32	start;	/* physical start address */
-};
-
-/* VGA text type displays */
-#define ATAG_VIDEOTEXT	0x54410003
-
-struct tag_videotext {
-	u8		x;
-	u8		y;
-	u16		video_page;
-	u8		video_mode;
-	u8		video_cols;
-	u16		video_ega_bx;
-	u8		video_lines;
-	u8		video_isvga;
-	u16		video_points;
-};
-
-/* describes how the ramdisk will be used in kernel */
-#define ATAG_RAMDISK	0x54410004
-
-struct tag_ramdisk {
-	u32 flags;	/* bit 0 = load, bit 1 = prompt */
-	u32 size;	/* decompressed ramdisk size in _kilo_ bytes */
-	u32 start;	/* starting block of floppy-based RAM disk image */
-};
-
-/* describes where the compressed ramdisk image lives (virtual address) */
-/*
- * this one accidentally used virtual addresses - as such,
- * its depreciated.
- */
-#define ATAG_INITRD	0x54410005
-
-/* describes where the compressed ramdisk image lives (physical address) */
-#define ATAG_INITRD2	0x54420005
-
-struct tag_initrd {
-	u32 start;	/* physical start address */
-	u32 size;	/* size of compressed ramdisk image in bytes */
-};
-
-/* board serial number. "64 bits should be enough for everybody" */
-#define ATAG_SERIAL	0x54410006
-
-struct tag_serialnr {
-	u32 low;
-	u32 high;
-};
-
-/* board revision */
-#define ATAG_REVISION	0x54410007
-
-struct tag_revision {
-	u32 rev;
-};
-
-/* initial values for vesafb-type framebuffers. see struct screen_info
- * in include/linux/tty.h
- */
-#define ATAG_VIDEOLFB	0x54410008
-
-struct tag_videolfb {
-	u16		lfb_width;
-	u16		lfb_height;
-	u16		lfb_depth;
-	u16		lfb_linelength;
-	u32		lfb_base;
-	u32		lfb_size;
-	u8		red_size;
-	u8		red_pos;
-	u8		green_size;
-	u8		green_pos;
-	u8		blue_size;
-	u8		blue_pos;
-	u8		rsvd_size;
-	u8		rsvd_pos;
-};
-
-/* command line: \0 terminated string */
-#define ATAG_CMDLINE	0x54410009
-
-struct tag_cmdline {
-	char	cmdline[1];	/* this is the minimum size */
-};
-
-/* acorn RiscPC specific information */
-#define ATAG_ACORN	0x41000101
-
-struct tag_acorn {
-	u32 memc_control_reg;
-	u32 vram_pages;
-	u8 sounddefault;
-	u8 adfsdrives;
-};
-
-/* footbridge memory clock, see arch/arm/mach-footbridge/arch.c */
-#define ATAG_MEMCLK	0x41000402
-
-struct tag_memclk {
-	u32 fmemclk;
-};
-
-struct tag {
-	struct tag_header hdr;
-	union {
-		struct tag_core		core;
-		struct tag_mem32	mem;
-		struct tag_videotext	videotext;
-		struct tag_ramdisk	ramdisk;
-		struct tag_initrd	initrd;
-		struct tag_serialnr	serialnr;
-		struct tag_revision	revision;
-		struct tag_videolfb	videolfb;
-		struct tag_cmdline	cmdline;
-
-		/*
-		 * Acorn specific
-		 */
-		struct tag_acorn	acorn;
-
-		/*
-		 * DC21285 specific
-		 */
-		struct tag_memclk	memclk;
-	} u;
-};
-
-struct tagtable {
-	u32 tag;
-	int (*parse)(const struct tag *);
-};
-
-#define __tag __attribute__((unused, __section__(".taglist")))
-#define __tagtable(tag, fn) \
-static struct tagtable __tagtable_##fn __tag = { tag, fn }
-
-#define tag_member_present(tag,member)				\
-	((unsigned long)(&((struct tag *)0L)->member + 1)	\
-		<= (tag)->hdr.size * 4)
-
-#define tag_next(t)	((struct tag *)((u32 *)(t) + (t)->hdr.size))
-#define tag_size(type)	((sizeof(struct tag_header) + sizeof(struct type)) >> 2)
-
-#define for_each_tag(t,base)		\
-	for (t = base; t->hdr.size; t = tag_next(t))
-
-/*
- * Memory map description
- */
-#define NR_BANKS 8
-
-struct meminfo {
-	int nr_banks;
-	unsigned long end;
-	struct {
-		unsigned long start;
-		unsigned long size;
-		int           node;
-	} bank[NR_BANKS];
-};
-
-extern struct meminfo meminfo;
-
-#endif
diff --git a/arch/arm/include/asm/sizes.h b/arch/arm/include/asm/sizes.h
deleted file mode 100644
index b0b4f6a..0000000
--- a/arch/arm/include/asm/sizes.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-/*  Size defintions
- *  Copyright (C) ARM Limited 1998. All rights reserved.
- */
-
-#ifndef __sizes_h
-#define __sizes_h                       1
-
-/* handy sizes */
-#define SZ_1K                           0x00000400
-#define SZ_4K                           0x00001000
-#define SZ_8K                           0x00002000
-#define SZ_16K                          0x00004000
-#define SZ_32K                          0x00008000
-#define SZ_64K                          0x00010000
-#define SZ_128K                         0x00020000
-#define SZ_256K                         0x00040000
-#define SZ_512K                         0x00080000
-
-#define SZ_1M                           0x00100000
-#define SZ_2M                           0x00200000
-#define SZ_4M                           0x00400000
-#define SZ_8M                           0x00800000
-#define SZ_16M                          0x01000000
-#define SZ_31M                          0x01F00000
-#define SZ_32M                          0x02000000
-#define SZ_64M                          0x04000000
-#define SZ_128M                         0x08000000
-#define SZ_256M                         0x10000000
-#define SZ_512M                         0x20000000
-
-#define SZ_1G                           0x40000000
-#define SZ_2G                           0x80000000
-
-#endif
-
-/*         END */
diff --git a/arch/arm/include/asm/string.h b/arch/arm/include/asm/string.h
deleted file mode 100644
index c3ea582..0000000
--- a/arch/arm/include/asm/string.h
+++ /dev/null
@@ -1,47 +0,0 @@
-#ifndef __ASM_ARM_STRING_H
-#define __ASM_ARM_STRING_H
-
-/*
- * We don't do inline string functions, since the
- * optimised inline asm versions are not small.
- */
-
-#undef __HAVE_ARCH_STRRCHR
-extern char * strrchr(const char * s, int c);
-
-#undef __HAVE_ARCH_STRCHR
-extern char * strchr(const char * s, int c);
-
-#undef __HAVE_ARCH_MEMCPY
-extern void * memcpy(void *, const void *, __kernel_size_t);
-
-#undef __HAVE_ARCH_MEMMOVE
-extern void * memmove(void *, const void *, __kernel_size_t);
-
-#undef __HAVE_ARCH_MEMCHR
-extern void * memchr(const void *, int, __kernel_size_t);
-
-#undef __HAVE_ARCH_MEMZERO
-#undef __HAVE_ARCH_MEMSET
-extern void * memset(void *, int, __kernel_size_t);
-
-#if 0
-extern void __memzero(void *ptr, __kernel_size_t n);
-
-#define memset(p,v,n)							\
-	({								\
-		if ((n) != 0) {						\
-			if (__builtin_constant_p((v)) && (v) == 0)	\
-				__memzero((p),(n));			\
-			else						\
-				memset((p),(v),(n));			\
-		}							\
-		(p);							\
-	})
-
-#define memzero(p,n) ({ if ((n) != 0) __memzero((p),(n)); (p); })
-#else
-extern void memzero(void *ptr, __kernel_size_t n);
-#endif
-
-#endif
diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
deleted file mode 100644
index 2b28a26..0000000
--- a/arch/arm/include/asm/system.h
+++ /dev/null
@@ -1,84 +0,0 @@
-#ifndef __ASM_ARM_SYSTEM_H
-#define __ASM_ARM_SYSTEM_H
-
-#ifdef __KERNEL__
-
-#define CPU_ARCH_UNKNOWN	0
-#define CPU_ARCH_ARMv3		1
-#define CPU_ARCH_ARMv4		2
-#define CPU_ARCH_ARMv4T		3
-#define CPU_ARCH_ARMv5		4
-#define CPU_ARCH_ARMv5T		5
-#define CPU_ARCH_ARMv5TE	6
-#define CPU_ARCH_ARMv5TEJ	7
-#define CPU_ARCH_ARMv6		8
-#define CPU_ARCH_ARMv7		9
-
-/*
- * CR1 bits (CP#15 CR1)
- */
-#define CR_M	(1 << 0)	/* MMU enable				*/
-#define CR_A	(1 << 1)	/* Alignment abort enable		*/
-#define CR_C	(1 << 2)	/* Dcache enable			*/
-#define CR_W	(1 << 3)	/* Write buffer enable			*/
-#define CR_P	(1 << 4)	/* 32-bit exception handler		*/
-#define CR_D	(1 << 5)	/* 32-bit data address range		*/
-#define CR_L	(1 << 6)	/* Implementation defined		*/
-#define CR_B	(1 << 7)	/* Big endian				*/
-#define CR_S	(1 << 8)	/* System MMU protection		*/
-#define CR_R	(1 << 9)	/* ROM MMU protection			*/
-#define CR_F	(1 << 10)	/* Implementation defined		*/
-#define CR_Z	(1 << 11)	/* Implementation defined		*/
-#define CR_I	(1 << 12)	/* Icache enable			*/
-#define CR_V	(1 << 13)	/* Vectors relocated to 0xffff0000	*/
-#define CR_RR	(1 << 14)	/* Round Robin cache replacement	*/
-#define CR_L4	(1 << 15)	/* LDR pc can set T bit			*/
-#define CR_DT	(1 << 16)
-#define CR_IT	(1 << 18)
-#define CR_ST	(1 << 19)
-#define CR_FI	(1 << 21)	/* Fast interrupt (lower latency mode)	*/
-#define CR_U	(1 << 22)	/* Unaligned access operation		*/
-#define CR_XP	(1 << 23)	/* Extended page tables			*/
-#define CR_VE	(1 << 24)	/* Vectored interrupts			*/
-#define CR_EE	(1 << 25)	/* Exception (Big) Endian		*/
-#define CR_TRE	(1 << 28)	/* TEX remap enable			*/
-#define CR_AFE	(1 << 29)	/* Access flag enable			*/
-#define CR_TE	(1 << 30)	/* Thumb exception enable		*/
-
-/*
- * This is used to ensure the compiler did actually allocate the register we
- * asked it for some inline assembly sequences.  Apparently we can't trust
- * the compiler from one version to another so a bit of paranoia won't hurt.
- * This string is meant to be concatenated with the inline asm string and
- * will cause compilation to stop on mismatch.
- * (for details, see gcc PR 15089)
- */
-#define __asmeq(x, y)  ".ifnc " x "," y " ; .err ; .endif\n\t"
-
-#ifndef __ASSEMBLY__
-
-#define isb() __asm__ __volatile__ ("" : : : "memory")
-
-#define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t");
-
-static inline unsigned int get_cr(void)
-{
-	unsigned int val;
-	asm("mrc p15, 0, %0, c1, c0, 0	@ get CR" : "=r" (val) : : "cc");
-	return val;
-}
-
-static inline void set_cr(unsigned int val)
-{
-	asm volatile("mcr p15, 0, %0, c1, c0, 0	@ set CR"
-	  : : "r" (val) : "cc");
-	isb();
-}
-
-#endif /* __ASSEMBLY__ */
-
-#define arch_align_stack(x) (x)
-
-#endif /* __KERNEL__ */
-
-#endif
diff --git a/arch/arm/include/asm/types.h b/arch/arm/include/asm/types.h
deleted file mode 100644
index 71dc049..0000000
--- a/arch/arm/include/asm/types.h
+++ /dev/null
@@ -1,53 +0,0 @@
-#ifndef __ASM_ARM_TYPES_H
-#define __ASM_ARM_TYPES_H
-
-typedef unsigned short umode_t;
-
-/*
- * __xx is ok: it doesn't pollute the POSIX namespace. Use these in the
- * header files exported to user space
- */
-
-typedef __signed__ char __s8;
-typedef unsigned char __u8;
-
-typedef __signed__ short __s16;
-typedef unsigned short __u16;
-
-typedef __signed__ int __s32;
-typedef unsigned int __u32;
-
-#if defined(__GNUC__)
-__extension__ typedef __signed__ long long __s64;
-__extension__ typedef unsigned long long __u64;
-#endif
-
-/*
- * These aren't exported outside the kernel to avoid name space clashes
- */
-#ifdef __KERNEL__
-
-typedef signed char s8;
-typedef unsigned char u8;
-
-typedef signed short s16;
-typedef unsigned short u16;
-
-typedef signed int s32;
-typedef unsigned int u32;
-
-typedef signed long long s64;
-typedef unsigned long long u64;
-
-#define BITS_PER_LONG 32
-
-/* Dma addresses are 32-bits wide.  */
-
-typedef u32 dma_addr_t;
-
-typedef unsigned long phys_addr_t;
-typedef unsigned long phys_size_t;
-
-#endif /* __KERNEL__ */
-
-#endif
diff --git a/arch/arm/include/asm/u-boot-arm.h b/arch/arm/include/asm/u-boot-arm.h
deleted file mode 100644
index 33973a3..0000000
--- a/arch/arm/include/asm/u-boot-arm.h
+++ /dev/null
@@ -1,76 +0,0 @@
-/*
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Alex Zuepke <azu@sysgo.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef _U_BOOT_ARM_H_
-#define _U_BOOT_ARM_H_	1
-
-/* for the following variables, see start.S */
-extern ulong _bss_start_ofs;	/* BSS start relative to _start */
-extern ulong _bss_end_ofs;		/* BSS end relative to _start */
-extern ulong IRQ_STACK_START;	/* top of IRQ stack */
-extern ulong FIQ_STACK_START;	/* top of FIQ stack */
-extern ulong _TEXT_BASE;	/* code start */
-extern ulong _datarel_start_ofs;
-extern ulong _datarelrolocal_start_ofs;
-extern ulong _datarellocal_start_ofs;
-extern ulong _datarelro_start_ofs;
-extern ulong IRQ_STACK_START_IN;	/* 8 bytes in IRQ stack */
-
-/* cpu/.../cpu.c */
-int	cpu_init(void);
-int	cleanup_before_linux(void);
-
-/* cpu/.../arch/cpu.c */
-int	arch_cpu_init(void);
-int	arch_misc_init(void);
-
-/* board/.../... */
-int	board_init(void);
-int	dram_init (void);
-void	dram_init_banksize (void);
-void	setup_serial_tag (struct tag **params);
-void	setup_revision_tag (struct tag **params);
-
-/* ------------------------------------------------------------ */
-/* Here is a list of some prototypes which are incompatible to	*/
-/* the U-Boot implementation					*/
-/* To be fixed!							*/
-/* ------------------------------------------------------------ */
-/* common/cmd_nvedit.c */
-int	setenv		(char *, char *);
-
-/* cpu/.../interrupt.c */
-int	arch_interrupt_init	(void);
-void	reset_timer_masked	(void);
-ulong	get_timer_masked	(void);
-void	udelay_masked		(unsigned long usec);
-
-/* cpu/.../timer.c */
-int	timer_init		(void);
-
-#endif	/* _U_BOOT_ARM_H_ */
diff --git a/arch/arm/include/asm/u-boot.h b/arch/arm/include/asm/u-boot.h
deleted file mode 100644
index ed33327..0000000
--- a/arch/arm/include/asm/u-boot.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Alex Zuepke <azu@sysgo.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- ********************************************************************
- * NOTE: This header file defines an interface to U-Boot. Including
- * this (unmodified) header file in another file is considered normal
- * use of U-Boot, and does *not* fall under the heading of "derived
- * work".
- ********************************************************************
- */
-
-#ifndef _U_BOOT_H_
-#define _U_BOOT_H_	1
-
-typedef struct bd_info {
-    int			bi_baudrate;	/* serial console baudrate */
-    unsigned long	bi_ip_addr;	/* IP Address */
-    ulong	        bi_arch_number;	/* unique id for this board */
-    ulong	        bi_boot_params;	/* where this board expects params */
-    struct				/* RAM configuration */
-    {
-	ulong start;
-	ulong size;
-    }			bi_dram[CONFIG_NR_DRAM_BANKS];
-} bd_t;
-
-#endif	/* _U_BOOT_H_ */
diff --git a/arch/arm/include/asm/unaligned.h b/arch/arm/include/asm/unaligned.h
deleted file mode 100644
index 44593a8..0000000
--- a/arch/arm/include/asm/unaligned.h
+++ /dev/null
@@ -1,19 +0,0 @@
-#ifndef _ASM_ARM_UNALIGNED_H
-#define _ASM_ARM_UNALIGNED_H
-
-#include <linux/unaligned/le_byteshift.h>
-#include <linux/unaligned/be_byteshift.h>
-#include <linux/unaligned/generic.h>
-
-/*
- * Select endianness
- */
-#ifndef __ARMEB__
-#define get_unaligned	__get_unaligned_le
-#define put_unaligned	__put_unaligned_le
-#else
-#define get_unaligned	__get_unaligned_be
-#define put_unaligned	__put_unaligned_be
-#endif
-
-#endif /* _ASM_ARM_UNALIGNED_H */
diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile
deleted file mode 100644
index 454440c..0000000
--- a/arch/arm/lib/Makefile
+++ /dev/null
@@ -1,82 +0,0 @@
-#
-# (C) Copyright 2002-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(ARCH).o
-LIBGCC	= $(obj)libgcc.o
-
-GLSOBJS	+= _ashldi3.o
-GLSOBJS	+= _ashrdi3.o
-GLSOBJS	+= _divsi3.o
-GLSOBJS	+= _lshrdi3.o
-GLSOBJS	+= _modsi3.o
-GLSOBJS	+= _udivsi3.o
-GLSOBJS	+= _umodsi3.o
-
-GLCOBJS	+= div0.o
-
-COBJS-y	+= board.o
-COBJS-y	+= bootm.o
-COBJS-y	+= cache.o
-ifndef CONFIG_SYS_NO_CP15_CACHE
-COBJS-y	+= cache-cp15.o
-endif
-COBJS-y	+= interrupts.o
-COBJS-y	+= reset.o
-
-SRCS	:= $(GLSOBJS:.o=.S) $(GLCOBJS:.o=.c) \
-	   $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
-LGOBJS	:= $(addprefix $(obj),$(GLSOBJS)) \
-	   $(addprefix $(obj),$(GLCOBJS))
-
-# Always build libarm.o
-TARGETS	:= $(LIB)
-
-# Build private libgcc only when asked for
-ifdef USE_PRIVATE_LIBGCC
-TARGETS	+= $(LIBGCC)
-endif
-
-# For EABI conformant tool chains, provide eabi_compat()
-ifneq (,$(findstring -mabi=aapcs-linux,$(PLATFORM_CPPFLAGS)))
-TARGETS	+= $(obj)eabi_compat.o
-endif
-
-all:	$(TARGETS)
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-$(LIBGCC): $(obj).depend $(LGOBJS)
-	$(call cmd_link_o_target, $(LGOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/arch/arm/lib/_ashldi3.S b/arch/arm/lib/_ashldi3.S
deleted file mode 100644
index 834ddc2..0000000
--- a/arch/arm/lib/_ashldi3.S
+++ /dev/null
@@ -1,48 +0,0 @@
-/* Copyright 1995, 1996, 1998, 1999, 2000, 2003, 2004, 2005
-   Free Software Foundation, Inc.
-
-This file is free software; you can redistribute it and/or modify it
-under the terms of the GNU General Public License as published by the
-Free Software Foundation; either version 2, or (at your option) any
-later version.
-
-In addition to the permissions in the GNU General Public License, the
-Free Software Foundation gives you unlimited permission to link the
-compiled version of this file into combinations with other programs,
-and to distribute those combinations without any restriction coming
-from the use of this file.  (The General Public License restrictions
-do apply in other respects; for example, they cover modification of
-the file, and distribution when not linked into a combine
-executable.)
-
-This file is distributed in the hope that it will be useful, but
-WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with this program; see the file COPYING.  If not, write to
-the Free Software Foundation, 51 Franklin Street, Fifth Floor,
-Boston, MA 02110-1301, USA.  */
-
-
-#ifdef __ARMEB__
-#define al r1
-#define ah r0
-#else
-#define al r0
-#define ah r1
-#endif
-
-.globl __ashldi3
-.globl	__aeabi_llsl
-__ashldi3:
-__aeabi_llsl:
-
-	subs	r3, r2, #32
-	rsb	ip, r2, #32
-	movmi	ah, ah, lsl r2
-	movpl	ah, al, lsl r3
-	orrmi	ah, ah, al, lsr ip
-	mov	al, al, lsl r2
-	mov	pc, lr
diff --git a/arch/arm/lib/_ashrdi3.S b/arch/arm/lib/_ashrdi3.S
deleted file mode 100644
index 671ac87..0000000
--- a/arch/arm/lib/_ashrdi3.S
+++ /dev/null
@@ -1,48 +0,0 @@
-/* Copyright 1995, 1996, 1998, 1999, 2000, 2003, 2004, 2005
-   Free Software Foundation, Inc.
-
-This file is free software; you can redistribute it and/or modify it
-under the terms of the GNU General Public License as published by the
-Free Software Foundation; either version 2, or (at your option) any
-later version.
-
-In addition to the permissions in the GNU General Public License, the
-Free Software Foundation gives you unlimited permission to link the
-compiled version of this file into combinations with other programs,
-and to distribute those combinations without any restriction coming
-from the use of this file.  (The General Public License restrictions
-do apply in other respects; for example, they cover modification of
-the file, and distribution when not linked into a combine
-executable.)
-
-This file is distributed in the hope that it will be useful, but
-WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with this program; see the file COPYING.  If not, write to
-the Free Software Foundation, 51 Franklin Street, Fifth Floor,
-Boston, MA 02110-1301, USA.  */
-
-
-#ifdef __ARMEB__
-#define al r1
-#define ah r0
-#else
-#define al r0
-#define ah r1
-#endif
-
-.globl __ashrdi3
-.globl __aeabi_lasr
-__ashrdi3:
-__aeabi_lasr:
-
-	subs	r3, r2, #32
-	rsb	ip, r2, #32
-	movmi	al, al, lsr r2
-	movpl	al, ah, asr r3
-	orrmi	al, al, ah, lsl ip
-	mov	ah, ah, asr r2
-	mov	pc, lr
diff --git a/arch/arm/lib/_divsi3.S b/arch/arm/lib/_divsi3.S
deleted file mode 100644
index cfbadb2..0000000
--- a/arch/arm/lib/_divsi3.S
+++ /dev/null
@@ -1,142 +0,0 @@
-
-.macro ARM_DIV_BODY dividend, divisor, result, curbit
-
-#if __LINUX_ARM_ARCH__ >= 5
-
-	clz	\curbit, \divisor
-	clz	\result, \dividend
-	sub	\result, \curbit, \result
-	mov	\curbit, #1
-	mov	\divisor, \divisor, lsl \result
-	mov	\curbit, \curbit, lsl \result
-	mov	\result, #0
-
-#else
-
-	@ Initially shift the divisor left 3 bits if possible,
-	@ set curbit accordingly.  This allows for curbit to be located
-	@ at the left end of each 4 bit nibbles in the division loop
-	@ to save one loop in most cases.
-	tst	\divisor, #0xe0000000
-	moveq	\divisor, \divisor, lsl #3
-	moveq	\curbit, #8
-	movne	\curbit, #1
-
-	@ Unless the divisor is very big, shift it up in multiples of
-	@ four bits, since this is the amount of unwinding in the main
-	@ division loop.  Continue shifting until the divisor is
-	@ larger than the dividend.
-1:	cmp	\divisor, #0x10000000
-	cmplo	\divisor, \dividend
-	movlo	\divisor, \divisor, lsl #4
-	movlo	\curbit, \curbit, lsl #4
-	blo	1b
-
-	@ For very big divisors, we must shift it a bit at a time, or
-	@ we will be in danger of overflowing.
-1:	cmp	\divisor, #0x80000000
-	cmplo	\divisor, \dividend
-	movlo	\divisor, \divisor, lsl #1
-	movlo	\curbit, \curbit, lsl #1
-	blo	1b
-
-	mov	\result, #0
-
-#endif
-
-	@ Division loop
-1:	cmp	\dividend, \divisor
-	subhs	\dividend, \dividend, \divisor
-	orrhs	\result,   \result,   \curbit
-	cmp	\dividend, \divisor,  lsr #1
-	subhs	\dividend, \dividend, \divisor, lsr #1
-	orrhs	\result,   \result,   \curbit,  lsr #1
-	cmp	\dividend, \divisor,  lsr #2
-	subhs	\dividend, \dividend, \divisor, lsr #2
-	orrhs	\result,   \result,   \curbit,  lsr #2
-	cmp	\dividend, \divisor,  lsr #3
-	subhs	\dividend, \dividend, \divisor, lsr #3
-	orrhs	\result,   \result,   \curbit,  lsr #3
-	cmp	\dividend, #0			@ Early termination?
-	movnes	\curbit,   \curbit,  lsr #4	@ No, any more bits to do?
-	movne	\divisor,  \divisor, lsr #4
-	bne	1b
-
-.endm
-
-.macro ARM_DIV2_ORDER divisor, order
-
-#if __LINUX_ARM_ARCH__ >= 5
-
-	clz	\order, \divisor
-	rsb	\order, \order, #31
-
-#else
-
-	cmp	\divisor, #(1 << 16)
-	movhs	\divisor, \divisor, lsr #16
-	movhs	\order, #16
-	movlo	\order, #0
-
-	cmp	\divisor, #(1 << 8)
-	movhs	\divisor, \divisor, lsr #8
-	addhs	\order, \order, #8
-
-	cmp	\divisor, #(1 << 4)
-	movhs	\divisor, \divisor, lsr #4
-	addhs	\order, \order, #4
-
-	cmp	\divisor, #(1 << 2)
-	addhi	\order, \order, #3
-	addls	\order, \order, \divisor, lsr #1
-
-#endif
-
-.endm
-
-	.align	5
-.globl __divsi3
-.globl __aeabi_idiv
-__divsi3:
-__aeabi_idiv:
-	cmp	r1, #0
-	eor	ip, r0, r1			@ save the sign of the result.
-	beq	Ldiv0
-	rsbmi	r1, r1, #0			@ loops below use unsigned.
-	subs	r2, r1, #1			@ division by 1 or -1 ?
-	beq	10f
-	movs	r3, r0
-	rsbmi	r3, r0, #0			@ positive dividend value
-	cmp	r3, r1
-	bls	11f
-	tst	r1, r2				@ divisor is power of 2 ?
-	beq	12f
-
-	ARM_DIV_BODY r3, r1, r0, r2
-
-	cmp	ip, #0
-	rsbmi	r0, r0, #0
-	mov	pc, lr
-
-10:	teq	ip, r0				@ same sign ?
-	rsbmi	r0, r0, #0
-	mov	pc, lr
-
-11:	movlo	r0, #0
-	moveq	r0, ip, asr #31
-	orreq	r0, r0, #1
-	mov	pc, lr
-
-12:	ARM_DIV2_ORDER r1, r2
-
-	cmp	ip, #0
-	mov	r0, r3, lsr r2
-	rsbmi	r0, r0, #0
-	mov	pc, lr
-
-Ldiv0:
-
-	str	lr, [sp, #-4]!
-	bl	__div0
-	mov	r0, #0			@ About as wrong as it could be.
-	ldr	pc, [sp], #4
diff --git a/arch/arm/lib/_lshrdi3.S b/arch/arm/lib/_lshrdi3.S
deleted file mode 100644
index e7fa799..0000000
--- a/arch/arm/lib/_lshrdi3.S
+++ /dev/null
@@ -1,48 +0,0 @@
-/* Copyright 1995, 1996, 1998, 1999, 2000, 2003, 2004, 2005
-   Free Software Foundation, Inc.
-
-This file is free software; you can redistribute it and/or modify it
-under the terms of the GNU General Public License as published by the
-Free Software Foundation; either version 2, or (at your option) any
-later version.
-
-In addition to the permissions in the GNU General Public License, the
-Free Software Foundation gives you unlimited permission to link the
-compiled version of this file into combinations with other programs,
-and to distribute those combinations without any restriction coming
-from the use of this file.  (The General Public License restrictions
-do apply in other respects; for example, they cover modification of
-the file, and distribution when not linked into a combine
-executable.)
-
-This file is distributed in the hope that it will be useful, but
-WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with this program; see the file COPYING.  If not, write to
-the Free Software Foundation, 51 Franklin Street, Fifth Floor,
-Boston, MA 02110-1301, USA.  */
-
-
-#ifdef __ARMEB__
-#define al r1
-#define ah r0
-#else
-#define al r0
-#define ah r1
-#endif
-
-.globl __lshrdi3
-.globl __aeabi_llsr
-__lshrdi3:
-__aeabi_llsr:
-
-	subs	r3, r2, #32
-	rsb	ip, r2, #32
-	movmi	al, al, lsr r2
-	movpl	al, ah, lsr r3
-	orrmi	al, al, ah, lsl ip
-	mov	ah, ah, lsr r2
-	mov	pc, lr
diff --git a/arch/arm/lib/_modsi3.S b/arch/arm/lib/_modsi3.S
deleted file mode 100644
index 539c584..0000000
--- a/arch/arm/lib/_modsi3.S
+++ /dev/null
@@ -1,99 +0,0 @@
-
-.macro ARM_MOD_BODY dividend, divisor, order, spare
-
-#if __LINUX_ARM_ARCH__ >= 5
-
-	clz	\order, \divisor
-	clz	\spare, \dividend
-	sub	\order, \order, \spare
-	mov	\divisor, \divisor, lsl \order
-
-#else
-
-	mov	\order, #0
-
-	@ Unless the divisor is very big, shift it up in multiples of
-	@ four bits, since this is the amount of unwinding in the main
-	@ division loop.  Continue shifting until the divisor is
-	@ larger than the dividend.
-1:	cmp	\divisor, #0x10000000
-	cmplo	\divisor, \dividend
-	movlo	\divisor, \divisor, lsl #4
-	addlo	\order, \order, #4
-	blo	1b
-
-	@ For very big divisors, we must shift it a bit at a time, or
-	@ we will be in danger of overflowing.
-1:	cmp	\divisor, #0x80000000
-	cmplo	\divisor, \dividend
-	movlo	\divisor, \divisor, lsl #1
-	addlo	\order, \order, #1
-	blo	1b
-
-#endif
-
-	@ Perform all needed substractions to keep only the reminder.
-	@ Do comparisons in batch of 4 first.
-	subs	\order, \order, #3		@ yes, 3 is intended here
-	blt	2f
-
-1:	cmp	\dividend, \divisor
-	subhs	\dividend, \dividend, \divisor
-	cmp	\dividend, \divisor,  lsr #1
-	subhs	\dividend, \dividend, \divisor, lsr #1
-	cmp	\dividend, \divisor,  lsr #2
-	subhs	\dividend, \dividend, \divisor, lsr #2
-	cmp	\dividend, \divisor,  lsr #3
-	subhs	\dividend, \dividend, \divisor, lsr #3
-	cmp	\dividend, #1
-	mov	\divisor, \divisor, lsr #4
-	subges	\order, \order, #4
-	bge	1b
-
-	tst	\order, #3
-	teqne	\dividend, #0
-	beq	5f
-
-	@ Either 1, 2 or 3 comparison/substractions are left.
-2:	cmn	\order, #2
-	blt	4f
-	beq	3f
-	cmp	\dividend, \divisor
-	subhs	\dividend, \dividend, \divisor
-	mov	\divisor,  \divisor,  lsr #1
-3:	cmp	\dividend, \divisor
-	subhs	\dividend, \dividend, \divisor
-	mov	\divisor,  \divisor,  lsr #1
-4:	cmp	\dividend, \divisor
-	subhs	\dividend, \dividend, \divisor
-5:
-.endm
-
-	.align	5
-.globl __modsi3
-__modsi3:
-	cmp	r1, #0
-	beq	Ldiv0
-	rsbmi	r1, r1, #0			@ loops below use unsigned.
-	movs	ip, r0				@ preserve sign of dividend
-	rsbmi	r0, r0, #0			@ if negative make positive
-	subs	r2, r1, #1			@ compare divisor with 1
-	cmpne	r0, r1				@ compare dividend with divisor
-	moveq	r0, #0
-	tsthi	r1, r2				@ see if divisor is power of 2
-	andeq	r0, r0, r2
-	bls	10f
-
-	ARM_MOD_BODY r0, r1, r2, r3
-
-10:	cmp	ip, #0
-	rsbmi	r0, r0, #0
-	mov	pc, lr
-
-
-Ldiv0:
-
-	str	lr, [sp, #-4]!
-	bl	__div0
-	mov	r0, #0			@ About as wrong as it could be.
-	ldr	pc, [sp], #4
diff --git a/arch/arm/lib/_udivsi3.S b/arch/arm/lib/_udivsi3.S
deleted file mode 100644
index 1309802..0000000
--- a/arch/arm/lib/_udivsi3.S
+++ /dev/null
@@ -1,93 +0,0 @@
-/* # 1 "libgcc1.S" */
-@ libgcc1 routines for ARM cpu.
-@ Division routines, written by Richard Earnshaw, (rearnsha@armltd.co.uk)
-dividend	.req	r0
-divisor		.req	r1
-result		.req	r2
-curbit		.req	r3
-/* ip		.req	r12	*/
-/* sp		.req	r13	*/
-/* lr		.req	r14	*/
-/* pc		.req	r15	*/
-	.text
-	.globl	 __udivsi3
-	.type	__udivsi3 ,function
-	.globl	__aeabi_uidiv
-	.type	__aeabi_uidiv ,function
-	.align	0
- __udivsi3:
- __aeabi_uidiv:
-	cmp	divisor, #0
-	beq	Ldiv0
-	mov	curbit, #1
-	mov	result, #0
-	cmp	dividend, divisor
-	bcc	Lgot_result
-Loop1:
-	@ Unless the divisor is very big, shift it up in multiples of
-	@ four bits, since this is the amount of unwinding in the main
-	@ division loop.  Continue shifting until the divisor is
-	@ larger than the dividend.
-	cmp	divisor, #0x10000000
-	cmpcc	divisor, dividend
-	movcc	divisor, divisor, lsl #4
-	movcc	curbit, curbit, lsl #4
-	bcc	Loop1
-Lbignum:
-	@ For very big divisors, we must shift it a bit at a time, or
-	@ we will be in danger of overflowing.
-	cmp	divisor, #0x80000000
-	cmpcc	divisor, dividend
-	movcc	divisor, divisor, lsl #1
-	movcc	curbit, curbit, lsl #1
-	bcc	Lbignum
-Loop3:
-	@ Test for possible subtractions, and note which bits
-	@ are done in the result.  On the final pass, this may subtract
-	@ too much from the dividend, but the result will be ok, since the
-	@ "bit" will have been shifted out at the bottom.
-	cmp	dividend, divisor
-	subcs	dividend, dividend, divisor
-	orrcs	result, result, curbit
-	cmp	dividend, divisor, lsr #1
-	subcs	dividend, dividend, divisor, lsr #1
-	orrcs	result, result, curbit, lsr #1
-	cmp	dividend, divisor, lsr #2
-	subcs	dividend, dividend, divisor, lsr #2
-	orrcs	result, result, curbit, lsr #2
-	cmp	dividend, divisor, lsr #3
-	subcs	dividend, dividend, divisor, lsr #3
-	orrcs	result, result, curbit, lsr #3
-	cmp	dividend, #0			@ Early termination?
-	movnes	curbit, curbit, lsr #4		@ No, any more bits to do?
-	movne	divisor, divisor, lsr #4
-	bne	Loop3
-Lgot_result:
-	mov	r0, result
-	mov	pc, lr
-Ldiv0:
-	str	lr, [sp, #-4]!
-	bl	 __div0       (PLT)
-	mov	r0, #0			@ about as wrong as it could be
-	ldmia	sp!, {pc}
-	.size  __udivsi3       , . -  __udivsi3
-
-.globl __aeabi_uidivmod
-__aeabi_uidivmod:
-
-	stmfd	sp!, {r0, r1, ip, lr}
-	bl	__aeabi_uidiv
-	ldmfd	sp!, {r1, r2, ip, lr}
-	mul	r3, r0, r2
-	sub	r1, r1, r3
-	mov	pc, lr
-
-.globl __aeabi_idivmod
-__aeabi_idivmod:
-
-	stmfd	sp!, {r0, r1, ip, lr}
-	bl	__aeabi_idiv
-	ldmfd	sp!, {r1, r2, ip, lr}
-	mul	r3, r0, r2
-	sub	r1, r1, r3
-	mov	pc, lr
diff --git a/arch/arm/lib/_umodsi3.S b/arch/arm/lib/_umodsi3.S
deleted file mode 100644
index 8465ef0..0000000
--- a/arch/arm/lib/_umodsi3.S
+++ /dev/null
@@ -1,88 +0,0 @@
-/* # 1 "libgcc1.S" */
-@ libgcc1 routines for ARM cpu.
-@ Division routines, written by Richard Earnshaw, (rearnsha@armltd.co.uk)
-/* # 145 "libgcc1.S" */
-dividend	.req	r0
-divisor		.req	r1
-overdone	.req	r2
-curbit		.req	r3
-/* ip		.req	r12	*/
-/* sp		.req	r13	*/
-/* lr		.req	r14	*/
-/* pc		.req	r15	*/
-	.text
-	.globl	 __umodsi3
-	.type  __umodsi3       ,function
-	.align 0
- __umodsi3      :
-	cmp	divisor, #0
-	beq	Ldiv0
-	mov	curbit, #1
-	cmp	dividend, divisor
-	movcc	pc, lr
-Loop1:
-	@ Unless the divisor is very big, shift it up in multiples of
-	@ four bits, since this is the amount of unwinding in the main
-	@ division loop.  Continue shifting until the divisor is
-	@ larger than the dividend.
-	cmp	divisor, #0x10000000
-	cmpcc	divisor, dividend
-	movcc	divisor, divisor, lsl #4
-	movcc	curbit, curbit, lsl #4
-	bcc	Loop1
-Lbignum:
-	@ For very big divisors, we must shift it a bit at a time, or
-	@ we will be in danger of overflowing.
-	cmp	divisor, #0x80000000
-	cmpcc	divisor, dividend
-	movcc	divisor, divisor, lsl #1
-	movcc	curbit, curbit, lsl #1
-	bcc	Lbignum
-Loop3:
-	@ Test for possible subtractions.  On the final pass, this may
-	@ subtract too much from the dividend, so keep track of which
-	@ subtractions are done, we can fix them up afterwards...
-	mov	overdone, #0
-	cmp	dividend, divisor
-	subcs	dividend, dividend, divisor
-	cmp	dividend, divisor, lsr #1
-	subcs	dividend, dividend, divisor, lsr #1
-	orrcs	overdone, overdone, curbit, ror #1
-	cmp	dividend, divisor, lsr #2
-	subcs	dividend, dividend, divisor, lsr #2
-	orrcs	overdone, overdone, curbit, ror #2
-	cmp	dividend, divisor, lsr #3
-	subcs	dividend, dividend, divisor, lsr #3
-	orrcs	overdone, overdone, curbit, ror #3
-	mov	ip, curbit
-	cmp	dividend, #0			@ Early termination?
-	movnes	curbit, curbit, lsr #4		@ No, any more bits to do?
-	movne	divisor, divisor, lsr #4
-	bne	Loop3
-	@ Any subtractions that we should not have done will be recorded in
-	@ the top three bits of "overdone".  Exactly which were not needed
-	@ are governed by the position of the bit, stored in ip.
-	@ If we terminated early, because dividend became zero,
-	@ then none of the below will match, since the bit in ip will not be
-	@ in the bottom nibble.
-	ands	overdone, overdone, #0xe0000000
-	moveq	pc, lr				@ No fixups needed
-	tst	overdone, ip, ror #3
-	addne	dividend, dividend, divisor, lsr #3
-	tst	overdone, ip, ror #2
-	addne	dividend, dividend, divisor, lsr #2
-	tst	overdone, ip, ror #1
-	addne	dividend, dividend, divisor, lsr #1
-	mov	pc, lr
-Ldiv0:
-	str	lr, [sp, #-4]!
-	bl	 __div0       (PLT)
-	mov	r0, #0			@ about as wrong as it could be
-	ldmia	sp!, {pc}
-	.size  __umodsi3       , . -  __umodsi3
-/* # 320 "libgcc1.S" */
-/* # 421 "libgcc1.S" */
-/* # 433 "libgcc1.S" */
-/* # 456 "libgcc1.S" */
-/* # 500 "libgcc1.S" */
-/* # 580 "libgcc1.S" */
diff --git a/arch/arm/lib/board.c b/arch/arm/lib/board.c
deleted file mode 100644
index c620d2c..0000000
--- a/arch/arm/lib/board.c
+++ /dev/null
@@ -1,649 +0,0 @@
-/*
- * (C) Copyright 2002-2006
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * To match the U-Boot user interface on ARM platforms to the U-Boot
- * standard (as on PPC platforms), some messages with debug character
- * are removed from the default U-Boot build.
- *
- * Define DEBUG here if you want additional info as shown below
- * printed upon startup:
- *
- * U-Boot code: 00F00000 -> 00F3C774  BSS: -> 00FC3274
- * IRQ Stack: 00ebff7c
- * FIQ Stack: 00ebef7c
- */
-
-#include <common.h>
-#include <command.h>
-#include <malloc.h>
-#include <stdio_dev.h>
-#include <timestamp.h>
-#include <version.h>
-#include <net.h>
-#include <serial.h>
-#include <nand.h>
-#include <onenand_uboot.h>
-#include <mmc.h>
-
-#ifdef CONFIG_BITBANGMII
-#include <miiphy.h>
-#endif
-
-#ifdef CONFIG_DRIVER_SMC91111
-#include "../drivers/net/smc91111.h"
-#endif
-#ifdef CONFIG_DRIVER_LAN91C96
-#include "../drivers/net/lan91c96.h"
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-ulong monitor_flash_len;
-
-#ifdef CONFIG_HAS_DATAFLASH
-extern int  AT91F_DataflashInit(void);
-extern void dataflash_print_info(void);
-#endif
-
-#ifndef CONFIG_IDENT_STRING
-#define CONFIG_IDENT_STRING ""
-#endif
-
-const char version_string[] =
-	U_BOOT_VERSION" (" U_BOOT_DATE " - " U_BOOT_TIME ")"CONFIG_IDENT_STRING;
-
-#ifdef CONFIG_DRIVER_RTL8019
-extern void rtl8019_get_enetaddr (uchar * addr);
-#endif
-
-#if defined(CONFIG_HARD_I2C) || \
-    defined(CONFIG_SOFT_I2C)
-#include <i2c.h>
-#endif
-
-
-/************************************************************************
- * Coloured LED functionality
- ************************************************************************
- * May be supplied by boards if desired
- */
-void inline __coloured_LED_init (void) {}
-void coloured_LED_init (void) __attribute__((weak, alias("__coloured_LED_init")));
-void inline __red_LED_on (void) {}
-void red_LED_on (void) __attribute__((weak, alias("__red_LED_on")));
-void inline __red_LED_off(void) {}
-void red_LED_off(void) __attribute__((weak, alias("__red_LED_off")));
-void inline __green_LED_on(void) {}
-void green_LED_on(void) __attribute__((weak, alias("__green_LED_on")));
-void inline __green_LED_off(void) {}
-void green_LED_off(void) __attribute__((weak, alias("__green_LED_off")));
-void inline __yellow_LED_on(void) {}
-void yellow_LED_on(void) __attribute__((weak, alias("__yellow_LED_on")));
-void inline __yellow_LED_off(void) {}
-void yellow_LED_off(void) __attribute__((weak, alias("__yellow_LED_off")));
-void inline __blue_LED_on(void) {}
-void blue_LED_on(void) __attribute__((weak, alias("__blue_LED_on")));
-void inline __blue_LED_off(void) {}
-void blue_LED_off(void) __attribute__((weak, alias("__blue_LED_off")));
-
-/************************************************************************
- * Init Utilities							*
- ************************************************************************
- * Some of this code should be moved into the core functions,
- * or dropped completely,
- * but let's get it working (again) first...
- */
-
-#if defined(CONFIG_ARM_DCC) && !defined(CONFIG_BAUDRATE)
-#define CONFIG_BAUDRATE 115200
-#endif
-static int init_baudrate (void)
-{
-	char tmp[64];	/* long enough for environment variables */
-	int i = getenv_f("baudrate", tmp, sizeof (tmp));
-
-	gd->baudrate = (i > 0)
-			? (int) simple_strtoul (tmp, NULL, 10)
-			: CONFIG_BAUDRATE;
-
-	return (0);
-}
-
-static int display_banner (void)
-{
-	printf ("\n\n%s\n\n", version_string);
-	debug ("U-Boot code: %08lX -> %08lX  BSS: -> %08lX\n",
-	       _TEXT_BASE,
-	       _bss_start_ofs+_TEXT_BASE, _bss_end_ofs+_TEXT_BASE);
-#ifdef CONFIG_MODEM_SUPPORT
-	debug ("Modem Support enabled\n");
-#endif
-#ifdef CONFIG_USE_IRQ
-	debug ("IRQ Stack: %08lx\n", IRQ_STACK_START);
-	debug ("FIQ Stack: %08lx\n", FIQ_STACK_START);
-#endif
-
-	return (0);
-}
-
-/*
- * WARNING: this code looks "cleaner" than the PowerPC version, but
- * has the disadvantage that you either get nothing, or everything.
- * On PowerPC, you might see "DRAM: " before the system hangs - which
- * gives a simple yet clear indication which part of the
- * initialization if failing.
- */
-static int display_dram_config (void)
-{
-	int i;
-
-#ifdef DEBUG
-	puts ("RAM Configuration:\n");
-
-	for(i=0; i<CONFIG_NR_DRAM_BANKS; i++) {
-		printf ("Bank #%d: %08lx ", i, gd->bd->bi_dram[i].start);
-		print_size (gd->bd->bi_dram[i].size, "\n");
-	}
-#else
-	ulong size = 0;
-
-	for (i=0; i<CONFIG_NR_DRAM_BANKS; i++) {
-		size += gd->bd->bi_dram[i].size;
-	}
-	puts("DRAM:  ");
-	print_size(size, "\n");
-#endif
-
-	return (0);
-}
-
-#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C)
-static int init_func_i2c (void)
-{
-	puts ("I2C:   ");
-	i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
-	puts ("ready\n");
-	return (0);
-}
-#endif
-
-#if defined(CONFIG_CMD_PCI) || defined (CONFIG_PCI)
-#include <pci.h>
-static int arm_pci_init(void)
-{
-	pci_init();
-	return 0;
-}
-#endif /* CONFIG_CMD_PCI || CONFIG_PCI */
-
-/*
- * Breathe some life into the board...
- *
- * Initialize a serial port as console, and carry out some hardware
- * tests.
- *
- * The first part of initialization is running from Flash memory;
- * its main purpose is to initialize the RAM so that we
- * can relocate the monitor code to RAM.
- */
-
-/*
- * All attempts to come up with a "common" initialization sequence
- * that works for all boards and architectures failed: some of the
- * requirements are just _too_ different. To get rid of the resulting
- * mess of board dependent #ifdef'ed code we now make the whole
- * initialization sequence configurable to the user.
- *
- * The requirements for any new initalization function is simple: it
- * receives a pointer to the "global data" structure as it's only
- * argument, and returns an integer return code, where 0 means
- * "continue" and != 0 means "fatal error, hang the system".
- */
-typedef int (init_fnc_t) (void);
-
-int print_cpuinfo (void);
-
-void __dram_init_banksize(void)
-{
-	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
-	gd->bd->bi_dram[0].size =  gd->ram_size;
-}
-void dram_init_banksize(void)
-	__attribute__((weak, alias("__dram_init_banksize")));
-
-init_fnc_t *init_sequence[] = {
-#if defined(CONFIG_ARCH_CPU_INIT)
-	arch_cpu_init,		/* basic arch cpu dependent setup */
-#endif
-#if defined(CONFIG_BOARD_EARLY_INIT_F)
-	board_early_init_f,
-#endif
-	timer_init,		/* initialize timer */
-#ifdef CONFIG_FSL_ESDHC
-	get_clocks,
-#endif
-	env_init,		/* initialize environment */
-	init_baudrate,		/* initialze baudrate settings */
-	serial_init,		/* serial communications setup */
-	console_init_f,		/* stage 1 init of console */
-	display_banner,		/* say that we are here */
-#if defined(CONFIG_DISPLAY_CPUINFO)
-	print_cpuinfo,		/* display cpu info (and speed) */
-#endif
-#if defined(CONFIG_DISPLAY_BOARDINFO)
-	checkboard,		/* display board info */
-#endif
-#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C)
-	init_func_i2c,
-#endif
-	dram_init,		/* configure available RAM banks */
-#if defined(CONFIG_CMD_PCI) || defined (CONFIG_PCI)
-	arm_pci_init,
-#endif
-	NULL,
-};
-
-void board_init_f (ulong bootflag)
-{
-	bd_t *bd;
-	init_fnc_t **init_fnc_ptr;
-	gd_t *id;
-	ulong addr, addr_sp;
-
-	/* Pointer is writable since we allocated a register for it */
-	gd = (gd_t *) ((CONFIG_SYS_INIT_SP_ADDR) & ~0x07);
-	/* compiler optimization barrier needed for GCC >= 3.4 */
-	__asm__ __volatile__("": : :"memory");
-
-	memset ((void*)gd, 0, sizeof (gd_t));
-
-	gd->mon_len = _bss_end_ofs;
-
-	for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) {
-		if ((*init_fnc_ptr)() != 0) {
-			hang ();
-		}
-	}
-
-	debug ("monitor len: %08lX\n", gd->mon_len);
-	/*
-	 * Ram is setup, size stored in gd !!
-	 */
-	debug ("ramsize: %08lX\n", gd->ram_size);
-#if defined(CONFIG_SYS_MEM_TOP_HIDE)
-	/*
-	 * Subtract specified amount of memory to hide so that it won't
-	 * get "touched" at all by U-Boot. By fixing up gd->ram_size
-	 * the Linux kernel should now get passed the now "corrected"
-	 * memory size and won't touch it either. This should work
-	 * for arch/ppc and arch/powerpc. Only Linux board ports in
-	 * arch/powerpc with bootwrapper support, that recalculate the
-	 * memory size from the SDRAM controller setup will have to
-	 * get fixed.
-	 */
-	gd->ram_size -= CONFIG_SYS_MEM_TOP_HIDE;
-#endif
-
-	addr = CONFIG_SYS_SDRAM_BASE + gd->ram_size;
-
-#ifdef CONFIG_LOGBUFFER
-#ifndef CONFIG_ALT_LB_ADDR
-	/* reserve kernel log buffer */
-	addr -= (LOGBUFF_RESERVE);
-	debug ("Reserving %dk for kernel logbuffer at %08lx\n", LOGBUFF_LEN, addr);
-#endif
-#endif
-
-#ifdef CONFIG_PRAM
-	/*
-	 * reserve protected RAM
-	 */
-	i = getenv_r ("pram", (char *)tmp, sizeof (tmp));
-	reg = (i > 0) ? simple_strtoul ((const char *)tmp, NULL, 10) : CONFIG_PRAM;
-	addr -= (reg << 10);		/* size is in kB */
-	debug ("Reserving %ldk for protected RAM at %08lx\n", reg, addr);
-#endif /* CONFIG_PRAM */
-
-#if !(defined(CONFIG_SYS_NO_ICACHE) && defined(CONFIG_SYS_NO_DCACHE))
-	/* reserve TLB table */
-	addr -= (4096 * 4);
-
-	/* round down to next 64 kB limit */
-	addr &= ~(0x10000 - 1);
-
-	gd->tlb_addr = addr;
-	debug ("TLB table at: %08lx\n", addr);
-#endif
-
-	/* round down to next 4 kB limit */
-	addr &= ~(4096 - 1);
-	debug ("Top of RAM usable for U-Boot at: %08lx\n", addr);
-
-#ifdef CONFIG_VFD
-#	ifndef PAGE_SIZE
-#	  define PAGE_SIZE 4096
-#	endif
-	/*
-	 * reserve memory for VFD display (always full pages)
-	 */
-	addr -= vfd_setmem (addr);
-	gd->fb_base = addr;
-#endif /* CONFIG_VFD */
-
-#ifdef CONFIG_LCD
-	/* reserve memory for LCD display (always full pages) */
-	addr = lcd_setmem (addr);
-	gd->fb_base = addr;
-#endif /* CONFIG_LCD */
-
-	/*
-	 * reserve memory for U-Boot code, data & bss
-	 * round down to next 4 kB limit
-	 */
-	addr -= gd->mon_len;
-	addr &= ~(4096 - 1);
-
-	debug ("Reserving %ldk for U-Boot at: %08lx\n", gd->mon_len >> 10, addr);
-
-#ifndef CONFIG_PRELOADER
-	/*
-	 * reserve memory for malloc() arena
-	 */
-	addr_sp = addr - TOTAL_MALLOC_LEN;
-	debug ("Reserving %dk for malloc() at: %08lx\n",
-			TOTAL_MALLOC_LEN >> 10, addr_sp);
-	/*
-	 * (permanently) allocate a Board Info struct
-	 * and a permanent copy of the "global" data
-	 */
-	addr_sp -= sizeof (bd_t);
-	bd = (bd_t *) addr_sp;
-	gd->bd = bd;
-	debug ("Reserving %zu Bytes for Board Info at: %08lx\n",
-			sizeof (bd_t), addr_sp);
-	addr_sp -= sizeof (gd_t);
-	id = (gd_t *) addr_sp;
-	debug ("Reserving %zu Bytes for Global Data at: %08lx\n",
-			sizeof (gd_t), addr_sp);
-
-	/* setup stackpointer for exeptions */
-	gd->irq_sp = addr_sp;
-#ifdef CONFIG_USE_IRQ
-	addr_sp -= (CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ);
-	debug ("Reserving %zu Bytes for IRQ stack at: %08lx\n",
-		CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ, addr_sp);
-#endif
-	/* leave 3 words for abort-stack    */
-	addr_sp -= 3;
-
-	/* 8-byte alignment for ABI compliance */
-	addr_sp &= ~0x07;
-#else
-	addr_sp += 128;	/* leave 32 words for abort-stack   */
-	gd->irq_sp = addr_sp;
-#endif
-
-	debug ("New Stack Pointer is: %08lx\n", addr_sp);
-
-#ifdef CONFIG_POST
-	post_bootmode_init();
-	post_run (NULL, POST_ROM | post_bootmode_get(0));
-#endif
-
-	gd->bd->bi_baudrate = gd->baudrate;
-	/* Ram ist board specific, so move it to board code ... */
-	dram_init_banksize();
-	display_dram_config();	/* and display it */
-
-	gd->relocaddr = addr;
-	gd->start_addr_sp = addr_sp;
-	gd->reloc_off = addr - _TEXT_BASE;
-	debug ("relocation Offset is: %08lx\n", gd->reloc_off);
-	memcpy (id, (void *)gd, sizeof (gd_t));
-
-	relocate_code (addr_sp, id, addr);
-
-	/* NOTREACHED - relocate_code() does not return */
-}
-
-#if !defined(CONFIG_SYS_NO_FLASH)
-static char *failed = "*** failed ***\n";
-#endif
-
-/************************************************************************
- *
- * This is the next part if the initialization sequence: we are now
- * running from RAM and have a "normal" C environment, i. e. global
- * data can be written, BSS has been cleared, the stack size in not
- * that critical any more, etc.
- *
- ************************************************************************
- */
-
-void board_init_r (gd_t *id, ulong dest_addr)
-{
-	char *s;
-	bd_t *bd;
-	ulong malloc_start;
-#if !defined(CONFIG_SYS_NO_FLASH)
-	ulong flash_size;
-#endif
-
-	gd = id;
-	bd = gd->bd;
-
-	gd->flags |= GD_FLG_RELOC;	/* tell others: relocation done */
-
-	monitor_flash_len = _bss_start_ofs;
-	debug ("monitor flash len: %08lX\n", monitor_flash_len);
-	board_init();	/* Setup chipselects */
-
-#ifdef CONFIG_SERIAL_MULTI
-	serial_initialize();
-#endif
-
-	debug ("Now running in RAM - U-Boot at: %08lx\n", dest_addr);
-
-#ifdef CONFIG_LOGBUFFER
-	logbuff_init_ptrs ();
-#endif
-#ifdef CONFIG_POST
-	post_output_backlog ();
-#endif
-
-	/* The Malloc area is immediately below the monitor copy in DRAM */
-	malloc_start = dest_addr - TOTAL_MALLOC_LEN;
-	mem_malloc_init (malloc_start, TOTAL_MALLOC_LEN);
-
-#if !defined(CONFIG_SYS_NO_FLASH)
-	puts ("Flash: ");
-
-	if ((flash_size = flash_init ()) > 0) {
-# ifdef CONFIG_SYS_FLASH_CHECKSUM
-		print_size (flash_size, "");
-		/*
-		 * Compute and print flash CRC if flashchecksum is set to 'y'
-		 *
-		 * NOTE: Maybe we should add some WATCHDOG_RESET()? XXX
-		 */
-		s = getenv ("flashchecksum");
-		if (s && (*s == 'y')) {
-			printf ("  CRC: %08X",
-				crc32 (0, (const unsigned char *) CONFIG_SYS_FLASH_BASE, flash_size)
-			);
-		}
-		putc ('\n');
-# else	/* !CONFIG_SYS_FLASH_CHECKSUM */
-		print_size (flash_size, "\n");
-# endif /* CONFIG_SYS_FLASH_CHECKSUM */
-	} else {
-		puts (failed);
-		hang ();
-	}
-#endif
-
-#if defined(CONFIG_CMD_NAND)
-	puts ("NAND:  ");
-	nand_init();		/* go init the NAND */
-#endif
-
-#if defined(CONFIG_CMD_ONENAND)
-	onenand_init();
-#endif
-
-#ifdef CONFIG_GENERIC_MMC
-       puts("MMC:   ");
-       mmc_initialize(bd);
-#endif
-
-#ifdef CONFIG_HAS_DATAFLASH
-	AT91F_DataflashInit();
-	dataflash_print_info();
-#endif
-
-	/* initialize environment */
-	env_relocate ();
-
-#ifdef CONFIG_VFD
-	/* must do this after the framebuffer is allocated */
-	drv_vfd_init();
-#endif /* CONFIG_VFD */
-
-	/* IP Address */
-	gd->bd->bi_ip_addr = getenv_IPaddr ("ipaddr");
-
-	stdio_init ();	/* get the devices list going. */
-
-	jumptable_init ();
-
-#if defined(CONFIG_API)
-	/* Initialize API */
-	api_init ();
-#endif
-
-	console_init_r ();	/* fully init console as a device */
-
-#if defined(CONFIG_ARCH_MISC_INIT)
-	/* miscellaneous arch dependent initialisations */
-	arch_misc_init ();
-#endif
-#if defined(CONFIG_MISC_INIT_R)
-	/* miscellaneous platform dependent initialisations */
-	misc_init_r ();
-#endif
-
-	 /* set up exceptions */
-	interrupt_init ();
-	/* enable exceptions */
-	enable_interrupts ();
-
-	/* Perform network card initialisation if necessary */
-#if defined(CONFIG_DRIVER_SMC91111) || defined (CONFIG_DRIVER_LAN91C96)
-	/* XXX: this needs to be moved to board init */
-	if (getenv ("ethaddr")) {
-		uchar enetaddr[6];
-		eth_getenv_enetaddr("ethaddr", enetaddr);
-		smc_set_mac_addr(enetaddr);
-	}
-#endif /* CONFIG_DRIVER_SMC91111 || CONFIG_DRIVER_LAN91C96 */
-
-	/* Initialize from environment */
-	if ((s = getenv ("loadaddr")) != NULL) {
-		load_addr = simple_strtoul (s, NULL, 16);
-	}
-#if defined(CONFIG_CMD_NET)
-	if ((s = getenv ("bootfile")) != NULL) {
-		copy_filename (BootFile, s, sizeof (BootFile));
-	}
-#endif
-
-#ifdef BOARD_LATE_INIT
-	board_late_init ();
-#endif
-
-#ifdef CONFIG_BITBANGMII
-	bb_miiphy_init();
-#endif
-#if defined(CONFIG_CMD_NET)
-#if defined(CONFIG_NET_MULTI)
-	puts ("Net:   ");
-#endif
-	eth_initialize(gd->bd);
-#if defined(CONFIG_RESET_PHY_R)
-	debug ("Reset Ethernet PHY\n");
-	reset_phy();
-#endif
-#endif
-
-#ifdef CONFIG_POST
-	post_run (NULL, POST_RAM | post_bootmode_get(0));
-#endif
-
-#if defined(CONFIG_PRAM) || defined(CONFIG_LOGBUFFER)
-	/*
-	 * Export available size of memory for Linux,
-	 * taking into account the protected RAM at top of memory
-	 */
-	{
-		ulong pram;
-		uchar memsz[32];
-#ifdef CONFIG_PRAM
-		char *s;
-
-		if ((s = getenv ("pram")) != NULL) {
-			pram = simple_strtoul (s, NULL, 10);
-		} else {
-			pram = CONFIG_PRAM;
-		}
-#else
-		pram=0;
-#endif
-#ifdef CONFIG_LOGBUFFER
-#ifndef CONFIG_ALT_LB_ADDR
-		/* Also take the logbuffer into account (pram is in kB) */
-		pram += (LOGBUFF_LEN+LOGBUFF_OVERHEAD)/1024;
-#endif
-#endif
-		sprintf ((char *)memsz, "%ldk", (bd->bi_memsize / 1024) - pram);
-		setenv ("mem", (char *)memsz);
-	}
-#endif
-
-	/* main_loop() can return to retry autoboot, if so just run it again. */
-	for (;;) {
-		main_loop ();
-	}
-
-	/* NOTREACHED - no way out of command loop except booting */
-}
-
-void hang (void)
-{
-	puts ("### ERROR ### Please RESET the board ###\n");
-	for (;;);
-}
diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c
deleted file mode 100644
index 7734953..0000000
--- a/arch/arm/lib/bootm.c
+++ /dev/null
@@ -1,343 +0,0 @@
-/*
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * Copyright (C) 2001  Erik Mouw (J.A.K.Mouw@its.tudelft.nl)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307	 USA
- *
- */
-
-#include <common.h>
-#include <command.h>
-#include <image.h>
-#include <u-boot/zlib.h>
-#include <asm/byteorder.h>
-#include <fdt.h>
-#include <libfdt.h>
-#include <fdt_support.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#if defined (CONFIG_SETUP_MEMORY_TAGS) || \
-    defined (CONFIG_CMDLINE_TAG) || \
-    defined (CONFIG_INITRD_TAG) || \
-    defined (CONFIG_SERIAL_TAG) || \
-    defined (CONFIG_REVISION_TAG)
-static void setup_start_tag (bd_t *bd);
-
-# ifdef CONFIG_SETUP_MEMORY_TAGS
-static void setup_memory_tags (bd_t *bd);
-# endif
-static void setup_commandline_tag (bd_t *bd, char *commandline);
-
-# ifdef CONFIG_INITRD_TAG
-static void setup_initrd_tag (bd_t *bd, ulong initrd_start,
-			      ulong initrd_end);
-# endif
-static void setup_end_tag (bd_t *bd);
-
-static struct tag *params;
-#endif /* CONFIG_SETUP_MEMORY_TAGS || CONFIG_CMDLINE_TAG || CONFIG_INITRD_TAG */
-
-static ulong get_sp(void);
-#if defined(CONFIG_OF_LIBFDT)
-static int bootm_linux_fdt(int machid, bootm_headers_t *images);
-#endif
-
-void arch_lmb_reserve(struct lmb *lmb)
-{
-	ulong sp;
-
-	/*
-	 * Booting a (Linux) kernel image
-	 *
-	 * Allocate space for command line and board info - the
-	 * address should be as high as possible within the reach of
-	 * the kernel (see CONFIG_SYS_BOOTMAPSZ settings), but in unused
-	 * memory, which means far enough below the current stack
-	 * pointer.
-	 */
-	sp = get_sp();
-	debug("## Current stack ends at 0x%08lx ", sp);
-
-	/* adjust sp by 1K to be safe */
-	sp -= 1024;
-	lmb_reserve(lmb, sp,
-		    gd->bd->bi_dram[0].start + gd->bd->bi_dram[0].size - sp);
-}
-
-static void announce_and_cleanup(void)
-{
-	printf("\nStarting kernel ...\n\n");
-
-#ifdef CONFIG_USB_DEVICE
-	{
-		extern void udc_disconnect(void);
-		udc_disconnect();
-	}
-#endif
-	cleanup_before_linux();
-}
-
-int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images)
-{
-	bd_t	*bd = gd->bd;
-	char	*s;
-	int	machid = bd->bi_arch_number;
-	void	(*kernel_entry)(int zero, int arch, uint params);
-
-#ifdef CONFIG_CMDLINE_TAG
-	char *commandline = getenv ("bootargs");
-#endif
-
-	if ((flag != 0) && (flag != BOOTM_STATE_OS_GO))
-		return 1;
-
-	s = getenv ("machid");
-	if (s) {
-		machid = simple_strtoul (s, NULL, 16);
-		printf ("Using machid 0x%x from environment\n", machid);
-	}
-
-	show_boot_progress (15);
-
-#ifdef CONFIG_OF_LIBFDT
-	if (images->ft_len)
-		return bootm_linux_fdt(machid, images);
-#endif
-
-	kernel_entry = (void (*)(int, int, uint))images->ep;
-
-	debug ("## Transferring control to Linux (at address %08lx) ...\n",
-	       (ulong) kernel_entry);
-
-#if defined (CONFIG_SETUP_MEMORY_TAGS) || \
-    defined (CONFIG_CMDLINE_TAG) || \
-    defined (CONFIG_INITRD_TAG) || \
-    defined (CONFIG_SERIAL_TAG) || \
-    defined (CONFIG_REVISION_TAG)
-	setup_start_tag (bd);
-#ifdef CONFIG_SERIAL_TAG
-	setup_serial_tag (&params);
-#endif
-#ifdef CONFIG_REVISION_TAG
-	setup_revision_tag (&params);
-#endif
-#ifdef CONFIG_SETUP_MEMORY_TAGS
-	setup_memory_tags (bd);
-#endif
-#ifdef CONFIG_CMDLINE_TAG
-	setup_commandline_tag (bd, commandline);
-#endif
-#ifdef CONFIG_INITRD_TAG
-	if (images->rd_start && images->rd_end)
-		setup_initrd_tag (bd, images->rd_start, images->rd_end);
-#endif
-	setup_end_tag(bd);
-#endif
-
-	announce_and_cleanup();
-
-	kernel_entry(0, machid, bd->bi_boot_params);
-	/* does not return */
-
-	return 1;
-}
-
-#if defined(CONFIG_OF_LIBFDT)
-static int fixup_memory_node(void *blob)
-{
-	bd_t	*bd = gd->bd;
-	int bank;
-	u64 start[CONFIG_NR_DRAM_BANKS];
-	u64 size[CONFIG_NR_DRAM_BANKS];
-
-	for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
-		start[bank] = bd->bi_dram[bank].start;
-		size[bank] = bd->bi_dram[bank].size;
-	}
-
-	return fdt_fixup_memory_banks(blob, start, size, CONFIG_NR_DRAM_BANKS);
-}
-
-static int bootm_linux_fdt(int machid, bootm_headers_t *images)
-{
-	ulong rd_len;
-	void (*kernel_entry)(int zero, int dt_machid, void *dtblob);
-	ulong bootmap_base = getenv_bootm_low();
-	ulong of_size = images->ft_len;
-	char **of_flat_tree = &images->ft_addr;
-	ulong *initrd_start = &images->initrd_start;
-	ulong *initrd_end = &images->initrd_end;
-	struct lmb *lmb = &images->lmb;
-	int ret;
-
-	kernel_entry = (void (*)(int, int, void *))images->ep;
-
-	rd_len = images->rd_end - images->rd_start;
-	ret = boot_ramdisk_high(lmb, images->rd_start, rd_len,
-				initrd_start, initrd_end);
-	if (ret)
-		return ret;
-
-	ret = boot_relocate_fdt(lmb, bootmap_base, of_flat_tree, &of_size);
-	if (ret)
-		return ret;
-
-	debug("## Transferring control to Linux (at address %08lx) ...\n",
-	       (ulong) kernel_entry);
-
-	fdt_chosen(*of_flat_tree, 1);
-
-	fixup_memory_node(*of_flat_tree);
-
-	fdt_initrd(*of_flat_tree, *initrd_start, *initrd_end, 1);
-
-	announce_and_cleanup();
-
-	kernel_entry(0, machid, *of_flat_tree);
-	/* does not return */
-
-	return 1;
-}
-#endif
-
-#if defined (CONFIG_SETUP_MEMORY_TAGS) || \
-    defined (CONFIG_CMDLINE_TAG) || \
-    defined (CONFIG_INITRD_TAG) || \
-    defined (CONFIG_SERIAL_TAG) || \
-    defined (CONFIG_REVISION_TAG)
-static void setup_start_tag (bd_t *bd)
-{
-	params = (struct tag *) bd->bi_boot_params;
-
-	params->hdr.tag = ATAG_CORE;
-	params->hdr.size = tag_size (tag_core);
-
-	params->u.core.flags = 0;
-	params->u.core.pagesize = 0;
-	params->u.core.rootdev = 0;
-
-	params = tag_next (params);
-}
-
-
-#ifdef CONFIG_SETUP_MEMORY_TAGS
-static void setup_memory_tags (bd_t *bd)
-{
-	int i;
-
-	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
-		params->hdr.tag = ATAG_MEM;
-		params->hdr.size = tag_size (tag_mem32);
-
-		params->u.mem.start = bd->bi_dram[i].start;
-		params->u.mem.size = bd->bi_dram[i].size;
-
-		params = tag_next (params);
-	}
-}
-#endif /* CONFIG_SETUP_MEMORY_TAGS */
-
-
-static void setup_commandline_tag (bd_t *bd, char *commandline)
-{
-	char *p;
-
-	if (!commandline)
-		return;
-
-	/* eat leading white space */
-	for (p = commandline; *p == ' '; p++);
-
-	/* skip non-existent command lines so the kernel will still
-	 * use its default command line.
-	 */
-	if (*p == '\0')
-		return;
-
-	params->hdr.tag = ATAG_CMDLINE;
-	params->hdr.size =
-		(sizeof (struct tag_header) + strlen (p) + 1 + 4) >> 2;
-
-	strcpy (params->u.cmdline.cmdline, p);
-
-	params = tag_next (params);
-}
-
-
-#ifdef CONFIG_INITRD_TAG
-static void setup_initrd_tag (bd_t *bd, ulong initrd_start, ulong initrd_end)
-{
-	/* an ATAG_INITRD node tells the kernel where the compressed
-	 * ramdisk can be found. ATAG_RDIMG is a better name, actually.
-	 */
-	params->hdr.tag = ATAG_INITRD2;
-	params->hdr.size = tag_size (tag_initrd);
-
-	params->u.initrd.start = initrd_start;
-	params->u.initrd.size = initrd_end - initrd_start;
-
-	params = tag_next (params);
-}
-#endif /* CONFIG_INITRD_TAG */
-
-#ifdef CONFIG_SERIAL_TAG
-void setup_serial_tag (struct tag **tmp)
-{
-	struct tag *params = *tmp;
-	struct tag_serialnr serialnr;
-	void get_board_serial(struct tag_serialnr *serialnr);
-
-	get_board_serial(&serialnr);
-	params->hdr.tag = ATAG_SERIAL;
-	params->hdr.size = tag_size (tag_serialnr);
-	params->u.serialnr.low = serialnr.low;
-	params->u.serialnr.high= serialnr.high;
-	params = tag_next (params);
-	*tmp = params;
-}
-#endif
-
-#ifdef CONFIG_REVISION_TAG
-void setup_revision_tag(struct tag **in_params)
-{
-	u32 rev = 0;
-	u32 get_board_rev(void);
-
-	rev = get_board_rev();
-	params->hdr.tag = ATAG_REVISION;
-	params->hdr.size = tag_size (tag_revision);
-	params->u.revision.rev = rev;
-	params = tag_next (params);
-}
-#endif  /* CONFIG_REVISION_TAG */
-
-static void setup_end_tag (bd_t *bd)
-{
-	params->hdr.tag = ATAG_NONE;
-	params->hdr.size = 0;
-}
-#endif /* CONFIG_SETUP_MEMORY_TAGS || CONFIG_CMDLINE_TAG || CONFIG_INITRD_TAG */
-
-static ulong get_sp(void)
-{
-	ulong ret;
-
-	asm("mov %0, sp" : "=r"(ret) : );
-	return ret;
-}
diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c
deleted file mode 100644
index d9175f0..0000000
--- a/arch/arm/lib/cache-cp15.c
+++ /dev/null
@@ -1,183 +0,0 @@
-/*
- * (C) Copyright 2002
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/system.h>
-
-#if !(defined(CONFIG_SYS_NO_ICACHE) && defined(CONFIG_SYS_NO_DCACHE))
-
-#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
-#define CACHE_SETUP	0x1a
-#else
-#define CACHE_SETUP	0x1e
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static void cp_delay (void)
-{
-	volatile int i;
-
-	/* copro seems to need some delay between reading and writing */
-	for (i = 0; i < 100; i++)
-		nop();
-	asm volatile("" : : : "memory");
-}
-
-static inline void dram_bank_mmu_setup(int bank)
-{
-	u32 *page_table = (u32 *)gd->tlb_addr;
-	bd_t *bd = gd->bd;
-	int	i;
-
-	debug("%s: bank: %d\n", __func__, bank);
-	for (i = bd->bi_dram[bank].start >> 20;
-	     i < (bd->bi_dram[bank].start + bd->bi_dram[bank].size) >> 20;
-	     i++) {
-		page_table[i] = i << 20 | (3 << 10) | CACHE_SETUP;
-	}
-}
-
-/* to activate the MMU we need to set up virtual memory: use 1M areas */
-static inline void mmu_setup(void)
-{
-	u32 *page_table = (u32 *)gd->tlb_addr;
-	int i;
-	u32 reg;
-
-	/* Set up an identity-mapping for all 4GB, rw for everyone */
-	for (i = 0; i < 4096; i++)
-		page_table[i] = i << 20 | (3 << 10) | 0x12;
-
-	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
-		dram_bank_mmu_setup(i);
-	}
-
-	/* Copy the page table address to cp15 */
-	asm volatile("mcr p15, 0, %0, c2, c0, 0"
-		     : : "r" (page_table) : "memory");
-	/* Set the access control to all-supervisor */
-	asm volatile("mcr p15, 0, %0, c3, c0, 0"
-		     : : "r" (~0));
-	/* and enable the mmu */
-	reg = get_cr();	/* get control reg. */
-	cp_delay();
-	set_cr(reg | CR_M);
-}
-
-/* cache_bit must be either CR_I or CR_C */
-static void cache_enable(uint32_t cache_bit)
-{
-	uint32_t reg;
-
-	/* The data cache is not active unless the mmu is enabled too */
-	if (cache_bit == CR_C)
-		mmu_setup();
-	reg = get_cr();	/* get control reg. */
-	cp_delay();
-	set_cr(reg | cache_bit);
-}
-
-/* cache_bit must be either CR_I or CR_C */
-static void cache_disable(uint32_t cache_bit)
-{
-	uint32_t reg;
-
-	if (cache_bit == CR_C) {
-		/* if cache isn;t enabled no need to disable */
-		reg = get_cr();
-		if ((reg & CR_C) != CR_C)
-			return;
-		/* if disabling data cache, disable mmu too */
-		cache_bit |= CR_M;
-		flush_cache(0, ~0);
-	}
-	reg = get_cr();
-	cp_delay();
-	set_cr(reg & ~cache_bit);
-}
-#endif
-
-#ifdef CONFIG_SYS_NO_ICACHE
-void icache_enable (void)
-{
-	return;
-}
-
-void icache_disable (void)
-{
-	return;
-}
-
-int icache_status (void)
-{
-	return 0;					/* always off */
-}
-#else
-void icache_enable(void)
-{
-	cache_enable(CR_I);
-}
-
-void icache_disable(void)
-{
-	cache_disable(CR_I);
-}
-
-int icache_status(void)
-{
-	return (get_cr() & CR_I) != 0;
-}
-#endif
-
-#ifdef CONFIG_SYS_NO_DCACHE
-void dcache_enable (void)
-{
-	return;
-}
-
-void dcache_disable (void)
-{
-	return;
-}
-
-int dcache_status (void)
-{
-	return 0;					/* always off */
-}
-#else
-void dcache_enable(void)
-{
-	cache_enable(CR_C);
-}
-
-void dcache_disable(void)
-{
-	cache_disable(CR_C);
-}
-
-int dcache_status(void)
-{
-	return (get_cr() & CR_C) != 0;
-}
-#endif
diff --git a/arch/arm/lib/cache.c b/arch/arm/lib/cache.c
deleted file mode 100644
index 30686fe..0000000
--- a/arch/arm/lib/cache.c
+++ /dev/null
@@ -1,47 +0,0 @@
-/*
- * (C) Copyright 2002
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/* for now: just dummy functions to satisfy the linker */
-
-#include <common.h>
-
-void  flush_cache (unsigned long dummy1, unsigned long dummy2)
-{
-#if defined(CONFIG_OMAP2420) || defined(CONFIG_ARM1136)
-	void arm1136_cache_flush(void);
-
-	arm1136_cache_flush();
-#endif
-#ifdef CONFIG_ARM926EJS
-	/* test and clean, page 2-23 of arm926ejs manual */
-	asm("0: mrc p15, 0, r15, c7, c10, 3\n\t" "bne 0b\n" : : : "memory");
-	/* disable write buffer as well (page 2-22) */
-	asm("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
-#endif
-#ifdef CONFIG_OMAP34XX
-	void v7_flush_cache_all(void);
-
-	v7_flush_cache_all();
-#endif
-	return;
-}
diff --git a/arch/arm/lib/div0.c b/arch/arm/lib/div0.c
deleted file mode 100644
index 6267bf1..0000000
--- a/arch/arm/lib/div0.c
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * (C) Copyright 2002
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/* Replacement (=dummy) for GNU/Linux division-by zero handler */
-void __div0 (void)
-{
-	extern void hang (void);
-
-	hang();
-}
diff --git a/arch/arm/lib/eabi_compat.c b/arch/arm/lib/eabi_compat.c
deleted file mode 100644
index eb3e26d..0000000
--- a/arch/arm/lib/eabi_compat.c
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * Utility functions needed for (some) EABI conformant tool chains.
- *
- * (C) Copyright 2009 Wolfgang Denk <wd@denx.de>
- *
- * This program is Free Software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- */
-
-#include <common.h>
-
-int raise (int signum)
-{
-	printf("raise: Signal # %d caught\n", signum);
-	return 0;
-}
-
-/* Dummy function to avoid linker complaints */
-void __aeabi_unwind_cpp_pr0(void)
-{
-};
diff --git a/arch/arm/lib/interrupts.c b/arch/arm/lib/interrupts.c
deleted file mode 100644
index 74ff5ce..0000000
--- a/arch/arm/lib/interrupts.c
+++ /dev/null
@@ -1,198 +0,0 @@
-/*
- * (C) Copyright 2003
- * Texas Instruments <www.ti.com>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Alex Zuepke <azu@sysgo.de>
- *
- * (C) Copyright 2002-2004
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * (C) Copyright 2004
- * Philippe Robin, ARM Ltd. <philippe.robin@arm.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/proc-armv/ptrace.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#ifdef CONFIG_USE_IRQ
-int interrupt_init (void)
-{
-	/*
-	 * setup up stacks if necessary
-	 */
-	IRQ_STACK_START = gd->irq_sp - 4;
-	IRQ_STACK_START_IN = gd->irq_sp + 8;
-	FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ;
-
-	return arch_interrupt_init();
-}
-
-/* enable IRQ interrupts */
-void enable_interrupts (void)
-{
-	unsigned long temp;
-	__asm__ __volatile__("mrs %0, cpsr\n"
-			     "bic %0, %0, #0x80\n"
-			     "msr cpsr_c, %0"
-			     : "=r" (temp)
-			     :
-			     : "memory");
-}
-
-
-/*
- * disable IRQ/FIQ interrupts
- * returns true if interrupts had been enabled before we disabled them
- */
-int disable_interrupts (void)
-{
-	unsigned long old,temp;
-	__asm__ __volatile__("mrs %0, cpsr\n"
-			     "orr %1, %0, #0xc0\n"
-			     "msr cpsr_c, %1"
-			     : "=r" (old), "=r" (temp)
-			     :
-			     : "memory");
-	return (old & 0x80) == 0;
-}
-#else
-int interrupt_init (void)
-{
-	/*
-	 * setup up stacks if necessary
-	 */
-	IRQ_STACK_START_IN = gd->irq_sp + 8;
-
-	return 0;
-}
-
-void enable_interrupts (void)
-{
-	return;
-}
-int disable_interrupts (void)
-{
-	return 0;
-}
-#endif
-
-
-void bad_mode (void)
-{
-	panic ("Resetting CPU ...\n");
-	reset_cpu (0);
-}
-
-void show_regs (struct pt_regs *regs)
-{
-	unsigned long flags;
-	const char *processor_modes[] = {
-	"USER_26",	"FIQ_26",	"IRQ_26",	"SVC_26",
-	"UK4_26",	"UK5_26",	"UK6_26",	"UK7_26",
-	"UK8_26",	"UK9_26",	"UK10_26",	"UK11_26",
-	"UK12_26",	"UK13_26",	"UK14_26",	"UK15_26",
-	"USER_32",	"FIQ_32",	"IRQ_32",	"SVC_32",
-	"UK4_32",	"UK5_32",	"UK6_32",	"ABT_32",
-	"UK8_32",	"UK9_32",	"UK10_32",	"UND_32",
-	"UK12_32",	"UK13_32",	"UK14_32",	"SYS_32",
-	};
-
-	flags = condition_codes (regs);
-
-	printf ("pc : [<%08lx>]	   lr : [<%08lx>]\n"
-		"sp : %08lx  ip : %08lx	 fp : %08lx\n",
-		instruction_pointer (regs),
-		regs->ARM_lr, regs->ARM_sp, regs->ARM_ip, regs->ARM_fp);
-	printf ("r10: %08lx  r9 : %08lx	 r8 : %08lx\n",
-		regs->ARM_r10, regs->ARM_r9, regs->ARM_r8);
-	printf ("r7 : %08lx  r6 : %08lx	 r5 : %08lx  r4 : %08lx\n",
-		regs->ARM_r7, regs->ARM_r6, regs->ARM_r5, regs->ARM_r4);
-	printf ("r3 : %08lx  r2 : %08lx	 r1 : %08lx  r0 : %08lx\n",
-		regs->ARM_r3, regs->ARM_r2, regs->ARM_r1, regs->ARM_r0);
-	printf ("Flags: %c%c%c%c",
-		flags & CC_N_BIT ? 'N' : 'n',
-		flags & CC_Z_BIT ? 'Z' : 'z',
-		flags & CC_C_BIT ? 'C' : 'c', flags & CC_V_BIT ? 'V' : 'v');
-	printf ("  IRQs %s  FIQs %s  Mode %s%s\n",
-		interrupts_enabled (regs) ? "on" : "off",
-		fast_interrupts_enabled (regs) ? "on" : "off",
-		processor_modes[processor_mode (regs)],
-		thumb_mode (regs) ? " (T)" : "");
-}
-
-void do_undefined_instruction (struct pt_regs *pt_regs)
-{
-	printf ("undefined instruction\n");
-	show_regs (pt_regs);
-	bad_mode ();
-}
-
-void do_software_interrupt (struct pt_regs *pt_regs)
-{
-	printf ("software interrupt\n");
-	show_regs (pt_regs);
-	bad_mode ();
-}
-
-void do_prefetch_abort (struct pt_regs *pt_regs)
-{
-	printf ("prefetch abort\n");
-	show_regs (pt_regs);
-	bad_mode ();
-}
-
-void do_data_abort (struct pt_regs *pt_regs)
-{
-	printf ("data abort\n");
-	show_regs (pt_regs);
-	bad_mode ();
-}
-
-void do_not_used (struct pt_regs *pt_regs)
-{
-	printf ("not used\n");
-	show_regs (pt_regs);
-	bad_mode ();
-}
-
-void do_fiq (struct pt_regs *pt_regs)
-{
-	printf ("fast interrupt request\n");
-	show_regs (pt_regs);
-	bad_mode ();
-}
-
-#ifndef CONFIG_USE_IRQ
-void do_irq (struct pt_regs *pt_regs)
-{
-	printf ("interrupt request\n");
-	show_regs (pt_regs);
-	bad_mode ();
-}
-#endif
diff --git a/arch/arm/lib/reset.c b/arch/arm/lib/reset.c
deleted file mode 100644
index 08e6acb..0000000
--- a/arch/arm/lib/reset.c
+++ /dev/null
@@ -1,53 +0,0 @@
-/*
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Alex Zuepke <azu@sysgo.de>
- *
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * (C) Copyright 2004
- * DAVE Srl
- * http://www.dave-tech.it
- * http://www.wawnet.biz
- * mailto:info@wawnet.biz
- *
- * (C) Copyright 2004 Texas Insturments
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-
-int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-	puts ("resetting ...\n");
-
-	udelay (50000);				/* wait 50 ms */
-
-	disable_interrupts();
-	reset_cpu(0);
-
-	/*NOTREACHED*/
-	return 0;
-}