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| author | wdenk <wdenk> | 2003-07-17 23:16:40 +0000 |
|---|---|---|
| committer | wdenk <wdenk> | 2003-07-17 23:16:40 +0000 |
| commit | 2535d60277cc295adf75cd5721dcecd840c69a63 (patch) | |
| tree | a4a7c42580ded1e631658cec4f7a26d8e677a342 /board/lantec | |
| parent | 945af8d723a29e9b6289d84250745ed0dc16fc81 (diff) | |
| download | bootable_bootloader_goldelico_gta04-2535d60277cc295adf75cd5721dcecd840c69a63.zip bootable_bootloader_goldelico_gta04-2535d60277cc295adf75cd5721dcecd840c69a63.tar.gz bootable_bootloader_goldelico_gta04-2535d60277cc295adf75cd5721dcecd840c69a63.tar.bz2 | |
* Patch by Martin Krause, 17 Jul 2003:
add delay to get I2C working with "imm" command and s3c24x0_i2c.c
* Patch by Richard Woodruff, 17 July 03:
- Fixed bug in OMAP1510 baud rate divisor settings.
* Patch by Nye Liu, 16 July 2003:
MPC860FADS fixes:
- add MPC86xADS support (uses MPC86xADS.h)
- add 866P/T core support (also MPC859T/MPC859DSL/MPC852T)
o PLPRCR changes
o BRG changes (EXTAL/XTAL restricted to 10MHz)
o don't trust gclk() software measurement by default, depend on
CONFIG_8xx_GCLK_FREQ
- add DRAM SIMM not installed detection
- use more "correct" SDRAM initialization sequence
- allow different SDRAM sizes (8xxADS has 8M)
- default DER is 0
- remove unused MAMR defines from FADS860T.h (all done in fads.c)
- rename MAMR/MBMR defines to be more consistent. Should eventually
be merged into MxMR to better reflect the PowerQUICC datasheet.
* Patch by Yuli Barcohen, 16 Jul 2003:
support new Motorola PQ2FADS-ZU evaluation board which replaced
MPC8260ADS and MPC8266ADS
Diffstat (limited to 'board/lantec')
| -rw-r--r-- | board/lantec/lantec.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/board/lantec/lantec.c b/board/lantec/lantec.c index 812f65a..655c951 100644 --- a/board/lantec/lantec.c +++ b/board/lantec/lantec.c @@ -149,7 +149,7 @@ long int initdram (int board_type) udelay(1); /* 0x80006106 */ memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS3 | MCR_MLCF(1) | MCR_MAD(0x06); - memctl->memc_mamr |= MAMR_PTBE; /* refresh enabled */ + memctl->memc_mamr |= MAMR_PTAE; /* refresh enabled */ udelay(200); @@ -170,7 +170,7 @@ long int initdram (int board_type) (ulong *)SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE); - memctl->memc_mamr = CFG_MAMR_8COL | MAMR_PTBE; + memctl->memc_mamr = CFG_MAMR_8COL | MAMR_PTAE; /* * Final mapping: |