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author | Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> | 2008-10-16 15:01:15 +0200 |
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committer | Wolfgang Denk <wd@denx.de> | 2008-10-18 21:54:03 +0200 |
commit | 6d0f6bcf337c5261c08fabe12982178c2c489d76 (patch) | |
tree | ae13958ffa9c6b58c2ea97aac07a4ad2f04a350f /board/mx1fs2 | |
parent | 71edc271816ec82cf0550dd6980be2da3cc2ad9e (diff) | |
download | bootable_bootloader_goldelico_gta04-6d0f6bcf337c5261c08fabe12982178c2c489d76.zip bootable_bootloader_goldelico_gta04-6d0f6bcf337c5261c08fabe12982178c2c489d76.tar.gz bootable_bootloader_goldelico_gta04-6d0f6bcf337c5261c08fabe12982178c2c489d76.tar.bz2 |
rename CFG_ macros to CONFIG_SYS
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Diffstat (limited to 'board/mx1fs2')
-rw-r--r-- | board/mx1fs2/flash.c | 24 | ||||
-rw-r--r-- | board/mx1fs2/lowlevel_init.S | 34 |
2 files changed, 29 insertions, 29 deletions
diff --git a/board/mx1fs2/flash.c b/board/mx1fs2/flash.c index 8be0f49..da4ebe6 100644 --- a/board/mx1fs2/flash.c +++ b/board/mx1fs2/flash.c @@ -28,7 +28,7 @@ #define FLASH_BANK_SIZE MX1FS2_FLASH_BANK_SIZE #define MAIN_SECT_SIZE MX1FS2_FLASH_SECT_SIZE -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ /* * NOTE - CONFIG_FLASH_16BIT means the CPU interface is 16-bit, it @@ -62,7 +62,7 @@ static void flash_reset(flash_info_t * info); static int write_word_intel(flash_info_t * info, FPWV * dest, FPW data); static int write_word_amd(flash_info_t * info, FPWV * dest, FPW data); #define write_word(in, de, da) write_word_amd(in, de, da) -#ifdef CFG_FLASH_PROTECTION +#ifdef CONFIG_SYS_FLASH_PROTECTION static void flash_sync_real_protect(flash_info_t * info); #endif @@ -77,14 +77,14 @@ flash_init(void) int i, j; ulong size = 0; - for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { + for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { ulong flashbase = 0; flash_info[i].flash_id = (FLASH_MAN_AMD & FLASH_VENDMASK) | (FLASH_AM640U & FLASH_TYPEMASK); flash_info[i].size = FLASH_BANK_SIZE; - flash_info[i].sector_count = CFG_MAX_FLASH_SECT; - memset(flash_info[i].protect, 0, CFG_MAX_FLASH_SECT); + flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT; + memset(flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT); switch (i) { case 0: flashbase = MX1FS2_FLASH_BASE; @@ -101,8 +101,8 @@ flash_init(void) /* Protect monitor and environment sectors */ flash_protect(FLAG_PROTECT_SET, - CFG_FLASH_BASE, - CFG_FLASH_BASE + _bss_start - _armboot_start, + CONFIG_SYS_FLASH_BASE, + CONFIG_SYS_FLASH_BASE + _bss_start - _armboot_start, &flash_info[0]); flash_protect(FLAG_PROTECT_SET, @@ -389,7 +389,7 @@ flash_get_size(FPWV * addr, flash_info_t * info) } #endif /* 0 */ -#ifdef CFG_FLASH_PROTECTION +#ifdef CONFIG_SYS_FLASH_PROTECTION /*----------------------------------------------------------------------- */ @@ -528,7 +528,7 @@ flash_erase(flash_info_t * info, int s_first, int s_last) udelay(1000); while ((*addr & (FPW) 0x00800080) != (FPW) 0x00800080) { - if ((now = get_timer(0)) - start > CFG_FLASH_ERASE_TOUT) { + if ((now = get_timer(0)) - start > CONFIG_SYS_FLASH_ERASE_TOUT) { printf("Timeout\n"); if (intel) { @@ -720,7 +720,7 @@ write_word_amd(flash_info_t * info, FPWV * dest, FPW data) /* data polling for D7 */ while (res == 0 && (*dest & (FPW) 0x00800080) != (data & (FPW) 0x00800080)) { - if (get_timer(0) - start > CFG_FLASH_WRITE_TOUT) { + if (get_timer(0) - start > CONFIG_SYS_FLASH_WRITE_TOUT) { *dest = (FPW) 0x00F000F0; /* reset bank */ printf("SHA timeout\n"); res = 1; @@ -768,7 +768,7 @@ write_word_intel(flash_info_t * info, FPWV * dest, FPW data) start = get_timer(0); while (res == 0 && (*dest & (FPW) 0x00800080) != (FPW) 0x00800080) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { *dest = (FPW) 0x00B000B0; /* Suspend program */ res = 1; } @@ -783,7 +783,7 @@ write_word_intel(flash_info_t * info, FPWV * dest, FPW data) return (res); } -#ifdef CFG_FLASH_PROTECTION +#ifdef CONFIG_SYS_FLASH_PROTECTION /*----------------------------------------------------------------------- */ int diff --git a/board/mx1fs2/lowlevel_init.S b/board/mx1fs2/lowlevel_init.S index 4b2cb48..56a4819 100644 --- a/board/mx1fs2/lowlevel_init.S +++ b/board/mx1fs2/lowlevel_init.S @@ -29,19 +29,19 @@ lowlevel_init: /* Change PERCLK1DIV to 14 ie 14+1 */ ldr r0, =PCDR - ldr r1, =CFG_PCDR_VAL + ldr r1, =CONFIG_SYS_PCDR_VAL str r1, [r0] /* set MCU PLL Control Register 0 */ ldr r0, =MPCTL0 - ldr r1, =CFG_MPCTL0_VAL + ldr r1, =CONFIG_SYS_MPCTL0_VAL str r1, [r0] /* set MCU PLL Control Register 1 */ ldr r0, =MPCTL1 - ldr r1, =CFG_MPCTL1_VAL + ldr r1, =CONFIG_SYS_MPCTL1_VAL str r1, [r0] /* set mpll restart bit */ @@ -63,13 +63,13 @@ lowlevel_init: /* set System PLL Control Register 0 */ ldr r0, =SPCTL0 - ldr r1, =CFG_SPCTL0_VAL + ldr r1, =CONFIG_SYS_SPCTL0_VAL str r1, [r0] /* set System PLL Control Register 1 */ ldr r0, =SPCTL1 - ldr r1, =CFG_SPCTL1_VAL + ldr r1, =CONFIG_SYS_SPCTL1_VAL str r1, [r0] /* set spll restart bit */ @@ -89,11 +89,11 @@ lowlevel_init: bne 1b ldr r0, =CSCR - ldr r1, =CFG_CSCR_VAL + ldr r1, =CONFIG_SYS_CSCR_VAL str r1, [r0] ldr r0, =GPCR - ldr r1, =CFG_GPCR_VAL + ldr r1, =CONFIG_SYS_GPCR_VAL str r1, [r0] /* @@ -122,43 +122,43 @@ lowlevel_init: MCR p15,0,r0,c1,c0,0 ldr r0, =GIUS(0) - ldr r1, =CFG_GIUS_A_VAL + ldr r1, =CONFIG_SYS_GIUS_A_VAL str r1, [r0] ldr r0, =FMCR - ldr r1, =CFG_FMCR_VAL + ldr r1, =CONFIG_SYS_FMCR_VAL str r1, [r0] ldr r0, =CS0U - ldr r1, =CFG_CS0U_VAL + ldr r1, =CONFIG_SYS_CS0U_VAL str r1, [r0] ldr r0, =CS0L - ldr r1, =CFG_CS0L_VAL + ldr r1, =CONFIG_SYS_CS0L_VAL str r1, [r0] ldr r0, =CS1U - ldr r1, =CFG_CS1U_VAL + ldr r1, =CONFIG_SYS_CS1U_VAL str r1, [r0] ldr r0, =CS1L - ldr r1, =CFG_CS1L_VAL + ldr r1, =CONFIG_SYS_CS1L_VAL str r1, [r0] ldr r0, =CS4U - ldr r1, =CFG_CS4U_VAL + ldr r1, =CONFIG_SYS_CS4U_VAL str r1, [r0] ldr r0, =CS4L - ldr r1, =CFG_CS4L_VAL + ldr r1, =CONFIG_SYS_CS4L_VAL str r1, [r0] ldr r0, =CS5U - ldr r1, =CFG_CS5U_VAL + ldr r1, =CONFIG_SYS_CS5U_VAL str r1, [r0] ldr r0, =CS5L - ldr r1, =CFG_CS5L_VAL + ldr r1, =CONFIG_SYS_CS5L_VAL str r1, [r0] /* SDRAM Setup */ |