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author | wdenk <wdenk> | 2002-11-03 00:38:21 +0000 |
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committer | wdenk <wdenk> | 2002-11-03 00:38:21 +0000 |
commit | fe8c2806cdba70479e351299881a395dc2be7785 (patch) | |
tree | a1e8b98a1838cba6e6f5c765d9d85339257c45f5 /board/sbc8260 | |
parent | f9087a3213cc245cf9b90436475b5af822bd7579 (diff) | |
download | bootable_bootloader_goldelico_gta04-fe8c2806cdba70479e351299881a395dc2be7785.zip bootable_bootloader_goldelico_gta04-fe8c2806cdba70479e351299881a395dc2be7785.tar.gz bootable_bootloader_goldelico_gta04-fe8c2806cdba70479e351299881a395dc2be7785.tar.bz2 |
Initial revision
Diffstat (limited to 'board/sbc8260')
-rw-r--r-- | board/sbc8260/flash.c | 392 | ||||
-rw-r--r-- | board/sbc8260/sbc8260.c | 289 |
2 files changed, 681 insertions, 0 deletions
diff --git a/board/sbc8260/flash.c b/board/sbc8260/flash.c new file mode 100644 index 0000000..ab2bf35 --- /dev/null +++ b/board/sbc8260/flash.c @@ -0,0 +1,392 @@ +/* + * (C) Copyright 2000 + * Marius Groeger <mgroeger@sysgo.de> + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Flash Routines for AMD 29F080B devices + * + *-------------------------------------------------------------------- + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <mpc8xx.h> + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; + +/*----------------------------------------------------------------------- + * Functions + */ + +static ulong flash_get_size (vu_long *addr, flash_info_t *info); +static int write_word (flash_info_t *info, ulong dest, ulong data); + +/*----------------------------------------------------------------------- + */ + +unsigned long flash_init (void) +{ + unsigned long size; + int i; + + /* Init: no FLASHes known */ + for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) { + flash_info[i].flash_id = FLASH_UNKNOWN; + } + + /* for now, only support the 4 MB Flash SIMM */ + size = flash_get_size((vu_long *)CFG_FLASH0_BASE, &flash_info[0]); + + /* + * protect monitor and environment sectors + */ + +#if CFG_MONITOR_BASE >= CFG_FLASH0_BASE + flash_protect(FLAG_PROTECT_SET, + CFG_MONITOR_BASE, + CFG_MONITOR_BASE+CFG_MONITOR_LEN-1, + &flash_info[0]); +#endif + +#if (CFG_ENV_IS_IN_FLASH == 1) && defined(CFG_ENV_ADDR) +# ifndef CFG_ENV_SIZE +# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE +# endif + flash_protect(FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR + CFG_ENV_SIZE - 1, + &flash_info[0]); +#endif + + return /*size*/ (CFG_FLASH0_SIZE * 1024 * 1024); +} + +/*----------------------------------------------------------------------- + */ +void flash_print_info (flash_info_t *info) +{ + int i; + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("missing or unknown FLASH type\n"); + return; + } + + switch ((info->flash_id >> 16) & 0xff) { + case 0x1: + printf ("AMD "); + break; + default: + printf ("Unknown Vendor "); + break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case AMD_ID_F040B: + printf ("AM29F040B (4 Mbit)\n"); + break; + case AMD_ID_F080B: + printf ("AM29F080B (8 Mbit)\n"); + break; + default: + printf ("Unknown Chip Type\n"); + break; + } + + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + + printf (" Sector Start Addresses:"); + for (i=0; i<info->sector_count; ++i) { + if ((i % 5) == 0) + printf ("\n "); + printf (" %08lX%s", + info->start[i], + info->protect[i] ? " (RO)" : " " + ); + } + printf ("\n"); + return; +} + +/* + * The following code cannot be run from FLASH! + */ + +static ulong flash_get_size (vu_long *addr, flash_info_t *info) +{ + short i; + vu_long vendor, devid; + ulong base = (ulong)addr; + +/* printf("addr = %08lx\n", (unsigned long)addr); */ + + /* Reset and Write auto select command: read Manufacturer ID */ + addr[0] = 0xf0f0f0f0; + addr[0x0555] = 0xAAAAAAAA; + addr[0x02AA] = 0x55555555; + addr[0x0555] = 0x90909090; + udelay (1000); + + vendor = addr[0]; +/* printf("vendor = %08lx\n", vendor); */ + if (vendor != 0x01010101) { + info->size = 0; + goto out; + } + + devid = addr[1]; +/* printf("devid = %08lx\n", devid); */ + + if ((devid & 0xff) == AMD_ID_F080B) { + info->flash_id = (vendor & 0xff) << 16 | AMD_ID_F080B; + /* we have 16 sectors with 64KB each x 4 */ + info->sector_count = 16; + info->size = 4 * info->sector_count * 64*1024; + } + else { + info->size = 0; + goto out; + } + + /* check for protected sectors */ + for (i = 0; i < info->sector_count; i++) { + /* sector base address */ + info->start[i] = base + i * (info->size / info->sector_count); + /* read sector protection at sector address, (A7 .. A0) = 0x02 */ + /* D0 = 1 if protected */ + addr = (volatile unsigned long *)(info->start[i]); + info->protect[i] = addr[2] & 1; + } + + /* reset command */ + addr = (vu_long *)info->start[0]; + +out: + addr[0] = 0xf0f0f0f0; + + return info->size; +} + + +/*----------------------------------------------------------------------- + */ + +int flash_erase (flash_info_t *info, int s_first, int s_last) +{ + vu_long *addr = (vu_long*)(info->start[0]); + int flag, prot, sect, l_sect; + ulong start, now, last; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf ("- missing\n"); + } else { + printf ("- no sectors to erase\n"); + } + return 1; + } + + prot = 0; + for (sect = s_first; sect <= s_last; sect++) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf ("\n"); + } + + l_sect = -1; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + addr[0x0555] = 0xAAAAAAAA; + addr[0x02AA] = 0x55555555; + addr[0x0555] = 0x80808080; + addr[0x0555] = 0xAAAAAAAA; + addr[0x02AA] = 0x55555555; + udelay (100); + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect<=s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + addr = (vu_long*)(info->start[sect]); + addr[0] = 0x30303030; + l_sect = sect; + } + } + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* wait at least 80us - let's wait 1 ms */ + udelay (1000); + + /* + * We wait for the last triggered sector + */ + if (l_sect < 0) + goto DONE; + + start = get_timer (0); + last = start; + addr = (vu_long*)(info->start[l_sect]); + while ((addr[0] & 0x80808080) != 0x80808080) { + if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + printf ("Timeout\n"); + return 1; + } + /* show that we're waiting */ + if ((now - last) > 1000) { /* every second */ + serial_putc ('.'); + last = now; + } + } + + DONE: + /* reset to read mode */ + addr = (volatile unsigned long *)info->start[0]; + addr[0] = 0xF0F0F0F0; /* reset bank */ + + printf (" done\n"); + return 0; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ + +int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) +{ + ulong cp, wp, data; + int i, l, rc; + + wp = (addr & ~3); /* get lower word aligned address */ + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i=0, cp=wp; i<l; ++i, ++cp) { + data = (data << 8) | (*(uchar *)cp); + } + for (; i<4 && cnt>0; ++i) { + data = (data << 8) | *src++; + --cnt; + ++cp; + } + for (; cnt==0 && i<4; ++i, ++cp) { + data = (data << 8) | (*(uchar *)cp); + } + + if ((rc = write_word(info, wp, data)) != 0) { + return (rc); + } + wp += 4; + } + + /* + * handle word aligned part + */ + while (cnt >= 4) { + data = 0; + for (i=0; i<4; ++i) { + data = (data << 8) | *src++; + } + if ((rc = write_word(info, wp, data)) != 0) { + return (rc); + } + wp += 4; + cnt -= 4; + } + + if (cnt == 0) { + return (0); + } + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { + data = (data << 8) | *src++; + --cnt; + } + for (; i<4; ++i, ++cp) { + data = (data << 8) | (*(uchar *)cp); + } + + return (write_word(info, wp, data)); +} + +/*----------------------------------------------------------------------- + * Write a word to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_word (flash_info_t *info, ulong dest, ulong data) +{ + vu_long *addr = (vu_long*)(info->start[0]); + ulong start; + int flag; + + /* Check if Flash is (sufficiently) erased */ + if ((*((vu_long *)dest) & data) != data) { + return (2); + } + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + addr[0x0555] = 0xAAAAAAAA; + addr[0x02AA] = 0x55555555; + addr[0x0555] = 0xA0A0A0A0; + + *((vu_long *)dest) = data; + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* data polling for D7 */ + start = get_timer (0); + while ((*((vu_long *)dest) & 0x80808080) != (data & 0x80808080)) { + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + return (1); + } + } + return (0); +} + +/*----------------------------------------------------------------------- + */ diff --git a/board/sbc8260/sbc8260.c b/board/sbc8260/sbc8260.c new file mode 100644 index 0000000..48aefa0 --- /dev/null +++ b/board/sbc8260/sbc8260.c @@ -0,0 +1,289 @@ +/* + * (C) Copyright 2000 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Marius Groeger <mgroeger@sysgo.de> + * + * (C) Copyright 2001 + * Advent Networks, Inc. <http://www.adventnetworks.com> + * Jay Monkman <jtm@smoothsmoothie.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <ioports.h> +#include <mpc8260.h> + +/* + * I/O Port configuration table + * + * if conf is 1, then that port pin will be configured at boot time + * according to the five values podr/pdir/ppar/psor/pdat for that entry + */ + +const iop_conf_t iop_conf_tab[4][32] = { + + /* Port A configuration */ + { /* conf ppar psor pdir podr pdat */ + /* PA31 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 *ATMTXEN */ + /* PA30 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 ATMTCA */ + /* PA29 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 ATMTSOC */ + /* PA28 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 *ATMRXEN */ + /* PA27 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 ATMRSOC */ + /* PA26 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 ATMRCA */ + /* PA25 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */ + /* PA24 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */ + /* PA23 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */ + /* PA22 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */ + /* PA21 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */ + /* PA20 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */ + /* PA19 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */ + /* PA18 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */ + /* PA17 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[7] */ + /* PA16 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[6] */ + /* PA15 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[5] */ + /* PA14 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[4] */ + /* PA13 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[3] */ + /* PA12 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[2] */ + /* PA11 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[1] */ + /* PA10 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[0] */ + /* PA9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC2 TXD */ + /* PA8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC2 RXD */ + /* PA7 */ { 1, 0, 0, 1, 0, 0 }, /* PA7 */ + /* PA6 */ { 1, 0, 0, 1, 0, 0 }, /* PA6 */ + /* PA5 */ { 1, 0, 0, 1, 0, 0 }, /* PA5 */ + /* PA4 */ { 1, 0, 0, 1, 0, 0 }, /* PA4 */ + /* PA3 */ { 1, 0, 0, 1, 0, 0 }, /* PA3 */ + /* PA2 */ { 1, 0, 0, 1, 0, 0 }, /* PA2 */ + /* PA1 */ { 1, 0, 0, 1, 0, 0 }, /* PA1 */ + /* PA0 */ { 1, 0, 0, 1, 0, 0 } /* PA0 */ + }, + + /* Port B configuration */ + { /* conf ppar psor pdir podr pdat */ + /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ + /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ + /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ + /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ + /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ + /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ + /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ + /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ + /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ + /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ + /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ + /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ + /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ + /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ + /* PB17 */ { 1, 0, 0, 1, 0, 0 }, /* PB17 */ + /* PB16 */ { 1, 0, 0, 1, 0, 0 }, /* PB16 */ + /* PB15 */ { 1, 0, 0, 1, 0, 0 }, /* PB15 */ + /* PB14 */ { 1, 0, 0, 1, 0, 0 }, /* PB14 */ + /* PB13 */ { 1, 0, 0, 1, 0, 0 }, /* PB13 */ + /* PB12 */ { 1, 0, 0, 1, 0, 0 }, /* PB12 */ + /* PB11 */ { 1, 0, 0, 1, 0, 0 }, /* PB11 */ + /* PB10 */ { 1, 0, 0, 1, 0, 0 }, /* PB10 */ + /* PB9 */ { 1, 0, 0, 1, 0, 0 }, /* PB9 */ + /* PB8 */ { 1, 0, 0, 1, 0, 0 }, /* PB8 */ + /* PB7 */ { 1, 0, 0, 1, 0, 0 }, /* PB7 */ + /* PB6 */ { 1, 0, 0, 1, 0, 0 }, /* PB6 */ + /* PB5 */ { 1, 0, 0, 1, 0, 0 }, /* PB5 */ + /* PB4 */ { 1, 0, 0, 1, 0, 0 }, /* PB4 */ + /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ + }, + + /* Port C */ + { /* conf ppar psor pdir podr pdat */ + /* PC31 */ { 1, 0, 0, 1, 0, 0 }, /* PC31 */ + /* PC30 */ { 1, 0, 0, 1, 0, 0 }, /* PC30 */ + /* PC29 */ { 1, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */ + /* PC28 */ { 1, 0, 0, 1, 0, 0 }, /* PC28 */ + /* PC27 */ { 1, 0, 0, 1, 0, 0 }, /* PC27 */ + /* PC26 */ { 1, 0, 0, 1, 0, 0 }, /* PC26 */ + /* PC25 */ { 1, 0, 0, 1, 0, 0 }, /* PC25 */ + /* PC24 */ { 1, 0, 0, 1, 0, 0 }, /* PC24 */ + /* PC23 */ { 1, 1, 0, 1, 0, 0 }, /* ATMTFCLK */ + /* PC22 */ { 1, 1, 0, 0, 0, 0 }, /* ATMRFCLK */ + /* PC21 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */ + /* PC20 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */ + /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK */ + /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII TX_CLK */ + /* PC17 */ { 1, 0, 0, 1, 0, 0 }, /* PC17 */ + /* PC16 */ { 1, 0, 0, 1, 0, 0 }, /* PC16 */ + /* PC15 */ { 1, 0, 0, 1, 0, 0 }, /* PC15 */ + /* PC14 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */ + /* PC13 */ { 1, 0, 0, 1, 0, 0 }, /* PC13 */ + /* PC12 */ { 1, 0, 0, 1, 0, 0 }, /* PC12 */ + /* PC11 */ { 1, 0, 0, 1, 0, 0 }, /* PC11 */ + /* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* FCC2 MDC */ + /* PC9 */ { 1, 0, 0, 1, 0, 0 }, /* FCC2 MDIO */ + /* PC8 */ { 1, 0, 0, 1, 0, 0 }, /* PC8 */ + /* PC7 */ { 1, 0, 0, 1, 0, 0 }, /* PC7 */ + /* PC6 */ { 1, 0, 0, 1, 0, 0 }, /* PC6 */ + /* PC5 */ { 1, 0, 0, 1, 0, 0 }, /* PC5 */ + /* PC4 */ { 1, 0, 0, 1, 0, 0 }, /* PC4 */ + /* PC3 */ { 1, 0, 0, 1, 0, 0 }, /* PC3 */ + /* PC2 */ { 1, 0, 0, 1, 0, 1 }, /* ENET FDE */ + /* PC1 */ { 1, 0, 0, 1, 0, 0 }, /* ENET DSQE */ + /* PC0 */ { 1, 0, 0, 1, 0, 0 }, /* ENET LBK */ + }, + + /* Port D */ + { /* conf ppar psor pdir podr pdat */ + /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */ + /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */ + /* PD29 */ { 1, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */ + /* PD28 */ { 1, 0, 0, 1, 0, 0 }, /* PD28 */ + /* PD27 */ { 1, 0, 0, 1, 0, 0 }, /* PD27 */ + /* PD26 */ { 1, 0, 0, 1, 0, 0 }, /* PD26 */ + /* PD25 */ { 1, 0, 0, 1, 0, 0 }, /* PD25 */ + /* PD24 */ { 1, 0, 0, 1, 0, 0 }, /* PD24 */ + /* PD23 */ { 1, 0, 0, 1, 0, 0 }, /* PD23 */ + /* PD22 */ { 1, 0, 0, 1, 0, 0 }, /* PD22 */ + /* PD21 */ { 1, 0, 0, 1, 0, 0 }, /* PD21 */ + /* PD20 */ { 1, 0, 0, 1, 0, 0 }, /* PD20 */ + /* PD19 */ { 1, 0, 0, 1, 0, 0 }, /* PD19 */ + /* PD18 */ { 1, 0, 0, 1, 0, 0 }, /* PD18 */ + /* PD17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */ + /* PD16 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */ +#if defined(CONFIG_SOFT_I2C) + /* PD15 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SDA */ + /* PD14 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SCL */ +#else +#if defined(CONFIG_HARD_I2C) + /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */ + /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */ +#else /* normal I/O port pins */ + /* PD15 */ { 1, 0, 0, 1, 0, 0 }, /* I2C SDA */ + /* PD14 */ { 1, 0, 0, 1, 0, 0 }, /* I2C SCL */ +#endif +#endif + /* PD13 */ { 1, 0, 0, 0, 0, 0 }, /* PD13 */ + /* PD12 */ { 1, 0, 0, 0, 0, 0 }, /* PD12 */ + /* PD11 */ { 1, 0, 0, 0, 0, 0 }, /* PD11 */ + /* PD10 */ { 1, 0, 0, 0, 0, 0 }, /* PD10 */ + /* PD9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 TXD */ + /* PD8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 RXD */ + /* PD7 */ { 1, 0, 0, 1, 0, 1 }, /* PD7 */ + /* PD6 */ { 1, 0, 0, 1, 0, 1 }, /* PD6 */ + /* PD5 */ { 1, 0, 0, 1, 0, 1 }, /* PD5 */ + /* PD4 */ { 1, 0, 0, 1, 0, 1 }, /* PD4 */ + /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ + } +}; + +/* ------------------------------------------------------------------------- */ + +/* + * Check Board Identity: + */ + +int checkboard (void) +{ + puts ("Board: EST SBC8260\n"); + return 0; +} + +/* ------------------------------------------------------------------------- */ + +long int initdram (int board_type) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile memctl8260_t *memctl = &immap->im_memctl; + volatile uchar c = 0, *ramaddr = (uchar *) (CFG_SDRAM_BASE + 0x8); + ulong psdmr = CFG_PSDMR; + int i; + + /* + * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35): + * + * "At system reset, initialization software must set up the + * programmable parameters in the memory controller banks registers + * (ORx, BRx, P/LSDMR). After all memory parameters are configured, + * system software should execute the following initialization sequence + * for each SDRAM device. + * + * 1. Issue a PRECHARGE-ALL-BANKS command + * 2. Issue eight CBR REFRESH commands + * 3. Issue a MODE-SET command to initialize the mode register + * + * The initial commands are executed by setting P/LSDMR[OP] and + * accessing the SDRAM with a single-byte transaction." + * + * The appropriate BRx/ORx registers have already been set when we + * get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE. + */ + + memctl->memc_psrt = CFG_PSRT; + memctl->memc_mptpr = CFG_MPTPR; + + memctl->memc_psdmr = psdmr | PSDMR_OP_PREA; + *ramaddr = c; + + memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR; + for (i = 0; i < 8; i++) + *ramaddr = c; + + memctl->memc_psdmr = psdmr | PSDMR_OP_MRW; + *ramaddr = c; + + memctl->memc_psdmr = psdmr | PSDMR_OP_NORM | PSDMR_RFEN; + *ramaddr = c; + + /* return total ram size */ + return (CFG_SDRAM0_SIZE * 1024 * 1024); +} + +#ifdef CONFIG_MISC_INIT_R +/* ------------------------------------------------------------------------- */ +int misc_init_r (void) +{ +#ifdef CFG_LED_BASE + uchar ds = *(unsigned char *) (CFG_LED_BASE + 1); + uchar ss; + uchar tmp[64]; + int res; + + if ((ds != 0) && (ds != 0xff)) { + res = getenv_r ("ethaddr", tmp, sizeof (tmp)); + if (res > 0) { + ss = ((ds >> 4) & 0x0f); + ss += ss < 0x0a ? '0' : ('a' - 10); + tmp[15] = ss; + + ss = (ds & 0x0f); + ss += ss < 0x0a ? '0' : ('a' - 10); + tmp[16] = ss; + + tmp[17] = '\0'; + setenv ("ethaddr", tmp); + /* set the led to show the address */ + *((unsigned char *) (CFG_LED_BASE + 1)) = ds; + } + } +#endif /* CFG_LED_BASE */ + return (0); +} +#endif /* CONFIG_MISC_INIT_R */ |