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| author | Kumar Gala <galak@kernel.crashing.org> | 2008-01-16 10:04:42 -0600 |
|---|---|---|
| committer | Kumar Gala <galak@kernel.crashing.org> | 2008-01-16 23:21:56 -0600 |
| commit | c8c41d4a80b1a8ad5984a287d81ea780496259f8 (patch) | |
| tree | d16801f7e70a98bc8f7f636bc458ccbc087bbe0c /board/sbc8560 | |
| parent | 54a5070115eff38e9b324b78abdfa0b4520580b9 (diff) | |
| download | bootable_bootloader_goldelico_gta04-c8c41d4a80b1a8ad5984a287d81ea780496259f8.zip bootable_bootloader_goldelico_gta04-c8c41d4a80b1a8ad5984a287d81ea780496259f8.tar.gz bootable_bootloader_goldelico_gta04-c8c41d4a80b1a8ad5984a287d81ea780496259f8.tar.bz2 | |
85xx: Use proper defines for PCI addresses
We should be using the _MEM_PHYS for LAW and TLB setup and not _MEM_BASE.
While _MEM_BASE & _MEM_PHYS are normally the same, _MEM_BASE should only
be used for configuring the PCI ATMU.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'board/sbc8560')
| -rw-r--r-- | board/sbc8560/init.S | 4 | ||||
| -rw-r--r-- | board/sbc8560/law.c | 2 |
2 files changed, 3 insertions, 3 deletions
diff --git a/board/sbc8560/init.S b/board/sbc8560/init.S index e149fbd..3baa506 100644 --- a/board/sbc8560/init.S +++ b/board/sbc8560/init.S @@ -103,8 +103,8 @@ tlb1_entry: .long FSL_BOOKE_MAS0(1,7,0) .long FSL_BOOKE_MAS1(1,1,0,0,BOOKE_PAGESZ_256M) - .long FSL_BOOKE_MAS2(CFG_PCI_MEM_BASE,(MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_PCI_MEM_BASE,0,(MAS3_SX|MAS3_SW|MAS3_SR)) + .long FSL_BOOKE_MAS2(CFG_PCI_MEM_PHYS,(MAS2_I|MAS2_G)) + .long FSL_BOOKE_MAS3(CFG_PCI_MEM_PHYS,0,(MAS3_SX|MAS3_SW|MAS3_SR)) #if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR) .long FSL_BOOKE_MAS0(1,15,0) diff --git a/board/sbc8560/law.c b/board/sbc8560/law.c index d1c6dc2..e370853 100644 --- a/board/sbc8560/law.c +++ b/board/sbc8560/law.c @@ -53,7 +53,7 @@ struct law_entry law_table[] = { #ifndef CONFIG_SPD_EEPROM SET_LAW_ENTRY(1, CFG_DDR_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_DDR), #endif - SET_LAW_ENTRY(2, CFG_PCI_MEM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_PCI), + SET_LAW_ENTRY(2, CFG_PCI_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCI), SET_LAW_ENTRY(3, CFG_LBC_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_LBC), }; |