Merge with http://www.denx.de/git/u-boot.git

52 files changed, 3207 insertions, 199 deletions

diff --git a/board/adder/adder.c b/board/adder/adder.c
index cab6e2f..aa78158 100644
--- a/board/adder/adder.c
+++ b/board/adder/adder.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2004 Arabella Software Ltd.
+ * Copyright (C) 2004-2005 Arabella Software Ltd.
  * Yuli Barcohen <yuli@arabellasw.com>
  *
  * Support for Analogue&Micro Adder boards family.
@@ -28,7 +28,8 @@
 #include <mpc8xx.h>
 
 /*
- * SDRAM is single Samsung K4S643232F-T70 chip.
+ * SDRAM is single Samsung K4S643232F-T70   chip (8MB)
+ *       or single Micron  MT48LC4M32B2TG-7 chip (16MB).
  * Minimal CPU frequency is 40MHz.
  */
 static uint sdram_table[] = {
@@ -53,7 +54,7 @@ static uint sdram_table[] = {
 	0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
 
 	/* Refresh	(offset 0x30 in UPM RAM) */
-	0x1ff5fca4, 0xfffffc04, 0xfffffc04, 0xfffffc04,
+	0x1ff5fc84, 0xfffffc04, 0xfffffc04, 0xfffffc04,
 	0xfffffc84, 0xfffffc07, 0xfffffc04, 0xfffffc04,
 	0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
 
@@ -63,7 +64,7 @@ static uint sdram_table[] = {
 
 long int initdram (int board_type)
 {
-	long int msize = CFG_SDRAM_SIZE;
+	long int msize;
 	volatile immap_t     *immap  = (volatile immap_t *)CFG_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
 
@@ -72,11 +73,11 @@ long int initdram (int board_type)
 	/* Configure SDRAM refresh */
 	memctl->memc_mptpr = MPTPR_PTP_DIV32; /* BRGCLK/32 */
 
-	memctl->memc_mamr = (94 << 24) | CFG_MAMR;
-	memctl->memc_mar  = 0x0;
+	memctl->memc_mamr = (94 << 24) | CFG_MAMR; /* No refresh */
 	udelay(200);
 
 	/* Run precharge from location 0x15 */
+	memctl->memc_mar = 0x0;
 	memctl->memc_mcr = 0x80002115;
 	udelay(200);
 
@@ -84,13 +85,18 @@ long int initdram (int board_type)
 	memctl->memc_mcr = 0x80002830;
 	udelay(200);
 
-	memctl->memc_mar = 0x88;
-	udelay(200);
-
 	/* Run MRS pattern from location 0x16 */
+	memctl->memc_mar = 0x88;
 	memctl->memc_mcr = 0x80002116;
 	udelay(200);
 
+	memctl->memc_mamr |=  MAMR_PTAE; /* Enable refresh */
+	memctl->memc_or1   = ~(CFG_SDRAM_MAX_SIZE - 1) | OR_CSNT_SAM;
+	memctl->memc_br1   =  CFG_SDRAM_BASE | BR_PS_32 | BR_MS_UPMA | BR_V;
+
+	msize = get_ram_size(CFG_SDRAM_BASE, CFG_SDRAM_MAX_SIZE);
+	memctl->memc_or1  |= ~(msize - 1);
+
 	return msize;
 }
 
diff --git a/board/at91rm9200dk/at45.c b/board/at91rm9200dk/at45.c
index 3c00132..f886fe4 100644
--- a/board/at91rm9200dk/at45.c
+++ b/board/at91rm9200dk/at45.c
@@ -593,7 +593,7 @@ int AT91F_DataFlashRead(
 		if (AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY) != DATAFLASH_OK)
 			return -1;
 
-		if (AT91F_DataFlashContinuousRead (pDataFlash, addr, buffer, SizeToRead) != DATAFLASH_OK)
+		if (AT91F_DataFlashContinuousRead (pDataFlash, addr, (uchar *)buffer, SizeToRead) != DATAFLASH_OK)
 			return -1;
 
 		size -= SizeToRead;
diff --git a/board/at91rm9200dk/flash.c b/board/at91rm9200dk/flash.c
index f6228ef..0513d61 100644
--- a/board/at91rm9200dk/flash.c
+++ b/board/at91rm9200dk/flash.c
@@ -393,8 +393,7 @@ outahere:
  * Copy memory to flash
  */
 
-volatile static int write_word (flash_info_t * info, ulong dest,
-								ulong data)
+static int write_word (flash_info_t * info, ulong dest, ulong data)
 {
 	volatile u16 *addr = (volatile u16 *) dest;
 	ulong result;
@@ -409,7 +408,6 @@ volatile static int write_word (flash_info_t * info, ulong dest,
 	if ((result & data) != data)
 		return ERR_NOT_ERASED;
 
-
 	/*
 	 * Disable interrupts which might cause a timeout
 	 * here. Remember that our exception vectors are
diff --git a/board/cmc_pu2/load_sernum_ethaddr.c b/board/cmc_pu2/load_sernum_ethaddr.c
index 94aa30d..354566c 100644
--- a/board/cmc_pu2/load_sernum_ethaddr.c
+++ b/board/cmc_pu2/load_sernum_ethaddr.c
@@ -69,8 +69,8 @@ int i2c_read (unsigned char chip, unsigned int addr, int alen,
 void load_sernum_ethaddr (void)
 {
 	struct manufacturer_data data;
-	unsigned char  serial [9];
-	unsigned char  ethaddr[18];
+	char  ethaddr[18];
+	char  serial [9];
 	unsigned short chksum;
 	unsigned char *p;
 	unsigned short i, is, id;
diff --git a/board/cobra5272/flash.c b/board/cobra5272/flash.c
index 6f5874a..73cc2f2 100644
--- a/board/cobra5272/flash.c
+++ b/board/cobra5272/flash.c
@@ -256,8 +256,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last)
 	return rc;
 }
 
-
-volatile static int write_word (flash_info_t * info, ulong dest, ulong data)
+static int write_word (flash_info_t * info, ulong dest, ulong data)
 {
 	volatile u16 *addr = (volatile u16 *) dest;
 	ulong result;
diff --git a/board/delta/nand.c b/board/delta/nand.c
index c332f71..5d2cd65 100644
--- a/board/delta/nand.c
+++ b/board/delta/nand.c
@@ -229,7 +229,7 @@ static void wait_us(unsigned long us)
 	}
 }
 
-static void dfc_clear_nddb()
+static void dfc_clear_nddb(void)
 {
 	NDCR &= ~NDCR_ND_RUN;
 	wait_us(CFG_NAND_OTHER_TO);
@@ -263,7 +263,7 @@ static unsigned long dfc_wait_event(unsigned long event)
 }
 
 /* we don't always wan't to do this */
-static void dfc_new_cmd()
+static void dfc_new_cmd(void)
 {
 	int retry = 0;
 	unsigned long status;
@@ -393,7 +393,7 @@ static void dfc_cmdfunc(struct mtd_info *mtd, unsigned command,
 	return;
 }
 
-static void dfc_gpio_init()
+static void dfc_gpio_init(void)
 {
 	DFC_DEBUG2("Setting up DFC GPIO's.\n");
 
diff --git a/board/ep88x/Makefile b/board/ep88x/Makefile
new file mode 100644
index 0000000..9123a80
--- /dev/null
+++ b/board/ep88x/Makefile
@@ -0,0 +1,46 @@
+#
+# Copyright (C) 2004 Arabella Software Ltd.
+# Yuli Barcohen <yuli@arabellasw.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= $(BOARD).o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
diff --git a/board/ep88x/config.mk b/board/ep88x/config.mk
new file mode 100644
index 0000000..72b326c
--- /dev/null
+++ b/board/ep88x/config.mk
@@ -0,0 +1,27 @@
+#
+# Copyright (C) 2005 Arabella Software Ltd.
+# Yuli Barcohen <yuli@arabellasw.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# Embedded Planet EP88x boards
+#
+TEXT_BASE = 0xFC000000
diff --git a/board/ep88x/ep88x.c b/board/ep88x/ep88x.c
new file mode 100644
index 0000000..5f57f36
--- /dev/null
+++ b/board/ep88x/ep88x.c
@@ -0,0 +1,133 @@
+/*
+ * Copyright (C) 2005 Arabella Software Ltd.
+ * Yuli Barcohen <yuli@arabellasw.com>
+ *
+ * Support for Embedded Planet EP88x boards.
+ * Tested on EP88xC with MPC885 CPU, 64MB SDRAM and 16MB flash.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+
+/*
+ * SDRAM uses two Micron chips.
+ * Minimal CPU frequency is 40MHz.
+ */
+static uint sdram_table[] = {
+	/* Single read	(offset 0x00 in UPM RAM) */
+	0xEFCBCC04, 0x0F37C804, 0x0EEEC004, 0x01B98404,
+	0x1FF74C00, 0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05,
+
+	/* Burst read	(offset 0x08 in UPM RAM) */
+	0xEFCBCC04, 0x0F37C804, 0x0EEEC004, 0x00BDC404,
+	0x00FFCC00, 0x00FFCC00, 0x01FB8C00, 0x1FF74C00,
+	0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05,
+	0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05,
+
+	/* Single write (offset 0x18 in UPM RAM) */
+	0xEFCBCC04, 0x0F37C804, 0x0EEE8002, 0x01B90404,
+	0x1FF74C05, 0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05,
+
+	/* Burst write	(offset 0x20 in UPM RAM) */
+	0xEFCBCC04, 0x0F37C804, 0x0EEE8000, 0x00BD4400,
+	0x00FFCC00, 0x00FFCC02, 0x01FB8C04, 0x1FF74C05,
+	0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05,
+	0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05,
+
+	/* Refresh	(offset 0x30 in UPM RAM) */
+	0xEFFACC04, 0x0FF5CC04, 0x0FFFCC04, 0x1FFFCC04,
+	0xFFFFCC05, 0xFFFFCC05, 0xEFFB8C34, 0x0FF74C34,
+	0x0FFACCB4, 0x0FF5CC34, 0x0FFFC034, 0x0FFFC0B4,
+
+	/* Exception	(offset 0x3C in UPM RAM) */
+	0x0FEA8034, 0x1FB54034,	0xFFFFCC34, 0xFFFFCC05
+};
+
+int board_early_init_f (void)
+{
+	vu_char *bcsr = (vu_char *)CFG_BCSR;
+
+	bcsr[0] |= 0x0C; /* Turn the LEDs off */
+	bcsr[2] |= 0x08; /* Enable flash WE# line - necessary for
+			    flash detection by CFI driver
+			 */
+
+#if defined(CONFIG_8xx_CONS_SMC1)
+	bcsr[6] |= 0x10; /* Enables RS-232 transceiver */
+#endif
+#if defined(CONFIG_8xx_CONS_SCC2)
+	bcsr[7] |= 0x10; /* Enables RS-232 transceiver */
+#endif
+#ifdef CONFIG_ETHER_ON_FEC1
+	bcsr[8] |= 0xC0; /* Enable Ethernet 1 PHY */
+#endif
+#ifdef CONFIG_ETHER_ON_FEC2
+	bcsr[8] |= 0x30; /* Enable Ethernet 2 PHY */
+#endif
+
+	return 0;
+}
+
+long int initdram (int board_type)
+{
+	long int msize;
+	volatile immap_t     *immap  = (volatile immap_t *)CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+
+	upmconfig(UPMA, sdram_table, sizeof(sdram_table) / sizeof(uint));
+
+	/* Configure SDRAM refresh */
+	memctl->memc_mptpr = MPTPR_PTP_DIV2; /* BRGCLK/2 */
+
+	memctl->memc_mamr = (65 << 24) | CFG_MAMR; /* No refresh */
+	udelay(100);
+
+	/* Run MRS pattern from location 0x36 */
+	memctl->memc_mar = 0x88;
+	memctl->memc_mcr = 0x80002236;
+	udelay(100);
+
+	memctl->memc_mamr |=  MAMR_PTAE; /* Enable refresh */
+	memctl->memc_or1   = ~(CFG_SDRAM_MAX_SIZE - 1) | OR_CSNT_SAM;
+	memctl->memc_br1   =  CFG_SDRAM_BASE | BR_PS_32 | BR_MS_UPMA | BR_V;
+
+	msize = get_ram_size(CFG_SDRAM_BASE, CFG_SDRAM_MAX_SIZE);
+	memctl->memc_or1  |= ~(msize - 1);
+
+	return msize;
+}
+
+int checkboard( void )
+{
+	vu_char *bcsr = (vu_char *)CFG_BCSR;
+
+	puts("Board: ");
+	switch (bcsr[15]) {
+	case 0xE7:
+		puts("EP88xC 1.0");
+		break;
+	default:
+		printf("unknown ID=%02X", bcsr[15]);
+	}
+	printf("  CPLD revision %d\n", bcsr[14]);
+
+	return 0;
+}
diff --git a/board/ep88x/u-boot.lds b/board/ep88x/u-boot.lds
new file mode 100644
index 0000000..1d2a7d7
--- /dev/null
+++ b/board/ep88x/u-boot.lds
@@ -0,0 +1,122 @@
+/*
+ * (C) Copyright 2001-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Modified by Yuli Barcohen <yuli@arabellasw.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp        : { *(.interp)		}
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)	}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)	}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)	}
+  .rela.got      : { *(.rela.got)	}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)	}
+  .rela.bss      : { *(.rela.bss)	}
+  .rel.plt       : { *(.rel.plt)	}
+  .rela.plt      : { *(.rela.plt)	}
+  .init          : { *(.init)		}
+  .plt           : { *(.plt)		}
+  .text          :
+  {
+    cpu/mpc8xx/start.o	(.text)
+    *(.text)
+    *(.fixup)
+    *(.got1)
+    . = ALIGN(16);
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
+ENTRY(_start)
diff --git a/board/ezkit533/Makefile b/board/ezkit533/Makefile
new file mode 100644
index 0000000..c9b3c92
--- /dev/null
+++ b/board/ezkit533/Makefile
@@ -0,0 +1,44 @@
+#
+# U-boot - Makefile
+#
+# Copyright (c) 2005 blackfin.uclinux.org
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o flash.o ezkit533.o
+
+$(LIB):	.depend $(OBJS)
+	$(AR) crv $@ $(OBJS)
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/ezkit533/config.mk b/board/ezkit533/config.mk
new file mode 100644
index 0000000..36c9f99
--- /dev/null
+++ b/board/ezkit533/config.mk
@@ -0,0 +1,25 @@
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+TEXT_BASE = 0x01FC0000
+PLATFORM_CPPFLAGS += -I$(TOPDIR)
diff --git a/board/ezkit533/ezkit533.c b/board/ezkit533/ezkit533.c
new file mode 100644
index 0000000..f8ee900
--- /dev/null
+++ b/board/ezkit533/ezkit533.c
@@ -0,0 +1,71 @@
+/*
+ * U-boot - ezkit533.c
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#if defined(CONFIG_MISC_INIT_R)
+#include "psd4256.h"
+#endif
+
+int checkboard(void)
+{
+	printf("CPU:   ADSP BF533 Rev.: 0.%d\n", *pCHIPID >> 28);
+	printf("Board: ADI BF533 EZ-Kit Lite board\n");
+	printf("       Support: http://blackfin.uclinux.org/\n");
+	printf("       Richard Klingler <richard@uclinux.net>\n");
+	return 0;
+}
+
+long int initdram(int board_type)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+#ifdef DEBUG
+	int brate;
+	char *tmp = getenv("baudrate");
+	brate = simple_strtoul(tmp, NULL, 16);
+	printf("Serial Port initialized with Baud rate = %x\n",brate);
+	printf("SDRAM attributes:\n");
+	printf("tRCD %d SCLK Cycles,tRP %d SCLK Cycles,tRAS %d SCLK Cycles"
+	       "tWR %d SCLK Cycles,CAS Latency %d SCLK cycles \n",
+	       3, 3, 6, 2, 3);
+	printf("SDRAM Begin: 0x%x\n", CFG_SDRAM_BASE);
+	printf("Bank size = %d MB\n", CFG_MAX_RAM_SIZE >> 20);
+#endif
+	gd->bd->bi_memstart = CFG_SDRAM_BASE;
+	gd->bd->bi_memsize = CFG_MAX_RAM_SIZE;
+	return CFG_MAX_RAM_SIZE;
+}
+
+#if defined(CONFIG_MISC_INIT_R)
+/* miscellaneous platform dependent initialisations */
+int misc_init_r(void)
+{
+	/* Set direction bits for Video en/decoder reset as output	*/
+	*(volatile unsigned char *)(CFG_FLASH1_BASE + PSD_PORTA_DIR) = PSDA_VDEC_RST | PSDA_VENC_RST;
+	/* Deactivate Video en/decoder reset lines			*/
+	*(volatile unsigned char *)(CFG_FLASH1_BASE + PSD_PORTA_DOUT) = PSDA_VDEC_RST | PSDA_VENC_RST;
+}
+#endif
diff --git a/board/ezkit533/flash-defines.h b/board/ezkit533/flash-defines.h
new file mode 100644
index 0000000..8f9dff5
--- /dev/null
+++ b/board/ezkit533/flash-defines.h
@@ -0,0 +1,130 @@
+/*
+ * U-boot - flash-defines.h
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __FLASHDEFINES_H__
+#define __FLASHDEFINES_H__
+
+#include <common.h>
+
+#define V_ULONG(a)		(*(volatile unsigned long *)( a ))
+#define V_BYTE(a)		(*(volatile unsigned char *)( a ))
+#define TRUE			0x1
+#define FALSE			0x0
+#define BUFFER_SIZE		0x80000
+#define NO_COMMAND		0
+#define GET_CODES		1
+#define RESET			2
+#define WRITE			3
+#define FILL			4
+#define ERASE_ALL		5
+#define ERASE_SECT		6
+#define READ			7
+#define GET_SECTNUM		8
+#define FLASH_START_L 		0x0000
+#define FLASH_START_H 		0x2000
+#define FLASH_TOT_SECT		40
+#define FLASH_SIZE 		0x220000
+#define FLASH_MAN_ST 		2
+#define CFG_FLASH0_BASE		0x20000000
+#define RESET_VAL		0xF0
+
+
+asm("#define FLASH_START_L 0x0000");
+asm("#define FLASH_START_H 0x2000");
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+
+int get_codes(void);
+int poll_toggle_bit(long lOffset);
+void reset_flash(void);
+int erase_flash(void);
+int erase_block_flash(int,unsigned long);
+void unlock_flash(long lOffset);
+int write_data(long lStart, long lCount, long lStride, int *pnData);
+int FillData(long lStart, long lCount, long lStride, int *pnData);
+int read_data(long lStart, long lCount, long lStride, int *pnData);
+int read_flash(long nOffset, int *pnValue);
+int write_flash(long nOffset, int nValue);
+void get_sector_number(long lOffset, int *pnSector);
+int GetSectorProtectionStatus(flash_info_t * info, int nSector);
+int GetOffset(int nBlock);
+int AFP_NumSectors = 40;
+long AFP_SectorSize1 = 0x10000;
+int AFP_SectorSize2 = 0x4000;
+
+#define WRITESEQ1		0x0AAA
+#define WRITESEQ2		0x0554
+#define WRITESEQ3		0x0AAA
+#define WRITESEQ4		0x0AAA
+#define WRITESEQ5		0x0554
+#define WRITESEQ6		0x0AAA
+#define WRITEDATA1		0xaa
+#define WRITEDATA2		0x55
+#define WRITEDATA3		0x80
+#define WRITEDATA4		0xaa
+#define WRITEDATA5		0x55
+#define WRITEDATA6		0x10
+#define PriFlashABegin		0
+#define SecFlashABegin		32
+#define SecFlashBBegin		36
+#define PriFlashAOff		0x0
+#define PriFlashBOff		0x100000
+#define SecFlashAOff		0x200000
+#define SecFlashBOff		0x280000
+#define INVALIDLOCNSTART	0x20270000
+#define INVALIDLOCNEND		0x20280000
+#define BlockEraseVal		0x30
+#define UNLOCKDATA1		0xaa
+#define UNLOCKDATA2		0x55
+#define UNLOCKDATA3		0xa0
+#define GETCODEDATA1		0xaa
+#define GETCODEDATA2		0x55
+#define GETCODEDATA3		0x90
+#define SecFlashASec1Off	0x200000
+#define SecFlashASec2Off	0x204000
+#define SecFlashASec3Off	0x206000
+#define SecFlashASec4Off	0x208000
+#define SecFlashAEndOff		0x210000
+#define SecFlashBSec1Off	0x280000
+#define SecFlashBSec2Off	0x284000
+#define SecFlashBSec3Off	0x286000
+#define SecFlashBSec4Off	0x288000
+#define SecFlashBEndOff		0x290000
+
+#define SECT32			32
+#define SECT33			33
+#define SECT34			34
+#define SECT35			35
+#define SECT36			36
+#define SECT37			37
+#define SECT38			38
+#define SECT39			39
+
+#define FLASH_SUCCESS	0
+#define FLASH_FAIL	-1
+
+#endif
diff --git a/board/ezkit533/flash.c b/board/ezkit533/flash.c
new file mode 100644
index 0000000..b0a0796
--- /dev/null
+++ b/board/ezkit533/flash.c
@@ -0,0 +1,476 @@
+/*
+ * U-boot - flash.c Flash driver for PSD4256GV
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ * This file is based on BF533EzFlash.c originally written by Analog Devices, Inc.
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include "flash-defines.h"
+
+void flash_reset(void)
+{
+	reset_flash();
+}
+
+unsigned long flash_get_size(ulong baseaddr, flash_info_t * info,
+			     int bank_flag)
+{
+	int id = 0, i = 0;
+	static int FlagDev = 1;
+
+	id = get_codes();
+	if(FlagDev)	{
+#ifdef DEBUG
+		printf("Device ID of the Flash is %x\n", id);
+#endif
+		FlagDev = 0;
+	}
+	info->flash_id = id;
+
+	switch (bank_flag) {
+	case 0:
+		for (i = PriFlashABegin; i < SecFlashABegin; i++)
+			info->start[i] = (baseaddr + (i * AFP_SectorSize1));
+		info->size = 0x200000;
+		info->sector_count = 32;
+		break;
+	case 1:
+		info->start[0] = baseaddr + SecFlashASec1Off;
+		info->start[1] = baseaddr + SecFlashASec2Off;
+		info->start[2] = baseaddr + SecFlashASec3Off;
+		info->start[3] = baseaddr + SecFlashASec4Off;
+		info->size = 0x10000;
+		info->sector_count = 4;
+		break;
+	case 2:
+		info->start[0] = baseaddr + SecFlashBSec1Off;
+		info->start[1] = baseaddr + SecFlashBSec2Off;
+		info->start[2] = baseaddr + SecFlashBSec3Off;
+		info->start[3] = baseaddr + SecFlashBSec4Off;
+		info->size = 0x10000;
+		info->sector_count = 4;
+		break;
+	}
+	return (info->size);
+}
+
+unsigned long flash_init(void)
+{
+	unsigned long size_b0, size_b1, size_b2;
+	int i;
+
+	size_b0 = size_b1 = size_b2 = 0;
+#ifdef DEBUG
+	printf("Flash Memory Start 0x%x\n", CFG_FLASH_BASE);
+	printf("Memory Map for the Flash\n");
+	printf("0x20000000 - 0x200FFFFF Flash A Primary (1MB)\n");
+	printf("0x20100000 - 0x201FFFFF Flash B Primary (1MB)\n");
+	printf("0x20200000 - 0x2020FFFF Flash A Secondary (64KB)\n");
+	printf("0x20280000 - 0x2028FFFF Flash B Secondary (64KB)\n");
+	printf("Please type command flinfo for information on Sectors \n");
+#endif
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	size_b0 = flash_get_size(CFG_FLASH0_BASE, &flash_info[0], 0);
+	size_b1 = flash_get_size(CFG_FLASH0_BASE, &flash_info[1], 1);
+	size_b2 = flash_get_size(CFG_FLASH0_BASE, &flash_info[2], 2);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN || size_b0 == 0) {
+		printf("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+			size_b0, size_b0 >> 20);
+	}
+
+	(void)flash_protect(FLAG_PROTECT_SET,CFG_FLASH0_BASE,(flash_info[0].start[2] - 1),&flash_info[0]);
+
+	return (size_b0 + size_b1 + size_b2);
+}
+
+void flash_print_info(flash_info_t * info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id) {
+	case FLASH_PSD4256GV:
+		printf("ST Microelectronics ");
+		break;
+	default:
+		printf("Unknown Vendor ");
+		break;
+	}
+	for (i = 0; i < info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf("\n   ");
+		printf(" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     ");
+	}
+	printf("\n");
+	return;
+}
+
+int flash_erase(flash_info_t * info, int s_first, int s_last)
+{
+	int cnt = 0,i;
+	int prot,sect;
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect])
+			prot++;
+	}
+
+	if (prot)
+		printf ("- Warning: %d protected sectors will not be erased!\n", prot);
+	else
+		printf ("\n");
+
+	cnt = s_last - s_first + 1;
+
+	if (cnt == FLASH_TOT_SECT) {
+		printf("Erasing flash, Please Wait \n");
+		if(erase_flash() < 0) {
+			printf("Erasing flash failed \n");
+			return FLASH_FAIL;
+		}
+	} else {
+		printf("Erasing Flash locations, Please Wait\n");
+		for (i = s_first; i <= s_last; i++) {
+			if (info->protect[i] == 0) {	/* not protected */
+				if(erase_block_flash(i, info->start[i]) < 0) {
+					printf("Error Sector erasing \n");
+					return FLASH_FAIL;
+				}
+			}
+		}
+	}
+	return FLASH_SUCCESS;
+}
+
+int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	int ret;
+
+	ret = write_data(addr, cnt, 1, (int *) src);
+	if(ret == FLASH_FAIL)
+		return ERR_NOT_ERASED;
+	return FLASH_SUCCESS;
+}
+
+
+int write_data(long lStart, long lCount, long lStride, int *pnData)
+{
+	long i = 0;
+	int j = 0;
+	unsigned long ulOffset = lStart - CFG_FLASH_BASE;
+	int d;
+	int iShift = 0;
+	int iNumWords = 2;
+	int nLeftover = lCount % 4;
+	int nSector = 0;
+
+	for (i = 0; (i < lCount / 4) && (i < BUFFER_SIZE); i++) {
+		for (iShift = 0, j = 0; (j < iNumWords);
+			j++, ulOffset += (lStride * 2)) {
+			if ((ulOffset >= INVALIDLOCNSTART)
+			&& (ulOffset < INVALIDLOCNEND)) {
+				printf("Invalid locations, Try writing to another location \n");
+				return FLASH_FAIL;
+			}
+			get_sector_number(ulOffset, &nSector);
+			read_flash(ulOffset,&d);
+			if(d != 0xffff) {
+				printf("Flash not erased at offset 0x%x Please erase to reprogram \n",ulOffset);
+				return FLASH_FAIL;
+			}
+			unlock_flash(ulOffset);
+			if(write_flash(ulOffset, (pnData[i] >> iShift)) < 0) {
+				printf("Error programming the flash \n");
+				return FLASH_FAIL;
+			}
+			iShift += 16;
+		}
+	}
+	if (nLeftover > 0) {
+		if ((ulOffset >= INVALIDLOCNSTART)
+			&& (ulOffset < INVALIDLOCNEND))
+				return FLASH_FAIL;
+		get_sector_number(ulOffset, &nSector);
+		read_flash(ulOffset,&d);
+		if(d != 0xffff) {
+			printf("Flash already programmed. Please erase to reprogram \n");
+			printf("uloffset = 0x%x \t d = 0x%x\n",ulOffset,d);
+			return FLASH_FAIL;
+		}
+		unlock_flash(ulOffset);
+		if(write_flash(ulOffset, pnData[i]) < 0) {
+			printf("Error programming the flash \n");
+			return FLASH_FAIL;
+		}
+	}
+	return FLASH_SUCCESS;
+}
+
+int read_data(long ulStart, long lCount, long lStride, int *pnData)
+{
+	long i = 0;
+	int j = 0;
+	long ulOffset = ulStart;
+	int iShift = 0;
+	int iNumWords = 2;
+	int nLeftover = lCount % 4;
+	int nHi, nLow;
+	int nSector = 0;
+
+	for (i = 0; (i < lCount / 4) && (i < BUFFER_SIZE); i++) {
+		for (iShift = 0, j = 0; j < iNumWords; j += 2) {
+			if ((ulOffset >= INVALIDLOCNSTART)
+				&& (ulOffset < INVALIDLOCNEND))
+					return FLASH_FAIL;
+
+			get_sector_number(ulOffset, &nSector);
+			read_flash(ulOffset, &nLow);
+			ulOffset += (lStride * 2);
+			read_flash(ulOffset, &nHi);
+			ulOffset += (lStride * 2);
+			pnData[i] = (nHi << 16) | nLow;
+		}
+	}
+	if (nLeftover > 0) {
+		if ((ulOffset >= INVALIDLOCNSTART)
+			&& (ulOffset < INVALIDLOCNEND))
+				return FLASH_FAIL;
+
+		get_sector_number(ulOffset, &nSector);
+		read_flash(ulOffset, &pnData[i]);
+	}
+	return FLASH_SUCCESS;
+}
+
+int write_flash(long nOffset, int nValue)
+{
+	long addr;
+
+	addr = (CFG_FLASH_BASE + nOffset);
+	asm("ssync;");
+	*(unsigned volatile short *) addr = nValue;
+	asm("ssync;");
+	if(poll_toggle_bit(nOffset) < 0)
+		return FLASH_FAIL;
+	return FLASH_SUCCESS;
+}
+
+int read_flash(long nOffset, int *pnValue)
+{
+	int nValue = 0x0;
+	long addr = (CFG_FLASH_BASE + nOffset);
+
+	if (nOffset != 0x2)
+		reset_flash();
+	asm("ssync;");
+	nValue = *(volatile unsigned short *) addr;
+	asm("ssync;");
+	*pnValue = nValue;
+	return TRUE;
+}
+
+int poll_toggle_bit(long lOffset)
+{
+	unsigned int u1,u2;
+	unsigned long timeout = 0xFFFFFFFF;
+	volatile unsigned long *FB = (volatile unsigned long *)(0x20000000 + lOffset);
+	while(1) {
+		if(timeout < 0)
+			break;
+		u1 = *(volatile unsigned short *)FB;
+		u2 = *(volatile unsigned short *)FB;
+		if((u1 & 0x0040) == (u2 & 0x0040))
+			return FLASH_SUCCESS;
+		if((u2 & 0x0020) == 0x0000)
+			continue;
+		u1 = *(volatile unsigned short *)FB;
+		if((u2 & 0x0040) == (u1 & 0x0040))
+			return FLASH_SUCCESS;
+		else {
+			reset_flash();
+			return FLASH_FAIL;
+		}
+		timeout--;
+	}
+	printf("Time out occured \n");
+	if(timeout <0)	return FLASH_FAIL;
+}
+
+void reset_flash(void)
+{
+	write_flash(WRITESEQ1, RESET_VAL);
+	/* Wait for 10 micro seconds */
+	udelay(10);
+}
+
+int erase_flash(void)
+{
+	write_flash(WRITESEQ1, WRITEDATA1);
+	write_flash(WRITESEQ2, WRITEDATA2);
+	write_flash(WRITESEQ3, WRITEDATA3);
+	write_flash(WRITESEQ4, WRITEDATA4);
+	write_flash(WRITESEQ5, WRITEDATA5);
+	write_flash(WRITESEQ6, WRITEDATA6);
+
+	if(poll_toggle_bit(0x0000) < 0)
+		return FLASH_FAIL;
+
+	write_flash(SecFlashAOff + WRITESEQ1, WRITEDATA1);
+	write_flash(SecFlashAOff + WRITESEQ2, WRITEDATA2);
+	write_flash(SecFlashAOff + WRITESEQ3, WRITEDATA3);
+	write_flash(SecFlashAOff + WRITESEQ4, WRITEDATA4);
+	write_flash(SecFlashAOff + WRITESEQ5, WRITEDATA5);
+	write_flash(SecFlashAOff + WRITESEQ6, WRITEDATA6);
+
+	if(poll_toggle_bit(SecFlashASec1Off) < 0)
+		return FLASH_FAIL;
+
+	write_flash(PriFlashBOff + WRITESEQ1, WRITEDATA1);
+	write_flash(PriFlashBOff + WRITESEQ2, WRITEDATA2);
+	write_flash(PriFlashBOff + WRITESEQ3, WRITEDATA3);
+	write_flash(PriFlashBOff + WRITESEQ4, WRITEDATA4);
+	write_flash(PriFlashBOff + WRITESEQ5, WRITEDATA5);
+	write_flash(PriFlashBOff + WRITESEQ6, WRITEDATA6);
+
+	if(poll_toggle_bit(PriFlashBOff) <0)
+		return FLASH_FAIL;
+
+	write_flash(SecFlashBOff + WRITESEQ1, WRITEDATA1);
+	write_flash(SecFlashBOff + WRITESEQ2, WRITEDATA2);
+	write_flash(SecFlashBOff + WRITESEQ3, WRITEDATA3);
+	write_flash(SecFlashBOff + WRITESEQ4, WRITEDATA4);
+	write_flash(SecFlashBOff + WRITESEQ5, WRITEDATA5);
+	write_flash(SecFlashBOff + WRITESEQ6, WRITEDATA6);
+
+	if(poll_toggle_bit(SecFlashBOff) < 0)
+		return FLASH_FAIL;
+
+	return FLASH_SUCCESS;
+}
+
+int erase_block_flash(int nBlock, unsigned long address)
+{
+	long ulSectorOff = 0x0;
+
+	if ((nBlock < 0) || (nBlock > AFP_NumSectors))
+		return FALSE;
+
+	ulSectorOff = (address - CFG_FLASH_BASE);
+
+	write_flash((WRITESEQ1 | ulSectorOff), WRITEDATA1);
+	write_flash((WRITESEQ2 | ulSectorOff), WRITEDATA2);
+	write_flash((WRITESEQ3 | ulSectorOff), WRITEDATA3);
+	write_flash((WRITESEQ4 | ulSectorOff), WRITEDATA4);
+	write_flash((WRITESEQ5 | ulSectorOff), WRITEDATA5);
+
+	write_flash(ulSectorOff, BlockEraseVal);
+
+	if(poll_toggle_bit(ulSectorOff) < 0)
+		return FLASH_FAIL;
+
+	return FLASH_SUCCESS;
+}
+
+void unlock_flash(long ulOffset)
+{
+	unsigned long ulOffsetAddr = ulOffset;
+	ulOffsetAddr &= 0xFFFF0000;
+
+	write_flash((WRITESEQ1 | ulOffsetAddr), UNLOCKDATA1);
+	write_flash((WRITESEQ2 | ulOffsetAddr), UNLOCKDATA2);
+	write_flash((WRITESEQ3 | ulOffsetAddr), UNLOCKDATA3);
+}
+
+int get_codes()
+{
+	int dev_id = 0;
+
+	write_flash(WRITESEQ1, GETCODEDATA1);
+	write_flash(WRITESEQ2, GETCODEDATA2);
+	write_flash(WRITESEQ3, GETCODEDATA3);
+
+	read_flash(0x0002, &dev_id);
+	dev_id &= 0x00FF;
+
+	reset_flash();
+
+	return dev_id;
+}
+
+void get_sector_number(long ulOffset, int *pnSector)
+{
+	int nSector = 0;
+
+	if (ulOffset >= SecFlashAOff) {
+		if ((ulOffset < SecFlashASec1Off)
+			&& (ulOffset < SecFlashASec2Off)) {
+				nSector = SECT32;
+		} else if ((ulOffset >= SecFlashASec2Off)
+			&& (ulOffset < SecFlashASec3Off)) {
+				nSector = SECT33;
+		} else if ((ulOffset >= SecFlashASec3Off)
+			&& (ulOffset < SecFlashASec4Off)) {
+				nSector = SECT34;
+		} else if ((ulOffset >= SecFlashASec4Off)
+			&& (ulOffset < SecFlashAEndOff)) {
+				nSector = SECT35;
+		}
+	} else if (ulOffset >= SecFlashBOff) {
+		if ((ulOffset < SecFlashBSec1Off)
+			&& (ulOffset < SecFlashBSec2Off)) {
+				nSector = SECT36;
+		}
+		if ((ulOffset < SecFlashBSec2Off)
+			&& (ulOffset < SecFlashBSec3Off)) {
+				nSector = SECT37;
+		}
+		if ((ulOffset < SecFlashBSec3Off)
+			&& (ulOffset < SecFlashBSec4Off)) {
+				nSector = SECT38;
+		}
+		if ((ulOffset < SecFlashBSec4Off)
+			&& (ulOffset < SecFlashBEndOff)) {
+				nSector = SECT39;
+		}
+	} else if ((ulOffset >= PriFlashAOff) && (ulOffset < SecFlashAOff)) {
+		nSector = ulOffset & 0xffff0000;
+		nSector = ulOffset >> 16;
+		nSector = nSector & 0x000ff;
+	}
+
+	if ((nSector >= 0) && (nSector < AFP_NumSectors)) {
+		*pnSector = nSector;
+	}
+}
diff --git a/board/ezkit533/psd4256.h b/board/ezkit533/psd4256.h
new file mode 100644
index 0000000..01f6566
--- /dev/null
+++ b/board/ezkit533/psd4256.h
@@ -0,0 +1,67 @@
+/*
+ * U-boot - psd4256.h
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Flash A/B Port A configuration registers.
+ * Addresses are offset values to CFG_FLASH1_BASE
+ * for Flash A and CFG_FLASH2_BASE for Flash B.
+ */
+
+#define	PSD_PORTA_DIN	0x070000
+#define	PSD_PORTA_DOUT	0x070004
+#define	PSD_PORTA_DIR	0x070006
+
+/*
+ * Flash A/B Port B configuration registers
+ * Addresses are offset values to CFG_FLASH1_BASE
+ * for Flash A and CFG_FLASH2_BASE for Flash B.
+ */
+
+#define	PSD_PORTB_DIN	0x070001
+#define	PSD_PORTB_DOUT	0x070005
+#define	PSD_PORTB_DIR	0x070007
+
+/*
+ * Flash A Port A Bit definitions
+ */
+
+#define	PSDA_PPICLK1	0x20		/* PPI Clock select bit 1		*/
+#define	PSDA_PPICLK0	0x10		/* PPI Clock select bit 0		*/
+#define	PSDA_VDEC_RST	0x08		/* Video decoder reset, 0 = RESET	*/
+#define	PSDA_VENC_RST	0x04		/* Video encoder reset, 0 = RESET	*/
+#define	PSDA_CODEC_RST	0x01		/* Codec reset, 0 = RESET		*/
+
+/*
+ * Flash A Port B Bit definitions
+ */
+
+#define	PSDA_LED9	0x20		/* LED 9, 1 = LED ON			*/
+#define	PSDA_LED8	0x10		/* LED 8, 1 = LED ON			*/
+#define	PSDA_LED7	0x08		/* LED 7, 1 = LED ON			*/
+#define	PSDA_LED6	0x04		/* LED 6, 1 = LED ON			*/
+#define	PSDA_LED5	0x02		/* LED 5, 1 = LED ON			*/
+#define	PSDA_LED4	0x01		/* LED 4, 1 = LED ON			*/
diff --git a/board/ezkit533/u-boot.lds b/board/ezkit533/u-boot.lds
new file mode 100644
index 0000000..10203ff
--- /dev/null
+++ b/board/ezkit533/u-boot.lds
@@ -0,0 +1,148 @@
+/*
+ * U-boot - u-boot.lds
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(bfin)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)	}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)	}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)	}
+  .rela.got      : { *(.rela.got)	}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)	}
+  .rela.bss      : { *(.rela.bss)	}
+  .rel.plt       : { *(.rel.plt)	}
+  .rela.plt      : { *(.rela.plt)	}
+  .init          : { *(.init)		}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector before the environment sector. If it throws 	*/
+    /* an error during compilation remove an object here to get	*/
+    /* it linked after the configuration sector.		*/
+
+    cpu/bf533/start.o		(.text)
+    cpu/bf533/start1.o		(.text)
+    cpu/bf533/traps.o		(.text)
+    cpu/bf533/interrupt.o	(.text)
+    cpu/bf533/serial.o		(.text)
+    common/dlmalloc.o		(.text)
+    lib_generic/vsprintf.o	(.text)
+    lib_generic/crc32.o		(.text)
+    lib_generic/zlib.o		(.text)
+    board/ezkit533/ezkit533.o		(.text)
+
+    . = DEFINED(env_offset) ? env_offset : .;
+    common/environment.o	(.text)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/fads/fads.c b/board/fads/fads.c
index 013b3cb..7b04af5 100644
--- a/board/fads/fads.c
+++ b/board/fads/fads.c
@@ -726,24 +726,23 @@ static void checkdboard(void)
 
 int checkboard (void)
 {
-	/* get revision from BCSR 3 */
+#if   defined(CONFIG_MPC86xADS)
+	puts ("Board: MPC86xADS\n");
+#elif defined(CONFIG_MPC885ADS)
+	puts ("Board: MPC885ADS\n");
+#else /* Only old ADS/FADS have got revision ID in BCSR3 */
 	uint r =  (((*((uint *) BCSR3) >> 23) & 1) << 3)
 		| (((*((uint *) BCSR3) >> 19) & 1) << 2)
 		| (((*((uint *) BCSR3) >> 16) & 3));
 
 	puts ("Board: ");
-
-#if defined(CONFIG_MPC86xADS)
-	puts ("MPC86xADS");
-#elif defined(CONFIG_MPC885ADS)
-	puts ("MPC885ADS");
-	r = 0; /* I've got NR (No Revision) board */
-#elif defined(CONFIG_FADS)
+#if defined(CONFIG_FADS)
 	puts ("FADS");
 	checkdboard ();
 #else
 	puts ("ADS");
 #endif
+
 	puts (" rev ");
 
 	switch (r) {
@@ -758,13 +757,9 @@ int checkboard (void)
 		puts ("A - warning, read errata \n");
 		break;
 	case 0x03:
-		puts ("B \n");
+		puts ("B\n");
 		break;
-#elif defined(CONFIG_MPC885ADS)
-	case 0x00:
-		puts ("NR\n");
-		break;
-#else  /* FADS and newer */
+#else  /* FADS */
 	case 0x00:
 		puts ("ENG\n");
 		break;
@@ -776,6 +771,7 @@ int checkboard (void)
 		printf ("unknown (0x%x)\n", r);
 		return -1;
 	}
+#endif /* CONFIG_MPC86xADS */
 
 	return 0;
 }
@@ -848,7 +844,7 @@ int pcmcia_init(void)
 	switch ((pcmp->pcmc_pipr >> 14) & 3)
 #endif
 	{
-	case 0x00 :
+	case 0x03 :
 		printf("5V");
 		v = 5;
 		break;
@@ -860,7 +856,7 @@ int pcmcia_init(void)
 		v = 5;
 #endif
 		break;
-	case 0x03 :
+	case 0x00 :
 		printf("5V, 3V and x.xV");
 #ifdef CONFIG_FADS
 		v = 3; /* User lower voltage if supported! */
diff --git a/board/fads/fads.h b/board/fads/fads.h
index 1127c7f..e981be0 100644
--- a/board/fads/fads.h
+++ b/board/fads/fads.h
@@ -55,18 +55,26 @@
 #define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
 #endif
 
-#undef	CONFIG_BOOTARGS
-#define CONFIG_BOOTCOMMAND							\
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_NFSBOOTCOMMAND							\
     "dhcp;"									\
-    "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "		\
-    "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;"	\
+    "setenv bootargs root=/dev/nfs rw nfsroot=$rootpath "			\
+    "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:eth0:off;"		\
     "bootm"
 
+#define CONFIG_BOOTCOMMAND							\
+    "setenv bootargs root=/dev/mtdblock2 rw mtdparts=phys:1280K(ROM)ro,-(root) "\
+    "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:eth0:off;"		\
+    "bootm fe080000"
+
+#undef CONFIG_BOOTARGS
+
 #undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
 #define CONFIG_BZIP2	 /* include support for bzip2 compressed images */
 
 /*
- * New MPC86xADS and Duet provide two Ethernet connectivity options:
+ * New MPC86xADS and MPC885ADS provide two Ethernet connectivity options:
  * 10Mbit/s on SCC and 100Mbit/s on FEC. FADS provides SCC Ethernet on
  * motherboard and FEC Ethernet on daughterboard. All new PQ1 chips have
  * got FEC so FEC is the default.
@@ -89,7 +97,9 @@
 
 #ifndef CONFIG_COMMANDS
 #define CONFIG_COMMANDS	(CONFIG_CMD_DFL   \
+			 | CFG_CMD_ASKENV \
 			 | CFG_CMD_DHCP   \
+			 | CFG_CMD_ECHO   \
 			 | CFG_CMD_IMMAP  \
 			 | CFG_CMD_JFFS2  \
 			 | CFG_CMD_MII    \
@@ -104,16 +114,18 @@
 /*
  * Miscellaneous configurable options
  */
-#undef	CFG_LONGHELP			/* undef to save memory		*/
-#define	CFG_PROMPT		"=>"	/* Monitor Command Prompt	*/
+#define	CFG_PROMPT		"=>"		/* Monitor Command Prompt	*/
+#define CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2	"> "
+#define	CFG_LONGHELP				/* #undef to save memory	*/
 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#define	CFG_CBSIZE		1024		/* Console I/O Buffer Size	*/
 #else
-#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#define	CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
 #endif
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define	CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) /* Print Buffer Size	*/
+#define	CFG_MAXARGS		16		/* max number of command args	*/
+#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
 
 #define CFG_LOAD_ADDR	 	0x00100000
 
@@ -126,6 +138,7 @@
  * (address mappings, register initial values, etc.)
  * You should know what you are doing if you make changes here.
  */
+
 /*-----------------------------------------------------------------------
  * Internal Memory Mapped Register
  */
@@ -148,6 +161,14 @@
 #define	CFG_SDRAM_BASE		0x00000000
 #if defined(CONFIG_MPC86xADS) || defined(CONFIG_MPC885ADS) /* New ADS or Duet */
 #define	CFG_SDRAM_SIZE		0x00800000      	/* 8 Mbyte */
+/*
+ * 2048	SDRAM rows
+ * 1000	factor s -> ms
+ * 64	PTP (pre-divider from MPTPR) from SDRAM example configuration
+ * 4	Number of refresh cycles per period
+ * 64	Refresh cycle in ms per number of rows
+ */
+#define CFG_PTA_PER_CLK		((2048 * 64 * 1000) / (4 * 64))
 #elif defined(CONFIG_FADS)				/* Old/new FADS */
 #define	CFG_SDRAM_SIZE		0x00400000		/* 4 Mbyte */
 #else							/* Old ADS */
@@ -223,9 +244,7 @@
  * Cache Configuration
  */
 #define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 #define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
-#endif
 
 /*-----------------------------------------------------------------------
  * I2C configuration
@@ -277,31 +296,21 @@
  * power management and some other internal clocks
  */
 #define SCCR_MASK	SCCR_EBDF11
-#define CFG_SCCR	(SCCR_TBS|SCCR_COM00|SCCR_DFSYNC00|SCCR_DFBRG00|SCCR_DFNL000|SCCR_DFNH000|SCCR_DFLCD000|SCCR_DFALCD00)
+#define CFG_SCCR	SCCR_TBS
 
 /*-----------------------------------------------------------------------
- * PLPRCR - PLL, Low-Power, and Reset Control Register		14-22
+ * DER - Debug Enable Register
  *-----------------------------------------------------------------------
- * set the PLL, the low-power modes and the reset control
- */
-#ifndef CFG_PLPRCR
-#define CFG_PLPRCR	PLPRCR_TEXPS
-#endif
-
-/*-----------------------------------------------------------------------
- *
- *-----------------------------------------------------------------------
- *
+ * Set to zero to prevent the processor from entering debug mode
  */
 #define CFG_DER		 0
 
-/* Because of the way the 860 starts up and assigns CS0 the
-* entire address space, we have to set the memory controller
-* differently.  Normally, you write the option register
-* first, and then enable the chip select by writing the
-* base register.  For CS0, you must write the base register
-* first, followed by the option register.
-*/
+/* Because of the way the 860 starts up and assigns CS0 the entire
+ * address space, we have to set the memory controller differently.
+ * Normally, you write the option register first, and then enable the
+ * chip select by writing the base register.  For CS0, you must write
+ * the base register first, followed by the option register.
+ */
 
 /*
  * Init Memory Controller:
@@ -335,9 +344,6 @@
 
 /* values according to the manual */
 
-#define PCMCIA_MEM_ADDR		((uint)0xFF020000)
-#define PCMCIA_MEM_SIZE		((uint)(64 * 1024))
-
 #define	BCSR0			((uint) (BCSR_ADDR + 0x00))
 #define	BCSR1			((uint) (BCSR_ADDR + 0x04))
 #define	BCSR2			((uint) (BCSR_ADDR + 0x08))
@@ -396,59 +402,28 @@
 #define BCSR4_TFPLDL             ((uint)0x40000000)
 #define BCSR4_TPSQEL             ((uint)0x20000000)
 #define BCSR4_SIGNAL_LAMP        ((uint)0x10000000)
-#define BCSR4_FETH_EN            ((uint)0x08000000)
-#define BCSR4_FETHCFG0           ((uint)0x04000000)
-#define BCSR4_FETHFDE            ((uint)0x02000000)
-#define BCSR4_FETHCFG1           ((uint)0x00400000)
-#define BCSR4_FETHRST            ((uint)0x00200000)
-
-#ifdef CONFIG_MPC823
+#if defined(CONFIG_MPC823)
 #define BCSR4_USB_EN             ((uint)0x08000000)
-#endif /* CONFIG_MPC823 */
-#ifdef CONFIG_MPC860SAR
-#define BCSR4_UTOPIA_EN          ((uint)0x08000000)
-#endif /* CONFIG_MPC860SAR */
-#ifdef CONFIG_MPC860T
-#define BCSR4_FETH_EN            ((uint)0x08000000)
-#endif /* CONFIG_MPC860T */
-#ifdef CONFIG_MPC823
 #define BCSR4_USB_SPEED          ((uint)0x04000000)
-#endif /* CONFIG_MPC823 */
-#ifdef CONFIG_MPC860T
-#define BCSR4_FETHCFG0           ((uint)0x04000000)
-#endif /* CONFIG_MPC860T */
-#ifdef CONFIG_MPC823
 #define BCSR4_VCCO               ((uint)0x02000000)
-#endif /* CONFIG_MPC823 */
-#ifdef CONFIG_MPC860T
-#define BCSR4_FETHFDE            ((uint)0x02000000)
-#endif /* CONFIG_MPC860T */
-#ifdef CONFIG_MPC823
 #define BCSR4_VIDEO_ON           ((uint)0x00800000)
-#endif /* CONFIG_MPC823 */
-#ifdef CONFIG_MPC823
 #define BCSR4_VDO_EKT_CLK_EN     ((uint)0x00400000)
-#endif /* CONFIG_MPC823 */
-#ifdef CONFIG_MPC860T
-#define BCSR4_FETHCFG1           ((uint)0x00400000)
-#endif /* CONFIG_MPC860T */
-#ifdef CONFIG_MPC823
 #define BCSR4_VIDEO_RST          ((uint)0x00200000)
-#endif /* CONFIG_MPC823 */
-#ifdef CONFIG_MPC860T
-#define BCSR4_FETHRST            ((uint)0x00200000)
-#endif /* CONFIG_MPC860T */
-#ifdef CONFIG_MPC823
 #define BCSR4_MODEM_EN           ((uint)0x00100000)
-#endif /* CONFIG_MPC823 */
-#ifdef CONFIG_MPC823
 #define BCSR4_DATA_VOICE         ((uint)0x00080000)
-#endif /* CONFIG_MPC823 */
-#ifdef CONFIG_MPC850
+#elif defined(CONFIG_MPC850)
 #define BCSR4_DATA_VOICE         ((uint)0x00080000)
-#endif /* CONFIG_MPC850 */
+#elif defined(CONFIG_MPC860SAR)
+#define BCSR4_UTOPIA_EN          ((uint)0x08000000)
+#else /* MPC860T and other chips with FEC */
+#define BCSR4_FETH_EN            ((uint)0x08000000)
+#define BCSR4_FETHCFG0           ((uint)0x04000000)
+#define BCSR4_FETHFDE            ((uint)0x02000000)
+#define BCSR4_FETHCFG1           ((uint)0x00400000)
+#define BCSR4_FETHRST            ((uint)0x00200000)
+#endif
 
-/* BSCR5 exists on MPC86xADS and Duet ADS only */
+/* BSCR5 exists on MPC86xADS and MPC885ADS only */
 
 #define CFG_PHYDEV_ADDR		(BCSR_ADDR + 0x20000)
 
@@ -511,4 +486,4 @@
 #define CFG_ATA_ALT_OFFSET	0x0000
 
 #define CONFIG_DISK_SPINUP_TIME 1000000
-#undef CONFIG_DISK_SPINUP_TIME	/* usin´ Compact Flash */
+/* #undef CONFIG_DISK_SPINUP_TIME */	/* usin  Compact Flash */
diff --git a/board/icecube/flash.c b/board/icecube/flash.c
index 713011c..15e86d3 100644
--- a/board/icecube/flash.c
+++ b/board/icecube/flash.c
@@ -23,6 +23,7 @@
 
 #include <common.h>
 
+#ifndef CFG_FLASH_CFI_DRIVER
 flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
 
 /* NOTE - CONFIG_FLASH_16BIT means the CPU interface is 16-bit, it
@@ -489,3 +490,4 @@ static int write_word_amd (flash_info_t *info, FPWV *dest, FPW data)
 
 	return (res);
 }
+#endif /*CFG_FLASH_CFI_DRIVER*/
diff --git a/board/icecube/icecube.c b/board/icecube/icecube.c
index 1f1a74c..44831c6 100644
--- a/board/icecube/icecube.c
+++ b/board/icecube/icecube.c
@@ -28,12 +28,15 @@
 #include <mpc5xxx.h>
 #include <pci.h>
 
-#if defined(CONFIG_MPC5200_DDR)
-#include "mt46v16m16-75.h"
+#if defined(CONFIG_LITE5200B)
+#include "mt46v32m16.h"
 #else
+# if defined(CONFIG_MPC5200_DDR)
+#  include "mt46v16m16-75.h"
+# else
 #include "mt48lc16m16a2-75.h"
+# endif
 #endif
-
 #ifndef CFG_RAMBOOT
 static void sdram_start (int hi_addr)
 {
@@ -236,7 +239,9 @@ long int initdram (int board_type)
 
 int checkboard (void)
 {
-#if defined(CONFIG_MPC5200)
+#if defined (CONFIG_LITE5200B)
+	puts ("Board: Freescale Lite5200B\n");
+#elif defined(CONFIG_MPC5200)
 	puts ("Board: Motorola MPC5200 (IceCube)\n");
 #elif defined(CONFIG_MGT5100)
 	puts ("Board: Motorola MGT5100 (IceCube)\n");
diff --git a/board/icecube/mt46v32m16.h b/board/icecube/mt46v32m16.h
new file mode 100644
index 0000000..de2b48b
--- /dev/null
+++ b/board/icecube/mt46v32m16.h
@@ -0,0 +1,37 @@
+/*
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#define SDRAM_DDR	1		/* is DDR */
+
+#if defined(CONFIG_MPC5200)
+/* Settings for XLB = 132 MHz */
+#define SDRAM_MODE	0x018D0000
+#define SDRAM_EMODE	0x40090000
+#define SDRAM_CONTROL	0x704f0f00
+#define SDRAM_CONFIG1	0x73722930
+#define SDRAM_CONFIG2	0x47770000
+#define SDRAM_TAPDELAY	0x10000000
+
+#else
+#error CONFIG_MPC5200 not defined
+#endif
diff --git a/board/lart/flash.c b/board/lart/flash.c
index 5232ed2..28c4531 100644
--- a/board/lart/flash.c
+++ b/board/lart/flash.c
@@ -348,7 +348,7 @@ outahere:
  * Copy memory to flash
  */
 
-volatile static int write_word (flash_info_t *info, ulong dest, ulong data)
+static int write_word (flash_info_t *info, ulong dest, ulong data)
 {
     vu_long *addr = (vu_long *)dest;
     ulong result;
diff --git a/board/lpd7a40x/flash.c b/board/lpd7a40x/flash.c
index 2dfe376..d18720e 100644
--- a/board/lpd7a40x/flash.c
+++ b/board/lpd7a40x/flash.c
@@ -351,8 +351,7 @@ outahere:
  * Copy memory to flash
  */
 
-volatile static int write_word (flash_info_t * info, ulong dest,
-								ulong data)
+static int write_word (flash_info_t * info, ulong dest, ulong data)
 {
 	vu_long *addr = (vu_long *) dest;
 	ulong result;
diff --git a/board/m5272c3/flash.c b/board/m5272c3/flash.c
index fb91843..f156342 100644
--- a/board/m5272c3/flash.c
+++ b/board/m5272c3/flash.c
@@ -256,8 +256,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last)
 	return rc;
 }
 
-
-volatile static int write_word (flash_info_t * info, ulong dest, ulong data)
+static int write_word (flash_info_t * info, ulong dest, ulong data)
 {
 	volatile u16 *addr = (volatile u16 *) dest;
 	ulong result;
diff --git a/board/m5282evb/flash.c b/board/m5282evb/flash.c
index ff70783..95f35ad 100644
--- a/board/m5282evb/flash.c
+++ b/board/m5282evb/flash.c
@@ -256,8 +256,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last)
 	return rc;
 }
 
-
-volatile static int write_word (flash_info_t * info, ulong dest, ulong data)
+static int write_word (flash_info_t * info, ulong dest, ulong data)
 {
 	volatile u16 *addr = (volatile u16 *) dest;
 	ulong result;
diff --git a/board/mpc8349ads/Makefile b/board/mpc8349ads/Makefile
index 4327b0d..f865f9c 100644
--- a/board/mpc8349ads/Makefile
+++ b/board/mpc8349ads/Makefile
@@ -24,7 +24,7 @@ include $(TOPDIR)/config.mk
 
 LIB	= lib$(BOARD).a
 
-OBJS	:= $(BOARD).o
+OBJS	:= $(BOARD).o pci.o
 
 $(LIB):	$(OBJS) $(SOBJS)
 	$(AR) crv $@ $(OBJS)
diff --git a/board/mpc8349ads/mpc8349ads.c b/board/mpc8349ads/mpc8349ads.c
index da8d3d7..505acbc 100644
--- a/board/mpc8349ads/mpc8349ads.c
+++ b/board/mpc8349ads/mpc8349ads.c
@@ -147,47 +147,6 @@ int checkboard (void)
 	return 0;
 }
 
-#if defined(CONFIG_PCI)
-/*
- * Initialize PCI Devices, report devices found
- */
-#ifndef CONFIG_PCI_PNP
-static struct pci_config_table pci_mpc83xxads_config_table[] = {
-	{PCI_ANY_ID,PCI_ANY_ID,PCI_ANY_ID,PCI_ANY_ID,
-	pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
-				    PCI_ENET0_MEMADDR,
-				    PCI_COMMON_MEMORY | PCI_COMMAND_MASTER
-	} },
-	{}
-}
-#endif
-
-
-volatile static struct pci_controller hose[] = {
-	{
-#ifndef CONFIG_PCI_PNP
-	config_table:pci_mpc83xxads_config_table,
-#endif
-	},
-	{
-#ifndef CONFIG_PCI_PNP
-	config_table:pci_mpc83xxads_config_table,
-#endif
-	}
-};
-#endif /* CONFIG_PCI */
-
-
-void
-pci_init_board(void)
-{
-#ifdef CONFIG_PCI
-	extern void pci_mpc83xx_init(volatile struct pci_controller *hose);
-
-	pci_mpc83xx_init(hose);
-#endif /* CONFIG_PCI */
-}
-
 /*
  * if MPC8349ADS is soldered with SDRAM
  */
diff --git a/board/mpc8349ads/pci.c b/board/mpc8349ads/pci.c
new file mode 100644
index 0000000..c559424
--- /dev/null
+++ b/board/mpc8349ads/pci.c
@@ -0,0 +1,380 @@
+/*
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <asm/mmu.h>
+#include <common.h>
+#include <asm/global_data.h>
+#include <pci.h>
+#include <asm/mpc8349_pci.h>
+#include <i2c.h>
+
+#ifdef CONFIG_PCI
+
+/* System RAM mapped to PCI space */
+#define CONFIG_PCI_SYS_MEM_BUS	CFG_SDRAM_BASE
+#define CONFIG_PCI_SYS_MEM_PHYS	CFG_SDRAM_BASE
+
+#ifndef CONFIG_PCI_PNP
+static struct pci_config_table pci_mpc83xxads_config_table[] = {
+	{PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
+	 PCI_IDSEL_NUMBER, PCI_ANY_ID,
+ 	 pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
+				     PCI_ENET0_MEMADDR,
+				     PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER
+		}
+	},
+	{}
+};
+#endif
+
+static struct pci_controller pci_hose[] = {
+       {
+#ifndef CONFIG_PCI_PNP
+       config_table:pci_mpc83xxads_config_table,
+#endif
+       },
+       {
+#ifndef CONFIG_PCI_PNP
+       config_table:pci_mpc83xxads_config_table,
+#endif
+       }
+};
+
+/**************************************************************************
+ *
+ * pib_init() -- initialize the PCA9555PW IO expander on the PIB board
+ *
+ */
+void
+pib_init(void)
+{
+	u8 val8;
+	/*
+	 * Assign PIB PMC slot to desired PCI bus
+	 */
+	mpc8349_i2c = (i2c_t*)(CFG_IMMRBAR + CFG_I2C2_OFFSET);
+	i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE);
+
+	val8 = 0;
+	i2c_write(0x23, 0x6, 1, &val8, 1);
+	i2c_write(0x23, 0x7, 1, &val8, 1);
+	val8 = 0xff;
+	i2c_write(0x23, 0x2, 1, &val8, 1);
+	i2c_write(0x23, 0x3, 1, &val8, 1);
+
+	val8 = 0;
+	i2c_write(0x26, 0x6, 1, &val8, 1);
+	val8 = 0x34;
+	i2c_write(0x26, 0x7, 1, &val8, 1);
+#if defined(PCI_64BIT)
+	val8 = 0xf4;	/* PMC2:PCI1/64-bit */
+#elif defined(PCI_ALL_PCI1)
+	val8 = 0xf3;	/* PMC1:PCI1 PMC2:PCI1 PMC3:PCI1 */
+#elif defined(PCI_ONE_PCI1)
+	val8 = 0xf9;	/* PMC1:PCI1 PMC2:PCI2 PMC3:PCI2 */
+#else
+	val8 = 0xf5;	/* PMC1:PCI1 PMC2:PCI1 PMC3:PCI2 */
+#endif
+	i2c_write(0x26, 0x2, 1, &val8, 1);
+	val8 = 0xff;
+	i2c_write(0x26, 0x3, 1, &val8, 1);
+	val8 = 0;
+	i2c_write(0x27, 0x6, 1, &val8, 1);
+	i2c_write(0x27, 0x7, 1, &val8, 1);
+	val8 = 0xff;
+	i2c_write(0x27, 0x2, 1, &val8, 1);
+	val8 = 0xef;
+	i2c_write(0x27, 0x3, 1, &val8, 1);
+	asm("eieio");
+
+#if defined(PCI_64BIT)
+	printf("PCI1: 64-bit on PMC2\n");
+#elif defined(PCI_ALL_PCI1)
+	printf("PCI1: 32-bit on PMC1, PMC2, PMC3\n");
+#elif defined(PCI_ONE_PCI1)
+	printf("PCI1: 32-bit on PMC1\n");
+	printf("PCI2: 32-bit on PMC2, PMC3\n");
+#else
+	printf("PCI1: 32-bit on PMC1, PMC2\n");
+	printf("PCI2: 32-bit on PMC3\n");
+#endif
+}
+
+/**************************************************************************
+ * pci_init_board()
+ *
+ * NOTICE: PCI2 is not currently supported
+ *
+ */
+void
+pci_init_board(void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+	volatile immap_t *	immr;
+	volatile clk8349_t *	clk;
+	volatile law8349_t *	pci_law;
+	volatile pot8349_t *	pci_pot;
+	volatile pcictrl8349_t *	pci_ctrl;
+	volatile pciconf8349_t *	pci_conf;
+	u16 reg16;
+	u32 reg32;
+	u32 dev;
+	struct	pci_controller * hose;
+
+	immr = (immap_t *)CFG_IMMRBAR;
+	clk = (clk8349_t *)&immr->clk;
+	pci_law = immr->sysconf.pcilaw;
+	pci_pot = immr->ios.pot;
+	pci_ctrl = immr->pci_ctrl;
+	pci_conf = immr->pci_conf;
+
+	hose = &pci_hose[0];
+
+	pib_init();
+
+	/*
+	 * Configure PCI controller and PCI_CLK_OUTPUT both in 66M mode
+	 */
+
+	reg32 = clk->occr;
+	udelay(2000);
+	clk->occr = 0xff000000;
+	udelay(2000);
+
+	/*
+	 * Release PCI RST Output signal
+	 */
+	pci_ctrl[0].gcr = 0;
+	udelay(2000);
+	pci_ctrl[0].gcr = 1;
+
+#ifdef CONFIG_MPC83XX_PCI2
+	pci_ctrl[1].gcr = 0;
+	udelay(2000);
+	pci_ctrl[1].gcr = 1;
+#endif
+
+	/* We need to wait at least a 1sec based on PCI specs */
+	{
+		int i;
+
+		for (i = 0; i < 1000; ++i)
+			udelay (1000);
+	}
+
+	/*
+	 * Configure PCI Local Access Windows
+	 */
+	pci_law[0].bar = CFG_PCI1_MEM_PHYS & LAWBAR_BAR;
+	pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G;
+
+	pci_law[1].bar = CFG_PCI1_IO_PHYS & LAWBAR_BAR;
+	pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_32M;
+
+	/*
+	 * Configure PCI Outbound Translation Windows
+	 */
+
+	/* PCI1 mem space - prefetch */
+	pci_pot[0].potar = (CFG_PCI1_MEM_BASE >> 12) & POTAR_TA_MASK;
+	pci_pot[0].pobar = (CFG_PCI1_MEM_PHYS >> 12) & POBAR_BA_MASK;
+	pci_pot[0].pocmr = POCMR_EN | POCMR_PREFETCH_EN | (POCMR_CM_256M & POCMR_CM_MASK);
+
+	/* PCI1 IO space */
+	pci_pot[1].potar = (CFG_PCI1_IO_BASE >> 12) & POTAR_TA_MASK;
+	pci_pot[1].pobar = (CFG_PCI1_IO_PHYS >> 12) & POBAR_BA_MASK;
+	pci_pot[1].pocmr = POCMR_EN | POCMR_IO | (POCMR_CM_1M & POCMR_CM_MASK);
+
+	/* PCI1 mmio - non-prefetch mem space */
+	pci_pot[2].potar = (CFG_PCI1_MMIO_BASE >> 12) & POTAR_TA_MASK;
+	pci_pot[2].pobar = (CFG_PCI1_MMIO_PHYS >> 12) & POBAR_BA_MASK;
+	pci_pot[2].pocmr = POCMR_EN | (POCMR_CM_256M & POCMR_CM_MASK);
+
+	/*
+	 * Configure PCI Inbound Translation Windows
+	 */
+
+	/* we need RAM mapped to PCI space for the devices to
+	 * access main memory */
+	pci_ctrl[0].pitar1 = 0x0;
+	pci_ctrl[0].pibar1 = 0x0;
+	pci_ctrl[0].piebar1 = 0x0;
+	pci_ctrl[0].piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | (__ilog2(gd->ram_size) - 1);
+
+	hose->first_busno = 0;
+	hose->last_busno = 0xff;
+
+	/* PCI memory prefetch space */
+	pci_set_region(hose->regions + 0,
+		       CFG_PCI1_MEM_BASE,
+		       CFG_PCI1_MEM_PHYS,
+		       CFG_PCI1_MEM_SIZE,
+		       PCI_REGION_MEM|PCI_REGION_PREFETCH);
+
+	/* PCI memory space */
+	pci_set_region(hose->regions + 1,
+		       CFG_PCI1_MMIO_BASE,
+		       CFG_PCI1_MMIO_PHYS,
+		       CFG_PCI1_MMIO_SIZE,
+		       PCI_REGION_MEM);
+
+	/* PCI IO space */
+	pci_set_region(hose->regions + 2,
+		       CFG_PCI1_IO_BASE,
+		       CFG_PCI1_IO_PHYS,
+		       CFG_PCI1_IO_SIZE,
+		       PCI_REGION_IO);
+
+	/* System memory space */
+	pci_set_region(hose->regions + 3,
+		       CONFIG_PCI_SYS_MEM_BUS,
+		       CONFIG_PCI_SYS_MEM_PHYS,
+		       gd->ram_size,
+		       PCI_REGION_MEM | PCI_REGION_MEMORY);
+
+	hose->region_count = 4;
+
+	pci_setup_indirect(hose,
+			   (CFG_IMMRBAR+0x8300),
+			   (CFG_IMMRBAR+0x8304));
+
+	pci_register_hose(hose);
+
+	/*
+	 * Write to Command register
+	 */
+	reg16 = 0xff;
+	dev = PCI_BDF(hose->first_busno, 0, 0);
+	pci_hose_read_config_word (hose, dev, PCI_COMMAND, &reg16);
+	reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
+	pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16);
+
+	/*
+	 * Clear non-reserved bits in status register.
+	 */
+	pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);
+	pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
+	pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
+
+#ifdef CONFIG_PCI_SCAN_SHOW
+	printf("PCI:   Bus Dev VenId DevId Class Int\n");
+#endif
+	/*
+	 * Hose scan.
+	 */
+	hose->last_busno = pci_hose_scan(hose);
+
+#ifdef CONFIG_MPC83XX_PCI2
+	hose = &pci_hose[1];
+
+	/*
+	 * Configure PCI Outbound Translation Windows
+	 */
+
+	/* PCI2 mem space - prefetch */
+	pci_pot[3].potar = (CFG_PCI2_MEM_BASE >> 12) & POTAR_TA_MASK;
+	pci_pot[3].pobar = (CFG_PCI2_MEM_PHYS >> 12) & POBAR_BA_MASK;
+	pci_pot[3].pocmr = POCMR_EN | POCMR_PCI2 | POCMR_PREFETCH_EN | (POCMR_CM_256M & POCMR_CM_MASK);
+
+	/* PCI2 IO space */
+	pci_pot[4].potar = (CFG_PCI2_IO_BASE >> 12) & POTAR_TA_MASK;
+	pci_pot[4].pobar = (CFG_PCI2_IO_PHYS >> 12) & POBAR_BA_MASK;
+	pci_pot[4].pocmr = POCMR_EN | POCMR_PCI2 | POCMR_IO | (POCMR_CM_1M & POCMR_CM_MASK);
+
+	/* PCI2 mmio - non-prefetch mem space */
+	pci_pot[5].potar = (CFG_PCI2_MMIO_BASE >> 12) & POTAR_TA_MASK;
+	pci_pot[5].pobar = (CFG_PCI2_MMIO_PHYS >> 12) & POBAR_BA_MASK;
+	pci_pot[5].pocmr = POCMR_EN | POCMR_PCI2 | (POCMR_CM_256M & POCMR_CM_MASK);
+
+	/*
+	 * Configure PCI Inbound Translation Windows
+	 */
+
+	/* we need RAM mapped to PCI space for the devices to
+	 * access main memory */
+	pci_ctrl[1].pitar1 = 0x0;
+	pci_ctrl[1].pibar1 = 0x0;
+	pci_ctrl[1].piebar1 = 0x0;
+	pci_ctrl[1].piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | (__ilog2(gd->ram_size) - 1);
+
+	hose->first_busno = pci_hose[0].last_busno + 1;
+	hose->last_busno = 0xff;
+
+	/* PCI memory prefetch space */
+	pci_set_region(hose->regions + 0,
+		       CFG_PCI2_MEM_BASE,
+		       CFG_PCI2_MEM_PHYS,
+		       CFG_PCI2_MEM_SIZE,
+		       PCI_REGION_MEM|PCI_REGION_PREFETCH);
+
+	/* PCI memory space */
+	pci_set_region(hose->regions + 1,
+		       CFG_PCI2_MMIO_BASE,
+		       CFG_PCI2_MMIO_PHYS,
+		       CFG_PCI2_MMIO_SIZE,
+		       PCI_REGION_MEM);
+
+	/* PCI IO space */
+	pci_set_region(hose->regions + 2,
+		       CFG_PCI2_IO_BASE,
+		       CFG_PCI2_IO_PHYS,
+		       CFG_PCI2_IO_SIZE,
+		       PCI_REGION_IO);
+
+	/* System memory space */
+	pci_set_region(hose->regions + 3,
+		       CONFIG_PCI_SYS_MEM_BUS,
+		       CONFIG_PCI_SYS_MEM_PHYS,
+		       gd->ram_size,
+		       PCI_REGION_MEM | PCI_REGION_MEMORY);
+
+	hose->region_count = 4;
+
+	pci_setup_indirect(hose,
+			   (CFG_IMMRBAR+0x8380),
+			   (CFG_IMMRBAR+0x8384));
+
+	pci_register_hose(hose);
+
+	/*
+	 * Write to Command register
+	 */
+	reg16 = 0xff;
+	dev = PCI_BDF(hose->first_busno, 0, 0);
+	pci_hose_read_config_word (hose, dev, PCI_COMMAND, &reg16);
+	reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
+	pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16);
+
+	/*
+	 * Clear non-reserved bits in status register.
+	 */
+	pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);
+	pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
+	pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
+
+	/*
+	 * Hose scan.
+	 */
+	hose->last_busno = pci_hose_scan(hose);
+#endif
+
+}
+#endif /* CONFIG_PCI */
diff --git a/board/mpc8349emds/Makefile b/board/mpc8349emds/Makefile
new file mode 100644
index 0000000..38bbb67
--- /dev/null
+++ b/board/mpc8349emds/Makefile
@@ -0,0 +1,46 @@
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= $(BOARD).o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
diff --git a/board/mpc8349emds/config.mk b/board/mpc8349emds/config.mk
new file mode 100644
index 0000000..edf64d1
--- /dev/null
+++ b/board/mpc8349emds/config.mk
@@ -0,0 +1,28 @@
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# MPC8349EMDS
+#
+
+TEXT_BASE  =   0xFE000000
diff --git a/board/mpc8349emds/mpc8349emds.c b/board/mpc8349emds/mpc8349emds.c
new file mode 100644
index 0000000..73a33f6
--- /dev/null
+++ b/board/mpc8349emds/mpc8349emds.c
@@ -0,0 +1,602 @@
+/*
+ * (C) Copyright 2006
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <ioports.h>
+#include <mpc83xx.h>
+#include <asm/mpc8349_pci.h>
+#include <i2c.h>
+#include <spd.h>
+#include <miiphy.h>
+#include <command.h>
+#if defined(CONFIG_PCI)
+#include <pci.h>
+#endif
+#if defined(CONFIG_SPD_EEPROM)
+#include <spd_sdram.h>
+#endif
+int fixed_sdram(void);
+void sdram_init(void);
+
+#if defined(CONFIG_DDR_ECC) && defined(CONFIG_MPC83XX)
+void ddr_enable_ecc(unsigned int dram_size);
+#endif
+
+int board_early_init_f (void)
+{
+	volatile u8* bcsr = (volatile u8*)CFG_BCSR;
+
+	/* Enable flash write */
+	bcsr[1] &= ~0x01;
+
+	return 0;
+}
+
+#define ns2clk(ns) (ns / (1000000000 / CONFIG_8349_CLKIN) + 1)
+
+long int initdram (int board_type)
+{
+	volatile immap_t *im = (immap_t *)CFG_IMMRBAR;
+	u32 msize = 0;
+
+	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
+		return -1;
+
+	puts("Initializing\n");
+
+	/* DDR SDRAM - Main SODIMM */
+	im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR;
+#if defined(CONFIG_SPD_EEPROM)
+	msize = spd_sdram();
+#else
+	msize = fixed_sdram();
+#endif
+	/*
+	 * Initialize SDRAM if it is on local bus.
+	 */
+	sdram_init();
+
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+	/*
+	 * Initialize and enable DDR ECC.
+	 */
+	ddr_enable_ecc(msize * 1024 * 1024);
+#endif
+	puts("   DDR RAM: ");
+	/* return total bus SDRAM size(bytes)  -- DDR */
+	return (msize * 1024 * 1024);
+}
+
+#if !defined(CONFIG_SPD_EEPROM)
+/*************************************************************************
+ *  fixed sdram init -- doesn't use serial presence detect.
+ ************************************************************************/
+int fixed_sdram(void)
+{
+	volatile immap_t *im = (immap_t *)CFG_IMMRBAR;
+	u32 msize = 0;
+	u32 ddr_size;
+	u32 ddr_size_log2;
+
+	msize = CFG_DDR_SIZE;
+	for (ddr_size = msize << 20, ddr_size_log2 = 0;
+	     (ddr_size > 1);
+	     ddr_size = ddr_size>>1, ddr_size_log2++) {
+		if (ddr_size & 1) {
+			return -1;
+		}
+	}
+	im->sysconf.ddrlaw[0].bar = ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff);
+	im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
+
+#if (CFG_DDR_SIZE != 256)
+#warning Currenly any ddr size other than 256 is not supported
+#endif
+	im->ddr.csbnds[2].csbnds = 0x0000000f;
+	im->ddr.cs_config[2] = CFG_DDR_CONFIG;
+
+	/* currently we use only one CS, so disable the other banks */ 
+	im->ddr.cs_config[0] = 0;
+	im->ddr.cs_config[1] = 0;
+	im->ddr.cs_config[3] = 0;
+
+	im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1;
+	im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2;
+	
+	im->ddr.sdram_cfg =
+		SDRAM_CFG_SREN
+#if defined(CONFIG_DDR_2T_TIMING)
+		| SDRAM_CFG_2T_EN
+#endif
+		| 2 << SDRAM_CFG_SDRAM_TYPE_SHIFT;
+#if defined (CONFIG_DDR_32BIT)
+	/* for 32-bit mode burst length is 8 */
+	im->ddr.sdram_cfg |= (SDRAM_CFG_32_BE | SDRAM_CFG_8_BE);
+#endif
+	im->ddr.sdram_mode = CFG_DDR_MODE;
+
+	im->ddr.sdram_interval = CFG_DDR_INTERVAL; 
+	udelay(200);
+
+	/* enable DDR controller */
+	im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
+	return msize;
+}
+#endif/*!CFG_SPD_EEPROM*/
+
+
+int checkboard (void)
+{
+	puts("Board: Freescale MPC8349EMDS\n");
+	return 0;
+}
+
+#if defined(CONFIG_PCI)
+/*
+ * Initialize PCI Devices, report devices found
+ */
+#ifndef CONFIG_PCI_PNP
+static struct pci_config_table pci_mpc8349emds_config_table[] = {
+	{PCI_ANY_ID,PCI_ANY_ID,PCI_ANY_ID,PCI_ANY_ID,
+	pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
+				    PCI_ENET0_MEMADDR,
+				    PCI_COMMON_MEMORY | PCI_COMMAND_MASTER
+	} },
+	{}
+}
+#endif
+
+volatile static struct pci_controller hose[] = {
+	{
+#ifndef CONFIG_PCI_PNP
+	config_table:pci_mpc8349emds_config_table,
+#endif
+	},
+	{
+#ifndef CONFIG_PCI_PNP
+	config_table:pci_mpc8349emds_config_table,
+#endif
+	}
+};
+#endif /* CONFIG_PCI */
+
+void pci_init_board(void)
+{
+#ifdef CONFIG_PCI
+	extern void pci_mpc83xx_init(volatile struct pci_controller *hose);
+
+	pci_mpc83xx_init(hose);
+#endif /* CONFIG_PCI */
+}
+
+/*
+ * if MPC8349EMDS is soldered with SDRAM
+ */
+#if defined(CFG_BR2_PRELIM)  \
+	&& defined(CFG_OR2_PRELIM) \
+	&& defined(CFG_LBLAWBAR2_PRELIM) \
+	&& defined(CFG_LBLAWAR2_PRELIM)
+/*
+ * Initialize SDRAM memory on the Local Bus.
+ */
+
+void sdram_init(void)
+{
+	volatile immap_t *immap = (immap_t *)CFG_IMMRBAR;
+	volatile lbus8349_t *lbc= &immap->lbus;
+	uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
+
+	puts("\n   SDRAM on Local Bus: ");
+	print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
+
+	/*
+	 * Setup SDRAM Base and Option Registers, already done in cpu_init.c
+	 */
+
+	/* setup mtrpt, lsrt and lbcr for LB bus */
+	lbc->lbcr = CFG_LBC_LBCR;
+	lbc->mrtpr = CFG_LBC_MRTPR;
+	lbc->lsrt = CFG_LBC_LSRT;
+	asm("sync");
+
+	/*
+	 * Configure the SDRAM controller Machine Mode Register.
+	 */
+	lbc->lsdmr = CFG_LBC_LSDMR_5; /* 0x40636733; normal operation */
+
+	lbc->lsdmr = CFG_LBC_LSDMR_1; /* 0x68636733; precharge all the banks */
+	asm("sync");
+	*sdram_addr = 0xff;
+	udelay(100);
+
+	lbc->lsdmr = CFG_LBC_LSDMR_2; /* 0x48636733; auto refresh */
+	asm("sync");
+	/*1 times*/
+	*sdram_addr = 0xff;
+	udelay(100);
+	/*2 times*/
+	*sdram_addr = 0xff;
+	udelay(100);
+	/*3 times*/
+	*sdram_addr = 0xff;
+	udelay(100);
+	/*4 times*/
+	*sdram_addr = 0xff;
+	udelay(100);
+	/*5 times*/
+	*sdram_addr = 0xff;
+	udelay(100);
+	/*6 times*/
+	*sdram_addr = 0xff;
+	udelay(100);
+	/*7 times*/
+	*sdram_addr = 0xff;
+	udelay(100);
+	/*8 times*/
+	*sdram_addr = 0xff;
+	udelay(100);
+
+	/* 0x58636733; mode register write operation */
+	lbc->lsdmr = CFG_LBC_LSDMR_4;
+	asm("sync");
+	*sdram_addr = 0xff;
+	udelay(100);
+
+	lbc->lsdmr = CFG_LBC_LSDMR_5; /* 0x40636733; normal operation */
+	asm("sync");
+	*sdram_addr = 0xff;
+	udelay(100);
+}
+#else
+void sdram_init(void)
+{
+	put("SDRAM on Local Bus is NOT available!\n");
+}
+#endif
+
+#if defined(CONFIG_DDR_ECC) && defined(CONFIG_DDR_ECC_CMD)
+/*
+ * ECC user commands
+ */
+void ecc_print_status(void)
+{
+	volatile immap_t *immap = (immap_t *)CFG_IMMRBAR;
+	volatile ddr8349_t *ddr = &immap->ddr;
+
+	printf("\nECC mode: %s\n\n", (ddr->sdram_cfg & SDRAM_CFG_ECC_EN) ? "ON" : "OFF");
+
+	/* Interrupts */
+	printf("Memory Error Interrupt Enable:\n");
+	printf("  Multiple-Bit Error Interrupt Enable: %d\n",
+			(ddr->err_int_en & ECC_ERR_INT_EN_MBEE) ? 1 : 0);
+	printf("  Single-Bit Error Interrupt Enable: %d\n",
+			(ddr->err_int_en & ECC_ERR_INT_EN_SBEE) ? 1 : 0);
+	printf("  Memory Select Error Interrupt Enable: %d\n\n",
+			(ddr->err_int_en & ECC_ERR_INT_EN_MSEE) ? 1 : 0);
+
+	/* Error disable */
+	printf("Memory Error Disable:\n");
+	printf("  Multiple-Bit Error Disable: %d\n",
+			(ddr->err_disable & ECC_ERROR_DISABLE_MBED) ? 1 : 0);
+	printf("  Sinle-Bit Error Disable: %d\n",
+			(ddr->err_disable & ECC_ERROR_DISABLE_SBED) ? 1 : 0);
+	printf("  Memory Select Error Disable: %d\n\n",
+			(ddr->err_disable & ECC_ERROR_DISABLE_MSED) ? 1 : 0);
+
+	/* Error injection */
+	printf("Memory Data Path Error Injection Mask High/Low: %08lx %08lx\n",
+			ddr->data_err_inject_hi, ddr->data_err_inject_lo);
+
+	printf("Memory Data Path Error Injection Mask ECC:\n");
+	printf("  ECC Mirror Byte: %d\n",
+			(ddr->ecc_err_inject & ECC_ERR_INJECT_EMB) ? 1 : 0);
+	printf("  ECC Injection Enable: %d\n",
+			(ddr->ecc_err_inject & ECC_ERR_INJECT_EIEN) ? 1 : 0);
+	printf("  ECC Error Injection Mask: 0x%02x\n\n",
+			ddr->ecc_err_inject & ECC_ERR_INJECT_EEIM);
+
+	/* SBE counter/threshold */
+	printf("Memory Single-Bit Error Management (0..255):\n");
+	printf("  Single-Bit Error Threshold: %d\n",
+			(ddr->err_sbe & ECC_ERROR_MAN_SBET) >> ECC_ERROR_MAN_SBET_SHIFT);
+	printf("  Single-Bit Error Counter: %d\n\n",
+			(ddr->err_sbe & ECC_ERROR_MAN_SBEC) >> ECC_ERROR_MAN_SBEC_SHIFT);
+
+	/* Error detect */
+	printf("Memory Error Detect:\n");
+	printf("  Multiple Memory Errors: %d\n",
+			(ddr->err_detect & ECC_ERROR_DETECT_MME) ? 1 : 0);
+	printf("  Multiple-Bit Error: %d\n",
+			(ddr->err_detect & ECC_ERROR_DETECT_MBE) ? 1 : 0);
+	printf("  Single-Bit Error: %d\n",
+			(ddr->err_detect & ECC_ERROR_DETECT_SBE) ? 1 : 0);
+	printf("  Memory Select Error: %d\n\n",
+			(ddr->err_detect & ECC_ERROR_DETECT_MSE) ? 1 : 0);
+
+	/* Capture data */
+	printf("Memory Error Address Capture: 0x%08lx\n", ddr->capture_address);
+	printf("Memory Data Path Read Capture High/Low: %08lx %08lx\n",
+			ddr->capture_data_hi, ddr->capture_data_lo);
+	printf("Memory Data Path Read Capture ECC: 0x%02x\n\n",
+		ddr->capture_ecc & CAPTURE_ECC_ECE);
+
+	printf("Memory Error Attributes Capture:\n");
+	printf("  Data Beat Number: %d\n",
+			(ddr->capture_attributes & ECC_CAPT_ATTR_BNUM) >> ECC_CAPT_ATTR_BNUM_SHIFT);
+	printf("  Transaction Size: %d\n",
+			(ddr->capture_attributes & ECC_CAPT_ATTR_TSIZ) >> ECC_CAPT_ATTR_TSIZ_SHIFT);
+	printf("  Transaction Source: %d\n",
+			(ddr->capture_attributes & ECC_CAPT_ATTR_TSRC) >> ECC_CAPT_ATTR_TSRC_SHIFT);
+	printf("  Transaction Type: %d\n",
+			(ddr->capture_attributes & ECC_CAPT_ATTR_TTYP) >> ECC_CAPT_ATTR_TTYP_SHIFT);
+	printf("  Error Information Valid: %d\n\n",
+			ddr->capture_attributes & ECC_CAPT_ATTR_VLD);
+}
+
+int do_ecc ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	volatile immap_t *immap = (immap_t *)CFG_IMMRBAR;
+	volatile ddr8349_t *ddr = &immap->ddr;
+	volatile u32 val;
+	u64 *addr, count, val64;
+	register u64 *i;
+	
+	if (argc > 4) {
+		printf ("Usage:\n%s\n", cmdtp->usage);
+		return 1;
+	}
+	
+	if (argc == 2) {
+		if (strcmp(argv[1], "status") == 0) {
+			ecc_print_status();
+			return 0;
+		} else if (strcmp(argv[1], "captureclear") == 0) {
+			ddr->capture_address = 0;
+			ddr->capture_data_hi = 0;
+			ddr->capture_data_lo = 0;
+			ddr->capture_ecc = 0;
+			ddr->capture_attributes = 0;
+			return 0;
+		}
+	} 
+	
+	if (argc == 3) {
+		if (strcmp(argv[1], "sbecnt") == 0) {
+			val = simple_strtoul(argv[2], NULL, 10);
+			if (val > 255) {
+				printf("Incorrect Counter value, should be 0..255\n");
+				return 1;
+			}
+
+			val = (val << ECC_ERROR_MAN_SBEC_SHIFT);
+			val |= (ddr->err_sbe & ECC_ERROR_MAN_SBET);
+
+			ddr->err_sbe = val;
+			return 0;
+		} else if (strcmp(argv[1], "sbethr") == 0) {
+			val = simple_strtoul(argv[2], NULL, 10);
+			if (val > 255) {
+				printf("Incorrect Counter value, should be 0..255\n");
+				return 1;
+			}
+
+			val = (val << ECC_ERROR_MAN_SBET_SHIFT);
+			val |= (ddr->err_sbe & ECC_ERROR_MAN_SBEC);
+
+			ddr->err_sbe = val;
+			return 0;
+		} else if (strcmp(argv[1], "errdisable") == 0) {
+			val = ddr->err_disable;
+
+			if (strcmp(argv[2], "+sbe") == 0) {
+				val |= ECC_ERROR_DISABLE_SBED;
+			} else if (strcmp(argv[2], "+mbe") == 0) {
+				val |= ECC_ERROR_DISABLE_MBED;
+			} else if (strcmp(argv[2], "+mse") == 0) {
+				val |= ECC_ERROR_DISABLE_MSED;
+			} else if (strcmp(argv[2], "+all") == 0) {
+				val |= (ECC_ERROR_DISABLE_SBED | 
+					ECC_ERROR_DISABLE_MBED | 
+					ECC_ERROR_DISABLE_MSED);
+			} else if (strcmp(argv[2], "-sbe") == 0) {
+				val &= ~ECC_ERROR_DISABLE_SBED;
+			} else if (strcmp(argv[2], "-mbe") == 0) {
+				val &= ~ECC_ERROR_DISABLE_MBED;
+			} else if (strcmp(argv[2], "-mse") == 0) {
+				val &= ~ECC_ERROR_DISABLE_MSED;
+			} else if (strcmp(argv[2], "-all") == 0) {
+				val &= ~(ECC_ERROR_DISABLE_SBED | 
+					ECC_ERROR_DISABLE_MBED | 
+					ECC_ERROR_DISABLE_MSED);
+			} else {
+				printf("Incorrect err_disable field\n");
+				return 1;
+			}
+
+			ddr->err_disable = val;
+			__asm__ __volatile__ ("sync");
+			__asm__ __volatile__ ("isync");
+			return 0;
+		} else if (strcmp(argv[1], "errdetectclr") == 0) {
+			val = ddr->err_detect;
+
+			if (strcmp(argv[2], "mme") == 0) {
+				val |= ECC_ERROR_DETECT_MME;
+			} else if (strcmp(argv[2], "sbe") == 0) {
+				val |= ECC_ERROR_DETECT_SBE;
+			} else if (strcmp(argv[2], "mbe") == 0) {
+				val |= ECC_ERROR_DETECT_MBE;
+			} else if (strcmp(argv[2], "mse") == 0) {
+				val |= ECC_ERROR_DETECT_MSE;
+			} else if (strcmp(argv[2], "all") == 0) {
+				val |= (ECC_ERROR_DETECT_MME |
+					ECC_ERROR_DETECT_MBE |
+					ECC_ERROR_DETECT_SBE |
+					ECC_ERROR_DETECT_MSE);
+			} else {
+				printf("Incorrect err_detect field\n");
+				return 1;
+			}
+
+			ddr->err_detect = val;
+			return 0;
+		} else if (strcmp(argv[1], "injectdatahi") == 0) {
+			val = simple_strtoul(argv[2], NULL, 16);
+
+			ddr->data_err_inject_hi = val;
+			return 0;
+		} else if (strcmp(argv[1], "injectdatalo") == 0) {
+			val = simple_strtoul(argv[2], NULL, 16);
+
+			ddr->data_err_inject_lo = val;
+			return 0;
+		} else if (strcmp(argv[1], "injectecc") == 0) {
+			val = simple_strtoul(argv[2], NULL, 16);
+			if (val > 0xff) {
+				printf("Incorrect ECC inject mask, should be 0x00..0xff\n");
+				return 1;
+			}
+			val |= (ddr->ecc_err_inject & ~ECC_ERR_INJECT_EEIM);
+
+			ddr->ecc_err_inject = val;
+			return 0;
+		} else if (strcmp(argv[1], "inject") == 0) {
+			val = ddr->ecc_err_inject;
+
+			if (strcmp(argv[2], "en") == 0)
+				val |= ECC_ERR_INJECT_EIEN;
+			else if (strcmp(argv[2], "dis") == 0)
+				val &= ~ECC_ERR_INJECT_EIEN;
+			else
+				printf("Incorrect command\n");
+
+			ddr->ecc_err_inject = val;
+			__asm__ __volatile__ ("sync");
+			__asm__ __volatile__ ("isync");
+			return 0;
+		} else if (strcmp(argv[1], "mirror") == 0) {
+			val = ddr->ecc_err_inject;
+
+			if (strcmp(argv[2], "en") == 0)
+				val |= ECC_ERR_INJECT_EMB;
+			else if (strcmp(argv[2], "dis") == 0)
+				val &= ~ECC_ERR_INJECT_EMB;
+			else
+				printf("Incorrect command\n");
+
+			ddr->ecc_err_inject = val;
+			return 0;
+		}
+	}
+
+	if (argc == 4) {
+		if (strcmp(argv[1], "test") == 0) {
+			addr = (u64 *)simple_strtoul(argv[2], NULL, 16);
+			count = simple_strtoul(argv[3], NULL, 16);
+
+			if ((u32)addr % 8) {
+				printf("Address not alligned on double word boundary\n");
+				return 1;
+			}
+
+			disable_interrupts();
+			icache_disable();
+
+			for (i = addr; i < addr + count; i++) {
+				/* enable injects */
+				ddr->ecc_err_inject |= ECC_ERR_INJECT_EIEN;
+				__asm__ __volatile__ ("sync");
+				__asm__ __volatile__ ("isync");
+
+				/* write memory location injecting errors */
+				*i = 0x1122334455667788ULL;
+				__asm__ __volatile__ ("sync");
+
+				/* disable injects */
+				ddr->ecc_err_inject &= ~ECC_ERR_INJECT_EIEN;
+				__asm__ __volatile__ ("sync");
+				__asm__ __volatile__ ("isync");
+
+				/* read data, this generates ECC error */
+				val64 = *i;
+				__asm__ __volatile__ ("sync");
+
+				/* disable errors for ECC */
+				ddr->err_disable |= ~ECC_ERROR_ENABLE;
+				__asm__ __volatile__ ("sync");
+				__asm__ __volatile__ ("isync");
+
+				/* re-initialize memory, write the location again
+				 * NOT injecting errors this time */
+				*i = 0xcafecafecafecafeULL;
+				__asm__ __volatile__ ("sync");
+
+				/* enable errors for ECC */
+				ddr->err_disable &= ECC_ERROR_ENABLE;
+				__asm__ __volatile__ ("sync");
+				__asm__ __volatile__ ("isync");
+			}
+
+			icache_enable();
+			enable_interrupts();
+
+			return 0;
+		}
+	}
+
+	printf ("Usage:\n%s\n", cmdtp->usage);
+	return 1;
+}
+
+U_BOOT_CMD(
+	ecc,     4,     0,      do_ecc,
+	"ecc     - support for DDR ECC features\n",
+	"status              - print out status info\n"
+	"ecc captureclear        - clear capture regs data\n"
+	"ecc sbecnt <val>        - set Single-Bit Error counter\n"
+	"ecc sbethr <val>        - set Single-Bit Threshold\n"
+	"ecc errdisable <flag>   - clear/set disable Memory Error Disable, flag:\n"
+	"  [-|+]sbe - Single-Bit Error\n"
+	"  [-|+]mbe - Multiple-Bit Error\n"
+	"  [-|+]mse - Memory Select Error\n"
+	"  [-|+]all - all errors\n"
+	"ecc errdetectclr <flag> - clear Memory Error Detect, flag:\n"
+	"  mme - Multiple Memory Errors\n"
+	"  sbe - Single-Bit Error\n"
+	"  mbe - Multiple-Bit Error\n"
+	"  mse - Memory Select Error\n"
+	"  all - all errors\n"
+	"ecc injectdatahi <hi>  - set Memory Data Path Error Injection Mask High\n"
+	"ecc injectdatalo <lo>  - set Memory Data Path Error Injection Mask Low\n"
+	"ecc injectecc <ecc>    - set ECC Error Injection Mask\n"
+	"ecc inject <en|dis>    - enable/disable error injection\n"
+	"ecc mirror <en|dis>    - enable/disable mirror byte\n"
+	"ecc test <addr> <cnt>  - test mem region:\n"
+	"  - enables injects\n"
+	"  - writes pattern injecting errors\n"
+	"  - disables injects\n"
+	"  - reads pattern back, generates error\n"
+	"  - re-inits memory"
+);
+#endif /* if defined(CONFIG_DDR_ECC) && defined(CONFIG_DDR_ECC_CMD) */
diff --git a/board/mpc8349emds/u-boot.lds b/board/mpc8349emds/u-boot.lds
new file mode 100644
index 0000000..937c87a
--- /dev/null
+++ b/board/mpc8349emds/u-boot.lds
@@ -0,0 +1,123 @@
+/*
+ * (C) Copyright 2006
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/mpc83xx/start.o	(.text)
+    *(.text)
+    *(.fixup)
+    *(.got1)
+    . = ALIGN(16);
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
+ENTRY(_start)
diff --git a/board/netstar/Makefile b/board/netstar/Makefile
index 8ef2189..3a20501 100644
--- a/board/netstar/Makefile
+++ b/board/netstar/Makefile
@@ -80,6 +80,6 @@ distclean:	clean
 .depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
 		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
 
--include .depend
+sinclude .depend
 
 #########################################################################
diff --git a/board/netstar/crcek b/board/netstar/crcek
deleted file mode 100755
index 9593f89..0000000
--- a/board/netstar/crcek
+++ /dev/null
diff --git a/board/netstar/eeprom b/board/netstar/eeprom
deleted file mode 100755
index c30c98b..0000000
--- a/board/netstar/eeprom
+++ /dev/null
diff --git a/board/netstar/flash.c b/board/netstar/flash.c
index f555c0c..692c416 100644
--- a/board/netstar/flash.c
+++ b/board/netstar/flash.c
@@ -230,7 +230,7 @@ out:
  * Copy memory to flash
  */
 
-volatile static int write_hword(flash_info_t *info, ulong dest, ushort data)
+static int write_hword(flash_info_t *info, ulong dest, ushort data)
 {
 	vu_short *addr = (vu_short *) dest;
 	ushort result;
diff --git a/board/netstar/nand.c b/board/netstar/nand.c
index e5b7f33..f470c1a 100644
--- a/board/netstar/nand.c
+++ b/board/netstar/nand.c
@@ -48,10 +48,12 @@ static void netstar_nand_hwcontrol(struct mtd_info *mtd, int cmd)
 /*
  *	chip R/B detection
  */
+/***
 static int netstar_nand_ready(struct mtd_info *mtd)
 {
 	return (*(volatile ushort *)GPIO_DATA_INPUT_REG) & 0x02;
 }
+***/
 
 void board_nand_init(struct nand_chip *nand)
 {
diff --git a/board/shannon/flash.c b/board/shannon/flash.c
index 13c01d8..475b76b 100644
--- a/board/shannon/flash.c
+++ b/board/shannon/flash.c
@@ -315,7 +315,7 @@ outahere:
  * Copy memory to flash
  */
 
-volatile static int write_word (flash_info_t *info, ulong dest, ulong data)
+static int write_word (flash_info_t *info, ulong dest, ulong data)
 {
     vu_long *addr = (vu_long *)dest;
     ulong result;
diff --git a/board/smdk2400/flash.c b/board/smdk2400/flash.c
index a108af7..fd9992d 100644
--- a/board/smdk2400/flash.c
+++ b/board/smdk2400/flash.c
@@ -353,8 +353,7 @@ outahere:
  * Copy memory to flash
  */
 
-volatile static int write_word (flash_info_t * info, ulong dest,
-								ulong data)
+static int write_word (flash_info_t * info, ulong dest, ulong data)
 {
 	vu_long *addr = (vu_long *) dest;
 	ulong result;
diff --git a/board/stamp/Makefile b/board/stamp/Makefile
new file mode 100644
index 0000000..ab97e1b
--- /dev/null
+++ b/board/stamp/Makefile
@@ -0,0 +1,68 @@
+#
+# U-boot - Makefile
+#
+# Copyright (c) 2005 blackfin.uclinux.org
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o stamp.o
+SOBJS	=
+
+$(LIB):	.depend $(OBJS)
+	$(AR) crv $@ $(OBJS)
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/stamp/config.mk b/board/stamp/config.mk
new file mode 100644
index 0000000..0d00730
--- /dev/null
+++ b/board/stamp/config.mk
@@ -0,0 +1,25 @@
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+TEXT_BASE = 0x07FC0000
+PLATFORM_CPPFLAGS += -I$(TOPDIR)
diff --git a/board/stamp/stamp.c b/board/stamp/stamp.c
new file mode 100644
index 0000000..3fe0134
--- /dev/null
+++ b/board/stamp/stamp.c
@@ -0,0 +1,275 @@
+/*
+ * U-boot - stamp.c STAMP board specific routines
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/mem_init.h>
+#include "stamp.h"
+
+#define STATUS_LED_OFF 0
+#define STATUS_LED_ON  1
+
+#ifdef CONFIG_SHOW_BOOT_PROGRESS
+# define SHOW_BOOT_PROGRESS(arg)	show_boot_progress(arg)
+#else
+# define SHOW_BOOT_PROGRESS(arg)
+#endif
+
+int checkboard (void)
+{
+	printf ("CPU:   ADSP BF533 Rev.: 0.%d\n", *pCHIPID >> 28);
+	printf ("Board: ADI BF533 Stamp board\n");
+	printf ("       Support: http://blackfin.uclinux.org/\n");
+	printf ("       Richard Klingler <richard@uclinux.net>\n");
+	return 0;
+}
+
+long int initdram (int board_type)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+#ifdef DEBUG
+	printf ("SDRAM attributes:\n");
+	printf ("  tRCD:%d Cycles; tRP:%d Cycles; tRAS:%d Cycles; tWR:%d Cycles; "
+		"CAS Latency:%d cycles\n",
+		(SDRAM_tRCD >> 15),
+		(SDRAM_tRP >> 11),
+		(SDRAM_tRAS >> 6),
+		(SDRAM_tWR >> 19),
+		(SDRAM_CL >> 2));
+	printf ("SDRAM Begin: 0x%x\n", CFG_SDRAM_BASE);
+	printf ("Bank size = %d MB\n", 128);
+#endif
+	gd->bd->bi_memstart = CFG_SDRAM_BASE;
+	gd->bd->bi_memsize = CFG_MAX_RAM_SIZE;
+	return (gd->bd->bi_memsize);
+}
+
+void swap_to (int device_id)
+{
+
+	if (device_id == ETHERNET) {
+		*pFIO_DIR = PF0;
+		asm ("ssync;");
+		*pFIO_FLAG_S = PF0;
+		asm ("ssync;");
+	} else if (device_id == FLASH) {
+		*pFIO_DIR = (PF4 | PF3 | PF2 | PF1 | PF0);
+		*pFIO_FLAG_S = (PF4 | PF3 | PF2);
+		*pFIO_MASKA_D = (PF8 | PF6 | PF5);
+		*pFIO_MASKB_D = (PF7);
+		*pFIO_POLAR = (PF8 | PF6 | PF5);
+		*pFIO_EDGE = (PF8 | PF7 | PF6 | PF5);
+		*pFIO_INEN = (PF8 | PF7 | PF6 | PF5);
+		*pFIO_FLAG_D = (PF4 | PF3 | PF2);
+		asm ("ssync;");
+	} else {
+		printf ("Unknown bank to switch\n");
+	}
+
+	return;
+}
+
+#if defined(CONFIG_MISC_INIT_R)
+/* miscellaneous platform dependent initialisations */
+int misc_init_r (void)
+{
+	int i;
+	int cf_stat = 0;
+
+	/* Check whether CF card is inserted */
+	*pFIO_EDGE = FIO_EDGE_CF_BITS;
+	*pFIO_POLAR = FIO_POLAR_CF_BITS;
+	for (i = 0; i < 0x300; i++)
+		asm ("nop;");
+
+	if ((*pFIO_FLAG_S) & CF_STAT_BITS) {
+		cf_stat = 0;
+	} else {
+		cf_stat = 1;
+	}
+
+	*pFIO_EDGE = FIO_EDGE_BITS;
+	*pFIO_POLAR = FIO_POLAR_BITS;
+
+
+	if (cf_stat) {
+		printf ("Booting from COMPACT flash\n");
+
+		/* Set cycle time for CF */
+		*(volatile unsigned long *) ambctl1 = CF_AMBCTL1VAL;
+
+		for (i = 0; i < 0x1000; i++)
+			asm ("nop;");
+		for (i = 0; i < 0x1000; i++)
+			asm ("nop;");
+		for (i = 0; i < 0x1000; i++)
+			asm ("nop;");
+
+		serial_setbrg ();
+		ide_init ();
+
+		setenv ("bootargs", "");
+		setenv ("bootcmd",
+			"fatload ide 0:1 0x1000000 uImage-stamp;bootm 0x1000000;bootm 0x20100000");
+	} else {
+		printf ("Booting from FLASH\n");
+	}
+
+	return 1;
+}
+#endif
+
+#ifdef CONFIG_STAMP_CF
+
+void cf_outb (unsigned char val, volatile unsigned char *addr)
+{
+	/*
+	 * Set PF1 PF0 respectively to 0 1 to divert address
+	 * to the expansion memory banks
+	 */
+	*pFIO_FLAG_S = CF_PF0;
+	*pFIO_FLAG_C = CF_PF1;
+	asm ("ssync;");
+
+	*(addr) = val;
+	asm ("ssync;");
+
+	/* Setback PF1 PF0 to 0 0 to address external
+	 * memory banks  */
+	*(volatile unsigned short *) pFIO_FLAG_C = CF_PF1_PF0;
+	asm ("ssync;");
+}
+
+unsigned char cf_inb (volatile unsigned char *addr)
+{
+	volatile unsigned char c;
+
+	*pFIO_FLAG_S = CF_PF0;
+	*pFIO_FLAG_C = CF_PF1;
+	asm ("ssync;");
+
+	c = *(addr);
+	asm ("ssync;");
+
+	*pFIO_FLAG_C = CF_PF1_PF0;
+	asm ("ssync;");
+
+	return c;
+}
+
+void cf_insw (unsigned short *sect_buf, unsigned short *addr, int words)
+{
+	int i;
+
+	*pFIO_FLAG_S = CF_PF0;
+	*pFIO_FLAG_C = CF_PF1;
+	asm ("ssync;");
+
+	for (i = 0; i < words; i++) {
+		*(sect_buf + i) = *(addr);
+		asm ("ssync;");
+	}
+
+	*pFIO_FLAG_C = CF_PF1_PF0;
+	asm ("ssync;");
+}
+
+void cf_outsw (unsigned short *addr, unsigned short *sect_buf, int words)
+{
+	int i;
+
+	*pFIO_FLAG_S = CF_PF0;
+	*pFIO_FLAG_C = CF_PF1;
+	asm ("ssync;");
+
+	for (i = 0; i < words; i++) {
+		*(addr) = *(sect_buf + i);
+		asm ("ssync;");
+	}
+
+	*pFIO_FLAG_C = CF_PF1_PF0;
+	asm ("ssync;");
+}
+#endif
+
+void stamp_led_set (int LED1, int LED2, int LED3)
+{
+	*pFIO_INEN &= ~(PF2 | PF3 | PF4);
+	*pFIO_DIR |= (PF2 | PF3 | PF4);
+
+	if (LED1 == STATUS_LED_OFF)
+		*pFIO_FLAG_S = PF2;
+	else
+		*pFIO_FLAG_C = PF2;
+	if (LED2 == STATUS_LED_OFF)
+		*pFIO_FLAG_S = PF3;
+	else
+		*pFIO_FLAG_C = PF3;
+	if (LED3 == STATUS_LED_OFF)
+		*pFIO_FLAG_S = PF4;
+	else
+		*pFIO_FLAG_C = PF4;
+	asm ("ssync;");
+}
+
+void show_boot_progress (int status)
+{
+	switch (status) {
+	case 1:
+		stamp_led_set (STATUS_LED_OFF, STATUS_LED_OFF, STATUS_LED_ON);
+		break;
+	case 2:
+		stamp_led_set (STATUS_LED_OFF, STATUS_LED_ON, STATUS_LED_OFF);
+		break;
+	case 3:
+		stamp_led_set (STATUS_LED_OFF, STATUS_LED_ON, STATUS_LED_ON);
+		break;
+	case 4:
+		stamp_led_set (STATUS_LED_ON, STATUS_LED_OFF, STATUS_LED_OFF);
+		break;
+	case 5:
+	case 6:
+		stamp_led_set (STATUS_LED_ON, STATUS_LED_OFF, STATUS_LED_ON);
+		break;
+	case 7:
+	case 8:
+		stamp_led_set (STATUS_LED_ON, STATUS_LED_ON, STATUS_LED_OFF);
+		break;
+	case 9:
+	case 10:
+	case 11:
+	case 12:
+	case 13:
+	case 14:
+	case 15:
+		stamp_led_set (STATUS_LED_OFF, STATUS_LED_OFF,
+			       STATUS_LED_OFF);
+		break;
+	default:
+		stamp_led_set (STATUS_LED_ON, STATUS_LED_ON, STATUS_LED_ON);
+		break;
+	}
+}
diff --git a/board/stamp/stamp.h b/board/stamp/stamp.h
new file mode 100644
index 0000000..7bc33b4
--- /dev/null
+++ b/board/stamp/stamp.h
@@ -0,0 +1,57 @@
+/*
+ * U-boot - stamp.h
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __STAMP_H__
+#define __STAMP_H__
+
+extern void init_Flags(void);
+
+extern volatile unsigned long *ambctl0;
+extern volatile unsigned long *ambctl1;
+extern volatile unsigned long *amgctl;
+
+extern unsigned long pll_div_fact;
+extern void serial_setbrg(void);
+extern void pll_set(int vco, int crystal_frq, int pll_div);
+
+/* Definitions used in  Compact Flash Boot support */
+#define FIO_EDGE_CF_BITS 	0x0000
+#define FIO_POLAR_CF_BITS 	0x0000
+#define	FIO_EDGE_BITS  		0x1E0
+#define	FIO_POLAR_BITS  	0x160
+
+/* Compact flash status bits in status register */
+#define CF_STAT_BITS 		0x00000060
+
+/* CF Flags used to switch between expansion and external
+ * memory banks
+ */
+#define CF_PF0			0x0001
+#define CF_PF1			0x0002
+#define CF_PF1_PF0		0x0003
+
+#endif
diff --git a/board/stamp/u-boot.lds b/board/stamp/u-boot.lds
new file mode 100644
index 0000000..9a22e50
--- /dev/null
+++ b/board/stamp/u-boot.lds
@@ -0,0 +1,147 @@
+/*
+ * U-boot - u-boot.lds
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(bfin)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)	}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)	}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)	}
+  .rela.got      : { *(.rela.got)	}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)	}
+  .rela.bss      : { *(.rela.bss)	}
+  .rel.plt       : { *(.rel.plt)	}
+  .rela.plt      : { *(.rela.plt)	}
+  .init          : { *(.init)		}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector before the environment sector. If it throws 	*/
+    /* an error during compilation remove an object here to get	*/
+    /* it linked after the configuration sector.		*/
+
+    cpu/bf533/start.o		(.text)
+    cpu/bf533/start1.o		(.text)
+    cpu/bf533/traps.o		(.text)
+    cpu/bf533/interrupt.o	(.text)
+    cpu/bf533/serial.o		(.text)
+    common/dlmalloc.o		(.text)
+    lib_generic/vsprintf.o	(.text)
+    lib_generic/crc32.o		(.text)
+    lib_generic/zlib.o		(.text)
+
+    . = DEFINED(env_offset) ? env_offset : .;
+    common/environment.o	(.text)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/trab/Makefile b/board/trab/Makefile
index ced9bc5..159404b 100644
--- a/board/trab/Makefile
+++ b/board/trab/Makefile
@@ -47,7 +47,7 @@ trab_fkt.srec:	trab_fkt.o rs485.o tsc2000.o $(LIB)
 	$(OBJCOPY) -O srec $(<:.o=) $@
 
 trab_fkt.bin:	trab_fkt.srec
-	$(OBJCOPY) -O binary $< $@ 2>/dev/null
+	$(OBJCOPY) -I srec -O binary $< $@
 
 clean:
 	rm -f $(SOBJS) $(OBJS)
diff --git a/board/trab/flash.c b/board/trab/flash.c
index b4435e3..8cdd824 100644
--- a/board/trab/flash.c
+++ b/board/trab/flash.c
@@ -308,8 +308,7 @@ outahere:
  * Copy memory to flash
  */
 
-volatile static int write_word (flash_info_t * info, ulong dest,
-								ulong data)
+static int write_word (flash_info_t * info, ulong dest, ulong data)
 {
 	vu_long *addr = (vu_long *) dest;
 	ulong result;
diff --git a/board/versatile/split_by_variant.sh b/board/versatile/split_by_variant.sh
index 35c663e..576f238 100755
--- a/board/versatile/split_by_variant.sh
+++ b/board/versatile/split_by_variant.sh
@@ -36,5 +36,5 @@ fi
 # ---------------------------------------------------------
 # Complete the configuration
 # ---------------------------------------------------------
-./mkconfig -a versatile arm arm926ejs versatile
+./mkconfig -a versatile arm arm926ejs versatile NULL versatile
 echo "Variant:: $variant"
diff --git a/board/xilinx/xilinx_enet/emac_adapter.c b/board/xilinx/xilinx_enet/emac_adapter.c
index 5c492eb..b30e897 100644
--- a/board/xilinx/xilinx_enet/emac_adapter.c
+++ b/board/xilinx/xilinx_enet/emac_adapter.c
@@ -39,7 +39,6 @@
 
 #include <common.h>
 #include <net.h>
-#include <configs/ml300.h>
 #include "xparameters.h"
 #include "xemac.h"
 
diff --git a/board/xilinx/xilinx_iic/iic_adapter.c b/board/xilinx/xilinx_iic/iic_adapter.c
index f3ecba7..163fe15 100644
--- a/board/xilinx/xilinx_iic/iic_adapter.c
+++ b/board/xilinx/xilinx_iic/iic_adapter.c
@@ -40,7 +40,6 @@
 #include <common.h>
 #include <environment.h>
 #include <net.h>
-#include <configs/ml300.h>
 #include "xparameters.h"
 
 #ifdef CFG_ENV_IS_IN_EEPROM
diff --git a/board/zpc1900/config.mk b/board/zpc1900/config.mk
index 1072dc7..3e53b2b 100644
--- a/board/zpc1900/config.mk
+++ b/board/zpc1900/config.mk
@@ -27,4 +27,4 @@
 # ZPC.1900 board
 #
 
-TEXT_BASE = 0xFFE00000
+TEXT_BASE = 0xFE000000
diff --git a/board/zpc1900/zpc1900.c b/board/zpc1900/zpc1900.c
index 6d16a0d..7db535e 100644
--- a/board/zpc1900/zpc1900.c
+++ b/board/zpc1900/zpc1900.c
@@ -2,7 +2,7 @@
  * (C) Copyright 2001-2003
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
- * (C) Copyright 2003 Arabella Software Ltd.
+ * (C) Copyright 2003-2005 Arabella Software Ltd.
  * Yuli Barcohen <yuli@arabellasw.com>
  *
  * See file CREDITS for list of people who contributed to this
@@ -27,9 +27,6 @@
 #include <common.h>
 #include <ioports.h>
 #include <mpc8260.h>
-#include <asm/m8260_pci.h>
-#include <i2c.h>
-#include <spd.h>
 #include <miiphy.h>
 
 /*
@@ -167,8 +164,8 @@ const iop_conf_t iop_conf_tab[4][32] = {
 	/* PD18 */ {   0,   0,   0,   0,   0,   0   }, /* PD18 */
 	/* PD17 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXPRTY */
 	/* PD16 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXPRTY */
-	/* PD15 */ {   1,   1,   1,   0,   1,   0   }, /* I2C SDA */
-	/* PD14 */ {   1,   1,   1,   0,   1,   0   }, /* I2C SCL */
+	/* PD15 */ {   0,   1,   1,   0,   1,   0   }, /* I2C SDA */
+	/* PD14 */ {   0,   1,   1,   0,   1,   0   }, /* I2C SCL */
 	/* PD13 */ {   0,   0,   0,   0,   0,   0   }, /* PD13 */
 	/* PD12 */ {   0,   0,   0,   0,   0,   0   }, /* PD12 */
 	/* PD11 */ {   0,   0,   0,   0,   0,   0   }, /* PD11 */
@@ -231,11 +228,10 @@ long int initdram(int board_type)
 	vu_char *ramaddr;
 	uchar c = 0xFF;
 	long int msize = CFG_SDRAM_SIZE;
-	uint psdmr = CFG_PSDMR;
 	int i;
 
 	if (bcsr[4] & BCSR_PCI_MODE) { /* PCI mode selected by JP9 */
-		immap->im_clkrst.car_sccr |= M826X_SCCR_PCI_MODE_EN;
+		immap->im_clkrst.car_sccr |= SCCR_PCI_MODE;
 		immap->im_siu_conf.sc_siumcr =
 			(immap->im_siu_conf.sc_siumcr & ~SIUMCR_LBPC11)
 			| SIUMCR_LBPC01;
@@ -255,10 +251,10 @@ long int initdram(int board_type)
 	*/
 	if ((immap->im_siu_conf.sc_siumcr & SIUMCR_LBPC11) == SIUMCR_LBPC00) {
 		memctl->memc_lsrt  = CFG_LSRT;
-		memctl->memc_or4   = 0xFFC01480;
-		memctl->memc_br4   = CFG_LSDRAM_BASE | 0x00001861;
-		memctl->memc_lsdmr = CFG_LSDMR | PSDMR_OP_PREA;
+		memctl->memc_or4   = CFG_LSDRAM_OR;
+		memctl->memc_br4   = CFG_LSDRAM_BR;
 		ramaddr = (vu_char *)CFG_LSDRAM_BASE;
+		memctl->memc_lsdmr = CFG_LSDMR | PSDMR_OP_PREA;
 		*ramaddr = c;
 		memctl->memc_lsdmr = CFG_LSDMR | PSDMR_OP_CBRR;
 		for (i = 0; i < 8; i++)
@@ -271,8 +267,8 @@ long int initdram(int board_type)
 
 	/* Initialise 60x bus SDRAM */
 	memctl->memc_psrt = CFG_PSRT;
-	memctl->memc_or2  = 0xFC0028C0;
-	memctl->memc_br2  = CFG_SDRAM_BASE | 0x00000041;
+	memctl->memc_or2  = CFG_PSDRAM_OR;
+	memctl->memc_br2  = CFG_PSDRAM_BR;
 	/*
 	 * The mode data for Mode Register Write command must appear on
 	 * the address lines during a mode-set cycle. It is driven by
@@ -283,15 +279,15 @@ long int initdram(int board_type)
 	 * length must be 4.
 	 */
 	ramaddr = (vu_char *)(CFG_SDRAM_BASE |
-			      ((psdmr & PSDMR_CL_MSK) << 7) | 0x10);
-	memctl->memc_psdmr = psdmr | PSDMR_OP_PREA; /* Precharge all banks */
+			      ((CFG_PSDMR & PSDMR_CL_MSK) << 7) | 0x10);
+	memctl->memc_psdmr = CFG_PSDMR | PSDMR_OP_PREA; /* Precharge all banks */
 	*ramaddr = c;
-	memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR; /* CBR refresh */
+	memctl->memc_psdmr = CFG_PSDMR | PSDMR_OP_CBRR; /* CBR refresh */
 	for (i = 0; i < 8; i++)
 		*ramaddr = c;
-	memctl->memc_psdmr = psdmr | PSDMR_OP_MRW;  /* Mode Register write */
+	memctl->memc_psdmr = CFG_PSDMR | PSDMR_OP_MRW;  /* Mode Register write */
 	*ramaddr = c;
-	memctl->memc_psdmr = psdmr | PSDMR_RFEN;    /* Refresh enable */
+	memctl->memc_psdmr = CFG_PSDMR | PSDMR_RFEN;    /* Refresh enable */
 	*ramaddr = c;
 #endif /* CFG_RAMBOOT */