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| author | Jason Jin <Jason.Jin@freescale.com> | 2008-10-31 05:07:04 -0500 |
|---|---|---|
| committer | Scott Wood <scottwood@freescale.com> | 2008-10-31 13:14:31 -0500 |
| commit | c57fc28947e248fb03c49a28b467686299895055 (patch) | |
| tree | 49ae1e8c6cf330dfc82849c066ee17ef658aa121 /board | |
| parent | 6fc110bd8a8d642b8f7b0653bd9a08a0b7c3d50b (diff) | |
| download | bootable_bootloader_goldelico_gta04-c57fc28947e248fb03c49a28b467686299895055.zip bootable_bootloader_goldelico_gta04-c57fc28947e248fb03c49a28b467686299895055.tar.gz bootable_bootloader_goldelico_gta04-c57fc28947e248fb03c49a28b467686299895055.tar.bz2 | |
NAND: Add NAND support for MPC8536DS board
This patch defines 1M TLB&LAW size for NAND on MPC8536DS, assigns 0xffa00000
for CONFIG_SYS_NAND_BASE and adds other NAND supports in config file.
It also moves environment(CONFIG_ENV_ADDR) outside of u-boot image.
Singed-off-by: Jason Jin <Jason.Jin@freescale.com>
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'board')
| -rw-r--r-- | board/freescale/mpc8536ds/law.c | 1 | ||||
| -rw-r--r-- | board/freescale/mpc8536ds/tlb.c | 5 |
2 files changed, 6 insertions, 0 deletions
diff --git a/board/freescale/mpc8536ds/law.c b/board/freescale/mpc8536ds/law.c index 8013d41..0861fa7 100644 --- a/board/freescale/mpc8536ds/law.c +++ b/board/freescale/mpc8536ds/law.c @@ -38,6 +38,7 @@ struct law_entry law_table[] = { SET_LAW(CONFIG_SYS_PCIE3_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_PCIE_3), SET_LAW(CONFIG_SYS_PCIE3_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_3), SET_LAW(PIXIS_BASE, LAW_SIZE_4K, LAW_TRGT_IF_LBC), + SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC), }; int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/mpc8536ds/tlb.c b/board/freescale/mpc8536ds/tlb.c index ebf41ce..c81a959 100644 --- a/board/freescale/mpc8536ds/tlb.c +++ b/board/freescale/mpc8536ds/tlb.c @@ -66,6 +66,11 @@ struct fsl_e_tlb_entry tlb_table[] = { SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_IO_PHYS, CONFIG_SYS_PCI1_IO_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 3, BOOKE_PAGESZ_256K, 1), + + /* *I*G - NAND */ + SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 4, BOOKE_PAGESZ_1M, 1), }; int num_tlb_entries = ARRAY_SIZE(tlb_table); |