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| author | Shinya Kuribayashi <skuribay@ruby.dti.ne.jp> | 2008-06-05 22:29:00 +0900 |
|---|---|---|
| committer | Shinya Kuribayashi <shinya.kuribayashi@necel.com> | 2008-06-05 22:29:00 +0900 |
| commit | 7daf2ebe9196dd67131a06d85049c3a8a08ca413 (patch) | |
| tree | 971e897a7f47762e1d4029780ebd059330d94fc2 /cpu/mips | |
| parent | f0d5a6f060d00358b85c62a921a423ea8df71184 (diff) | |
| download | bootable_bootloader_goldelico_gta04-7daf2ebe9196dd67131a06d85049c3a8a08ca413.zip bootable_bootloader_goldelico_gta04-7daf2ebe9196dd67131a06d85049c3a8a08ca413.tar.gz bootable_bootloader_goldelico_gta04-7daf2ebe9196dd67131a06d85049c3a8a08ca413.tar.bz2 | |
[MIPS] Update <asm/addrspace.h> header
- Fix traditional KSEG names
- Replace PHYSADDR with CPHYSADDR
Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
Diffstat (limited to 'cpu/mips')
| -rw-r--r-- | cpu/mips/cache.S | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/cpu/mips/cache.S b/cpu/mips/cache.S index 7966079..ee5d411 100644 --- a/cpu/mips/cache.S +++ b/cpu/mips/cache.S @@ -40,7 +40,7 @@ */ #define MIPS_MAX_CACHE_SIZE 0x10000 -#define INDEX_BASE KSEG0 +#define INDEX_BASE CKSEG0 .macro cache_op op addr .set push @@ -218,7 +218,7 @@ NESTED(mips_cache_reset, 0, ra) /* * Now clear that much memory starting from zero. */ - PTR_LI a0, KSEG1 + PTR_LI a0, CKSEG1 PTR_ADDU a1, a0, v0 2: PTR_ADDIU a0, 64 f_fill64 a0, -64, zero @@ -318,7 +318,7 @@ LEAF(dcache_enable) .globl mips_cache_lock .ent mips_cache_lock mips_cache_lock: - li a1, K0BASE - CACHE_LOCK_SIZE + li a1, CKSEG0 - CACHE_LOCK_SIZE addu a0, a1 li a2, CACHE_LOCK_SIZE li a3, CFG_CACHELINE_SIZE |