diff options
author | Wolfgang Denk <wd@denx.de> | 2008-05-20 16:00:29 +0200 |
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committer | Wolfgang Denk <wd@denx.de> | 2008-05-21 00:14:08 +0200 |
commit | 53677ef18e25c97ac613349087c5cb33ae5a2741 (patch) | |
tree | f947d34d6efaee2401ea0e4c6104ef2f6a0f7ad0 /cpu/ppc4xx | |
parent | 727f63334676e760877d43bfb8f0e9331ac8b101 (diff) | |
download | bootable_bootloader_goldelico_gta04-53677ef18e25c97ac613349087c5cb33ae5a2741.zip bootable_bootloader_goldelico_gta04-53677ef18e25c97ac613349087c5cb33ae5a2741.tar.gz bootable_bootloader_goldelico_gta04-53677ef18e25c97ac613349087c5cb33ae5a2741.tar.bz2 |
Big white-space cleanup.
This commit gets rid of a huge amount of silly white-space issues.
Especially, all sequences of SPACEs followed by TAB characters get
removed (unless they appear in print statements).
Also remove all embedded "vim:" and "vi:" statements which hide
indentation problems.
Signed-off-by: Wolfgang Denk <wd@denx.de>
Diffstat (limited to 'cpu/ppc4xx')
-rw-r--r-- | cpu/ppc4xx/4xx_pci.c | 2 | ||||
-rw-r--r-- | cpu/ppc4xx/4xx_pcie.c | 4 | ||||
-rw-r--r-- | cpu/ppc4xx/i2c.c | 2 | ||||
-rw-r--r-- | cpu/ppc4xx/kgdb.S | 2 | ||||
-rw-r--r-- | cpu/ppc4xx/speed.c | 2 | ||||
-rw-r--r-- | cpu/ppc4xx/start.S | 58 | ||||
-rw-r--r-- | cpu/ppc4xx/usb_ohci.c | 2 |
7 files changed, 36 insertions, 36 deletions
diff --git a/cpu/ppc4xx/4xx_pci.c b/cpu/ppc4xx/4xx_pci.c index 941d4dc..c28c7ac 100644 --- a/cpu/ppc4xx/4xx_pci.c +++ b/cpu/ppc4xx/4xx_pci.c @@ -46,7 +46,7 @@ * 10-Dec-99 Updated PCI_Write_CFG_Reg for pass2 errata #6 JWB * 11-Jan-00 Ensure PMMxMAs disabled before setting PMMxLAs. This is not * really required after a reset since PMMxMAs are already - * disabled but is a good practice nonetheless. JWB + * disabled but is a good practice nonetheless. JWB * 12-Jun-01 stefan.roese@esd-electronics.com * - PCI host/adapter handling reworked * 09-Jul-01 stefan.roese@esd-electronics.com diff --git a/cpu/ppc4xx/4xx_pcie.c b/cpu/ppc4xx/4xx_pcie.c index f9a1988..503facc 100644 --- a/cpu/ppc4xx/4xx_pcie.c +++ b/cpu/ppc4xx/4xx_pcie.c @@ -444,8 +444,8 @@ static void ppc4xx_setup_utl(u32 port) /* * TODO: double check PCI express SDR based on the latest user manual - * Some registers specified here no longer exist.. has to be - * updated based on the final EAS spec. + * Some registers specified here no longer exist.. has to be + * updated based on the final EAS spec. */ static int check_error(void) { diff --git a/cpu/ppc4xx/i2c.c b/cpu/ppc4xx/i2c.c index 47c264e..d8be2ce 100644 --- a/cpu/ppc4xx/i2c.c +++ b/cpu/ppc4xx/i2c.c @@ -61,7 +61,7 @@ static void _i2c_bus_reset(void) /* write 1 in IRQP IRQD LA ICT XFRA to clear these fields */ out_8((u8 *)IIC_EXTSTS, 0x8F); - /* Place chip in the reset state */ + /* Place chip in the reset state */ out_8((u8 *)IIC_XTCNTLSS, IIC_XTCNTLSS_SRST); /* Check if bus is free */ diff --git a/cpu/ppc4xx/kgdb.S b/cpu/ppc4xx/kgdb.S index 42b9546..4227a4c 100644 --- a/cpu/ppc4xx/kgdb.S +++ b/cpu/ppc4xx/kgdb.S @@ -45,7 +45,7 @@ kgdb_flush_cache_all: iccci r0,r0 /* iccci invalidates the entire I cache */ /* dcache */ addi r6,0,0x0000 /* clear GPR 6 */ - addi r7,r0, 128 /* do loop for # of dcache lines */ + addi r7,r0, 128 /* do loop for # of dcache lines */ /* NOTE: dccci invalidates both */ mtctr r7 /* ways in the D cache */ ..dcloop: diff --git a/cpu/ppc4xx/speed.c b/cpu/ppc4xx/speed.c index 8b4e64a..ef47ffc 100644 --- a/cpu/ppc4xx/speed.c +++ b/cpu/ppc4xx/speed.c @@ -1126,7 +1126,7 @@ void get_sys_info (sys_info_t * sysInfo) m = sysInfo->pllFwdDiv * plb2xDiv * 2 * sysInfo->pllOpbDiv * sysInfo->pllExtBusDiv; break; - case PLL_FBK_PLL_LOCAL: + case PLL_FBK_PLL_LOCAL: break; default: printf("%s unknown m\n", __FUNCTION__); diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S index a513b45..0008170 100644 --- a/cpu/ppc4xx/start.S +++ b/cpu/ppc4xx/start.S @@ -852,7 +852,7 @@ _start: mtdccr r1 /* data cache */ addis r1,r0,CFG_INIT_RAM_ADDR@h - ori r1,r1,CFG_INIT_SP_OFFSET /* set up the stack to SDRAM */ + ori r1,r1,CFG_INIT_SP_OFFSET /* set up the stack to SDRAM */ li r0, 0 /* Make room for stack frame header and */ stwu r0, -4(r1) /* clear final stack frame so that */ stwu r0, -4(r1) /* stack backtraces terminate cleanly */ @@ -947,11 +947,11 @@ _start: /*----------------------------------------------------------------------- */ /* DMA Status, clear to come up clean */ /*----------------------------------------------------------------------- */ - addis r3,r0, 0xFFFF /* Clear all existing DMA status */ + addis r3,r0, 0xFFFF /* Clear all existing DMA status */ ori r3,r3, 0xFFFF mtdcr dmasr, r3 - bl ppc405ep_init /* do ppc405ep specific init */ + bl ppc405ep_init /* do ppc405ep specific init */ #endif /* CONFIG_405EP */ #if defined(CFG_OCM_DATA_ADDR) && defined(CFG_OCM_DATA_SIZE) @@ -1809,13 +1809,13 @@ ppc405ep_init: !----------------------------------------------------------------------- */ mfdcr r5, CPC0_PLLMR1 - rlwinm r4,r5,1,0x1 /* get system clock source (SSCS) */ + rlwinm r4,r5,1,0x1 /* get system clock source (SSCS) */ cmpi cr0,0,r4,0x1 - beq pll_done /* if SSCS =b'1' then PLL has */ - /* already been set */ - /* and CPU has been reset */ - /* so skip to next section */ + beq pll_done /* if SSCS =b'1' then PLL has */ + /* already been set */ + /* and CPU has been reset */ + /* so skip to next section */ #ifdef CONFIG_BUBINGA /* @@ -1837,13 +1837,13 @@ ppc405ep_init: lwz r4, 0(r3) addis r5,0,NVRVFY1@h addi r5,r5,NVRVFY1@l - cmp cr0,0,r4,r5 /* Compare 1st NVRAM Magic number*/ + cmp cr0,0,r4,r5 /* Compare 1st NVRAM Magic number*/ bne ..no_pllset addi r3,r3,4 lwz r4, 0(r3) addis r5,0,NVRVFY2@h addi r5,r5,NVRVFY2@l - cmp cr0,0,r4,r5 /* Compare 2 NVRAM Magic number */ + cmp cr0,0,r4,r5 /* Compare 2 NVRAM Magic number */ bne ..no_pllset addi r3,r3,8 /* Skip over conf_size */ lwz r4, 4(r3) /* Load PLLMR1 value from NVRAM */ @@ -1867,7 +1867,7 @@ ppc405ep_init: #if defined(CONFIG_ZEUS) mfdcr r4, CPC0_BOOT andi. r5, r4, CPC0_BOOT_SEP@l - bne strap_1 /* serial eeprom present */ + bne strap_1 /* serial eeprom present */ lis r3,0x0000 addi r3,r3,0x3030 lis r4,0x8042 @@ -1879,10 +1879,10 @@ strap_1: b 1f #endif - addis r3,0,PLLMR0_DEFAULT@h /* PLLMR0 default value */ - ori r3,r3,PLLMR0_DEFAULT@l /* */ - addis r4,0,PLLMR1_DEFAULT@h /* PLLMR1 default value */ - ori r4,r4,PLLMR1_DEFAULT@l /* */ + addis r3,0,PLLMR0_DEFAULT@h /* PLLMR0 default value */ + ori r3,r3,PLLMR0_DEFAULT@l /* */ + addis r4,0,PLLMR1_DEFAULT@h /* PLLMR1 default value */ + ori r4,r4,PLLMR1_DEFAULT@l /* */ #ifdef CONFIG_TAIHU b 1f @@ -1898,7 +1898,7 @@ strap_1: #endif /* CONFIG_TAIHU */ 1: - b pll_write /* Write the CPC0_PLLMR with new value */ + b pll_write /* Write the CPC0_PLLMR with new value */ pll_done: /* @@ -1915,7 +1915,7 @@ pll_done: pci_wait: bdnz pci_wait - blr /* return to main code */ + blr /* return to main code */ /* !----------------------------------------------------------------------------- @@ -1936,20 +1936,20 @@ pci_wait: pll_write: mfdcr r5, CPC0_UCR andis. r5,r5,0xFFFF - ori r5,r5,0x0101 /* Stop the UART clocks */ - mtdcr CPC0_UCR,r5 /* Before changing PLL */ + ori r5,r5,0x0101 /* Stop the UART clocks */ + mtdcr CPC0_UCR,r5 /* Before changing PLL */ mfdcr r5, CPC0_PLLMR1 - rlwinm r5,r5,0,0x7FFFFFFF /* Disable PLL */ + rlwinm r5,r5,0,0x7FFFFFFF /* Disable PLL */ mtdcr CPC0_PLLMR1,r5 - oris r5,r5,0x4000 /* Set PLL Reset */ + oris r5,r5,0x4000 /* Set PLL Reset */ mtdcr CPC0_PLLMR1,r5 - mtdcr CPC0_PLLMR0,r3 /* Set clock dividers */ - rlwinm r5,r4,0,0x3FFFFFFF /* Reset & Bypass new PLL dividers */ - oris r5,r5,0x4000 /* Set PLL Reset */ - mtdcr CPC0_PLLMR1,r5 /* Set clock dividers */ - rlwinm r5,r5,0,0xBFFFFFFF /* Clear PLL Reset */ + mtdcr CPC0_PLLMR0,r3 /* Set clock dividers */ + rlwinm r5,r4,0,0x3FFFFFFF /* Reset & Bypass new PLL dividers */ + oris r5,r5,0x4000 /* Set PLL Reset */ + mtdcr CPC0_PLLMR1,r5 /* Set clock dividers */ + rlwinm r5,r5,0,0xBFFFFFFF /* Clear PLL Reset */ mtdcr CPC0_PLLMR1,r5 /* @@ -1970,9 +1970,9 @@ pll_wait: * Not sure if this is needed... */ addis r3,0,0x1000 - mtspr dbcr0,r3 /* This will cause a CPU core reset, and */ - /* execution will continue from the poweron */ - /* vector of 0xfffffffc */ + mtspr dbcr0,r3 /* This will cause a CPU core reset, and */ + /* execution will continue from the poweron */ + /* vector of 0xfffffffc */ #endif /* CONFIG_405EP */ #if defined(CONFIG_440) diff --git a/cpu/ppc4xx/usb_ohci.c b/cpu/ppc4xx/usb_ohci.c index 7dbb288..5dbd842 100644 --- a/cpu/ppc4xx/usb_ohci.c +++ b/cpu/ppc4xx/usb_ohci.c @@ -1600,7 +1600,7 @@ int usb_lowlevel_init(void) gohci.sleeping = 0; gohci.irq = -1; #if defined(CONFIG_440EP) - gohci.regs = (struct ohci_regs *)(CFG_PERIPHERAL_BASE | 0x1000); + gohci.regs = (struct ohci_regs *)(CFG_PERIPHERAL_BASE | 0x1000); #elif defined(CONFIG_440EPX) || defined(CFG_USB_HOST) gohci.regs = (struct ohci_regs *)(CFG_USB_HOST); #endif |