diff options
| author | Julien May <mailinglist@miromico.ch> | 2008-06-23 13:57:52 +0200 |
|---|---|---|
| committer | Haavard Skinnemoen <haavard.skinnemoen@atmel.com> | 2008-07-30 10:06:11 +0200 |
| commit | 5c374c9ee16fee2bf68533cc4010b3c0df21f783 (patch) | |
| tree | ba1adfdfda78d9c7061199fc4de438527b941df5 /cpu | |
| parent | 1ca9950b46c0aded14c80f728f6238625d723a19 (diff) | |
| download | bootable_bootloader_goldelico_gta04-5c374c9ee16fee2bf68533cc4010b3c0df21f783.zip bootable_bootloader_goldelico_gta04-5c374c9ee16fee2bf68533cc4010b3c0df21f783.tar.gz bootable_bootloader_goldelico_gta04-5c374c9ee16fee2bf68533cc4010b3c0df21f783.tar.bz2 | |
Add support for the hammerhead (AVR32) board
The Hammerhead platform is built around a AVR32 32-bit microcontroller
from Atmel. It offers versatile peripherals, such as ethernet, usb
device, usb host etc.
The board also incooperates a power supply and is a Power over Ethernet
(PoE) Powered Device (PD).
Additonally, a Cyclone III FPGA from Altera is integrated on the board.
The FPGA is mapped into the 32-bit AVR memory bus. The FPGA offers two
DDR2 SDRAM interfaces, which will cover even the most exceptional need
of memory bandwidth. Together with the onboard video decoder the board
is ready for video processing.
For more information see: http:///www.miromico.com/hammerhead
Signed-off-by: Julien May <mailinglist@miromico.ch>
[haavard.skinnemoen@atmel.com: various small fixes and adaptions]
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Diffstat (limited to 'cpu')
| -rw-r--r-- | cpu/at32ap/at32ap700x/sm.h | 2 | ||||
| -rw-r--r-- | cpu/at32ap/cpu.c | 3 |
2 files changed, 4 insertions, 1 deletions
diff --git a/cpu/at32ap/at32ap700x/sm.h b/cpu/at32ap/at32ap700x/sm.h index 6492c8e..b6e4409 100644 --- a/cpu/at32ap/at32ap700x/sm.h +++ b/cpu/at32ap/at32ap700x/sm.h @@ -21,7 +21,7 @@ #define SM_PM_IMR 0x0048 #define SM_PM_ISR 0x004c #define SM_PM_ICR 0x0050 -#define SM_PM_GCCTRL 0x0060 +#define SM_PM_GCCTRL(x) (0x0060 + 4 * x) #define SM_RTC_CTRL 0x0080 #define SM_RTC_VAL 0x0084 #define SM_RTC_TOP 0x0088 diff --git a/cpu/at32ap/cpu.c b/cpu/at32ap/cpu.c index 0ba8361..1a13702 100644 --- a/cpu/at32ap/cpu.c +++ b/cpu/at32ap/cpu.c @@ -65,6 +65,9 @@ int cpu_init(void) sysreg_write(EVBA, (unsigned long)&_evba); asm volatile("csrf %0" : : "i"(SYSREG_EM_OFFSET)); + if(gclk_init) + gclk_init(); + return 0; } |