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| author | Scott Wood <scottwood@freescale.com> | 2008-05-22 15:02:46 -0500 |
|---|---|---|
| committer | Scott Wood <scottwood@freescale.com> | 2008-08-12 11:31:26 -0500 |
| commit | 300253306acc72b1b2e9faf0987f86551151d7cf (patch) | |
| tree | 643e6d50f2dcbab09e5208ed1d2b323370278bf1 /drivers/mtd | |
| parent | 9c814b0a716aae884bec977b9a032dfa59cfb79a (diff) | |
| download | bootable_bootloader_goldelico_gta04-300253306acc72b1b2e9faf0987f86551151d7cf.zip bootable_bootloader_goldelico_gta04-300253306acc72b1b2e9faf0987f86551151d7cf.tar.gz bootable_bootloader_goldelico_gta04-300253306acc72b1b2e9faf0987f86551151d7cf.tar.bz2 | |
fsl_elbc_nand: Hard-code the FBAR/FPAR split.
The hardware has separate registers for block and page-within-block,
but the division between the two has no apparent relation to the
actual erase block size of the NAND chip.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Diffstat (limited to 'drivers/mtd')
| -rw-r--r-- | drivers/mtd/nand/fsl_elbc_nand.c | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/drivers/mtd/nand/fsl_elbc_nand.c b/drivers/mtd/nand/fsl_elbc_nand.c index ab3e0fd..0bd1bdb 100644 --- a/drivers/mtd/nand/fsl_elbc_nand.c +++ b/drivers/mtd/nand/fsl_elbc_nand.c @@ -138,15 +138,14 @@ static void set_addr(struct mtd_info *mtd, int column, int page_addr, int oob) ctrl->page = page_addr; - out_be32(&lbc->fbar, - page_addr >> (chip->phys_erase_shift - chip->page_shift)); - if (priv->page_size) { + out_be32(&lbc->fbar, page_addr >> 6); out_be32(&lbc->fpar, ((page_addr << FPAR_LP_PI_SHIFT) & FPAR_LP_PI) | (oob ? FPAR_LP_MS : 0) | column); buf_num = (page_addr & 1) << 2; } else { + out_be32(&lbc->fbar, page_addr >> 5); out_be32(&lbc->fpar, ((page_addr << FPAR_SP_PI_SHIFT) & FPAR_SP_PI) | (oob ? FPAR_SP_MS : 0) | column); |