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| author | Julien May <mailinglist@miromico.ch> | 2008-06-23 13:57:52 +0200 |
|---|---|---|
| committer | Haavard Skinnemoen <haavard.skinnemoen@atmel.com> | 2008-07-30 10:06:11 +0200 |
| commit | 5c374c9ee16fee2bf68533cc4010b3c0df21f783 (patch) | |
| tree | ba1adfdfda78d9c7061199fc4de438527b941df5 /include/asm-avr32 | |
| parent | 1ca9950b46c0aded14c80f728f6238625d723a19 (diff) | |
| download | bootable_bootloader_goldelico_gta04-5c374c9ee16fee2bf68533cc4010b3c0df21f783.zip bootable_bootloader_goldelico_gta04-5c374c9ee16fee2bf68533cc4010b3c0df21f783.tar.gz bootable_bootloader_goldelico_gta04-5c374c9ee16fee2bf68533cc4010b3c0df21f783.tar.bz2 | |
Add support for the hammerhead (AVR32) board
The Hammerhead platform is built around a AVR32 32-bit microcontroller
from Atmel. It offers versatile peripherals, such as ethernet, usb
device, usb host etc.
The board also incooperates a power supply and is a Power over Ethernet
(PoE) Powered Device (PD).
Additonally, a Cyclone III FPGA from Altera is integrated on the board.
The FPGA is mapped into the 32-bit AVR memory bus. The FPGA offers two
DDR2 SDRAM interfaces, which will cover even the most exceptional need
of memory bandwidth. Together with the onboard video decoder the board
is ready for video processing.
For more information see: http:///www.miromico.com/hammerhead
Signed-off-by: Julien May <mailinglist@miromico.ch>
[haavard.skinnemoen@atmel.com: various small fixes and adaptions]
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Diffstat (limited to 'include/asm-avr32')
| -rw-r--r-- | include/asm-avr32/arch-at32ap700x/clk.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/include/asm-avr32/arch-at32ap700x/clk.h b/include/asm-avr32/arch-at32ap700x/clk.h index a9d8431..e9a4fe4 100644 --- a/include/asm-avr32/arch-at32ap700x/clk.h +++ b/include/asm-avr32/arch-at32ap700x/clk.h @@ -82,6 +82,7 @@ static inline unsigned long get_spi_clk_rate(unsigned int dev_id) #endif extern void clk_init(void); +extern void gclk_init(void) __attribute__((weak)); /* Board code may need the SDRAM base clock as a compile-time constant */ #define SDRAMC_BUS_HZ (MAIN_CLK_RATE >> CFG_CLKDIV_HSB) |