avr32: refactor the portmux/gpio code

  - Separate the portmux configuration functionality from the GPIO pin
    control API.
  - Separate the controller-specific code from the chip-specific code.
  - Allow "ganged" port configuration (multiple pins at once).
  - Add more flexibility to the "canned" peripheral select functions:
      - Allow using more than 23 address bits, more chip selects, as
	well as NAND- and CF-specific pins.
      - Make the MACB SPEED pin optional, and choose between MII/RMII
	using a parameter instead of an #ifdef.
      - Make it possible to use other MMC slots than slot 0, and support
	different MMC/SDCard data bus widths.
  - Use more reasonable pull-up defaults; floating pins may consume a
    lot of power.
  - Get rid of some custom portmux code from the mimc200 board code. The
    old gpio/portmux API couldn't really handle its requirements, but
    the new one can.
  - Add documentation.

The end result is slightly smaller code for all boards. Which isn't
really the point, but at least it isn't any larger.

This has been verified on ATSTK1002 and ATNGW100. I'd appreciate if
the board maintainers could help me test this on their boards. In
particular, the mimc200 port has lost a lot of code, so I'm hoping Mark
can help me out.

Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Cc: Hans-Christian Egtvedt <hans-christian.egtvedt@atmel.com>
Cc: Mark Jackson <mpfj@mimc.co.uk>
Cc: Alex Raimondi <alex.raimondi@miromico.ch>
Cc: Julien May <julien.may@miromico.ch>

Changes since v1:
  * Enable pullup on NWAIT
  * Add missing include to portmux-pio.h
  * Rename CONFIG_PIO2 -> CONFIG_PORTMUX_PIO to match docs

3 files changed, 235 insertions, 176 deletions

diff --git a/include/asm-avr32/arch-at32ap700x/gpio.h b/include/asm-avr32/arch-at32ap700x/gpio.h
index 8c922c7..303e353 100644
--- a/include/asm-avr32/arch-at32ap700x/gpio.h
+++ b/include/asm-avr32/arch-at32ap700x/gpio.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2006 Atmel Corporation
+ * Copyright (C) 2006, 2008 Atmel Corporation
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -31,161 +31,17 @@
  * Pin numbers identifying specific GPIO pins on the chip.
  */
 #define GPIO_PIOA_BASE	(0)
-#define GPIO_PIN_PA0	(GPIO_PIOA_BASE +  0)
-#define GPIO_PIN_PA1	(GPIO_PIOA_BASE +  1)
-#define GPIO_PIN_PA2	(GPIO_PIOA_BASE +  2)
-#define GPIO_PIN_PA3	(GPIO_PIOA_BASE +  3)
-#define GPIO_PIN_PA4	(GPIO_PIOA_BASE +  4)
-#define GPIO_PIN_PA5	(GPIO_PIOA_BASE +  5)
-#define GPIO_PIN_PA6	(GPIO_PIOA_BASE +  6)
-#define GPIO_PIN_PA7	(GPIO_PIOA_BASE +  7)
-#define GPIO_PIN_PA8	(GPIO_PIOA_BASE +  8)
-#define GPIO_PIN_PA9	(GPIO_PIOA_BASE +  9)
-#define GPIO_PIN_PA10	(GPIO_PIOA_BASE + 10)
-#define GPIO_PIN_PA11	(GPIO_PIOA_BASE + 11)
-#define GPIO_PIN_PA12	(GPIO_PIOA_BASE + 12)
-#define GPIO_PIN_PA13	(GPIO_PIOA_BASE + 13)
-#define GPIO_PIN_PA14	(GPIO_PIOA_BASE + 14)
-#define GPIO_PIN_PA15	(GPIO_PIOA_BASE + 15)
-#define GPIO_PIN_PA16	(GPIO_PIOA_BASE + 16)
-#define GPIO_PIN_PA17	(GPIO_PIOA_BASE + 17)
-#define GPIO_PIN_PA18	(GPIO_PIOA_BASE + 18)
-#define GPIO_PIN_PA19	(GPIO_PIOA_BASE + 19)
-#define GPIO_PIN_PA20	(GPIO_PIOA_BASE + 20)
-#define GPIO_PIN_PA21	(GPIO_PIOA_BASE + 21)
-#define GPIO_PIN_PA22	(GPIO_PIOA_BASE + 22)
-#define GPIO_PIN_PA23	(GPIO_PIOA_BASE + 23)
-#define GPIO_PIN_PA24	(GPIO_PIOA_BASE + 24)
-#define GPIO_PIN_PA25	(GPIO_PIOA_BASE + 25)
-#define GPIO_PIN_PA26	(GPIO_PIOA_BASE + 26)
-#define GPIO_PIN_PA27	(GPIO_PIOA_BASE + 27)
-#define GPIO_PIN_PA28	(GPIO_PIOA_BASE + 28)
-#define GPIO_PIN_PA29	(GPIO_PIOA_BASE + 29)
-#define GPIO_PIN_PA30	(GPIO_PIOA_BASE + 30)
-#define GPIO_PIN_PA31	(GPIO_PIOA_BASE + 31)
-
 #define GPIO_PIOB_BASE	(GPIO_PIOA_BASE + 32)
-#define GPIO_PIN_PB0	(GPIO_PIOB_BASE +  0)
-#define GPIO_PIN_PB1	(GPIO_PIOB_BASE +  1)
-#define GPIO_PIN_PB2	(GPIO_PIOB_BASE +  2)
-#define GPIO_PIN_PB3	(GPIO_PIOB_BASE +  3)
-#define GPIO_PIN_PB4	(GPIO_PIOB_BASE +  4)
-#define GPIO_PIN_PB5	(GPIO_PIOB_BASE +  5)
-#define GPIO_PIN_PB6	(GPIO_PIOB_BASE +  6)
-#define GPIO_PIN_PB7	(GPIO_PIOB_BASE +  7)
-#define GPIO_PIN_PB8	(GPIO_PIOB_BASE +  8)
-#define GPIO_PIN_PB9	(GPIO_PIOB_BASE +  9)
-#define GPIO_PIN_PB10	(GPIO_PIOB_BASE + 10)
-#define GPIO_PIN_PB11	(GPIO_PIOB_BASE + 11)
-#define GPIO_PIN_PB12	(GPIO_PIOB_BASE + 12)
-#define GPIO_PIN_PB13	(GPIO_PIOB_BASE + 13)
-#define GPIO_PIN_PB14	(GPIO_PIOB_BASE + 14)
-#define GPIO_PIN_PB15	(GPIO_PIOB_BASE + 15)
-#define GPIO_PIN_PB16	(GPIO_PIOB_BASE + 16)
-#define GPIO_PIN_PB17	(GPIO_PIOB_BASE + 17)
-#define GPIO_PIN_PB18	(GPIO_PIOB_BASE + 18)
-#define GPIO_PIN_PB19	(GPIO_PIOB_BASE + 19)
-#define GPIO_PIN_PB20	(GPIO_PIOB_BASE + 20)
-#define GPIO_PIN_PB21	(GPIO_PIOB_BASE + 21)
-#define GPIO_PIN_PB22	(GPIO_PIOB_BASE + 22)
-#define GPIO_PIN_PB23	(GPIO_PIOB_BASE + 23)
-#define GPIO_PIN_PB24	(GPIO_PIOB_BASE + 24)
-#define GPIO_PIN_PB25	(GPIO_PIOB_BASE + 25)
-#define GPIO_PIN_PB26	(GPIO_PIOB_BASE + 26)
-#define GPIO_PIN_PB27	(GPIO_PIOB_BASE + 27)
-#define GPIO_PIN_PB28	(GPIO_PIOB_BASE + 28)
-#define GPIO_PIN_PB29	(GPIO_PIOB_BASE + 29)
-#define GPIO_PIN_PB30	(GPIO_PIOB_BASE + 30)
-
 #define GPIO_PIOC_BASE	(GPIO_PIOB_BASE + 32)
-#define GPIO_PIN_PC0	(GPIO_PIOC_BASE +  0)
-#define GPIO_PIN_PC1	(GPIO_PIOC_BASE +  1)
-#define GPIO_PIN_PC2	(GPIO_PIOC_BASE +  2)
-#define GPIO_PIN_PC3	(GPIO_PIOC_BASE +  3)
-#define GPIO_PIN_PC4	(GPIO_PIOC_BASE +  4)
-#define GPIO_PIN_PC5	(GPIO_PIOC_BASE +  5)
-#define GPIO_PIN_PC6	(GPIO_PIOC_BASE +  6)
-#define GPIO_PIN_PC7	(GPIO_PIOC_BASE +  7)
-#define GPIO_PIN_PC8	(GPIO_PIOC_BASE +  8)
-#define GPIO_PIN_PC9	(GPIO_PIOC_BASE +  9)
-#define GPIO_PIN_PC10	(GPIO_PIOC_BASE + 10)
-#define GPIO_PIN_PC11	(GPIO_PIOC_BASE + 11)
-#define GPIO_PIN_PC12	(GPIO_PIOC_BASE + 12)
-#define GPIO_PIN_PC13	(GPIO_PIOC_BASE + 13)
-#define GPIO_PIN_PC14	(GPIO_PIOC_BASE + 14)
-#define GPIO_PIN_PC15	(GPIO_PIOC_BASE + 15)
-#define GPIO_PIN_PC16	(GPIO_PIOC_BASE + 16)
-#define GPIO_PIN_PC17	(GPIO_PIOC_BASE + 17)
-#define GPIO_PIN_PC18	(GPIO_PIOC_BASE + 18)
-#define GPIO_PIN_PC19	(GPIO_PIOC_BASE + 19)
-#define GPIO_PIN_PC20	(GPIO_PIOC_BASE + 20)
-#define GPIO_PIN_PC21	(GPIO_PIOC_BASE + 21)
-#define GPIO_PIN_PC22	(GPIO_PIOC_BASE + 22)
-#define GPIO_PIN_PC23	(GPIO_PIOC_BASE + 23)
-#define GPIO_PIN_PC24	(GPIO_PIOC_BASE + 24)
-#define GPIO_PIN_PC25	(GPIO_PIOC_BASE + 25)
-#define GPIO_PIN_PC26	(GPIO_PIOC_BASE + 26)
-#define GPIO_PIN_PC27	(GPIO_PIOC_BASE + 27)
-#define GPIO_PIN_PC28	(GPIO_PIOC_BASE + 28)
-#define GPIO_PIN_PC29	(GPIO_PIOC_BASE + 29)
-#define GPIO_PIN_PC30	(GPIO_PIOC_BASE + 30)
-#define GPIO_PIN_PC31	(GPIO_PIOC_BASE + 31)
-
 #define GPIO_PIOD_BASE	(GPIO_PIOC_BASE + 32)
-#define GPIO_PIN_PD0	(GPIO_PIOD_BASE +  0)
-#define GPIO_PIN_PD1	(GPIO_PIOD_BASE +  1)
-#define GPIO_PIN_PD2	(GPIO_PIOD_BASE +  2)
-#define GPIO_PIN_PD3	(GPIO_PIOD_BASE +  3)
-#define GPIO_PIN_PD4	(GPIO_PIOD_BASE +  4)
-#define GPIO_PIN_PD5	(GPIO_PIOD_BASE +  5)
-#define GPIO_PIN_PD6	(GPIO_PIOD_BASE +  6)
-#define GPIO_PIN_PD7	(GPIO_PIOD_BASE +  7)
-#define GPIO_PIN_PD8	(GPIO_PIOD_BASE +  8)
-#define GPIO_PIN_PD9	(GPIO_PIOD_BASE +  9)
-#define GPIO_PIN_PD10	(GPIO_PIOD_BASE + 10)
-#define GPIO_PIN_PD11	(GPIO_PIOD_BASE + 11)
-#define GPIO_PIN_PD12	(GPIO_PIOD_BASE + 12)
-#define GPIO_PIN_PD13	(GPIO_PIOD_BASE + 13)
-#define GPIO_PIN_PD14	(GPIO_PIOD_BASE + 14)
-#define GPIO_PIN_PD15	(GPIO_PIOD_BASE + 15)
-#define GPIO_PIN_PD16	(GPIO_PIOD_BASE + 16)
-#define GPIO_PIN_PD17	(GPIO_PIOD_BASE + 17)
-
 #define GPIO_PIOE_BASE	(GPIO_PIOD_BASE + 32)
-#define GPIO_PIN_PE0	(GPIO_PIOE_BASE +  0)
-#define GPIO_PIN_PE1	(GPIO_PIOE_BASE +  1)
-#define GPIO_PIN_PE2	(GPIO_PIOE_BASE +  2)
-#define GPIO_PIN_PE3	(GPIO_PIOE_BASE +  3)
-#define GPIO_PIN_PE4	(GPIO_PIOE_BASE +  4)
-#define GPIO_PIN_PE5	(GPIO_PIOE_BASE +  5)
-#define GPIO_PIN_PE6	(GPIO_PIOE_BASE +  6)
-#define GPIO_PIN_PE7	(GPIO_PIOE_BASE +  7)
-#define GPIO_PIN_PE8	(GPIO_PIOE_BASE +  8)
-#define GPIO_PIN_PE9	(GPIO_PIOE_BASE +  9)
-#define GPIO_PIN_PE10	(GPIO_PIOE_BASE + 10)
-#define GPIO_PIN_PE11	(GPIO_PIOE_BASE + 11)
-#define GPIO_PIN_PE12	(GPIO_PIOE_BASE + 12)
-#define GPIO_PIN_PE13	(GPIO_PIOE_BASE + 13)
-#define GPIO_PIN_PE14	(GPIO_PIOE_BASE + 14)
-#define GPIO_PIN_PE15	(GPIO_PIOE_BASE + 15)
-#define GPIO_PIN_PE16	(GPIO_PIOE_BASE + 16)
-#define GPIO_PIN_PE17	(GPIO_PIOE_BASE + 17)
-#define GPIO_PIN_PE18	(GPIO_PIOE_BASE + 18)
-#define GPIO_PIN_PE19	(GPIO_PIOE_BASE + 19)
-#define GPIO_PIN_PE20	(GPIO_PIOE_BASE + 20)
-#define GPIO_PIN_PE21	(GPIO_PIOE_BASE + 21)
-#define GPIO_PIN_PE22	(GPIO_PIOE_BASE + 22)
-#define GPIO_PIN_PE23	(GPIO_PIOE_BASE + 23)
-#define GPIO_PIN_PE24	(GPIO_PIOE_BASE + 24)
-#define GPIO_PIN_PE25	(GPIO_PIOE_BASE + 25)
-#define GPIO_PIN_PE26	(GPIO_PIOE_BASE + 26)
+#define GPIO_PIN_PA(x)	(GPIO_PIOA_BASE + (x))
+#define GPIO_PIN_PB(x)	(GPIO_PIOB_BASE + (x))
+#define GPIO_PIN_PC(x)	(GPIO_PIOC_BASE + (x))
+#define GPIO_PIN_PD(x)	(GPIO_PIOD_BASE + (x))
+#define GPIO_PIN_PE(x)	(GPIO_PIOE_BASE + (x))
 
-#define GPIOF_PULLUP	0x00000001	/* (not-OUT) Enable pull-up */
-#define GPIOF_OUTPUT	0x00000002	/* (OUT) Enable output driver */
-#define GPIOF_DEGLITCH	0x00000004	/* (IN) Filter glitches */
-#define GPIOF_MULTIDRV	0x00000008	/* Enable multidriver option */
-
-static inline void *gpio_pin_to_addr(unsigned int pin)
+static inline void *pio_pin_to_port(unsigned int pin)
 {
 	switch (pin >> 5) {
 	case 0:
@@ -203,30 +59,6 @@ static inline void *gpio_pin_to_addr(unsigned int pin)
 	}
 }
 
-void gpio_select_periph_A(unsigned int pin, int use_pullup);
-void gpio_select_periph_B(unsigned int pin, int use_pullup);
-void gpio_select_pio(unsigned int pin, unsigned long gpiof_flags);
-void gpio_set_value(unsigned int pin, int value);
-int gpio_get_value(unsigned int pin);
-
-void gpio_enable_ebi(void);
-
-#ifdef AT32AP700x_CHIP_HAS_USART
-void gpio_enable_usart0(void);
-void gpio_enable_usart1(void);
-void gpio_enable_usart2(void);
-void gpio_enable_usart3(void);
-#endif
-#ifdef AT32AP700x_CHIP_HAS_MACB
-void gpio_enable_macb0(void);
-void gpio_enable_macb1(void);
-#endif
-#ifdef AT32AP700x_CHIP_HAS_MMCI
-void gpio_enable_mmci(void);
-#endif
-#ifdef AT32AP700x_CHIP_HAS_SPI
-void gpio_enable_spi0(unsigned long cs_mask);
-void gpio_enable_spi1(unsigned long cs_mask);
-#endif
+#include <asm/arch-common/portmux-pio.h>
 
 #endif /* __ASM_AVR32_ARCH_GPIO_H__ */
diff --git a/include/asm-avr32/arch-at32ap700x/portmux.h b/include/asm-avr32/arch-at32ap700x/portmux.h
new file mode 100644
index 0000000..96fe70d
--- /dev/null
+++ b/include/asm-avr32/arch-at32ap700x/portmux.h
@@ -0,0 +1,89 @@
+/*
+ * Copyright (C) 2006, 2008 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __ASM_AVR32_ARCH_PORTMUX_H__
+#define __ASM_AVR32_ARCH_PORTMUX_H__
+
+#include <asm/arch/gpio.h>
+
+#define PORTMUX_PORT_A		((void *)PIOA_BASE)
+#define PORTMUX_PORT_B		((void *)PIOB_BASE)
+#define PORTMUX_PORT_C		((void *)PIOC_BASE)
+#define PORTMUX_PORT_D		((void *)PIOD_BASE)
+#define PORTMUX_PORT_E		((void *)PIOE_BASE)
+
+void portmux_enable_ebi(unsigned int bus_width, unsigned int addr_width,
+		unsigned long flags, unsigned long drive_strength);
+
+#define PORTMUX_EBI_CS(x)	(1 << (x))
+#define PORTMUX_EBI_NAND	(1 << 6)
+#define PORTMUX_EBI_CF(x)	(1 << ((x) + 7))
+#define PORTMUX_EBI_NWAIT	(1 << 9)
+
+#ifdef AT32AP700x_CHIP_HAS_USART
+static inline void portmux_enable_usart0(unsigned long drive_strength)
+{
+	portmux_select_peripheral(PORTMUX_PORT_A, (1 << 8) | (1 << 9),
+			PORTMUX_FUNC_B, 0);
+}
+
+static inline void portmux_enable_usart1(unsigned long drive_strength)
+{
+	portmux_select_peripheral(PORTMUX_PORT_A, (1 << 17) | (1 << 18),
+			PORTMUX_FUNC_A, 0);
+}
+
+static inline void portmux_enable_usart2(unsigned long drive_strength)
+{
+	portmux_select_peripheral(PORTMUX_PORT_B, (1 << 26) | (1 << 27),
+			PORTMUX_FUNC_B, 0);
+}
+
+static inline void portmux_enable_usart3(unsigned long drive_strength)
+{
+	portmux_select_peripheral(PORTMUX_PORT_B, (1 << 17) | (1 << 18),
+			PORTMUX_FUNC_B, 0);
+}
+#endif
+#ifdef AT32AP700x_CHIP_HAS_MACB
+void portmux_enable_macb0(unsigned long flags, unsigned long drive_strength);
+void portmux_enable_macb1(unsigned long flags, unsigned long drive_strength);
+
+#define PORTMUX_MACB_RMII	(0)
+#define PORTMUX_MACB_MII	(1 << 0)
+#define PORTMUX_MACB_SPEED	(1 << 1)
+
+#endif
+#ifdef AT32AP700x_CHIP_HAS_MMCI
+void portmux_enable_mmci(unsigned int slot, unsigned long flags,
+		unsigned long drive_strength);
+
+#define PORTMUX_MMCI_4BIT	(1 << 0)
+#define PORTMUX_MMCI_8BIT	(PORTMUX_MMCI_4BIT | (1 << 1))
+#define PORTMUX_MMCI_EXT_PULLUP	(1 << 2)
+
+#endif
+#ifdef AT32AP700x_CHIP_HAS_SPI
+void portmux_enable_spi0(unsigned long cs_mask, unsigned long drive_strength);
+void portmux_enable_spi1(unsigned long cs_mask, unsigned long drive_strength);
+#endif
+
+#endif /* __ASM_AVR32_ARCH_PORTMUX_H__ */
diff --git a/include/asm-avr32/arch-common/portmux-pio.h b/include/asm-avr32/arch-common/portmux-pio.h
new file mode 100644
index 0000000..1abe5be
--- /dev/null
+++ b/include/asm-avr32/arch-common/portmux-pio.h
@@ -0,0 +1,138 @@
+/*
+ * Copyright (C) 2006, 2008 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __AVR32_PORTMUX_PIO_H__
+#define __AVR32_PORTMUX_PIO_H__
+
+#include <asm/io.h>
+
+/* PIO register offsets */
+#define PIO_PER			0x0000
+#define PIO_PDR			0x0004
+#define PIO_PSR			0x0008
+#define PIO_OER			0x0010
+#define PIO_ODR			0x0014
+#define PIO_OSR			0x0018
+#define PIO_IFER		0x0020
+#define PIO_IFDR		0x0024
+#define PIO_ISFR		0x0028
+#define PIO_SODR		0x0030
+#define PIO_CODR		0x0034
+#define PIO_ODSR		0x0038
+#define PIO_PDSR		0x003c
+#define PIO_IER			0x0040
+#define PIO_IDR			0x0044
+#define PIO_IMR			0x0048
+#define PIO_ISR			0x004c
+#define PIO_MDER		0x0050
+#define PIO_MDDR		0x0054
+#define PIO_MDSR		0x0058
+#define PIO_PUDR		0x0060
+#define PIO_PUER		0x0064
+#define PIO_PUSR		0x0068
+#define PIO_ASR			0x0070
+#define PIO_BSR			0x0074
+#define PIO_ABSR		0x0078
+#define PIO_OWER		0x00a0
+#define PIO_OWDR		0x00a4
+#define PIO_OWSR		0x00a8
+
+/* Hardware register access */
+#define pio_readl(base, reg)				\
+	__raw_readl((void *)base + PIO_##reg)
+#define pio_writel(base, reg, value)			\
+	__raw_writel((value), (void *)base + PIO_##reg)
+
+/* Portmux API starts here. See doc/README.AVR32-port-muxing */
+
+enum portmux_function {
+	PORTMUX_FUNC_A,
+	PORTMUX_FUNC_B,
+};
+
+/* Pull-down, buskeeper and drive strength are not supported */
+#define PORTMUX_DIR_INPUT	(0 << 0)
+#define PORTMUX_DIR_OUTPUT	(1 << 0)
+#define PORTMUX_INIT_LOW	(0 << 1)
+#define PORTMUX_INIT_HIGH	(1 << 1)
+#define PORTMUX_PULL_UP		(1 << 2)
+#define PORTMUX_PULL_DOWN	(0)
+#define PORTMUX_BUSKEEPER	PORTMUX_PULL_UP
+#define PORTMUX_DRIVE_MIN	(0)
+#define PORTMUX_DRIVE_LOW	(0)
+#define PORTMUX_DRIVE_HIGH	(0)
+#define PORTMUX_DRIVE_MAX	(0)
+#define PORTMUX_OPEN_DRAIN	(1 << 3)
+
+void portmux_select_peripheral(void *port, unsigned long pin_mask,
+		enum portmux_function func, unsigned long flags);
+void portmux_select_gpio(void *port, unsigned long pin_mask,
+		unsigned long flags);
+
+/* Internal helper functions */
+
+static inline void __pio_set_output_value(void *port, unsigned int pin,
+		int value)
+{
+	/*
+	 * value will usually be constant, but it's pretty cheap
+	 * either way.
+	 */
+	if (value)
+		pio_writel(port, SODR, 1 << pin);
+	else
+		pio_writel(port, CODR, 1 << pin);
+}
+
+static inline int __pio_get_input_value(void *port, unsigned int pin)
+{
+	return (pio_readl(port, PDSR) >> pin) & 1;
+}
+
+void pio_set_output_value(unsigned int pin, int value);
+int pio_get_input_value(unsigned int pin);
+
+/* GPIO API starts here */
+
+/*
+ * GCC doesn't realize that the constant case is extremely trivial,
+ * so we need to help it make the right decision by using
+ * always_inline.
+ */
+__attribute__((always_inline))
+static inline void gpio_set_value(unsigned int pin, int value)
+{
+	if (__builtin_constant_p(pin))
+		__pio_set_output_value(pio_pin_to_port(pin), pin & 0x1f, value);
+	else
+		pio_set_output_value(pin, value);
+}
+
+__attribute__((always_inline))
+static inline int gpio_get_value(unsigned int pin)
+{
+	if (__builtin_constant_p(pin))
+		return __pio_get_input_value(pio_pin_to_port(pin), pin & 0x1f);
+	else
+		return pio_get_input_value(pin);
+}
+
+#endif /* __AVR32_PORTMUX_PIO_H__ */