AVR32: Make SDRAM refresh rate configurable

The existing code assumes the SDRAM row refresh period should always
be 15.6 us. This is not always true, and indeed on the ATNGW100, the
refresh rate should really be 7.81 us.

Add a refresh_period member to struct sdram_info and initialize it
properly for both ATSTK1000 and ATNGW100. Out-of-tree boards will
panic() until the refresh_period member is updated properly.

Big thanks to Gerhard Berghofer for pointing out this issue.

Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>

2 files changed, 6 insertions, 0 deletions

diff --git a/include/asm-avr32/arch-at32ap700x/clk.h b/include/asm-avr32/arch-at32ap700x/clk.h
index ea84c08..385319a 100644
--- a/include/asm-avr32/arch-at32ap700x/clk.h
+++ b/include/asm-avr32/arch-at32ap700x/clk.h
@@ -75,4 +75,7 @@ static inline unsigned long get_mci_clk_rate(void)
 }
 #endif
 
+/* Board code may need the SDRAM base clock as a compile-time constant */
+#define SDRAMC_BUS_HZ	(MAIN_CLK_RATE >> CFG_CLKDIV_HSB)
+
 #endif /* __ASM_AVR32_ARCH_CLK_H__ */
diff --git a/include/asm-avr32/sdram.h b/include/asm-avr32/sdram.h
index 5057eef..833af6e 100644
--- a/include/asm-avr32/sdram.h
+++ b/include/asm-avr32/sdram.h
@@ -26,6 +26,9 @@ struct sdram_info {
 	unsigned long phys_addr;
 	unsigned int row_bits, col_bits, bank_bits;
 	unsigned int cas, twr, trc, trp, trcd, tras, txsr;
+
+	/* SDRAM refresh period in cycles */
+	unsigned long refresh_period;
 };
 
 extern unsigned long sdram_init(const struct sdram_info *info);