summaryrefslogtreecommitdiffstats
path: root/include/asm-ppc/4xx_pcie.h
diff options
context:
space:
mode:
authorStefan Roese <sr@denx.de>2007-10-13 16:43:23 +0200
committerStefan Roese <sr@denx.de>2007-10-31 21:20:50 +0100
commitd4cb2d17946466740afeb195a57d6cb290bf4cc0 (patch)
tree81e5eee8d2e12c4714cd7ff213696b1a3b8f74ef /include/asm-ppc/4xx_pcie.h
parentfd671802b67a0ef37a06124fa2ce85f00aa22c6f (diff)
downloadbootable_bootloader_goldelico_gta04-d4cb2d17946466740afeb195a57d6cb290bf4cc0.zip
bootable_bootloader_goldelico_gta04-d4cb2d17946466740afeb195a57d6cb290bf4cc0.tar.gz
bootable_bootloader_goldelico_gta04-d4cb2d17946466740afeb195a57d6cb290bf4cc0.tar.bz2
ppc4xx: Dynamic configuration of 4xx PCIe mode as root or endpoint mode
This patch adds support for dynamic configuration of PCIe ports for the AMCC PPC4xx boards equipped with PCIe interfaces. These are the PPC440SPe boards Yucca & Katmai and the 405EX board Kilauea. This dynamic configuration is done via the "pcie_mode" environement variable. This variable can be set to "EP" or "RP" for endpoint or rootpoint mode. Multiple values can be joined via the ":" delimiter. Here an example: pcie_mode=RP:EP:EP This way, PCIe port 0 will be configured as rootpoint, PCIe port 1 and 2 as endpoint. Per default Yucca will be configured as: pcie_mode=RP:EP:EP Per default Katmai will be configured as: pcie_mode=RP:RP:REP Per default Kilauea will be configured as: pcie_mode=RP:RP Signed-off-by: Tirumala R Marri <tmarri@amcc.com> Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'include/asm-ppc/4xx_pcie.h')
-rw-r--r--include/asm-ppc/4xx_pcie.h52
1 files changed, 52 insertions, 0 deletions
diff --git a/include/asm-ppc/4xx_pcie.h b/include/asm-ppc/4xx_pcie.h
index 17ac57b..1830c6a 100644
--- a/include/asm-ppc/4xx_pcie.h
+++ b/include/asm-ppc/4xx_pcie.h
@@ -244,6 +244,9 @@
#define U64_TO_U32_LOW(val) ((u32)((val) & 0x00000000ffffffffULL))
#define U64_TO_U32_HIGH(val) ((u32)((val) >> 32))
+/*
+ * Prototypes
+ */
int ppc4xx_init_pcie(void);
int ppc4xx_init_pcie_rootport(int port);
int ppc4xx_init_pcie_endport(int port);
@@ -251,6 +254,55 @@ void ppc4xx_setup_pcie_rootpoint(struct pci_controller *hose, int port);
int ppc4xx_setup_pcie_endpoint(struct pci_controller *hose, int port);
int pcie_hose_scan(struct pci_controller *hose, int bus);
+/*
+ * Function to determine root port or endport from env variable.
+ */
+static inline int is_end_point(int port)
+{
+ static char s[10], *tk;
+
+ strcpy(s, getenv("pcie_mode"));
+ tk = strtok(s, ":");
+
+ switch (port) {
+ case 0:
+ if (tk != NULL) {
+ if (!(strcmp(tk, "ep") && strcmp(tk, "EP")))
+ return 1;
+ else
+ return 0;
+ }
+ else
+ return 0;
+
+ case 1:
+ tk = strtok(NULL, ":");
+ if (tk != NULL) {
+ if (!(strcmp(tk, "ep") && strcmp(tk, "EP")))
+ return 1;
+ else
+ return 0;
+ }
+ else
+ return 0;
+
+ case 2:
+ tk = strtok(NULL, ":");
+ if (tk != NULL)
+ tk = strtok(NULL, ":");
+ if (tk != NULL) {
+ if (!(strcmp(tk, "ep") && strcmp(tk, "EP")))
+ return 1;
+ else
+ return 0;
+ }
+ else
+ return 0;
+ }
+
+ return 0;
+}
+
static inline void mdelay(int n)
{
u32 ms = n;