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authorPoonam_Aggrwal-b10812 <b10812@freescale.com>2009-01-04 08:46:38 +0530
committerAndy Fleming <afleming@freescale.com>2009-02-16 18:06:03 -0600
commite1be0d25ecf494ae81245ca438738ba839d6329b (patch)
tree674b59945a588f6b5f663f85eb94594de6f89d94 /include/asm-ppc/fsl_ddr_sdram.h
parente0c4fac79d4d74572ddd43f75e7189cecca8d0ad (diff)
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32bit BUg fix for DDR2 on 8572
This errata fix is required for 32 bit DDR2 controller on 8572. May also be required for P10XX20XX platforms Signed-off-by: Poonam_Agarwal-b10812 <b10812@lc1106.zin33.ap.freescale.net>
Diffstat (limited to 'include/asm-ppc/fsl_ddr_sdram.h')
-rw-r--r--include/asm-ppc/fsl_ddr_sdram.h17
1 files changed, 17 insertions, 0 deletions
diff --git a/include/asm-ppc/fsl_ddr_sdram.h b/include/asm-ppc/fsl_ddr_sdram.h
index b213af3..6e3b255 100644
--- a/include/asm-ppc/fsl_ddr_sdram.h
+++ b/include/asm-ppc/fsl_ddr_sdram.h
@@ -51,6 +51,23 @@ typedef ddr3_spd_eeprom_t generic_spd_eeprom_t;
#define FSL_DDR_BANK_INTERLEAVING 0x2
#define FSL_DDR_SUPERBANK_INTERLEAVING 0x3
+/* DDR_SDRAM_CFG - DDR SDRAM Control Configuration
+ */
+#define SDRAM_CFG_MEM_EN 0x80000000
+#define SDRAM_CFG_SREN 0x40000000
+#define SDRAM_CFG_ECC_EN 0x20000000
+#define SDRAM_CFG_RD_EN 0x10000000
+#define SDRAM_CFG_SDRAM_TYPE_DDR1 0x02000000
+#define SDRAM_CFG_SDRAM_TYPE_DDR2 0x03000000
+#define SDRAM_CFG_SDRAM_TYPE_MASK 0x07000000
+#define SDRAM_CFG_SDRAM_TYPE_SHIFT 24
+#define SDRAM_CFG_DYN_PWR 0x00200000
+#define SDRAM_CFG_32_BE 0x00080000
+#define SDRAM_CFG_8_BE 0x00040000
+#define SDRAM_CFG_NCAP 0x00020000
+#define SDRAM_CFG_2T_EN 0x00008000
+#define SDRAM_CFG_BI 0x00000001
+
/* Record of register values computed */
typedef struct fsl_ddr_cfg_regs_s {
struct {