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| author | Andy Fleming <afleming@freescale.com> | 2007-08-14 01:34:21 -0500 |
|---|---|---|
| committer | Andrew Fleming-AFLEMING <afleming@freescale.com> | 2007-08-14 01:34:21 -0500 |
| commit | 61a21e980a7b9188424d04f1c265fdc5c21c7e85 (patch) | |
| tree | 9037e89c6f5ccb72b5e8b1dc150c6b0afd569531 /include/asm-ppc/processor.h | |
| parent | 7bd30fc4a6475b41d6679ae3aafc9fa505260c47 (diff) | |
| download | bootable_bootloader_goldelico_gta04-61a21e980a7b9188424d04f1c265fdc5c21c7e85.zip bootable_bootloader_goldelico_gta04-61a21e980a7b9188424d04f1c265fdc5c21c7e85.tar.gz bootable_bootloader_goldelico_gta04-61a21e980a7b9188424d04f1c265fdc5c21c7e85.tar.bz2 | |
85xx start.S cleanup and exception support
From: Ed Swarthout <Ed.Swarthout@freescale.com>
Support external interrupts from platform to eliminate system hangs.
Define CONFIG_INTERRUPTS board configure option to enable.
Enable ecm, ddr, lbc, and pci/pcie error interrupts in PIC.
Remove extra cpu initialization redundant with hardware initialization.
Whitespace cleanup.
Define and use _START_OFFSET consistent with other processors using
ppc_asm.tmpl
Move additional code from .text to boot page to make room for
exception vectors at start of image.
Handle Machine Check, External and Critical exceptions.
Fix e500 machine check error determination in traps.c
TEXT_BASE can now be 0xfffc_0000 - which cuts binary image in half.
Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
Acked-by: Andy Fleming <afleming@freescale.com>
Diffstat (limited to 'include/asm-ppc/processor.h')
| -rw-r--r-- | include/asm-ppc/processor.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h index 9be5a27..0a160e2 100644 --- a/include/asm-ppc/processor.h +++ b/include/asm-ppc/processor.h @@ -217,12 +217,14 @@ #define HID0_DPM (1<<20) #define HID0_ICE (1<<HID0_ICE_SHIFT) /* Instruction Cache Enable */ #define HID0_DCE (1<<HID0_DCE_SHIFT) /* Data Cache Enable */ +#define HID0_TBEN (1<<14) /* Time Base Enable */ #define HID0_ILOCK (1<<13) /* Instruction Cache Lock */ #define HID0_DLOCK (1<<HID0_DLOCK_SHIFT) /* Data Cache Lock */ #define HID0_ICFI (1<<11) /* Instr. Cache Flash Invalidate */ #define HID0_DCFI (1<<10) /* Data Cache Flash Invalidate */ #define HID0_DCI HID0_DCFI #define HID0_SPD (1<<9) /* Speculative disable */ +#define HID0_ENMAS7 (1<<7) /* Enable MAS7 Update for 36-bit phys */ #define HID0_SGE (1<<7) /* Store Gathering Enable */ #define HID0_SIED HID_SGE /* Serial Instr. Execution [Disable] */ #define HID0_DCFA (1<<6) /* Data Cache Flush Assist */ @@ -450,6 +452,7 @@ #define SPRN_PID1 0x279 /* Process ID Register 1 */ #define SPRN_PID2 0x27a /* Process ID Register 2 */ #define SPRN_MCSR 0x23c /* Machine Check Syndrome register */ +#define SPRN_MCAR 0x23d /* Machine Check Address register */ #ifdef CONFIG_440 #define MCSR_MCS 0x80000000 /* Machine Check Summary */ #define MCSR_IB 0x40000000 /* Instruction PLB Error */ |