Initial revision

5 files changed, 549 insertions, 0 deletions

diff --git a/post/cache.c b/post/cache.c
new file mode 100644
index 0000000..501465c
--- /dev/null
+++ b/post/cache.c
@@ -0,0 +1,81 @@
+/*
+ * (C) Copyright 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+/* Cache test
+ *
+ * This test verifies the CPU data and instruction cache using
+ * several test scenarios.
+ */
+
+#ifdef CONFIG_POST
+
+#include <post.h>
+#include <watchdog.h>
+
+#if CONFIG_POST & CFG_POST_CACHE
+
+#define CACHE_POST_SIZE	1024
+
+extern int cache_post_test1 (char *, unsigned int);
+extern int cache_post_test2 (char *, unsigned int);
+extern int cache_post_test3 (char *, unsigned int);
+extern int cache_post_test4 (char *, unsigned int);
+extern int cache_post_test5 (void);
+extern int cache_post_test6 (void);
+
+int cache_post_test (int flags)
+{
+	int ints = disable_interrupts ();
+	int res = 0;
+	static char ta[CACHE_POST_SIZE + 0xf];
+	char *testarea = (char *) (((unsigned long) ta + 0xf) & ~0xf);
+
+	WATCHDOG_RESET ();
+	if (res == 0)
+		res = cache_post_test1 (testarea, CACHE_POST_SIZE);
+	WATCHDOG_RESET ();
+	if (res == 0)
+		res = cache_post_test2 (testarea, CACHE_POST_SIZE);
+	WATCHDOG_RESET ();
+	if (res == 0)
+		res = cache_post_test3 (testarea, CACHE_POST_SIZE);
+	WATCHDOG_RESET ();
+	if (res == 0)
+		res = cache_post_test4 (testarea, CACHE_POST_SIZE);
+	WATCHDOG_RESET ();
+	if (res == 0)
+		res = cache_post_test5 ();
+	WATCHDOG_RESET ();
+	if (res == 0)
+		res = cache_post_test6 ();
+
+	WATCHDOG_RESET ();
+	if (ints)
+		enable_interrupts ();
+	return res;
+}
+
+#endif /* CONFIG_POST & CFG_POST_CACHE */
+#endif /* CONFIG_POST */
diff --git a/post/i2c.c b/post/i2c.c
new file mode 100644
index 0000000..2e38986
--- /dev/null
+++ b/post/i2c.c
@@ -0,0 +1,55 @@
+/*
+ * (C) Copyright 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#ifdef CONFIG_POST
+
+/*
+ * I2C test
+ *
+ * For verifying the I2C bus, a full I2C bus scanning is performed.
+ * If any I2C device is found, the test is considered as passed,
+ * otherwise failed.
+ */
+
+#include <post.h>
+#include <i2c.h>
+
+#if CONFIG_POST & CFG_POST_I2C
+
+int i2c_post_test (int flags)
+{
+	unsigned int i;
+	unsigned int chips = 0;
+
+	for (i = 0; i < 128; i++) {
+		if (i2c_probe (i) == 0)
+			chips++;
+	}
+
+	return chips > 0 ? 0 : -1;
+}
+
+#endif /* CONFIG_POST & CFG_POST_I2C */
+#endif /* CONFIG_POST */
diff --git a/post/rtc.c b/post/rtc.c
new file mode 100644
index 0000000..7d4f9b8
--- /dev/null
+++ b/post/rtc.c
@@ -0,0 +1,183 @@
+/*
+ * (C) Copyright 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+/*
+ * RTC test
+ *
+ * The Real Time Clock (RTC) operation is verified by this test.
+ * The following features are verified:
+ *   o) Time uniformity
+ *      This is verified by reading RTC in polling within
+ *      a short period of time.
+ *   o) Passing month boundaries
+ *      This is checked by setting RTC to a second before
+ *      a month boundary and reading it after its passing the
+ *      boundary. The test is performed for both leap- and
+ *      nonleap-years.
+ */
+
+#ifdef CONFIG_POST
+
+#include <post.h>
+#include <rtc.h>
+
+#if CONFIG_POST & CFG_POST_RTC
+
+static int rtc_post_skip (ulong * diff)
+{
+	struct rtc_time tm1;
+	struct rtc_time tm2;
+	ulong start1;
+	ulong start2;
+
+	rtc_get (&tm1);
+	start1 = get_timer (0);
+
+	while (1) {
+		rtc_get (&tm2);
+		start2 = get_timer (0);
+		if (tm1.tm_sec != tm2.tm_sec)
+			break;
+		if (start2 - start1 > 1500)
+			break;
+	}
+
+	if (tm1.tm_sec != tm2.tm_sec) {
+		*diff = start2 - start1;
+
+		return 0;
+	} else {
+		return -1;
+	}
+}
+
+static void rtc_post_restore (struct rtc_time *tm, unsigned int sec)
+{
+	time_t t = mktime (tm->tm_year, tm->tm_mon, tm->tm_mday, tm->tm_hour,
+					   tm->tm_min, tm->tm_sec) + sec;
+	struct rtc_time ntm;
+
+	to_tm (t, &ntm);
+
+	rtc_set (&ntm);
+}
+
+int rtc_post_test (int flags)
+{
+	ulong diff;
+	unsigned int i;
+	struct rtc_time svtm;
+	static unsigned int daysnl[] =
+			{ 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31 };
+	static unsigned int daysl[] =
+			{ 31, 29, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31 };
+	unsigned int ynl = 1999;
+	unsigned int yl = 2000;
+	unsigned int skipped = 0;
+
+	/* Time uniformity */
+	if (rtc_post_skip (&diff) != 0) {
+		post_log ("Timeout while waiting for a new second !\n");
+
+		return -1;
+	}
+
+	for (i = 0; i < 5; i++) {
+		if (rtc_post_skip (&diff) != 0) {
+			post_log ("Timeout while waiting for a new second !\n");
+
+			return -1;
+		}
+
+		if (diff < 950 || diff > 1050) {
+			post_log ("Invalid second duration !\n");
+
+			return -1;
+		}
+	}
+
+	/* Passing month boundaries */
+
+	if (rtc_post_skip (&diff) != 0) {
+		post_log ("Timeout while waiting for a new second !\n");
+
+		return -1;
+	}
+	rtc_get (&svtm);
+
+	for (i = 0; i < 12; i++) {
+		time_t t = mktime (ynl, i + 1, daysnl[i], 23, 59, 59);
+		struct rtc_time tm;
+
+		to_tm (t, &tm);
+		rtc_set (&tm);
+
+		skipped++;
+		if (rtc_post_skip (&diff) != 0) {
+			rtc_post_restore (&svtm, skipped);
+			post_log ("Timeout while waiting for a new second !\n");
+
+			return -1;
+		}
+
+		rtc_get (&tm);
+		if (tm.tm_mon == i + 1) {
+			rtc_post_restore (&svtm, skipped);
+			post_log ("Month %d boundary is not passed !\n", i + 1);
+
+			return -1;
+		}
+	}
+
+	for (i = 0; i < 12; i++) {
+		time_t t = mktime (yl, i + 1, daysl[i], 23, 59, 59);
+		struct rtc_time tm;
+
+		to_tm (t, &tm);
+		rtc_set (&tm);
+
+		skipped++;
+		if (rtc_post_skip (&diff) != 0) {
+			rtc_post_restore (&svtm, skipped);
+			post_log ("Timeout while waiting for a new second !\n");
+
+			return -1;
+		}
+
+		rtc_get (&tm);
+		if (tm.tm_mon == i + 1) {
+			rtc_post_restore (&svtm, skipped);
+			post_log ("Month %d boundary is not passed !\n", i + 1);
+
+			return -1;
+		}
+	}
+	rtc_post_restore (&svtm, skipped);
+
+	return 0;
+}
+
+#endif /* CONFIG_POST & CFG_POST_RTC */
+#endif /* CONFIG_POST */
diff --git a/post/spr.c b/post/spr.c
new file mode 100644
index 0000000..97f7610
--- /dev/null
+++ b/post/spr.c
@@ -0,0 +1,152 @@
+/*
+ * (C) Copyright 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+/*
+ * SPR test
+ *
+ * The test checks the contents of Special Purpose Registers (SPR) listed
+ * in the spr_test_list array below.
+ * Each SPR value is read using mfspr instruction, some bits are masked
+ * according to the table and the resulting value is compared to the
+ * corresponding table value.
+ */
+
+#ifdef CONFIG_POST
+
+#include <post.h>
+
+#if CONFIG_POST & CFG_POST_SPR
+
+static struct
+{
+    int number;
+    char * name;
+    unsigned long mask;
+    unsigned long value;
+} spr_test_list [] = {
+	/* Standard Special-Purpose Registers */
+
+        {1,	"XER",		0x00000000,	0x00000000},
+        {8,	"LR",		0x00000000,	0x00000000},
+        {9,	"CTR",		0x00000000,	0x00000000},
+        {18,	"DSISR",	0x00000000,	0x00000000},
+        {19,	"DAR",		0x00000000,	0x00000000},
+        {22,	"DEC",		0x00000000,	0x00000000},
+        {26,	"SRR0",		0x00000000,	0x00000000},
+        {27,	"SRR1",		0x00000000,	0x00000000},
+        {272,	"SPRG0",	0x00000000,	0x00000000},
+        {273,	"SPRG1",	0x00000000,	0x00000000},
+        {274,	"SPRG2",	0x00000000,	0x00000000},
+        {275,	"SPRG3",	0x00000000,	0x00000000},
+        {287,	"PVR",		0xFFFF0000,	0x00500000},
+
+	/* Additional Special-Purpose Registers */
+
+        {144,	"CMPA",		0x00000000,	0x00000000},
+        {145,	"CMPB",		0x00000000,	0x00000000},
+        {146,	"CMPC",		0x00000000,	0x00000000},
+        {147,	"CMPD",		0x00000000,	0x00000000},
+        {148,	"ICR",		0xFFFFFFFF,	0x00000000},
+        {149,	"DER",		0x00000000,	0x00000000},
+        {150,	"COUNTA",	0xFFFFFFFF,	0x00000000},
+        {151,	"COUNTB",	0xFFFFFFFF,	0x00000000},
+        {152,	"CMPE",		0x00000000,	0x00000000},
+        {153,	"CMPF",		0x00000000,	0x00000000},
+        {154,	"CMPG",		0x00000000,	0x00000000},
+        {155,	"CMPH",		0x00000000,	0x00000000},
+        {156,	"LCTRL1",	0xFFFFFFFF,	0x00000000},
+        {157,	"LCTRL2",	0xFFFFFFFF,	0x00000000},
+        {158,	"ICTRL",	0xFFFFFFFF,	0x00000007},
+        {159,	"BAR",		0x00000000,	0x00000000},
+        {630,	"DPDR",		0x00000000,	0x00000000},
+        {631,	"DPIR",		0x00000000,	0x00000000},
+        {638,	"IMMR",		0xFFFF0000,	CFG_IMMR  },
+        {560,	"IC_CST",	0x8E380000,	0x00000000},
+        {561,	"IC_ADR",	0x00000000,	0x00000000},
+        {562,	"IC_DAT",	0x00000000,	0x00000000},
+        {568,	"DC_CST",	0xEF380000,	0x00000000},
+        {569,	"DC_ADR",	0x00000000,	0x00000000},
+        {570,	"DC_DAT",	0x00000000,	0x00000000},
+        {784,	"MI_CTR",	0xFFFFFFFF,	0x00000000},
+        {786,	"MI_AP",	0x00000000,	0x00000000},
+        {787,	"MI_EPN",	0x00000000,	0x00000000},
+        {789,	"MI_TWC",	0xFFFFFE02,	0x00000000},
+        {790,	"MI_RPN",	0x00000000,	0x00000000},
+        {816,	"MI_DBCAM",	0x00000000,	0x00000000},
+        {817,	"MI_DBRAM0",	0x00000000,	0x00000000},
+        {818,	"MI_DBRAM1",	0x00000000,	0x00000000},
+        {792,	"MD_CTR",	0xFFFFFFFF,	0x04000000},
+        {793,	"M_CASID",	0xFFFFFFF0,	0x00000000},
+        {794,	"MD_AP",	0x00000000,	0x00000000},
+        {795,	"MD_EPN",	0x00000000,	0x00000000},
+        {796,	"M_TWB",	0x00000003,	0x00000000},
+        {797,	"MD_TWC",	0x00000003,	0x00000000},
+        {798,	"MD_RPN",	0x00000000,	0x00000000},
+        {799,	"M_TW",		0x00000000,	0x00000000},
+        {824,	"MD_DBCAM",	0x00000000,	0x00000000},
+        {825,	"MD_DBRAM0",	0x00000000,	0x00000000},
+        {826,	"MD_DBRAM1",	0x00000000,	0x00000000},
+};
+
+static int spr_test_list_size =
+		sizeof (spr_test_list) / sizeof (spr_test_list[0]);
+
+int spr_post_test (int flags)
+{
+	int ret = 0;
+	int ic = icache_status ();
+	int i;
+
+	unsigned long code[] = {
+		0x7c6002a6,				/* mfspr r3,SPR */
+		0x4e800020				/* blr          */
+	};
+	unsigned long (*get_spr) (void) = (void *) code;
+
+	if (ic)
+		icache_disable ();
+
+	for (i = 0; i < spr_test_list_size; i++) {
+		int num = spr_test_list[i].number;
+
+		/* mfspr r3,num */
+		code[0] = 0x7c6002a6 | ((num & 0x1F) << 16) | ((num & 0x3E0) << 6);
+
+		if ((get_spr () & spr_test_list[i].mask) !=
+			(spr_test_list[i].value & spr_test_list[i].mask)) {
+			post_log ("The value of %s special register "
+				  "is incorrect: 0x%08X\n",
+					spr_test_list[i].name, get_spr ());
+			ret = -1;
+		}
+	}
+
+	if (ic)
+		icache_enable ();
+
+	return ret;
+}
+#endif /* CONFIG_POST & CFG_POST_SPR */
+#endif /* CONFIG_POST */
diff --git a/post/watchdog.c b/post/watchdog.c
new file mode 100644
index 0000000..0cdfbf0
--- /dev/null
+++ b/post/watchdog.c
@@ -0,0 +1,78 @@
+/*
+ * (C) Copyright 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+/*
+ * Watchdog test
+ *
+ * The test verifies the watchdog timer operation.
+ * On the first iteration, the test routine disables interrupts and
+ * makes a 10-second delay. If the system does not reboot during this delay,
+ * the watchdog timer is not operational and the test fails. If the system
+ * reboots, on the second iteration the test routine reports a success.
+ */
+
+#ifdef CONFIG_POST
+
+#include <post.h>
+#include <watchdog.h>
+
+#if CONFIG_POST & CFG_POST_WATCHDOG
+
+static ulong gettbl (void)
+{
+	ulong r;
+
+  asm ("mftbl %0":"=r" (r));
+
+	return r;
+}
+
+int watchdog_post_test (int flags)
+{
+	if (flags & POST_REBOOT) {
+		/* Test passed */
+
+		return 0;
+	} else {
+		/* 10-second delay */
+		int ints = disable_interrupts ();
+		ulong base = gettbl ();
+		ulong clk = get_tbclk ();
+
+		while ((gettbl () - base) / 10 < clk);
+
+		if (ints)
+			enable_interrupts ();
+
+                /*
+                 * If we have reached this point, the watchdog timer
+		 * does not work
+		 */
+		return -1;
+	}
+}
+
+#endif /* CONFIG_POST & CFG_POST_WATCHDOG */
+#endif /* CONFIG_POST */