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author | H. Nikolaus Schaller <hns@goldelico.com> | 2012-03-26 20:55:28 +0200 |
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committer | H. Nikolaus Schaller <hns@goldelico.com> | 2012-03-26 20:55:28 +0200 |
commit | 92988a21ad4c4c9504295ccb580c9f806134471b (patch) | |
tree | 5effc9f14170112450de05c67dafbe8d5034d595 /u-boot/board/assabet | |
parent | ca2b506783b676c95762c54ea24dcfdaae1947c9 (diff) | |
download | bootable_bootloader_goldelico_gta04-92988a21ad4c4c9504295ccb580c9f806134471b.zip bootable_bootloader_goldelico_gta04-92988a21ad4c4c9504295ccb580c9f806134471b.tar.gz bootable_bootloader_goldelico_gta04-92988a21ad4c4c9504295ccb580c9f806134471b.tar.bz2 |
added boot script files to repository
Diffstat (limited to 'u-boot/board/assabet')
-rw-r--r-- | u-boot/board/assabet/Makefile | 53 | ||||
-rw-r--r-- | u-boot/board/assabet/assabet.c | 131 | ||||
-rw-r--r-- | u-boot/board/assabet/config.mk | 7 | ||||
-rw-r--r-- | u-boot/board/assabet/setup.S | 136 |
4 files changed, 327 insertions, 0 deletions
diff --git a/u-boot/board/assabet/Makefile b/u-boot/board/assabet/Makefile new file mode 100644 index 0000000..b3cf4aa --- /dev/null +++ b/u-boot/board/assabet/Makefile @@ -0,0 +1,53 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# 2004 (c) MontaVista Software, Inc. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS := assabet.o +SOBJS := setup.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS) $(SOBJS)) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/u-boot/board/assabet/assabet.c b/u-boot/board/assabet/assabet.c new file mode 100644 index 0000000..753c8d2 --- /dev/null +++ b/u-boot/board/assabet/assabet.c @@ -0,0 +1,131 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Marius Groeger <mgroeger@sysgo.de> + * + * 2004 (c) MontaVista Software, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <netdev.h> +#include <SA-1100.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* ------------------------------------------------------------------------- */ + +/* + * Board dependent initialisation + */ + +#define ECOR 0x8000 +#define ECOR_RESET 0x80 +#define ECOR_LEVEL_IRQ 0x40 +#define ECOR_WR_ATTRIB 0x04 +#define ECOR_ENABLE 0x01 + +#define ECSR 0x8002 +#define ECSR_IOIS8 0x20 +#define ECSR_PWRDWN 0x04 +#define ECSR_INT 0x02 +#define SMC_IO_SHIFT 2 +#define NCR_0 (*((volatile u_char *)(0x100000a0))) +#define NCR_ENET_OSC_EN (1<<3) + +static inline u8 +readb(volatile u8 * p) +{ + return *p; +} + +static inline void +writeb(u8 v, volatile u8 * p) +{ + *p = v; +} + +static void +smc_init(void) +{ + u8 ecor; + u8 ecsr; + volatile u8 *addr = (volatile u8 *)(0x18000000 + (1 << 25)); + + NCR_0 |= NCR_ENET_OSC_EN; + udelay(100); + + ecor = readb(addr + (ECOR << SMC_IO_SHIFT)) & ~ECOR_RESET; + writeb(ecor | ECOR_RESET, addr + (ECOR << SMC_IO_SHIFT)); + udelay(100); + + /* + * The device will ignore all writes to the enable bit while + * reset is asserted, even if the reset bit is cleared in the + * same write. Must clear reset first, then enable the device. + */ + writeb(ecor, addr + (ECOR << SMC_IO_SHIFT)); + writeb(ecor | ECOR_ENABLE, addr + (ECOR << SMC_IO_SHIFT)); + + /* + * Set the appropriate byte/word mode. + */ + ecsr = readb(addr + (ECSR << SMC_IO_SHIFT)) & ~ECSR_IOIS8; + ecsr |= ECSR_IOIS8; + writeb(ecsr, addr + (ECSR << SMC_IO_SHIFT)); + udelay(100); +} + +static void +neponset_init(void) +{ + smc_init(); +} + +int +board_init(void) +{ + gd->bd->bi_arch_number = MACH_TYPE_ASSABET; + gd->bd->bi_boot_params = 0xc0000100; + + neponset_init(); + + return 0; +} + +int +dram_init(void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + + return (0); +} + +#ifdef CONFIG_CMD_NET +int board_eth_init(bd_t *bis) +{ + int rc = 0; +#ifdef CONFIG_LAN91C96 + rc = lan91c96_initialize(0, CONFIG_LAN91C96_BASE); +#endif + return rc; +} +#endif diff --git a/u-boot/board/assabet/config.mk b/u-boot/board/assabet/config.mk new file mode 100644 index 0000000..d9866a0 --- /dev/null +++ b/u-boot/board/assabet/config.mk @@ -0,0 +1,7 @@ +# +# SA-1110 based Intel Assabet board +# +# The Intel Assabet 1 bank of 32 MiB SDRAM +# + +CONFIG_SYS_TEXT_BASE = 0xc1f00000 diff --git a/u-boot/board/assabet/setup.S b/u-boot/board/assabet/setup.S new file mode 100644 index 0000000..56ea0dd --- /dev/null +++ b/u-boot/board/assabet/setup.S @@ -0,0 +1,136 @@ +/* + * Memory Setup stuff - taken from blob memsetup.S + * + * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and + * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl) + * 2004 (c) MontaVista Software, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#include "config.h" +#include "version.h" + + +/*----------------------------------------------------------------------- + * Board defines: + */ + +#define MDCNFG 0x00 +#define MDCAS00 0x04 +#define MDCAS01 0x08 +#define MDCAS02 0x0C +#define MSC0 0x10 +#define MSC1 0x14 +#define MECR 0x18 +#define MDREFR 0x1C +#define MDCAS20 0x20 +#define MDCAS21 0x24 +#define MDCAS22 0x28 +#define MSC2 0x2C +#define SMCNFG 0x30 + +#define ASSABET_BCR (0x12000000) +#define ASSABET_BCR_DB1110 (0x00a07490 | (0<<16) | (0<<17)) +#define ASSABET_SCR_nNEPONSET (1 << 9) +#define NEPONSET_LEDS (0x10000010) + + +/*----------------------------------------------------------------------- + * Setup parameters for the board: + */ + + +MEM_BASE: .long 0xa0000000 +MEM_START: .long 0xc0000000 + +mdcnfg: .long 0x72547254 +mdcas00: .long 0xaaaaaa7f +mdcas01: .long 0xaaaaaaaa +mdcas02: .long 0xaaaaaaaa +msc0: .long 0x4b384370 +msc1: .long 0x22212419 +mecr: .long 0x994a994a +mdrefr: .long 0x04340327 +mdcas20: .long 0xaaaaaa7f +mdcas21: .long 0xaaaaaaaa +mdcas22: .long 0xaaaaaaaa +msc2: .long 0x42196669 +smcnfg: .long 0x00000000 + +BCR: .long ASSABET_BCR +BCR_DB1110: .long ASSABET_BCR_DB1110 +LEDS: .long NEPONSET_LEDS + + + .globl lowlevel_init +lowlevel_init: + + /* Setting up the memory and stuff */ + + ldr r0, MEM_BASE + ldr r1, mdcas00 + str r1, [r0, #MDCAS00] + ldr r1, mdcas01 + str r1, [r0, #MDCAS01] + ldr r1, mdcas02 + str r1, [r0, #MDCAS02] + ldr r1, mdcas20 + str r1, [r0, #MDCAS20] + ldr r1, mdcas21 + str r1, [r0, #MDCAS21] + ldr r1, mdcas22 + str r1, [r0, #MDCAS22] + ldr r1, mdrefr + str r1, [r0, #MDREFR] + ldr r1, mecr + str r1, [r0, #MECR] + ldr r1, msc0 + str r1, [r0, #MSC0] + ldr r1, msc1 + str r1, [r0, #MSC1] + ldr r1, msc2 + str r1, [r0, #MSC2] + ldr r1, smcnfg + str r1, [r0, #SMCNFG] + + ldr r1, mdcnfg + str r1, [r0, #MDCNFG] + + /* Load something to activate bank */ + ldr r2, MEM_START +.rept 8 + ldr r3, [r2] +.endr + + /* Enable SDRAM */ + orr r1, r1, #0x00000001 + str r1, [r0, #MDCNFG] + + ldr r1, BCR + ldr r2, BCR_DB1110 + str r2, [r1] + + ldr r1, LEDS + mov r0, #0x3 + str r0, [r1] + + /* All done... */ + mov pc, lr |