added boot script files to repository

48 files changed, 7208 insertions, 0 deletions

diff --git a/u-boot/board/goldelico/beagle-expander/Makefile b/u-boot/board/goldelico/beagle-expander/Makefile
new file mode 100644
index 0000000..f75a580
--- /dev/null
+++ b/u-boot/board/goldelico/beagle-expander/Makefile
@@ -0,0 +1,49 @@
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= beagleexpander.o ../gta04b2/COM37H3M05DTC.o ../gta04b2/trf7960.o ../gta04/backlight.o ../gta04/status.o ../gta04/tsc2007.o ../gta04/dssfb.o ../gta04/gps.o ../gta04/shutdown.o ../gta04/systest.o ../gta04/commands.o
+
+SRCS	:= $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
\ No newline at end of file
diff --git a/u-boot/board/goldelico/beagle-expander/beagleexpander.c b/u-boot/board/goldelico/beagle-expander/beagleexpander.c
new file mode 100644
index 0000000..bd58b1f
--- /dev/null
+++ b/u-boot/board/goldelico/beagle-expander/beagleexpander.c
@@ -0,0 +1,24 @@
+#include <common.h>
+#include <twl4030.h>
+#include <asm/io.h>
+#include <asm/arch/mmc_host_def.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/gpio.h>
+#include <asm/mach-types.h>
+#include "../../ti/beagle/beagle.h"
+#include "beagleexpander.h"
+
+// make us initialize using both pinmux sets
+
+void muxinit(void)
+{
+	MUX_BEAGLE();
+	MUX_BEAGLE_EXPANDER();
+}
+
+#undef MUX_BEAGLE
+#define MUX_BEAGLE() muxinit()
+
+// take the original beagle.c code
+#include "../../ti/beagle/beagle.c"
diff --git a/u-boot/board/goldelico/beagle-expander/beagleexpander.h b/u-boot/board/goldelico/beagle-expander/beagleexpander.h
new file mode 100644
index 0000000..049d999
--- /dev/null
+++ b/u-boot/board/goldelico/beagle-expander/beagleexpander.h
@@ -0,0 +1,30 @@
+// all pins on BB expansion connector
+
+// GPIO -> BB-Pin -> Expander function
+
+#define MUX_BEAGLE_EXPANDER() \
+MUX_VAL(CP(MMC2_CLK),		(IEN  | PTD | EN  | M1)) /*GPIO_130 -> MCSPI3-CLK -> TRF*/\
+MUX_VAL(CP(MMC2_CLK),		(IDIS | PTD | EN  | M4)) /*GPIO_130 -> MCSPI3-CLK -> TRF*/\
+MUX_VAL(CP(MMC2_CMD),		(IDIS | PTD | EN  | M1)) /*GPIO_131 -> MCSPI3-SIMO -> TRF*/\
+MUX_VAL(CP(MMC2_CMD),		(IDIS | PTD | EN  | M4)) /*GPIO_131 -> MCSPI3-SIMO -> TRF*/\
+MUX_VAL(CP(MMC2_DAT0),		(IEN  | PTU | EN  | M1)) /*GPIO_132 -> MCSPI3-SOMI -> TRF*/\
+MUX_VAL(CP(MMC2_DAT0),		(IEN  | PTU | EN  | M4)) /*GPIO_132 -> MCSPI3-SOMI -> TRF*/\
+MUX_VAL(CP(MMC2_DAT1),		(IEN  | PTU | EN  | M4)) /*GPIO_133 -> UART3-RX (software)*/\
+MUX_VAL(CP(MMC2_DAT2),		(IDIS | PTU | EN  | M4)) /*GPIO_134 -> UART3-TX (software)*/\
+MUX_VAL(CP(MMC2_DAT3),		(IDIS | PTU | EN  | M1)) /*GPIO_135 -> MCSPI3-CS0*/\
+MUX_VAL(CP(MMC2_DAT4),		(IEN  | PTD | EN  | M4)) /*GPIO_136 - AUX */\
+MUX_VAL(CP(MMC2_DAT5),		(IEN  | PTU | EN  | M4)) /*GPIO_137 - POWER */\
+MUX_VAL(CP(MMC2_DAT6),		(IDIS | PTU | EN  | M4)) /*GPIO_138 - UART3-RTS (software) */\
+MUX_VAL(CP(MMC2_DAT7),		(IEN  | PTU | EN  | M4)) /*GPIO_139 - UART3-CTS (software) */\
+MUX_VAL(CP(UART2_RX),		(IEN  | PTU | EN  | M4)) /*GPIO_143 - UART2-RX */\
+MUX_VAL(CP(UART2_CTS),		(IDIS | PTU | EN  | M4)) /*GPIO_144 - UART2-CTS */\
+MUX_VAL(CP(UART2_RTS),		(IDIS | PTU | EN  | M4)) /*GPIO_145 - UART2-RTS */\
+MUX_VAL(CP(UART2_TX),		(IEN  | PTU | EN  | M4)) /*GPIO_146 - UART2-TX */\
+MUX_VAL(CP(MCBSP1_CLKR),	(IEN  | PTD | EN  | M4)) /*GPIO_156 - KEYIRQ -> TRF IRQ */\
+MUX_VAL(CP(MCBSP1_FSR),		(IEN  | PTU | EN  | M4)) /*GPIO_157 - PENIRQ */\
+MUX_VAL(CP(MCBSP1_DX),		(IDIS | PTD | EN  | M4)) /*GPIO_158 - Display STBY */\
+MUX_VAL(CP(MCBSP1_DR),		(IDIS | PTD | EN  | M4)) /*GPIO_159 - McBSP1-DR -> TRF EN2 */\
+MUX_VAL(CP(MCBSP_CLKS),		(IEN  | PTU | DIS | M0)) /*McBSP_CLKS */\
+MUX_VAL(CP(MCBSP1_FSX),		(IDIS | PTD | EN  | M4)) /*GPIO_161 - McBSP1-FSX -> TRF EN */\
+MUX_VAL(CP(MCBSP1_CLKX),	(IDIS | PTD | EN  | M4)) /*GPIO_162 - McBSP1-CLKX -> UART3 Powerdown */
+
diff --git a/u-boot/board/goldelico/beagle-expander/config.mk b/u-boot/board/goldelico/beagle-expander/config.mk
new file mode 100644
index 0000000..cf055db
--- /dev/null
+++ b/u-boot/board/goldelico/beagle-expander/config.mk
@@ -0,0 +1,33 @@
+#
+# (C) Copyright 2006
+# Texas Instruments, <www.ti.com>
+#
+# Beagle Board uses OMAP3 (ARM-CortexA8) cpu
+# see http://www.ti.com/ for more information on Texas Instruments
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+# Physical Address:
+# 8000'0000 (bank0)
+# A000/0000 (bank1)
+# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
+# (mem base + reserved)
+
+# For use with external or internal boots.
+CONFIG_SYS_TEXT_BASE = 0x80008000
diff --git a/u-boot/board/goldelico/beagle-hybrid/Makefile b/u-boot/board/goldelico/beagle-hybrid/Makefile
new file mode 100644
index 0000000..d249281
--- /dev/null
+++ b/u-boot/board/goldelico/beagle-hybrid/Makefile
@@ -0,0 +1,49 @@
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= beaglehyb.o ../gta04/TD028TTEC1.o ../gta04/jbt6k74.o ../gta04/backlight.o ../gta04/status.o ../gta04/tsc2007.o ../gta04/dssfb.o ../gta04/gps.o ../gta04/shutdown.o ../gta04/systest.o ../gta04/commands.o
+
+SRCS	:= $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
\ No newline at end of file
diff --git a/u-boot/board/goldelico/beagle-hybrid/beaglehyb.c b/u-boot/board/goldelico/beagle-hybrid/beaglehyb.c
new file mode 100644
index 0000000..7fbe8d2
--- /dev/null
+++ b/u-boot/board/goldelico/beagle-hybrid/beaglehyb.c
@@ -0,0 +1,24 @@
+#include <common.h>
+#include <twl4030.h>
+#include <asm/io.h>
+#include <asm/arch/mmc_host_def.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/gpio.h>
+#include <asm/mach-types.h>
+#include "../../ti/beagle/beagle.h"
+#include "beaglehyb.h"
+
+// make us initialize using both pinmux sets
+
+void muxinit(void)
+{
+	MUX_BEAGLE();
+	MUX_BEAGLE_HYBRID();
+}
+
+#undef MUX_BEAGLE
+#define MUX_BEAGLE() muxinit()
+
+// take the original beagle.c code
+#include "../../ti/beagle/beagle.c"
diff --git a/u-boot/board/goldelico/beagle-hybrid/beaglehyb.h b/u-boot/board/goldelico/beagle-hybrid/beaglehyb.h
new file mode 100644
index 0000000..71470f8
--- /dev/null
+++ b/u-boot/board/goldelico/beagle-hybrid/beaglehyb.h
@@ -0,0 +1,18 @@
+#define MUX_BEAGLE_HYBRID() \
+MUX_VAL(CP(MMC2_CLK),		(IEN  | PTU | EN  | M0)) /*GPIO_130 -> MMC2_CLK*/\
+MUX_VAL(CP(MMC2_CMD),		(IEN  | PTU | EN  | M0)) /*GPIO_131 -> MMC2_CMD*/\
+MUX_VAL(CP(MMC2_DAT0),		(IEN  | PTU | EN  | M0)) /*GPIO_132 -> MMC2_DAT0*/\
+MUX_VAL(CP(MMC2_DAT1),		(IEN  | PTU | EN  | M0)) /*GPIO_133 -> MMC2_DAT1*/\
+MUX_VAL(CP(MMC2_DAT2),		(IEN  | PTU | EN  | M0)) /*GPIO_134 -> MMC2_DAT2*/\
+MUX_VAL(CP(MMC2_DAT3),		(IEN  | PTU | EN  | M0)) /*GPIO_135 -> MMC2_DAT3*/\
+MUX_VAL(CP(MMC2_DAT4),		(IEN  | PTU | EN  | M4)) /*GPIO_136 - AUX */\
+MUX_VAL(CP(MMC2_DAT5),		(IEN  | PTU | EN  | M4)) /*GPIO_137 - POWER */\
+MUX_VAL(CP(MMC2_DAT6),		(IEN  | PTU | DIS  | M4)) /*GPIO_138 - EXT-ANT */\
+MUX_VAL(CP(MMC2_DAT7),		(IEN  | PTU | EN  | M4)) /*GPIO_139 - RS232 EXT */\
+MUX_VAL(CP(MCBSP1_CLKR),	(IDIS | PTD | DIS | M4)) /*GPIO_156 - GPS ON(0)/OFF(1)*/\
+MUX_VAL(CP(MCBSP1_FSR),		(IEN  | PTU | EN  | M4)) /*GPIO_157 - PENIRQ */\
+MUX_VAL(CP(MCBSP1_DX),		(IDIS | PTD | EN  | M4)) /*GPIO_158 - DOUT */\
+MUX_VAL(CP(MCBSP1_DR),		(IEN  | PTU | DIS | M4)) /*GPIO_159 - DIN - pulled up */\
+MUX_VAL(CP(MCBSP_CLKS),		(IEN  | PTU | DIS | M0)) /*McBSP_CLKS*/\
+MUX_VAL(CP(MCBSP1_FSX),		(IDIS | PTU | EN  | M4)) /*GPIO_161 - CS */\
+MUX_VAL(CP(MCBSP1_CLKX),	(IDIS | PTD | EN  | M4)) /*GPIO_162 - SCL */
diff --git a/u-boot/board/goldelico/beagle-hybrid/config.mk b/u-boot/board/goldelico/beagle-hybrid/config.mk
new file mode 100644
index 0000000..cf055db
--- /dev/null
+++ b/u-boot/board/goldelico/beagle-hybrid/config.mk
@@ -0,0 +1,33 @@
+#
+# (C) Copyright 2006
+# Texas Instruments, <www.ti.com>
+#
+# Beagle Board uses OMAP3 (ARM-CortexA8) cpu
+# see http://www.ti.com/ for more information on Texas Instruments
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+# Physical Address:
+# 8000'0000 (bank0)
+# A000/0000 (bank1)
+# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
+# (mem base + reserved)
+
+# For use with external or internal boots.
+CONFIG_SYS_TEXT_BASE = 0x80008000
diff --git a/u-boot/board/goldelico/gta04/COMMANDS b/u-boot/board/goldelico/gta04/COMMANDS
new file mode 100644
index 0000000..01fa68e
--- /dev/null
+++ b/u-boot/board/goldelico/gta04/COMMANDS
@@ -0,0 +1,22 @@
+new uBoot commands:
+
+status in[it]		setup GPIOs
+status ge[t]		get button status
+status se[t] hh		set LEDs to lower 4 bit
+status se[t]		increment last state, i.e. make LEDs count
+status mi[rror]		read button status and mirror to LEDs until a key is pressed
+status bl[ink]		blink LEDs
+
+lcm in[it]			initialize subsystem (DSS, GPIOs etc.)
+lcm ba[cklight] dd	set backlight level (0..255)
+lcm po[wer] dd		set power level (0..2)
+lcm on				set lcm on
+lcm of[f]			set lcm off
+
+gps on | of[f]		control GPS receiver (and initialize UART)
+gps re[ad]			read GPS NMEA from UART until a key is pressed
+
+tsc init			initialize/enable TSC2007 through I2C2
+tsc get				read current ADC values (incl. internal temp and AUX/photosensor)
+tsc lo[op]			read x/y coordinates
+tsc ch[oose]		somehow allow to define receptive fields and use the result to select different boot options
diff --git a/u-boot/board/goldelico/gta04/Makefile b/u-boot/board/goldelico/gta04/Makefile
new file mode 100644
index 0000000..5afd6df
--- /dev/null
+++ b/u-boot/board/goldelico/gta04/Makefile
@@ -0,0 +1,49 @@
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= gta04.o ../gta04/TD028TTEC1.o ../gta04/jbt6k74.o ../gta04/backlight.o ../gta04/status.o ../gta04/tsc2007.o ../gta04/dssfb.o ../gta04/gps.o ../gta04/shutdown.o  ../gta04/systest.o ../gta04/commands.o ../gta04/i2c1-fix.o ../gta04/ulpi-phy.o  ../gta04/twl4030-additions.o
+
+SRCS	:= $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
\ No newline at end of file
diff --git a/u-boot/board/goldelico/gta04/TD028TTEC1.c b/u-boot/board/goldelico/gta04/TD028TTEC1.c
new file mode 100644
index 0000000..94667a3
--- /dev/null
+++ b/u-boot/board/goldelico/gta04/TD028TTEC1.c
@@ -0,0 +1,260 @@
+/* u-boot driver for the tpo TD028TTEC1 LCM
+ *
+ * Copyright (C) 2006-2007 by OpenMoko, Inc.
+ * Author: Harald Welte <laforge@openmoko.org>
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+/* modified by hns@goldelico.com
+ * now is just a SPI/GPIO driver to the serial interface of the TD028TTEC1
+ 
+ *** should all this code be moved to drivers/misc or drivers/video ?
+ 
+ */
+
+#include <common.h>
+#include <asm/errno.h>
+#include <asm/io.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/gpio.h>
+#include <asm/mach-types.h>
+#include "TD028TTEC1.h"
+
+#ifdef CONFIG_OMAP3_BEAGLE
+
+#ifdef CONFIG_OMAP3_GTA04
+
+#define GPIO_CS		19
+#define GPIO_SCL	12
+#define GPIO_DIN	18
+#define GPIO_DOUT	20
+
+#else	/* Beagle Hybrid */
+
+#define GPIO_CS		161
+#define GPIO_SCL	162
+#define GPIO_DIN	159
+#define GPIO_DOUT	158
+
+#endif
+
+#define SPI_READ()      (omap_get_gpio_datain(GPIO_DIN))
+#define SPI_CS(bit) 	(omap_set_gpio_dataout(GPIO_CS, bit))
+#define SPI_SDA(bit)    (omap_set_gpio_dataout(GPIO_DOUT, bit))
+#define SPI_SCL(bit)    (omap_set_gpio_dataout(GPIO_SCL, bit))
+
+#elif !defined(CONFIG_GTA02_REVISION)	/* GTA01 */
+
+#define GTA01_SCLK	(1 << 7) 	/* GPG7 */
+#define GTA01_MOSI	(1 << 6)	/* GPG6 */
+#define GTA01_MISO	(1 << 5)	/* GPG5 */
+#define GTA01_CS	(1 << 3)	/* GPG3 */
+
+#define SPI_READ        ((immr->GPGDAT & GTA01_MISO) != 0)
+
+#define SPI_CS(bit) 	if (bit) gpio->GPGDAT |= GTA01_CS; \
+			else gpio->GPGDAT &= ~GTA01_CS
+
+#define SPI_SDA(bit)    if (bit) gpio->GPGDAT |=  GTA01_MOSI; \
+			else    gpio->GPGDAT &= ~GTA01_MOSI
+
+#define SPI_SCL(bit)    if (bit) gpio->GPGDAT |=  GTA01_SCLK; \
+			else    gpio->GPGDAT &= ~GTA01_SCLK
+
+#else /* GTA02 */
+
+extern void smedia3362_spi_cs(int);
+extern void smedia3362_spi_sda(int);
+extern void smedia3362_spi_scl(int);
+extern void smedia3362_lcm_reset(int);
+
+#define SPI_READ	$not$implemented$
+#define SPI_CS(b)   smedia3362_spi_cs(b)
+#define SPI_SDA(b)  smedia3362_spi_sda(b)
+#define SPI_SCL(b)  smedia3362_spi_scl(b)
+   
+#endif
+
+
+/* 150uS minimum clock cycle, we have two of this plus our other
+ * instructions */
+
+#define SPI_DELAY()	udelay(150)
+
+static int jbt_spi_xfer(int wordnum, int bitlen, u_int16_t *dout)
+{
+#if !defined(_BEAGLE_)
+	S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
+#endif
+	u_int16_t tmpdout = 0;
+	int   i, j;
+
+//	DEBUGP("spi_xfer: dout %08X wordnum %u bitlen %d\n",
+//		*(uint *)dout, wordnum, bitlen);
+
+	SPI_CS(0);
+
+	for (i = 0; i < wordnum; i ++) {
+		tmpdout = dout[i];
+
+		for (j = 0; j < bitlen; j++) {
+			SPI_SCL(0);
+			if (tmpdout & (1 << (bitlen-1))) {
+				SPI_SDA(1);
+//				DEBUGPC("1");
+//				VERIFY(1);
+			} else {
+				SPI_SDA(0);
+//				DEBUGPC("0");
+//				VERIFY(0);
+			}
+			SPI_DELAY();
+			SPI_SCL(1);
+			SPI_DELAY();
+			tmpdout <<= 1;
+		}
+//		DEBUGPC(" ");
+	}
+//	DEBUGPC("\n");
+
+	SPI_CS(1);
+
+	return 0;
+}
+
+#define JBT_COMMAND	0x000
+#define JBT_DATA	0x100
+
+int jbt_reg_write_nodata(struct jbt_info *jbt, u_int8_t reg)
+{
+	int rc;
+	
+	jbt->tx_buf[0] = JBT_COMMAND | reg;
+	
+	rc = jbt_spi_xfer(1, 9, jbt->tx_buf);
+	
+	return rc;
+}
+
+
+int jbt_reg_write(struct jbt_info *jbt, u_int8_t reg, u_int8_t data)
+{
+	int rc;
+	
+	jbt->tx_buf[0] = JBT_COMMAND | reg;
+	jbt->tx_buf[1] = JBT_DATA | data;
+	
+	rc = jbt_spi_xfer(2, 9, jbt->tx_buf);
+	
+	return rc;
+}
+
+int jbt_reg_write16(struct jbt_info *jbt, u_int8_t reg, u_int16_t data)
+{
+	int rc;
+	
+	jbt->tx_buf[0] = JBT_COMMAND | reg;
+	jbt->tx_buf[1] = JBT_DATA | (data >> 8);
+	jbt->tx_buf[2] = JBT_DATA | (data & 0xff);
+	
+	rc = jbt_spi_xfer(3, 9, jbt->tx_buf);
+	
+	return rc;
+}
+
+int jbt_check(void)
+{ // check if we have connectivity
+#if defined(_BEAGLE_)
+	int err;
+	int i;
+	int failed=0;
+	int cnt0 = 0;
+	int cnt1 = 0;
+
+#if 0
+	printf("jbt_reg_init()\n");
+#endif
+	err = omap_request_gpio(GPIO_CS);
+	SPI_CS(1);	// unselect
+	err |= omap_request_gpio(GPIO_SCL);
+	SPI_SCL(1);	// default
+	err |= omap_request_gpio(GPIO_DOUT);
+	SPI_SDA(0);
+	err |= omap_request_gpio(GPIO_DIN);
+	if(err)
+		{
+		printf("jbt_reg_init() - could not get GPIOs\n");
+		return 1;
+		}
+#if 1		// should have already been done by MUX settings!
+	omap_set_gpio_direction(GPIO_CS, 0);	// output
+	omap_set_gpio_direction(GPIO_SCL, 0);	// output
+	omap_set_gpio_direction(GPIO_DOUT, 0);	// output
+	omap_set_gpio_direction(GPIO_DIN, 1);	// input (for reading back)
+#endif
+	
+	//	omap_free_gpio(GPIO_DIN);
+	//	omap_free_gpio(GPIO_DOUT);
+	//	omap_free_gpio(GPIO_CS);
+	//	omap_free_gpio(GPIO_SCL);
+	
+	for(i=0; i<16; i++)
+		{ // check for connection between GPIO158 -> GPIO159; since we have 10 kOhm pse. make sure that the PUP/PDN is disabled on DIN in the MUX config!
+			int bit=i&1;
+			SPI_SDA(bit);	// write bit
+			SPI_DELAY();
+#if 0
+			printf("bit: %d out: %d in: %d (%d)\n", bit, omap_get_gpio_datain(GPIO_DOUT), omap_get_gpio_datain(GPIO_DIN), SPI_READ());
+#endif
+			if(SPI_READ() != bit)	// did not read back
+				failed++;
+			if(SPI_READ())
+				cnt1++;
+			else
+				cnt0++;
+		}	
+	if(failed > 0)
+		{
+		printf("DISPLAY:    ");
+		if(cnt0 == 0)
+			printf("DIN (GPIO%d) stuck at 0\n", GPIO_DIN);
+		else if(cnt1 == 0)
+			printf("DIN (GPIO%d) stuck at 1\n", GPIO_DIN);
+		else 
+			printf("DIN-DOUT (GPIO%d- (GPIO%d)) connetion broken\n", GPIO_DIN, GPIO_DOUT);
+		return 1;
+		}
+#endif
+	return 0;
+}
+
+int jbt_reg_init(void)
+{
+	
+	if(jbt_check())
+		return 1;	// some error
+	/* according to data sheet: wait 50ms (Tpos of LCM). However, 50ms
+	 * seems unreliable with later LCM batches, increasing to 90ms */
+	udelay(90000);
+	printf("did jbt_reg_init()\n");
+	return 0;
+}
+
+
diff --git a/u-boot/board/goldelico/gta04/TD028TTEC1.h b/u-boot/board/goldelico/gta04/TD028TTEC1.h
new file mode 100644
index 0000000..19bcc07
--- /dev/null
+++ b/u-boot/board/goldelico/gta04/TD028TTEC1.h
@@ -0,0 +1,22 @@
+#ifndef _TD028TTEC1_H
+#define _TD028TTEC1_H
+
+#define _BEAGLE_
+
+#define JBT_TX_BUF_SIZE
+struct jbt_info {
+	u_int16_t tx_buf[4];
+	struct spi_device *spi_dev;
+	int state;
+};
+
+#define JBT_COMMAND	0x000
+#define JBT_DATA	0x100
+
+int jbt_reg_init(void);
+int jbt_reg_write_nodata(struct jbt_info *jbt, u_int8_t reg);
+int jbt_reg_write(struct jbt_info *jbt, u_int8_t reg, u_int8_t data);
+int jbt_reg_write16(struct jbt_info *jbt, u_int8_t reg, u_int16_t data);
+int jbt_check(void);
+
+#endif
diff --git a/u-boot/board/goldelico/gta04/backlight.c b/u-boot/board/goldelico/gta04/backlight.c
new file mode 100644
index 0000000..76b6e43
--- /dev/null
+++ b/u-boot/board/goldelico/gta04/backlight.c
@@ -0,0 +1,113 @@
+/* u-boot driver for the GTA04 backlight
+ *
+ * Copyright (C) 2010 by Golden Delicious Computers GmbH&Co. KG
+ * Author: H. Nikolaus Schaller <hns@goldelico.com>
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <asm/errno.h>
+#include <asm/io.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/gpio.h>
+#include <asm/mach-types.h>
+#include "backlight.h"
+
+#if defined(CONFIG_OMAP3_GTA04)
+
+#define GPIO_BACKLIGHT		57	/* = GPT11_PWM */
+#define GPT_BACKLIGHT		OMAP34XX_GPT11
+
+#elif defined(CONFIG_OMAP3_BEAGLE_HYBRID)
+
+#define GPIO_BACKLIGHT		145	/* = GPT10_PWM */
+#define GPT_BACKLIGHT		OMAP34XX_GPT10
+
+#elif defined(CONFIG_OMAP3_BEAGLE_EXPANDER)
+
+#define GPIO_BACKLIGHT		146	/* = GPT11_PWM (instead of UART2-TX) */
+#define GPT_BACKLIGHT		OMAP34XX_GPT11
+
+#else
+
+#error undefined CONFIG
+
+#endif
+
+#define USE_PWM	0
+
+void backlight_set_level(int level)	// 0..255
+{
+#if USE_PWM
+	struct gptimer *gpt_base = (struct gptimer *)GPT_BACKLIGHT;
+	// 	writel(value, &gpt_base->registername);
+#else
+	omap_set_gpio_dataout(GPIO_BACKLIGHT, level >= 128);	// for simplicity we just have on/off
+	level=(level >= 128)?255:0;
+#endif
+	printf("lcm backlight level set to %d (0..255)\n", level);
+}
+
+int backlight_init(void)
+{
+#if USE_PWM
+	struct gptimer *gpt_base = (struct gptimer *)GPT_BACKLIGHT;
+#if defined(CONFIG_OMAP3_GTA04)
+	MUX_VAL(CP(GPMC_NCS6),		(IEN | PTD | DIS | M3)) /* GPT_11 - Backlight enable*/\
+#elif defined(CONFIG_OMAP3_BEAGLE_HYBRID)
+	MUX_VAL(CP(UART2_RTS),		(IEN  | PTD | DIS | M2)) /* switch to GPT10 */
+#elif defined(CONFIG_OMAP3_BEAGLE_EXPANDER)
+	MUX_VAL(CP(UART2_TX),		(IEN  | PTD | DIS | M2)) /* switch to GPT11 */
+#else	
+#error undefined CONFIG
+#endif
+	// 	writel(value, &gpt_base->registername);
+	// program registers for generating a 100-1000 Hz PWM signal
+	// or PWM synchronized to VSYNC (to avoid flicker)
+	printf("did backlight_init() on PWM\n");
+
+#error todo
+	
+#else
+#if defined(CONFIG_OMAP3_GTA04)
+	MUX_VAL(CP(GPMC_NCS6),		(IEN | PTD | DIS | M4)) /*GPIO_57 - Backlight enable*/
+#elif defined(CONFIG_OMAP3_BEAGLE_HYBRID)
+	MUX_VAL(CP(UART2_RTS),		(IEN  | PTD | DIS | M4)) /*GPIO_145*/
+#elif defined(CONFIG_OMAP3_BEAGLE_EXPANDER)
+	MUX_VAL(CP(UART2_TX),		(IEN  | PTD | DIS | M4)) /*GPIO_146*/
+#else	
+#error undefined CONFIG
+#endif
+	if(omap_request_gpio(GPIO_BACKLIGHT) == 0)	// 0 == ok
+		{
+		omap_set_gpio_direction(GPIO_BACKLIGHT, 0);		// output
+		printf("did backlight_init() on GPIO_%d\n", GPIO_BACKLIGHT);		
+		}
+	else
+		{
+		printf("backlight_init() on GPIO_%d failed\n", GPIO_BACKLIGHT);		
+		}
+
+#endif
+
+	return 0;
+}
+
+
diff --git a/u-boot/board/goldelico/gta04/backlight.h b/u-boot/board/goldelico/gta04/backlight.h
new file mode 100644
index 0000000..5c299d9
--- /dev/null
+++ b/u-boot/board/goldelico/gta04/backlight.h
@@ -0,0 +1,7 @@
+#ifndef _BACKLIGHT_H
+#define _BACKLIGHT_H
+
+void backlight_set_level(int level);	// 0..255
+int backlight_init(void);
+
+#endif
diff --git a/u-boot/board/goldelico/gta04/commands.c b/u-boot/board/goldelico/gta04/commands.c
new file mode 100644
index 0000000..eb75c1f
--- /dev/null
+++ b/u-boot/board/goldelico/gta04/commands.c
@@ -0,0 +1,782 @@
+/* u-boot extended commands for flash
+ *
+ * Copyright (C) 2010 by Golden Delicious Computers GmbH&Co. KG
+ * Author: H. Nikolaus Schaller <hns@goldelico.com>
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/errno.h>
+#include <asm/io.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/gpio.h>
+#include <asm/mach-types.h>
+
+#include "backlight.h"
+#include "dssfb.h"
+#include "jbt6k74.h"
+#include "status.h"
+#include "gps.h"
+#include "tsc2007.h"
+#include "shutdown.h"
+#include "systest.h"
+#include "twl4030-additions.h"
+
+/* LCM commands */
+
+static int do_lcd_color(int argc, char *const argv[])
+{
+	unsigned int color;
+	if (argc < 3) {
+		printf ("lcm color: missing color (0..ffffff).\n");
+		return (-1);
+	}
+	color=simple_strtoul(argv[2], NULL, 16);
+	omap3_set_color(color);
+	return 0;
+}
+
+static int do_lcd_framebuffer(int argc, char *const argv[])
+{
+	void *addr;
+	if (argc < 3) {
+		printf ("lcm fb: missing address.\n");
+		return (-1);
+	}
+	addr=(void *) simple_strtoul(argv[2], NULL, 16);
+	omap3_dss_set_fb(addr);
+	return 0;
+}
+
+static int do_lcd_backlight(int argc, char *const argv[])
+{
+	unsigned char level;
+	if (argc < 3) {
+		printf ("lcm backlight: missing level (0..255).\n");
+		return (-1);
+	}
+	level=simple_strtoul(argv[2], NULL, 10);
+	backlight_set_level(level);
+	return 0;
+}
+
+static char *lcdmodel="td028";
+
+static int do_lcd_power(int argc, char *const argv[])
+{
+	if(strcmp(lcdmodel, "td028") == 0)
+		{
+		int state=JBT_STATE_NORMAL;
+		if (argc < 3)
+			{
+			printf ("lcm power: missing state (0..2).\n");
+			return (-1);
+			}
+		state=simple_strtoul(argv[2], NULL, 10);
+		if(state > 2)
+			{
+			printf ("lcm power: invalid state (0..2).\n");
+			return (-1);
+			}
+		jbt6k74_enter_state(state);
+		printf("lcm state set to %s\n", jbt_state());	
+		}
+	return 0;
+}
+
+static int do_lcd_onoff(int argc, char *const argv[], int flag)
+{
+	if(strcmp(lcdmodel, "td028") == 0)
+		jbt6k74_display_onoff(flag);
+	else
+		jbt6k74_display_onoff(flag);
+	printf("display power %s\n", flag?"on":"off");
+	return 0;
+}
+
+static int do_lcd_init(int argc, char *const argv[])
+{
+	// check argv for user specified lcdmodel
+	return board_video_init(NULL);
+}
+
+static int do_lcd_start(int argc, char *const argv[])
+{
+	// check argv for user specified lcdmodel
+	if(board_video_init(NULL))
+		return 1;
+	if(strcmp(lcdmodel, "td028") == 0)
+		{
+		jbt6k74_enter_state(2);
+		jbt6k74_display_onoff(1);
+		backlight_set_level(255);		
+		}
+	return 0;
+}
+
+static int do_lcd(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+{
+	int len;
+	
+	if (argc < 2) {
+		printf ("lcm: missing subcommand.\n");
+		return (-1);
+	}
+	
+	len = strlen (argv[1]);
+	if (strncmp ("ba", argv[1], 2) == 0) {
+		return do_lcd_backlight (argc, argv);
+	} else if (strncmp ("po", argv[1], 2) == 0) {
+		return do_lcd_power (argc, argv);
+	} else if (strncmp ("of", argv[1], 2) == 0) {
+		return do_lcd_onoff (argc, argv, 0);
+	} else if (strncmp ("on", argv[1], 2) == 0) {
+		return do_lcd_onoff (argc, argv, 1);
+	} else if (strncmp ("in", argv[1], 2) == 0) {
+		return do_lcd_init (argc, argv);
+	} else if (strncmp ("co", argv[1], 2) == 0) {
+		return do_lcd_color (argc, argv);
+	} else if (strncmp ("fb", argv[1], 2) == 0) {
+		return do_lcd_framebuffer (argc, argv);
+	} else if (strncmp ("st", argv[1], 2) == 0) {
+		return do_lcd_start (argc, argv);
+	} else {
+		printf ("lcm: unknown operation: %s\n", argv[1]);
+	}
+	
+	return (0);
+}
+
+U_BOOT_CMD(lcm, 3, 0, do_lcd, "LCM sub-system",
+		   "init [model] - initialize DSS, GPIOs and LCM controller\n"
+		   "backlight level - set backlight level\n"
+		   "off - switch off\n"
+		   "on - switch on\n"
+		   "power mode - set power mode\n"
+		   "start [model] - initialize, switch on power and enable backlight\n"
+		   "color hhhhhh - switch color (can be used without init)\n"
+		   "fb address - set framebuffer address (can be used without init)\n"
+		   );
+
+/* TSC commands */
+
+static int do_tsc_init(int argc, char *const argv[])
+{
+	tsc2007_init();
+	return 0;
+}
+
+static int do_tsc_get(int argc, char *const argv[])
+{
+	print_adc();
+	printf("\n");
+	return 0;
+}
+
+static int do_tsc_loop(int argc, char *const argv[])
+{
+	printf("permanently reading ADCs of TSC.\n"
+		   "Press any key to stop\n\n");
+	while (!tstc() && (status_get_buttons()&0x09) == 0)
+		{
+			print_adc();
+			printf("\r");
+		}
+	if(tstc())
+		getc();
+	printf("\n");
+	return 0;
+}
+
+static int do_tsc_gloop(int argc, char *const argv[])
+{
+	unsigned short *fb=(void *) 0x81000000;	// base address to be used as RGB16 framebuffer
+	printf("permanently reading ADCs of TSC to framebuffer.\n"
+		   "Press any key to stop\n\n");
+	omap3_dss_set_fb(fb);
+	while (!tstc() && (status_get_buttons()&0x09) == 0)
+		{
+		int i;
+		for(i=0; i<8; i++)
+			{
+			int val=(480*read_adc(i))/4096;
+			int x, y;
+			printf("%d: %d\n", i, val);
+			for(y=16*i; y<16*i+16; y++)
+				{ // draw colored bar depending on current value
+					for(x=0; x<480; x++)
+						fb[x+480*y]=(x < val)?0xfc00:0x03ff;
+				}
+			}
+		}
+	if(tstc())
+		getc();
+	printf("\n");
+	return 0;
+}
+
+
+
+static int tsc_choice=0;
+
+static int do_tsc_selection(int argc, char *const argv[])
+{ // tsc selection number
+	if (argc != 3)
+		{
+			printf ("tsc selection: missing number of selection to check for.\n");
+			return (-1);
+		}
+	return tsc_choice == simple_strtoul(argv[2], NULL, 10)?0:1;
+}
+
+static int do_tsc_choose(int argc, char *const argv[])
+{ // tsc choose cols rows
+	int cols;
+	int rows;
+	int x;
+	int y;
+	tsc_choice=0;	// reset choice
+	if (argc != 4)
+		{
+			printf ("tsc choose: missing number of cols and rows.\n");
+			return (-1);
+		}
+	cols=simple_strtoul(argv[2], NULL, 10);
+	rows=simple_strtoul(argv[3], NULL, 10);
+	printf("Choosing by waiting for touch.\n");
+	for(y=0; y<rows; y++)
+		for(x=0; x<cols; x++)
+			printf("%d%s", 1+x+y*cols, (x+1==cols)?"\n":" ");
+	printf("Press touch or any key to stop\n\n");
+	while (!tstc())
+		{
+			if(pendown(NULL, NULL) && pendown(&x, &y))
+				{ // still pressed - should now be stable
+#if 0
+					printf("xy: %d/%d\n", x, y);
+					printf("xy: %d/%d\n", x*cols, y*rows);
+#endif
+					x=(x*cols)/4096;
+					y=((4095-y)*rows)/4096;	// (0,0) is lower left corner in our hardware
+					tsc_choice=1+x+y*cols;	// return 1..rows*cols
+#if 0
+					while(pendown(NULL, NULL))
+						{ // wait for pen-up
+							if(tstc())
+								break;
+						}
+#endif
+					if(tstc())
+						break;
+#if 1
+					printf("did choose %d/%d -> %d\n", x, y, tsc_choice);
+#endif
+					return 0;
+				}
+		}
+	if(tstc())
+		getc();
+	return 0;
+}
+
+static int do_tsc(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+{
+	int len;
+	
+	if (argc < 2) {
+		printf ("tsc: missing subcommand.\n");
+		return (-1);
+	}
+	
+	len = strlen (argv[1]);
+	if (strncmp ("ge", argv[1], 2) == 0) {
+		return do_tsc_get (argc, argv);
+	} else if (strncmp ("lo", argv[1], 2) == 0) {
+		return do_tsc_loop (argc, argv);
+	} else if (strncmp ("gl", argv[1], 2) == 0) {
+		return do_tsc_gloop (argc, argv);
+	} else if (strncmp ("ch", argv[1], 2) == 0) {
+		return do_tsc_choose (argc, argv);
+	} else if (strncmp ("se", argv[1], 2) == 0) {
+		return do_tsc_selection (argc, argv);
+	} else if (strncmp ("in", argv[1], 2) == 0) {
+		return do_tsc_init (argc, argv);
+	} else {
+		printf ("tsc: unknown operation: %s\n", argv[1]);
+	}
+	
+	return (0);
+}
+
+
+U_BOOT_CMD(tsc, 4, 0, do_tsc, "TSC2007 sub-system",
+		   "in[it] - initialize TSC2007\n"
+		   "ge[t] - read ADCs\n"
+		   "lo[op] - loop and display x/y coordinates\n"
+		   "gl[oop] - loop and draw to framebuffer\n"
+		   "ch[oose] cols rows - choose item\n"
+		   "se[lection] p - check if item p (1 .. cols*rows) was selected\n"
+		   );
+
+/** Status commands */
+
+static int do_status_init(int argc, char *const argv[])
+{
+	status_init();
+	return 0;
+}
+
+static void print_buttons(int status)
+{
+	printf("AUX: %s Power: %s Antenna: %s Pen: %s", (status&0x01)?"on":"off", (status&0x08)?"on":"off", (status&0x02)?"EXT":"INT", (status&0x10)?"1":"0");
+}
+
+static int do_status_check(int argc, char *const argv[])
+{ // can be used in if construct
+	int state=status_get_buttons();
+	if (argc < 3)
+		{
+			printf ("status check: missing mask.\n");
+			return (-1);
+		}
+	state &= simple_strtoul(argv[2], NULL, 16);
+	return (state != 0)?0:1;
+}
+
+static int do_status_get(int argc, char *const argv[])
+{
+	int status=status_get_buttons();
+	printf("button status: %02x\n", status);
+	print_buttons(status);
+	printf("\n");
+	return 0;
+}
+
+static int do_status_set(int argc, char *const argv[])
+{ // status set hh
+	static int state;
+	if(argc == 2)
+		state++;
+	else
+		state=simple_strtoul(argv[2], NULL, 16);
+	status_set_status(state);
+	return 0;
+}
+
+static int do_status_loop(int argc, char *const argv[])
+{
+	printf("mirroring buttons to LEDs.\n"
+		   "Press any key to stop\n\n");
+	while (!tstc() && !pendown(NULL, NULL))
+		{
+			int state=status_get_buttons();
+			print_buttons(state);
+			printf("\r");
+			status_set_status(state);	// mirror to LEDs
+			udelay(100000);	// 0.1 seconds
+		}
+	if(tstc())
+		getc();
+	printf("\n");
+	return 0;
+}
+
+static int do_status_blink(int argc, char *const argv[])
+{
+	int value=0;
+	printf("blinking LEDs.\n"
+		   "Press any key to stop\n\n");
+	while (!tstc() && !pendown(NULL, NULL))
+		{
+			status_set_status(value++);	// mirror to LEDs
+			udelay(100000);	// 0.1 seconds
+		}
+	if(tstc())
+		getc();
+	return 0;
+}
+
+static int do_status_flash(int argc, char *const argv[])
+{
+	int len;
+	
+	if (argc < 3) {
+		printf ("status flash: missing subcommand.\n");
+		return (-1);
+	}
+	
+	len = strlen (argv[2]);
+	if (strncmp ("of", argv[2], 2) == 0) {
+		return status_set_flash (0);
+	} else if (strncmp ("on", argv[2], 2) == 0) {
+		return status_set_flash (1);
+	} else if (strncmp ("fl", argv[2], 2) == 0) {
+		return status_set_flash (2);
+	} else {
+		printf ("status: unknown operation: %s\n", argv[1]);
+		return 1;
+	}
+	return (0);
+}
+
+static int do_status_vibra(int argc, char *const argv[])
+{
+	static int value;
+	if (argc < 3) {
+		printf ("status vibra: missing value.\n");
+		return (-1);
+	}
+	value=simple_strtol(argv[2], NULL, 10);
+	return status_set_vibra(value);
+}
+
+static int do_status(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+{
+	int len;
+	
+	if (argc < 2) {
+		printf ("status: missing subcommand.\n");
+		return (-1);
+	}
+	
+	len = strlen (argv[1]);
+	if (strncmp ("ge", argv[1], 2) == 0) {
+		return do_status_get (argc, argv);
+	} else if (strncmp ("se", argv[1], 2) == 0) {
+		return do_status_set (argc, argv);
+	} else if (strncmp ("mi", argv[1], 2) == 0) {
+		return do_status_loop (argc, argv);
+	} else if (strncmp ("bl", argv[1], 2) == 0) {
+		return do_status_blink (argc, argv);
+	} else if (strncmp ("in", argv[1], 2) == 0) {
+		return do_status_init (argc, argv);
+	} else if (strncmp ("ch", argv[1], 2) == 0) {
+		return do_status_check (argc, argv);
+	} else if (strncmp ("fl", argv[1], 2) == 0) {
+		return do_status_flash (argc, argv);
+	} else if (strncmp ("vi", argv[1], 2) == 0) {
+		return do_status_vibra (argc, argv);
+	} else {
+		printf ("status: unknown operation: %s\n", argv[1]);
+	}
+	
+	return (0);
+}
+
+
+U_BOOT_CMD(status, 3, 0, do_status, "LED and Buttons sub-system",
+		   "in[it] - initialize GPIOs\n"
+		   "ge[t] - print button status\n"
+		   "ch[eck] - check button status\n"
+		   "se[t] value - set LEDs state\n"
+		   "mi[rror] - read buttons and mirror to LEDs\n"
+		   "bl[ink] - blink LEDs\n"
+		   "fl[ash] of[f] | on | fl[ash] - control torch / flashlight\n"
+		   "vi[bra] -256..256 - run vibracall motor\n"
+		   );
+
+/** GPS commands */
+
+static int do_gps_init(int argc, char *const argv[])
+{
+	return gps_init();
+}
+
+static int do_gps_on(int argc, char *const argv[])
+{
+	// should we better send a single ongoing pulse of at least 2 32 kHz cycles?
+	gps_on();
+	printf("GPS on\n");
+	return 0;
+}
+
+static int do_gps_off(int argc, char *const argv[])
+{
+	gps_off();
+	printf("GPS off\n");
+	return 0;
+}
+
+static int do_gps_echo(int argc, char *const argv[])
+{
+	gps_echo();
+	return 0;
+}
+
+// FIXME: "gps cmd" to send a string
+
+static int do_gps(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+{
+	int len;
+	
+	if (argc < 2) {
+		printf ("gps: missing subcommand.\n");
+		return (-1);
+	}
+	
+	len = strlen (argv[1]);
+	if (strncmp ("on", argv[1], 2) == 0) {
+		return do_gps_on (argc, argv);
+	} else if (strncmp ("of", argv[1], 2) == 0) {
+		return do_gps_off (argc, argv);
+	} else if (strncmp ("in", argv[1], 2) == 0) {
+		return do_gps_init (argc, argv);
+	} else if (strncmp ("ec", argv[1], 2) == 0) {
+		return do_gps_echo (argc, argv);
+	} else {
+		printf ("gps: unknown operation: %s\n", argv[1]);
+	}
+	
+	return (0);
+}
+
+
+U_BOOT_CMD(gps, 3, 0, do_gps, "GPS sub-system",
+		   "init - initialize GPIOs\n"
+		   "on - enable GPS\n"
+		   "off - disable GPS\n"
+		   "cmd string - send string\n"
+		   "echo - echo GPS out to console\n"
+		   );
+
+#include "ulpi-phy.h"
+
+static int do_systest_all(int argc, char *const argv[])
+{
+	unsigned short *fb=(void *) 0x81000000;	// base address to be used as RGB16 framebuffer
+	printf("permanently doing complete systest.\n"
+		   "Press any key to stop\n\n");
+	omap3_dss_set_fb(fb);
+	audiotest_init(0);
+	while (!tstc() && (status_get_buttons()&0x09) == 0)
+		{
+		int i;
+		for(i=0; i<8; i++)
+			{
+			int val=(480*read_adc(i))/4096;
+			int x, y;
+			printf("%d: %d\n", i, val);
+			for(y=16*i; y<16*i+16; y++)
+				{ // draw colored bar depending on current value
+					for(x=0; x<480; x++)
+						fb[x+480*y]=(x < val)?0xfc00:0x03ff;
+				}
+			}
+		// show hardware test results (chip availability)
+		// continue to play some sound every loop...
+		}
+	if(tstc())
+		getc();
+	printf("\n");
+	return 0;
+}
+
+static int do_systest(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+{
+	if(argc >= 2) {
+		if (strncmp ("au", argv[1], 2) == 0) {
+			return audiotest(0);
+		}
+		if (strncmp ("al", argv[1], 2) == 0) {
+			return do_systest_all (argc, argv);
+		}
+		if (strncmp ("ir", argv[1], 2) == 0) {
+			return irdatest();
+		}
+		if (strncmp ("wl", argv[1], 2) == 0) {
+			return wlanbttest(1);
+		}
+		if (strncmp ("wp", argv[1], 2) == 0) {
+			return wlanbttest(0);	// just power on
+		}
+		if (strncmp ("ch", argv[1], 2) == 0) {
+			return twl4030_init_battery_charging();
+		}
+		if (strncmp ("gp", argv[1], 2) == 0) {
+			return gpiotest();
+		}
+	}
+	if(argc == 3) {
+		if (strncmp ("ot", argv[1], 2) == 0) {
+			return OTGchargepump(simple_strtoul(argv[2], NULL, 10));			
+		}
+		if (strncmp ("ul", argv[1], 2) == 0) {
+			int port=simple_strtoul(argv[2], NULL, 10);	/* 0, 1, ... */
+			int reg;
+			for(reg=0; reg <= 0x3f; reg++)
+				printf("ulpi reg %02x: %02x\n", reg, ulpi_direct_access(port, reg, 0, 0));
+		}
+	}
+	return systest();
+}
+
+U_BOOT_CMD(systest, 3, 0, do_systest, "System Test",
+		   "al[l] - graphical test mode\n"
+		   "au[dio] - test audio\n"
+		   "ir[da] - test IrDA\n"
+		   "gp[io] - test some GPIOs\n"
+		   "wl[anbt] - test WLAN/BT module\n"
+		   "wp - apply power to WLAN/BT module\n"
+		   "ch[arging] - init and test BCI/BKBAT\n"
+		   "ot[g] n - enable/disable OTG charge pump\n"
+		   "ul[pi] n - read ULPI register n\n"
+		   "<no args> - test presence of I2C devices and some TPS65950 registers\n"
+		   );
+
+
+static int do_poweroff(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+{
+	backlight_set_level(0);
+	jbt6k74_enter_state(0);
+	jbt6k74_display_onoff(0);
+	shutdown();	// finally shut down power
+	printf ("failed to power down\n");
+	return (0);
+}
+
+U_BOOT_CMD(poweroff, 2, 0, do_poweroff, "Poweroff",
+		   "");
+
+static int do_suspend(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+{
+	backlight_set_level(0);
+	jbt6k74_enter_state(0);
+	jbt6k74_display_onoff(0);
+	suspend();	// put CPU in sleep mode so that it can be waked up by pressing the AUX button or other events
+	printf ("suspend finished\n");
+	return (0);
+}
+
+U_BOOT_CMD(suspend, 2, 0, do_suspend, "Suspend",
+		   "");
+
+
+static int do_mux(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+{
+	int cols=0;
+	char *addr=(char *) 0x48002030;
+	printf("PADCONF [0:15] [16:31]\n");
+	while(addr < (char *) 0x48002A28) {
+		u16 mux=*(u16 *) addr;
+		if(cols == 0)
+			printf("%08x", (unsigned int) addr);			
+		printf(" %c%d%c", (mux&8)?((mux&0x10?'U':'D')):' ', (mux&7), (mux&0x100)?'I':'O');
+		addr+=2;
+		if(addr == (char *) 0x48002262)
+			addr= (char *) 0x480025D8, cols=1;	// skip block and force new line
+		if(addr == (char *) 0x480025FC)
+			addr= (char *) 0x48002A00, cols=1;	// skip block and force new line
+		if(++cols == 2) {
+			printf("\n");
+			cols=0;
+		}
+	}
+	if(cols != 0)
+		printf("\n");
+	return (0);
+}
+
+U_BOOT_CMD(mux, 2, 0, do_mux, "Pinmux", "");
+
+
+static int do_gpio(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+{
+	int g;
+	if(argc == 3) {
+		if (strncmp ("on", argv[1], 2) == 0) {
+			g=simple_strtoul(argv[2], NULL, 10);
+			omap_request_gpio(g);
+			omap_set_gpio_dataout(g, 1);
+			//			omap_free_gpio(g); - switches back to input
+			return 0;
+		}
+		else if (strncmp ("of", argv[1], 2) == 0) {
+			g=simple_strtoul(argv[2], NULL, 10);
+			omap_request_gpio(g);
+			omap_set_gpio_dataout(g, 0);
+			//			omap_free_gpio(g); - switches back to input
+			return 0;
+		}
+		else if (strncmp ("in", argv[1], 2) == 0) {
+			g=simple_strtoul(argv[2], NULL, 10);
+			omap_request_gpio(g);
+			omap_set_gpio_direction(g, 1);
+			//			omap_free_gpio(g); - switches back to input
+			return 0;
+		}
+		else if (strncmp ("ou", argv[1], 2) == 0) {
+			g=simple_strtoul(argv[2], NULL, 10);
+			omap_request_gpio(g);
+			omap_set_gpio_direction(g, 0);
+			//			omap_free_gpio(g); - switches back to input
+			return 0;
+		}
+	}
+	if(argc == 1 || argc == 3)
+		{ // no arguments or from..to
+			int i=0;
+			int end=6*32;
+			int n=10;	// number of columns
+			int col=0;
+			if(argc == 3) {
+				i=simple_strtoul(argv[1], NULL, 10);
+				end=simple_strtoul(argv[2], NULL, 10)+1;	// include
+			}
+			for(; i<end; i++)
+				{
+				if(col == 0)
+					printf("%03d", i);
+				printf(" %d", omap_get_gpio_datain(i));
+				if(++col == n)
+					printf("\n"), col=0;
+				}
+			if(col != 0)
+				printf("\n");	// last line		
+		}
+	else if(argc == 2) { // n only
+		if(omap_get_gpio_datain(simple_strtoul(argv[1], NULL, 10)))
+			{
+			printf("1\n");
+			return 1;
+			}
+		else
+			{
+			printf("0\n");
+			return 0;
+			}
+		}
+	else {
+		printf ("gpio: unknown subcommand.\n");
+		return (-1);
+	}
+
+	return (0);
+}
+
+U_BOOT_CMD(gpio, 3, 0, do_gpio, "GPIO sub-system",
+		   " - print all\n"
+		   "n - print and return state\n"
+		   "m n - print state in given range\n"
+		   "on n - set to 1\n"
+		   "of[f] n - set to 0\n"
+		   "in n - switch to input\n"
+		   "ou[t] n - switch to out (does not change pinmux!)\n"
+		   );
diff --git a/u-boot/board/goldelico/gta04/config.mk b/u-boot/board/goldelico/gta04/config.mk
new file mode 100644
index 0000000..cf055db
--- /dev/null
+++ b/u-boot/board/goldelico/gta04/config.mk
@@ -0,0 +1,33 @@
+#
+# (C) Copyright 2006
+# Texas Instruments, <www.ti.com>
+#
+# Beagle Board uses OMAP3 (ARM-CortexA8) cpu
+# see http://www.ti.com/ for more information on Texas Instruments
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+# Physical Address:
+# 8000'0000 (bank0)
+# A000/0000 (bank1)
+# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
+# (mem base + reserved)
+
+# For use with external or internal boots.
+CONFIG_SYS_TEXT_BASE = 0x80008000
diff --git a/u-boot/board/goldelico/gta04/dssfb.c b/u-boot/board/goldelico/gta04/dssfb.c
new file mode 100644
index 0000000..4eff169
--- /dev/null
+++ b/u-boot/board/goldelico/gta04/dssfb.c
@@ -0,0 +1,257 @@
+/* u-boot driver for the DSS and framebuffer
+ *
+ * Copyright (C) 2010 by Golden Delicious Computers GmbH&Co. KG
+ * Author: H. Nikolaus Schaller <hns@goldelico.com>
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <asm/errno.h>
+#include <asm/io.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/gpio.h>
+#include <asm/mach-types.h>
+#include <asm/arch/clocks.h>
+#include <asm/arch/clocks_omap3.h>
+#include "dssfb.h"
+
+#if 0
+#define DEBUGP(x, args...) printf("%s: " x, __FUNCTION__, ## args);
+#define DEBUGPC(x, args...) printf(x, ## args);
+#define VERIFY(VAL) if(SPI_READ() != (VAL)) { printf("expected: %d found: %d\n", VAL, SPI_READ()); return 1; }
+#else
+#define DEBUGP(x, args...) do { } while (0)
+#define DEBUGPC(x, args...) do { } while (0)
+#define VERIFY(VAL) if(SPI_READ() != (VAL)) { return 1; }
+#endif
+
+void omap3_dss_go(void)
+{ // push changes from shadow register to display controller
+	struct dispc_regs *dispc = (struct dispc_regs *) OMAP3_DISPC_BASE;
+
+	u32 l = 0;
+	l = readl(&dispc->control);
+	l |= GO_LCD | GO_DIG;
+	writel(l, &dispc->control);
+	while((readl(&dispc->control) & (GO_LCD | GO_DIG)) != 0)
+		udelay(1000);	// udelay(1000) until the bit(s) are reset by Hardware!
+	DEBUGP("omap3_dss_go() dispc_control: %08x\n", readl(&dispc->control));
+}
+
+struct gfx_regs 
+{
+	u32 gfx_ba[2];				/* 80 */
+	u32 gfx_position;			/* 88 */
+	u32 gfx_size;				/* 8c */
+	u32 reserved1[4];			
+	u32 gfx_attributes;			/* a0 */
+#define GFX_ENABLE 0x0001
+	u32 gfx_fifo_threshold;		/* a4 */
+	u32 gfx_fifo_size_status;	/* a8 */
+	u32 gfx_row_inc;			/* ac */
+	u32 gfx_pixel_inc;			/* b0 */
+	u32 gfx_window_skip;		/* b4 */
+	u32 gfx_table_ba;			/* b8 */
+};
+
+#define OMAP3_GFX_BASE (0x48050480)
+
+int omap3_dss_enable_fb(int flag)
+{
+	struct gfx_regs *gfx = (struct gfx_regs *) OMAP3_GFX_BASE;
+	u32 l = readl(&gfx->gfx_attributes);
+	if(flag)
+		l |= GFX_ENABLE;
+	else
+		l &= ~GFX_ENABLE;
+	DEBUGP("write %x to gfx_attibutes: %08x\n", l, &gfx->gfx_attributes);
+	writel(l, &gfx->gfx_attributes);
+	omap3_dss_go();
+	DEBUGP("framebuffer enabled: %d\n", flag);
+	DEBUGP("gfx_attibutes: %08x\n", readl(&gfx->gfx_attributes));
+	return 0;
+}
+
+int omap3_dss_set_fb(void *addr)
+{ // set framebuffer address
+	struct dispc_regs *dispc = (struct dispc_regs *) OMAP3_DISPC_BASE;
+	struct gfx_regs *gfx = (struct gfx_regs *) OMAP3_GFX_BASE;
+	if(addr != NULL)
+		{
+			//			u32 l = readl(&dispc->control);
+			//			l |= GO_LCD | GO_DIG;
+			//			writel(l, &dispc->control);
+			//			printf("write %x to gfx_attibutes: %08x\n", l, &gfx->gfx_attributes);
+			//			writel(l, &gfx->gfx_attributes);
+			//			printf("gfx_ba[0]: %08x\n", &gfx->gfx_ba[0]);
+			writel((u32) addr, &gfx->gfx_ba[0]);
+			writel((u32) addr, &gfx->gfx_ba[1]);
+			//			printf("framebuffer address: %08x\n", addr);
+			writel(0, &gfx->gfx_position);
+			//			printf("size_lcd: %08x\n", readl(&dispc->size_lcd));
+			writel(readl(&dispc->size_lcd), &gfx->gfx_size);
+			writel(0x008c, &gfx->gfx_attributes);	// 16x32 bit bursts + RGB16?
+			writel(((0x3fc << 16) + (0x3bc)), &gfx->gfx_fifo_threshold);	// high & low
+			writel(1024, &gfx->gfx_fifo_size_status);	// FIFO size in bytes
+			writel(1, &gfx->gfx_row_inc);
+			writel(1, &gfx->gfx_pixel_inc);
+			writel(0, &gfx->gfx_window_skip);
+			writel(0x807ff000, &gfx->gfx_table_ba);
+			omap3_dss_enable_fb(1);
+#if DEBUG
+			{
+				u32 addr;
+				for(addr=0x48050010; addr <= 0x48050010; addr+=4)
+					printf("%08x: %08x\n", addr, readl(addr));
+				for(addr=0x48050040; addr <= 0x48050058; addr+=4)
+					printf("%08x: %08x\n", addr, readl(addr));
+				for(addr=0x48050410; addr <= 0x48050414; addr+=4)
+					printf("%08x: %08x\n", addr, readl(addr));
+				for(addr=0x48050444; addr <= 0x4805048c; addr+=4)
+					printf("%08x: %08x\n", addr, readl(addr));
+				for(addr=0x480504a0; addr <= 0x480504b8; addr+=4)
+					printf("%08x: %08x\n", addr, readl(addr));
+			}
+#endif
+		}
+	else
+		{ // disable
+			omap3_dss_enable_fb(0);
+		}
+	return 0;
+}
+
+int omap3_set_color(u32 color)
+{
+	struct dispc_regs *dispc = (struct dispc_regs *) OMAP3_DISPC_BASE;
+	writel(color, &dispc->default_color0);
+	omap3_dss_go();
+	printf("background color: %06x\n", color);
+	return 0;
+}
+
+/*
+ * Display Configuration
+ */
+
+#define DVI_BEAGLE_ORANGE_COL		0x00FF8000
+#define VENC_HEIGHT			0x00ef
+#define VENC_WIDTH			0x027f
+
+/*
+ * Configure VENC in DSS for Beagle to generate Color Bar
+ *
+ * Kindly refer to OMAP TRM for definition of these values.
+ */
+static const struct venc_regs venc_config_std_tv = {
+	.status					= 0x0000001B,
+	.f_control				= 0x00000040,
+	.vidout_ctrl				= 0x00000000,
+	.sync_ctrl				= 0x00008000,
+	.llen					= 0x00008359,
+	.flens					= 0x0000020C,
+	.hfltr_ctrl				= 0x00000000,
+	.cc_carr_wss_carr			= 0x043F2631,
+	.c_phase				= 0x00000024,
+	.gain_u					= 0x00000130,
+	.gain_v					= 0x00000198,
+	.gain_y					= 0x000001C0,
+	.black_level				= 0x0000006A,
+	.blank_level				= 0x0000005C,
+	.x_color				= 0x00000000,
+	.m_control				= 0x00000001,
+	.bstamp_wss_data			= 0x0000003F,
+	.s_carr					= 0x21F07C1F,
+	.line21					= 0x00000000,
+	.ln_sel					= 0x00000015,
+	.l21__wc_ctl				= 0x00001400,
+	.htrigger_vtrigger			= 0x00000000,
+	.savid__eavid				= 0x069300F4,
+	.flen__fal				= 0x0016020C,
+	.lal__phase_reset			= 0x00060107,
+	.hs_int_start_stop_x			= 0x008D034E,
+	.hs_ext_start_stop_x			= 0x000F0359,
+	.vs_int_start_x				= 0x01A00000,
+	.vs_int_stop_x__vs_int_start_y		= 0x020501A0,
+	.vs_int_stop_y__vs_ext_start_x		= 0x01AC0024,
+	.vs_ext_stop_x__vs_ext_start_y		= 0x020D01AC,
+	.vs_ext_stop_y				= 0x00000006,
+	.avid_start_stop_x			= 0x03480079,
+	.avid_start_stop_y			= 0x02040024,
+	.fid_int_start_x__fid_int_start_y	= 0x0001008A,
+	.fid_int_offset_y__fid_ext_start_x	= 0x01AC0106,
+	.fid_ext_start_y__fid_ext_offset_y	= 0x01060006,
+	.tvdetgp_int_start_stop_x		= 0x00140001,
+	.tvdetgp_int_start_stop_y		= 0x00010001,
+	.gen_ctrl				= 0x00FF0000,
+	.output_control				= 0x0000000D,
+	.dac_b__dac_c				= 0x00000000
+};
+
+/*
+ * Configure Timings for DVI D
+ */
+static const struct panel_config dvid_cfg = {
+	.timing_h	= 0x0ff03f31, /* Horizantal timing */
+	.timing_v	= 0x01400504, /* Vertical timing */
+	.pol_freq	= 0x00007028, /* Pol Freq */
+	.divisor	= 0x00010006, /* 72Mhz Pixel Clock */
+	.lcd_size	= 0x02ff03ff, /* 1024x768 */
+	.panel_type	= 0x01, /* TFT */
+	.data_lines	= 0x03, /* 24 Bit RGB */
+	.load_mode	= 0x02, /* Frame Mode */
+	.panel_color	= DVI_BEAGLE_ORANGE_COL /* ORANGE */
+};
+
+void dssfb_init(const struct panel_config *lcm_cfg)
+{
+#ifdef CONFIG_OMAP3_GTA04A2	/* delayed on GTA04A2 */
+	struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
+	printf("prcm base = %p\n", (void *) prcm_base);
+	printf("ick_dss_on\n");
+	sr32(&prcm_base->iclken_dss, 0, 32, ICK_DSS_ON);
+	sdelay(1000);
+	printf("fck_dss_on\n");
+	sr32(&prcm_base->fclken_dss, 0, 32, FCK_DSS_ON);
+	sdelay(1000);
+//	printf("fck_cam_on\n");
+//	sr32(&prcm_base->fclken_cam, 0, 32, FCK_CAM_ON);
+//	printf("ick_cam_on\n");
+//	sr32(&prcm_base->iclken_cam, 0, 32, ICK_CAM_ON);
+	sdelay(1000);
+#else
+	// FIXME: restore original code
+#endif
+	printf("dss panel config\n");	
+	omap3_dss_panel_config(lcm_cfg);	// set new config
+	printf("dss enable\n");
+	omap3_dss_enable();	// and (re)enable
+}
+
+/*
+ * Configure DSS to display background color on DVID
+ * Configure VENC to display color bar on S-Video
+ */
+void display_init(void)
+{
+	omap3_dss_venc_config(&venc_config_std_tv, VENC_HEIGHT, VENC_WIDTH);
+	omap3_dss_panel_config(&dvid_cfg);
+}
+
diff --git a/u-boot/board/goldelico/gta04/dssfb.h b/u-boot/board/goldelico/gta04/dssfb.h
new file mode 100644
index 0000000..a71b193
--- /dev/null
+++ b/u-boot/board/goldelico/gta04/dssfb.h
@@ -0,0 +1,34 @@
+/* u-boot driver for the DSS and framebuffer
+ *
+ * Copyright (C) 2010 by Golden Delicious Computers GmbH&Co. KG
+ * Author: H. Nikolaus Schaller <hns@goldelico.com>
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <asm/arch/dss.h>
+
+void dssfb_init(const struct panel_config *lcm_cfg);
+
+void omap3_dss_go(void);
+
+int omap3_dss_enable_fb(int flag);
+
+int omap3_dss_set_fb(void *addr);	// set framebuffer address
+
+int omap3_set_color(u32 color);	// set background color
diff --git a/u-boot/board/goldelico/gta04/gps.c b/u-boot/board/goldelico/gta04/gps.c
new file mode 100644
index 0000000..7f74dc8
--- /dev/null
+++ b/u-boot/board/goldelico/gta04/gps.c
@@ -0,0 +1,136 @@
+/* u-boot driver for the GTA04 LEDs and Buttons
+ *
+ * Copyright (C) 2010 by Golden Delicious Computers GmbH&Co. KG
+ * Author: H. Nikolaus Schaller <hns@goldelico.com>
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <asm/errno.h>
+#include <asm/io.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/gpio.h>
+#include <asm/mach-types.h>
+#include <ns16550.h>
+#include <twl4030.h>
+#include "gps.h"
+
+#ifdef CONFIG_OMAP3_GTA04
+
+#define GPIO_GPSEXT		144		// external GPS antenna plugged in
+#define GPIO_GPS_ON		145		// reset for GPS module
+
+#else /* Beagle Hybrid */
+
+#define GPIO_GPSEXT		138		// external GPS antenna plugged in
+#define GPIO_GPS_ON		156
+
+#endif
+
+int gps_init(void)
+{
+	extern int get_board_revision(void);
+#define REVISION_XM 0
+	if(get_board_revision() == REVISION_XM) {
+		/* Set VAUX1 to 3.3V for GTA04E display board */
+		twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VAUX1_DEDICATED,
+							/*TWL4030_PM_RECEIVER_VAUX1_VSEL_33*/ 0x07,
+							TWL4030_PM_RECEIVER_VAUX1_DEV_GRP,
+							TWL4030_PM_RECEIVER_DEV_GRP_P1);
+		udelay(5000);
+	}
+#ifdef CONFIG_OMAP3_GTA04
+	/* ext. GPS Ant VSIM = 2.8 V (3.0V) */
+	twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VSIM_DEDICATED,
+							/*TWL4030_PM_RECEIVER_VSIM_VSEL_28*/ 0x04 /* 0x05 */,
+							TWL4030_PM_RECEIVER_VSIM_DEV_GRP,
+							TWL4030_PM_RECEIVER_DEV_GRP_P1);
+	udelay(5000);
+#endif
+	
+	omap_request_gpio(GPIO_GPS_ON);
+	omap_set_gpio_direction(GPIO_GPS_ON, 0);		// output
+	omap_request_gpio(GPIO_GPSEXT);
+	omap_set_gpio_direction(GPIO_GPSEXT, 1);		// input
+	return 0;
+}
+
+void gps_on(void)
+{
+	omap_set_gpio_dataout(GPIO_GPS_ON, 1);
+	if(omap_get_gpio_datain(GPIO_GPSEXT))
+		printf("external antenna\n");
+	else
+		printf("internal antenna\n");
+}
+
+void gps_off(void)
+{
+	omap_set_gpio_dataout(GPIO_GPS_ON, 0);
+}
+
+static int lastant=-1;
+static long timer;
+
+#define TIMEOUT 2	// in seconds
+
+void gps_echo(void)
+{
+	#define MODE_X_DIV 16
+	int baudrate=9600;
+	int divisor=(CONFIG_SYS_NS16550_CLK + (baudrate * (MODE_X_DIV / 2))) / (MODE_X_DIV * baudrate);
+	NS16550_reinit((NS16550_t)CONFIG_SYS_NS16550_COM2, divisor);	// initialize UART
+	while (1)
+		{ // echo in both directions
+			int ant=omap_get_gpio_datain(GPIO_GPSEXT);
+			if(ant != lastant)
+				{ // changed
+					if(ant)
+						printf("external antenna\n");
+					else
+						printf("internal antenna\n");
+					lastant=ant;
+				}
+			if(NS16550_tstc((NS16550_t)CONFIG_SYS_NS16550_COM2))
+				{
+				putc(NS16550_getc((NS16550_t)CONFIG_SYS_NS16550_COM2));	// from GPS to console
+				timer=0;	// data received
+				}
+			if(tstc())
+				{
+				int c=getc();
+				if(c == 0x03)	// ctrl-C
+					break;
+				// NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM2, c);
+				break;
+				}
+			if(timer++ > 2*10000)
+				{ // timeout - try to wakeup/reset the chip
+					printf("no data: on-off impulse\n");
+					omap_set_gpio_dataout(GPIO_GPS_ON, 1);
+					udelay(5000);
+					omap_set_gpio_dataout(GPIO_GPS_ON, 1);
+					timer=0;
+				}
+			udelay(100);	// 10 kHz @ 9 kbit/s
+		}
+	printf("\n");
+}
+
diff --git a/u-boot/board/goldelico/gta04/gps.h b/u-boot/board/goldelico/gta04/gps.h
new file mode 100644
index 0000000..937beb0
--- /dev/null
+++ b/u-boot/board/goldelico/gta04/gps.h
@@ -0,0 +1,11 @@
+#ifndef _GPS_H
+#define _GPS_H
+
+int gps_init(void);
+
+void gps_on(void);
+void gps_off(void);
+
+void gps_echo(void);
+
+#endif
diff --git a/u-boot/board/goldelico/gta04/gta04.c b/u-boot/board/goldelico/gta04/gta04.c
new file mode 100644
index 0000000..e9bdd87
--- /dev/null
+++ b/u-boot/board/goldelico/gta04/gta04.c
@@ -0,0 +1,291 @@
+/*
+ * (C) Copyright 2004-2008
+ * Texas Instruments, <www.ti.com>
+ *
+ * Author :
+ *	Sunil Kumar <sunilsaini05@gmail.com>
+ *	Shashi Ranjan <shashiranjanmca05@gmail.com>
+ *
+ * Derived from Beagle Board and 3430 SDP code by
+ *	Richard Woodruff <r-woodruff2@ti.com>
+ *	Syed Mohammed Khasim <khasim@ti.com>
+ *
+ * Authos:
+ *  Nikolaus Schaller <hns@goldelico.com>
+ *  adapted to GTA04
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <twl4030.h>
+#include <asm/io.h>
+#include <asm/arch/mmc_host_def.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/gpio.h>
+#include <asm/mach-types.h>
+#include "gta04.h"
+
+#if 1	/* testing tool; you can call notify() anywhere even before initialization to see how far the code comes */
+
+/******************************************************************************
+ * Routine: delay
+ * Description: spinning delay to use before udelay works
+ *****************************************************************************/
+static inline void mydelay(unsigned long loops)
+{
+	__asm__ volatile ("1:\n" "subs %0, %1, #1\n"
+					  "bne 1b":"=r" (loops):"0"(loops));
+}
+
+static inline void myudelay(unsigned long us)
+{
+	mydelay(us * 200); /* approximate */
+}
+
+#define BLON()	MUX_VAL(CP(GPMC_NCS6),      (IEN | PTU | EN  | M4)) /*GPT_PWM11/GPIO57*/
+#define BLOFF()	MUX_VAL(CP(GPMC_NCS6),      (IEN | PTD | EN  | M4)) /*GPT_PWM11/GPIO57*/
+
+void notify(int number)
+{ // flash LCD backlight
+	BLOFF();
+	myudelay(200*1000);
+	BLON();
+	myudelay(50*1000);	// flash
+	BLOFF();
+	myudelay(1500*1000);
+}
+
+#endif
+
+
+/*
+ * Routine: board_init
+ * Description: Early hardware init.
+ */
+int board_init(void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+	gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
+	/* board id for Linux */
+	gd->bd->bi_arch_number = MACH_TYPE_GTA04;
+	/* boot param addr */
+	gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
+	
+	return 0;
+}
+
+/*
+ * Routine: get_board_revision
+ * Description: Detect if we are running on a Beagle revision Ax/Bx,
+ *		C1/2/3, C4 or xM. This can be done by reading
+ *		the level of GPIO173, GPIO172 and GPIO171. This should
+ *		result in
+ *		GPIO173, GPIO172, GPIO171: 1 1 1 => Ax/Bx
+ *		GPIO173, GPIO172, GPIO171: 1 1 0 => C1/2/3
+ *		GPIO173, GPIO172, GPIO171: 1 0 1 => C4
+ *		GPIO173, GPIO172, GPIO171: 0 0 0 => xM
+ */
+int get_board_revision(void)
+{
+	return 6;	// configure pinmux for C1/2/3
+}
+
+/*
+ * Routine: misc_init_r
+ * Description: Configure board specific parts
+ */
+
+#define TCA6507_BUS			(2-1)	// I2C2
+#define TCA6507_ADDRESS		0x45
+
+/* register numbers */
+#define TCA6507_SELECT0						0
+#define TCA6507_SELECT1						1
+#define TCA6507_SELECT2						2
+
+int misc_init_r(void)
+{
+	struct gpio *gpio5_base = (struct gpio *)OMAP34XX_GPIO5_BASE;
+	struct gpio *gpio6_base = (struct gpio *)OMAP34XX_GPIO6_BASE;
+
+	/* ITG3200 & HMC5883L VAUX2 = 2.8V */
+	twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VAUX2_DEDICATED,
+							/*TWL4030_PM_RECEIVER_VAUX2_VSEL_28*/ 0x09,
+							TWL4030_PM_RECEIVER_VAUX2_DEV_GRP,
+							TWL4030_PM_RECEIVER_DEV_GRP_P1);
+	/* Camera VAUX3 = 2.5V */
+	twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VAUX3_DEDICATED,
+							/*TWL4030_PM_RECEIVER_VAUX3_VSEL_25*/ 0x02,
+							TWL4030_PM_RECEIVER_VAUX3_DEV_GRP,
+							TWL4030_PM_RECEIVER_DEV_GRP_P1);
+
+	i2c_set_bus_num(TCA6507_BUS);	// write I2C2
+	i2c_reg_write(TCA6507_ADDRESS, TCA6507_SELECT0, 0);
+	i2c_reg_write(TCA6507_ADDRESS, TCA6507_SELECT1, 0);
+	i2c_reg_write(TCA6507_ADDRESS, TCA6507_SELECT2, 0x40);	// pull down reset for WLAN&BT chip
+	i2c_set_bus_num(0);	// write I2C1
+
+#if 0 // FIXME: enable only on demand if we want to test BT/WIFI - and apply RESET
+	/* Bluetooth VAUX4 = 3.3V -- CHECKME: 3.3 V is not officially supported! We use 0x09 = 2.8V here*/
+	twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VAUX4_DEDICATED,
+							/*TWL4030_PM_RECEIVER_VAUX4_VSEL_33*/ 0x09,
+							TWL4030_PM_RECEIVER_VAUX4_DEV_GRP,
+							TWL4030_PM_RECEIVER_DEV_GRP_P1);
+#endif
+
+	/* make dependent on CPU type */
+	setenv("mpurate", "600");
+	setenv("mpurate", "800");
+
+	twl4030_power_init();
+	
+	// we have no LEDs on TPS on GTA04
+	// but a power on/off button (8 seconds)
+	twl4030_power_reset_init();
+
+#if 0
+	// FIXME: check this!!!
+	
+	/* Configure GPIOs to output */
+	writel(~(GPIO23 | GPIO10 | GPIO8 | GPIO2 | GPIO1), &gpio6_base->oe);
+	writel(~(GPIO31 | GPIO30 | GPIO29 | GPIO28 | GPIO22 | GPIO21 |
+			 GPIO15 | GPIO14 | GPIO13 | GPIO12), &gpio5_base->oe);
+	
+	/* Set GPIOs */
+	writel(GPIO23 | GPIO10 | GPIO8 | GPIO2 | GPIO1,
+		   &gpio6_base->setdataout);
+	writel(GPIO31 | GPIO30 | GPIO29 | GPIO28 | GPIO22 | GPIO21 |
+		   GPIO15 | GPIO14 | GPIO13 | GPIO12, &gpio5_base->setdataout);
+#endif
+	
+#if 1	// duplicate with twl4030-additions
+	
+#define TWL4030_BB_CFG_BBCHEN		(1 << 4)
+#define TWL4030_BB_CFG_BBSEL_3200MV	(3 << 2)
+#define TWL4030_BB_CFG_BBISEL_500UA	2
+	
+	/* Enable battery backup capacitor (3.2V, 0.5mA charge current) */
+	twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER,
+						 TWL4030_BB_CFG_BBCHEN | TWL4030_BB_CFG_BBSEL_3200MV |
+						 TWL4030_BB_CFG_BBISEL_500UA, TWL4030_PM_RECEIVER_BB_CFG);
+#endif
+	
+	dieid_num_r();
+
+#if 0	// check if watchdog is switched off
+	{	
+		struct _watchdog {
+			u32 widr;	/* 0x00 r */
+			u8 res1[0x0c];
+			u32 wd_sysconfig;	/* 0x10 rw */
+			u32 ws_sysstatus;	/* 0x14 r */
+			u32 wisr;
+			u32 wier;
+			u8 res2[0x04];
+			u32 wclr;	/* 0x24 rw */
+			u32 wcrr;
+			u32 wldr;
+			u32 wtgr;
+			u32 wwps;	/* 0x34 r */
+			u8 res3[0x10];
+			u32 wspr;	/* 0x48 rw */
+		};
+		struct _watchdog *wd2_base = (struct watchdog *)WD2_BASE;
+		struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
+
+		printf("idlest_wkup = %08x\n", readl(&prcm_base->idlest_wkup));
+		printf("widr = %08x\n", readl(&wd2_base->widr));
+		printf("wd_sysconfig = %08x\n", readl(&wd2_base->wd_sysconfig));
+		printf("ws_sysstatus = %08x\n", readl(&wd2_base->ws_sysstatus));
+		printf("wisr = %08x\n", readl(&wd2_base->wisr));
+		printf("wier = %08x\n", readl(&wd2_base->wier));
+		printf("wclr = %08x\n", readl(&wd2_base->wclr));
+		printf("wcrr = %08x\n", readl(&wd2_base->wcrr));
+		printf("wldr = %08x\n", readl(&wd2_base->wldr));
+		printf("wtgr = %08x\n", readl(&wd2_base->wtgr));
+		printf("wwps = %08x\n", readl(&wd2_base->wwps));
+		printf("wspr = %08x\n", readl(&wd2_base->wspr));
+				  
+		writel(WD_UNLOCK2, &wd2_base->wspr);
+		myudelay(100);
+		writel(WD_UNLOCK1, &wd2_base->wspr);
+		myudelay(100);
+		writel(WD_UNLOCK2, &wd2_base->wspr);
+		myudelay(100);
+		writel(WD_UNLOCK1, &wd2_base->wspr);
+		myudelay(100);
+		writel(WD_UNLOCK2, &wd2_base->wspr);
+
+		myudelay(10000); // so that we can see if the counter counts...
+		
+		printf("idlest_wkup = %08x\n", readl(&prcm_base->idlest_wkup));
+		printf("widr = %08x\n", readl(&wd2_base->widr));
+		printf("wd_sysconfig = %08x\n", readl(&wd2_base->wd_sysconfig));
+		printf("ws_sysstatus = %08x\n", readl(&wd2_base->ws_sysstatus));
+		printf("wisr = %08x\n", readl(&wd2_base->wisr));
+		printf("wier = %08x\n", readl(&wd2_base->wier));
+		printf("wclr = %08x\n", readl(&wd2_base->wclr));
+		printf("wcrr = %08x\n", readl(&wd2_base->wcrr));
+		printf("wldr = %08x\n", readl(&wd2_base->wldr));
+		printf("wtgr = %08x\n", readl(&wd2_base->wtgr));
+		printf("wwps = %08x\n", readl(&wd2_base->wwps));
+		printf("wspr = %08x\n", readl(&wd2_base->wspr));
+
+		writel(readl(&wd2_base->wtgr) + 1, &wd2_base->wtgr);
+		
+		printf("idlest_wkup = %08x\n", readl(&prcm_base->idlest_wkup));
+		printf("widr = %08x\n", readl(&wd2_base->widr));
+		printf("wd_sysconfig = %08x\n", readl(&wd2_base->wd_sysconfig));
+		printf("ws_sysstatus = %08x\n", readl(&wd2_base->ws_sysstatus));
+		printf("wisr = %08x\n", readl(&wd2_base->wisr));
+		printf("wier = %08x\n", readl(&wd2_base->wier));
+		printf("wclr = %08x\n", readl(&wd2_base->wclr));
+		printf("wcrr = %08x\n", readl(&wd2_base->wcrr));
+		printf("wldr = %08x\n", readl(&wd2_base->wldr));
+		printf("wtgr = %08x\n", readl(&wd2_base->wtgr));
+		printf("wwps = %08x\n", readl(&wd2_base->wwps));
+		printf("wspr = %08x\n", readl(&wd2_base->wspr));
+		
+	}
+#endif				  
+				  
+	return 0;
+}
+
+/*
+ * Routine: set_muxconf_regs
+ * Description: Setting up the configuration Mux registers specific to the
+ *		hardware. Many pins need to be moved from protect to primary
+ *		mode.
+ */
+void set_muxconf_regs(void)
+{
+	MUX_BEAGLE();
+	MUX_BEAGLE_GTA04();
+}
+
+#ifdef CONFIG_GENERIC_MMC
+int board_mmc_init(bd_t *bis)
+{
+	omap_mmc_init(0);
+	return 0;
+}
+#endif
diff --git a/u-boot/board/goldelico/gta04/gta04.h b/u-boot/board/goldelico/gta04/gta04.h
new file mode 100644
index 0000000..bd56326
--- /dev/null
+++ b/u-boot/board/goldelico/gta04/gta04.h
@@ -0,0 +1,601 @@
+/*
+ * (C) Copyright 2008
+ * Dirk Behme <dirk.behme@gmail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _GTA04_H_
+#define _GTA04_H_
+
+const omap3_sysinfo sysinfo = {
+	DDR_STACKED,
+	"GTA04",
+#if defined(CONFIG_ENV_IS_IN_ONENAND)
+	"OneNAND",
+#else
+	"NAND",
+#endif
+};
+
+/* BeagleBoard revisions */
+#define REVISION_AXBX	0x7
+#define REVISION_CX	0x6
+#define REVISION_C4	0x5
+#define REVISION_XM	0x0
+
+/*
+ * IEN  - Input Enable
+ * IDIS - Input Disable
+ * PTD  - Pull type Down
+ * PTU  - Pull type Up
+ * DIS  - Pull type selection is inactive
+ * EN   - Pull type selection is active
+ * M0   - Mode 0
+ * The commented string gives the final mux configuration for that pin
+ */
+#define MUX_BEAGLE() \
+/*SDRC*/\
+MUX_VAL(CP(SDRC_D0),		(IEN  | PTD | DIS | M0)) /*SDRC_D0*/\
+MUX_VAL(CP(SDRC_D1),		(IEN  | PTD | DIS | M0)) /*SDRC_D1*/\
+MUX_VAL(CP(SDRC_D2),		(IEN  | PTD | DIS | M0)) /*SDRC_D2*/\
+MUX_VAL(CP(SDRC_D3),		(IEN  | PTD | DIS | M0)) /*SDRC_D3*/\
+MUX_VAL(CP(SDRC_D4),		(IEN  | PTD | DIS | M0)) /*SDRC_D4*/\
+MUX_VAL(CP(SDRC_D5),		(IEN  | PTD | DIS | M0)) /*SDRC_D5*/\
+MUX_VAL(CP(SDRC_D6),		(IEN  | PTD | DIS | M0)) /*SDRC_D6*/\
+MUX_VAL(CP(SDRC_D7),		(IEN  | PTD | DIS | M0)) /*SDRC_D7*/\
+MUX_VAL(CP(SDRC_D8),		(IEN  | PTD | DIS | M0)) /*SDRC_D8*/\
+MUX_VAL(CP(SDRC_D9),		(IEN  | PTD | DIS | M0)) /*SDRC_D9*/\
+MUX_VAL(CP(SDRC_D10),		(IEN  | PTD | DIS | M0)) /*SDRC_D10*/\
+MUX_VAL(CP(SDRC_D11),		(IEN  | PTD | DIS | M0)) /*SDRC_D11*/\
+MUX_VAL(CP(SDRC_D12),		(IEN  | PTD | DIS | M0)) /*SDRC_D12*/\
+MUX_VAL(CP(SDRC_D13),		(IEN  | PTD | DIS | M0)) /*SDRC_D13*/\
+MUX_VAL(CP(SDRC_D14),		(IEN  | PTD | DIS | M0)) /*SDRC_D14*/\
+MUX_VAL(CP(SDRC_D15),		(IEN  | PTD | DIS | M0)) /*SDRC_D15*/\
+MUX_VAL(CP(SDRC_D16),		(IEN  | PTD | DIS | M0)) /*SDRC_D16*/\
+MUX_VAL(CP(SDRC_D17),		(IEN  | PTD | DIS | M0)) /*SDRC_D17*/\
+MUX_VAL(CP(SDRC_D18),		(IEN  | PTD | DIS | M0)) /*SDRC_D18*/\
+MUX_VAL(CP(SDRC_D19),		(IEN  | PTD | DIS | M0)) /*SDRC_D19*/\
+MUX_VAL(CP(SDRC_D20),		(IEN  | PTD | DIS | M0)) /*SDRC_D20*/\
+MUX_VAL(CP(SDRC_D21),		(IEN  | PTD | DIS | M0)) /*SDRC_D21*/\
+MUX_VAL(CP(SDRC_D22),		(IEN  | PTD | DIS | M0)) /*SDRC_D22*/\
+MUX_VAL(CP(SDRC_D23),		(IEN  | PTD | DIS | M0)) /*SDRC_D23*/\
+MUX_VAL(CP(SDRC_D24),		(IEN  | PTD | DIS | M0)) /*SDRC_D24*/\
+MUX_VAL(CP(SDRC_D25),		(IEN  | PTD | DIS | M0)) /*SDRC_D25*/\
+MUX_VAL(CP(SDRC_D26),		(IEN  | PTD | DIS | M0)) /*SDRC_D26*/\
+MUX_VAL(CP(SDRC_D27),		(IEN  | PTD | DIS | M0)) /*SDRC_D27*/\
+MUX_VAL(CP(SDRC_D28),		(IEN  | PTD | DIS | M0)) /*SDRC_D28*/\
+MUX_VAL(CP(SDRC_D29),		(IEN  | PTD | DIS | M0)) /*SDRC_D29*/\
+MUX_VAL(CP(SDRC_D30),		(IEN  | PTD | DIS | M0)) /*SDRC_D30*/\
+MUX_VAL(CP(SDRC_D31),		(IEN  | PTD | DIS | M0)) /*SDRC_D31*/\
+MUX_VAL(CP(SDRC_CLK),		(IEN  | PTD | DIS | M0)) /*SDRC_CLK*/\
+MUX_VAL(CP(SDRC_DQS0),		(IEN  | PTD | DIS | M0)) /*SDRC_DQS0*/\
+MUX_VAL(CP(SDRC_DQS1),		(IEN  | PTD | DIS | M0)) /*SDRC_DQS1*/\
+MUX_VAL(CP(SDRC_DQS2),		(IEN  | PTD | DIS | M0)) /*SDRC_DQS2*/\
+MUX_VAL(CP(SDRC_DQS3),		(IEN  | PTD | DIS | M0)) /*SDRC_DQS3*/\
+/*GPMC*/\
+MUX_VAL(CP(GPMC_A1),		(IDIS | PTD | DIS | M0)) /*GPMC_A1*/\
+MUX_VAL(CP(GPMC_A2),		(IDIS | PTD | DIS | M0)) /*GPMC_A2*/\
+MUX_VAL(CP(GPMC_A3),		(IDIS | PTD | DIS | M0)) /*GPMC_A3*/\
+MUX_VAL(CP(GPMC_A4),		(IDIS | PTD | DIS | M0)) /*GPMC_A4*/\
+MUX_VAL(CP(GPMC_A5),		(IDIS | PTD | DIS | M0)) /*GPMC_A5*/\
+MUX_VAL(CP(GPMC_A6),		(IDIS | PTD | DIS | M0)) /*GPMC_A6*/\
+MUX_VAL(CP(GPMC_A7),		(IDIS | PTD | DIS | M0)) /*GPMC_A7*/\
+MUX_VAL(CP(GPMC_A8),		(IDIS | PTD | DIS | M0)) /*GPMC_A8*/\
+MUX_VAL(CP(GPMC_A9),		(IDIS | PTD | DIS | M0)) /*GPMC_A9*/\
+MUX_VAL(CP(GPMC_A10),		(IDIS | PTD | DIS | M0)) /*GPMC_A10*/\
+MUX_VAL(CP(GPMC_D0),		(IEN  | PTD | DIS | M0)) /*GPMC_D0*/\
+MUX_VAL(CP(GPMC_D1),		(IEN  | PTD | DIS | M0)) /*GPMC_D1*/\
+MUX_VAL(CP(GPMC_D2),		(IEN  | PTD | DIS | M0)) /*GPMC_D2*/\
+MUX_VAL(CP(GPMC_D3),		(IEN  | PTD | DIS | M0)) /*GPMC_D3*/\
+MUX_VAL(CP(GPMC_D4),		(IEN  | PTD | DIS | M0)) /*GPMC_D4*/\
+MUX_VAL(CP(GPMC_D5),		(IEN  | PTD | DIS | M0)) /*GPMC_D5*/\
+MUX_VAL(CP(GPMC_D6),		(IEN  | PTD | DIS | M0)) /*GPMC_D6*/\
+MUX_VAL(CP(GPMC_D7),		(IEN  | PTD | DIS | M0)) /*GPMC_D7*/\
+MUX_VAL(CP(GPMC_D8),		(IEN  | PTD | DIS | M0)) /*GPMC_D8*/\
+MUX_VAL(CP(GPMC_D9),		(IEN  | PTD | DIS | M0)) /*GPMC_D9*/\
+MUX_VAL(CP(GPMC_D10),		(IEN  | PTD | DIS | M0)) /*GPMC_D10*/\
+MUX_VAL(CP(GPMC_D11),		(IEN  | PTD | DIS | M0)) /*GPMC_D11*/\
+MUX_VAL(CP(GPMC_D12),		(IEN  | PTD | DIS | M0)) /*GPMC_D12*/\
+MUX_VAL(CP(GPMC_D13),		(IEN  | PTD | DIS | M0)) /*GPMC_D13*/\
+MUX_VAL(CP(GPMC_D14),		(IEN  | PTD | DIS | M0)) /*GPMC_D14*/\
+MUX_VAL(CP(GPMC_D15),		(IEN  | PTD | DIS | M0)) /*GPMC_D15*/\
+MUX_VAL(CP(GPMC_NCS0),		(IDIS | PTU | EN  | M0)) /*GPMC_nCS0*/\
+MUX_VAL(CP(GPMC_NCS1),		(IDIS | PTU | EN  | M0)) /*GPMC_nCS1*/\
+MUX_VAL(CP(GPMC_NCS2),		(IDIS | PTU | EN  | M0)) /*GPMC_nCS2*/\
+MUX_VAL(CP(GPMC_NCS3),		(IDIS | PTU | EN  | M0)) /*GPMC_nCS3*/\
+MUX_VAL(CP(GPMC_NCS4),		(IDIS | PTU | EN  | M0)) /*GPMC_nCS4*/\
+MUX_VAL(CP(GPMC_NCS5),		(IDIS | PTD | DIS | M0)) /*GPMC_nCS5*/\
+MUX_VAL(CP(GPMC_NCS6),		(IEN  | PTD | DIS | M1)) /*SYS_nDMA_REQ2*/\
+MUX_VAL(CP(GPMC_NCS7),		(IEN  | PTU | EN  | M1)) /*SYS_nDMA_REQ3*/\
+MUX_VAL(CP(GPMC_NBE1),		(IEN  | PTD | DIS | M0)) /*GPMC_nBE1*/\
+MUX_VAL(CP(GPMC_WAIT2),		(IEN  | PTU | EN  | M0)) /*GPMC_WAIT2*/\
+MUX_VAL(CP(GPMC_WAIT3),		(IEN  | PTU | EN  | M0)) /*GPMC_WAIT3*/\
+MUX_VAL(CP(GPMC_CLK),		(IDIS | PTD | DIS | M0)) /*GPMC_CLK*/\
+MUX_VAL(CP(GPMC_NADV_ALE),	(IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\
+MUX_VAL(CP(GPMC_NOE),		(IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\
+MUX_VAL(CP(GPMC_NWE),		(IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\
+MUX_VAL(CP(GPMC_NBE0_CLE),	(IDIS | PTD | DIS | M0)) /*GPMC_nBE0_CLE*/\
+MUX_VAL(CP(GPMC_NWP),		(IEN  | PTD | DIS | M0)) /*GPMC_nWP*/\
+MUX_VAL(CP(GPMC_WAIT0),		(IEN  | PTU | EN  | M0)) /*GPMC_WAIT0*/\
+MUX_VAL(CP(GPMC_WAIT1),		(IEN  | PTU | EN  | M0)) /*GPMC_WAIT1*/\
+/*DSS*/\
+MUX_VAL(CP(DSS_PCLK),		(IDIS | PTD | DIS | M0)) /*DSS_PCLK*/\
+MUX_VAL(CP(DSS_HSYNC),		(IDIS | PTD | DIS | M0)) /*DSS_HSYNC*/\
+MUX_VAL(CP(DSS_VSYNC),		(IDIS | PTD | DIS | M0)) /*DSS_VSYNC*/\
+MUX_VAL(CP(DSS_ACBIAS),		(IDIS | PTD | DIS | M0)) /*DSS_ACBIAS*/\
+MUX_VAL(CP(DSS_DATA0),		(IDIS | PTD | DIS | M0)) /*DSS_DATA0*/\
+MUX_VAL(CP(DSS_DATA1),		(IDIS | PTD | DIS | M0)) /*DSS_DATA1*/\
+MUX_VAL(CP(DSS_DATA2),		(IDIS | PTD | DIS | M0)) /*DSS_DATA2*/\
+MUX_VAL(CP(DSS_DATA3),		(IDIS | PTD | DIS | M0)) /*DSS_DATA3*/\
+MUX_VAL(CP(DSS_DATA4),		(IDIS | PTD | DIS | M0)) /*DSS_DATA4*/\
+MUX_VAL(CP(DSS_DATA5),		(IDIS | PTD | DIS | M0)) /*DSS_DATA5*/\
+MUX_VAL(CP(DSS_DATA6),		(IDIS | PTD | DIS | M0)) /*DSS_DATA6*/\
+MUX_VAL(CP(DSS_DATA7),		(IDIS | PTD | DIS | M0)) /*DSS_DATA7*/\
+MUX_VAL(CP(DSS_DATA8),		(IDIS | PTD | DIS | M0)) /*DSS_DATA8*/\
+MUX_VAL(CP(DSS_DATA9),		(IDIS | PTD | DIS | M0)) /*DSS_DATA9*/\
+MUX_VAL(CP(DSS_DATA10),		(IDIS | PTD | DIS | M0)) /*DSS_DATA10*/\
+MUX_VAL(CP(DSS_DATA11),		(IDIS | PTD | DIS | M0)) /*DSS_DATA11*/\
+MUX_VAL(CP(DSS_DATA12),		(IDIS | PTD | DIS | M0)) /*DSS_DATA12*/\
+MUX_VAL(CP(DSS_DATA13),		(IDIS | PTD | DIS | M0)) /*DSS_DATA13*/\
+MUX_VAL(CP(DSS_DATA14),		(IDIS | PTD | DIS | M0)) /*DSS_DATA14*/\
+MUX_VAL(CP(DSS_DATA15),		(IDIS | PTD | DIS | M0)) /*DSS_DATA15*/\
+MUX_VAL(CP(DSS_DATA16),		(IDIS | PTD | DIS | M0)) /*DSS_DATA16*/\
+MUX_VAL(CP(DSS_DATA17),		(IDIS | PTD | DIS | M0)) /*DSS_DATA17*/\
+MUX_VAL(CP(DSS_DATA18),		(IDIS | PTD | DIS | M0)) /*DSS_DATA18*/\
+MUX_VAL(CP(DSS_DATA19),		(IDIS | PTD | DIS | M0)) /*DSS_DATA19*/\
+MUX_VAL(CP(DSS_DATA20),		(IDIS | PTD | DIS | M0)) /*DSS_DATA20*/\
+MUX_VAL(CP(DSS_DATA21),		(IDIS | PTD | DIS | M0)) /*DSS_DATA21*/\
+MUX_VAL(CP(DSS_DATA22),		(IDIS | PTD | DIS | M0)) /*DSS_DATA22*/\
+MUX_VAL(CP(DSS_DATA23),		(IDIS | PTD | DIS | M0)) /*DSS_DATA23*/\
+/*CAMERA*/\
+MUX_VAL(CP(CAM_HS),		(IEN  | PTU | EN  | M0)) /*CAM_HS */\
+MUX_VAL(CP(CAM_VS),		(IEN  | PTU | EN  | M0)) /*CAM_VS */\
+MUX_VAL(CP(CAM_XCLKA),		(IDIS | PTD | DIS | M0)) /*CAM_XCLKA*/\
+MUX_VAL(CP(CAM_PCLK),		(IEN  | PTU | EN  | M0)) /*CAM_PCLK*/\
+MUX_VAL(CP(CAM_FLD),		(IDIS | PTD | DIS | M4)) /*GPIO_98*/\
+MUX_VAL(CP(CAM_D0),		(IEN  | PTD | DIS | M0)) /*CAM_D0*/\
+MUX_VAL(CP(CAM_D1),		(IEN  | PTD | DIS | M0)) /*CAM_D1*/\
+MUX_VAL(CP(CAM_D2),		(IEN  | PTD | DIS | M0)) /*CAM_D2*/\
+MUX_VAL(CP(CAM_D3),		(IEN  | PTD | DIS | M0)) /*CAM_D3*/\
+MUX_VAL(CP(CAM_D4),		(IEN  | PTD | DIS | M0)) /*CAM_D4*/\
+MUX_VAL(CP(CAM_D5),		(IEN  | PTD | DIS | M0)) /*CAM_D5*/\
+MUX_VAL(CP(CAM_D6),		(IEN  | PTD | DIS | M0)) /*CAM_D6*/\
+MUX_VAL(CP(CAM_D7),		(IEN  | PTD | DIS | M0)) /*CAM_D7*/\
+MUX_VAL(CP(CAM_D8),		(IEN  | PTD | DIS | M0)) /*CAM_D8*/\
+MUX_VAL(CP(CAM_D9),		(IEN  | PTD | DIS | M0)) /*CAM_D9*/\
+MUX_VAL(CP(CAM_D10),		(IEN  | PTD | DIS | M0)) /*CAM_D10*/\
+MUX_VAL(CP(CAM_D11),		(IEN  | PTD | DIS | M0)) /*CAM_D11*/\
+MUX_VAL(CP(CAM_XCLKB),		(IDIS | PTD | DIS | M0)) /*CAM_XCLKB*/\
+MUX_VAL(CP(CAM_WEN),		(IEN  | PTD | DIS | M4)) /*GPIO_167*/\
+MUX_VAL(CP(CAM_STROBE),		(IDIS | PTD | DIS | M0)) /*CAM_STROBE*/\
+MUX_VAL(CP(CSI2_DX0),		(IEN  | PTD | DIS | M0)) /*CSI2_DX0*/\
+MUX_VAL(CP(CSI2_DY0),		(IEN  | PTD | DIS | M0)) /*CSI2_DY0*/\
+MUX_VAL(CP(CSI2_DX1),		(IEN  | PTD | DIS | M0)) /*CSI2_DX1*/\
+MUX_VAL(CP(CSI2_DY1),		(IEN  | PTD | DIS | M0)) /*CSI2_DY1*/\
+/*Audio Interface */\
+MUX_VAL(CP(MCBSP2_FSX),		(IEN  | PTD | DIS | M0)) /*McBSP2_FSX*/\
+MUX_VAL(CP(MCBSP2_CLKX),	(IEN  | PTD | DIS | M0)) /*McBSP2_CLKX*/\
+MUX_VAL(CP(MCBSP2_DR),		(IEN  | PTD | DIS | M0)) /*McBSP2_DR*/\
+MUX_VAL(CP(MCBSP2_DX),		(IDIS | PTD | DIS | M0)) /*McBSP2_DX*/\
+/*Expansion card */\
+MUX_VAL(CP(MMC1_CLK),		(IDIS | PTU | EN  | M0)) /*MMC1_CLK*/\
+MUX_VAL(CP(MMC1_CMD),		(IEN  | PTU | EN  | M0)) /*MMC1_CMD*/\
+MUX_VAL(CP(MMC1_DAT0),		(IEN  | PTU | EN  | M0)) /*MMC1_DAT0*/\
+MUX_VAL(CP(MMC1_DAT1),		(IEN  | PTU | EN  | M0)) /*MMC1_DAT1*/\
+MUX_VAL(CP(MMC1_DAT2),		(IEN  | PTU | EN  | M0)) /*MMC1_DAT2*/\
+MUX_VAL(CP(MMC1_DAT3),		(IEN  | PTU | EN  | M0)) /*MMC1_DAT3*/\
+MUX_VAL(CP(MMC1_DAT4),		(IEN  | PTU | EN  | M0)) /*MMC1_DAT4*/\
+MUX_VAL(CP(MMC1_DAT5),		(IEN  | PTU | EN  | M0)) /*MMC1_DAT5*/\
+MUX_VAL(CP(MMC1_DAT6),		(IEN  | PTU | EN  | M0)) /*MMC1_DAT6*/\
+MUX_VAL(CP(MMC1_DAT7),		(IEN  | PTU | EN  | M0)) /*MMC1_DAT7*/\
+/*Wireless LAN */\
+MUX_VAL(CP(MMC2_CLK),		(IEN  | PTU | EN  | M4)) /*GPIO_130*/\
+MUX_VAL(CP(MMC2_CMD),		(IEN  | PTU | EN  | M4)) /*GPIO_131*/\
+MUX_VAL(CP(MMC2_DAT0),		(IEN  | PTU | EN  | M4)) /*GPIO_132*/\
+MUX_VAL(CP(MMC2_DAT1),		(IEN  | PTU | EN  | M4)) /*GPIO_133*/\
+MUX_VAL(CP(MMC2_DAT2),		(IEN  | PTU | EN  | M4)) /*GPIO_134*/\
+MUX_VAL(CP(MMC2_DAT3),		(IEN  | PTU | EN  | M4)) /*GPIO_135*/\
+MUX_VAL(CP(MMC2_DAT4),		(IEN  | PTU | EN  | M4)) /*GPIO_136*/\
+MUX_VAL(CP(MMC2_DAT5),		(IEN  | PTU | EN  | M4)) /*GPIO_137*/\
+MUX_VAL(CP(MMC2_DAT6),		(IEN  | PTU | EN  | M4)) /*GPIO_138*/\
+MUX_VAL(CP(MMC2_DAT7),		(IEN  | PTU | EN  | M4)) /*GPIO_139*/\
+/*Bluetooth*/\
+MUX_VAL(CP(MCBSP3_DX),		(IEN  | PTD | DIS | M1)) /*UART2_CTS*/\
+MUX_VAL(CP(MCBSP3_DR),		(IDIS | PTD | DIS | M1)) /*UART2_RTS*/\
+MUX_VAL(CP(MCBSP3_CLKX),	(IDIS | PTD | DIS | M1)) /*UART2_TX*/\
+MUX_VAL(CP(MCBSP3_FSX),		(IEN  | PTD | DIS | M1)) /*UART2_RX*/\
+MUX_VAL(CP(UART2_CTS),		(IEN  | PTD | DIS | M4)) /*GPIO_144*/\
+MUX_VAL(CP(UART2_RTS),		(IEN  | PTD | DIS | M4)) /*GPIO_145*/\
+MUX_VAL(CP(UART2_TX),		(IEN  | PTD | DIS | M4)) /*GPIO_146*/\
+MUX_VAL(CP(UART2_RX),		(IEN  | PTD | DIS | M4)) /*GPIO_147*/\
+/*Modem Interface */\
+MUX_VAL(CP(UART1_TX),		(IDIS | PTD | DIS | M0)) /*UART1_TX*/\
+MUX_VAL(CP(UART1_RTS),		(IDIS | PTD | DIS | M4)) /*GPIO_149*/ \
+MUX_VAL(CP(UART1_CTS),		(IDIS | PTD | DIS | M4)) /*GPIO_150*/ \
+MUX_VAL(CP(UART1_RX),		(IEN  | PTD | DIS | M0)) /*UART1_RX*/\
+MUX_VAL(CP(MCBSP4_CLKX),	(IEN  | PTD | DIS | M1)) /*SSI1_DAT_RX*/\
+MUX_VAL(CP(MCBSP4_DR),		(IEN  | PTD | DIS | M1)) /*SSI1_FLAG_RX*/\
+MUX_VAL(CP(MCBSP4_DX),		(IEN  | PTD | DIS | M1)) /*SSI1_RDY_RX*/\
+MUX_VAL(CP(MCBSP4_FSX),		(IEN  | PTD | DIS | M1)) /*SSI1_WAKE*/\
+MUX_VAL(CP(MCBSP1_CLKR),	(IDIS | PTD | DIS | M4)) /*GPIO_156*/\
+MUX_VAL(CP(MCBSP1_FSR),		(IDIS | PTU | EN  | M4)) /*GPIO_157*/\
+MUX_VAL(CP(MCBSP1_DX),		(IDIS | PTD | DIS | M4)) /*GPIO_158*/\
+MUX_VAL(CP(MCBSP1_DR),		(IDIS | PTD | DIS | M4)) /*GPIO_159*/\
+MUX_VAL(CP(MCBSP_CLKS),		(IEN  | PTU | DIS | M0)) /*McBSP_CLKS*/\
+MUX_VAL(CP(MCBSP1_FSX),		(IDIS | PTD | DIS | M4)) /*GPIO_161*/\
+MUX_VAL(CP(MCBSP1_CLKX),	(IDIS | PTD | DIS | M4)) /*GPIO_162*/\
+/*Serial Interface*/\
+MUX_VAL(CP(UART3_CTS_RCTX),	(IEN  | PTD | EN  | M0)) /*UART3_CTS_RCTX*/\
+MUX_VAL(CP(UART3_RTS_SD),	(IDIS | PTD | DIS | M0)) /*UART3_RTS_SD */\
+MUX_VAL(CP(UART3_RX_IRRX),	(IEN  | PTD | DIS | M0)) /*UART3_RX_IRRX*/\
+MUX_VAL(CP(UART3_TX_IRTX),	(IDIS | PTD | DIS | M0)) /*UART3_TX_IRTX*/\
+MUX_VAL(CP(HSUSB0_CLK),		(IEN  | PTD | DIS | M0)) /*HSUSB0_CLK*/\
+MUX_VAL(CP(HSUSB0_STP),		(IDIS | PTU | EN  | M0)) /*HSUSB0_STP*/\
+MUX_VAL(CP(HSUSB0_DIR),		(IEN  | PTD | DIS | M0)) /*HSUSB0_DIR*/\
+MUX_VAL(CP(HSUSB0_NXT),		(IEN  | PTD | DIS | M0)) /*HSUSB0_NXT*/\
+MUX_VAL(CP(HSUSB0_DATA0),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA0*/\
+MUX_VAL(CP(HSUSB0_DATA1),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA1*/\
+MUX_VAL(CP(HSUSB0_DATA2),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA2*/\
+MUX_VAL(CP(HSUSB0_DATA3),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA3*/\
+MUX_VAL(CP(HSUSB0_DATA4),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA4*/\
+MUX_VAL(CP(HSUSB0_DATA5),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA5*/\
+MUX_VAL(CP(HSUSB0_DATA6),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA6*/\
+MUX_VAL(CP(HSUSB0_DATA7),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA7*/\
+MUX_VAL(CP(I2C1_SCL),		(IEN  | PTU | EN  | M0)) /*I2C1_SCL*/\
+MUX_VAL(CP(I2C1_SDA),		(IEN  | PTU | EN  | M0)) /*I2C1_SDA*/\
+MUX_VAL(CP(I2C2_SCL),		(IEN  | PTU | EN  | M0)) /*I2C2_SCL*/\
+MUX_VAL(CP(I2C2_SDA),		(IEN  | PTU | EN  | M0)) /*I2C2_SDA*/\
+MUX_VAL(CP(I2C3_SCL),		(IEN  | PTU | EN  | M0)) /*I2C3_SCL*/\
+MUX_VAL(CP(I2C3_SDA),		(IEN  | PTU | EN  | M0)) /*I2C3_SDA*/\
+MUX_VAL(CP(I2C4_SCL),		(IEN  | PTU | EN  | M0)) /*I2C4_SCL*/\
+MUX_VAL(CP(I2C4_SDA),		(IEN  | PTU | EN  | M0)) /*I2C4_SDA*/\
+MUX_VAL(CP(HDQ_SIO),		(IDIS | PTU | EN  | M4)) /*GPIO_170*/\
+MUX_VAL(CP(MCSPI1_CLK),		(IEN  | PTU | EN  | M4)) /*GPIO_171*/\
+MUX_VAL(CP(MCSPI1_SIMO),	(IEN  | PTU | EN  | M4)) /*GPIO_172*/\
+MUX_VAL(CP(MCSPI1_SOMI),	(IEN  | PTU | EN  | M4)) /*GPIO_173*/\
+MUX_VAL(CP(MCSPI1_CS0),		(IEN  | PTD | EN  | M0)) /*McSPI1_CS0*/\
+MUX_VAL(CP(MCSPI1_CS1),		(IDIS | PTD | EN  | M0)) /*McSPI1_CS1*/\
+MUX_VAL(CP(MCSPI1_CS2),		(IDIS | PTD | DIS | M4)) /*GPIO_176*/\
+/* USB EHCI (port 2) */\
+MUX_VAL(CP(MCSPI1_CS3),		(IEN  | PTU | DIS | M3)) /*HSUSB2_DATA2*/\
+MUX_VAL(CP(MCSPI2_CLK),		(IEN  | PTU | DIS | M3)) /*HSUSB2_DATA7*/\
+MUX_VAL(CP(MCSPI2_SIMO),	(IEN  | PTU | DIS | M3)) /*HSUSB2_DATA4*/\
+MUX_VAL(CP(MCSPI2_SOMI),	(IEN  | PTU | DIS | M3)) /*HSUSB2_DATA5*/\
+MUX_VAL(CP(MCSPI2_CS0),		(IEN  | PTU | DIS | M3)) /*HSUSB2_DATA6*/\
+MUX_VAL(CP(MCSPI2_CS1),		(IEN  | PTU | DIS | M3)) /*HSUSB2_DATA3*/\
+MUX_VAL(CP(ETK_D10_ES2),	(IEN  | PTU | DIS | M3)) /*HSUSB2_CLK*/\
+MUX_VAL(CP(ETK_D11_ES2),	(IDIS | PTU | EN  | M3)) /*HSUSB2_STP*/\
+MUX_VAL(CP(ETK_D12_ES2),	(IEN  | PTU | DIS | M3)) /*HSUSB2_DIR*/\
+MUX_VAL(CP(ETK_D13_ES2),	(IEN  | PTU | DIS | M3)) /*HSUSB2_NXT*/\
+MUX_VAL(CP(ETK_D14_ES2),	(IEN  | PTU | DIS | M3)) /*HSUSB2_DATA0*/\
+MUX_VAL(CP(ETK_D15_ES2),	(IEN  | PTU | DIS | M3)) /*HSUSB2_DATA1*/\
+/*Control and debug */\
+MUX_VAL(CP(SYS_32K),		(IEN  | PTD | DIS | M0)) /*SYS_32K*/\
+MUX_VAL(CP(SYS_CLKREQ),		(IEN  | /*PTD*/PTU | /*DIS*/EN | M0)) /*SYS_CLKREQ*/\
+MUX_VAL(CP(SYS_NIRQ),		(IEN  | PTU | EN  | M0)) /*SYS_nIRQ*/\
+MUX_VAL(CP(SYS_BOOT0),		(IEN  | PTD | DIS | M4)) /*GPIO_2*/\
+MUX_VAL(CP(SYS_BOOT1),		(IEN  | PTD | DIS | M4)) /*GPIO_3*/\
+MUX_VAL(CP(SYS_BOOT2),		(IEN  | PTD | DIS | M4)) /*GPIO_4 - MMC1_WP*/\
+MUX_VAL(CP(SYS_BOOT3),		(IEN  | PTD | DIS | M4)) /*GPIO_5*/\
+MUX_VAL(CP(SYS_BOOT4),		(IEN  | PTD | DIS | M4)) /*GPIO_6*/\
+MUX_VAL(CP(SYS_BOOT5),		(IEN  | PTD | DIS | M4)) /*GPIO_7*/\
+MUX_VAL(CP(SYS_BOOT6),		(IDIS | PTD | DIS | M4)) /*GPIO_8*/ \
+MUX_VAL(CP(SYS_OFF_MODE),	(IEN  | PTD | DIS | M0)) /*GPIO_9 / SYS_OFF_MODE*/\
+MUX_VAL(CP(SYS_CLKOUT1),	(IEN  | PTD | DIS | M4)) /*GPIO_10 / SYS_CLKOUT1*/\
+MUX_VAL(CP(SYS_CLKOUT2),	(IEN  | PTU | EN  | M4)) /*GPIO_186*/\
+/* should be removed or initialized correctly from the beginning since it may result in a glitch on these pins that we use as GPIOs */\
+MUX_VAL(CP(ETK_CLK_ES2),	(IDIS | PTU | EN  | M3)) /*HSUSB1_STP*/\
+MUX_VAL(CP(ETK_CTL_ES2),	(IDIS | PTU | DIS | M3)) /*HSUSB1_CLK*/\
+MUX_VAL(CP(ETK_D0_ES2),		(IEN  | PTU | DIS | M1)) /*MCSPI3_SIMO*/\
+MUX_VAL(CP(ETK_D1_ES2),		(IEN  | PTU | DIS | M1)) /*MCSPI3_SOMI*/\
+MUX_VAL(CP(ETK_D2_ES2),		(IEN  | PTU | DIS | M1)) /*MCSPI3_CS0*/\
+MUX_VAL(CP(ETK_D3_ES2),		(IEN  | PTU | DIS | M1)) /*MCSPI3_CLK*/\
+MUX_VAL(CP(ETK_D4_ES2),		(IEN  | PTU | DIS | M3)) /*HSUSB1_DATA4*/\
+MUX_VAL(CP(ETK_D5_ES2),		(IEN  | PTU | DIS | M3)) /*HSUSB1_DATA5*/\
+MUX_VAL(CP(ETK_D6_ES2),		(IEN  | PTU | DIS | M3)) /*HSUSB1_DATA6*/\
+MUX_VAL(CP(ETK_D7_ES2),		(IEN  | PTU | DIS | M3)) /*HSUSB1_DATA3*/\
+MUX_VAL(CP(ETK_D8_ES2),		(IEN  | PTU | DIS | M3)) /*HSUSB1_DIR*/\
+MUX_VAL(CP(ETK_D9_ES2),		(IEN  | PTU | DIS | M3)) /*HSUSB1_NXT*/\
+/* end remove */\
+MUX_VAL(CP(D2D_MCAD1),		(IEN  | PTD | EN  | M0)) /*d2d_mcad1*/\
+MUX_VAL(CP(D2D_MCAD2),		(IEN  | PTD | EN  | M0)) /*d2d_mcad2*/\
+MUX_VAL(CP(D2D_MCAD3),		(IEN  | PTD | EN  | M0)) /*d2d_mcad3*/\
+MUX_VAL(CP(D2D_MCAD4),		(IEN  | PTD | EN  | M0)) /*d2d_mcad4*/\
+MUX_VAL(CP(D2D_MCAD5),		(IEN  | PTD | EN  | M0)) /*d2d_mcad5*/\
+MUX_VAL(CP(D2D_MCAD6),		(IEN  | PTD | EN  | M0)) /*d2d_mcad6*/\
+MUX_VAL(CP(D2D_MCAD7),		(IEN  | PTD | EN  | M0)) /*d2d_mcad7*/\
+MUX_VAL(CP(D2D_MCAD8),		(IEN  | PTD | EN  | M0)) /*d2d_mcad8*/\
+MUX_VAL(CP(D2D_MCAD9),		(IEN  | PTD | EN  | M0)) /*d2d_mcad9*/\
+MUX_VAL(CP(D2D_MCAD10),		(IEN  | PTD | EN  | M0)) /*d2d_mcad10*/\
+MUX_VAL(CP(D2D_MCAD11),		(IEN  | PTD | EN  | M0)) /*d2d_mcad11*/\
+MUX_VAL(CP(D2D_MCAD12),		(IEN  | PTD | EN  | M0)) /*d2d_mcad12*/\
+MUX_VAL(CP(D2D_MCAD13),		(IEN  | PTD | EN  | M0)) /*d2d_mcad13*/\
+MUX_VAL(CP(D2D_MCAD14),		(IEN  | PTD | EN  | M0)) /*d2d_mcad14*/\
+MUX_VAL(CP(D2D_MCAD15),		(IEN  | PTD | EN  | M0)) /*d2d_mcad15*/\
+MUX_VAL(CP(D2D_MCAD16),		(IEN  | PTD | EN  | M0)) /*d2d_mcad16*/\
+MUX_VAL(CP(D2D_MCAD17),		(IEN  | PTD | EN  | M0)) /*d2d_mcad17*/\
+MUX_VAL(CP(D2D_MCAD18),		(IEN  | PTD | EN  | M0)) /*d2d_mcad18*/\
+MUX_VAL(CP(D2D_MCAD19),		(IEN  | PTD | EN  | M0)) /*d2d_mcad19*/\
+MUX_VAL(CP(D2D_MCAD20),		(IEN  | PTD | EN  | M0)) /*d2d_mcad20*/\
+MUX_VAL(CP(D2D_MCAD21),		(IEN  | PTD | EN  | M0)) /*d2d_mcad21*/\
+MUX_VAL(CP(D2D_MCAD22),		(IEN  | PTD | EN  | M0)) /*d2d_mcad22*/\
+MUX_VAL(CP(D2D_MCAD23),		(IEN  | PTD | EN  | M0)) /*d2d_mcad23*/\
+MUX_VAL(CP(D2D_MCAD24),		(IEN  | PTD | EN  | M0)) /*d2d_mcad24*/\
+MUX_VAL(CP(D2D_MCAD25),		(IEN  | PTD | EN  | M0)) /*d2d_mcad25*/\
+MUX_VAL(CP(D2D_MCAD26),		(IEN  | PTD | EN  | M0)) /*d2d_mcad26*/\
+MUX_VAL(CP(D2D_MCAD27),		(IEN  | PTD | EN  | M0)) /*d2d_mcad27*/\
+MUX_VAL(CP(D2D_MCAD28),		(IEN  | PTD | EN  | M0)) /*d2d_mcad28*/\
+MUX_VAL(CP(D2D_MCAD29),		(IEN  | PTD | EN  | M0)) /*d2d_mcad29*/\
+MUX_VAL(CP(D2D_MCAD30),		(IEN  | PTD | EN  | M0)) /*d2d_mcad30*/\
+MUX_VAL(CP(D2D_MCAD31),		(IEN  | PTD | EN  | M0)) /*d2d_mcad31*/\
+MUX_VAL(CP(D2D_MCAD32),		(IEN  | PTD | EN  | M0)) /*d2d_mcad32*/\
+MUX_VAL(CP(D2D_MCAD33),		(IEN  | PTD | EN  | M0)) /*d2d_mcad33*/\
+MUX_VAL(CP(D2D_MCAD34),		(IEN  | PTD | EN  | M0)) /*d2d_mcad34*/\
+MUX_VAL(CP(D2D_MCAD35),		(IEN  | PTD | EN  | M0)) /*d2d_mcad35*/\
+MUX_VAL(CP(D2D_MCAD36),		(IEN  | PTD | EN  | M0)) /*d2d_mcad36*/\
+MUX_VAL(CP(D2D_CLK26MI),	(IEN  | PTD | DIS | M0)) /*d2d_clk26mi*/\
+MUX_VAL(CP(D2D_NRESPWRON),	(IEN  | PTD | EN  | M0)) /*d2d_nrespwron*/\
+MUX_VAL(CP(D2D_NRESWARM),	(IEN  | PTU | EN  | M0)) /*d2d_nreswarm */\
+MUX_VAL(CP(D2D_ARM9NIRQ),	(IEN  | PTD | DIS | M0)) /*d2d_arm9nirq */\
+MUX_VAL(CP(D2D_UMA2P6FIQ),	(IEN  | PTD | DIS | M0)) /*d2d_uma2p6fiq*/\
+MUX_VAL(CP(D2D_SPINT),		(IEN  | PTD | EN  | M0)) /*d2d_spint*/\
+MUX_VAL(CP(D2D_FRINT),		(IEN  | PTD | EN  | M0)) /*d2d_frint*/\
+MUX_VAL(CP(D2D_DMAREQ0),	(IEN  | PTD | DIS | M0)) /*d2d_dmareq0*/\
+MUX_VAL(CP(D2D_DMAREQ1),	(IEN  | PTD | DIS | M0)) /*d2d_dmareq1*/\
+MUX_VAL(CP(D2D_DMAREQ2),	(IEN  | PTD | DIS | M0)) /*d2d_dmareq2*/\
+MUX_VAL(CP(D2D_DMAREQ3),	(IEN  | PTD | DIS | M0)) /*d2d_dmareq3*/\
+MUX_VAL(CP(D2D_N3GTRST),	(IEN  | PTD | DIS | M0)) /*d2d_n3gtrst*/\
+MUX_VAL(CP(D2D_N3GTDI),		(IEN  | PTD | DIS | M0)) /*d2d_n3gtdi*/\
+MUX_VAL(CP(D2D_N3GTDO),		(IEN  | PTD | DIS | M0)) /*d2d_n3gtdo*/\
+MUX_VAL(CP(D2D_N3GTMS),		(IEN  | PTD | DIS | M0)) /*d2d_n3gtms*/\
+MUX_VAL(CP(D2D_N3GTCK),		(IEN  | PTD | DIS | M0)) /*d2d_n3gtck*/\
+MUX_VAL(CP(D2D_N3GRTCK),	(IEN  | PTD | DIS | M0)) /*d2d_n3grtck*/\
+MUX_VAL(CP(D2D_MSTDBY),		(IEN  | PTU | EN  | M0)) /*d2d_mstdby*/\
+MUX_VAL(CP(D2D_SWAKEUP),	(IEN  | PTD | EN  | M0)) /*d2d_swakeup*/\
+MUX_VAL(CP(D2D_IDLEREQ),	(IEN  | PTD | DIS | M0)) /*d2d_idlereq*/\
+MUX_VAL(CP(D2D_IDLEACK),	(IEN  | PTU | EN  | M0)) /*d2d_idleack*/\
+MUX_VAL(CP(D2D_MWRITE),		(IEN  | PTD | DIS | M0)) /*d2d_mwrite*/\
+MUX_VAL(CP(D2D_SWRITE),		(IEN  | PTD | DIS | M0)) /*d2d_swrite*/\
+MUX_VAL(CP(D2D_MREAD),		(IEN  | PTD | DIS | M0)) /*d2d_mread*/\
+MUX_VAL(CP(D2D_SREAD),		(IEN  | PTD | DIS | M0)) /*d2d_sread*/\
+MUX_VAL(CP(D2D_MBUSFLAG),	(IEN  | PTD | DIS | M0)) /*d2d_mbusflag*/\
+MUX_VAL(CP(D2D_SBUSFLAG),	(IEN  | PTD | DIS | M0)) /*d2d_sbusflag*/\
+MUX_VAL(CP(SDRC_CKE0),		(IDIS | PTU | EN  | M0)) /*sdrc_cke0*/\
+MUX_VAL(CP(SDRC_CKE1),		(IDIS | PTU | EN  | M0)) /*sdrc_cke1*/
+
+#define MUX_BEAGLE_C() \
+MUX_VAL(CP(MCBSP3_DX),		(IEN  | PTD | DIS | M4)) /*GPIO_140*/\
+MUX_VAL(CP(MCBSP3_DR),		(IEN  | PTD | DIS | M4)) /*GPIO_142*/\
+MUX_VAL(CP(MCBSP3_CLKX),	(IEN  | PTD | DIS | M4)) /*GPIO_141*/\
+MUX_VAL(CP(UART2_CTS),		(IEN  | PTU | EN  | M0)) /*UART2_CTS*/\
+MUX_VAL(CP(UART2_RTS),		(IDIS | PTD | DIS | M0)) /*UART2_RTS*/\
+MUX_VAL(CP(UART2_TX),		(IDIS | PTD | DIS | M0)) /*UART2_TX*/
+
+#define MUX_BEAGLE_XM() \
+MUX_VAL(CP(GPMC_NCS5),		(IDIS | PTD | EN  | M4)) /*GPIO_56*/\
+MUX_VAL(CP(GPMC_WAIT0),		(IDIS | PTU | EN  | M4)) /*GPIO_63*/\
+MUX_VAL(CP(MMC1_DAT7),		(IDIS | PTU | EN  | M4)) /*GPIO_129*/\
+MUX_VAL(CP(HDQ_SIO),		(IDIS | PTU | EN  | M4)) /*GPIO_170*/\
+MUX_VAL(CP(MCBSP3_DX),		(IEN  | PTD | DIS | M4)) /*GPIO_140*/\
+MUX_VAL(CP(MCBSP3_DR),		(IEN  | PTD | DIS | M4)) /*GPIO_142*/\
+MUX_VAL(CP(MCBSP3_CLKX),	(IEN  | PTD | DIS | M4)) /*GPIO_141*/\
+MUX_VAL(CP(UART2_CTS),		(IEN  | PTU | EN  | M0)) /*UART2_CTS*/\
+MUX_VAL(CP(UART2_RTS),		(IDIS | PTD | DIS | M0)) /*UART2_RTS*/\
+MUX_VAL(CP(UART2_TX),		(IDIS | PTD | DIS | M0)) /*UART2_TX*/\
+MUX_VAL(CP(DSS_DATA0),		(IDIS | PTD | DIS | M7)) /*safe_mode*/\
+MUX_VAL(CP(DSS_DATA1),		(IDIS | PTD | DIS | M7)) /*safe_mode*/\
+MUX_VAL(CP(DSS_DATA2),		(IDIS | PTD | DIS | M7)) /*safe_mode*/\
+MUX_VAL(CP(DSS_DATA3),		(IDIS | PTD | DIS | M7)) /*safe_mode*/\
+MUX_VAL(CP(DSS_DATA4),		(IDIS | PTD | DIS | M7)) /*safe_mode*/\
+MUX_VAL(CP(DSS_DATA5),		(IDIS | PTD | DIS | M7)) /*safe_mode*/\
+MUX_VAL(CP(DSS_DATA18),		(IDIS | PTD | DIS | M3)) /*DSS_DATA0*/\
+MUX_VAL(CP(DSS_DATA19),		(IDIS | PTD | DIS | M3)) /*DSS_DATA1*/\
+MUX_VAL(CP(DSS_DATA20),		(IDIS | PTD | DIS | M3)) /*DSS_DATA2*/\
+MUX_VAL(CP(DSS_DATA21),		(IDIS | PTD | DIS | M3)) /*DSS_DATA3*/\
+MUX_VAL(CP(DSS_DATA22),		(IDIS | PTD | DIS | M3)) /*DSS_DATA4*/\
+MUX_VAL(CP(DSS_DATA23),		(IDIS | PTD | DIS | M3)) /*DSS_DATA5*/\
+MUX_VAL(CP(SYS_BOOT0),		(IDIS | PTD | DIS | M3)) /*DSS_DATA18*/\
+MUX_VAL(CP(SYS_BOOT1),		(IDIS | PTD | DIS | M3)) /*DSS_DATA19*/\
+MUX_VAL(CP(SYS_BOOT3),		(IDIS | PTD | DIS | M3)) /*DSS_DATA20*/\
+MUX_VAL(CP(SYS_BOOT4),		(IDIS | PTD | DIS | M3)) /*DSS_DATA21*/\
+MUX_VAL(CP(SYS_BOOT5),		(IDIS | PTD | DIS | M3)) /*DSS_DATA22*/\
+MUX_VAL(CP(SYS_BOOT6),		(IDIS | PTD | DIS | M3)) /*DSS_DATA23*/
+
+#define MUX_TINCANTOOLS_ZIPPY() \
+MUX_VAL(CP(MMC2_CLK),       (IEN  | PTU | EN  | M0)) /*MMC2_CLK*/\
+MUX_VAL(CP(MMC2_CMD),       (IEN  | PTU | EN  | M0)) /*MMC2_CMD*/\
+MUX_VAL(CP(MMC2_DAT0),      (IEN  | PTU | EN  | M0)) /*MMC2_DAT0*/\
+MUX_VAL(CP(MMC2_DAT1),      (IEN  | PTU | EN  | M0)) /*MMC2_DAT1*/\
+MUX_VAL(CP(MMC2_DAT2),      (IEN  | PTU | EN  | M0)) /*MMC2_DAT2*/\
+MUX_VAL(CP(MMC2_DAT3),      (IEN  | PTU | EN  | M0)) /*MMC2_DAT3*/\
+MUX_VAL(CP(MMC2_DAT4),      (IEN  | PTU | EN  | M1)) /*MMC2_DIR_DAT0*/\
+MUX_VAL(CP(MMC2_DAT5),      (IEN  | PTU | EN  | M1)) /*MMC2_DIR_DAT1*/\
+MUX_VAL(CP(MMC2_DAT6),      (IEN  | PTU | EN  | M1)) /*MMC2_DIR_CMD*/\
+MUX_VAL(CP(MMC2_DAT7),      (IEN  | PTU | EN  | M1)) /*MMC2_CLKIN*/\
+MUX_VAL(CP(MCBSP1_CLKR),    (IEN  | PTU | EN  | M1)) /*MCSPI4_CLK*/\
+MUX_VAL(CP(MCBSP1_FSR),     (IEN  | PTU | EN  | M4)) /*GPIO_157*/\
+MUX_VAL(CP(MCBSP1_DX),      (IEN  | PTD | EN  | M1)) /*MCSPI4_SIMO*/\
+MUX_VAL(CP(MCBSP1_DR),      (IEN  | PTD | DIS | M1)) /*MCSPI4_SOMI*/\
+MUX_VAL(CP(MCBSP1_FSX),     (IEN  | PTD | EN  | M1)) /*MCSPI4_CS0*/\
+MUX_VAL(CP(MCBSP1_CLKX),    (IEN  | PTD | DIS | M4)) /*GPIO_162*/\
+MUX_VAL(CP(MCBSP3_DX),      (IEN  | PTD | DIS | M4)) /*GPIO_140*/\
+MUX_VAL(CP(MCBSP3_DR),      (IEN  | PTD | DIS | M4)) /*GPIO_142*/\
+MUX_VAL(CP(MCBSP3_CLKX),    (IEN  | PTD | DIS | M4)) /*GPIO_141*/
+
+#define MUX_TINCANTOOLS_TRAINER() \
+MUX_VAL(CP(MMC2_CLK),       (IEN  | PTU | EN  | M4)) /*GPIO_130*/\
+MUX_VAL(CP(MMC2_CMD),       (IEN  | PTU | EN  | M4)) /*GPIO_131*/\
+MUX_VAL(CP(MMC2_DAT0),      (IEN  | PTU | EN  | M4)) /*GPIO_132*/\
+MUX_VAL(CP(MMC2_DAT1),      (IEN  | PTU | EN  | M4)) /*GPIO_133*/\
+MUX_VAL(CP(MMC2_DAT2),      (IEN  | PTU | EN  | M4)) /*GPIO_134*/\
+MUX_VAL(CP(MMC2_DAT3),      (IEN  | PTU | EN  | M4)) /*GPIO_135*/\
+MUX_VAL(CP(MMC2_DAT4),      (IEN  | PTU | EN  | M4)) /*GPIO_136*/\
+MUX_VAL(CP(MMC2_DAT5),      (IEN  | PTU | EN  | M4)) /*GPIO_137*/\
+MUX_VAL(CP(MMC2_DAT6),      (IEN  | PTU | EN  | M4)) /*GPIO_138*/\
+MUX_VAL(CP(MMC2_DAT7),      (IEN  | PTU | EN  | M4)) /*GPIO_139*/\
+MUX_VAL(CP(MCBSP3_DX),      (IEN  | PTU | EN  | M4)) /*GPIO_140*/\
+MUX_VAL(CP(MCBSP3_CLKX),    (IEN  | PTU | EN  | M4)) /*GPIO_141*/\
+MUX_VAL(CP(MCBSP1_CLKX),    (IEN  | PTU | EN  | M4)) /*GPIO_162*/
+
+#define MUX_KBADC_BEAGLEFPGA() \
+MUX_VAL(CP(MCBSP1_CLKR),    (IEN  | PTU | DIS | M1)) /*MCSPI4_CLK*/\
+MUX_VAL(CP(MCBSP1_DX),      (IDIS | PTU | DIS | M1)) /*MCSPI4_SIMO*/\
+MUX_VAL(CP(MCBSP1_DR),      (IEN  | PTU | EN  | M1)) /*MCSPI4_SOMI*/\
+MUX_VAL(CP(MCBSP1_FSX),     (IDIS | PTU | DIS | M1)) /*MCSPI4_CS0*/
+
+/*
+ * IEN  - Input Enable
+ * IDIS - Input Disable (i.e. output only; IEN means bidirectional mode)
+ * PTD  - Pull type Down
+ * PTU  - Pull type Up
+ * DIS  - Pull type selection is inactive
+ * EN   - Pull type selection is active
+ * M0   - Mode 0 (as defined by pin name)
+ * M4	- Mode 4 (GPIO)
+ */
+
+#if defined(CONFIG_I2C_OMAP_GTA04A2)
+
+#define MUX_BEAGLE_GTA04() \
+MUX_VAL(CP(ETK_CLK_ES2),	(IDIS | PTU | EN  | M4)) /*GPIO_12 - Display serial clock*/\
+MUX_VAL(CP(ETK_CTL_ES2),	(IDIS | PTU | EN  | M4)) /*GPIO_13 - IrDA FIR-SEL*/\
+MUX_VAL(CP(ETK_D4_ES2),		(IEN  | PTU | DIS | M4)) /*GPIO_18 - Display DIN*/\
+MUX_VAL(CP(ETK_D5_ES2),		(IDIS | PTU | EN  | M4)) /*GPIO_19 - Display chip select*/\
+MUX_VAL(CP(ETK_D6_ES2),		(IDIS | PTU | EN  | M4)) /*GPIO_20 - Display DOUT*/\
+MUX_VAL(CP(ETK_D7_ES2),		(IEN  | PTU | EN  | M4)) /*GPIO_21 - RS232 enable*/\
+MUX_VAL(CP(GPMC_NCS6),		(IDIS | PTD | DIS | M4)) /*GPIO_57/GPT_11 - Backlight enable*/\
+MUX_VAL(CP(GPMC_WAIT3),		(IDIS | PTU | DIS | M4)) /*GPIO_65 - AUX IN/OUT*/\
+MUX_VAL(CP(CSI2_DX0),		(IEN  | PTU | EN  | M4)) /*GPIO_112 - Video Out Enable --- FIXME: this is a Input Only!*/\
+MUX_VAL(CP(CSI2_DY0),		(IEN  | PTU | DIS | M4)) /*GPIO_113 - Barometer INT*/\
+MUX_VAL(CP(CSI2_DX1),		(IEN  | PTU | DIS | M4)) /*GPIO_114 - Accel1 INT*/\
+MUX_VAL(CP(CSI2_DY1),		(IEN  | PTU | DIS | M4)) /*GPIO_115 - Accel2 INT*/\
+MUX_VAL(CP(MMC2_CLK),		(IEN  | PTU | EN  | M0)) /*GPIO_130 -> MMC2_CLK*/\
+MUX_VAL(CP(MMC2_CMD),		(IEN  | PTU | EN  | M0)) /*GPIO_131 -> MMC2_CMD*/\
+MUX_VAL(CP(MMC2_DAT0),		(IEN  | PTU | EN  | M0)) /*GPIO_132 -> MMC2_DAT0*/\
+MUX_VAL(CP(MMC2_DAT1),		(IEN  | PTU | EN  | M0)) /*GPIO_133 -> MMC2_DAT1*/\
+MUX_VAL(CP(MMC2_DAT2),		(IEN  | PTU | EN  | M0)) /*GPIO_134 -> MMC2_DAT2*/\
+MUX_VAL(CP(MMC2_DAT3),		(IEN  | PTU | EN  | M0)) /*GPIO_135 -> MMC2_DAT3*/\
+MUX_VAL(CP(MMC2_DAT4),		(IEN  | PTU | EN  | M1)) /*GPIO_136 - MMC2_DIR_DAT0 */\
+MUX_VAL(CP(MMC2_DAT5),		(IEN  | PTU | EN  | M1)) /*GPIO_137 - MMC2_DIR_DAT1 */\
+MUX_VAL(CP(MMC2_DAT6),		(IEN  | PTU | EN  | M1)) /*GPIO_138 - MMC2_DIR_CMD */\
+MUX_VAL(CP(MMC2_DAT7),		(IEN  | PTU | EN  | M1)) /*GPIO_139 - MMC2_DIR_CLKIN */\
+MUX_VAL(CP(UART2_CTS),		(IEN  | PTU | DIS | M4)) /*GPIO_144 - ext Ant */\
+MUX_VAL(CP(UART2_RTS),		(IDIS | PTD | DIS | M4)) /*GPIO_145 - GPS ON(0)/OFF(1)*/\
+MUX_VAL(CP(UART2_TX),		(IDIS | PTU | DIS | M0)) /*GPIO_146 - GPS_TX */\
+MUX_VAL(CP(UART2_RX),		(IEN  | PTU | DIS | M0)) /*GPIO_147 - GPS_RX */\
+MUX_VAL(CP(MCBSP1_CLKR),	(IDIS | PTD | DIS | M0)) /*GPIO_156 - FM TRX*/\
+MUX_VAL(CP(MCBSP1_FSR),		(IEN  | PTU | EN  | M0)) /*GPIO_157 -  */\
+MUX_VAL(CP(MCBSP1_DX),		(IDIS | PTD | EN  | M0)) /*GPIO_158 -  */\
+MUX_VAL(CP(MCBSP1_DR),		(IEN  | PTU | DIS | M0)) /*GPIO_159 -  */\
+MUX_VAL(CP(MCBSP_CLKS),		(IEN  | PTU | EN  | M4)) /*GPIO_160 - PENIRQ*/\
+MUX_VAL(CP(MCBSP1_FSX),		(IDIS | PTU | EN  | M0)) /*GPIO_161 -  */\
+MUX_VAL(CP(MCBSP1_CLKX),	(IDIS | PTD | EN  | M0)) /*GPIO_162 -  */\
+MUX_VAL(CP(MCBSP4_CLKX),	(IEN  | PTD | DIS | M0)) /*MCBSP4_CLKX*/\
+MUX_VAL(CP(MCBSP4_DR),		(IEN  | PTD | DIS | M0)) /*MCBSP4_DR*/\
+MUX_VAL(CP(MCBSP4_DX),		(IEN  | PTD | DIS | M0)) /*MCBSP4_DX*/\
+MUX_VAL(CP(MCBSP4_FSX),		(IEN  | PTD | DIS | M0)) /*MCBSP4_FSX*/\
+MUX_VAL(CP(MCSPI1_CLK),		(IEN  | PTU | EN  | M4)) /*GPIO_171 - Version sense*/\
+MUX_VAL(CP(MCSPI1_SIMO),	(IEN  | PTU | EN  | M4)) /*GPIO_172 - Version sense*/\
+MUX_VAL(CP(MCSPI1_SOMI),	(IEN  | PTU | EN  | M4)) /*GPIO_173 - Version sense*/\
+MUX_VAL(CP(MCSPI1_CS0),		(IEN  | PTD | EN  | M4)) /*GPIO_174 - USB-PHY-RESET*/\
+MUX_VAL(CP(MCSPI1_CS1),		(IEN  | PTU | DIS | M4)) /*GPIO_175/MMC3CMD - WAKE_WWAN */\
+MUX_VAL(CP(MCSPI1_CS2),		(IEN  | PTD | DIS | M4)) /*GPIO_176/MMC3CLK - 3G_WOE */\
+
+#else 	// GTA04A3ff has some improved mux assignments
+
+#define MUX_BEAGLE_GTA04() \
+/*GPIO10 - Keyboard Controller INT - n/a*/\
+MUX_VAL(CP(ETK_CLK_ES2),	(IDIS | PTU | EN  | M4)) /*GPIO_12 - Display serial clock*/\
+MUX_VAL(CP(ETK_CTL_ES2),	(IEN  | PTU | EN  | M4)) /*GPIO_13 - RS232 enable*/\
+MUX_VAL(CP(ETK_D4_ES2),		(IEN  | PTU | DIS | M4)) /*GPIO_18 - Display DIN*/\
+MUX_VAL(CP(ETK_D5_ES2),		(IDIS | PTU | EN  | M4)) /*GPIO_19 - Display chip select*/\
+MUX_VAL(CP(ETK_D6_ES2),		(IDIS | PTU | EN  | M4)) /*GPIO_20 - Display DOUT*/\
+MUX_VAL(CP(ETK_D7_ES2),		(IEN  | PTU | EN  | M4)) /*GPIO_21 - RS232 EXT line*/\
+MUX_VAL(CP(ETK_D8_ES2),		(IEN  | PTU | EN  | M4)) /*GPIO_22 - MSECURE*/\
+MUX_VAL(CP(ETK_D9_ES2),		(IEN  | PTD | EN  | M4)) /*GPIO_23 - Video Out Enable*/\
+MUX_VAL(CP(GPMC_NCS3),		(IEN  | PTD | DIS | M4)) /*GPIO_54 - PoP Temp INT*/\
+MUX_VAL(CP(GPMC_NCS4),		(IEN  | PTU | EN  | M4)) /*GPIO_55 - AUX Out enable*/\
+MUX_VAL(CP(GPMC_NCS5),		(IEN  | PTD | DIS | M4)) /*GPIO_56 - Gyro INT*/\
+MUX_VAL(CP(GPMC_NCS6),		(IEN  | PTU | EN  | M4)) /*GPIO_57(GPT_11) - Backlight enable*/\
+MUX_VAL(CP(CSI2_DX0),		(IEN  | PTU | EN  | M4)) /*GPIO_112 - Compass DRDY*/\
+MUX_VAL(CP(CSI2_DY0),		(IEN  | PTU | DIS | M4)) /*GPIO_113 - Barometer EOC*/\
+MUX_VAL(CP(CSI2_DX1),		(IEN  | PTU | DIS | M4)) /*GPIO_114 - Accel2 INT*/\
+MUX_VAL(CP(CSI2_DY1),		(IEN  | PTU | DIS | M4)) /*GPIO_115 - Accel1 INT*/\
+MUX_VAL(CP(MMC2_CLK),		(IEN  | PTU | EN  | M0)) /*GPIO_130 -> MMC2_CLK*/\
+MUX_VAL(CP(MMC2_CMD),		(IEN  | PTU | EN  | M0)) /*GPIO_131 -> MMC2_CMD*/\
+MUX_VAL(CP(MMC2_DAT0),		(IEN  | PTU | EN  | M0)) /*GPIO_132 -> MMC2_DAT0*/\
+MUX_VAL(CP(MMC2_DAT1),		(IEN  | PTU | EN  | M0)) /*GPIO_133 -> MMC2_DAT1*/\
+MUX_VAL(CP(MMC2_DAT2),		(IEN  | PTU | EN  | M0)) /*GPIO_134 -> MMC2_DAT2*/\
+MUX_VAL(CP(MMC2_DAT3),		(IEN  | PTU | EN  | M0)) /*GPIO_135 -> MMC2_DAT3*/\
+MUX_VAL(CP(MMC2_DAT4),		(IEN  | PTU | EN  | M1)) /*GPIO_136 -> MMC2_DIR_DAT0 */\
+MUX_VAL(CP(MMC2_DAT5),		(IEN  | PTU | EN  | M1)) /*GPIO_137 -> MMC2_DIR_DAT1 */\
+MUX_VAL(CP(MMC2_DAT6),		(IEN  | PTU | EN  | M1)) /*GPIO_138 -> MMC2_DIR_CMD */\
+MUX_VAL(CP(MMC2_DAT7),		(IEN  | PTU | EN  | M1)) /*GPIO_139 -> MMC2_DIR_CLKIN */\
+MUX_VAL(CP(UART2_CTS),		(IEN  | PTU | DIS | M4)) /*GPIO_144 - ext Ant */\
+MUX_VAL(CP(UART2_RTS),		(IEN  | PTD | DIS | M4)) /*GPIO_145 - GPS ON(0)/OFF(1)*/\
+MUX_VAL(CP(UART2_TX),		(IDIS | PTU | DIS | M0)) /*GPIO_146 -> GPS_TX */\
+MUX_VAL(CP(UART2_RX),		(IEN  | PTU | DIS | M0)) /*GPIO_147 -> GPS_RX */\
+MUX_VAL(CP(UART1_TX),		(IDIS | PTD | DIS | M0)) /*UART1_TX -> Bluetooth HCI */\
+MUX_VAL(CP(UART1_RTS),		(IDIS | PTD | DIS | M0)) /*UART1_RTS -> Bluetooth HCI */ \
+MUX_VAL(CP(UART1_CTS),		(IEN  | PTD | DIS | M0)) /*UART1_CTS -> Bluetooth HCI */ \
+MUX_VAL(CP(UART1_RX),		(IEN  | PTD | DIS | M0)) /*UART1_RX -> Bluetooth HCI */\
+MUX_VAL(CP(MCBSP3_DX),		(IDIS | PTD | DIS | M0)) /*McBSP3 -> Bluetooth PCM */\
+MUX_VAL(CP(MCBSP3_DR),		(IEN  | PTD | DIS | M0)) /**/\
+MUX_VAL(CP(MCBSP3_CLKX),	(IDIS | PTD | DIS | M0)) /**/\
+MUX_VAL(CP(MCBSP3_FSX),		(IEN  | PTD | DIS | M0)) /**/\
+MUX_VAL(CP(MCBSP1_CLKR),	(IDIS | PTD | DIS | M0)) /*GPIO_156 -> FM TRX*/\
+MUX_VAL(CP(MCBSP1_FSR),		(IEN  | PTU | EN  | M0)) /*GPIO_157 -> MCBSP1_FSR */\
+MUX_VAL(CP(MCBSP1_DX),		(IDIS | PTD | EN  | M0)) /*GPIO_158 -> MCBSP1_DX */\
+MUX_VAL(CP(MCBSP1_DR),		(IEN  | PTU | DIS | M0)) /*GPIO_159 -> MCBSP1_DR */\
+MUX_VAL(CP(MCBSP_CLKS),		(IEN  | PTU | DIS | M4)) /*GPIO_160 - PENIRQ*/\
+MUX_VAL(CP(MCBSP1_FSX),		(IDIS | PTU | EN  | M0)) /*GPIO_161 -> MCBSP1_FSX */\
+MUX_VAL(CP(MCBSP1_CLKX),	(IDIS | PTD | EN  | M0)) /*GPIO_162 -> MCBSP1_CLKX */\
+MUX_VAL(CP(MCBSP4_CLKX),	(IEN  | PTD | DIS | M0)) /*MCBSP4_CLKX*/\
+MUX_VAL(CP(MCBSP4_DR),		(IEN  | PTD | DIS | M0)) /*MCBSP4_DR*/\
+MUX_VAL(CP(MCBSP4_DX),		(IEN  | PTD | DIS | M0)) /*MCBSP4_DX*/\
+MUX_VAL(CP(MCBSP4_FSX),		(IEN  | PTD | DIS | M0)) /*MCBSP4_FSX*/\
+MUX_VAL(CP(HDQ_SIO),		(IEN  | PTU | EN  | M0)) /*GPIO_170 -> HDQ*/\
+MUX_VAL(CP(MCSPI1_CLK),		(IEN  | PTU | EN  | M4)) /*GPIO_171 - Version sense*/\
+MUX_VAL(CP(MCSPI1_SIMO),	(IEN  | PTU | EN  | M4)) /*GPIO_172 - Version sense*/\
+MUX_VAL(CP(MCSPI1_SOMI),	(IEN  | PTU | EN  | M4)) /*GPIO_173 - Version sense*/\
+MUX_VAL(CP(MCSPI1_CS0),		(IEN  | PTU | EN  | M4)) /*GPIO_174 - USB-PHY-RESET*/\
+MUX_VAL(CP(MCSPI1_CS1),		(IEN  | PTD | DIS | M4)) /*GPIO_175/MMC3CMD - WAKE_WWAN/ON_KEY */\
+MUX_VAL(CP(MCSPI1_CS2),		(IEN  | PTD | DIS | M4)) /*GPIO_176/MMC3CLK - 3G_WOE/ KEY_IRQ */\
+MUX_VAL(CP(SYS_CLKOUT2),	(IEN  | PTD | DIS | M4)) /*GPIO_186 - WWAN_RESET (GTA04A4ff) */\
+
+#if 0 // test HSUSB2 wiring
+/* USB EHCI (port 2) */\
+MUX_VAL(CP(MCSPI1_CS3),		(IEN  | PTU | EN | M4)) /*GPIO177 - HSUSB2_DATA2*/\
+MUX_VAL(CP(MCSPI2_CLK),		(IEN  | PTU | EN | M4)) /*GPIO178 - HSUSB2_DATA7*/\
+MUX_VAL(CP(MCSPI2_SIMO),	(IEN  | PTU | EN | M4)) /*GPIO179 - HSUSB2_DATA4*/\
+MUX_VAL(CP(MCSPI2_SOMI),	(IEN  | PTU | EN | M4)) /*GPIO180 - HSUSB2_DATA5*/\
+MUX_VAL(CP(MCSPI2_CS0),		(IEN  | PTU | EN | M4)) /*GPIO181 - HSUSB2_DATA6*/\
+MUX_VAL(CP(MCSPI2_CS1),		(IEN  | PTU | EN | M4)) /*GPIO182 - HSUSB2_DATA3*/\
+MUX_VAL(CP(ETK_D10_ES2),	(IEN  | PTU | EN | M4)) /*GPIO24 - HSUSB2_CLK*/\
+MUX_VAL(CP(ETK_D11_ES2),	(IEN  | PTU | EN | M4)) /*GPIO25 - HSUSB2_STP*/\
+MUX_VAL(CP(ETK_D12_ES2),	(IEN  | PTU | EN | M4)) /*GPIO26 - HSUSB2_DIR*/\
+MUX_VAL(CP(ETK_D13_ES2),	(IEN  | PTU | EN | M4)) /*GPIO27 - HSUSB2_NXT*/\
+MUX_VAL(CP(ETK_D14_ES2),	(IEN  | PTU | EN | M4)) /*GPIO28 - HSUSB2_DATA0*/\
+MUX_VAL(CP(ETK_D15_ES2),	(IEN  | PTU | EN | M4)) /*GPIO29 - HSUSB2_DATA1*/\
+
+#endif
+
+#endif
+
+#endif	/* _GTA04_H_ */
diff --git a/u-boot/board/goldelico/gta04/i2c1-fix.c b/u-boot/board/goldelico/gta04/i2c1-fix.c
new file mode 100644
index 0000000..2e21acc
--- /dev/null
+++ b/u-boot/board/goldelico/gta04/i2c1-fix.c
@@ -0,0 +1,291 @@
+/* u-boot driver for the layout issue of the I2C1 on the GTA04A2 board
+ *
+ * Copyright (C) 2010 by Golden Delicious Computers GmbH&Co. KG
+ * Author: H. Nikolaus Schaller <hns@goldelico.com>
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * fragments taken from http://www.koders.com/c/fidDC48AC380BE8326E4C3F14F8195BBDB8ED713932.aspx?s=%22Cam%22#L4
+ * see: // see http://www.cc5x.de/I2C.html
+ *
+ */
+
+
+#include <common.h>
+#include <asm/errno.h>
+#include <asm/io.h>
+#include <asm/mach-types.h>
+#include <asm/arch/i2c.h>
+#include <asm/io.h>
+
+#ifdef CONFIG_OMAP3_GTA04A2
+
+/* #error this is for GTA04A2 only */
+
+#include "../../../drivers/i2c/omap24xx_i2c.h"
+
+/* this is a bit-bang driver for the I2C1
+ since the GTA04A2 board has swapped SCL and SDA.
+ We can access these lines in System Test Mode
+ through the I2C_SYSTEST register in ST_EN mode
+ */
+
+#define I2C_SYSTEST_ST_EN	(1 << 15) /* System test enable */
+#define I2C_SYSTEST_FREE	(1 << 14) /* Free running mode, on brkpoint) */
+#define I2C_SYSTEST_TMODE_MASK	(3 << 12) /* Test mode select */
+#define I2C_SYSTEST_TMODE_SHIFT	(12)	  /* Test mode select */
+#define I2C_SYSTEST_SCL_I	(1 << 3)  /* SCL line sense input value */
+#define I2C_SYSTEST_SCL_O	(1 << 2)  /* SCL line drive output value */
+#define I2C_SYSTEST_SDA_I	(1 << 1)  /* SDA line sense input value */
+#define I2C_SYSTEST_SDA_O	(1 << 0)  /* SDA line drive output value */
+
+#define KBIT	100
+
+static inline void delay_full_clock(void)
+{
+	udelay(1000/KBIT);
+}
+static inline void delay_half_clock(void)
+{
+	udelay(500/KBIT);
+}
+static inline void delay_quarter_clock(void)
+{
+	udelay(250/KBIT);
+}
+
+static inline void setscl(struct i2c *base, int state)
+{
+	if(base == (struct i2c *)I2C_BASE1)
+		{ // swap SCL&SDA on I2C1 due to hardware bug
+			if (state) {
+				base->systest |= I2C_SYSTEST_SDA_O;
+			} else {
+				base->systest &= ~I2C_SYSTEST_SDA_O;
+			}			
+		}
+	else
+		{		
+			if (state) {
+				base->systest |= I2C_SYSTEST_SCL_O;
+			} else {
+				base->systest &= ~I2C_SYSTEST_SCL_O;
+			}
+		}
+}
+
+static inline void setsda(struct i2c *base, int state)
+{
+	if(base == (struct i2c *)I2C_BASE1)
+		{ // swap SCL&SDA on I2C1 due to hardware bug
+			if (state) {
+				base->systest |= I2C_SYSTEST_SCL_O;
+			} else {
+				base->systest &= ~I2C_SYSTEST_SCL_O;
+			}
+		}
+	else
+		{
+			if (state) {
+				base->systest |= I2C_SYSTEST_SDA_O;
+			} else {
+				base->systest &= ~I2C_SYSTEST_SDA_O;
+			}
+		}
+} 
+
+static inline int getscl(struct i2c *base)
+{
+	if(base == (struct i2c *)I2C_BASE1)
+		{ // swap SCL&SDA on I2C1 due to hardware bug
+			return (base->systest & I2C_SYSTEST_SDA_I) ? 1 : 0;
+		}
+	else
+		return (base->systest & I2C_SYSTEST_SCL_I) ? 1 : 0;
+}
+
+static inline int getsda(struct i2c *base)
+{
+	if(base == (struct i2c *)I2C_BASE1)
+		{ // swap SCL&SDA on I2C1 due to hardware bug
+			return (base->systest & I2C_SYSTEST_SCL_I) ? 1 : 0;			
+		}
+	else
+		return (base->systest & I2C_SYSTEST_SDA_I) ? 1 : 0;
+}
+
+static inline void busidle(struct i2c *base)
+{
+	/*
+	 * float the SCL and SDA lines. The lines have pull-ups
+	 */
+	setscl(base, 1);
+	setsda(base, 1);
+}
+
+static inline void start(struct i2c *base)
+{
+	busidle(base);
+	delay_full_clock();
+	setsda(base, 0);	// switch data during SCL=H -> this is START
+	delay_quarter_clock();
+	setscl(base, 0);	// switch clock -> prepare for bits
+	//	printf("start\n");
+}
+
+static inline void stop(struct i2c *base)
+{
+	setsda(base, 0);	// set next data bit
+	delay_quarter_clock();
+	setscl(base, 1);	// this is like sending a 0 bit
+	delay_half_clock();
+	setsda(base, 1);	// but switch data during clock -> STOP
+	delay_quarter_clock();
+}
+
+static inline void write_bit(struct i2c *base, int bit)
+{
+//	printf("write bit %d\n", bit);
+	setsda(base, bit);
+	delay_quarter_clock();
+	setscl(base, 1);
+	delay_half_clock();
+	setscl(base, 0);
+	delay_quarter_clock();
+}
+
+static inline int read_bit(struct i2c *base)
+{
+	int bit;
+	setsda(base, 1);	// so that we can read from the OC line...
+	delay_quarter_clock();
+	setscl(base, 1);
+	delay_half_clock();
+	setscl(base, 0);
+	bit = getsda(base);
+	delay_quarter_clock();
+//	printf("read bit %d\n", bit);
+	return bit;
+}
+
+static int write_byte(struct i2c *base, int byte)
+{
+	int i;
+	
+	for (i=7; i>=0; i--)
+		write_bit(base, (byte & (1<<i)) != 0);
+	return read_bit(base) == 0; // ok (1) if NACK is asserted
+}
+
+static int read_byte(struct i2c *base)
+{
+	int i;
+	u8 byte=0;
+		
+	for (i=7; i>=0; i--)
+		byte = (byte << 1) | read_bit(base);
+	return byte;
+}
+
+int i2c_bitbang_probe(struct i2c *base, unchar devaddr)
+{
+//	printf("i2c probe %02x SDA %d SCL %d\n", devaddr, getsda(base), getscl(base));
+	start(base);
+	if (write_byte(base, (devaddr<<1))) { // write probe
+		stop(base);	// send stop condition
+		return 0;	// ok
+	}
+	stop(base);	// send stop condition
+	return 1;	// fail
+}
+
+int i2c_bitbang_write_byte (struct i2c *base, u8 devaddr, u8 regoffset, u8 value)
+{
+//	printf("i2c-bb write dev=%02x regoffset=%02x value=%02x\n", devaddr, regoffset, value);
+	start(base);
+	if (write_byte(base, (devaddr<<1))) { // send chip address for write command
+		if (write_byte(base, regoffset)) { // send register offset
+			if (write_byte(base, value)) { // send value
+				stop(base);	// send stop condition
+				return 0;	// ok
+			}
+		}
+	}
+	stop(base);	// send stop condition
+	return 1;	// fail
+}
+
+int i2c_bitbang_read_byte (struct i2c *base, u8 devaddr, u8 regoffset, u8 * value)
+{
+//	printf("i2c-bb read dev=%02x regoffset=%02x ", devaddr, regoffset);
+	start(base);
+	if (write_byte(base, (devaddr<<1))) { // send chip address for write command
+		if (write_byte(base, regoffset)) { // send register offset - this defines where we want to read
+			start(base);	// repeated start
+			if (write_byte(base, (devaddr<<1) | 1)) { // send chip address for read command
+				*value = read_byte(base);
+//				printf("%02x\n", *value);
+				write_bit(base, 1);	// NAK
+				stop(base);	// send stop condition
+				return 0;	// ok
+			}
+			else {
+//				printf(" 2nd chip address error ");
+			}
+		}
+		else {
+//			printf(" offset error ");
+		}
+	}
+	else {
+//		printf(" chip address error ");
+	}
+
+	stop(base);	// send stop condition
+	return 1;	// fail
+}
+
+void i2c_bitbang_init(struct i2c *base)
+{
+	writew(I2C_SYSTEST_ST_EN | I2C_SYSTEST_FREE | (3 << I2C_SYSTEST_TMODE_SHIFT), &base->systest);
+	busidle(base);
+//	printf("i2c-bb init base=%08x\n", base);
+#if OLD
+	printf("I2C_SYSTEST1 *0x4807003C = %04x\n", readw(0x4807003C));
+	printf("I2C_SYSTEST2 *0x4807203C = %04x\n", readw(0x4807203C));
+	printf("I2C_SYSTEST3 *0x4806003C = %04x\n", readw(0x4806003C));
+	setscl(base, 0);
+	delay_full_clock();
+	printf("I2C_SYSTEST2 *0x4807203C = %04x\n", readw(0x4807203C));
+	setscl(base, 1);
+	delay_full_clock();
+	printf("I2C_SYSTEST2 *0x4807203C = %04x\n", readw(0x4807203C));
+#endif
+}
+
+
+void i2c_bitbang_close(struct i2c *base)
+{
+	busidle(base);	
+	base->systest = 0; // get out of test mode
+}
+
+#else
+
+/* not required */
+
+#endif
diff --git a/u-boot/board/goldelico/gta04/jbt6k74.c b/u-boot/board/goldelico/gta04/jbt6k74.c
new file mode 100644
index 0000000..fcc7615
--- /dev/null
+++ b/u-boot/board/goldelico/gta04/jbt6k74.c
@@ -0,0 +1,380 @@
+/* u-boot driver for the tpo JBT6K74-AS LCM ASIC
+ *
+ * Copyright (C) 2006-2007 by OpenMoko, Inc.
+ * Author: Harald Welte <laforge@openmoko.org>
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+/* modified by hns@goldelico.com
+ * to separate jbt commands from communication (throgh SPI or GPIOs)
+ */
+
+#include <common.h>
+#include <asm/errno.h>
+#include <asm/io.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/gpio.h>
+#include <asm/mach-types.h>
+#include <asm/arch/dss.h>
+#include <twl4030.h>
+#include "dssfb.h"
+#include "jbt6k74.h"
+
+// FIXME: we have somehow mixed up the file names...
+
+// configure beagle board DSS for the TD28TTEC1
+
+#define DVI_BACKGROUND_COLOR		0x00fadc29	// rgb(250, 220, 41)
+
+#define DSS1_FCLK		432000000	// compare table 4-32. figure 15-65 - but there are other factors
+#define DSS1_FCLK3730	108000000	// compare table 3-34, figure 7-63 - but there are other factors
+#define PIXEL_CLOCK		22000000	// approx. 22 MHz (will be divided from 432 MHz)
+
+// all values are min ratings
+
+#define VDISP	640				// vertical active area
+#define VFP		4				// vertical front porch
+#define VS		2				// VSYNC pulse width (negative going)
+#define VBP		2				// vertical back porch
+#define VDS		(VS+VBP)		// vertical data start
+#define VBL		(VS+VBP+VFP)	// vertical blanking period
+#define VP		(VDISP+VBL)		// vertical cycle
+
+#define HDISP	480				// horizontal active area
+#define HFP		24				// horizontal front porch
+#define HS		8				// HSYNC pulse width (negative going)
+#define HBP		8				// horizontal back porch
+#define HDS		(HS+HBP)		// horizontal data start
+#define HBL		(HS+HBP+HFP)	// horizontal blanking period
+#define HP		(HDISP+HBL)		// horizontal cycle
+
+#if 0
+#define DEBUGP(x, args...) printf("%s: " x, __FUNCTION__, ## args);
+#define DEBUGPC(x, args...) printf(x, ## args);
+#else
+#define DEBUGP(x, args...) do { } while (0)
+#define DEBUGPC(x, args...) do { } while (0)
+#endif
+
+static /*const*/ struct panel_config lcm_cfg = 
+{
+	.timing_h	= ((HBP-1)<<20) | ((HFP-1)<<8) | ((HS-1)<<0), /* Horizantal timing */
+	.timing_v	= ((VBP+0)<<20) | ((VFP+0)<<8) | ((VS-1)<<0), /* Vertical timing */
+	.pol_freq	= (1<<17)|(0<<16)|(0<<15)|(1<<14)|(1<<13)|(1<<12)|0x28,    /* Pol Freq */
+	.divisor	= (0x0001<<16)|(DSS1_FCLK/PIXEL_CLOCK), /* Pixel Clock divisor from dss1_fclk */
+	.lcd_size	= ((HDISP-1)<<0) | ((VDISP-1)<<16), /* as defined by LCM */
+	.panel_type	= 0x01, /* TFT */
+	.data_lines	= 0x03, /* 24 Bit RGB */
+	.load_mode	= 0x02, /* Frame Mode */
+	.panel_color	= DVI_BACKGROUND_COLOR
+};
+
+
+enum jbt_register {
+	JBT_REG_SLEEP_IN		= 0x10,
+	JBT_REG_SLEEP_OUT		= 0x11,
+
+	JBT_REG_DISPLAY_OFF		= 0x28,
+	JBT_REG_DISPLAY_ON		= 0x29,
+
+	JBT_REG_RGB_FORMAT		= 0x3a,
+	JBT_REG_QUAD_RATE		= 0x3b,
+
+	JBT_REG_POWER_ON_OFF		= 0xb0,
+	JBT_REG_BOOSTER_OP		= 0xb1,
+	JBT_REG_BOOSTER_MODE		= 0xb2,
+	JBT_REG_BOOSTER_FREQ		= 0xb3,
+	JBT_REG_OPAMP_SYSCLK		= 0xb4,
+	JBT_REG_VSC_VOLTAGE		= 0xb5,
+	JBT_REG_VCOM_VOLTAGE		= 0xb6,
+	JBT_REG_EXT_DISPL		= 0xb7,
+	JBT_REG_OUTPUT_CONTROL		= 0xb8,
+	JBT_REG_DCCLK_DCEV		= 0xb9,
+	JBT_REG_DISPLAY_MODE1		= 0xba,
+	JBT_REG_DISPLAY_MODE2		= 0xbb,
+	JBT_REG_DISPLAY_MODE		= 0xbc,
+	JBT_REG_ASW_SLEW		= 0xbd,
+	JBT_REG_DUMMY_DISPLAY		= 0xbe,
+	JBT_REG_DRIVE_SYSTEM		= 0xbf,
+
+	JBT_REG_SLEEP_OUT_FR_A		= 0xc0,
+	JBT_REG_SLEEP_OUT_FR_B		= 0xc1,
+	JBT_REG_SLEEP_OUT_FR_C		= 0xc2,
+	JBT_REG_SLEEP_IN_LCCNT_D	= 0xc3,
+	JBT_REG_SLEEP_IN_LCCNT_E	= 0xc4,
+	JBT_REG_SLEEP_IN_LCCNT_F	= 0xc5,
+	JBT_REG_SLEEP_IN_LCCNT_G	= 0xc6,
+
+	JBT_REG_GAMMA1_FINE_1		= 0xc7,
+	JBT_REG_GAMMA1_FINE_2		= 0xc8,
+	JBT_REG_GAMMA1_INCLINATION	= 0xc9,
+	JBT_REG_GAMMA1_BLUE_OFFSET	= 0xca,
+
+	JBT_REG_BLANK_CONTROL		= 0xcf,
+	JBT_REG_BLANK_TH_TV		= 0xd0,
+	JBT_REG_CKV_ON_OFF		= 0xd1,
+	JBT_REG_CKV_1_2			= 0xd2,
+	JBT_REG_OEV_TIMING		= 0xd3,
+	JBT_REG_ASW_TIMING_1		= 0xd4,
+	JBT_REG_ASW_TIMING_2		= 0xd5,
+
+	JBT_REG_HCLOCK_VGA		= 0xec,
+	JBT_REG_HCLOCK_QVGA		= 0xed,
+
+};
+
+static const char *jbt_state_names[] = {
+	[JBT_STATE_DEEP_STANDBY]	= "deep-standby",
+	[JBT_STATE_SLEEP]		= "sleep",
+	[JBT_STATE_NORMAL]		= "normal",
+};
+
+static struct jbt_info _jbt, *jbt = &_jbt;
+
+const char *jbt_state(void)
+{
+	return jbt_state_names[jbt->state];
+}
+
+static int jbt_init_regs(struct jbt_info *jbt)
+{
+	int rc;
+
+	DEBUGP("entering\n");
+
+	rc = jbt_reg_write(jbt, JBT_REG_DISPLAY_MODE1, 0x01);
+	rc |= jbt_reg_write(jbt, JBT_REG_DISPLAY_MODE2, 0x00);
+	rc |= jbt_reg_write(jbt, JBT_REG_RGB_FORMAT, 0x60);
+	rc |= jbt_reg_write(jbt, JBT_REG_DRIVE_SYSTEM, 0x10);
+	rc |= jbt_reg_write(jbt, JBT_REG_BOOSTER_OP, 0x56);
+	rc |= jbt_reg_write(jbt, JBT_REG_BOOSTER_MODE, 0x33);
+	rc |= jbt_reg_write(jbt, JBT_REG_BOOSTER_FREQ, 0x11);
+	rc |= jbt_reg_write(jbt, JBT_REG_BOOSTER_FREQ, 0x11);
+	rc |= jbt_reg_write(jbt, JBT_REG_OPAMP_SYSCLK, 0x02);
+	rc |= jbt_reg_write(jbt, JBT_REG_VSC_VOLTAGE, 0x2b);
+	rc |= jbt_reg_write(jbt, JBT_REG_VCOM_VOLTAGE, 0x40);
+	rc |= jbt_reg_write(jbt, JBT_REG_EXT_DISPL, 0x03);
+	rc |= jbt_reg_write(jbt, JBT_REG_DCCLK_DCEV, 0x04);
+	/*
+	 * default of 0x02 in JBT_REG_ASW_SLEW responsible for 72Hz requirement
+	 * to avoid red / blue flicker
+	 */
+	rc |= jbt_reg_write(jbt, JBT_REG_ASW_SLEW, 0x04);
+	rc |= jbt_reg_write(jbt, JBT_REG_DUMMY_DISPLAY, 0x00);
+
+	rc |= jbt_reg_write(jbt, JBT_REG_SLEEP_OUT_FR_A, 0x11);
+	rc |= jbt_reg_write(jbt, JBT_REG_SLEEP_OUT_FR_B, 0x11);
+	rc |= jbt_reg_write(jbt, JBT_REG_SLEEP_OUT_FR_C, 0x11);
+	rc |= jbt_reg_write16(jbt, JBT_REG_SLEEP_IN_LCCNT_D, 0x2040);
+	rc |= jbt_reg_write16(jbt, JBT_REG_SLEEP_IN_LCCNT_E, 0x60c0);
+	rc |= jbt_reg_write16(jbt, JBT_REG_SLEEP_IN_LCCNT_F, 0x1020);
+	rc |= jbt_reg_write16(jbt, JBT_REG_SLEEP_IN_LCCNT_G, 0x60c0);
+
+	rc |= jbt_reg_write16(jbt, JBT_REG_GAMMA1_FINE_1, 0x5533);
+	rc |= jbt_reg_write(jbt, JBT_REG_GAMMA1_FINE_2, 0x00);
+	rc |= jbt_reg_write(jbt, JBT_REG_GAMMA1_INCLINATION, 0x00);
+	rc |= jbt_reg_write(jbt, JBT_REG_GAMMA1_BLUE_OFFSET, 0x00);
+	rc |= jbt_reg_write(jbt, JBT_REG_GAMMA1_BLUE_OFFSET, 0x00);
+
+	rc |= jbt_reg_write16(jbt, JBT_REG_HCLOCK_VGA, 0x1f0);
+	rc |= jbt_reg_write(jbt, JBT_REG_BLANK_CONTROL, 0x02);
+	rc |= jbt_reg_write16(jbt, JBT_REG_BLANK_TH_TV, 0x0804);
+	rc |= jbt_reg_write16(jbt, JBT_REG_BLANK_TH_TV, 0x0804);
+
+	rc |= jbt_reg_write(jbt, JBT_REG_CKV_ON_OFF, 0x01);
+	rc |= jbt_reg_write16(jbt, JBT_REG_CKV_1_2, 0x0000);
+
+	rc |= jbt_reg_write16(jbt, JBT_REG_OEV_TIMING, 0x0d0e);
+	rc |= jbt_reg_write16(jbt, JBT_REG_ASW_TIMING_1, 0x11a4);
+	rc |= jbt_reg_write(jbt, JBT_REG_ASW_TIMING_2, 0x0e);
+
+#if 0
+	rc |= jbt_reg_write16(jbt, JBT_REG_HCLOCK_QVGA, 0x00ff);
+	rc |= jbt_reg_write16(jbt, JBT_REG_HCLOCK_QVGA, 0x00ff);
+#endif
+
+	if(rc)
+		printf("jbt_init_regs() failed\n");
+	else
+		printf("did jbt_init_regs()\n");
+	return rc;
+}
+
+static int standby_to_sleep(struct jbt_info *jbt)
+{
+	int rc;
+
+	DEBUGP("entering\n");
+
+	/* three times command zero */
+	rc = jbt_reg_write_nodata(jbt, 0x00);
+	udelay(1000);
+	rc = jbt_reg_write_nodata(jbt, 0x00);
+	udelay(1000);
+	rc = jbt_reg_write_nodata(jbt, 0x00);
+	udelay(1000);
+
+	/* deep standby out */
+	rc |= jbt_reg_write(jbt, JBT_REG_POWER_ON_OFF, 0x17);
+
+	return rc;
+}
+
+static int sleep_to_normal(struct jbt_info *jbt)
+{
+	int rc;
+	DEBUGP("entering\n");
+
+	/* RGB I/F on, RAM wirte off, QVGA through, SIGCON enable */
+	rc = jbt_reg_write(jbt, JBT_REG_DISPLAY_MODE, 0x80);
+
+	/* Quad mode off */
+	rc |= jbt_reg_write(jbt, JBT_REG_QUAD_RATE, 0x00);
+
+	/* AVDD on, XVDD on */
+	rc |= jbt_reg_write(jbt, JBT_REG_POWER_ON_OFF, 0x16);
+
+	/* Output control */
+	rc |= jbt_reg_write16(jbt, JBT_REG_OUTPUT_CONTROL, 0xfff9);
+
+	/* Sleep mode off */
+	rc |= jbt_reg_write_nodata(jbt, JBT_REG_SLEEP_OUT);
+
+	/* at this point we have like 50% grey */
+
+	/* initialize register set */
+	rc |= jbt_init_regs(jbt);
+	return rc;
+}
+
+static int normal_to_sleep(struct jbt_info *jbt)
+{
+	int rc;
+	DEBUGP("entering\n");
+
+	rc = jbt_reg_write_nodata(jbt, JBT_REG_DISPLAY_OFF);
+	rc |= jbt_reg_write16(jbt, JBT_REG_OUTPUT_CONTROL, 0x8002);
+	rc |= jbt_reg_write_nodata(jbt, JBT_REG_SLEEP_IN);
+
+	return rc;
+}
+
+static int sleep_to_standby(struct jbt_info *jbt)
+{
+	DEBUGP("entering\n");
+	return jbt_reg_write(jbt, JBT_REG_POWER_ON_OFF, 0x00);
+}
+
+/* frontend function */
+int jbt6k74_enter_state(enum jbt_state new_state)
+{
+	int rc = -EINVAL;
+
+	DEBUGP("entering(old_state=%u, new_state=%u)\n", jbt->state, new_state);
+
+	switch (jbt->state) {
+	case JBT_STATE_DEEP_STANDBY:
+		switch (new_state) {
+		case JBT_STATE_DEEP_STANDBY:
+			rc = 0;
+			break;
+		case JBT_STATE_SLEEP:
+			rc = standby_to_sleep(jbt);
+			break;
+		case JBT_STATE_NORMAL:
+			/* first transition into sleep */
+			rc = standby_to_sleep(jbt);
+			/* then transition into normal */
+			rc |= sleep_to_normal(jbt);
+			break;
+		}
+		break;
+	case JBT_STATE_SLEEP:
+		switch (new_state) {
+		case JBT_STATE_SLEEP:
+			rc = 0;
+			break;
+		case JBT_STATE_DEEP_STANDBY:
+			rc = sleep_to_standby(jbt);
+			break;
+		case JBT_STATE_NORMAL:
+			rc = sleep_to_normal(jbt);
+			break;
+		}
+		break;
+	case JBT_STATE_NORMAL:
+		switch (new_state) {
+		case JBT_STATE_NORMAL:
+			rc = 0;
+			break;
+		case JBT_STATE_DEEP_STANDBY:
+			/* first transition into sleep */
+			rc = normal_to_sleep(jbt);
+			/* then transition into deep standby */
+			rc |= sleep_to_standby(jbt);
+			break;
+		case JBT_STATE_SLEEP:
+			rc = normal_to_sleep(jbt);
+			break;
+		}
+		break;
+	}
+	if(rc)
+		printf("jbt6k74_enter_state() failed.\n");
+	else
+		jbt->state=new_state;
+	return rc;
+}
+
+int jbt6k74_display_onoff(int on)
+{
+	DEBUGP("entering\n");
+	if (on)
+		return jbt_reg_write_nodata(jbt, JBT_REG_DISPLAY_ON);
+	else
+		return jbt_reg_write_nodata(jbt, JBT_REG_DISPLAY_OFF);
+}
+
+int board_video_init(GraphicDevice *pGD)
+{
+	extern int get_board_revision(void);
+	backlight_init();	// initialize backlight
+#define REVISION_XM 0
+	if(get_board_revision() == REVISION_XM) {
+		/* Set VAUX1 to 3.3V for GTA04E display board */
+		twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VAUX1_DEDICATED,
+								/*TWL4030_PM_RECEIVER_VAUX1_VSEL_33*/ 0x07,
+								TWL4030_PM_RECEIVER_VAUX1_DEV_GRP,
+								TWL4030_PM_RECEIVER_DEV_GRP_P1);
+		udelay(5000);
+	}
+	if(jbt_reg_init())	// initialize SPI
+		{
+		printf("No LCM connected\n");
+		return 1;
+		}
+	if (get_cpu_family() == CPU_OMAP36XX)
+		lcm_cfg.divisor	= (0x0001<<16)|(DSS1_FCLK3730/PIXEL_CLOCK), /* Pixel Clock divisor from dss1_fclk */
+	dssfb_init(&lcm_cfg);
+	
+	printf("did board_video_init()\n");
+	return 0;
+}
+
diff --git a/u-boot/board/goldelico/gta04/jbt6k74.h b/u-boot/board/goldelico/gta04/jbt6k74.h
new file mode 100644
index 0000000..170873f
--- /dev/null
+++ b/u-boot/board/goldelico/gta04/jbt6k74.h
@@ -0,0 +1,19 @@
+#ifndef _JBT6K74_H
+#define _JBT6K74_H
+
+#include <video_fb.h>
+#include "TD028TTEC1.h"
+#include "backlight.h"
+
+enum jbt_state {
+	JBT_STATE_DEEP_STANDBY,
+	JBT_STATE_SLEEP,
+	JBT_STATE_NORMAL,
+};
+
+int jbt6k74_display_onoff(int on);
+int jbt6k74_enter_state(enum jbt_state new_state);
+const char *jbt_state(void);
+int board_video_init(GraphicDevice *pGD);
+
+#endif
diff --git a/u-boot/board/goldelico/gta04/shutdown.c b/u-boot/board/goldelico/gta04/shutdown.c
new file mode 100644
index 0000000..1ebe661
--- /dev/null
+++ b/u-boot/board/goldelico/gta04/shutdown.c
@@ -0,0 +1,63 @@
+/* u-boot driver for the GTA04 shutdown
+ *
+ * Copyright (C) 2010 by Golden Delicious Computers GmbH&Co. KG
+ * Author: H. Nikolaus Schaller <hns@goldelico.com>
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <asm/errno.h>
+#include <asm/io.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/gpio.h>
+#include <asm/mach-types.h>
+#include <twl4030.h>
+#include "shutdown.h"
+
+void shutdown(void)
+{
+	u8 val = 0;
+	if(i2c_set_bus_num(0))
+		{
+		printf ("could not select I2C1\n");
+		return;
+		}
+	printf("shutting down by writing DEVOFF register of TPS65950\n");
+	if (twl4030_i2c_read_u8(TWL4030_CHIP_PM_MASTER, &val,
+							TWL4030_PM_MASTER_P1_SW_EVENTS)) {
+		printf("Error:TWL4030: failed to read the power register\n");
+		printf("Could not initialize hardware reset\n");
+	} else {
+		val |= TWL4030_PM_MASTER_SW_EVENTS_DEVOFF;
+		if (twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER, val,
+								 TWL4030_PM_MASTER_P1_SW_EVENTS)) {
+			printf("Error:TWL4030: failed to write the power register\n");
+			printf("Could not initialize hardware reset\n");
+		}
+	}
+	// CHECKME: do we have to write PM_MASTER_P2 and _P3?
+}
+
+void suspend(void)
+{
+	// enable the AUX button interrupt for Wakeup
+	// suspend (sleep) the CPU
+	// the TPS should remain powered on
+}
diff --git a/u-boot/board/goldelico/gta04/shutdown.h b/u-boot/board/goldelico/gta04/shutdown.h
new file mode 100644
index 0000000..b1638ea
--- /dev/null
+++ b/u-boot/board/goldelico/gta04/shutdown.h
@@ -0,0 +1,30 @@
+/* u-boot extended commands for GTA04
+ *
+ * Copyright (C) 2010 by Golden Delicious Computers GmbH&Co. KG
+ * Author: H. Nikolaus Schaller <hns@goldelico.com>
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#ifndef _SHUTDOWN_H
+#define _SHUTDOWN_H
+
+void shutdown(void);
+void suspend(void);
+
+#endif
diff --git a/u-boot/board/goldelico/gta04/status.c b/u-boot/board/goldelico/gta04/status.c
new file mode 100644
index 0000000..aebd95e
--- /dev/null
+++ b/u-boot/board/goldelico/gta04/status.c
@@ -0,0 +1,289 @@
+/* u-boot driver for the GTA04 LEDs and Buttons
+ *
+ * Copyright (C) 2010 by Golden Delicious Computers GmbH&Co. KG
+ * Author: H. Nikolaus Schaller <hns@goldelico.com>
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <asm/errno.h>
+#include <asm/io.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/gpio.h>
+#include <asm/mach-types.h>
+#include <i2c.h>
+#include <twl4030.h>
+#include "status.h"
+
+#if defined(CONFIG_OMAP3_GTA04)
+
+// no need to probe for LED controller (compiler should optimize unnecessary code)
+#define hasTCA6507 (1==1)
+
+#else
+
+static int hasTCA6507=0;
+
+#endif
+
+#define TWL4030_I2C_BUS		(1-1)	// I2C1
+#define TCA6507_BUS			(2-1)	// I2C2
+#define TCA6507_ADDRESS		0x45
+
+/* register numbers */
+#define TCA6507_SELECT0						0
+#define TCA6507_SELECT1						1
+#define TCA6507_SELECT2						2
+#define TCA6507_FADE_ON_TIME				3
+#define TCA6507_FULLY_ON_TIME				4
+#define TCA6507_FADR_OFF_TIME				5
+#define TCA6507_FIRST_FULLY_OFF_TIME		6
+#define TCA6507_SECOND_FULLY_OFF_TIME		7
+#define TCA6507_MAXIMUM_INTENSITY			8
+#define TCA6507_ONE_SHOT_MASTER_INTENSITY	9
+#define TCA6507_INITIALIZATION				10
+
+#define TCA6507_AUTO_INCREMENT				16
+
+// we can't include "beagle.h"
+/* BeagleBoard revisions */
+extern int get_board_revision(void); 
+#define REVISION_AXBX	0x7
+#define REVISION_CX	0x6
+#define REVISION_C4	0x5
+#define REVISION_XM	0x0
+
+static int isXM = 0;
+
+#if defined(CONFIG_OMAP3_GTA04)
+
+#define GPIO_AUX		7		// AUX/User button
+#define GPIO_POWER		-1		// N/A on GTA04 (access through TPS65950)
+#define GPIO_GPSEXT		144		// external GPS antenna is plugged in
+#define GPIO_PENIRQ		160		// TSC must be set up to provide PENIRQ
+
+#elif defined(CONFIG_OMAP3_BEAGLE_HYBRID)
+
+#define GPIO_AUX		136		// AUX/User button
+#define GPIO_POWER		137		// POWER button
+#define GPIO_GPSEXT		138		// external GPS antenna is plugged in
+#define GPIO_PENIRQ		157		// TSC must be set up to provide PENIRQ
+
+#elif defined(CONFIG_OMAP3_BEAGLE_EXPANDER)
+
+#define GPIO_AUX		136		// AUX/User button
+#define GPIO_POWER		137		// POWER button
+#define GPIO_GPSEXT		138		// external GPS antenna is plugged in
+#define GPIO_PENIRQ		157		// TSC must be set up to provide PENIRQ
+
+#else
+
+#error unknown config
+
+#endif
+
+#define GPIO_LED_AUX_RED		(isXM?88:70)		// AUX
+#define GPIO_LED_AUX_GREEN		(isXM?89:71)		// AUX
+#define GPIO_LED_POWER_RED		78					// Power
+#define GPIO_LED_POWER_GREEN	79					// Power
+#define GPIO_LED_VIBRA			(isXM?2:88)			// Vibracall motor
+#define GPIO_LED_UNUSED			(isXM?3:89)			// unused
+
+static int status;
+
+void status_set_status(int value)
+{
+	status=value;
+	if(!hasTCA6507) {
+		omap_set_gpio_dataout(GPIO_LED_AUX_RED, (value&(1 << 0)));
+		omap_set_gpio_dataout(GPIO_LED_AUX_GREEN, (value&(1 << 1)));
+		omap_set_gpio_dataout(GPIO_LED_POWER_RED, (value&(1 << 3)));
+		omap_set_gpio_dataout(GPIO_LED_POWER_GREEN, (value&(1 << 4)));
+		omap_set_gpio_dataout(GPIO_LED_VIBRA, (value&(1 << 6)));
+		omap_set_gpio_dataout(GPIO_LED_UNUSED, (value&(1 << 7)));
+		}
+	else {
+		value &= 0x3f;	// 6 LEDs only - 7th is reserved to reset the WLAN/BT chip
+		i2c_set_bus_num(TCA6507_BUS);	// write I2C2
+		// we could write a autoincrement address and all 3 bytes in a single message
+		// we could set the TCA to do smooth transitions
+		i2c_reg_write(TCA6507_ADDRESS, TCA6507_SELECT0, 0);
+		i2c_reg_write(TCA6507_ADDRESS, TCA6507_SELECT1, 0);
+		i2c_reg_write(TCA6507_ADDRESS, TCA6507_SELECT2, value);	// 1 = on
+	}
+}
+
+int status_get_buttons(void)
+{ // convert button state into led state
+#if defined(CONFIG_OMAP3_GTA04)
+	u8 val;
+	i2c_set_bus_num(TWL4030_I2C_BUS);	// read I2C1
+	twl4030_i2c_read_u8(TWL4030_CHIP_PM_MASTER, &val, TWL4030_PM_MASTER_STS_HW_CONDITIONS);	// read state of power button (bit 0) from TPS65950
+	return ((omap_get_gpio_datain(GPIO_AUX)) << 0) |
+		((omap_get_gpio_datain(GPIO_GPSEXT)) << 1) |
+		(((val&0x01) != 0) << 3) |
+		((omap_get_gpio_datain(GPIO_PENIRQ)) << 4);
+#elif defined(CONFIG_OMAP3_BEAGLE_EXPANDER)
+	return
+		((omap_get_gpio_datain(GPIO_AUX)) << 0) |
+		((0) << 1) |
+		((!omap_get_gpio_datain(GPIO_POWER)) << 3) |
+		((omap_get_gpio_datain(GPIO_PENIRQ)) << 4);
+#else
+	return
+		((!omap_get_gpio_datain(GPIO_AUX)) << 0) |
+		((omap_get_gpio_datain(GPIO_GPSEXT)) << 1) |
+		((!omap_get_gpio_datain(GPIO_POWER)) << 3) |
+		((omap_get_gpio_datain(GPIO_PENIRQ)) << 4);
+#endif
+}
+
+int status_init(void)
+{
+	isXM = (get_board_revision() == REVISION_XM);
+#if !defined(CONFIG_OMAP3_GTA04)
+	if(i2c_set_bus_num(TCA6507_BUS))
+		{
+		printf ("could not select I2C2\n");
+		return 1;
+		}
+	hasTCA6507 = !i2c_probe(TCA6507_ADDRESS);
+#endif
+	
+	if(!hasTCA6507) {
+		if(isXM) { // XM has scrambled dss assignment with respect to default ball name
+			MUX_VAL(CP(DSS_DATA18),		(IEN | PTD | EN | M4)); /*GPIO */
+			MUX_VAL(CP(DSS_DATA19),		(IEN | PTD | EN | M4)); /*GPIO */
+			MUX_VAL(CP(DSS_DATA8),		(IEN | PTD | EN | M4)); /*GPIO */
+			MUX_VAL(CP(DSS_DATA9),		(IEN | PTD | EN | M4)); /*GPIO */
+			MUX_VAL(CP(SYS_BOOT0),		(IEN | PTD | EN | M4)); /*GPIO */
+			MUX_VAL(CP(SYS_BOOT1),		(IEN | PTD | EN | M4)); /*GPIO */
+		}
+		else {
+			MUX_VAL(CP(DSS_DATA0),		(IEN | PTD | EN | M4)); /*GPIO */
+			MUX_VAL(CP(DSS_DATA1),		(IEN | PTD | EN | M4)); /*GPIO */
+			MUX_VAL(CP(DSS_DATA8),		(IEN | PTD | EN | M4)); /*GPIO */
+			MUX_VAL(CP(DSS_DATA9),		(IEN | PTD | EN | M4)); /*GPIO */
+			MUX_VAL(CP(DSS_DATA16),		(IEN | PTD | EN | M4)); /*GPIO */
+			MUX_VAL(CP(DSS_DATA17),		(IEN | PTD | EN | M4)); /*GPIO */
+		}
+		
+		omap_request_gpio(GPIO_LED_AUX_GREEN);
+		omap_request_gpio(GPIO_LED_AUX_RED);
+		omap_request_gpio(GPIO_LED_POWER_GREEN);
+		omap_request_gpio(GPIO_LED_POWER_RED);
+		omap_request_gpio(GPIO_LED_VIBRA);
+		omap_request_gpio(GPIO_LED_UNUSED);
+		omap_request_gpio(GPIO_POWER);
+	}
+	else {
+		// initialize I2C controller
+	}
+	
+	omap_request_gpio(GPIO_AUX);
+	omap_request_gpio(GPIO_GPSEXT);
+	omap_request_gpio(GPIO_PENIRQ);
+	
+	if(!hasTCA6507) {
+		omap_set_gpio_direction(GPIO_LED_AUX_GREEN, 0);		// output
+		omap_set_gpio_direction(GPIO_LED_AUX_RED, 0);		// output
+		omap_set_gpio_direction(GPIO_LED_POWER_GREEN, 0);		// output
+		omap_set_gpio_direction(GPIO_LED_POWER_RED, 0);		// output
+		omap_set_gpio_direction(GPIO_LED_VIBRA, 0);		// output
+		omap_set_gpio_direction(GPIO_LED_UNUSED, 0);		// output
+		omap_set_gpio_direction(GPIO_POWER, 1);		// input
+		}
+	
+	omap_set_gpio_direction(GPIO_AUX, 1);		// input
+#ifndef CONFIG_OMAP3_GTA04
+	omap_set_gpio_direction(GPIO_POWER, 1);		// input
+#endif
+	omap_set_gpio_direction(GPIO_GPSEXT, 1);	// input
+
+	// when sould we do omap_free_gpio(GPIO_LED_AUX_GREEN); ?
+	printf("did init LED driver for %s\n", hasTCA6507?"TCA6507":"GPIOs");
+
+	return 0;
+}
+
+int status_set_flash (int mode)
+{ // 0: off, 1: torch, 2: flash
+	if(i2c_set_bus_num(TCA6507_BUS))
+		{
+		printf ("could not select I2C2\n");
+		return 1;
+		}
+	// initialize if needed
+	// set flash controller mode
+	return 0;
+}
+
+int status_set_vibra (int value)
+{ // 0: off otherwise msb controls left/right (2's complement)
+	unsigned char byte;
+	if(i2c_set_bus_num(TWL4030_I2C_BUS))
+		{
+		printf ("could not select I2C1\n");
+		return 1;
+		}
+	
+	// program Audio controller (see document SWCU050D)
+	
+	byte = 0x00;						// LEDAON=LEDBON=0
+	i2c_write(0x4A, 0xEE, 1, &byte, 1);	// LEDEN
+	byte = value != 0 ? 0x03 : 0x00;	// 8 kHz, Codec on (if value != 0), Option 1:RX and TX stereo audio path
+	i2c_write(0x49, 0x01, 1, &byte, 1);	// CODEC_MODE
+	byte = 0x16;						// APLL_EN enabled, 26 MHz
+	i2c_write(0x49, 0x3a, 1, &byte, 1);	// APLL_CTL
+	byte = 0x04;						// use PWM
+	i2c_write(0x4B, 0x60, 1, &byte, 1);	// VIBRATOR_CFG
+	byte = value > 0?0x01:0x03;			// use VIBRADIR, local driver, enable
+	i2c_write(0x49, 0x45, 1, &byte, 1);	// VIBRATOR_CFG
+	byte = 256-(value>=0?value:-value);	// PWM turnon value
+	if(byte == 0) byte = 0x01;			// 0x00 is forbidden!
+	i2c_write(0x49, 0x46, 1, &byte, 1);	// VIBRA_SEL
+
+	// do we have to set some Audio PLL frequency (number 6 & 7?)
+
+	/*
+	 To use the vibrator H-bridge:
+	 1. Disable LEDA: Set the LEDEN[0]LEDAON bit to logic 0.
+	 2. Disable LEDB: Set the LEDEN[1]LEDBON bit to logic 0.
+	 3. Turn on the codec:
+	 Set the CODEC_MODE[1] CODECPDZ bit to 1.
+	 The H-bridge vibrator can get its operation from the following sources:
+	 •	An audio channel can provide the stimulus.
+	 •	A PWM in the audio subchip can generate the signal.
+	 If an audio channel provides the motivating force for the vibrator (for example: the audio right 1 channel):
+	 1. Set the VIBR_CTL[4]VIBRA_SEL bit to 1.
+	 2. Set the VIBR_CTL[5]VIBRA_DIR_SEL bit to 1.
+	 3. Set the VIBR_CTL[3:2]VIBRA_AUDIO_SEL bit field to 0x1 (audio right 1 channel).
+	 4. Select the use of the SIGN bit to determine the output phase to VIBRA_P and VIBRA_M. 
+	 5. Set the VIBRA_CTL[0]VIBRA_EN bit to 1 (power to the H-bridge is driven by audiodata).
+	 Notes:
+	 •	If audio data drives the vibrator H-bridge, set the VIBRA_SET register to 0xFF.
+	 •	The direction of the vibrator H-bridge controlled by the VIBRA_DIR bit can be changed
+	 on the fly.
+	 6. Set the audio PLL input frequency: The APLL_CTL APLL_INFREQ bitfield=0x6.
+	 7. Enable the audio PLL: The APLL_CTL APLL_ENbit=1.
+	 Note:	Do not enable LEDA/B and the H-vibrator simultaneously.
+	 */
+	return 0;	
+}
diff --git a/u-boot/board/goldelico/gta04/status.h b/u-boot/board/goldelico/gta04/status.h
new file mode 100644
index 0000000..5bed2e2
--- /dev/null
+++ b/u-boot/board/goldelico/gta04/status.h
@@ -0,0 +1,12 @@
+#ifndef _STATUS_H
+#define _STATUS_H
+
+int status_init (void);
+
+void status_set_status (int value);
+int status_get_buttons (void);
+
+int status_set_flash (int mode);	// 0: off, 1: torch, 2: flash
+int status_set_vibra (int value);	// 0: off, >0 / <0 determines polarity . -255 ... +255
+
+#endif
diff --git a/u-boot/board/goldelico/gta04/systest.c b/u-boot/board/goldelico/gta04/systest.c
new file mode 100644
index 0000000..5df301c
--- /dev/null
+++ b/u-boot/board/goldelico/gta04/systest.c
@@ -0,0 +1,850 @@
+/* u-boot driver for the GTA04 shutdown
+ *
+ * Copyright (C) 2010 by Golden Delicious Computers GmbH&Co. KG
+ * Author: H. Nikolaus Schaller <hns@goldelico.com>
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <asm/errno.h>
+#include <asm/io.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/gpio.h>
+#include <asm/mach-types.h>
+#include <i2c.h>
+#include <twl4030.h>
+#include <ns16550.h>
+#include "systest.h"
+#include "TD028TTEC1.h"
+#include "ulpi-phy.h"
+#include "status.h"
+#include "tsc2007.h"
+#include "twl4030-additions.h"
+
+#define TWL4030_I2C_BUS			(1-1)
+
+int bt_hci(int msg)
+{
+#define MODE_X_DIV 16
+	int baudrate=9600;
+	int divisor=(CONFIG_SYS_NS16550_CLK + (baudrate * (MODE_X_DIV / 2))) / (MODE_X_DIV * baudrate);
+	char send[]={
+		0x01,	// command
+#define OGF 0x01
+#define OCF 0x0002	// HCI_Inquiry_Cancel
+#define OP ((OGF<<10)+OCF)
+		OP&0xff, OP>>8
+	};
+	NS16550_reinit((NS16550_t)CONFIG_SYS_NS16550_COM1, divisor);	// initialize UART
+	int i;
+	int bytes=0;
+	long timer=(1*1000*1000)/40;	// 1 second total timeout
+#if 1 // GPIO test for UART lines
+	if(msg)
+		{ // print states of UART lines
+			MUX_VAL(CP(UART1_TX),		(IEN  | PTU | EN | M4)) /*UART1_TX -> Bluetooth HCI */\
+			MUX_VAL(CP(UART1_RTS),		(IEN  | PTU | EN | M4)) /*UART1_RTS -> Bluetooth HCI */ \
+			MUX_VAL(CP(UART1_CTS),		(IEN  | PTU | EN | M4)) /*UART1_CTS -> Bluetooth HCI */ \
+			MUX_VAL(CP(UART1_RX),		(IEN  | PTU | EN | M4)) /*UART1_RX -> Bluetooth HCI */
+
+			MUX_VAL(CP(UART2_CTS),		(IEN  | PTU | DIS | M4)) /*GPIO_144 - ext Ant */\
+			MUX_VAL(CP(UART2_RTS),		(IEN  | PTD | DIS | M4)) /*GPIO_145 - GPS ON(0)/OFF(1)*/\
+			MUX_VAL(CP(UART2_TX),		(IEN  | PTU | DIS | M4)) /*GPIO_146 - GPS_TX */\
+			MUX_VAL(CP(UART2_RX),		(IEN  | PTU | DIS | M4)) /*GPIO_147 - GPS_RX */\
+			
+			udelay(100);
+			
+			omap_request_gpio(148);
+			omap_request_gpio(149);
+			omap_request_gpio(150);
+			omap_request_gpio(151);
+			omap_set_gpio_direction(148, 1);	// 1=input
+			omap_set_gpio_direction(149, 1);	// 1=input
+			omap_set_gpio_direction(150, 1);	// 1=input
+			omap_set_gpio_direction(151, 1);	// 1=input
+			printf("UART1 RTS: %d\n", omap_get_gpio_datain(149));
+			printf("UART1 CTS: %d\n", omap_get_gpio_datain(150));
+			printf("UART1 TX:  %d\n", omap_get_gpio_datain(148));
+			printf("UART1 RX:  %d\n", omap_get_gpio_datain(151));
+			
+			omap_request_gpio(144);
+			omap_request_gpio(145);
+			omap_request_gpio(146);
+			omap_request_gpio(147);
+			omap_set_gpio_direction(144, 1);	// 1=input
+			omap_set_gpio_direction(145, 1);	// 1=input
+			omap_set_gpio_direction(146, 1);	// 1=input
+			omap_set_gpio_direction(147, 1);	// 1=input
+			printf("UART2 RTS: %d\n", omap_get_gpio_datain(145));
+			printf("UART2 CTS: %d\n", omap_get_gpio_datain(144));
+			printf("UART2 TX:  %d\n", omap_get_gpio_datain(146));
+			printf("UART2 RX:  %d\n", omap_get_gpio_datain(147));
+			
+			MUX_VAL(CP(UART1_TX),		(IDIS | PTD | DIS | M0)) /*UART1_TX -> Bluetooth HCI */\
+			MUX_VAL(CP(UART1_RTS),		(IDIS | PTD | DIS | M0)) /*UART1_RTS -> Bluetooth HCI */ \
+			MUX_VAL(CP(UART1_CTS),		(IEN  | PTD | DIS | M0)) /*UART1_CTS -> Bluetooth HCI */ \
+			MUX_VAL(CP(UART1_RX),		(IEN  | PTD | DIS | M0)) /*UART1_RX -> Bluetooth HCI */\
+
+			MUX_VAL(CP(UART2_CTS),		(IEN  | PTU | DIS | M4)) /*GPIO_144 - ext Ant */\
+			MUX_VAL(CP(UART2_RTS),		(IDIS | PTD | DIS | M4)) /*GPIO_145 - GPS ON(0)/OFF(1)*/\
+			MUX_VAL(CP(UART2_TX),		(IDIS | PTU | DIS | M0)) /*GPIO_146 - GPS_TX */\
+			MUX_VAL(CP(UART2_RX),		(IEN  | PTU | DIS | M0)) /*GPIO_147 - GPS_RX */\
+			udelay(100);
+		}
+#endif
+	if(msg)
+		printf("HCI send:");
+	for (i=0; i<sizeof(send); i++)
+		{ // send bytes on HCI port
+			if(msg)
+				printf(" %02x", send[i]);
+			NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, send[i]);
+		}
+	if(msg)
+		printf("\n");
+	if(msg)
+		printf("HCI receive:");
+	while (timer-- > 0)
+		{ //
+			if(NS16550_tstc((NS16550_t)CONFIG_SYS_NS16550_COM1))
+				{ // byte received
+					int c=NS16550_getc((NS16550_t)CONFIG_SYS_NS16550_COM1);
+					if(msg)
+						printf(" %02x", c);	// from GPS to console
+					bytes++;	// one more received
+				}
+			udelay(40);	// 115200 bit/s is approx. 86 us per byte 
+		}
+	if(bytes == 0)
+		{
+		if(msg)
+			printf(" timed out\n");
+		return 0;			
+		}
+	if(msg)
+		printf("\n");
+	return 1;
+}
+
+int systest(void)
+{
+	int r;
+	i2c_set_bus_num(TWL4030_I2C_BUS);	// I2C1
+	printf("TPS65950:      %s\n", !(r=i2c_probe(TWL4030_CHIP_USB))?"found":"-");	// responds on 4 addresses 0x48..0x4b
+	if(!r)
+		{ // was ok, ask for details
+		u8 val;
+		u8 val2;
+		twl4030_i2c_read_u8(TWL4030_CHIP_PM_MASTER, &val, TWL4030_PM_MASTER_STS_HW_CONDITIONS);
+		printf("  STS_HW_CON: %02x", val);	// decode bits
+		if(val & 0x80) printf(" VBUS");
+		if(val & 0x08) printf(" NRESWARM");
+		if(val & 0x04) printf(" USB");
+		if(val & 0x02) printf(" CHG");
+		if(val & 0x01) printf(" PWRON");
+		printf("\n");
+		twl4030_i2c_read_u8(TWL4030_CHIP_PM_MASTER, &val, 0x2e);
+		printf("  PWR_ISR1:   %02x", val);
+		// decode bits
+		printf("\n");
+		twl4030_i2c_read_u8(TWL4030_CHIP_PM_RECEIVER, &val, TWL4030_PM_MASTER_SC_DETECT1);
+		printf("  SC_DETECT:  1:%02x", val);
+		twl4030_i2c_read_u8(TWL4030_CHIP_PM_RECEIVER, &val, TWL4030_PM_MASTER_SC_DETECT1);
+		printf(" 2:%02x\n", val);
+		twl4030_i2c_read_u8(TWL4030_CHIP_MAIN_CHARGE, &val, 0x82);
+		printf("  BCIMFSTS2:  %02x\n", val);
+		twl4030_i2c_read_u8(TWL4030_CHIP_MAIN_CHARGE, &val, 0x83);
+		printf("  BCIMFSTS3:  %02x\n", val);
+		twl4030_i2c_read_u8(TWL4030_CHIP_MAIN_CHARGE, &val, 0x84);
+		printf("  BCIMFSTS4:  %02x\n", val);
+		twl4030_i2c_read_u8(TWL4030_CHIP_MADC, &val, 0x57);
+		twl4030_i2c_read_u8(TWL4030_CHIP_MADC, &val2, 0x58);
+		printf("  BTEMP:   %d\n", (val2<<2)+(val>>6));
+		twl4030_i2c_read_u8(TWL4030_CHIP_MADC, &val, 0x59);
+		twl4030_i2c_read_u8(TWL4030_CHIP_MADC, &val2, 0x5a);
+		printf("  USBVBUS: %d\n", (val2<<2)+(val>>6));
+		twl4030_i2c_read_u8(TWL4030_CHIP_MADC, &val, 0x5b);
+		twl4030_i2c_read_u8(TWL4030_CHIP_MADC, &val2, 0x5c);
+		printf("  ICHG:    %d\n", (val2<<2)+(val>>6));
+		twl4030_i2c_read_u8(TWL4030_CHIP_MADC, &val, 0x5d);
+		twl4030_i2c_read_u8(TWL4030_CHIP_MADC, &val2, 0x5e);
+		printf("  VCHG:    %d\n", (val2<<2)+(val>>6));
+		twl4030_i2c_read_u8(TWL4030_CHIP_MADC, &val, 0x5f);
+		twl4030_i2c_read_u8(TWL4030_CHIP_MADC, &val2, 0x60);
+		printf("  VBAT:    %d\n", (val2<<2)+(val>>6));
+		}
+	i2c_set_bus_num(1);	// I2C2
+	printf("TSC2007:       %s\n", !i2c_probe(0x48)?"found":"-");
+	printf("TCA6507:       %s\n", !i2c_probe(0x45)?"found":"-");
+	printf("LIS302 TOP:    %s\n", !i2c_probe(0x1c)?"found":"-");
+	printf("LIS302 BOTTOM: %s\n", !i2c_probe(0x1d)?"found":"-");
+	printf("LSM303:        %s\n", !i2c_probe(0x19)?"found":"-");
+	printf("HMC58xx:       %s\n", !i2c_probe(0x1e)?"found":"-");
+	printf("BMA180:        %s\n", !i2c_probe(0x41)?"found":"-");
+	printf("BMP085:        %s\n", !i2c_probe(0x77)?"found":"-");
+	printf("ITG3200:       %s\n", !i2c_probe(0x68)?"found":"-");
+	printf("Si47xx:        %s\n", !i2c_probe(0x11)?"found":"-");
+	printf("TCA8418:       %s\n", !i2c_probe(0x64)?"found":"-");
+	printf("OV9655:        %s\n", !i2c_probe(0x30)?"found":"-");
+	printf("TPS61050:      %s\n", !i2c_probe(0x33)?"found":"-");
+	printf("EEPROM:        %s\n", !i2c_probe(0x50)?"found":"-");
+	printf("VCNL4000:      %s\n", !i2c_probe(0x13)?"found":"-");
+	i2c_set_bus_num(2);	// I2C3
+	/* nothing to check */
+	i2c_set_bus_num(TWL4030_I2C_BUS);	// I2C1
+	if(!jbt_check())
+	    printf("DISPLAY:       ok\n");
+	else
+		printf("DISPLAY:       failed\n");
+#if HAVE_ULPI_TEST
+	printf("PHY-WWAN:      %s\n", (ulpi_direct_access(1, 1, 0, 0) == 0x04)?"found":"-");	// read reg 1 (vendor id) of HSUSB2
+#endif
+	// LEDs
+	// GPS/UART
+	// RAM-Test
+	// NAND-Test
+	// Buttons
+	// Power
+	// real Display communication
+	// PCM
+	// OTG USB
+	// Charger
+	// internal USB
+	// UMTS Module
+	printf("BT HCI:        %s\n", bt_hci(0)?"found":"-");
+	return (0);
+}
+
+/* audio test taken from BeagleBoard B validation U-Boot (1.3.3) */
+/* http://code.google.com/p/beagleboard/wiki/BeagleSourceCode */
+
+static ushort tone[] = {
+	0x0ce4, 0x0ce4, 0x1985, 0x1985, 0x25A1, 0x25A1, 0x30FD, 0x30FE,
+	0x3B56, 0x3B55, 0x447A, 0x447A, 0x4C3B, 0x4C3C, 0x526D, 0x526C,
+	0x56F1, 0x56F1, 0x59B1, 0x59B1, 0x5A9E, 0x5A9D, 0x59B1, 0x59B2,
+	0x56F3, 0x56F2, 0x526D, 0x526D, 0x4C3B, 0x4C3B, 0x447C, 0x447C,
+	0x3B5A, 0x3B59, 0x30FE, 0x30FE, 0x25A5, 0x25A6, 0x1989, 0x198A,
+	0x0CE5, 0x0CE3, 0x0000, 0x0000, 0xF31C, 0xF31C, 0xE677, 0xE676,
+	0xDA5B, 0xDA5B, 0xCF03, 0xCF03, 0xC4AA, 0xC4AA, 0xBB83, 0xBB83,
+	0xB3C5, 0xB3C5, 0xAD94, 0xAD94, 0xA90D, 0xA90E, 0xA64F, 0xA64E,
+	0xA562, 0xA563, 0xA64F, 0xA64F, 0xA910, 0xA90F, 0xAD93, 0xAD94,
+	0xB3C4, 0xB3C4, 0xBB87, 0xBB86, 0xC4AB, 0xC4AB, 0xCF03, 0xCF03,
+	0xDA5B, 0xDA5A, 0xE67B, 0xE67B, 0xF31B, 0xF3AC, 0x0000, 0x0000,
+	0x0CE4, 0x0CE4, 0x1985, 0x1985, 0x25A1, 0x25A1, 0x30FD, 0x30FE,
+	0x3B56, 0x3B55, 0x447A, 0x447A, 0x4C3B, 0x4C3C, 0x526D, 0x526C,
+	0x56F1, 0x56F1, 0x59B1, 0x59B1, 0x5A9E, 0x5A9D, 0x59B1, 0x59B2,
+	0x56F3, 0x56F2, 0x526D, 0x526D, 0x4C3B, 0x4C3B, 0x447C, 0x447C,
+	0x3B5A, 0x3B59, 0x30FE, 0x30FE, 0x25A5, 0x25A6, 0x1989, 0x198A,
+	0x0CE5, 0x0CE3, 0x0000, 0x0000, 0xF31C, 0xF31C, 0xE677, 0xE676,
+	0xDA5B, 0xDA5B, 0xCF03, 0xCF03, 0xC4AA, 0xC4AA, 0xBB83, 0xBB83,
+	0xB3C5, 0xB3C5, 0xAD94, 0xAD94, 0xA90D, 0xA90E, 0xA64F, 0xA64E,
+	0xA562, 0xA563, 0xA64F, 0xA64F, 0xA910, 0xA90F, 0xAD93, 0xAD94,
+	0xB3C4, 0xB3C4, 0xBB87, 0xBB86, 0xC4AB, 0xC4AB, 0xCF03, 0xCF03,
+	0xDA5B, 0xDA5A, 0xE67B, 0xE67B, 0xF31B, 0xF3AC, 0x0000, 0x0000,
+	0x0CE4, 0x0CE4, 0x1985, 0x1985, 0x25A1, 0x25A1, 0x30FD, 0x30FE,
+	0x3B56, 0x3B55, 0x447A, 0x447A, 0x4C3B, 0x4C3C, 0x526D, 0x526C,
+	0x56F1, 0x56F1, 0x59B1, 0x59B1, 0x5A9E, 0x5A9D, 0x59B1, 0x59B2,
+	0x56F3, 0x56F2, 0x526D, 0x526D, 0x4C3B, 0x4C3B, 0x447C, 0x447C,
+	0x3B5A, 0x3B59, 0x30FE, 0x30FE, 0x25A5, 0x25A6, 0x1989, 0x198A,
+	0x0CE5, 0x0CE3, 0x0000, 0x0000, 0xF31C, 0xF31C, 0xE677, 0xE676,
+	0xDA5B, 0xDA5B, 0xCF03, 0xCF03, 0xC4AA, 0xC4AA, 0xBB83, 0xBB83,
+	0xB3C5, 0xB3C5, 0xAD94, 0xAD94, 0xA90D, 0xA90E, 0xA64F, 0xA64E,
+	0xA562, 0xA563, 0xA64F, 0xA64F, 0xA910, 0xA90F, 0xAD93, 0xAD94,
+	0xB3C4, 0xB3C4, 0xBB87, 0xBB86, 0xC4AB, 0xC4AB, 0xCF03, 0xCF03,
+	0xDA5B, 0xDA5A, 0xE67B, 0xE67B, 0xF31B, 0xF3AC, 0x0000, 0x0000
+};
+
+int audiotest_init(int channel)
+{
+	
+	unsigned char byte;
+	
+	printf("Test Audio Tone on Speaker\n");
+	printf("Initializing over I2C1");
+	i2c_set_bus_num(TWL4030_I2C_BUS);	// I2C1
+	
+	// program Audio controller (see document SWCU050D)
+	
+	// ??? VAUX3 is not connected on BB ???
+	// so what is the setting for 2.8V good for?
+/*	
+	byte = 0x20;						// RES_TYPE2=2, RES_TYPE=0
+	i2c_write(0x4B, 0x7A, 1, &byte, 1);	// VAUX3_DEV_GRP
+	byte = 0x03;						// no trim, 2.8V
+	i2c_write(0x4B, 0x7D, 1, &byte, 1);	// VAUX3_DEDICATED
+
+	
+	byte = 0xE0;						// DEV_GRP belongs to all device groups
+	i2c_write(0x4B, 0x8E, 1, &byte, 1);	// VPLL2_DEV_GRP
+	byte = 0x05;						// 1.8V
+	i2c_write(0x4B, 0x91, 1, &byte, 1);	// VPLL2_DEDICATED
+ */
+	
+	byte = 0x03;						// 8 kHz, Codec on, Option 1:RX and TX stereo audio path
+	i2c_write(0x49, 0x01, 1, &byte, 1);	// CODEC_MODE
+	byte = 0xc0;						// Audio RX Right2 enable, Left 2 enable
+	i2c_write(0x49, 0x02, 1, &byte, 1);	// OPTION
+/*
+	byte = 0x00;
+	i2c_write(0x49, 0x03, 1, &byte, 1);	// ?
+ */
+	byte = 0x00;
+	i2c_write(0x49, 0x04, 1, &byte, 1);	// MICBIAS_CTL
+	byte = 0x00;
+	i2c_write(0x49, 0x05, 1, &byte, 1);	// ANAMICL
+	byte = 0x00;
+	i2c_write(0x49, 0x06, 1, &byte, 1);	// ANAMICR
+	byte = 0x00;
+	i2c_write(0x49, 0x07, 1, &byte, 1);	// AVADC_CTL
+	byte = 0x00;
+	i2c_write(0x49, 0x08, 1, &byte, 1);	// ADCMICSEL
+	byte = 0x00;
+	i2c_write(0x49, 0x09, 1, &byte, 1);	// DIGMIXING
+	byte = 0x00;
+	i2c_write(0x49, 0x0a, 1, &byte, 1);	// ATXL1PGA
+	byte = 0x00;
+	i2c_write(0x49, 0x0b, 1, &byte, 1);	// ATXR1PGA
+	byte = 0x00;
+	i2c_write(0x49, 0x0c, 1, &byte, 1);	// AVTXL2PGA
+	byte = 0x00;
+	i2c_write(0x49, 0x0d, 1, &byte, 1);	// AVTXR2PGA
+	byte = 0x01;						// TDM/CODEC master mode, 16 bit sample/word, codec mode format, clk256 disabled, Application mode
+	i2c_write(0x49, 0x0e, 1, &byte, 1);	// AUDIO_IF
+	byte = 0x00;
+	i2c_write(0x49, 0x0f, 1, &byte, 1);	// VOICE_IF
+	byte = 0x00;
+	i2c_write(0x49, 0x10, 1, &byte, 1);	// ARXR1PGA
+	byte = 0x00;
+	i2c_write(0x49, 0x11, 1, &byte, 1);	// ARXL1PGA
+	byte = 0x6c;						// ARXR2PGA_CGAIN=6 dB, ARXR2PGA_FGAIN=-31 dB
+	i2c_write(0x49, 0x12, 1, &byte, 1);	// ARXR2PGA
+	byte = 0x6c;						// ARXL2PGA_CGAIN=6 dB, ARXR2PGA_FGAIN=-31 dB
+	i2c_write(0x49, 0x13, 1, &byte, 1);	// ARXL2PGA
+	byte = 0x00;
+	i2c_write(0x49, 0x14, 1, &byte, 1);	// VRXPGA
+	byte = 0x00;
+	i2c_write(0x49, 0x15, 1, &byte, 1);	// VSTPGA
+	byte = 0x00;
+	i2c_write(0x49, 0x16, 1, &byte, 1);	// VRX2ARXPGA
+	byte = 0x0c;						// VDAC_EN off, ADACL2_EN & ADACR2_EN on, ADACL1_EN & ADACR1_EN off
+	i2c_write(0x49, 0x17, 1, &byte, 1);	// AVDAC_CTL
+	byte = 0x00;
+	i2c_write(0x49, 0x18, 1, &byte, 1);	// ARX2VTXPGA
+	byte = 0x00;
+	i2c_write(0x49, 0x19, 1, &byte, 1);	// ARXL1_APGA_CTL
+	byte = 0x00;
+	i2c_write(0x49, 0x1a, 1, &byte, 1);	// ARXR1_APGA_CTL
+	byte = 0x2b;						// 2 dB, no FM loop, Digital-Analog path enable, Analog PGA application mode
+	i2c_write(0x49, 0x1b, 1, &byte, 1);	// ARXL2_APGA_CTL
+	byte = 0x2b;						// 2 dB, no FM loop, Digital-Analog path enable, Analog PGA application mode
+	i2c_write(0x49, 0x1c, 1, &byte, 1);	// ARXR2_APGA_CTL
+	byte = 0x00;
+	i2c_write(0x49, 0x1d, 1, &byte, 1);	// ATX2ARXPGA
+	byte = 0x00;
+	i2c_write(0x49, 0x1e, 1, &byte, 1);	// BT_IF
+	byte = 0x00;
+	i2c_write(0x49, 0x1f, 1, &byte, 1);	// BTPGA
+	byte = 0x00;
+	i2c_write(0x49, 0x20, 1, &byte, 1);	// BTSTPGA
+	byte = 0x34;						// 0 dB, EAR_AL2_EN
+	i2c_write(0x49, 0x21, 1, &byte, 1);	// EAR_CTL
+	byte = 0x24;						// HSOR_AR2_EN, HSOL_AL2_EN
+	i2c_write(0x49, 0x22, 1, &byte, 1);	// HS_SEL
+	byte = 0x0a;						// HSR_GAIN & HSL_GAIN = 0 dB
+	i2c_write(0x49, 0x23, 1, &byte, 1);	// HS_GAIN_SET
+	byte = 0x42;						// VMID_EN enable, ramp down 20ms
+	i2c_write(0x49, 0x24, 1, &byte, 1);	// HS_POPN_SET
+	byte = 0x00;
+	i2c_write(0x49, 0x25, 1, &byte, 1);	// PREDL_CTL
+	byte = 0x00;
+	i2c_write(0x49, 0x26, 1, &byte, 1);	// PREDR_CTL
+	byte = 0x00;
+	i2c_write(0x49, 0x27, 1, &byte, 1);	// PRECKL_CTL
+	byte = 0x00;
+	i2c_write(0x49, 0x28, 1, &byte, 1);	// PRECKR_CTL
+	byte = 0x00;
+	i2c_write(0x49, 0x29, 1, &byte, 1);	// HFL_CTL
+	byte = 0x00;
+	i2c_write(0x49, 0x2a, 1, &byte, 1);	// HFR_CTL
+	byte = 0x00;
+	i2c_write(0x49, 0x2b, 1, &byte, 1);	// ALC_CTL
+	byte = 0x00;
+	i2c_write(0x49, 0x2c, 1, &byte, 1);	// ALC_SET1
+	byte = 0x00;
+	i2c_write(0x49, 0x2d, 1, &byte, 1);	// ALC_SET2
+	byte = 0x00;
+	i2c_write(0x49, 0x2e, 1, &byte, 1);	// BOOST_CTL
+	byte = 0x00;
+	i2c_write(0x49, 0x2f, 1, &byte, 1);	// SOFTVOL_CTL
+	byte = 0x00;
+	i2c_write(0x49, 0x30, 1, &byte, 1);	// DTMF_FREQSEL
+	byte = 0x00;
+	i2c_write(0x49, 0x31, 1, &byte, 1);	// DTMF_TONEXT1H
+	byte = 0x00;
+	i2c_write(0x49, 0x32, 1, &byte, 1);	// DTMF_TONEXT1L
+	byte = 0x00;
+	i2c_write(0x49, 0x33, 1, &byte, 1);	// DTMF_TONEXT2H
+	byte = 0x00;
+	i2c_write(0x49, 0x34, 1, &byte, 1);	// DTMF_TONEXT2L
+	byte = 0x00;
+	i2c_write(0x49, 0x35, 1, &byte, 1);	// DTMF_TONOFF
+	byte = 0x00;
+	i2c_write(0x49, 0x36, 1, &byte, 1);	// DTMF_WANONOFF
+	byte = 0x00;
+	i2c_write(0x49, 0x37, 1, &byte, 1);	// I2S_RX_SCRAMBLE_H
+	byte = 0x00;
+	i2c_write(0x49, 0x38, 1, &byte, 1);	// I2S_RX_SCRAMBLE_M
+	byte = 0x00;
+	i2c_write(0x49, 0x39, 1, &byte, 1);	// I2S_RX_SCRAMBLE_L
+//	byte = 0x15;						// APLL_EN enabled, 19.2 MHz
+	byte = 0x16;						// APLL_EN enabled, 26 MHz
+	i2c_write(0x49, 0x3a, 1, &byte, 1);	// APLL_CTL
+	byte = 0x00;
+	i2c_write(0x49, 0x3b, 1, &byte, 1);	// DTMF_CTL
+	byte = 0x00;
+	i2c_write(0x49, 0x3c, 1, &byte, 1);	// DTMF_PGA_CTL2
+	byte = 0x00;
+	i2c_write(0x49, 0x3d, 1, &byte, 1);	// DTMF_PGA_CTL1
+	byte = 0x00;
+	i2c_write(0x49, 0x3e, 1, &byte, 1);	// MISC_SET_1
+	byte = 0x00;
+	i2c_write(0x49, 0x3f, 1, &byte, 1);	// PCMBTMUX
+/*
+	byte = 0x00;
+	i2c_write(0x49, 0x40, 1, &byte, 1);	// ?
+	byte = 0x00;
+	i2c_write(0x49, 0x41, 1, &byte, 1);	// ?
+	byte = 0x00;
+	i2c_write(0x49, 0x42, 1, &byte, 1);	// ?
+	byte = 0x00;
+	i2c_write(0x49, 0x43, 1, &byte, 1);	// ?
+ */
+	byte = 0x00;
+	i2c_write(0x49, 0x44, 1, &byte, 1);	// RX_PATH_SEL
+	byte = 0x00;
+	i2c_write(0x49, 0x45, 1, &byte, 1);	// VDL_APGA_CTL
+	byte = 0x00;
+	i2c_write(0x49, 0x46, 1, &byte, 1);	// VIBRA_CTL
+	byte = 0x00;
+	i2c_write(0x49, 0x47, 1, &byte, 1);	// VIBRA_SET
+	byte = 0x00;
+	i2c_write(0x49, 0x48, 1, &byte, 1);	// ANAMIC_GAIN
+	byte = 0x00;
+	i2c_write(0x49, 0x49, 1, &byte, 1);	// MISC_SET_2
+
+	// check for errors...
+	
+	// initialize McBSP2 and fill with data ???
+	
+	*((uint *) 0x4902208c) = 0x00000208;	// MCBSPLP_SYSCONFIG_REG
+	*((uint *) 0x49022090) = 0x00000000;	// MCBSPLP_THRSH2_REG
+	*((uint *) 0x49022094) = 0x00000000;	// MCBSPLP_THRSH1_REG
+	*((uint *) 0x490220ac) = 0x00001008;	// MCBSPLP_XCCR_REG
+	*((uint *) 0x490220b0) = 0x00000808;	// MCBSPLP_RCCR_REG
+	*((uint *) 0x49022018) = 0x00000000;	// MCBSPLP_RCR2_REG
+	*((uint *) 0x4902201c) = 0x00000000;	// MCBSPLP_RCR1_REG
+	*((uint *) 0x49022020) = 0x00000000;	// MCBSPLP_XCR2_REG
+	*((uint *) 0x49022024) = 0x00000000;	// MCBSPLP_XCR1_REG
+	*((uint *) 0x49022028) = 0x00000000;	// MCBSPLP_SRGR2_REG
+	*((uint *) 0x4902202c) = 0x00000000;	// MCBSPLP_SRGR1_REG
+	*((uint *) 0x49022048) = 0x00000083;	// MCBSPLP_PCR_REG	/ SCLKME, CLKXP, CLKRP
+	*((uint *) 0x49022010) = 0x00000200;	// MCBSPLP_SPCR2_REG / FREE, !XRST
+	*((uint *) 0x49022014) = 0x00000000;	// MCBSPLP_SPCR1_REG / !RRST
+//	*((uint *) 0x4902207c) = 0x00000023;	// MCBSPLP_REV_REG (is read only???)
+	*((uint *) 0x49022010) = 0x00000201;	// MCBSPLP_SPCR2_REG / FREE, XRST
+	*((uint *) 0x49022008) = 0x000056f3;	// MCBSPLP_DXR_REG - write first byte
+	printf("  ... complete\n");
+	return 0;
+
+}
+
+int audiotest_send(void)
+{
+	int count = 0;
+	printf("Sending data");
+
+	for (count = 0; count < 50; count++) {
+		int bytes;
+		for (bytes = 0; bytes < sizeof(tone) / 2; bytes++) {
+			*((uint *) 0x49022008) = tone[bytes];	// MCBSPLP_DXR_REG
+			udelay(100);
+		}
+	}
+	printf("  ... complete\n");
+
+	return 0;
+}
+
+int audiotest(int channel)
+{
+	return audiotest_init(channel) || audiotest_send();
+}
+
+#define RS232_ENABLE	13
+#define RS232_RX		165	// UART3
+#define RS232_TX		166	// UART3
+
+int irdatest(void)
+{
+#ifdef CONFIG_OMAP3_GTA04
+	printf("Stop through touch screen or AUX button - RS232 is disabled\n");
+	udelay(50000);	// wait until RS232 is finished
+	// switch RS232_ENABLE to IrDA through Pull-Down and RXTX to GPIO mode
+	MUX_VAL(CP(UART3_RX_IRRX),	(IEN  | PTD | DIS | M4)); /*UART3_RX_IRRX*/
+	MUX_VAL(CP(UART3_TX_IRTX),	(IDIS | PTD | DIS | M4)); /*UART3_TX_IRTX*/
+	omap_request_gpio(RS232_RX);
+	omap_set_gpio_direction(RS232_RX, 1);	// 1=input
+	omap_request_gpio(RS232_TX);
+	omap_set_gpio_direction(RS232_TX, 0);
+	omap_set_gpio_dataout(RS232_TX, 0);	// set TX=low to select SIR mode
+	udelay(10);
+	MUX_VAL(CP(ETK_CTL_ES2),	(IEN  | PTD | EN  | M4)); /*GPIO_13 - RS232 enable*/
+	udelay(1000);
+	while(!pendown(NULL, NULL) && (status_get_buttons()&0x09) == 0)
+		{
+		// make IrDA blink
+		omap_set_gpio_dataout(RS232_TX, 1);
+		udelay(150);
+		omap_set_gpio_dataout(RS232_TX, 0);
+		udelay(150);
+		if(!omap_get_gpio_datain(RS232_RX))	// RX is active low
+			status_set_status(0x018);	// echo IrDA sensor status to red power button led
+		else
+			status_set_status(0x000);
+		}
+	// switch back to UART mode
+	MUX_VAL(CP(UART3_RX_IRRX),	(IEN  | PTD | DIS | M0)); /*UART3_RX_IRRX*/
+	MUX_VAL(CP(UART3_TX_IRTX),	(IDIS | PTD | DIS | M0)); /*UART3_TX_IRTX*/
+	MUX_VAL(CP(ETK_CTL_ES2),	(IEN  | PTU | EN  | M4)); /*GPIO_13 - RS232 enable*/
+	udelay(1000);
+	printf("done.\n");
+	return 0;
+#else
+	printf("n/a\n");
+	return 1;
+#endif
+}
+
+#ifdef CONFIG_OMAP3_GTA04
+int wlabbtpower(void)
+{ /* Bluetooth VAUX4 = 3.3V -- CHECKME: 3.3 V is not officially supported by TPS! We use 0x09 = 2.8V here*/
+#define TCA6507_BUS			(2-1)	// I2C2
+#define TCA6507_ADDRESS		0x45
+	
+	/* register numbers */
+#define TCA6507_SELECT0						0
+#define TCA6507_SELECT1						1
+#define TCA6507_SELECT2						2
+	
+	printf("activate WiFi/BT reset\n");
+	i2c_set_bus_num(TCA6507_BUS);	// write I2C2
+	i2c_reg_write(TCA6507_ADDRESS, TCA6507_SELECT0, 0);
+	i2c_reg_write(TCA6507_ADDRESS, TCA6507_SELECT1, 0);
+	i2c_reg_write(TCA6507_ADDRESS, TCA6507_SELECT2, 0x40);	// pull down reset for WLAN&BT chip
+	i2c_set_bus_num(0);	// write I2C1
+	printf("power on VAUX4\n");
+	twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VAUX4_DEDICATED,
+							/* 2.8V: */ 0x09 /* 3.15V: 0x0c */,
+							TWL4030_PM_RECEIVER_VAUX4_DEV_GRP,
+							TWL4030_PM_RECEIVER_DEV_GRP_P1);
+	udelay(20*1000);	// wait a little until power stabilizes
+	printf("release WiFi/BT reset\n");
+	i2c_set_bus_num(TCA6507_BUS);	// write I2C2
+	i2c_reg_write(TCA6507_ADDRESS, TCA6507_SELECT0, 0);
+	i2c_reg_write(TCA6507_ADDRESS, TCA6507_SELECT1, 0);
+	i2c_reg_write(TCA6507_ADDRESS, TCA6507_SELECT2, 0);	// release reset for WLAN&BT chip
+	i2c_set_bus_num(0);	// write I2C1
+	return 0;
+}
+#endif
+
+int wlanbttest(int test)
+{ /* Bluetooth VAUX4 = 3.3V -- CHECKME: 3.3 V is not officially supported! We use 0x09 = 2.8V here*/
+#ifdef CONFIG_OMAP3_GTA04
+	wlabbtpower();
+	if(test)
+		{
+		// now, we should be able to test the UART for the BT part...
+		return !bt_hci(1);
+		}
+	return 0;
+#else
+	printf("n/a\n");
+	return 1;
+#endif
+}
+
+int OTGchargepump(int enable)
+{
+	if(enable)
+		twl4030_i2c_write_u8(TWL4030_CHIP_USB, 0x20, TWL4030_USB_OTG_CTRL_SET);
+	else
+		twl4030_i2c_write_u8(TWL4030_CHIP_USB, 0x20, TWL4030_USB_OTG_CTRL_CLR);
+	return 0;
+}
+
+static struct
+{
+	int gpio;
+	int inputonly;		// can't switch to output mode (Table 2-24. General-Purpose IOs Signals Description)
+	char *name;
+	unsigned offset;	// PIN-MUX control address -> writew((VALUE), OMAP34XX_CTRL_BASE + (OFFSET));
+} gpiotable[] = {
+	{ 7, 0, "AUX button", CP(SYS_BOOT5) },
+	
+	{ 10, 0, "A3: KEYIRQ / A4: 3G_WAKE", CP(SYS_CLKOUT1) },
+	
+	{ 12, 0, "Display SCL", CP(ETK_CLK_ES2) },
+	
+	// CHECKME: doesn't this interfere with RS232 operation?
+	//	{ 13, 1, "RS232 enable", CP(ETK_CTL_ES2) }, 
+	
+	{ 18, 0, "Display DR", CP(ETK_D4_ES2) },
+	{ 19, 0, "Display XCS", CP(ETK_D5_ES2) },
+	{ 20, 0, "Display DX", CP(ETK_D6_ES2) },
+	{ 21, 0, "RS232 EXT", CP(ETK_D7_ES2) },
+	
+	{ 23, 0, "Video out en", CP(ETK_D9_ES2) },
+	{ 24, 0, "HSUSB2_CLK", CP(ETK_D10_ES2) },
+	{ 25, 0, "HSUSB2_STP", CP(ETK_D11_ES2) },
+	{ 26, 0, "HSUSB2_DIR", CP(ETK_D12_ES2) },
+	{ 27, 0, "HSUSB2_NXT", CP(ETK_D13_ES2) },
+	{ 28, 0, "HSUSB2_DATA0", CP(ETK_D14_ES2) },
+	{ 29, 0, "HSUSB2_DATA1", CP(ETK_D15_ES2) },
+	
+	{ 54, 0, "PoP Temp", CP(GPMC_NCS3) },
+	{ 55, 0, "Audio out en", CP(GPMC_NCS4) },
+	{ 56, 0, "Gyro int", CP(GPMC_NCS5) },	
+	{ 57, 0, "Backlight en", CP(GPMC_NCS6) },
+	
+	{ 66, 0, "PCLK", CP(DSS_PCLK) },
+	{ 67, 0, "HSYNC", CP(DSS_HSYNC) },
+	{ 68, 0, "VSYNC", CP(DSS_VSYNC) },
+	{ 69, 0, "DE", CP(DSS_ACBIAS) },
+	{ 70, 0, "DSS0", CP(DSS_DATA0) },
+	{ 71, 0, "DSS1", CP(DSS_DATA1) },
+	{ 72, 0, "DSS2", CP(DSS_DATA2) },
+	{ 73, 0, "DSS3", CP(DSS_DATA3) },
+	{ 74, 0, "DSS4", CP(DSS_DATA4) },
+	{ 75, 0, "DSS5", CP(DSS_DATA5) },
+	{ 76, 0, "DSS6", CP(DSS_DATA6) },
+	{ 77, 0, "DSS7", CP(DSS_DATA7) },
+	{ 78, 0, "DSS8", CP(DSS_DATA8) },
+	{ 79, 0, "DSS9", CP(DSS_DATA9) },
+	{ 80, 0, "DSS10", CP(DSS_DATA10) },
+	{ 81, 0, "DSS11", CP(DSS_DATA11) },
+	{ 82, 0, "DSS12", CP(DSS_DATA12) },
+	{ 83, 0, "DSS13", CP(DSS_DATA13) },
+	{ 84, 0, "DSS14", CP(DSS_DATA14) },
+	{ 85, 0, "DSS15", CP(DSS_DATA15) },
+	{ 86, 0, "DSS16", CP(DSS_DATA16) },
+	{ 87, 0, "DSS17", CP(DSS_DATA17) },
+	{ 88, 0, "DSS18", CP(DSS_DATA18) },
+	{ 89, 0, "DSS19", CP(DSS_DATA19) },
+	{ 90, 0, "DSS20", CP(DSS_DATA20) },
+	{ 91, 0, "DSS21", CP(DSS_DATA21) },
+	{ 92, 0, "DSS22", CP(DSS_DATA22) },
+	{ 93, 0, "DSS23", CP(DSS_DATA23) },
+	{ 94, 0, "CAM_HS", CP(CAM_HS) },
+	{ 95, 0, "CAM_VS", CP(CAM_VS) },
+	{ 96, 0, "CAM_XCLKA", CP(CAM_XCLKA) },
+	{ 97, 0, "CAM_PCLK", CP(CAM_PCLK) },
+	{ 98, 0, "CAM_RESET", CP(CAM_FLD) },
+	{ 99, 1, "CAM_D0", CP(CAM_D0) },
+	{ 100, 1, "CAM_D1", CP(CAM_D1) },
+	{ 101, 0, "CAM_D2", CP(CAM_D2) },
+	{ 102, 0, "CAM_D3", CP(CAM_D3) },
+	{ 103, 0, "CAM_D4", CP(CAM_D4) },
+	{ 104, 0, "CAM_D5", CP(CAM_D5) },
+	{ 105, 1, "CAM_D6", CP(CAM_D6) },
+	{ 106, 1, "CAM_D7", CP(CAM_D7) },
+	{ 107, 1, "CAM_D8", CP(CAM_D8) },
+	{ 108, 1, "CAM_D9", CP(CAM_D9) },
+	{ 109, 0, "CAM_D10", CP(CAM_D10) },
+	{ 110, 0, "CAM_D11", CP(CAM_D11) },
+	{ 111, 0, "CAM_XCLKB", CP(CAM_XCLKB) },
+	{ 112, 1, "Compass rdy", CP(CSI2_DX0) },
+	{ 113, 1, "Baro EOC", CP(CSI2_DY0) },
+	{ 114, 1, "Accel2 int", CP(CSI2_DX1) },
+	{ 115, 1, "Accel1 int", CP(CSI2_DY1) },
+	{ 116, 0, "Audio_FSX", CP(MCBSP2_FSX) },
+	{ 117, 0, "Audio_CLKX", CP(MCBSP2_CLKX) },
+	{ 118, 0, "Audio_DR", CP(MCBSP2_DR) },
+	{ 119, 0, "Audio_DX", CP(MCBSP2_DX) },
+
+	/*	this are duplicate GPIOs with MMC1
+	{ 120, 0, "HSUSB0_CLK", CP(HSUSB0_CLK) },
+	{ 121, 0, "HSUSB0_STP", CP(HSUSB0_STP) },
+	{ 122, 0, "HSUSB0_DIR", CP(HSUSB0_DIR) },
+	
+	{ 124, 0, "HSUSB0_NXT", CP(HSUSB0_NXT) },
+	{ 125, 0, "HSUSB0_DATA0", CP(HSUSB0_DATA0) },
+	 */
+
+	{ 126, 0, "CAM_STROBE", CP(CAM_STROBE) },
+	
+	/*	this are duplicate GPIOs with MMC2
+	 { 130, 0, "HSUSB0_DATA1", CP(HSUSB0_DATA1) },
+	 { 131, 0, "HSUSB0_DATA2", CP(HSUSB0_DATA2) },
+	 */
+	
+	{ 130, 0, "MMC2_CLK", CP(MMC2_CLK) },
+	{ 131, 0, "MMC2_CMD", CP(MMC2_CMD) },
+	{ 132, 0, "MMC2_DAT0", CP(MMC2_DAT0) },
+	{ 133, 0, "MMC2_DAT1", CP(MMC2_DAT1) },
+	{ 134, 0, "MMC2_DAT2", CP(MMC2_DAT2) },
+	{ 135, 0, "MMC2_DAT3", CP(MMC2_DAT3) },
+	{ 136, 0, "MMC2_DIR_DAT0", CP(MMC2_DAT4) },
+	{ 137, 0, "MMC2_DIR_DAT1", CP(MMC2_DAT5) },
+	{ 138, 0, "MMC2_DIR_CMD", CP(MMC2_DAT6) },
+	{ 139, 0, "MMC2_DIR_CLKIN", CP(MMC2_DAT7) },	
+	{ 140, 0, "BT_DX", CP(MCBSP3_DX) },
+	{ 141, 0, "BT_DR", CP(MCBSP3_DR) },
+	{ 142, 0, "BT_CLKX", CP(MCBSP3_CLKX) },
+	{ 143, 0, "BT_FSX", CP(MCBSP3_FSX) },
+	{ 144, 0, "Ext Ant", CP(UART2_CTS) },
+//	{ 145, 0, "GPS enable", CP(UART2_RTS) },	// should remain disabled!
+	{ 146, 0, "GPS_TX", CP(UART2_TX) },
+	{ 147, 0, "GPS_RX", CP(UART2_RX) },
+	{ 148, 0, "BT_TX", CP(UART1_TX) },
+	{ 149, 0, "BT_RTS", CP(UART1_RTS) },
+	{ 150, 0, "BT_CTS", CP(UART1_CTS) },
+	{ 151, 0, "BT_RX", CP(UART1_RX) },
+	{ 152, 0, "WWAN_CLKX", CP(MCBSP4_CLKX) },
+	{ 153, 0, "WWAN_DR", CP(MCBSP4_DR) },
+	{ 154, 0, "WWAN_DX", CP(MCBSP4_DX) },
+	{ 155, 0, "WWAN_FSX", CP(MCBSP4_FSX) },
+	{ 156, 0, "FM_CLKR", CP(MCBSP1_CLKR) },
+	{ 157, 0, "FM_FSR", CP(MCBSP1_FSR) },
+	{ 158, 0, "FM_DX", CP(MCBSP1_DX) },
+	{ 159, 0, "FM_DR", CP(MCBSP1_DR) },
+	{ 160, 0, "PENIRQ", CP(MCBSP_CLKS) },
+	{ 161, 0, "FM_FSX", CP(MCBSP1_FSX) },
+	{ 162, 0, "FM_CLKX", CP(MCBSP1_CLKX) },
+		
+	{ 167, 0, "CAM_PWDN", CP(CAM_WEN) },
+	
+	{ 169, 0, "HSUSB0_DATA3", CP(HSUSB0_DATA3) },
+
+	{ 171, 0, "Revision 0x1", CP(MCSPI1_CLK) },
+	{ 172, 0, "Revision 0x2", CP(MCSPI1_SIMO) },
+	{ 173, 0, "Revision 0x4", CP(MCSPI1_SOMI) },
+//	{ 174, 0, "USB3322 reset", CP(MCSPI1_CS0) },	// should remain in reset state
+	{ 175, 0, "A3: HOST_WAKE / A4:spare", CP(MCSPI1_CS1) },
+	{ 176, 0, "A3: 3G_WAKE / A4: KEYIRQ", CP(MCSPI1_CS2) },
+	{ 177, 0, "HSUSB2_DATA2", CP(MCSPI1_CS3) },
+	{ 178, 0, "HSUSB2_DATA7", CP(MCSPI2_CLK) },
+	{ 179, 0, "HSUSB2_DATA4", CP(MCSPI2_SIMO) },
+	{ 180, 0, "HSUSB2_DATA5", CP(MCSPI2_SOMI) },
+	{ 181, 0, "HSUSB2_DATA6", CP(MCSPI2_CS0) },
+	{ 182, 0, "HSUSB2_DATA3", CP(MCSPI2_CS1) },
+	
+	{ 186, 0, "A3: spare / A4: ON_KEY", CP(SYS_CLKOUT2) },
+	
+	{ 188, 0, "HSUSB0_DATA4", CP(HSUSB0_DATA4) },
+	{ 189, 0, "HSUSB0_DATA5", CP(HSUSB0_DATA5) },
+	{ 190, 0, "HSUSB0_DATA6", CP(HSUSB0_DATA6) },
+	{ 191, 0, "HSUSB0_DATA7", CP(HSUSB0_DATA7) },
+	
+};
+
+
+int gpiotest(void)
+{
+	int i;
+	printf("testing GPIOs for stuck-at, floating and shorts\n");
+	omap_set_gpio_direction(174, 0);	// switch to output
+	omap_set_gpio_dataout(174, 0); // activate reset of USB3322
+	// Camera reset?
+	// WLAN-Reset?
+	// switch off GPS (if on)
+	for(i=0; i<sizeof(gpiotable)/sizeof(gpiotable[0]); i++)
+		{
+		int g=gpiotable[i].gpio;
+		omap_request_gpio(g);
+		omap_set_gpio_direction(g, 1);	// make them all inputs
+		if(gpiotable[i].offset)
+			writew((IEN  | PTD | DIS | M4), OMAP34XX_CTRL_BASE + (gpiotable[i].offset));	// make input GPIO w/o pullup/down
+		udelay(100);
+		}
+	for(i=0; i<sizeof(gpiotable)/sizeof(gpiotable[0]); i++)
+		{ // loop over all inputs
+			int g=gpiotable[i].gpio;
+			char *n=gpiotable[i].name;
+			int j;
+			for(j=0; j<sizeof(gpiotable)/sizeof(gpiotable[0]); j++)
+				{ // check for shorts with other GPIOs switched to output
+					int gj=gpiotable[j].gpio;
+					char *nj=gpiotable[j].name;
+					int valdn, valup; 
+					int stuck=0;	// if known to be stuck
+					int follows=0;	// if known to follow
+					if(!gpiotable[j].inputonly)
+						{ // test with active I/O
+							omap_set_gpio_direction(gj, 0);	// switch to output
+							udelay(100);
+							omap_set_gpio_dataout(gj, 0); // set other output to 0
+							udelay(100);
+							valdn=omap_get_gpio_datain(g);	// read value of input GPIO under test
+							omap_set_gpio_dataout(gj, 1); // set other output to 1
+							udelay(100);
+							valup=omap_get_gpio_datain(g);	// read value of input GPIO under test
+							omap_set_gpio_direction(gj, 1);	// switch back to input
+							udelay(300);
+							if(valdn == 0 && valup == 1)
+								{ // our input follows the other in output mode
+								if(i != j)
+									printf("GPIO %d (%s) follows GPIO %d (%s)\n", g, n, gj, nj), follows=1;
+								}
+							else if(i == j)
+								{ // output does *not* read back the input value -> shorted
+									if(valdn == 0 && valup == 0)
+										printf("GPIO %d (%s) stuck at 0\n", g, n), stuck=1;
+									else if(valdn == 1 && valup == 1)
+										printf("GPIO %d (%s) stuck at 1\n", g, n), stuck=1;
+								}
+						}
+					writew((IEN  | PTD | EN | M4), OMAP34XX_CTRL_BASE + (gpiotable[j].offset));	// make other GPIO input with pulldown
+					udelay(300);
+					valdn=omap_get_gpio_datain(g);	// read value of GPIO under test
+					writew((IEN  | PTU | EN | M4), OMAP34XX_CTRL_BASE + (gpiotable[j].offset));	// make other GPIO input with pullup
+					udelay(300);
+					valup=omap_get_gpio_datain(g);	// read value of GPIO under test
+					writew((IEN  | PTD | DIS | M4), OMAP34XX_CTRL_BASE + (gpiotable[j].offset)); // make other GPIO w/o pullup/down
+					udelay(100);
+					if(valdn == 0 && valup == 1)
+						{ // follows the other pull-up/down
+							if(i == j)
+								printf("GPIO %d (%s) floating\n", g, n);	// follows our own pull-up/down
+							else if(!follows)
+								printf("GPIO %d (%s) weakly follows GPIO %d (%s)\n", g, n, gj, nj, gpiotable[j].inputonly?" (strong not tested)":"");	// -> GPIOs are connected with low to high resistance
+						}
+					else if(i == j && !stuck)
+						{
+						if(valdn == 0 && valup == 0)
+							printf("GPIO %d (%s) weak 0%s\n", g, n, gpiotable[j].inputonly?" (strong not tested)":"");
+						else if(valdn == 1 && valup == 1)
+							printf("GPIO %d (%s) weak 1%s\n", g, n, gpiotable[j].inputonly?" (strong not tested)":"");
+						}
+				}
+		}											 
+	return 0;
+}
+	
diff --git a/u-boot/board/goldelico/gta04/systest.h b/u-boot/board/goldelico/gta04/systest.h
new file mode 100644
index 0000000..4126b3b
--- /dev/null
+++ b/u-boot/board/goldelico/gta04/systest.h
@@ -0,0 +1,36 @@
+/* u-boot extended commands for GTA04
+ *
+ * Copyright (C) 2010 by Golden Delicious Computers GmbH&Co. KG
+ * Author: H. Nikolaus Schaller <hns@goldelico.com>
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#ifndef _SYSTEST_H
+#define _SYSTEST_H
+
+int systest(void);
+int audiotest_init(int channel);
+int audiotest_send(void);
+int audiotest(int channel);
+int irdatest(void);
+int wlanbttest(int serial);
+int OTGchargepump(int enable);
+int gpiotest(void);
+
+#endif
diff --git a/u-boot/board/goldelico/gta04/tsc2007.c b/u-boot/board/goldelico/gta04/tsc2007.c
new file mode 100644
index 0000000..b2a0cfa
--- /dev/null
+++ b/u-boot/board/goldelico/gta04/tsc2007.c
@@ -0,0 +1,181 @@
+/* u-boot driver for the TSC2007 connected to I2C2
+ *
+ * Copyright (C) 2010 by Golden Delicious Computers GmbH&Co. KG
+ * Author: H. Nikolaus Schaller <hns@goldelico.com>
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <asm/errno.h>
+#include <asm/io.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/gpio.h>
+#include <asm/mach-types.h>
+#include <i2c.h>
+#include "tsc2007.h"
+
+#define TSC2007_BUS 2	// I2C2
+#define TSC2007_ADDRESS 0x48
+
+// command byte definitions:
+// channel selection and power down
+
+#define TSC2007_TEMP0	0x00
+#define TSC2007_AUX		0x20
+#define TSC2007_TEMP1	0x40
+#define TSC2007_ACTX	0x80
+#define TSC2007_ACTY	0x90
+#define TSC2007_ACTXY	0xA0
+#define TSC2007_X		0xc0
+#define TSC2007_Y		0xd0
+#define TSC2007_Z1		0xe0
+#define TSC2007_Z2		0xf0
+
+#define TSC2007_POWER_DOWN		0x00	// must be sent once after power up
+#define TSC2007_ADC_ON			0x04
+#define TSC2007_ADC_OFF_PENIRQ	0x08
+
+#define TSC2007_12Bit2MHz		0x00
+#define TSC2007_8Bit4MHz		0x02
+
+// setup command
+
+#define TSC2007_SETUP		0xb0
+
+#define TSC2007_USE_MAV		0x00
+#define TSC2007_BYPASS_MAV	0x02
+
+#define TSC2007_50kPUP		0x00
+#define TSC2007_90kPUP		0x01
+
+/*
+ int i2c_read(u_int8_t chip, u_int32_t addr, int alen, u_int8_t *buf, int len)
+ int i2c_write(u_int8_t chip, u_int32_t addr, int alen, u_int8_t *buf, int len)
+*/
+
+static int didNotInit=1;
+
+int tsc2007_cmd(int cmd)
+{ // send command
+	unsigned char buf[16];
+	buf[0]=cmd;
+	if (i2c_write(TSC2007_ADDRESS, cmd, 1, buf, 0))	// write 1 byte command
+		{
+			printf ("Error writing the TSC.\n");
+			return 1;
+		}
+	return 0;
+}
+
+int tsc2007_init(void)
+{
+	if(i2c_set_bus_num(TSC2007_BUS-1))
+		{
+			printf ("could not select I2C2\n");
+			return 1;
+		}
+	
+	if(i2c_probe(TSC2007_ADDRESS))
+		{
+		printf ("could not probe TSC2007\n");
+		return 1;		
+		}
+	
+	didNotInit = tsc2007_cmd(TSC2007_SETUP|TSC2007_USE_MAV|TSC2007_50kPUP);
+	didNotInit |= tsc2007_cmd(TSC2007_POWER_DOWN);
+	
+	if(didNotInit)
+		printf("did tsc2007_init() failed.\n");
+	else
+		printf("did tsc2007_init()\n");
+
+	return 0;
+}
+
+int read_adc(int adcnum)
+{ // read ADC and return value in range 0..4095
+	unsigned char c;
+	unsigned char buf[16];
+	static int cmd[]={ 
+		TSC2007_X,
+		TSC2007_Y,
+		TSC2007_Z1,
+		TSC2007_Z2,
+		TSC2007_TEMP0,
+		TSC2007_TEMP1,
+		TSC2007_AUX,
+		TSC2007_AUX
+	};
+	if(didNotInit)
+		return -1;
+	if(i2c_get_bus_num() != TSC2007_BUS-1 && i2c_set_bus_num(TSC2007_BUS-1))
+		{
+		printf ("could not select I2C2\n");
+		return -1;
+		}
+	c=cmd[adcnum%8] | TSC2007_ADC_ON | TSC2007_12Bit2MHz;
+//	printf("send %02x\n", c);
+	if (i2c_read(TSC2007_ADDRESS, c, 1, buf, 1))
+		{
+			printf ("Error reading the TSC.\n");
+			return -1;
+		}
+	return ((unsigned)buf[0]) << 4;	// read 1 byte only
+	
+//	return (buf[0]<<4)+(buf[1]>>4);	// 12 bit
+}
+
+void print_adc(void)
+{
+	printf("0:%04u 1:%04u 2:%04u 3:%04u 4:%04u 5:%04u 6:%04u 7:%04u",
+		   read_adc(0),
+		   read_adc(1),
+		   read_adc(2),
+		   read_adc(3),
+		   read_adc(4),
+		   read_adc(5),
+		   read_adc(6),
+		   read_adc(7));
+}
+
+int pendown(int *x, int *y)
+{
+#if 1
+	int z;
+	int xx;
+	int yy;
+	xx=read_adc(0);
+	yy=read_adc(1);
+	z=read_adc(2);	// read Z
+	if(z < 0)
+		return 0;	// read error
+#if 0
+	printf("z=%04d x:%04d y:%04d\n", z, xx, yy);
+#endif
+	if(x) *x=xx;
+	if(y) *y=yy;
+	udelay(10000);	// reduce I2C traffic and debounce...
+	return z > 200;	// was pressed
+#else
+	// must be in PENIRQ mode...
+	return (status_get_buttons() & (1 << 4)) == 0;
+#endif
+}
+
diff --git a/u-boot/board/goldelico/gta04/tsc2007.h b/u-boot/board/goldelico/gta04/tsc2007.h
new file mode 100644
index 0000000..476d253
--- /dev/null
+++ b/u-boot/board/goldelico/gta04/tsc2007.h
@@ -0,0 +1,9 @@
+#ifndef _TSC2007_H
+#define _TSC2007_H
+
+int tsc2007_init(void);
+int read_adc(int adcnum);
+void print_adc(void);
+int pendown(int *x, int *y);
+
+#endif
diff --git a/u-boot/board/goldelico/gta04/twl4030-additions.c b/u-boot/board/goldelico/gta04/twl4030-additions.c
new file mode 100644
index 0000000..89d94f2
--- /dev/null
+++ b/u-boot/board/goldelico/gta04/twl4030-additions.c
@@ -0,0 +1,509 @@
+/*
+ * Copyright (C) 2007-2008 Texas Instruments, Inc.
+ *
+ * (C) Copyright 2009
+ * Windriver, <www.windriver.com>
+ * Tom Rix <Tom.Rix@windriver.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * this patch was found here: https://gforge.ti.com/gf/project/omapandroid/mailman/?action=ListThreads&mailman_id=22&_forum_action=ForumMessageBrowse&thread_id=1252
+ *
+ */
+#include <twl4030.h>
+#include "twl4030-additions.h"
+
+/*
+ * Battery
+ */
+
+#define mdelay(n) ({ unsigned long msec = (n); while (msec--) udelay(1000); })
+
+static inline int clear_n_set(u8 chip_no, u8 clear, u8 set, u8 reg)
+{
+	int ret;
+	u8 val = 0;
+	
+	/* Gets the initial register value */
+	ret = twl4030_i2c_read_u8(chip_no, &val, reg);
+	if (ret) {
+		printf("a\n");
+		return ret;
+	}
+	
+	/* Clearing all those bits to clear */
+	val &= ~(clear);
+	
+	/* Setting all those bits to set */
+	val |= set;
+	
+	/* Update the register */
+	ret = twl4030_i2c_write_u8(chip_no, val, reg);
+	if (ret) {
+		printf("b\n");
+		return ret;
+	}
+	return 0;
+}
+
+/*
+ * Disable/Enable AC Charge funtionality.
+ */
+static int twl4030_ac_charger_enable(int enable)
+{
+	int ret;
+	
+	if (enable) {
+		/* forcing the field BCIAUTOAC (BOOT_BCI[0]) to 1 */
+		ret = clear_n_set(TWL4030_CHIP_PM_MASTER, 0,
+						  +	 (CONFIG_DONE | BCIAUTOWEN | BCIAUTOAC),
+						  +	 REG_BOOT_BCI);
+		if (ret)
+			return ret;
+	} else {
+		/* forcing the field BCIAUTOAC (BOOT_BCI[0]) to 0 */
+		ret = clear_n_set(TWL4030_CHIP_PM_MASTER, BCIAUTOAC,
+						  +	 (CONFIG_DONE | BCIAUTOWEN),
+						  +	 REG_BOOT_BCI);
+		if (ret)
+			return ret;
+	}
+	return 0;
+}
+
+/*
+ * Disable/Enable USB Charge funtionality.
+ */
+static int twl4030_usb_charger_enable(int enable)
+{
+	u8 value;
+	int ret;
+	
+	if (enable) {
+		/* enable access to BCIIREF1 */
+		ret = twl4030_i2c_write_u8(TWL4030_CHIP_MAIN_CHARGE, 0xE7,
+								   +	 REG_BCIMFKEY);
+		if (ret)
+			return ret;
+		
+		/* set charging current = 852mA */
+		ret = twl4030_i2c_write_u8(TWL4030_CHIP_MAIN_CHARGE, 0xFF,
+								   +	 REG_BCIIREF1);
+		if (ret)
+			return ret;
+		
+		/* forcing the field BCIAUTOUSB (BOOT_BCI[1]) to 1 */
+		ret = clear_n_set(TWL4030_CHIP_PM_MASTER, 0,
+						  +	 (CONFIG_DONE | BCIAUTOWEN | BCIAUTOUSB),
+						  +	 REG_BOOT_BCI);
+		if (ret)
+			return ret;
+		
+		/* Enabling interfacing with usb thru OCP */
+		ret = clear_n_set(TWL4030_CHIP_USB, 0, PHY_DPLL_CLK,
+						  +	 REG_PHY_CLK_CTRL);
+		if (ret)
+			return ret;
+		
+		value = 0;
+		
+		while (!(value & PHY_DPLL_CLK)) {
+			udelay(10);
+			ret = twl4030_i2c_read_u8(TWL4030_CHIP_USB, &value,
+									  +	 REG_PHY_CLK_CTRL_STS);
+			if (ret)
+				return ret;
+		}
+		
+		/* OTG_EN (POWER_CTRL[5]) to 1 */
+		ret = clear_n_set(TWL4030_CHIP_USB, 0, OTG_EN,
+						  +	 REG_POWER_CTRL);
+		if (ret)
+			return ret;
+		
+		mdelay(50);
+		
+		/* forcing USBFASTMCHG(BCIMFSTS4[2]) to 1 */
+		ret = clear_n_set(TWL4030_CHIP_MAIN_CHARGE, 0,
+						  +	 USBFASTMCHG, REG_BCIMFSTS4);
+		if (ret)
+			return ret;
+	} else {
+		ret = clear_n_set(TWL4030_CHIP_PM_MASTER, BCIAUTOUSB,
+						  +	 (CONFIG_DONE | BCIAUTOWEN), REG_BOOT_BCI);
+		if (ret)
+			return ret;
+	}
+	
+	return 0;
+}
+
+/*
+ * Setup the twl4030 MADC module to measure the backup
+ * battery voltage.
+ */
+static int twl4030_madc_setup(void)
+{
+	int ret = 0;
+	
+	/* turning MADC clocks on */
+	ret = clear_n_set(TWL4030_CHIP_INTBR, 0,
+					  +	 (MADC_HFCLK_EN | DEFAULT_MADC_CLK_EN), REG_GPBR1);
+	if (ret)
+		return ret;
+	
+	/* turning adc_on */
+	ret = twl4030_i2c_write_u8(TWL4030_CHIP_MADC, MADC_ON,
+							   +	 REG_CTRL1);
+	if (ret)
+		return ret;
+	
+	/* setting MDC channel 9 to trigger by SW1 */
+	ret = clear_n_set(TWL4030_CHIP_MADC, 0, SW1_CH9_SEL,
+					  +	 REG_SW1SELECT_MSB);
+	
+	return ret;
+}
+
+/*
+ * Charge backup battery through main battery
+ */
+static int twl4030_charge_backup_battery(void)
+{
+	int ret;
+	
+	ret = clear_n_set(TWL4030_CHIP_PM_RECIEVER, 0xff,
+					  +	 (BBCHEN | BBSEL_3200mV | BBISEL_500uA), REG_BB_CFG);
+	if (ret)
+		return ret;
+	
+	return 0;
+}
+
+/*
+ * Helper function to read a 2-byte register on BCI module
+ */
+static int read_bci_val(u8 reg)
+{
+	int ret = 0, temp = 0;
+	u8 val;
+	
+	/* reading MSB */
+	ret = twl4030_i2c_read_u8(TWL4030_CHIP_MAIN_CHARGE, &val, reg + 1);
+	if (ret)
+		return ret;
+	
+	temp = ((int)(val & 0x03)) << 8;
+	
+	/* reading LSB */
+	ret = twl4030_i2c_read_u8(TWL4030_CHIP_MAIN_CHARGE, &val, reg);
+	if (ret)
+		return ret;
+	
+	return temp + val;
+}
+
+/*
+ * Triggers the sw1 request for the twl4030 module to measure the sw1 selected
+ * channels
+ */
+static int twl4030_madc_sw1_trigger(void)
+{
+	u8 val;
+	int ret;
+	
+	/* Triggering SW1 MADC convertion */
+	ret = twl4030_i2c_read_u8(TWL4030_CHIP_MADC, &val, REG_CTRL_SW1);
+	if (ret)
+		return ret;
+	
+	val |= SW1_TRIGGER;
+	
+	ret = twl4030_i2c_write_u8(TWL4030_CHIP_MADC, val, REG_CTRL_SW1);
+	if (ret)
+		return ret;
+	
+	/* Waiting until the SW1 conversion ends*/
+	val = BUSY;
+	
+	while (!((val & EOC_SW1) && (!(val & BUSY)))) {
+		ret = twl4030_i2c_read_u8(TWL4030_CHIP_MADC, &val,
+								  +	 REG_CTRL_SW1);
+		if (ret)
+			return ret;
+		mdelay(10);
+	}
+	
+	return 0;
+}
+
+/*
+ * Return battery voltage
+ */
+static int twl4030_get_battery_voltage(void)
+{
+	int volt;
+	
+	volt = read_bci_val(T2_BATTERY_VOLT);
+	return (volt * 588) / 100;
+}
+
+/*
+ * Return battery temperature (uncalibrated)
+ * current = 10uA, full scale 1023 = 1.5V; prescaler=1
+ * 10k @ 25C -> 0.1V -> 68
+ * 26.6k @ 0C -> 0.26V -> 182
+ */
+
+#define R0C	26600
+#define R25C 10000
+
+#define VSTEP ((15*10000)/1023))
+#define VAL0C (R0C/VSTEP)
+#define VAL25C (R25C/VSTEP)
+
+static int twl4030_get_battery_temperature(void)
+{
+	int temperature;
+	
+	temperature = read_bci_val(T2_BATTERY_TEMP);
+	return ((R0C - temperature) * 25) / (R0C - R25C);	// CHECKME
+//	return ((182 - temperature) * 25) / (182 - 68);	// CHECKME
+}
+
+/*
+ * Return battery current
+ */
+static int twl4030_get_battery_current(void)
+{
+	int current;
+	
+	/* from linux driver
+	 int curr;
+	 int ret;
+	 u8 bcictl1;
+	 
+	 curr = twl4030bci_read_adc_val(TWL4030_BCIICHG);
+	 if (curr < 0)
+	 return curr;
+	 
+	 ret = twl4030_bci_read(TWL4030_BCICTL1, &bcictl1);
+	 if (ret)
+	 return ret;
+	 
+	 ret = (curr * 16618 - 850 * 10000) / 10;
+	 if (bcictl1 & TWL4030_CGAIN)
+	 ret *= 2;
+	 
+	 return ret;
+*/	 
+	
+	current = read_bci_val(T2_BATTERY_CUR);
+	return ((current - 512) * 1) / 1;	// FIXME
+}
+
+/*
+ * Return the battery backup voltage
+ */
+static int twl4030_get_backup_battery_voltage(void)
+{
+	int ret, temp;
+	u8 volt;
+	
+	/* trigger MADC convertion */
+	twl4030_madc_sw1_trigger();
+	
+	ret = twl4030_i2c_read_u8(TWL4030_CHIP_MADC, &volt, REG_GPCH9 + 1);
+	if (ret)
+		return ret;
+	
+	temp = ((int) volt) << 2;
+	
+	ret = twl4030_i2c_read_u8(TWL4030_CHIP_MADC, &volt, REG_GPCH9);
+	if (ret)
+		return ret;
+	
+	temp = temp + ((int) ((volt & MADC_LSB_MASK) >> 6));
+	
+	return (temp * 441) / 100;
+}
+
+/*
+ * Return the AC power supply voltage
+ */
+static int twl4030_get_ac_charger_voltage(void)
+{
+	int volt = read_bci_val(T2_BATTERY_ACVOLT);
+	return (volt * 735) / 100;
+}
+
+/*
+ * Return the USB power supply voltage
+ */
+static int twl4030_get_usb_charger_voltage(void)
+{
+	int volt = read_bci_val(T2_BATTERY_USBVOLT);
+	return (volt * 2058) / 300;
+}
+
+/*
+ * Battery charging main function called from board-specific file
+ */
+
+int twl4030_init_battery_charging(void)
+{
+	u8 batstsmchg, batstspchg, hwsts;
+	int battery_volt = 0, charger_present = 0;
+	int ret = 0;
+	
+#ifdef CONFIG_3430ZOOM2
+	/* For Zoom2 enable Main charge Automatic mode:
+	 * by enabling MADC clocks
+	 */
+	
+	/* Enable AC charging */
+	ret = clear_n_set(TWL4030_CHIP_INTBR, 0,
+					  +	 (MADC_HFCLK_EN | DEFAULT_MADC_CLK_EN), REG_GPBR1);
+	
+	udelay(100);
+	
+	
+	ret = twl4030_i2c_write_u8(TWL4030_CHIP_MAIN_CHARGE, 0xE7,
+							   +	 REG_BCIMFKEY);
+	/* set MAX charging current */
+	ret = twl4030_i2c_write_u8(TWL4030_CHIP_MAIN_CHARGE, 0xFF,
+							   +	 REG_BCIIREF1);
+		
+	/* Done for Zoom2 */
+	return 0;
+#endif
+	
+	/* check for battery presence */
+	ret = twl4030_i2c_read_u8(TWL4030_CHIP_MAIN_CHARGE, &batstsmchg,
+							  +	 REG_BCIMFSTS3);
+	if (ret)
+		return ret;
+	
+	ret = twl4030_i2c_read_u8(TWL4030_CHIP_PRECHARGE, &batstspchg,
+							  +	 REG_BCIMFSTS1);
+	if (ret)
+		return ret;
+	
+	if (!((batstspchg & BATSTSPCHG) || (batstsmchg & BATSTSMCHG))) {
+		printf("no battery\n");
+		return ret;	/* no battery */		
+	}
+	
+	ret = twl4030_madc_setup();
+	if (ret) {
+		printf("twl4030 madc setup error %d\n", ret);
+		return ret;
+	}
+	/* backup battery charges through main battery */
+	ret = twl4030_charge_backup_battery();
+	if (ret) {
+		printf("backup battery charging error\n");
+		return ret;
+	}
+	
+	// SPLITME here - up to here it is init, all below can be a systest user command
+	
+	/* check for charger presence */
+	ret = twl4030_i2c_read_u8(TWL4030_CHIP_PM_MASTER, &hwsts,
+							  +	 REG_STS_HW_CONDITIONS);
+	if (ret)
+		return ret;
+	
+	if (hwsts & STS_CHG) {
+		printf("AC charger detected\n");
+		ret = twl4030_ac_charger_enable(1);
+		if (ret)
+			return ret;
+		charger_present = 1;
+	} else {
+		if (hwsts & STS_VBUS) {
+			printf("USB charger detected\n");
+			charger_present = 1;
+		}
+		/* usb charging is enabled regardless of the whether the
+		 * charger is attached, otherwise the main battery voltage
+		 * cannot be read
+		 */
+		ret = twl4030_usb_charger_enable(1);
+		if (ret)
+			return ret;
+	}
+	battery_volt = twl4030_get_battery_voltage();
+	printf("Main battery charge:    %d mV\n", battery_volt);
+	printf("Battery temperature:    %d C\n", twl4030_get_battery_temperature());
+	printf("Backup battery voltage: %d mV\n", twl4030_get_backup_battery_voltage());
+	printf("AC charger voltage:     %d mV\n", twl4030_get_ac_charger_voltage());
+	printf("USB charger voltage:    %d mV\n", twl4030_get_usb_charger_voltage());
+	printf("Charging current:       %d mA\n", twl4030_get_battery_current());
+	return ret;
+}
+
+#if (defined(CONFIG_TWL4030_KEYPAD) && (CONFIG_TWL4030_KEYPAD))
+/*
+ * Keypad
+ */
+int twl4030_keypad_init(void)
+{
+	int ret = 0;
+	u8 ctrl;
+	ret = twl4030_i2c_read_u8(TWL4030_CHIP_KEYPAD, &ctrl, KEYPAD_KEYP_CTRL_REG);
+	if (!ret) {
+		ctrl |= CTRL_KBD_ON | CTRL_SOFT_NRST;
+		ctrl &= ~CTRL_SOFTMODEN;
+		ret = twl4030_i2c_write_u8(TWL4030_CHIP_KEYPAD, ctrl, KEYPAD_KEYP_CTRL_REG);
+	}
+	return ret;
+}
+
+int twl4030_keypad_reset(void)
+{
+	int ret = 0;
+	u8 ctrl;
+	ret = twl4030_i2c_read_u8(TWL4030_CHIP_KEYPAD, &ctrl, KEYPAD_KEYP_CTRL_REG);
+	if (!ret) {
+		ctrl &= ~CTRL_SOFT_NRST;
+		ret = twl4030_i2c_write_u8(TWL4030_CHIP_KEYPAD, ctrl, KEYPAD_KEYP_CTRL_REG);
+	}
+	return ret;
+}
+
+int twl4030_keypad_keys_pressed(unsigned char *key1, unsigned char *key2)
+{
+	int ret = 0;
+	u8 cb, c, rb, r;
+	for (cb = 0; cb < 8; cb++) {
+		c = 0xff & ~(1 << cb);
+		twl4030_i2c_write_u8(TWL4030_CHIP_KEYPAD, c, KEYPAD_KBC_REG);
+		twl4030_i2c_read_u8(TWL4030_CHIP_KEYPAD, &r, KEYPAD_KBR_REG);
+		for (rb = 0; rb < 8; rb++) {
+			if (!(r & (1 << rb))) {
+				if (!ret)
+					*key1 = cb << 3 | rb;
+				else if (1 == ret)
+					*key2 = cb << 3 | rb;
+				ret++;
+			}
+		}
+	}
+	return ret;
+}
+
+#endif
diff --git a/u-boot/board/goldelico/gta04/twl4030-additions.h b/u-boot/board/goldelico/gta04/twl4030-additions.h
new file mode 100644
index 0000000..4ddd8e2
--- /dev/null
+++ b/u-boot/board/goldelico/gta04/twl4030-additions.h
@@ -0,0 +1,203 @@
+/*
+   * (C) Copyright 2009
+   * Windriver, <www.windriver.com>
+   * Tom Rix <Tom.Rix@windriver.com>
+   *
+   * This program is free software; you can redistribute it and/or
+   * modify it under the terms of the GNU General Public License as
+   * published by the Free Software Foundation; either version 2 of
+   * the License, or (at your option) any later version.
+   *
+   * This program is distributed in the hope that it will be useful,
+   * but WITHOUT ANY WARRANTY; without even the implied warranty of
+   * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+   * GNU General Public License for more details.
+   *
+   * You should have received a copy of the GNU General Public License
+   * along with this program; if not, write to the Free Software
+   * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+   * MA 02111-1307 USA
+   */
+
+#include <common.h>
+#include <i2c.h>
+
+/* I2C chip addresses */
+
+/* USB ID */
+#define TWL4030_CHIP_USB	 0x48
+/* AUD ID */
+#define TWL4030_CHIP_AUDIO_VOICE	0x49
+#define TWL4030_CHIP_GPIO	 0x49
+#define TWL4030_CHIP_INTBR	 0x49
+#define TWL4030_CHIP_PIH	 0x49
+#define TWL4030_CHIP_TEST	 0x49
+/* AUX ID */
+#define TWL4030_CHIP_KEYPAD	 0x4a
+#define TWL4030_CHIP_MADC	 0x4a
+#define TWL4030_CHIP_INTERRUPTS	 0x4a
+#define TWL4030_CHIP_LED	 0x4a
+#define TWL4030_CHIP_MAIN_CHARGE	0x4a
+#define TWL4030_CHIP_PRECHARGE	 0x4a
+#define TWL4030_CHIP_PWM0	 0x4a
+#define TWL4030_CHIP_PWM1	 0x4a
+#define TWL4030_CHIP_PWMA	 0x4a
+#define TWL4030_CHIP_PWMB	 0x4a
+/* POWER ID */
+#define TWL4030_CHIP_BACKUP	 0x4b
+#define TWL4030_CHIP_INT	 0x4b
+#define TWL4030_CHIP_PM_MASTER	 0x4b
+#define TWL4030_CHIP_PM_RECIEVER	0x4b
+#define TWL4030_CHIP_RTC	 0x4b
+#define TWL4030_CHIP_SECURED_REG	0x4b
+
+/* Register base addresses */
+
+/* USB ID */
+#define TWL4030_BASEADD_USB	 0x0000
+/* AUD ID */
+#define TWL4030_BASEADD_AUDIO_VOICE	0x0000
+#define TWL4030_BASEADD_GPIO	 0x0098
+#define TWL4030_BASEADD_INTBR	 0x0085
+#define TWL4030_BASEADD_PIH	 0x0080
+#define TWL4030_BASEADD_TEST	 0x004C
+/* AUX ID */
+#define TWL4030_BASEADD_INTERRUPTS	0x00B9
+#define TWL4030_BASEADD_LED	 0x00EE
+#define TWL4030_BASEADD_MADC	 0x0000
+#define TWL4030_BASEADD_MAIN_CHARGE	0x0074
+#define TWL4030_BASEADD_PRECHARGE	0x00AA
+#define TWL4030_BASEADD_PWM0	 0x00F8
+#define TWL4030_BASEADD_PWM1	 0x00FB
+#define TWL4030_BASEADD_PWMA	 0x00EF
+#define TWL4030_BASEADD_PWMB	 0x00F1
+#define TWL4030_BASEADD_KEYPAD	 0x00D2
+/* POWER ID */
+#define TWL4030_BASEADD_BACKUP	 0x0014
+#define TWL4030_BASEADD_INT	 0x002E
+#define TWL4030_BASEADD_PM_MASTER	0x0036
+#define TWL4030_BASEADD_PM_RECIEVER	0x005B
+#define TWL4030_BASEADD_RTC	 0x001C
+#define TWL4030_BASEADD_SECURED_REG	0x0000
+
+/* Register addresses */
+
+#define REG_STS_HW_CONDITIONS	(TWL4030_BASEADD_PM_MASTER + 0x0F)
+#define STS_VBUS	 0x080
+#define STS_CHG	 0x02
+#define REG_BCICTL1 (TWL4030_BASEADD_PM_MASTER + 0x023)
+#define REG_BCICTL2 (TWL4030_BASEADD_PM_MASTER + 0x024)
+#define CGAIN	 0x020
+#define ITHEN	 0x010
+#define ITHSENS	 0x007
+#define REG_BCIMFTH1	 (TWL4030_BASEADD_PM_MASTER + 0x016)
+#define REG_BCIMFTH2	 (TWL4030_BASEADD_PM_MASTER + 0x017)
+#define BCIAUTOWEN	 (TWL4030_BASEADD_PM_MASTER + 0x020)
+#define CONFIG_DONE	 0x010
+#define BCIAUTOUSB	 0x002
+#define BCIAUTOAC	 0x001
+#define BCIMSTAT_MASK	 0x03F
+#define REG_BOOT_BCI	 (TWL4030_BASEADD_PM_MASTER + 0x007)
+
+#define REG_GPBR1	 (TWL4030_BASEADD_INTBR + 0x0c)
+#define MADC_HFCLK_EN	 0x80
+#define DEFAULT_MADC_CLK_EN	0x10
+
+#define REG_CTRL1	 (TWL4030_BASEADD_MADC + 0x00)
+#define MADC_ON	 0x01
+#define REG_SW1SELECT_MSB	0x07
+#define SW1_CH9_SEL	 0x02
+#define REG_CTRL_SW1	 (TWL4030_BASEADD_MADC + 0x012)
+#define SW1_TRIGGER	 0x020
+#define EOC_SW1	 0x002
+#define BUSY	 0x001
+#define REG_GPCH9	 (TWL4030_BASEADD_MADC + 0x049)
+
+#define REG_BCIMSTATEC	 (TWL4030_BASEADD_MAIN_CHARGE + 0x002)
+#define REG_BCIMFSTS2	 (TWL4030_BASEADD_MAIN_CHARGE + 0x00E)
+#define REG_BCIMFSTS3 (TWL4030_BASEADD_MAIN_CHARGE + 0x00F)
+#define REG_BCIMFSTS4	 (TWL4030_BASEADD_MAIN_CHARGE + 0x010)
+#define REG_BCIMFKEY	 (TWL4030_BASEADD_MAIN_CHARGE + 0x011)
+#define REG_BCIIREF1	 (TWL4030_BASEADD_MAIN_CHARGE + 0x027)
+
+#define REG_BCIMFSTS1	 (TWL4030_BASEADD_PRECHARGE + 0x001)
+#define USBFASTMCHG	 0x004
+#define BATSTSPCHG	 0x004
+#define BATSTSMCHG	 0x040
+#define VBATOV4	 0x020
+#define VBATOV3	 0x010
+#define VBATOV2	 0x008
+#define VBATOV1	 0x004
+#define MADC_LSB_MASK	 0xC0
+#define REG_BB_CFG	 (TWL4030_BASEADD_PM_RECIEVER + 0x12)
+#define BBCHEN	 0x10
+#define	 BBSEL_2500mV	 0x00
+#define	 BBSEL_3000mV	 0x04
+#define	 BBSEL_3100mV	 0x08
+#define	 BBSEL_3200mV	 0x0C
+#define	 BBISEL_25uA	 0x00
+#define	 BBISEL_150uA	 0x01
+#define	 BBISEL_500uA	 0x02
+#define	 BBISEL_1000uA	 0x03
+
+#define REG_POWER_CTRL	 (TWL4030_BASEADD_USB + 0x0AC)
+#define REG_POWER_CTRL_SET (TWL4030_BASEADD_USB + 0x0AD)
+#define REG_POWER_CTRL_CLR	(TWL4030_BASEADD_USB + 0x0AE)
+#define OTG_EN	 0x020
+#define REG_PHY_CLK_CTRL	(TWL4030_BASEADD_USB + 0x0FE)
+#define REG_PHY_CLK_CTRL_STS (TWL4030_BASEADD_USB + 0x0FF)
+#define PHY_DPLL_CLK	 0x01
+
+/* TWL4030 battery measuring parameters */
+#define T2_BATTERY_VOLT	 (TWL4030_BASEADD_MAIN_CHARGE + 0x04)
+#define T2_BATTERY_TEMP	 (TWL4030_BASEADD_MAIN_CHARGE + 0x06)
+#define T2_BATTERY_CUR	 (TWL4030_BASEADD_MAIN_CHARGE + 0x08)
+#define T2_BATTERY_ACVOLT	(TWL4030_BASEADD_MAIN_CHARGE + 0x0A)
+#define T2_BATTERY_USBVOLT	(TWL4030_BASEADD_MAIN_CHARGE + 0x0C)
+
+/* Keypad */
+#define KEYPAD_KEYP_CTRL_REG 0xD2
+#define KEYPAD_KEY_DEB_REG 0xD3
+#define KEYPAD_LONG_KEY_REG1 0xD4
+#define KEYPAD_LK_PTV_REG 0xD5
+#define KEYPAD_TIME_OUT_REG1 0xD6
+#define KEYPAD_TIME_OUT_REG2 0xD7
+#define KEYPAD_KBC_REG 0xD8
+#define KEYPAD_KBR_REG 0xD9
+#define KEYPAD_KEYP_SMS 0xDA
+#define KEYPAD_FULL_CODE_7_0 0xDB
+#define KEYPAD_FULL_CODE_15_8 0xDC
+#define KEYPAD_FULL_CODE_23_16 0xDD
+#define KEYPAD_FULL_CODE_31_24 0xDE
+#define KEYPAD_FULL_CODE_39_32 0xDF
+#define KEYPAD_FULL_CODE_47_40 0xE0
+#define KEYPAD_FULL_CODE_55_48 0xE1
+#define KEYPAD_FULL_CODE_63_56 0xE2
+#define KEYPAD_KEYP_ISR1 0xE3
+#define KEYPAD_KEYP_IMR1 0xE4
+#define KEYPAD_KEYP_ISR2 0xE5
+#define KEYPAD_KEYP_IMR2 0xE6
+#define KEYPAD_KEYP_SIR 0xE7
+#define KEYPAD_KEYP_EDR 0xE8
+#define KEYPAD_KEYP_SIH_CTRL 0xE9
+
+#define CTRL_KBD_ON (1 << 6)
+#define CTRL_RP_EN (1 << 5)
+#define CTRL_TOLE_EN (1 << 4)
+#define CTRL_TOE_EN (1 << 3)
+#define CTRL_LK_EN (1 << 2)
+#define CTRL_SOFTMODEN (1 << 1)
+#define CTRL_SOFT_NRST (1 << 0)
+
+int twl4030_init_battery_charging(void);
+
+/* Declarations for users of the keypad, stubs for everyone else. */
+#if (defined(CONFIG_TWL4030_KEYPAD) && (CONFIG_TWL4030_KEYPAD))
+int twl4030_keypad_init(void);
+int twl4030_keypad_reset(void);
+int twl4030_keypad_keys_pressed(unsigned char *key1, unsigned char *key2);
+#else
+#define twl4030_keypad_init() 0
+#define twl4030_keypad_reset() 0
+#define twl4030_keypad_keys_pressed(a, b) 0
+#endif
diff --git a/u-boot/board/goldelico/gta04/ulpi-phy.c b/u-boot/board/goldelico/gta04/ulpi-phy.c
new file mode 100644
index 0000000..15986e5
--- /dev/null
+++ b/u-boot/board/goldelico/gta04/ulpi-phy.c
@@ -0,0 +1,73 @@
+/* u-boot driver to access ULPI PHY registers through EHCI controller
+ *
+ * Copyright (C) 2010 by Golden Delicious Computers GmbH&Co. KG
+ * Author: H. Nikolaus Schaller <hns@goldelico.com>
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+/* FIXME 
+ * needs to enable clock USBHOST_FCLK etc.
+ */
+
+#include <common.h>
+#include <asm/errno.h>
+#include <asm/io.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/gpio.h>
+#include <asm/mach-types.h>
+#include "ulpi-phy.h"
+
+#define EHCI_BASE			(0x480648A4)
+
+#define	EHCI_INSNREG05_ULPI				(0xA4)
+#define	EHCI_INSNREG05_ULPI_CONTROL_SHIFT		31
+#define	EHCI_INSNREG05_ULPI_PORTSEL_SHIFT		24
+#define	EHCI_INSNREG05_ULPI_OPSEL_SHIFT			22
+#define	EHCI_INSNREG05_ULPI_REGADD_SHIFT		16
+#define	EHCI_INSNREG05_ULPI_EXTREGADD_SHIFT		8
+#define	EHCI_INSNREG05_ULPI_WRDATA_SHIFT		0
+
+/* read/write Registers in ULPI-PHY */
+
+u8 ulpi_direct_access(u8 port, u8 reg, int write, u8 value)
+{
+#if 0	// FIXME: we need to have the clocks and the EHCI controller enabled!
+	u32 val;
+	u32 cmd = (((u32)value) << EHCI_INSNREG05_ULPI_WRDATA_SHIFT); /* value to write */
+	if(reg > 0x3f || reg == 0x2f)
+		cmd |= (((u32)reg & 0xff) << EHCI_INSNREG05_ULPI_EXTREGADD_SHIFT) | (0x2f << EHCI_INSNREG05_ULPI_REGADD_SHIFT);	/* extended address */
+	else
+		cmd |= (((u32)reg & 0x3f) << EHCI_INSNREG05_ULPI_REGADD_SHIFT);
+	cmd |= ((write? 0x02 : 0x03) << EHCI_INSNREG05_ULPI_OPSEL_SHIFT);
+	cmd |= (((u32)(port+1) & 3) << EHCI_INSNREG05_ULPI_PORTSEL_SHIFT);	/* port counts 0,1,2 */
+	cmd |= (1 << EHCI_INSNREG05_ULPI_CONTROL_SHIFT);	/* Start */
+	
+	writel(cmd, EHCI_BASE + EHCI_INSNREG05_ULPI);	/* write EHCI_INSNREG05_ULPI */
+	
+	// do {
+	udelay(100);	/* wait a little */
+	val = readl(EHCI_BASE + EHCI_INSNREG05_ULPI);	/* read EHCI_INSNREG05_ULPI */
+	/* do we need a timepout if the PHY chip is not present? */
+	// } while(!(val & (1<<EHCI_INSNREG05_ULPI_CONTROL_SHIFT)));
+	return val;
+#else
+	return 0;
+#endif
+}
diff --git a/u-boot/board/goldelico/gta04/ulpi-phy.h b/u-boot/board/goldelico/gta04/ulpi-phy.h
new file mode 100644
index 0000000..7443c37
--- /dev/null
+++ b/u-boot/board/goldelico/gta04/ulpi-phy.h
@@ -0,0 +1,6 @@
+#ifndef _ULPI_PHY_H
+#define _ULPI_PHY_H
+
+u8 ulpi_direct_access(u8 port, u8 reg, int write, u8 value);
+
+#endif
diff --git a/u-boot/board/goldelico/gta04b2/COM37H3M05DTC.c b/u-boot/board/goldelico/gta04b2/COM37H3M05DTC.c
new file mode 100644
index 0000000..e2b4d49
--- /dev/null
+++ b/u-boot/board/goldelico/gta04b2/COM37H3M05DTC.c
@@ -0,0 +1,142 @@
+/* u-boot driver for the OrtusTech COM37H3M05DTC LCM
+ *
+ * Copyright (C) 2006-2007 by OpenMoko, Inc.
+ * Author: Harald Welte <laforge@openmoko.org>
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <asm/errno.h>
+#include <asm/io.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/gpio.h>
+#include <asm/mach-types.h>
+#include <twl4030.h>
+#include "../gta04/dssfb.h"
+#include "../gta04/jbt6k74.h"	// FIXME: change to display.h and make it more generic
+#include "COM37H3M05DTC.h"
+
+#ifdef CONFIG_OMAP3_BEAGLE_EXPANDER
+#define GPIO_STBY 158
+#else
+#define GPIO_STBY 20
+#endif
+
+// configure beagle board DSS for the COM37H3M05DTC
+
+#define DVI_BACKGROUND_COLOR		0x00fadc29	// rgb(250, 220, 41)
+
+#define DSS1_FCLK	432000000	// see figure 15-65
+#define PIXEL_CLOCK	22400000	// approx. 22.4 MHz (will be divided from 432 MHz)
+
+// all values are min ratings
+
+#define VDISP	640				// vertical active area
+#define VFP		2				// vertical front porch
+#define VS		1				// VSYNC pulse width (negative going)
+#define VBP		3				// vertical back porch
+#define VDS		(VS+VBP)		// vertical data start
+#define VBL		(VS+VBP+VFP)	// vertical blanking period
+#define VP		(VDISP+VBL)		// vertical cycle
+
+#define HDISP	480				// horizontal active area
+#define HFP		2				// horizontal front porch
+#define HS		2				// HSYNC pulse width (negative going)
+#define HBP		9				// horizontal back porch
+#define HDS		(HS+HBP)		// horizontal data start
+#define HBL		(HS+HBP+HFP)	// horizontal blanking period
+#define HP		(HDISP+HBL)		// horizontal cycle
+
+static const struct panel_config lcm_cfg = 
+{
+	.timing_h	= ((HBP-1)<<20) | ((HFP-1)<<8) | ((HS-1)<<0), /* Horizantal timing */
+	.timing_v	= ((VBP+0)<<20) | ((VFP+0)<<8) | ((VS-1)<<0), /* Vertical timing */
+	// negative clock edge
+	// negative sync pulse
+	// positive DE pulse
+	.pol_freq	= (1<<17)|(1<<16)|(0<<15)|(0<<14)|(1<<13)|(1<<12)|0x28,    /* Pol Freq */
+	.divisor	= (0x0001<<16)|(DSS1_FCLK/PIXEL_CLOCK), /* Pixel Clock divisor from dss1_fclk */
+	.lcd_size	= ((HDISP-1)<<0) | ((VDISP-1)<<16), /* as defined by LCM */
+	.panel_type	= 0x01, /* TFT */
+	.data_lines	= 0x03, /* 24 Bit RGB */
+	.load_mode	= 0x02, /* Frame Mode */
+	.panel_color	= DVI_BACKGROUND_COLOR
+};
+
+int jbt_reg_init(void)
+{
+	omap_request_gpio(GPIO_STBY);
+	omap_set_gpio_direction(GPIO_STBY, 0);		// output
+	return 0;
+}
+
+int jbt_check(void)
+{
+	return 0;
+}
+
+const char *jbt_state(void)
+{
+	return "?";
+}
+
+/* frontend function */
+int jbt6k74_enter_state(enum jbt_state new_state)
+{
+	return 0;
+}
+
+int jbt6k74_display_onoff(int on)
+{
+	omap_set_gpio_dataout(GPIO_STBY, on?1:0);	// on = no STBY
+	return 0;
+}
+
+int board_video_init(GraphicDevice *pGD)
+{
+	extern int get_board_revision(void);
+	
+	// FIXME: here we should pass down the GPIO(s)
+	
+	backlight_init();	// initialize backlight
+#define REVISION_XM 0
+	if(get_board_revision() == REVISION_XM) {
+		/* Set VAUX1 to 3.3V for GTA04E display board */
+		twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VAUX1_DEDICATED,
+								/*TWL4030_PM_RECEIVER_VAUX1_VSEL_33*/ 0x07,
+								TWL4030_PM_RECEIVER_VAUX1_DEV_GRP,
+								TWL4030_PM_RECEIVER_DEV_GRP_P1);
+		udelay(5000);
+	}
+	
+	// FIXME: here we should init the TSC and pass down the GPIO numbers and resistance values
+	
+	if(jbt_reg_init())	// initialize SPI
+		{
+		printf("No LCM connected\n");
+		return 1;
+		}
+	
+	dssfb_init(&lcm_cfg);
+	
+	printf("did board_video_init()\n");
+	return 0;
+}
+
diff --git a/u-boot/board/goldelico/gta04b2/COM37H3M05DTC.h b/u-boot/board/goldelico/gta04b2/COM37H3M05DTC.h
new file mode 100644
index 0000000..87c7b57
--- /dev/null
+++ b/u-boot/board/goldelico/gta04b2/COM37H3M05DTC.h
@@ -0,0 +1,6 @@
+#ifndef _COM37H3M05DTC_H
+#define _COM37H3M05DTC_H
+
+#define _BEAGLE_
+
+#endif
diff --git a/u-boot/board/goldelico/gta04b2/Makefile b/u-boot/board/goldelico/gta04b2/Makefile
new file mode 100644
index 0000000..9cecfa8
--- /dev/null
+++ b/u-boot/board/goldelico/gta04b2/Makefile
@@ -0,0 +1,49 @@
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= gta04b2.o COM37H3M05DTC.o trf7960.o ../gta04/backlight.o ../gta04/status.o ../gta04/tsc2007.o ../gta04/dssfb.o ../gta04/gps.o ../gta04/shutdown.o ../gta04/systest.o ../gta04/commands.o ../gta04/ulpi-phy.o  ../gta04/twl4030-additions.o
+
+SRCS	:= $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
\ No newline at end of file
diff --git a/u-boot/board/goldelico/gta04b2/config.mk b/u-boot/board/goldelico/gta04b2/config.mk
new file mode 100644
index 0000000..cf055db
--- /dev/null
+++ b/u-boot/board/goldelico/gta04b2/config.mk
@@ -0,0 +1,33 @@
+#
+# (C) Copyright 2006
+# Texas Instruments, <www.ti.com>
+#
+# Beagle Board uses OMAP3 (ARM-CortexA8) cpu
+# see http://www.ti.com/ for more information on Texas Instruments
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+# Physical Address:
+# 8000'0000 (bank0)
+# A000/0000 (bank1)
+# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
+# (mem base + reserved)
+
+# For use with external or internal boots.
+CONFIG_SYS_TEXT_BASE = 0x80008000
diff --git a/u-boot/board/goldelico/gta04b2/gta04b2.c b/u-boot/board/goldelico/gta04b2/gta04b2.c
new file mode 100644
index 0000000..3675a89
--- /dev/null
+++ b/u-boot/board/goldelico/gta04b2/gta04b2.c
@@ -0,0 +1,24 @@
+#include <common.h>
+#include <twl4030.h>
+#include <asm/io.h>
+#include <asm/arch/mmc_host_def.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/gpio.h>
+#include <asm/mach-types.h>
+#include "../gta04/gta04.h"
+#include "gta04b2.h"
+
+// make us initialize using both pinmux sets
+
+void muxinit(void)
+{
+	MUX_BEAGLE();
+	MUX_BEAGLE_EXPANDER();
+}
+
+#undef MUX_BEAGLE
+#define MUX_BEAGLE() muxinit()
+
+// take the original beagle.c code
+#include "../gta04/gta04.c"
diff --git a/u-boot/board/goldelico/gta04b2/gta04b2.h b/u-boot/board/goldelico/gta04b2/gta04b2.h
new file mode 100644
index 0000000..668f5f9
--- /dev/null
+++ b/u-boot/board/goldelico/gta04b2/gta04b2.h
@@ -0,0 +1,34 @@
+// all pins on GTA04 expansion connector
+
+// GPIO -> GTA04-Pin -> Expander function
+
+#define MUX_BEAGLE_EXPANDER() \
+
+// FIXME: clean up so that we have the right PinMuxes
+#if 0
+
+MUX_VAL(CP(ETK_D0),		(IEN  | PTD | EN  | M1)) /*GPIO_17 -> MCSPI3-CLK -> TRF*/\
+MUX_VAL(CP(MMC2_CLK),		(IDIS | PTD | EN  | M4)) /*GPIO_130 -> MCSPI3-CLK -> TRF*/\
+MUX_VAL(CP(MMC2_CMD),		(IDIS | PTD | EN  | M4)) /*GPIO_131 -> MCSPI3-SIMO -> TRF*/\
+MUX_VAL(CP(MMC2_DAT0),		(IEN  | PTU | EN  | M4)) /*GPIO_132 -> MCSPI3-SOMI -> TRF*/\
+MUX_VAL(CP(MCBSP1_DX),		(IDIS | PTD | EN  | M4)) /*GPIO_158 - Display STBY */\
+MUX_VAL(CP(MCBSP1_DR),		(IDIS | PTD | EN  | M4)) /*GPIO_159 - McBSP1-DR -> TRF EN2 */\
+MUX_VAL(CP(MCBSP1_FSX),		(IDIS | PTD | EN  | M4)) /*GPIO_161 - McBSP1-FSX -> TRF EN */\
+
+MUX_VAL(CP(MMC2_DAT1),		(IEN  | PTU | EN  | M4)) /*GPIO_133 -> UART3-RX (software)*/\
+MUX_VAL(CP(MMC2_DAT2),		(IDIS | PTU | EN  | M4)) /*GPIO_134 -> UART3-TX (software)*/\
+MUX_VAL(CP(MMC2_DAT3),		(IDIS | PTU | EN  | M1)) /*GPIO_135 -> MCSPI3-CS0*/\
+MUX_VAL(CP(MMC2_DAT4),		(IEN  | PTD | EN  | M4)) /*GPIO_136 - AUX */\
+MUX_VAL(CP(MMC2_DAT5),		(IEN  | PTU | EN  | M4)) /*GPIO_137 - POWER */\
+MUX_VAL(CP(MMC2_DAT6),		(IDIS | PTU | EN  | M4)) /*GPIO_138 - UART3-RTS (software) */\
+MUX_VAL(CP(MMC2_DAT7),		(IEN  | PTU | EN  | M4)) /*GPIO_139 - UART3-CTS (software) */\
+MUX_VAL(CP(UART2_RX),		(IEN  | PTU | EN  | M4)) /*GPIO_143 - UART2-RX */\
+MUX_VAL(CP(UART2_CTS),		(IDIS | PTU | EN  | M4)) /*GPIO_144 - UART2-CTS */\
+MUX_VAL(CP(UART2_RTS),		(IDIS | PTU | EN  | M4)) /*GPIO_145 - UART2-RTS */\
+MUX_VAL(CP(UART2_TX),		(IEN  | PTU | EN  | M4)) /*GPIO_146 - UART2-TX */\
+MUX_VAL(CP(MCBSP1_CLKR),	(IEN  | PTD | EN  | M4)) /*GPIO_156 - KEYIRQ -> TRF IRQ */\
+MUX_VAL(CP(MCBSP1_FSR),		(IEN  | PTU | EN  | M4)) /*GPIO_157 - PENIRQ */\
+MUX_VAL(CP(MCBSP_CLKS),		(IEN  | PTU | DIS | M0)) /*McBSP_CLKS */\
+MUX_VAL(CP(MCBSP1_CLKX),	(IDIS | PTD | EN  | M4)) /*GPIO_162 - McBSP1-CLKX -> UART3 Powerdown */
+
+#endif
diff --git a/u-boot/board/goldelico/gta04b2/trf7960.c b/u-boot/board/goldelico/gta04b2/trf7960.c
new file mode 100644
index 0000000..fd90792
--- /dev/null
+++ b/u-boot/board/goldelico/gta04b2/trf7960.c
@@ -0,0 +1,945 @@
+/*
+ * (C) Copyright 2011
+ * H. Nikolaus Schaller, Golden Delicious Computers, hns@goldelico.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <spi.h>
+#include <asm/arch/gpio.h>
+#include <malloc.h>
+
+/* board specific configuration */
+
+struct trf7960 {
+	/*
+	 * OMAP3 McSPI (MultiChannel SPI) has 4 busses (modules)
+	 * with different number of chip selects (CS, channels):
+	 * McSPI1 has 4 CS (bus 0, cs 0 - 3)
+	 * McSPI2 has 2 CS (bus 1, cs 0 - 1)
+	 * McSPI3 has 2 CS (bus 2, cs 0 - 1)
+	 * McSPI4 has 1 CS (bus 3, cs 0)
+	 */
+	int bus;
+	int cs;
+	int clock;
+	int irq;	/* GPIO that receives IRQ; use -1 if we have no IRQ */
+	int en;		/* GPIO that controls EN; use -1 if hardwired */
+	int en2;	/* GPIO that controls EN2; use -1 if hardwired (use same if both are parallel) */
+	int vio;	/* specify 10*VIO i.e. 18 for 1.8V, 33 for 3.3V */
+	struct spi_slave *slave;
+	/* internal */
+	int done;	/* done interrupt flag */
+	uchar *datapointer;	/* RX/TX data pointer */
+	int bytes;		/* number of remaining bytes to transmit (may be negative) */
+};
+
+/* low level functions */
+
+#define TRF7960_REG_CSC		0x00	/* Chip Status control (R/W) */
+#define TRF7960_REG_ISOC	0x01	/* ISO control (R/W) */
+#define TRF7960_REG_ISO14443BTXOPT	0x02	/* TX Options (R/W) */
+#define TRF7960_REG_ISO14443AHBROPT	0x03	/* High Bitrate Options (R/W) */
+#define TRF7960_REG_TXTIMERMSB	0x04	/* TX Timer (R/W) */
+#define TRF7960_REG_TXTIMERLSB	0x05	/* TX Timer (R/W) */
+#define TRF7960_REG_TXPULSEC	0x06	/* TX Pulse Lenght control (R/W) */
+#define TRF7960_REG_RXNRWAIT	0x07	/* RX no response wait (R/W) */
+#define TRF7960_REG_RXWAIT	0x08	/* RX wait time (after TX) (R/W) */
+#define TRF7960_REG_MODCLK	0x09	/* Modulator and SYS_CLK (R/W) */
+#define TRF7960_REG_RXSPECIAL	0x0a	/* RX special setting (R/W) */
+#define TRF7960_REG_REGIO	0x0b	/* Regulator and IO control (R/W) */
+#define TRF7960_REG_IRQ	0x0c	/* IRQ status (R) */
+#define TRF7960_REG_IRQMASK	0x0d	/* Collision position (MSB) and Interrupt Mask (R/W) */
+#define TRF7960_REG_COLLISION	0x0e	/* Collision position (LSB) (R) */
+#define TRF7960_REG_RSSI	0x0f	/* RSSI levels and oscillator status (R) */
+#define TRF7960_REG_FIFO_STATUS	0x1c	/* FIFO status (R) */
+#define TRF7960_REG_FIFO_TXLEN1	0x1d	/* TX length byte 1 (R/W) */
+#define TRF7960_REG_FIFO_TXLEN2	0x1e	/* TX length byte 2 (R/W) */
+#define TRF7960_REG_FIFO_DATA	0x1f	/* FIFO I/O register (R/W) */
+
+/* FIXME: add bit masks for these registers */
+
+#define TRF7960_CMD_IDLE	0x00
+#define TRF7960_CMD_INIT	0x03
+#define TRF7960_CMD_RESET	0x0f		/* reset FIFO */
+#define TRF7960_CMD_TX_NOCRC	0x10
+#define TRF7960_CMD_TX_CRC	0x11	/* TX with CRC */
+#define TRF7960_CMD_TX_DELAYED_NOCRC	0x12
+#define TRF7960_CMD_TX_DELAYED_CRC	0x13
+#define TRF7960_CMD_TX_NEXT_SLOT	0x14	/* send EOF / next slot */
+#define TRF7960_CMD_RX_BLOCK	0x16	/* block receiver */
+#define TRF7960_CMD_RX_ENABLE	0x17	/* enable receiver */
+#define TRF7960_CMD_TEST_RF_INT	0x18
+#define TRF7960_CMD_TEST_RF_EXT	0x19
+#define TRF7960_CMD_RX_GAIN_ADJUST	0x1a
+
+/* first byte sent through SPI */
+#define TRF7960_COMMAND		0x80
+#define TRF7960_ADDRESS		0x00	/* combine with READ/WRITE and optionally CONTINUE */
+#define TRF7960_READ		0x40
+#define TRF7960_WRITE		0x00
+#define TRF7960_CONTINUE	0x20
+
+/* power modes (increasing power demand) */
+#define TRF7960_POWER_DOWN	0
+#define TRF7960_POWER_60kHz	1		/* VDD_X available, 60 kHz */
+#define TRF7960_POWER_STANDBY	2	/* 13.56 MHz osc. on, SYS_CLK available; regulators in low power */
+#define TRF7960_POWER_ACTIVE	3	/* 13.56 MHz osc. on, SYS_CLK available; regulators active */
+#define TRF7960_POWER_RX	4	/* RX active */
+#define TRF7960_POWER_RXTX_HALF	5	/* RX+TX active; half power mode */
+#define TRF7960_POWER_RXTX_FULL	6	/* RX+TX active; full power mode */
+
+/* protocols */
+#define TRF7960_PROTOCOL_ISO15693_LBR_1SC_4		0x00
+#define TRF7960_PROTOCOL_ISO15693_LBR_1SC_256	0x01
+#define TRF7960_PROTOCOL_ISO15693_HBR_1SC_4		0x02
+#define TRF7960_PROTOCOL_ISO15693_HBR_1SC_256	0x03
+#define TRF7960_PROTOCOL_ISO15693_LBR_2SC_4		0x04
+#define TRF7960_PROTOCOL_ISO15693_LBR_2SC_256	0x05
+#define TRF7960_PROTOCOL_ISO15693_HBR_2SC_4		0x06
+#define TRF7960_PROTOCOL_ISO15693_HBR_2SC_256	0x07
+#define TRF7960_PROTOCOL_ISO14443A_BR_106	0x08
+#define TRF7960_PROTOCOL_ISO14443A_BR_212	0x09
+#define TRF7960_PROTOCOL_ISO14443A_BR_424	0x0a
+#define TRF7960_PROTOCOL_ISO14443A_BR_848	0x0b
+#define TRF7960_PROTOCOL_ISO14443B_BR_106	0x0c
+#define TRF7960_PROTOCOL_ISO14443B_BR_212	0x0d
+#define TRF7960_PROTOCOL_ISO14443B_BR_424	0x0e
+#define TRF7960_PROTOCOL_ISO14443B_BR_848	0x0f
+#define TRF7960_PROTOCOL_TAGIT	0x13
+
+/* */
+
+#if 1	/* fix HW problem with TRF7960 being in "SPI without SS" mode */
+
+#define spi_xfer bitbang_spi_xfer
+#define spi_claim_bus(X)
+#define spi_release_bus(X)
+
+#define McSPI3_CLK	130
+#define McSPI3_SIMO	131
+#define McSPI3_SOMI	132
+
+#define HALFBIT 1	/* 1us gives approx. 500kHz clock */
+
+static int bitbang_spi_xfer(struct spi_slave *slave, int bitlen, uchar writeBuffer[], uchar readBuffer[], int flags)
+{ /* generates bitlen+2 clock pulses */
+	static int first=1;
+	int bit;
+	uchar wb=0;
+	uchar rb=0;
+	if(first) { /* if not correctly done by pinmux */
+		omap_set_gpio_direction(McSPI3_CLK, 0);
+		omap_set_gpio_direction(McSPI3_SIMO, 0);
+		omap_set_gpio_direction(McSPI3_SOMI, 1);
+		omap_set_gpio_dataout(McSPI3_CLK, 0);
+		omap_set_gpio_dataout(McSPI3_SIMO, 0);	/* send out constant 0 bits (idle command) */
+		first=0;
+		udelay(100);
+	}
+#if 0
+	printf("bitbang_spi_xfer %d bits\n", bitlen);
+#endif
+	if(flags & SPI_XFER_BEGIN) {
+		omap_set_gpio_dataout(McSPI3_CLK, 1);
+		udelay(HALFBIT);	/* may be optional (>50ns) */
+		omap_set_gpio_dataout(McSPI3_SIMO, 1);	/* start condition (data transision while clock=1) */
+		udelay(HALFBIT);		
+	}
+	omap_set_gpio_dataout(McSPI3_CLK, 0);
+	for(bit=0; bit < bitlen; bit++)
+		{ /* write data */
+			if(bit%8 == 0)
+				wb=writeBuffer[bit/8];
+			omap_set_gpio_dataout(McSPI3_SIMO, (wb&0x80)?1:0);	/* send MSB first */
+			wb <<= 1;
+			udelay(HALFBIT);
+			omap_set_gpio_dataout(McSPI3_CLK, 1);
+			udelay(HALFBIT);
+			omap_set_gpio_dataout(McSPI3_CLK, 0);
+			rb = (rb<<1) | omap_get_gpio_datain(McSPI3_SOMI);	/* sample on falling edge and receive MSB first */
+			if(bit%8 == 7)
+				readBuffer[bit/8]=rb;
+		}
+	if(flags & SPI_XFER_END) {
+		omap_set_gpio_dataout(McSPI3_SIMO, 1);	/* set data to 1 */
+		udelay(HALFBIT);
+		omap_set_gpio_dataout(McSPI3_CLK, 1);
+		udelay(HALFBIT);
+		omap_set_gpio_dataout(McSPI3_SIMO, 0);	/* stop condition (data transision while clock=1) */
+		udelay(HALFBIT);	/* may be optional (>50ns) */
+		omap_set_gpio_dataout(McSPI3_CLK, 0);
+		udelay(HALFBIT);
+	}
+	return 0;
+}
+
+#endif
+					 
+static inline int readRegister(struct trf7960 *device, uchar addr)
+{
+	uchar writeBuffer[2];
+	uchar readBuffer[2];
+	writeBuffer[0] = TRF7960_ADDRESS | TRF7960_READ | addr;
+	spi_claim_bus(device->slave);
+	if(spi_xfer(device->slave, 16, writeBuffer, readBuffer, SPI_XFER_BEGIN | SPI_XFER_END) != 0)
+		return -1;
+	spi_release_bus(device->slave);
+	return readBuffer[1];
+}
+
+static inline int writeRegister(struct trf7960 *device, uchar addr, uchar byte)
+{
+	uchar writeBuffer[2];
+	uchar readBuffer[2];
+	writeBuffer[0] = TRF7960_ADDRESS | TRF7960_WRITE | addr;
+	writeBuffer[1] = byte;
+	spi_claim_bus(device->slave);
+	if(spi_xfer(device->slave, 2*8, writeBuffer, readBuffer, SPI_XFER_BEGIN | SPI_XFER_END) != 0)
+		return -1;
+	spi_release_bus(device->slave);
+	return 0;
+}
+
+static inline int sendCommand(struct trf7960 *device, uchar cmd)
+{
+	uchar writeBuffer[1];
+	uchar readBuffer[1];
+	writeBuffer[0] = TRF7960_COMMAND | cmd;
+	spi_claim_bus(device->slave);
+	if(spi_xfer(device->slave, 8, writeBuffer, readBuffer, SPI_XFER_BEGIN | SPI_XFER_END) != 0)
+		return -1;
+	spi_release_bus(device->slave);
+	return 0;
+}
+
+/* mid level  (should be partially mapped to sysfs) */
+
+int resetIRQ(struct trf7960 *device)
+{
+	uchar writeBuffer[3];
+	uchar readBuffer[3];
+	writeBuffer[0] = TRF7960_ADDRESS | TRF7960_READ | TRF7960_CONTINUE | TRF7960_REG_IRQ;
+	writeBuffer[1] = 0;	// dummy read
+	writeBuffer[2] = 0;	// dummy read
+	spi_claim_bus(device->slave);
+	if(spi_xfer(device->slave, 3*8, writeBuffer, readBuffer, SPI_XFER_BEGIN | SPI_XFER_END) != 0)
+		return -1;
+	spi_release_bus(device->slave);
+#if 0
+	{
+	int i;
+	for(i=0; i<3; i++)
+		printf("rb[i]=%02x\n", readBuffer[i]);
+	}
+#endif
+	return readBuffer[1];
+}
+
+int getCollisionPosition(struct trf7960 *device)
+{
+	uchar writeBuffer[3];
+	uchar readBuffer[3];
+	writeBuffer[0] = TRF7960_ADDRESS | TRF7960_READ | TRF7960_CONTINUE | TRF7960_REG_IRQMASK;
+	writeBuffer[1] = 0;	// dummy read
+	writeBuffer[2] = 0;	// dummy read
+	spi_claim_bus(device->slave);
+	if(spi_xfer(device->slave, 3*8, writeBuffer, readBuffer, SPI_XFER_BEGIN | SPI_XFER_END) != 0)
+		return -1;
+	spi_release_bus(device->slave);
+	return ((readBuffer[1]&0xc0)<<2) | readBuffer[2];	// combine into 10 bits
+}
+
+/* how to handle spi_claim_bus during irq handler? */
+
+int prepareIrq(struct trf7960 *device, uchar *data, unsigned int bytes)
+{
+#if 1
+	printf("prepareIrq data=%p bytes=%u\n", data, bytes);
+#endif
+#if 0
+	{
+	//	uchar irq=readRegister(device, TRF7960_REG_IRQ);
+	uchar irq=resetIRQ(device);
+	printf("    irq-status=%02x\n", irq);		
+	}
+#endif
+#if 0
+	while(device->irq >= 0 && omap_get_gpio_datain(device->irq)) {
+		printf("prepareIrq: IRQ pin already active!\n");
+		resetIRQ(device);
+	}
+#endif
+	device->done=0;	/* not yet done */
+	device->datapointer=data;
+	device->bytes=bytes;
+	/* enable IRQ */
+	return 0;
+}
+
+void handleInterrupt(struct trf7960 *device)
+{ /* process interrupt */
+	unsigned char buffer[12];
+//	uchar irq=readRegister(device, TRF7960_REG_IRQ);
+	uchar irq=resetIRQ(device);
+	if(!irq)
+		return;	/* false alarm or waitIrq */
+	if(device->done)
+		return;	/* unprocessed previous interrupt */
+#if 0
+	printf("handleirq %02x\n", irq);
+#endif
+	device->done=irq;	/* set done flag with interrupt flags */
+#if 0	// read again test (did a read reset the IRQ flags?)
+	irq=readRegister(device, TRF7960_REG_IRQ);
+	printf("handleirq %02x %02x\n", device->done, irq);
+	irq=device->done;	/* restore */
+#endif
+#if 0
+	udelay(5);
+	if(device->irq >= 0 && omap_get_gpio_datain(device->irq))
+		printf("  IRQ pin still/again active!\n");
+#endif
+	if(irq & 0x80) { /* end of TX */
+#if 1
+		printf("handleirq end of TX %02x\n", irq);
+#endif
+		sendCommand(device, TRF7960_CMD_RESET);	/* reset FIFO */
+		return;
+		}
+	if(irq & 0x02) { /* collision occurred */
+		int position;
+#if 1
+		printf("handleirq collision %02x\n", irq);
+#endif
+		// FIXME: combine into single message
+		sendCommand(device, TRF7960_CMD_RX_BLOCK);	/* block RX */
+		position=getCollisionPosition(device);
+#if 1
+		printf("position=%d\n", position);
+#endif
+		// number of valid bytes is collpos - 32
+		// read bytes
+		// handle broken byte
+		sendCommand(device, TRF7960_CMD_RESET);	/* reset FIFO */
+	}
+	else if(irq & 0x40) { /* end of RX */
+		uchar fifosr=readRegister(device, TRF7960_REG_FIFO_STATUS);
+		uchar unread=(fifosr&0xf) + 1;
+#if 1
+		printf("handleirq end of RX %02x fifosr=%02x unread=%d\n", irq, fifosr, unread);
+#endif
+		int n = device->bytes <= unread ? device->bytes : unread;	/* limit to remaining bytes in FIFO or buffer */
+		buffer[0] = TRF7960_READ | TRF7960_CONTINUE | TRF7960_REG_FIFO_DATA;	/* continuous read from FIFO */
+		memset(&buffer[1], 0, sizeof(buffer)/sizeof(buffer[0])-1);	/* clear buffer so that we don't write garbage */
+		if(spi_xfer(device->slave, 8*sizeof(buffer[0])*(2 + n), buffer, buffer, SPI_XFER_BEGIN | SPI_XFER_END) != 0)	/* we need 8 more clocks to receive the last byte */
+			return;	/* spi error */
+		memcpy(device->datapointer, &buffer[1], n);	/* buffer[0] are the first 8 bits shifted out while we did send the command */
+		device->datapointer += n;
+		device->bytes -= n;
+#if 1
+		if(device->bytes > 0)
+			printf("  remaining buffer=%d\n", device->bytes);
+#endif
+		// handle broken byte
+		sendCommand(device, TRF7960_CMD_RESET);	/* reset FIFO */		
+	}
+	else if(irq & 0x20) { /* FIFO interrupt */
+		int n = device->bytes <= 9 ? device->bytes : 9;	/* limit to 9 bytes */
+#if 1
+		printf("handleirq fifo request %02x (%d bytes remaining)\n", irq, device->bytes);
+#endif
+		if(n > 0) {
+			if(irq & 0x80) { /* write next n bytes to FIFO (up to 9 or as defined by bytes) */
+#if 1
+				printf("write more (%d)\n", n);
+#endif
+				buffer[0] = TRF7960_WRITE | TRF7960_CONTINUE | TRF7960_REG_FIFO_DATA;	/* continuous write to FIFO */
+				memcpy(&buffer[1], device->datapointer, n);
+				if(spi_xfer(device->slave, 8*sizeof(buffer[0])*(1 + n), buffer, buffer, SPI_XFER_BEGIN | SPI_XFER_END) != 0)
+					return;	/* spi error */
+				device->datapointer += n;
+				device->bytes -= n;				
+			} else { /* read next 9 bytes from FIFO in one sequence */
+#if 1
+				printf("read more (%d)\n", n);
+#endif
+				buffer[0] = TRF7960_READ | TRF7960_CONTINUE | TRF7960_REG_FIFO_DATA;	/* continuous read from FIFO */
+				memset(&buffer[1], 0, sizeof(buffer)/sizeof(buffer[0])-1);	/* clear buffer so that we don't write garbage */
+				if(spi_xfer(device->slave, 8*sizeof(buffer[0])*(2 + n), buffer, buffer, SPI_XFER_BEGIN | SPI_XFER_END) != 0)	/* we need 8 more clocks to receive the last byte */
+					return;	/* spi error */
+				memcpy(device->datapointer, &buffer[1], n);	/* buffer[0] are the first 8 bits shifted out while we did send the command */
+				device->datapointer += n;
+				device->bytes -= n;
+			}
+			device->done=0;	/* don't notify successful data trandfer as 'done' status */
+		}
+		// else some error (FIFO interrupt but no data available or buffer is full
+	}
+}
+
+void waitIrq(struct trf7960 *device)
+{ /* wait for IRQ */
+#if 0
+	printf("waitIrq %d\n", device->irq);
+#endif
+	if(device->irq >= 0)	{ /* check IRQ pin */
+		int cnt=2000;	// software timeout
+		while(!omap_get_gpio_datain(device->irq) && cnt-- > 0)
+			udelay(500); /* wait for IRQ pin */
+		handleInterrupt(device);
+	}
+	else { /* poll interrupt register to check for interrupts */
+		while(!device->done)
+			handleInterrupt(device);
+	}
+#if 0
+	printf("waitIrq -> %02x\n", device->done);
+#endif
+}
+
+int setPowerMode(struct trf7960 *device, int mode)
+{ /* control power modes */
+	int status = 0;
+#if 1
+	printf("setPowerMode %d\n", mode);
+#endif
+	if(mode < TRF7960_POWER_DOWN || mode > TRF7960_POWER_RXTX_FULL)
+		return -1;
+	if(device->en >= 0)
+		omap_set_gpio_direction(device->en, 0);		/* make output */
+	if(device->en2 >= 0)
+		omap_set_gpio_direction(device->en2, 0);	/* make output */
+	if(device->irq >= 0)
+		omap_set_gpio_direction(device->irq, 1);	/* make input */
+	if(mode == TRF7960_POWER_DOWN) {
+		if(device->slave) {
+			spi_free_slave(device->slave);
+			device->slave = NULL;
+		}
+		if(device->en >= 0)
+			omap_set_gpio_dataout(device->en, 0);
+		if(device->en2 >= 0 && device->en != device->en2)
+			omap_set_gpio_dataout(device->en2, 0);	/* not tied togehter */
+	}
+	else if(mode == TRF7960_POWER_60kHz) {
+		if(device->en >= 0 && device->en2 >= 0 && device->en == device->en2)
+			return -1;	/* can't control them separately */
+		if(device->en >= 0)
+			omap_set_gpio_dataout(device->en, 0);
+		if(device->en2 >= 0)
+			omap_set_gpio_dataout(device->en2, 1);
+	}
+	else {
+		if(device->en >= 0)
+			omap_set_gpio_dataout(device->en, 1);
+		if(!device->slave) {
+			device->slave = spi_setup_slave(device->bus, device->cs, device->clock, SPI_MODE_0);
+			if(!device->slave)
+				return -1;	// failed			
+		}
+		udelay(1000);	/* wait until we can read/write */
+		status = readRegister(device, TRF7960_REG_CSC);
+#if 1
+		printf("CSC = %02x\n", status);
+#endif
+		if(status < 0)
+			return status;	/* some error */
+		switch(mode) {
+			case TRF7960_POWER_STANDBY:
+				status |= 0x80;
+				break;
+			case TRF7960_POWER_ACTIVE:
+				status &= 0x5d;
+				break;
+			case TRF7960_POWER_RX:
+				status &= 0x5d;
+				status |= 0x02;
+				break;
+			case TRF7960_POWER_RXTX_HALF:
+				status &= 0x4f;
+				status |= 0x20;
+				break;
+			case TRF7960_POWER_RXTX_FULL:
+				status &= 0x4f;
+				status |= 0x30;
+				break;
+			default:
+				return -1;
+		}
+#if 1
+		printf("   => %02x\n", status);
+#endif
+		status = writeRegister(device, TRF7960_REG_CSC, status);
+		// init other registers (only if previous mode was 0 or 1)
+		if(device->vio < 27)
+			; /* set bit 5 in Reg #0x0b to decrease output resistance for low voltage I/O */
+		udelay(5000);	/* wait until reader has recovered (should depend on previous and current mode) */
+	}
+	return status;
+}
+
+int chooseProtocol(struct trf7960 *device, int protocol)
+{
+#if 1
+	printf("chooseProtocol %d\n", protocol);
+#endif
+	if((protocol < 0 || protocol >15) && protocol != 0x13)
+		return -1;
+	protocol |= readRegister(device, TRF7960_REG_CSC) & 0x80;	/* keep no RX CRC mode */
+	return writeRegister(device, TRF7960_REG_ISOC, protocol);
+}
+
+/* high level functions (protocol handlers) */
+/* the meaning of the flags and command codes in ISO15693 mode are described in TI document sloa141.pdf */
+
+int scanInventory(struct trf7960 *device, uchar flags, uchar length, void (*found)(struct trf7960 *device, uint64_t uid, int rssi))
+{ /* poll for tag uids and resolve collisions */
+	static uchar buffer[32];	/* shared rx/tx buffer */
+	uchar collisionslots[16];	/* up to 16 collision slots */
+	int collisions = 0;
+	uchar mask[8];	/* up to 8 mask bytes */
+	int slot;
+	int slots = (flags & (1<<5)) ? 1 : 16;	/* multislot flag */
+	
+	int masksize = (length + 7) / 8;	/* add one mask byte for each started 8 bits */
+	int pdusize = 3 + masksize;			/* flags byte + command byte + mask length byte + mask bytes */
+	
+	int protocol = readRegister(device, TRF7960_REG_ISOC) & 0x1f;
+
+	if((protocol & 0x18) == TRF7960_PROTOCOL_ISO15693_LBR_1SC_4)
+		;	/* ISO15693 */
+	// FIXME: implement different algorithms for other protocols
+	if((protocol & 0x1c) == TRF7960_PROTOCOL_ISO14443A_BR_106)
+		return -1;	/* ISO14443A */
+	if((protocol & 0x1c) == TRF7960_PROTOCOL_ISO14443B_BR_106)
+		return -1;	/* ISO14443B */
+	if(protocol == TRF7960_PROTOCOL_TAGIT)
+		return -1;	/* Tag-It */
+	if(protocol >= 0x10)
+		return -1;	/* undefined */
+#if 1
+	printf("inventoryRequest\n");
+#endif
+	spi_claim_bus(device->slave);
+	
+	if(writeRegister(device, TRF7960_REG_IRQMASK, 0x3f))	/* enable no-response interrupt */
+		return -1;
+
+	// write modulator control
+	/* writeRegister(device, TRF... 0x09, something); */
+	// set rxnoresponse timeout to 0x2f if bit1 is 0 (low data rate), 0x13 else (high data rate)
+	
+	buffer[0] = TRF7960_COMMAND | TRF7960_CMD_RESET;	/* reset FIFO */
+	buffer[1] = TRF7960_COMMAND | TRF7960_CMD_TX_CRC;	/* start TX with CRC */
+	buffer[2] = 0x3d;	/* continuous write to register 0x1d */
+	
+	buffer[5] = flags;	/* ISO15693 flags */
+	buffer[6] = 0x01;	/* ISO15693 inventory command */
+	if(flags & (1<<4)) { /* AFI */
+		buffer[7] = 0;	/* insert AFI value */
+		buffer[8] = length;	/* mask length in bits */
+		memcpy(&buffer[9], mask, masksize);	/* append mask */
+		pdusize++;
+	}
+	else {
+		buffer[7] = length;	/* mask length in bits */
+		memcpy(&buffer[8], mask, masksize);	/* append mask */		
+	}
+	buffer[3] = pdusize >> 8;
+	buffer[4] = pdusize << 4;
+	prepareIrq(device, &buffer[5+12], pdusize-12);
+	if(pdusize > 12)
+		pdusize=12; /* limit initial transmission - remainder is sent by interrupt handler */
+#if 0
+	printf("length = %d\n", length);
+	printf("masksize = %d\n", masksize);
+	printf("pdusize = %d\n", pdusize);
+	printf("bitsize = %d\n", 8*sizeof(buffer[0])*(5 + pdusize));
+#endif
+	if(spi_xfer(device->slave, 8*sizeof(buffer[0])*(5 + pdusize), buffer, buffer, SPI_XFER_BEGIN | SPI_XFER_END) != 0)
+		return -1;
+#if 0
+	printf("cmd sent\n");
+#endif
+	waitIrq(device);	/* wait for TX interrupt */
+#if 0
+	printf("tx done %02x\n", device->done);
+#endif
+	if(!(device->done & 0x80)) {
+#if 1
+		printf(" unknown TX interrupt %02x\n", device->done);
+#endif
+		return -1;
+	}
+	collisions=0;
+	for(slot=0; slot < slots; slot++) { /* repeat for all time slots */
+		int rssi;
+#if 0
+		printf("slot %d\n", slot);
+#endif
+		prepareIrq(device, buffer, 10);	/* prepare for RX of tag id (2 bytes status + 8 bytes UID) */
+		waitIrq(device);	/* wait for RX interrupt */
+#if 1
+		printf("rx[%d] done %02x", slot, device->done);
+#endif
+		rssi = readRegister(device, TRF7960_REG_RSSI) & 0x3f;
+#if 0
+		printf(" rssi=%02o", rssi);	/* print 2 octal digits for AUX and Active channel */
+#endif
+		if(device->done & 0x02) { /* collision */
+#if 1
+			printf(" collision\n");
+#endif
+			collisionslots[collisions++]=slot;	/* remember slot number */
+		}
+		else if(device->done & 0x01) {
+			/* ignore no response timeout */
+#if 1
+			printf(" no response\n");
+#endif
+		}
+		/* check for other errors */
+		else if(device->done & 0x40) { /* RX done - FIFO already reset */
+			union {
+				uint64_t uid;
+				char b[sizeof(uint64_t)];
+			} uid;
+#if 0
+			printf(" valid id received\n");
+#endif
+			// buffer[0] and buffer[1] appear to be status flags and 00 if ok
+			memcpy(uid.b, &buffer[2], sizeof(uid.uid));	/* extract UID */
+			(*found)(device, le64_to_cpu(uid.uid), rssi);	/* notify caller */
+		}
+		else {
+#if 1
+			printf(" unknown condition %02x\n", device->done);
+#endif
+			break;	/* unknown interrupt reason */
+		}
+		if(!(device->done & 0x40))
+			sendCommand(device, TRF7960_CMD_RESET);	/* reset FIFO */
+		if(slots == 16) { /* send EOF only in ISO15693 multislot Inventory command */
+			sendCommand(device, TRF7960_CMD_RX_BLOCK);
+			sendCommand(device, TRF7960_CMD_RX_ENABLE);
+			sendCommand(device, TRF7960_CMD_TX_NEXT_SLOT);
+		}
+	}
+	if(slots == 16 ) {
+		int i;
+#if 1
+		printf("did have %d collisions\n", collisions);
+#endif
+		for(i=0; i<collisions; i++) { /* loop over all slots with collision */
+			// generate new mask (increased length by 4) from collision slot numbers
+			// inventoryRequest(new mask, length+4)
+		}
+	}
+	// FIXME: how to handle collision in single slot mode?
+	// disable irq
+	spi_release_bus(device->slave);
+	return 0;
+}
+
+int readBlocks(struct trf7960 *device, uchar flags, uint64_t uid, uchar firstBlock, uchar blocks, uchar *data)
+{ /* read single/multiple blocks */
+	static uchar buffer[32];	/* shared rx/tx buffer */
+	char *rxbuf;
+	int pdusize = 4 + (uid?sizeof(uid):0);			/* flags byte + command byte + optional uid + firstblock + #blocks */
+#if 1
+	printf("readBlocks\n");
+#endif
+	if(blocks == 0)
+		return 0;	/* no blocks */
+	spi_claim_bus(device->slave);
+	
+	if(writeRegister(device, TRF7960_REG_IRQMASK, 0x3f))	/* enable no-response interrupt */
+		return -1;
+	
+	rxbuf=malloc(2+32*blocks);	// allocate enough memory for storing 32*blocks bytes
+	if(!rxbuf)
+		return -1;	// can't allocate
+
+	buffer[0] = TRF7960_COMMAND | TRF7960_CMD_RESET;	/* reset FIFO */
+	buffer[1] = TRF7960_COMMAND | TRF7960_CMD_TX_CRC;	/* start TX with CRC */
+	buffer[2] = 0x3d;	/* continuous write to register 0x1d */
+	
+	buffer[5] = flags;	/* ISO15693 flags */
+	buffer[6] = blocks > 1 ? 0x23 : 0x20;	/* ISO15693 read single or multiple blocks command */
+	if(uid) { /* include uid if not 0LL */
+		union {
+			uint64_t uid;
+			char b[sizeof(uint64_t)];
+		} uid2;
+		uid2.uid=cpu_to_le64(uid);
+		memcpy(&buffer[7], uid2.b, sizeof(uid2.b));
+		pdusize=2+8+1;
+		buffer[15]=firstBlock;
+		if(blocks > 1) {
+			buffer[16]=blocks-1;
+			pdusize++;
+		}
+	} else { /* no UID */
+		pdusize=2+1;
+		buffer[7]=firstBlock;
+		if(blocks > 1) {
+			buffer[8]=blocks-1;
+			pdusize++;
+		}
+	}
+	buffer[3] = pdusize >> 8;
+	buffer[4] = pdusize << 4;
+	prepareIrq(device, &buffer[5+12], pdusize-12);
+	if(pdusize > 12)
+		pdusize=12; /* limit initial transmission - remainder is sent by interrupt handler */
+#if 1
+	printf("firstBlock = %d\n", firstBlock);
+	printf("blocks = %d\n", blocks);
+	printf("pdusize = %d\n", pdusize);
+	printf("bitsize = %d\n", 8*sizeof(buffer[0])*(5 + pdusize));
+#endif
+	if(spi_xfer(device->slave, 8*sizeof(buffer[0])*(5 + pdusize), buffer, buffer, SPI_XFER_BEGIN | SPI_XFER_END) != 0) {
+		free(rxbuf);
+		return -1;
+	}
+#if 1
+	printf("cmd sent\n");
+#endif
+	waitIrq(device);	/* wait for TX interrupt */
+#if 1
+	printf("tx done %02x\n", device->done);
+#endif
+	if(!device->done & 0x80) {
+#if 1
+		printf(" unknown TX interrupt %02x\n", device->done);
+#endif
+		free(rxbuf);
+		return -1;
+	}
+	// FIXME: the first bytes received are not data bytes but the received PDU!
+	// should we introduce some chained mbuf scheme???
+	prepareIrq(device, rxbuf, 2+32*blocks);	/* prepare for receiving n*32 bytes RX */
+	waitIrq(device);	/* wait for RX interrupt */
+	// check for standard RX done or Collision or timeout or other errors
+#if 1
+	printf("rx done %02x\n", device->done);
+	if(device->done & 0x01)
+		printf("  timeout\n");
+	if(device->done & 0x02)
+		printf("  collision\n");
+#endif
+	if(rxbuf[0] != 0)
+		printf("  rx flags %02x\n", rxbuf[0]);
+	// if ok, read the flags byte from the received PDU to determine potential errors
+	memcpy(data, rxbuf+2, 32*blocks);	// copy payload
+	free(rxbuf);
+	return 0;
+}
+
+int writeBlocks(struct trf7960 *device, uchar flags, uint64_t uid, uchar firstBlock, uchar blocks, uchar *data)
+{ /* write single/multiple blocks */
+	return -1;
+}
+ 
+/* this all below belongs to GUI/board driver */
+
+/* define BeagleBoard + Expander hardware IF */
+
+struct trf7960 rfid_board = {
+	.bus = 2,	/* McSPI3 */
+	.cs = 0,	/* CS0 */
+	.clock = 1000000,	/* clock speed */
+	.irq = 156,	/* KEYIRQ/GPIO156 */
+	.en = 161,
+	.en2 = 159,
+	.vio = 18	/* we use 1.8V IO */
+};
+
+static int numfound;
+
+static void found(struct trf7960 *device, uint64_t uid, int rssi)
+{
+	extern void status_set_status(int value);
+//	int i;
+	numfound++;
+	printf("UID = %llX", uid);
+//	for(i=0; i < 8; i++)
+//		printf("%02x", (uid>>(8*(7-i))));
+	printf(" rssi = %d/%d\n", rssi/8, rssi%8);
+}
+
+static int do_rfid(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+{
+	int len;
+	static int statusinit;
+	extern void status_set_status(int value);
+	extern int status_init(void);
+	
+	if (argc < 2) {
+		printf ("rfid: missing subcommand.\n");
+		return (-1);
+	}
+	
+	if (!statusinit) { // initialize status LEDs for scan/loop subcommands
+		status_init();
+		statusinit=1;
+	}
+	
+	len = strlen (argv[1]);
+	if (strncmp ("po", argv[1], 2) == 0) {
+		return setPowerMode(&rfid_board, simple_strtoul(argv[2], NULL, 10)) < 0?1:0;
+		
+#if 1
+	} else if (strncmp ("re", argv[1], 2) == 0) {
+		int r;
+		for(r=0; r <= 0x1f; r++)
+			printf("%02x: %02x\n", r, readRegister(&rfid_board, r));
+	} else if (strncmp ("co", argv[1], 2) == 0) {
+		return 1;
+	} else if (strncmp ("rw", argv[1], 2) == 0) {
+#define MAX_SPI_BYTES 32
+		static int   		bitlen;
+		static uchar 		dout[MAX_SPI_BYTES];
+		static uchar 		din[MAX_SPI_BYTES];
+		char  *cp = 0;
+		uchar tmp;
+		int   j;
+		int   rcode = 0;
+		if (argc >= 3)
+			bitlen = simple_strtoul(argv[2], NULL, 10);
+		if (argc >= 4) {
+			cp = argv[3];
+			for(j = 0; *cp; j++, cp++) {
+				tmp = *cp - '0';
+				if(tmp > 9)
+					tmp -= ('A' - '0') - 10;
+				if(tmp > 15)
+					tmp -= ('a' - 'A');
+				if(tmp > 15) {
+					printf("Hex conversion error on %c\n", *cp);
+					return 1;
+				}
+				if((j % 2) == 0)
+					dout[j / 2] = (tmp << 4);
+				else
+					dout[j / 2] |= tmp;
+			}
+		}
+		if ((bitlen < 0) || (bitlen >  (MAX_SPI_BYTES * 8))) {
+			printf("Invalid bitlen %d\n", bitlen);
+			return 1;
+		}
+		
+		if(spi_xfer(rfid_board.slave, bitlen, dout, din,
+					SPI_XFER_BEGIN | SPI_XFER_END) != 0) {
+			printf("Error during SPI transaction\n");
+			rcode = 1;
+		} else {
+			for(j = 0; j < ((bitlen + 7) / 8); j++) {
+				printf("%02X", din[j]);
+			}
+			printf("\n");
+		}		
+#endif
+	} else if (strncmp ("sc", argv[1], 2) == 0) {
+		numfound=0;
+		setPowerMode(&rfid_board, TRF7960_POWER_RXTX_FULL);
+		chooseProtocol(&rfid_board, 0x02);	/* ISO15693 26kbps one-sub 1-out-of-4 (default) */
+		scanInventory(&rfid_board, 0x06 /* 0x26 1slot */, 0, &found);
+		setPowerMode(&rfid_board, TRF7960_POWER_STANDBY);
+		status_set_status(numfound > 0?0x3f:0x00);	/* LEDs on/off */
+	} else if (strncmp ("lo", argv[1], 2) == 0) {
+		setPowerMode(&rfid_board, TRF7960_POWER_RXTX_FULL);
+		chooseProtocol(&rfid_board, 0x02);	/* ISO15693 26kbps one-sub 1-out-of-4 (default) */
+		while(!tstc()) { // scan until key is pressed
+			numfound=0;
+			scanInventory(&rfid_board, 0x06 /* 0x26 1slot */, 0, &found);
+			status_set_status(numfound);	/* LEDs binary count */
+			udelay(300*1000);	// wait 0.3 seconds
+		}
+		setPowerMode(&rfid_board, TRF7960_POWER_STANDBY);
+		if(tstc())
+			getc();
+	} else if (strncmp ("rb", argv[1], 2) == 0) { // read block
+		uint64_t uid=0;	/* set by =uid (hex) */
+		uchar firstBlock=0;	/* set by next parameter */
+		uchar blocks=1;	/* set by +n parameter (decimal) */
+		uchar *data;
+		int r;
+		int i=2;
+		if(argv[i] && argv[i][0] == '=') {
+			uid=simple_strtoull(argv[i]+1, NULL, 16);
+			i++;
+		}
+		if(argv[i] && argv[i][0] == '+') {
+			blocks=simple_strtoul(argv[i]+1, NULL, 10);
+			i++;
+		}
+		if(argv[i]) {
+			firstBlock=simple_strtoul(argv[i], NULL, 10);
+			i++;
+		}
+		data=malloc(32*blocks);	// allocate enough memory for storing 32*blocks bytes!
+		if(!data) {
+			printf ("rfid %s: can't allocate buffer for %d blocks\n", argv[1], blocks);			
+			return (1);
+		}
+		setPowerMode(&rfid_board, TRF7960_POWER_RXTX_FULL);
+		chooseProtocol(&rfid_board, 0x02);	/* ISO15693 26kbps one-sub 1-out-of-4 (default) */
+		r=readBlocks(&rfid_board, uid > 0?0x16:0x06, uid, firstBlock, blocks, data);
+		printf("r=%d\n", r);
+		for(i=0; i<blocks; i++) { // print data (hex)
+			int b;
+			for(b=0; b<32; b++) {
+				if(b%16 == 0) {
+					if(b == 0)
+						printf("%03d: ", firstBlock+i);
+					else
+						printf("     ");					
+				}
+				printf("%02x", data[32*i+b]);
+				if(b%16 == 15)
+					printf("\n");
+			}
+		}
+		setPowerMode(&rfid_board, TRF7960_POWER_STANDBY);
+		free(data);
+	} else if (strncmp ("wb", argv[1], 2) == 0) {
+		// FIXME: write block
+	} else {
+		printf ("rfid: unknown operation: %s\n", argv[1]);
+	}
+	
+	return (0);
+}
+
+U_BOOT_CMD(
+	rfid,	5,	1,	do_rfid,
+	"RFID utility command",
+	"po[wer] n - set power state (0=off, 1=60kHz, 2=standby, 3=active, 4=rx, 5=half, 6=full)\n"
+	"re[gisters] - read registers\n"
+    "rw [bitlen [hexvalue]] - read/write SPI data block\n"
+    "sc[an] - scan inventory\n"
+	"lo[op] - permanently scan inventory until key is pressed\n"
+    "rb[lock] [=uid] [+n] [first] - read n (default=1) 32 byte block(s) starting at first\n"
+    "wb[lock] [=uid] [+n] first hexvalue - write n (default=1) 32 byte block(s) starting at first\n"
+);
diff --git a/u-boot/board/goldelico/panda-hybrid/Makefile b/u-boot/board/goldelico/panda-hybrid/Makefile
new file mode 100644
index 0000000..849e243
--- /dev/null
+++ b/u-boot/board/goldelico/panda-hybrid/Makefile
@@ -0,0 +1,50 @@
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= pandahyb.o 
+#../gta04/TD028TTEC1.o ../gta04/jbt6k74.o ../gta04/backlight.o ../gta04/status.o ../gta04/tsc2007.o ../gta04/dssfb.o ../gta04/gps.o ../gta04/shutdown.o ../gta04/systest.o ../gta04/commands.o
+
+SRCS	:= $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
\ No newline at end of file
diff --git a/u-boot/board/goldelico/panda-hybrid/config.mk b/u-boot/board/goldelico/panda-hybrid/config.mk
new file mode 100644
index 0000000..cf055db
--- /dev/null
+++ b/u-boot/board/goldelico/panda-hybrid/config.mk
@@ -0,0 +1,33 @@
+#
+# (C) Copyright 2006
+# Texas Instruments, <www.ti.com>
+#
+# Beagle Board uses OMAP3 (ARM-CortexA8) cpu
+# see http://www.ti.com/ for more information on Texas Instruments
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+# Physical Address:
+# 8000'0000 (bank0)
+# A000/0000 (bank1)
+# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
+# (mem base + reserved)
+
+# For use with external or internal boots.
+CONFIG_SYS_TEXT_BASE = 0x80008000
diff --git a/u-boot/board/goldelico/panda-hybrid/pandahyb.c b/u-boot/board/goldelico/panda-hybrid/pandahyb.c
new file mode 100644
index 0000000..1ff467a
--- /dev/null
+++ b/u-boot/board/goldelico/panda-hybrid/pandahyb.c
@@ -0,0 +1,31 @@
+#include <common.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/mmc_host_def.h>
+#include "../../ti/panda/panda.h"
+#include "pandahyb.h"
+
+/*
+ somehow redefine:
+ const struct omap_sysinfo sysinfo = {
+	"Board: OMAP4 Panda\n"
+};
+*/
+
+// tamper with set_muxconf_regs() to extend its functionality
+
+void do_set_mux(u32 base, struct pad_conf_entry const *array, int size);
+void set_muxconf_regs_inherited(void);
+
+void set_muxconf_regs(void)
+{
+	set_muxconf_regs_inherited();	// call "superclass method"
+	do_set_mux(CONTROL_PADCONF_CORE, hybrid_padconf_array,
+			   sizeof(hybrid_padconf_array) /
+			   sizeof(struct pad_conf_entry));
+	
+}
+
+// rename original definition in panda.c
+#define set_muxconf_regs set_muxconf_regs_inherited
+
+#include "../../ti/panda/panda.c"
diff --git a/u-boot/board/goldelico/panda-hybrid/pandahyb.h b/u-boot/board/goldelico/panda-hybrid/pandahyb.h
new file mode 100644
index 0000000..4501239
--- /dev/null
+++ b/u-boot/board/goldelico/panda-hybrid/pandahyb.h
@@ -0,0 +1,32 @@
+// FIXME: Panda has a different initialization scheme!
+// we have to extend const struct pad_conf_entry core_padconf_array[]
+
+#include <asm/io.h>
+#include <asm/arch/mux_omap4.h>
+
+const struct pad_conf_entry hybrid_padconf_array[] = {
+	// add entries
+};
+	
+#if 0
+
+#define MUX_BEAGLE_HYBRID() \
+MUX_VAL(CP(MMC2_CLK),		(IEN  | PTU | EN  | M0)) /*GPIO_130 -> MMC2_CLK*/\
+MUX_VAL(CP(MMC2_CMD),		(IEN  | PTU | EN  | M0)) /*GPIO_131 -> MMC2_CMD*/\
+MUX_VAL(CP(MMC2_DAT0),		(IEN  | PTU | EN  | M0)) /*GPIO_132 -> MMC2_DAT0*/\
+MUX_VAL(CP(MMC2_DAT1),		(IEN  | PTU | EN  | M0)) /*GPIO_133 -> MMC2_DAT1*/\
+MUX_VAL(CP(MMC2_DAT2),		(IEN  | PTU | EN  | M0)) /*GPIO_134 -> MMC2_DAT2*/\
+MUX_VAL(CP(MMC2_DAT3),		(IEN  | PTU | EN  | M0)) /*GPIO_135 -> MMC2_DAT3*/\
+MUX_VAL(CP(MMC2_DAT4),		(IEN  | PTU | EN  | M4)) /*GPIO_136 - AUX */\
+MUX_VAL(CP(MMC2_DAT5),		(IEN  | PTU | EN  | M4)) /*GPIO_137 - POWER */\
+MUX_VAL(CP(MMC2_DAT6),		(IEN  | PTU | DIS  | M4)) /*GPIO_138 - EXT-ANT */\
+MUX_VAL(CP(MMC2_DAT7),		(IEN  | PTU | EN  | M4)) /*GPIO_139 - RS232 EXT */\
+MUX_VAL(CP(MCBSP1_CLKR),	(IDIS | PTD | DIS | M4)) /*GPIO_156 - GPS ON(0)/OFF(1)*/\
+MUX_VAL(CP(MCBSP1_FSR),		(IEN  | PTU | EN  | M4)) /*GPIO_157 - PENIRQ */\
+MUX_VAL(CP(MCBSP1_DX),		(IDIS | PTD | EN  | M4)) /*GPIO_158 - DOUT */\
+MUX_VAL(CP(MCBSP1_DR),		(IEN  | PTU | DIS | M4)) /*GPIO_159 - DIN - pulled up */\
+MUX_VAL(CP(MCBSP_CLKS),		(IEN  | PTU | DIS | M0)) /*McBSP_CLKS*/\
+MUX_VAL(CP(MCBSP1_FSX),		(IDIS | PTU | EN  | M4)) /*GPIO_161 - CS */\
+MUX_VAL(CP(MCBSP1_CLKX),	(IDIS | PTD | EN  | M4)) /*GPIO_162 - SCL */
+
+#endif