added boot script files to repository

6 files changed, 987 insertions, 0 deletions

diff --git a/u-boot/board/hidden_dragon/Makefile b/u-boot/board/hidden_dragon/Makefile
new file mode 100644
index 0000000..befc92a
--- /dev/null
+++ b/u-boot/board/hidden_dragon/Makefile
@@ -0,0 +1,44 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS =  $(BOARD).o flash.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/hidden_dragon/README b/u-boot/board/hidden_dragon/README
new file mode 100644
index 0000000..529fe2b
--- /dev/null
+++ b/u-boot/board/hidden_dragon/README
@@ -0,0 +1,60 @@
+U-Boot for Hidden Dragon board
+------------------------------
+
+Hidden Dragon is a MPC824x-based board by Motorola. For the most
+part it is similar to Sandpoint8245 board. So unless otherwise
+mentioned, the codes in this directory are adapted from ../sandpoint
+directory.
+
+Apparently there are very few of this board out there. Even Motorola
+website does not have any info on it.
+
+RAM:
+  start = 0x0000 0000
+  size	= 0x0200 0000 (32 MB)
+
+Flash:
+  BANK ONE:
+    start = 0xFFE0 0000
+    size  = 0x0020 0000 (2 MB)
+    flash chip = 29LV160TE (1x16 Mbits or 2x8 Mbits)
+    flash sectors = 16K, 2x8K, 32K, 31x64K
+
+  BANK TWO:
+    NONE
+
+The processor interrupt vectors reside on the first 256 bytes
+starting from address 0xFFF00000. The "reset vector" (first
+instruction executed after reset) is located on 0xFFF0 0100.
+
+U-Boot is configured to reside in flash starting at the address of
+0xFFF00000. The environment space is located in flash separately from
+U-Boot, at the second sector of the first flash bank, starting from
+0xFFE04000 until 0xFFE06000 (8KB).
+
+Network:
+  - RTL8139 chip on the base board	  (SUPPORTED)
+  - RTL8129 chip on the processor board	  (NOT SUPPORTED)
+
+Serial:
+  - Two NS16550 compatible UART on the processor board	(SUPPORTED)
+  - One NS16550 compatible UART on the base board	(UNTESTED)
+
+Misc:
+  VIA686A PCI SuperIO peripheral controller
+  - 2 USB ports		    (UNTESTED)
+  - 2 PS2 ports		    (UNTESTED)
+  - Parallel port	    (UNTESTED)
+  - IDE & floppy interface  (UNTESTED)
+
+  S3 Savage4 video card	    (UNTESTED)
+
+TODO:
+-----
+- Support for the VIA686A based peripherals
+- The RTL8139 driver frequently gives rx error.
+- Support for RTL8129 network controller. (Why is the support removed from
+  rtl8139.c driver?)
+
+(C) Copyright 2004
+Yusdi Santoso, Adaptec Inc., yusdi_santoso@adaptec.com
diff --git a/u-boot/board/hidden_dragon/early_init.S b/u-boot/board/hidden_dragon/early_init.S
new file mode 100644
index 0000000..61b4b55
--- /dev/null
+++ b/u-boot/board/hidden_dragon/early_init.S
@@ -0,0 +1,153 @@
+/*
+ * (C) Copyright 2001
+ * Thomas Koeller, tkoeller@gmx.net
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef	__ASSEMBLY__
+#define __ASSEMBLY__	1
+#endif
+
+#include <asm-offsets.h>
+#include <config.h>
+#include <asm/processor.h>
+#include <mpc824x.h>
+#include <ppc_asm.tmpl>
+
+#if defined(USE_DINK32)
+  /* We are running from RAM, so do not clear the MCCR1_MEMGO bit! */
+  #define MCCR1VAL ((CONFIG_SYS_ROMNAL << MCCR1_ROMNAL_SHIFT) | (CONFIG_SYS_ROMFAL << MCCR1_ROMFAL_SHIFT) | MCCR1_MEMGO)
+#else
+  #define MCCR1VAL (CONFIG_SYS_ROMNAL << MCCR1_ROMNAL_SHIFT) | (CONFIG_SYS_ROMFAL << MCCR1_ROMFAL_SHIFT)
+#endif
+
+	.text
+
+	/* Values to program into memory controller registers */
+tbl:	.long	MCCR1, MCCR1VAL
+	.long	MCCR2, CONFIG_SYS_REFINT << MCCR2_REFINT_SHIFT
+	.long	MCCR3
+	.long	(((CONFIG_SYS_BSTOPRE & 0x000000f0) >> 4) << MCCR3_BSTOPRE2TO5_SHIFT) | \
+		(CONFIG_SYS_REFREC << MCCR3_REFREC_SHIFT) | \
+		(CONFIG_SYS_RDLAT  << MCCR3_RDLAT_SHIFT)
+	.long	MCCR4
+	.long	(CONFIG_SYS_PRETOACT << MCCR4_PRETOACT_SHIFT) | (CONFIG_SYS_ACTTOPRE << MCCR4_ACTTOPRE_SHIFT) | \
+		(CONFIG_SYS_REGISTERD_TYPE_BUFFER << 20) | \
+		(((CONFIG_SYS_BSTOPRE & 0x00000300) >> 8) << MCCR4_BSTOPRE0TO1_SHIFT ) | \
+		((CONFIG_SYS_SDMODE_CAS_LAT << 4) | (CONFIG_SYS_SDMODE_WRAP << 3) | \
+		(CONFIG_SYS_SDMODE_BURSTLEN) << MCCR4_SDMODE_SHIFT) | \
+		(CONFIG_SYS_ACTTORW << MCCR4_ACTTORW_SHIFT) | \
+		((CONFIG_SYS_BSTOPRE & 0x0000000f) << MCCR4_BSTOPRE6TO9_SHIFT )
+	.long	MSAR1
+	.long	(((CONFIG_SYS_BANK0_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) <<  0) | \
+		(((CONFIG_SYS_BANK1_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) <<  8) | \
+		(((CONFIG_SYS_BANK2_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \
+		(((CONFIG_SYS_BANK3_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24)
+	.long	EMSAR1
+	.long	(((CONFIG_SYS_BANK0_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) <<  0) | \
+		(((CONFIG_SYS_BANK1_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) <<  8) | \
+		(((CONFIG_SYS_BANK2_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \
+		(((CONFIG_SYS_BANK3_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24)
+	.long	MSAR2
+	.long	(((CONFIG_SYS_BANK4_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) <<  0) | \
+		(((CONFIG_SYS_BANK5_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) <<  8) | \
+		(((CONFIG_SYS_BANK6_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \
+		(((CONFIG_SYS_BANK7_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24)
+	.long	EMSAR2
+	.long	(((CONFIG_SYS_BANK4_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) <<  0) | \
+		(((CONFIG_SYS_BANK5_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) <<  8) | \
+		(((CONFIG_SYS_BANK6_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \
+		(((CONFIG_SYS_BANK7_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24)
+	.long	MEAR1
+	.long	(((CONFIG_SYS_BANK0_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) <<  0) | \
+		(((CONFIG_SYS_BANK1_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) <<  8) | \
+		(((CONFIG_SYS_BANK2_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \
+		(((CONFIG_SYS_BANK3_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24)
+	.long	EMEAR1
+	.long	(((CONFIG_SYS_BANK0_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) <<  0) | \
+		(((CONFIG_SYS_BANK1_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) <<  8) | \
+		(((CONFIG_SYS_BANK2_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \
+		(((CONFIG_SYS_BANK3_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24)
+	.long	MEAR2
+	.long	(((CONFIG_SYS_BANK4_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) <<  0) | \
+		(((CONFIG_SYS_BANK5_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) <<  8) | \
+		(((CONFIG_SYS_BANK6_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \
+		(((CONFIG_SYS_BANK7_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24)
+	.long	EMEAR2
+	.long	(((CONFIG_SYS_BANK4_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) <<  0) | \
+		(((CONFIG_SYS_BANK5_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) <<  8) | \
+		(((CONFIG_SYS_BANK6_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \
+		(((CONFIG_SYS_BANK7_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24)
+	.long	0
+
+
+	/*
+	 * Early CPU initialization. Set up memory controller, so we can access any RAM at all. This
+	 * must be done in assembly, since we have no stack at this point.
+	 */
+	.global	early_init_f
+early_init_f:
+	mflr	r10
+
+	/* basic memory controller configuration */
+	lis	r3, CONFIG_ADDR_HIGH
+	lis	r4, CONFIG_DATA_HIGH
+	bl	lab
+lab:	mflr	r5
+	lwzu	r0, tbl - lab(r5)
+loop:	lwz	r1, 4(r5)
+	stwbrx	r0, 0, r3
+	eieio
+	stwbrx	r1, 0, r4
+	eieio
+	lwzu	r0, 8(r5)
+	cmpli	cr0, 0, r0, 0
+	bne	cr0, loop
+
+	/* set bank enable bits */
+	lis	r0, MBER@h
+	ori	r0, 0, MBER@l
+	li	r1, CONFIG_SYS_BANK_ENABLE
+	stwbrx	r0, 0, r3
+	eieio
+	stb	r1, 0(r4)
+	eieio
+
+	/* delay loop */
+	lis	r0, 0x0003
+	mtctr   r0
+delay:	bdnz	delay
+
+	/* enable memory controller */
+	lis	r0, MCCR1@h
+	ori	r0, 0, MCCR1@l
+	stwbrx	r0, 0, r3
+	eieio
+	lwbrx	r0, 0, r4
+	oris	r0, 0, MCCR1_MEMGO@h
+	stwbrx	r0, 0, r4
+	eieio
+
+	/* set up stack pointer */
+	lis	r1, CONFIG_SYS_INIT_SP_OFFSET@h
+	ori	r1, r1, CONFIG_SYS_INIT_SP_OFFSET@l
+
+	mtlr	r10
+	blr
diff --git a/u-boot/board/hidden_dragon/flash.c b/u-boot/board/hidden_dragon/flash.c
new file mode 100644
index 0000000..2ce1dc4
--- /dev/null
+++ b/u-boot/board/hidden_dragon/flash.c
@@ -0,0 +1,575 @@
+/*
+ * (C) Copyright 2004
+ * Yusdi Santoso, Adaptec Inc., yusdi_santoso@adaptec.com
+ *
+ * (C) Copyright 2000-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc824x.h>
+#include <asm/processor.h>
+#include <asm/pci_io.h>
+#include <w83c553f.h>
+
+#define ROM_CS0_START	0xFF800000
+#define ROM_CS1_START	0xFF000000
+
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips    */
+
+#if defined(CONFIG_ENV_IS_IN_FLASH)
+# ifndef  CONFIG_ENV_ADDR
+#  define CONFIG_ENV_ADDR  (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
+# endif
+# ifndef  CONFIG_ENV_SIZE
+#  define CONFIG_ENV_SIZE  CONFIG_ENV_SECT_SIZE
+# endif
+# ifndef  CONFIG_ENV_SECT_SIZE
+#  define CONFIG_ENV_SECT_SIZE  CONFIG_ENV_SIZE
+# endif
+#endif
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static int write_word (flash_info_t *info, ulong dest, ulong data);
+
+/*flash command address offsets*/
+
+#define ADDR0		(0xAAA)
+#define ADDR1		(0x555)
+#define ADDR3		(0x001)
+
+#define FLASH_WORD_SIZE unsigned char
+
+/*-----------------------------------------------------------------------
+ */
+
+static unsigned long flash_id (unsigned char mfct, unsigned char chip)
+	__attribute__ ((const));
+
+typedef struct {
+	FLASH_WORD_SIZE extval;
+	unsigned short intval;
+} map_entry;
+
+static unsigned long flash_id (unsigned char mfct, unsigned char chip)
+{
+	static const map_entry mfct_map[] = {
+		{(FLASH_WORD_SIZE) AMD_MANUFACT,
+		 (unsigned short) ((unsigned long) FLASH_MAN_AMD >> 16)},
+		{(FLASH_WORD_SIZE) FUJ_MANUFACT,
+		 (unsigned short) ((unsigned long) FLASH_MAN_FUJ >> 16)},
+		{(FLASH_WORD_SIZE) STM_MANUFACT,
+		 (unsigned short) ((unsigned long) FLASH_MAN_STM >> 16)},
+		{(FLASH_WORD_SIZE) MT_MANUFACT,
+		 (unsigned short) ((unsigned long) FLASH_MAN_MT >> 16)},
+		{(FLASH_WORD_SIZE) INTEL_MANUFACT,
+		 (unsigned short) ((unsigned long) FLASH_MAN_INTEL >> 16)},
+		{(FLASH_WORD_SIZE) INTEL_ALT_MANU,
+		 (unsigned short) ((unsigned long) FLASH_MAN_INTEL >> 16)}
+	};
+
+	static const map_entry chip_map[] = {
+		{AMD_ID_F040B, FLASH_AM040},
+		{(FLASH_WORD_SIZE) STM_ID_x800AB, FLASH_STM800AB}
+	};
+
+	const map_entry *p;
+	unsigned long result = FLASH_UNKNOWN;
+
+	/* find chip id */
+	for (p = &chip_map[0];
+	     p < &chip_map[sizeof chip_map / sizeof chip_map[0]]; p++)
+		if (p->extval == chip) {
+			result = FLASH_VENDMASK | p->intval;
+			break;
+		}
+
+	/* find vendor id */
+	for (p = &mfct_map[0];
+	     p < &mfct_map[sizeof mfct_map / sizeof mfct_map[0]]; p++)
+		if (p->extval == mfct) {
+			result &= ~FLASH_VENDMASK;
+			result |= (unsigned long) p->intval << 16;
+			break;
+		}
+
+	return result;
+}
+
+unsigned long flash_init (void)
+{
+	unsigned long i;
+	unsigned char j;
+	static const ulong flash_banks[] = CONFIG_SYS_FLASH_BANKS;
+
+	/* Init: no FLASHes known */
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
+		flash_info_t *const pflinfo = &flash_info[i];
+
+		pflinfo->flash_id = FLASH_UNKNOWN;
+		pflinfo->size = 0;
+		pflinfo->sector_count = 0;
+	}
+
+	/* Enable writes to Hidden Dragon flash */
+	{
+		register unsigned char temp;
+
+		CONFIG_READ_BYTE (CONFIG_SYS_WINBOND_ISA_CFG_ADDR + WINBOND_CSCR,
+				  temp);
+		temp &= ~0x20;	/* clear BIOSWP bit */
+		CONFIG_WRITE_BYTE (CONFIG_SYS_WINBOND_ISA_CFG_ADDR + WINBOND_CSCR,
+				   temp);
+	}
+
+	for (i = 0; i < sizeof flash_banks / sizeof flash_banks[0]; i++) {
+		flash_info_t *const pflinfo = &flash_info[i];
+		const unsigned long base_address = flash_banks[i];
+		volatile FLASH_WORD_SIZE *const flash =
+			(FLASH_WORD_SIZE *) base_address;
+
+		flash[0xAAA << (3 * i)] = 0xaa;
+		flash[0x555 << (3 * i)] = 0x55;
+		flash[0xAAA << (3 * i)] = 0x90;
+		__asm__ __volatile__ ("sync");
+
+		pflinfo->flash_id =
+			flash_id (flash[0x0], flash[0x2 + 14 * i]);
+
+		switch (pflinfo->flash_id & FLASH_TYPEMASK) {
+		case FLASH_AM040:
+			pflinfo->size = 0x00080000;
+			pflinfo->sector_count = 8;
+			for (j = 0; j < 8; j++) {
+				pflinfo->start[j] =
+					base_address + 0x00010000 * j;
+				pflinfo->protect[j] = flash[(j << 16) | 0x2];
+			}
+			break;
+		case FLASH_STM800AB:
+			pflinfo->size = 0x00100000;
+			pflinfo->sector_count = 19;
+			pflinfo->start[0] = base_address;
+			pflinfo->start[1] = base_address + 0x4000;
+			pflinfo->start[2] = base_address + 0x6000;
+			pflinfo->start[3] = base_address + 0x8000;
+			for (j = 1; j < 16; j++) {
+				pflinfo->start[j + 3] =
+					base_address + 0x00010000 * j;
+			}
+			break;
+		default:
+			/* The chip used is not listed in flash_id
+			   TODO: Change this to explicitly detect the flash type
+			 */
+			{
+				int sector_addr = base_address;
+
+				pflinfo->size = 0x00200000;
+				pflinfo->sector_count = 35;
+				pflinfo->start[0] = sector_addr;
+				sector_addr += 0x4000;	/* 16K */
+				pflinfo->start[1] = sector_addr;
+				sector_addr += 0x2000;	/* 8K */
+				pflinfo->start[2] = sector_addr;
+				sector_addr += 0x2000;	/* 8K */
+				pflinfo->start[3] = sector_addr;
+				sector_addr += 0x8000;	/* 32K */
+
+				for (j = 4; j < 35; j++) {
+					pflinfo->start[j] = sector_addr;
+					sector_addr += 0x10000;	/* 64K */
+				}
+			}
+			break;
+		}
+		/* Protect monitor and environment sectors
+		 */
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
+		flash_protect (FLAG_PROTECT_SET,
+			       CONFIG_SYS_MONITOR_BASE,
+			       CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
+			       &flash_info[0]);
+#endif
+
+#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR)
+		flash_protect (FLAG_PROTECT_SET,
+			       CONFIG_ENV_ADDR,
+			       CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1,
+			       &flash_info[0]);
+#endif
+
+		/* reset device to read mode */
+		flash[0x0000] = 0xf0;
+		__asm__ __volatile__ ("sync");
+	}
+
+	/* only have 1 bank */
+	return flash_info[0].size;
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t * info)
+{
+	static const char unk[] = "Unknown";
+	const char *mfct = unk, *type = unk;
+	unsigned int i;
+
+	if (info->flash_id != FLASH_UNKNOWN) {
+		switch (info->flash_id & FLASH_VENDMASK) {
+		case FLASH_MAN_AMD:
+			mfct = "AMD";
+			break;
+		case FLASH_MAN_FUJ:
+			mfct = "FUJITSU";
+			break;
+		case FLASH_MAN_STM:
+			mfct = "STM";
+			break;
+		case FLASH_MAN_SST:
+			mfct = "SST";
+			break;
+		case FLASH_MAN_BM:
+			mfct = "Bright Microelectonics";
+			break;
+		case FLASH_MAN_INTEL:
+			mfct = "Intel";
+			break;
+		}
+
+		switch (info->flash_id & FLASH_TYPEMASK) {
+		case FLASH_AM040:
+			type = "AM29F040B (512K * 8, uniform sector size)";
+			break;
+		case FLASH_AM400B:
+			type = "AM29LV400B (4 Mbit, bottom boot sect)";
+			break;
+		case FLASH_AM400T:
+			type = "AM29LV400T (4 Mbit, top boot sector)";
+			break;
+		case FLASH_AM800B:
+			type = "AM29LV800B (8 Mbit, bottom boot sect)";
+			break;
+		case FLASH_AM800T:
+			type = "AM29LV800T (8 Mbit, top boot sector)";
+			break;
+		case FLASH_AM160T:
+			type = "AM29LV160T (16 Mbit, top boot sector)";
+			break;
+		case FLASH_AM320B:
+			type = "AM29LV320B (32 Mbit, bottom boot sect)";
+			break;
+		case FLASH_AM320T:
+			type = "AM29LV320T (32 Mbit, top boot sector)";
+			break;
+		case FLASH_STM800AB:
+			type = "M29W800AB (8 Mbit, bottom boot sect)";
+			break;
+		case FLASH_SST800A:
+			type = "SST39LF/VF800 (8 Mbit, uniform sector size)";
+			break;
+		case FLASH_SST160A:
+			type = "SST39LF/VF160 (16 Mbit, uniform sector size)";
+			break;
+		}
+	}
+
+	printf ("\n  Brand: %s Type: %s\n"
+		"  Size: %lu KB in %d Sectors\n",
+		mfct, type, info->size >> 10, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+
+	for (i = 0; i < info->sector_count; i++) {
+		unsigned long size;
+		unsigned int erased;
+		unsigned long *flash = (unsigned long *) info->start[i];
+
+		/*
+		 * Check if whole sector is erased
+		 */
+		size = (i != (info->sector_count - 1)) ?
+			(info->start[i + 1] - info->start[i]) >> 2 :
+			(info->start[0] + info->size - info->start[i]) >> 2;
+
+		for (flash = (unsigned long *) info->start[i], erased = 1;
+		     (flash != (unsigned long *) info->start[i] + size)
+		     && erased; flash++)
+			erased = *flash == ~0x0UL;
+
+		printf ("%s %08lX %s %s",
+			(i % 5) ? "" : "\n   ",
+			info->start[i],
+			erased ? "E" : " ", info->protect[i] ? "RO" : "  ");
+	}
+
+	puts ("\n");
+	return;
+}
+
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+	volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *) (info->start[0]);
+	int flag, prot, sect, l_sect;
+	ulong start, now, last;
+	unsigned char sh8b;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	if ((info->flash_id == FLASH_UNKNOWN) ||
+	    (info->flash_id > (FLASH_MAN_STM | FLASH_AMD_COMP))) {
+		printf ("Can't erase unknown flash type - aborted\n");
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n", prot);
+	} else {
+		printf ("\n");
+	}
+
+	l_sect = -1;
+
+	/* Check the ROM CS */
+	if ((info->start[0] >= ROM_CS1_START)
+	    && (info->start[0] < ROM_CS0_START))
+		sh8b = 3;
+	else
+		sh8b = 0;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00AA00AA;
+	addr[ADDR1 << sh8b] = (FLASH_WORD_SIZE) 0x00550055;
+	addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00800080;
+	addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00AA00AA;
+	addr[ADDR1 << sh8b] = (FLASH_WORD_SIZE) 0x00550055;
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			addr = (FLASH_WORD_SIZE *) (info->start[0] +
+						    ((info->start[sect] -
+						      info->start[0]) << sh8b));
+			if (info->flash_id & FLASH_MAN_SST) {
+				addr[ADDR0 << sh8b] =
+					(FLASH_WORD_SIZE) 0x00AA00AA;
+				addr[ADDR1 << sh8b] =
+					(FLASH_WORD_SIZE) 0x00550055;
+				addr[ADDR0 << sh8b] =
+					(FLASH_WORD_SIZE) 0x00800080;
+				addr[ADDR0 << sh8b] =
+					(FLASH_WORD_SIZE) 0x00AA00AA;
+				addr[ADDR1 << sh8b] =
+					(FLASH_WORD_SIZE) 0x00550055;
+				addr[0] = (FLASH_WORD_SIZE) 0x00500050;	/* block erase */
+				udelay (30000);	/* wait 30 ms */
+			} else
+				addr[0] = (FLASH_WORD_SIZE) 0x00300030;	/* sector erase */
+			l_sect = sect;
+		}
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts ();
+
+	/* wait at least 80us - let's wait 1 ms */
+	udelay (1000);
+
+	/*
+	 * We wait for the last triggered sector
+	 */
+	if (l_sect < 0)
+		goto DONE;
+
+	start = get_timer (0);
+	last = start;
+	addr = (FLASH_WORD_SIZE *) (info->start[0] + ((info->start[l_sect] -
+						       info->
+						       start[0]) << sh8b));
+	while ((addr[0] & (FLASH_WORD_SIZE) 0x00800080) !=
+	       (FLASH_WORD_SIZE) 0x00800080) {
+		if ((now = get_timer (start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+			printf ("Timeout\n");
+			return 1;
+		}
+		/* show that we're waiting */
+		if ((now - last) > 1000) {	/* every second */
+			serial_putc ('.');
+			last = now;
+		}
+	}
+
+      DONE:
+	/* reset to read mode */
+	addr = (FLASH_WORD_SIZE *) info->start[0];
+	addr[0] = (FLASH_WORD_SIZE) 0x00F000F0;	/* reset bank */
+
+	printf (" done\n");
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	ulong cp, wp, data;
+	int i, l, rc;
+
+	wp = (addr & ~3);	/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i = 0, cp = wp; i < l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+		for (; i < 4 && cnt > 0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt == 0 && i < 4; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+
+		if ((rc = write_word (info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 4;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 4) {
+		data = 0;
+		for (i = 0; i < 4; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_word (info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 4;
+		cnt -= 4;
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i < 4; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *) cp);
+	}
+
+	return (write_word (info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word (flash_info_t * info, ulong dest, ulong data)
+{
+	volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *) info->start[0];
+	volatile FLASH_WORD_SIZE *dest2;
+	volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *) & data;
+	ulong start;
+	int flag;
+	int i;
+	unsigned char sh8b;
+
+	/* Check the ROM CS */
+	if ((info->start[0] >= ROM_CS1_START)
+	    && (info->start[0] < ROM_CS0_START))
+		sh8b = 3;
+	else
+		sh8b = 0;
+
+	dest2 = (FLASH_WORD_SIZE *) (((dest - info->start[0]) << sh8b) +
+				     info->start[0]);
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*dest2 & (FLASH_WORD_SIZE) data) != (FLASH_WORD_SIZE) data) {
+		return (2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	for (i = 0; i < 4 / sizeof (FLASH_WORD_SIZE); i++) {
+		addr2[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00AA00AA;
+		addr2[ADDR1 << sh8b] = (FLASH_WORD_SIZE) 0x00550055;
+		addr2[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00A000A0;
+
+		dest2[i << sh8b] = data2[i];
+
+		/* re-enable interrupts if necessary */
+		if (flag)
+			enable_interrupts ();
+
+		/* data polling for D7 */
+		start = get_timer (0);
+		while ((dest2[i << sh8b] & (FLASH_WORD_SIZE) 0x00800080) !=
+		       (data2[i] & (FLASH_WORD_SIZE) 0x00800080)) {
+			if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
+				return (1);
+			}
+		}
+	}
+
+	return (0);
+}
diff --git a/u-boot/board/hidden_dragon/hidden_dragon.c b/u-boot/board/hidden_dragon/hidden_dragon.c
new file mode 100644
index 0000000..027aa45
--- /dev/null
+++ b/u-boot/board/hidden_dragon/hidden_dragon.c
@@ -0,0 +1,101 @@
+/*
+ * (C) Copyright 2004
+ * Yusdi Santoso, Adaptec Inc., yusdi_santoso@adaptec.com
+ *
+ * (C) Copyright 2000
+ * Rob Taylor, Flying Pig Systems. robt@flyingpig.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc824x.h>
+#include <pci.h>
+#include <netdev.h>
+
+int checkboard (void)
+{
+	/*TODO: Check processor type */
+
+	puts (	"Board: Hidden Dragon "
+#ifdef CONFIG_MPC8240
+		"8240"
+#endif
+#ifdef CONFIG_MPC8245
+		"8245"
+#endif
+		" ##Test not implemented yet##\n");
+	/* TODO: Implement board test */
+	return 0;
+}
+
+phys_size_t initdram (int board_type)
+{
+	long size;
+	long new_bank0_end;
+	long mear1;
+	long emear1;
+
+	size = get_ram_size(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MAX_RAM_SIZE);
+
+	new_bank0_end = size - 1;
+	mear1 = mpc824x_mpc107_getreg(MEAR1);
+	emear1 = mpc824x_mpc107_getreg(EMEAR1);
+	mear1 = (mear1  & 0xFFFFFF00) |
+		((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT);
+	emear1 = (emear1 & 0xFFFFFF00) |
+		((new_bank0_end & MICR_ADDR_MASK) >> MICR_EADDR_SHIFT);
+	mpc824x_mpc107_setreg(MEAR1, mear1);
+	mpc824x_mpc107_setreg(EMEAR1, emear1);
+
+	return (size);
+}
+
+/*
+ * Initialize PCI Devices, report devices found.
+ */
+#ifndef CONFIG_PCI_PNP
+static struct pci_config_table pci_hidden_dragon_config_table[] = {
+	{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0f, PCI_ANY_ID,
+	  pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
+				       PCI_ENET0_MEMADDR,
+				       PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }},
+	{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x10, PCI_ANY_ID,
+	  pci_cfgfunc_config_device, { PCI_ENET1_IOADDR,
+				       PCI_ENET1_MEMADDR,
+				       PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }},
+	{ }
+};
+#endif
+
+struct pci_controller hose = {
+#ifndef CONFIG_PCI_PNP
+	config_table: pci_hidden_dragon_config_table,
+#endif
+};
+
+void pci_init_board(void)
+{
+	pci_mpc824x_init(&hose);
+}
+
+int board_eth_init(bd_t *bis)
+{
+	return pci_eth_init(bis);
+}
diff --git a/u-boot/board/hidden_dragon/speed.h b/u-boot/board/hidden_dragon/speed.h
new file mode 100644
index 0000000..3f32a14
--- /dev/null
+++ b/u-boot/board/hidden_dragon/speed.h
@@ -0,0 +1,54 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*-----------------------------------------------------------------------
+ * Timer value for timer 2, ICLK = 10
+ *
+ * SPEED_FCOUNT2 =  GCLK / (16 * (TIMER_TMR_PS + 1))
+ * SPEED_TMR3_PS = (GCLK / (16 * SPEED_FCOUNT3)) - 1
+ *
+ * SPEED_FCOUNT2	timer 2 counting frequency
+ * GCLK			CPU clock
+ * SPEED_TMR2_PS	prescaler
+ */
+#define SPEED_TMR2_PS	(250 - 1)	/* divide by 250	*/
+
+/*-----------------------------------------------------------------------
+ * Timer value for PIT
+ *
+ * PIT_TIME = SPEED_PITC / PITRTCLK
+ * PITRTCLK = 8192
+ */
+#define SPEED_PITC	(82 << 16)	/* start counting from 82	*/
+
+/*
+ * The new value for PTA is calculated from
+ *
+ *	PTA = (gclk * Trefresh) / (2 ^ (2 * DFBRG) * PTP * NCS)
+ *
+ * gclk		CPU clock (not bus clock !)
+ * Trefresh	Refresh cycle * 4 (four word bursts used)
+ * DFBRG	For normal mode (no clock reduction) always 0
+ * PTP		Prescaler (already adjusted for no. of banks and 4K / 8K refresh)
+ * NCS		Number of SDRAM banks (chip selects) on this UPM.
+ */