added boot script files to repository

23 files changed, 2077 insertions, 0 deletions

diff --git a/u-boot/board/matrix_vision/common/Makefile b/u-boot/board/matrix_vision/common/Makefile
new file mode 100644
index 0000000..2ad54a0
--- /dev/null
+++ b/u-boot/board/matrix_vision/common/Makefile
@@ -0,0 +1,54 @@
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)board/$(VENDOR)/common)
+endif
+
+LIB	= $(obj)lib$(VENDOR).o
+
+COBJS-y	= mv_common.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/matrix_vision/common/mv_common.c b/u-boot/board/matrix_vision/common/mv_common.c
new file mode 100644
index 0000000..0afc535
--- /dev/null
+++ b/u-boot/board/matrix_vision/common/mv_common.c
@@ -0,0 +1,126 @@
+/*
+ * (C) Copyright 2008
+ * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <environment.h>
+#include <fpga.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static char* entries_to_keep[] = {
+	"serial#", "ethaddr", "eth1addr", "model_info", "sensor_cnt",
+	"fpgadatasize", "ddr_size", "use_dhcp", "use_static_ipaddr",
+	"static_ipaddr", "static_netmask", "static_gateway",
+	"syslog", "watchdog", "netboot", "evo8serialnumber" };
+
+#define MV_MAX_ENV_ENTRY_LENGTH	64
+#define MV_KEEP_ENTRIES		ARRAY_SIZE(entries_to_keep)
+
+void mv_reset_environment(void)
+{
+	int i;
+	char *s[MV_KEEP_ENTRIES];
+	char entries[MV_KEEP_ENTRIES][MV_MAX_ENV_ENTRY_LENGTH];
+
+	printf("\n*** RESET ENVIRONMENT ***\n");
+
+	memset(entries, 0, MV_KEEP_ENTRIES * MV_MAX_ENV_ENTRY_LENGTH);
+	for (i = 0; i < MV_KEEP_ENTRIES; i++) {
+		s[i] = getenv(entries_to_keep[i]);
+		if (s[i]) {
+			printf("save '%s' : %s\n", entries_to_keep[i], s[i]);
+			strncpy(entries[i], s[i], MV_MAX_ENV_ENTRY_LENGTH);
+		}
+	}
+
+	gd->env_valid = 0;
+	env_relocate();
+
+	for (i = 0; i < MV_KEEP_ENTRIES; i++) {
+		if (s[i]) {
+			printf("restore '%s' : %s\n", entries_to_keep[i], s[i]);
+			setenv(entries_to_keep[i], s[i]);
+		}
+	}
+
+	saveenv();
+}
+
+int mv_load_fpga(void)
+{
+	int result;
+	size_t data_size = 0;
+	void *fpga_data = NULL;
+	char *datastr = getenv("fpgadata");
+	char *sizestr = getenv("fpgadatasize");
+
+	if (getenv("skip_fpga")) {
+		printf("found 'skip_fpga' -> FPGA _not_ loaded !\n");
+		return -1;
+	}
+	printf("loading FPGA\n");
+
+	if (datastr)
+		fpga_data = (void *)simple_strtoul(datastr, NULL, 16);
+	if (sizestr)
+		data_size = (size_t)simple_strtoul(sizestr, NULL, 16);
+	if (!data_size) {
+		printf("fpgadatasize invalid -> FPGA _not_ loaded !\n");
+		return -1;
+	}
+
+	result = fpga_load(0, fpga_data, data_size);
+	if (!result)
+		show_boot_progress(0);
+
+	return result;
+}
+
+u8 *dhcp_vendorex_prep(u8 *e)
+{
+	char *ptr;
+
+	/* DHCP vendor-class-identifier = 60 */
+	if ((ptr = getenv("dhcp_vendor-class-identifier"))) {
+		*e++ = 60;
+		*e++ = strlen(ptr);
+		while (*ptr)
+			*e++ = *ptr++;
+	}
+	/* DHCP_CLIENT_IDENTIFIER = 61 */
+	if ((ptr = getenv("dhcp_client_id"))) {
+		*e++ = 61;
+		*e++ = strlen(ptr);
+		while (*ptr)
+			*e++ = *ptr++;
+	}
+
+	return e;
+}
+
+u8 *dhcp_vendorex_proc(u8 *popt)
+{
+	return NULL;
+}
diff --git a/u-boot/board/matrix_vision/common/mv_common.h b/u-boot/board/matrix_vision/common/mv_common.h
new file mode 100644
index 0000000..046c038
--- /dev/null
+++ b/u-boot/board/matrix_vision/common/mv_common.h
@@ -0,0 +1,25 @@
+/*
+ * Copyright 2008 Matrix Vision GmbH
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+extern int mv_load_fpga(void);
+extern void mv_reset_environment(void);
diff --git a/u-boot/board/matrix_vision/mvbc_p/Makefile b/u-boot/board/matrix_vision/mvbc_p/Makefile
new file mode 100644
index 0000000..9ee0895
--- /dev/null
+++ b/u-boot/board/matrix_vision/mvbc_p/Makefile
@@ -0,0 +1,50 @@
+#
+# (C) Copyright 2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2004-2008
+# Matrix-Vision GmbH, info@matrix-vision.de
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= $(BOARD).o fpga.o
+
+SRCS    := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS    := $(addprefix $(obj),$(COBJS))
+SOBJS   := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+	        $(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
diff --git a/u-boot/board/matrix_vision/mvbc_p/fpga.c b/u-boot/board/matrix_vision/mvbc_p/fpga.c
new file mode 100644
index 0000000..3ed46fe
--- /dev/null
+++ b/u-boot/board/matrix_vision/mvbc_p/fpga.c
@@ -0,0 +1,174 @@
+/*
+ * (C) Copyright 2002
+ * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
+ * Keith Outwater, keith_outwater@mvis.com.
+ *
+ * (C) Copyright 2008
+ * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <ACEX1K.h>
+#include <command.h>
+#include "fpga.h"
+#include "mvbc_p.h"
+
+#ifdef FPGA_DEBUG
+#define fpga_debug(fmt, args...)	printf("%s: "fmt, __func__, ##args)
+#else
+#define fpga_debug(fmt, args...)
+#endif
+
+Altera_CYC2_Passive_Serial_fns altera_fns = {
+	fpga_null_fn,
+	fpga_config_fn,
+	fpga_status_fn,
+	fpga_done_fn,
+	fpga_wr_fn,
+	fpga_null_fn,
+	fpga_null_fn,
+};
+
+Altera_desc cyclone2 = {
+	Altera_CYC2,
+	passive_serial,
+	Altera_EP2C8_SIZE,
+	(void *) &altera_fns,
+	NULL,
+};
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int mvbc_p_init_fpga(void)
+{
+	fpga_debug("Initialize FPGA interface\n");
+	fpga_init();
+	fpga_add(fpga_altera, &cyclone2);
+	fpga_config_fn(0, 1, 0);
+	udelay(60);
+
+	return 1;
+}
+
+int fpga_null_fn(int cookie)
+{
+	return 0;
+}
+
+int fpga_config_fn(int assert, int flush, int cookie)
+{
+	struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio*)MPC5XXX_GPIO;
+	u32 dvo = gpio->simple_dvo;
+
+	fpga_debug("SET config : %s\n", assert ? "low" : "high");
+	if (assert)
+		dvo |= FPGA_CONFIG;
+	else
+		dvo &= ~FPGA_CONFIG;
+
+	if (flush)
+		gpio->simple_dvo = dvo;
+
+	return assert;
+}
+
+int fpga_done_fn(int cookie)
+{
+	struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio*)MPC5XXX_GPIO;
+	int result = 0;
+
+	udelay(10);
+	fpga_debug("CONF_DONE check ... ");
+	if (gpio->simple_ival & FPGA_CONF_DONE) {
+		fpga_debug("high\n");
+		result = 1;
+	} else
+		fpga_debug("low\n");
+
+	return result;
+}
+
+int fpga_status_fn(int cookie)
+{
+	struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio*)MPC5XXX_GPIO;
+	int result = 0;
+
+	fpga_debug("STATUS check ... ");
+	if (gpio->sint_ival & FPGA_STATUS) {
+		fpga_debug("high\n");
+		result = 1;
+	} else
+		fpga_debug("low\n");
+
+	return result;
+}
+
+int fpga_clk_fn(int assert_clk, int flush, int cookie)
+{
+	struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio*)MPC5XXX_GPIO;
+	u32 dvo = gpio->simple_dvo;
+
+	fpga_debug("CLOCK %s\n", assert_clk ? "high" : "low");
+	if (assert_clk)
+		dvo |= FPGA_CCLK;
+	else
+		dvo &= ~FPGA_CCLK;
+
+	if (flush)
+		gpio->simple_dvo = dvo;
+
+	return assert_clk;
+}
+
+static inline int _write_fpga(u8 val)
+{
+	int i;
+	struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio*)MPC5XXX_GPIO;
+	u32 dvo = gpio->simple_dvo;
+
+	for (i=0; i<8; i++) {
+		dvo &= ~FPGA_CCLK;
+		gpio->simple_dvo = dvo;
+		dvo &= ~FPGA_DIN;
+		if (val & 1)
+			dvo |= FPGA_DIN;
+		gpio->simple_dvo = dvo;
+		dvo |= FPGA_CCLK;
+		gpio->simple_dvo = dvo;
+		val >>= 1;
+	}
+
+	return 0;
+}
+
+int fpga_wr_fn(void *buf, size_t len, int flush, int cookie)
+{
+	unsigned char *data = (unsigned char *) buf;
+	int i;
+
+	fpga_debug("fpga_wr: buf %p / size %d\n", buf, len);
+	for (i = 0; i < len; i++)
+		_write_fpga(data[i]);
+	fpga_debug("\n");
+
+	return FPGA_SUCCESS;
+}
diff --git a/u-boot/board/matrix_vision/mvbc_p/fpga.h b/u-boot/board/matrix_vision/mvbc_p/fpga.h
new file mode 100644
index 0000000..3723073
--- /dev/null
+++ b/u-boot/board/matrix_vision/mvbc_p/fpga.h
@@ -0,0 +1,34 @@
+/*
+ * (C) Copyright 2002
+ * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
+ * Keith Outwater, keith_outwater@mvis.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+extern int mvbc_p_init_fpga(void);
+
+extern int fpga_pgm_fn(int assert_pgm, int flush, int cookie);
+extern int fpga_status_fn(int cookie);
+extern int fpga_config_fn(int assert, int flush, int cookie);
+extern int fpga_done_fn(int cookie);
+extern int fpga_clk_fn(int assert_clk, int flush, int cookie);
+extern int fpga_wr_fn(void *buf, size_t len, int flush, int cookie);
+extern int fpga_null_fn(int cookie);
diff --git a/u-boot/board/matrix_vision/mvbc_p/mvbc_p.c b/u-boot/board/matrix_vision/mvbc_p/mvbc_p.c
new file mode 100644
index 0000000..4392176
--- /dev/null
+++ b/u-boot/board/matrix_vision/mvbc_p/mvbc_p.c
@@ -0,0 +1,271 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * (C) Copyright 2005-2007
+ * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc5xxx.h>
+#include <malloc.h>
+#include <pci.h>
+#include <i2c.h>
+#include <fpga.h>
+#include <environment.h>
+#include <fdt_support.h>
+#include <netdev.h>
+#include <asm/io.h>
+#include "fpga.h"
+#include "mvbc_p.h"
+#include "../common/mv_common.h"
+
+#define SDRAM_MODE	0x00CD0000
+#define SDRAM_CONTROL	0x504F0000
+#define SDRAM_CONFIG1	0xD2322800
+#define SDRAM_CONFIG2	0x8AD70000
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void sdram_start (int hi_addr)
+{
+	long hi_bit = hi_addr ? 0x01000000 : 0;
+
+	/* unlock mode register */
+	out_be32((u32*)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | 0x80000000 | hi_bit);
+
+	/* precharge all banks */
+	out_be32((u32*)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | 0x80000002 | hi_bit);
+
+	/* precharge all banks */
+	out_be32((u32*)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | 0x80000002 | hi_bit);
+
+	/* auto refresh */
+	out_be32((u32*)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | 0x80000004 | hi_bit);
+
+	/* set mode register */
+	out_be32((u32*)MPC5XXX_SDRAM_MODE, SDRAM_MODE);
+
+	/* normal operation */
+	out_be32((u32*)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | hi_bit);
+}
+
+phys_addr_t initdram (int board_type)
+{
+	ulong dramsize = 0;
+	ulong test1,
+	      test2;
+
+	/* setup SDRAM chip selects */
+	out_be32((u32*)MPC5XXX_SDRAM_CS0CFG, 0x0000001e);
+
+	/* setup config registers */
+	out_be32((u32*)MPC5XXX_SDRAM_CONFIG1, SDRAM_CONFIG1);
+	out_be32((u32*)MPC5XXX_SDRAM_CONFIG2, SDRAM_CONFIG2);
+
+	/* find RAM size using SDRAM CS0 only */
+	sdram_start(0);
+	test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
+	sdram_start(1);
+	test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
+	if (test1 > test2) {
+		sdram_start(0);
+		dramsize = test1;
+	} else
+		dramsize = test2;
+
+	if (dramsize < (1 << 20))
+		dramsize = 0;
+
+	if (dramsize > 0)
+		out_be32((u32*)MPC5XXX_SDRAM_CS0CFG, 0x13 +
+			__builtin_ffs(dramsize >> 20) - 1);
+	else
+		out_be32((u32*)MPC5XXX_SDRAM_CS0CFG, 0);
+
+	return dramsize;
+}
+
+void mvbc_init_gpio(void)
+{
+	struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio*)MPC5XXX_GPIO;
+
+	printf("Ports : 0x%08x\n", gpio->port_config);
+	printf("PORCFG: 0x%08lx\n", *(vu_long*)MPC5XXX_CDM_PORCFG);
+
+	out_be32(&gpio->simple_ddr, SIMPLE_DDR);
+	out_be32(&gpio->simple_dvo, SIMPLE_DVO);
+	out_be32(&gpio->simple_ode, SIMPLE_ODE);
+	out_be32(&gpio->simple_gpioe, SIMPLE_GPIOEN);
+
+	out_8(&gpio->sint_ode, SINT_ODE);
+	out_8(&gpio->sint_ddr, SINT_DDR);
+	out_8(&gpio->sint_dvo, SINT_DVO);
+	out_8(&gpio->sint_inten, SINT_INTEN);
+	out_be16(&gpio->sint_itype, SINT_ITYPE);
+	out_8(&gpio->sint_gpioe, SINT_GPIOEN);
+
+	out_8((u8*)MPC5XXX_WU_GPIO_ODE, WKUP_ODE);
+	out_8((u8*)MPC5XXX_WU_GPIO_DIR, WKUP_DIR);
+	out_8((u8*)MPC5XXX_WU_GPIO_DATA_O, WKUP_DO);
+	out_8((u8*)MPC5XXX_WU_GPIO_ENABLE, WKUP_EN);
+
+	printf("simple_gpioe: 0x%08x\n", gpio->simple_gpioe);
+	printf("sint_gpioe  : 0x%08x\n", gpio->sint_gpioe);
+}
+
+int misc_init_r(void)
+{
+	char *s = getenv("reset_env");
+
+	if (!s) {
+		if (in_8((u8*)MPC5XXX_WU_GPIO_DATA_I) & MPC5XXX_GPIO_WKUP_6)
+			return 0;
+		udelay(50000);
+		if (in_8((u8*)MPC5XXX_WU_GPIO_DATA_I) & MPC5XXX_GPIO_WKUP_6)
+			return 0;
+		udelay(50000);
+		if (in_8((u8*)MPC5XXX_WU_GPIO_DATA_I) & MPC5XXX_GPIO_WKUP_6)
+			return 0;
+	}
+	printf(" === FACTORY RESET ===\n");
+	mv_reset_environment();
+	saveenv();
+
+	return -1;
+}
+
+int checkboard(void)
+{
+	mvbc_init_gpio();
+	printf("Board: Matrix Vision mvBlueCOUGAR-P\n");
+
+	return 0;
+}
+
+void flash_preinit(void)
+{
+	/*
+	 * Now, when we are in RAM, enable flash write
+	 * access for detection process.
+	 * Note that CS_BOOT cannot be cleared when
+	 * executing in flash.
+	 */
+	clrbits_be32((u32*)MPC5XXX_BOOTCS_CFG, 0x1);
+}
+
+void flash_afterinit(ulong size)
+{
+	out_be32((u32*)MPC5XXX_BOOTCS_START, START_REG(CONFIG_SYS_BOOTCS_START |
+		size));
+	out_be32((u32*)MPC5XXX_CS0_START, START_REG(CONFIG_SYS_BOOTCS_START |
+		size));
+	out_be32((u32*)MPC5XXX_BOOTCS_STOP, STOP_REG(CONFIG_SYS_BOOTCS_START | size,
+		size));
+	out_be32((u32*)MPC5XXX_CS0_STOP, STOP_REG(CONFIG_SYS_BOOTCS_START | size,
+		size));
+}
+
+void pci_mvbc_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
+{
+	unsigned char line = 0xff;
+	char *s = getenv("pci_latency");
+	u32 base;
+	u8 val = 0;
+
+	if (s)
+		val = simple_strtoul(s, NULL, 16);
+
+	if (PCI_BUS(dev) == 0) {
+		switch (PCI_DEV (dev)) {
+		case 0xa: /* FPGA */
+			line = 3;
+			pci_hose_read_config_dword(hose, dev, PCI_BASE_ADDRESS_0, &base);
+			printf("found FPGA - enable arbitration\n");
+			writel(0x03, (u32*)(base + 0x80c0));
+			writel(0xf0, (u32*)(base + 0x8080));
+			if (val)
+				pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, val);
+			break;
+		case 0xb: /* LAN */
+			line = 2;
+			if (val)
+				pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, val);
+			break;
+		case 0x1a:
+			break;
+		default:
+			printf ("***pci_scan: illegal dev = 0x%08x\n", PCI_DEV (dev));
+			break;
+		}
+		pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, line);
+	}
+}
+
+struct pci_controller hose = {
+	fixup_irq:pci_mvbc_fixup_irq
+};
+
+extern void pci_mpc5xxx_init(struct pci_controller *);
+
+void pci_init_board(void)
+{
+	mvbc_p_init_fpga();
+	mv_load_fpga();
+	pci_mpc5xxx_init(&hose);
+}
+
+void show_boot_progress(int val)
+{
+	struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio*)MPC5XXX_GPIO;
+
+	switch(val) {
+	case 0: /* FPGA ok */
+		setbits_be32(&gpio->simple_dvo, LED_G0);
+		break;
+	case 65:
+		setbits_be32(&gpio->simple_dvo, LED_G1);
+		break;
+	case 12:
+		setbits_be32(&gpio->simple_dvo, LED_Y);
+		break;
+	case 15:
+		setbits_be32(&gpio->simple_dvo, LED_R);
+		break;
+	default:
+		break;
+	}
+
+}
+
+void ft_board_setup(void *blob, bd_t *bd)
+{
+	ft_cpu_setup(blob, bd);
+}
+
+int board_eth_init(bd_t *bis)
+{
+	cpu_eth_init(bis); /* Built in FEC comes first */
+	return pci_eth_init(bis);
+}
diff --git a/u-boot/board/matrix_vision/mvbc_p/mvbc_p.h b/u-boot/board/matrix_vision/mvbc_p/mvbc_p.h
new file mode 100644
index 0000000..be1542b
--- /dev/null
+++ b/u-boot/board/matrix_vision/mvbc_p/mvbc_p.h
@@ -0,0 +1,43 @@
+#ifndef __MVBC_H__
+#define __MVBC_H__
+
+#define LED_G0          MPC5XXX_GPIO_SIMPLE_PSC2_0
+#define LED_G1          MPC5XXX_GPIO_SIMPLE_PSC2_1
+#define LED_Y           MPC5XXX_GPIO_SIMPLE_PSC2_2
+#define LED_R           MPC5XXX_GPIO_SIMPLE_PSC2_3
+#define ARB_X_EN        MPC5XXX_GPIO_WKUP_PSC2_4
+
+#define FPGA_DIN        MPC5XXX_GPIO_SIMPLE_PSC3_0
+#define FPGA_CCLK       MPC5XXX_GPIO_SIMPLE_PSC3_1
+#define FPGA_CONF_DONE  MPC5XXX_GPIO_SIMPLE_PSC3_2
+#define FPGA_CONFIG     MPC5XXX_GPIO_SIMPLE_PSC3_3
+#define FPGA_STATUS     MPC5XXX_GPIO_SINT_PSC3_4
+
+#define MAN_RST         MPC5XXX_GPIO_WKUP_PSC6_0
+#define WD_TS           MPC5XXX_GPIO_WKUP_PSC6_1
+#define WD_WDI          MPC5XXX_GPIO_SIMPLE_PSC6_2
+#define COP_PRESENT     MPC5XXX_GPIO_SIMPLE_PSC6_3
+#define FACT_RST        MPC5XXX_GPIO_WKUP_6
+#define FLASH_RBY       MPC5XXX_GPIO_WKUP_7
+
+#define SIMPLE_DDR      (LED_G0 | LED_G1 | LED_Y | LED_R | \
+			 FPGA_DIN | FPGA_CCLK | FPGA_CONFIG | WD_WDI)
+#define SIMPLE_DVO      (FPGA_CONFIG)
+#define SIMPLE_ODE      (FPGA_CONFIG | LED_G0 | LED_G1 | LED_Y | LED_R)
+#define SIMPLE_GPIOEN   (LED_G0 | LED_G1 | LED_Y | LED_R | \
+			 FPGA_DIN | FPGA_CCLK | FPGA_CONF_DONE | FPGA_CONFIG |\
+			 WD_WDI | COP_PRESENT)
+
+#define SINT_ODE        0
+#define SINT_DDR        0
+#define SINT_DVO        0
+#define SINT_INTEN      0
+#define SINT_ITYPE      0
+#define SINT_GPIOEN     (FPGA_STATUS)
+
+#define WKUP_ODE        (MAN_RST)
+#define WKUP_DIR        (ARB_X_EN|MAN_RST|WD_TS)
+#define WKUP_DO         (ARB_X_EN|MAN_RST|WD_TS)
+#define WKUP_EN         (ARB_X_EN|MAN_RST|WD_TS|FACT_RST|FLASH_RBY)
+
+#endif
diff --git a/u-boot/board/matrix_vision/mvbc_p/mvbc_p_autoscript b/u-boot/board/matrix_vision/mvbc_p/mvbc_p_autoscript
new file mode 100644
index 0000000..9b21f30
--- /dev/null
+++ b/u-boot/board/matrix_vision/mvbc_p/mvbc_p_autoscript
@@ -0,0 +1,48 @@
+echo
+echo "==== running autoscript ===="
+echo
+setenv bootdtb bootm \${kernel_boot} \${mv_initrd_addr_ram} \${mv_dtb_addr_ram}
+setenv ramkernel setenv kernel_boot \${loadaddr}
+setenv flashkernel setenv kernel_boot \${mv_kernel_addr}
+setenv cpird cp \${mv_initrd_addr} \${mv_initrd_addr_ram} \${mv_initrd_length}
+setenv bootfromflash run flashkernel cpird ramparam addcons e1000para addprofile bootdtb
+setenv getdtb tftp \${mv_dtb_addr_ram} \${dtb_name}
+setenv cpdtb cp \${mv_dtb_addr} \${mv_dtb_addr_ram} 0x2000
+setenv rundtb fdt addr \${mv_dtb_addr_ram}\;fdt boardsetup
+setenv bootfromnet tftp \${mv_initrd_addr_ram} \${initrd_name}\;run ramkernel
+if test ${console} = yes;
+then
+setenv addcons setenv bootargs \${bootargs} console=ttyPSC\${console_nr},\${baudrate}N8
+else
+setenv addcons setenv bootargs \${bootargs} console=tty0
+fi
+setenv e1000para setenv bootargs \${bootargs} e1000.TxDescriptors=256 e1000.SmartPowerDownEnable=1
+setenv set_static_ip setenv ipaddr \${static_ipaddr}
+setenv set_static_nm setenv netmask \${static_netmask}
+setenv set_static_gw setenv gatewayip \${static_gateway}
+setenv set_ip setenv ip \${ipaddr}::\${gatewayip}:\${netmask}
+setenv ramparam setenv bootargs root=/dev/ram0 ro rootfstype=squashfs
+if test ${oprofile} = yes;
+then
+setenv addprofile setenv bootargs \${bootargs} profile=\${profile}
+fi
+if test ${autoscript_boot} != no;
+then
+  if test ${netboot} = yes;
+  then
+    bootp
+    if test $? = 0;
+    then
+      echo "=== bootp succeeded -> netboot ==="
+      run set_ip
+      run getdtb rundtb bootfromnet ramparam addcons e1000para addprofile bootdtb
+    else
+      echo "=== netboot failed ==="
+    fi
+  fi
+  run set_static_ip set_static_nm set_static_gw set_ip
+  echo "=== bootfromflash ==="
+  run cpdtb rundtb bootfromflash
+else
+  echo "=== boot stopped with autoscript_boot no ==="
+fi
diff --git a/u-boot/board/matrix_vision/mvblm7/Makefile b/u-boot/board/matrix_vision/mvblm7/Makefile
new file mode 100644
index 0000000..2ee74e0
--- /dev/null
+++ b/u-boot/board/matrix_vision/mvblm7/Makefile
@@ -0,0 +1,49 @@
+#
+# Copyright (C) Freescale Semiconductor, Inc. 2006.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= $(BOARD).o pci.o fpga.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+	@mkimage -T script -C none -n M7_script -d bootscript $(obj)bootscript.img
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend $(obj)bootscript.img
+
+#########################################################################
+
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/matrix_vision/mvblm7/bootscript b/u-boot/board/matrix_vision/mvblm7/bootscript
new file mode 100644
index 0000000..dc385fd
--- /dev/null
+++ b/u-boot/board/matrix_vision/mvblm7/bootscript
@@ -0,0 +1,43 @@
+echo
+echo "==== running autoscript ===="
+echo
+setenv bootdtb bootm \${kernel_boot} \${mv_initrd_addr_ram} \${mv_dtb_addr_ram}
+setenv ramkernel setenv kernel_boot \${loadaddr}
+setenv flashkernel setenv kernel_boot \${mv_kernel_addr}
+setenv cpird cp \${mv_initrd_addr} \${mv_initrd_addr_ram} \${mv_initrd_length}
+setenv bootfromflash run flashkernel cpird ramparam addcons bootdtb
+setenv getdtb tftp \${mv_dtb_addr_ram} \${dtb_name}
+setenv cpdtb cp \${mv_dtb_addr} \${mv_dtb_addr_ram} 0x2000
+setenv rundtb fdt addr \${mv_dtb_addr_ram}\;fdt boardsetup
+setenv bootfromnet tftp \${mv_initrd_addr_ram} \${initrd_name}\;run ramkernel
+if test ${console} = yes;
+then
+setenv addcons setenv bootargs \${bootargs} console=ttyS\${console_nr},\${baudrate}N8
+else
+setenv addcons setenv bootargs \${bootargs} console=tty0
+fi
+setenv set_static_ip setenv ipaddr \${static_ipaddr}
+setenv set_static_nm setenv netmask \${static_netmask}
+setenv set_static_gw setenv gatewayip \${static_gateway}
+setenv set_ip setenv ip \${ipaddr}::\${gatewayip}:\${netmask}
+setenv ramparam setenv bootargs root=/dev/ram0 ro rootfstype=squashfs
+if test ${autoscript_boot} != no;
+then
+  if test ${netboot} = yes;
+  then
+    bootp
+    if test $? = 0;
+    then
+      echo "=== bootp succeeded -> netboot ==="
+      run set_ip
+      run getdtb rundtb bootfromnet ramparam addcons bootdtb
+    else
+      echo "=== netboot failed ==="
+    fi
+  fi
+  run set_static_ip set_static_nm set_static_gw set_ip
+  echo "=== bootfromflash ==="
+  run cpdtb rundtb bootfromflash
+else
+  echo "=== boot stopped with autoscript_boot no ==="
+fi
diff --git a/u-boot/board/matrix_vision/mvblm7/fpga.c b/u-boot/board/matrix_vision/mvblm7/fpga.c
new file mode 100644
index 0000000..7b03d6f
--- /dev/null
+++ b/u-boot/board/matrix_vision/mvblm7/fpga.c
@@ -0,0 +1,186 @@
+/*
+ * (C) Copyright 2002
+ * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
+ * Keith Outwater, keith_outwater@mvis.com.
+ *
+ * (C) Copyright 2008
+ * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <ACEX1K.h>
+#include <command.h>
+#include "fpga.h"
+#include "mvblm7.h"
+
+#ifdef FPGA_DEBUG
+#define fpga_debug(fmt, args...)      printf("%s: "fmt, __func__, ##args)
+#else
+#define fpga_debug(fmt, args...)
+#endif
+
+Altera_CYC2_Passive_Serial_fns altera_fns = {
+	fpga_null_fn,
+	fpga_config_fn,
+	fpga_status_fn,
+	fpga_done_fn,
+	fpga_wr_fn,
+	fpga_null_fn,
+	fpga_null_fn,
+};
+
+Altera_desc cyclone2 = {
+	Altera_CYC2,
+	passive_serial,
+	Altera_EP2C20_SIZE,
+	(void *) &altera_fns,
+	NULL,
+	0
+};
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int mvblm7_init_fpga(void)
+{
+	fpga_debug("Initialize FPGA interface\n");
+	fpga_init();
+	fpga_add(fpga_altera, &cyclone2);
+	fpga_config_fn(0, 1, 0);
+	udelay(60);
+
+	return 1;
+}
+
+int fpga_null_fn(int cookie)
+{
+	return 0;
+}
+
+int fpga_config_fn(int assert, int flush, int cookie)
+{
+	volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
+	volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)&im->gpio[0];
+	u32 dvo = gpio->dat;
+
+	fpga_debug("SET config : %s\n", assert ? "low" : "high");
+	if (assert)
+		dvo |= FPGA_CONFIG;
+	else
+		dvo &= ~FPGA_CONFIG;
+
+	if (flush)
+		gpio->dat = dvo;
+
+	return assert;
+}
+
+int fpga_done_fn(int cookie)
+{
+	volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
+	volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)&im->gpio[0];
+	int result = 0;
+
+	udelay(10);
+	fpga_debug("CONF_DONE check ... ");
+	if (gpio->dat & FPGA_CONF_DONE)  {
+		fpga_debug("high\n");
+		result = 1;
+	} else
+		fpga_debug("low\n");
+
+	return result;
+}
+
+int fpga_status_fn(int cookie)
+{
+	volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
+	volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)&im->gpio[0];
+	int result = 0;
+
+	fpga_debug("STATUS check ... ");
+	if (gpio->dat & FPGA_STATUS)  {
+		fpga_debug("high\n");
+		result = 1;
+	} else
+		fpga_debug("low\n");
+
+	return result;
+}
+
+int fpga_clk_fn(int assert_clk, int flush, int cookie)
+{
+	volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
+	volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)&im->gpio[0];
+	u32 dvo = gpio->dat;
+
+	fpga_debug("CLOCK %s\n", assert_clk ? "high" : "low");
+	if (assert_clk)
+		dvo |= FPGA_CCLK;
+	else
+		dvo &= ~FPGA_CCLK;
+
+	if (flush)
+		gpio->dat = dvo;
+
+	return assert_clk;
+}
+
+static inline int _write_fpga(u8 val, int dump)
+{
+	volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
+	volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)&im->gpio[0];
+	int i;
+	u32 dvo = gpio->dat;
+
+	if (dump)
+		fpga_debug("  %02x -> ", val);
+	for (i = 0; i < 8; i++) {
+		dvo &= ~FPGA_CCLK;
+		gpio->dat = dvo;
+		dvo &= ~FPGA_DIN;
+		if (dump)
+			fpga_debug("%d ", val&1);
+		if (val & 1)
+			dvo |= FPGA_DIN;
+		gpio->dat = dvo;
+		dvo |= FPGA_CCLK;
+		gpio->dat = dvo;
+		val >>= 1;
+	}
+	if (dump)
+		fpga_debug("\n");
+
+	return 0;
+}
+
+int fpga_wr_fn(void *buf, size_t len, int flush, int cookie)
+{
+	unsigned char *data = (unsigned char *) buf;
+	int i;
+
+	fpga_debug("fpga_wr: buf %p / size %d\n", buf, len);
+	for (i = 0; i < len; i++)
+		_write_fpga(data[i], 0);
+	fpga_debug("\n");
+
+	return FPGA_SUCCESS;
+}
diff --git a/u-boot/board/matrix_vision/mvblm7/fpga.h b/u-boot/board/matrix_vision/mvblm7/fpga.h
new file mode 100644
index 0000000..19277eb
--- /dev/null
+++ b/u-boot/board/matrix_vision/mvblm7/fpga.h
@@ -0,0 +1,34 @@
+/*
+ * (C) Copyright 2002
+ * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
+ * Keith Outwater, keith_outwater@mvis.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+extern int mvblm7_init_fpga(void);
+
+extern int fpga_pgm_fn(int assert_pgm, int flush, int cookie);
+extern int fpga_status_fn(int cookie);
+extern int fpga_config_fn(int assert, int flush, int cookie);
+extern int fpga_done_fn(int cookie);
+extern int fpga_clk_fn(int assert_clk, int flush, int cookie);
+extern int fpga_wr_fn(void *buf, size_t len, int flush, int cookie);
+extern int fpga_null_fn(int cookie);
diff --git a/u-boot/board/matrix_vision/mvblm7/mvblm7.c b/u-boot/board/matrix_vision/mvblm7/mvblm7.c
new file mode 100644
index 0000000..6a4ed52
--- /dev/null
+++ b/u-boot/board/matrix_vision/mvblm7/mvblm7.c
@@ -0,0 +1,152 @@
+/*
+ * Copyright (C) Freescale Semiconductor, Inc. 2006.
+ *
+ * (C) Copyright 2008
+ * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <ioports.h>
+#include <mpc83xx.h>
+#include <asm/mpc8349_pci.h>
+#include <pci.h>
+#include <spi.h>
+#include <asm/mmu.h>
+#if defined(CONFIG_OF_LIBFDT)
+#include <libfdt.h>
+#endif
+
+#include "../common/mv_common.h"
+#include "mvblm7.h"
+
+int fixed_sdram(void)
+{
+	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
+	u32 msize = 0;
+	u32 ddr_size;
+	u32 ddr_size_log2;
+	char *s = getenv("ddr_size");
+
+	msize = CONFIG_SYS_DDR_SIZE;
+	if (s) {
+		u32 env_ddr_size = simple_strtoul(s, NULL, 10);
+		if (env_ddr_size == 512)
+			msize = 512;
+	}
+
+	for (ddr_size = msize << 20, ddr_size_log2 = 0;
+	     (ddr_size > 1);
+	     ddr_size = ddr_size >> 1, ddr_size_log2++) {
+		if (ddr_size & 1)
+			return -1;
+	}
+	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
+	im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) &
+		LAWAR_SIZE);
+
+	im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS;
+	im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
+	im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
+	im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
+	im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
+	im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
+	im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
+	im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
+	im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
+	im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
+	im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
+	im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL;
+
+	asm("sync;isync");
+	udelay(600);
+
+	im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
+
+	asm("sync;isync");
+	udelay(500);
+
+	return msize;
+}
+
+phys_size_t initdram(int board_type)
+{
+	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
+	u32 msize = 0;
+
+	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
+		return -1;
+
+	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
+	msize = fixed_sdram();
+
+	/* return total bus RAM size(bytes) */
+	return msize * 1024 * 1024;
+}
+
+int misc_init_r(void)
+{
+	char *s = getenv("reset_env");
+
+	if (s) {
+		mv_reset_environment();
+	}
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	puts("Board: Matrix Vision mvBlueLYNX-M7\n");
+
+	return 0;
+}
+
+#ifdef CONFIG_HARD_SPI
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+	return bus == 0 && cs == 0;
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+	volatile gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0];
+
+	iopd->dat &= ~MVBLM7_MMC_CS;
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+	volatile gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0];
+
+	iopd->dat |= ~MVBLM7_MMC_CS;
+}
+#endif
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+void ft_board_setup(void *blob, bd_t *bd)
+{
+	ft_cpu_setup(blob, bd);
+#ifdef CONFIG_PCI
+	ft_pci_setup(blob, bd);
+#endif
+}
+
+#endif
diff --git a/u-boot/board/matrix_vision/mvblm7/mvblm7.h b/u-boot/board/matrix_vision/mvblm7/mvblm7.h
new file mode 100644
index 0000000..de9fec7
--- /dev/null
+++ b/u-boot/board/matrix_vision/mvblm7/mvblm7.h
@@ -0,0 +1,20 @@
+#ifndef __MVBC_H__
+#define __MVBC_H__
+
+#define MV_GPIO
+
+#define FPGA_CONFIG     0x80000000
+#define FPGA_CCLK       0x40000000
+#define FPGA_DIN        0x20000000
+#define FPGA_STATUS     0x10000000
+#define FPGA_CONF_DONE  0x08000000
+
+#define WD_WDI          0x00400000
+#define WD_TS           0x00200000
+#define MAN_RST         0x00100000
+
+#define MV_GPIO_DAT	(WD_TS)
+#define MV_GPIO_OUT	(FPGA_CONFIG|FPGA_DIN|FPGA_CCLK|MVBLM7_MMC_CS)
+#define MV_GPIO_ODE	(FPGA_CONFIG|MAN_RST)
+
+#endif
diff --git a/u-boot/board/matrix_vision/mvblm7/pci.c b/u-boot/board/matrix_vision/mvblm7/pci.c
new file mode 100644
index 0000000..921e80b
--- /dev/null
+++ b/u-boot/board/matrix_vision/mvblm7/pci.c
@@ -0,0 +1,105 @@
+/*
+ * Copyright (C) Freescale Semiconductor, Inc. 2006.
+ *
+ * (C) Copyright 2008
+ * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#if defined(CONFIG_OF_LIBFDT)
+#include <libfdt.h>
+#endif
+#include <pci.h>
+#include <mpc83xx.h>
+#include <fpga.h>
+#include "mvblm7.h"
+#include "fpga.h"
+#include "../common/mv_common.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct pci_region pci_regions[] = {
+	{
+		bus_start: CONFIG_SYS_PCI1_MEM_BASE,
+		phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
+		size: CONFIG_SYS_PCI1_MEM_SIZE,
+		flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
+	},
+	{
+		bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
+		phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
+		size: CONFIG_SYS_PCI1_MMIO_SIZE,
+		flags: PCI_REGION_MEM
+	},
+	{
+		bus_start: CONFIG_SYS_PCI1_IO_BASE,
+		phys_start: CONFIG_SYS_PCI1_IO_PHYS,
+		size: CONFIG_SYS_PCI1_IO_SIZE,
+		flags: PCI_REGION_IO
+	}
+};
+
+void pci_init_board(void)
+{
+	int i;
+	volatile immap_t *immr;
+	volatile pcictrl83xx_t *pci_ctrl;
+	volatile gpio83xx_t *gpio;
+	volatile clk83xx_t *clk;
+	volatile law83xx_t *pci_law;
+	struct pci_region *reg[] = { pci_regions };
+
+	immr = (immap_t *) CONFIG_SYS_IMMR;
+	clk = (clk83xx_t *) &immr->clk;
+	pci_ctrl = immr->pci_ctrl;
+	pci_law = immr->sysconf.pcilaw;
+	gpio  = (volatile gpio83xx_t *)&immr->gpio[0];
+
+	gpio->dat = MV_GPIO_DAT;
+	gpio->odr = MV_GPIO_ODE;
+	gpio->dir = MV_GPIO_OUT;
+
+	printf("SICRH / SICRL : 0x%08x / 0x%08x\n", immr->sysconf.sicrh,
+		immr->sysconf.sicrl);
+
+	mvblm7_init_fpga();
+	mv_load_fpga();
+
+	gpio->dir = MV_GPIO_OUT & ~(FPGA_DIN|FPGA_CCLK);
+
+	/* Enable PCI_CLK_OUTPUTs 0 and 1 with 1:1 clocking */
+	clk->occr = 0xc0000000;
+
+	pci_ctrl[0].gcr = 0;
+	udelay(2000);
+	pci_ctrl[0].gcr = 1;
+
+	for (i = 0; i < 1000; ++i)
+		udelay(1000);
+
+	pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
+	pci_law[0].ar = LBLAWAR_EN | LBLAWAR_1GB;
+
+	pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
+	pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
+
+	mpc83xx_pci_init(1, reg);
+}
diff --git a/u-boot/board/matrix_vision/mvsmr/Makefile b/u-boot/board/matrix_vision/mvsmr/Makefile
new file mode 100644
index 0000000..8ee556c
--- /dev/null
+++ b/u-boot/board/matrix_vision/mvsmr/Makefile
@@ -0,0 +1,51 @@
+#
+# (C) Copyright 2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2004-2008
+# Matrix-Vision GmbH, info@matrix-vision.de
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= $(BOARD).o fpga.o
+
+SRCS    := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS    := $(addprefix $(obj),$(COBJS))
+SOBJS   := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+	        $(call cmd_link_o_target, $(OBJS))
+	@mkimage -T script -C none -n mvSMR_Script -d bootscript $(obj)bootscript.img
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend $(obj)bootscript.img
+
+#########################################################################
+
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
diff --git a/u-boot/board/matrix_vision/mvsmr/bootscript b/u-boot/board/matrix_vision/mvsmr/bootscript
new file mode 100644
index 0000000..02c802c
--- /dev/null
+++ b/u-boot/board/matrix_vision/mvsmr/bootscript
@@ -0,0 +1,42 @@
+echo
+echo "==== running autoscript ===="
+echo
+setenv boot24 'bootm ${kernel_boot} ${mv_initrd_addr_ram}'
+setenv ramkernel 'setenv kernel_boot ${loadaddr}'
+setenv flashkernel 'setenv kernel_boot ${mv_kernel_addr}'
+setenv cpird 'cp ${mv_initrd_addr} ${mv_initrd_addr_ram} ${mv_initrd_length}'
+setenv bootfromflash run flashkernel cpird addcons boot24
+setenv bootfromnet 'tftp ${mv_initrd_addr_ram} ${initrd_name};run ramkernel'
+if test ${console} = yes;
+then
+setenv addcons 'setenv bootargs ${bootargs} console=ttyS${console_nr},${baudrate}N8'
+else
+setenv addcons 'setenv bootargs ${bootargs} console=tty0'
+fi
+setenv set_static_ip 'setenv ipaddr ${static_ipaddr}'
+setenv set_static_nm 'setenv netmask ${static_netmask}'
+setenv set_static_gw 'setenv gatewayip ${static_gateway}'
+setenv set_ip 'setenv ip ${ipaddr}::${gatewayip}:${netmask}'
+if test ${servicemode} != yes;
+then
+  echo "=== forced flash mode ==="
+  run set_static_ip set_static_nm set_static_gw set_ip bootfromflash
+fi
+if test ${autoscript_boot} != no;
+then
+  if test ${netboot} = yes;
+  then
+    bootp
+    if test $? = 0;
+    then
+      echo "=== bootp succeeded -> netboot ==="
+      run set_ip bootfromnet addcons boot24
+    else
+      echo "=== netboot failed ==="
+    fi
+  fi
+  echo "=== bootfromflash ==="
+  run set_static_ip set_static_nm set_static_gw set_ip bootfromflash
+else
+  echo "=== boot stopped with autoscript_boot no ==="
+fi
diff --git a/u-boot/board/matrix_vision/mvsmr/fpga.c b/u-boot/board/matrix_vision/mvsmr/fpga.c
new file mode 100644
index 0000000..6320a69
--- /dev/null
+++ b/u-boot/board/matrix_vision/mvsmr/fpga.c
@@ -0,0 +1,129 @@
+/*
+ * (C) Copyright 2002
+ * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
+ * Keith Outwater, keith_outwater@mvis.com.
+ *
+ * (C) Copyright 2010
+ * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <spartan3.h>
+#include <command.h>
+#include <asm/io.h>
+#include "fpga.h"
+#include "mvsmr.h"
+
+Xilinx_Spartan3_Slave_Serial_fns fpga_fns = {
+	fpga_pre_config_fn,
+	fpga_pgm_fn,
+	fpga_clk_fn,
+	fpga_init_fn,
+	fpga_done_fn,
+	fpga_wr_fn,
+	0
+};
+
+Xilinx_desc spartan3 = {
+	Xilinx_Spartan2,
+	slave_serial,
+	XILINX_XC3S200_SIZE,
+	(void *) &fpga_fns,
+	0,
+};
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int mvsmr_init_fpga(void)
+{
+	fpga_init();
+	fpga_add(fpga_xilinx, &spartan3);
+
+	return 1;
+}
+
+int fpga_init_fn(int cookie)
+{
+	struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
+
+	if (in_be32(&gpio->simple_ival) & FPGA_CONFIG)
+		return 0;
+
+	return 1;
+}
+
+int fpga_done_fn(int cookie)
+{
+	struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
+	int result = 0;
+
+	udelay(10);
+	if (in_be32(&gpio->simple_ival) & FPGA_DONE)
+		result = 1;
+
+	return result;
+}
+
+int fpga_pgm_fn(int assert, int flush, int cookie)
+{
+	struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
+
+	if (!assert)
+		setbits_8(&gpio->sint_dvo, FPGA_STATUS);
+	else
+		clrbits_8(&gpio->sint_dvo, FPGA_STATUS);
+
+	return assert;
+}
+
+int fpga_clk_fn(int assert_clk, int flush, int cookie)
+{
+	struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
+
+	if (assert_clk)
+		setbits_be32(&gpio->simple_dvo, FPGA_CCLK);
+	else
+		clrbits_be32(&gpio->simple_dvo, FPGA_CCLK);
+
+	return assert_clk;
+}
+
+int fpga_wr_fn(int assert_write, int flush, int cookie)
+{
+	struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
+
+	if (assert_write)
+		setbits_be32(&gpio->simple_dvo, FPGA_DIN);
+	else
+		clrbits_be32(&gpio->simple_dvo, FPGA_DIN);
+
+	return assert_write;
+}
+
+int fpga_pre_config_fn(int cookie)
+{
+	struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
+
+	setbits_8(&gpio->sint_dvo, FPGA_STATUS);
+
+	return 0;
+}
diff --git a/u-boot/board/matrix_vision/mvsmr/fpga.h b/u-boot/board/matrix_vision/mvsmr/fpga.h
new file mode 100644
index 0000000..ee690e6
--- /dev/null
+++ b/u-boot/board/matrix_vision/mvsmr/fpga.h
@@ -0,0 +1,32 @@
+/*
+ * (C) Copyright 2008
+ * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+extern int mvsmr_init_fpga(void);
+
+extern int fpga_pgm_fn(int assert_pgm, int flush, int cookie);
+extern int fpga_init_fn(int cookie);
+extern int fpga_clk_fn(int assert_clk, int flush, int cookie);
+extern int fpga_wr_fn(int assert_write, int flush, int cookie);
+extern int fpga_done_fn(int cookie);
+extern int fpga_pre_config_fn(int cookie);
diff --git a/u-boot/board/matrix_vision/mvsmr/mvsmr.c b/u-boot/board/matrix_vision/mvsmr/mvsmr.c
new file mode 100644
index 0000000..69655c4
--- /dev/null
+++ b/u-boot/board/matrix_vision/mvsmr/mvsmr.c
@@ -0,0 +1,264 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * (C) Copyright 2005-2010
+ * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc5xxx.h>
+#include <malloc.h>
+#include <pci.h>
+#include <i2c.h>
+#include <fpga.h>
+#include <environment.h>
+#include <netdev.h>
+#include <asm/io.h>
+#include "fpga.h"
+#include "mvsmr.h"
+#include "../common/mv_common.h"
+
+#define SDRAM_DDR	1
+#define SDRAM_MODE	0x018D0000
+#define SDRAM_EMODE	0x40090000
+#define SDRAM_CONTROL	0x715f0f00
+#define SDRAM_CONFIG1	0xd3722930
+#define SDRAM_CONFIG2	0x46770000
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void sdram_start(int hi_addr)
+{
+	long hi_bit = hi_addr ? 0x01000000 : 0;
+
+	/* unlock mode register */
+	out_be32((u32 *)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | 0x80000000 |
+		hi_bit);
+
+	/* precharge all banks */
+	out_be32((u32 *)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | 0x80000002 |
+		hi_bit);
+
+	/* set mode register: extended mode */
+	out_be32((u32 *)MPC5XXX_SDRAM_MODE, SDRAM_EMODE);
+
+	/* set mode register: reset DLL */
+	out_be32((u32 *)MPC5XXX_SDRAM_MODE, SDRAM_MODE | 0x04000000);
+
+	/* precharge all banks */
+	out_be32((u32 *)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | 0x80000002 |
+		hi_bit);
+
+	/* auto refresh */
+	out_be32((u32 *)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | 0x80000004 |
+		hi_bit);
+
+	/* set mode register */
+	out_be32((u32 *)MPC5XXX_SDRAM_MODE, SDRAM_MODE);
+
+	/* normal operation */
+	out_be32((u32 *)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | hi_bit);
+}
+
+phys_addr_t initdram(int board_type)
+{
+	ulong dramsize = 0;
+	ulong test1,
+	      test2;
+
+	/* setup SDRAM chip selects */
+	out_be32((u32 *)MPC5XXX_SDRAM_CS0CFG, 0x0000001e);
+
+	/* setup config registers */
+	out_be32((u32 *)MPC5XXX_SDRAM_CONFIG1, SDRAM_CONFIG1);
+	out_be32((u32 *)MPC5XXX_SDRAM_CONFIG2, SDRAM_CONFIG2);
+
+	/* find RAM size using SDRAM CS0 only */
+	sdram_start(0);
+	test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
+	sdram_start(1);
+	test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
+	if (test1 > test2) {
+		sdram_start(0);
+		dramsize = test1;
+	} else
+		dramsize = test2;
+
+	if (dramsize < (1 << 20))
+		dramsize = 0;
+
+	if (dramsize > 0)
+		out_be32((u32 *)MPC5XXX_SDRAM_CS0CFG, 0x13 +
+			__builtin_ffs(dramsize >> 20) - 1);
+	else
+		out_be32((u32 *)MPC5XXX_SDRAM_CS0CFG, 0);
+
+	return dramsize;
+}
+
+void mvsmr_init_gpio(void)
+{
+	struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
+	struct mpc5xxx_wu_gpio *wu_gpio =
+		(struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO;
+	struct mpc5xxx_gpt_0_7 *timers = (struct mpc5xxx_gpt_0_7 *)MPC5XXX_GPT;
+
+	printf("Ports : 0x%08x\n", gpio->port_config);
+	printf("PORCFG: 0x%08x\n", in_be32((unsigned *)MPC5XXX_CDM_PORCFG));
+
+	out_be32(&gpio->simple_ddr, SIMPLE_DDR);
+	out_be32(&gpio->simple_dvo, SIMPLE_DVO);
+	out_be32(&gpio->simple_ode, SIMPLE_ODE);
+	out_be32(&gpio->simple_gpioe, SIMPLE_GPIOEN);
+
+	out_8(&gpio->sint_ode, SINT_ODE);
+	out_8(&gpio->sint_ddr, SINT_DDR);
+	out_8(&gpio->sint_dvo, SINT_DVO);
+	out_8(&gpio->sint_inten, SINT_INTEN);
+	out_be16(&gpio->sint_itype, SINT_ITYPE);
+	out_8(&gpio->sint_gpioe, SINT_GPIOEN);
+
+	out_8(&wu_gpio->ode, WKUP_ODE);
+	out_8(&wu_gpio->ddr, WKUP_DIR);
+	out_8(&wu_gpio->dvo, WKUP_DO);
+	out_8(&wu_gpio->enable, WKUP_EN);
+
+	out_be32(&timers->gpt0.emsr, 0x00000234); /* OD output high */
+	out_be32(&timers->gpt1.emsr, 0x00000234);
+	out_be32(&timers->gpt2.emsr, 0x00000234);
+	out_be32(&timers->gpt3.emsr, 0x00000234);
+	out_be32(&timers->gpt4.emsr, 0x00000234);
+	out_be32(&timers->gpt5.emsr, 0x00000234);
+	out_be32(&timers->gpt6.emsr, 0x00000024); /* push-pull output low */
+	out_be32(&timers->gpt7.emsr, 0x00000024);
+}
+
+int misc_init_r(void)
+{
+	char *s = getenv("reset_env");
+
+	if (s) {
+		printf(" === FACTORY RESET ===\n");
+		mv_reset_environment();
+		saveenv();
+	}
+
+	return -1;
+}
+
+void mvsmr_get_dbg_present(void)
+{
+	struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
+	struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)MPC5XXX_PSC1;
+
+	if (in_be32(&gpio->simple_ival) & COP_PRESENT) {
+		setenv("dbg_present", "no\0");
+		setenv("bootstopkey", "abcdefghijklmnopqrstuvwxyz\0");
+	} else {
+		setenv("dbg_present", "yes\0");
+		setenv("bootstopkey", "s\0");
+		setbits_8(&psc->command, PSC_RX_ENABLE);
+	}
+}
+
+void mvsmr_get_service_mode(void)
+{
+	struct mpc5xxx_wu_gpio *wu_gpio =
+		(struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO;
+
+	if (in_8(&wu_gpio->ival) & SERVICE_MODE)
+		setenv("servicemode", "no\0");
+	else
+		setenv("servicemode", "yes\0");
+}
+
+int mvsmr_get_mac(void)
+{
+	unsigned char mac[6];
+	struct mpc5xxx_wu_gpio *wu_gpio =
+		(struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO;
+
+	if (in_8(&wu_gpio->ival) & LAN_PRSNT) {
+		setenv("lan_present", "no\0");
+		return -1;
+	} else
+		setenv("lan_present", "yes\0");
+
+	i2c_read(0x50, 0, 1, mac, 6);
+
+	eth_setenv_enetaddr("ethaddr", mac);
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	mvsmr_init_gpio();
+	printf("Board: Matrix Vision mvSMR\n");
+
+	return 0;
+}
+
+void flash_preinit(void)
+{
+	/*
+	 * Now, when we are in RAM, enable flash write
+	 * access for detection process.
+	 * Note that CS_BOOT cannot be cleared when
+	 * executing in flash.
+	 */
+	clrbits_be32((u32 *)MPC5XXX_BOOTCS_CFG, 0x1);
+}
+
+void flash_afterinit(ulong size)
+{
+	out_be32((u32 *)MPC5XXX_BOOTCS_START,
+		START_REG(CONFIG_SYS_BOOTCS_START | size));
+	out_be32((u32 *)MPC5XXX_CS0_START,
+		START_REG(CONFIG_SYS_BOOTCS_START | size));
+	out_be32((u32 *)MPC5XXX_BOOTCS_STOP,
+		STOP_REG(CONFIG_SYS_BOOTCS_START | size, size));
+	out_be32((u32 *)MPC5XXX_CS0_STOP,
+		STOP_REG(CONFIG_SYS_BOOTCS_START | size, size));
+}
+
+struct pci_controller hose;
+
+void pci_init_board(void)
+{
+	mvsmr_get_dbg_present();
+	mvsmr_get_service_mode();
+	mvsmr_init_fpga();
+	mv_load_fpga();
+	pci_mpc5xxx_init(&hose);
+}
+
+int board_eth_init(bd_t *bis)
+{
+	if (!mvsmr_get_mac())
+		return cpu_eth_init(bis);
+
+	return pci_eth_init(bis);
+}
diff --git a/u-boot/board/matrix_vision/mvsmr/mvsmr.h b/u-boot/board/matrix_vision/mvsmr/mvsmr.h
new file mode 100644
index 0000000..b8320f1
--- /dev/null
+++ b/u-boot/board/matrix_vision/mvsmr/mvsmr.h
@@ -0,0 +1,43 @@
+#include <pci.h>
+
+extern void pci_mpc5xxx_init(struct pci_controller *);
+
+#define FPGA_DIN	MPC5XXX_GPIO_SIMPLE_PSC3_0
+#define FPGA_CCLK	MPC5XXX_GPIO_SIMPLE_PSC3_1
+#define FPGA_DONE	MPC5XXX_GPIO_SIMPLE_PSC3_2
+#define FPGA_CONFIG	MPC5XXX_GPIO_SIMPLE_PSC3_3
+#define FPGA_STATUS	MPC5XXX_GPIO_SINT_PSC3_4
+#define S_FPGA_DIN	MPC5XXX_GPIO_SINT_PSC3_5
+#define S_FPGA_CCLK	MPC5XXX_GPIO_SIMPLE_PSC3_6
+#define S_FPGA_DONE	MPC5XXX_GPIO_SIMPLE_PSC3_7
+#define S_FPGA_CONFIG	MPC5XXX_GPIO_SINT_PSC3_8
+#define S_FPGA_STATUS	MPC5XXX_GPIO_WKUP_PSC3_9
+
+#define MAN_RST		MPC5XXX_GPIO_WKUP_PSC6_0
+#define WD_TS		MPC5XXX_GPIO_WKUP_PSC6_1
+#define WD_WDI		MPC5XXX_GPIO_SIMPLE_PSC6_2
+#define COP_PRESENT	MPC5XXX_GPIO_SIMPLE_PSC6_3
+#define SERVICE_MODE	MPC5XXX_GPIO_WKUP_6
+#define FLASH_RBY	MPC5XXX_GPIO_WKUP_7
+#define UART_EN1	MPC5XXX_GPIO_WKUP_PSC1_4
+#define LAN_PRSNT	MPC5XXX_GPIO_WKUP_PSC2_4
+
+#define SIMPLE_DDR	(FPGA_DIN | FPGA_CCLK | FPGA_CONFIG | WD_WDI |\
+			 S_FPGA_CCLK)
+#define SIMPLE_DVO	(FPGA_CONFIG)
+#define SIMPLE_ODE	(FPGA_CONFIG)
+#define SIMPLE_GPIOEN	(FPGA_DIN | FPGA_CCLK | FPGA_DONE | FPGA_CONFIG |\
+			 S_FPGA_CCLK | S_FPGA_DONE | WD_WDI | COP_PRESENT)
+
+#define SINT_ODE	0x1
+#define SINT_DDR	0x3
+#define SINT_DVO	0x1
+#define SINT_INTEN	0
+#define SINT_ITYPE	0
+#define SINT_GPIOEN	(FPGA_STATUS | S_FPGA_DIN | S_FPGA_CONFIG)
+
+#define WKUP_ODE	(MAN_RST | S_FPGA_STATUS)
+#define WKUP_DIR	(MAN_RST | WD_TS | S_FPGA_STATUS)
+#define WKUP_DO		(MAN_RST | WD_TS | S_FPGA_STATUS)
+#define WKUP_EN		(MAN_RST | WD_TS | S_FPGA_STATUS | SERVICE_MODE |\
+			 FLASH_RBY | UART_EN1 | LAN_PRSNT)
diff --git a/u-boot/board/matrix_vision/mvsmr/u-boot.lds b/u-boot/board/matrix_vision/mvsmr/u-boot.lds
new file mode 100644
index 0000000..074a482
--- /dev/null
+++ b/u-boot/board/matrix_vision/mvsmr/u-boot.lds
@@ -0,0 +1,102 @@
+/*
+ * (C) Copyright 2003-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ * (C) Copyright 2010
+ * André Schwarz, Matrix Vision GmbH, as@matrix-vision.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within  */
+    /* the first two sectors (=8KB) of our S29GL flash chip */
+    arch/powerpc/cpu/mpc5xxx/start.o	(.text*)
+    arch/powerpc/cpu/mpc5xxx/traps.o	(.text*)
+    board/matrix_vision/common/libmatrix_vision.o (.text*)
+
+    /* This is only needed to force failure if size of above code will ever */
+    /* increase and grow into reserved space. */
+    . = ALIGN(0x2000);	/* location counter has to be 0x4000 now */
+    . += 0x4000;	/* ->0x8000, i.e. move to env_offset */
+
+    . = env_offset;	/* ld error as soon as above ALIGN misplaces lc */
+    common/env_embedded.o        (.ppcenv)
+
+    *(.text*)
+    . = ALIGN(16);
+    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+  }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    KEEP(*(.got))
+    _GOT2_TABLE_ = .;
+    KEEP(*(.got2))
+    _FIXUP_TABLE_ = .;
+    KEEP(*(.fixup))
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data*)
+    *(.sdata*)
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss (NOLOAD)       :
+  {
+   *(.bss*)
+   *(.sbss*)
+   . = ALIGN(4);
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}