diff options
| -rw-r--r-- | MAINTAINERS | 1 | ||||
| -rwxr-xr-x | MAKEALL | 1 | ||||
| -rw-r--r-- | Makefile | 3 | ||||
| -rw-r--r-- | board/mosaixtech/icon/Makefile | 53 | ||||
| -rw-r--r-- | board/mosaixtech/icon/chip_config.c | 55 | ||||
| -rw-r--r-- | board/mosaixtech/icon/config.mk | 34 | ||||
| -rw-r--r-- | board/mosaixtech/icon/icon.c | 319 | ||||
| -rw-r--r-- | board/mosaixtech/icon/init.S | 88 | ||||
| -rw-r--r-- | include/configs/icon.h | 308 |
9 files changed, 862 insertions, 0 deletions
diff --git a/MAINTAINERS b/MAINTAINERS index a5d5835..00e06b7 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -368,6 +368,7 @@ Stefan Roese <sr@denx.de> ebony PPC440GP glacier PPC460GT haleakala PPC405EXr + icon PPC440SPe katmai PPC440SPe kilauea PPC405EX lwmon5 PPC440EPx @@ -224,6 +224,7 @@ LIST_4xx=" \ hcu5 \ HH405 \ HUB405 \ + icon \ intip \ JSE \ KAREF \ @@ -1357,6 +1357,9 @@ HH405_config: unconfig HUB405_config: unconfig @$(MKCONFIG) $(@:_config=) powerpc ppc4xx hub405 esd +icon_config: unconfig + @$(MKCONFIG) $(@:_config=) powerpc ppc4xx icon mosaixtech + # Compact-Center(codename intip) & DevCon-Center use different U-Boot images intip_config \ devconcenter_config: unconfig diff --git a/board/mosaixtech/icon/Makefile b/board/mosaixtech/icon/Makefile new file mode 100644 index 0000000..dad0457 --- /dev/null +++ b/board/mosaixtech/icon/Makefile @@ -0,0 +1,53 @@ +# +# (C) Copyright 2009-2010 +# Stefan Roese, DENX Software Engineering, sr@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS-y := $(BOARD).o +COBJS-$(CONFIG_CMD_CHIP_CONFIG) += chip_config.o +SOBJS = init.o + +COBJS := $(COBJS-y) +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/mosaixtech/icon/chip_config.c b/board/mosaixtech/icon/chip_config.c new file mode 100644 index 0000000..b9dd447 --- /dev/null +++ b/board/mosaixtech/icon/chip_config.c @@ -0,0 +1,55 @@ +/* + * (C) Copyright 2009-2010 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#include <common.h> +#include <asm/ppc4xx_config.h> + +struct ppc4xx_config ppc4xx_config_val[] = { + { + "400-133", "CPU: 400 PLB: 133 OPB: 66 EBC: 66", + { 0x86, 0x78, 0xc2, 0xc6, 0x05, 0xa5, 0x04, 0xe1 } + }, + { + "500-166", "CPU: 500 PLB: 166 OPB: 83 EBC: 83", + { 0x87, 0x78, 0xf2, 0xc6, 0x05, 0xa5, 0x04, 0xe1 } + }, + { + "533-133", "CPU: 533 PLB: 133 OPB: 66 EBC: 66", + { 0x87, 0x79, 0x02, 0x52, 0x05, 0xa5, 0x04, 0xe1 } + }, + { + "667-133", "CPU: 667 PLB: 133 OPB: 66 EBC: 66", + { 0x87, 0x79, 0x42, 0x56, 0x05, 0xa5, 0x04, 0xe1 } + }, + { + "667-166", "CPU: 667 PLB: 166 OPB: 83 EBC: 83", + { 0x87, 0x79, 0x42, 0x06, 0x05, 0xa5, 0x04, 0xe1 } + }, + { + "800-160", "CPU: 800 PLB: 160 OPB: 53 EBC: 17", + { 0x86, 0x79, 0x81, 0xa7, 0x07, 0xa5, 0x04, 0xe1 } + }, +}; + +int ppc4xx_config_count = ARRAY_SIZE(ppc4xx_config_val); diff --git a/board/mosaixtech/icon/config.mk b/board/mosaixtech/icon/config.mk new file mode 100644 index 0000000..b2748ce --- /dev/null +++ b/board/mosaixtech/icon/config.mk @@ -0,0 +1,34 @@ +# +# (C) Copyright 2009-2010 +# Stefan Roese, DENX Software Engineering, sr@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +TEXT_BASE = 0xFFFA0000 + +PLATFORM_CPPFLAGS += -DCONFIG_440=1 + +ifeq ($(debug),1) +PLATFORM_CPPFLAGS += -DDEBUG +endif + +ifeq ($(dbcr),1) +PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000 +endif diff --git a/board/mosaixtech/icon/icon.c b/board/mosaixtech/icon/icon.c new file mode 100644 index 0000000..fbace9e --- /dev/null +++ b/board/mosaixtech/icon/icon.c @@ -0,0 +1,319 @@ +/* + * (C) Copyright 2009-2010 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#include <common.h> +#include <ppc4xx.h> +#include <i2c.h> +#include <libfdt.h> +#include <fdt_support.h> +#include <netdev.h> +#include <asm/processor.h> +#include <asm/io.h> +#include <asm/gpio.h> +#include <asm/4xx_pcie.h> +#include <asm/errno.h> +#include <asm/mmu.h> + +DECLARE_GLOBAL_DATA_PTR; + +int board_early_init_f(void) +{ + unsigned long mfr; + + /* + * Interrupt controller setup for the ICON 440SPe board. + * + *-------------------------------------------------------------------- + * IRQ | Source | Pol. | Sensi.| Crit. + *--------+-----------------------------------+-------+-------+------- + * IRQ 00 | UART0 | High | Level | Non + * IRQ 01 | UART1 | High | Level | Non + * IRQ 02 | IIC0 | High | Level | Non + * IRQ 03 | IIC1 | High | Level | Non + * IRQ 04 | PCI0X0 MSG IN | High | Level | Non + * IRQ 05 | PCI0X0 CMD Write | High | Level | Non + * IRQ 06 | PCI0X0 Power Mgt | High | Level | Non + * IRQ 07 | PCI0X0 VPD Access | Rising| Edge | Non + * IRQ 08 | PCI0X0 MSI level 0 | High | Lvl/ed| Non + * IRQ 09 | External IRQ 15 - (PCI-Express) | pgm H | Pgm | Non + * IRQ 10 | UIC2 Non-critical Int. | NA | NA | Non + * IRQ 11 | UIC2 Critical Interrupt | NA | NA | Crit + * IRQ 12 | PCI Express MSI Level 0 | Rising| Edge | Non + * IRQ 13 | PCI Express MSI Level 1 | Rising| Edge | Non + * IRQ 14 | PCI Express MSI Level 2 | Rising| Edge | Non + * IRQ 15 | PCI Express MSI Level 3 | Rising| Edge | Non + * IRQ 16 | UIC3 Non-critical Int. | NA | NA | Non + * IRQ 17 | UIC3 Critical Interrupt | NA | NA | Crit + * IRQ 18 | External IRQ 14 - (PCI-Express) | Pgm | Pgm | Non + * IRQ 19 | DMA Channel 0 FIFO Full | High | Level | Non + * IRQ 20 | DMA Channel 0 Stat FIFO | High | Level | Non + * IRQ 21 | DMA Channel 1 FIFO Full | High | Level | Non + * IRQ 22 | DMA Channel 1 Stat FIFO | High | Level | Non + * IRQ 23 | I2O Inbound Doorbell | High | Level | Non + * IRQ 24 | Inbound Post List FIFO Not Empt | High | Level | Non + * IRQ 25 | I2O Region 0 LL PLB Write | High | Level | Non + * IRQ 26 | I2O Region 1 LL PLB Write | High | Level | Non + * IRQ 27 | I2O Region 0 HB PLB Write | High | Level | Non + * IRQ 28 | I2O Region 1 HB PLB Write | High | Level | Non + * IRQ 29 | GPT Down Count Timer | Rising| Edge | Non + * IRQ 30 | UIC1 Non-critical Int. | NA | NA | Non + * IRQ 31 | UIC1 Critical Interrupt | NA | NA | Crit. + *-------------------------------------------------------------------- + * IRQ 32 | Ext. IRQ 13 - (PCI-Express) |pgm (H)|pgm/Lvl| Non + * IRQ 33 | MAL Serr | High | Level | Non + * IRQ 34 | MAL Txde | High | Level | Non + * IRQ 35 | MAL Rxde | High | Level | Non + * IRQ 36 | DMC CE or DMC UE | High | Level | Non + * IRQ 37 | EBC or UART2 | High |Lvl Edg| Non + * IRQ 38 | MAL TX EOB | High | Level | Non + * IRQ 39 | MAL RX EOB | High | Level | Non + * IRQ 40 | PCIX0 MSI Level 1 | High |Lvl Edg| Non + * IRQ 41 | PCIX0 MSI level 2 | High |Lvl Edg| Non + * IRQ 42 | PCIX0 MSI level 3 | High |Lvl Edg| Non + * IRQ 43 | L2 Cache | Risin | Edge | Non + * IRQ 44 | GPT Compare Timer 0 | Risin | Edge | Non + * IRQ 45 | GPT Compare Timer 1 | Risin | Edge | Non + * IRQ 46 | GPT Compare Timer 2 | Risin | Edge | Non + * IRQ 47 | GPT Compare Timer 3 | Risin | Edge | Non + * IRQ 48 | GPT Compare Timer 4 | Risin | Edge | Non + * IRQ 49 | Ext. IRQ 12 - PCI-X |pgm/Fal|pgm/Lvl| Non + * IRQ 50 | Ext. IRQ 11 - |pgm (H)|pgm/Lvl| Non + * IRQ 51 | Ext. IRQ 10 - |pgm (H)|pgm/Lvl| Non + * IRQ 52 | Ext. IRQ 9 |pgm (H)|pgm/Lvl| Non + * IRQ 53 | Ext. IRQ 8 |pgm (H)|pgm/Lvl| Non + * IRQ 54 | DMA Error | High | Level | Non + * IRQ 55 | DMA I2O Error | High | Level | Non + * IRQ 56 | Serial ROM | High | Level | Non + * IRQ 57 | PCIX0 Error | High | Edge | Non + * IRQ 58 | Ext. IRQ 7- |pgm (H)|pgm/Lvl| Non + * IRQ 59 | Ext. IRQ 6- |pgm (H)|pgm/Lvl| Non + * IRQ 60 | EMAC0 Interrupt | High | Level | Non + * IRQ 61 | EMAC0 Wake-up | High | Level | Non + * IRQ 62 | Reserved | High | Level | Non + * IRQ 63 | XOR | High | Level | Non + *-------------------------------------------------------------------- + * IRQ 64 | PE0 AL | High | Level | Non + * IRQ 65 | PE0 VPD Access | Risin | Edge | Non + * IRQ 66 | PE0 Hot Reset Request | Risin | Edge | Non + * IRQ 67 | PE0 Hot Reset Request | Falli | Edge | Non + * IRQ 68 | PE0 TCR | High | Level | Non + * IRQ 69 | PE0 BusMaster VCO | Falli | Edge | Non + * IRQ 70 | PE0 DCR Error | High | Level | Non + * IRQ 71 | Reserved | N/A | N/A | Non + * IRQ 72 | PE1 AL | High | Level | Non + * IRQ 73 | PE1 VPD Access | Risin | Edge | Non + * IRQ 74 | PE1 Hot Reset Request | Risin | Edge | Non + * IRQ 75 | PE1 Hot Reset Request | Falli | Edge | Non + * IRQ 76 | PE1 TCR | High | Level | Non + * IRQ 77 | PE1 BusMaster VCO | Falli | Edge | Non + * IRQ 78 | PE1 DCR Error | High | Level | Non + * IRQ 79 | Reserved | N/A | N/A | Non + * IRQ 80 | PE2 AL | High | Level | Non + * IRQ 81 | PE2 VPD Access | Risin | Edge | Non + * IRQ 82 | PE2 Hot Reset Request | Risin | Edge | Non + * IRQ 83 | PE2 Hot Reset Request | Falli | Edge | Non + * IRQ 84 | PE2 TCR | High | Level | Non + * IRQ 85 | PE2 BusMaster VCO | Falli | Edge | Non + * IRQ 86 | PE2 DCR Error | High | Level | Non + * IRQ 87 | Reserved | N/A | N/A | Non + * IRQ 88 | External IRQ(5) | Progr | Progr | Non + * IRQ 89 | External IRQ 4 - Ethernet | Progr | Progr | Non + * IRQ 90 | External IRQ 3 - PCI-X | Progr | Progr | Non + * IRQ 91 | External IRQ 2 - PCI-X | Progr | Progr | Non + * IRQ 92 | External IRQ 1 - PCI-X | Progr | Progr | Non + * IRQ 93 | External IRQ 0 - PCI-X | Progr | Progr | Non + * IRQ 94 | Reserved | N/A | N/A | Non + * IRQ 95 | Reserved | N/A | N/A | Non + *-------------------------------------------------------------------- + * IRQ 96 | PE0 INTA | High | Level | Non + * IRQ 97 | PE0 INTB | High | Level | Non + * IRQ 98 | PE0 INTC | High | Level | Non + * IRQ 99 | PE0 INTD | High | Level | Non + * IRQ 100| PE1 INTA | High | Level | Non + * IRQ 101| PE1 INTB | High | Level | Non + * IRQ 102| PE1 INTC | High | Level | Non + * IRQ 103| PE1 INTD | High | Level | Non + * IRQ 104| PE2 INTA | High | Level | Non + * IRQ 105| PE2 INTB | High | Level | Non + * IRQ 106| PE2 INTC | High | Level | Non + * IRQ 107| PE2 INTD | Risin | Edge | Non + * IRQ 108| PCI Express MSI Level 4 | Risin | Edge | Non + * IRQ 109| PCI Express MSI Level 5 | Risin | Edge | Non + * IRQ 110| PCI Express MSI Level 6 | Risin | Edge | Non + * IRQ 111| PCI Express MSI Level 7 | Risin | Edge | Non + * IRQ 116| PCI Express MSI Level 12 | Risin | Edge | Non + * IRQ 112| PCI Express MSI Level 8 | Risin | Edge | Non + * IRQ 113| PCI Express MSI Level 9 | Risin | Edge | Non + * IRQ 114| PCI Express MSI Level 10 | Risin | Edge | Non + * IRQ 115| PCI Express MSI Level 11 | Risin | Edge | Non + * IRQ 117| PCI Express MSI Level 13 | Risin | Edge | Non + * IRQ 118| PCI Express MSI Level 14 | Risin | Edge | Non + * IRQ 119| PCI Express MSI Level 15 | Risin | Edge | Non + * IRQ 120| PCI Express MSI Level 16 | Risin | Edge | Non + * IRQ 121| PCI Express MSI Level 17 | Risin | Edge | Non + * IRQ 122| PCI Express MSI Level 18 | Risin | Edge | Non + * IRQ 123| PCI Express MSI Level 19 | Risin | Edge | Non + * IRQ 124| PCI Express MSI Level 20 | Risin | Edge | Non + * IRQ 125| PCI Express MSI Level 21 | Risin | Edge | Non + * IRQ 126| PCI Express MSI Level 22 | Risin | Edge | Non + * IRQ 127| PCI Express MSI Level 23 | Risin | Edge | Non + */ + + /* + * Put UICs in PowerPC 440SPe mode. + * Initialise UIC registers. Clear all interrupts. Disable all + * interrupts. Set critical interrupt values. Set interrupt polarities. + * Set interrupt trigger levels. Make bit 0 High priority. Clear all + * interrupts again. + */ + mtdcr(UIC3SR, 0xffffffff); /* Clear all interrupts */ + mtdcr(UIC3ER, 0x00000000); /* disable all interrupts */ + mtdcr(UIC3CR, 0x00000000); /* Set Critical / Non Critical IRQs */ + mtdcr(UIC3PR, 0xffffffff); /* Set Interrupt Polarities*/ + mtdcr(UIC3TR, 0x001fffff); /* Set Interrupt Trigger Levels */ + mtdcr(UIC3VR, 0x00000001); /* Set Vect base=0,INT31 Highest prio */ + mtdcr(UIC3SR, 0x00000000); /* clear all interrupts*/ + mtdcr(UIC3SR, 0xffffffff); /* clear all interrupts*/ + + mtdcr(UIC2SR, 0xffffffff); /* Clear all interrupts */ + mtdcr(UIC2ER, 0x00000000); /* disable all interrupts*/ + mtdcr(UIC2CR, 0x00000000); /* Set Critical / Non Critical IRQs */ + mtdcr(UIC2PR, 0xebebebff); /* Set Interrupt Polarities*/ + mtdcr(UIC2TR, 0x74747400); /* Set Interrupt Trigger Levels */ + mtdcr(UIC2VR, 0x00000001); /* Set Vect base=0,INT31 Highest prio */ + mtdcr(UIC2SR, 0x00000000); /* clear all interrupts */ + mtdcr(UIC2SR, 0xffffffff); /* clear all interrupts */ + + mtdcr(UIC1SR, 0xffffffff); /* Clear all interrupts*/ + mtdcr(UIC1ER, 0x00000000); /* disable all interrupts*/ + mtdcr(UIC1CR, 0x00000000); /* Set Critical / Non Critical IRQs */ + mtdcr(UIC1PR, 0xffffffff); /* Set Interrupt Polarities */ + mtdcr(UIC1TR, 0x001f8040); /* Set Interrupt Trigger Levels*/ + mtdcr(UIC1VR, 0x00000001); /* Set Vect base=0,INT31 Highest prio */ + mtdcr(UIC1SR, 0x00000000); /* clear all interrupts*/ + mtdcr(UIC1SR, 0xffffffff); /* clear all interrupts*/ + + mtdcr(UIC0SR, 0xffffffff); /* Clear all interrupts */ + mtdcr(UIC0ER, 0x00000000); /* disable all int. excepted cascade */ + mtdcr(UIC0CR, 0x00104001); /* Set Critical / Non Critical IRQs */ + mtdcr(UIC0PR, 0xffffffff); /* Set Interrupt Polarities*/ + mtdcr(UIC0TR, 0x010f0004); /* Set Interrupt Trigger Levels */ + mtdcr(UIC0VR, 0x00000001); /* Set Vect base=0,INT31 Highest prio */ + mtdcr(UIC0SR, 0x00000000); /* clear all interrupts*/ + mtdcr(UIC0SR, 0xffffffff); /* clear all interrupts*/ + + mfsdr(SDR0_MFR, mfr); + mfr |= SDR0_MFR_FIXD; /* Workaround for PCI/DMA */ + mtsdr(SDR0_MFR, mfr); + + mtsdr(SDR0_PFC0, CONFIG_SYS_PFC0); + + out_be32((void *)GPIO0_OR, CONFIG_SYS_GPIO_OR); + out_be32((void *)GPIO0_ODR, CONFIG_SYS_GPIO_ODR); + out_be32((void *)GPIO0_TCR, CONFIG_SYS_GPIO_TCR); + + return 0; +} + +int board_early_init_r(void) +{ + /* + * ICON has 64MBytes of NOR FLASH (Spansion 29GL512), but the + * boot EBC mapping only supports a maximum of 16MBytes + * (4.ff00.0000 - 4.ffff.ffff). + * To solve this problem, the FLASH has to get remapped to another + * EBC address which accepts bigger regions: + * + * 0xfc00.0000 -> 4.ec00.0000 + */ + + /* Remap the NOR FLASH to 0xec00.0000 ... 0xefff.ffff */ + mtebc(PB0CR, CONFIG_SYS_FLASH_BASE_PHYS_L | 0xda000); + + /* Remove TLB entry of boot EBC mapping */ + remove_tlb(CONFIG_SYS_BOOT_BASE_ADDR, 16 << 20); + + /* Add TLB entry for 0xfc00.0000 -> 0x4.ec00.0000 */ + program_tlb(CONFIG_SYS_FLASH_BASE_PHYS, CONFIG_SYS_FLASH_BASE, + CONFIG_SYS_FLASH_SIZE, TLB_WORD2_I_ENABLE); + + /* + * Now accessing of the whole 64Mbytes of NOR FLASH at virtual address + * 0xfc00.0000 is possible + */ + + /* + * Clear potential errors resulting from auto-calibration. + * If not done, then we could get an interrupt later on when + * exceptions are enabled. + */ + set_mcsr(get_mcsr()); + + return 0; +} + +int checkboard(void) +{ + char *s = getenv("serial#"); + + printf("Board: ICON"); + if (s != NULL) { + puts(", serial# "); + puts(s); + } + putc('\n'); + + return 0; +} + +/* + * Override the default functions in cpu/ppc4xx/44x_spd_ddr2.c with + * board specific values. + * + * Tested successfully with the following SODIMM: + * Crucial CT6464AC667.4FE - 512MB SO-DIMM (single rank) + * + * Tests with Micron MT4HTF6464HZ-667H1 showed problems in "cold" state, + * directly after power-up. Only after running for more than 10 minutes + * real stable auto-calibration windows could be found. + */ +u32 ddr_wrdtr(u32 default_val) +{ + return SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_90_DEG_ADV; +} + +u32 ddr_clktr(u32 default_val) +{ + return SDRAM_CLKTR_CLKP_180_DEG_ADV; +} + +/* + * Override the weak default implementation and return the + * last PCIe slot number (max number - 1). + */ +int board_pcie_last(void) +{ + /* Only 2 PCIe ports used on ICON, so the last one is 1 */ + return 1; +} diff --git a/board/mosaixtech/icon/init.S b/board/mosaixtech/icon/init.S new file mode 100644 index 0000000..70ed6ce --- /dev/null +++ b/board/mosaixtech/icon/init.S @@ -0,0 +1,88 @@ +/* + * (C) Copyright 2009-2010 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <ppc_asm.tmpl> +#include <config.h> +#include <asm/mmu.h> + +/* + * TLB TABLE + * + * This table is used by the cpu boot code to setup the initial tlb + * entries. Rather than make broad assumptions in the cpu source tree, + * this table lets each board set things up however they like. + * + * Pointer to the table is returned in r1 + * + */ + + .section .bootpg,"ax" + + .globl tlbtab +tlbtab: + tlbtab_start + + /* + * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to + * use the speed up boot process. It is patched after relocation to + * enable SA_I. + */ + tlbentry(CONFIG_SYS_BOOT_BASE_ADDR, SZ_16M, CONFIG_SYS_BOOT_BASE_ADDR, + 4, AC_RWX | SA_G) /* TLB 0 */ + + /* + * TLB entries for SDRAM are not needed on this platform. + * They are dynamically generated in the SPD DDR(2) detection + * routine. + */ + + tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x00000000, 4, + AC_RWX | SA_I) + + tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_4K, 0xF0000000, 4, + AC_RW | SA_IG) + + tlbentry(CONFIG_SYS_ACE_BASE, SZ_1K, + CONFIG_SYS_ACE_BASE_PHYS_L, CONFIG_SYS_ACE_BASE_PHYS_H, + AC_RW | SA_IG) + + tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 0xC, + AC_RW | SA_IG) + tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, + AC_RW | SA_IG) + tlbentry(CONFIG_SYS_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, + AC_RW | SA_IG) + + tlbentry(CONFIG_SYS_PCIE0_CFGBASE, SZ_16M, 0x00000000, 0xD, + AC_RW | SA_IG) + tlbentry(CONFIG_SYS_PCIE1_CFGBASE, SZ_16M, 0x20000000, 0xD, + AC_RW | SA_IG) + tlbentry(CONFIG_SYS_PCIE2_CFGBASE, SZ_16M, 0x40000000, 0xD, + AC_RW | SA_IG) + tlbentry(CONFIG_SYS_PCIE0_XCFGBASE, SZ_1K, 0x10000000, 0xD, + AC_RW | SA_IG) + tlbentry(CONFIG_SYS_PCIE1_XCFGBASE, SZ_1K, 0x30000000, 0xD, + AC_RW | SA_IG) + tlbentry(CONFIG_SYS_PCIE2_XCFGBASE, SZ_1K, 0x50000000, 0xD, + AC_RW | SA_IG) + tlbtab_end diff --git a/include/configs/icon.h b/include/configs/icon.h new file mode 100644 index 0000000..3a57d69 --- /dev/null +++ b/include/configs/icon.h @@ -0,0 +1,308 @@ +/* + * (C) Copyright 2009-2010 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * icon.h - configuration for Mosaixtech ICON (440SPe) + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + */ +#define CONFIG_ICON 1 /* Board is icon */ +#define CONFIG_4xx 1 /* ... PPC4xx family */ +#define CONFIG_440 1 /* ... PPC440 family */ +#define CONFIG_440SPE 1 /* Specifc SPe support */ +#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ +#define CONFIG_SYS_4xx_RESET_TYPE 0x2 /* use chip reset on this board */ + +/* + * Include common defines/options for all AMCC eval boards + */ +#define CONFIG_HOSTNAME icon +#include "amcc-common.h" + +#define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */ +#define CONFIG_BOARD_EARLY_INIT_R /* Call board_early_init_r */ + +/* + * Base addresses -- Note these are effective addresses where the + * actual resources get mapped (not physical addresses) + */ +#define CONFIG_SYS_FLASH_BASE 0xfc000000 /* later mapped to this addr */ +#define CONFIG_SYS_PERIPHERAL_BASE 0xa0000000 /* internal peripherals */ +#define CONFIG_SYS_ISRAM_BASE 0x90000000 /* internal SRAM */ + +#define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped PCI memory */ +#define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */ +#define CONFIG_SYS_PCI_TARGBASE CONFIG_SYS_PCI_MEMBASE + +#define CONFIG_SYS_PCIE_MEMBASE 0xb0000000 /* mapped PCIe memory */ +#define CONFIG_SYS_PCIE_MEMSIZE 0x08000000 /* incr for PCIe port */ +#define CONFIG_SYS_PCIE_BASE 0xe0000000 /* PCIe UTL regs */ + +#define CONFIG_SYS_PCIE0_CFGBASE 0xc0000000 +#define CONFIG_SYS_PCIE1_CFGBASE 0xc1000000 +#define CONFIG_SYS_PCIE2_CFGBASE 0xc2000000 +#define CONFIG_SYS_PCIE0_XCFGBASE 0xc3000000 +#define CONFIG_SYS_PCIE1_XCFGBASE 0xc3001000 +#define CONFIG_SYS_PCIE2_XCFGBASE 0xc3002000 + +/* base address of inbound PCIe window */ +#define CONFIG_SYS_PCIE_INBOUND_BASE 0x0000000000000000ULL + +/* System RAM mapped to PCI space */ +#define CONFIG_PCI_SYS_MEM_BUS CONFIG_SYS_SDRAM_BASE +#define CONFIG_PCI_SYS_MEM_PHYS CONFIG_SYS_SDRAM_BASE +#define CONFIG_PCI_SYS_MEM_SIZE (1024 * 1024 * 1024) + +#define CONFIG_SYS_ACE_BASE 0xfb000000 /* Xilinx ACE CF */ +#define CONFIG_SYS_ACE_BASE_PHYS_H 0x4 +#define CONFIG_SYS_ACE_BASE_PHYS_L 0xfe000000 + +#define CONFIG_SYS_FLASH_SIZE (64 << 20) +#define CONFIG_SYS_BOOT_BASE_ADDR 0xFF000000 /* EBC Boot Space */ +#define CONFIG_SYS_FLASH_BASE_PHYS_H 0x4 +#define CONFIG_SYS_FLASH_BASE_PHYS_L 0xEC000000 +#define CONFIG_SYS_FLASH_BASE_PHYS (((u64)CONFIG_SYS_FLASH_BASE_PHYS_H << 32) | \ + (u64)CONFIG_SYS_FLASH_BASE_PHYS_L) + +/* + * Initial RAM & stack pointer (placed in internal SRAM) + */ +#define CONFIG_SYS_TEMP_STACK_OCM 1 +#define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_ISRAM_BASE +#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_ISRAM_BASE /* Init RAM */ +#define CONFIG_SYS_INIT_RAM_END 0x2000 /* end used area */ +#define CONFIG_SYS_GBL_DATA_SIZE 128 /* sizeof init data */ + +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - \ + CONFIG_SYS_GBL_DATA_SIZE) +#define CONFIG_SYS_POST_WORD_ADDR (CONFIG_SYS_GBL_DATA_OFFSET - 0x4) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_POST_WORD_ADDR + +/* + * Serial Port + */ +#undef CONFIG_UART1_CONSOLE +#undef CONFIG_SYS_EXT_SERIAL_CLOCK + +/* + * DDR2 SDRAM + */ +#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */ +#define SPD_EEPROM_ADDRESS { 0x51 } /* SPD I2C SPD addresses */ +#define CONFIG_DDR_ECC /* with ECC support */ +#define CONFIG_DDR_RQDC_FIXED 0x80000038 /* fixed value for RQDC */ + +/* + * I2C + */ +#define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */ + +#define CONFIG_I2C_MULTI_BUS +#define CONFIG_SYS_SPD_BUS_NUM 0 /* The I2C bus for SPD */ + +#define CONFIG_SYS_I2C_MULTI_EEPROMS +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 + +/* I2C bootstrap EEPROM */ +#define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR 0x50 +#define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET 0 +#define CONFIG_4xx_CONFIG_BLOCKSIZE 8 + +/* I2C RTC */ +#define CONFIG_RTC_M41T11 +#define CONFIG_SYS_RTC_BUS_NUM 1 /* The I2C bus for RTC */ +#define CONFIG_SYS_I2C_RTC_ADDR 0x68 +#define CONFIG_SYS_M41T11_BASE_YEAR 1900 /* play along with linux */ + +/* + * Environment + */ +#define CONFIG_ENV_IS_IN_FLASH 1 /* Environment uses flash */ + +/* + * Default environment variables + */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_AMCC_DEF_ENV \ + CONFIG_AMCC_DEF_ENV_POWERPC \ + CONFIG_AMCC_DEF_ENV_NOR_UPD \ + "kernel_addr=fc000000\0" \ + "fdt_addr=fc1e0000\0" \ + "ramdisk_addr=fc200000\0" \ + "pciconfighost=1\0" \ + "pcie_mode=RP:RP:RP\0" \ + "" + +/* + * Commands additional to the ones defined in amcc-common.h + */ +#define CONFIG_CMD_CHIP_CONFIG +#define CONFIG_CMD_DATE +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_CMD_PCI +#define CONFIG_CMD_SDRAM +#define CONFIG_CMD_SNTP + +#define CONFIG_IBM_EMAC4_V4 /* 440SPe has this EMAC version */ +#define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */ +#define CONFIG_HAS_ETH0 +#define CONFIG_PHY_RESET /* reset phy upon startup */ +#define CONFIG_PHY_RESET_DELAY 1000 +#define CONFIG_CIS8201_PHY /* Enable RGMII mode for Cicada phy */ +#define CONFIG_PHY_GIGE /* Include GbE speed/duplex det. */ + +/* + * FLASH related + */ +#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */ +#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ +#define CONFIG_SYS_FLASH_CFI_AMD_RESET /* Use AMD (Spansion) reset cmd */ +#define CONFIG_SYS_CFI_FLASH_STATUS_POLL /* use status poll method */ + +#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors*/ + +#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* TO for Flash Erase (ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* TO for Flash Write (ms) */ + +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* use buffered writes */ +#define CONFIG_SYS_FLASH_EMPTY_INFO /* 'E' for empty sector */ + +#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */ +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Env Sector */ + +/* Address and size of Redundant Environment Sector */ +#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) + +/* + * PCI stuff + */ +/* General PCI */ +#define CONFIG_PCI /* include pci support */ +#define CONFIG_PCI_PNP /* do pci plug-and-play */ +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CONFIG_PCI_CONFIG_HOST_BRIDGE +#define CONFIG_PCI_BOOTDELAY 1000 /* enable pci bootdelay variable*/ + +/* Board-specific PCI */ +#define CONFIG_SYS_PCI_TARGET_INIT /* let board init pci target */ +#undef CONFIG_SYS_PCI_MASTER_INIT + +#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014 /* IBM */ +#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */ + +/* + * Xilinx System ACE support + */ +#define CONFIG_SYSTEMACE /* Enable SystemACE support */ +#define CONFIG_SYS_SYSTEMACE_WIDTH 16 /* Data bus width is 16 */ +#define CONFIG_SYS_SYSTEMACE_BASE CONFIG_SYS_ACE_BASE +#define CONFIG_DOS_PARTITION + +/* + * External Bus Controller (EBC) Setup + */ + +/* Memory Bank 0 (Flash) initialization */ +#define CONFIG_SYS_EBC_PB0AP (EBC_BXAP_BME_DISABLED | \ + EBC_BXAP_TWT_ENCODE(7) | \ + EBC_BXAP_BCE_DISABLE | \ + EBC_BXAP_BCT_2TRANS | \ + EBC_BXAP_CSN_ENCODE(0) | \ + EBC_BXAP_OEN_ENCODE(0) | \ + EBC_BXAP_WBN_ENCODE(0) | \ + EBC_BXAP_WBF_ENCODE(0) | \ + EBC_BXAP_TH_ENCODE(0) | \ + EBC_BXAP_RE_DISABLED | \ + EBC_BXAP_SOR_DELAYED | \ + EBC_BXAP_BEM_WRITEONLY | \ + EBC_BXAP_PEN_DISABLED) +#define CONFIG_SYS_EBC_PB0CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) | \ + EBC_BXCR_BS_64MB | \ + EBC_BXCR_BU_RW | \ + EBC_BXCR_BW_16BIT) + +/* Memory Bank 1 (Xilinx System ACE controller) initialization */ +#define CONFIG_SYS_EBC_PB1AP (EBC_BXAP_BME_DISABLED | \ + EBC_BXAP_TWT_ENCODE(4) | \ + EBC_BXAP_BCE_DISABLE | \ + EBC_BXAP_BCT_2TRANS | \ + EBC_BXAP_CSN_ENCODE(0) | \ + EBC_BXAP_OEN_ENCODE(0) | \ + EBC_BXAP_WBN_ENCODE(0) | \ + EBC_BXAP_WBF_ENCODE(0) | \ + EBC_BXAP_TH_ENCODE(0) | \ + EBC_BXAP_RE_DISABLED | \ + EBC_BXAP_SOR_NONDELAYED | \ + EBC_BXAP_BEM_WRITEONLY | \ + EBC_BXAP_PEN_DISABLED) +#define CONFIG_SYS_EBC_PB1CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_ACE_BASE_PHYS_L) | \ + EBC_BXCR_BS_1MB | \ + EBC_BXCR_BU_RW | \ + EBC_BXCR_BW_16BIT) + +/* + * Initialize EBC CONFIG - + * Keep the Default value, but the bit PDT which has to be set to 1 ?TBC + * default value : 0x07C00000 - 0 0 000 1 1 1 1 1 0000 0 00000 000000000000 + */ +#define CONFIG_SYS_EBC_CFG (EBC_CFG_LE_UNLOCK | \ + EBC_CFG_PTD_ENABLE | \ + EBC_CFG_RTC_16PERCLK | \ + EBC_CFG_ATC_PREVIOUS | \ + EBC_CFG_DTC_PREVIOUS | \ + EBC_CFG_CTC_PREVIOUS | \ + EBC_CFG_OEO_PREVIOUS | \ + EBC_CFG_EMC_DEFAULT | \ + EBC_CFG_PME_DISABLE | \ + EBC_CFG_PR_16) + +/* + * GPIO Setup + */ +#define CONFIG_SYS_GPIO_PCIE_PRESENT0 17 +#define CONFIG_SYS_GPIO_PCIE_PRESENT1 21 +#define CONFIG_SYS_GPIO_PCIE_PRESENT2 23 +#define CONFIG_SYS_GPIO_RS232_FORCEOFF 30 + +#define CONFIG_SYS_PFC0 (GPIO_VAL(CONFIG_SYS_GPIO_PCIE_PRESENT0) | \ + GPIO_VAL(CONFIG_SYS_GPIO_PCIE_PRESENT1) | \ + GPIO_VAL(CONFIG_SYS_GPIO_PCIE_PRESENT2) | \ + GPIO_VAL(CONFIG_SYS_GPIO_RS232_FORCEOFF)) +#define CONFIG_SYS_GPIO_OR GPIO_VAL(CONFIG_SYS_GPIO_RS232_FORCEOFF) +#define CONFIG_SYS_GPIO_TCR GPIO_VAL(CONFIG_SYS_GPIO_RS232_FORCEOFF) +#define CONFIG_SYS_GPIO_ODR 0 + +#endif /* __CONFIG_H */ |