diff options
| -rw-r--r-- | Makefile | 2 | ||||
| -rw-r--r-- | board/mpc7448hpc2/Makefile | 20 | ||||
| -rw-r--r-- | board/mpc7448hpc2/asm_init.S | 1143 | ||||
| -rw-r--r-- | board/mpc7448hpc2/mpc7448hpc2.c | 152 | ||||
| -rw-r--r-- | board/mpc7448hpc2/tsi108_init.c | 421 | ||||
| -rw-r--r-- | cpu/74xx_7xx/cpu.c | 16 | ||||
| -rw-r--r-- | cpu/74xx_7xx/speed.c | 82 | ||||
| -rw-r--r-- | doc/README.mpc7448hpc2 | 206 | ||||
| -rw-r--r-- | drivers/tsi108_eth.c | 835 | ||||
| -rw-r--r-- | drivers/tsi108_i2c.c | 60 | ||||
| -rw-r--r-- | drivers/tsi108_pci.c | 34 | ||||
| -rw-r--r-- | include/configs/mpc7448hpc2.h | 290 | ||||
| -rw-r--r-- | include/tsi108.h | 280 |
13 files changed, 1747 insertions, 1794 deletions
@@ -1722,7 +1722,7 @@ EVB64260_750CX_config: unconfig @$(MKCONFIG) EVB64260 ppc 74xx_7xx evb64260 mpc7448hpc2_config: unconfig - @./mkconfig $(@:_config=) ppc 74xx_7xx mpc7448hpc2 + @$(MKCONFIG) $(@:_config=) ppc 74xx_7xx mpc7448hpc2 P3G4_config: unconfig @$(MKCONFIG) $(@:_config=) ppc 74xx_7xx evb64260 diff --git a/board/mpc7448hpc2/Makefile b/board/mpc7448hpc2/Makefile index d5ed01f..e3d757d 100644 --- a/board/mpc7448hpc2/Makefile +++ b/board/mpc7448hpc2/Makefile @@ -23,26 +23,30 @@ include $(TOPDIR)/config.mk -LIB = lib$(BOARD).a +LIB = $(obj)lib$(BOARD).a -OBJS = $(BOARD).o tsi108_init.o +COBJS := $(BOARD).o tsi108_init.o +SOBJS := asm_init.o -SOBJS = asm_init.o +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) -$(LIB): .depend $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) $(SOBJS) +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) clean: rm -f $(SOBJS) $(OBJS) +.PHONY: distclean distclean: clean rm -f $(LIB) core *.bak .depend ######################################################################### -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ +# defines $(obj).depend target +include $(SRCTREE)/rules.mk -sinclude .depend +sinclude ($obj).depend ######################################################################### diff --git a/board/mpc7448hpc2/asm_init.S b/board/mpc7448hpc2/asm_init.S index 8c15a3d..a7a40a1 100644 --- a/board/mpc7448hpc2/asm_init.S +++ b/board/mpc7448hpc2/asm_init.S @@ -1,10 +1,10 @@ -/***************************************************************************** +/* * (C) Copyright 2004-05; Tundra Semiconductor Corp. - * + * * Added automatic detect of SDC settings * Copyright (c) 2005 Freescale Semiconductor, Inc. * Maintainer tie-fei.zang@freescale.com - * + * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of @@ -19,9 +19,9 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA - ****************************************************************************/ + */ -/*---------------------------------------------------------------------------- +/* * FILENAME: asm_init.s * * Originator: Alex Bounine @@ -29,7 +29,7 @@ * DESCRIPTION: * Initialization code for the Tundra Tsi108 bridge chip * - *---------------------------------------------------------------------------*/ + */ #include <config.h> #include <version.h> @@ -40,15 +40,15 @@ #include <tsi108.h> -/*=========================================================================== +/* * Build Configuration Options */ -/* #define DISABLE_PBM disables usage of PB Master */ -/* #define SDC_HARDCODED_INIT config SDRAM controller with hardcoded values */ -/* #define SDC_AUTOPRECH_EN enable SDRAM auto precharge */ +/* #define DISABLE_PBM disables usage of PB Master */ +/* #define SDC_HARDCODED_INIT config SDRAM controller with hardcoded values */ +/* #define SDC_AUTOPRECH_EN enable SDRAM auto precharge */ -/* =========================================================================== +/* * Hardcoded SDC settings */ @@ -56,571 +56,543 @@ /* Micron MT9HTF6472AY-40EA1 : Unbuffered, 512MB, 400, CL3, Single Rank */ -#define VAL_SD_REFRESH (0x61A) -#define VAL_SD_TIMING (0x0308336b) -#define VAL_SD_D0_CTRL (0x07100021) /* auto-precharge disabled */ -#define VAL_SD_D0_BAR (0x0FE00000) /* 512MB @ 0x00000000 */ -#define VAL_SD_D1_CTRL (0x07100021) /* auto-precharge disabled */ -#define VAL_SD_D1_BAR (0x0FE00200) /* 512MB @ 0x20000000 */ +#define VAL_SD_REFRESH (0x61A) +#define VAL_SD_TIMING (0x0308336b) +#define VAL_SD_D0_CTRL (0x07100021) /* auto-precharge disabled */ +#define VAL_SD_D0_BAR (0x0FE00000) /* 512MB @ 0x00000000 */ +#define VAL_SD_D1_CTRL (0x07100021) /* auto-precharge disabled */ +#define VAL_SD_D1_BAR (0x0FE00200) /* 512MB @ 0x20000000 */ #endif /* SDC_HARDCODED_INIT */ -/*--------------------------------------------------------------------------- +/* CPU Configuration: CPU Address and Data Parity enables. #define CPU_AP #define CPU_DP +*/ -=========================================================================== - Macros - - !!! Attention !!! Macros LOAD_PTR, LOAD_U32 and LOAD_MEM defined below are - expected to work correctly for the CSR space within 32KB range. - - LOAD_PTR and LOAD_U32 - load specified register with a 32 bit constant. - These macros are absolutely identical except their names. This difference - is provided intentionally for better readable code. - -------------------------------------------------------------------------*/ +/* + * Macros + * !!! Attention !!! Macros LOAD_PTR, LOAD_U32 and LOAD_MEM defined below are + * expected to work correctly for the CSR space within 32KB range. + * + * LOAD_PTR and LOAD_U32 - load specified register with a 32 bit constant. + * These macros are absolutely identical except their names. This difference + * is provided intentionally for better readable code. + */ #define LOAD_PTR(reg,const32) \ - addis reg,r0,const32@h; ori reg,reg,const32@l + addis reg,r0,const32@h; ori reg,reg,const32@l #define LOAD_U32(reg,const32) \ - addis reg,r0,const32@h; ori reg,reg,const32@l + addis reg,r0,const32@h; ori reg,reg,const32@l -/* LOADMEM initializes a register with the contents of a specified 32-bit memory - location, usually a CSR value.*/ +/* LOADMEM initializes a register with the contents of a specified 32-bit + * memory location, usually a CSR value. + */ #define LOAD_MEM(reg,addr32) \ - addis reg,r0,addr32@ha; lwz reg,addr32@l(reg) + addis reg,r0,addr32@ha; lwz reg,addr32@l(reg) #ifndef SDC_HARDCODED_INIT sdc_clk_sync: /* MHz: 0,0,183,100,133,167,200,233 */ - .long 0,0, 6, 10, 8, 6, 5, 4 /* nSec */ + .long 0, 0, 6, 10, 8, 6, 5, 4 /* nSec */ #endif -/*=========================================================================== - board_asm_init() - early initialization function. Coded to be portable to - dual-CPU configuration. - Checks CPU number and performs board HW initialization if called for CPU0. - - Registers used: r3,r4,r5,r6,r19,r29 -=========================================================================== - ---------------------------------------------------------------------------- - NOTE: For dual-CPU configuration only CPU0 is allowed to configure Tsi108 - and the rest of the board. Current implementation demonstrates two - possible ways to identify CPU number: - - for MPC74xx platform: uses MSSCR0[ID] bit as defined in UM. - - for PPC750FX/GX boards: uses WHO_AM_I bit reported by Tsi108. ----------------------------------------------------------------------------*/ +/* + * board_asm_init() - early initialization function. Coded to be portable to + * dual-CPU configuration. + * Checks CPU number and performs board HW initialization if called for CPU0. + * Registers used: r3,r4,r5,r6,r19,r29 + * + * NOTE: For dual-CPU configuration only CPU0 is allowed to configure Tsi108 + * and the rest of the board. Current implementation demonstrates two + * possible ways to identify CPU number: + * - for MPC74xx platform: uses MSSCR0[ID] bit as defined in UM. + * - for PPC750FX/GX boards: uses WHO_AM_I bit reported by Tsi108. + */ - .globl board_asm_init + .globl board_asm_init board_asm_init: + mflr r19 /* Save LR to be able return later. */ + bl icache_enable /* Enable icache to reduce reads from flash. */ - mflr r19 /* Save LR to be able return later. */ - - bl icache_enable /* Enable icache to reduce reads from flash. */ +/* Initialize pointer to Tsi108 register space */ - /* Initialize pointer to Tsi108 register space - -------------------------------------------------------------------------*/ + LOAD_PTR(r29,CFG_TSI108_CSR_RST_BASE)/* r29 - pointer to tsi108 CSR space */ + ori r4,r29,TSI108_PB_REG_OFFSET - LOAD_PTR(r29,CFG_TSI108_CSR_RST_BASE)/* r29 - pointer to tsi108 CSR space */ - ori r4,r29,TSI108_PB_REG_OFFSET +/* Check Processor Version Number */ - /*------------------------------------------------------------------------- - Check Processor Version Number */ + mfspr r3, PVR + rlwinm r3,r3,16,16,23 /* get ((Processor Version Number) & 0xFF00) */ - mfspr r3, PVR - rlwinm r3,r3,16,16,23 /* get ((Processor Version Number) & 0xFF00) */ + cmpli 0,0,r3,0x8000 /* MPC74xx */ + bne cont_brd_init - cmpli 0,0,r3,0x8000 /* MPC74xx */ - bne cont_brd_init - - /* ------------------------------------------ - For MPC744x/5x enable extended BATs[4-7] - Sri: Set HIGH_BAT_EN and XBSEN, and SPD =1 - to disable prefetch - */ - - mfspr r5, HID0 - oris r5, r5, 0x0080 /* Set HID0[HIGH_BAT_EN] bit #8 */ - ori r5, r5, 0x0380 /* Set SPD,XBSEN,SGE bits #22,23,24 */ - mtspr HID0, r5 - isync - sync + /* + * For MPC744x/5x enable extended BATs[4-7] + * Sri: Set HIGH_BAT_EN and XBSEN, and SPD =1 + * to disable prefetch + */ - /* Adding code to disable external interventions in MPX bus mode */ - mfspr r3, 1014 - oris r3, r3, 0x0100 /* Set the EIDIS bit in MSSCR0: bit 7 */ - mtspr 1014, r3 - isync - sync + mfspr r5, HID0 + oris r5, r5, 0x0080 /* Set HID0[HIGH_BAT_EN] bit #8 */ + ori r5, r5, 0x0380 /* Set SPD,XBSEN,SGE bits #22,23,24 */ + mtspr HID0, r5 + isync + sync - /* Sri: code to enable FP unit */ - mfmsr r3 - ori r3, r3, 0x2000 - mtmsr r3 - isync - sync + /* Adding code to disable external interventions in MPX bus mode */ + mfspr r3, 1014 + oris r3, r3, 0x0100 /* Set the EIDIS bit in MSSCR0: bit 7 */ + mtspr 1014, r3 + isync + sync -#if(1) /* def CONFIG_DUAL_CPU - ------------------------------------------------------------------------- - For MPC74xx processor, use MSSCR0[ID] bit to identify CPU number. - */ + /* Sri: code to enable FP unit */ + mfmsr r3 + ori r3, r3, 0x2000 + mtmsr r3 + isync + sync - mfspr r3,1014 /* read MSSCR0 */ - rlwinm. r3,r3,27,31,31 /* get processor ID number */ - mtspr SPRN_PIR,r3 /* Save CPU ID */ - sync - bne init_done - b do_tsi108_init + /* def CONFIG_DUAL_CPU + * For MPC74xx processor, use MSSCR0[ID] bit to identify CPU number. + */ +#if(1) + mfspr r3,1014 /* read MSSCR0 */ + rlwinm. r3,r3,27,31,31 /* get processor ID number */ + mtspr SPRN_PIR,r3 /* Save CPU ID */ + sync + bne init_done + b do_tsi108_init cont_brd_init: - /* An alternative method of checking the processor number (in addition - to configuration using MSSCR0[ID] bit on MPC74xx). - Good for IBM PPC750FX/GX. - */ - - lwz r3,PB_BUS_MS_SELECT(r4) /* read PB_ID register */ - rlwinm. r3,r3,24,31,31 /* get processor ID number */ - - bne init_done + /* An alternative method of checking the processor number (in addition + * to configuration using MSSCR0[ID] bit on MPC74xx). + * Good for IBM PPC750FX/GX. + */ + lwz r3,PB_BUS_MS_SELECT(r4) /* read PB_ID register */ + rlwinm. r3,r3,24,31,31 /* get processor ID number */ + bne init_done #else cont_brd_init: #endif /* CONFIG_DUAL_CPU */ - /* Initialize Tsi108 chip - --------------------------------------------------------------------------- - */ + /* Initialize Tsi108 chip */ do_tsi108_init: - /*-------------------------------------------------------------------------- - Adjust HLP/Flash parameters. By default after reset the HLP port is set - to support slow devices. Better performance can be achived when an optimal - parameters are used for specific EPROM device. - NOTE: This should be performed ASAP for the emulation platform because - it has 5MHz HLP clocking. - */ + /* + * Adjust HLP/Flash parameters. By default after reset the HLP port is + * set to support slow devices. Better performance can be achived when + * an optimal parameters are used for specific EPROM device. + * NOTE: This should be performed ASAP for the emulation platform + * because it has 5MHz HLP clocking. + */ #ifdef CONFIG_TSI108EMU - ori r4,r29,TSI108_HLP_REG_OFFSET - LOAD_U32(r5,0x434422c0) - stw r5,0x08(r4) /* set HLP B0_CTRL0 */ - sync - LOAD_U32(r5,0xd0012000) - stw r5,0x0c(r4) /* set HLP B0_CTRL1 */ - sync + ori r4,r29,TSI108_HLP_REG_OFFSET + LOAD_U32(r5,0x434422c0) + stw r5,0x08(r4) /* set HLP B0_CTRL0 */ + sync + LOAD_U32(r5,0xd0012000) + stw r5,0x0c(r4) /* set HLP B0_CTRL1 */ + sync #endif - /* ------------------------------------------------------------------------- - * Initialize PB interface. - */ + /* Initialize PB interface. */ - ori r4,r29,TSI108_PB_REG_OFFSET + ori r4,r29,TSI108_PB_REG_OFFSET #if (CFG_TSI108_CSR_BASE != CFG_TSI108_CSR_RST_BASE) - /* Relocate (if required) Tsi108 registers. Set new value for PB_REG_BAR: - * Note we are in the 32-bit address mode. - */ - LOAD_U32(r5,(CFG_TSI108_CSR_BASE | 0x01)) /* value for PB_REG_BAR: BA + EN*/ - stw r5,PB_REG_BAR(r4) - andis. r29,r5,0xFFFF - sync - - ori r4,r29,TSI108_PB_REG_OFFSET + /* Relocate (if required) Tsi108 registers. Set new value for + * PB_REG_BAR: + * Note we are in the 32-bit address mode. + */ + LOAD_U32(r5,(CFG_TSI108_CSR_BASE | 0x01)) /* PB_REG_BAR: BA + EN */ + stw r5,PB_REG_BAR(r4) + andis. r29,r5,0xFFFF + sync + ori r4,r29,TSI108_PB_REG_OFFSET #endif - /* Set PB Slave configuration register */ + /* Set PB Slave configuration register */ -/* LOAD_U32(r5,0x000024C7) value for PB_SCR: TEA enabled,AACK delay = 7 */ - LOAD_U32(r5,0x00002481) /* value for PB_SCR: TEA enabled,AACK delay = 1 */ - lwz r3, PB_RSR(r4) /* get PB bus mode */ - xori r3,r3,0x0001 /* mask PB_BMODE: r3 -> (0 = 60X, 1 = MPX) */ - rlwimi r5,r3,14,17,17 /* for MPX: set DTI_MODE bit */ - stw r5,PB_SCR(r4) - sync + LOAD_U32(r5,0x00002481) /* PB_SCR: TEA enabled,AACK delay = 1 */ + lwz r3, PB_RSR(r4) /* get PB bus mode */ + xori r3,r3,0x0001 /* mask PB_BMODE: r3 -> (0 = 60X, 1 = MPX) */ + rlwimi r5,r3,14,17,17 /* for MPX: set DTI_MODE bit */ + stw r5,PB_SCR(r4) + sync - /* Configure PB Arbiter */ + /* Configure PB Arbiter */ - lwz r5,PB_ARB_CTRL(r4) /* Read PB Arbiter Control Register */ - li r3, 0x00F0 /* ARB_PIPELINE_DEP mask */ + lwz r5,PB_ARB_CTRL(r4) /* Read PB Arbiter Control Register */ + li r3, 0x00F0 /* ARB_PIPELINE_DEP mask */ #ifdef DISABLE_PBM - ori r3,r3,0x1000 /* add PBM_EN to clear (enabled by default) */ + ori r3,r3,0x1000 /* add PBM_EN to clear (enabled by default) */ #endif - andc r5,r5,r3 /* Clear the masked bit fields */ -/* ori r5,r5,0x0040 Set pipeline depth 4 - ori r5,r5,0x0080 Set pipeline depth 8 - ori r5,r5,0x0020 !!!avb Testing: set pipeline depth 2 */ - ori r5,r5,0x0001 - stw r5,PB_ARB_CTRL(r4) - -#if (0) /* currently using the default settings for PBM after reset */ - LOAD_U32(r5,0x) /* value for PB_MCR */ - stw r5,PB_MCR(r4) - sync - - LOAD_U32(r5,0x) /* value for PB_MCMD */ - stw r5,PB_MCMD(r4) - sync + andc r5,r5,r3 /* Clear the masked bit fields */ + ori r5,r5,0x0001 /* Set pipeline depth */ + stw r5,PB_ARB_CTRL(r4) + +#if (0) /* currently using the default settings for PBM after reset */ + LOAD_U32(r5,0x) /* value for PB_MCR */ + stw r5,PB_MCR(r4) + sync + + LOAD_U32(r5,0x) /* value for PB_MCMD */ + stw r5,PB_MCMD(r4) + sync #endif -/* Disable or enable PVT based on processor bus frequency - 1. Read CG_PWRUP_STATUS register field bits 18,17,16 - 2. See if the value is < or > 133mhz (18:16 = 100) - 3. If > enable PVT - */ + /* Disable or enable PVT based on processor bus frequency + * 1. Read CG_PWRUP_STATUS register field bits 18,17,16 + * 2. See if the value is < or > 133mhz (18:16 = 100) + * 3. If > enable PVT + */ - LOAD_U32(r3,0xC0002234) - lwz r3,0(r3) - rlwinm r3,r3,16,29,31 + LOAD_U32(r3,0xC0002234) + lwz r3,0(r3) + rlwinm r3,r3,16,29,31 - cmpi 0,0,r3,0x0004 - bgt sdc_init + cmpi 0,0,r3,0x0004 + bgt sdc_init #ifndef CONFIG_TSI108EMU - /* FIXME: Disable PB calibration control for any real Tsi108 board */ - li r5,0x0101 /* disable calibration control */ - stw r5,PB_PVT_CTRL2(r4) - sync + /* FIXME: Disable PB calibration control for any real Tsi108 board */ + li r5,0x0101 /* disable calibration control */ + stw r5,PB_PVT_CTRL2(r4) + sync #endif -/*--------------------------------------------------------------------------- - Initialize SDRAM controller. -----------------------------------------------------------------------------*/ + /* Initialize SDRAM controller. */ sdc_init: #ifndef SDC_HARDCODED_INIT - /* get SDC clock prior doing sdram controller autoconfig */ - ori r4,r29,TSI108_CLK_REG_OFFSET /* r4 - ptr to CG registers */ - lwz r3, CG_PWRUP_STATUS(r4) /* get CG configuration */ - rlwinm r3,r3,12,29,31 /* r3 - SD clk */ - lis r5,sdc_clk_sync@h - ori r5,r5,sdc_clk_sync@l - /* Sri: At this point check if r3 = 001. If yes, - * the memory frequency should be same as the - * MPX bus frequency - */ - cmpi 0,0,r3,0x0001 - bne get_nsec - lwz r6, CG_PWRUP_STATUS(r4) - rlwinm r6,r6,16,29,31 - mr r3,r6 + /* get SDC clock prior doing sdram controller autoconfig */ + ori r4,r29,TSI108_CLK_REG_OFFSET /* r4 - ptr to CG registers */ + lwz r3, CG_PWRUP_STATUS(r4) /* get CG configuration */ + rlwinm r3,r3,12,29,31 /* r3 - SD clk */ + lis r5,sdc_clk_sync@h + ori r5,r5,sdc_clk_sync@l + /* Sri: At this point check if r3 = 001. If yes, + * the memory frequency should be same as the + * MPX bus frequency + */ + cmpi 0,0,r3,0x0001 + bne get_nsec + lwz r6, CG_PWRUP_STATUS(r4) + rlwinm r6,r6,16,29,31 + mr r3,r6 get_nsec: - rlwinm r3,r3,2,0,31 - lwzx r9,r5,r3 /* get SD clk rate in nSec */ - /* ATTN: r9 will be used by SPD routine */ + rlwinm r3,r3,2,0,31 + lwzx r9,r5,r3 /* get SD clk rate in nSec */ + /* ATTN: r9 will be used by SPD routine */ #endif /* !SDC_HARDCODED_INIT */ - ori r4,r29,TSI108_SD_REG_OFFSET /* r4 - ptr to SDRAM registers */ + ori r4,r29,TSI108_SD_REG_OFFSET /* r4 - ptr to SDRAM registers */ - /* Initialize SDRAM controller. SDRAM Size = 512MB, One DIMM. */ + /* Initialize SDRAM controller. SDRAM Size = 512MB, One DIMM. */ - LOAD_U32(r5,0x00) - stw r5,SD_INT_ENABLE(r4) /* Ensure that interrupts are disabled */ + LOAD_U32(r5,0x00) + stw r5,SD_INT_ENABLE(r4) /* Ensure that interrupts are disabled */ #ifdef ENABLE_SDRAM_ECC - li r5, 0x01 + li r5, 0x01 #endif /* ENABLE_SDRAM_ECC */ - stw r5,SD_ECC_CTRL(r4) /* Enable/Disable ECC */ - sync + stw r5,SD_ECC_CTRL(r4) /* Enable/Disable ECC */ + sync #ifdef SDC_HARDCODED_INIT /* config sdram controller with hardcoded values */ - /* First read the CG_PWRUP_STATUS register to get the - memory speed from bits 22,21,20 */ - - LOAD_U32(r3,0xC0002234) - lwz r3,0(r3) - rlwinm r3,r3,12,29,31 + /* First read the CG_PWRUP_STATUS register to get the + * memory speed from bits 22,21,20 + */ - /* Now first check for 166, then 200, or default */ + LOAD_U32(r3,0xC0002234) + lwz r3,0(r3) + rlwinm r3,r3,12,29,31 - cmpi 0,0,r3,0x0005 - bne check_for_200mhz + /* Now first check for 166, then 200, or default */ - /* set values for 166 Mhz memory speed */ + cmpi 0,0,r3,0x0005 + bne check_for_200mhz - /* Set refresh rate and timing parameters */ - LOAD_U32(r5,0x00000515) - stw r5,SD_REFRESH(r4) - LOAD_U32(r5,0x03073368) - stw r5,SD_TIMING(r4) - sync + /* set values for 166 Mhz memory speed + * Set refresh rate and timing parameters + */ + LOAD_U32(r5,0x00000515) + stw r5,SD_REFRESH(r4) + LOAD_U32(r5,0x03073368) + stw r5,SD_TIMING(r4) + sync - /* Initialize DIMM0 control and BAR registers */ - LOAD_U32(r5,VAL_SD_D0_CTRL) /* auto-precharge disabled */ + /* Initialize DIMM0 control and BAR registers */ + LOAD_U32(r5,VAL_SD_D0_CTRL) /* auto-precharge disabled */ #ifdef SDC_AUTOPRECH_EN - oris r5,r5,0x0001 /* set auto precharge EN bit */ + oris r5,r5,0x0001 /* set auto precharge EN bit */ #endif - stw r5,SD_D0_CTRL(r4) - LOAD_U32(r5,VAL_SD_D0_BAR) - stw r5,SD_D0_BAR(r4) - sync - - /* Initialize DIMM1 control and BAR registers - * (same as dimm 0, next 512MB, disabled) - */ - LOAD_U32(r5,VAL_SD_D1_CTRL) /* auto-precharge disabled */ + stw r5,SD_D0_CTRL(r4) + LOAD_U32(r5,VAL_SD_D0_BAR) + stw r5,SD_D0_BAR(r4) + sync + + /* Initialize DIMM1 control and BAR registers + * (same as dimm 0, next 512MB, disabled) + */ + LOAD_U32(r5,VAL_SD_D1_CTRL) /* auto-precharge disabled */ #ifdef SDC_AUTOPRECH_EN - oris r5,r5,0x0001 /* set auto precharge EN bit */ + oris r5,r5,0x0001 /* set auto precharge EN bit */ #endif - stw r5,SD_D1_CTRL(r4) - LOAD_U32(r5,VAL_SD_D1_BAR) - stw r5,SD_D1_BAR(r4) - sync + stw r5,SD_D1_CTRL(r4) + LOAD_U32(r5,VAL_SD_D1_BAR) + stw r5,SD_D1_BAR(r4) + sync - b sdc_init_done + b sdc_init_done check_for_200mhz: - cmpi 0,0,r3,0x0006 - bne set_default_values + cmpi 0,0,r3,0x0006 + bne set_default_values - /* set values for 200Mhz memory speed */ - - /* Set refresh rate and timing parameters */ - LOAD_U32(r5,0x0000061a) - stw r5,SD_REFRESH(r4) - LOAD_U32(r5,0x03083348) - stw r5,SD_TIMING(r4) - sync + /* set values for 200Mhz memory speed + * Set refresh rate and timing parameters + */ + LOAD_U32(r5,0x0000061a) + stw r5,SD_REFRESH(r4) + LOAD_U32(r5,0x03083348) + stw r5,SD_TIMING(r4) + sync - /* Initialize DIMM0 control and BAR registers */ - LOAD_U32(r5,VAL_SD_D0_CTRL) /* auto-precharge disabled */ + /* Initialize DIMM0 control and BAR registers */ + LOAD_U32(r5,VAL_SD_D0_CTRL) /* auto-precharge disabled */ #ifdef SDC_AUTOPRECH_EN - oris r5,r5,0x0001 /* set auto precharge EN bit */ + oris r5,r5,0x0001 /* set auto precharge EN bit */ #endif - stw r5,SD_D0_CTRL(r4) - LOAD_U32(r5,VAL_SD_D0_BAR) - stw r5,SD_D0_BAR(r4) - sync - - /* Initialize DIMM1 control and BAR registers - * (same as dimm 0, next 512MB, disabled) - */ - LOAD_U32(r5,VAL_SD_D1_CTRL) /* auto-precharge disabled */ + stw r5,SD_D0_CTRL(r4) + LOAD_U32(r5,VAL_SD_D0_BAR) + stw r5,SD_D0_BAR(r4) + sync + + /* Initialize DIMM1 control and BAR registers + * (same as dimm 0, next 512MB, disabled) + */ + LOAD_U32(r5,VAL_SD_D1_CTRL) /* auto-precharge disabled */ #ifdef SDC_AUTOPRECH_EN - oris r5,r5,0x0001 /* set auto precharge EN bit */ + oris r5,r5,0x0001 /* set auto precharge EN bit */ #endif - stw r5,SD_D1_CTRL(r4) - LOAD_U32(r5,VAL_SD_D1_BAR) - stw r5,SD_D1_BAR(r4) - sync + stw r5,SD_D1_CTRL(r4) + LOAD_U32(r5,VAL_SD_D1_BAR) + stw r5,SD_D1_BAR(r4) + sync - b sdc_init_done + b sdc_init_done set_default_values: - /* Set refresh rate and timing parameters */ - LOAD_U32(r5,VAL_SD_REFRESH) - stw r5,SD_REFRESH(r4) - LOAD_U32(r5,VAL_SD_TIMING) - stw r5,SD_TIMING(r4) - sync + /* Set refresh rate and timing parameters */ + LOAD_U32(r5,VAL_SD_REFRESH) + stw r5,SD_REFRESH(r4) + LOAD_U32(r5,VAL_SD_TIMING) + stw r5,SD_TIMING(r4) + sync - /* Initialize DIMM0 control and BAR registers */ - LOAD_U32(r5,VAL_SD_D0_CTRL) /* auto-precharge disabled */ + /* Initialize DIMM0 control and BAR registers */ + LOAD_U32(r5,VAL_SD_D0_CTRL) /* auto-precharge disabled */ #ifdef SDC_AUTOPRECH_EN - oris r5,r5,0x0001 /* set auto precharge EN bit */ + oris r5,r5,0x0001 /* set auto precharge EN bit */ #endif - stw r5,SD_D0_CTRL(r4) - LOAD_U32(r5,VAL_SD_D0_BAR) - stw r5,SD_D0_BAR(r4) - sync - - /* Initialize DIMM1 control and BAR registers - * (same as dimm 0, next 512MB, disabled) - */ - LOAD_U32(r5,VAL_SD_D1_CTRL) /* auto-precharge disabled */ + stw r5,SD_D0_CTRL(r4) + LOAD_U32(r5,VAL_SD_D0_BAR) + stw r5,SD_D0_BAR(r4) + sync + + /* Initialize DIMM1 control and BAR registers + * (same as dimm 0, next 512MB, disabled) + */ + LOAD_U32(r5,VAL_SD_D1_CTRL) /* auto-precharge disabled */ #ifdef SDC_AUTOPRECH_EN - oris r5,r5,0x0001 /* set auto precharge EN bit */ + oris r5,r5,0x0001 /* set auto precharge EN bit */ #endif - stw r5,SD_D1_CTRL(r4) - LOAD_U32(r5,VAL_SD_D1_BAR) - stw r5,SD_D1_BAR(r4) - sync - + stw r5,SD_D1_CTRL(r4) + LOAD_U32(r5,VAL_SD_D1_BAR) + stw r5,SD_D1_BAR(r4) + sync #else /* !SDC_HARDCODED_INIT */ - - bl tsi108_sdram_spd /* automatically detect SDC settings */ - + bl tsi108_sdram_spd /* automatically detect SDC settings */ #endif /* SDC_HARDCODED_INIT */ sdc_init_done: #ifdef DISABLE_PBM - LOAD_U32(r5,0x00000030) /* PB_EN + OCN_EN */ + LOAD_U32(r5,0x00000030) /* PB_EN + OCN_EN */ #else - LOAD_U32(r5,0x00000230) /* PB_EN + OCN_EN + PB/OCN=80/20 */ + LOAD_U32(r5,0x00000230) /* PB_EN + OCN_EN + PB/OCN=80/20 */ #endif /* DISABLE_PBM */ #ifdef CONFIG_TSI108EMU - oris r5,r5,0x0010 /* set EMULATION_MODE bit */ + oris r5,r5,0x0010 /* set EMULATION_MODE bit */ #endif - stw r5,SD_CTRL(r4) - eieio - sync + stw r5,SD_CTRL(r4) + eieio + sync - /* Enable SDRAM access */ + /* Enable SDRAM access */ - oris r5,r5,0x8000 /* start SDC: set SD_CTRL[ENABLE] bit */ - stw r5,SD_CTRL(r4) - sync + oris r5,r5,0x8000 /* start SDC: set SD_CTRL[ENABLE] bit */ + stw r5,SD_CTRL(r4) + sync wait_init_complete: - lwz r5,SD_STATUS(r4) - andi. r5,r5,0x0001 - beq wait_init_complete /* wait until SDRAM initialization is complete */ - -/*--------------------------------------------------------------------------- - Map SDRAM into the processor bus address space ----------------------------------------------------------------------------*/ + lwz r5,SD_STATUS(r4) + andi. r5,r5,0x0001 + /* wait until SDRAM initialization is complete */ + beq wait_init_complete - ori r4,r29,TSI108_PB_REG_OFFSET + /* Map SDRAM into the processor bus address space */ - /* Setup BARs associated with direct path PB<->SDRAM */ + ori r4,r29,TSI108_PB_REG_OFFSET - /* PB_SDRAM_BAR1: - provides a direct path to the main system memory (cacheable SDRAM) */ + /* Setup BARs associated with direct path PB<->SDRAM */ - LOAD_U32(r5, 0x00000011) /* BA=0,Size=512MB, ENable, No Addr.Translation */ - stw r5,PB_SDRAM_BAR1(r4) - sync + /* PB_SDRAM_BAR1: + * provides a direct path to the main system memory (cacheable SDRAM) + */ - /* Make sure that PB_SDRAM_BAR1 decoder is set - (to allow following immediate read from SDRAM) */ - lwz r5,PB_SDRAM_BAR1(r4) - sync + /* BA=0,Size=512MB, ENable, No Addr.Translation */ + LOAD_U32(r5, 0x00000011) + stw r5,PB_SDRAM_BAR1(r4) + sync - /* PB_SDRAM_BAR2: - provides non-cacheable alias (via the direct path) to main system memory. - Size = 512MB, ENable, Addr.Translation - ON, - BA = 0x0_40000000, TA = 0x0_00000000 */ + /* Make sure that PB_SDRAM_BAR1 decoder is set + * (to allow following immediate read from SDRAM) + */ + lwz r5,PB_SDRAM_BAR1(r4) + sync - LOAD_U32(r5, 0x40010011) - stw r5,PB_SDRAM_BAR2(r4) - sync + /* PB_SDRAM_BAR2: + * provides non-cacheable alias (via the direct path) to main + * system memory. + * Size = 512MB, ENable, Addr.Translation - ON, + * BA = 0x0_40000000, TA = 0x0_00000000 + */ - /* Make sure that PB_SDRAM_BAR2 decoder is set - (to allow following immediate read from SDRAM) */ - lwz r5,PB_SDRAM_BAR2(r4) - sync + LOAD_U32(r5, 0x40010011) + stw r5,PB_SDRAM_BAR2(r4) + sync + /* Make sure that PB_SDRAM_BAR2 decoder is set + * (to allow following immediate read from SDRAM) + */ + lwz r5,PB_SDRAM_BAR2(r4) + sync init_done: - /* All done. Restore LR and return. */ - mtlr r19 - blr + /* All done. Restore LR and return. */ + mtlr r19 + blr #if (0) -/*=========================================================================== - init_cpu1 - - This routine enables CPU1 on the dual-processor system. -===========================================================================*/ + /* + * init_cpu1 + * This routine enables CPU1 on the dual-processor system. + * Now there is only one processor in the system + */ - .global enable_cpu1 + .global enable_cpu1 enable_cpu1: - lis r3,Tsi108_Base@ha /* Get Grendel CSR Base Addr */ - addi r3,r3,Tsi108_Base@l - lwz r3,0(r3) /* R3 = CSR Base Addr */ - ori r4,r3,TSI108_PB_REG_OFFSET - lwz r3,PB_ARB_CTRL(r4) /* Read PB Arbiter Control Register */ - ori r3,r3,0x0200 /* Set M1_EN bit */ - stw r3,PB_ARB_CTRL(r4) + lis r3,Tsi108_Base@ha /* Get Grendel CSR Base Addr */ + addi r3,r3,Tsi108_Base@l + lwz r3,0(r3) /* R3 = CSR Base Addr */ + ori r4,r3,TSI108_PB_REG_OFFSET + lwz r3,PB_ARB_CTRL(r4) /* Read PB Arbiter Control Register */ + ori r3,r3,0x0200 /* Set M1_EN bit */ + stw r3,PB_ARB_CTRL(r4) - blr + blr #endif -/*=========================================================================== - enable_EI - - Enable CPU core external interrupt -===========================================================================*/ + /* + * enable_EI + * Enable CPU core external interrupt + */ - .global enable_EI + .global enable_EI enable_EI: - mfmsr r3 - ori r3,r3,0x8000 /* set EE bit */ - mtmsr r3 - blr - -/*=========================================================================== - disable_EI + mfmsr r3 + ori r3,r3,0x8000 /* set EE bit */ + mtmsr r3 + blr - Disable CPU core external interrupt -===========================================================================*/ + /* + * disable_EI + * Disable CPU core external interrupt + */ - .global disable_EI + .global disable_EI disable_EI: - mfmsr r3 - li r4,-32768 /* aka "li r4,0x8000" */ - andc r3,r3,r4 /* clear EE bit */ - mtmsr r3 - blr + mfmsr r3 + li r4,-32768 /* aka "li r4,0x8000" */ + andc r3,r3,r4 /* clear EE bit */ + mtmsr r3 + blr #ifdef ENABLE_SDRAM_ECC -/*=========================================================================== - enable_ECC + /* enables SDRAM ECC */ - enables SDRAM ECC -===========================================================================*/ - - .global enable_ECC + .global enable_ECC enable_ECC: - ori r4,r29,TSI108_SD_REG_OFFSET - lwz r3,SD_ECC_CTRL(r4) /* Read SDRAM ECC Control Register */ - ori r3,r3,0x0001 /* Set ECC_EN bit */ - stw r3,SD_ECC_CTRL(r4) - blr - -/*=========================================================================== - clear_ECC_err + ori r4,r29,TSI108_SD_REG_OFFSET + lwz r3,SD_ECC_CTRL(r4) /* Read SDRAM ECC Control Register */ + ori r3,r3,0x0001 /* Set ECC_EN bit */ + stw r3,SD_ECC_CTRL(r4) + blr - Clears all pending SDRAM ECC errors - (normally after SDRAM scrubbing/initialization) -===========================================================================*/ + /* + * clear_ECC_err + * Clears all pending SDRAM ECC errors + * (normally after SDRAM scrubbing/initialization) + */ - .global clear_ECC_err + .global clear_ECC_err clear_ECC_err: - ori r4,r29,TSI108_SD_REG_OFFSET -/* lwz r3,SD_INT_STATUS(r4) Read SDRAM ECC Control Register */ - ori r3,r0,0x0030 /* ECC_UE_INT + ECC_CE_INT bits */ - stw r3,SD_INT_STATUS(r4) - blr + ori r4,r29,TSI108_SD_REG_OFFSET + ori r3,r0,0x0030 /* ECC_UE_INT + ECC_CE_INT bits */ + stw r3,SD_INT_STATUS(r4) + blr #endif /* ENABLE_SDRAM_ECC */ #ifndef SDC_HARDCODED_INIT -/******************************************************************** - * SDRAM SPD Support - */ - + /* SDRAM SPD Support */ #define SD_I2C_CTRL1 (0x400) #define SD_I2C_CTRL2 (0x404) #define SD_I2C_RD_DATA (0x408) -#define SD_I2C_WR_DATA (0x40C) +#define SD_I2C_WR_DATA (0x40C) -/* - * SDRAM SPD Support Macros - */ + /* + * SDRAM SPD Support Macros + */ #define SPD_DIMM0 (0x00000100) -#define SPD_DIMM1 (0x00000200) /* SPD_DIMM1 was 0x00000000 */ +#define SPD_DIMM1 (0x00000200) /* SPD_DIMM1 was 0x00000000 */ #define SPD_RDIMM (0x01) #define SPD_UDIMM (0x02) @@ -651,30 +623,30 @@ clear_ECC_err: * r10 - number of DDR slot where first SPD device is detected */ -#define READ_SPD(byte_num) \ - addis r3, 0, byte_num@l;\ - or r3, r3, r10;\ - ori r3, r3, 0x0A;\ - stw r3, SD_I2C_CTRL1(r4);\ - li r3, I2C_CNTRL2_START;\ - stw r3, SD_I2C_CTRL2(r4);\ - eieio;\ - sync;\ - li r3, 0x100;\ -1: ;\ - addic. r3, r3, -1;\ - bne 1b;\ -2: ;\ - lwz r5, SD_I2C_CTRL2(r4);\ - rlwinm. r3,r5,0,23,23;\ - bne 2b;\ - rlwinm. r3,r5,0,3,3;\ - lwz r3, SD_I2C_RD_DATA(r4) +#define READ_SPD(byte_num) \ + addis r3, 0, byte_num@l; \ + or r3, r3, r10; \ + ori r3, r3, 0x0A; \ + stw r3, SD_I2C_CTRL1(r4); \ + li r3, I2C_CNTRL2_START; \ + stw r3, SD_I2C_CTRL2(r4); \ + eieio; \ + sync; \ + li r3, 0x100; \ +1:; \ + addic. r3, r3, -1; \ + bne 1b; \ +2:; \ + lwz r5, SD_I2C_CTRL2(r4); \ + rlwinm. r3,r5,0,23,23; \ + bne 2b; \ + rlwinm. r3,r5,0,3,3; \ + lwz r3,SD_I2C_RD_DATA(r4) #define SPD_MIN_RFRSH (0x80) #define SPD_MAX_RFRSH (0x85) -refresh_rates: /* in nSec */ +refresh_rates: /* in nSec */ .long 15625 /* Normal (0x80) */ .long 3900 /* Reduced 0.25x (0x81) */ .long 7800 /* Reduced 0.5x (0x82) */ @@ -682,274 +654,265 @@ refresh_rates: /* in nSec */ .long 62500 /* Extended 4x (0x84) */ .long 125000 /* Extended 8x (0x85) */ -/*=========================================================================== +/* * tsi108_sdram_spd * * Inittializes SDRAM Controller using DDR2 DIMM Serial Presence Detect data * Uses registers: r4 - SDC base address (not changed) * r9 - SDC clocking period in nSec * Changes registers: r3,r5,r6,r7,r8,r10,r11 - *==========================================================================*/ + */ tsi108_sdram_spd: - li r10,SPD_DIMM0 + li r10,SPD_DIMM0 xor r11,r11,r11 /* DIMM Base Address: starts from 0 */ do_first_dimm: - /************************************** - * Program Refresh Rate Register - */ + /* Program Refresh Rate Register */ + + READ_SPD(12) /* get Refresh Rate */ + beq check_next_slot + li r5, ERR_RFRSH_RATE + cmpi 0,0,r3,SPD_MIN_RFRSH + ble spd_fail + cmpi 0,0,r3,SPD_MAX_RFRSH + bgt spd_fail + addi r3,r3,-SPD_MIN_RFRSH + rlwinm r3,r3,2,0,31 + lis r5,refresh_rates@h + ori r5,r5,refresh_rates@l + lwzx r5,r5,r3 /* get refresh rate in nSec */ + divwu r5,r5,r9 /* calculate # of SDC clocks */ + stw r5,SD_REFRESH(r4) /* Set refresh rate */ + sync - READ_SPD(12) /* get Refresh Rate */ - beq check_next_slot - li r5, ERR_RFRSH_RATE - cmpi 0,0,r3,SPD_MIN_RFRSH - ble spd_fail - cmpi 0,0,r3,SPD_MAX_RFRSH - bgt spd_fail - addi r3,r3,-SPD_MIN_RFRSH - rlwinm r3,r3,2,0,31 - lis r5,refresh_rates@h - ori r5,r5,refresh_rates@l - lwzx r5,r5,r3 /* get refresh rate in nSec */ - divwu r5,r5,r9 /* calculate # of SDC clocks */ - stw r5,SD_REFRESH(r4) /* Set refresh rate */ - sync - - /************************************** - * Program SD Timing Register - */ + /* Program SD Timing Register */ - li r7, 0 /* clear r7 prior parameter collection */ + li r7, 0 /* clear r7 prior parameter collection */ - READ_SPD(20) /* get DIMM type: Registered or Unbuffered */ + READ_SPD(20) /* get DIMM type: Registered or Unbuffered */ beq spd_read_fail - li r5, ERR_DIMM_TYPE - cmpi 0,0,r3,SPD_UDIMM - beq do_cl - cmpi 0,0,r3,SPD_RDIMM - bne spd_fail - oris r7,r7,0x1000 /* set SD_TIMING[DIMM_TYPE] bit */ + li r5, ERR_DIMM_TYPE + cmpi 0,0,r3,SPD_UDIMM + beq do_cl + cmpi 0,0,r3,SPD_RDIMM + bne spd_fail + oris r7,r7,0x1000 /* set SD_TIMING[DIMM_TYPE] bit */ do_cl: - READ_SPD(18) /* Get CAS Latency */ + READ_SPD(18) /* Get CAS Latency */ beq spd_read_fail - li r5,ERR_CL_VALUE - andi. r6,r3,SPD_CAS_3 - beq cl_4 - li r6,3 - b set_cl + li r5,ERR_CL_VALUE + andi. r6,r3,SPD_CAS_3 + beq cl_4 + li r6,3 + b set_cl cl_4: - andi. r6,r3,SPD_CAS_4 - beq cl_5 - li r6,4 - b set_cl + andi. r6,r3,SPD_CAS_4 + beq cl_5 + li r6,4 + b set_cl cl_5: - andi. r6,r3,SPD_CAS_5 - beq spd_fail - li r6,5 + andi. r6,r3,SPD_CAS_5 + beq spd_fail + li r6,5 set_cl: - rlwimi r7,r6,24,5,7 + rlwimi r7,r6,24,5,7 - READ_SPD(30) /* Get tRAS */ + READ_SPD(30) /* Get tRAS */ beq spd_read_fail - divwu r6,r3,r9 - mullw r8,r6,r9 - subf. r8,r8,r3 + divwu r6,r3,r9 + mullw r8,r6,r9 + subf. r8,r8,r3 beq set_tras - addi r6,r6,1 + addi r6,r6,1 set_tras: li r5,ERR_TRAS_FAIL - cmpi 0,0,r6,0x0F /* max supported value */ - bgt spd_fail - rlwimi r7,r6,16,12,15 + cmpi 0,0,r6,0x0F /* max supported value */ + bgt spd_fail + rlwimi r7,r6,16,12,15 READ_SPD(29) /* Get tRCD */ beq spd_read_fail - rlwinm r3,r3,30,2,31/* right shift tRCD by 2 bits as per DDR2 spec */ - divwu r6,r3,r9 - mullw r8,r6,r9 - subf. r8,r8,r3 + /* right shift tRCD by 2 bits as per DDR2 spec */ + rlwinm r3,r3,30,2,31 + divwu r6,r3,r9 + mullw r8,r6,r9 + subf. r8,r8,r3 beq set_trcd - addi r6,r6,1 + addi r6,r6,1 set_trcd: - li r5,ERR_TRCD_FAIL - cmpi 0,0,r6,0x07 /* max supported value */ - bgt spd_fail - rlwimi r7,r6,12,17,19 + li r5,ERR_TRCD_FAIL + cmpi 0,0,r6,0x07 /* max supported value */ + bgt spd_fail + rlwimi r7,r6,12,17,19 READ_SPD(27) /* Get tRP value */ beq spd_read_fail - rlwinm r3,r3,30,2,31 /* right shift tRP by 2 bits as per DDR2 spec */ - divwu r6,r3,r9 - mullw r8,r6,r9 - subf. r8,r8,r3 + rlwinm r3,r3,30,2,31 /* right shift tRP by 2 bits as per DDR2 spec */ + divwu r6,r3,r9 + mullw r8,r6,r9 + subf. r8,r8,r3 beq set_trp - addi r6,r6,1 + addi r6,r6,1 set_trp: - li r5,ERR_TRP_FAIL - cmpi 0,0,r6,0x07 /* max supported value */ - bgt spd_fail - rlwimi r7,r6,8,21,23 + li r5,ERR_TRP_FAIL + cmpi 0,0,r6,0x07 /* max supported value */ + bgt spd_fail + rlwimi r7,r6,8,21,23 READ_SPD(36) /* Get tWR value */ beq spd_read_fail - rlwinm r3,r3,30,2,31 /* right shift tWR by 2 bits as per DDR2 spec */ - divwu r6,r3,r9 - mullw r8,r6,r9 - subf. r8,r8,r3 + rlwinm r3,r3,30,2,31 /* right shift tWR by 2 bits as per DDR2 spec */ + divwu r6,r3,r9 + mullw r8,r6,r9 + subf. r8,r8,r3 beq set_twr - addi r6,r6,1 + addi r6,r6,1 set_twr: - addi r6,r6,-1 /* Tsi108 SDC always gives one extra clock */ - li r5,ERR_TWR_FAIL - cmpi 0,0,r6,0x07 /* max supported value */ - bgt spd_fail - rlwimi r7,r6,5,24,26 + addi r6,r6,-1 /* Tsi108 SDC always gives one extra clock */ + li r5,ERR_TWR_FAIL + cmpi 0,0,r6,0x07 /* max supported value */ + bgt spd_fail + rlwimi r7,r6,5,24,26 READ_SPD(42) /* Get tRFC */ beq spd_read_fail - li r5, ERR_TRFC_FAIL + li r5, ERR_TRFC_FAIL /* Tsi108 spec: tRFC=(tRFC + 1)/2 */ - addi r3,r3,1 - rlwinm. r3,r3,31,1,31 /* divide by 2 */ - beq spd_fail - divwu r6,r3,r9 - mullw r8,r6,r9 - subf. r8,r8,r3 + addi r3,r3,1 + rlwinm. r3,r3,31,1,31 /* divide by 2 */ + beq spd_fail + divwu r6,r3,r9 + mullw r8,r6,r9 + subf. r8,r8,r3 beq set_trfc - addi r6,r6,1 + addi r6,r6,1 set_trfc: - cmpi 0,0,r6,0x1F /* max supported value */ - bgt spd_fail - rlwimi r7,r6,0,27,31 + cmpi 0,0,r6,0x1F /* max supported value */ + bgt spd_fail + rlwimi r7,r6,0,27,31 stw r7,SD_TIMING(r4) sync - /*===================================================================== + /* * The following two registers are set on per-DIMM basis. * The SD_REFRESH and SD_TIMING settings are common for both DIMMS - *===================================================================== */ do_each_dimm: - /***************************************** - * Program SDRAM DIMM Control Register - */ + /* Program SDRAM DIMM Control Register */ - li r7, 0 /* clear r7 prior parameter collection */ + li r7, 0 /* clear r7 prior parameter collection */ READ_SPD(13) /* Get Primary SDRAM Width */ beq spd_read_fail - cmpi 0,0,r3,4 /* Check for 4-bit SDRAM */ - beq do_nbank - oris r7,r7,0x0010 /* Set MEM_WIDTH bit */ + cmpi 0,0,r3,4 /* Check for 4-bit SDRAM */ + beq do_nbank + oris r7,r7,0x0010 /* Set MEM_WIDTH bit */ do_nbank: READ_SPD(17) /* Get Number of banks on SDRAM device */ beq spd_read_fail /* Grendel only distinguish betw. 4 or 8-bank memory parts */ - li r5,ERR_UNKNOWN_PART /* non-supported memory part */ - cmpi 0,0,r3,4 - beq do_nrank - cmpi 0,0,r3,8 - bne spd_fail - ori r7,r7,0x1000 + li r5,ERR_UNKNOWN_PART /* non-supported memory part */ + cmpi 0,0,r3,4 + beq do_nrank + cmpi 0,0,r3,8 + bne spd_fail + ori r7,r7,0x1000 do_nrank: - READ_SPD(5) /* Get # of Ranks */ + READ_SPD(5) /* Get # of Ranks */ beq spd_read_fail - li r5,ERR_NRANK_INVALID - andi. r6,r3,0x7 /* Use bits [2..0] only */ - beq do_addr_mode - cmpi 0,0,r6,1 - bgt spd_fail - rlwimi r7,r6,8,23,23 + li r5,ERR_NRANK_INVALID + andi. r6,r3,0x7 /* Use bits [2..0] only */ + beq do_addr_mode + cmpi 0,0,r6,1 + bgt spd_fail + rlwimi r7,r6,8,23,23 do_addr_mode: - READ_SPD(4) /* Get # of Column Addresses */ + READ_SPD(4) /* Get # of Column Addresses */ beq spd_read_fail - li r5, ERR_ADDR_MODE - andi. r3,r3,0x0f /* cut off reserved bits */ - cmpi 0,0,r3,8 - ble spd_fail - cmpi 0,0,r3,15 - bgt spd_fail - addi r6,r3,-8 /* calculate ADDR_MODE parameter */ - rlwimi r7,r6,4,24,27 /* set ADDR_MODE field */ + li r5, ERR_ADDR_MODE + andi. r3,r3,0x0f /* cut off reserved bits */ + cmpi 0,0,r3,8 + ble spd_fail + cmpi 0,0,r3,15 + bgt spd_fail + addi r6,r3,-8 /* calculate ADDR_MODE parameter */ + rlwimi r7,r6,4,24,27 /* set ADDR_MODE field */ set_dimm_ctrl: #ifdef SDC_AUTOPRECH_EN - oris r7,r7,0x0001 /* set auto precharge EN bit */ + oris r7,r7,0x0001 /* set auto precharge EN bit */ #endif - ori r7,r7,1 /* set ENABLE bit */ - cmpi 0,0,r10,SPD_DIMM0 - bne 1f - stw r7,SD_D0_CTRL(r4) + ori r7,r7,1 /* set ENABLE bit */ + cmpi 0,0,r10,SPD_DIMM0 + bne 1f + stw r7,SD_D0_CTRL(r4) sync - b set_dimm_bar + b set_dimm_bar 1: - stw r7,SD_D1_CTRL(r4) + stw r7,SD_D1_CTRL(r4) sync - /******************************************** - * Program SDRAM DIMMx Base Address Register - */ + /* Program SDRAM DIMMx Base Address Register */ set_dimm_bar: READ_SPD(5) /* get # of Ranks */ beq spd_read_fail - andi.r7,r3,0x7 - addi r7,r7,1 - READ_SPD(31) /* Read DIMM rank density */ + andi. r7,r3,0x7 + addi r7,r7,1 + READ_SPD(31) /* Read DIMM rank density */ beq spd_read_fail - rlwinm r5,r3,27,29,31 - rlwinm r6,r3,3,24,28 - or r5,r6,r5 /* r5 = Normalized Rank Density byte */ - lis r8, 0x0080 /* 128MB >> 4 */ - mullw r8,r8,r5 /* r8 = (rank_size >> 4) */ - mullw r8,r8,r7 /* r8 = (DIMM_size >> 4) */ - neg r7,r8 - rlwinm r7,r7,28,4,31 - or r7,r7,r11 /* set ADDR field */ - rlwinm r8,r8,12,20,31 - add r11,r11,r8 /* set Base Addr for next DIMM */ - - cmpi 0,0,r10,SPD_DIMM0 - bne set_dimm1_size - stw r7,SD_D0_BAR(r4) - sync - li r10,SPD_DIMM1 + rlwinm r5,r3,27,29,31 + rlwinm r6,r3,3,24,28 + or r5,r6,r5 /* r5 = Normalized Rank Density byte */ + lis r8, 0x0080 /* 128MB >> 4 */ + mullw r8,r8,r5 /* r8 = (rank_size >> 4) */ + mullw r8,r8,r7 /* r8 = (DIMM_size >> 4) */ + neg r7,r8 + rlwinm r7,r7,28,4,31 + or r7,r7,r11 /* set ADDR field */ + rlwinm r8,r8,12,20,31 + add r11,r11,r8 /* set Base Addr for next DIMM */ + + cmpi 0,0,r10,SPD_DIMM0 + bne set_dimm1_size + stw r7,SD_D0_BAR(r4) + sync + li r10,SPD_DIMM1 READ_SPD(0) bne do_each_dimm b spd_done set_dimm1_size: - stw r7,SD_D1_BAR(r4) + stw r7,SD_D1_BAR(r4) sync spd_done: blr check_next_slot: - cmpi 0,0,r10,SPD_DIMM1 - beq spd_read_fail - li r10,SPD_DIMM1 - b do_first_dimm + cmpi 0,0,r10,SPD_DIMM1 + beq spd_read_fail + li r10,SPD_DIMM1 + b do_first_dimm spd_read_fail: ori r3,r0,0xdead - b err_hung + b err_hung spd_fail: li r3,0x0bad sync -err_hung: /* hang here for debugging */ - nop - nop - b err_hung +err_hung: /* hang here for debugging */ + nop + nop + b err_hung #endif /* !SDC_HARDCODED_INIT */ - diff --git a/board/mpc7448hpc2/mpc7448hpc2.c b/board/mpc7448hpc2/mpc7448hpc2.c index f90a751..4d221e7 100644 --- a/board/mpc7448hpc2/mpc7448hpc2.c +++ b/board/mpc7448hpc2/mpc7448hpc2.c @@ -25,7 +25,7 @@ */ /* - * board support/init functions for the + * board support/init functions for the * Freescale MPC7448 HPC2 (High-Performance Computing 2 Platform). */ @@ -33,39 +33,38 @@ #include <74xx_7xx.h> #if defined(CONFIG_OF_FLAT_TREE) #include <ft_build.h> -extern void ft_cpu_setup(void *blob, bd_t *bd); +extern void ft_cpu_setup (void *blob, bd_t *bd); #endif #undef DEBUG -extern void flush_data_cache(void); -extern void invalidate_l1_instruction_cache(void); -extern void tsi108_init_f(void); +extern void flush_data_cache (void); +extern void invalidate_l1_instruction_cache (void); +extern void tsi108_init_f (void); -int display_mem_map(void); +int display_mem_map (void); -void after_reloc(ulong dest_addr) +void after_reloc (ulong dest_addr) { DECLARE_GLOBAL_DATA_PTR; /* * Jump to the main U-Boot board init code */ - board_init_r((gd_t *) gd, dest_addr); + board_init_r ((gd_t *) gd, dest_addr); /* NOTREACHED */ } /* * Check Board Identity: - * * report board type */ -int checkboard(void) +int checkboard (void) { int l_type = 0; - printf("BOARD: %s\n", CFG_BOARD_NAME); + printf ("BOARD: %s\n", CFG_BOARD_NAME); return (l_type); } @@ -75,19 +74,19 @@ int checkboard(void) * report calling processor number */ -int read_pid(void) +int read_pid (void) { return 0; /* we are on single CPU platform for a while */ } -long int dram_size(int board_type) +long int dram_size (int board_type) { return 0x20000000; /* 256M bytes */ } -long int initdram(int board_type) +long int initdram (int board_type) { - return dram_size(board_type); + return dram_size (board_type); } /* DRAM check routines copied from gw8260 */ @@ -114,11 +113,11 @@ long int initdram(int board_type) /* May cloober fr0. */ /* */ /*********************************************************************/ -static void move64(unsigned long long *src, unsigned long long *dest) +static void move64 (unsigned long long *src, unsigned long long *dest) { - asm("lfd 0, 0(3)\n\t" /* fpr0 = *scr */ - "stfd 0, 0(4)" /* *dest = fpr0 */ - : : :"fr0"); /* Clobbers fr0 */ + asm ("lfd 0, 0(3)\n\t" /* fpr0 = *scr */ + "stfd 0, 0(4)" /* *dest = fpr0 */ + : : :"fr0"); /* Clobbers fr0 */ return; } @@ -183,28 +182,28 @@ unsigned long long pattern[] = { /* Assumes only one one SDRAM bank */ /* */ /*********************************************************************/ -int mem_test_data(void) +int mem_test_data (void) { unsigned long long *pmem = (unsigned long long *)CFG_MEMTEST_START; unsigned long long temp64; - int num_patterns = sizeof(pattern) / sizeof(pattern[0]); + int num_patterns = sizeof (pattern) / sizeof (pattern[0]); int i; unsigned int hi, lo; for (i = 0; i < num_patterns; i++) { - move64(&(pattern[i]), pmem); - move64(pmem, &temp64); + move64 (&(pattern[i]), pmem); + move64 (pmem, &temp64); - /* hi = (temp64>>32) & 0xffffffff; */ - /* lo = temp64 & 0xffffffff; */ - /* printf("\ntemp64 = 0x%08x%08x", hi, lo); */ + /* hi = (temp64>>32) & 0xffffffff; */ + /* lo = temp64 & 0xffffffff; */ + /* printf ("\ntemp64 = 0x%08x%08x", hi, lo); */ hi = (pattern[i] >> 32) & 0xffffffff; lo = pattern[i] & 0xffffffff; - /* printf("\npattern[%d] = 0x%08x%08x", i, hi, lo); */ + /* printf ("\npattern[%d] = 0x%08x%08x", i, hi, lo); */ if (temp64 != pattern[i]) { - printf("\n Data Test Failed, pattern 0x%08x%08x", + printf ("\n Data Test Failed, pattern 0x%08x%08x", hi, lo); return 1; } @@ -236,7 +235,7 @@ int mem_test_data(void) /* */ /* */ /*********************************************************************/ -int mem_test_address(void) +int mem_test_address (void) { volatile unsigned int *pmem = (volatile unsigned int *)CFG_MEMTEST_START; @@ -251,13 +250,13 @@ int mem_test_address(void) /* verify each loaction */ for (i = 0; i < size; i++) { if (pmem[i] != i) { - printf("\n Address Test Failed at 0x%x", i); + printf ("\n Address Test Failed at 0x%x", i); return 1; } } return 0; } -#endif /* CFG_DRAM_TEST_ADDRESS */ +#endif /* CFG_DRAM_TEST_ADDRESS */ #if defined (CFG_DRAM_TEST_WALK) /*********************************************************************/ @@ -287,7 +286,7 @@ int mem_test_address(void) /* */ /* */ /*********************************************************************/ -int mem_march(volatile unsigned long long *base, +int mem_march (volatile unsigned long long *base, unsigned int size, unsigned long long rmask, unsigned long long wmask, short read, short write) @@ -299,14 +298,14 @@ int mem_march(volatile unsigned long long *base, for (i = 0; i < size; i++) { if (read != 0) { /* temp = base[i]; */ - move64((unsigned long long *)&(base[i]), &temp); + move64 ((unsigned long long *)&(base[i]), &temp); if (rmask != temp) { hitemp = (temp >> 32) & 0xffffffff; lotemp = temp & 0xffffffff; himask = (rmask >> 32) & 0xffffffff; lomask = rmask & 0xffffffff; - printf("\n Walking one's test failed: \ + printf ("\n Walking one's test failed: \ address = 0x%08x," "\n\texpected \ 0x%08x%08x, found 0x%08x%08x", i << 3,\ himask, lomask, hitemp, lotemp); @@ -315,12 +314,12 @@ int mem_march(volatile unsigned long long *base, } if (write != 0) { /* base[i] = wmask; */ - move64(&wmask, (unsigned long long *)&(base[i])); + move64 (&wmask, (unsigned long long *)&(base[i])); } } return 0; } -#endif /* CFG_DRAM_TEST_WALK */ +#endif /* CFG_DRAM_TEST_WALK */ /*********************************************************************/ /* NAME: mem_test_walk() - a simple walking ones test */ @@ -348,7 +347,7 @@ int mem_march(volatile unsigned long long *base, /* */ /* */ /*********************************************************************/ -int mem_test_walk(void) +int mem_test_walk (void) { unsigned long long mask; volatile unsigned long long *pmem = @@ -359,32 +358,31 @@ int mem_test_walk(void) mask = 0x01; - printf("Initial Pass"); - mem_march(pmem, size, 0x0, 0x1, 0, 1); + printf ("Initial Pass"); + mem_march (pmem, size, 0x0, 0x1, 0, 1); - printf("\b\b\b\b\b\b\b\b\b\b\b\b"); - printf(" "); - printf(" "); - printf("\b\b\b\b\b\b\b\b\b\b\b\b"); + printf ("\b\b\b\b\b\b\b\b\b\b\b\b"); + printf (" "); + printf (" "); + printf ("\b\b\b\b\b\b\b\b\b\b\b\b"); for (i = 0; i < 63; i++) { - printf("Pass %2d", i + 2); - if (mem_march(pmem, size, mask, mask << 1, 1, 1) != 0) { - /*printf("mask: 0x%x, pass: %d, ", mask, i); */ + printf ("Pass %2d", i + 2); + if (mem_march(pmem, size, mask, mask << 1, 1, 1) != 0) + /*printf ("mask: 0x%x, pass: %d, ", mask, i); */ return 1; - } mask = mask << 1; - printf("\b\b\b\b\b\b\b"); + printf ("\b\b\b\b\b\b\b"); } - printf("Last Pass"); + printf ("Last Pass"); if (mem_march(pmem, size, 0, mask, 0, 1) != 0) { - /* printf("mask: 0x%x", mask); */ + /* printf ("mask: 0x%x", mask); */ return 1; } - printf("\b\b\b\b\b\b\b\b\b"); - printf(" "); - printf("\b\b\b\b\b\b\b\b\b"); + printf ("\b\b\b\b\b\b\b\b\b"); + printf (" "); + printf ("\b\b\b\b\b\b\b\b\b"); return 0; } @@ -412,60 +410,58 @@ int mem_test_walk(void) /* */ /* */ /*********************************************************************/ -int testdram(void) +int testdram (void) { char *s; int rundata, runaddress, runwalk; - s = getenv("testdramdata"); + s = getenv ("testdramdata"); rundata = (s && (*s == 'y')) ? 1 : 0; - s = getenv("testdramaddress"); + s = getenv ("testdramaddress"); runaddress = (s && (*s == 'y')) ? 1 : 0; - s = getenv("testdramwalk"); + s = getenv ("testdramwalk"); runwalk = (s && (*s == 'y')) ? 1 : 0; /* rundata = 1; */ /* runaddress = 0; */ /* runwalk = 0; */ - if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) { - printf("Testing RAM from 0x%08x to 0x%08x ... \ + if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) + printf ("Testing RAM from 0x%08x to 0x%08x ... \ (don't panic... that will take a moment !!!!)\n", \ CFG_MEMTEST_START, CFG_MEMTEST_END); - } #ifdef CFG_DRAM_TEST_DATA if (rundata == 1) { - printf("Test DATA ... "); + printf ("Test DATA ... "); if (mem_test_data () == 1) { - printf("failed \n"); + printf ("failed \n"); return 1; } else - printf("ok \n"); + printf ("ok \n"); } #endif #ifdef CFG_DRAM_TEST_ADDRESS if (runaddress == 1) { - printf("Test ADDRESS ... "); + printf ("Test ADDRESS ... "); if (mem_test_address () == 1) { - printf("failed \n"); + printf ("failed \n"); return 1; } else - printf("ok \n"); + printf ("ok \n"); } #endif #ifdef CFG_DRAM_TEST_WALK if (runwalk == 1) { - printf("Test WALKING ONEs ... "); - if (mem_test_walk() == 1) { - printf("failed \n"); + printf ("Test WALKING ONEs ... "); + if (mem_test_walk () == 1) { + printf ("failed \n"); return 1; } else - printf("ok \n"); + printf ("ok \n"); } #endif - if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) { - printf("passed\n"); - } + if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) + printf ("passed\n"); return 0; } @@ -473,17 +469,17 @@ int testdram(void) #if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) void -ft_board_setup(void *blob, bd_t *bd) +ft_board_setup (void *blob, bd_t *bd) { u32 *p; int len; - ft_cpu_setup(blob, bd); + ft_cpu_setup (blob, bd); - p = ft_get_prop(blob, "/memory/reg", &len); + p = ft_get_prop (blob, "/memory/reg", &len); if (p != NULL) { - *p++ = cpu_to_be32(bd->bi_memstart); - *p = cpu_to_be32(bd->bi_memsize); + *p++ = cpu_to_be32 (bd->bi_memstart); + *p = cpu_to_be32 (bd->bi_memsize); } } #endif diff --git a/board/mpc7448hpc2/tsi108_init.c b/board/mpc7448hpc2/tsi108_init.c index 6f517f5..fdb5365 100644 --- a/board/mpc7448hpc2/tsi108_init.c +++ b/board/mpc7448hpc2/tsi108_init.c @@ -1,6 +1,6 @@ /***************************************************************************** * (C) Copyright 2003; Tundra Semiconductor Corp. - * + * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of @@ -33,7 +33,7 @@ #include <asm/processor.h> #include <tsi108.h> -extern void mpicInit(int verbose); +extern void mpicInit (int verbose); /* * Configuration Options @@ -118,11 +118,11 @@ static PLL_CTRL_SET pll0_config[8] = { static int pb_clk_sel[8] = { 0, 0, 183, 100, 133, 167, 200, 233 }; /* - * get_board_bus_clk() + * get_board_bus_clk () * * returns the bus clock in Hz. */ -unsigned long get_board_bus_clk(void) +unsigned long get_board_bus_clk (void) { ulong i; @@ -134,37 +134,38 @@ unsigned long get_board_bus_clk(void) } /* - * board_early_init_f() + * board_early_init_f () * * board-specific initialization executed from flash */ -int board_early_init_f(void) +int board_early_init_f (void) { DECLARE_GLOBAL_DATA_PTR; ulong i; gd->mem_clk = 0; - i = in32(CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PWRUP_STATUS); - i = (i >> 20) & 0x07; + i = in32 (CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + + CG_PWRUP_STATUS); + i = (i >> 20) & 0x07; /* value of SW4[4:7] */ switch (i) { - case 0: - printf("Using external clock\n"); + case 0: /* external clock */ + printf ("Using external clock\n"); break; - case 1: + case 1: /* system clock */ gd->mem_clk = gd->bus_clk; break; - case 4: - case 5: - case 6: + case 4: /* 133 MHz */ + case 5: /* 166 MHz */ + case 6: /* 200 MHz */ gd->mem_clk = pb_clk_sel[i] * 1000000; break; default: - printf("Invalid DDR2 clock setting\n"); + printf ("Invalid DDR2 clock setting\n"); return -1; } - printf("BUS! %d MHz\n", get_board_bus_clk() / 1000000); - printf("MEM! %d MHz\n", gd->mem_clk / 1000000); + printf ("BUS: %d MHz\n", get_board_bus_clk() / 1000000); + printf ("MEM: %d MHz\n", gd->mem_clk / 1000000); return 0; } @@ -173,175 +174,174 @@ int board_early_init_f(void) * relocation. Contains code that cannot be executed from flash. */ -int board_early_init_r(void) +int board_early_init_r (void) { ulong temp, i; ulong reg_val; volatile ulong *reg_ptr; reg_ptr = - (ulong *) (CFG_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + 0x900); + (ulong *) (CFG_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + 0x900); for (i = 0; i < 32; i++) { *reg_ptr++ = 0x00000201; /* SWAP ENABLED */ *reg_ptr++ = 0x00; } - __asm__ __volatile__("eieio"); - __asm__ __volatile__("sync"); + __asm__ __volatile__ ("eieio"); + __asm__ __volatile__ ("sync"); /* Setup PB_OCN_BAR2: size 256B + ENable @ 0x0_80000000 */ - out32(CFG_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_OCN_BAR2, - 0x80000001); - __asm__ __volatile__("sync"); + out32 (CFG_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_OCN_BAR2, + 0x80000001); + __asm__ __volatile__ ("sync"); /* Make sure that OCN_BAR2 decoder is set (to allow following immediate - * read from SDRAM) + * read from SDRAM) */ temp = in32(CFG_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_OCN_BAR2); - __asm__ __volatile__("sync"); + __asm__ __volatile__ ("sync"); /* * Remap PB_OCN_BAR1 to accomodate PCI-bus aperture and EPROM into the * processor bus address space. Immediately after reset LUT and address * translation are disabled for this BAR. Now we have to initialize LUT * and switch from the BOOT mode to the normal operation mode. - * + * * The aperture defined by PB_OCN_BAR1 startes at address 0xE0000000 - * and covers 512MB of address space. To allow larger aperture we also + * and covers 512MB of address space. To allow larger aperture we also * have to relocate register window of Tsi108 * - * Initialize LUT (32-entries) prior switching PB_OCN_BAR1 from BOOT + * Initialize LUT (32-entries) prior switching PB_OCN_BAR1 from BOOT * mode. - * + * * initialize pointer to LUT associated with PB_OCN_BAR1 */ reg_ptr = - (ulong *) (CFG_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + 0x800); + (ulong *) (CFG_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + 0x800); for (i = 0; i < 32; i++) { *reg_ptr++ = pb2ocn_lut1[i].lower; *reg_ptr++ = pb2ocn_lut1[i].upper; } - __asm__ __volatile__("sync"); + __asm__ __volatile__ ("sync"); /* Base addresses for Cs0, CS1, CS2, CS3 */ - out32(CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B0_ADDR, - 0x00000000); - __asm__ __volatile__("sync"); + out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B0_ADDR, + 0x00000000); + __asm__ __volatile__ ("sync"); - out32(CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B1_ADDR, - 0x00100000); - __asm__ __volatile__("sync"); + out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B1_ADDR, + 0x00100000); + __asm__ __volatile__ ("sync"); - out32(CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B2_ADDR, - 0x00200000); - __asm__ __volatile__("sync"); + out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B2_ADDR, + 0x00200000); + __asm__ __volatile__ ("sync"); - out32(CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B3_ADDR, - 0x00300000); - __asm__ __volatile__("sync"); + out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B3_ADDR, + 0x00300000); + __asm__ __volatile__ ("sync"); /* Masks for HLP banks */ - out32(CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B0_MASK, - 0xFFF00000); - __asm__ __volatile__("sync"); + out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B0_MASK, + 0xFFF00000); + __asm__ __volatile__ ("sync"); - out32(CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B1_MASK, - 0xFFF00000); - __asm__ __volatile__("sync"); + out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B1_MASK, + 0xFFF00000); + __asm__ __volatile__ ("sync"); - out32(CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B2_MASK, - 0xFFF00000); - __asm__ __volatile__("sync"); + out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B2_MASK, + 0xFFF00000); + __asm__ __volatile__ ("sync"); - out32(CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B3_MASK, - 0xFFF00000); - __asm__ __volatile__("sync"); + out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B3_MASK, + 0xFFF00000); + __asm__ __volatile__ ("sync"); /* Set CTRL0 values for banks */ - out32(CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B0_CTRL0, - 0x7FFC44C2); - __asm__ __volatile__("sync"); + out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B0_CTRL0, + 0x7FFC44C2); + __asm__ __volatile__ ("sync"); - out32(CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B1_CTRL0, - 0x7FFC44C0); - __asm__ __volatile__("sync"); + out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B1_CTRL0, + 0x7FFC44C0); + __asm__ __volatile__ ("sync"); - out32(CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B2_CTRL0, - 0x7FFC44C0); - __asm__ __volatile__("sync"); + out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B2_CTRL0, + 0x7FFC44C0); + __asm__ __volatile__ ("sync"); - out32(CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B3_CTRL0, - 0x7FFC44C2); - __asm__ __volatile__("sync"); + out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B3_CTRL0, + 0x7FFC44C2); + __asm__ __volatile__ ("sync"); /* Set banks to latched mode, enabled, and other default settings */ - out32(CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B0_CTRL1, - 0x7C0F2000); - __asm__ __volatile__("sync"); + out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B0_CTRL1, + 0x7C0F2000); + __asm__ __volatile__ ("sync"); - out32(CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B1_CTRL1, - 0x7C0F2000); - __asm__ __volatile__("sync"); + out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B1_CTRL1, + 0x7C0F2000); + __asm__ __volatile__ ("sync"); - out32(CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B2_CTRL1, - 0x7C0F2000); - __asm__ __volatile__("sync"); + out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B2_CTRL1, + 0x7C0F2000); + __asm__ __volatile__ ("sync"); - out32(CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B3_CTRL1, - 0x7C0F2000); - __asm__ __volatile__("sync"); + out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B3_CTRL1, + 0x7C0F2000); + __asm__ __volatile__ ("sync"); /* * Set new value for PB_OCN_BAR1: switch from BOOT to LUT mode. * value for PB_OCN_BAR1: (BA-0xE000_0000 + size 512MB + ENable) */ - out32(CFG_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_OCN_BAR1, - 0xE0000011); - __asm__ __volatile__("sync"); + out32 (CFG_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_OCN_BAR1, + 0xE0000011); + __asm__ __volatile__ ("sync"); - /* Make sure that OCN_BAR2 decoder is set (to allow following - * immediate read from SDRAM) + /* Make sure that OCN_BAR2 decoder is set (to allow following + * immediate read from SDRAM) */ - + temp = in32(CFG_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_OCN_BAR1); - __asm__ __volatile__("sync"); + __asm__ __volatile__ ("sync"); /* * SRI: At this point we have enabled the HLP banks. That means we can * now read from the NVRAM and initialize the environment variables. * We will over-ride the env_init called in board_init_f * This is really a work-around because, the HLP bank 1 - * where NVRAM resides is not visible during board_init_f + * where NVRAM resides is not visible during board_init_f * (lib_ppc/board.c) * Alternatively, we could use the I2C EEPROM at start-up to configure * and enable all HLP banks and not just HLP 0 as is being done for * Taiga Rev. 2. */ - env_init(); + env_init (); #ifndef DISABLE_PBM /* - * For IBM processors we have to set Address-Only commands generated + * For IBM processors we have to set Address-Only commands generated * by PBM that are different from ones set after reset. */ - temp = get_cpu_type(); + temp = get_cpu_type (); - if ((CPU_750FX == temp) || (CPU_750GX == temp)) { - out32(CFG_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_MCMD, - 0x00009955); - } + if ((CPU_750FX == temp) || (CPU_750GX == temp)) + out32 (CFG_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_MCMD, + 0x00009955); #endif /* DISABLE_PBM */ #ifdef CONFIG_PCI @@ -350,42 +350,42 @@ int board_early_init_r(void) */ /* Map PCI/X Configuration Space (16MB @ 0x0_FE000000) */ - out32(CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_PFAB_BAR0_UPPER, - 0); - __asm__ __volatile__("sync"); + out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + + PCI_PFAB_BAR0_UPPER, 0); + __asm__ __volatile__ ("sync"); - out32(CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_PFAB_BAR0, - 0xFB000001); - __asm__ __volatile__("sync"); + out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_PFAB_BAR0, + 0xFB000001); + __asm__ __volatile__ ("sync"); /* Set Bus Number for the attached PCI/X bus (we will use 0 for NB) */ - temp = - in32(CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_PCIX_STAT); + temp = in32(CFG_TSI108_CSR_BASE + + TSI108_PCI_REG_OFFSET + PCI_PCIX_STAT); temp &= ~0xFF00; /* Clear the BUS_NUM field */ - out32(CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_PCIX_STAT, - temp); + out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_PCIX_STAT, + temp); /* Map PCI/X IO Space (64KB @ 0x0_FD000000) takes one 16MB LUT entry */ - out32(CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_PFAB_IO_UPPER, - 0); - __asm__ __volatile__("sync"); + out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_PFAB_IO_UPPER, + 0); + __asm__ __volatile__ ("sync"); /* This register is on the PCI side to interpret the address it receives - * and maps it as a IO address. + * and maps it as a IO address. */ - out32(CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_PFAB_IO, - 0xFA000001); - __asm__ __volatile__("sync"); + out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_PFAB_IO, + 0xFA000001); + __asm__ __volatile__ ("sync"); /* * Map PCI/X Memory Space * - * Transactions directed from OCM to PCI Memory Space are directed + * Transactions directed from OCM to PCI Memory Space are directed * from PB to PCI * unchanged (as defined by PB_OCN_BAR1,2 and LUT settings). * If address remapping is required the corresponding PCI_PFAB_MEM32 @@ -393,7 +393,7 @@ int board_early_init_r(void) * * Map the path from the PCI/X bus into the system memory * - * The memory mapped window assotiated with PCI P2O_BAR2 provides + * The memory mapped window assotiated with PCI P2O_BAR2 provides * access to the system memory without address remapping. * All system memory is opened for accesses initiated by PCI/X bus * masters. @@ -404,13 +404,13 @@ int board_early_init_r(void) */ reg_ptr = - (ulong *) (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + 0x500); + (ulong *) (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + 0x500); #ifdef DISABLE_PBM - /* In case when PBM is disabled (no HW supported cache snoopng on PB) - * P2O_BAR2 is directly mapped into the system memory without address - * translation. + /* In case when PBM is disabled (no HW supported cache snoopng on PB) + * P2O_BAR2 is directly mapped into the system memory without address + * translation. */ reg_val = 0x00000004; /* SDRAM port + NO Addr_Translation */ @@ -438,30 +438,30 @@ int board_early_init_r(void) reg_val = 0x00007100; #endif - __asm__ __volatile__("eieio"); - __asm__ __volatile__("sync"); + __asm__ __volatile__ ("eieio"); + __asm__ __volatile__ ("sync"); - out32(CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_PAGE_SIZES, - reg_val); - __asm__ __volatile__("sync"); + out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_PAGE_SIZES, + reg_val); + __asm__ __volatile__ ("sync"); - /* Set 64-bit PCI bus address for system memory - * ( 0 is the best choice for easy mapping) + /* Set 64-bit PCI bus address for system memory + * ( 0 is the best choice for easy mapping) */ - out32(CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR2, - 0x00000000); - out32(CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR2_UPPER, - 0x00000000); - __asm__ __volatile__("sync"); + out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR2, + 0x00000000); + out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR2_UPPER, + 0x00000000); + __asm__ __volatile__ ("sync"); #ifndef DISABLE_PBM /* - * The memory mapped window assotiated with PCI P2O_BAR3 provides - * access to the system memory using SDRAM OCN port and address - * translation. This is alternative way to access SDRAM from PCI + * The memory mapped window assotiated with PCI P2O_BAR3 provides + * access to the system memory using SDRAM OCN port and address + * translation. This is alternative way to access SDRAM from PCI * required for Tsi108 emulation testing. - * All system memory is opened for accesses initiated by + * All system memory is opened for accesses initiated by * PCI/X bus masters. * * Initialize LUT associated with PCI P2O_BAR3 @@ -469,7 +469,7 @@ int board_early_init_r(void) * set pointer to LUT associated with PCI P2O_BAR3 */ reg_ptr = - (ulong *) (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + 0x600); + (ulong *) (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + 0x600); reg_val = 0x00000004; /* Destination port = SDC */ @@ -483,45 +483,45 @@ int board_early_init_r(void) reg_val += 0x01000000; } - __asm__ __volatile__("eieio"); - __asm__ __volatile__("sync"); + __asm__ __volatile__ ("eieio"); + __asm__ __volatile__ ("sync"); /* Configure PCI P2O_BAR3 (size = 512MB, Enabled) */ reg_val = - in32(CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + + in32(CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_PAGE_SIZES); reg_val &= ~0x00FF; reg_val |= 0x0071; - out32(CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_PAGE_SIZES, - reg_val); - __asm__ __volatile__("sync"); + out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_PAGE_SIZES, + reg_val); + __asm__ __volatile__ ("sync"); /* Set 64-bit base PCI bus address for window (0x20000000) */ - out32(CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR3_UPPER, - 0x00000000); - out32(CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR3, - 0x20000000); - __asm__ __volatile__("sync"); + out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR3_UPPER, + 0x00000000); + out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR3, + 0x20000000); + __asm__ __volatile__ ("sync"); #endif /* !DISABLE_PBM */ #ifdef ENABLE_PCI_CSR_BAR /* open if required access to Tsi108 CSRs from the PCI/X bus */ /* enable BAR0 on the PCI/X bus */ - reg_val = - in32(CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_MISC_CSR); + reg_val = in32(CFG_TSI108_CSR_BASE + + TSI108_PCI_REG_OFFSET + PCI_MISC_CSR); reg_val |= 0x02; - out32(CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_MISC_CSR, - reg_val); - __asm__ __volatile__("sync"); + out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_MISC_CSR, + reg_val); + __asm__ __volatile__ ("sync"); - out32(CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR0_UPPER, - 0x00000000); - out32(CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR0, - CFG_TSI108_CSR_BASE); - __asm__ __volatile__("sync"); + out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR0_UPPER, + 0x00000000); + out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR0, + CFG_TSI108_CSR_BASE); + __asm__ __volatile__ ("sync"); #endif @@ -531,32 +531,32 @@ int board_early_init_r(void) reg_val = in32(CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_CSR); reg_val |= 0x06; - out32(CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_CSR, reg_val); - __asm__ __volatile__("sync"); + out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_CSR, reg_val); + __asm__ __volatile__ ("sync"); #endif /* CONFIG_PCI */ /* * Initialize MPIC outputs (interrupt pins): * Interrupt routing on the Grendel Emul. Board: - * PB_INT[0] -> INT (CPU0) - * PB_INT[1] -> INT (CPU1) - * PB_INT[2] -> MCP (CPU0) - * PB_INT[3] -> MCP (CPU1) + * PB_INT[0] -> INT (CPU0) + * PB_INT[1] -> INT (CPU1) + * PB_INT[2] -> MCP (CPU0) + * PB_INT[3] -> MCP (CPU1) * Set interrupt controller outputs as Level_Sensitive/Active_Low */ - out32(CFG_TSI108_CSR_BASE + TSI108_MPIC_REG_OFFSET + MPIC_CSR(0), 0x02); - out32(CFG_TSI108_CSR_BASE + TSI108_MPIC_REG_OFFSET + MPIC_CSR(1), 0x02); - out32(CFG_TSI108_CSR_BASE + TSI108_MPIC_REG_OFFSET + MPIC_CSR(2), 0x02); - out32(CFG_TSI108_CSR_BASE + TSI108_MPIC_REG_OFFSET + MPIC_CSR(3), 0x02); - __asm__ __volatile__("sync"); + out32 (CFG_TSI108_CSR_BASE + TSI108_MPIC_REG_OFFSET + MPIC_CSR(0), 0x02); + out32 (CFG_TSI108_CSR_BASE + TSI108_MPIC_REG_OFFSET + MPIC_CSR(1), 0x02); + out32 (CFG_TSI108_CSR_BASE + TSI108_MPIC_REG_OFFSET + MPIC_CSR(2), 0x02); + out32 (CFG_TSI108_CSR_BASE + TSI108_MPIC_REG_OFFSET + MPIC_CSR(3), 0x02); + __asm__ __volatile__ ("sync"); /* * Ensure that Machine Check exception is enabled * We need it to support PCI Bus probing (configuration reads) */ - reg_val = mfmsr(); + reg_val = mfmsr (); mtmsr(reg_val | MSR_ME); return 0; @@ -567,7 +567,7 @@ int board_early_init_r(void) * used in the misc_init_r function */ -unsigned long get_l2cr(void) +unsigned long get_l2cr (void) { unsigned long l2controlreg; asm volatile ("mfspr %0, 1017":"=r" (l2controlreg):); @@ -581,79 +581,82 @@ unsigned long get_l2cr(void) * */ -int misc_init_r(void) +int misc_init_r (void) { DECLARE_GLOBAL_DATA_PTR; #ifdef CFG_CLK_SPREAD /* Initialize Spread-Spectrum Clock generation */ ulong i; /* Ensure that Spread-Spectrum is disabled */ - out32(CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL0_CTRL0, 0); - out32(CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL1_CTRL0, 0); + out32 (CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL0_CTRL0, 0); + out32 (CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL1_CTRL0, 0); /* Initialize PLL1: CG_PCI_CLK , internal OCN_CLK * Uses pre-calculated value for Fout = 800 MHz, Fs = 30 kHz, D = 0.5% */ - out32(CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL1_CTRL0, 0x002e0044); /* D = 0.25% */ - out32(CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL1_CTRL1, 0x00000039); /* BWADJ */ + out32 (CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL1_CTRL0, + 0x002e0044); /* D = 0.25% */ + out32 (CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL1_CTRL1, + 0x00000039); /* BWADJ */ /* Initialize PLL0: CG_PB_CLKO */ /* Detect PB clock freq. */ i = in32(CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PWRUP_STATUS); i = (i >> 16) & 0x07; /* Get PB PLL multiplier */ - out32(CFG_TSI108_CSR_BASE + - TSI108_CLK_REG_OFFSET + CG_PLL0_CTRL0, pll0_config[i].ctrl0); - out32(CFG_TSI108_CSR_BASE + - TSI108_CLK_REG_OFFSET + CG_PLL0_CTRL1, pll0_config[i].ctrl1); + out32 (CFG_TSI108_CSR_BASE + + TSI108_CLK_REG_OFFSET + CG_PLL0_CTRL0, pll0_config[i].ctrl0); + out32 (CFG_TSI108_CSR_BASE + + TSI108_CLK_REG_OFFSET + CG_PLL0_CTRL1, pll0_config[i].ctrl1); /* Wait and set SSEN for both PLL0 and 1 */ - udelay(1000); - out32(CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL1_CTRL0, 0x802e0044); /* D=0.25% */ - out32(CFG_TSI108_CSR_BASE + - TSI108_CLK_REG_OFFSET + CG_PLL0_CTRL0, - 0x80000000 | pll0_config[i].ctrl0); + udelay (1000); + out32 (CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL1_CTRL0, + 0x802e0044); /* D=0.25% */ + out32 (CFG_TSI108_CSR_BASE + + TSI108_CLK_REG_OFFSET + CG_PLL0_CTRL0, + 0x80000000 | pll0_config[i].ctrl0); #endif /* CFG_CLK_SPREAD */ #ifdef CFG_L2 - l2cache_enable(); + l2cache_enable (); #endif - printf("BUS: %d MHz\n", gd->bus_clk / 1000000); - printf("MEM: %d MHz\n", gd->mem_clk / 1000000); + printf ("BUS: %d MHz\n", gd->bus_clk / 1000000); + printf ("MEM: %d MHz\n", gd->mem_clk / 1000000); /* - * All the information needed to print the cache details is avaiblable - * at this point i.e. above call to l2cache_enable is the very last - * thing done with regards to enabling diabling the cache. + * All the information needed to print the cache details is avaiblable + * at this point i.e. above call to l2cache_enable is the very last + * thing done with regards to enabling diabling the cache. * So this seems like a good place to print all this information */ - printf("CACHE: "); + printf ("CACHE: "); switch (get_cpu_type()) { case CPU_7447A: - printf("L1 Instruction cache - 32KB 8-way"); - (get_hid0() & (1 << 15)) ? printf(" ENABLED\n") : - printf(" DISABLED\n"); - printf(" L1 Data cache - 32KB 8-way"); - (get_hid0() & (1 << 14)) ? printf(" ENABLED\n") : - printf(" DISABLED\n"); - printf(" Unified L2 cache - 512KB 8-way"); - (get_l2cr() & (1 << 31)) ? printf(" ENABLED\n") : - printf(" DISABLED\n"); - printf("\n"); + printf ("L1 Instruction cache - 32KB 8-way"); + (get_hid0 () & (1 << 15)) ? printf (" ENABLED\n") : + printf (" DISABLED\n"); + printf ("L1 Data cache - 32KB 8-way"); + (get_hid0 () & (1 << 14)) ? printf (" ENABLED\n") : + printf (" DISABLED\n"); + printf ("Unified L2 cache - 512KB 8-way"); + (get_l2cr () & (1 << 31)) ? printf (" ENABLED\n") : + printf (" DISABLED\n"); + printf ("\n"); break; case CPU_7448: - printf("L1 Instruction cache - 32KB 8-way"); - (get_hid0() & (1 << 15)) ? printf(" ENABLED\n") : - printf(" DISABLED\n"); - printf(" L1 Data cache - 32KB 8-way"); - (get_hid0() & (1 << 14)) ? printf(" ENABLED\n") : - printf(" DISABLED\n"); - printf(" Unified L2 cache - 1MB 8-way"); - (get_l2cr() & (1 << 31)) ? printf(" ENABLED\n") : - printf(" DISABLED\n"); + printf ("L1 Instruction cache - 32KB 8-way"); + (get_hid0 () & (1 << 15)) ? printf (" ENABLED\n") : + printf (" DISABLED\n"); + printf ("L1 Data cache - 32KB 8-way"); + (get_hid0 () & (1 << 14)) ? printf (" ENABLED\n") : + printf (" DISABLED\n"); + printf ("Unified L2 cache - 1MB 8-way"); + (get_l2cr () & (1 << 31)) ? printf (" ENABLED\n") : + printf (" DISABLED\n"); break; default: break; diff --git a/cpu/74xx_7xx/cpu.c b/cpu/74xx_7xx/cpu.c index c3aadca..fc3b092 100644 --- a/cpu/74xx_7xx/cpu.c +++ b/cpu/74xx_7xx/cpu.c @@ -303,7 +303,7 @@ watchdog_reset(void) #ifdef CONFIG_OF_FLAT_TREE void -ft_cpu_setup(void *blob, bd_t *bd) +ft_cpu_setup (void *blob, bd_t *bd) { u32 *p; ulong clock; @@ -311,18 +311,18 @@ ft_cpu_setup(void *blob, bd_t *bd) clock = bd->bi_busfreq; - p = ft_get_prop(blob, "/cpus/" OF_CPU "/bus-frequency", &len); + p = ft_get_prop (blob, "/cpus/" OF_CPU "/bus-frequency", &len); if (p != NULL) - *p = cpu_to_be32(clock); + *p = cpu_to_be32 (clock); #if defined(CONFIG_TSI108_ETH) - p = ft_get_prop(blob, "/" OF_TSI "/ethernet@6200/address", &len); - memcpy(p, bd->bi_enetaddr, 6); + p = ft_get_prop (blob, "/" OF_TSI "/ethernet@6200/address", &len); + memcpy (p, bd->bi_enetaddr, 6); #endif - + #if defined(CONFIG_HAS_ETH1) - p = ft_get_prop(blob, "/" OF_TSI "/ethernet@6600/address", &len); - memcpy(p, bd->bi_enet1addr, 6); + p = ft_get_prop (blob, "/" OF_TSI "/ethernet@6600/address", &len); + memcpy (p, bd->bi_enet1addr, 6); #endif } #endif diff --git a/cpu/74xx_7xx/speed.c b/cpu/74xx_7xx/speed.c index d520794..af4aca5 100644 --- a/cpu/74xx_7xx/speed.c +++ b/cpu/74xx_7xx/speed.c @@ -31,7 +31,7 @@ DECLARE_GLOBAL_DATA_PTR; -extern unsigned long get_board_bus_clk(void); +extern unsigned long get_board_bus_clk (void); static const int hid1_multipliers_x_10[] = { 25, /* 0000 - 2.5x */ @@ -53,38 +53,38 @@ static const int hid1_multipliers_x_10[] = { }; static const int hid1_7447A_multipliers_x_10[] = { - 115, /* 00000 - 11.5x */ - 170, /* 00001 - 17x */ - 75, /* 00010 - 7.5x */ - 150, /* 00011 - 15x */ - 70, /* 00100 - 7x */ - 180, /* 00101 - 18x */ - 10, /* 00110 - bypass */ - 200, /* 00111 - 20x */ - 20, /* 01000 - 2x */ - 210, /* 01001 - 21x */ - 65, /* 01010 - 6.5x */ - 130, /* 01011 - 13x */ - 85, /* 01100 - 8.5x */ - 240, /* 01101 - 13x */ - 95, /* 01110 - 9.5x */ - 90, /* 01111 - 9x */ - 30, /* 10000 - 3x */ - 105, /* 10001 - 10.5x */ - 55, /* 10010 - 5.5x */ - 110, /* 10011 - 11x */ - 40, /* 10100 - 4x */ - 100, /* 10101 - 10x */ - 50, /* 10110 - 5x */ - 120, /* 10111 - 12x */ - 80, /* 11000 - 8x */ - 140, /* 11001 - 14x */ - 60, /* 11010 - 6x */ - 160, /* 11011 - 16x */ - 135, /* 11100 - 13.5x */ - 280, /* 11101 - 28x */ - 0, /* 11110 - off */ - 125 /* 11111 - 12.5x */ + 115, /* 00000 - 11.5x */ + 170, /* 00001 - 17x */ + 75, /* 00010 - 7.5x */ + 150, /* 00011 - 15x */ + 70, /* 00100 - 7x */ + 180, /* 00101 - 18x */ + 10, /* 00110 - bypass */ + 200, /* 00111 - 20x */ + 20, /* 01000 - 2x */ + 210, /* 01001 - 21x */ + 65, /* 01010 - 6.5x */ + 130, /* 01011 - 13x */ + 85, /* 01100 - 8.5x */ + 240, /* 01101 - 13x */ + 95, /* 01110 - 9.5x */ + 90, /* 01111 - 9x */ + 30, /* 10000 - 3x */ + 105, /* 10001 - 10.5x */ + 55, /* 10010 - 5.5x */ + 110, /* 10011 - 11x */ + 40, /* 10100 - 4x */ + 100, /* 10101 - 10x */ + 50, /* 10110 - 5x */ + 120, /* 10111 - 12x */ + 80, /* 11000 - 8x */ + 140, /* 11001 - 14x */ + 60, /* 11010 - 6x */ + 160, /* 11011 - 16x */ + 135, /* 11100 - 13.5x */ + 280, /* 11101 - 28x */ + 0, /* 11110 - off */ + 125 /* 11111 - 12.5x */ }; static const int hid1_fx_multipliers_x_10[] = { @@ -127,16 +127,17 @@ int get_clocks (void) ulong clock = 0; #ifdef CFG_CONFIG_BUS_CLK - gd->bus_clk = get_board_bus_clk(); + gd->bus_clk = get_board_bus_clk (); /* bus clock is configurable */ #else - gd->bus_clk = CFG_BUS_CLK; + gd->bus_clk = CFG_BUS_CLK; /* bus clock is a fixed frequency */ #endif /* calculate the clock frequency based upon the CPU type */ switch (get_cpu_type()) { case CPU_7447A: case CPU_7448: - clock = (gd->bus_clk / 10) * hid1_7447A_multipliers_x_10[(get_hid1 () >> 12) & 0x1F]; + clock = (gd->bus_clk / 10) * + hid1_7447A_multipliers_x_10[(get_hid1 () >> 12) & 0x1F]; break; case CPU_7455: @@ -146,12 +147,14 @@ int get_clocks (void) * Make sure division is done before multiplication to prevent 32-bit * arithmetic overflows which will cause a negative number */ - clock = (gd->bus_clk / 10) * hid1_multipliers_x_10[(get_hid1 () >> 13) & 0xF]; + clock = (gd->bus_clk / 10) * + hid1_multipliers_x_10[(get_hid1 () >> 13) & 0xF]; break; case CPU_750GX: case CPU_750FX: - clock = gd->bus_clk * hid1_fx_multipliers_x_10[get_hid1 () >> 27] / 10; + clock = gd->bus_clk * + hid1_fx_multipliers_x_10[get_hid1 () >> 27] / 10; break; case CPU_7450: @@ -168,7 +171,8 @@ int get_clocks (void) * Make sure division is done before multiplication to prevent 32-bit * arithmetic overflows which will cause a negative number */ - clock = (gd->bus_clk / 10) * hid1_multipliers_x_10[get_hid1 () >> 28]; + clock = (gd->bus_clk / 10) * + hid1_multipliers_x_10[get_hid1 () >> 28]; break; case CPU_UNKNOWN: diff --git a/doc/README.mpc7448hpc2 b/doc/README.mpc7448hpc2 index 5142a0f..0e40e39 100644 --- a/doc/README.mpc7448hpc2 +++ b/doc/README.mpc7448hpc2 @@ -3,23 +3,23 @@ Freescale MPC7448hpc2 (Taiga) board Created 08/11/2006 Roy Zang -------------------------- -MPC7448hpc2 (Taiga) board is a high-performance PowerPC server reference -design, which is optimized for high speed throughput between the processor and +MPC7448hpc2 (Taiga) board is a high-performance PowerPC server reference +design, which is optimized for high speed throughput between the processor and the memory, disk drive and Ethernet port subsystems. -MPC7448hpc2(Taiga) is designed to the micro-ATX chassis, allowing it to be -used in 1U or 2U rack-mount chassis¡¯, as well as in standard ATX/Micro-ATX +MPC7448hpc2(Taiga) is designed to the micro-ATX chassis, allowing it to be +used in 1U or 2U rack-mount chassis¡¯, as well as in standard ATX/Micro-ATX chassis. Building U-Boot ------------------ The mpc7448hpc2 code base is known to compile using: - Binutils 2.15, Gcc 3.4.3, Glibc 2.3.3 + Binutils 2.15, Gcc 3.4.3, Glibc 2.3.3 - $ make mpc7448hpc2_config - Configuring for mpc7448hpc2 board... + $ make mpc7448hpc2_config + Configuring for mpc7448hpc2 board... - $ make + $ make Memory Map ---------- @@ -28,25 +28,24 @@ The memory map is setup for Linux to operate properly. The mapping is: - Range Start Range End Definition Size - - 0x0000_0000 0x7fff_ffff DDR 2G - 0xe000_0000 0xe7ff_ffff PCI Memory 128M - 0xfa00_0000 0xfaff_ffff PCI IO 16M - 0xfb00_0000 0xfbff_ffff PCI Config 16M - 0xfc00_0000 0xfc0f_ffff NVRAM/CADMUS 1M - 0xfe00_0000 0xfeff_ffff PromJet 16M - 0xff00_0000 0xff80_0000 FLASH (boot flash) 8M - 0xff80_0000 0xffff_ffff FLASH (second half flash) 8M + Range Start Range End Definition Size + 0x0000_0000 0x7fff_ffff DDR 2G + 0xe000_0000 0xe7ff_ffff PCI Memory 128M + 0xfa00_0000 0xfaff_ffff PCI IO 16M + 0xfb00_0000 0xfbff_ffff PCI Config 16M + 0xfc00_0000 0xfc0f_ffff NVRAM/CADMUS 1M + 0xfe00_0000 0xfeff_ffff PromJet 16M + 0xff00_0000 0xff80_0000 FLASH (boot flash) 8M + 0xff80_0000 0xffff_ffff FLASH (second half flash) 8M Using Flash ----------- -The MPC7448hpc2 board has two "banks" of flash, each 8MB in size -(2^23 = 0x00800000). +The MPC7448hpc2 board has two "banks" of flash, each 8MB in size +(2^23 = 0x00800000). -Note: the "bank" here refers to half of the flash. In fact, there is only one +Note: the "bank" here refers to half of the flash. In fact, there is only one bank of flash, which is divided into low and high half. Each is controlled by the most significant bit of the address bus. The so called "bank" is only for convenience. @@ -57,137 +56,130 @@ settings for updating flash are given below. The u-boot commands for copying the boot-bank into the secondary bank are as follows: - erase ff800000 ff880000 - cp.b ff000000 ff800000 80000 + erase ff800000 ff880000 + cp.b ff000000 ff800000 80000 U-boot commands for downloading an image via tftp and flashing it into the secondary bank: - tftp 10000 <u-boot.bin.image> - erase ff000000 ff080000 - cp.b 10000 ff000000 80000 - + tftp 10000 <u-boot.bin.image> + erase ff000000 ff080000 + cp.b 10000 ff000000 80000 After copying the image into the second bank of flash, be sure to toggle SW3[4] on board before resetting the board in order to set the secondary bank as the boot-bank. - Board Switches ---------------------- - Most switches on the board should not be changed. The most frequent user-settable switches on the board are used to configure the flash banks and determining the PCI frequency. SW1[1-5]: Processor core voltage - 12345 Core Voltage - ----- - SW1=01111 1.000V. - SW1=01101 1.100V. - SW1=01011 1.200V. - SW1=01001 1.300V only for MPC7447A. + 12345 Core Voltage + ----- + SW1=01111 1.000V. + SW1=01101 1.100V. + SW1=01011 1.200V. + SW1=01001 1.300V only for MPC7447A. SW2[1-6]: CPU core frequency - CPU Core Frequency (MHz) + CPU Core Frequency (MHz) Bus Frequency - 123456 100 133 167 200 Ratio + 123456 100 133 167 200 Ratio - ------ - SW2=101100 500 667 833 1000 5x - SW2=100100 550 733 917 1100 5.5x - SW2=110100 600 800 1000 1200 6x - SW2=010100 650 866 1083 1300 6.5x - SW2=001000 700 930 1167 1400 7x - SW2=000100 750 1000 1250 1500 7.5x - SW2=110000 800 1066 1333 1600 8x - SW2=011000 850 1333 1417 1700 8.5x only for MPC7447A - SW2=011110 900 1200 1500 1800 9x - -This table shows only a subset of available frequency options; see the CPU + ------ + SW2=101100 500 667 833 1000 5x + SW2=100100 550 733 917 1100 5.5x + SW2=110100 600 800 1000 1200 6x + SW2=010100 650 866 1083 1300 6.5x + SW2=001000 700 930 1167 1400 7x + SW2=000100 750 1000 1250 1500 7.5x + SW2=110000 800 1066 1333 1600 8x + SW2=011000 850 1333 1417 1700 8.5x only for MPC7447A + SW2=011110 900 1200 1500 1800 9x + +This table shows only a subset of available frequency options; see the CPU hardware specifications for more information. - SW2[7-8]: Bus Protocol and CPU Reset Option - 7 - - - SW2=0 System bus uses MPX bus protocol - SW2=1 System bus uses 60x bus protocol - - 8 - - - SW2=0 TSI108 can cause CPU reset - SW2=1 TSI108 can not cause CPU reset + 7 + - + SW2=0 System bus uses MPX bus protocol + SW2=1 System bus uses 60x bus protocol + 8 + - + SW2=0 TSI108 can cause CPU reset + SW2=1 TSI108 can not cause CPU reset SW3[1-8] system options - 123 - --- - SW3=xxx Connected to GPIO[0:2] on TSI108 + 123 + --- + SW3=xxx Connected to GPIO[0:2] on TSI108 - 4 - - - SW3=0 CPU boots from low half of flash - SW3=1 CPU boots from high half of flash + 4 + - + SW3=0 CPU boots from low half of flash + SW3=1 CPU boots from high half of flash - 5 - - - SW3=0 SATA and slot2 connected to PCI bus - SW3=1 Only slot1 connected to PCI bus + 5 + - + SW3=0 SATA and slot2 connected to PCI bus + SW3=1 Only slot1 connected to PCI bus - 6 - - - SW3=0 USB connected to PCI bus - SW3=1 USB disconnected from PCI bus + 6 + - + SW3=0 USB connected to PCI bus + SW3=1 USB disconnected from PCI bus - 7 - - - SW3=0 Flash is write protected - SW3=1 Flash is NOT write protected + 7 + - + SW3=0 Flash is write protected + SW3=1 Flash is NOT write protected - 8 - - - SW3=0 CPU will boot from flash - SW3=1 CPU will boot from PromJet + 8 + - + SW3=0 CPU will boot from flash + SW3=1 CPU will boot from PromJet SW4[1-3]: System bus frequency Bus Frequency (MHz) - --- - SW4=010 183 - SW4=011 100 - SW4=100 133 - SW4=101 166 only for MPC7447A - SW4=110 200 only for MPC7448 - others reserved - + --- + SW4=010 183 + SW4=011 100 + SW4=100 133 + SW4=101 166 only for MPC7447A + SW4=110 200 only for MPC7448 + others reserved SW4[4-6]: DDR2 SDRAM frequency Bus Frequency (MHz) - --- - SW4=000 external clock - SW4=011 system clock - SW4=100 133 - SW4=101 166 - SW4=110 200 - others reserved - + --- + SW4=000 external clock + SW4=011 system clock + SW4=100 133 + SW4=101 166 + SW4=110 200 + others reserved SW4[7-8]: PCI/PCI-X frequency control - 7 - - - SW4=0 PCI/PCI-X bus operates normally - SW4=1 PCI bus forced to PCI-33 mode - - 8 - - - SW4=0 PCI-X mode at 133 MHz allowed - SW4=1 PCI-X mode limited to 100 MHz + 7 + - + SW4=0 PCI/PCI-X bus operates normally + SW4=1 PCI bus forced to PCI-33 mode + + 8 + - + SW4=0 PCI-X mode at 133 MHz allowed + SW4=1 PCI-X mode limited to 100 MHz diff --git a/drivers/tsi108_eth.c b/drivers/tsi108_eth.c index d95a047..47341be 100644 --- a/drivers/tsi108_eth.c +++ b/drivers/tsi108_eth.c @@ -46,7 +46,9 @@ #endif #if TSI108_ETH_DEBUG > 0 -#define debug_lev(lev, fmt, args...) if (lev <= TSI108_ETH_DEBUG) printf("%s %d: " fmt, __FUNCTION__, __LINE__, ##args) +#define debug_lev(lev, fmt, args...) \ +if (lev <= TSI108_ETH_DEBUG) \ +printf ("%s %d: " fmt, __FUNCTION__, __LINE__, ##args) #else #define debug_lev(lev, fmt, args...) do{}while(0) #endif @@ -54,322 +56,322 @@ #define RX_PRINT_ERRORS #define TX_PRINT_ERRORS -#define ETH_BASE (CFG_TSI108_CSR_BASE + 0x6000) +#define ETH_BASE (CFG_TSI108_CSR_BASE + 0x6000) -#define ETH_PORT_OFFSET 0x400 +#define ETH_PORT_OFFSET 0x400 #define __REG32(base, offset) (*((volatile u32 *)((char *)(base) + (offset)))) -#define reg_MAC_CONFIG_1(base) __REG32(base, 0x00000000) -#define MAC_CONFIG_1_TX_ENABLE (0x00000001) -#define MAC_CONFIG_1_SYNC_TX_ENABLE (0x00000002) -#define MAC_CONFIG_1_RX_ENABLE (0x00000004) -#define MAC_CONFIG_1_SYNC_RX_ENABLE (0x00000008) -#define MAC_CONFIG_1_TX_FLOW_CONTROL (0x00000010) -#define MAC_CONFIG_1_RX_FLOW_CONTROL (0x00000020) -#define MAC_CONFIG_1_LOOP_BACK (0x00000100) -#define MAC_CONFIG_1_RESET_TX_FUNCTION (0x00010000) -#define MAC_CONFIG_1_RESET_RX_FUNCTION (0x00020000) -#define MAC_CONFIG_1_RESET_TX_MAC (0x00040000) -#define MAC_CONFIG_1_RESET_RX_MAC (0x00080000) -#define MAC_CONFIG_1_SIM_RESET (0x40000000) -#define MAC_CONFIG_1_SOFT_RESET (0x80000000) - -#define reg_MAC_CONFIG_2(base) __REG32(base, 0x00000004) -#define MAC_CONFIG_2_FULL_DUPLEX (0x00000001) -#define MAC_CONFIG_2_CRC_ENABLE (0x00000002) -#define MAC_CONFIG_2_PAD_CRC (0x00000004) -#define MAC_CONFIG_2_LENGTH_CHECK (0x00000010) -#define MAC_CONFIG_2_HUGE_FRAME (0x00000020) -#define MAC_CONFIG_2_INTERFACE_MODE(val) (((val) & 0x3) << 8) -#define MAC_CONFIG_2_PREAMBLE_LENGTH(val) (((val) & 0xf) << 12) -#define INTERFACE_MODE_NIBBLE 1 /* 10/100 Mb/s MII) */ -#define INTERFACE_MODE_BYTE 2 /* 1000 Mb/s GMII/TBI */ - -#define reg_MAXIMUM_FRAME_LENGTH(base) __REG32(base, 0x00000010) - -#define reg_MII_MGMT_CONFIG(base) __REG32(base, 0x00000020) -#define MII_MGMT_CONFIG_MGMT_CLOCK_SELECT(val) ((val) & 0x7) -#define MII_MGMT_CONFIG_NO_PREAMBLE (0x00000010) -#define MII_MGMT_CONFIG_SCAN_INCREMENT (0x00000020) -#define MII_MGMT_CONFIG_RESET_MGMT (0x80000000) - -#define reg_MII_MGMT_COMMAND(base) __REG32(base, 0x00000024) -#define MII_MGMT_COMMAND_READ_CYCLE (0x00000001) -#define MII_MGMT_COMMAND_SCAN_CYCLE (0x00000002) - -#define reg_MII_MGMT_ADDRESS(base) __REG32(base, 0x00000028) -#define reg_MII_MGMT_CONTROL(base) __REG32(base, 0x0000002c) -#define reg_MII_MGMT_STATUS(base) __REG32(base, 0x00000030) - -#define reg_MII_MGMT_INDICATORS(base) __REG32(base, 0x00000034) -#define MII_MGMT_INDICATORS_BUSY (0x00000001) -#define MII_MGMT_INDICATORS_SCAN (0x00000002) -#define MII_MGMT_INDICATORS_NOT_VALID (0x00000004) - -#define reg_INTERFACE_STATUS(base) __REG32(base, 0x0000003c) -#define INTERFACE_STATUS_LINK_FAIL (0x00000008) -#define INTERFACE_STATUS_EXCESS_DEFER (0x00000200) - -#define reg_STATION_ADDRESS_1(base) __REG32(base, 0x00000040) -#define reg_STATION_ADDRESS_2(base) __REG32(base, 0x00000044) - -#define reg_PORT_CONTROL(base) __REG32(base, 0x00000200) -#define PORT_CONTROL_PRI (0x00000001) -#define PORT_CONTROL_BPT (0x00010000) -#define PORT_CONTROL_SPD (0x00040000) -#define PORT_CONTROL_RBC (0x00080000) -#define PORT_CONTROL_PRB (0x00200000) -#define PORT_CONTROL_DIS (0x00400000) -#define PORT_CONTROL_TBI (0x00800000) -#define PORT_CONTROL_STE (0x10000000) -#define PORT_CONTROL_ZOR (0x20000000) -#define PORT_CONTROL_CLR (0x40000000) -#define PORT_CONTROL_SRT (0x80000000) - -#define reg_TX_CONFIG(base) __REG32(base, 0x00000220) -#define TX_CONFIG_START_Q (0x00000003) -#define TX_CONFIG_EHP (0x00400000) -#define TX_CONFIG_CHP (0x00800000) -#define TX_CONFIG_RST (0x80000000) - -#define reg_TX_CONTROL(base) __REG32(base, 0x00000224) -#define TX_CONTROL_GO (0x00008000) -#define TX_CONTROL_MP (0x01000000) -#define TX_CONTROL_EAI (0x20000000) -#define TX_CONTROL_ABT (0x40000000) -#define TX_CONTROL_EII (0x80000000) - -#define reg_TX_STATUS(base) __REG32(base, 0x00000228) -#define TX_STATUS_QUEUE_USABLE (0x0000000f) -#define TX_STATUS_CURR_Q (0x00000300) -#define TX_STATUS_ACT (0x00008000) -#define TX_STATUS_QUEUE_IDLE (0x000f0000) -#define TX_STATUS_EOQ_PENDING (0x0f000000) - -#define reg_TX_EXTENDED_STATUS(base) __REG32(base, 0x0000022c) -#define TX_EXTENDED_STATUS_END_OF_QUEUE_CONDITION (0x0000000f) -#define TX_EXTENDED_STATUS_END_OF_FRAME_CONDITION (0x00000f00) -#define TX_EXTENDED_STATUS_DESCRIPTOR_INTERRUPT_CONDITION (0x000f0000) -#define TX_EXTENDED_STATUS_ERROR_FLAG (0x0f000000) - -#define reg_TX_THRESHOLDS(base) __REG32(base, 0x00000230) +#define reg_MAC_CONFIG_1(base) __REG32(base, 0x00000000) +#define MAC_CONFIG_1_TX_ENABLE (0x00000001) +#define MAC_CONFIG_1_SYNC_TX_ENABLE (0x00000002) +#define MAC_CONFIG_1_RX_ENABLE (0x00000004) +#define MAC_CONFIG_1_SYNC_RX_ENABLE (0x00000008) +#define MAC_CONFIG_1_TX_FLOW_CONTROL (0x00000010) +#define MAC_CONFIG_1_RX_FLOW_CONTROL (0x00000020) +#define MAC_CONFIG_1_LOOP_BACK (0x00000100) +#define MAC_CONFIG_1_RESET_TX_FUNCTION (0x00010000) +#define MAC_CONFIG_1_RESET_RX_FUNCTION (0x00020000) +#define MAC_CONFIG_1_RESET_TX_MAC (0x00040000) +#define MAC_CONFIG_1_RESET_RX_MAC (0x00080000) +#define MAC_CONFIG_1_SIM_RESET (0x40000000) +#define MAC_CONFIG_1_SOFT_RESET (0x80000000) + +#define reg_MAC_CONFIG_2(base) __REG32(base, 0x00000004) +#define MAC_CONFIG_2_FULL_DUPLEX (0x00000001) +#define MAC_CONFIG_2_CRC_ENABLE (0x00000002) +#define MAC_CONFIG_2_PAD_CRC (0x00000004) +#define MAC_CONFIG_2_LENGTH_CHECK (0x00000010) +#define MAC_CONFIG_2_HUGE_FRAME (0x00000020) +#define MAC_CONFIG_2_INTERFACE_MODE(val) (((val) & 0x3) << 8) +#define MAC_CONFIG_2_PREAMBLE_LENGTH(val) (((val) & 0xf) << 12) +#define INTERFACE_MODE_NIBBLE 1 /* 10/100 Mb/s MII) */ +#define INTERFACE_MODE_BYTE 2 /* 1000 Mb/s GMII/TBI */ + +#define reg_MAXIMUM_FRAME_LENGTH(base) __REG32(base, 0x00000010) + +#define reg_MII_MGMT_CONFIG(base) __REG32(base, 0x00000020) +#define MII_MGMT_CONFIG_MGMT_CLOCK_SELECT(val) ((val) & 0x7) +#define MII_MGMT_CONFIG_NO_PREAMBLE (0x00000010) +#define MII_MGMT_CONFIG_SCAN_INCREMENT (0x00000020) +#define MII_MGMT_CONFIG_RESET_MGMT (0x80000000) + +#define reg_MII_MGMT_COMMAND(base) __REG32(base, 0x00000024) +#define MII_MGMT_COMMAND_READ_CYCLE (0x00000001) +#define MII_MGMT_COMMAND_SCAN_CYCLE (0x00000002) + +#define reg_MII_MGMT_ADDRESS(base) __REG32(base, 0x00000028) +#define reg_MII_MGMT_CONTROL(base) __REG32(base, 0x0000002c) +#define reg_MII_MGMT_STATUS(base) __REG32(base, 0x00000030) + +#define reg_MII_MGMT_INDICATORS(base) __REG32(base, 0x00000034) +#define MII_MGMT_INDICATORS_BUSY (0x00000001) +#define MII_MGMT_INDICATORS_SCAN (0x00000002) +#define MII_MGMT_INDICATORS_NOT_VALID (0x00000004) + +#define reg_INTERFACE_STATUS(base) __REG32(base, 0x0000003c) +#define INTERFACE_STATUS_LINK_FAIL (0x00000008) +#define INTERFACE_STATUS_EXCESS_DEFER (0x00000200) + +#define reg_STATION_ADDRESS_1(base) __REG32(base, 0x00000040) +#define reg_STATION_ADDRESS_2(base) __REG32(base, 0x00000044) + +#define reg_PORT_CONTROL(base) __REG32(base, 0x00000200) +#define PORT_CONTROL_PRI (0x00000001) +#define PORT_CONTROL_BPT (0x00010000) +#define PORT_CONTROL_SPD (0x00040000) +#define PORT_CONTROL_RBC (0x00080000) +#define PORT_CONTROL_PRB (0x00200000) +#define PORT_CONTROL_DIS (0x00400000) +#define PORT_CONTROL_TBI (0x00800000) +#define PORT_CONTROL_STE (0x10000000) +#define PORT_CONTROL_ZOR (0x20000000) +#define PORT_CONTROL_CLR (0x40000000) +#define PORT_CONTROL_SRT (0x80000000) + +#define reg_TX_CONFIG(base) __REG32(base, 0x00000220) +#define TX_CONFIG_START_Q (0x00000003) +#define TX_CONFIG_EHP (0x00400000) +#define TX_CONFIG_CHP (0x00800000) +#define TX_CONFIG_RST (0x80000000) + +#define reg_TX_CONTROL(base) __REG32(base, 0x00000224) +#define TX_CONTROL_GO (0x00008000) +#define TX_CONTROL_MP (0x01000000) +#define TX_CONTROL_EAI (0x20000000) +#define TX_CONTROL_ABT (0x40000000) +#define TX_CONTROL_EII (0x80000000) + +#define reg_TX_STATUS(base) __REG32(base, 0x00000228) +#define TX_STATUS_QUEUE_USABLE (0x0000000f) +#define TX_STATUS_CURR_Q (0x00000300) +#define TX_STATUS_ACT (0x00008000) +#define TX_STATUS_QUEUE_IDLE (0x000f0000) +#define TX_STATUS_EOQ_PENDING (0x0f000000) + +#define reg_TX_EXTENDED_STATUS(base) __REG32(base, 0x0000022c) +#define TX_EXTENDED_STATUS_END_OF_QUEUE_CONDITION (0x0000000f) +#define TX_EXTENDED_STATUS_END_OF_FRAME_CONDITION (0x00000f00) +#define TX_EXTENDED_STATUS_DESCRIPTOR_INTERRUPT_CONDITION (0x000f0000) +#define TX_EXTENDED_STATUS_ERROR_FLAG (0x0f000000) + +#define reg_TX_THRESHOLDS(base) __REG32(base, 0x00000230) #define reg_TX_DIAGNOSTIC_ADDR(base) __REG32(base, 0x00000270) -#define TX_DIAGNOSTIC_ADDR_INDEX (0x0000007f) -#define TX_DIAGNOSTIC_ADDR_DFR (0x40000000) -#define TX_DIAGNOSTIC_ADDR_AI (0x80000000) - -#define reg_TX_DIAGNOSTIC_DATA(base) __REG32(base, 0x00000274) - -#define reg_TX_ERROR_STATUS(base) __REG32(base, 0x00000278) -#define TX_ERROR_STATUS (0x00000278) -#define TX_ERROR_STATUS_QUEUE_0_ERROR_RESPONSE (0x0000000f) -#define TX_ERROR_STATUS_TEA_ON_QUEUE_0 (0x00000010) -#define TX_ERROR_STATUS_RER_ON_QUEUE_0 (0x00000020) -#define TX_ERROR_STATUS_TER_ON_QUEUE_0 (0x00000040) -#define TX_ERROR_STATUS_DER_ON_QUEUE_0 (0x00000080) -#define TX_ERROR_STATUS_QUEUE_1_ERROR_RESPONSE (0x00000f00) -#define TX_ERROR_STATUS_TEA_ON_QUEUE_1 (0x00001000) -#define TX_ERROR_STATUS_RER_ON_QUEUE_1 (0x00002000) -#define TX_ERROR_STATUS_TER_ON_QUEUE_1 (0x00004000) -#define TX_ERROR_STATUS_DER_ON_QUEUE_1 (0x00008000) -#define TX_ERROR_STATUS_QUEUE_2_ERROR_RESPONSE (0x000f0000) -#define TX_ERROR_STATUS_TEA_ON_QUEUE_2 (0x00100000) -#define TX_ERROR_STATUS_RER_ON_QUEUE_2 (0x00200000) -#define TX_ERROR_STATUS_TER_ON_QUEUE_2 (0x00400000) -#define TX_ERROR_STATUS_DER_ON_QUEUE_2 (0x00800000) -#define TX_ERROR_STATUS_QUEUE_3_ERROR_RESPONSE (0x0f000000) -#define TX_ERROR_STATUS_TEA_ON_QUEUE_3 (0x10000000) -#define TX_ERROR_STATUS_RER_ON_QUEUE_3 (0x20000000) -#define TX_ERROR_STATUS_TER_ON_QUEUE_3 (0x40000000) -#define TX_ERROR_STATUS_DER_ON_QUEUE_3 (0x80000000) - -#define reg_TX_QUEUE_0_CONFIG(base) __REG32(base, 0x00000280) -#define TX_QUEUE_0_CONFIG_OCN_PORT (0x0000003f) -#define TX_QUEUE_0_CONFIG_BSWP (0x00000400) -#define TX_QUEUE_0_CONFIG_WSWP (0x00000800) -#define TX_QUEUE_0_CONFIG_AM (0x00004000) -#define TX_QUEUE_0_CONFIG_GVI (0x00008000) -#define TX_QUEUE_0_CONFIG_EEI (0x00010000) -#define TX_QUEUE_0_CONFIG_ELI (0x00020000) -#define TX_QUEUE_0_CONFIG_ENI (0x00040000) -#define TX_QUEUE_0_CONFIG_ESI (0x00080000) -#define TX_QUEUE_0_CONFIG_EDI (0x00100000) - -#define reg_TX_QUEUE_0_BUF_CONFIG(base) __REG32(base, 0x00000284) -#define TX_QUEUE_0_BUF_CONFIG_OCN_PORT (0x0000003f) -#define TX_QUEUE_0_BUF_CONFIG_BURST (0x00000300) -#define TX_QUEUE_0_BUF_CONFIG_BSWP (0x00000400) -#define TX_QUEUE_0_BUF_CONFIG_WSWP (0x00000800) - -#define OCN_PORT_HLP 0 /* HLP Interface */ -#define OCN_PORT_PCI_X 1 /* PCI-X Interface */ +#define TX_DIAGNOSTIC_ADDR_INDEX (0x0000007f) +#define TX_DIAGNOSTIC_ADDR_DFR (0x40000000) +#define TX_DIAGNOSTIC_ADDR_AI (0x80000000) + +#define reg_TX_DIAGNOSTIC_DATA(base) __REG32(base, 0x00000274) + +#define reg_TX_ERROR_STATUS(base) __REG32(base, 0x00000278) +#define TX_ERROR_STATUS (0x00000278) +#define TX_ERROR_STATUS_QUEUE_0_ERROR_RESPONSE (0x0000000f) +#define TX_ERROR_STATUS_TEA_ON_QUEUE_0 (0x00000010) +#define TX_ERROR_STATUS_RER_ON_QUEUE_0 (0x00000020) +#define TX_ERROR_STATUS_TER_ON_QUEUE_0 (0x00000040) +#define TX_ERROR_STATUS_DER_ON_QUEUE_0 (0x00000080) +#define TX_ERROR_STATUS_QUEUE_1_ERROR_RESPONSE (0x00000f00) +#define TX_ERROR_STATUS_TEA_ON_QUEUE_1 (0x00001000) +#define TX_ERROR_STATUS_RER_ON_QUEUE_1 (0x00002000) +#define TX_ERROR_STATUS_TER_ON_QUEUE_1 (0x00004000) +#define TX_ERROR_STATUS_DER_ON_QUEUE_1 (0x00008000) +#define TX_ERROR_STATUS_QUEUE_2_ERROR_RESPONSE (0x000f0000) +#define TX_ERROR_STATUS_TEA_ON_QUEUE_2 (0x00100000) +#define TX_ERROR_STATUS_RER_ON_QUEUE_2 (0x00200000) +#define TX_ERROR_STATUS_TER_ON_QUEUE_2 (0x00400000) +#define TX_ERROR_STATUS_DER_ON_QUEUE_2 (0x00800000) +#define TX_ERROR_STATUS_QUEUE_3_ERROR_RESPONSE (0x0f000000) +#define TX_ERROR_STATUS_TEA_ON_QUEUE_3 (0x10000000) +#define TX_ERROR_STATUS_RER_ON_QUEUE_3 (0x20000000) +#define TX_ERROR_STATUS_TER_ON_QUEUE_3 (0x40000000) +#define TX_ERROR_STATUS_DER_ON_QUEUE_3 (0x80000000) + +#define reg_TX_QUEUE_0_CONFIG(base) __REG32(base, 0x00000280) +#define TX_QUEUE_0_CONFIG_OCN_PORT (0x0000003f) +#define TX_QUEUE_0_CONFIG_BSWP (0x00000400) +#define TX_QUEUE_0_CONFIG_WSWP (0x00000800) +#define TX_QUEUE_0_CONFIG_AM (0x00004000) +#define TX_QUEUE_0_CONFIG_GVI (0x00008000) +#define TX_QUEUE_0_CONFIG_EEI (0x00010000) +#define TX_QUEUE_0_CONFIG_ELI (0x00020000) +#define TX_QUEUE_0_CONFIG_ENI (0x00040000) +#define TX_QUEUE_0_CONFIG_ESI (0x00080000) +#define TX_QUEUE_0_CONFIG_EDI (0x00100000) + +#define reg_TX_QUEUE_0_BUF_CONFIG(base) __REG32(base, 0x00000284) +#define TX_QUEUE_0_BUF_CONFIG_OCN_PORT (0x0000003f) +#define TX_QUEUE_0_BUF_CONFIG_BURST (0x00000300) +#define TX_QUEUE_0_BUF_CONFIG_BSWP (0x00000400) +#define TX_QUEUE_0_BUF_CONFIG_WSWP (0x00000800) + +#define OCN_PORT_HLP 0 /* HLP Interface */ +#define OCN_PORT_PCI_X 1 /* PCI-X Interface */ #define OCN_PORT_PROCESSOR_MASTER 2 /* Processor Interface (master) */ -#define OCN_PORT_PROCESSOR_SLAVE 3 /* Processor Interface (slave) */ -#define OCN_PORT_MEMORY 4 /* Memory Controller */ -#define OCN_PORT_DMA 5 /* DMA Controller */ -#define OCN_PORT_ETHERNET 6 /* Ethernet Controller */ -#define OCN_PORT_PRINT 7 /* Print Engine Interface */ - -#define reg_TX_QUEUE_0_PTR_LOW(base) __REG32(base, 0x00000288) - -#define reg_TX_QUEUE_0_PTR_HIGH(base) __REG32(base, 0x0000028c) -#define TX_QUEUE_0_PTR_HIGH_VALID (0x80000000) - -#define reg_RX_CONFIG(base) __REG32(base, 0x00000320) -#define RX_CONFIG_DEF_Q (0x00000003) -#define RX_CONFIG_EMF (0x00000100) -#define RX_CONFIG_EUF (0x00000200) -#define RX_CONFIG_BFE (0x00000400) -#define RX_CONFIG_MFE (0x00000800) -#define RX_CONFIG_UFE (0x00001000) -#define RX_CONFIG_SE (0x00002000) -#define RX_CONFIG_ABF (0x00200000) -#define RX_CONFIG_APE (0x00400000) -#define RX_CONFIG_CHP (0x00800000) -#define RX_CONFIG_RST (0x80000000) - -#define reg_RX_CONTROL(base) __REG32(base, 0x00000324) -#define GE_E0_RX_CONTROL_QUEUE_ENABLES (0x0000000f) -#define GE_E0_RX_CONTROL_GO (0x00008000) -#define GE_E0_RX_CONTROL_EAI (0x20000000) -#define GE_E0_RX_CONTROL_ABT (0x40000000) -#define GE_E0_RX_CONTROL_EII (0x80000000) - -#define reg_RX_EXTENDED_STATUS(base) __REG32(base, 0x0000032c) -#define RX_EXTENDED_STATUS (0x0000032c) -#define RX_EXTENDED_STATUS_EOQ (0x0000000f) -#define RX_EXTENDED_STATUS_EOQ_0 (0x00000001) -#define RX_EXTENDED_STATUS_EOF (0x00000f00) -#define RX_EXTENDED_STATUS_DESCRIPTOR_INTERRUPT_CONDITION (0x000f0000) -#define RX_EXTENDED_STATUS_ERROR_FLAG (0x0f000000) - -#define reg_RX_THRESHOLDS(base) __REG32(base, 0x00000330) - -#define reg_RX_DIAGNOSTIC_ADDR(base) __REG32(base, 0x00000370) -#define RX_DIAGNOSTIC_ADDR_INDEX (0x0000007f) -#define RX_DIAGNOSTIC_ADDR_DFR (0x40000000) -#define RX_DIAGNOSTIC_ADDR_AI (0x80000000) - -#define reg_RX_DIAGNOSTIC_DATA(base) __REG32(base, 0x00000374) - -#define reg_RX_QUEUE_0_CONFIG(base) __REG32(base, 0x00000380) -#define RX_QUEUE_0_CONFIG_OCN_PORT (0x0000003f) -#define RX_QUEUE_0_CONFIG_BSWP (0x00000400) -#define RX_QUEUE_0_CONFIG_WSWP (0x00000800) -#define RX_QUEUE_0_CONFIG_AM (0x00004000) -#define RX_QUEUE_0_CONFIG_EEI (0x00010000) -#define RX_QUEUE_0_CONFIG_ELI (0x00020000) -#define RX_QUEUE_0_CONFIG_ENI (0x00040000) -#define RX_QUEUE_0_CONFIG_ESI (0x00080000) -#define RX_QUEUE_0_CONFIG_EDI (0x00100000) - -#define reg_RX_QUEUE_0_BUF_CONFIG(base) __REG32(base, 0x00000384) -#define RX_QUEUE_0_BUF_CONFIG_OCN_PORT (0x0000003f) -#define RX_QUEUE_0_BUF_CONFIG_BURST (0x00000300) -#define RX_QUEUE_0_BUF_CONFIG_BSWP (0x00000400) -#define RX_QUEUE_0_BUF_CONFIG_WSWP (0x00000800) - -#define reg_RX_QUEUE_0_PTR_LOW(base) __REG32(base, 0x00000388) - -#define reg_RX_QUEUE_0_PTR_HIGH(base) __REG32(base, 0x0000038c) -#define RX_QUEUE_0_PTR_HIGH_VALID (0x80000000) +#define OCN_PORT_PROCESSOR_SLAVE 3 /* Processor Interface (slave) */ +#define OCN_PORT_MEMORY 4 /* Memory Controller */ +#define OCN_PORT_DMA 5 /* DMA Controller */ +#define OCN_PORT_ETHERNET 6 /* Ethernet Controller */ +#define OCN_PORT_PRINT 7 /* Print Engine Interface */ + +#define reg_TX_QUEUE_0_PTR_LOW(base) __REG32(base, 0x00000288) + +#define reg_TX_QUEUE_0_PTR_HIGH(base) __REG32(base, 0x0000028c) +#define TX_QUEUE_0_PTR_HIGH_VALID (0x80000000) + +#define reg_RX_CONFIG(base) __REG32(base, 0x00000320) +#define RX_CONFIG_DEF_Q (0x00000003) +#define RX_CONFIG_EMF (0x00000100) +#define RX_CONFIG_EUF (0x00000200) +#define RX_CONFIG_BFE (0x00000400) +#define RX_CONFIG_MFE (0x00000800) +#define RX_CONFIG_UFE (0x00001000) +#define RX_CONFIG_SE (0x00002000) +#define RX_CONFIG_ABF (0x00200000) +#define RX_CONFIG_APE (0x00400000) +#define RX_CONFIG_CHP (0x00800000) +#define RX_CONFIG_RST (0x80000000) + +#define reg_RX_CONTROL(base) __REG32(base, 0x00000324) +#define GE_E0_RX_CONTROL_QUEUE_ENABLES (0x0000000f) +#define GE_E0_RX_CONTROL_GO (0x00008000) +#define GE_E0_RX_CONTROL_EAI (0x20000000) +#define GE_E0_RX_CONTROL_ABT (0x40000000) +#define GE_E0_RX_CONTROL_EII (0x80000000) + +#define reg_RX_EXTENDED_STATUS(base) __REG32(base, 0x0000032c) +#define RX_EXTENDED_STATUS (0x0000032c) +#define RX_EXTENDED_STATUS_EOQ (0x0000000f) +#define RX_EXTENDED_STATUS_EOQ_0 (0x00000001) +#define RX_EXTENDED_STATUS_EOF (0x00000f00) +#define RX_EXTENDED_STATUS_DESCRIPTOR_INTERRUPT_CONDITION (0x000f0000) +#define RX_EXTENDED_STATUS_ERROR_FLAG (0x0f000000) + +#define reg_RX_THRESHOLDS(base) __REG32(base, 0x00000330) + +#define reg_RX_DIAGNOSTIC_ADDR(base) __REG32(base, 0x00000370) +#define RX_DIAGNOSTIC_ADDR_INDEX (0x0000007f) +#define RX_DIAGNOSTIC_ADDR_DFR (0x40000000) +#define RX_DIAGNOSTIC_ADDR_AI (0x80000000) + +#define reg_RX_DIAGNOSTIC_DATA(base) __REG32(base, 0x00000374) + +#define reg_RX_QUEUE_0_CONFIG(base) __REG32(base, 0x00000380) +#define RX_QUEUE_0_CONFIG_OCN_PORT (0x0000003f) +#define RX_QUEUE_0_CONFIG_BSWP (0x00000400) +#define RX_QUEUE_0_CONFIG_WSWP (0x00000800) +#define RX_QUEUE_0_CONFIG_AM (0x00004000) +#define RX_QUEUE_0_CONFIG_EEI (0x00010000) +#define RX_QUEUE_0_CONFIG_ELI (0x00020000) +#define RX_QUEUE_0_CONFIG_ENI (0x00040000) +#define RX_QUEUE_0_CONFIG_ESI (0x00080000) +#define RX_QUEUE_0_CONFIG_EDI (0x00100000) + +#define reg_RX_QUEUE_0_BUF_CONFIG(base) __REG32(base, 0x00000384) +#define RX_QUEUE_0_BUF_CONFIG_OCN_PORT (0x0000003f) +#define RX_QUEUE_0_BUF_CONFIG_BURST (0x00000300) +#define RX_QUEUE_0_BUF_CONFIG_BSWP (0x00000400) +#define RX_QUEUE_0_BUF_CONFIG_WSWP (0x00000800) + +#define reg_RX_QUEUE_0_PTR_LOW(base) __REG32(base, 0x00000388) + +#define reg_RX_QUEUE_0_PTR_HIGH(base) __REG32(base, 0x0000038c) +#define RX_QUEUE_0_PTR_HIGH_VALID (0x80000000) /* * PHY register definitions */ /* the first 15 PHY registers are standard. */ -#define PHY_CTRL_REG 0 /* Control Register */ -#define PHY_STATUS_REG 1 /* Status Regiser */ -#define PHY_ID1_REG 2 /* Phy Id Reg (word 1) */ -#define PHY_ID2_REG 3 /* Phy Id Reg (word 2) */ -#define PHY_AN_ADV_REG 4 /* Autoneg Advertisement */ -#define PHY_LP_ABILITY_REG 5 /* Link Partner Ability (Base Page) */ -#define PHY_AUTONEG_EXP_REG 6 /* Autoneg Expansion Reg */ -#define PHY_NEXT_PAGE_TX_REG 7 /* Next Page TX */ -#define PHY_LP_NEXT_PAGE_REG 8 /* Link Partner Next Page */ -#define PHY_1000T_CTRL_REG 9 /* 1000Base-T Control Reg */ -#define PHY_1000T_STATUS_REG 10 /* 1000Base-T Status Reg */ -#define PHY_EXT_STATUS_REG 11 /* Extended Status Reg */ +#define PHY_CTRL_REG 0 /* Control Register */ +#define PHY_STATUS_REG 1 /* Status Regiser */ +#define PHY_ID1_REG 2 /* Phy Id Reg (word 1) */ +#define PHY_ID2_REG 3 /* Phy Id Reg (word 2) */ +#define PHY_AN_ADV_REG 4 /* Autoneg Advertisement */ +#define PHY_LP_ABILITY_REG 5 /* Link Partner Ability (Base Page) */ +#define PHY_AUTONEG_EXP_REG 6 /* Autoneg Expansion Reg */ +#define PHY_NEXT_PAGE_TX_REG 7 /* Next Page TX */ +#define PHY_LP_NEXT_PAGE_REG 8 /* Link Partner Next Page */ +#define PHY_1000T_CTRL_REG 9 /* 1000Base-T Control Reg */ +#define PHY_1000T_STATUS_REG 10 /* 1000Base-T Status Reg */ +#define PHY_EXT_STATUS_REG 11 /* Extended Status Reg */ /* * PHY Register bit masks. */ -#define PHY_CTRL_RESET (1 << 15) -#define PHY_CTRL_LOOPBACK (1 << 14) -#define PHY_CTRL_SPEED0 (1 << 13) -#define PHY_CTRL_AN_EN (1 << 12) -#define PHY_CTRL_PWR_DN (1 << 11) -#define PHY_CTRL_ISOLATE (1 << 10) -#define PHY_CTRL_RESTART_AN (1 << 9) -#define PHY_CTRL_FULL_DUPLEX (1 << 8) -#define PHY_CTRL_CT_EN (1 << 7) -#define PHY_CTRL_SPEED1 (1 << 6) - -#define PHY_STAT_100BASE_T4 (1 << 15) -#define PHY_STAT_100BASE_X_FD (1 << 14) -#define PHY_STAT_100BASE_X_HD (1 << 13) -#define PHY_STAT_10BASE_T_FD (1 << 12) -#define PHY_STAT_10BASE_T_HD (1 << 11) -#define PHY_STAT_100BASE_T2_FD (1 << 10) -#define PHY_STAT_100BASE_T2_HD (1 << 9) -#define PHY_STAT_EXT_STAT (1 << 8) -#define PHY_STAT_RESERVED (1 << 7) -#define PHY_STAT_MFPS (1 << 6) /* Management Frames Preamble Suppression */ -#define PHY_STAT_AN_COMPLETE (1 << 5) -#define PHY_STAT_REM_FAULT (1 << 4) -#define PHY_STAT_AN_CAP (1 << 3) -#define PHY_STAT_LINK_UP (1 << 2) -#define PHY_STAT_JABBER (1 << 1) -#define PHY_STAT_EXT_CAP (1 << 0) - -#define TBI_CONTROL_2 0x11 -#define TBI_CONTROL_2_ENABLE_COMMA_DETECT 0x0001 -#define TBI_CONTROL_2_ENABLE_WRAP 0x0002 -#define TBI_CONTROL_2_G_MII_MODE 0x0010 -#define TBI_CONTROL_2_RECEIVE_CLOCK_SELECT 0x0020 -#define TBI_CONTROL_2_AUTO_NEGOTIATION_SENSE 0x0100 -#define TBI_CONTROL_2_DISABLE_TRANSMIT_RUNNING_DISPARITY 0x1000 -#define TBI_CONTROL_2_DISABLE_RECEIVE_RUNNING_DISPARITY 0x2000 -#define TBI_CONTROL_2_SHORTCUT_LINK_TIMER 0x4000 -#define TBI_CONTROL_2_SOFT_RESET 0x8000 +#define PHY_CTRL_RESET (1 << 15) +#define PHY_CTRL_LOOPBACK (1 << 14) +#define PHY_CTRL_SPEED0 (1 << 13) +#define PHY_CTRL_AN_EN (1 << 12) +#define PHY_CTRL_PWR_DN (1 << 11) +#define PHY_CTRL_ISOLATE (1 << 10) +#define PHY_CTRL_RESTART_AN (1 << 9) +#define PHY_CTRL_FULL_DUPLEX (1 << 8) +#define PHY_CTRL_CT_EN (1 << 7) +#define PHY_CTRL_SPEED1 (1 << 6) + +#define PHY_STAT_100BASE_T4 (1 << 15) +#define PHY_STAT_100BASE_X_FD (1 << 14) +#define PHY_STAT_100BASE_X_HD (1 << 13) +#define PHY_STAT_10BASE_T_FD (1 << 12) +#define PHY_STAT_10BASE_T_HD (1 << 11) +#define PHY_STAT_100BASE_T2_FD (1 << 10) +#define PHY_STAT_100BASE_T2_HD (1 << 9) +#define PHY_STAT_EXT_STAT (1 << 8) +#define PHY_STAT_RESERVED (1 << 7) +#define PHY_STAT_MFPS (1 << 6) /* Management Frames Preamble Suppression */ +#define PHY_STAT_AN_COMPLETE (1 << 5) +#define PHY_STAT_REM_FAULT (1 << 4) +#define PHY_STAT_AN_CAP (1 << 3) +#define PHY_STAT_LINK_UP (1 << 2) +#define PHY_STAT_JABBER (1 << 1) +#define PHY_STAT_EXT_CAP (1 << 0) + +#define TBI_CONTROL_2 0x11 +#define TBI_CONTROL_2_ENABLE_COMMA_DETECT 0x0001 +#define TBI_CONTROL_2_ENABLE_WRAP 0x0002 +#define TBI_CONTROL_2_G_MII_MODE 0x0010 +#define TBI_CONTROL_2_RECEIVE_CLOCK_SELECT 0x0020 +#define TBI_CONTROL_2_AUTO_NEGOTIATION_SENSE 0x0100 +#define TBI_CONTROL_2_DISABLE_TRANSMIT_RUNNING_DISPARITY 0x1000 +#define TBI_CONTROL_2_DISABLE_RECEIVE_RUNNING_DISPARITY 0x2000 +#define TBI_CONTROL_2_SHORTCUT_LINK_TIMER 0x4000 +#define TBI_CONTROL_2_SOFT_RESET 0x8000 /* marvel specific */ -#define MV1111_EXT_CTRL1_REG 16 /* PHY Specific Control Reg */ -#define MV1111_SPEC_STAT_REG 17 /* PHY Specific Status Reg */ -#define MV1111_EXT_CTRL2_REG 20 /* Extended PHY Specific Control Reg */ +#define MV1111_EXT_CTRL1_REG 16 /* PHY Specific Control Reg */ +#define MV1111_SPEC_STAT_REG 17 /* PHY Specific Status Reg */ +#define MV1111_EXT_CTRL2_REG 20 /* Extended PHY Specific Control Reg */ /* * MARVELL 88E1111 PHY register bit masks */ /* PHY Specific Status Register (MV1111_EXT_CTRL1_REG) */ -#define SPEC_STAT_SPEED_MASK (3 << 14) -#define SPEC_STAT_FULL_DUP (1 << 13) -#define SPEC_STAT_PAGE_RCVD (1 << 12) -#define SPEC_STAT_RESOLVED (1 << 11) /* Speed and Duplex Resolved */ -#define SPEC_STAT_LINK_UP (1 << 10) -#define SPEC_STAT_CABLE_LEN_MASK (7 << 7) /* Cable Length (100/1000 modes only) */ -#define SPEC_STAT_MDIX (1 << 6) -#define SPEC_STAT_POLARITY (1 << 1) -#define SPEC_STAT_JABBER (1 << 0) +#define SPEC_STAT_SPEED_MASK (3 << 14) +#define SPEC_STAT_FULL_DUP (1 << 13) +#define SPEC_STAT_PAGE_RCVD (1 << 12) +#define SPEC_STAT_RESOLVED (1 << 11) /* Speed and Duplex Resolved */ +#define SPEC_STAT_LINK_UP (1 << 10) +#define SPEC_STAT_CABLE_LEN_MASK (7 << 7)/* Cable Length (100/1000 modes only) */ +#define SPEC_STAT_MDIX (1 << 6) +#define SPEC_STAT_POLARITY (1 << 1) +#define SPEC_STAT_JABBER (1 << 0) -#define SPEED_1000 (2 << 14) -#define SPEED_100 (1 << 14) -#define SPEED_10 (0 << 14) +#define SPEED_1000 (2 << 14) +#define SPEED_100 (1 << 14) +#define SPEED_10 (0 << 14) -#define TBI_ADDR 0x1E /* Ten Bit Interface address */ +#define TBI_ADDR 0x1E /* Ten Bit Interface address */ /* negotiated link parameters */ -#define LINK_SPEED_UNKNOWN 0 -#define LINK_SPEED_10 1 -#define LINK_SPEED_100 2 -#define LINK_SPEED_1000 3 +#define LINK_SPEED_UNKNOWN 0 +#define LINK_SPEED_10 1 +#define LINK_SPEED_100 2 +#define LINK_SPEED_1000 3 -#define LINK_DUPLEX_UNKNOWN 0 -#define LINK_DUPLEX_HALF 1 -#define LINK_DUPLEX_FULL 2 +#define LINK_DUPLEX_UNKNOWN 0 +#define LINK_DUPLEX_HALF 1 +#define LINK_DUPLEX_FULL 2 static unsigned int phy_address[] = { 8, 9 }; @@ -390,56 +392,56 @@ struct dma_descriptor { }; /* last next descriptor address flag */ -#define DMA_DESCR_LAST (1 << 31) +#define DMA_DESCR_LAST (1 << 31) /* TX DMA descriptor config status bits */ -#define DMA_DESCR_TX_EOF (1 << 0) /* end of frame */ -#define DMA_DESCR_TX_SOF (1 << 1) /* start of frame */ -#define DMA_DESCR_TX_PFVLAN (1 << 2) -#define DMA_DESCR_TX_HUGE (1 << 3) -#define DMA_DESCR_TX_PAD (1 << 4) -#define DMA_DESCR_TX_CRC (1 << 5) -#define DMA_DESCR_TX_DESCR_INT (1 << 14) -#define DMA_DESCR_TX_RETRY_COUNT 0x000F0000 -#define DMA_DESCR_TX_ONE_COLLISION (1 << 20) -#define DMA_DESCR_TX_LATE_COLLISION (1 << 24) -#define DMA_DESCR_TX_UNDERRUN (1 << 25) -#define DMA_DESCR_TX_RETRY_LIMIT (1 << 26) -#define DMA_DESCR_TX_OK (1 << 30) -#define DMA_DESCR_TX_OWNER (1 << 31) +#define DMA_DESCR_TX_EOF (1 << 0) /* end of frame */ +#define DMA_DESCR_TX_SOF (1 << 1) /* start of frame */ +#define DMA_DESCR_TX_PFVLAN (1 << 2) +#define DMA_DESCR_TX_HUGE (1 << 3) +#define DMA_DESCR_TX_PAD (1 << 4) +#define DMA_DESCR_TX_CRC (1 << 5) +#define DMA_DESCR_TX_DESCR_INT (1 << 14) +#define DMA_DESCR_TX_RETRY_COUNT 0x000F0000 +#define DMA_DESCR_TX_ONE_COLLISION (1 << 20) +#define DMA_DESCR_TX_LATE_COLLISION (1 << 24) +#define DMA_DESCR_TX_UNDERRUN (1 << 25) +#define DMA_DESCR_TX_RETRY_LIMIT (1 << 26) +#define DMA_DESCR_TX_OK (1 << 30) +#define DMA_DESCR_TX_OWNER (1 << 31) /* RX DMA descriptor status bits */ -#define DMA_DESCR_RX_EOF (1 << 0) -#define DMA_DESCR_RX_SOF (1 << 1) -#define DMA_DESCR_RX_VTF (1 << 2) -#define DMA_DESCR_RX_FRAME_IS_TYPE (1 << 3) -#define DMA_DESCR_RX_SHORT_FRAME (1 << 4) -#define DMA_DESCR_RX_HASH_MATCH (1 << 7) -#define DMA_DESCR_RX_BAD_FRAME (1 << 8) -#define DMA_DESCR_RX_OVERRUN (1 << 9) -#define DMA_DESCR_RX_MAX_FRAME_LEN (1 << 11) -#define DMA_DESCR_RX_CRC_ERROR (1 << 12) -#define DMA_DESCR_RX_DESCR_INT (1 << 13) -#define DMA_DESCR_RX_OWNER (1 << 15) - -#define RX_BUFFER_SIZE PKTSIZE -#define NUM_RX_DESC PKTBUFSRX +#define DMA_DESCR_RX_EOF (1 << 0) +#define DMA_DESCR_RX_SOF (1 << 1) +#define DMA_DESCR_RX_VTF (1 << 2) +#define DMA_DESCR_RX_FRAME_IS_TYPE (1 << 3) +#define DMA_DESCR_RX_SHORT_FRAME (1 << 4) +#define DMA_DESCR_RX_HASH_MATCH (1 << 7) +#define DMA_DESCR_RX_BAD_FRAME (1 << 8) +#define DMA_DESCR_RX_OVERRUN (1 << 9) +#define DMA_DESCR_RX_MAX_FRAME_LEN (1 << 11) +#define DMA_DESCR_RX_CRC_ERROR (1 << 12) +#define DMA_DESCR_RX_DESCR_INT (1 << 13) +#define DMA_DESCR_RX_OWNER (1 << 15) + +#define RX_BUFFER_SIZE PKTSIZE +#define NUM_RX_DESC PKTBUFSRX static struct dma_descriptor tx_descriptor __attribute__ ((aligned(32))); static struct dma_descriptor rx_descr_array[NUM_RX_DESC] - __attribute__ ((aligned(32))); + __attribute__ ((aligned(32))); static struct dma_descriptor *rx_descr_current; -static int tsi108_eth_probe(struct eth_device *dev, bd_t * bis); -static int tsi108_eth_send(struct eth_device *dev, +static int tsi108_eth_probe (struct eth_device *dev, bd_t * bis); +static int tsi108_eth_send (struct eth_device *dev, volatile void *packet, int length); -static int tsi108_eth_recv(struct eth_device *dev); -static void tsi108_eth_halt(struct eth_device *dev); -static unsigned int read_phy(unsigned int base, +static int tsi108_eth_recv (struct eth_device *dev); +static void tsi108_eth_halt (struct eth_device *dev); +static unsigned int read_phy (unsigned int base, unsigned int phy_addr, unsigned int phy_reg); -static void write_phy(unsigned int base, +static void write_phy (unsigned int base, unsigned int phy_addr, unsigned int phy_reg, unsigned int phy_data); @@ -447,15 +449,15 @@ static void write_phy(unsigned int base, /* * print phy debug infomation */ -static void dump_phy_regs(unsigned int phy_addr) +static void dump_phy_regs (unsigned int phy_addr) { int i; - printf("PHY %d registers\n", phy_addr); + printf ("PHY %d registers\n", phy_addr); for (i = 0; i <= 30; i++) { - printf("%2d 0x%04x\n", i, read_phy(ETH_BASE, phy_addr, i)); + printf ("%2d 0x%04x\n", i, read_phy (ETH_BASE, phy_addr, i)); } - printf("\n"); + printf ("\n"); } #else @@ -466,27 +468,27 @@ static void dump_phy_regs(unsigned int phy_addr) /* * print debug infomation */ -static void tx_diag_regs(unsigned int base) +static void tx_diag_regs (unsigned int base) { int i; unsigned long dummy; - printf("TX diagnostics registers\n"); + printf ("TX diagnostics registers\n"); reg_TX_DIAGNOSTIC_ADDR(base) = 0x00 | TX_DIAGNOSTIC_ADDR_AI; - udelay(1000); + udelay (1000); dummy = reg_TX_DIAGNOSTIC_DATA(base); for (i = 0x00; i <= 0x05; i++) { - udelay(1000); - printf("0x%02x 0x%08x\n", i, reg_TX_DIAGNOSTIC_DATA(base)); + udelay (1000); + printf ("0x%02x 0x%08x\n", i, reg_TX_DIAGNOSTIC_DATA(base)); } reg_TX_DIAGNOSTIC_ADDR(base) = 0x40 | TX_DIAGNOSTIC_ADDR_AI; - udelay(1000); + udelay (1000); dummy = reg_TX_DIAGNOSTIC_DATA(base); for (i = 0x40; i <= 0x47; i++) { - udelay(1000); - printf("0x%02x 0x%08x\n", i, reg_TX_DIAGNOSTIC_DATA(base)); + udelay (1000); + printf ("0x%02x 0x%08x\n", i, reg_TX_DIAGNOSTIC_DATA(base)); } - printf("\n"); + printf ("\n"); } #else @@ -497,27 +499,27 @@ static void tx_diag_regs(unsigned int base) /* * print debug infomation */ -static void rx_diag_regs(unsigned int base) +static void rx_diag_regs (unsigned int base) { int i; unsigned long dummy; - printf("RX diagnostics registers\n"); + printf ("RX diagnostics registers\n"); reg_RX_DIAGNOSTIC_ADDR(base) = 0x00 | RX_DIAGNOSTIC_ADDR_AI; - udelay(1000); + udelay (1000); dummy = reg_RX_DIAGNOSTIC_DATA(base); for (i = 0x00; i <= 0x05; i++) { - udelay(1000); - printf("0x%02x 0x%08x\n", i, reg_RX_DIAGNOSTIC_DATA(base)); + udelay (1000); + printf ("0x%02x 0x%08x\n", i, reg_RX_DIAGNOSTIC_DATA(base)); } reg_RX_DIAGNOSTIC_ADDR(base) = 0x40 | RX_DIAGNOSTIC_ADDR_AI; - udelay(1000); + udelay (1000); dummy = reg_RX_DIAGNOSTIC_DATA(base); for (i = 0x08; i <= 0x0a; i++) { - udelay(1000); - printf("0x%02x 0x%08x\n", i, reg_RX_DIAGNOSTIC_DATA(base)); + udelay (1000); + printf ("0x%02x 0x%08x\n", i, reg_RX_DIAGNOSTIC_DATA(base)); } - printf("\n"); + printf ("\n"); } #else @@ -528,15 +530,15 @@ static void rx_diag_regs(unsigned int base) /* * print debug infomation */ -static void debug_mii_regs(unsigned int base) +static void debug_mii_regs (unsigned int base) { - printf("MII_MGMT_CONFIG 0x%08x\n", reg_MII_MGMT_CONFIG(base)); - printf("MII_MGMT_COMMAND 0x%08x\n", reg_MII_MGMT_COMMAND(base)); - printf("MII_MGMT_ADDRESS 0x%08x\n", reg_MII_MGMT_ADDRESS(base)); - printf("MII_MGMT_CONTROL 0x%08x\n", reg_MII_MGMT_CONTROL(base)); - printf("MII_MGMT_STATUS 0x%08x\n", reg_MII_MGMT_STATUS(base)); - printf("MII_MGMT_INDICATORS 0x%08x\n", reg_MII_MGMT_INDICATORS(base)); - printf("\n"); + printf ("MII_MGMT_CONFIG 0x%08x\n", reg_MII_MGMT_CONFIG(base)); + printf ("MII_MGMT_COMMAND 0x%08x\n", reg_MII_MGMT_COMMAND(base)); + printf ("MII_MGMT_ADDRESS 0x%08x\n", reg_MII_MGMT_ADDRESS(base)); + printf ("MII_MGMT_CONTROL 0x%08x\n", reg_MII_MGMT_CONTROL(base)); + printf ("MII_MGMT_STATUS 0x%08x\n", reg_MII_MGMT_STATUS(base)); + printf ("MII_MGMT_INDICATORS 0x%08x\n", reg_MII_MGMT_INDICATORS(base)); + printf ("\n"); } #else @@ -546,15 +548,15 @@ static void debug_mii_regs(unsigned int base) /* * Wait until the phy bus is non-busy */ -static void phy_wait(unsigned int base, unsigned int condition) +static void phy_wait (unsigned int base, unsigned int condition) { int timeout; timeout = 0; while (reg_MII_MGMT_INDICATORS(base) & condition) { - udelay(10); + udelay (10); if (++timeout > 10000) { - printf("ERROR: timeout waiting for phy bus (%d)\n", + printf ("ERROR: timeout waiting for phy bus (%d)\n", condition); break; } @@ -564,12 +566,12 @@ static void phy_wait(unsigned int base, unsigned int condition) /* * read phy register */ -static unsigned int read_phy(unsigned int base, +static unsigned int read_phy (unsigned int base, unsigned int phy_addr, unsigned int phy_reg) { unsigned int value; - phy_wait(base, MII_MGMT_INDICATORS_BUSY); + phy_wait (base, MII_MGMT_INDICATORS_BUSY); reg_MII_MGMT_ADDRESS(base) = (phy_addr << 8) | phy_reg; @@ -580,7 +582,7 @@ static unsigned int read_phy(unsigned int base, reg_MII_MGMT_COMMAND(base) = MII_MGMT_COMMAND_READ_CYCLE; /* wait for the read to complete */ - phy_wait(base, + phy_wait (base, MII_MGMT_INDICATORS_NOT_VALID | MII_MGMT_INDICATORS_BUSY); value = reg_MII_MGMT_STATUS(base); @@ -593,11 +595,11 @@ static unsigned int read_phy(unsigned int base, /* * write phy register */ -static void write_phy(unsigned int base, +static void write_phy (unsigned int base, unsigned int phy_addr, unsigned int phy_reg, unsigned int phy_data) { - phy_wait(base, MII_MGMT_INDICATORS_BUSY); + phy_wait (base, MII_MGMT_INDICATORS_BUSY); reg_MII_MGMT_ADDRESS(base) = (phy_addr << 8) | phy_reg; @@ -611,7 +613,7 @@ static void write_phy(unsigned int base, /* * configure the marvell 88e1111 phy */ -static int marvell_88e_phy_config(struct eth_device *dev, int *speed, +static int marvell_88e_phy_config (struct eth_device *dev, int *speed, int *duplex) { unsigned long base; @@ -630,40 +632,39 @@ static int marvell_88e_phy_config(struct eth_device *dev, int *speed, phy_addr = (unsigned long)dev->priv; /* Take the PHY out of reset. */ - write_phy(ETH_BASE, phy_addr, PHY_CTRL_REG, PHY_CTRL_RESET); + write_phy (ETH_BASE, phy_addr, PHY_CTRL_REG, PHY_CTRL_RESET); /* Wait for the reset process to complete. */ - udelay(10); + udelay (10); timeout = 0; while ((phy_status = - read_phy(ETH_BASE, phy_addr, PHY_CTRL_REG)) & PHY_CTRL_RESET) { - udelay(10); + read_phy (ETH_BASE, phy_addr, PHY_CTRL_REG)) & PHY_CTRL_RESET) { + udelay (10); if (++timeout > 10000) { - printf("ERROR: timeout waiting for phy reset\n"); + printf ("ERROR: timeout waiting for phy reset\n"); break; } } /* TBI Configuration. */ - write_phy(base, TBI_ADDR, TBI_CONTROL_2, TBI_CONTROL_2_G_MII_MODE | + write_phy (base, TBI_ADDR, TBI_CONTROL_2, TBI_CONTROL_2_G_MII_MODE | TBI_CONTROL_2_RECEIVE_CLOCK_SELECT); /* Wait for the link to be established. */ timeout = 0; do { - udelay(20000); - phy_status = read_phy(ETH_BASE, phy_addr, PHY_STATUS_REG); + udelay (20000); + phy_status = read_phy (ETH_BASE, phy_addr, PHY_STATUS_REG); if (++timeout > 100) { debug_lev(1, "ERROR: unable to establish link!!!\n"); break; } } while ((phy_status & PHY_STAT_LINK_UP) == 0); - if ((phy_status & PHY_STAT_LINK_UP) == 0) { + if ((phy_status & PHY_STAT_LINK_UP) == 0) return 0; - } value = 0; - phy_spec_status = read_phy(ETH_BASE, phy_addr, MV1111_SPEC_STAT_REG); + phy_spec_status = read_phy (ETH_BASE, phy_addr, MV1111_SPEC_STAT_REG); if (phy_spec_status & SPEC_STAT_RESOLVED) { switch (phy_spec_status & SPEC_STAT_SPEED_MASK) { case SPEED_1000: @@ -681,45 +682,41 @@ static int marvell_88e_phy_config(struct eth_device *dev, int *speed, if (phy_spec_status & SPEC_STAT_FULL_DUP) { phy_duplex = LINK_DUPLEX_FULL; value |= PHY_CTRL_FULL_DUPLEX; - } else { + } else phy_duplex = LINK_DUPLEX_HALF; - } } /* set TBI speed */ - write_phy(base, TBI_ADDR, PHY_CTRL_REG, value); - write_phy(base, TBI_ADDR, PHY_AN_ADV_REG, 0x0060); + write_phy (base, TBI_ADDR, PHY_CTRL_REG, value); + write_phy (base, TBI_ADDR, PHY_AN_ADV_REG, 0x0060); #if TSI108_ETH_DEBUG > 0 - printf("%s link is up", dev->name); - phy_spec_status = read_phy(ETH_BASE, phy_addr, MV1111_SPEC_STAT_REG); + printf ("%s link is up", dev->name); + phy_spec_status = read_phy (ETH_BASE, phy_addr, MV1111_SPEC_STAT_REG); if (phy_spec_status & SPEC_STAT_RESOLVED) { switch (phy_speed) { case LINK_SPEED_1000: - printf(", 1000 Mbps"); + printf (", 1000 Mbps"); break; case LINK_SPEED_100: - printf(", 100 Mbps"); + printf (", 100 Mbps"); break; case LINK_SPEED_10: - printf(", 10 Mbps"); + printf (", 10 Mbps"); break; } - if (phy_duplex == LINK_DUPLEX_FULL) { - printf(", Full duplex"); - } else { - printf(", Half duplex"); - } + if (phy_duplex == LINK_DUPLEX_FULL) + printf (", Full duplex"); + else + printf (", Half duplex"); } - printf("\n"); + printf ("\n"); #endif - dump_phy_regs(TBI_ADDR); - if (speed) { + dump_phy_regs (TBI_ADDR); + if (speed) *speed = phy_speed; - } - if (duplex) { + if (duplex) *duplex = phy_duplex; - } return 1; } @@ -729,7 +726,7 @@ static int marvell_88e_phy_config(struct eth_device *dev, int *speed, * * register the tsi108 ethernet controllers with the multi-ethernet system */ -int tsi108_eth_initialize(bd_t * bis) +int tsi108_eth_initialize (bd_t * bis) { struct eth_device *dev; int index; @@ -737,7 +734,7 @@ int tsi108_eth_initialize(bd_t * bis) for (index = 0; index < CONFIG_TSI108_ETH_NUM_PORTS; index++) { dev = (struct eth_device *)malloc(sizeof(struct eth_device)); - sprintf(dev->name, "TSI108_eth%d", index); + sprintf (dev->name, "TSI108_eth%d", index); dev->iobase = ETH_BASE + (index * ETH_PORT_OFFSET); dev->priv = (void *)(phy_address[index]); @@ -754,7 +751,7 @@ int tsi108_eth_initialize(bd_t * bis) /* * probe for and initialize a single ethernet interface */ -static int tsi108_eth_probe(struct eth_device *dev, bd_t * bis) +static int tsi108_eth_probe (struct eth_device *dev, bd_t * bis) { unsigned long base; unsigned long value; @@ -794,25 +791,23 @@ static int tsi108_eth_probe(struct eth_device *dev, bd_t * bis) reg_STATION_ADDRESS_2(base) = (dev->enetaddr[1] << 24) | (dev->enetaddr[0] << 16); - if (marvell_88e_phy_config(dev, &speed, &duplex) == 0) { + if (marvell_88e_phy_config(dev, &speed, &duplex) == 0) return 0; - } value = MAC_CONFIG_2_PREAMBLE_LENGTH(7) | MAC_CONFIG_2_PAD_CRC | MAC_CONFIG_2_CRC_ENABLE; - if (speed == LINK_SPEED_1000) { + if (speed == LINK_SPEED_1000) value |= MAC_CONFIG_2_INTERFACE_MODE(INTERFACE_MODE_BYTE); - } else { + else { value |= MAC_CONFIG_2_INTERFACE_MODE(INTERFACE_MODE_NIBBLE); reg_PORT_CONTROL(base) |= PORT_CONTROL_SPD; } if (duplex == LINK_DUPLEX_FULL) { value |= MAC_CONFIG_2_FULL_DUPLEX; reg_PORT_CONTROL(base) &= ~PORT_CONTROL_BPT; - } else { + } else reg_PORT_CONTROL(base) |= PORT_CONTROL_BPT; - } reg_MAC_CONFIG_2(base) = value; reg_RX_CONFIG(base) = RX_CONFIG_SE; @@ -875,7 +870,7 @@ static int tsi108_eth_probe(struct eth_device *dev, bd_t * bis) /* * send a packet */ -static int tsi108_eth_send(struct eth_device *dev, +static int tsi108_eth_send (struct eth_device *dev, volatile void *packet, int length) { unsigned long base; @@ -894,9 +889,8 @@ static int tsi108_eth_send(struct eth_device *dev, (unsigned long)tx_descr + sizeof(struct dma_descriptor)); - if (timeout != 0) { - udelay(15); - } + if (timeout != 0) + udelay (15); if (++timeout > 10000) { tx_diag_regs(base); debug_lev(1, @@ -908,7 +902,7 @@ static int tsi108_eth_send(struct eth_device *dev, status = le32_to_cpu(tx_descr->config_status); if ((status & DMA_DESCR_TX_OK) == 0) { #ifdef TX_PRINT_ERRORS - printf("TX packet error: 0x%08x\n %s%s%s%s\n", status, + printf ("TX packet error: 0x%08x\n %s%s%s%s\n", status, status & DMA_DESCR_TX_OK ? "tx error, " : "", status & DMA_DESCR_TX_RETRY_LIMIT ? "retry limit reached, " : "", @@ -918,7 +912,7 @@ static int tsi108_eth_send(struct eth_device *dev, #endif } - debug_lev(9, "sending packet %d\n", length); + debug_lev (9, "sending packet %d\n", length); tx_descr->start_addr0 = cpu_to_le32((vuint32) packet); tx_descr->start_addr1 = 0; tx_descr->next_descr_addr0 = 0; @@ -946,7 +940,7 @@ static int tsi108_eth_send(struct eth_device *dev, /* * Check for received packets and send them up the protocal stack */ -static int tsi108_eth_recv(struct eth_device *dev) +static int tsi108_eth_recv (struct eth_device *dev) { struct dma_descriptor *rx_descr; unsigned long base; @@ -957,7 +951,7 @@ static int tsi108_eth_recv(struct eth_device *dev) base = dev->iobase; /* make sure we see the changes made by the DMA engine */ - invalidate_dcache_range((unsigned long)rx_descr_array, + invalidate_dcache_range ((unsigned long)rx_descr_array, (unsigned long)rx_descr_array + sizeof(rx_descr_array)); @@ -968,7 +962,7 @@ static int tsi108_eth_recv(struct eth_device *dev) status = le32_to_cpu(rx_descr->config_status); if (status & DMA_DESCR_RX_BAD_FRAME) { #ifdef RX_PRINT_ERRORS - printf("RX packet error: 0x%08x\n %s%s%s%s%s%s\n", + printf ("RX packet error: 0x%08x\n %s%s%s%s%s%s\n", status, status & DMA_DESCR_RX_FRAME_IS_TYPE ? "too big, " : "", @@ -989,24 +983,23 @@ static int tsi108_eth_recv(struct eth_device *dev) /*** process packet ***/ buffer = (volatile uchar - *)(le32_to_cpu(rx_descr->start_addr0)); - NetReceive(buffer, length); + *)(le32_to_cpu (rx_descr->start_addr0)); + NetReceive (buffer, length); - invalidate_dcache_range((unsigned long)buffer, + invalidate_dcache_range ((unsigned long)buffer, (unsigned long)buffer + RX_BUFFER_SIZE); } /* Give this buffer back to the DMA engine */ rx_descr->vlan_byte_count = 0; - rx_descr->config_status = cpu_to_le32((RX_BUFFER_SIZE << 16) | + rx_descr->config_status = cpu_to_le32 ((RX_BUFFER_SIZE << 16) | DMA_DESCR_RX_OWNER); /* move descriptor pointer forward */ rx_descr = (struct dma_descriptor - *)(le32_to_cpu(rx_descr->next_descr_addr0)); - if (rx_descr == 0) { + *)(le32_to_cpu (rx_descr->next_descr_addr0)); + if (rx_descr == 0) rx_descr = &rx_descr_array[0]; - } } /* remember where we are for next time */ rx_descr_current = rx_descr; @@ -1026,7 +1019,7 @@ static int tsi108_eth_recv(struct eth_device *dev) /* * disable an ethernet interface */ -static void tsi108_eth_halt(struct eth_device *dev) +static void tsi108_eth_halt (struct eth_device *dev) { unsigned long base; diff --git a/drivers/tsi108_i2c.c b/drivers/tsi108_i2c.c index 08e5e3b..c100cb8 100644 --- a/drivers/tsi108_i2c.c +++ b/drivers/tsi108_i2c.c @@ -23,19 +23,18 @@ */ #include <config.h> +#include <common.h> #ifdef CONFIG_TSI108_I2C - -#include <common.h> #include <tsi108.h> #if (CONFIG_COMMANDS & CFG_CMD_I2C) -#define I2C_DELAY 100000 +#define I2C_DELAY 100000 #undef DEBUG_I2C #ifdef DEBUG_I2C -#define DPRINT(x) printf(x) +#define DPRINT(x) printf (x) #else #define DPRINT(x) #endif @@ -43,7 +42,7 @@ /* All functions assume that Tsi108 I2C block is the only master on the bus */ /* I2C read helper function */ -static int i2c_read_byte( +static int i2c_read_byte ( uint i2c_chan, /* I2C channel number: 0 - main, 1 - SDC SPD */ uchar chip_addr,/* I2C device address on the bus */ uint byte_addr, /* Byte address within I2C device */ @@ -55,19 +54,17 @@ static int i2c_read_byte( u32 op_status = TSI108_I2C_TIMEOUT_ERR; u32 chan_offset = TSI108_I2C_OFFSET; - DPRINT(("I2C read_byte() %d 0x%02x 0x%02x\n", + DPRINT (("I2C read_byte() %d 0x%02x 0x%02x\n", i2c_chan, chip_addr, byte_addr)); - if (0 != i2c_chan) { + if (0 != i2c_chan) chan_offset = TSI108_I2C_SDRAM_OFFSET; - } /* Check if I2C operation is in progress */ temp = *(u32 *) (CFG_TSI108_CSR_BASE + chan_offset + I2C_CNTRL2); if (0 == (temp & (I2C_CNTRL2_RD_STATUS | I2C_CNTRL2_WR_STATUS | - I2C_CNTRL2_START)) - ) { + I2C_CNTRL2_START))) { /* Set device address and operation (read = 0) */ temp = (byte_addr << 16) | ((chip_addr & 0x07) << 8) | ((chip_addr >> 3) & 0x0F); @@ -75,7 +72,7 @@ static int i2c_read_byte( temp; /* Issue the read command - * (at this moment all other parameters are 0 + * (at this moment all other parameters are 0 * (size = 1 byte, lane = 0) */ @@ -108,7 +105,7 @@ static int i2c_read_byte( /* report HW error */ op_status = TSI108_I2C_IF_ERROR; - DPRINT(("I2C HW error reported: 0x%02x\n", temp)); + DPRINT (("I2C HW error reported: 0x%02x\n", temp)); } break; @@ -117,20 +114,20 @@ static int i2c_read_byte( } else { op_status = TSI108_I2C_IF_BUSY; - DPRINT(("I2C Transaction start failed: 0x%02x\n", temp)); + DPRINT (("I2C Transaction start failed: 0x%02x\n", temp)); } - DPRINT(("I2C read_byte() status: 0x%02x\n", op_status)); + DPRINT (("I2C read_byte() status: 0x%02x\n", op_status)); return op_status; } -/* +/* * I2C Read interface as defined in "include/i2c.h" : * chip_addr: I2C chip address, range 0..127 * (to read from SPD channel EEPROM use (0xD0 ... 0xD7) * NOTE: The bit 7 in the chip_addr serves as a channel select. * This hack is for enabling "isdram" command on Tsi108 boards - * without changes to common code. Used for I2C reads only. + * without changes to common code. Used for I2C reads only. * byte_addr: Memory or register address within the chip * alen: Number of bytes to use for addr (typically 1, 2 for larger * memories, 0 for register type devices with only one @@ -141,7 +138,8 @@ static int i2c_read_byte( * Returns: 0 on success, not 0 on failure */ -int i2c_read(uchar chip_addr, uint byte_addr, int alen, uchar * buffer, int len) +int i2c_read (uchar chip_addr, uint byte_addr, int alen, + uchar * buffer, int len) { u32 op_status = TSI108_I2C_PARAM_ERR; u32 i2c_if = 0; @@ -159,20 +157,20 @@ int i2c_read(uchar chip_addr, uint byte_addr, int alen, uchar * buffer, int len) buffer++); if (TSI108_I2C_SUCCESS != op_status) { - DPRINT(("I2C read_byte() failed: 0x%02x (%d left)\n", op_status, len)); + DPRINT (("I2C read_byte() failed: 0x%02x (%d left)\n", op_status, len)); break; } } } - DPRINT(("I2C read() status: 0x%02x\n", op_status)); + DPRINT (("I2C read() status: 0x%02x\n", op_status)); return op_status; } /* I2C write helper function */ -static int i2c_write_byte(uchar chip_addr,/* I2C device address on the bus */ +static int i2c_write_byte (uchar chip_addr,/* I2C device address on the bus */ uint byte_addr, /* Byte address within I2C device */ uchar * buffer /* pointer to data buffer */ ) @@ -210,7 +208,7 @@ static int i2c_write_byte(uchar chip_addr,/* I2C device address on the bus */ /* Wait until operation completed */ do { - // Read I2C operation status + /* Read I2C operation status */ temp = *(u32 *) (CFG_TSI108_CSR_BASE + TSI108_I2C_OFFSET + I2C_CNTRL2); @@ -227,7 +225,7 @@ static int i2c_write_byte(uchar chip_addr,/* I2C device address on the bus */ /* report detected HW error */ op_status = TSI108_I2C_IF_ERROR; - DPRINT(("I2C HW error reported: 0x%02x\n", temp)); + DPRINT (("I2C HW error reported: 0x%02x\n", temp)); } break; @@ -237,13 +235,13 @@ static int i2c_write_byte(uchar chip_addr,/* I2C device address on the bus */ } else { op_status = TSI108_I2C_IF_BUSY; - DPRINT(("I2C Transaction start failed: 0x%02x\n", temp)); + DPRINT (("I2C Transaction start failed: 0x%02x\n", temp)); } return op_status; } -/* +/* * I2C Write interface as defined in "include/i2c.h" : * chip_addr: I2C chip address, range 0..127 * byte_addr: Memory or register address within the chip @@ -256,7 +254,7 @@ static int i2c_write_byte(uchar chip_addr,/* I2C device address on the bus */ * Returns: 0 on success, not 0 on failure */ -int i2c_write(uchar chip_addr, uint byte_addr, int alen, uchar * buffer, +int i2c_write (uchar chip_addr, uint byte_addr, int alen, uchar * buffer, int len) { u32 op_status = TSI108_I2C_PARAM_ERR; @@ -265,10 +263,10 @@ int i2c_write(uchar chip_addr, uint byte_addr, int alen, uchar * buffer, if (chip_addr <= 0x7F && (byte_addr + len) <= (0x01 << (alen * 8))) { while (len--) { op_status = - i2c_write_byte(chip_addr, byte_addr++, buffer++); + i2c_write_byte (chip_addr, byte_addr++, buffer++); if (TSI108_I2C_SUCCESS != op_status) { - DPRINT(("I2C write_byte() failed: 0x%02x (%d left)\n", op_status, len)); + DPRINT (("I2C write_byte() failed: 0x%02x (%d left)\n", op_status, len)); break; } @@ -278,13 +276,13 @@ int i2c_write(uchar chip_addr, uint byte_addr, int alen, uchar * buffer, return op_status; } -/* +/* * I2C interface function as defined in "include/i2c.h". * Probe the given I2C chip address by reading single byte from offset 0. * Returns 0 if a chip responded, not 0 on failure. */ -int i2c_probe(uchar chip) +int i2c_probe (uchar chip) { u32 tmp; @@ -293,8 +291,8 @@ int i2c_probe(uchar chip) * The Tsi108 HW doesn't support sending just the chip address * and checkong for an <ACK> back. */ - return i2c_read(chip, 0, 1, (char *)&tmp, 1); + return i2c_read (chip, 0, 1, (char *)&tmp, 1); } -#endif /* (CONFIG_COMMANDS & CFG_CMD_I2C) */ +#endif /* (CONFIG_COMMANDS & CFG_CMD_I2C) */ #endif /* CONFIG_TSI108_I2C */ diff --git a/drivers/tsi108_pci.c b/drivers/tsi108_pci.c index f374ede..9f606df 100644 --- a/drivers/tsi108_pci.c +++ b/drivers/tsi108_pci.c @@ -36,7 +36,7 @@ struct pci_controller local_hose; -void tsi108_clear_pci_error(void) +void tsi108_clear_pci_error (void) { u32 err_stat, err_addr, pci_stat; @@ -79,11 +79,11 @@ void tsi108_clear_pci_error(void) return; } -unsigned int __get_pci_config_dword(u32 addr) +unsigned int __get_pci_config_dword (u32 addr) { unsigned int retval; - __asm__ __volatile__(" lwbrx %0,0,%1\n" + __asm__ __volatile__ (" lwbrx %0,0,%1\n" "1: eieio\n" "2:\n" ".section .fixup,\"ax\"\n" @@ -97,53 +97,53 @@ unsigned int __get_pci_config_dword(u32 addr) return (retval); } -static int tsi108_read_config_dword(struct pci_controller *hose, +static int tsi108_read_config_dword (struct pci_controller *hose, pci_dev_t dev, int offset, u32 * value) { dev &= (CFG_PCI_CFG_SIZE - 1); dev |= (CFG_PCI_CFG_BASE | (offset & 0xfc)); *value = __get_pci_config_dword(dev); if (0xFFFFFFFF == *value) - tsi108_clear_pci_error(); + tsi108_clear_pci_error (); return 0; } -static int tsi108_write_config_dword(struct pci_controller *hose, +static int tsi108_write_config_dword (struct pci_controller *hose, pci_dev_t dev, int offset, u32 value) { dev &= (CFG_PCI_CFG_SIZE - 1); dev |= (CFG_PCI_CFG_BASE | (offset & 0xfc)); - out_le32((volatile unsigned *)dev, value); + out_le32 ((volatile unsigned *)dev, value); return 0; } -void pci_init_board(void) +void pci_init_board (void) { struct pci_controller *hose = (struct pci_controller *)&local_hose; hose->first_busno = 0; hose->last_busno = 0xff; - pci_set_region(hose->regions + 0, + pci_set_region (hose->regions + 0, CFG_PCI_MEMORY_BUS, CFG_PCI_MEMORY_PHYS, CFG_PCI_MEMORY_SIZE, PCI_REGION_MEM | PCI_REGION_MEMORY); /* PCI memory space */ - pci_set_region(hose->regions + 1, + pci_set_region (hose->regions + 1, CFG_PCI_MEM_BUS, CFG_PCI_MEM_PHYS, CFG_PCI_MEM_SIZE, PCI_REGION_MEM); /* PCI I/O space */ - pci_set_region(hose->regions + 2, + pci_set_region (hose->regions + 2, CFG_PCI_IO_BUS, CFG_PCI_IO_PHYS, CFG_PCI_IO_SIZE, PCI_REGION_IO); hose->region_count = 3; - pci_set_ops(hose, + pci_set_ops (hose, pci_hose_read_config_byte_via_dword, pci_hose_read_config_word_via_dword, tsi108_read_config_dword, @@ -151,22 +151,22 @@ void pci_init_board(void) pci_hose_write_config_word_via_dword, tsi108_write_config_dword); - pci_register_hose(hose); + pci_register_hose (hose); - hose->last_busno = pci_hose_scan(hose); + hose->last_busno = pci_hose_scan (hose); - debug("Done PCI initialization\n"); + debug ("Done PCI initialization\n"); return; } #ifdef CONFIG_OF_FLAT_TREE void -ft_pci_setup(void *blob, bd_t *bd) +ft_pci_setup (void *blob, bd_t *bd) { u32 *p; int len; - p = (u32 *)ft_get_prop(blob, "/" OF_TSI "/pci@1000/bus-range", &len); + p = (u32 *)ft_get_prop (blob, "/" OF_TSI "/pci@1000/bus-range", &len); if (p != NULL) { p[0] = local_hose.first_busno; p[1] = local_hose.last_busno; diff --git a/include/configs/mpc7448hpc2.h b/include/configs/mpc7448hpc2.h index 24cc86b..b13b699 100644 --- a/include/configs/mpc7448hpc2.h +++ b/include/configs/mpc7448hpc2.h @@ -24,12 +24,11 @@ * MA 02111-1307 USA */ -/**************************************************************** - * +/* * board specific configuration options for Freescale * MPC7448HPC2 (High-Performance Computing II) (Taiga) board * - ****************************************************************/ + */ #ifndef __CONFIG_H #define __CONFIG_H @@ -45,11 +44,11 @@ #define CONFIG_750FX /* this option to enable init of extended BATs */ #define CONFIG_ALTIVEC /* undef to disable */ -#define CFG_BOARD_NAME "MPC7448 HPC II" -#define CONFIG_IDENT_STRING " Freescale MPC7448 HPC II" +#define CFG_BOARD_NAME "MPC7448 HPC II" +#define CONFIG_IDENT_STRING " Freescale MPC7448 HPC II" -#define CFG_OCN_CLK 133000000 /* 133 MHz */ -#define CFG_CONFIG_BUS_CLK 133000000 +#define CFG_OCN_CLK 133000000 /* 133 MHz */ +#define CFG_CONFIG_BUS_CLK 133000000 #define CFG_CLK_SPREAD /* Enable Spread-Spectrum Clock generation */ @@ -63,10 +62,10 @@ /* Default MAC Addresses for on-chip GIGE Controller */ -#define CONFIG_ETHADDR 00:06:D2:00:00:01 +#define CONFIG_ETHADDR 00:06:D2:00:00:01 #define CONFIG_HAS_ETH1 -#define CONFIG_ETH1ADDR 00:06:D2:00:00:02 +#define CONFIG_ETH1ADDR 00:06:D2:00:00:02 #define CONFIG_ENV_OVERWRITE @@ -75,12 +74,12 @@ * (easy to change) */ -#define CONFIG_BAUDRATE 115200 /* console baudrate = 115000 */ +#define CONFIG_BAUDRATE 115200 /* console baudrate = 115000 */ /*#define CFG_HUSH_PARSER */ #undef CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " +#define CFG_PROMPT_HUSH_PS2 "> " /* Pass open firmware flat tree */ #define CONFIG_OF_FLAT_TREE 1 @@ -99,29 +98,30 @@ * for your console driver. * * what to do: - * If you have hacked a serial cable onto the second DUART channel, change the CFG_DUART port from 1 - * to 0 below. + * If you have hacked a serial cable onto the second DUART channel, + * change the CFG_DUART port from 1 to 0 below. * */ -#define CONFIG_CONS_INDEX 1 +#define CONFIG_CONS_INDEX 1 #define CFG_NS16550 #define CFG_NS16550_SERIAL -#define CFG_NS16550_REG_SIZE 1 +#define CFG_NS16550_REG_SIZE 1 #define CFG_NS16550_CLK CFG_OCN_CLK * 8 -#define CFG_NS16550_COM1 (CFG_TSI108_CSR_RST_BASE+0x7808) -#define CFG_NS16550_COM2 (CFG_TSI108_CSR_RST_BASE+0x7C08) +#define CFG_NS16550_COM1 (CFG_TSI108_CSR_RST_BASE+0x7808) +#define CFG_NS16550_COM2 (CFG_TSI108_CSR_RST_BASE+0x7C08) #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } -#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ +#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ #define CONFIG_ZERO_BOOTDELAY_CHECK #undef CONFIG_BOOTARGS -/*#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" */ +/* #define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" + * to mount root filesystem over NFS;echo" */ #if (CONFIG_BOOTDELAY >= 0) -#define CONFIG_BOOTCOMMAND "tftpboot 0x400000 zImage.initrd.elf;\ +#define CONFIG_BOOTCOMMAND "tftpboot 0x400000 zImage.initrd.elf;\ setenv bootargs $(bootargs) $(bootargs_root) nfsroot=$(serverip):$(rootpath) \ ip=$(ipaddr):$(serverip)$(bootargs_end); bootm 0x400000; " @@ -130,34 +130,34 @@ #undef CONFIG_EXTRA_ENV_SETTINGS -#define CONFIG_SERIAL "No. 1" +#define CONFIG_SERIAL "No. 1" /* Networking Configuration */ -#define KSEG1ADDR(a) (a) /* Needed by the rtl8139 driver */ +#define KSEG1ADDR(a) (a) /* Needed by the rtl8139 driver */ #define CONFIG_TSI108_ETH -#define CONFIG_TSI108_ETH_NUM_PORTS 2 +#define CONFIG_TSI108_ETH_NUM_PORTS 2 #define CONFIG_NET_MULTI -#define CONFIG_IPADDR 172.27.234.48 -#define CONFIG_SERVERIP 172.27.234.10 -#define CONFIG_NETMASK 255.255.0.0 -#define CONFIG_GATEWAYIP 172.27.255.254 +#define CONFIG_IPADDR 172.27.234.48 +#define CONFIG_SERVERIP 172.27.234.10 +#define CONFIG_NETMASK 255.255.0.0 +#define CONFIG_GATEWAYIP 172.27.255.254 -#define CONFIG_BOOTFILE zImage.initrd.elf -#define CONFIG_LOADADDR 0x400000 +#define CONFIG_BOOTFILE zImage.initrd.elf +#define CONFIG_LOADADDR 0x400000 /*-------------------------------------------------------------------------- */ -#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */ +#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */ #define CFG_LOADS_BAUD_CHANGE /* allow baudrate changes */ #undef CONFIG_WATCHDOG /* watchdog disabled */ -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \ - CONFIG_BOOTP_BOOTFILESIZE) +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \ + CONFIG_BOOTP_BOOTFILESIZE) #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ | CFG_CMD_ASKENV \ @@ -178,59 +178,59 @@ /*set date in u-boot*/ #define CONFIG_RTC_M48T35A -#define CFG_NVRAM_BASE_ADDR 0xfc000000 -#define CFG_NVRAM_SIZE 0x8000 +#define CFG_NVRAM_BASE_ADDR 0xfc000000 +#define CFG_NVRAM_SIZE 0x8000 /* * Miscellaneous configurable options */ -#define CONFIG_VERSION_VARIABLE 1 +#define CONFIG_VERSION_VARIABLE 1 #define CONFIG_TSI108_I2C -#define CFG_I2C_EEPROM_ADDR 0x50 /* I2C EEPROM page 1 */ -#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ +#define CFG_I2C_EEPROM_ADDR 0x50 /* I2C EEPROM page 1 */ +#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ #if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */ +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */ #else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ #endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)/* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ /* #define CFG_DRAM_TEST - * DRAM tests - * CFG_DRAM_TEST - enables the following tests. + * DRAM tests + * CFG_DRAM_TEST - enables the following tests. * - * CFG_DRAM_TEST_DATA - Enables test for shorted or open data lines - * Environment variable 'test_dram_data' must be - * set to 'y'. - * CFG_DRAM_TEST_ADDRESS - Enables test to verify that each word is uniquely - * addressable. Environment variable - * 'test_dram_address' must be set to 'y'. - * CFG_DRAM_TEST_WALK - Enables test a 64-bit walking ones pattern test. - * This test takes about 6 minutes to test 64 MB. - * Environment variable 'test_dram_walk' must be - * set to 'y'. + * CFG_DRAM_TEST_DATA - Enables test for shorted or open data lines + * Environment variable 'test_dram_data' must be + * set to 'y'. + * CFG_DRAM_TEST_ADDRESS - Enables test to verify that each word + * is uniquely addressable. Environment variable + * 'test_dram_address' must be set to 'y'. + * CFG_DRAM_TEST_WALK - Enables test a 64-bit walking ones pattern test. + * This test takes about 6 minutes to test 64 MB. + * Environment variable 'test_dram_walk' must be + * set to 'y'. */ #undef CFG_DRAM_TEST -#define CFG_MEMTEST_START 0x00400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x07c00000 /* 4 ... 124 MB in DRAM */ +#define CFG_MEMTEST_START 0x00400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x07c00000 /* 4 ... 124 MB in DRAM */ #if defined(CFG_DRAM_TEST) #define CFG_DRAM_TEST_DATA #define CFG_DRAM_TEST_ADDRESS #define CFG_DRAM_TEST_WALK -#endif /* CFG_DRAM_TEST */ +#endif /* CFG_DRAM_TEST */ -#define CFG_LOAD_ADDR 0x00400000 /* default load address */ +#define CFG_LOAD_ADDR 0x00400000 /* default load address */ -#define CFG_HZ 1000 /* decr freq: 1ms ticks */ +#define CFG_HZ 1000 /* decr freq: 1ms ticks */ /* * Low Level Configuration Settings @@ -246,12 +246,12 @@ * When locking data in cache you should point the CFG_INIT_RAM_ADDRESS * To an unused memory region. The stack will remain in cache until RAM * is initialized -*/ + */ #undef CFG_INIT_RAM_LOCK -#define CFG_INIT_RAM_ADDR 0x07d00000 /* unused memory region */ -#define CFG_INIT_RAM_END 0x4000 /* larger space - we have SDRAM initialized */ +#define CFG_INIT_RAM_ADDR 0x07d00000 /* unused memory region */ +#define CFG_INIT_RAM_END 0x4000/* larger space - we have SDRAM initialized */ -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for init data */ +#define CFG_GBL_DATA_SIZE 128/* size in bytes reserved for init data */ #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) /*----------------------------------------------------------------------- @@ -260,54 +260,54 @@ * Please note that CFG_SDRAM_BASE _must_ start at 0 */ -#define CFG_SDRAM_BASE 0x00000000 /* first 256 MB of SDRAM */ -#define CFG_SDRAM1_BASE 0x10000000 /* next 256MB of SDRAM */ +#define CFG_SDRAM_BASE 0x00000000 /* first 256 MB of SDRAM */ +#define CFG_SDRAM1_BASE 0x10000000 /* next 256MB of SDRAM */ -#define CFG_SDRAM2_BASE 0x40000000 /* beginning of non-cacheable alias for SDRAM - first 256MB */ -#define CFG_SDRAM3_BASE 0x50000000 /* next Non-Cacheable 256MB of SDRAM */ +#define CFG_SDRAM2_BASE 0x40000000 /* beginning of non-cacheable alias for SDRAM - first 256MB */ +#define CFG_SDRAM3_BASE 0x50000000 /* next Non-Cacheable 256MB of SDRAM */ -#define CFG_PCI_PFM_BASE 0x80000000 /* Prefetchable (cacheable) PCI/X PFM and SDRAM OCN (128MB+128MB) */ +#define CFG_PCI_PFM_BASE 0x80000000 /* Prefetchable (cacheable) PCI/X PFM and SDRAM OCN (128MB+128MB) */ -#define CFG_PCI_MEM32_BASE 0xE0000000 /* Non-Cacheable PCI/X MEM and SDRAM OCN (128MB+128MB) */ +#define CFG_PCI_MEM32_BASE 0xE0000000 /* Non-Cacheable PCI/X MEM and SDRAM OCN (128MB+128MB) */ -#define CFG_MISC_REGION_BASE 0xf0000000 /* Base Address for (PCI/X + Flash) region */ +#define CFG_MISC_REGION_BASE 0xf0000000 /* Base Address for (PCI/X + Flash) region */ -#define CFG_FLASH_BASE 0xff000000 /* Base Address of Flash device */ -#define CFG_FLASH_BASE2 0xfe000000 /* Alternate Flash Base Address */ +#define CFG_FLASH_BASE 0xff000000 /* Base Address of Flash device */ +#define CFG_FLASH_BASE2 0xfe000000 /* Alternate Flash Base Address */ #define CONFIG_VERY_BIG_RAM /* we will use up to 256M memory for cause we are short of BATS */ -#define PCI0_IO_BASE_BOOTM 0xfd000000 +#define PCI0_IO_BASE_BOOTM 0xfd000000 -#define CFG_RESET_ADDRESS 0x3fffff00 -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CFG_MONITOR_BASE TEXT_BASE /* u-boot code base */ -#define CFG_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc */ +#define CFG_RESET_ADDRESS 0x3fffff00 +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#define CFG_MONITOR_BASE TEXT_BASE /* u-boot code base */ +#define CFG_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc */ /* Peripheral Device section */ -/******************************************************* +/* * Resources on the Tsi108 - *******************************************************/ + */ -#define CFG_TSI108_CSR_RST_BASE 0xC0000000 /* Tsi108 CSR base after reset */ -#define CFG_TSI108_CSR_BASE CFG_TSI108_CSR_RST_BASE /* Runtime Tsi108 CSR base */ +#define CFG_TSI108_CSR_RST_BASE 0xC0000000 /* Tsi108 CSR base after reset */ +#define CFG_TSI108_CSR_BASE CFG_TSI108_CSR_RST_BASE /* Runtime Tsi108 CSR base */ #define ENABLE_PCI_CSR_BAR /* enables access to Tsi108 CSRs from the PCI/X bus */ #undef DISABLE_PBM -/*----------------------------------------------------------------------- +/* * PCI stuff - *----------------------------------------------------------------------- + * */ #define CONFIG_PCI /* include pci support */ #define CONFIG_TSI108_PCI /* include tsi108 pci support */ -#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ -#define PCI_HOST_FORCE 1 /* configure as pci host */ -#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ +#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ +#define PCI_HOST_FORCE 1 /* configure as pci host */ +#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ #define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ #define CONFIG_PCI_PNP /* do pci plug-and-play */ @@ -315,20 +315,20 @@ /* PCI MEMORY MAP section */ /* PCI view of System Memory */ -#define CFG_PCI_MEMORY_BUS 0x00000000 -#define CFG_PCI_MEMORY_PHYS 0x00000000 -#define CFG_PCI_MEMORY_SIZE 0x80000000 +#define CFG_PCI_MEMORY_BUS 0x00000000 +#define CFG_PCI_MEMORY_PHYS 0x00000000 +#define CFG_PCI_MEMORY_SIZE 0x80000000 /* PCI Memory Space */ -#define CFG_PCI_MEM_BUS (CFG_PCI_MEM_PHYS) -#define CFG_PCI_MEM_PHYS (CFG_PCI_MEM32_BASE) //CFG_PCI_MEM32_BASE = 0xE0000000 -#define CFG_PCI_MEM_SIZE 0x10000000 /* 256 MB space for PCI/X Mem + SDRAM OCN */ +#define CFG_PCI_MEM_BUS (CFG_PCI_MEM_PHYS) +#define CFG_PCI_MEM_PHYS (CFG_PCI_MEM32_BASE) /* 0xE0000000 */ +#define CFG_PCI_MEM_SIZE 0x10000000 /* 256 MB space for PCI/X Mem + SDRAM OCN */ /* PCI I/O Space */ -#define CFG_PCI_IO_BUS 0x00000000 -#define CFG_PCI_IO_PHYS 0xfa000000 /* Changed from fd000000 */ +#define CFG_PCI_IO_BUS 0x00000000 +#define CFG_PCI_IO_PHYS 0xfa000000 /* Changed from fd000000 */ -#define CFG_PCI_IO_SIZE 0x01000000 /* 16MB */ +#define CFG_PCI_IO_SIZE 0x01000000 /* 16MB */ #define _IO_BASE 0x00000000 /* points to PCI I/O space */ @@ -336,91 +336,91 @@ #define CFG_PCI_CFG_BASE 0xfb000000 /* Changed from FE000000 */ #define CFG_PCI_CFG_SIZE 0x01000000 /* 16MB */ -#define CFG_IBAT0U 0xFE0003FF -#define CFG_IBAT0L 0xFE000002 +#define CFG_IBAT0U 0xFE0003FF +#define CFG_IBAT0L 0xFE000002 -#define CFG_IBAT1U 0x00007FFF -#define CFG_IBAT1L 0x00000012 +#define CFG_IBAT1U 0x00007FFF +#define CFG_IBAT1L 0x00000012 -#define CFG_IBAT2U 0x80007FFF -#define CFG_IBAT2L 0x80000022 +#define CFG_IBAT2U 0x80007FFF +#define CFG_IBAT2L 0x80000022 -#define CFG_IBAT3U 0x00000000 -#define CFG_IBAT3L 0x00000000 +#define CFG_IBAT3U 0x00000000 +#define CFG_IBAT3L 0x00000000 -#define CFG_IBAT4U 0x00000000 -#define CFG_IBAT4L 0x00000000 +#define CFG_IBAT4U 0x00000000 +#define CFG_IBAT4L 0x00000000 -#define CFG_IBAT5U 0x00000000 -#define CFG_IBAT5L 0x00000000 +#define CFG_IBAT5U 0x00000000 +#define CFG_IBAT5L 0x00000000 -#define CFG_IBAT6U 0x00000000 -#define CFG_IBAT6L 0x00000000 +#define CFG_IBAT6U 0x00000000 +#define CFG_IBAT6L 0x00000000 -#define CFG_IBAT7U 0x00000000 -#define CFG_IBAT7L 0x00000000 +#define CFG_IBAT7U 0x00000000 +#define CFG_IBAT7L 0x00000000 -#define CFG_DBAT0U 0xE0003FFF -#define CFG_DBAT0L 0xE000002A +#define CFG_DBAT0U 0xE0003FFF +#define CFG_DBAT0L 0xE000002A -#define CFG_DBAT1U 0x00007FFF -#define CFG_DBAT1L 0x00000012 +#define CFG_DBAT1U 0x00007FFF +#define CFG_DBAT1L 0x00000012 -#define CFG_DBAT2U 0x00000000 -#define CFG_DBAT2L 0x00000000 +#define CFG_DBAT2U 0x00000000 +#define CFG_DBAT2L 0x00000000 -#define CFG_DBAT3U 0xC0000003 -#define CFG_DBAT3L 0xC000002A +#define CFG_DBAT3U 0xC0000003 +#define CFG_DBAT3L 0xC000002A -#define CFG_DBAT4U 0x00000000 -#define CFG_DBAT4L 0x00000000 +#define CFG_DBAT4U 0x00000000 +#define CFG_DBAT4L 0x00000000 -#define CFG_DBAT5U 0x00000000 -#define CFG_DBAT5L 0x00000000 +#define CFG_DBAT5U 0x00000000 +#define CFG_DBAT5L 0x00000000 -#define CFG_DBAT6U 0x00000000 -#define CFG_DBAT6L 0x00000000 +#define CFG_DBAT6U 0x00000000 +#define CFG_DBAT6L 0x00000000 -#define CFG_DBAT7U 0x00000000 -#define CFG_DBAT7L 0x00000000 +#define CFG_DBAT7U 0x00000000 +#define CFG_DBAT7L 0x00000000 /* I2C addresses for the two DIMM SPD chips */ -#define DIMM0_I2C_ADDR 0x51 -#define DIMM1_I2C_ADDR 0x52 +#define DIMM0_I2C_ADDR 0x51 +#define DIMM1_I2C_ADDR 0x52 /* * For booting Linux, the board info and command line data * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CFG_BOOTMAPSZ (8<<20) /* Initial Memory map for Linux */ +#define CFG_BOOTMAPSZ (8<<20) /* Initial Memory map for Linux */ /*----------------------------------------------------------------------- * FLASH organization */ -#define CFG_MAX_FLASH_BANKS 1 /* Flash can be at one of two addresses */ -#define FLASH_BANK_SIZE 0x01000000 /* 16 MB Total */ +#define CFG_MAX_FLASH_BANKS 1/* Flash can be at one of two addresses */ +#define FLASH_BANK_SIZE 0x01000000 /* 16 MB Total */ #define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE, CFG_FLASH_BASE2} #define CFG_FLASH_CFI_DRIVER #define CFG_FLASH_CFI #define CFG_FLASH_CFI_SWAP -#define PHYS_FLASH_SIZE 0x01000000 -#define CFG_MAX_FLASH_SECT (128) +#define PHYS_FLASH_SIZE 0x01000000 +#define CFG_MAX_FLASH_SECT (128) #define CFG_ENV_IS_IN_NVRAM -#define CFG_ENV_ADDR 0xFC000000 +#define CFG_ENV_ADDR 0xFC000000 -#define CFG_ENV_OFFSET 0x00000000 /* Offset of Environment Sector */ -#define CFG_ENV_SIZE 0x00000400 /* Total Size of Environment Space */ +#define CFG_ENV_OFFSET 0x00000000 /* Offset of Environment Sector */ +#define CFG_ENV_SIZE 0x00000400 /* Total Size of Environment Space */ /*----------------------------------------------------------------------- * Cache Configuration */ -#define CFG_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */ +#define CFG_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */ #if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif /*----------------------------------------------------------------------- @@ -429,16 +429,16 @@ */ #undef CFG_L2 -#define L2_INIT 0 -#define L2_ENABLE (L2_INIT | L2CR_L2E) +#define L2_INIT 0 +#define L2_ENABLE (L2_INIT | L2CR_L2E) /* * Internal Definitions * * Boot Flags */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ #define CFG_EXCEPTION_AFTER_RELOCATE #define CFG_SERIAL_HANG_IN_EXCEPTION -#endif /* __CONFIG_H */ +#endif /* __CONFIG_H */ diff --git a/include/tsi108.h b/include/tsi108.h index 072daa0..ba62e7a 100644 --- a/include/tsi108.h +++ b/include/tsi108.h @@ -31,191 +31,191 @@ #ifndef _TSI108_H_ #define _TSI108_H_ -#define TSI108_HLP_REG_OFFSET (0x0000) -#define TSI108_PCI_REG_OFFSET (0x1000) -#define TSI108_CLK_REG_OFFSET (0x2000) -#define TSI108_PB_REG_OFFSET (0x3000) -#define TSI108_SD_REG_OFFSET (0x4000) -#define TSI108_MPIC_REG_OFFSET (0x7400) - -#define PB_ID (0x000) -#define PB_RSR (0x004) -#define PB_BUS_MS_SELECT (0x008) -#define PB_ISR (0x00C) -#define PB_ARB_CTRL (0x018) -#define PB_PVT_CTRL2 (0x034) -#define PB_SCR (0x400) -#define PB_ERRCS (0x404) -#define PB_AERR (0x408) -#define PB_REG_BAR (0x410) -#define PB_OCN_BAR1 (0x414) -#define PB_OCN_BAR2 (0x418) -#define PB_SDRAM_BAR1 (0x41C) -#define PB_SDRAM_BAR2 (0x420) -#define PB_MCR (0xC00) -#define PB_MCMD (0xC04) - -#define HLP_B0_ADDR (0x000) -#define HLP_B1_ADDR (0x010) -#define HLP_B2_ADDR (0x020) -#define HLP_B3_ADDR (0x030) - -#define HLP_B0_MASK (0x004) -#define HLP_B1_MASK (0x014) -#define HLP_B2_MASK (0x024) -#define HLP_B3_MASK (0x034) - -#define HLP_B0_CTRL0 (0x008) -#define HLP_B1_CTRL0 (0x018) -#define HLP_B2_CTRL0 (0x028) -#define HLP_B3_CTRL0 (0x038) - -#define HLP_B0_CTRL1 (0x00C) -#define HLP_B1_CTRL1 (0x01C) -#define HLP_B2_CTRL1 (0x02C) -#define HLP_B3_CTRL1 (0x03C) - -#define PCI_CSR (0x004) -#define PCI_P2O_BAR0 (0x010) -#define PCI_P2O_BAR0_UPPER (0x014) -#define PCI_P2O_BAR2 (0x018) -#define PCI_P2O_BAR2_UPPER (0x01C) -#define PCI_P2O_BAR3 (0x020) -#define PCI_P2O_BAR3_UPPER (0x024) - -#define PCI_MISC_CSR (0x040) -#define PCI_P2O_PAGE_SIZES (0x04C) - -#define PCI_PCIX_STAT (0x0F4) - -#define PCI_IRP_STAT (0x184) - -#define PCI_PFAB_BAR0 (0x204) -#define PCI_PFAB_BAR0_UPPER (0x208) -#define PCI_PFAB_IO (0x20C) -#define PCI_PFAB_IO_UPPER (0x210) - -#define PCI_PFAB_MEM32 (0x214) -#define PCI_PFAB_MEM32_REMAP (0x218) -#define PCI_PFAB_MEM32_MASK (0x21C) - -#define CG_PLL0_CTRL0 (0x210) -#define CG_PLL0_CTRL1 (0x214) -#define CG_PLL1_CTRL0 (0x220) -#define CG_PLL1_CTRL1 (0x224) -#define CG_PWRUP_STATUS (0x234) +#define TSI108_HLP_REG_OFFSET (0x0000) +#define TSI108_PCI_REG_OFFSET (0x1000) +#define TSI108_CLK_REG_OFFSET (0x2000) +#define TSI108_PB_REG_OFFSET (0x3000) +#define TSI108_SD_REG_OFFSET (0x4000) +#define TSI108_MPIC_REG_OFFSET (0x7400) + +#define PB_ID (0x000) +#define PB_RSR (0x004) +#define PB_BUS_MS_SELECT (0x008) +#define PB_ISR (0x00C) +#define PB_ARB_CTRL (0x018) +#define PB_PVT_CTRL2 (0x034) +#define PB_SCR (0x400) +#define PB_ERRCS (0x404) +#define PB_AERR (0x408) +#define PB_REG_BAR (0x410) +#define PB_OCN_BAR1 (0x414) +#define PB_OCN_BAR2 (0x418) +#define PB_SDRAM_BAR1 (0x41C) +#define PB_SDRAM_BAR2 (0x420) +#define PB_MCR (0xC00) +#define PB_MCMD (0xC04) + +#define HLP_B0_ADDR (0x000) +#define HLP_B1_ADDR (0x010) +#define HLP_B2_ADDR (0x020) +#define HLP_B3_ADDR (0x030) + +#define HLP_B0_MASK (0x004) +#define HLP_B1_MASK (0x014) +#define HLP_B2_MASK (0x024) +#define HLP_B3_MASK (0x034) + +#define HLP_B0_CTRL0 (0x008) +#define HLP_B1_CTRL0 (0x018) +#define HLP_B2_CTRL0 (0x028) +#define HLP_B3_CTRL0 (0x038) + +#define HLP_B0_CTRL1 (0x00C) +#define HLP_B1_CTRL1 (0x01C) +#define HLP_B2_CTRL1 (0x02C) +#define HLP_B3_CTRL1 (0x03C) + +#define PCI_CSR (0x004) +#define PCI_P2O_BAR0 (0x010) +#define PCI_P2O_BAR0_UPPER (0x014) +#define PCI_P2O_BAR2 (0x018) +#define PCI_P2O_BAR2_UPPER (0x01C) +#define PCI_P2O_BAR3 (0x020) +#define PCI_P2O_BAR3_UPPER (0x024) + +#define PCI_MISC_CSR (0x040) +#define PCI_P2O_PAGE_SIZES (0x04C) + +#define PCI_PCIX_STAT (0x0F4) + +#define PCI_IRP_STAT (0x184) + +#define PCI_PFAB_BAR0 (0x204) +#define PCI_PFAB_BAR0_UPPER (0x208) +#define PCI_PFAB_IO (0x20C) +#define PCI_PFAB_IO_UPPER (0x210) + +#define PCI_PFAB_MEM32 (0x214) +#define PCI_PFAB_MEM32_REMAP (0x218) +#define PCI_PFAB_MEM32_MASK (0x21C) + +#define CG_PLL0_CTRL0 (0x210) +#define CG_PLL0_CTRL1 (0x214) +#define CG_PLL1_CTRL0 (0x220) +#define CG_PLL1_CTRL1 (0x224) +#define CG_PWRUP_STATUS (0x234) #define MPIC_CSR(n) (0x30C + (n * 0x40)) -#define SD_CTRL (0x000) -#define SD_STATUS (0x004) -#define SD_TIMING (0x008) -#define SD_REFRESH (0x00C) -#define SD_INT_STATUS (0x010) -#define SD_INT_ENABLE (0x014) -#define SD_INT_SET (0x018) -#define SD_D0_CTRL (0x020) -#define SD_D1_CTRL (0x024) -#define SD_D0_BAR (0x028) -#define SD_D1_BAR (0x02C) -#define SD_ECC_CTRL (0x040) -#define SD_DLL_STATUS (0x250) - -#define TS_SD_CTRL_ENABLE (1 << 31) - -#define PB_ERRCS_ES (1 << 1) -#define PB_ISR_PBS_RD_ERR (1 << 8) -#define PCI_IRP_STAT_P_CSR (1 << 23) - -/* +#define SD_CTRL (0x000) +#define SD_STATUS (0x004) +#define SD_TIMING (0x008) +#define SD_REFRESH (0x00C) +#define SD_INT_STATUS (0x010) +#define SD_INT_ENABLE (0x014) +#define SD_INT_SET (0x018) +#define SD_D0_CTRL (0x020) +#define SD_D1_CTRL (0x024) +#define SD_D0_BAR (0x028) +#define SD_D1_BAR (0x02C) +#define SD_ECC_CTRL (0x040) +#define SD_DLL_STATUS (0x250) + +#define TS_SD_CTRL_ENABLE (1 << 31) + +#define PB_ERRCS_ES (1 << 1) +#define PB_ISR_PBS_RD_ERR (1 << 8) +#define PCI_IRP_STAT_P_CSR (1 << 23) + +/* * I2C : Register address offset definitions */ -#define I2C_CNTRL1 (0x00000000) -#define I2C_CNTRL2 (0x00000004) -#define I2C_RD_DATA (0x00000008) -#define I2C_TX_DATA (0x0000000c) +#define I2C_CNTRL1 (0x00000000) +#define I2C_CNTRL2 (0x00000004) +#define I2C_RD_DATA (0x00000008) +#define I2C_TX_DATA (0x0000000c) /* * I2C : Register Bit Masks and Reset Values - * definitions for every register + * definitions for every register */ /* I2C_CNTRL1 : Reset Value */ -#define I2C_CNTRL1_RESET_VALUE (0x0000000a) +#define I2C_CNTRL1_RESET_VALUE (0x0000000a) /* I2C_CNTRL1 : Register Bits Masks Definitions */ -#define I2C_CNTRL1_DEVCODE (0x0000000f) -#define I2C_CNTRL1_PAGE (0x00000700) -#define I2C_CNTRL1_BYTADDR (0x00ff0000) -#define I2C_CNTRL1_I2CWRITE (0x01000000) +#define I2C_CNTRL1_DEVCODE (0x0000000f) +#define I2C_CNTRL1_PAGE (0x00000700) +#define I2C_CNTRL1_BYTADDR (0x00ff0000) +#define I2C_CNTRL1_I2CWRITE (0x01000000) /* I2C_CNTRL1 : Read/Write Bit Mask Definition */ -#define I2C_CNTRL1_RWMASK (0x01ff070f) +#define I2C_CNTRL1_RWMASK (0x01ff070f) /* I2C_CNTRL1 : Unused/Reserved bits Definition */ -#define I2C_CNTRL1_RESERVED (0xfe00f8f0) +#define I2C_CNTRL1_RESERVED (0xfe00f8f0) /* I2C_CNTRL2 : Reset Value */ -#define I2C_CNTRL2_RESET_VALUE (0x00000000) +#define I2C_CNTRL2_RESET_VALUE (0x00000000) /* I2C_CNTRL2 : Register Bits Masks Definitions */ -#define I2C_CNTRL2_SIZE (0x00000003) -#define I2C_CNTRL2_LANE (0x0000000c) -#define I2C_CNTRL2_MULTIBYTE (0x00000010) -#define I2C_CNTRL2_START (0x00000100) -#define I2C_CNTRL2_WR_STATUS (0x00010000) -#define I2C_CNTRL2_RD_STATUS (0x00020000) -#define I2C_CNTRL2_I2C_TO_ERR (0x04000000) -#define I2C_CNTRL2_I2C_CFGERR (0x08000000) -#define I2C_CNTRL2_I2C_CMPLT (0x10000000) +#define I2C_CNTRL2_SIZE (0x00000003) +#define I2C_CNTRL2_LANE (0x0000000c) +#define I2C_CNTRL2_MULTIBYTE (0x00000010) +#define I2C_CNTRL2_START (0x00000100) +#define I2C_CNTRL2_WR_STATUS (0x00010000) +#define I2C_CNTRL2_RD_STATUS (0x00020000) +#define I2C_CNTRL2_I2C_TO_ERR (0x04000000) +#define I2C_CNTRL2_I2C_CFGERR (0x08000000) +#define I2C_CNTRL2_I2C_CMPLT (0x10000000) /* I2C_CNTRL2 : Read/Write Bit Mask Definition */ -#define I2C_CNTRL2_RWMASK (0x0000011f) +#define I2C_CNTRL2_RWMASK (0x0000011f) /* I2C_CNTRL2 : Unused/Reserved bits Definition */ -#define I2C_CNTRL2_RESERVED (0xe3fcfee0) +#define I2C_CNTRL2_RESERVED (0xe3fcfee0) /* I2C_RD_DATA : Reset Value */ -#define I2C_RD_DATA_RESET_VALUE (0x00000000) +#define I2C_RD_DATA_RESET_VALUE (0x00000000) /* I2C_RD_DATA : Register Bits Masks Definitions */ -#define I2C_RD_DATA_RBYTE0 (0x000000ff) -#define I2C_RD_DATA_RBYTE1 (0x0000ff00) -#define I2C_RD_DATA_RBYTE2 (0x00ff0000) -#define I2C_RD_DATA_RBYTE3 (0xff000000) +#define I2C_RD_DATA_RBYTE0 (0x000000ff) +#define I2C_RD_DATA_RBYTE1 (0x0000ff00) +#define I2C_RD_DATA_RBYTE2 (0x00ff0000) +#define I2C_RD_DATA_RBYTE3 (0xff000000) /* I2C_RD_DATA : Read/Write Bit Mask Definition */ -#define I2C_RD_DATA_RWMASK (0x00000000) +#define I2C_RD_DATA_RWMASK (0x00000000) /* I2C_RD_DATA : Unused/Reserved bits Definition */ -#define I2C_RD_DATA_RESERVED (0x00000000) +#define I2C_RD_DATA_RESERVED (0x00000000) /* I2C_TX_DATA : Reset Value */ -#define I2C_TX_DATA_RESET_VALUE (0x00000000) +#define I2C_TX_DATA_RESET_VALUE (0x00000000) /* I2C_TX_DATA : Register Bits Masks Definitions */ -#define I2C_TX_DATA_TBYTE0 (0x000000ff) -#define I2C_TX_DATA_TBYTE1 (0x0000ff00) -#define I2C_TX_DATA_TBYTE2 (0x00ff0000) -#define I2C_TX_DATA_TBYTE3 (0xff000000) +#define I2C_TX_DATA_TBYTE0 (0x000000ff) +#define I2C_TX_DATA_TBYTE1 (0x0000ff00) +#define I2C_TX_DATA_TBYTE2 (0x00ff0000) +#define I2C_TX_DATA_TBYTE3 (0xff000000) /* I2C_TX_DATA : Read/Write Bit Mask Definition */ -#define I2C_TX_DATA_RWMASK (0xffffffff) +#define I2C_TX_DATA_RWMASK (0xffffffff) /* I2C_TX_DATA : Unused/Reserved bits Definition */ -#define I2C_TX_DATA_RESERVED (0x00000000) +#define I2C_TX_DATA_RESERVED (0x00000000) -#define TSI108_I2C_OFFSET 0x7000 /* register block offset for general use I2C channel */ -#define TSI108_I2C_SDRAM_OFFSET 0x4400 /* register block offset for SPD I2C channel */ +#define TSI108_I2C_OFFSET 0x7000 /* offset for general use I2C channel */ +#define TSI108_I2C_SDRAM_OFFSET 0x4400 /* offset for SPD I2C channel */ -#define I2C_EEPROM_DEVCODE 0xA /* standard I2C EEPROM device code */ +#define I2C_EEPROM_DEVCODE 0xA /* standard I2C EEPROM device code */ /* I2C status codes */ -#define TSI108_I2C_SUCCESS 0 -#define TSI108_I2C_PARAM_ERR 1 -#define TSI108_I2C_TIMEOUT_ERR 2 -#define TSI108_I2C_IF_BUSY 3 -#define TSI108_I2C_IF_ERROR 4 +#define TSI108_I2C_SUCCESS 0 +#define TSI108_I2C_PARAM_ERR 1 +#define TSI108_I2C_TIMEOUT_ERR 2 +#define TSI108_I2C_IF_BUSY 3 +#define TSI108_I2C_IF_ERROR 4 #endif /* _TSI108_H_ */ |