diff options
Diffstat (limited to 'board/amcc/acadia')
| -rw-r--r-- | board/amcc/acadia/Makefile | 51 | ||||
| -rw-r--r-- | board/amcc/acadia/acadia.c | 118 | ||||
| -rw-r--r-- | board/amcc/acadia/cmd_acadia.c | 99 | ||||
| -rw-r--r-- | board/amcc/acadia/config.mk | 37 | ||||
| -rw-r--r-- | board/amcc/acadia/memory.c | 110 | ||||
| -rw-r--r-- | board/amcc/acadia/pll.c | 195 | ||||
| -rw-r--r-- | board/amcc/acadia/u-boot-nand.lds | 103 |
7 files changed, 0 insertions, 713 deletions
diff --git a/board/amcc/acadia/Makefile b/board/amcc/acadia/Makefile deleted file mode 100644 index b277287..0000000 --- a/board/amcc/acadia/Makefile +++ /dev/null @@ -1,51 +0,0 @@ -# -# (C) Copyright 2007 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS = $(BOARD).o cmd_acadia.o memory.o pll.o -SOBJS = - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS)) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak $(obj).depend - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/amcc/acadia/acadia.c b/board/amcc/acadia/acadia.c deleted file mode 100644 index 4825611..0000000 --- a/board/amcc/acadia/acadia.c +++ /dev/null @@ -1,118 +0,0 @@ -/* - * (C) Copyright 2007 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <asm/processor.h> - -extern void board_pll_init_f(void); - -static void acadia_gpio_init(void) -{ - /* - * GPIO0 setup (select GPIO or alternate function) - */ - out32(GPIO0_OSRL, CONFIG_SYS_GPIO0_OSRL); - out32(GPIO0_OSRH, CONFIG_SYS_GPIO0_OSRH); /* output select */ - out32(GPIO0_ISR1L, CONFIG_SYS_GPIO0_ISR1L); - out32(GPIO0_ISR1H, CONFIG_SYS_GPIO0_ISR1H); /* input select */ - out32(GPIO0_TSRL, CONFIG_SYS_GPIO0_TSRL); - out32(GPIO0_TSRH, CONFIG_SYS_GPIO0_TSRH); /* three-state select */ - out32(GPIO0_TCR, CONFIG_SYS_GPIO0_TCR); /* enable output driver for outputs */ - - /* - * Ultra (405EZ) was nice enough to add another GPIO controller - */ - out32(GPIO1_OSRH, CONFIG_SYS_GPIO1_OSRH); /* output select */ - out32(GPIO1_OSRL, CONFIG_SYS_GPIO1_OSRL); - out32(GPIO1_ISR1H, CONFIG_SYS_GPIO1_ISR1H); /* input select */ - out32(GPIO1_ISR1L, CONFIG_SYS_GPIO1_ISR1L); - out32(GPIO1_TSRH, CONFIG_SYS_GPIO1_TSRH); /* three-state select */ - out32(GPIO1_TSRL, CONFIG_SYS_GPIO1_TSRL); - out32(GPIO1_TCR, CONFIG_SYS_GPIO1_TCR); /* enable output driver for outputs */ -} - -int board_early_init_f(void) -{ - unsigned int reg; - -#if !defined(CONFIG_NAND_U_BOOT) - /* don't reinit PLL when booting via I2C bootstrap option */ - mfsdr(SDR0_PINSTP, reg); - if (reg != 0xf0000000) - board_pll_init_f(); -#endif - - acadia_gpio_init(); - - /* Configure 405EZ for NAND usage */ - mtsdr(SDR0_NAND0, SDR_NAND0_NDEN | SDR_NAND0_NDAREN | SDR_NAND0_NDRBEN); - mfsdr(SDR0_ULTRA0, reg); - reg &= ~SDR_ULTRA0_CSN_MASK; - reg |= (SDR_ULTRA0_CSNSEL0 >> CONFIG_SYS_NAND_CS) | - SDR_ULTRA0_NDGPIOBP | - SDR_ULTRA0_EBCRDYEN | - SDR_ULTRA0_NFSRSTEN; - mtsdr(SDR0_ULTRA0, reg); - - /* USB Host core needs this bit set */ - mfsdr(SDR0_ULTRA1, reg); - mtsdr(SDR0_ULTRA1, reg | SDR_ULTRA1_LEDNENABLE); - - mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ - mtdcr(UIC0ER, 0x00000000); /* disable all ints */ - mtdcr(UIC0CR, 0x00000010); - mtdcr(UIC0PR, 0xFE7FFFF0); /* set int polarities */ - mtdcr(UIC0TR, 0x00000010); /* set int trigger levels */ - mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ - - return 0; -} - -int misc_init_f(void) -{ - /* Set EPLD to take PHY out of reset */ - out8(CONFIG_SYS_CPLD_BASE + 0x05, 0x00); - udelay(100000); - - return 0; -} - -/* - * Check Board Identity: - */ -int checkboard(void) -{ - char *s = getenv("serial#"); - u8 rev; - - rev = in8(CONFIG_SYS_CPLD_BASE + 0); - printf("Board: Acadia - AMCC PPC405EZ Evaluation Board, Rev. %X", rev); - - if (s != NULL) { - puts(", serial# "); - puts(s); - } - putc('\n'); - - return (0); -} diff --git a/board/amcc/acadia/cmd_acadia.c b/board/amcc/acadia/cmd_acadia.c deleted file mode 100644 index 6936e51..0000000 --- a/board/amcc/acadia/cmd_acadia.c +++ /dev/null @@ -1,99 +0,0 @@ -/* - * (C) Copyright 2007 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - */ - -#include <common.h> -#include <command.h> -#include <i2c.h> - -static u8 boot_267_nor[] = { - 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x8e, 0x00, - 0x14, 0xc0, 0x36, 0xcc, 0x00, 0x0c, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00 -}; - -static u8 boot_267_nand[] = { - 0xd0, 0x38, 0xc3, 0x50, 0x13, 0x88, 0x8e, 0x00, - 0x14, 0xc0, 0x36, 0xcc, 0x00, 0x0c, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00 -}; - -static int do_bootstrap(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - u8 chip; - u8 *buf; - int cpu_freq; - - if (argc < 3) - return cmd_usage(cmdtp); - - cpu_freq = simple_strtol(argv[1], NULL, 10); - if (cpu_freq != 267) { - printf("Unsupported cpu-frequency - only 267 supported\n"); - return 1; - } - - /* use 0x50 as I2C EEPROM address for now */ - chip = 0x50; - - if ((strcmp(argv[2], "nor") != 0) && - (strcmp(argv[2], "nand") != 0)) { - printf("Unsupported boot-device - only nor|nand support\n"); - return 1; - } - - if (strcmp(argv[2], "nand") == 0) { - switch (cpu_freq) { - case 267: - buf = boot_267_nand; - break; - default: - break; - } - } else { - switch (cpu_freq) { - case 267: - buf = boot_267_nor; - break; - default: - break; - } - } - - if (i2c_write(chip, 0, 1, buf, 16) != 0) - printf("Error writing to EEPROM at address 0x%x\n", chip); - udelay(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS * 1000); - if (i2c_write(chip, 0x10, 1, buf+16, 4) != 0) - printf("Error2 writing to EEPROM at address 0x%x\n", chip); - - printf("Done\n"); - printf("Please power-cycle the board for the changes to take effect\n"); - - return 0; -} - -U_BOOT_CMD( - bootstrap, 3, 0, do_bootstrap, - "program the I2C bootstrap EEPROM", - "<cpu-freq> <nor|nand> - program the I2C bootstrap EEPROM" -); diff --git a/board/amcc/acadia/config.mk b/board/amcc/acadia/config.mk deleted file mode 100644 index 2f2787f..0000000 --- a/board/amcc/acadia/config.mk +++ /dev/null @@ -1,37 +0,0 @@ -# -# (C) Copyright 2007-2010 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# AMCC 405EZ Reference Platform (Acadia) board -# - -ifeq ($(debug),1) -PLATFORM_CPPFLAGS += -DDEBUG -endif - -ifdef CONFIG_SYS_LDSCRIPT -# need to strip off double quotes -LDSCRIPT := $(subst ",,$(CONFIG_SYS_LDSCRIPT)) -else ifdef CONFIG_NAND_U_BOOT -LDSCRIPT := $(TOPDIR)/board/$(BOARDDIR)/u-boot-nand.lds -endif diff --git a/board/amcc/acadia/memory.c b/board/amcc/acadia/memory.c deleted file mode 100644 index 703a668..0000000 --- a/board/amcc/acadia/memory.c +++ /dev/null @@ -1,110 +0,0 @@ -/* - * (C) Copyright 2007 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* define DEBUG for debugging output (obviously ;-)) */ -#if 0 -#define DEBUG -#endif - -#include <common.h> -#include <asm/processor.h> -#include <asm/io.h> -#include <asm/ppc4xx-gpio.h> - -extern void board_pll_init_f(void); - -#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) -static void cram_bcr_write(u32 wr_val) -{ - wr_val <<= 2; - - /* set CRAM_CRE to 1 */ - gpio_write_bit(CONFIG_SYS_GPIO_CRAM_CRE, 1); - - /* Write BCR to CRAM on CS1 */ - out32(wr_val + 0x00200000, 0); - debug("CRAM VAL: %08x for CS1 ", wr_val + 0x00200000); - - /* Write BCR to CRAM on CS2 */ - out32(wr_val + 0x02200000, 0); - debug("CRAM VAL: %08x for CS2\n", wr_val + 0x02200000); - - sync(); - eieio(); - - /* set CRAM_CRE back to 0 (normal operation) */ - gpio_write_bit(CONFIG_SYS_GPIO_CRAM_CRE, 0); - - return; -} -#endif - -phys_size_t initdram(int board_type) -{ -#if defined(CONFIG_NAND_SPL) - u32 reg; - - /* don't reinit PLL when booting via I2C bootstrap option */ - mfsdr(SDR0_PINSTP, reg); - if (reg != 0xf0000000) - board_pll_init_f(); -#endif - -#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) - int i; - u32 val; - - /* 1. EBC need to program READY, CLK, ADV for ASync mode */ - gpio_config(CONFIG_SYS_GPIO_CRAM_CLK, GPIO_OUT, GPIO_SEL, GPIO_OUT_0); - gpio_config(CONFIG_SYS_GPIO_CRAM_ADV, GPIO_OUT, GPIO_SEL, GPIO_OUT_0); - gpio_config(CONFIG_SYS_GPIO_CRAM_CRE, GPIO_OUT, GPIO_SEL, GPIO_OUT_0); - gpio_config(CONFIG_SYS_GPIO_CRAM_WAIT, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG); - - /* 2. EBC in Async mode */ - mtebc(PB1AP, 0x078F1EC0); - mtebc(PB2AP, 0x078F1EC0); - mtebc(PB1CR, 0x000BC000); - mtebc(PB2CR, 0x020BC000); - - /* 3. Set CRAM in Sync mode */ - cram_bcr_write(0x7012); /* CRAM burst setting */ - - /* 4. EBC in Sync mode */ - mtebc(PB1AP, 0x9C0201C0); - mtebc(PB2AP, 0x9C0201C0); - - /* Set GPIO pins back to alternate function */ - gpio_config(CONFIG_SYS_GPIO_CRAM_CLK, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG); - gpio_config(CONFIG_SYS_GPIO_CRAM_ADV, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG); - - /* Config EBC to use RDY */ - mfsdr(SDR0_ULTRA0, val); - mtsdr(SDR0_ULTRA0, val | SDR_ULTRA0_EBCRDYEN); - - /* Wait a short while, since for NAND booting this is too fast */ - for (i=0; i<200000; i++) - ; -#endif - - return (CONFIG_SYS_MBYTES_RAM << 20); -} diff --git a/board/amcc/acadia/pll.c b/board/amcc/acadia/pll.c deleted file mode 100644 index 6327d6c..0000000 --- a/board/amcc/acadia/pll.c +++ /dev/null @@ -1,195 +0,0 @@ -/* - * (C) Copyright 2007 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <asm/processor.h> -#include <asm/ppc405.h> - -/* test-only: move into cpu directory!!! */ - -#if defined(PLLMR0_200_133_66) -void board_pll_init_f(void) -{ - /* - * set PLL clocks based on input sysclk is 33M - * - * ---------------------------------- - * | CLK | FREQ (MHz) | DIV RATIO | - * ---------------------------------- - * | CPU | 200.0 | 4 (0x02)| - * | PLB | 133.3 | 6 (0x06)| - * | OPB | 66.6 | 12 (0x0C)| - * | EBC | 66.6 | 12 (0x0C)| - * | SPI | 66.6 | 12 (0x0C)| - * | UART0 | 10.0 | 40 (0x28)| - * | UART1 | 10.0 | 40 (0x28)| - * | DAC | 2.0 | 200 (0xC8)| - * | ADC | 2.0 | 200 (0xC8)| - * | PWM | 100.0 | 4 (0x04)| - * | EMAC | 25.0 | 16 (0x10)| - * ----------------------------------- - */ - - /* Initialize PLL */ - mtcpr(CPR0_PLLC, 0x0000033c); - mtcpr(CPR0_PLLD, 0x0c010200); - mtcpr(CPR0_PRIMAD, 0x04060c0c); - mtcpr(CPR0_PERD0, 0x000c0000); /* SPI clk div. eq. OPB clk div. */ - mtcpr(CPR0_CLKUPD, 0x40000000); -} - -#elif defined(PLLMR0_266_160_80) - -void board_pll_init_f(void) -{ - /* - * set PLL clocks based on input sysclk is 33M - * - * ---------------------------------- - * | CLK | FREQ (MHz) | DIV RATIO | - * ---------------------------------- - * | CPU | 266.64 | 3 | - * | PLB | 159.98 | 5 (0x05)| - * | OPB | 79.99 | 10 (0x0A)| - * | EBC | 79.99 | 10 (0x0A)| - * | SPI | 79.99 | 10 (0x0A)| - * | UART0 | 28.57 | 7 (0x07)| - * | UART1 | 28.57 | 7 (0x07)| - * | DAC | 28.57 | 7 (0xA7)| - * | ADC | 4 | 50 (0x32)| - * | PWM | 28.57 | 7 (0x07)| - * | EMAC | 4 | 50 (0x32)| - * ----------------------------------- - */ - - /* Initialize PLL */ - mtcpr(CPR0_PLLC, 0x20000238); - mtcpr(CPR0_PLLD, 0x03010400); - mtcpr(CPR0_PRIMAD, 0x03050a0a); - mtcpr(CPR0_PERC0, 0x00000000); - mtcpr(CPR0_PERD0, 0x070a0707); /* SPI clk div. eq. OPB clk div. */ - mtcpr(CPR0_PERD1, 0x07323200); - mtcpr(CPR0_CLKUP, 0x40000000); -} - -#elif defined(PLLMR0_333_166_83) - -void board_pll_init_f(void) -{ - /* - * set PLL clocks based on input sysclk is 33M - * - * ---------------------------------- - * | CLK | FREQ (MHz) | DIV RATIO | - * ---------------------------------- - * | CPU | 333.33 | 2 | - * | PLB | 166.66 | 4 (0x04)| - * | OPB | 83.33 | 8 (0x08)| - * | EBC | 83.33 | 8 (0x08)| - * | SPI | 83.33 | 8 (0x08)| - * | UART0 | 16.66 | 5 (0x05)| - * | UART1 | 16.66 | 5 (0x05)| - * | DAC | ???? | 166 (0xA6)| - * | ADC | ???? | 166 (0xA6)| - * | PWM | 41.66 | 3 (0x03)| - * | EMAC | ???? | 3 (0x03)| - * ----------------------------------- - */ - - /* Initialize PLL */ - mtcpr(CPR0_PLLC, 0x0000033C); - mtcpr(CPR0_PLLD, 0x0a010000); - mtcpr(CPR0_PRIMAD, 0x02040808); - mtcpr(CPR0_PERD0, 0x02080505); /* SPI clk div. eq. OPB clk div. */ - mtcpr(CPR0_PERD1, 0xA6A60300); - mtcpr(CPR0_CLKUP, 0x40000000); -} - -#elif defined(PLLMR0_100_100_12) - -void board_pll_init_f(void) -{ - /* - * set PLL clocks based on input sysclk is 33M - * - * ---------------------- - * | CLK | FREQ (MHz) | - * ---------------------- - * | CPU | 100.00 | - * | PLB | 100.00 | - * | OPB | 12.00 | - * | EBC | 49.00 | - * ---------------------- - */ - - /* Initialize PLL */ - mtcpr(CPR0_PLLC, 0x000003BC); - mtcpr(CPR0_PLLD, 0x06060600); - mtcpr(CPR0_PRIMAD, 0x02020004); - mtcpr(CPR0_PERD0, 0x04002828); /* SPI clk div. eq. OPB clk div. */ - mtcpr(CPR0_PERD1, 0xC8C81600); - mtcpr(CPR0_CLKUP, 0x40000000); -} -#endif /* CPU_<speed>_405EZ */ - -#if defined(CONFIG_NAND_SPL) || defined(CONFIG_SPI_SPL) -/* - * Get timebase clock frequency - */ -unsigned long get_tbclk(void) -{ - unsigned long cpr_plld; - unsigned long cpr_primad; - unsigned long primad_cpudv; - unsigned long pllFbkDiv; - unsigned long freqProcessor; - - /* - * Read PLL Mode registers - */ - mfcpr(CPR0_PLLD, cpr_plld); - - /* - * Read CPR_PRIMAD register - */ - mfcpr(CPR0_PRIMAD, cpr_primad); - - /* - * Determine CPU clock frequency - */ - primad_cpudv = ((cpr_primad & PRIMAD_CPUDV_MASK) >> 24); - if (primad_cpudv == 0) - primad_cpudv = 16; - - /* - * Determine FBK_DIV. - */ - pllFbkDiv = ((cpr_plld & PLLD_FBDV_MASK) >> 24); - if (pllFbkDiv == 0) - pllFbkDiv = 256; - - freqProcessor = (CONFIG_SYS_CLK_FREQ * pllFbkDiv) / primad_cpudv; - - return (freqProcessor); -} -#endif /* defined(CONFIG_NAND_SPL) || defined(CONFIG_SPI_SPL) */ diff --git a/board/amcc/acadia/u-boot-nand.lds b/board/amcc/acadia/u-boot-nand.lds deleted file mode 100644 index c2a04c7..0000000 --- a/board/amcc/acadia/u-boot-nand.lds +++ /dev/null @@ -1,103 +0,0 @@ -/* - * (C) Copyright 2007 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - arch/powerpc/cpu/ppc4xx/start.o (.text*) - - /* Align to next NAND block */ - . = ALIGN(0x4000); - common/env_embedded.o (.ppcenv) - /* Keep some space here for redundant env and potential bad env blocks */ - . = ALIGN(0x10000); - - *(.text*) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - KEEP(*(.got)) - _GOT2_TABLE_ = .; - KEEP(*(.got2)) - _FIXUP_TABLE_ = .; - KEEP(*(.fixup)) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data*) - *(.sdata*) - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.bss*) - *(.sbss*) - *(COMMON) - . = ALIGN(4); - } - - _end = . ; - PROVIDE (end = .); -} |