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-rw-r--r--board/mpc8260ads/mpc8260ads.c4
-rw-r--r--board/mpl/common/common_util.c4
-rw-r--r--board/mpl/vcma9/config.mk4
-rw-r--r--board/mpl/vcma9/memsetup.S12
-rw-r--r--board/mpl/vcma9/vcma9.c95
-rw-r--r--board/mpl/vcma9/vcma9.h88
-rw-r--r--board/smdk2400/smdk2400.c30
-rw-r--r--board/smdk2410/config.mk4
-rw-r--r--board/smdk2410/smdk2410.c38
-rw-r--r--board/trab/trab.c84
-rw-r--r--board/trab/vfd.c93
11 files changed, 314 insertions, 142 deletions
diff --git a/board/mpc8260ads/mpc8260ads.c b/board/mpc8260ads/mpc8260ads.c
index 2200a24..d0ee921 100644
--- a/board/mpc8260ads/mpc8260ads.c
+++ b/board/mpc8260ads/mpc8260ads.c
@@ -9,6 +9,10 @@
* (C) Copyright 2001, Stuart Hughes, Lineo Inc, stuarth@lineo.com
* Added support for the 16M dram simm on the 8260ads boards
*
+ * (C) Copyright 2003 Arabella Software Ltd.
+ * Yuli Barcohen <yuli@arabellasw.com>
+ * Added support for SDRAM DIMMs SPD EEPROM, MII, Ethernet PHY init.
+ *
* See file CREDITS for list of people who contributed to this
* project.
*
diff --git a/board/mpl/common/common_util.c b/board/mpl/common/common_util.c
index aa2ba6f..503654e 100644
--- a/board/mpl/common/common_util.c
+++ b/board/mpl/common/common_util.c
@@ -45,7 +45,11 @@ extern int gunzip (void *, int, unsigned char *, int *);
extern int mem_test(unsigned long start, unsigned long ramsize, int quiet);
#define I2C_BACKUP_ADDR 0x7C00 /* 0x200 bytes for backup */
+#if defined(CONFIG_PIP405) || defined(CONFIG_MIP405)
#define IMAGE_SIZE 0x80000
+#elif defined(CONFIG_VCMA9)
+#define IMAGE_SIZE 0x40000 /* ugly, but it works for now */
+#endif
extern flash_info_t flash_info[]; /* info for FLASH chips */
diff --git a/board/mpl/vcma9/config.mk b/board/mpl/vcma9/config.mk
index 19ef187..95d69cc 100644
--- a/board/mpl/vcma9/config.mk
+++ b/board/mpl/vcma9/config.mk
@@ -15,10 +15,10 @@
# Linux-Kernel is expected to be at 3000'8000, entry 3000'8000
# optionally with a ramdisk at 3080'0000
#
-# we load ourself to 33F0'0000
+# we load ourself to 33F8'0000
#
# download area is 3300'0000
#
-TEXT_BASE = 0x33F00000
+TEXT_BASE = 0x33F80000
diff --git a/board/mpl/vcma9/memsetup.S b/board/mpl/vcma9/memsetup.S
index 80721cd..557e554 100644
--- a/board/mpl/vcma9/memsetup.S
+++ b/board/mpl/vcma9/memsetup.S
@@ -54,8 +54,10 @@
/* BANK0CON */
#define B0_Tacs 0x0 /* 0clk */
-#define B0_Tcos 0x0 /* 0clk */
-#define B0_Tacc 0x5 /* 8clk */
+#define B0_Tcos 0x1 /* 1clk */
+/*#define B0_Tcos 0x0 0clk */
+#define B0_Tacc 0x7 /* 14clk */
+/*#define B0_Tacc 0x5 8clk */
#define B0_Tcoh 0x0 /* 0clk */
#define B0_Tah 0x0 /* 0clk */
#define B0_Tacp 0x0 /* page mode is not used */
@@ -63,8 +65,10 @@
/* BANK1CON */
#define B1_Tacs 0x0 /* 0clk */
-#define B1_Tcos 0x0 /* 0clk */
-#define B1_Tacc 0x5 /* 8clk */
+#define B1_Tcos 0x1 /* 1clk */
+/*#define B1_Tcos 0x0 0clk */
+#define B1_Tacc 0x7 /* 14clk */
+/*#define B1_Tacc 0x5 8clk */
#define B1_Tcoh 0x0 /* 0clk */
#define B1_Tah 0x0 /* 0clk */
#define B1_Tacp 0x0 /* page mode is not used */
diff --git a/board/mpl/vcma9/vcma9.c b/board/mpl/vcma9/vcma9.c
index 4743e6b..b051bfe 100644
--- a/board/mpl/vcma9/vcma9.c
+++ b/board/mpl/vcma9/vcma9.c
@@ -72,41 +72,46 @@ static inline void delay(unsigned long loops)
int board_init(void)
{
DECLARE_GLOBAL_DATA_PTR;
+ S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
+ S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
/* to reduce PLL lock time, adjust the LOCKTIME register */
- rLOCKTIME = 0xFFFFFF;
+ clk_power->LOCKTIME = 0xFFFFFF;
/* configure MPLL */
- rMPLLCON = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV);
+ clk_power->MPLLCON = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV);
/* some delay between MPLL and UPLL */
delay (4000);
/* configure UPLL */
- rUPLLCON = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV);
+ clk_power->UPLLCON = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV);
/* some delay between MPLL and UPLL */
delay (8000);
/* set up the I/O ports */
- rGPACON = 0x007FFFFF;
- rGPBCON = 0x002AAAAA;
- rGPBUP = 0x000002BF;
- rGPCCON = 0xAAAAAAAA;
- rGPCUP = 0x0000FFFF;
- rGPDCON = 0xAAAAAAAA;
- rGPDUP = 0x0000FFFF;
- rGPECON = 0xAAAAAAAA;
- rGPEUP = 0x000037F7;
- rGPFCON = 0x00000000;
- rGPFUP = 0x00000000;
- rGPGCON = 0xFFEAFF5A;
- rGPGUP = 0x0000F0DC;
- rGPHCON = 0x0028AAAA;
- rGPHUP = 0x00000656;
+ gpio->GPACON = 0x007FFFFF;
+ gpio->GPBCON = 0x002AAAAA;
+ gpio->GPBUP = 0x000002BF;
+ gpio->GPCCON = 0xAAAAAAAA;
+ gpio->GPCUP = 0x0000FFFF;
+ gpio->GPDCON = 0xAAAAAAAA;
+ gpio->GPDUP = 0x0000FFFF;
+ gpio->GPECON = 0xAAAAAAAA;
+ gpio->GPEUP = 0x000037F7;
+ gpio->GPFCON = 0x00000000;
+ gpio->GPFUP = 0x00000000;
+ gpio->GPGCON = 0xFFEAFF5A;
+ gpio->GPGUP = 0x0000F0DC;
+ gpio->GPHCON = 0x0028AAAA;
+ gpio->GPHUP = 0x00000656;
/* setup correct IRQ modes for NIC */
- rEXTINT2 = (rEXTINT2 & ~(7<<8)) | (4<<8); /* rising edge mode */
+ gpio->EXTINT2 = (gpio->EXTINT2 & ~(7<<8)) | (4<<8); /* rising edge mode */
+
+ /* select USB port 2 to be host or device (fix to host for now) */
+ gpio->MISCCR |= 0x08;
/* init serial */
gd->baudrate = CONFIG_BAUDRATE;
@@ -136,6 +141,50 @@ int dram_init(void)
}
/*
+ * NAND flash initialization.
+ */
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+extern void
+nand_probe(ulong physadr);
+
+
+static inline void NF_Reset(void)
+{
+ int i;
+
+ NF_SetCE(NFCE_LOW);
+ NF_Cmd(0xFF); /* reset command */
+ for(i = 0; i < 10; i++); /* tWB = 100ns. */
+ NF_WaitRB(); /* wait 200~500us; */
+ NF_SetCE(NFCE_HIGH);
+}
+
+
+static inline void NF_Init(void)
+{
+#define TACLS 0
+#define TWRPH0 3
+#define TWRPH1 0
+ NF_Conf((1<<15)|(0<<14)|(0<<13)|(1<<12)|(1<<11)|(TACLS<<8)|(TWRPH0<<4)|(TWRPH1<<0));
+ //nand->NFCONF = (1<<15)|(1<<14)|(1<<13)|(1<<12)|(1<<11)|(TACLS<<8)|(TWRPH0<<4)|(TWRPH1<<0);
+ // 1 1 1 1, 1 xxx, r xxx, r xxx
+ // En 512B 4step ECCR nFCE=H tACLS tWRPH0 tWRPH1
+
+ NF_Reset();
+}
+
+void
+nand_init(void)
+{
+ S3C2410_NAND * const nand = S3C2410_GetBase_NAND();
+
+ NF_Init();
+ printf("NAND flash probing at 0x%.8lX\n", (ulong)nand);
+ nand_probe((ulong)nand);
+}
+#endif
+
+/*
* Get some Board/PLD Info
*/
@@ -195,12 +244,12 @@ int checkboard(void)
puts ("### No HW ID - assuming VCMA9");
} else {
b->serial_name[5] = 0;
- printf ("%s-%d Rev %c SN: %s", b->serial_name, Get_Board_Config(),
+ printf ("%s-%d PCB Rev %c SN: %s", b->serial_name, Get_Board_Config(),
Get_Board_PCB(), &b->serial_name[6]);
}
} else {
s[5] = 0;
- printf ("%s-%d Rev %c SN: %s", s, Get_Board_Config(), Get_Board_PCB(),
+ printf ("%s-%d PCB Rev %c SN: %s", s, Get_Board_Config(), Get_Board_PCB(),
&s[6]);
}
printf("\n");
@@ -211,7 +260,7 @@ int checkboard(void)
void print_vcma9_rev(void)
{
- printf("Board: VCMA9-%d Rev: %c (PLD Ver: %d, Rev: %d)\n",
+ printf("Board: VCMA9-%d PCB Rev: %c (PLD Ver: %d, Rev: %d)\n",
Get_Board_Config(), Get_Board_PCB(),
Get_PLD_Version(), Get_PLD_Revision());
}
@@ -245,5 +294,3 @@ void print_vcma9_info(void)
{
print_vcma9_rev();
}
-
-
diff --git a/board/mpl/vcma9/vcma9.h b/board/mpl/vcma9/vcma9.h
index bc0e3a4..4299d4e 100644
--- a/board/mpl/vcma9/vcma9.h
+++ b/board/mpl/vcma9/vcma9.h
@@ -25,11 +25,97 @@
* Global routines used for VCMA9
*****************************************************************************/
+#include <s3c2410.h>
extern int mem_test(unsigned long start, unsigned long ramsize,int mode);
void print_vcma9_info(void);
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+typedef enum {
+ NFCE_LOW,
+ NFCE_HIGH
+} NFCE_STATE;
+
+static inline void NF_Conf(u16 conf)
+{
+ S3C2410_NAND * const nand = S3C2410_GetBase_NAND();
+
+ nand->NFCONF = conf;
+}
+
+static inline void NF_Cmd(u8 cmd)
+{
+ S3C2410_NAND * const nand = S3C2410_GetBase_NAND();
+
+ nand->NFCMD = cmd;
+}
+
+static inline void NF_CmdW(u8 cmd)
+{
+ NF_Cmd(cmd);
+ udelay(1);
+}
+
+static inline void NF_Addr(u8 addr)
+{
+ S3C2410_NAND * const nand = S3C2410_GetBase_NAND();
+
+ nand->NFADDR = addr;
+}
+
+static inline void NF_SetCE(NFCE_STATE s)
+{
+ S3C2410_NAND * const nand = S3C2410_GetBase_NAND();
+
+ switch (s) {
+ case NFCE_LOW:
+ nand->NFCONF &= ~(1<<11);
+ break;
+
+ case NFCE_HIGH:
+ nand->NFCONF |= (1<<11);
+ break;
+ }
+}
+
+static inline void NF_WaitRB(void)
+{
+ S3C2410_NAND * const nand = S3C2410_GetBase_NAND();
+
+ while (!(nand->NFSTAT & (1<<0)));
+}
+
+static inline void NF_Write(u8 data)
+{
+ S3C2410_NAND * const nand = S3C2410_GetBase_NAND();
+
+ nand->NFDATA = data;
+}
+
+static inline u8 NF_Read(void)
+{
+ S3C2410_NAND * const nand = S3C2410_GetBase_NAND();
+
+ return(nand->NFDATA);
+}
+
+static inline void NF_Init_ECC(void)
+{
+ S3C2410_NAND * const nand = S3C2410_GetBase_NAND();
+
+ nand->NFCONF |= (1<<12);
+}
+
+static inline u32 NF_Read_ECC(void)
+{
+ S3C2410_NAND * const nand = S3C2410_GetBase_NAND();
+
+ return(nand->NFECC);
+}
+
+#endif
+
#define PLD_BASE_ADDRESS 0x2C000100
#define PLD_ID_REG (PLD_BASE_ADDRESS + 0)
@@ -39,5 +125,3 @@ void print_vcma9_info(void);
#define PLD_GPCD_REG (PLD_BASE_ADDRESS + 4)
#define PLD_BOARD_REG (PLD_BASE_ADDRESS + 5)
-
-
diff --git a/board/smdk2400/smdk2400.c b/board/smdk2400/smdk2400.c
index 2b61b2d..2d6be31 100644
--- a/board/smdk2400/smdk2400.c
+++ b/board/smdk2400/smdk2400.c
@@ -46,33 +46,35 @@ extern int do_mdm_init; /* defined in common/main.c */
int board_init (void)
{
DECLARE_GLOBAL_DATA_PTR;
+ S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
+ S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
/* memory and cpu-speed are setup before relocation */
/* change the clock to be 50 MHz 1:1:1 */
- rMPLLCON = 0x5c042;
- rCLKDIVN = 0;
+ clk_power->MPLLCON = 0x5c042;
+ clk_power->CLKDIVN = 0;
/* set up the I/O ports */
- rPACON = 0x3ffff;
- rPBCON = 0xaaaaaaaa;
- rPBUP = 0xffff;
- rPECON = 0x0;
- rPEUP = 0x0;
+ gpio->PACON = 0x3ffff;
+ gpio->PBCON = 0xaaaaaaaa;
+ gpio->PBUP = 0xffff;
+ gpio->PECON = 0x0;
+ gpio->PEUP = 0x0;
#ifdef CONFIG_HWFLOW
/*CTS[0] RTS[0] INPUT INPUT TXD[0] INPUT RXD[0] */
/* 10, 10, 00, 00, 10, 00, 10 */
- rPFCON=0xa22;
+ gpio->PFCON=0xa22;
/* Disable pull-up on Rx, Tx, CTS and RTS pins */
- rPFUP=0x35;
+ gpio->PFUP=0x35;
#else
/*INPUT INPUT INPUT INPUT TXD[0] INPUT RXD[0] */
/* 00, 00, 00, 00, 10, 00, 10 */
- rPFCON = 0x22;
+ gpio->PFCON = 0x22;
/* Disable pull-up on Rx and Tx pins */
- rPFUP = 0x5;
+ gpio->PFUP = 0x5;
#endif /* CONFIG_HWFLOW */
- rPGCON = 0x0;
- rPGUP = 0x0;
- rOPENCR = 0x0;
+ gpio->PGCON = 0x0;
+ gpio->PGUP = 0x0;
+ gpio->OPENCR = 0x0;
/* arch number of SAMSUNG-Board to MACH_TYPE_SMDK2400 */
gd->bd->bi_arch_number = 145;
diff --git a/board/smdk2410/config.mk b/board/smdk2410/config.mk
index b06b493..1af85da 100644
--- a/board/smdk2410/config.mk
+++ b/board/smdk2410/config.mk
@@ -16,10 +16,10 @@
# Linux-Kernel is expected to be at 3000'8000, entry 3000'8000
# optionally with a ramdisk at 3080'0000
#
-# we load ourself to 33F0'0000
+# we load ourself to 33F8'0000
#
# download area is 3300'0000
#
-TEXT_BASE = 0x33F00000
+TEXT_BASE = 0x33F80000
diff --git a/board/smdk2410/smdk2410.c b/board/smdk2410/smdk2410.c
index 7f983ef..207cd44 100644
--- a/board/smdk2410/smdk2410.c
+++ b/board/smdk2410/smdk2410.c
@@ -68,38 +68,40 @@ static inline void delay (unsigned long loops)
int board_init (void)
{
DECLARE_GLOBAL_DATA_PTR;
+ S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
+ S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
/* to reduce PLL lock time, adjust the LOCKTIME register */
- rLOCKTIME = 0xFFFFFF;
+ clk_power->LOCKTIME = 0xFFFFFF;
/* configure MPLL */
- rMPLLCON = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV);
+ clk_power->MPLLCON = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV);
/* some delay between MPLL and UPLL */
delay (4000);
/* configure UPLL */
- rUPLLCON = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV);
+ clk_power->UPLLCON = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV);
/* some delay between MPLL and UPLL */
delay (8000);
/* set up the I/O ports */
- rGPACON = 0x007FFFFF;
- rGPBCON = 0x00044555;
- rGPBUP = 0x000007FF;
- rGPCCON = 0xAAAAAAAA;
- rGPCUP = 0x0000FFFF;
- rGPDCON = 0xAAAAAAAA;
- rGPDUP = 0x0000FFFF;
- rGPECON = 0xAAAAAAAA;
- rGPEUP = 0x0000FFFF;
- rGPFCON = 0x000055AA;
- rGPFUP = 0x000000FF;
- rGPGCON = 0xFF95FFBA;
- rGPGUP = 0x0000FFFF;
- rGPHCON = 0x002AFAAA;
- rGPHUP = 0x000007FF;
+ gpio->GPACON = 0x007FFFFF;
+ gpio->GPBCON = 0x00044555;
+ gpio->GPBUP = 0x000007FF;
+ gpio->GPCCON = 0xAAAAAAAA;
+ gpio->GPCUP = 0x0000FFFF;
+ gpio->GPDCON = 0xAAAAAAAA;
+ gpio->GPDUP = 0x0000FFFF;
+ gpio->GPECON = 0xAAAAAAAA;
+ gpio->GPEUP = 0x0000FFFF;
+ gpio->GPFCON = 0x000055AA;
+ gpio->GPFUP = 0x000000FF;
+ gpio->GPGCON = 0xFF95FFBA;
+ gpio->GPGUP = 0x0000FFFF;
+ gpio->GPHCON = 0x002AFAAA;
+ gpio->GPHUP = 0x000007FF;
/* arch number of SMDK2410-Board */
gd->bd->bi_arch_number = 193;
diff --git a/board/trab/trab.c b/board/trab/trab.c
index 6c9971f..dd4105d 100644
--- a/board/trab/trab.c
+++ b/board/trab/trab.c
@@ -71,37 +71,39 @@ int board_init ()
extern int vfd_init_clocks(void);
#endif
DECLARE_GLOBAL_DATA_PTR;
+ S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
+ S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
/* memory and cpu-speed are setup before relocation */
#ifdef CONFIG_TRAB_50MHZ
/* change the clock to be 50 MHz 1:1:1 */
/* MDIV:0x5c PDIV:4 SDIV:2 */
- rMPLLCON = 0x5c042;
- rCLKDIVN = 0;
+ clk_power->MPLLCON = 0x5c042;
+ clk_power->CLKDIVN = 0;
#else
/* change the clock to be 133 MHz 1:2:4 */
/* MDIV:0x7d PDIV:4 SDIV:1 */
- rMPLLCON = 0x7d041;
- rCLKDIVN = 3;
+ clk_power->MPLLCON = 0x7d041;
+ clk_power->CLKDIVN = 3;
#endif
/* set up the I/O ports */
- rPACON = 0x3ffff;
- rPBCON = 0xaaaaaaaa;
- rPBUP = 0xffff;
+ gpio->PACON = 0x3ffff;
+ gpio->PBCON = 0xaaaaaaaa;
+ gpio->PBUP = 0xffff;
/* INPUT nCTS0 nRTS0 TXD[1] TXD[0] RXD[1] RXD[0] */
/* 00, 10, 10, 10, 10, 10, 10 */
- rPFCON = (2<<0) | (2<<2) | (2<<4) | (2<<6) | (2<<8) | (2<<10);
+ gpio->PFCON = (2<<0) | (2<<2) | (2<<4) | (2<<6) | (2<<8) | (2<<10);
#ifdef CONFIG_HWFLOW
/* do not pull up RXD0, RXD1, TXD0, TXD1, CTS0, RTS0 */
- rPFUP = (1<<0) | (1<<1) | (1<<2) | (1<<3) | (1<<4) | (1<<5);
+ gpio->PFUP = (1<<0) | (1<<1) | (1<<2) | (1<<3) | (1<<4) | (1<<5);
#else
/* do not pull up RXD0, RXD1, TXD0, TXD1 */
- rPFUP = (1<<0) | (1<<1) | (1<<2) | (1<<3);
+ gpio->PFUP = (1<<0) | (1<<1) | (1<<2) | (1<<3);
#endif
- rPGCON = 0x0;
- rPGUP = 0x0;
- rOPENCR= 0x0;
+ gpio->PGCON = 0x0;
+ gpio->PGUP = 0x0;
+ gpio->OPENCR= 0x0;
/* arch number of SAMSUNG-Board */
/* MACH_TYPE_SMDK2400 */
@@ -112,8 +114,8 @@ int board_init ()
gd->bd->bi_boot_params = 0x0c000100;
/* Make sure both buzzers are turned off */
- rPDCON |= 0x5400;
- rPDDAT &= ~0xE0;
+ gpio->PDCON |= 0x5400;
+ gpio->PDDAT &= ~0xE0;
#ifdef CONFIG_VFD
vfd_init_clocks();
@@ -305,57 +307,73 @@ static int key_pressed(void)
#ifdef CFG_BRIGHTNESS
-#define SET_CS_TOUCH (rPDDAT &= 0x5FF)
-#define CLR_CS_TOUCH (rPDDAT |= 0x200)
+static inline void SET_CS_TOUCH(void)
+{
+ S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
+
+ gpio->PDDAT &= 0x5FF;
+}
+
+static inline void CLR_CS_TOUCH(void)
+{
+ S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
+
+ gpio->PDDAT |= 0x200;
+}
static void spi_init(void)
{
+ S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
+ S3C24X0_SPI * const spi = S3C24X0_GetBase_SPI();
int i;
/* Configure I/O ports. */
- rPDCON = (rPDCON & 0xF3FFFF) | 0x040000;
- rPGCON = (rPGCON & 0x0F3FFF) | 0x008000;
- rPGCON = (rPGCON & 0x0CFFFF) | 0x020000;
- rPGCON = (rPGCON & 0x03FFFF) | 0x080000;
+ gpio->PDCON = (gpio->PDCON & 0xF3FFFF) | 0x040000;
+ gpio->PGCON = (gpio->PGCON & 0x0F3FFF) | 0x008000;
+ gpio->PGCON = (gpio->PGCON & 0x0CFFFF) | 0x020000;
+ gpio->PGCON = (gpio->PGCON & 0x03FFFF) | 0x080000;
- CLR_CS_TOUCH;
+ CLR_CS_TOUCH();
- rSPPRE = 0x1F; /* Baudrate ca. 514kHz */
- rSPPIN = 0x01; /* SPI-MOSI holds Level after last bit */
- rSPCON = 0x1A; /* Polling, Prescaler, Master, CPOL=0, CPHA=1 */
+ spi->ch[0].SPPRE = 0x1F; /* Baudrate ca. 514kHz */
+ spi->ch[0].SPPIN = 0x01; /* SPI-MOSI holds Level after last bit */
+ spi->ch[0].SPCON = 0x1A; /* Polling, Prescaler, Master, CPOL=0, CPHA=1 */
/* Dummy byte ensures clock to be low. */
for (i = 0; i < 10; i++) {
- rSPTDAT = 0xFF;
+ spi->ch[0].SPTDAT = 0xFF;
}
wait_transmit_done();
}
static void wait_transmit_done(void)
{
- while (!(rSPSTA & 0x01)); /* wait until transfer is done */
+ S3C24X0_SPI * const spi = S3C24X0_GetBase_SPI();
+
+ while (!(spi->ch[0].SPSTA & 0x01)); /* wait until transfer is done */
}
static void tsc2000_write(unsigned int page, unsigned int reg,
unsigned int data)
{
+ S3C24X0_SPI * const spi = S3C24X0_GetBase_SPI();
unsigned int command;
- SET_CS_TOUCH;
+ SET_CS_TOUCH();
command = 0x0000;
command |= (page << 11);
command |= (reg << 5);
- rSPTDAT = (command & 0xFF00) >> 8;
+ spi->ch[0].SPTDAT = (command & 0xFF00) >> 8;
wait_transmit_done();
- rSPTDAT = (command & 0x00FF);
+ spi->ch[0].SPTDAT = (command & 0x00FF);
wait_transmit_done();
- rSPTDAT = (data & 0xFF00) >> 8;
+ spi->ch[0].SPTDAT = (data & 0xFF00) >> 8;
wait_transmit_done();
- rSPTDAT = (data & 0x00FF);
+ spi->ch[0].SPTDAT = (data & 0x00FF);
wait_transmit_done();
- CLR_CS_TOUCH;
+ CLR_CS_TOUCH();
}
static void tsc2000_set_brightness(void)
diff --git a/board/trab/vfd.c b/board/trab/vfd.c
index e00294f..1abc2ad 100644
--- a/board/trab/vfd.c
+++ b/board/trab/vfd.c
@@ -359,14 +359,17 @@ void transfer_pic(int display, unsigned char *adr, int height, int width)
*/
int vfd_init_clocks (void)
{
+ S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
+ S3C24X0_TIMERS * const timers = S3C24X0_GetBase_TIMERS();
+ S3C24X0_LCD * const lcd = S3C24X0_GetBase_LCD();
/* try to determine display type from the value
* defined by pull-ups
*/
- rPCUP = (rPCUP & 0xFFF0); /* activate GPC0...GPC3 pullups */
- rPCCON = (rPCCON & 0xFFFFFF00); /* configure GPC0...GPC3 as inputs */
+ gpio->PCUP = (gpio->PCUP & 0xFFF0); /* activate GPC0...GPC3 pullups */
+ gpio->PCCON = (gpio->PCCON & 0xFFFFFF00); /* configure GPC0...GPC3 as inputs */
udelay (10); /* allow signals to settle */
- vfd_board_id = (~rPCDAT) & 0x000F; /* read GPC0...GPC3 port pins */
+ vfd_board_id = (~gpio->PCDAT) & 0x000F; /* read GPC0...GPC3 port pins */
VFD_DISABLE; /* activate blank for the vfd */
@@ -377,39 +380,39 @@ int vfd_init_clocks (void)
/* If new board revision, then use PWM 3 as cpld-clock */
/* Enable 500 Hz timer for fill level sensor to operate properly */
/* Configure TOUT3 as functional pin, disable pull-up */
- rPDCON &= ~0x30000;
- rPDCON |= 0x20000;
- rPDUP |= (1 << 8);
+ gpio->PDCON &= ~0x30000;
+ gpio->PDCON |= 0x20000;
+ gpio->PDUP |= (1 << 8);
/* Configure the prescaler */
- rTCFG0 &= ~0xff00;
- rTCFG0 |= 0x0f00;
+ timers->TCFG0 &= ~0xff00;
+ timers->TCFG0 |= 0x0f00;
/* Select MUX input (divider) for timer3 (1/16) */
- rTCFG1 &= ~0xf000;
- rTCFG1 |= 0x3000;
+ timers->TCFG1 &= ~0xf000;
+ timers->TCFG1 |= 0x3000;
/* Enable autoreload and set the counter and compare
* registers to values for the 500 Hz clock
* (for a given prescaler (15) and divider (16)):
* counter = (66000000 / 500) >> 9;
*/
- rTCNTB3 = 0x101;
- rTCMPB3 = 0x101 / 2;
+ timers->ch[3].TCNTB = 0x101;
+ timers->ch[3].TCMPB = 0x101 / 2;
/* Start timer */
- rTCON = (rTCON | UPDATE3 | RELOAD3) & ~INVERT3;
- rTCON = (rTCON | START3) & ~UPDATE3;
+ timers->TCON = (timers->TCON | UPDATE3 | RELOAD3) & ~INVERT3;
+ timers->TCON = (timers->TCON | START3) & ~UPDATE3;
}
#endif
/* If old board revision, then use vm-signal as cpld-clock */
- rLCDCON2 = 0x00FFC000;
- rLCDCON3 = 0x0007FF00;
- rLCDCON4 = 0x00000000;
- rLCDCON5 = 0x00000400;
- rLCDCON1 = 0x00000B75;
+ lcd->LCDCON2 = 0x00FFC000;
+ lcd->LCDCON3 = 0x0007FF00;
+ lcd->LCDCON4 = 0x00000000;
+ lcd->LCDCON5 = 0x00000400;
+ lcd->LCDCON1 = 0x00000B75;
/* VM (GPD1) is used as clock for the CPLD */
- rPDCON = (rPDCON & 0xFFFFFFF3) | 0x00000008;
+ gpio->PDCON = (gpio->PDCON & 0xFFFFFFF3) | 0x00000008;
return 0;
}
@@ -425,6 +428,8 @@ int vfd_init_clocks (void)
*/
int drv_vfd_init(void)
{
+ S3C24X0_LCD * const lcd = S3C24X0_GetBase_LCD();
+ S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
char *tmp;
ulong palette;
static int vfd_init_done = 0;
@@ -481,40 +486,40 @@ int drv_vfd_init(void)
* see manual S3C2400
*/
/* Stopp LCD-Controller */
- rLCDCON1 = 0x00000000;
+ lcd->LCDCON1 = 0x00000000;
/* frame buffer startadr */
- rLCDSADDR1 = gd->fb_base >> 1;
+ lcd->LCDSADDR1 = gd->fb_base >> 1;
/* frame buffer endadr */
- rLCDSADDR2 = (gd->fb_base + FRAME_BUF_SIZE) >> 1;
- rLCDSADDR3 = ((256/4));
-rLCDCON2 = 0x000DC000;
+ lcd->LCDSADDR2 = (gd->fb_base + FRAME_BUF_SIZE) >> 1;
+ lcd->LCDSADDR3 = ((256/4));
+ lcd->LCDCON2 = 0x000DC000;
if(gd->vfd_type == VFD_TYPE_MN11236)
- rLCDCON2 = 37 << 14; /* MN11236: 38 lines */
+ lcd->LCDCON2 = 37 << 14; /* MN11236: 38 lines */
else
- rLCDCON2 = 55 << 14; /* T119C: 56 lines */
- rLCDCON3 = 0x0051000A;
- rLCDCON4 = 0x00000001;
+ lcd->LCDCON2 = 55 << 14; /* T119C: 56 lines */
+ lcd->LCDCON3 = 0x0051000A;
+ lcd->LCDCON4 = 0x00000001;
if (gd->vfd_type && vfd_inv_data)
- rLCDCON5 = 0x000004C0;
+ lcd->LCDCON5 = 0x000004C0;
else
- rLCDCON5 = 0x00000440;
+ lcd->LCDCON5 = 0x00000440;
/* Port pins as LCD output */
- rPCCON = (rPCCON & 0xFFFFFF00)| 0x000000AA;
- rPDCON = (rPDCON & 0xFFFFFF03)| 0x000000A8;
+ gpio->PCCON = (gpio->PCCON & 0xFFFFFF00)| 0x000000AA;
+ gpio->PDCON = (gpio->PDCON & 0xFFFFFF03)| 0x000000A8;
/* Synchronize VFD enable with LCD controller to avoid flicker */
- rLCDCON1 = 0x00000B75; /* Start LCD-Controller */
- while((rLCDCON5 & 0x180000)!=0x100000); /* Wait for end of VSYNC */
- while((rLCDCON5 & 0x060000)!=0x040000); /* Wait for next HSYNC */
- while((rLCDCON5 & 0x060000)==0x040000);
- while((rLCDCON5 & 0x060000)!=0x000000);
+ lcd->LCDCON1 = 0x00000B75; /* Start LCD-Controller */
+ while((lcd->LCDCON5 & 0x180000)!=0x100000); /* Wait for end of VSYNC */
+ while((lcd->LCDCON5 & 0x060000)!=0x040000); /* Wait for next HSYNC */
+ while((lcd->LCDCON5 & 0x060000)==0x040000);
+ while((lcd->LCDCON5 & 0x060000)!=0x000000);
if(gd->vfd_type)
VFD_ENABLE;
- debug ("LCDSADDR1: %lX\n", rLCDSADDR1);
- debug ("LCDSADDR2: %lX\n", rLCDSADDR2);
- debug ("LCDSADDR3: %lX\n", rLCDSADDR3);
+ debug ("LCDSADDR1: %lX\n", lcd->LCDSADDR1);
+ debug ("LCDSADDR2: %lX\n", lcd->LCDSADDR2);
+ debug ("LCDSADDR3: %lX\n", lcd->LCDSADDR3);
return 0;
}
@@ -525,9 +530,11 @@ rLCDCON2 = 0x000DC000;
*/
void disable_vfd (void)
{
+ S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
+
VFD_DISABLE;
- rPDCON &= ~0xC;
- rPDUP &= ~0x2;
+ gpio->PDCON &= ~0xC;
+ gpio->PDUP &= ~0x2;
}
/************************************************************************/
generated by cgit v1.1 at 2024-12-27 18:54:29 +0000