diff options
Diffstat (limited to 'include')
| -rw-r--r-- | include/asm-arm/arch-arm720t/netarm_dma_module.h | 184 | ||||
| -rw-r--r-- | include/asm-arm/arch-arm720t/netarm_eni_module.h | 121 | ||||
| -rw-r--r-- | include/asm-arm/arch-arm720t/netarm_eth_module.h | 160 | ||||
| -rw-r--r-- | include/asm-arm/arch-arm720t/netarm_gen_module.h | 170 | ||||
| -rw-r--r-- | include/asm-arm/arch-arm720t/netarm_mem_module.h | 158 | ||||
| -rw-r--r-- | include/asm-arm/arch-arm720t/netarm_registers.h | 80 | ||||
| -rw-r--r-- | include/asm-arm/arch-arm720t/netarm_ser_module.h | 347 | ||||
| -rw-r--r-- | include/cmd_confdefs.h | 1 | ||||
| -rw-r--r-- | include/configs/modnet50.h | 179 | ||||
| -rw-r--r-- | include/fat.h | 4 |
10 files changed, 1404 insertions, 0 deletions
diff --git a/include/asm-arm/arch-arm720t/netarm_dma_module.h b/include/asm-arm/arch-arm720t/netarm_dma_module.h new file mode 100644 index 0000000..c517035 --- /dev/null +++ b/include/asm-arm/arch-arm720t/netarm_dma_module.h @@ -0,0 +1,184 @@ +/* + * include/asm-armnommu/arch-netarm/netarm_dma_module.h + * + * Copyright (C) 2000 NETsilicon, Inc. + * Copyright (C) 2000 WireSpeed Communications Corporation + * + * This software is copyrighted by WireSpeed. LICENSEE agrees that + * it will not delete this copyright notice, trademarks or protective + * notices from any copy made by LICENSEE. + * + * This software is provided "AS-IS" and any express or implied + * warranties or conditions, including but not limited to any + * implied warranties of merchantability and fitness for a particular + * purpose regarding this software. In no event shall WireSpeed + * be liable for any indirect, consequential, or incidental damages, + * loss of profits or revenue, loss of use or data, or interruption + * of business, whether the alleged damages are labeled in contract, + * tort, or indemnity. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * + * author(s) : Joe deBlaquiere + * David Smith + */ + +#ifndef __NETARM_DMA_MODULE_REGISTERS_H +#define __NETARM_DMA_MODULE_REGISTERS_H + +/* GEN unit register offsets */ + +#define NETARM_DMA_MODULE_BASE (0xFF900000) + +#define get_dma_reg_addr(c) ((volatile unsigned int *)(NETARM_DMA_MODULE_BASE + (c))) + +#define NETARM_DMA1A_BFR_DESCRPTOR_PTR (0x00) +#define NETARM_DMA1A_CONTROL (0x10) +#define NETARM_DMA1A_STATUS (0x14) +#define NETARM_DMA1B_BFR_DESCRPTOR_PTR (0x20) +#define NETARM_DMA1B_CONTROL (0x30) +#define NETARM_DMA1B_STATUS (0x34) +#define NETARM_DMA1C_BFR_DESCRPTOR_PTR (0x40) +#define NETARM_DMA1C_CONTROL (0x50) +#define NETARM_DMA1C_STATUS (0x54) +#define NETARM_DMA1D_BFR_DESCRPTOR_PTR (0x60) +#define NETARM_DMA1D_CONTROL (0x70) +#define NETARM_DMA1D_STATUS (0x74) + +#define NETARM_DMA2_BFR_DESCRPTOR_PTR (0x80) +#define NETARM_DMA2_CONTROL (0x90) +#define NETARM_DMA2_STATUS (0x94) + +#define NETARM_DMA3_BFR_DESCRPTOR_PTR (0xA0) +#define NETARM_DMA3_CONTROL (0xB0) +#define NETARM_DMA3_STATUS (0xB4) + +#define NETARM_DMA4_BFR_DESCRPTOR_PTR (0xC0) +#define NETARM_DMA4_CONTROL (0xD0) +#define NETARM_DMA4_STATUS (0xD4) + +#define NETARM_DMA5_BFR_DESCRPTOR_PTR (0xE0) +#define NETARM_DMA5_CONTROL (0xF0) +#define NETARM_DMA5_STATUS (0xF4) + +#define NETARM_DMA6_BFR_DESCRPTOR_PTR (0x100) +#define NETARM_DMA6_CONTROL (0x110) +#define NETARM_DMA6_STATUS (0x114) + +#define NETARM_DMA7_BFR_DESCRPTOR_PTR (0x120) +#define NETARM_DMA7_CONTROL (0x130) +#define NETARM_DMA7_STATUS (0x134) + +#define NETARM_DMA8_BFR_DESCRPTOR_PTR (0x140) +#define NETARM_DMA8_CONTROL (0x150) +#define NETARM_DMA8_STATUS (0x154) + +#define NETARM_DMA9_BFR_DESCRPTOR_PTR (0x160) +#define NETARM_DMA9_CONTROL (0x170) +#define NETARM_DMA9_STATUS (0x174) + +#define NETARM_DMA10_BFR_DESCRPTOR_PTR (0x180) +#define NETARM_DMA10_CONTROL (0x190) +#define NETARM_DMA10_STATUS (0x194) + +/* select bitfield defintions */ + +/* DMA Control Register ( 0xFF90_0XX0 ) */ + +#define NETARM_DMA_CTL_ENABLE (0x80000000) + +#define NETARM_DMA_CTL_ABORT (0x40000000) + +#define NETARM_DMA_CTL_BUS_100_PERCENT (0x00000000) +#define NETARM_DMA_CTL_BUS_75_PERCENT (0x10000000) +#define NETARM_DMA_CTL_BUS_50_PERCENT (0x20000000) +#define NETARM_DMA_CTL_BUS_25_PERCENT (0x30000000) + +#define NETARM_DMA_CTL_BUS_MASK (0x30000000) + +#define NETARM_DMA_CTL_MODE_FB_TO_MEM (0x00000000) +#define NETARM_DMA_CTL_MODE_FB_FROM_MEM (0x04000000) +#define NETARM_DMA_CTL_MODE_MEM_TO_MEM (0x08000000) + +#define NETARM_DMA_CTL_BURST_NONE (0x00000000) +#define NETARM_DMA_CTL_BURST_8_BYTE (0x01000000) +#define NETARM_DMA_CTL_BURST_16_BYTE (0x02000000) + +#define NETARM_DMA_CTL_BURST_MASK (0x03000000) + +#define NETARM_DMA_CTL_SRC_INCREMENT (0x00200000) + +#define NETARM_DMA_CTL_DST_INCREMENT (0x00100000) + +/* these apply only to ext xfers on DMA 3 or 4 */ + +#define NETARM_DMA_CTL_CH_3_4_REQ_EXT (0x00800000) + +#define NETARM_DMA_CTL_CH_3_4_DATA_32 (0x00000000) +#define NETARM_DMA_CTL_CH_3_4_DATA_16 (0x00010000) +#define NETARM_DMA_CTL_CH_3_4_DATA_8 (0x00020000) + +#define NETARM_DMA_CTL_STATE(X) ((X) & 0xFC00) +#define NETARM_DMA_CTL_INDEX(X) ((X) & 0x03FF) + +/* DMA Status Register ( 0xFF90_0XX4 ) */ + +#define NETARM_DMA_STAT_NC_INTPEN (0x80000000) +#define NETARM_DMA_STAT_EC_INTPEN (0x40000000) +#define NETARM_DMA_STAT_NR_INTPEN (0x20000000) +#define NETARM_DMA_STAT_CA_INTPEN (0x10000000) +#define NETARM_DMA_STAT_INTPEN_MASK (0xF0000000) + +#define NETARM_DMA_STAT_NC_INT_EN (0x00800000) +#define NETARM_DMA_STAT_EC_INT_EN (0x00400000) +#define NETARM_DMA_STAT_NR_INT_EN (0x00200000) +#define NETARM_DMA_STAT_CA_INT_EN (0x00100000) +#define NETARM_DMA_STAT_INT_EN_MASK (0x00F00000) + +#define NETARM_DMA_STAT_WRAP (0x00080000) +#define NETARM_DMA_STAT_IDONE (0x00040000) +#define NETARM_DMA_STAT_LAST (0x00020000) +#define NETARM_DMA_STAT_FULL (0x00010000) + +#define NETARM_DMA_STAT_BUFLEN(X) ((X) & 0x7FFF) + +/* DMA Buffer Descriptor Word 0 bitfields. */ + +#define NETARM_DMA_BD0_WRAP (0x80000000) +#define NETARM_DMA_BD0_IDONE (0x40000000) +#define NETARM_DMA_BD0_LAST (0x20000000) +#define NETARM_DMA_BD0_BUFPTR_MASK (0x1FFFFFFF) + +/* DMA Buffer Descriptor Word 1 bitfields. */ + +#define NETARM_DMA_BD1_STATUS_MASK (0xFFFF0000) +#define NETARM_DMA_BD1_FULL (0x00008000) +#define NETARM_DMA_BD1_BUFLEN_MASK (0x00007FFF) + +#ifndef __ASSEMBLER__ + +typedef struct __NETARM_DMA_Buff_Desc_FlyBy +{ + unsigned int word0; + unsigned int word1; +} NETARM_DMA_Buff_Desc_FlyBy, *pNETARM_DMA_Buff_Desc_FlyBy ; + +typedef struct __NETARM_DMA_Buff_Desc_M_to_M +{ + unsigned int word0; + unsigned int word1; + unsigned int word2; + unsigned int word3; +} NETARM_DMA_Buff_Desc_M_to_M, *pNETARM_DMA_Buff_Desc_M_to_M ; + +#endif + +#endif + diff --git a/include/asm-arm/arch-arm720t/netarm_eni_module.h b/include/asm-arm/arch-arm720t/netarm_eni_module.h new file mode 100644 index 0000000..317b354 --- /dev/null +++ b/include/asm-arm/arch-arm720t/netarm_eni_module.h @@ -0,0 +1,121 @@ +/* + * include/asm-armnommu/arch-netarm/netarm_eni_module.h + * + * Copyright (C) 2000 NETsilicon, Inc. + * Copyright (C) 2000 WireSpeed Communications Corporation + * + * This software is copyrighted by WireSpeed. LICENSEE agrees that + * it will not delete this copyright notice, trademarks or protective + * notices from any copy made by LICENSEE. + * + * This software is provided "AS-IS" and any express or implied + * warranties or conditions, including but not limited to any + * implied warranties of merchantability and fitness for a particular + * purpose regarding this software. In no event shall WireSpeed + * be liable for any indirect, consequential, or incidental damages, + * loss of profits or revenue, loss of use or data, or interruption + * of business, whether the alleged damages are labeled in contract, + * tort, or indemnity. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * + * author(s) : David Smith + */ + +#ifndef __NETARM_ENI_MODULE_REGISTERS_H +#define __NETARM_ENI_MODULE_REGISTERS_H + +/* ENI unit register offsets */ + +/* #ifdef CONFIG_ARCH_NETARM */ +#define NETARM_ENI_MODULE_BASE (0xFFA00000) +/* #endif / * CONFIG_ARCH_NETARM */ + +#define get_eni_reg_addr(c) ((volatile unsigned int *)(NETARM_ENI_MODULE_BASE + (c))) +#define get_eni_ctl_reg_addr(minor) \ + (get_eni_reg_addr(NETARM_ENI_1284_PORT1_CONTROL) + (minor)) + +#define NETARM_ENI_GENERAL_CONTROL (0x00) +#define NETARM_ENI_STATUS_CONTROL (0x04) +#define NETARM_ENI_FIFO_MODE_DATA (0x08) + +#define NETARM_ENI_1284_PORT1_CONTROL (0x10) +#define NETARM_ENI_1284_PORT2_CONTROL (0x14) +#define NETARM_ENI_1284_PORT3_CONTROL (0x18) +#define NETARM_ENI_1284_PORT4_CONTROL (0x1c) + +#define NETARM_ENI_1284_CHANNEL1_DATA (0x20) +#define NETARM_ENI_1284_CHANNEL2_DATA (0x24) +#define NETARM_ENI_1284_CHANNEL3_DATA (0x28) +#define NETARM_ENI_1284_CHANNEL4_DATA (0x2c) + +#define NETARM_ENI_ENI_CONTROL (0x30) +#define NETARM_ENI_ENI_PULSED_INTR (0x34) +#define NETARM_ENI_ENI_SHARED_RAM_ADDR (0x38) +#define NETARM_ENI_ENI_SHARED (0x3c) + +/* select bitfield defintions */ + +/* General Control Register (0xFFA0_0000) */ + +#define NETARM_ENI_GCR_ENIMODE_IEEE1284 (0x00000001) +#define NETARM_ENI_GCR_ENIMODE_SHRAM16 (0x00000004) +#define NETARM_ENI_GCR_ENIMODE_SHRAM8 (0x00000005) +#define NETARM_ENI_GCR_ENIMODE_FIFO16 (0x00000006) +#define NETARM_ENI_GCR_ENIMODE_FIFO8 (0x00000007) + +#define NETARM_ENI_GCR_ENIMODE_MASK (0x00000007) + +/* IEEE 1284 Port Control Registers 1-4 (0xFFA0_0010, 0xFFA0_0014, + 0xFFA0_0018, 0xFFA0_001c) */ + +#define NETARM_ENI_1284PC_PORT_ENABLE (0x80000000) +#define NETARM_ENI_1284PC_DMA_ENABLE (0x40000000) +#define NETARM_ENI_1284PC_OBE_INT_EN (0x20000000) +#define NETARM_ENI_1284PC_ACK_INT_EN (0x10000000) +#define NETARM_ENI_1284PC_ECP_MODE (0x08000000) +#define NETARM_ENI_1284PC_LOOPBACK_MODE (0x04000000) + +#define NETARM_ENI_1284PC_STROBE_TIME0 (0x00000000) /* 0.5 uS */ +#define NETARM_ENI_1284PC_STROBE_TIME1 (0x01000000) /* 1.0 uS */ +#define NETARM_ENI_1284PC_STROBE_TIME2 (0x02000000) /* 5.0 uS */ +#define NETARM_ENI_1284PC_STROBE_TIME3 (0x03000000) /* 10.0 uS */ +#define NETARM_ENI_1284PC_STROBE_MASK (0x03000000) + +#define NETARM_ENI_1284PC_MAN_STROBE_EN (0x00800000) +#define NETARM_ENI_1284PC_FAST_MODE (0x00400000) +#define NETARM_ENI_1284PC_BIDIR_MODE (0x00200000) + +#define NETARM_ENI_1284PC_MAN_STROBE (0x00080000) +#define NETARM_ENI_1284PC_AUTO_FEED (0x00040000) +#define NETARM_ENI_1284PC_INIT (0x00020000) +#define NETARM_ENI_1284PC_HSELECT (0x00010000) +#define NETARM_ENI_1284PC_FE_INT_EN (0x00008000) +#define NETARM_ENI_1284PC_EPP_MODE (0x00004000) +#define NETARM_ENI_1284PC_IBR_INT_EN (0x00002000) +#define NETARM_ENI_1284PC_IBR (0x00001000) + +#define NETARM_ENI_1284PC_RXFDB_1BYTE (0x00000400) +#define NETARM_ENI_1284PC_RXFDB_2BYTE (0x00000800) +#define NETARM_ENI_1284PC_RXFDB_3BYTE (0x00000c00) +#define NETARM_ENI_1284PC_RXFDB_4BYTE (0x00000000) + +#define NETARM_ENI_1284PC_RBCC (0x00000200) +#define NETARM_ENI_1284PC_RBCT (0x00000100) +#define NETARM_ENI_1284PC_ACK (0x00000080) +#define NETARM_ENI_1284PC_FIFO_E (0x00000040) +#define NETARM_ENI_1284PC_OBE (0x00000020) +#define NETARM_ENI_1284PC_ACK_INT (0x00000010) +#define NETARM_ENI_1284PC_BUSY (0x00000008) +#define NETARM_ENI_1284PC_PE (0x00000004) +#define NETARM_ENI_1284PC_PSELECT (0x00000002) +#define NETARM_ENI_1284PC_FAULT (0x00000001) + +#endif /* __NETARM_ENI_MODULE_REGISTERS_H */ diff --git a/include/asm-arm/arch-arm720t/netarm_eth_module.h b/include/asm-arm/arch-arm720t/netarm_eth_module.h new file mode 100644 index 0000000..8f2f369 --- /dev/null +++ b/include/asm-arm/arch-arm720t/netarm_eth_module.h @@ -0,0 +1,160 @@ +/* + * include/asm-armnommu/arch-netarm/netarm_eth_module.h + * + * Copyright (C) 2000 NETsilicon, Inc. + * Copyright (C) 2000 WireSpeed Communications Corporation + * + * This software is copyrighted by WireSpeed. LICENSEE agrees that + * it will not delete this copyright notice, trademarks or protective + * notices from any copy made by LICENSEE. + * + * This software is provided "AS-IS" and any express or implied + * warranties or conditions, including but not limited to any + * implied warranties of merchantability and fitness for a particular + * purpose regarding this software. In no event shall WireSpeed + * be liable for any indirect, consequential, or incidental damages, + * loss of profits or revenue, loss of use or data, or interruption + * of business, whether the alleged damages are labeled in contract, + * tort, or indemnity. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * + * author(s) : Jackie Smith Cashion + * David Smith + */ + +#ifndef __NETARM_ETH_MODULE_REGISTERS_H +#define __NETARM_ETH_MODULE_REGISTERS_H + +/* ETH unit register offsets */ + +#define NETARM_ETH_MODULE_BASE (0xFF800000) + +#define get_eth_reg_addr(c) ((volatile unsigned int *)(NETARM_ETH_MODULE_BASE + (c))) + +#define NETARM_ETH_GEN_CTRL (0x000) /* Ethernet Gen Control Reg */ +#define NETARM_ETH_GEN_STAT (0x004) /* Ethernet Gen Status Reg */ +#define NETARM_ETH_FIFO_DAT1 (0x008) /* Fifo Data Reg 1 */ +#define NETARM_ETH_FIFO_DAT2 (0x00C) /* Fifo Data Reg 2 */ +#define NETARM_ETH_TX_STAT (0x010) /* Transmit Status Reg */ +#define NETARM_ETH_RX_STAT (0x014) /* Receive Status Reg */ + +#define NETARM_ETH_MAC_CFG (0x400) /* MAC Configuration Reg */ +#define NETARM_ETH_PCS_CFG (0x408) /* PCS Configuration Reg */ +#define NETARM_ETH_STL_CFG (0x410) /* STL Configuration Reg */ +#define NETARM_ETH_B2B_IPG_GAP_TMR (0x440) /* Back-to-back IPG + Gap Timer Reg */ +#define NETARM_ETH_NB2B_IPG_GAP_TMR (0x444) /* Non Back-to-back + IPG Gap Timer Reg */ +#define NETARM_ETH_MII_CMD (0x540) /* MII (PHY) Command Reg */ +#define NETARM_ETH_MII_ADDR (0x544) /* MII Address Reg */ +#define NETARM_ETH_MII_WRITE (0x548) /* MII Write Data Reg */ +#define NETARM_ETH_MII_READ (0x54C) /* MII Read Data Reg */ +#define NETARM_ETH_MII_IND (0x550) /* MII Indicators Reg */ +#define NETARM_ETH_MIB_CRCEC (0x580) /* (MIB) CRC Error Counter */ +#define NETARM_ETH_MIB_AEC (0x584) /* Alignment Error Counter */ +#define NETARM_ETH_MIB_CEC (0x588) /* Code Error Counter */ +#define NETARM_ETH_MIB_LFC (0x58C) /* Long Frame Counter */ +#define NETARM_ETH_MIB_SFC (0x590) /* Short Frame Counter */ +#define NETARM_ETH_MIB_LCC (0x594) /* Late Collision Counter */ +#define NETARM_ETH_MIB_EDC (0x598) /* Excessive Deferral + Counter */ +#define NETARM_ETH_MIB_MCC (0x59C) /* Maximum Collision Counter */ +#define NETARM_ETH_SAL_FILTER (0x5C0) /* SAL Station Address + Filter Reg */ +#define NETARM_ETH_SAL_STATION_ADDR_1 (0x5C4) /* SAL Station Address + Reg */ +#define NETARM_ETH_SAL_STATION_ADDR_2 (0x5C8) +#define NETARM_ETH_SAL_STATION_ADDR_3 (0x5CC) +#define NETARM_ETH_SAL_HASH_TBL_1 (0x5D0) /* SAL Multicast Hash Table*/ +#define NETARM_ETH_SAL_HASH_TBL_2 (0x5D4) +#define NETARM_ETH_SAL_HASH_TBL_3 (0x5D8) +#define NETARM_ETH_SAL_HASH_TBL_4 (0x5DC) + +/* select bitfield defintions */ + +/* Ethernet General Control Register (0xFF80_0000) */ + +#define NETARM_ETH_GCR_ERX (0x80000000) /* Enable Receive FIFO */ +#define NETARM_ETH_GCR_ERXDMA (0x40000000) /* Enable Receive DMA */ +#define NETARM_ETH_GCR_ETX (0x00800000) /* Enable Transmit FIFO */ +#define NETARM_ETH_GCR_ETXDMA (0x00400000) /* Enable Transmit DMA */ +#define NETARM_ETH_GCR_ETXWM_50 (0x00100000) /* Transmit FIFO Water + Mark. Start transmit + when FIFO is 50% + full. */ +#define NETARM_ETH_GCR_PNA (0x00000400) /* pSOS pNA Buffer + Descriptor Format */ + +/* Ethernet General Status Register (0xFF80_0004) */ + +#define NETARM_ETH_GST_RXFDB (0x30000000) +#define NETARM_ETH_GST_RXREGR (0x08000000) /* Receive Register + Ready */ +#define NETARM_ETH_GST_RXFIFOH (0x04000000) +#define NETARM_ETH_GST_RXBR (0x02000000) +#define NETARM_ETH_GST_RXSKIP (0x01000000) + +#define NETARM_ETH_GST_TXBC (0x00020000) + + +/* Ethernet Transmit Status Register (0xFF80_0010) */ + +#define NETARM_ETH_TXSTAT_TXOK (0x00008000) + + +/* Ethernet Receive Status Register (0xFF80_0014) */ + +#define NETARM_ETH_RXSTAT_SIZE (0xFFFF0000) +#define NETARM_ETH_RXSTAT_RXOK (0x00002000) + + +/* PCS Configuration Register (0xFF80_0408) */ + +#define NETARM_ETH_PCSC_NOCFR (0x1) /* Disable Ciphering */ +#define NETARM_ETH_PCSC_ENJAB (0x2) /* Enable Jabber Protection */ +#define NETARM_ETH_PCSC_CLKS_25M (0x0) /* 25 MHz Clock Speed Select */ +#define NETARM_ETH_PCSC_CLKS_33M (0x4) /* 33 MHz Clock Speed Select */ + +/* STL Configuration Register (0xFF80_0410) */ + +#define NETARM_ETH_STLC_RXEN (0x2) /* Enable Packet Receiver */ +#define NETARM_ETH_STLC_AUTOZ (0x4) /* Auto Zero Statistics */ + +/* MAC Configuration Register (0xFF80_0400) */ + +#define NETARM_ETH_MACC_HUGEN (0x1) /* Enable Unlimited Transmit + Frame Sizes */ +#define NETARM_ETH_MACC_PADEN (0x4) /* Automatic Pad Fill Frames + to 64 Bytes */ +#define NETARM_ETH_MACC_CRCEN (0x8) /* Append CRC to Transmit + Frames */ + +/* MII (PHY) Command Register (0xFF80_0540) */ + +#define NETARM_ETH_MIIC_RSTAT (0x1) /* Single Scan for Read Data */ + +/* MII Indicators Register (0xFF80_0550) */ + +#define NETARM_ETH_MIII_BUSY (0x1) /* MII I/F Busy with + Read/Write */ + +/* SAL Station Address Filter Register (0xFF80_05C0) */ + +#define NETARM_ETH_SALF_PRO (0x8) /* Enable Promiscuous Mode */ +#define NETARM_ETH_SALF_PRM (0x4) /* Accept All Multicast + Packets */ +#define NETARM_ETH_SALF_PRA (0x2) /* Accept Mulitcast Packets + using Hash Table */ +#define NETARM_ETH_SALF_BROAD (0x1) /* Accept All Broadcast + Packets */ + + +#endif /* __NETARM_GEN_MODULE_REGISTERS_H */ diff --git a/include/asm-arm/arch-arm720t/netarm_gen_module.h b/include/asm-arm/arch-arm720t/netarm_gen_module.h new file mode 100644 index 0000000..6ab5cc1 --- /dev/null +++ b/include/asm-arm/arch-arm720t/netarm_gen_module.h @@ -0,0 +1,170 @@ +/* + * include/asm-armnommu/arch-netarm/netarm_gen_module.h + * + * Copyright (C) 2000, 2001 NETsilicon, Inc. + * Copyright (C) 2000, 2001 Red Hat, Inc. + * + * This software is copyrighted by Red Hat. LICENSEE agrees that + * it will not delete this copyright notice, trademarks or protective + * notices from any copy made by LICENSEE. + * + * This software is provided "AS-IS" and any express or implied + * warranties or conditions, including but not limited to any + * implied warranties of merchantability and fitness for a particular + * purpose regarding this software. In no event shall Red Hat + * be liable for any indirect, consequential, or incidental damages, + * loss of profits or revenue, loss of use or data, or interruption + * of business, whether the alleged damages are labeled in contract, + * tort, or indemnity. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * + * author(s) : Joe deBlaquiere + */ + +#ifndef __NETARM_GEN_MODULE_REGISTERS_H +#define __NETARM_GEN_MODULE_REGISTERS_H + +/* GEN unit register offsets */ + +#define NETARM_GEN_MODULE_BASE (0xFFB00000) + +#define get_gen_reg_addr(c) ((volatile unsigned int *)(NETARM_GEN_MODULE_BASE + (c))) + +#define NETARM_GEN_SYSTEM_CONTROL (0x00) +#define NETARM_GEN_STATUS_CONTROL (0x04) +#define NETARM_GEN_PLL_CONTROL (0x08) +#define NETARM_GEN_SOFTWARE_SERVICE (0x0c) + +#define NETARM_GEN_TIMER1_CONTROL (0x10) +#define NETARM_GEN_TIMER1_STATUS (0x14) +#define NETARM_GEN_TIMER2_CONTROL (0x18) +#define NETARM_GEN_TIMER2_STATUS (0x1c) + +#define NETARM_GEN_PORTA (0x20) +#define NETARM_GEN_PORTB (0x24) +#define NETARM_GEN_PORTC (0x28) + +#define NETARM_GEN_INTR_ENABLE (0x30) +#define NETARM_GEN_INTR_ENABLE_SET (0x34) +#define NETARM_GEN_INTR_ENABLE_CLR (0x38) +#define NETARM_GEN_INTR_STATUS_EN (0x34) +#define NETARM_GEN_INTR_STATUS_RAW (0x38) + +#define NETARM_GEN_CACHE_CONTROL1 (0x40) +#define NETARM_GEN_CACHE_CONTROL2 (0x44) + +/* select bitfield definitions */ + +/* System Control Register ( 0xFFB0_0000 ) */ + +#define NETARM_GEN_SYS_CFG_LENDIAN (0x80000000) +#define NETARM_GEN_SYS_CFG_BENDIAN (0x00000000) + +#define NETARM_GEN_SYS_CFG_BUSQRTR (0x00000000) +#define NETARM_GEN_SYS_CFG_BUSHALF (0x20000000) +#define NETARM_GEN_SYS_CFG_BUSFULL (0x40000000) + +#define NETARM_GEN_SYS_CFG_BCLK_DISABLE (0x10000000) + +#define NETARM_GEN_SYS_CFG_WDOG_EN (0x01000000) +#define NETARM_GEN_SYS_CFG_WDOG_IRQ (0x00000000) +#define NETARM_GEN_SYS_CFG_WDOG_FIQ (0x00400000) +#define NETARM_GEN_SYS_CFG_WDOG_RST (0x00800000) +#define NETARM_GEN_SYS_CFG_WDOG_24 (0x00000000) +#define NETARM_GEN_SYS_CFG_WDOG_26 (0x00100000) +#define NETARM_GEN_SYS_CFG_WDOG_28 (0x00200000) +#define NETARM_GEN_SYS_CFG_WDOG_29 (0x00300000) + +#define NETARM_GEN_SYS_CFG_BUSMON_EN (0x00040000) +#define NETARM_GEN_SYS_CFG_BUSMON_128 (0x00000000) +#define NETARM_GEN_SYS_CFG_BUSMON_64 (0x00010000) +#define NETARM_GEN_SYS_CFG_BUSMON_32 (0x00020000) +#define NETARM_GEN_SYS_CFG_BUSMON_16 (0x00030000) + +#define NETARM_GEN_SYS_CFG_USER_EN (0x00008000) +#define NETARM_GEN_SYS_CFG_BUSER_EN (0x00004000) + +#define NETARM_GEN_SYS_CFG_BUSARB_INT (0x00002000) +#define NETARM_GEN_SYS_CFG_BUSARB_EXT (0x00000000) + +#define NETARM_GEN_SYS_CFG_DMATST (0x00001000) + +#define NETARM_GEN_SYS_CFG_TEALAST (0x00000800) + +#define NETARM_GEN_SYS_CFG_ALIGN_ABORT (0x00000400) + +#define NETARM_GEN_SYS_CFG_CACHE_EN (0x00000200) + +#define NETARM_GEN_SYS_CFG_WRI_BUF_EN (0x00000100) + +#define NETARM_GEN_SYS_CFG_CACHE_INIT (0x00000080) + +/* PLL Control Register ( 0xFFB0_0008 ) */ + +#define NETARM_GEN_PLL_CTL_PLLCNT_MASK (0x0F000000) + +#define NETARM_GEN_PLL_CTL_PLLCNT(x) (((x)<<24) & \ + NETARM_GEN_PLL_CTL_PLLCNT_MASK) + +/* Defaults for POLTST and ICP Fields in PLL CTL */ +#define NETARM_GEN_PLL_CTL_OUTDIV(x) (x) +#define NETARM_GEN_PLL_CTL_INDIV(x) ((x)<<6) +#define NETARM_GEN_PLL_CTL_POLTST_DEF (0x00000E00) +#define NETARM_GEN_PLL_CTL_ICP_DEF (0x0000003C) + + +/* Software Service Register ( 0xFFB0_000C ) */ + +#define NETARM_GEN_SW_SVC_RESETA (0x123) +#define NETARM_GEN_SW_SVC_RESETB (0x321) + +/* PORT C Register ( 0xFFB0_0028 ) */ + +#define NETARM_GEN_PORT_MODE(x) (((x)<<24) + (0xFF00)) +#define NETARM_GEN_PORT_DIR(x) (((x)<<16) + (0xFF00)) + +/* Timer Registers ( 0xFFB0_0010 0xFFB0_0018 ) */ + +#define NETARM_GEN_TCTL_ENABLE (0x80000000) +#define NETARM_GEN_TCTL_INT_ENABLE (0x40000000) + +#define NETARM_GEN_TCTL_USE_IRQ (0x00000000) +#define NETARM_GEN_TCTL_USE_FIQ (0x20000000) + +#define NETARM_GEN_TCTL_USE_PRESCALE (0x10000000) +#define NETARM_GEN_TCTL_INIT_COUNT(x) ((x) & 0x1FF) + +#define NETARM_GEN_TSTAT_INTPEN (0x40000000) +#define NETARM_GEN_TSTAT_CTC_MASK (0x000001FF) + +/* prescale to msecs conversion */ + +#define NETARM_GEN_TIMER_MSEC_P(x) ( ( ( 20480 ) * ( 0x1FF - ( (x) & \ + NETARM_GEN_TSTAT_CTC_MASK ) + \ + 1 ) ) / (NETARM_XTAL_FREQ/1000) ) + +#define NETARM_GEN_TIMER_SET_HZ(x) ( ( ((NETARM_XTAL_FREQ/(20480*(x)))-1) & \ + NETARM_GEN_TSTAT_CTC_MASK ) | \ + NETARM_GEN_TCTL_USE_PRESCALE ) + +#if 0 +/* ifdef CONFIG_NETARM_PLL_BYPASS else */ +#error test +#define NETARM_GEN_TIMER_MSEC_P(x) ( ( ( 4096 ) * ( 0x1FF - ( (x) & \ + NETARM_GEN_TSTAT_CTC_MASK ) + \ + 1 ) ) / (NETARM_XTAL_FREQ/1000) ) + +#define NETARM_GEN_TIMER_SET_HZ(x) ( ( ((NETARM_XTAL_FREQ/(4096*(x)))-1) & \ + NETARM_GEN_TSTAT_CTC_MASK ) | \ + NETARM_GEN_TCTL_USE_PRESCALE ) +#endif + +#endif diff --git a/include/asm-arm/arch-arm720t/netarm_mem_module.h b/include/asm-arm/arch-arm720t/netarm_mem_module.h new file mode 100644 index 0000000..02ca9fb --- /dev/null +++ b/include/asm-arm/arch-arm720t/netarm_mem_module.h @@ -0,0 +1,158 @@ +/* + * include/asm-armnommu/arch-netarm/netarm_mem_module.h + * + * Copyright (C) 2000, 2001 NETsilicon, Inc. + * Copyright (C) 2000, 2001 Red Hat, Inc. + * + * This software is copyrighted by Red Hat. LICENSEE agrees that + * it will not delete this copyright notice, trademarks or protective + * notices from any copy made by LICENSEE. + * + * This software is provided "AS-IS" and any express or implied + * warranties or conditions, including but not limited to any + * implied warranties of merchantability and fitness for a particular + * purpose regarding this software. In no event shall Red Hat + * be liable for any indirect, consequential, or incidental damages, + * loss of profits or revenue, loss of use or data, or interruption + * of business, whether the alleged damages are labeled in contract, + * tort, or indemnity. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * + * author(s) : Joe deBlaquiere + */ + +#ifndef __NETARM_MEM_MODULE_REGISTERS_H +#define __NETARM_MEM_MODULE_REGISTERS_H + +/* GEN unit register offsets */ + +#define NETARM_MEM_MODULE_BASE (0xFFC00000) + +#define NETARM_MEM_MODULE_CONFIG (0x00) +#define NETARM_MEM_CS0_BASE_ADDR (0x10) +#define NETARM_MEM_CS0_OPTIONS (0x14) +#define NETARM_MEM_CS1_BASE_ADDR (0x20) +#define NETARM_MEM_CS1_OPTIONS (0x24) +#define NETARM_MEM_CS2_BASE_ADDR (0x30) +#define NETARM_MEM_CS2_OPTIONS (0x34) +#define NETARM_MEM_CS3_BASE_ADDR (0x40) +#define NETARM_MEM_CS3_OPTIONS (0x44) +#define NETARM_MEM_CS4_BASE_ADDR (0x50) +#define NETARM_MEM_CS4_OPTIONS (0x54) + +/* select bitfield defintions */ + +/* Module Configuration Register ( 0xFFC0_0000 ) */ + +#define NETARM_MEM_CFG_REFR_COUNT_MASK (0xFF000000) +#define NETARM_MEM_CFG_REFRESH_EN (0x00800000) + +#define NETARM_MEM_CFG_REFR_CYCLE_8CLKS (0x00000000) +#define NETARM_MEM_CFG_REFR_CYCLE_6CLKS (0x00200000) +#define NETARM_MEM_CFG_REFR_CYCLE_5CLKS (0x00400000) +#define NETARM_MEM_CFG_REFR_CYCLE_4CLKS (0x00600000) + +#define NETARM_MEM_CFG_PORTC_AMUX (0x00100000) + +#define NETARM_MEM_CFG_A27_ADDR (0x00080000) +#define NETARM_MEM_CFG_A27_CS0OE (0x00000000) + +#define NETARM_MEM_CFG_A26_ADDR (0x00040000) +#define NETARM_MEM_CFG_A26_CS0WE (0x00000000) + +#define NETARM_MEM_CFG_A25_ADDR (0x00020000) +#define NETARM_MEM_CFG_A25_BLAST (0x00000000) + +#define NETARM_MEM_CFG_PORTC_AMUX2 (0x00010000) + + +/* range on this period is about 1 to 275 usec (with 18.432MHz clock) */ +/* the expression will round down, so make sure to reverse it to verify */ +/* it is what you want. period = [( count + 1 ) * 20] / Fcrystal */ +/* (note: Fxtal = Fcrystal/5, see HWRefGuide sections 8.2.5 and 11.3.2) */ + +#define NETARM_MEM_REFR_PERIOD_USEC(p) (NETARM_MEM_CFG_REFR_COUNT_MASK & \ + (((((NETARM_XTAL_FREQ/(1000))*p)/(20000) \ + ) - (1) ) << (24))) + +#if 0 +/* range on this period is about 1 to 275 usec (with 18.432MHz clock) */ +/* the expression will round down, so make sure to reverse it toverify */ +/* it is what you want. period = [( count + 1 ) * 4] / Fxtal */ + +#define NETARM_MEM_REFR_PERIOD_USEC(p) (NETARM_MEM_CFG_REFR_COUNT_MASK & \ + (((((NETARM_XTAL_FREQ/(1000))*p)/(4000) \ + ) - (1) ) << (24))) +#endif + +/* Base Address Registers (0xFFC0_00X0) */ + +#define NETARM_MEM_BAR_BASE_MASK (0xFFFFF000) + +/* macro to define base */ + +#define NETARM_MEM_BAR_BASE(x) ((x) & NETARM_MEM_BAR_BASE_MASK) + +#define NETARM_MEM_BAR_DRAM_FP (0x00000000) +#define NETARM_MEM_BAR_DRAM_EDO (0x00000100) +#define NETARM_MEM_BAR_DRAM_SYNC (0x00000200) + +#define NETARM_MEM_BAR_DRAM_MUX_INT (0x00000000) +#define NETARM_MEM_BAR_DRAM_MUX_EXT (0x00000080) + +#define NETARM_MEM_BAR_DRAM_MUX_BAL (0x00000000) +#define NETARM_MEM_BAR_DRAM_MUX_UNBAL (0x00000020) + +#define NETARM_MEM_BAR_1BCLK_IDLE (0x00000010) + +#define NETARM_MEM_BAR_DRAM_SEL (0x00000008) + +#define NETARM_MEM_BAR_BURST_EN (0x00000004) + +#define NETARM_MEM_BAR_WRT_PROT (0x00000002) + +#define NETARM_MEM_BAR_VALID (0x00000001) + +/* Option Registers (0xFFC0_00X4) */ + +/* macro to define which bits of the base are significant */ + +#define NETARM_MEM_OPT_BASE_USE(x) ((x) & NETARM_MEM_BAR_BASE_MASK) + +#define NETARM_MEM_OPT_WAIT_MASK (0x00000F00) + +#define NETARM_MEM_OPT_WAIT_STATES(x) (((x) << 8 ) & NETARM_MEM_OPT_WAIT_MASK ) + +#define NETARM_MEM_OPT_BCYC_1 (0x00000000) +#define NETARM_MEM_OPT_BCYC_2 (0x00000040) +#define NETARM_MEM_OPT_BCYC_3 (0x00000080) +#define NETARM_MEM_OPT_BCYC_4 (0x000000C0) + +#define NETARM_MEM_OPT_BSIZE_2 (0x00000000) +#define NETARM_MEM_OPT_BSIZE_4 (0x00000010) +#define NETARM_MEM_OPT_BSIZE_8 (0x00000020) +#define NETARM_MEM_OPT_BSIZE_16 (0x00000030) + +#define NETARM_MEM_OPT_32BIT (0x00000000) +#define NETARM_MEM_OPT_16BIT (0x00000004) +#define NETARM_MEM_OPT_8BIT (0x00000008) +#define NETARM_MEM_OPT_32BIT_EXT_ACK (0x0000000C) + +#define NETARM_MEM_OPT_BUS_SIZE_MASK (0x0000000C) + +#define NETARM_MEM_OPT_READ_ASYNC (0x00000000) +#define NETARM_MEM_OPT_READ_SYNC (0x00000002) + +#define NETARM_MEM_OPT_WRITE_ASYNC (0x00000000) +#define NETARM_MEM_OPT_WRITE_SYNC (0x00000001) + +#endif + diff --git a/include/asm-arm/arch-arm720t/netarm_registers.h b/include/asm-arm/arch-arm720t/netarm_registers.h new file mode 100644 index 0000000..231a378 --- /dev/null +++ b/include/asm-arm/arch-arm720t/netarm_registers.h @@ -0,0 +1,80 @@ +/* + * linux/include/asm-arm/arch-netarm/netarm_registers.h + * + * Copyright (C) 2000, 2001 NETsilicon, Inc. + * Copyright (C) 2000, 2001 WireSpeed Communications Corporation + * + * This software is copyrighted by WireSpeed. LICENSEE agrees that + * it will not delete this copyright notice, trademarks or protective + * notices from any copy made by LICENSEE. + * + * This software is provided "AS-IS" and any express or implied + * warranties or conditions, including but not limited to any + * implied warranties of merchantability and fitness for a particular + * purpose regarding this software. In no event shall WireSpeed + * be liable for any indirect, consequential, or incidental damages, + * loss of profits or revenue, loss of use or data, or interruption + * of business, whether the alleged damages are labeled in contract, + * tort, or indemnity. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * + * author(s) : Joe deBlaquiere + */ + +#ifndef __NET_ARM_REGISTERS_H +#define __NET_ARM_REGISTERS_H + +#include <config.h> + +/* fundamental constants : */ +/* the input crystal/clock frequency ( in Hz ) */ +#define NETARM_XTAL_FREQ_25MHz (18432000) +#define NETARM_XTAL_FREQ_33MHz (23698000) +#define NETARM_XTAL_FREQ_EMLIN1 (20000000) + +/* the frequency of SYS_CLK */ +#if defined(CONFIG_NETARM_EMLIN) + +/* EMLIN board: 33 MHz (exp.) */ +#define NETARM_PLL_COUNT_VAL 6 +#define NETARM_XTAL_FREQ NETARM_XTAL_FREQ_25MHz + +#elif defined(CONFIG_NETARM_NET40_REV2) + +/* NET+40 Rev2 boards: 33 MHz (with NETARM_XTAL_FREQ_25MHz) */ +#define NETARM_PLL_COUNT_VAL 6 +#define NETARM_XTAL_FREQ NETARM_XTAL_FREQ_25MHz + +#elif defined(CONFIG_NETARM_NET40_REV4) + +/* NET+40 Rev4 boards with EDO must clock slower: 25 MHz (with + NETARM_XTAL_FREQ_25MHz) 4 */ +#define NETARM_PLL_COUNT_VAL 4 +#define NETARM_XTAL_FREQ NETARM_XTAL_FREQ_25MHz + +#else /* CONFIG_NETARM_NET50 */ + +/* NET+50 boards: 40 MHz (with NETARM_XTAL_FREQ_25MHz) */ +#define NETARM_PLL_COUNT_VAL 8 +#define NETARM_XTAL_FREQ NETARM_XTAL_FREQ_25MHz + +#endif + +/* #include "arm_registers.h" */ +#include <asm/arch/netarm_gen_module.h> +#include <asm/arch/netarm_mem_module.h> +#include <asm/arch/netarm_ser_module.h> +#include <asm/arch/netarm_eni_module.h> +#include <asm/arch/netarm_dma_module.h> +#include <asm/arch/netarm_eth_module.h> + +#endif + diff --git a/include/asm-arm/arch-arm720t/netarm_ser_module.h b/include/asm-arm/arch-arm720t/netarm_ser_module.h new file mode 100644 index 0000000..fceabd1 --- /dev/null +++ b/include/asm-arm/arch-arm720t/netarm_ser_module.h @@ -0,0 +1,347 @@ +/* + * linux/include/asm-arm/arch-netarm/netarm_ser_module.h + * + * Copyright (C) 2000 NETsilicon, Inc. + * Copyright (C) 2000 Red Hat, Inc. + * + * This software is copyrighted by Red Hat. LICENSEE agrees that + * it will not delete this copyright notice, trademarks or protective + * notices from any copy made by LICENSEE. + * + * This software is provided "AS-IS" and any express or implied + * warranties or conditions, including but not limited to any + * implied warranties of merchantability and fitness for a particular + * purpose regarding this software. In no event shall Red Hat + * be liable for any indirect, consequential, or incidental damages, + * loss of profits or revenue, loss of use or data, or interruption + * of business, whether the alleged damages are labeled in contract, + * tort, or indemnity. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * + * author(s) : Joe deBlaquiere + * Clark Williams + */ + +#ifndef __NETARM_SER_MODULE_REGISTERS_H +#define __NETARM_SER_MODULE_REGISTERS_H + +#ifndef __ASSEMBLER__ + +/* (--sub)#include "types.h" */ + +/* serial channel control structure */ +typedef struct { + u32 ctrl_a; + u32 ctrl_b; + u32 status_a; + u32 bitrate; + u32 fifo; + u32 rx_buf_timer; + u32 rx_char_timer; + u32 rx_match; + u32 rx_match_mask; + u32 ctrl_c; + u32 status_b; + u32 status_c; + u32 fifo_last; + u32 unused[3]; +} netarm_serial_channel_t; + +#endif + +/* SER unit register offsets */ + +/* #ifdef CONFIG_ARCH_NETARM */ +#define NETARM_SER_MODULE_BASE (0xFFD00000) +/* #else */ +/* extern serial_channel_t netarm_dummy_registers[]; */ +/* #define NETARM_SER_MODULE_BASE (netarm_dummy_registers) */ +/* #ifndef NETARM_XTAL_FREQ */ +/* #define NETARM_XTAL_FREQ 18432000 */ +/* #endif */ +/* #endif */ + +/* calculate the sysclk value from the pll setting */ +#define NETARM_PLLED_SYSCLK_FREQ (( NETARM_XTAL_FREQ / 5 ) * \ + ( NETARM_PLL_COUNT_VAL + 3 )) + +#define get_serial_channel(c) (&(((netarm_serial_channel_t *)NETARM_SER_MODULE_BASE)[c])) + +#define NETARM_SER_CH1_CTRL_A (0x00) +#define NETARM_SER_CH1_CTRL_B (0x04) +#define NETARM_SER_CH1_STATUS_A (0x08) +#define NETARM_SER_CH1_BITRATE (0x0C) +#define NETARM_SER_CH1_FIFO (0x10) +#define NETARM_SER_CH1_RX_BUF_TMR (0x14) +#define NETARM_SER_CH1_RX_CHAR_TMR (0x18) +#define NETARM_SER_CH1_RX_MATCH (0x1c) +#define NETARM_SER_CH1_RX_MATCH_MASK (0x20) +#define NETARM_SER_CH1_CTRL_C (0x24) +#define NETARM_SER_CH1_STATUS_B (0x28) +#define NETARM_SER_CH1_STATUS_C (0x2c) +#define NETARM_SER_CH1_FIFO_LAST (0x30) + +#define NETARM_SER_CH2_CTRL_A (0x40) +#define NETARM_SER_CH2_CTRL_B (0x44) +#define NETARM_SER_CH2_STATUS_A (0x48) +#define NETARM_SER_CH2_BITRATE (0x4C) +#define NETARM_SER_CH2_FIFO (0x50) +#define NETARM_SER_CH2_RX_BUF_TMR (0x54) +#define NETARM_SER_CH2_RX_CHAR_TMR (0x58) +#define NETARM_SER_CH2_RX_MATCH (0x5c) +#define NETARM_SER_CH2_RX_MATCH_MASK (0x60) +#define NETARM_SER_CH2_CTRL_C (0x64) +#define NETARM_SER_CH2_STATUS_B (0x68) +#define NETARM_SER_CH2_STATUS_C (0x6c) +#define NETARM_SER_CH2_FIFO_LAST (0x70) + +/* select bitfield defintions */ + +/* Control Register A */ + +#define NETARM_SER_CTLA_ENABLE (0x80000000) +#define NETARM_SER_CTLA_BRK (0x40000000) + +#define NETARM_SER_CTLA_STICKP (0x20000000) + +#define NETARM_SER_CTLA_P_EVEN (0x18000000) +#define NETARM_SER_CTLA_P_ODD (0x08000000) +#define NETARM_SER_CTLA_P_NONE (0x00000000) + +/* if you read the errata, you will find that the STOP bits don't work right */ +#define NETARM_SER_CTLA_2STOP (0x00000000) +#define NETARM_SER_CTLA_3STOP (0x04000000) + +#define NETARM_SER_CTLA_5BITS (0x00000000) +#define NETARM_SER_CTLA_6BITS (0x01000000) +#define NETARM_SER_CTLA_7BITS (0x02000000) +#define NETARM_SER_CTLA_8BITS (0x03000000) + +#define NETARM_SER_CTLA_CTSTX (0x00800000) +#define NETARM_SER_CTLA_RTSRX (0x00400000) + +#define NETARM_SER_CTLA_LOOP_REM (0x00200000) +#define NETARM_SER_CTLA_LOOP_LOC (0x00100000) + +#define NETARM_SER_CTLA_GPIO2 (0x00080000) +#define NETARM_SER_CTLA_GPIO1 (0x00040000) + +#define NETARM_SER_CTLA_DTR_EN (0x00020000) +#define NETARM_SER_CTLA_RTS_EN (0x00010000) + +#define NETARM_SER_CTLA_IE_RX_BRK (0x00008000) +#define NETARM_SER_CTLA_IE_RX_FRMERR (0x00004000) +#define NETARM_SER_CTLA_IE_RX_PARERR (0x00002000) +#define NETARM_SER_CTLA_IE_RX_OVERRUN (0x00001000) +#define NETARM_SER_CTLA_IE_RX_RDY (0x00000800) +#define NETARM_SER_CTLA_IE_RX_HALF (0x00000400) +#define NETARM_SER_CTLA_IE_RX_FULL (0x00000200) +#define NETARM_SER_CTLA_IE_RX_DMAEN (0x00000100) +#define NETARM_SER_CTLA_IE_RX_DCD (0x00000080) +#define NETARM_SER_CTLA_IE_RX_RI (0x00000040) +#define NETARM_SER_CTLA_IE_RX_DSR (0x00000020) + +#define NETARM_SER_CTLA_IE_RX_ALL (NETARM_SER_CTLA_IE_RX_BRK \ + |NETARM_SER_CTLA_IE_RX_FRMERR \ + |NETARM_SER_CTLA_IE_RX_PARERR \ + |NETARM_SER_CTLA_IE_RX_OVERRUN \ + |NETARM_SER_CTLA_IE_RX_RDY \ + |NETARM_SER_CTLA_IE_RX_HALF \ + |NETARM_SER_CTLA_IE_RX_FULL \ + |NETARM_SER_CTLA_IE_RX_DMAEN \ + |NETARM_SER_CTLA_IE_RX_DCD \ + |NETARM_SER_CTLA_IE_RX_RI \ + |NETARM_SER_CTLA_IE_RX_DSR) + +#define NETARM_SER_CTLA_IE_TX_CTS (0x00000010) +#define NETARM_SER_CTLA_IE_TX_EMPTY (0x00000008) +#define NETARM_SER_CTLA_IE_TX_HALF (0x00000004) +#define NETARM_SER_CTLA_IE_TX_FULL (0x00000002) +#define NETARM_SER_CTLA_IE_TX_DMAEN (0x00000001) + +#define NETARM_SER_CTLA_IE_TX_ALL (NETARM_SER_CTLA_IE_TX_CTS \ + |NETARM_SER_CTLA_IE_TX_EMPTY \ + |NETARM_SER_CTLA_IE_TX_HALF \ + |NETARM_SER_CTLA_IE_TX_FULL \ + |NETARM_SER_CTLA_IE_TX_DMAEN) + +/* Control Register B */ + +#define NETARM_SER_CTLB_MATCH1_EN (0x80000000) +#define NETARM_SER_CTLB_MATCH2_EN (0x40000000) +#define NETARM_SER_CTLB_MATCH3_EN (0x20000000) +#define NETARM_SER_CTLB_MATCH4_EN (0x10000000) + +#define NETARM_SER_CTLB_RBGT_EN (0x08000000) +#define NETARM_SER_CTLB_RCGT_EN (0x04000000) + +#define NETARM_SER_CTLB_UART_MODE (0x00000000) +#define NETARM_SER_CTLB_HDLC_MODE (0x00100000) +#define NETARM_SER_CTLB_SPI_MAS_MODE (0x00200000) +#define NETARM_SER_CTLB_SPI_SLV_MODE (0x00300000) + +#define NETARM_SER_CTLB_REV_BIT_ORDER (0x00080000) + +#define NETARM_SER_CTLB_MAM1 (0x00040000) +#define NETARM_SER_CTLB_MAM2 (0x00020000) + +/* Status Register A */ + +#define NETARM_SER_STATA_MATCH1 (0x80000000) +#define NETARM_SER_STATA_MATCH2 (0x40000000) +#define NETARM_SER_STATA_MATCH3 (0x20000000) +#define NETARM_SER_STATA_MATCH4 (0x10000000) + +#define NETARM_SER_STATA_BGAP (0x80000000) +#define NETARM_SER_STATA_CGAP (0x40000000) + +#define NETARM_SER_STATA_RX_1B (0x00100000) +#define NETARM_SER_STATA_RX_2B (0x00200000) +#define NETARM_SER_STATA_RX_3B (0x00300000) +#define NETARM_SER_STATA_RX_4B (0x00000000) + +/* downshifted values */ + +#define NETARM_SER_STATA_RXFDB_1BYTES (0x001) +#define NETARM_SER_STATA_RXFDB_2BYTES (0x002) +#define NETARM_SER_STATA_RXFDB_3BYTES (0x003) +#define NETARM_SER_STATA_RXFDB_4BYTES (0x000) + +#define NETARM_SER_STATA_RXFDB_MASK (0x00300000) +#define NETARM_SER_STATA_RXFDB(x) (((x) & NETARM_SER_STATA_RXFDB_MASK) \ + >> 20) + +#define NETARM_SER_STATA_DCD (0x00080000) +#define NETARM_SER_STATA_RI (0x00040000) +#define NETARM_SER_STATA_DSR (0x00020000) +#define NETARM_SER_STATA_CTS (0x00010000) + +#define NETARM_SER_STATA_RX_BRK (0x00008000) +#define NETARM_SER_STATA_RX_FRMERR (0x00004000) +#define NETARM_SER_STATA_RX_PARERR (0x00002000) +#define NETARM_SER_STATA_RX_OVERRUN (0x00001000) +#define NETARM_SER_STATA_RX_RDY (0x00000800) +#define NETARM_SER_STATA_RX_HALF (0x00000400) +#define NETARM_SER_STATA_RX_CLOSED (0x00000200) +#define NETARM_SER_STATA_RX_FULL (0x00000100) +#define NETARM_SER_STATA_RX_DCD (0x00000080) +#define NETARM_SER_STATA_RX_RI (0x00000040) +#define NETARM_SER_STATA_RX_DSR (0x00000020) + +#define NETARM_SER_STATA_TX_CTS (0x00000010) +#define NETARM_SER_STATA_TX_RDY (0x00000008) +#define NETARM_SER_STATA_TX_HALF (0x00000004) +#define NETARM_SER_STATA_TX_FULL (0x00000002) +#define NETARM_SER_STATA_TX_DMAEN (0x00000001) + +/* you have to clear all receive signals to get the fifo to move forward */ +#define NETARM_SER_STATA_CLR_ALL (NETARM_SER_STATA_RX_BRK | \ + NETARM_SER_STATA_RX_FRMERR | \ + NETARM_SER_STATA_RX_PARERR | \ + NETARM_SER_STATA_RX_OVERRUN | \ + NETARM_SER_STATA_RX_HALF | \ + NETARM_SER_STATA_RX_CLOSED | \ + NETARM_SER_STATA_RX_FULL | \ + NETARM_SER_STATA_RX_DCD | \ + NETARM_SER_STATA_RX_RI | \ + NETARM_SER_STATA_RX_DSR | \ + NETARM_SER_STATA_TX_CTS ) + +/* Bit Rate Registers */ + +#define NETARM_SER_BR_EN (0x80000000) +#define NETARM_SER_BR_TMODE (0x40000000) + +#define NETARM_SER_BR_RX_CLK_INT (0x00000000) +#define NETARM_SER_BR_RX_CLK_EXT (0x20000000) +#define NETARM_SER_BR_TX_CLK_INT (0x00000000) +#define NETARM_SER_BR_TX_CLK_EXT (0x10000000) + +#define NETARM_SER_BR_RX_CLK_DRV (0x08000000) +#define NETARM_SER_BR_TX_CLK_DRV (0x04000000) + +#define NETARM_SER_BR_CLK_EXT_5 (0x00000000) +#define NETARM_SER_BR_CLK_SYSTEM (0x01000000) +#define NETARM_SER_BR_CLK_OUT1A (0x02000000) +#define NETARM_SER_BR_CLK_OUT2A (0x03000000) + +#define NETARM_SER_BR_TX_CLK_INV (0x00800000) +#define NETARM_SER_BR_RX_CLK_INV (0x00400000) + +/* complete settings assuming system clock input is 18MHz */ + +#define NETARM_SER_BR_MASK (0x000007FF) + +/* bit rate determined from equation Fbr = Fxtal / [ 10 * ( N + 1 ) ] */ +/* from section 7.5.4 of HW Ref Guide */ + +/* #ifdef CONFIG_NETARM_PLL_BYPASS */ +#define NETARM_SER_BR_X16(x) ( NETARM_SER_BR_EN | \ + NETARM_SER_BR_RX_CLK_INT | \ + NETARM_SER_BR_TX_CLK_INT | \ + NETARM_SER_BR_CLK_EXT_5 | \ + ( ( ( ( NETARM_XTAL_FREQ / \ + ( x * 10 ) ) - 1 ) / 16 ) & \ + NETARM_SER_BR_MASK ) ) +/* +#else +#define NETARM_SER_BR_X16(x) ( NETARM_SER_BR_EN | \ + NETARM_SER_BR_RX_CLK_INT | \ + NETARM_SER_BR_TX_CLK_INT | \ + NETARM_SER_BR_CLK_SYSTEM | \ + ( ( ( ( NETARM_PLLED_SYSCLK_FREQ / \ + ( x * 2 ) ) - 1 ) / 16 ) & \ + NETARM_SER_BR_MASK ) ) +#endif +*/ + +/* Receive Buffer Gap Timer */ + +#define NETARM_SER_RX_GAP_TIMER_EN (0x80000000) +#define NETARM_SER_RX_GAP_MASK (0x00003FFF) + +/* rx gap is a function of bit rate x */ + +/* #ifdef CONFIG_NETARM_PLL_BYPASS */ +#define NETARM_SER_RXGAP(x) ( NETARM_SER_RX_GAP_TIMER_EN | \ + ( ( ( ( 10 * NETARM_XTAL_FREQ ) / \ + ( x * 5 * 512 ) ) - 1 ) & \ + NETARM_SER_RX_GAP_MASK ) ) +/* +#else +#define NETARM_SER_RXGAP(x) ( NETARM_SER_RX_GAP_TIMER_EN | \ + ( ( ( ( 2 * NETARM_PLLED_SYSCLK_FREQ ) / \ + ( x * 512 ) ) - 1 ) & \ + NETARM_SER_RX_GAP_MASK ) ) +#endif +*/ + +#if 0 +#define NETARM_SER_RXGAP(x) ( NETARM_SER_RX_GAP_TIMER_EN | \ + ( ( ( ( 2 * NETARM_PLLED_SYSCLK_FREQ ) / \ + ( x * 5 * 512 ) ) - 1 ) & \ + NETARM_SER_RX_GAP_MASK ) ) +#define NETARM_SER_RXGAP(x) ( NETARM_SER_RX_GAP_TIMER_EN | \ + ( ( ( ( 10 * NETARM_XTAL_FREQ ) / \ + ( x * 512 ) ) - 1 ) & \ + NETARM_SER_RX_GAP_MASK ) ) +#endif + +#define MIN_BAUD_RATE 600 +#define MAX_BAUD_RATE 115200 + +/* the default BAUD rate for the BOOTLOADER, there is a separate */ +/* setting in the serial driver <arch/armnommu/drivers/char/serial-netarm.h> */ +#define DEFAULT_BAUD_RATE 9600 +#define NETARM_SER_FIFO_SIZE 32 +#define MIN_GAP 0 + +#endif diff --git a/include/cmd_confdefs.h b/include/cmd_confdefs.h index ebea56b..af5654c 100644 --- a/include/cmd_confdefs.h +++ b/include/cmd_confdefs.h @@ -85,6 +85,7 @@ #define CFG_CMD_MMC 0x0008000000000000U /* MMC support */ #define CFG_CMD_FAT 0x0010000000000000U /* FAT support */ #define CFG_CMD_IMLS 0x0020000000000000U /* List all found images */ +#define CFG_CMD_ITEST 0x0040000000000000U /* Integer (and string) test */ #define CFG_CMD_ALL 0xFFFFFFFFFFFFFFFFU /* ALL commands */ diff --git a/include/configs/modnet50.h b/include/configs/modnet50.h new file mode 100644 index 0000000..fd1b47c --- /dev/null +++ b/include/configs/modnet50.h @@ -0,0 +1,179 @@ +/* + * (C) Copyright 2004 + * IMMS, gGmbH <www.imms.de> + * Thomas Elste <info@elste.org> + * + * Configuation settings for ModNET50 board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * If we are developing, we might want to start u-boot from ram + * so we MUST NOT initialize critical regs like mem-timing ... + */ +#define CONFIG_INIT_CRITICAL /* undef for developing */ + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_ARM7 1 /* This is a ARM7 CPU */ +#define CONFIG_ARM_THUMB 1 /* this is an ARM720TDMI */ +#define CONFIG_NETARM /* it's a Netsiclicon NET+ARM */ +#undef CONFIG_NETARM_NET40_REV2 /* it's a Net+40 Rev. 2 */ +#undef CONFIG_NETARM_NET40_REV4 /* it's a Net+40 Rev. 4 */ +#define CONFIG_NETARM_NET50 /* it's a Net+50 */ + +#define CONFIG_MODNET50 1 /* on an ModNET50 Board */ + +#undef CONFIG_USE_IRQ /* don't need them anymore */ + +/* + * Size of malloc() pool + */ +#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) +#define CFG_GBL_DATA_SIZE 128 + +/* + * Hardware drivers + */ +#define CONFIG_DRIVER_NETARMETH 1 + +/* + * select serial console configuration + */ +#define CONFIG_SERIAL1 1 /* we use Serial line 1 */ + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_BAUDRATE 38400 + +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE) + +#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_JFFS2)) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include <cmd_confdefs.h> + +#define CONFIG_NETMASK 255.255.255.0 +#define CONFIG_IPADDR 192.168.30.2 +#define CONFIG_SERVERIP 192.168.30.122 +#define CFG_ETH_PHY_ADDR 0x100 +#define CONFIG_CMDLINE_TAG /* submit bootargs to kernel */ + +/*#define CONFIG_BOOTDELAY 10*/ +/* args and cmd for uClinux-image @ 0x10020000, ramdisk-image @ 0x100a0000 */ +#define CONFIG_BOOTCOMMAND "bootm 0x10020000 0x100a0000" +#define CONFIG_BOOTARGS "console=ttyS0,38400 initrd=0x100a0040,530K root=/dev/ram keepinitrd" + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "modnet50 # " /* Monitor Command Prompt */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x00400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x00800000 /* 4 ... 8 MB in DRAM */ + +#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ + +#define CFG_LOAD_ADDR 0x00500000 /* default load address */ + +#define CFG_HZ 900 /* decrementer freq: 2 kHz */ + + /* valid baudrates */ +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/*----------------------------------------------------------------------- + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below +*/ +#define CONFIG_STACKSIZE (128*1024) /* regular stack */ +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ +#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ +#endif + +/*----------------------------------------------------------------------- + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 banks of DRAM */ +#define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */ +#define PHYS_SDRAM_1_SIZE 0x01000000 /* 16 MB */ +#define PHYS_SDRAM_2 0x01000000 /* SDRAM Bank #1 */ +#define PHYS_SDRAM_2_SIZE 0x01000000 /* 16 MB */ + +#define PHYS_FLASH_1 0x10000000 /* Flash Bank #1 */ +#define PHYS_FLASH_1_SIZE 0x00200000 /* 2 MB (one chip only, 16bit access) */ + +#define PHYS_FLASH_2 0x10200001 +#define PHYS_FLASH_2_SIZE 0x00200000 + +#define CONFIG_NETARM_EEPROM +/* #ifdef CONFIG_NETARM_EEPROM */ +#define PHYS_NVRAM_1 0x20000000 /* EEPROM Bank #1 */ +#define PHYS_NVRAM_SIZE 0x00002000 /* 8 KB */ +/* #endif */ + +#define PHYS_EXT_1 0x30000000 /* Extensions Bank #1 */ +#define PHYS_EXT_SIZE 0x01000000 /* 32 MB memory mapped I/O */ + +#define CFG_FLASH_BASE PHYS_FLASH_1 +#define CFG_FLASH_SIZE PHYS_FLASH_1_SIZE + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 35 /* max number of sectors on one chip */ +#define CFG_MAIN_SECT_SIZE 0x00010000 /* main size of sectors on one chip */ + +/* timeout values are in ticks */ +#define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* Timeout for Flash Erase */ +#define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* Timeout for Flash Write */ + +/* environment settings */ +#define CFG_ENV_IS_IN_FLASH +#undef CFG_ENV_IS_NOWHERE + +#define CFG_ENV_ADDR 0x1001C000 /* environment start address */ +#define CFG_ENV_SECT_SIZE 0x10000 /* Total Size of Environment Sector */ +#define CFG_ENV_SIZE 0x4000 /* max size for environment */ + +/* Flash banks JFFS2 should use */ +#define CFG_JFFS2_FIRST_BANK 0 +#define CFG_JFFS2_FIRST_SECTOR 8 +#define CFG_JFFS2_NUM_BANKS 2 + +#endif /* __CONFIG_H */ diff --git a/include/fat.h b/include/fat.h index 8fffb42..13910f9 100644 --- a/include/fat.h +++ b/include/fat.h @@ -67,6 +67,10 @@ #define DELETED_FLAG ((char)0xe5) /* Marks deleted files when in name[0] */ #define aRING 0x05 /* Used to represent 'å' in name[0] */ +/* Indicates that the entry is the last long entry in a set of long + * dir entries + */ +#define LAST_LONG_ENTRY_MASK 0x40 /* Flags telling whether we should read a file or list a directory */ #define LS_NO 0 |