summaryrefslogtreecommitdiffstats
path: root/u-boot/board/cray
diff options
context:
space:
mode:
Diffstat (limited to 'u-boot/board/cray')
-rw-r--r--u-boot/board/cray/L1/L1.c366
-rw-r--r--u-boot/board/cray/L1/L1.h44
-rw-r--r--u-boot/board/cray/L1/Makefile63
-rw-r--r--u-boot/board/cray/L1/bootscript.hush117
-rw-r--r--u-boot/board/cray/L1/flash.c470
-rw-r--r--u-boot/board/cray/L1/init.S140
-rw-r--r--u-boot/board/cray/L1/patchme30
-rw-r--r--u-boot/board/cray/L1/u-boot.lds.debug135
-rw-r--r--u-boot/board/cray/L1/x2c.awk6
9 files changed, 1371 insertions, 0 deletions
diff --git a/u-boot/board/cray/L1/L1.c b/u-boot/board/cray/L1/L1.c
new file mode 100644
index 0000000..d87b6ef
--- /dev/null
+++ b/u-boot/board/cray/L1/L1.c
@@ -0,0 +1,366 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/ppc4xx-i2c.h>
+#include <command.h>
+#include <rtc.h>
+#include <post.h>
+#include <net.h>
+#include <malloc.h>
+
+#define L1_MEMSIZE (32*1024*1024)
+
+/* the std. DHCP stufff */
+#define DHCP_ROUTER 3
+#define DHCP_NETMASK 1
+#define DHCP_BOOTFILE 67
+#define DHCP_ROOTPATH 17
+#define DHCP_HOSTNAME 12
+
+/* some extras used by CRAY
+ *
+ * on the server this looks like:
+ *
+ * option L1-initrd-image code 224 = string;
+ * option L1-initrd-image "/opt/craysv2/craymcu/l1/flash/initrd.image"
+ */
+#define DHCP_L1_INITRD 224
+
+/* new, [better?] way via official vendor-extensions, defining an option
+ * space.
+ * on the server this looks like:
+ *
+ * option space CRAYL1;
+ * option CRAYL1.initrd code 3 = string;
+ * ..etc...
+ */
+#define DHCP_VENDOR_SPECX 43
+#define DHCP_VX_INITRD 3
+#define DHCP_VX_BOOTCMD 4
+#define DHCP_VX_BOOTARGS 5
+#define DHCP_VX_ROOTDEV 6
+#define DHCP_VX_FROMFLASH 7
+#define DHCP_VX_BOOTSCRIPT 8
+#define DHCP_VX_RCFILE 9
+#define DHCP_VX_MAGIC 10
+
+/* Things DHCP server can tellme about. If there's no flash address, then
+ * they dont participate in 'update' to flash, and we force their values
+ * back to '0' every boot to be sure to get them fresh from DHCP. Yes, I
+ * know this is a pain...
+ *
+ * If I get no bootfile, boot from flash. If rootpath, use that. If no
+ * rootpath use initrd in flash.
+ */
+typedef struct dhcp_item_s {
+ u8 dhcp_option;
+ u8 dhcp_vendor_option;
+ char *dhcpvalue;
+ char *envname;
+} dhcp_item_t;
+static dhcp_item_t Things[] = {
+ {DHCP_ROUTER, 0, NULL, "gateway"},
+ {DHCP_NETMASK, 0, NULL, "netmask"},
+ {DHCP_BOOTFILE, 0, NULL, "bootfile"},
+ {DHCP_ROOTPATH, 0, NULL, "rootpath"},
+ {DHCP_HOSTNAME, 0, NULL, "hostname"},
+ {DHCP_L1_INITRD, 0, NULL, "initrd"},
+/* and the other way.. */
+ {DHCP_VENDOR_SPECX, DHCP_VX_INITRD, NULL, "initrd"},
+ {DHCP_VENDOR_SPECX, DHCP_VX_BOOTCMD, NULL, "bootcmd"},
+ {DHCP_VENDOR_SPECX, DHCP_VX_FROMFLASH, NULL, "fromflash"},
+ {DHCP_VENDOR_SPECX, DHCP_VX_BOOTSCRIPT, NULL, "bootscript"},
+ {DHCP_VENDOR_SPECX, DHCP_VX_RCFILE, NULL, "rcfile"},
+ {DHCP_VENDOR_SPECX, DHCP_VX_BOOTARGS, NULL, "xbootargs"},
+ {DHCP_VENDOR_SPECX, DHCP_VX_ROOTDEV, NULL, NULL},
+ {DHCP_VENDOR_SPECX, DHCP_VX_MAGIC, NULL, NULL}
+};
+
+#define N_THINGS ((sizeof(Things))/(sizeof(dhcp_item_t)))
+
+extern char bootscript[];
+
+/* Here is the boot logic as HUSH script. Overridden by any TFP provided
+ * bootscript file.
+ */
+
+static void init_sdram (void);
+
+/* ------------------------------------------------------------------------- */
+int board_early_init_f (void)
+{
+ /* Running from ROM: global data is still READONLY */
+ init_sdram ();
+ mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
+ mtdcr (UIC0ER, 0x00000000); /* disable all ints */
+ mtdcr (UIC0CR, 0x00000020); /* set all but FPGA SMI to be non-critical */
+ mtdcr (UIC0PR, 0xFFFFFFE0); /* set int polarities */
+ mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */
+ mtdcr (UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */
+ mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
+ return 0;
+}
+
+/* ------------------------------------------------------------------------- */
+int checkboard (void)
+{
+ return (0);
+}
+/* ------------------------------------------------------------------------- */
+
+/* ------------------------------------------------------------------------- */
+int misc_init_r (void)
+{
+ char *s, *e;
+ image_header_t *hdr;
+ time_t timestamp;
+ struct rtc_time tm;
+ char bootcmd[32];
+
+ hdr = (image_header_t *) (CONFIG_SYS_MONITOR_BASE - image_get_header_size ());
+#if defined(CONFIG_FIT)
+ if (genimg_get_format ((void *)hdr) != IMAGE_FORMAT_LEGACY) {
+ puts ("Non legacy image format not supported\n");
+ return -1;
+ }
+#endif
+
+ timestamp = (time_t)image_get_time (hdr);
+ to_tm (timestamp, &tm);
+ printf ("Welcome to U-Boot on Cray L1. Compiled %4d-%02d-%02d %2d:%02d:%02d (UTC)\n", tm.tm_year, tm.tm_mon, tm.tm_mday, tm.tm_hour, tm.tm_min, tm.tm_sec);
+
+#define FACTORY_SETTINGS 0xFFFC0000
+ if ((s = getenv ("ethaddr")) == NULL) {
+ e = (char *) (FACTORY_SETTINGS);
+ if (*(e + 0) != '0'
+ || *(e + 1) != '0'
+ || *(e + 2) != ':'
+ || *(e + 3) != '4' || *(e + 4) != '0' || *(e + 17) != '\0') {
+ printf ("No valid MAC address in flash location 0x3C0000!\n");
+ } else {
+ printf ("Factory MAC: %s\n", e);
+ setenv ("ethaddr", e);
+ }
+ }
+ sprintf (bootcmd,"source %X",(unsigned)bootscript);
+ setenv ("bootcmd", bootcmd);
+ return (0);
+}
+
+/* ------------------------------------------------------------------------- */
+/* stubs so we can print dates w/o any nvram RTC.*/
+int rtc_get (struct rtc_time *tmp)
+{
+ return 0;
+}
+int rtc_set (struct rtc_time *tmp)
+{
+ return 0;
+}
+void rtc_reset (void)
+{
+ return;
+}
+
+/* ------------------------------------------------------------------------- */
+/* Do sdram bank init in C so I can read it..no console to print to yet!
+ */
+static void init_sdram (void)
+{
+ unsigned long tmp;
+
+ /* write SDRAM bank 0 register */
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR);
+ mtdcr (SDRAM0_CFGDATA, 0x00062001);
+
+/* Set the SDRAM Timing reg, SDTR1 and the refresh timer reg, RTR. */
+/* To set the appropriate timings, we need to know the SDRAM speed. */
+/* We can use the PLB speed since the SDRAM speed is the same as */
+/* the PLB speed. The PLB speed is the FBK divider times the */
+/* 405GP reference clock, which on the L1 is 25MHz. */
+/* Thus, if FBK div is 2, SDRAM is 50MHz; if FBK div is 3, SDRAM is */
+/* 150MHz; if FBK is 3, SDRAM is 150MHz. */
+
+ /* divisor = ((mfdcr(strap)>> 28) & 0x3); */
+
+/* write SDRAM timing for 100MHz. */
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_TR);
+ mtdcr (SDRAM0_CFGDATA, 0x0086400D);
+
+/* write SDRAM refresh interval register */
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_RTR);
+ mtdcr (SDRAM0_CFGDATA, 0x05F00000);
+ udelay (200);
+
+/* sdram controller.*/
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG);
+ mtdcr (SDRAM0_CFGDATA, 0x90800000);
+ udelay (200);
+
+/* initially, disable ECC on all banks */
+ udelay (200);
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCCFG);
+ tmp = mfdcr (SDRAM0_CFGDATA);
+ tmp &= 0xff0fffff;
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCCFG);
+ mtdcr (SDRAM0_CFGDATA, tmp);
+
+ return;
+}
+
+extern int memory_post_test (int flags);
+
+int testdram (void)
+{
+ unsigned long tmp;
+ uint *pstart = (uint *) 0x00000000;
+ uint *pend = (uint *) L1_MEMSIZE;
+ uint *p;
+
+ if (getenv_f("booted",NULL,0) <= 0)
+ {
+ printf ("testdram..");
+ /*AA*/
+ for (p = pstart; p < pend; p++)
+ *p = 0xaaaaaaaa;
+ for (p = pstart; p < pend; p++) {
+ if (*p != 0xaaaaaaaa) {
+ printf ("SDRAM test fails at: %08x, was %08x expected %08x\n",
+ (uint) p, *p, 0xaaaaaaaa);
+ return 1;
+ }
+ }
+ /*55*/
+ for (p = pstart; p < pend; p++)
+ *p = 0x55555555;
+ for (p = pstart; p < pend; p++) {
+ if (*p != 0x55555555) {
+ printf ("SDRAM test fails at: %08x, was %08x expected %08x\n",
+ (uint) p, *p, 0x55555555);
+ return 1;
+ }
+ }
+ /*addr*/
+ for (p = pstart; p < pend; p++)
+ *p = (unsigned)p;
+ for (p = pstart; p < pend; p++) {
+ if (*p != (unsigned)p) {
+ printf ("SDRAM test fails at: %08x, was %08x expected %08x\n",
+ (uint) p, *p, (uint)p);
+ return 1;
+ }
+ }
+ printf ("Success. ");
+ }
+ printf ("Enable ECC..");
+
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG);
+ tmp = (mfdcr (SDRAM0_CFGDATA) & ~0xFFE00000) | 0x90800000;
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG);
+ mtdcr (SDRAM0_CFGDATA, tmp);
+ udelay (600);
+ for (p = (unsigned long) 0; ((unsigned long) p < L1_MEMSIZE); *p++ = 0L)
+ ;
+ udelay (400);
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCCFG);
+ tmp = mfdcr (SDRAM0_CFGDATA);
+ tmp |= 0x00800000;
+ mtdcr (SDRAM0_CFGDATA, tmp);
+ udelay (400);
+ printf ("enabled.\n");
+ return (0);
+}
+
+/* ------------------------------------------------------------------------- */
+static u8 *dhcp_env_update (u8 thing, u8 * pop)
+{
+ u8 i, oplen;
+
+ oplen = *(pop + 1);
+
+ if ((Things[thing].dhcpvalue = malloc (oplen)) == NULL) {
+ printf ("Whoops! failed to malloc space for DHCP thing %s\n",
+ Things[thing].envname);
+ return NULL;
+ }
+ for (i = 0; (i < oplen); i++)
+ if ((*(Things[thing].dhcpvalue + i) = *(pop + 2 + i)) == ' ')
+ break;
+ *(Things[thing].dhcpvalue + i) = '\0';
+
+/* set env. */
+ if (Things[thing].envname)
+ {
+ setenv (Things[thing].envname, Things[thing].dhcpvalue);
+ }
+ return ((u8 *)(Things[thing].dhcpvalue));
+}
+
+/* ------------------------------------------------------------------------- */
+u8 *dhcp_vendorex_prep (u8 * e)
+{
+ u8 thing;
+
+/* ask for the things I want. */
+ *e++ = 55; /* Parameter Request List */
+ *e++ = N_THINGS;
+ for (thing = 0; thing < N_THINGS; thing++)
+ *e++ = Things[thing].dhcp_option;
+ *e++ = 255;
+
+ return e;
+}
+
+/* ------------------------------------------------------------------------- */
+/* .. return NULL means it wasnt mine, non-null means I got it..*/
+u8 *dhcp_vendorex_proc (u8 * pop)
+{
+ u8 oplen, *sub_op, sub_oplen, *retval;
+ u8 thing = 0;
+
+ retval = NULL;
+ oplen = *(pop + 1);
+/* if pop is vender spec indicator, there are sub-options. */
+ if (*pop == DHCP_VENDOR_SPECX) {
+ for (sub_op = pop + 2;
+ oplen && (sub_oplen = *(sub_op + 1));
+ oplen -= sub_oplen, sub_op += (sub_oplen + 2)) {
+ for (thing = 0; thing < N_THINGS; thing++) {
+ if (*sub_op == Things[thing].dhcp_vendor_option) {
+ if (!(retval = dhcp_env_update (thing, sub_op))) {
+ return NULL;
+ }
+ }
+ }
+ }
+ } else {
+ for (thing = 0; thing < N_THINGS; thing++) {
+ if (*pop == Things[thing].dhcp_option)
+ if (!(retval = dhcp_env_update (thing, pop)))
+ return NULL;
+ }
+ }
+ return (pop);
+}
diff --git a/u-boot/board/cray/L1/L1.h b/u-boot/board/cray/L1/L1.h
new file mode 100644
index 0000000..c3a0b8f
--- /dev/null
+++ b/u-boot/board/cray/L1/L1.h
@@ -0,0 +1,44 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/****************************************************************************
+ * FLASH Memory Map as used by CRAY L1, 4MB AMD29F032B flash chip
+ *
+ * Start Address Length
+ * +++++++++++++++++++++++++ 0xFFC0_0000 Start of Flash -----------------
+ * | Failsafe Linux Image | (1M)
+ * +=======================+ 0xFFD0_0000
+ * | (Reserved FlashFiles) | (1M)
+ * +=======================+ 0xFFE0_0000
+ * | Failsafe RootFS | (1M)
+ * +=======================+ 0xFFF0_0000
+ * | |
+ * | U N U S E D |
+ * | |
+ * +-----------------------+ 0xFFFD_0000 U-Boot image header (64 bytes)
+ * | environment settings | (64k)
+ * +-----------------------+ 0xFFFE_0000 U-Boot image header (64 bytes)
+ * | U-Boot | 0xFFFE_0040 _start of U-Boot
+ * | | 0xFFFE_FFFC reset vector - branch to _start
+ * +++++++++++++++++++++++++ 0xFFFF_FFFF End of Flash -----------------
+ *****************************************************************************/
diff --git a/u-boot/board/cray/L1/Makefile b/u-boot/board/cray/L1/Makefile
new file mode 100644
index 0000000..d1a7a0b
--- /dev/null
+++ b/u-boot/board/cray/L1/Makefile
@@ -0,0 +1,63 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS = $(BOARD).o flash.o
+SOBJS = init.o
+
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+# HACK: depend needs bootscript.c, which needs tools/mkimage, which is not
+# built in the depend stage. So... put bootscript.o here, not in OBJS
+$(LIB): $(OBJS) $(SOBJS) $(obj)bootscript.o
+ $(call cmd_link_o_target, $^)
+
+clean:
+ rm -f $(SOBJS) $(OBJS) $(obj)bootscript.c \
+ $(obj)bootscript.image $(obj)bootscript.o
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+$(obj)$(BOARD).o : $(src)$(BOARD).c $(obj)bootscript.o
+
+$(obj)bootscript.c: $(obj)bootscript.image
+ od -t x1 -v -A x $^ | awk -f x2c.awk > $@
+
+$(obj)bootscript.image: $(src)bootscript.hush $(src)Makefile
+ -$(OBJTREE)/tools/mkimage -A ppc -O linux -T script -C none -a 0 -e 0 -n bootscript -d $(src)bootscript.hush $@
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/cray/L1/bootscript.hush b/u-boot/board/cray/L1/bootscript.hush
new file mode 100644
index 0000000..f2f78ad
--- /dev/null
+++ b/u-boot/board/cray/L1/bootscript.hush
@@ -0,0 +1,117 @@
+# $Header$
+# hush bootscript for PPCBOOT on L1
+# note: all #s are in hex, do _NOT_ prefix it with 0x
+
+flash_rfs=ffc00000
+flash_krl=fff00000
+tftp_addr=100000
+tftp2_addr=1000000
+
+if printenv booted
+then
+ echo already booted before
+else
+ echo first boot in environment, create and save settings
+ setenv booted OK
+ saveenv
+fi
+
+setenv autoload no
+# clear out stale env stuff, so we get fresh from dhcp.
+for setting in initrd fromflash kernel rootfs rootpath
+do
+setenv $setting
+done
+
+dhcp
+
+# if host provides us with a different bootscript, us it.
+if printenv bootscript
+ then
+ tftp $tftp_addr $bootcript
+ if imi $tftp_addr
+ then
+ source $tftp_addr
+ fi
+fi
+
+# default base kernel arguments.
+setenv bootargs $xbootargs devfs=mount ip=$ipaddr:$serverip:$gatewayip:$netmask:L1:eth0:off wdt=120
+
+# Have a kernel in flash?
+if imi $flash_krl
+then
+ echo ok kernel to boot from $flash_krl
+ setenv kernel $flash_krl
+else
+ echo no kernel to boot from $flash_krl, need tftp
+fi
+
+# Have a rootfs in flash?
+echo test for SQUASHfs at $flash_rfs
+
+if imi $flash_rfs
+then
+ echo appears to be a good initrd image at base of flash OK
+ setenv rootfs $flash_rfs
+else
+ echo no image at base of flash, need nfsroot or initrd
+fi
+
+# I boot from flash if told to and I can.
+if printenv fromflash && printenv kernel && printenv rootfs
+then
+ echo booting entirely from flash
+ setenv bootargs root=/dev/ram0 rw $bootargs
+ bootm $kernel $rootfs
+ echo oh no failed so I try some other stuff
+fi
+
+# TFTP down a kernel
+if printenv bootfile
+then
+ tftp $tftp_addr $bootfile
+ setenv kernel $tftp_addr
+ echo I will boot the TFTP kernel
+else
+ if printenv kernel
+ then
+ echo no bootfile specified, will use one from flash
+ else
+ setenv bootfile /opt/crayx1/craymcu/l1/flash/linux.image
+ echo OH NO! we have no bootfile,nor flash kernel! try default: $bootfile
+ tftp $tftp_addr $bootfile
+ setenv kernel $tftp_addr
+ fi
+fi
+
+# the rootfs.
+if printenv rootpath
+then
+ echo rootpath is $rootpath
+ if printenv initrd
+ then
+ echo initrd is also specified, so use $initrd
+ tftp $tftp2_addr $initrd
+ setenv bootargs root=/dev/ram0 rw cwsroot=$serverip:$rootpath $bootargs
+ bootm $kernel $tftp2_addr
+ else
+ echo initrd is not specified, so use NFSROOT $rootpat
+ setenv bootargs root=/dev/nfs ro nfsroot=$serverip:$rootpath $bootargs
+ bootm $kernel
+ fi
+else
+ echo we have no rootpath check for one in flash
+ if printenv rootfs
+ then
+ echo I will use the one in flash
+ setenv bootargs root=/dev/mtdblock/0 ro rootfstype=squashfs $bootargs
+ bootm $kernel
+ else
+ setenv rootpath /export/crayl1
+ echo OH NO! we have no rootpath,nor flash kernel! try default: $rootpath
+ setenv bootargs root=/dev/mtdblock/0 ro rootfstype=squashfs $bootargs
+ bootm $kernel
+ fi
+fi
+reset
diff --git a/u-boot/board/cray/L1/flash.c b/u-boot/board/cray/L1/flash.c
new file mode 100644
index 0000000..a3d893e
--- /dev/null
+++ b/u-boot/board/cray/L1/flash.c
@@ -0,0 +1,470 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Modified 4/5/2001
+ * Wait for completion of each sector erase command issued
+ * 4/5/2001
+ * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com
+ */
+
+/*
+ * Modified July 20, 2001
+ * Strip down to support ONLY the AMD29F032B.
+ * Dave Updegraff - Cray, Inc. dave@cray.com
+ */
+
+#include <common.h>
+#include <asm/ppc4xx.h>
+#include <asm/processor.h>
+
+/* The flash chip we use... */
+#define AMD_ID_F032B 0x41 /* 29F032B ID 32 Mbit,64 64Kx8 sectors */
+#define FLASH_AM320B 0x0009
+
+
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long *addr, flash_info_t *info);
+static int write_word (flash_info_t *info, ulong dest, ulong data);
+static void flash_get_offsets (ulong base, flash_info_t *info);
+
+#define ADDR0 0x5555
+#define ADDR1 0x2aaa
+#define FLASH_WORD_SIZE unsigned char
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+ unsigned long size_b0, size_b1;
+ int i;
+
+ /* Init: no FLASHes known */
+ for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+ flash_info[i].flash_id = FLASH_UNKNOWN;
+ }
+
+ /* Static FLASH Bank configuration here - FIXME XXX */
+
+ size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
+
+ if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+ printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+ size_b0, size_b0<<20);
+ }
+
+ /* Only one bank */
+ if (CONFIG_SYS_MAX_FLASH_BANKS == 1)
+ {
+ /* Setup offsets */
+ flash_get_offsets (FLASH_BASE0_PRELIM, &flash_info[0]);
+
+#if 0
+ /* Monitor protection ON by default */
+ (void)flash_protect(FLAG_PROTECT_SET,
+ FLASH_BASE0_PRELIM,
+ FLASH_BASE0_PRELIM+monitor_flash_len-1,
+ &flash_info[0]);
+#endif
+ size_b1 = 0 ;
+ flash_info[0].size = size_b0;
+ }
+
+ return (size_b0 + size_b1);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t *info)
+{
+ int i;
+
+ /* set up sector start address table */
+ for (i = 0; i < info->sector_count; i++)
+ info->start[i] = base + (i * 0x00010000);
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t *info)
+{
+ int i;
+ int k;
+ int size;
+ int erased;
+ volatile unsigned long *flash;
+
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf ("missing or unknown FLASH type\n");
+ return;
+ }
+
+ switch (info->flash_id & FLASH_VENDMASK) {
+ case FLASH_MAN_AMD: printf ("AMD "); break;
+ default: printf ("Unknown Vendor "); break;
+ }
+
+ switch (info->flash_id & FLASH_TYPEMASK) {
+ case FLASH_AM320B:printf ("AM29F032B (32 Mbit 64x64KB uniform sectors)\n");
+ break;
+ default: printf ("Unknown Chip Type\n");
+ break;
+ }
+
+ printf (" Size: %ld KB in %d Sectors\n",
+ info->size >> 10, info->sector_count);
+
+ printf (" Sector Start Addresses:");
+ for (i=0; i<info->sector_count; ++i) {
+ /*
+ * Check if whole sector is erased
+ */
+ if (i != (info->sector_count-1))
+ size = info->start[i+1] - info->start[i];
+ else
+ size = info->start[0] + info->size - info->start[i];
+ erased = 1;
+ flash = (volatile unsigned long *)info->start[i];
+ size = size >> 2; /* divide by 4 for longword access */
+ for (k=0; k<size; k++)
+ {
+ if (*flash++ != 0xffffffff)
+ {
+ erased = 0;
+ break;
+ }
+ }
+
+ if ((i % 5) == 0)
+ printf ("\n ");
+
+ printf (" %08lX%s%s",
+ info->start[i],
+ erased ? " E" : " ",
+ info->protect[i] ? "RO " : " "
+ );
+ }
+ printf ("\n");
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+static ulong flash_get_size (vu_long *addr, flash_info_t *info)
+{
+ short i;
+ FLASH_WORD_SIZE value;
+ ulong base = (ulong)addr;
+ volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *)addr;
+
+ /* Write auto select command: read Manufacturer ID */
+ addr2[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
+ addr2[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
+ addr2[ADDR0] = (FLASH_WORD_SIZE)0x00900090;
+
+ value = addr2[0];
+
+ switch (value) {
+ case (FLASH_WORD_SIZE)AMD_MANUFACT:
+ info->flash_id = FLASH_MAN_AMD;
+ break;
+ default:
+ info->flash_id = FLASH_UNKNOWN;
+ info->sector_count = 0;
+ info->size = 0;
+ return (0); /* no or unknown flash */
+ }
+
+ value = addr2[1]; /* device ID */
+
+ switch (value) {
+ case (FLASH_WORD_SIZE)AMD_ID_F032B:
+ info->flash_id += FLASH_AM320B;
+ info->sector_count = 64;
+ info->size = 0x0400000; /* => 4 MB */
+ break;
+ default:
+ info->flash_id = FLASH_UNKNOWN;
+ return (0); /* => no or unknown flash */
+
+ }
+
+ /* set up sector start address table */
+ for (i = 0; i < info->sector_count; i++)
+ info->start[i] = base + (i * 0x00010000);
+
+ /* check for protected sectors */
+ for (i = 0; i < info->sector_count; i++) {
+ /* read sector protection at sector address, (A7 .. A0) = 0x02 */
+ /* D0 = 1 if protected */
+ addr2 = (volatile FLASH_WORD_SIZE *)(info->start[i]);
+ info->protect[i] = addr2[2] & 1;
+ }
+
+ /*
+ * Prevent writes to uninitialized FLASH.
+ */
+ if (info->flash_id != FLASH_UNKNOWN) {
+ addr2 = (FLASH_WORD_SIZE *)info->start[0];
+ *addr2 = (FLASH_WORD_SIZE)0x00F000F0; /* reset bank */
+ }
+
+ return (info->size);
+}
+
+int wait_for_DQ7(flash_info_t *info, int sect)
+{
+ ulong start, now, last;
+ volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[sect]);
+
+ start = get_timer (0);
+ last = start;
+ while ((addr[0] & (FLASH_WORD_SIZE)0x00800080) != (FLASH_WORD_SIZE)0x00800080) {
+ if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+ printf ("Timeout\n");
+ return -1;
+ }
+ /* show that we're waiting */
+ if ((now - last) > 1000) { /* every second */
+ putc ('.');
+ last = now;
+ }
+ }
+ return 0;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+ volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[0]);
+ volatile FLASH_WORD_SIZE *addr2;
+ int flag, prot, sect, l_sect;
+
+ if ((s_first < 0) || (s_first > s_last)) {
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf ("- missing\n");
+ } else {
+ printf ("- no sectors to erase\n");
+ }
+ return 1;
+ }
+
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf ("Can't erase unknown flash type - aborted\n");
+ return 1;
+ }
+
+ prot = 0;
+ for (sect=s_first; sect<=s_last; ++sect) {
+ if (info->protect[sect]) {
+ prot++;
+ }
+ }
+
+ if (prot) {
+ printf ("- Warning: %d protected sectors will not be erased!\n",
+ prot);
+ } else {
+ printf ("\n");
+ }
+
+ l_sect = -1;
+
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts();
+
+ /* Start erase on unprotected sectors */
+ for (sect = s_first; sect<=s_last; sect++) {
+ if (info->protect[sect] == 0) { /* not protected */
+ addr2 = (FLASH_WORD_SIZE *)(info->start[sect]);
+ printf("Erasing sector %p\n", addr2);
+
+ addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
+ addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
+ addr[ADDR0] = (FLASH_WORD_SIZE)0x00800080;
+ addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
+ addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
+ addr2[0] = (FLASH_WORD_SIZE)0x00300030; /* sector erase */
+ l_sect = sect;
+ /*
+ * Wait for each sector to complete, it's more
+ * reliable. According to AMD Spec, you must
+ * issue all erase commands within a specified
+ * timeout. This has been seen to fail, especially
+ * if printf()s are included (for debug)!!
+ */
+ wait_for_DQ7(info, sect);
+ }
+ }
+
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts();
+
+ /* wait at least 80us - let's wait 1 ms */
+ udelay (1000);
+
+ /* reset to read mode */
+ addr = (FLASH_WORD_SIZE *)info->start[0];
+ addr[0] = (FLASH_WORD_SIZE)0x00F000F0; /* reset bank */
+
+ printf (" done\n");
+ return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+ ulong cp, wp, data;
+ int i, l, rc;
+
+ wp = (addr & ~3); /* get lower word aligned address */
+
+ /*
+ * handle unaligned start bytes
+ */
+ if ((l = addr - wp) != 0) {
+ data = 0;
+ for (i=0, cp=wp; i<l; ++i, ++cp) {
+ data = (data << 8) | (*(uchar *)cp);
+ }
+ for (; i<4 && cnt>0; ++i) {
+ data = (data << 8) | *src++;
+ --cnt;
+ ++cp;
+ }
+ for (; cnt==0 && i<4; ++i, ++cp) {
+ data = (data << 8) | (*(uchar *)cp);
+ }
+
+ if ((rc = write_word(info, wp, data)) != 0) {
+ return (rc);
+ }
+ wp += 4;
+ }
+
+ /*
+ * handle word aligned part
+ */
+ while (cnt >= 4) {
+ data = 0;
+ for (i=0; i<4; ++i) {
+ data = (data << 8) | *src++;
+ }
+ if ((rc = write_word(info, wp, data)) != 0) {
+ return (rc);
+ }
+ wp += 4;
+ cnt -= 4;
+ }
+
+ if (cnt == 0) {
+ return (0);
+ }
+
+ /*
+ * handle unaligned tail bytes
+ */
+ data = 0;
+ for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+ data = (data << 8) | *src++;
+ --cnt;
+ }
+ for (; i<4; ++i, ++cp) {
+ data = (data << 8) | (*(uchar *)cp);
+ }
+
+ return (write_word(info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word (flash_info_t *info, ulong dest, ulong data)
+{
+ volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *)(info->start[0]);
+ volatile FLASH_WORD_SIZE *dest2 = (FLASH_WORD_SIZE *)dest;
+ volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *)&data;
+ ulong start;
+ int flag;
+ int i;
+
+ /* Check if Flash is (sufficiently) erased */
+ if ((*((volatile FLASH_WORD_SIZE *)dest) &
+ (FLASH_WORD_SIZE)data) != (FLASH_WORD_SIZE)data) {
+ return (2);
+ }
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts();
+
+ for (i=0; i<4/sizeof(FLASH_WORD_SIZE); i++)
+ {
+ addr2[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
+ addr2[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
+ addr2[ADDR0] = (FLASH_WORD_SIZE)0x00A000A0;
+
+ dest2[i] = data2[i];
+
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts();
+
+ /* data polling for D7 */
+ start = get_timer (0);
+ while ((dest2[i] & (FLASH_WORD_SIZE)0x00800080) !=
+ (data2[i] & (FLASH_WORD_SIZE)0x00800080)) {
+ if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
+ return (1);
+ }
+ }
+ }
+
+ return (0);
+}
+
+/*-----------------------------------------------------------------------
+ */
diff --git a/u-boot/board/cray/L1/init.S b/u-boot/board/cray/L1/init.S
new file mode 100644
index 0000000..1662141
--- /dev/null
+++ b/u-boot/board/cray/L1/init.S
@@ -0,0 +1,140 @@
+/*------------------------------------------------------------------------------+ */
+/* */
+/* This source code is dual-licensed. You may use it under the terms */
+/* of the GNU General Public License version 2, or under the license */
+/* below. */
+/* */
+/* This source code has been made available to you by IBM on an AS-IS */
+/* basis. Anyone receiving this source is licensed under IBM */
+/* copyrights to use it in any way he or she deems fit, including */
+/* copying it, modifying it, compiling it, and redistributing it either */
+/* with or without modifications. No license under IBM patents or */
+/* patent applications is to be implied by the copyright license. */
+/* */
+/* Any user of this software should understand that IBM cannot provide */
+/* technical support for this software and will not be responsible for */
+/* any consequences resulting from the use of this software. */
+/* */
+/* Any person who transfers this source code or any derivative work */
+/* must include the IBM copyright notice, this paragraph, and the */
+/* preceding two paragraphs in the transferred software. */
+/* */
+/* COPYRIGHT I B M CORPORATION 1995 */
+/* LICENSED MATERIAL - PROGRAM PROPERTY OF I B M */
+/*------------------------------------------------------------------------------- */
+
+/*----------------------------------------------------------------------------- */
+/* Function: ext_bus_cntlr_init */
+/* Description: Initializes the External Bus Controller for the external */
+/* peripherals. IMPORTANT: For pass1 this code must run from */
+/* cache since you can not reliably change a peripheral banks */
+/* timing register (pbxap) while running code from that bank. */
+/* For ex., since we are running from ROM on bank 0, we can NOT */
+/* execute the code that modifies bank 0 timings from ROM, so */
+/* we run it from cache. */
+/* Bank 0 - Flash and SRAM */
+/* Bank 1 - NVRAM/RTC */
+/* Bank 2 - Keyboard/Mouse controller */
+/* Bank 3 - IR controller */
+/* Bank 4 - not used */
+/* Bank 5 - not used */
+/* Bank 6 - not used */
+/* Bank 7 - FPGA registers */
+/*-----------------------------------------------------------------------------#include <config.h> */
+#include <asm/ppc4xx.h>
+
+#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
+
+#include <ppc_asm.tmpl>
+#include <ppc_defs.h>
+
+#include <asm/cache.h>
+#include <asm/mmu.h>
+
+/* CRAY - L1: only nominally a 'walnut', since ext.Bus.Cntlr is all empty */
+/* except for #1 which we use for DMA'ing to IOCA-like things, so the */
+/* control registers to set that up are determined by what we've */
+/* empirically discovered work there. */
+
+ .globl ext_bus_cntlr_init
+ext_bus_cntlr_init:
+ mflr r4 /* save link register */
+ bl ..getAddr
+..getAddr:
+ mflr r3 /* get address of ..getAddr */
+ mtlr r4 /* restore link register */
+ addi r4,0,14 /* set ctr to 10; used to prefetch */
+ mtctr r4 /* 10 cache lines to fit this function */
+ /* in cache (gives us 8x10=80 instrctns) */
+..ebcloop:
+ icbt r0,r3 /* prefetch cache line for addr in r3 */
+ addi r3,r3,32 /* move to next cache line */
+ bdnz ..ebcloop /* continue for 10 cache lines */
+
+ /*------------------------------------------------------------------- */
+ /* Delay to ensure all accesses to ROM are complete before changing */
+ /* bank 0 timings. 200usec should be enough. */
+ /* 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles */
+ /*------------------------------------------------------------------- */
+ addis r3,0,0x0
+ ori r3,r3,0xA000 /* ensure 200usec have passed since reset */
+ mtctr r3
+..spinlp:
+ bdnz ..spinlp /* spin loop */
+
+
+ /*---------------------------------------------------------------------- */
+ /* Peripheral Bank 0 (Flash) initialization */
+ /*---------------------------------------------------------------------- */
+ /* 0x7F8FFE80 slowest boot */
+ addi r4,0,PB1AP
+ mtdcr EBC0_CFGADDR,r4
+ addis r4,0,0x9B01
+ ori r4,r4,0x5480
+ mtdcr EBC0_CFGDATA,r4
+
+ addi r4,0,PB0CR
+ mtdcr EBC0_CFGADDR,r4
+ addis r4,0,0xFFC5 /* BAS=0xFFC,BS=0x4(4MB),BU=0x3(R/W), */
+ ori r4,r4,0x8000 /* BW=0x0( 8 bits) */
+ mtdcr EBC0_CFGDATA,r4
+
+ blr
+
+ /*---------------------------------------------------------------------- */
+ /* Peripheral Bank 1 (NVRAM/RTC) initialization */
+ /* CRAY:the L1 has NOT this bank, it is tied to SV2/IOCA/etc/ instead */
+ /* and we do DMA on it. The ConfigurationRegister part is threfore */
+ /* almost arbitrary, except that our linux driver needs to know the */
+ /* address, but it can query, it.. */
+ /* */
+ /* The AccessParameter is CRITICAL, */
+ /* thouch, since it needs to agree with the electrical timings on the */
+ /* IOCA parallel interface. That value is: 0x0185,4380 */
+ /* BurstModeEnable BME=0 */
+ /* TransferWait TWT=3 */
+ /* ChipSelectOnTiming CSN=1 */
+ /* OutputEnableOnTimimg OEN=1 */
+ /* WriteByteEnableOnTiming WBN=1 */
+ /* WriteByteEnableOffTiming WBF=0 */
+ /* TransferHold TH=1 */
+ /* ReadyEnable RE=1 */
+ /* SampleOnReady SOR=1 */
+ /* ByteEnableMode BEM=0 */
+ /* ParityEnable PEN=0 */
+ /* all reserved bits=0 */
+ /*---------------------------------------------------------------------- */
+ /*---------------------------------------------------------------------- */
+ addi r4,0,PB1AP
+ mtdcr EBC0_CFGADDR,r4
+ addis r4,0,0x0185 /* hiword */
+ ori r4,r4,0x4380 /* loword */
+ mtdcr EBC0_CFGDATA,r4
+
+ addi r4,0,PB1CR
+ mtdcr EBC0_CFGADDR,r4
+ addis r4,0,0xF001 /* BAS=0xF00,BS=0x0(1MB),BU=0x3(R/W), */
+ ori r4,r4,0x8000 /* BW=0x0( 8 bits) */
+ mtdcr EBC0_CFGDATA,r4
+
+ blr
diff --git a/u-boot/board/cray/L1/patchme b/u-boot/board/cray/L1/patchme
new file mode 100644
index 0000000..e77ee7e
--- /dev/null
+++ b/u-boot/board/cray/L1/patchme
@@ -0,0 +1,30 @@
+# master confi.mk
+echo "CROSS_COMPILE = powerpc-linux-" >>include/config.mk
+
+# patch the examples/Makefile to ignore return value from OBJCOPY
+sed -e 's/$(OBJCOPY)/-&/' < examples/Makefile > examples/makefile
+
+# add a built target for mkimage on the target architecture
+sed -e 's/^all:.*$/all: .depend envcrc mkimage mkimage.ppc/' < tools/Makefile > tools/makefile
+
+cat <<EOF >>tools/makefile
+mkimage.ppc : mkimage.o.ppc crc32.o.ppc
+ powerpc-linux-gcc -msoft-float -Wall -Wstrict-prototypes -o \$@ \$^
+ powerpc-linux-strip $@
+
+XFLAGS="-D__KERNEL__ -I../include -DCONFIG_4xx -Wall -Wstict-prototypes"
+mkimage.o.ppc: mkimage.c
+ powerpc-linux-gcc -msoft-float -Wall -I../include -c -o \$@ \$^
+
+crc32.o.ppc: crc32.c
+ powerpc-linux-gcc -msoft-float -Wall -I../include -c -o \$@ \$^
+
+EOF
+
+# make an image by default out of the u-boot image
+sed -e 's/^all:.*$/all: u-boot.image /' < Makefile > makefile
+cat <<EOF >>makefile
+u-boot.image: u-boot.bin
+ tools/mkimage -A ppc -O linux -T firmware -C none -a 0 -e 0 -n U-Boot -d \$^ \$@
+
+EOF
diff --git a/u-boot/board/cray/L1/u-boot.lds.debug b/u-boot/board/cray/L1/u-boot.lds.debug
new file mode 100644
index 0000000..0e9cdcf
--- /dev/null
+++ b/u-boot/board/cray/L1/u-boot.lds.debug
@@ -0,0 +1,135 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+/* Do we need any of these for elf?
+ __DYNAMIC = 0; */
+SECTIONS
+{
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ /* WARNING - the following is hand-optimized to fit within */
+ /* the sector layout of our flash chips! XXX FIXME XXX */
+
+ mpc8xx/start.o (.text)
+ common/dlmalloc.o (.text)
+ lib/vsprintf.o (.text)
+ lib/crc32.o (.text)
+ arch/powerpc/lib/extable.o (.text)
+
+ common/env_embedded.o(.text)
+
+ *(.text)
+ *(.got1)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(.rodata)
+ *(.rodata1)
+ *(.rodata.str1.4)
+ *(.eh_frame)
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x0FFF) & 0xFFFFF000;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ *(.got)
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+ __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(4096);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(4096);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss :
+ {
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ }
+ _end = . ;
+ PROVIDE (end = .);
+}
diff --git a/u-boot/board/cray/L1/x2c.awk b/u-boot/board/cray/L1/x2c.awk
new file mode 100644
index 0000000..9235e6c
--- /dev/null
+++ b/u-boot/board/cray/L1/x2c.awk
@@ -0,0 +1,6 @@
+#!/bin/awk
+BEGIN { print "unsigned char bootscript[] = { \n"}
+{ for (i = 2; i <= NF ; i++ ) printf "0x"$i","
+ print ""
+}
+END { print "\n};\n" }
generated by cgit v1.1 at 2024-12-22 22:59:11 +0000