diff options
Diffstat (limited to 'u-boot/board/imx31_phycore')
| -rw-r--r-- | u-boot/board/imx31_phycore/Makefile | 51 | ||||
| -rw-r--r-- | u-boot/board/imx31_phycore/config.mk | 1 | ||||
| -rw-r--r-- | u-boot/board/imx31_phycore/imx31_phycore.c | 140 | ||||
| -rw-r--r-- | u-boot/board/imx31_phycore/lowlevel_init.S | 104 |
4 files changed, 296 insertions, 0 deletions
diff --git a/u-boot/board/imx31_phycore/Makefile b/u-boot/board/imx31_phycore/Makefile new file mode 100644 index 0000000..4fd4864 --- /dev/null +++ b/u-boot/board/imx31_phycore/Makefile @@ -0,0 +1,51 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS := imx31_phycore.o +SOBJS := lowlevel_init.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS) $(SOBJS)) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/u-boot/board/imx31_phycore/config.mk b/u-boot/board/imx31_phycore/config.mk new file mode 100644 index 0000000..0131edf --- /dev/null +++ b/u-boot/board/imx31_phycore/config.mk @@ -0,0 +1 @@ +CONFIG_SYS_TEXT_BASE = 0x87f00000 diff --git a/u-boot/board/imx31_phycore/imx31_phycore.c b/u-boot/board/imx31_phycore/imx31_phycore.c new file mode 100644 index 0000000..3d7b7f7 --- /dev/null +++ b/u-boot/board/imx31_phycore/imx31_phycore.c @@ -0,0 +1,140 @@ +/* + * + * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#include <common.h> +#include <s6e63d6.h> +#include <netdev.h> +#include <asm/arch/mx31.h> +#include <asm/arch/mx31-regs.h> + +DECLARE_GLOBAL_DATA_PTR; + +int dram_init (void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + + return 0; +} + +int board_init (void) +{ + __REG(CSCR_U(0)) = 0x0000cf03; /* CS0: Nor Flash */ + __REG(CSCR_L(0)) = 0x10000d03; + __REG(CSCR_A(0)) = 0x00720900; + + __REG(CSCR_U(1)) = 0x0000df06; /* CS1: Network Controller */ + __REG(CSCR_L(1)) = 0x444a4541; + __REG(CSCR_A(1)) = 0x44443302; + + __REG(CSCR_U(4)) = 0x0000d843; /* CS4: SRAM */ + __REG(CSCR_L(4)) = 0x22252521; + __REG(CSCR_A(4)) = 0x22220a00; + + /* setup pins for UART1 */ + mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX); + mx31_gpio_mux(MUX_TXD1__UART1_TXD_MUX); + mx31_gpio_mux(MUX_RTS1__UART1_RTS_B); + mx31_gpio_mux(MUX_CTS1__UART1_CTS_B); + + /* setup pins for I2C2 (for EEPROM, RTC) */ + mx31_gpio_mux(MUX_CSPI2_MOSI__I2C2_SCL); + mx31_gpio_mux(MUX_CSPI2_MISO__I2C2_SDA); + + gd->bd->bi_arch_number = MACH_TYPE_PCM037; /* board id for linux */ + gd->bd->bi_boot_params = (0x80000100); /* adress of boot parameters */ + + return 0; +} + +#ifdef BOARD_LATE_INIT +int board_late_init(void) +{ +#ifdef CONFIG_S6E63D6 + struct s6e63d6 data = { + /* + * See comment in mxc_spi.c::decode_cs() for .cs field format. + * We use GPIO 57 as a chipselect for the S6E63D6 and chipselect + * 2 of the SPI controller #1, since it is unused. + */ + .cs = 2 | (57 << 8), + .bus = 0, + .id = 0, + }; + int ret; + + /* SPI1 */ + mx31_gpio_mux(MUX_CSPI1_SCLK__CSPI1_CLK); + mx31_gpio_mux(MUX_CSPI1_SPI_RDY__CSPI1_DATAREADY_B); + mx31_gpio_mux(MUX_CSPI1_MOSI__CSPI1_MOSI); + mx31_gpio_mux(MUX_CSPI1_MISO__CSPI1_MISO); + mx31_gpio_mux(MUX_CSPI1_SS0__CSPI1_SS0_B); + mx31_gpio_mux(MUX_CSPI1_SS1__CSPI1_SS1_B); + mx31_gpio_mux(MUX_CSPI1_SS2__CSPI1_SS2_B); + + /* start SPI1 clock */ + __REG(CCM_CGR2) = __REG(CCM_CGR2) | (3 << 2); + + /* GPIO 57 */ + /* sw_mux_ctl_key_col4_key_col5_key_col6_key_col7 */ + mx31_gpio_mux(IOMUX_MODE(0x63, MUX_CTL_GPIO)); + + /* SPI1 CS2 is free */ + ret = s6e63d6_init(&data); + if (ret) + return ret; + + /* + * This is a "magic" sequence to initialise a C0240QGLA / C0283QGLC + * OLED display connected to a S6E63D6 SPI display controller in the + * 18 bit RGB mode + */ + s6e63d6_index(&data, 2); + s6e63d6_param(&data, 0x0182); + s6e63d6_index(&data, 3); + s6e63d6_param(&data, 0x8130); + s6e63d6_index(&data, 0x10); + s6e63d6_param(&data, 0x0000); + s6e63d6_index(&data, 5); + s6e63d6_param(&data, 0x0001); + s6e63d6_index(&data, 0x22); +#endif + return 0; +} +#endif + +int checkboard (void) +{ + printf("Board: Phytec phyCore i.MX31\n"); + return 0; +} + +int board_eth_init(bd_t *bis) +{ + int rc = 0; +#ifdef CONFIG_SMC911X + rc = smc911x_initialize(0, CONFIG_SMC911X_BASE); +#endif + return rc; +} diff --git a/u-boot/board/imx31_phycore/lowlevel_init.S b/u-boot/board/imx31_phycore/lowlevel_init.S new file mode 100644 index 0000000..c5d6eb0 --- /dev/null +++ b/u-boot/board/imx31_phycore/lowlevel_init.S @@ -0,0 +1,104 @@ +/* + * + * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <asm/arch/mx31-regs.h> + +.macro REG reg, val + ldr r2, =\reg + ldr r3, =\val + str r3, [r2] +.endm + +.macro REG8 reg, val + ldr r2, =\reg + ldr r3, =\val + strb r3, [r2] +.endm + +.macro DELAY loops + ldr r2, =\loops +1: + subs r2, r2, #1 + nop + bcs 1b +.endm + +.globl lowlevel_init +lowlevel_init: + + REG IPU_CONF, IPU_CONF_DI_EN + REG CCM_CCMR, 0x074B0BF5 + + DELAY 0x40000 + + REG CCM_CCMR, 0x074B0BF5 | CCMR_MPE + REG CCM_CCMR, (0x074B0BF5 | CCMR_MPE) & ~CCMR_MDS + + REG CCM_PDR0, PDR0_CSI_PODF(0xff1) | PDR0_PER_PODF(7) | PDR0_HSP_PODF(3) | PDR0_NFC_PODF(5) | PDR0_IPG_PODF(1) | PDR0_MAX_PODF(3) | PDR0_MCU_PODF(0) + + REG CCM_MPCTL, PLL_PD(0) | PLL_MFD(0xe) | PLL_MFI(9) | PLL_MFN(0xd) + + REG CCM_SPCTL, PLL_PD(1) | PLL_MFD(0x43) | PLL_MFI(12) | PLL_MFN(1) + + REG 0x43FAC26C, 0 /* SDCLK */ + REG 0x43FAC270, 0 /* CAS */ + REG 0x43FAC274, 0 /* RAS */ + REG 0x43FAC27C, 0x1000 /* CS2 (CSD0) */ + REG 0x43FAC284, 0 /* DQM3 */ + REG 0x43FAC288, 0 /* DQM2, DQM1, DQM0, SD31-SD0, A25-A0, MA10 (0x288..0x2DC) */ + REG 0x43FAC28C, 0 + REG 0x43FAC290, 0 + REG 0x43FAC294, 0 + REG 0x43FAC298, 0 + REG 0x43FAC29C, 0 + REG 0x43FAC2A0, 0 + REG 0x43FAC2A4, 0 + REG 0x43FAC2A8, 0 + REG 0x43FAC2AC, 0 + REG 0x43FAC2B0, 0 + REG 0x43FAC2B4, 0 + REG 0x43FAC2B8, 0 + REG 0x43FAC2BC, 0 + REG 0x43FAC2C0, 0 + REG 0x43FAC2C4, 0 + REG 0x43FAC2C8, 0 + REG 0x43FAC2CC, 0 + REG 0x43FAC2D0, 0 + REG 0x43FAC2D4, 0 + REG 0x43FAC2D8, 0 + REG 0x43FAC2DC, 0 + REG 0xB8001010, 0x00000004 + REG 0xB8001004, 0x006ac73a + REG 0xB8001000, 0x92100000 + REG 0x80000f00, 0x12344321 + REG 0xB8001000, 0xa2100000 + REG 0x80000000, 0x12344321 + REG 0x80000000, 0x12344321 + REG 0xB8001000, 0xb2100000 + REG8 0x80000033, 0xda + REG8 0x81000000, 0xff + REG 0xB8001000, 0x82226080 + REG 0x80000000, 0xDEADBEEF + REG 0xB8001010, 0x0000000c + + mov pc, lr |