diff options
Diffstat (limited to 'u-boot/board/ti/evm/evm.c')
| -rw-r--r-- | u-boot/board/ti/evm/evm.c | 194 |
1 files changed, 194 insertions, 0 deletions
diff --git a/u-boot/board/ti/evm/evm.c b/u-boot/board/ti/evm/evm.c new file mode 100644 index 0000000..aaf3033 --- /dev/null +++ b/u-boot/board/ti/evm/evm.c @@ -0,0 +1,194 @@ +/* + * (C) Copyright 2004-2008 + * Texas Instruments, <www.ti.com> + * + * Author : + * Manikandan Pillai <mani.pillai@ti.com> + * + * Derived from Beagle Board and 3430 SDP code by + * Richard Woodruff <r-woodruff2@ti.com> + * Syed Mohammed Khasim <khasim@ti.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include <common.h> +#include <netdev.h> +#include <asm/io.h> +#include <asm/arch/mem.h> +#include <asm/arch/mux.h> +#include <asm/arch/sys_proto.h> +#include <i2c.h> +#include <asm/mach-types.h> +#include "evm.h" + +DECLARE_GLOBAL_DATA_PTR; + +static u32 omap3_evm_version; + +u32 get_omap3_evm_rev(void) +{ + return omap3_evm_version; +} + +static void omap3_evm_get_revision(void) +{ +#if defined(CONFIG_CMD_NET) + /* + * Board revision can be ascertained only by identifying + * the Ethernet chipset. + */ + unsigned int smsc_id; + + /* Ethernet PHY ID is stored at ID_REV register */ + smsc_id = readl(CONFIG_SMC911X_BASE + 0x50) & 0xFFFF0000; + printf("Read back SMSC id 0x%x\n", smsc_id); + + switch (smsc_id) { + /* SMSC9115 chipset */ + case 0x01150000: + omap3_evm_version = OMAP3EVM_BOARD_GEN_1; + break; + /* SMSC 9220 chipset */ + case 0x92200000: + default: + omap3_evm_version = OMAP3EVM_BOARD_GEN_2; + } +#else +#if defined(CONFIG_STATIC_BOARD_REV) + /* + * Look for static defintion of the board revision + */ + omap3_evm_version = CONFIG_STATIC_BOARD_REV; +#else + /* + * Fallback to the default above. + */ + omap3_evm_version = OMAP3EVM_BOARD_GEN_2; +#endif +#endif /* CONFIG_CMD_NET */ +} + +#ifdef CONFIG_USB_OMAP3 +/* + * MUSB port on OMAP3EVM Rev >= E requires extvbus programming. + */ +u8 omap3_evm_need_extvbus(void) +{ + u8 retval = 0; + + if (get_omap3_evm_rev() >= OMAP3EVM_BOARD_GEN_2) + retval = 1; + + return retval; +} +#endif + +/* + * Routine: board_init + * Description: Early hardware init. + */ +int board_init(void) +{ + gpmc_init(); /* in SRAM or SDRAM, finish GPMC */ + /* board id for Linux */ + gd->bd->bi_arch_number = MACH_TYPE_OMAP3EVM; + /* boot param addr */ + gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); + + return 0; +} + +/* + * Routine: misc_init_r + * Description: Init ethernet (done here so udelay works) + */ +int misc_init_r(void) +{ + +#ifdef CONFIG_DRIVER_OMAP34XX_I2C + i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); +#endif + +#if defined(CONFIG_CMD_NET) + setup_net_chip(); +#endif + omap3_evm_get_revision(); + + dieid_num_r(); + + return 0; +} + +/* + * Routine: set_muxconf_regs + * Description: Setting up the configuration Mux registers specific to the + * hardware. Many pins need to be moved from protect to primary + * mode. + */ +void set_muxconf_regs(void) +{ + MUX_EVM(); +} + +/* + * Routine: setup_net_chip + * Description: Setting up the configuration GPMC registers specific to the + * Ethernet hardware. + */ +static void setup_net_chip(void) +{ + struct gpio *gpio3_base = (struct gpio *)OMAP34XX_GPIO3_BASE; + struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE; + + /* Configure GPMC registers */ + writel(NET_GPMC_CONFIG1, &gpmc_cfg->cs[5].config1); + writel(NET_GPMC_CONFIG2, &gpmc_cfg->cs[5].config2); + writel(NET_GPMC_CONFIG3, &gpmc_cfg->cs[5].config3); + writel(NET_GPMC_CONFIG4, &gpmc_cfg->cs[5].config4); + writel(NET_GPMC_CONFIG5, &gpmc_cfg->cs[5].config5); + writel(NET_GPMC_CONFIG6, &gpmc_cfg->cs[5].config6); + writel(NET_GPMC_CONFIG7, &gpmc_cfg->cs[5].config7); + + /* Enable off mode for NWE in PADCONF_GPMC_NWE register */ + writew(readw(&ctrl_base ->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe); + /* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */ + writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe); + /* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */ + writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00, + &ctrl_base->gpmc_nadv_ale); + + /* Make GPIO 64 as output pin */ + writel(readl(&gpio3_base->oe) & ~(GPIO0), &gpio3_base->oe); + + /* Now send a pulse on the GPIO pin */ + writel(GPIO0, &gpio3_base->setdataout); + udelay(1); + writel(GPIO0, &gpio3_base->cleardataout); + udelay(1); + writel(GPIO0, &gpio3_base->setdataout); +} + +int board_eth_init(bd_t *bis) +{ + int rc = 0; +#ifdef CONFIG_SMC911X + rc = smc911x_initialize(0, CONFIG_SMC911X_BASE); +#endif + return rc; +} |