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+ AMCC Ocotea Board
+
+ Last Update: March 2, 2004
+=======================================================================
+
+This file contains some handy info regarding U-Boot and the AMCC
+Ocotea 440gx evalutation board. See the README.ppc440 for additional
+information.
+
+
+SWITCH SETTINGS & JUMPERS
+==========================
+
+Here's what I've been using successfully. If you feel inclined to
+change things ... please read the docs!
+
+DIPSW U46 U80
+------------------------
+SW 1 off off
+SW 2 on off
+SW 3 off off
+SW 4 off off
+SW 5 off off
+SW 6 on on
+SW 7 on off
+SW 8 on off
+
+J41: strapped
+J42: open
+
+All others are factory default.
+
+
+I2C Information
+=====================
+
+See README.ebony for information.
+
+PCI
+===========================
+
+Untested at the time of writing.
+
+PPC440GX Ethernet EMACs
+===========================
+
+All EMAC ports have been tested and are known to work
+with EPS Group 4.
+
+Special note about the Cicada CIS8201:
+ The CIS8201 Gigabit PHY comes up in GMII mode by default.
+ One must hit an extended register to allow use of RGMII mode.
+ This has been done in the 440gx_enet.c file with a #ifdef/endif
+ pair.
+
+AMCC does not store the EMAC ethernet addresses within their PIBS bootloader.
+The addresses contained in the config header file are from my particular
+board and you _*should*_ change them to reflect your board either in the
+config file and/or in your environment variables. I found the addresses on
+labels on the bottom side of the board.
+
+
+BDI2k or JTAG Debugging
+===========================
+
+For ease of debugging you can swap the small boot flash and external SRAM
+by changing U46:3 to on. You can then use the sram as your boot flash by
+loading the sram via the jtag debugger.
+
+
+Regards,
+--Travis
+<tsawyer@sandburst.com>