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* fsl-ddr: add the DDR3 SPD infrastructureDave Liu2009-03-301-1/+30
| | | | | | | | | - support mirrored DIMMs, not support register DIMMs - test passed on P2020DS board with MT9JSF12872AY-1G1D1 - test passed on MPC8569MDS board with MT8JSF12864HY-1G1D1 Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Travis Wheatley <travis.wheatley@freescale.com>
* 32bit BUg fix for DDR2 on 8572Poonam_Aggrwal-b108122009-02-161-0/+17
| | | | | | | This errata fix is required for 32 bit DDR2 controller on 8572. May also be required for P10XX20XX platforms Signed-off-by: Poonam_Agarwal-b10812 <b10812@lc1106.zin33.ap.freescale.net>
* fsl-ddr: make the self refresh idle threshold configurableDave Liu2009-01-231-0/+4
| | | | | | | | | | | | | Some 85xx processors have the advanced power management feature, such as wake up ARP, that needs enable the automatic self refresh. If the DDR controller pass the SR_IT (self refresh idle threshold) idle cycles, it will automatically enter self refresh. However, anytime one transaction is issued to the DDR controller, it will reset the counter and exit self refresh state. Signed-off-by: Dave Liu <daveliu@freescale.com> Acked-by: Andy Fleming <afleming@freescale.com>
* fsl-ddr: clean up the ddr code for DDR3 controllerDave Liu2009-01-231-0/+3
| | | | | | | | - The DDR3 controller is expanding the bits for timing config - Add the DDR3 32-bit bus mode support Signed-off-by: Dave Liu <daveliu@freescale.com> Acked-by: Andy Fleming <afleming@freescale.com>
* Make DDR interleaving mode work correctlyHaiying Wang2008-10-181-0/+12
| | | | | | | | | | Fix some bugs: 1. Correctly set intlv_ctl in cs_config. 2. Correctly set sa, ea in cs_bnds when bank interleaving mode is enabled. 3. Set base_address and total memory for each ddr controller in memory controller interleaving mode. Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
* FSL DDR: Rewrite the FSL mpc8xxx DDR controller setup code.Kumar Gala2008-08-271-0/+137
The main purpose of this rewrite it to be able to share the same initialization code on all FSL PowerPC products that have DDR controllers. (83xx, 85xx, 86xx). The code is broken up into the following steps: GET_SPD COMPUTE_DIMM_PARMS COMPUTE_COMMON_PARMS GATHER_OPTS ASSIGN_ADDRESSES COMPUTE_REGS PROGRAM_REGS This allows us to share more code an easily allow for board specific code overrides. Additionally this code base adds support for >4G of DDR and provides a foundation for supporting interleaving on processors with more than one controller. Signed-off-by: James Yang <James.Yang@freescale.com> Signed-off-by: Jon Loeliger <jdl@freescale.com> Signed-off-by: Becky Bruce <becky.bruce@freescale.com> Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>