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/* DO NOT EDIT THIS FILE
* Automatically generated by generate-def-headers.xsl
* DO NOT EDIT THIS FILE
*/
#ifndef __BFIN_DEF_ADSP_BF561_proc__
#define __BFIN_DEF_ADSP_BF561_proc__
#include "../mach-common/ADSP-EDN-core_def.h"
#include "../mach-common/ADSP-EDN-DUAL-CORE-extended_def.h"
#define SICA_SWRST 0xFFC00100
#define SICA_SYSCR 0xFFC00104
#define SICA_RVECT 0xFFC00108
#define SICA_IMASK0 0xFFC0010C
#define SICA_IMASK1 0xFFC00110
#define SICA_ISR0 0xFFC00114
#define SICA_ISR1 0xFFC00118
#define SICA_IWR0 0xFFC0011C
#define SICA_IWR1 0xFFC00120
#define SICA_IAR0 0xFFC00124
#define SICA_IAR1 0xFFC00128
#define SICA_IAR2 0xFFC0012C
#define SICA_IAR3 0xFFC00130
#define SICA_IAR4 0xFFC00134
#define SICA_IAR5 0xFFC00138
#define SICA_IAR6 0xFFC0013C
#define SICA_IAR7 0xFFC00140
#define SICB_SWRST 0xFFC01100
#define SICB_SYSCR 0xFFC01104
#define SICB_RVECT 0xFFC01108
#define SICB_IMASK0 0xFFC0110C
#define SICB_IMASK1 0xFFC01110
#define SICB_ISR0 0xFFC01114
#define SICB_ISR1 0xFFC01118
#define SICB_IWR0 0xFFC0111C
#define SICB_IWR1 0xFFC01120
#define SICB_IAR0 0xFFC01124
#define SICB_IAR1 0xFFC01128
#define SICB_IAR2 0xFFC0112C
#define SICB_IAR3 0xFFC01130
#define SICB_IAR4 0xFFC01134
#define SICB_IAR5 0xFFC01138
#define SICB_IAR6 0xFFC0113C
#define SICB_IAR7 0xFFC01140
#define PPI0_CONTROL 0xFFC01000
#define PPI0_STATUS 0xFFC01004
#define PPI0_DELAY 0xFFC0100C
#define PPI0_COUNT 0xFFC01008
#define PPI0_FRAME 0xFFC01010
#define PPI1_CONTROL 0xFFC01300
#define PPI1_STATUS 0xFFC01304
#define PPI1_DELAY 0xFFC0130C
#define PPI1_COUNT 0xFFC01308
#define PPI1_FRAME 0xFFC01310
#define UART_THR 0xFFC00400
#define UART_RBR 0xFFC00400
#define UART_DLL 0xFFC00400
#define UART_DLH 0xFFC00404
#define UART_IER 0xFFC00404
#define UART_IIR 0xFFC00408
#define UART_LCR 0xFFC0040C
#define UART_MCR 0xFFC00410
#define UART_LSR 0xFFC00414
#define UART_MSR 0xFFC00418
#define UART_SCR 0xFFC0041C
#define UART_GCTL 0xFFC00424
#define UART_GBL 0xFFC00424
#define EBIU_AMGCTL 0xFFC00A00
#define EBIU_AMBCTL0 0xFFC00A04
#define EBIU_AMBCTL1 0xFFC00A08
#define EBIU_SDGCTL 0xFFC00A10
#define EBIU_SDBCTL 0xFFC00A14
#define EBIU_SDRRC 0xFFC00A18
#define EBIU_SDSTAT 0xFFC00A1C
#define L1_INST_SRAM 0xFFA00000 /* 0xFFA00000 -> 0xFFA03FFF Instruction Bank A SRAM */
#define L1_INST_SRAM_SIZE (0xFFA03FFF - 0xFFA00000 + 1)
#define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE)
#define L1_SRAM_SCRATCH 0xFFB00000 /* 0xFFB00000 -> 0xFFB00FFF Scratchpad SRAM */
#define L1_SRAM_SCRATCH_SIZE (0xFFB00FFF - 0xFFB00000 + 1)
#define L1_SRAM_SCRATCH_END (L1_SRAM_SCRATCH + L1_SRAM_SCRATCH_SIZE)
#define SYSMMR_BASE 0xFFC00000 /* 0xFFC00000 -> 0xFFFFFFFF MMR registers */
#define SYSMMR_BASE_SIZE (0xFFFFFFFF - 0xFFC00000 + 1)
#define SYSMMR_BASE_END (SYSMMR_BASE + SYSMMR_BASE_SIZE)
#endif /* __BFIN_DEF_ADSP_BF561_proc__ */
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