1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
|
/*
* (C) Copyright 2007
* Developed for DENX Software Engineering GmbH.
*
* Author: Pavel Kolesnikov <concord@emcraft.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/* define DEBUG for debugging output (obviously ;-)) */
#if 0
#define DEBUG
#endif
#include <common.h>
#include <watchdog.h>
#ifdef CONFIG_POST
#include <post.h>
#if CONFIG_POST & CFG_POST_ECC
/*
* MEMORY ECC test
*
* This test performs the checks ECC facility of memory.
*/
#include <asm/processor.h>
#include <asm/mmu.h>
#include <asm/io.h>
#include <ppc440.h>
#include "../../../board/lwmon5/sdram.h"
DECLARE_GLOBAL_DATA_PTR;
const static unsigned char syndrome_codes[] = {
0xF4, 0XF1, 0XEC ,0XEA, 0XE9, 0XE6, 0XE5, 0XE3,
0XDC, 0XDA, 0XD9, 0XD6, 0XD5, 0XD3, 0XCE, 0XCB,
0xB5, 0XB0, 0XAD, 0XAB, 0XA8, 0XA7, 0XA4, 0XA2,
0X9D, 0X9B, 0X98, 0X97, 0X94, 0X92, 0X8F, 0X8A,
0x75, 0x70, 0X6D, 0X6B, 0X68, 0X67, 0X64, 0X62,
0X5E, 0X5B, 0X58, 0X57, 0X54, 0X52, 0X4F, 0X4A,
0x34, 0x31, 0X2C, 0X2A, 0X29, 0X26, 0X25, 0X23,
0X1C, 0X1A, 0X19, 0X16, 0X15, 0X13, 0X0E, 0X0B,
0x80, 0x40, 0x20, 0x10, 0x08, 0x04, 0x02, 0x01
};
#define ECC_START_ADDR 0x10
#define ECC_STOP_ADDR 0x2000
#define ECC_PATTERN 0x0101010101010101ull
#define ECC_PATTERN_CORR 0x0101010101010100ull
#define ECC_PATTERN_UNCORR 0x010101010101010Full
static int test_ecc_error(void)
{
unsigned long value;
unsigned long hdata, ldata, haddr, laddr;
unsigned int bit;
int ret = 0;
mfsdram(DDR0_23, value);
for (bit = 0; bit < sizeof(syndrome_codes); bit++)
if (syndrome_codes[bit] == ((value >> 16) & 0xff))
break;
mfsdram(DDR0_00, value);
if (value & DDR0_00_INT_STATUS_BIT0) {
debug("Bit0. A single access outside the defined PHYSICAL"
" memory space detected\n");
mfsdram(DDR0_32, laddr);
mfsdram(DDR0_33, haddr);
debug(" addr = 0x%08x%08x\n", haddr, laddr);
ret = 1;
}
if (value & DDR0_00_INT_STATUS_BIT1) {
debug("Bit1. Multiple accesses outside the defined PHYSICAL"
" memory space detected\n");
ret = 2;
}
if (value & DDR0_00_INT_STATUS_BIT2) {
debug("Bit2. Single correctable ECC event detected\n");
mfsdram(DDR0_38, laddr);
mfsdram(DDR0_39, haddr);
mfsdram(DDR0_40, ldata);
mfsdram(DDR0_41, hdata);
debug(" 0x%08x - 0x%08x%08x, bit - %d\n",
laddr, hdata, ldata, bit);
ret = 3;
}
if (value & DDR0_00_INT_STATUS_BIT3) {
debug("Bit3. Multiple correctable ECC events detected\n");
mfsdram(DDR0_38, laddr);
mfsdram(DDR0_39, haddr);
mfsdram(DDR0_40, ldata);
mfsdram(DDR0_41, hdata);
debug(" 0x%08x - 0x%08x%08x, bit - %d\n",
laddr, hdata, ldata, bit);
ret = 4;
}
if (value & DDR0_00_INT_STATUS_BIT4) {
debug("Bit4. Single uncorrectable ECC event detected\n");
mfsdram(DDR0_34, laddr);
mfsdram(DDR0_35, haddr);
mfsdram(DDR0_36, ldata);
mfsdram(DDR0_37, hdata);
debug(" 0x%08x - 0x%08x%08x, bit - %d\n",
laddr, hdata, ldata, bit);
ret = 5;
}
if (value & DDR0_00_INT_STATUS_BIT5) {
debug("Bit5. Multiple uncorrectable ECC events detected\n");
mfsdram(DDR0_34, laddr);
mfsdram(DDR0_35, haddr);
mfsdram(DDR0_36, ldata);
mfsdram(DDR0_37, hdata);
debug(" 0x%08x - 0x%08x%08x, bit - %d\n",
laddr, hdata, ldata, bit);
ret = 6;
}
if (value & DDR0_00_INT_STATUS_BIT6) {
debug("Bit6. DRAM initialization complete\n");
ret = 7;
}
/* error status cleared */
mfsdram(DDR0_00, value);
mtsdram(DDR0_00, value | DDR0_00_INT_ACK_ALL);
return ret;
}
static int test_ecc(unsigned long ecc_addr)
{
volatile unsigned long long *ecc_mem;
unsigned long value;
unsigned long ecc_data;
volatile unsigned long *lecc_mem;
int pret, ret = 0;
sync();
eieio();
WATCHDOG_RESET();
ecc_mem = (unsigned long long *)ecc_addr;
lecc_mem = (ulong *)ecc_addr;
*ecc_mem = ECC_PATTERN;
pret = test_ecc_error();
if (pret != 0)
ret = 1;
/* disconnect ecc */
mfsdram(DDR0_22, value);
mtsdram(DDR0_22, (value &~ DDR0_22_CTRL_RAW_MASK)
| DDR0_22_CTRL_RAW_ECC_DISABLE);
/* injecting error */
*ecc_mem = ECC_PATTERN_CORR;
/* enable ecc */
mfsdram(DDR0_22, value);
mtsdram(DDR0_22, (value &~ DDR0_22_CTRL_RAW_MASK)
| DDR0_22_CTRL_RAW_ECC_ENABLE);
ecc_data = *lecc_mem;
pret = test_ecc_error();
/* if read data ok, 1 correctable error must be fixed */
if (pret != 3)
ret = 1;
/* test for uncorrectable error */
/* disconnect from ecc storage */
mfsdram(DDR0_22, value);
mtsdram(DDR0_22, (value &~ DDR0_22_CTRL_RAW_MASK)
| DDR0_22_CTRL_RAW_NO_ECC_RAM);
/* injecting multiply bit error */
*ecc_mem = ECC_PATTERN_UNCORR;
/* enable ecc */
mfsdram(DDR0_22, value);
mtsdram(DDR0_22, (value &~ DDR0_22_CTRL_RAW_MASK)
| DDR0_22_CTRL_RAW_ECC_ENABLE);
ecc_data = *lecc_mem;
/* what the data should be read? */
pret = test_ecc_error();
/* info about uncorrectable error must appear */
if (pret != 5)
ret = 1;
sync();
eieio();
return ret;
}
int ecc_post_test (int flags)
{
int ret = 0;
unsigned long value;
unsigned long iaddr;
#if CONFIG_DDR_ECC
sync();
eieio();
/* mask all int */
mfsdram(DDR0_01, value);
mtsdram(DDR0_01, (value &~ DDR0_01_INT_MASK_MASK)
| DDR0_01_INT_MASK_ALL_OFF);
/* clear error status */
mfsdram(DDR0_00, value);
mtsdram(DDR0_00, value | DDR0_00_INT_ACK_ALL);
/* enable full support of ECC */
mfsdram(DDR0_22, value);
mtsdram(DDR0_22, (value &~ DDR0_22_CTRL_RAW_MASK)
| DDR0_22_CTRL_RAW_ECC_ENABLE);
for (iaddr = ECC_START_ADDR; iaddr < ECC_STOP_ADDR; iaddr += iaddr) {
ret = test_ecc(iaddr);
if (ret)
break;
}
/* clear error status */
mfsdram(DDR0_00, value);
mtsdram(DDR0_00, value | DDR0_00_INT_ACK_ALL);
/*
* Clear possible errors resulting from ECC testing.
* If not done, then we could get an interrupt later on when
* exceptions are enabled.
*/
set_mcsr(get_mcsr());
#endif
return ret;
}
#endif /* CONFIG_POST & CFG_POST_ECC */
#endif /* CONFIG_POST */
|
