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| author | H. Nikolaus Schaller <hns@goldelico.com> | 2012-04-20 14:10:36 +0200 |
|---|---|---|
| committer | H. Nikolaus Schaller <hns@goldelico.com> | 2012-04-20 14:10:36 +0200 |
| commit | 819e36b8ceadb1d67db1ffe91b99c5282bfc6159 (patch) | |
| tree | caa2bc25e54f0d41abb61920f29d3bf5eee3d864 /x-loader/board | |
| parent | a9a9e3f6aed040a12daf64157615f5e9fed974bb (diff) | |
| download | bootable_bootloader_goldelico_gta04_x-loader-819e36b8ceadb1d67db1ffe91b99c5282bfc6159.zip bootable_bootloader_goldelico_gta04_x-loader-819e36b8ceadb1d67db1ffe91b99c5282bfc6159.tar.gz bootable_bootloader_goldelico_gta04_x-loader-819e36b8ceadb1d67db1ffe91b99c5282bfc6159.tar.bz2 | |
tree moved to a better location
Diffstat (limited to 'x-loader/board')
45 files changed, 0 insertions, 13436 deletions
diff --git a/x-loader/board/omap2420h4/Makefile b/x-loader/board/omap2420h4/Makefile deleted file mode 100644 index e6f7629..0000000 --- a/x-loader/board/omap2420h4/Makefile +++ /dev/null @@ -1,51 +0,0 @@ -# -# (C) Copyright 2000, 2001, 2002 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).a - -COBJS := omap2420h4.o -SOBJS := platform.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) $(SOBJS) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak $(obj).depend - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/x-loader/board/omap2420h4/config.mk b/x-loader/board/omap2420h4/config.mk deleted file mode 100644 index 1c770f3..0000000 --- a/x-loader/board/omap2420h4/config.mk +++ /dev/null @@ -1,26 +0,0 @@ -# -# (C) Copyright 2004 -# Texas Instruments, <www.ti.com> -# -# TI H4 board with OMAP2420 (ARM1136) cpu -# see http://www.ti.com/ for more information on Texas Instruments -# -# H4 has 1 bank of 32MB or 64MB mDDR-SDRAM on CS0 -# H4 has 1 bank of 32MB or 00MB mDDR-SDRAM on CS1 -# Physical Address: -# 8000'0000 (bank0) -# A000/0000 (bank1) ES2 will be configurable -# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000 -# (mem base + reserved) - -# For use with external or internal boots. -# CONFIG_PARTIAL_SRAM must be defined to use this. -TEXT_BASE = 0x80e80000 - -# Used with full SRAM boot. -# This is either with a GP system or a signed boot image. -# easiest, and safest way to go if you can. -# Comment out //CONFIG_PARTIAL_SRAM for this one. -# -#TEXT_BASE = 0x40280000 - diff --git a/x-loader/board/omap2420h4/omap2420h4.c b/x-loader/board/omap2420h4/omap2420h4.c deleted file mode 100644 index ef81b49..0000000 --- a/x-loader/board/omap2420h4/omap2420h4.c +++ /dev/null @@ -1,598 +0,0 @@ -/* - * Copyright (C) 2005 Texas Instruments. - * Jian Zhang <jzhang@ti.com> - * Richard Woodruff <r-woodruff2@ti.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#include <common.h> -#include <asm/arch/omap2420.h> -#include <asm/arch/bits.h> - -#include <asm/arch/mem.h> -#include <asm/arch/sys_info.h> -#include <asm/arch/clocks.h> - -static void wait_for_command_complete(unsigned int wd_base); -static void watchdog_init(void); -static void peripheral_enable(void); -static void muxSetupUART1(void); -static u32 get_cpu_rev(void); - - -/******************************************************* - * Routine: delay - * Description: spinning delay to use before udelay works - ******************************************************/ -static inline void delay (unsigned long loops) -{ - __asm__ volatile ("1:\n" - "subs %0, %1, #1\n" - "bne 1b":"=r" (loops):"0" (loops)); -} - -/***************************************** - * Routine: board_init - * Description: Early hardware init. - *****************************************/ -int board_init (void) -{ - return 0; -} - -#ifdef CFG_SDRAM_DDR -void -config_sdram_ddr(u32 rev) -{ - /* ball D11, mode 0 */ - __raw_writeb(0x08, 0x48000032); - - /* SDRC_CS0 Configuration */ - if (rev == CPU_2420_2422_ES1) { - __raw_writel(H4_2422_SDRC_MDCFG_0_DDR, SDRC_MCFG_0); - __raw_writel(H4_2422_SDRC_SHARING, SDRC_SHARING); - } else { - __raw_writel(H4_2420_SDRC_MDCFG_0_DDR, SDRC_MCFG_0); - __raw_writel(H4_2420_SDRC_SHARING, SDRC_SHARING); - } - - __raw_writel(H4_242x_SDRC_RFR_CTRL_ES1, SDRC_RFR_CTRL); - __raw_writel(H4_242x_SDRC_ACTIM_CTRLA_0_ES1, SDRC_ACTIM_CTRLA_0); - __raw_writel(H4_242x_SDRC_ACTIM_CTRLB_0_ES1, SDRC_ACTIM_CTRLB_0); - - /* Manual Command sequence */ - __raw_writel(CMD_NOP, SDRC_MANUAL_0); - __raw_writel(CMD_PRECHARGE, SDRC_MANUAL_0); - __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0); - __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0); - - - /* - * CS0 SDRC Mode Register - * Burst length = 4 - DDR memory - * Serial mode - * CAS latency = 3 - */ - __raw_writel(0x00000032, SDRC_MR_0); - - /* SDRC DLLA control register */ - /* Delay is 90 degrees */ - if (rev == CPU_2420_2422_ES1) { - /* Enable DLL, Load counter with 115 (middle of range) */ - __raw_writel(0x00000002, SDRC_DLLA_CTRL); - /* Enable DLL, Load counter with 128 (middle of range) */ - __raw_writel(0x00000002, SDRC_DLLB_CTRL); - } else { - /* Enable DLL, Load counter with 115 (middle of range) */ - __raw_writel(0x00000008, SDRC_DLLA_CTRL); // ES2.x - /* Enable DLL, Load counter with 128 (middle of range) */ - __raw_writel(0x00000008, SDRC_DLLB_CTRL); // ES2.x - } - -} -#endif // CFG_SDRAM_DDR - - -#ifdef CFG_SDRAM_COMBO -void -config_sdram_combo(u32 rev) -{ - - u32 dllctrl=0; - - /* ball C12, mode 0 */ - __raw_writeb(0x00, 0x480000a1); - /* ball D11, mode 0 */ - __raw_writeb(0x00, 0x48000032); - /* ball B13, mode 0 - for CKE1 (not needed rkw for combo) */ - __raw_writeb(0x00, 0x480000a3); - - /*configure sdrc 32 bit for COMBO ddr sdram. Issue soft reset */ - __raw_writel(0x00000012, SDRC_SYSCONFIG); - delay(200000); - __raw_writel(0x00000010, SDRC_SYSCONFIG); - - /* SDRCTriState: no Tris */ - /* CS0MuxCfg: 000 (32-bit SDRAM on D31..0) */ - __raw_writel(H4_2420_SDRC_SHARING, SDRC_SHARING); - - - /* CS0 SDRC Memory Configuration, */ - /* DDR-SDRAM, External SDRAM is x32bit, */ - /* Configure to MUX9: 1x8Mbx32 */ - __raw_writel(H4_2420_COMBO_MDCFG_0_DDR, SDRC_MCFG_0); - __raw_writel(H4_2420_SDRC_ACTIM_CTRLA_0, SDRC_ACTIM_CTRLA_0); - __raw_writel(H4_2420_SDRC_ACTIM_CTRLB_0, SDRC_ACTIM_CTRLB_0); - __raw_writel(H4_242x_SDRC_RFR_CTRL_ES1, SDRC_RFR_CTRL); - - /* Manual Command sequence */ - __raw_writel(CMD_NOP, SDRC_MANUAL_0); - __raw_writel(CMD_PRECHARGE, SDRC_MANUAL_0); - __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0); - __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0); - - /* CS0 SDRC Mode Register */ - /* Burst length = 4 - DDR memory */ - /* Serial mode */ - /* CAS latency = 3 */ - __raw_writel(H4_2422_SDRC_MR_0_DDR, SDRC_MR_0); - - /* CS1 SDRC Memory Configuration, */ - /* DDR-SDRAM, External SDRAM is x32bit, */ - /* Configure to MUX9: 1x8Mbx32 */ - __raw_writel(H4_2420_COMBO_MDCFG_0_DDR, SDRC_MCFG_1); - __raw_writel(H4_242X_SDRC_ACTIM_CTRLA_0_100MHz, SDRC_ACTIM_CTRLA_1); - __raw_writel(H4_2420_SDRC_ACTIM_CTRLB_0, SDRC_ACTIM_CTRLB_1); - __raw_writel(H4_242x_SDRC_RFR_CTRL_ES1, 0x680090d4); - - /* Manual Command sequence */ - __raw_writel(CMD_NOP, SDRC_MANUAL_1); - __raw_writel(CMD_PRECHARGE, SDRC_MANUAL_1); - __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_1); - __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_1); - - /* CS1 SDRC Mode Register */ - /* Burst length = 4 - DDR memory */ - /* Serial mode */ - /* CAS latency = 3 */ - __raw_writel(H4_2422_SDRC_MR_0_DDR, SDRC_MR_1); - - /* SDRC DLLA control register */ - /* Delay is 90 degrees */ - if (rev == CPU_242X_ES1) - dllctrl = (BIT0|BIT3); - else - dllctrl = BIT0; - - if (rev == CPU_2420_2422_ES1) { - /* Enable DLL, Load counter with 115 (middle of range) */ - __raw_writel(0x00007306, SDRC_DLLA_CTRL); - __raw_writel(0x00007302, SDRC_DLLA_CTRL); - /* Enable DLL, Load counter with 128 (middle of range) */ - __raw_writel(0x00007306, SDRC_DLLB_CTRL); /* load ctr value */ - __raw_writel(0x00007302, SDRC_DLLB_CTRL); /* lock and go */ - } - else { - /* Enable DLL, Load counter with 115 (middle of range) */ - __raw_writel(H4_2420_SDRC_DLLAB_CTRL, SDRC_DLLA_CTRL); // ES2.x - __raw_writel(H4_2420_SDRC_DLLAB_CTRL & ~(LOADDLL|dllctrl), SDRC_DLLA_CTRL); // ES2.x - __raw_writel(H4_2420_SDRC_DLLAB_CTRL, SDRC_DLLB_CTRL); // ES2.x ? - __raw_writel(H4_2420_SDRC_DLLAB_CTRL & ~(LOADDLL|dllctrl), SDRC_DLLB_CTRL); // ES2.x - } -} - -#endif // CFG_SDRAM_COMBO - -#ifdef CFG_SDRAM_SDR -void -config_sdram_sdr(u32 rev) -{ - u32 dllctrl=0; - - /* ball D11, mode 0 */ - __raw_writeb(0x00, 0x48000032); - - __raw_writel(0x00000012, SDRC_SYSCONFIG); - delay(200000); - __raw_writel(0x00000010, SDRC_SYSCONFIG); - - /* Chip-level shared interface management */ - /* SDRCTriState: no Tris */ - /* CS0MuxCfg: 000 (32-bit SDRAM on D31..0) */ - /* CS1MuxCfg: 000 (32-bit SDRAM on D31..0) */ - if (rev == CPU_2420_2422_ES1) - __raw_writel(H4_2422_SDRC_SHARING, SDRC_SHARING); - else - __raw_writel(H4_2420_SDRC_SHARING, SDRC_SHARING); - - /* CS0 SDRC Memory Configuration, */ - /* DDR-SDRAM, External SDRAM is x32bit, */ - /* Configure to MUX14: 32Mbx32 */ - __raw_writel(H4_2420_SDRC_MDCFG_0_SDR, SDRC_MCFG_0); /* diff from combo case */ - __raw_writel(H4_2420_SDRC_ACTIM_CTRLA_0, SDRC_ACTIM_CTRLA_0); - __raw_writel(H4_2420_SDRC_ACTIM_CTRLB_0, SDRC_ACTIM_CTRLB_0); - __raw_writel(H4_242x_SDRC_RFR_CTRL_ES1, SDRC_RFR_CTRL); - - /* Manual Command sequence */ - __raw_writel(CMD_NOP, SDRC_MANUAL_0); - __raw_writel(CMD_PRECHARGE, SDRC_MANUAL_0); - __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0); - __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0); - - /* CS0 SDRC Mode Register */ - /* Burst length = 2 - SDR memory */ - /* Serial mode */ - /* CAS latency = 3 */ - __raw_writel(H4_2420_SDRC_MR_0_SDR, SDRC_MR_0); /* diff from combo case */ - - /* SDRC DLLA control register */ - /* Enable DLL, Load counter with 115 (middle of range) */ - /* Delay is 90 degrees */ - - if (rev == CPU_242X_ES1) - dllctrl = (BIT0|BIT3); - else - dllctrl = BIT0; - - if (rev == CPU_2420_2422_ES1) { - __raw_writel(0x00007306, SDRC_DLLA_CTRL); - __raw_writel(0x00007302, SDRC_DLLA_CTRL); - /* Enable DLL, Load counter with 128 (middle of range) */ - __raw_writel(0x00007306, SDRC_DLLB_CTRL); /* load ctr value */ - __raw_writel(0x00007302, SDRC_DLLB_CTRL); /* lock and go */ - } - else { - __raw_writel(H4_2420_SDRC_DLLAB_CTRL, SDRC_DLLA_CTRL); // ES2.x - __raw_writel(H4_2420_SDRC_DLLAB_CTRL & ~(LOADDLL|dllctrl), SDRC_DLLA_CTRL); // ES2.x - /* Enable DLL, Load counter with 128 (middle of range) */ - __raw_writel(H4_2420_SDRC_DLLAB_CTRL, SDRC_DLLB_CTRL); // ES2.x - __raw_writel(H4_2420_SDRC_DLLAB_CTRL & ~(LOADDLL|dllctrl), SDRC_DLLB_CTRL); // ES2.x - } - -} -#endif // CFG_SDRAM_SDR - -#ifdef CFG_SDRAM_STACKED -void -config_sdram_stacked(u32 rev) -{ - - /* Pin Muxing for SDRC */ - __raw_writeb(0x00, 0x480000a1); /* mux mode 0 (CS1) */ - __raw_writeb(0x00, 0x480000a3); /* mux mode 0 (CKE1) */ - __raw_writeb(0x00, 0x48000032); /* connect sdrc_a12 */ - __raw_writeb(0x00, 0x48000031); /* connect sdrc_a13 */ - - /* configure sdrc 32 bit for COMBO ddr sdram */ - __raw_writel(0x00000010, SDRC_SYSCONFIG); /* no idle ack and RESET enable */ - delay(200000); - __raw_writel(0x00000010, SDRC_SYSCONFIG); /* smart idle mode */ - - /* SDRC_SHARING */ - /* U-boot is writing 0x00000100 though (H4_2420_SDRC_SHARING ) */ - //__raw_writel(H4_2420_SDRC_SHARING, SDRC_SHARING); - - __raw_writel(0x00004900, SDRC_SHARING); - - /* SDRC_CS0 Configuration */ - /* None for ES2.1 */ - - /* SDRC_CS1 Configuration */ - __raw_writel(0x00000000, SDRC_CS_CFG); /* Remap CS1 to 0x80000000 */ - - /* Disable power down of CKE */ - __raw_writel(0x00000085, SDRC_POWER); - - __raw_writel(0x01A02019, SDRC_MCFG_1); /* SDRC_MCFG1 */ - __raw_writel(0x0003DD03, SDRC_RFR_CTRL1); /* SDRC_RFR_CTRL1 */ - __raw_writel(0x92DDC485, SDRC_ACTIM_CTRLA_1); /* SDRC_ACTIM_CTRLA0 */ - __raw_writel(0x00000014, SDRC_ACTIM_CTRLB_1); /* SDRC_ACTIM_CTRLB0 */ - - /*Manual Command sequence */ - __raw_writel(CMD_NOP, SDRC_MANUAL_1); - __raw_writel(CMD_PRECHARGE, SDRC_MANUAL_1); - __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_1); - __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_1); - - /* CS0 SDRC Mode Register */ - /* Burst length = 4 - DDR memory */ - /* Serial mode */ - /* CAS latency = 3 */ - __raw_writel(0x00000032, SDRC_MR_1); - __raw_writel(0x00000020, SDRC_EMR2_1); /* weak-strength driver */ - - /* SDRC DLLA control register */ - /* Delay is 90 degrees */ - if (rev == CPU_2420_2422_ES1) { - /* Enable DLL, Load counter with 115 (middle of range) */ - __raw_writel(0x00007302, SDRC_DLLA_CTRL); - /* Enable DLL, Load counter with 128 (middle of range) */ - __raw_writel(0x00007302, SDRC_DLLB_CTRL); - } - else { - /* Enable DLL, Load counter with 115 (middle of range) */ - __raw_writel(0x00003108, SDRC_DLLA_CTRL); // ES2.x - /* Enable DLL, Load counter with 128 (middle of range) */ - __raw_writel(0x00003108, SDRC_DLLB_CTRL); // ES2.x - } -} -#endif // CFG_SDRAM_STACKED - -/********************************************************** - * Routine: s_init - * Description: Does early system init of muxing and clocks. - * - Called at time when only stack is available. - **********************************************************/ -int s_init(int skip) -{ - u32 rev; - - rev = get_cpu_rev(); - - watchdog_init(); - muxSetupUART1(); - delay(100); - - /*DPLL out = 2x DPLL --> core clock */ - __raw_writel(DPLL_OUT, CM_CLKSEL2_PLL); - - /*DPLL into low power bypass (others off) */ - __raw_writel(0x00000001, CM_CLKEN_PLL); - - /*MPU core clock = Core /2 = 300 */ - __raw_writel(MPU_DIV, CM_CLKSEL_MPU); - - /*DSPif=200, DSPif=100, IVA=200 */ - __raw_writel(DSP_DIV, CM_CLKSEL_DSP); - - /*GFX clock (L3/2) 50MHz */ - __raw_writel(GFX_DIV, CM_CLKSEL_GFX); - - /*L3=100, L4=100, DisplaySS=50 Vlync=96Mhz,ssi=100, usb=50 */ - __raw_writel(BUS_DIV, CM_CLKSEL1_CORE); - - /*12MHz apll src, 12/(1+1)*50=300 */ - __raw_writel(DPLL_VAL, CM_CLKSEL1_PLL); - - /*Valid the configuration */ - __raw_writel(0x00000001, PRCM_CLKCFG_CTRL); - delay(1000); - - /*Enable DPLL=300, 96MHz APLL locked. */ - __raw_writel(0x0000000F, CM_CLKEN_PLL); - delay(200000); - -#ifdef CFG_SDRAM_DDR - config_sdram_ddr(rev); -#elif defined(CFG_SDRAM_COMBO) - config_sdram_combo(rev); -#elif defined(CFG_SDRAM_SDR) - config_sdram_sdr(rev); -#elif defined(CFG_SDRAM_STACKED) - config_sdram_stacked(rev); -#else -#error SDRAM type not supported -#endif - - delay(20000); - peripheral_enable(); - return(0); -} - -/******************************************************* - * Routine: misc_init_r - * Description: Init ethernet (done here so udelay works) - ********************************************************/ -int misc_init_r (void) -{ - return(0); -} - -/**************************************** - * Routine: watchdog_init - * Description: Shut down watch dogs - *****************************************/ -static void watchdog_init(void) -{ -#define GP (BIT8|BIT9) - - /* There are 4 watch dogs. 1 secure, and 3 general purpose. - * I would expect that the ROM takes care of the secure one, - * but we will try also. Of the 3 GP ones, 1 can reset us - * directly, the other 2 only generate MPU interrupts. - */ - __raw_writel(WD_UNLOCK1 ,WD2_BASE+WSPR); - wait_for_command_complete(WD2_BASE); - __raw_writel(WD_UNLOCK2 ,WD2_BASE+WSPR); - -#if MPU_WD_CLOCKED /* value 0x10 stick on aptix, BIT4 polarity seems oppsite*/ - __raw_writel(WD_UNLOCK1 ,WD3_BASE+WSPR); - wait_for_command_complete(WD3_BASE); - __raw_writel(WD_UNLOCK2 ,WD3_BASE+WSPR); - - __raw_writel(WD_UNLOCK1 ,WD4_BASE+WSPR); - wait_for_command_complete(WD4_BASE); - __raw_writel(WD_UNLOCK2 ,WD4_BASE+WSPR); -#endif - -} - -/****************************************************** - * Routine: wait_for_command_complete - * Description: Wait for posting to finish on watchdog - ******************************************************/ -static void wait_for_command_complete(unsigned int wd_base) -{ - int pending = 1; - do { - pending = __raw_readl(wd_base+WWPS); - } while (pending); -} - - -/********************************************** - * Routine: dram_init - * Description: sets uboots idea of sdram size - **********************************************/ -int dram_init (void) -{ - return 0; -} - -/***************************************************************** - * Routine: peripheral_enable - * Description: Enable the clks & power for perifs (GPT2, UART1,...) - ******************************************************************/ -static void peripheral_enable(void) -{ - unsigned int v, if_clks=0, func_clks=0; - - /* Enable GP2 timer.*/ - if_clks |= BIT4; - func_clks |= BIT4; - v = __raw_readl(CM_CLKSEL2_CORE) | 0x4; /* Sys_clk input OMAP2420_GPT2 */ - __raw_writel(v, CM_CLKSEL2_CORE); - __raw_writel(0x1, CM_CLKSEL_WKUP); - -#ifdef CFG_NS16550 - /* Enable UART1 clock */ - func_clks |= BIT21; - if_clks |= BIT21; -#endif - v = __raw_readl(CM_ICLKEN1_CORE) | if_clks; /* Interface clocks on */ - __raw_writel(v,CM_ICLKEN1_CORE ); - v = __raw_readl(CM_FCLKEN1_CORE) | func_clks; /* Functional Clocks on */ - __raw_writel(v, CM_FCLKEN1_CORE); - delay(1000); - -#ifndef KERNEL_UPDATED - { -#define V1 0xffffffff -#define V2 0x00000007 - - __raw_writel(V1, CM_FCLKEN1_CORE); - __raw_writel(V2, CM_FCLKEN2_CORE); - __raw_writel(V1, CM_ICLKEN1_CORE); - __raw_writel(V1, CM_ICLKEN2_CORE); - } -#endif - -} - -/* Pin Muxing registers used for UART1 */ -#define CONTROL_PADCONF_UART1_CTS ((volatile unsigned char *)0x480000C5) -#define CONTROL_PADCONF_UART1_RTS ((volatile unsigned char *)0x480000C6) -#define CONTROL_PADCONF_UART1_TX ((volatile unsigned char *)0x480000C7) -#define CONTROL_PADCONF_UART1_RX ((volatile unsigned char *)0x480000C8) -/**************************************** - * Routine: muxSetupUART1 (ostboot) - * Description: Set up uart1 muxing - *****************************************/ -static void muxSetupUART1(void) -{ - volatile unsigned char *MuxConfigReg; - - /* UART1_CTS pin configuration, PIN = D21 */ - MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_UART1_CTS; - *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ - - /* UART1_RTS pin configuration, PIN = H21 */ - MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_UART1_RTS; - *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ - - /* UART1_TX pin configuration, PIN = L20 */ - MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_UART1_TX; - *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ - - /* UART1_RX pin configuration, PIN = T21 */ - MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_UART1_RX; - *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ -} - -int nand_init(void) -{ - u32 rev; - - rev = get_cpu_rev(); - - - /* GPMC pin muxing */ - (*(volatile int*)0x48000070) &= 0x000000FF; - (*(volatile int*)0x48000074) &= 0x00000000; - (*(volatile int*)0x48000078) &= 0x00000000; - (*(volatile int*)0x4800007C) &= 0x00000000; - (*(volatile int*)0x48000080) &= 0xFF000000; - - /* GPMC_IO_DIR */ - (*(volatile int*)0x4800008C) = 0x19000000; - - /* GPMC Configuration */ - (*(volatile int*)0x6800A010) = 0x0000000A; - while (((*(volatile int *)0x6800A014) & 0x00000001) == 0); - - (*(volatile int*)0x6800A050) = 0x00000001; - (*(volatile int*)0x6800A060) = 0x00001800; - (*(volatile int*)0x6800A064) = 0x00141400; - (*(volatile int*)0x6800A068) = 0x00141400; - (*(volatile int*)0x6800A06C) = 0x0F010F01; - (*(volatile int*)0x6800A070) = 0x010C1414; - (*(volatile int*)0x6800A074) = 0x00000A80; - (*(volatile int*)0x6800A078) = 0x00000C44; //base 0x04000000 - - (*(volatile int*)0x6800A0A8) = 0x00000000; - delay(1000); -#ifdef CFG_SDRAM_STACKED - (*(volatile int*)0x6800A090) = 0x00011000; -#else - (*(volatile int*)0x6800A090) = 0x00011200; -#endif - (*(volatile int*)0x6800A094) = 0x001f1f00; - (*(volatile int*)0x6800A098) = 0x00080802; - (*(volatile int*)0x6800A09C) = 0x1C091C09; - (*(volatile int*)0x6800A0A0) = 0x031A1F1F; - (*(volatile int*)0x6800A0A4) = 0x000003C2; - (*(volatile int*)0x6800A0A8) = 0x00000F48; - - if (rev != CPU_2420_2422_ES1) - (*(volatile int*)0x6800A040) = 0x1FF0; // es2.x - - if (nand_chip()){ - printf("Unsupported Chip!\n"); - return 1; - } - return 0; -} - -/****************************************** - * get_cpu_rev(void) - extract version info - ******************************************/ -u32 get_cpu_rev(void) -{ - u32 v; - v = __raw_readl(TAP_IDCODE_REG); - v = v >> 28; - return(v+1); /* currently 2422 and 2420 match up */ -} - -/* optionally do something like blinking LED */ -void board_hang (void) -{} - - - diff --git a/x-loader/board/omap2420h4/platform.S b/x-loader/board/omap2420h4/platform.S deleted file mode 100644 index 5cc37e5..0000000 --- a/x-loader/board/omap2420h4/platform.S +++ /dev/null @@ -1,218 +0,0 @@ -/* - * Board specific setup info - * - * (C) Copyright 2004 - * Texas Instruments, <www.ti.com> - * Richard Woodruff <r-woodruff2@ti.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <config.h> -#include <asm/arch/omap2420.h> -#include <asm/arch/mem.h> -#include <asm/arch/clocks.h> - -_TEXT_BASE: - .word TEXT_BASE /* sdram load addr from config.mk */ - -#ifdef CONFIG_PARTIAL_SRAM - -/************************************************************************** - * cpy_clk_code: relocates clock code into SRAM where its safer to execute - * R1 = SRAM destination address. - *************************************************************************/ -.global cpy_clk_code - cpy_clk_code: - /* Copy DPLL code into SRAM */ - adr r0, go_to_speed /* get addr of clock setting code */ - mov r2, #384 /* r2 size to copy (div by 32 bytes) */ - mov r1, r1 /* r1 <- dest address (passed in) */ - add r2, r2, r0 /* r2 <- source end address */ -next2: - ldmia r0!, {r3-r10} /* copy from source address [r0] */ - stmia r1!, {r3-r10} /* copy to target address [r1] */ - cmp r0, r2 /* until source end address [r2] */ - bne next2 - mov pc, lr /* back to caller */ - -/* **************************************************************************** - * go_to_speed: -Moves to bypass, -Commits clock dividers, -puts dpll at speed - * -executed from SRAM. - * R0 = PRCM_CLKCFG_CTRL - addr of valid reg - * R1 = CM_CLKEN_PLL - addr dpll ctlr reg - * R2 = dpll value - * R3 = CM_IDLEST_CKGEN - addr dpll lock wait - ******************************************************************************/ -.global go_to_speed - go_to_speed: - sub sp, sp, #0x4 /* get some stack space */ - str r4, [sp] /* save r4's value */ - - /* move into fast relock bypass */ - ldr r8, pll_ctl_add - mov r4, #0x2 - str r4, [r8] - ldr r4, pll_stat -block: - ldr r8, [r4] /* wait for bypass to take effect */ - and r8, r8, #0x3 - cmp r8, #0x1 - bne block - - /* set new dpll dividers _after_ in bypass */ - ldr r4, pll_div_add - ldr r8, pll_div_val - str r8, [r4] - - /* now prepare GPMC (flash) for new dpll speed */ - /* flash needs to be stable when we jump back to it */ - ldr r4, cfg3_0_addr - ldr r8, cfg3_0_val - str r8, [r4] - ldr r4, cfg4_0_addr - ldr r8, cfg4_0_val - str r8, [r4] - ldr r4, cfg1_0_addr - ldr r8, [r4] - orr r8, r8, #0x3 /* up gpmc divider */ - str r8, [r4] - - /* setup to 2x loop though code. The first loop pre-loads the - * icache, the 2nd commits the prcm config, and locks the dpll - */ - mov r4, #0x1000 /* spin spin spin */ - mov r8, #0x4 /* first pass condition & set registers */ - cmp r8, #0x4 -2: - ldrne r8, [r3] /* DPLL lock check */ - and r8, r8, #0x7 - cmp r8, #0x2 - beq 4f -3: - subeq r8, r8, #0x1 - streq r8, [r0] /* commit dividers (2nd time) */ - nop -lloop1: - sub r4, r4, #0x1 /* Loop currently necessary else bad jumps */ - nop - cmp r4, #0x0 - bne lloop1 - mov r4, #0x40000 - cmp r8, #0x1 - nop - streq r2, [r1] /* lock dpll (2nd time) */ - nop -lloop2: - sub r4, r4, #0x1 /* loop currently necessary else bad jumps */ - nop - cmp r4, #0x0 - bne lloop2 - mov r4, #0x40000 - cmp r8, #0x1 - nop - ldreq r8, [r3] /* get lock condition for dpll */ - cmp r8, #0x4 /* first time though? */ - bne 2b - moveq r8, #0x2 /* set to dpll check condition. */ - beq 3b /* if condition not true branch */ -4: - ldr r4, [sp] - add sp, sp, #0x4 /* return stack space */ - mov pc, lr /* back to caller, locked */ - -_go_to_speed: .word go_to_speed - -/* these constants need to be close for PIC code */ -cfg3_0_addr: - .word GPMC_CONFIG3_0 -cfg3_0_val: - .word SMNAND_GPMC_CONFIG3 -cfg4_0_addr: - .word GPMC_CONFIG4_0 -cfg4_0_val: - .word SMNAND_GPMC_CONFIG4 -cfg1_0_addr: - .word GPMC_CONFIG1_0 -pll_ctl_add: - .word CM_CLKEN_PLL -pll_stat: - .word CM_IDLEST_CKGEN -pll_div_add: - .word CM_CLKSEL1_PLL -pll_div_val: - .word DPLL_VAL /* DPLL setting (300MHz default) */ -#endif - -.globl platformsetup -platformsetup: - mov r3, r0 /* save skip information */ -#ifdef CONFIG_APTIX - ldr r0, REG_SDRC_MCFG_0 - ldr r1, VAL_SDRC_MCFG_0 - str r1, [r0] - ldr r0, REG_SDRC_MR_0 - ldr r1, VAL_SDRC_MR_0 - str r1, [r0] - /* a ddr needs emr1 set here */ - ldr r0, REG_SDRC_SHARING - ldr r1, VAL_SDRC_SHARING - str r1, [r0] - ldr r0, REG_SDRC_RFR_CTRL_0 - ldr r1, VAL_SDRC_RFR_CTRL_0 - str r1, [r0] - - /* little delay after init */ - mov r2, #0x1800 -1: - subs r2, r2, #0x1 - bne 1b -#endif -#ifdef CONFIG_PARTIAL_SRAM - ldr sp, SRAM_STACK - str ip, [sp] /* stash old link register */ - mov ip, lr /* save link reg across call */ - mov r0, r3 /* pass skip info to s_init */ - bl s_init /* go setup pll,mux,memory */ - ldr ip, [sp] /* restore save ip */ - mov lr, ip /* restore link reg */ -#endif - - /* map interrupt controller */ - ldr r0, VAL_INTH_SETUP - mcr p15, 0, r0, c15, c2, 4 - - /* back to arch calling code */ - mov pc, lr - - /* the literal pools origin */ - .ltorg - -REG_CONTROL_STATUS: - .word CONTROL_STATUS -VAL_INTH_SETUP: - .word PERIFERAL_PORT_BASE -SRAM_STACK: - .word LOW_LEVEL_SRAM_STACK - - - - - - diff --git a/x-loader/board/omap2420h4/x-load.lds b/x-loader/board/omap2420h4/x-load.lds deleted file mode 100644 index f664ca7..0000000 --- a/x-loader/board/omap2420h4/x-load.lds +++ /dev/null @@ -1,54 +0,0 @@ -/* - * January 2004 - Changed to support H4 device - * Copyright (c) 2004 Texas Instruments - * - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, <gj@denx.de> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN(4); - .text : - { - cpu/arm1136/start.o (.text) - *(.text) - } - - . = ALIGN(4); - .rodata : { *(.rodata) } - - . = ALIGN(4); - .data : { *(.data) } - - . = ALIGN(4); - .got : { *(.got) } - - . = ALIGN(4); - __bss_start = .; - .bss : { *(.bss) } - _end = .; -} diff --git a/x-loader/board/omap2430sdp/Makefile b/x-loader/board/omap2430sdp/Makefile deleted file mode 100644 index b6c984c..0000000 --- a/x-loader/board/omap2430sdp/Makefile +++ /dev/null @@ -1,51 +0,0 @@ -# -# (C) Copyright 2000, 2001, 2002 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).a - -COBJS := omap2430sdp.o -SOBJS := platform.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) $(SOBJS) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak $(obj).depend - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/x-loader/board/omap2430sdp/config.mk b/x-loader/board/omap2430sdp/config.mk deleted file mode 100644 index 7bc5078..0000000 --- a/x-loader/board/omap2430sdp/config.mk +++ /dev/null @@ -1,28 +0,0 @@ -# -# (C) Copyright 2004 -# Texas Instruments, <www.ti.com> -# -# TI H4 board with OMAP2420 (ARM1136) cpu -# see http://www.ti.com/ for more information on Texas Instruments -# -# H4 has 1 bank of 32MB or 64MB mDDR-SDRAM on CS0 -# H4 has 1 bank of 32MB or 00MB mDDR-SDRAM on CS1 -# Physical Address: -# 8000'0000 (bank0) -# A000/0000 (bank1) ES2 will be configurable -# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000 -# (mem base + reserved) - -# 2430 h4 has same mem configuration as h4. - -# For use with external or internal boots. -# CONFIG_PARTIAL_SRAM must be defined to use this. -TEXT_BASE = 0x80e80000 - -# Used with full SRAM boot. -# This is either with a GP system or a signed boot image. -# easiest, and safest way to go if you can. -# Comment out //CONFIG_PARTIAL_SRAM for this one. -# -#TEXT_BASE = 0x40280000 - diff --git a/x-loader/board/omap2430sdp/omap2430sdp.c b/x-loader/board/omap2430sdp/omap2430sdp.c deleted file mode 100644 index f2a7b42..0000000 --- a/x-loader/board/omap2430sdp/omap2430sdp.c +++ /dev/null @@ -1,746 +0,0 @@ -/* - * (C) Copyright 2004-2005 - * Texas Instruments, <www.ti.com> - * Jian Zhang <jzhang@ti.com> - * Richard Woodruff <r-woodruff2@ti.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#include <common.h> -#include <asm/arch/omap2430.h> -#include <asm/arch/bits.h> -#include <asm/arch/mem.h> -#include <asm/arch/sys_info.h> -#include <asm/arch/clocks.h> - -static void wait_for_command_complete(unsigned int wd_base); -static void watchdog_init(void); -static void peripheral_enable(void); -static void muxSetupAll(void); -static u32 get_cpu_rev(void); -static u32 get_device_type(void); -static void prcm_init(void); - - -/******************************************************* - * Routine: delay - * Description: spinning delay to use before udelay works - ******************************************************/ -static inline void delay (unsigned long loops) -{ - __asm__ volatile ("1:\n" - "subs %0, %1, #1\n" - "bne 1b":"=r" (loops):"0" (loops)); -} - -/***************************************** - * Routine: board_init - * Description: Early hardware init. - *****************************************/ -int board_init (void) -{ - return 0; -} - -/****************************************** - * get_cpu_rev(void) - extract version info - ******************************************/ -u32 get_cpu_rev(void) -{ - u32 v; - v = __raw_readl(TAP_IDCODE_REG); - v = v >> 28; - return(v+1); /* currently 2422 and 2420 match up */ -} - -/************************************************************* - * get_device_type(): tell if GP/HS/EMU/TST - *************************************************************/ -u32 get_device_type(void) -{ - int mode; - mode = __raw_readl(CONTROL_STATUS) & (DEVICE_MASK); - return(mode >>= 8); -} - -/************************************************************* - * Helper function to wait for the status of a register - *************************************************************/ -u32 wait_on_value(u32 read_bit_mask, u32 match_value, u32 read_addr, u32 bound) -{ - u32 i = 0, val; - do { - ++i; - val = __raw_readl(read_addr) & read_bit_mask; - if (val == match_value) - return(1); - if (i==bound) - return(0); - } while (1); -} - -/************************************************************* - * Support for multiple type of memory types - *************************************************************/ -#ifdef CFG_SDRAM_DDR -void -config_sdram_ddr(u32 rev) -{ - /* ball D11, mode 0 */ - __raw_writeb(0x08, 0x48000032); - - /* SDRC_CS0 Configuration */ - __raw_writel(H4_2420_SDRC_MDCFG_0_DDR, SDRC_MCFG_0); - __raw_writel(H4_2420_SDRC_SHARING, SDRC_SHARING); - - __raw_writel(H4_242x_SDRC_RFR_CTRL_ES1, SDRC_RFR_CTRL); - __raw_writel(H4_242x_SDRC_ACTIM_CTRLA_0_ES1, SDRC_ACTIM_CTRLA_0); - __raw_writel(H4_242x_SDRC_ACTIM_CTRLB_0_ES1, SDRC_ACTIM_CTRLB_0); - - /* Manual Command sequence */ - __raw_writel(CMD_NOP, SDRC_MANUAL_0); - __raw_writel(CMD_PRECHARGE, SDRC_MANUAL_0); - __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0); - __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0); - - - /* - * CS0 SDRC Mode Register - * Burst length = 4 - DDR memory - * Serial mode - * CAS latency = 3 - */ - __raw_writel(0x00000032, SDRC_MR_0); - - /* SDRC DLLA control register */ - /* Delay is 90 degrees */ - /* Enable DLL, Load counter with 115 (middle of range) */ - __raw_writel(0x00000008, SDRC_DLLA_CTRL); // ES2.x - /* Enable DLL, Load counter with 128 (middle of range) */ - __raw_writel(0x00000008, SDRC_DLLB_CTRL); // ES2.x - -} -#endif // CFG_SDRAM_DDR - -#ifdef CFG_SDRAM_COMBO -void -config_sdram_combo(u32 rev) -{ - - u32 dllctrl=0; - - /* ball C12, mode 0 */ - __raw_writeb(0x00, 0x480000a1); - /* ball D11, mode 0 */ - __raw_writeb(0x00, 0x48000032); - /* ball B13, mode 0 - for CKE1 (not needed rkw for combo) */ - __raw_writeb(0x00, 0x480000a3); - - /*configure sdrc 32 bit for COMBO ddr sdram. Issue soft reset */ - __raw_writel(0x00000012, SDRC_SYSCONFIG); - wait_on_value(BIT0, BIT0, SDRC_STATUS, 12000000); /* wait till reset done set */ - __raw_writel(0x00000000, SDRC_SYSCONFIG); - - /* SDRCTriState: no Tris */ - /* CS0MuxCfg: 000 (32-bit SDRAM on D31..0) */ - if (rev == CPU_2420_2422_ES1) - __raw_writel(H4_2422_SDRC_SHARING, SDRC_SHARING); - else - __raw_writel(H4_2420_SDRC_SHARING, SDRC_SHARING); - - - /* CS0 SDRC Memory Configuration, */ - /* DDR-SDRAM, External SDRAM is x32bit, */ - /* Configure to MUX9: 1x8Mbx32 */ - __raw_writel(H4_2420_COMBO_MDCFG_0_DDR, SDRC_MCFG_0); - __raw_writel(H4_2420_SDRC_ACTIM_CTRLA_0, SDRC_ACTIM_CTRLA_0); - __raw_writel(H4_2420_SDRC_ACTIM_CTRLB_0, SDRC_ACTIM_CTRLB_0); - - /* This is reqd only for ES1 */ - if (rev == CPU_242X_ES1) - __raw_writel(H4_242x_SDRC_RFR_CTRL_ES1, SDRC_RFR_CTRL); - - /* Manual Command sequence */ - __raw_writel(CMD_NOP, SDRC_MANUAL_0); - delay(5000); - __raw_writel(CMD_PRECHARGE, SDRC_MANUAL_0); - __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0); - __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0); - - /* CS0 SDRC Mode Register */ - /* Burst length = 4 - DDR memory */ - /* Serial mode */ - /* CAS latency = 3 */ - __raw_writel(H4_2422_SDRC_MR_0_DDR, SDRC_MR_0); - - /* CS1 SDRC Memory Configuration, */ - /* DDR-SDRAM, External SDRAM is x32bit, */ - /* Configure to MUX9: 1x8Mbx32 */ - __raw_writel(H4_2420_COMBO_MDCFG_0_DDR, SDRC_MCFG_1); - __raw_writel(H4_242X_SDRC_ACTIM_CTRLA_0_100MHz, SDRC_ACTIM_CTRLA_1); - __raw_writel(H4_2420_SDRC_ACTIM_CTRLB_0, SDRC_ACTIM_CTRLB_1); - /* This is reqd only for ES1 */ - if (rev == CPU_242X_ES1) - __raw_writel(H4_242x_SDRC_RFR_CTRL_ES1, 0x680090d4); - - /* Manual Command sequence */ - __raw_writel(CMD_NOP, 0x680090d8); - __raw_writel(CMD_PRECHARGE, 0x680090d8); - __raw_writel(CMD_AUTOREFRESH, 0x680090d8); - __raw_writel(CMD_AUTOREFRESH, 0x680090d8); - - /* CS1 SDRC Mode Register */ - /* Burst length = 4 - DDR memory */ - /* Serial mode */ - /* CAS latency = 3 */ - __raw_writel(H4_2422_SDRC_MR_0_DDR, 0x680090b4); - - /* SDRC DLLA control register */ - /* Delay is 90 degrees */ - - if (rev == CPU_242X_ES1) - dllctrl = (BIT0|BIT3); - else - dllctrl = BIT0; - - if (rev == CPU_2420_2422_ES1) { - /* Enable DLL, Load counter with 115 (middle of range) */ - __raw_writel(0x00007306, SDRC_DLLA_CTRL); - __raw_writel(0x00007302, SDRC_DLLA_CTRL); - /* Enable DLL, Load counter with 128 (middle of range) */ - __raw_writel(0x00007306, SDRC_DLLB_CTRL); /* load ctr value */ - __raw_writel(0x00007302, SDRC_DLLB_CTRL); /* lock and go */ - } - else { - /* Enable DLL, Load counter with 115 (middle of range) */ - __raw_writel(H4_2420_SDRC_DLLAB_CTRL, SDRC_DLLA_CTRL); // ES2.x - __raw_writel(H4_2420_SDRC_DLLAB_CTRL & ~(LOADDLL|dllctrl), SDRC_DLLA_CTRL); // ES2.x - // __raw_writel(0x00009808, SDRC_DLLA_CTRL); // ES2.x - /* Enable DLL, Load counter with 128 (middle of range) */ - __raw_writel(H4_2420_SDRC_DLLAB_CTRL, SDRC_DLLB_CTRL); // ES2.x ? - __raw_writel(H4_2420_SDRC_DLLAB_CTRL & ~(LOADDLL|dllctrl), SDRC_DLLB_CTRL); // ES2.x - //__raw_writel(0x00009808, SDRC_DLLB_CTRL); // ES2.x - } -} - -#endif // CFG_SDRAM_COMBO - -#ifdef CFG_2430SDRAM_DDR -void -config_2430sdram_ddr(u32 rev) -{ - u32 dllstat, dllctrl; - - __raw_writel(0x00000012, SDRC_SYSCONFIG); - wait_on_value(BIT0, BIT0, SDRC_STATUS, 12000000); /* wait till reset done set */ - __raw_writel(0x00000000, SDRC_SYSCONFIG); - - /* Chip-level shared interface management */ - /* SDRCTriState: no Tris */ - /* CS0MuxCfg: 000 (32-bit SDRAM on D31..0) */ - /* CS1MuxCfg: 000 (32-bit SDRAM on D31..0) */ - __raw_writel(H4_2420_SDRC_SHARING, SDRC_SHARING); - - /* CS0 SDRC Memory Configuration, */ - /* DDR-SDRAM, External SDRAM is x32bit, */ - /* Configure to MUX14: 32Mbx32 */ - __raw_writel(SDP_2430_SDRC_MDCFG_0_DDR, SDRC_MCFG_0); - __raw_writel(SDP_2430_SDRC_ACTIM_CTRLA_0, SDRC_ACTIM_CTRLA_0); - __raw_writel(H4_2420_SDRC_ACTIM_CTRLB_0, SDRC_ACTIM_CTRLB_0); - - __raw_writel(H4_2420_SDRC_RFR_CTRL, SDRC_RFR_CTRL); - - /* Manual Command sequence */ - __raw_writel(CMD_NOP, SDRC_MANUAL_0); - delay(5000); - __raw_writel(CMD_PRECHARGE, SDRC_MANUAL_0); - __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0); - __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0); - - /* CS0 SDRC Mode Register */ - /* Burst length = 2 - SDR memory */ - /* Serial mode */ - /* CAS latency = 3 */ - __raw_writel(H4_2420_SDRC_MR_0_DDR, SDRC_MR_0); - - /* Set up SDRC DLL values for 2430 DDR */ - dllctrl = (SDP_2430_SDRC_DLLAB_CTRL & ~BIT2); /* set target ctrl val */ - __raw_writel(dllctrl, SDRC_DLLA_CTRL); /* set lock mode */ - __raw_writel(dllctrl, SDRC_DLLB_CTRL); /* set lock mode */ - delay(0x1000); /* time to track to center */ - dllstat = __raw_readl(SDRC_DLLA_STATUS) & 0xFF00; /* get status */ - dllctrl = (dllctrl & 0x00FF) | dllstat | BIT2; /* build unlock value */ - __raw_writel(dllctrl, SDRC_DLLA_CTRL); /* set unlock mode */ - __raw_writel(dllctrl, SDRC_DLLB_CTRL); /* set unlock mode */ -} -#endif // CFG_2430SDRAM_DDR - -#ifdef CFG_SDRAM_STACKED -void -config_sdram_stacked(u32 rev) -{ - - /* Pin Muxing for SDRC */ - __raw_writeb(0x00, 0x480000a1); /* mux mode 0 (CS1) */ - __raw_writeb(0x00, 0x480000a3); /* mux mode 0 (CKE1) */ - __raw_writeb(0x00, 0x48000032); /* connect sdrc_a12 */ - __raw_writeb(0x00, 0x48000031); /* connect sdrc_a13 */ - - /* configure sdrc 32 bit for COMBO ddr sdram */ - __raw_writel(0x00000010, SDRC_SYSCONFIG); /* no idle ack and RESET enable */ - delay(200000); - __raw_writel(0x00000010, SDRC_SYSCONFIG); /* smart idle mode */ - - /* SDRC_SHARING */ - /* U-boot is writing 0x00000100 though (H4_2420_SDRC_SHARING ) */ - //__raw_writel(H4_2420_SDRC_SHARING, SDRC_SHARING); - - __raw_writel(0x00004900, SDRC_SHARING); - - /* SDRC_CS0 Configuration */ - /* None for ES2.1 */ - - /* SDRC_CS1 Configuration */ - __raw_writel(0x00000000, SDRC_CS_CFG); /* Remap CS1 to 0x80000000 */ - - /* Disable power down of CKE */ - __raw_writel(0x00000085, SDRC_POWER); - - __raw_writel(0x01A02019, SDRC_MCFG_1); /* SDRC_MCFG1 */ - __raw_writel(0x0003DD03, SDRC_RFR_CTRL1); /* SDRC_RFR_CTRL1 */ - __raw_writel(0x92DDC485, SDRC_ACTIM_CTRLA_1); /* SDRC_ACTIM_CTRLA0 */ - __raw_writel(0x00000014, SDRC_ACTIM_CTRLB_1); /* SDRC_ACTIM_CTRLB0 */ - - /*Manual Command sequence */ - __raw_writel(0x00000000, 0x680090D8); - __raw_writel(0x00000001, 0x680090D8); - __raw_writel(0x00000002, 0x680090D8); - __raw_writel(0x00000002, 0x680090D8); - - /* CS0 SDRC Mode Register */ - /* Burst length = 4 - DDR memory */ - /* Serial mode */ - /* CAS latency = 3 */ - __raw_writel(0x00000032, 0x680090B4); - __raw_writel(0x00000020, 0x680090BC); /* weak-strength driver */ - - /* SDRC DLLA control register */ - /* Delay is 90 degrees */ - if (rev == CPU_2420_2422_ES1) { - /* Enable DLL, Load counter with 115 (middle of range) */ - __raw_writel(0x00007302, SDRC_DLLA_CTRL); - /* Enable DLL, Load counter with 128 (middle of range) */ - __raw_writel(0x00007302, SDRC_DLLB_CTRL); - } - else { - /* Enable DLL, Load counter with 115 (middle of range) */ - __raw_writel(0x00003108, SDRC_DLLA_CTRL); // ES2.x - /* Enable DLL, Load counter with 128 (middle of range) */ - __raw_writel(0x00003108, SDRC_DLLB_CTRL); // ES2.x - } -} -#endif // CFG_SDRAM_STACKED - -/************************************************************* - * get_sys_clk_speed - determine reference oscillator speed - * based on known 32kHz clock and gptimer. - *************************************************************/ -u32 get_osc_clk_speed(u32 *shift) -{ -#define GPT_EN ((0<<2)|BIT1|BIT0) /* enable sys_clk NO-prescale /1 */ -#define GPT_CTR OMAP24XX_GPT2+TCRR /* read counter address */ - u32 start, cstart, cend, cdiff, val; - unsigned int v, if_clks=0, func_clks=0 ; - - - - if(__raw_readl(PRCM_CLKSRC_CTRL) & BIT7){ /* if currently /2 */ - *shift = 1; - }else{ - *shift = 0; - } - - /* enable timer2 */ - val = __raw_readl(CM_CLKSEL2_CORE) | 0x4; /* mask for sys_clk use */ - __raw_writel(val, CM_CLKSEL2_CORE); /* timer2 source to sys_clk */ - __raw_writel(BIT4, CM_ICLKEN1_CORE); /* timer2 interface clock on */ - __raw_writel(BIT4, CM_FCLKEN1_CORE); /* timer2 function clock on */ - /* Enable GP2 timer.*/ - if_clks |= BIT4; - func_clks |= BIT4; - v = __raw_readl(CM_ICLKEN1_CORE) | if_clks; /* Interface clocks on */ - __raw_writel(v,CM_ICLKEN1_CORE ); - v = __raw_readl(CM_FCLKEN1_CORE) | func_clks; /* Functional Clocks on */ - __raw_writel(v, CM_FCLKEN1_CORE); - __raw_writel(0, OMAP24XX_GPT2+TLDR); /* start counting at 0 */ - __raw_writel(GPT_EN, OMAP24XX_GPT2+TCLR); /* enable clock */ - /* enable 32kHz source */ /* enabled out of reset */ - /* determine sys_clk via gauging */ - start = 20 + __raw_readl(S32K_CR); /* start time in 20 cycles*/ - while(__raw_readl(S32K_CR) < start); /* dead loop till start time */ - cstart = __raw_readl(GPT_CTR); /* get start sys_clk count */ - while(__raw_readl(S32K_CR) < (start+20)); /* wait for 40 cycles */ - cend = __raw_readl(GPT_CTR); /* get end sys_clk count */ - cdiff = cend - cstart; /* get elapsed ticks */ - /* based on number of ticks assign speed */ - if(cdiff > (19000 >> *shift)) - return(S38_4M); - else if (cdiff > (15200 >> *shift)) - return(S26M); - else if (cdiff > (13000 >> *shift)) - return(S24M); - else if (cdiff > (9000 >> *shift)) - return(S19_2M); - else if (cdiff > (7600 >> *shift)) - return(S13M); - else - return(S12M); -} - -/********************************************************************************* - * prcm_init() - inits clocks for PRCM as defined in clocks.h (config II default). - * -- called from SRAM - *********************************************************************************/ -void -prcm_init() -{ - u32 div, speed, val, div_by_2; - - val = __raw_readl(PRCM_CLKSRC_CTRL) & ~(BIT1 | BIT0); -#if defined(OMAP2430_SQUARE_CLOCK_INPUT) - __raw_writel(val, PRCM_CLKSRC_CTRL); -#else - __raw_writel((val | BIT0), PRCM_CLKSRC_CTRL); -#endif - speed = get_osc_clk_speed(&div_by_2); - if((speed > S19_2M) && (!div_by_2)){ /* if fast && /2 off, enable it */ - val = ~(BIT6|BIT7) & __raw_readl(PRCM_CLKSRC_CTRL); - val |= (0x2 << 6); /* divide by 2 if (24,26,38.4) -> (12/13/19.2) */ - __raw_writel(val, PRCM_CLKSRC_CTRL); - } - - __raw_writel(0, CM_FCLKEN1_CORE); /* stop all clocks to reduce ringing */ - __raw_writel(0, CM_FCLKEN2_CORE); /* may not be necessary */ - __raw_writel(0, CM_ICLKEN1_CORE); - __raw_writel(0, CM_ICLKEN2_CORE); - - /*DPLL into low power bypass (others off) */ - __raw_writel(0x00000001, CM_CLKEN_PLL); - - __raw_writel(DPLL_OUT, CM_CLKSEL2_PLL); /* set DPLL out */ - __raw_writel(MPU_DIV, CM_CLKSEL_MPU); /* set MPU divider */ - __raw_writel(DSP_DIV, CM_CLKSEL_DSP); /* set dsp and iva dividers */ - __raw_writel(GFX_DIV, CM_CLKSEL_GFX); /* set gfx dividers */ - __raw_writel(MDM_DIV, CM_CLKSEL_MDM); /* set mdm dividers */ - - div = BUS_DIV; - __raw_writel(div, CM_CLKSEL1_CORE);/* set L3/L4/USB/Display/SSi dividers */ - delay(1000); - - /*13MHz apll src, PRCM 'x' DPLL rate */ - __raw_writel(DPLL_VAL, CM_CLKSEL1_PLL); - - /*Valid the configuration */ - __raw_writel(0x00000001, PRCM_CLKCFG_CTRL); - delay(1000); - - /* set up APLLS_CLKIN per crystal */ - if (speed > S19_2M) - speed >>= 1; /* if fast shift to /2 range */ - val = (0x2 << 23); /* default to 13Mhz for 2430c */ - if (speed == S12M) - val = (0x3 << 23); - else if (speed == S19_2M) - val = (0x0 << 23); - val |= (~(BIT23|BIT24|BIT25) & __raw_readl(CM_CLKSEL1_PLL)); - __raw_writel(val, CM_CLKSEL1_PLL); - - __raw_writel(DPLL_LOCK|APLL_LOCK, CM_CLKEN_PLL); /* enable apll */ - wait_on_value(BIT8, BIT8, CM_IDLEST_CKGEN, LDELAY);/* wait for apll lock */ - - delay(200000); -} - -void SEC_generic(void) -{ -/* Permission values for registers -Full fledged permissions to all */ -#define UNLOCK_1 0xFFFFFFFF -#define UNLOCK_2 0x00000000 -#define UNLOCK_3 0x0000FFFF - /* Protection Module Register Target APE (PM_RT)*/ - __raw_writel(UNLOCK_1, PM_RT_APE_BASE_ADDR_ARM + 0x68); /* REQ_INFO_PERMISSION_1 L*/ - __raw_writel(UNLOCK_1, PM_RT_APE_BASE_ADDR_ARM + 0x50); /* READ_PERMISSION_0 L*/ - __raw_writel(UNLOCK_1, PM_RT_APE_BASE_ADDR_ARM + 0x58); /* WRITE_PERMISSION_0 L*/ - __raw_writel(UNLOCK_2, PM_RT_APE_BASE_ADDR_ARM + 0x60); /* ADDR_MATCH_1 L*/ - - - __raw_writel(UNLOCK_3, PM_GPMC_BASE_ADDR_ARM + 0x48); /* REQ_INFO_PERMISSION_0 L*/ - __raw_writel(UNLOCK_3, PM_GPMC_BASE_ADDR_ARM + 0x50); /* READ_PERMISSION_0 L*/ - __raw_writel(UNLOCK_3, PM_GPMC_BASE_ADDR_ARM + 0x58); /* WRITE_PERMISSION_0 L*/ - - __raw_writel(UNLOCK_3, PM_OCM_RAM_BASE_ADDR_ARM + 0x48); /* REQ_INFO_PERMISSION_0 L*/ - __raw_writel(UNLOCK_3, PM_OCM_RAM_BASE_ADDR_ARM + 0x50); /* READ_PERMISSION_0 L*/ - __raw_writel(UNLOCK_3, PM_OCM_RAM_BASE_ADDR_ARM + 0x58); /* WRITE_PERMISSION_0 L*/ - __raw_writel(UNLOCK_2, PM_OCM_RAM_BASE_ADDR_ARM + 0x80); /* ADDR_MATCH_2 L*/ - - /* IVA Changes */ - __raw_writel(UNLOCK_3, PM_IVA2_BASE_ADDR_ARM + 0x48); /* REQ_INFO_PERMISSION_0 L*/ - __raw_writel(UNLOCK_3, PM_IVA2_BASE_ADDR_ARM + 0x50); /* READ_PERMISSION_0 L*/ - __raw_writel(UNLOCK_3, PM_IVA2_BASE_ADDR_ARM + 0x58); /* WRITE_PERMISSION_0 L*/ -} - -/********************************************************** - * Routine: try_unlock_sram() - * Description: If chip is GP type, unlock the SRAM for general use. - ***********************************************************/ -void try_unlock_sram(void) -{ - int mode; - - /* if GP device unlock device SRAM for general use */ - mode = get_device_type(); - - if ((mode == GP_DEVICE) || (mode == HS_DEVICE) || (mode == EMU_DEVICE) - || (mode == TST_DEVICE)) { - /* Secure or Emulation device - HS/E/T */ - SEC_generic(); - } - return; -} - -/********************************************************** - * Routine: s_init - * Description: Does early system init of muxing and clocks. - * - Called at time when only stack is available. - **********************************************************/ - -int s_init(int skip) -{ - u32 rev; - - rev = get_cpu_rev(); - - watchdog_init(); - try_unlock_sram(); - muxSetupAll(); - delay(100); - prcm_init(); - -#ifdef CFG_SDRAM_DDR - config_sdram_ddr(rev); -#elif defined(CFG_SDRAM_COMBO) - config_sdram_combo(rev); -#elif defined(CFG_2430SDRAM_DDR) - config_2430sdram_ddr(rev); -#elif defined(CFG_SDRAM_STACKED) - config_sdram_stacked(rev); -#else -#error SDRAM type not supported -#endif - - delay(20000); - peripheral_enable(); - return(0); -} - -/******************************************************* - * Routine: misc_init_r - * Description: Init ethernet (done here so udelay works) - ********************************************************/ -int misc_init_r (void) -{ - return(0); -} - -/**************************************** - * Routine: watchdog_init - * Description: Shut down watch dogs - *****************************************/ -static void watchdog_init(void) -{ -#define GP (BIT8|BIT9) - - /* There are 4 watch dogs. 1 secure, and 3 general purpose. - * I would expect that the ROM takes care of the secure one, - * but we will try also. Of the 3 GP ones, 1 can reset us - * directly, the other 2 only generate MPU interrupts. - */ - __raw_writel(WD_UNLOCK1 ,WD2_BASE+WSPR); - wait_for_command_complete(WD2_BASE); - __raw_writel(WD_UNLOCK2 ,WD2_BASE+WSPR); - -} - -/****************************************************** - * Routine: wait_for_command_complete - * Description: Wait for posting to finish on watchdog - ******************************************************/ -static void wait_for_command_complete(unsigned int wd_base) -{ - int pending = 1; - do { - pending = __raw_readl(wd_base+WWPS); - } while (pending); -} - - -/********************************************** - * Routine: dram_init - * Description: sets uboots idea of sdram size - **********************************************/ -int dram_init (void) -{ - return 0; -} - -/***************************************************************** - * Routine: peripheral_enable - * Description: Enable the clks & power for perifs (GPT2, UART1,...) - ******************************************************************/ -static void peripheral_enable(void) -{ - unsigned int v, if_clks=0, if_clks2 = 0, func_clks=0, func_clks2 = 0; - - /* Enable GP2 timer.*/ - if_clks |= BIT4; - func_clks |= BIT4; - v = __raw_readl(CM_CLKSEL2_CORE) | 0x4; /* Sys_clk input OMAP24XX_GPT2 */ - __raw_writel(v, CM_CLKSEL2_CORE); - __raw_writel(0x1, CM_CLKSEL_WKUP); - -#ifdef CFG_NS16550 - /* Enable UART1 clock */ - func_clks |= BIT21; - if_clks |= BIT21; -#endif - v = __raw_readl(CM_ICLKEN1_CORE) | if_clks; /* Interface clocks on */ - __raw_writel(v,CM_ICLKEN1_CORE ); - v = __raw_readl(CM_ICLKEN2_CORE) | if_clks2; /* Interface clocks on */ - __raw_writel(v, CM_ICLKEN2_CORE); - v = __raw_readl(CM_FCLKEN1_CORE) | func_clks; /* Functional Clocks on */ - __raw_writel(v, CM_FCLKEN1_CORE); - v = __raw_readl(CM_FCLKEN2_CORE) | func_clks2; /* Functional Clocks on */ - __raw_writel(v, CM_FCLKEN2_CORE); - delay(1000); - -} - -/* Do pin muxing for all the devices used in X-Loader */ -#define MUX_VAL(OFFSET,VALUE)\ - __raw_writeb(VALUE, OMAP24XX_CTRL_BASE + OFFSET); -static void muxSetupAll(void) -{ - /* UART 1*/ - MUX_VAL(0x00B1, 0x1B) /* uart1_cts- EN, HI, 3, ->gpio_32 */ - MUX_VAL(0x00B2, 0x1B) /* uart1_rts- EN, HI, 3, ->gpio_8 */ - MUX_VAL(0x00B3, 0x1B) /* uart1_tx- EN, HI, 3, ->gpio_9 */ - MUX_VAL(0x00B4, 0x1B) /* uart1_rx- EN, HI, 3, ->gpio_10 */ - MUX_VAL(0x0107, 0x01) /* ssi1_dat_tx- Dis, 1, ->uart1_tx */ - MUX_VAL(0x0108, 0x01) /* ssi1_flag_tx- Dis, 1, ->uart1_rts */ - MUX_VAL(0x0109, 0x01) /* ssi1_rdy_tx- Dis, 1, ->uart1_cts */ - MUX_VAL(0x010A, 0x01) /* ssi1_dat_rx- Dis, 1, ->uart1_rx */ - - /* Mux settings for SDRC */ - MUX_VAL(0x0054, 0x1B) /* sdrc_a14 - EN, HI, 3, ->gpio_0 */ - MUX_VAL(0x0055, 0x1B) /* sdrc_a13 - EN, HI, 3, ->gpio_1 */ - MUX_VAL(0x0056, 0x00) /* sdrc_a12 - Dis, 0 */ - MUX_VAL(0x0046, 0x00) /* sdrc_ncs1 - Dis, 0 */ - MUX_VAL(0x0048, 0x00) /* sdrc_cke1 - Dis, 0 */ - /* GPMC */ - MUX_VAL(0x0030, 0x00) /* gpmc_clk - Dis, 0 */ - MUX_VAL(0x0032, 0x00) /* gpmc_ncs1- Dis, 0 */ - MUX_VAL(0x0033, 0x00) /* gpmc_ncs2- Dis, 0 */ - MUX_VAL(0x0034, 0x03) /* gpmc_ncs3- Dis, 3, ->gpio_24 */ - MUX_VAL(0x0035, 0x03) /* gpmc_ncs4- Dis, 3, ->gpio_25 */ - MUX_VAL(0x0036, 0x00) /* gpmc_ncs5- Dis, 0 */ - MUX_VAL(0x0037, 0x03) /* gpmc_ncs6- Dis, 3, ->gpio_27 */ - MUX_VAL(0x0038, 0x00) /* gpmc_ncs7- Dis, 0 */ - MUX_VAL(0x0040, 0x18) /* gpmc_wait1- Dis, 0 */ - MUX_VAL(0x0041, 0x18) /* gpmc_wait2- Dis, 0 */ - MUX_VAL(0x0042, 0x1B) /* gpmc_wait3- EN, HI, 3, ->gpio_35 */ - MUX_VAL(0x0085, 0x1B) /* gpmc_a10- EN, HI, 3, ->gpio_3 */ -} - -int nand_init(void) -{ - u32 rev; - - /* GPMC Configuration */ - rev = get_cpu_rev(); - - /* global settings */ - __raw_writel(0x10, GPMC_SYSCONFIG); /* smart idle */ - __raw_writel(0x0, GPMC_IRQENABLE); /* isr's sources masked */ - __raw_writel(0, GPMC_TIMEOUT_CONTROL);/* timeout disable */ -#ifdef CFG_NAND - __raw_writel(0x001, GPMC_CONFIG); /* set nWP, disable limited addr */ -#endif - - /* Set the GPMC Vals . For NAND boot on 2430SDP, NAND is mapped at CS0 - * , NOR at CS1 and MPDB at CS5. And oneNAND boot, we map oneNAND at CS0. - * We configure only GPMC CS0 with required values. Configiring other devices - * at other CS in done in u-boot anyway. So we don't have to bother doing it here. - */ - __raw_writel(0, GPMC_CONFIG7_0); - sdelay(1000); - -#ifdef CFG_NAND - __raw_writel( SMNAND_GPMC_CONFIG1, GPMC_CONFIG1_0); - __raw_writel( SMNAND_GPMC_CONFIG2, GPMC_CONFIG2_0); - __raw_writel( SMNAND_GPMC_CONFIG3, GPMC_CONFIG3_0); - __raw_writel( SMNAND_GPMC_CONFIG4, GPMC_CONFIG4_0); - __raw_writel( SMNAND_GPMC_CONFIG5, GPMC_CONFIG5_0); - __raw_writel( SMNAND_GPMC_CONFIG6, GPMC_CONFIG6_0); - -#else /* CFG_ONENAND */ - __raw_writel( ONENAND_GPMC_CONFIG1, GPMC_CONFIG1_0); - __raw_writel( ONENAND_GPMC_CONFIG2, GPMC_CONFIG2_0); - __raw_writel( ONENAND_GPMC_CONFIG3, GPMC_CONFIG3_0); - __raw_writel( ONENAND_GPMC_CONFIG4, GPMC_CONFIG4_0); - __raw_writel( ONENAND_GPMC_CONFIG5, GPMC_CONFIG5_0); - __raw_writel( ONENAND_GPMC_CONFIG6, GPMC_CONFIG6_0); -#endif - - /* Enable the GPMC Mapping */ - __raw_writel(( ((OMAP24XX_GPMC_CS0_SIZE & 0xF)<<8) | - ((OMAP24XX_GPMC_CS0_MAP>>24) & 0x3F) | - (1<<6) ), GPMC_CONFIG7_0); - sdelay(2000); -#ifdef CFG_NAND - if (nand_chip()){ -#ifdef CFG_PRINTF - printf("Unsupported Chip!\n"); -#endif - return 1; - } -#else - if (onenand_chip()){ -#ifdef CFG_PRINTF - printf("OneNAND Unsupported !\n"); -#endif - return 1; - } - -#endif - return 0; -} - -/* optionally do something like blinking LED */ -void board_hang (void) -{ while (0) {};} diff --git a/x-loader/board/omap2430sdp/platform.S b/x-loader/board/omap2430sdp/platform.S deleted file mode 100644 index f221d7e..0000000 --- a/x-loader/board/omap2430sdp/platform.S +++ /dev/null @@ -1,198 +0,0 @@ -/* - * Board specific setup info - * - * (C) Copyright 2004-2005 - * Texas Instruments, <www.ti.com> - * Richard Woodruff <r-woodruff2@ti.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <config.h> -#include <asm/arch/mem.h> -#include <asm/arch/omap2430.h> -#include <asm/arch/clocks.h> - -_TEXT_BASE: - .word TEXT_BASE /* sdram load addr from config.mk */ - -/************************************************************************** - * cpy_clk_code: relocates clock code into SRAM where its safer to execute - * R1 = SRAM destination address. - *************************************************************************/ -.global cpy_clk_code - cpy_clk_code: - /* Copy DPLL code into SRAM */ - adr r0, go_to_speed /* get addr of clock setting code */ - mov r2, #384 /* r2 size to copy (div by 32 bytes) */ - mov r1, r1 /* r1 <- dest address (passed in) */ - add r2, r2, r0 /* r2 <- source end address */ -next2: - ldmia r0!, {r3-r10} /* copy from source address [r0] */ - stmia r1!, {r3-r10} /* copy to target address [r1] */ - cmp r0, r2 /* until source end address [r2] */ - bne next2 - mov pc, lr /* back to caller */ - -/* **************************************************************************** - * go_to_speed: -Moves to bypass, -Commits clock dividers, -puts dpll at speed - * -executed from SRAM. - * R0 = PRCM_CLKCFG_CTRL - addr of valid reg - * R1 = CM_CLKEN_PLL - addr dpll ctlr reg - * R2 = dpll value - * R3 = CM_IDLEST_CKGEN - addr dpll lock wait - ******************************************************************************/ -.global go_to_speed - go_to_speed: - sub sp, sp, #0x4 /* get some stack space */ - str r4, [sp] /* save r4's value */ - - /* move into fast relock bypass */ - ldr r8, pll_ctl_add - mov r4, #0x2 - str r4, [r8] - ldr r4, pll_stat -block: - ldr r8, [r4] /* wait for bypass to take effect */ - and r8, r8, #0x3 - cmp r8, #0x1 - bne block - - /* set new dpll dividers _after_ in bypass */ - ldr r4, pll_div_add - ldr r8, pll_div_val - str r8, [r4] - - /* now prepare GPMC (flash) for new dpll speed */ - /* flash needs to be stable when we jump back to it */ - ldr r4, flash_cfg3_addr - ldr r8, flash_cfg3_val - str r8, [r4] - ldr r4, flash_cfg4_addr - ldr r8, flash_cfg4_val - str r8, [r4] - ldr r4, flash_cfg1_addr - ldr r8, [r4] - orr r8, r8, #0x3 /* up gpmc divider */ - str r8, [r4] - - /* setup to 2x loop though code. The first loop pre-loads the - * icache, the 2nd commits the prcm config, and locks the dpll - */ - mov r4, #0x1000 /* spin spin spin */ - mov r8, #0x4 /* first pass condition & set registers */ - cmp r8, #0x4 -2: - ldrne r8, [r3] /* DPLL lock check */ - and r8, r8, #0x7 - cmp r8, #0x2 - beq 4f -3: - subeq r8, r8, #0x1 - streq r8, [r0] /* commit dividers (2nd time) */ - nop -lloop1: - sub r4, r4, #0x1 /* Loop currently necessary else bad jumps */ - nop - cmp r4, #0x0 - bne lloop1 - mov r4, #0x40000 - cmp r8, #0x1 - nop - streq r2, [r1] /* lock dpll (2nd time) */ - nop -lloop2: - sub r4, r4, #0x1 /* loop currently necessary else bad jumps */ - nop - cmp r4, #0x0 - bne lloop2 - mov r4, #0x40000 - cmp r8, #0x1 - nop - ldreq r8, [r3] /* get lock condition for dpll */ - cmp r8, #0x4 /* first time though? */ - bne 2b - moveq r8, #0x2 /* set to dpll check condition. */ - beq 3b /* if condition not true branch */ -4: - ldr r4, [sp] - add sp, sp, #0x4 /* return stack space */ - mov pc, lr /* back to caller, locked */ - -_go_to_speed: .word go_to_speed - -/* these constants need to be close for PIC code */ -#ifdef CFG_ONENAND -flash_cfg3_addr: - .word GPMC_CONFIG3_0 -flash_cfg3_val: - .word ONENAND_GPMC_CONFIG3 -flash_cfg4_addr: - .word GPMC_CONFIG4_0 -flash_cfg4_val: - .word ONENAND_GPMC_CONFIG4 -flash_cfg1_addr: - .word GPMC_CONFIG1_0 -#else -flash_cfg3_addr: - .word GPMC_CONFIG3_0 -flash_cfg3_val: - .word SMNAND_GPMC_CONFIG3 -flash_cfg4_addr: - .word GPMC_CONFIG4_0 -flash_cfg4_val: - .word SMNAND_GPMC_CONFIG4 -flash_cfg1_addr: - .word GPMC_CONFIG1_0 -#endif -pll_ctl_add: - .word CM_CLKEN_PLL -pll_stat: - .word CM_IDLEST_CKGEN -pll_div_add: - .word CM_CLKSEL1_PLL -pll_div_val: - .word DPLL_VAL /* DPLL setting (300MHz default) */ - -.globl platformsetup -platformsetup: - ldr sp, SRAM_STACK - str ip, [sp] /* stash old link register */ - mov ip, lr /* save link reg across call */ - bl s_init /* go setup pll,mux,memory */ - ldr ip, [sp] /* restore save ip */ - mov lr, ip /* restore link reg */ - - /* map interrupt controller */ - ldr r0, VAL_INTH_SETUP - mcr p15, 0, r0, c15, c2, 4 - - /* back to arch calling code */ - mov pc, lr - - /* the literal pools origin */ - .ltorg - -REG_CONTROL_STATUS: - .word CONTROL_STATUS -VAL_INTH_SETUP: - .word PERIFERAL_PORT_BASE -SRAM_STACK: - .word LOW_LEVEL_SRAM_STACK - diff --git a/x-loader/board/omap2430sdp/x-load.lds b/x-loader/board/omap2430sdp/x-load.lds deleted file mode 100644 index f12e8f8..0000000 --- a/x-loader/board/omap2430sdp/x-load.lds +++ /dev/null @@ -1,54 +0,0 @@ -/* - * January 2004 - Changed to support H4 device - * Copyright (c) 2004-2005 Texas Instruments - * - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, <gj@denx.de> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN(4); - .text : - { - cpu/arm1136/start.o (.text) - *(.text) - } - - . = ALIGN(4); - .rodata : { *(.rodata) } - - . = ALIGN(4); - .data : { *(.data) } - - . = ALIGN(4); - .got : { *(.got) } - - . = ALIGN(4); - __bss_start = .; - .bss : { *(.bss) } - _end = .; -} diff --git a/x-loader/board/omap3430labrador/Makefile b/x-loader/board/omap3430labrador/Makefile deleted file mode 100644 index d54b666..0000000 --- a/x-loader/board/omap3430labrador/Makefile +++ /dev/null @@ -1,51 +0,0 @@ -# -# (C) Copyright 2000, 2001, 2002 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).a - -COBJS := omap3430sdp.o -SOBJS := platform.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) $(SOBJS) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak $(obj).depend - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/x-loader/board/omap3430labrador/config.mk b/x-loader/board/omap3430labrador/config.mk deleted file mode 100644 index d6ad6c5..0000000 --- a/x-loader/board/omap3430labrador/config.mk +++ /dev/null @@ -1,22 +0,0 @@ -# -# (C) Copyright 2006 -# Texas Instruments, <www.ti.com> -# -# SDP3430 board uses OMAP3430 (ARM-CortexA8) cpu -# see http://www.ti.com/ for more information on Texas Instruments -# -# SDP3430 has 1 bank of 32MB or 128MB mDDR-SDRAM on CS0 -# SDP3430 has 1 bank of 32MB or 00MB mDDR-SDRAM on CS1 -# Physical Address: -# 8000'0000 (bank0) -# A000'0000 (bank1) - re-mappable below CS1 - -# For use if you want X-Loader to relocate from SRAM to DDR -#TEXT_BASE = 0x80e80000 - -# For XIP in 64K of SRAM or debug (GP device has it all availabe) -# SRAM 40200000-4020FFFF base -# initial stack at 0x4020fffc used in s_init (below xloader). -# The run time stack is (above xloader, 2k below) -# If any globals exist there needs to be room for them also -TEXT_BASE = 0x40208800 diff --git a/x-loader/board/omap3430labrador/omap3430sdp.c b/x-loader/board/omap3430labrador/omap3430sdp.c deleted file mode 100644 index 89d9ff1..0000000 --- a/x-loader/board/omap3430labrador/omap3430sdp.c +++ /dev/null @@ -1,753 +0,0 @@ -/* - * (C) Copyright 2006-2008 - * Texas Instruments, <www.ti.com> - * Jian Zhang <jzhang@ti.com> - * Richard Woodruff <r-woodruff2@ti.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#include <common.h> -#include <asm/arch/cpu.h> -#include <asm/arch/bits.h> -#include <asm/arch/mux.h> -#include <asm/arch/sys_proto.h> -#include <asm/arch/sys_info.h> -#include <asm/arch/clocks.h> -#include <asm/arch/mem.h> - -/* Used to index into DPLL parameter tables */ -struct dpll_param { - unsigned int m; - unsigned int n; - unsigned int fsel; - unsigned int m2; -}; - -typedef struct dpll_param dpll_param; - -#define MAX_SIL_INDEX 3 - -/* Following functions are exported from lowlevel_init.S */ -extern dpll_param * get_mpu_dpll_param(void); -extern dpll_param * get_iva_dpll_param(void); -extern dpll_param * get_core_dpll_param(void); -extern dpll_param * get_per_dpll_param(void); - -#define __raw_readl(a) (*(volatile unsigned int *)(a)) -#define __raw_writel(v,a) (*(volatile unsigned int *)(a) = (v)) -#define __raw_readw(a) (*(volatile unsigned short *)(a)) -#define __raw_writew(v,a) (*(volatile unsigned short *)(a) = (v)) - -/******************************************************* - * Routine: delay - * Description: spinning delay to use before udelay works - ******************************************************/ -static inline void delay(unsigned long loops) -{ - __asm__ volatile ("1:\n" "subs %0, %1, #1\n" - "bne 1b":"=r" (loops):"0"(loops)); -} - -/***************************************** - * Routine: board_init - * Description: Early hardware init. - *****************************************/ -int board_init (void) -{ - return 0; -} - -/************************************************************* - * get_device_type(): tell if GP/HS/EMU/TST - *************************************************************/ -u32 get_device_type(void) -{ - int mode; - mode = __raw_readl(CONTROL_STATUS) & (DEVICE_MASK); - return(mode >>= 8); -} - -/****************************************** - * get_cpu_rev(void) - extract version info - ******************************************/ -u32 get_cpu_rev(void) -{ - u32 cpuid=0; - /* On ES1.0 the IDCODE register is not exposed on L4 - * so using CPU ID to differentiate - * between ES2.0 and ES1.0. - */ - __asm__ __volatile__("mrc p15, 0, %0, c0, c0, 0":"=r" (cpuid)); - if((cpuid & 0xf) == 0x0) - return CPU_3430_ES1; - else - return CPU_3430_ES2; - -} - -/****************************************** - * cpu_is_3410(void) - returns true for 3410 - ******************************************/ -u32 cpu_is_3410(void) -{ - int status; - if(get_cpu_rev() < CPU_3430_ES2) { - return 0; - } else { - /* read scalability status and return 1 for 3410*/ - status = __raw_readl(CONTROL_SCALABLE_OMAP_STATUS); - /* Check whether MPU frequency is set to 266 MHz which - * is nominal for 3410. If yes return true else false - */ - if (((status >> 8) & 0x3) == 0x2) - return 1; - else - return 0; - } -} - -/***************************************************************** - * sr32 - clear & set a value in a bit range for a 32 bit address - *****************************************************************/ -void sr32(u32 addr, u32 start_bit, u32 num_bits, u32 value) -{ - u32 tmp, msk = 0; - msk = 1 << num_bits; - --msk; - tmp = __raw_readl(addr) & ~(msk << start_bit); - tmp |= value << start_bit; - __raw_writel(tmp, addr); -} - -/********************************************************************* - * wait_on_value() - common routine to allow waiting for changes in - * volatile regs. - *********************************************************************/ -u32 wait_on_value(u32 read_bit_mask, u32 match_value, u32 read_addr, u32 bound) -{ - u32 i = 0, val; - do { - ++i; - val = __raw_readl(read_addr) & read_bit_mask; - if (val == match_value) - return (1); - if (i == bound) - return (0); - } while (1); -} - -#ifdef CFG_3430SDRAM_DDR -/********************************************************************* - * config_3430sdram_ddr() - Init DDR on 3430SDP dev board. - *********************************************************************/ -void config_3430sdram_ddr(void) -{ - /* reset sdrc controller */ - __raw_writel(SOFTRESET, SDRC_SYSCONFIG); - wait_on_value(BIT0, BIT0, SDRC_STATUS, 12000000); - __raw_writel(0, SDRC_SYSCONFIG); - - /* setup sdrc to ball mux */ - __raw_writel(SDP_SDRC_SHARING, SDRC_SHARING); - - /* set mdcfg */ - __raw_writel(SDP_SDRC_MDCFG_0_DDR, SDRC_MCFG_0); - - /* set timing */ - __raw_writel(SDP_SDRC_ACTIM_CTRLA_0, SDRC_ACTIM_CTRLA_0); - __raw_writel(SDP_SDRC_ACTIM_CTRLB_0, SDRC_ACTIM_CTRLB_0); - __raw_writel(SDP_SDRC_RFR_CTRL, SDRC_RFR_CTRL); - - /* init sequence for mDDR/mSDR using manual commands (DDR is different) */ - __raw_writel(CMD_NOP, SDRC_MANUAL_0); - delay(5000); - __raw_writel(CMD_PRECHARGE, SDRC_MANUAL_0); - __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0); - __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0); - - /* set mr0 */ - __raw_writel(SDP_SDRC_MR_0_DDR, SDRC_MR_0); - - /* set up dll */ - __raw_writel(SDP_SDRC_DLLAB_CTRL, SDRC_DLLA_CTRL); - delay(0x2000); /* give time to lock */ - -} -#endif // CFG_3430SDRAM_DDR - -/************************************************************* - * get_sys_clk_speed - determine reference oscillator speed - * based on known 32kHz clock and gptimer. - *************************************************************/ -u32 get_osc_clk_speed(void) -{ - u32 start, cstart, cend, cdiff, val; - - val = __raw_readl(PRM_CLKSRC_CTRL); - /* If SYS_CLK is being divided by 2, remove for now */ - val = (val & (~BIT7)) | BIT6; - __raw_writel(val, PRM_CLKSRC_CTRL); - - /* enable timer2 */ - val = __raw_readl(CM_CLKSEL_WKUP) | BIT0; - __raw_writel(val, CM_CLKSEL_WKUP); /* select sys_clk for GPT1 */ - - /* Enable I and F Clocks for GPT1 */ - val = __raw_readl(CM_ICLKEN_WKUP) | BIT0 | BIT2; - __raw_writel(val, CM_ICLKEN_WKUP); - val = __raw_readl(CM_FCLKEN_WKUP) | BIT0; - __raw_writel(val, CM_FCLKEN_WKUP); - - __raw_writel(0, OMAP34XX_GPT1 + TLDR); /* start counting at 0 */ - __raw_writel(GPT_EN, OMAP34XX_GPT1 + TCLR); /* enable clock */ - /* enable 32kHz source *//* enabled out of reset */ - /* determine sys_clk via gauging */ - - start = 20 + __raw_readl(S32K_CR); /* start time in 20 cycles */ - while (__raw_readl(S32K_CR) < start); /* dead loop till start time */ - cstart = __raw_readl(OMAP34XX_GPT1 + TCRR); /* get start sys_clk count */ - while (__raw_readl(S32K_CR) < (start + 20)); /* wait for 40 cycles */ - cend = __raw_readl(OMAP34XX_GPT1 + TCRR); /* get end sys_clk count */ - cdiff = cend - cstart; /* get elapsed ticks */ - - /* based on number of ticks assign speed */ - if (cdiff > 19000) - return (S38_4M); - else if (cdiff > 15200) - return (S26M); - else if (cdiff > 13000) - return (S24M); - else if (cdiff > 9000) - return (S19_2M); - else if (cdiff > 7600) - return (S13M); - else - return (S12M); -} - -/****************************************************************************** - * get_sys_clkin_sel() - returns the sys_clkin_sel field value based on - * -- input oscillator clock frequency. - * - *****************************************************************************/ -void get_sys_clkin_sel(u32 osc_clk, u32 *sys_clkin_sel) -{ - if(osc_clk == S38_4M) - *sys_clkin_sel= 4; - else if(osc_clk == S26M) - *sys_clkin_sel = 3; - else if(osc_clk == S19_2M) - *sys_clkin_sel = 2; - else if(osc_clk == S13M) - *sys_clkin_sel = 1; - else if(osc_clk == S12M) - *sys_clkin_sel = 0; -} - -/****************************************************************************** - * prcm_init() - inits clocks for PRCM as defined in clocks.h - * -- called from SRAM, or Flash (using temp SRAM stack). - *****************************************************************************/ -void prcm_init(void) -{ - u32 osc_clk=0, sys_clkin_sel; - dpll_param *dpll_param_p; - u32 clk_index, sil_index; - - /* Gauge the input clock speed and find out the sys_clkin_sel - * value corresponding to the input clock. - */ - osc_clk = get_osc_clk_speed(); - get_sys_clkin_sel(osc_clk, &sys_clkin_sel); - - sr32(PRM_CLKSEL, 0, 3, sys_clkin_sel); /* set input crystal speed */ - - /* If the input clock is greater than 19.2M always divide/2 */ - if(sys_clkin_sel > 2) { - sr32(PRM_CLKSRC_CTRL, 6, 2, 2);/* input clock divider */ - clk_index = sys_clkin_sel/2; - } else { - sr32(PRM_CLKSRC_CTRL, 6, 2, 1);/* input clock divider */ - clk_index = sys_clkin_sel; - } - - sr32(PRM_CLKSRC_CTRL, 0, 2, 0);/* Bypass mode: T2 inputs a square clock */ - - /* The DPLL tables are defined according to sysclk value and - * silicon revision. The clk_index value will be used to get - * the values for that input sysclk from the DPLL param table - * and sil_index will get the values for that SysClk for the - * appropriate silicon rev. - */ - if(cpu_is_3410()) - sil_index = 2; - else { - if(get_cpu_rev() == CPU_3430_ES1) - sil_index = 0; - else if(get_cpu_rev() == CPU_3430_ES2) - sil_index = 1; - } - - /* Unlock MPU DPLL (slows things down, and needed later) */ - sr32(CM_CLKEN_PLL_MPU, 0, 3, PLL_LOW_POWER_BYPASS); - wait_on_value(BIT0, 0, CM_IDLEST_PLL_MPU, LDELAY); - - /* Getting the base address of Core DPLL param table*/ - dpll_param_p = (dpll_param *)get_core_dpll_param(); - /* Moving it to the right sysclk and ES rev base */ - dpll_param_p = dpll_param_p + MAX_SIL_INDEX*clk_index + sil_index; - /* CORE DPLL */ - /* sr32(CM_CLKSEL2_EMU) set override to work when asleep */ - sr32(CM_CLKEN_PLL, 0, 3, PLL_FAST_RELOCK_BYPASS); - wait_on_value(BIT0, 0, CM_IDLEST_CKGEN, LDELAY); - /* For 3430 ES1.0 Errata 1.50, default value directly doesnt - work. write another value and then default value. */ - sr32(CM_CLKSEL1_EMU, 16, 5, CORE_M3X2 + 1); /* m3x2 */ - sr32(CM_CLKSEL1_EMU, 16, 5, CORE_M3X2); /* m3x2 */ - sr32(CM_CLKSEL1_PLL, 27, 2, dpll_param_p->m2); /* Set M2 */ - sr32(CM_CLKSEL1_PLL, 16, 11, dpll_param_p->m); /* Set M */ - sr32(CM_CLKSEL1_PLL, 8, 7, dpll_param_p->n); /* Set N */ - sr32(CM_CLKSEL1_PLL, 6, 1, 0); /* 96M Src */ - sr32(CM_CLKSEL_CORE, 8, 4, CORE_SSI_DIV); /* ssi */ - sr32(CM_CLKSEL_CORE, 4, 2, CORE_FUSB_DIV); /* fsusb ES1 only */ - sr32(CM_CLKSEL_CORE, 2, 2, CORE_L4_DIV); /* l4 */ - sr32(CM_CLKSEL_CORE, 0, 2, CORE_L3_DIV); /* l3 */ - sr32(CM_CLKSEL_GFX, 0, 3, GFX_DIV); /* gfx */ - sr32(CM_CLKSEL_WKUP, 1, 2, WKUP_RSM); /* reset mgr */ - sr32(CM_CLKEN_PLL, 4, 4, dpll_param_p->fsel); /* FREQSEL */ - sr32(CM_CLKEN_PLL, 0, 3, PLL_LOCK); /* lock mode */ - wait_on_value(BIT0, 1, CM_IDLEST_CKGEN, LDELAY); - - /* Getting the base address to PER DPLL param table*/ - dpll_param_p = (dpll_param *)get_per_dpll_param(); - /* Moving it to the right sysclk base */ - dpll_param_p = dpll_param_p + clk_index; - /* PER DPLL */ - sr32(CM_CLKEN_PLL, 16, 3, PLL_STOP); - wait_on_value(BIT1, 0, CM_IDLEST_CKGEN, LDELAY); - sr32(CM_CLKSEL1_EMU, 24, 5, PER_M6X2); /* set M6 */ - sr32(CM_CLKSEL_CAM, 0, 5, PER_M5X2); /* set M5 */ - sr32(CM_CLKSEL_DSS, 0, 5, PER_M4X2); /* set M4 */ - sr32(CM_CLKSEL_DSS, 8, 5, PER_M3X2); /* set M3 */ - sr32(CM_CLKSEL3_PLL, 0, 5, dpll_param_p->m2); /* set M2 */ - sr32(CM_CLKSEL2_PLL, 8, 11, dpll_param_p->m); /* set m */ - sr32(CM_CLKSEL2_PLL, 0, 7, dpll_param_p->n); /* set n */ - sr32(CM_CLKEN_PLL, 20, 4, dpll_param_p->fsel);/* FREQSEL */ - sr32(CM_CLKEN_PLL, 16, 3, PLL_LOCK); /* lock mode */ - wait_on_value(BIT1, 2, CM_IDLEST_CKGEN, LDELAY); - - /* Getting the base address to MPU DPLL param table*/ - dpll_param_p = (dpll_param *)get_mpu_dpll_param(); - /* Moving it to the right sysclk and ES rev base */ - dpll_param_p = dpll_param_p + MAX_SIL_INDEX*clk_index + sil_index; - /* MPU DPLL (unlocked already) */ - sr32(CM_CLKSEL2_PLL_MPU, 0, 5, dpll_param_p->m2); /* Set M2 */ - sr32(CM_CLKSEL1_PLL_MPU, 8, 11, dpll_param_p->m); /* Set M */ - sr32(CM_CLKSEL1_PLL_MPU, 0, 7, dpll_param_p->n); /* Set N */ - sr32(CM_CLKEN_PLL_MPU, 4, 4, dpll_param_p->fsel); /* FREQSEL */ - sr32(CM_CLKEN_PLL_MPU, 0, 3, PLL_LOCK); /* lock mode */ - wait_on_value(BIT0, 1, CM_IDLEST_PLL_MPU, LDELAY); - - /* Getting the base address to IVA DPLL param table*/ - dpll_param_p = (dpll_param *)get_iva_dpll_param(); - /* Moving it to the right sysclk and ES rev base */ - dpll_param_p = dpll_param_p + MAX_SIL_INDEX*clk_index + sil_index; - /* IVA DPLL (set to 12*20=240MHz) */ - sr32(CM_CLKEN_PLL_IVA2, 0, 3, PLL_STOP); - wait_on_value(BIT0, 0, CM_IDLEST_PLL_IVA2, LDELAY); - sr32(CM_CLKSEL2_PLL_IVA2, 0, 5, dpll_param_p->m2); /* set M2 */ - sr32(CM_CLKSEL1_PLL_IVA2, 8, 11, dpll_param_p->m); /* set M */ - sr32(CM_CLKSEL1_PLL_IVA2, 0, 7, dpll_param_p->n); /* set N */ - sr32(CM_CLKEN_PLL_IVA2, 4, 4, dpll_param_p->fsel); /* FREQSEL */ - sr32(CM_CLKEN_PLL_IVA2, 0, 3, PLL_LOCK); /* lock mode */ - wait_on_value(BIT0, 1, CM_IDLEST_PLL_IVA2, LDELAY); - - /* Set up GPTimers to sys_clk source only */ - sr32(CM_CLKSEL_PER, 0, 8, 0xff); - sr32(CM_CLKSEL_WKUP, 0, 1, 1); - - delay(5000); -} - -/***************************************** - * Routine: secure_unlock - * Description: Setup security registers for access - * (GP Device only) - *****************************************/ -void secure_unlock(void) -{ - /* Permission values for registers -Full fledged permissions to all */ - #define UNLOCK_1 0xFFFFFFFF - #define UNLOCK_2 0x00000000 - #define UNLOCK_3 0x0000FFFF - /* Protection Module Register Target APE (PM_RT)*/ - __raw_writel(UNLOCK_1, RT_REQ_INFO_PERMISSION_1); - __raw_writel(UNLOCK_1, RT_READ_PERMISSION_0); - __raw_writel(UNLOCK_1, RT_WRITE_PERMISSION_0); - __raw_writel(UNLOCK_2, RT_ADDR_MATCH_1); - - __raw_writel(UNLOCK_3, GPMC_REQ_INFO_PERMISSION_0); - __raw_writel(UNLOCK_3, GPMC_READ_PERMISSION_0); - __raw_writel(UNLOCK_3, GPMC_WRITE_PERMISSION_0); - - __raw_writel(UNLOCK_3, OCM_REQ_INFO_PERMISSION_0); - __raw_writel(UNLOCK_3, OCM_READ_PERMISSION_0); - __raw_writel(UNLOCK_3, OCM_WRITE_PERMISSION_0); - __raw_writel(UNLOCK_2, OCM_ADDR_MATCH_2); - - /* IVA Changes */ - __raw_writel(UNLOCK_3, IVA2_REQ_INFO_PERMISSION_0); - __raw_writel(UNLOCK_3, IVA2_READ_PERMISSION_0); - __raw_writel(UNLOCK_3, IVA2_WRITE_PERMISSION_0); - - __raw_writel(UNLOCK_1, SMS_RG_ATT0); /* SDRC region 0 public */ -} - -/********************************************************** - * Routine: try_unlock_sram() - * Description: If chip is GP type, unlock the SRAM for - * general use. - ***********************************************************/ -void try_unlock_memory(void) -{ - int mode; - - /* if GP device unlock device SRAM for general use */ - /* secure code breaks for Secure/Emulation device - HS/E/T*/ - mode = get_device_type(); - if (mode == GP_DEVICE) { - secure_unlock(); - } - return; -} - -/********************************************************** - * Routine: s_init - * Description: Does early system init of muxing and clocks. - * - Called at time when only stack is available. - **********************************************************/ - -void s_init(void) -{ - watchdog_init(); -#ifdef CONFIG_3430_AS_3410 - /* setup the scalability control register for - * 3430 to work in 3410 mode - */ - __raw_writel(0x5ABF,CONTROL_SCALABLE_OMAP_OCP); -#endif - try_unlock_memory(); - set_muxconf_regs(); - delay(100); - prcm_init(); - per_clocks_enable(); - config_3430sdram_ddr(); -} - -/******************************************************* - * Routine: misc_init_r - * Description: Init ethernet (done here so udelay works) - ********************************************************/ -int misc_init_r (void) -{ - return(0); -} - -/****************************************************** - * Routine: wait_for_command_complete - * Description: Wait for posting to finish on watchdog - ******************************************************/ -void wait_for_command_complete(unsigned int wd_base) -{ - int pending = 1; - do { - pending = __raw_readl(wd_base + WWPS); - } while (pending); -} - -/**************************************** - * Routine: watchdog_init - * Description: Shut down watch dogs - *****************************************/ -void watchdog_init(void) -{ - /* There are 3 watch dogs WD1=Secure, WD2=MPU, WD3=IVA. WD1 is - * either taken care of by ROM (HS/EMU) or not accessible (GP). - * We need to take care of WD2-MPU or take a PRCM reset. WD3 - * should not be running and does not generate a PRCM reset. - */ - sr32(CM_FCLKEN_WKUP, 5, 1, 1); - sr32(CM_ICLKEN_WKUP, 5, 1, 1); - wait_on_value(BIT5, 0x20, CM_IDLEST_WKUP, 5); /* some issue here */ - - __raw_writel(WD_UNLOCK1, WD2_BASE + WSPR); - wait_for_command_complete(WD2_BASE); - __raw_writel(WD_UNLOCK2, WD2_BASE + WSPR); -} - -/********************************************** - * Routine: dram_init - * Description: sets uboots idea of sdram size - **********************************************/ -int dram_init (void) -{ - return 0; -} - -/***************************************************************** - * Routine: peripheral_enable - * Description: Enable the clks & power for perifs (GPT2, UART1,...) - ******************************************************************/ -void per_clocks_enable(void) -{ - /* Enable GP2 timer. */ - sr32(CM_CLKSEL_PER, 0, 1, 0x1); /* GPT2 = sys clk */ - sr32(CM_ICLKEN_PER, 3, 1, 0x1); /* ICKen GPT2 */ - sr32(CM_FCLKEN_PER, 3, 1, 0x1); /* FCKen GPT2 */ - -#ifdef CFG_NS16550 -////#ifdef CONFIG_SERIAL3 - sr32(CM_FCLKEN_PER, 11, 1, 0x1); - sr32(CM_ICLKEN_PER, 11, 1, 0x1); -////#else - /* Enable UART1 clocks */ - sr32(CM_FCLKEN1_CORE, 13, 1, 0x1); - sr32(CM_ICLKEN1_CORE, 13, 1, 0x1); -////#endif -#endif - delay(1000); -} - -/* Set MUX for UART, GPMC, SDRC, GPIO */ - -#define MUX_VAL(OFFSET,VALUE)\ - __raw_writew((VALUE), OMAP34XX_CTRL_BASE + (OFFSET)); - -#define CP(x) (CONTROL_PADCONF_##x) -/* - * IEN - Input Enable - * IDIS - Input Disable - * PTD - Pull type Down - * PTU - Pull type Up - * DIS - Pull type selection is inactive - * EN - Pull type selection is active - * M0 - Mode 0 - * The commented string gives the final mux configuration for that pin - */ -#define MUX_DEFAULT()\ - /*SDRC*/\ - MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /*SDRC_D0*/\ - MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /*SDRC_D1*/\ - MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /*SDRC_D2*/\ - MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /*SDRC_D3*/\ - MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /*SDRC_D4*/\ - MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /*SDRC_D5*/\ - MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /*SDRC_D6*/\ - MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /*SDRC_D7*/\ - MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /*SDRC_D8*/\ - MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /*SDRC_D9*/\ - MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /*SDRC_D10*/\ - MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /*SDRC_D11*/\ - MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /*SDRC_D12*/\ - MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /*SDRC_D13*/\ - MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /*SDRC_D14*/\ - MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /*SDRC_D15*/\ - MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /*SDRC_D16*/\ - MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /*SDRC_D17*/\ - MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /*SDRC_D18*/\ - MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /*SDRC_D19*/\ - MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /*SDRC_D20*/\ - MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /*SDRC_D21*/\ - MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /*SDRC_D22*/\ - MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /*SDRC_D23*/\ - MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /*SDRC_D24*/\ - MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /*SDRC_D25*/\ - MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /*SDRC_D26*/\ - MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /*SDRC_D27*/\ - MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /*SDRC_D28*/\ - MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /*SDRC_D29*/\ - MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /*SDRC_D30*/\ - MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /*SDRC_D31*/\ - MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /*SDRC_CLK*/\ - MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /*SDRC_DQS0*/\ - MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /*SDRC_DQS1*/\ - MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /*SDRC_DQS2*/\ - MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /*SDRC_DQS3*/\ - /*GPMC*/\ - MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0)) /*GPMC_A1*/\ - MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0)) /*GPMC_A2*/\ - MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0)) /*GPMC_A3*/\ - MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0)) /*GPMC_A4*/\ - MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0)) /*GPMC_A5*/\ - MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0)) /*GPMC_A6*/\ - MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0)) /*GPMC_A7*/\ - MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0)) /*GPMC_A8*/\ - MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M0)) /*GPMC_A9*/\ - MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0)) /*GPMC_A10*/\ - MUX_VAL(CP(GPMC_D0), (IEN | PTD | DIS | M0)) /*GPMC_D0*/\ - MUX_VAL(CP(GPMC_D1), (IEN | PTD | DIS | M0)) /*GPMC_D1*/\ - MUX_VAL(CP(GPMC_D2), (IEN | PTD | DIS | M0)) /*GPMC_D2*/\ - MUX_VAL(CP(GPMC_D3), (IEN | PTD | DIS | M0)) /*GPMC_D3*/\ - MUX_VAL(CP(GPMC_D4), (IEN | PTD | DIS | M0)) /*GPMC_D4*/\ - MUX_VAL(CP(GPMC_D5), (IEN | PTD | DIS | M0)) /*GPMC_D5*/\ - MUX_VAL(CP(GPMC_D6), (IEN | PTD | DIS | M0)) /*GPMC_D6*/\ - MUX_VAL(CP(GPMC_D7), (IEN | PTD | DIS | M0)) /*GPMC_D7*/\ - MUX_VAL(CP(GPMC_D8), (IEN | PTD | DIS | M0)) /*GPMC_D8*/\ - MUX_VAL(CP(GPMC_D9), (IEN | PTD | DIS | M0)) /*GPMC_D9*/\ - MUX_VAL(CP(GPMC_D10), (IEN | PTD | DIS | M0)) /*GPMC_D10*/\ - MUX_VAL(CP(GPMC_D11), (IEN | PTD | DIS | M0)) /*GPMC_D11*/\ - MUX_VAL(CP(GPMC_D12), (IEN | PTD | DIS | M0)) /*GPMC_D12*/\ - MUX_VAL(CP(GPMC_D13), (IEN | PTD | DIS | M0)) /*GPMC_D13*/\ - MUX_VAL(CP(GPMC_D14), (IEN | PTD | DIS | M0)) /*GPMC_D14*/\ - MUX_VAL(CP(GPMC_D15), (IEN | PTD | DIS | M0)) /*GPMC_D15*/\ - MUX_VAL(CP(GPMC_nCS0), (IDIS | PTU | EN | M0)) /*GPMC_nCS0*/\ - MUX_VAL(CP(GPMC_nCS1), (IDIS | PTU | EN | M0)) /*GPMC_nCS1*/\ - MUX_VAL(CP(GPMC_nCS2), (IDIS | PTU | EN | M0)) /*GPMC_nCS2*/\ - MUX_VAL(CP(GPMC_nCS3), (IDIS | PTU | EN | M0)) /*GPMC_nCS3*/\ - MUX_VAL(CP(GPMC_nCS4), (IDIS | PTU | EN | M0)) /*GPMC_nCS4 lab*/\ - MUX_VAL(CP(GPMC_nCS5), (IDIS | PTD | DIS | M0)) /*GPMC_nCS5 lab*/\ - MUX_VAL(CP(GPMC_nCS6), (IEN | PTD | DIS | M1)) /*sys_ndmareq1 lab*/\ - MUX_VAL(CP(GPMC_nCS7), (IEN | PTU | EN | M1)) /*GPMC_IO_DIR lab*/\ - MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M0)) /*GPMC_CLK*/\ - MUX_VAL(CP(GPMC_nADV_ALE), (IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\ - MUX_VAL(CP(GPMC_nOE), (IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\ - MUX_VAL(CP(GPMC_nWE), (IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\ - MUX_VAL(CP(GPMC_nBE0_CLE), (IDIS | PTD | DIS | M0)) /*GPMC_nBE0_CLE*/\ - MUX_VAL(CP(GPMC_nBE1), (IEN | PTD | DIS | M0)) /*GPMC_nBE1 lab*/\ - MUX_VAL(CP(GPMC_nWP), (IEN | PTD | DIS | M0)) /*GPMC_nWP*/\ - MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) /*GPMC_WAIT0*/\ - MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)) /*GPMC_WAIT1*/\ - MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M0)) /*gpmc_nWait lab*/\ - MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M0)) /*gpmc_nWait lab*/\ - MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)) /*DSS_DATA18*/\ - MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)) /*DSS_DATA19*/\ - MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)) /*DSS_DATA20*/\ - MUX_VAL(CP(CAM_XCLKB), (IDIS | PTD | DIS | M0)) /*CAM_XCLKB*/\ - MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4)) /*GPIO_167*/\ - MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /*UART1_TX*/\ - MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0)) /*UART1_RTS*/\ - MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M0)) /*UART1_CTS*/\ - MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /*UART1_RX*/\ - MUX_VAL(CP(McBSP1_DX), (IEN | PTD | DIS | M4)) /*GPIO_158*/\ - MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) /*SYS_32K*/\ - MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /*GPIO_2 */\ - MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) /*GPIO_3 */\ - MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /*GPIO_4 */\ - MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) /*GPIO_5 */\ - MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /*GPIO_6 */\ - MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /*GPIO_7 */\ - MUX_VAL(CP(SYS_BOOT6), (IEN | PTD | DIS | M4)) /*GPIO_8 */\ - MUX_VAL(CP(SYS_CLKOUT1), (IDIS | PTD | DIS | M0)) /*sys_clkout2 lab*/\ - MUX_VAL(CP(SYS_CLKOUT2), (IDIS | PTD | DIS | M0)) /*sys_clkout2 lab*/\ - MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0)) /*JTAG_nTRST*/\ - MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)) /*JTAG_TCK*/\ - MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)) /*JTAG_TMS*/\ - MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)) /*JTAG_TDI*/\ - MUX_VAL(CP(JTAG_EMU0), (IEN | PTD | DIS | M0)) /*JTAG_EMU0*/\ - MUX_VAL(CP(JTAG_EMU1), (IEN | PTD | DIS | M0)) /*JTAG_EMU1*/\ - MUX_VAL(CP(ETK_CLK), (IEN | PTD | DIS | M4)) /*GPIO_12*/\ - MUX_VAL(CP(ETK_CTL), (IEN | PTD | DIS | M4)) /*GPIO_13*/\ - MUX_VAL(CP(ETK_D0 ), (IEN | PTD | DIS | M4)) /*GPIO_14*/\ - MUX_VAL(CP(ETK_D1 ), (IEN | PTD | DIS | M4)) /*GPIO_15*/\ - MUX_VAL(CP(ETK_D2 ), (IEN | PTD | DIS | M4)) /*GPIO_16*/\ - MUX_VAL(CP(ETK_D10), (IEN | PTD | DIS | M4)) /*GPIO_24*/\ - MUX_VAL(CP(ETK_D11), (IEN | PTD | DIS | M4)) /*GPIO_25*/\ - MUX_VAL(CP(ETK_D12), (IEN | PTD | DIS | M4)) /*GPIO_26*/\ - MUX_VAL(CP(ETK_D13), (IEN | PTD | DIS | M4)) /*GPIO_27*/\ - MUX_VAL(CP(ETK_D14), (IEN | PTD | DIS | M4)) /*GPIO_28*/\ - MUX_VAL(CP(ETK_D15), (IEN | PTD | DIS | M4)) /*GPIO_29*/\ - MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | EN | M0)) /*UART3_CTS_RCTX */\ - MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0)) /*UART3_RTS_SD */\ - MUX_VAL(CP(UART3_RX_IRRX ), (IEN | PTD | DIS | M0)) /*UART3_RX_IRRX*/\ - MUX_VAL(CP(UART3_TX_IRTX ), (IDIS | PTD | DIS | M0)) /*UART3_TX_IRTX*/\ - MUX_VAL(CP(sdrc_cke0), (IDIS | PTU | EN | M0)) /*sdrc_cke0 */\ - MUX_VAL(CP(sdrc_cke1), (IDIS | PTD | DIS | M7)) /*sdrc_cke1 not used*/ -/********************************************************** - * Routine: set_muxconf_regs - * Description: Setting up the configuration Mux registers - * specific to the hardware. Many pins need - * to be moved from protect to primary mode. - *********************************************************/ -void set_muxconf_regs(void) -{ - MUX_DEFAULT(); -} - -/********************************************************** - * Routine: nand+_init - * Description: Set up nand for nand and jffs2 commands - *********************************************************/ -int nand_init(void) -{ - /* global settings */ - __raw_writel(0x10, GPMC_SYSCONFIG); /* smart idle */ - __raw_writel(0x0, GPMC_IRQENABLE); /* isr's sources masked */ - __raw_writel(0, GPMC_TIMEOUT_CONTROL);/* timeout disable */ -#ifdef CFG_NAND - __raw_writel(0x001, GPMC_CONFIG); /* set nWP, disable limited addr */ -#endif - - /* setup CS0 for Micron NAND, leave other CS's to u-boot */ - __raw_writel(0 , GPMC_CONFIG7 + GPMC_CONFIG_CS0); - delay(1000); - -#ifdef CFG_NAND - __raw_writel( M_NAND_GPMC_CONFIG1, GPMC_CONFIG1 + GPMC_CONFIG_CS0); - __raw_writel( M_NAND_GPMC_CONFIG2, GPMC_CONFIG2 + GPMC_CONFIG_CS0); - __raw_writel( M_NAND_GPMC_CONFIG3, GPMC_CONFIG3 + GPMC_CONFIG_CS0); - __raw_writel( M_NAND_GPMC_CONFIG4, GPMC_CONFIG4 + GPMC_CONFIG_CS0); - __raw_writel( M_NAND_GPMC_CONFIG5, GPMC_CONFIG5 + GPMC_CONFIG_CS0); - __raw_writel( M_NAND_GPMC_CONFIG6, GPMC_CONFIG6 + GPMC_CONFIG_CS0); - -#else /* CFG_ONENAND */ - __raw_writel( ONENAND_GPMC_CONFIG1, GPMC_CONFIG1 + GPMC_CONFIG_CS0); - __raw_writel( ONENAND_GPMC_CONFIG2, GPMC_CONFIG2 + GPMC_CONFIG_CS0); - __raw_writel( ONENAND_GPMC_CONFIG3, GPMC_CONFIG3 + GPMC_CONFIG_CS0); - __raw_writel( ONENAND_GPMC_CONFIG4, GPMC_CONFIG4 + GPMC_CONFIG_CS0); - __raw_writel( ONENAND_GPMC_CONFIG5, GPMC_CONFIG5 + GPMC_CONFIG_CS0); - __raw_writel( ONENAND_GPMC_CONFIG6, GPMC_CONFIG6 + GPMC_CONFIG_CS0); -#endif - - /* Enable the GPMC Mapping */ - __raw_writel(( ((OMAP34XX_GPMC_CS0_SIZE & 0xF)<<8) | - ((OMAP34XX_GPMC_CS0_MAP>>24) & 0x3F) | - (1<<6) ), (GPMC_CONFIG7 + GPMC_CONFIG_CS0)); - delay(2000); - -#ifdef CFG_NAND - if (nand_chip()){ -#ifdef CFG_PRINTF - printf("Unsupported Chip!\n"); -#endif - return 1; - } -#else - if (onenand_chip()){ -#ifdef CFG_PRINTF - printf("OneNAND Unsupported !\n"); -#endif - return 1; - } -#endif - return 0; -} - -/* optionally do something like blinking LED */ -void board_hang (void) -{ while (0) {};} diff --git a/x-loader/board/omap3430labrador/platform.S b/x-loader/board/omap3430labrador/platform.S deleted file mode 100644 index 5869270..0000000 --- a/x-loader/board/omap3430labrador/platform.S +++ /dev/null @@ -1,360 +0,0 @@ -/* - * Board specific setup info - * - * (C) Copyright 2004-2006 - * Texas Instruments, <www.ti.com> - * Richard Woodruff <r-woodruff2@ti.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <config.h> -#include <asm/arch/cpu.h> -#include <asm/arch/mem.h> -#include <asm/arch/clocks.h> - -_TEXT_BASE: - .word TEXT_BASE /* sdram load addr from config.mk */ - -#if !defined(CFG_NAND_BOOT) && !defined(CFG_NAND_BOOT) -/************************************************************************** - * cpy_clk_code: relocates clock code into SRAM where its safer to execute - * R1 = SRAM destination address. - *************************************************************************/ -.global cpy_clk_code - cpy_clk_code: - /* Copy DPLL code into SRAM */ - adr r0, go_to_speed /* get addr of clock setting code */ - mov r2, #384 /* r2 size to copy (div by 32 bytes) */ - mov r1, r1 /* r1 <- dest address (passed in) */ - add r2, r2, r0 /* r2 <- source end address */ -next2: - ldmia r0!, {r3-r10} /* copy from source address [r0] */ - stmia r1!, {r3-r10} /* copy to target address [r1] */ - cmp r0, r2 /* until source end address [r2] */ - bne next2 - mov pc, lr /* back to caller */ - -/* **************************************************************************** - * NOTE: 3430 X-loader currently does not use this code. -* It could be removed its is kept for compatabily with u-boot. - * - * go_to_speed: -Moves to bypass, -Commits clock dividers, -puts dpll at speed - * -executed from SRAM. - * R0 = CM_CLKEN_PLL-bypass value - * R1 = CM_CLKSEL1_PLL-m, n, and divider values - * R2 = CM_CLKSEL_CORE-divider values - * R3 = CM_IDLEST_CKGEN - addr dpll lock wait - * - * Note: If core unlocks/relocks and SDRAM is running fast already it gets - * confused. A reset of the controller gets it back. Taking away its - * L3 when its not in self refresh seems bad for it. Normally, this code - * runs from flash before SDR is init so that should be ok. - ******************************************************************************/ -.global go_to_speed - go_to_speed: - stmfd sp!, {r4-r6} - - /* move into fast relock bypass */ - ldr r4, pll_ctl_add - str r0, [r4] -wait1: - ldr r5, [r3] /* get status */ - and r5, r5, #0x1 /* isolate core status */ - cmp r5, #0x1 /* still locked? */ - beq wait1 /* if lock, loop */ - - /* set new dpll dividers _after_ in bypass */ - ldr r5, pll_div_add1 - str r1, [r5] /* set m, n, m2 */ - ldr r5, pll_div_add2 - str r2, [r5] /* set l3/l4/.. dividers*/ - ldr r5, pll_div_add3 /* wkup */ - ldr r2, pll_div_val3 /* rsm val */ - str r2, [r5] - ldr r5, pll_div_add4 /* gfx */ - ldr r2, pll_div_val4 - str r2, [r5] - ldr r5, pll_div_add5 /* emu */ - ldr r2, pll_div_val5 - str r2, [r5] - - /* now prepare GPMC (flash) for new dpll speed */ - /* flash needs to be stable when we jump back to it */ - ldr r5, flash_cfg3_addr - ldr r2, flash_cfg3_val - str r2, [r5] - ldr r5, flash_cfg4_addr - ldr r2, flash_cfg4_val - str r2, [r5] - ldr r5, flash_cfg5_addr - ldr r2, flash_cfg5_val - str r2, [r5] - ldr r5, flash_cfg1_addr - ldr r2, [r5] - orr r2, r2, #0x3 /* up gpmc divider */ - str r2, [r5] - - /* lock DPLL3 and wait a bit */ - orr r0, r0, #0x7 /* set up for lock mode */ - str r0, [r4] /* lock */ - nop /* ARM slow at this point working at sys_clk */ - nop - nop - nop -wait2: - ldr r5, [r3] /* get status */ - and r5, r5, #0x1 /* isolate core status */ - cmp r5, #0x1 /* still locked? */ - bne wait2 /* if lock, loop */ - nop - nop - nop - nop - ldmfd sp!, {r4-r6} - mov pc, lr /* back to caller, locked */ - -_go_to_speed: .word go_to_speed - -/* these constants need to be close for PIC code */ -/* The Nor has to be in the Flash Base CS0 for this condition to happen */ -flash_cfg1_addr: - .word (GPMC_CONFIG_CS0 + GPMC_CONFIG1) -flash_cfg3_addr: - .word (GPMC_CONFIG_CS0 + GPMC_CONFIG3) -flash_cfg3_val: - .word STNOR_GPMC_CONFIG3 -flash_cfg4_addr: - .word (GPMC_CONFIG_CS0 + GPMC_CONFIG4) -flash_cfg4_val: - .word STNOR_GPMC_CONFIG4 -flash_cfg5_val: - .word STNOR_GPMC_CONFIG5 -flash_cfg5_addr: - .word (GPMC_CONFIG_CS0 + GPMC_CONFIG5) -pll_ctl_add: - .word CM_CLKEN_PLL -pll_div_add1: - .word CM_CLKSEL1_PLL -pll_div_add2: - .word CM_CLKSEL_CORE -pll_div_add3: - .word CM_CLKSEL_WKUP -pll_div_val3: - .word (WKUP_RSM << 1) -pll_div_add4: - .word CM_CLKSEL_GFX -pll_div_val4: - .word (GFX_DIV << 0) -pll_div_add5: - .word CM_CLKSEL1_EMU -pll_div_val5: - .word CLSEL1_EMU_VAL - -#endif - -.globl lowlevel_init -lowlevel_init: - ldr sp, SRAM_STACK - str ip, [sp] /* stash old link register */ - mov ip, lr /* save link reg across call */ - bl s_init /* go setup pll,mux,memory */ - ldr ip, [sp] /* restore save ip */ - mov lr, ip /* restore link reg */ - - /* back to arch calling code */ - mov pc, lr - - /* the literal pools origin */ - .ltorg - -REG_CONTROL_STATUS: - .word CONTROL_STATUS -SRAM_STACK: - .word LOW_LEVEL_SRAM_STACK - -/* DPLL(1-4) PARAM TABLES */ -/* Each of the tables has M, N, FREQSEL, M2 values defined for nominal - * OPP (1.2V). The fields are defined according to dpll_param struct(clock.c). - * The values are defined for all possible sysclk and for ES1 and ES2. - */ - -mpu_dpll_param: -/* 12MHz */ -/* ES1 */ -.word 0x0FE,0x07,0x05,0x01 -/* ES2 */ -.word 0x0FA,0x05,0x07,0x01 -/* 3410 */ -.word 0x085,0x05,0x07,0x01 - -/* 13MHz */ -/* ES1 */ -.word 0x17D,0x0C,0x03,0x01 -/* ES2 */ -.word 0x1F4,0x0C,0x03,0x01 -/* 3410 */ -.word 0x10A,0x0C,0x03,0x01 - -/* 19.2MHz */ -/* ES1 */ -.word 0x179,0x12,0x04,0x01 -/* ES2 */ -.word 0x271,0x17,0x03,0x01 -/* 3410 */ -.word 0x14C,0x17,0x03,0x01 - -/* 26MHz */ -/* ES1 */ -.word 0x17D,0x19,0x03,0x01 -/* ES2 */ -.word 0x0FA,0x0C,0x07,0x01 -/* 3410 */ -.word 0x085,0x0C,0x07,0x01 - -/* 38.4MHz */ -/* ES1 */ -.word 0x1FA,0x32,0x03,0x01 -/* ES2 */ -.word 0x271,0x2F,0x03,0x01 -/* 3410 */ -.word 0x14C,0x2F,0x03,0x01 - - -.globl get_mpu_dpll_param -get_mpu_dpll_param: - adr r0, mpu_dpll_param - mov pc, lr - -iva_dpll_param: -/* 12MHz */ -/* ES1 */ -.word 0x07D,0x05,0x07,0x01 -/* ES2 */ -.word 0x0B4,0x05,0x07,0x01 -/* 3410 */ -.word 0x085,0x05,0x07,0x01 - -/* 13MHz */ -/* ES1 */ -.word 0x0FA,0x0C,0x03,0x01 -/* ES2 */ -.word 0x168,0x0C,0x03,0x01 -/* 3410 */ -.word 0x10A,0x0C,0x03,0x01 - -/* 19.2MHz */ -/* ES1 */ -.word 0x082,0x09,0x07,0x01 -/* ES2 */ -.word 0x0E1,0x0B,0x06,0x01 -/* 3410 */ -.word 0x14C,0x17,0x03,0x01 - -/* 26MHz */ -/* ES1 */ -.word 0x07D,0x0C,0x07,0x01 -/* ES2 */ -.word 0x0B4,0x0C,0x07,0x01 -/* 3410 */ -.word 0x085,0x0C,0x07,0x01 - -/* 38.4MHz */ -/* ES1 */ -.word 0x13F,0x30,0x03,0x01 -/* ES2 */ -.word 0x0E1,0x17,0x06,0x01 -/* 3410 */ -.word 0x14C,0x2F,0x03,0x01 - - -.globl get_iva_dpll_param -get_iva_dpll_param: - adr r0, iva_dpll_param - mov pc, lr - -/* Core DPLL targets for L3 at 166 & L133 */ -core_dpll_param: -/* 12MHz */ -/* ES1 */ -.word M_12_ES1,M_12_ES1,FSL_12_ES1,M2_12_ES1 -/* ES2 */ -.word M_12,N_12,FSEL_12,M2_12 -/* 3410 */ -.word M_12,N_12,FSEL_12,M2_12 - -/* 13MHz */ -/* ES1 */ -.word M_13_ES1,N_13_ES1,FSL_13_ES1,M2_13_ES1 -/* ES2 */ -.word M_13,N_13,FSEL_13,M2_13 -/* 3410 */ -.word M_13,N_13,FSEL_13,M2_13 - -/* 19.2MHz */ -/* ES1 */ -.word M_19p2_ES1,N_19p2_ES1,FSL_19p2_ES1,M2_19p2_ES1 -/* ES2 */ -.word M_19p2,N_19p2,FSEL_19p2,M2_19p2 -/* 3410 */ -.word M_19p2,N_19p2,FSEL_19p2,M2_19p2 - -/* 26MHz */ -/* ES1 */ -.word M_26_ES1,N_26_ES1,FSL_26_ES1,M2_26_ES1 -/* ES2 */ -.word M_26,N_26,FSEL_26,M2_26 -/* 3410 */ -.word M_26,N_26,FSEL_26,M2_26 - -/* 38.4MHz */ -/* ES1 */ -.word M_38p4_ES1,N_38p4_ES1,FSL_38p4_ES1,M2_38p4_ES1 -/* ES2 */ -.word M_38p4,N_38p4,FSEL_38p4,M2_38p4 -/* 3410 */ -.word M_38p4,N_38p4,FSEL_38p4,M2_38p4 - -.globl get_core_dpll_param -get_core_dpll_param: - adr r0, core_dpll_param - mov pc, lr - -/* PER DPLL values are same for both ES1 and ES2 */ -per_dpll_param: -/* 12MHz */ -.word 0xD8,0x05,0x07,0x09 - -/* 13MHz */ -.word 0x1B0,0x0C,0x03,0x09 - -/* 19.2MHz */ -.word 0xE1,0x09,0x07,0x09 - -/* 26MHz */ -.word 0xD8,0x0C,0x07,0x09 - -/* 38.4MHz */ -.word 0xE1,0x13,0x07,0x09 - -.globl get_per_dpll_param -get_per_dpll_param: - adr r0, per_dpll_param - mov pc, lr - diff --git a/x-loader/board/omap3430labrador/x-load.lds b/x-loader/board/omap3430labrador/x-load.lds deleted file mode 100644 index 9402f74..0000000 --- a/x-loader/board/omap3430labrador/x-load.lds +++ /dev/null @@ -1,54 +0,0 @@ -/* - * November 2006 - Changed to support 3430sdp device - * Copyright (c) 2004-2006 Texas Instruments - * - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, <gj@denx.de> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN(4); - .text : - { - cpu/omap3/start.o (.text) - *(.text) - } - - . = ALIGN(4); - .rodata : { *(.rodata) } - - . = ALIGN(4); - .data : { *(.data) } - - . = ALIGN(4); - .got : { *(.got) } - - . = ALIGN(4); - __bss_start = .; - .bss : { *(.bss) } - _end = .; -} diff --git a/x-loader/board/omap3430sdp/Makefile b/x-loader/board/omap3430sdp/Makefile deleted file mode 100644 index d54b666..0000000 --- a/x-loader/board/omap3430sdp/Makefile +++ /dev/null @@ -1,51 +0,0 @@ -# -# (C) Copyright 2000, 2001, 2002 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).a - -COBJS := omap3430sdp.o -SOBJS := platform.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) $(SOBJS) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak $(obj).depend - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/x-loader/board/omap3430sdp/config.mk b/x-loader/board/omap3430sdp/config.mk deleted file mode 100644 index d6ad6c5..0000000 --- a/x-loader/board/omap3430sdp/config.mk +++ /dev/null @@ -1,22 +0,0 @@ -# -# (C) Copyright 2006 -# Texas Instruments, <www.ti.com> -# -# SDP3430 board uses OMAP3430 (ARM-CortexA8) cpu -# see http://www.ti.com/ for more information on Texas Instruments -# -# SDP3430 has 1 bank of 32MB or 128MB mDDR-SDRAM on CS0 -# SDP3430 has 1 bank of 32MB or 00MB mDDR-SDRAM on CS1 -# Physical Address: -# 8000'0000 (bank0) -# A000'0000 (bank1) - re-mappable below CS1 - -# For use if you want X-Loader to relocate from SRAM to DDR -#TEXT_BASE = 0x80e80000 - -# For XIP in 64K of SRAM or debug (GP device has it all availabe) -# SRAM 40200000-4020FFFF base -# initial stack at 0x4020fffc used in s_init (below xloader). -# The run time stack is (above xloader, 2k below) -# If any globals exist there needs to be room for them also -TEXT_BASE = 0x40208800 diff --git a/x-loader/board/omap3430sdp/omap3430sdp.c b/x-loader/board/omap3430sdp/omap3430sdp.c deleted file mode 100644 index 6ed62bc..0000000 --- a/x-loader/board/omap3430sdp/omap3430sdp.c +++ /dev/null @@ -1,779 +0,0 @@ -/* - * (C) Copyright 2006 - * Texas Instruments, <www.ti.com> - * Jian Zhang <jzhang@ti.com> - * Richard Woodruff <r-woodruff2@ti.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#include <common.h> -#include <command.h> -#include <part.h> -#include <fat.h> -#include <asm/arch/cpu.h> -#include <asm/arch/bits.h> -#include <asm/arch/mux.h> -#include <asm/arch/sys_proto.h> -#include <asm/arch/sys_info.h> -#include <asm/arch/clocks.h> -#include <asm/arch/mem.h> - -/* Used to index into DPLL parameter tables */ -struct dpll_param { - unsigned int m; - unsigned int n; - unsigned int fsel; - unsigned int m2; -}; - -typedef struct dpll_param dpll_param; - -#define MAX_SIL_INDEX 3 - -/* Following functions are exported from lowlevel_init.S */ -extern dpll_param * get_mpu_dpll_param(); -extern dpll_param * get_iva_dpll_param(); -extern dpll_param * get_core_dpll_param(); -extern dpll_param * get_per_dpll_param(); - -#define __raw_readl(a) (*(volatile unsigned int *)(a)) -#define __raw_writel(v,a) (*(volatile unsigned int *)(a) = (v)) -#define __raw_readw(a) (*(volatile unsigned short *)(a)) -#define __raw_writew(v,a) (*(volatile unsigned short *)(a) = (v)) - -/******************************************************* - * Routine: delay - * Description: spinning delay to use before udelay works - ******************************************************/ -static inline void delay(unsigned long loops) -{ - __asm__ volatile ("1:\n" "subs %0, %1, #1\n" - "bne 1b":"=r" (loops):"0"(loops)); -} - -/***************************************** - * Routine: board_init - * Description: Early hardware init. - *****************************************/ -int board_init (void) -{ - return 0; -} - -/************************************************************* - * get_device_type(): tell if GP/HS/EMU/TST - *************************************************************/ -u32 get_device_type(void) -{ - int mode; - mode = __raw_readl(CONTROL_STATUS) & (DEVICE_MASK); - return(mode >>= 8); -} - -/****************************************** - * get_cpu_rev(void) - extract version info - ******************************************/ -u32 get_cpu_rev(void) -{ - u32 cpuid=0; - /* On ES1.0 the IDCODE register is not exposed on L4 - * so using CPU ID to differentiate - * between ES2.0 and ES1.0. - */ - __asm__ __volatile__("mrc p15, 0, %0, c0, c0, 0":"=r" (cpuid)); - if((cpuid & 0xf) == 0x0) - return CPU_3430_ES1; - else - return CPU_3430_ES2; - -} - -/****************************************** - * cpu_is_3410(void) - returns true for 3410 - ******************************************/ -u32 cpu_is_3410(void) -{ - int status; - if(get_cpu_rev() < CPU_3430_ES2) { - return 0; - } else { - /* read scalability status and return 1 for 3410*/ - status = __raw_readl(CONTROL_SCALABLE_OMAP_STATUS); - /* Check whether MPU frequency is set to 266 MHz which - * is nominal for 3410. If yes return true else false - */ - if (((status >> 8) & 0x3) == 0x2) - return 1; - else - return 0; - } -} - -/***************************************************************** - * sr32 - clear & set a value in a bit range for a 32 bit address - *****************************************************************/ -void sr32(u32 addr, u32 start_bit, u32 num_bits, u32 value) -{ - u32 tmp, msk = 0; - msk = 1 << num_bits; - --msk; - tmp = __raw_readl(addr) & ~(msk << start_bit); - tmp |= value << start_bit; - __raw_writel(tmp, addr); -} - -/********************************************************************* - * wait_on_value() - common routine to allow waiting for changes in - * volatile regs. - *********************************************************************/ -u32 wait_on_value(u32 read_bit_mask, u32 match_value, u32 read_addr, u32 bound) -{ - u32 i = 0, val; - do { - ++i; - val = __raw_readl(read_addr) & read_bit_mask; - if (val == match_value) - return (1); - if (i == bound) - return (0); - } while (1); -} - -#ifdef CFG_3430SDRAM_DDR -/********************************************************************* - * config_3430sdram_ddr() - Init DDR on 3430SDP dev board. - *********************************************************************/ -void config_3430sdram_ddr(void) -{ - /* reset sdrc controller */ - __raw_writel(SOFTRESET, SDRC_SYSCONFIG); - wait_on_value(BIT0, BIT0, SDRC_STATUS, 12000000); - __raw_writel(0, SDRC_SYSCONFIG); - - /* setup sdrc to ball mux */ - __raw_writel(SDP_SDRC_SHARING, SDRC_SHARING); - - /* set mdcfg */ - __raw_writel(SDP_SDRC_MDCFG_0_DDR, SDRC_MCFG_0); - - /* set timing */ - __raw_writel(SDP_SDRC_ACTIM_CTRLA_0, SDRC_ACTIM_CTRLA_0); - __raw_writel(SDP_SDRC_ACTIM_CTRLB_0, SDRC_ACTIM_CTRLB_0); - __raw_writel(SDP_SDRC_RFR_CTRL, SDRC_RFR_CTRL); - - /* init sequence for mDDR/mSDR using manual commands (DDR is different) */ - __raw_writel(CMD_NOP, SDRC_MANUAL_0); - delay(5000); - __raw_writel(CMD_PRECHARGE, SDRC_MANUAL_0); - __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0); - __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0); - - /* set mr0 */ - __raw_writel(SDP_SDRC_MR_0_DDR, SDRC_MR_0); - - /* set up dll */ - __raw_writel(SDP_SDRC_DLLAB_CTRL, SDRC_DLLA_CTRL); - delay(0x2000); /* give time to lock */ - -} -#endif // CFG_3430SDRAM_DDR - -/************************************************************* - * get_sys_clk_speed - determine reference oscillator speed - * based on known 32kHz clock and gptimer. - *************************************************************/ -u32 get_osc_clk_speed(void) -{ - u32 start, cstart, cend, cdiff, val; - - val = __raw_readl(PRM_CLKSRC_CTRL); - /* If SYS_CLK is being divided by 2, remove for now */ - val = (val & (~BIT7)) | BIT6; - __raw_writel(val, PRM_CLKSRC_CTRL); - - /* enable timer2 */ - val = __raw_readl(CM_CLKSEL_WKUP) | BIT0; - __raw_writel(val, CM_CLKSEL_WKUP); /* select sys_clk for GPT1 */ - - /* Enable I and F Clocks for GPT1 */ - val = __raw_readl(CM_ICLKEN_WKUP) | BIT0 | BIT2; - __raw_writel(val, CM_ICLKEN_WKUP); - val = __raw_readl(CM_FCLKEN_WKUP) | BIT0; - __raw_writel(val, CM_FCLKEN_WKUP); - - __raw_writel(0, OMAP34XX_GPT1 + TLDR); /* start counting at 0 */ - __raw_writel(GPT_EN, OMAP34XX_GPT1 + TCLR); /* enable clock */ - /* enable 32kHz source *//* enabled out of reset */ - /* determine sys_clk via gauging */ - - start = 20 + __raw_readl(S32K_CR); /* start time in 20 cycles */ - while (__raw_readl(S32K_CR) < start); /* dead loop till start time */ - cstart = __raw_readl(OMAP34XX_GPT1 + TCRR); /* get start sys_clk count */ - while (__raw_readl(S32K_CR) < (start + 20)); /* wait for 40 cycles */ - cend = __raw_readl(OMAP34XX_GPT1 + TCRR); /* get end sys_clk count */ - cdiff = cend - cstart; /* get elapsed ticks */ - - /* based on number of ticks assign speed */ - if (cdiff > 19000) - return (S38_4M); - else if (cdiff > 15200) - return (S26M); - else if (cdiff > 13000) - return (S24M); - else if (cdiff > 9000) - return (S19_2M); - else if (cdiff > 7600) - return (S13M); - else - return (S12M); -} - -/****************************************************************************** - * get_sys_clkin_sel() - returns the sys_clkin_sel field value based on - * -- input oscillator clock frequency. - * - *****************************************************************************/ -void get_sys_clkin_sel(u32 osc_clk, u32 *sys_clkin_sel) -{ - if(osc_clk == S38_4M) - *sys_clkin_sel= 4; - else if(osc_clk == S26M) - *sys_clkin_sel = 3; - else if(osc_clk == S19_2M) - *sys_clkin_sel = 2; - else if(osc_clk == S13M) - *sys_clkin_sel = 1; - else if(osc_clk == S12M) - *sys_clkin_sel = 0; -} - -/****************************************************************************** - * prcm_init() - inits clocks for PRCM as defined in clocks.h - * -- called from SRAM, or Flash (using temp SRAM stack). - *****************************************************************************/ -void prcm_init(void) -{ - u32 osc_clk=0, sys_clkin_sel; - dpll_param *dpll_param_p; - u32 clk_index, sil_index; - - /* Gauge the input clock speed and find out the sys_clkin_sel - * value corresponding to the input clock. - */ - osc_clk = get_osc_clk_speed(); - get_sys_clkin_sel(osc_clk, &sys_clkin_sel); - - sr32(PRM_CLKSEL, 0, 3, sys_clkin_sel); /* set input crystal speed */ - - /* If the input clock is greater than 19.2M always divide/2 */ - if(sys_clkin_sel > 2) { - sr32(PRM_CLKSRC_CTRL, 6, 2, 2);/* input clock divider */ - clk_index = sys_clkin_sel/2; - } else { - sr32(PRM_CLKSRC_CTRL, 6, 2, 1);/* input clock divider */ - clk_index = sys_clkin_sel; - } - - /* The DPLL tables are defined according to sysclk value and - * silicon revision. The clk_index value will be used to get - * the values for that input sysclk from the DPLL param table - * and sil_index will get the values for that SysClk for the - * appropriate silicon rev. - */ - if(cpu_is_3410()) - sil_index = 2; - else { - if(get_cpu_rev() == CPU_3430_ES1) - sil_index = 0; - else if(get_cpu_rev() == CPU_3430_ES2) - sil_index = 1; - } - - /* Unlock MPU DPLL (slows things down, and needed later) */ - sr32(CM_CLKEN_PLL_MPU, 0, 3, PLL_LOW_POWER_BYPASS); - wait_on_value(BIT0, 0, CM_IDLEST_PLL_MPU, LDELAY); - - /* Getting the base address of Core DPLL param table*/ - dpll_param_p = (dpll_param *)get_core_dpll_param(); - /* Moving it to the right sysclk and ES rev base */ - dpll_param_p = dpll_param_p + MAX_SIL_INDEX*clk_index + sil_index; - /* CORE DPLL */ - /* sr32(CM_CLKSEL2_EMU) set override to work when asleep */ - sr32(CM_CLKEN_PLL, 0, 3, PLL_FAST_RELOCK_BYPASS); - wait_on_value(BIT0, 0, CM_IDLEST_CKGEN, LDELAY); - sr32(CM_CLKSEL1_EMU, 16, 5, CORE_M3X2); /* m3x2 */ - sr32(CM_CLKSEL1_PLL, 27, 2, dpll_param_p->m2); /* Set M2 */ - sr32(CM_CLKSEL1_PLL, 16, 11, dpll_param_p->m); /* Set M */ - sr32(CM_CLKSEL1_PLL, 8, 7, dpll_param_p->n); /* Set N */ - sr32(CM_CLKSEL1_PLL, 6, 1, 0); /* 96M Src */ - sr32(CM_CLKSEL_CORE, 8, 4, CORE_SSI_DIV); /* ssi */ - sr32(CM_CLKSEL_CORE, 4, 2, CORE_FUSB_DIV); /* fsusb */ - sr32(CM_CLKSEL_CORE, 2, 2, CORE_L4_DIV); /* l4 */ - sr32(CM_CLKSEL_CORE, 0, 2, CORE_L3_DIV); /* l3 */ - sr32(CM_CLKSEL_GFX, 0, 3, GFX_DIV); /* gfx */ - sr32(CM_CLKSEL_WKUP, 1, 2, WKUP_RSM); /* reset mgr */ - sr32(CM_CLKEN_PLL, 4, 4, dpll_param_p->fsel); /* FREQSEL */ - sr32(CM_CLKEN_PLL, 0, 3, PLL_LOCK); /* lock mode */ - wait_on_value(BIT0, 1, CM_IDLEST_CKGEN, LDELAY); - - /* Getting the base address to PER DPLL param table*/ - dpll_param_p = (dpll_param *)get_per_dpll_param(); - /* Moving it to the right sysclk base */ - dpll_param_p = dpll_param_p + clk_index; - /* PER DPLL */ - sr32(CM_CLKEN_PLL, 16, 3, PLL_STOP); - wait_on_value(BIT1, 0, CM_IDLEST_CKGEN, LDELAY); - sr32(CM_CLKSEL1_EMU, 24, 5, PER_M6X2); /* set M6 */ - sr32(CM_CLKSEL_CAM, 0, 5, PER_M5X2); /* set M5 */ - sr32(CM_CLKSEL_DSS, 0, 5, PER_M4X2); /* set M4 */ - sr32(CM_CLKSEL_DSS, 8, 5, PER_M3X2); /* set M3 */ - sr32(CM_CLKSEL3_PLL, 0, 5, dpll_param_p->m2); /* set M2 */ - sr32(CM_CLKSEL2_PLL, 8, 11, dpll_param_p->m); /* set m */ - sr32(CM_CLKSEL2_PLL, 0, 7, dpll_param_p->n); /* set n */ - sr32(CM_CLKEN_PLL, 20, 4, dpll_param_p->fsel);/* FREQSEL */ - sr32(CM_CLKEN_PLL, 16, 3, PLL_LOCK); /* lock mode */ - wait_on_value(BIT1, 2, CM_IDLEST_CKGEN, LDELAY); - - /* Getting the base address to MPU DPLL param table*/ - dpll_param_p = (dpll_param *)get_mpu_dpll_param(); - /* Moving it to the right sysclk and ES rev base */ - dpll_param_p = dpll_param_p + MAX_SIL_INDEX*clk_index + sil_index; - /* MPU DPLL (unlocked already) */ - sr32(CM_CLKSEL2_PLL_MPU, 0, 5, dpll_param_p->m2); /* Set M2 */ - sr32(CM_CLKSEL1_PLL_MPU, 8, 11, dpll_param_p->m); /* Set M */ - sr32(CM_CLKSEL1_PLL_MPU, 0, 7, dpll_param_p->n); /* Set N */ - sr32(CM_CLKEN_PLL_MPU, 4, 4, dpll_param_p->fsel); /* FREQSEL */ - sr32(CM_CLKEN_PLL_MPU, 0, 3, PLL_LOCK); /* lock mode */ - wait_on_value(BIT0, 1, CM_IDLEST_PLL_MPU, LDELAY); - - /* Getting the base address to IVA DPLL param table*/ - dpll_param_p = (dpll_param *)get_iva_dpll_param(); - /* Moving it to the right sysclk and ES rev base */ - dpll_param_p = dpll_param_p + MAX_SIL_INDEX*clk_index + sil_index; - /* IVA DPLL (set to 12*20=240MHz) */ - sr32(CM_CLKEN_PLL_IVA2, 0, 3, PLL_STOP); - wait_on_value(BIT0, 0, CM_IDLEST_PLL_IVA2, LDELAY); - sr32(CM_CLKSEL2_PLL_IVA2, 0, 5, dpll_param_p->m2); /* set M2 */ - sr32(CM_CLKSEL1_PLL_IVA2, 8, 11, dpll_param_p->m); /* set M */ - sr32(CM_CLKSEL1_PLL_IVA2, 0, 7, dpll_param_p->n); /* set N */ - sr32(CM_CLKEN_PLL_IVA2, 4, 4, dpll_param_p->fsel); /* FREQSEL */ - sr32(CM_CLKEN_PLL_IVA2, 0, 3, PLL_LOCK); /* lock mode */ - wait_on_value(BIT0, 1, CM_IDLEST_PLL_IVA2, LDELAY); - - /* Set up GPTimers to sys_clk source only */ - sr32(CM_CLKSEL_PER, 0, 8, 0xff); - sr32(CM_CLKSEL_WKUP, 0, 1, 1); - - delay(5000); -} - -/***************************************** - * Routine: secure_unlock - * Description: Setup security registers for access - * (GP Device only) - *****************************************/ -void secure_unlock(void) -{ - /* Permission values for registers -Full fledged permissions to all */ - #define UNLOCK_1 0xFFFFFFFF - #define UNLOCK_2 0x00000000 - #define UNLOCK_3 0x0000FFFF - /* Protection Module Register Target APE (PM_RT)*/ - __raw_writel(UNLOCK_1, RT_REQ_INFO_PERMISSION_1); - __raw_writel(UNLOCK_1, RT_READ_PERMISSION_0); - __raw_writel(UNLOCK_1, RT_WRITE_PERMISSION_0); - __raw_writel(UNLOCK_2, RT_ADDR_MATCH_1); - - __raw_writel(UNLOCK_3, GPMC_REQ_INFO_PERMISSION_0); - __raw_writel(UNLOCK_3, GPMC_READ_PERMISSION_0); - __raw_writel(UNLOCK_3, GPMC_WRITE_PERMISSION_0); - - __raw_writel(UNLOCK_3, OCM_REQ_INFO_PERMISSION_0); - __raw_writel(UNLOCK_3, OCM_READ_PERMISSION_0); - __raw_writel(UNLOCK_3, OCM_WRITE_PERMISSION_0); - __raw_writel(UNLOCK_2, OCM_ADDR_MATCH_2); - - /* IVA Changes */ - __raw_writel(UNLOCK_3, IVA2_REQ_INFO_PERMISSION_0); - __raw_writel(UNLOCK_3, IVA2_READ_PERMISSION_0); - __raw_writel(UNLOCK_3, IVA2_WRITE_PERMISSION_0); - - __raw_writel(UNLOCK_1, SMS_RG_ATT0); /* SDRC region 0 public */ -} - -/********************************************************** - * Routine: try_unlock_sram() - * Description: If chip is GP type, unlock the SRAM for - * general use. - ***********************************************************/ -void try_unlock_memory(void) -{ - int mode; - - /* if GP device unlock device SRAM for general use */ - /* secure code breaks for Secure/Emulation device - HS/E/T*/ - mode = get_device_type(); - if (mode == GP_DEVICE) { - secure_unlock(); - } - return; -} - -/********************************************************** - * Routine: s_init - * Description: Does early system init of muxing and clocks. - * - Called at time when only stack is available. - **********************************************************/ - -void s_init(void) -{ - watchdog_init(); -#ifdef CONFIG_3430_AS_3410 - /* setup the scalability control register for - * 3430 to work in 3410 mode - */ - __raw_writel(0x5ABF,CONTROL_SCALABLE_OMAP_OCP); -#endif - try_unlock_memory(); - set_muxconf_regs(); - delay(100); - prcm_init(); - per_clocks_enable(); - config_3430sdram_ddr(); -} - -/******************************************************* - * Routine: misc_init_r - * Description: Init ethernet (done here so udelay works) - ********************************************************/ -int misc_init_r (void) -{ - return(0); -} - -/****************************************************** - * Routine: wait_for_command_complete - * Description: Wait for posting to finish on watchdog - ******************************************************/ -void wait_for_command_complete(unsigned int wd_base) -{ - int pending = 1; - do { - pending = __raw_readl(wd_base + WWPS); - } while (pending); -} - -/**************************************** - * Routine: watchdog_init - * Description: Shut down watch dogs - *****************************************/ -void watchdog_init(void) -{ - /* There are 3 watch dogs WD1=Secure, WD2=MPU, WD3=IVA. WD1 is - * either taken care of by ROM (HS/EMU) or not accessible (GP). - * We need to take care of WD2-MPU or take a PRCM reset. WD3 - * should not be running and does not generate a PRCM reset. - */ - sr32(CM_FCLKEN_WKUP, 5, 1, 1); - sr32(CM_ICLKEN_WKUP, 5, 1, 1); - wait_on_value(BIT5, 0x20, CM_IDLEST_WKUP, 5); /* some issue here */ - - __raw_writel(WD_UNLOCK1, WD2_BASE + WSPR); - wait_for_command_complete(WD2_BASE); - __raw_writel(WD_UNLOCK2, WD2_BASE + WSPR); -} - -/********************************************** - * Routine: dram_init - * Description: sets uboots idea of sdram size - **********************************************/ -int dram_init (void) -{ - return 0; -} - -/***************************************************************** - * Routine: peripheral_enable - * Description: Enable the clks & power for perifs (GPT2, UART1,...) - ******************************************************************/ -void per_clocks_enable(void) -{ - /* Enable GP2 timer. */ - sr32(CM_CLKSEL_PER, 0, 1, 0x1); /* GPT2 = sys clk */ - sr32(CM_ICLKEN_PER, 3, 1, 0x1); /* ICKen GPT2 */ - sr32(CM_FCLKEN_PER, 3, 1, 0x1); /* FCKen GPT2 */ - -#ifdef CFG_NS16550 - /* Enable UART1 clocks */ - sr32(CM_FCLKEN1_CORE, 13, 1, 0x1); - sr32(CM_ICLKEN1_CORE, 13, 1, 0x1); -#endif - delay(1000); -} - -/* Set MUX for UART, GPMC, SDRC, GPIO */ - -#define MUX_VAL(OFFSET,VALUE)\ - __raw_writew((VALUE), OMAP34XX_CTRL_BASE + (OFFSET)); - -#define CP(x) (CONTROL_PADCONF_##x) -/* - * IEN - Input Enable - * IDIS - Input Disable - * PTD - Pull type Down - * PTU - Pull type Up - * DIS - Pull type selection is inactive - * EN - Pull type selection is active - * M0 - Mode 0 - * The commented string gives the final mux configuration for that pin - */ -#define MUX_DEFAULT()\ - MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /*SDRC_D0*/\ - MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /*SDRC_D1*/\ - MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /*SDRC_D2*/\ - MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /*SDRC_D3*/\ - MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /*SDRC_D4*/\ - MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /*SDRC_D5*/\ - MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /*SDRC_D6*/\ - MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /*SDRC_D7*/\ - MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /*SDRC_D8*/\ - MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /*SDRC_D9*/\ - MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /*SDRC_D10*/\ - MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /*SDRC_D11*/\ - MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /*SDRC_D12*/\ - MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /*SDRC_D13*/\ - MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /*SDRC_D14*/\ - MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /*SDRC_D15*/\ - MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /*SDRC_D16*/\ - MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /*SDRC_D17*/\ - MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /*SDRC_D18*/\ - MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /*SDRC_D19*/\ - MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /*SDRC_D20*/\ - MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /*SDRC_D21*/\ - MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /*SDRC_D22*/\ - MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /*SDRC_D23*/\ - MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /*SDRC_D24*/\ - MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /*SDRC_D25*/\ - MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /*SDRC_D26*/\ - MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /*SDRC_D27*/\ - MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /*SDRC_D28*/\ - MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /*SDRC_D29*/\ - MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /*SDRC_D30*/\ - MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /*SDRC_D31*/\ - MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /*SDRC_CLK*/\ - MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /*SDRC_DQS0*/\ - MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /*SDRC_DQS1*/\ - MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /*SDRC_DQS2*/\ - MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /*SDRC_DQS3*/\ - MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0)) /*GPMC_A1*/\ - MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0)) /*GPMC_A2*/\ - MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0)) /*GPMC_A3*/\ - MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0)) /*GPMC_A4*/\ - MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0)) /*GPMC_A5*/\ - MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0)) /*GPMC_A6*/\ - MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0)) /*GPMC_A7*/\ - MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0)) /*GPMC_A8*/\ - MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M0)) /*GPMC_A9*/\ - MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0)) /*GPMC_A10*/\ - MUX_VAL(CP(GPMC_D0), (IEN | PTD | DIS | M0)) /*GPMC_D0*/\ - MUX_VAL(CP(GPMC_D1), (IEN | PTD | DIS | M0)) /*GPMC_D1*/\ - MUX_VAL(CP(GPMC_D2), (IEN | PTD | DIS | M0)) /*GPMC_D2*/\ - MUX_VAL(CP(GPMC_D3), (IEN | PTD | DIS | M0)) /*GPMC_D3*/\ - MUX_VAL(CP(GPMC_D4), (IEN | PTD | DIS | M0)) /*GPMC_D4*/\ - MUX_VAL(CP(GPMC_D5), (IEN | PTD | DIS | M0)) /*GPMC_D5*/\ - MUX_VAL(CP(GPMC_D6), (IEN | PTD | DIS | M0)) /*GPMC_D6*/\ - MUX_VAL(CP(GPMC_D7), (IEN | PTD | DIS | M0)) /*GPMC_D7*/\ - MUX_VAL(CP(GPMC_D8), (IEN | PTD | DIS | M0)) /*GPMC_D8*/\ - MUX_VAL(CP(GPMC_D9), (IEN | PTD | DIS | M0)) /*GPMC_D9*/\ - MUX_VAL(CP(GPMC_D10), (IEN | PTD | DIS | M0)) /*GPMC_D10*/\ - MUX_VAL(CP(GPMC_D11), (IEN | PTD | DIS | M0)) /*GPMC_D11*/\ - MUX_VAL(CP(GPMC_D12), (IEN | PTD | DIS | M0)) /*GPMC_D12*/\ - MUX_VAL(CP(GPMC_D13), (IEN | PTD | DIS | M0)) /*GPMC_D13*/\ - MUX_VAL(CP(GPMC_D14), (IEN | PTD | DIS | M0)) /*GPMC_D14*/\ - MUX_VAL(CP(GPMC_D15), (IEN | PTD | DIS | M0)) /*GPMC_D15*/\ - MUX_VAL(CP(GPMC_nCS0), (IDIS | PTU | EN | M0)) /*GPMC_nCS0*/\ - MUX_VAL(CP(GPMC_nCS1), (IDIS | PTU | EN | M0)) /*GPMC_nCS1*/\ - MUX_VAL(CP(GPMC_nCS2), (IDIS | PTU | EN | M0)) /*GPMC_nCS2*/\ - MUX_VAL(CP(GPMC_nCS3), (IDIS | PTU | EN | M0)) /*GPMC_nCS3*/\ - MUX_VAL(CP(GPMC_nCS4), (IDIS | PTU | EN | M0)) /*GPMC_nCS4*/\ - MUX_VAL(CP(GPMC_nCS5), (IDIS | PTU | EN | M0)) /*GPMC_nCS5*/\ - MUX_VAL(CP(GPMC_nCS6), (IDIS | PTU | EN | M0)) /*GPMC_nCS6*/\ - MUX_VAL(CP(GPMC_nCS7), (IDIS | PTU | EN | M0)) /*GPMC_nCS7*/\ - MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M0)) /*GPMC_CLK*/\ - MUX_VAL(CP(GPMC_nADV_ALE), (IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\ - MUX_VAL(CP(GPMC_nOE), (IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\ - MUX_VAL(CP(GPMC_nWE), (IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\ - MUX_VAL(CP(GPMC_nBE0_CLE), (IDIS | PTD | DIS | M0)) /*GPMC_nBE0_CLE*/\ - MUX_VAL(CP(GPMC_nBE1), (IDIS | PTD | DIS | M4)) /*GPIO_61*/\ - MUX_VAL(CP(GPMC_nWP), (IEN | PTD | DIS | M0)) /*GPMC_nWP*/\ - MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) /*GPMC_WAIT0*/\ - MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)) /*GPMC_WAIT1*/\ - MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4)) /*GPIO_64*/\ - MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M4)) /*GPIO_65*/\ - MUX_VAL(CP(DSS_DATA18), (IEN | PTD | DIS | M4)) /*GPIO_88*/\ - MUX_VAL(CP(DSS_DATA19), (IEN | PTD | DIS | M4)) /*GPIO_89*/\ - MUX_VAL(CP(DSS_DATA20), (IEN | PTD | DIS | M4)) /*GPIO_90*/\ - MUX_VAL(CP(DSS_DATA21), (IEN | PTD | DIS | M4)) /*GPIO_91*/\ - MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4)) /*GPIO_167*/\ - MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /*UART1_TX*/\ - MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0)) /*UART1_RTS*/\ - MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M0)) /*UART1_CTS*/\ - MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /*UART1_RX*/\ - MUX_VAL(CP(McBSP1_DX), (IEN | PTD | DIS | M4)) /*GPIO_158*/\ - MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) /*SYS_32K*/\ - MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /*GPIO_2 */\ - MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) /*GPIO_3 */\ - MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /*GPIO_4 */\ - MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) /*GPIO_5 */\ - MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /*GPIO_6 */\ - MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /*GPIO_7 */\ - MUX_VAL(CP(SYS_BOOT6), (IEN | PTD | DIS | M4)) /*GPIO_8 */\ - MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M4)) /*GPIO_186*/\ - MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0)) /*JTAG_nTRST*/\ - MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)) /*JTAG_TCK*/\ - MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)) /*JTAG_TMS*/\ - MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)) /*JTAG_TDI*/\ - MUX_VAL(CP(JTAG_EMU0), (IEN | PTD | DIS | M0)) /*JTAG_EMU0*/\ - MUX_VAL(CP(JTAG_EMU1), (IEN | PTD | DIS | M0)) /*JTAG_EMU1*/\ - MUX_VAL(CP(ETK_CLK), (IEN | PTD | DIS | M4)) /*GPIO_12*/\ - MUX_VAL(CP(ETK_CTL), (IEN | PTD | DIS | M4)) /*GPIO_13*/\ - MUX_VAL(CP(ETK_D0 ), (IEN | PTD | DIS | M4)) /*GPIO_14*/\ - MUX_VAL(CP(ETK_D1 ), (IEN | PTD | DIS | M4)) /*GPIO_15*/\ - MUX_VAL(CP(ETK_D2 ), (IEN | PTD | DIS | M4)) /*GPIO_16*/\ - MUX_VAL(CP(ETK_D10), (IEN | PTD | DIS | M4)) /*GPIO_24*/\ - MUX_VAL(CP(ETK_D11), (IEN | PTD | DIS | M4)) /*GPIO_25*/\ - MUX_VAL(CP(ETK_D12), (IEN | PTD | DIS | M4)) /*GPIO_26*/\ - MUX_VAL(CP(ETK_D13), (IEN | PTD | DIS | M4)) /*GPIO_27*/\ - MUX_VAL(CP(ETK_D14), (IEN | PTD | DIS | M4)) /*GPIO_28*/\ - MUX_VAL(CP(ETK_D15), (IEN | PTD | DIS | M4)) /*GPIO_29*/ - -/********************************************************** - * Routine: set_muxconf_regs - * Description: Setting up the configuration Mux registers - * specific to the hardware. Many pins need - * to be moved from protect to primary mode. - *********************************************************/ -void set_muxconf_regs(void) -{ - MUX_DEFAULT(); -} - -/********************************************************** - * Routine: nand+_init - * Description: Set up nand for nand and jffs2 commands - *********************************************************/ -int nand_init(void) -{ - /* global settings */ - __raw_writel(0x10, GPMC_SYSCONFIG); /* smart idle */ - __raw_writel(0x0, GPMC_IRQENABLE); /* isr's sources masked */ - __raw_writel(0, GPMC_TIMEOUT_CONTROL);/* timeout disable */ -#ifdef CFG_NAND - __raw_writel(0x001, GPMC_CONFIG); /* set nWP, disable limited addr */ -#endif - - /* Set the GPMC Vals . For NAND boot on 3430SDP, NAND is mapped at CS0 - * , NOR at CS1 and MPDB at CS3. And oneNAND boot, we map oneNAND at CS0. - * We configure only GPMC CS0 with required values. Configiring other devices - * at other CS in done in u-boot anyway. So we don't have to bother doing it here. - */ - __raw_writel(0 , GPMC_CONFIG7 + GPMC_CONFIG_CS0); - delay(1000); - -#ifdef CFG_NAND - __raw_writel( SMNAND_GPMC_CONFIG1, GPMC_CONFIG1 + GPMC_CONFIG_CS0); - __raw_writel( SMNAND_GPMC_CONFIG2, GPMC_CONFIG2 + GPMC_CONFIG_CS0); - __raw_writel( SMNAND_GPMC_CONFIG3, GPMC_CONFIG3 + GPMC_CONFIG_CS0); - __raw_writel( SMNAND_GPMC_CONFIG4, GPMC_CONFIG4 + GPMC_CONFIG_CS0); - __raw_writel( SMNAND_GPMC_CONFIG5, GPMC_CONFIG5 + GPMC_CONFIG_CS0); - __raw_writel( SMNAND_GPMC_CONFIG6, GPMC_CONFIG6 + GPMC_CONFIG_CS0); - -#else /* CFG_ONENAND */ - __raw_writel( ONENAND_GPMC_CONFIG1, GPMC_CONFIG1 + GPMC_CONFIG_CS0); - __raw_writel( ONENAND_GPMC_CONFIG2, GPMC_CONFIG2 + GPMC_CONFIG_CS0); - __raw_writel( ONENAND_GPMC_CONFIG3, GPMC_CONFIG3 + GPMC_CONFIG_CS0); - __raw_writel( ONENAND_GPMC_CONFIG4, GPMC_CONFIG4 + GPMC_CONFIG_CS0); - __raw_writel( ONENAND_GPMC_CONFIG5, GPMC_CONFIG5 + GPMC_CONFIG_CS0); - __raw_writel( ONENAND_GPMC_CONFIG6, GPMC_CONFIG6 + GPMC_CONFIG_CS0); -#endif - - /* Enable the GPMC Mapping */ - __raw_writel(( ((OMAP34XX_GPMC_CS0_SIZE & 0xF)<<8) | - ((OMAP34XX_GPMC_CS0_MAP>>24) & 0x3F) | - (1<<6) ), (GPMC_CONFIG7 + GPMC_CONFIG_CS0)); - delay(2000); -#if defined(CFG_NAND) - if (nand_chip()){ -#ifdef CFG_PRINTF - printf("Unsupported Chip!\n"); -#endif - return 1; - } -#elif defined(CFG_ONENAND) - if (onenand_chip()){ -#ifdef CFG_PRINTF - printf("OneNAND Unsupported !\n"); -#endif - return 1; - } -#endif - return 0; -} - -#ifdef CFG_CMD_FAT -typedef int (mmc_boot_addr) (void); -int mmc_boot(void) -{ - long size, i; - unsigned long offset = CFG_LOADADDR; - unsigned long count; - char buf[12]; - block_dev_desc_t *dev_desc = NULL; - int dev = 0; - int part = 1; - char *ep; - unsigned char ret = 0; - - printf("Starting X-loader on MMC \n"); - - ret = mmc_init(1); - if(ret == 0){ - printf("\n MMC init failed \n"); - return 0; - } - - dev_desc = mmc_get_dev(0); - fat_register_device(dev_desc, 1); - size = file_fat_read("u-boot.bin", (unsigned char *)offset, 0); - if (size == -1) { - return 0; - } - printf("\n%ld Bytes Read from MMC \n", size); - - printf("Starting OS Bootloader from MMC...\n"); - - ((mmc_boot_addr *) CFG_LOADADDR) (); - - return 0; -} -#endif - -/* optionally do something like blinking LED */ -void board_hang (void) -{ while (0) {};} diff --git a/x-loader/board/omap3430sdp/platform.S b/x-loader/board/omap3430sdp/platform.S deleted file mode 100644 index 5869270..0000000 --- a/x-loader/board/omap3430sdp/platform.S +++ /dev/null @@ -1,360 +0,0 @@ -/* - * Board specific setup info - * - * (C) Copyright 2004-2006 - * Texas Instruments, <www.ti.com> - * Richard Woodruff <r-woodruff2@ti.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <config.h> -#include <asm/arch/cpu.h> -#include <asm/arch/mem.h> -#include <asm/arch/clocks.h> - -_TEXT_BASE: - .word TEXT_BASE /* sdram load addr from config.mk */ - -#if !defined(CFG_NAND_BOOT) && !defined(CFG_NAND_BOOT) -/************************************************************************** - * cpy_clk_code: relocates clock code into SRAM where its safer to execute - * R1 = SRAM destination address. - *************************************************************************/ -.global cpy_clk_code - cpy_clk_code: - /* Copy DPLL code into SRAM */ - adr r0, go_to_speed /* get addr of clock setting code */ - mov r2, #384 /* r2 size to copy (div by 32 bytes) */ - mov r1, r1 /* r1 <- dest address (passed in) */ - add r2, r2, r0 /* r2 <- source end address */ -next2: - ldmia r0!, {r3-r10} /* copy from source address [r0] */ - stmia r1!, {r3-r10} /* copy to target address [r1] */ - cmp r0, r2 /* until source end address [r2] */ - bne next2 - mov pc, lr /* back to caller */ - -/* **************************************************************************** - * NOTE: 3430 X-loader currently does not use this code. -* It could be removed its is kept for compatabily with u-boot. - * - * go_to_speed: -Moves to bypass, -Commits clock dividers, -puts dpll at speed - * -executed from SRAM. - * R0 = CM_CLKEN_PLL-bypass value - * R1 = CM_CLKSEL1_PLL-m, n, and divider values - * R2 = CM_CLKSEL_CORE-divider values - * R3 = CM_IDLEST_CKGEN - addr dpll lock wait - * - * Note: If core unlocks/relocks and SDRAM is running fast already it gets - * confused. A reset of the controller gets it back. Taking away its - * L3 when its not in self refresh seems bad for it. Normally, this code - * runs from flash before SDR is init so that should be ok. - ******************************************************************************/ -.global go_to_speed - go_to_speed: - stmfd sp!, {r4-r6} - - /* move into fast relock bypass */ - ldr r4, pll_ctl_add - str r0, [r4] -wait1: - ldr r5, [r3] /* get status */ - and r5, r5, #0x1 /* isolate core status */ - cmp r5, #0x1 /* still locked? */ - beq wait1 /* if lock, loop */ - - /* set new dpll dividers _after_ in bypass */ - ldr r5, pll_div_add1 - str r1, [r5] /* set m, n, m2 */ - ldr r5, pll_div_add2 - str r2, [r5] /* set l3/l4/.. dividers*/ - ldr r5, pll_div_add3 /* wkup */ - ldr r2, pll_div_val3 /* rsm val */ - str r2, [r5] - ldr r5, pll_div_add4 /* gfx */ - ldr r2, pll_div_val4 - str r2, [r5] - ldr r5, pll_div_add5 /* emu */ - ldr r2, pll_div_val5 - str r2, [r5] - - /* now prepare GPMC (flash) for new dpll speed */ - /* flash needs to be stable when we jump back to it */ - ldr r5, flash_cfg3_addr - ldr r2, flash_cfg3_val - str r2, [r5] - ldr r5, flash_cfg4_addr - ldr r2, flash_cfg4_val - str r2, [r5] - ldr r5, flash_cfg5_addr - ldr r2, flash_cfg5_val - str r2, [r5] - ldr r5, flash_cfg1_addr - ldr r2, [r5] - orr r2, r2, #0x3 /* up gpmc divider */ - str r2, [r5] - - /* lock DPLL3 and wait a bit */ - orr r0, r0, #0x7 /* set up for lock mode */ - str r0, [r4] /* lock */ - nop /* ARM slow at this point working at sys_clk */ - nop - nop - nop -wait2: - ldr r5, [r3] /* get status */ - and r5, r5, #0x1 /* isolate core status */ - cmp r5, #0x1 /* still locked? */ - bne wait2 /* if lock, loop */ - nop - nop - nop - nop - ldmfd sp!, {r4-r6} - mov pc, lr /* back to caller, locked */ - -_go_to_speed: .word go_to_speed - -/* these constants need to be close for PIC code */ -/* The Nor has to be in the Flash Base CS0 for this condition to happen */ -flash_cfg1_addr: - .word (GPMC_CONFIG_CS0 + GPMC_CONFIG1) -flash_cfg3_addr: - .word (GPMC_CONFIG_CS0 + GPMC_CONFIG3) -flash_cfg3_val: - .word STNOR_GPMC_CONFIG3 -flash_cfg4_addr: - .word (GPMC_CONFIG_CS0 + GPMC_CONFIG4) -flash_cfg4_val: - .word STNOR_GPMC_CONFIG4 -flash_cfg5_val: - .word STNOR_GPMC_CONFIG5 -flash_cfg5_addr: - .word (GPMC_CONFIG_CS0 + GPMC_CONFIG5) -pll_ctl_add: - .word CM_CLKEN_PLL -pll_div_add1: - .word CM_CLKSEL1_PLL -pll_div_add2: - .word CM_CLKSEL_CORE -pll_div_add3: - .word CM_CLKSEL_WKUP -pll_div_val3: - .word (WKUP_RSM << 1) -pll_div_add4: - .word CM_CLKSEL_GFX -pll_div_val4: - .word (GFX_DIV << 0) -pll_div_add5: - .word CM_CLKSEL1_EMU -pll_div_val5: - .word CLSEL1_EMU_VAL - -#endif - -.globl lowlevel_init -lowlevel_init: - ldr sp, SRAM_STACK - str ip, [sp] /* stash old link register */ - mov ip, lr /* save link reg across call */ - bl s_init /* go setup pll,mux,memory */ - ldr ip, [sp] /* restore save ip */ - mov lr, ip /* restore link reg */ - - /* back to arch calling code */ - mov pc, lr - - /* the literal pools origin */ - .ltorg - -REG_CONTROL_STATUS: - .word CONTROL_STATUS -SRAM_STACK: - .word LOW_LEVEL_SRAM_STACK - -/* DPLL(1-4) PARAM TABLES */ -/* Each of the tables has M, N, FREQSEL, M2 values defined for nominal - * OPP (1.2V). The fields are defined according to dpll_param struct(clock.c). - * The values are defined for all possible sysclk and for ES1 and ES2. - */ - -mpu_dpll_param: -/* 12MHz */ -/* ES1 */ -.word 0x0FE,0x07,0x05,0x01 -/* ES2 */ -.word 0x0FA,0x05,0x07,0x01 -/* 3410 */ -.word 0x085,0x05,0x07,0x01 - -/* 13MHz */ -/* ES1 */ -.word 0x17D,0x0C,0x03,0x01 -/* ES2 */ -.word 0x1F4,0x0C,0x03,0x01 -/* 3410 */ -.word 0x10A,0x0C,0x03,0x01 - -/* 19.2MHz */ -/* ES1 */ -.word 0x179,0x12,0x04,0x01 -/* ES2 */ -.word 0x271,0x17,0x03,0x01 -/* 3410 */ -.word 0x14C,0x17,0x03,0x01 - -/* 26MHz */ -/* ES1 */ -.word 0x17D,0x19,0x03,0x01 -/* ES2 */ -.word 0x0FA,0x0C,0x07,0x01 -/* 3410 */ -.word 0x085,0x0C,0x07,0x01 - -/* 38.4MHz */ -/* ES1 */ -.word 0x1FA,0x32,0x03,0x01 -/* ES2 */ -.word 0x271,0x2F,0x03,0x01 -/* 3410 */ -.word 0x14C,0x2F,0x03,0x01 - - -.globl get_mpu_dpll_param -get_mpu_dpll_param: - adr r0, mpu_dpll_param - mov pc, lr - -iva_dpll_param: -/* 12MHz */ -/* ES1 */ -.word 0x07D,0x05,0x07,0x01 -/* ES2 */ -.word 0x0B4,0x05,0x07,0x01 -/* 3410 */ -.word 0x085,0x05,0x07,0x01 - -/* 13MHz */ -/* ES1 */ -.word 0x0FA,0x0C,0x03,0x01 -/* ES2 */ -.word 0x168,0x0C,0x03,0x01 -/* 3410 */ -.word 0x10A,0x0C,0x03,0x01 - -/* 19.2MHz */ -/* ES1 */ -.word 0x082,0x09,0x07,0x01 -/* ES2 */ -.word 0x0E1,0x0B,0x06,0x01 -/* 3410 */ -.word 0x14C,0x17,0x03,0x01 - -/* 26MHz */ -/* ES1 */ -.word 0x07D,0x0C,0x07,0x01 -/* ES2 */ -.word 0x0B4,0x0C,0x07,0x01 -/* 3410 */ -.word 0x085,0x0C,0x07,0x01 - -/* 38.4MHz */ -/* ES1 */ -.word 0x13F,0x30,0x03,0x01 -/* ES2 */ -.word 0x0E1,0x17,0x06,0x01 -/* 3410 */ -.word 0x14C,0x2F,0x03,0x01 - - -.globl get_iva_dpll_param -get_iva_dpll_param: - adr r0, iva_dpll_param - mov pc, lr - -/* Core DPLL targets for L3 at 166 & L133 */ -core_dpll_param: -/* 12MHz */ -/* ES1 */ -.word M_12_ES1,M_12_ES1,FSL_12_ES1,M2_12_ES1 -/* ES2 */ -.word M_12,N_12,FSEL_12,M2_12 -/* 3410 */ -.word M_12,N_12,FSEL_12,M2_12 - -/* 13MHz */ -/* ES1 */ -.word M_13_ES1,N_13_ES1,FSL_13_ES1,M2_13_ES1 -/* ES2 */ -.word M_13,N_13,FSEL_13,M2_13 -/* 3410 */ -.word M_13,N_13,FSEL_13,M2_13 - -/* 19.2MHz */ -/* ES1 */ -.word M_19p2_ES1,N_19p2_ES1,FSL_19p2_ES1,M2_19p2_ES1 -/* ES2 */ -.word M_19p2,N_19p2,FSEL_19p2,M2_19p2 -/* 3410 */ -.word M_19p2,N_19p2,FSEL_19p2,M2_19p2 - -/* 26MHz */ -/* ES1 */ -.word M_26_ES1,N_26_ES1,FSL_26_ES1,M2_26_ES1 -/* ES2 */ -.word M_26,N_26,FSEL_26,M2_26 -/* 3410 */ -.word M_26,N_26,FSEL_26,M2_26 - -/* 38.4MHz */ -/* ES1 */ -.word M_38p4_ES1,N_38p4_ES1,FSL_38p4_ES1,M2_38p4_ES1 -/* ES2 */ -.word M_38p4,N_38p4,FSEL_38p4,M2_38p4 -/* 3410 */ -.word M_38p4,N_38p4,FSEL_38p4,M2_38p4 - -.globl get_core_dpll_param -get_core_dpll_param: - adr r0, core_dpll_param - mov pc, lr - -/* PER DPLL values are same for both ES1 and ES2 */ -per_dpll_param: -/* 12MHz */ -.word 0xD8,0x05,0x07,0x09 - -/* 13MHz */ -.word 0x1B0,0x0C,0x03,0x09 - -/* 19.2MHz */ -.word 0xE1,0x09,0x07,0x09 - -/* 26MHz */ -.word 0xD8,0x0C,0x07,0x09 - -/* 38.4MHz */ -.word 0xE1,0x13,0x07,0x09 - -.globl get_per_dpll_param -get_per_dpll_param: - adr r0, per_dpll_param - mov pc, lr - diff --git a/x-loader/board/omap3430sdp/x-load.lds b/x-loader/board/omap3430sdp/x-load.lds deleted file mode 100644 index 9402f74..0000000 --- a/x-loader/board/omap3430sdp/x-load.lds +++ /dev/null @@ -1,54 +0,0 @@ -/* - * November 2006 - Changed to support 3430sdp device - * Copyright (c) 2004-2006 Texas Instruments - * - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, <gj@denx.de> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN(4); - .text : - { - cpu/omap3/start.o (.text) - *(.text) - } - - . = ALIGN(4); - .rodata : { *(.rodata) } - - . = ALIGN(4); - .data : { *(.data) } - - . = ALIGN(4); - .got : { *(.got) } - - . = ALIGN(4); - __bss_start = .; - .bss : { *(.bss) } - _end = .; -} diff --git a/x-loader/board/omap3530beagle/Makefile b/x-loader/board/omap3530beagle/Makefile deleted file mode 100644 index b7b51ce..0000000 --- a/x-loader/board/omap3530beagle/Makefile +++ /dev/null @@ -1,51 +0,0 @@ -# -# (C) Copyright 2000, 2001, 2002 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).a - -COBJS := omap3530beagle.o -SOBJS := platform.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) $(SOBJS) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak $(obj).depend - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/x-loader/board/omap3530beagle/config.mk b/x-loader/board/omap3530beagle/config.mk deleted file mode 100644 index f271b14..0000000 --- a/x-loader/board/omap3530beagle/config.mk +++ /dev/null @@ -1,20 +0,0 @@ -# -# (C) Copyright 2006 -# Texas Instruments, <www.ti.com> -# -# Beagle board uses TI OMAP3530 (ARM-CortexA8) cpu -# see http://www.ti.com/ for more information on Texas Instruments -# -# Beagle has 1 bank of 128MB mPOP-SDRAM on CS0 -# Physical Address: -# 8000'0000 (bank0) - -# For use if you want X-Loader to relocate from SRAM to DDR -#TEXT_BASE = 0x80e80000 - -# For XIP in 64K of SRAM or debug (GP device has it all availabe) -# SRAM 40200000-4020FFFF base -# initial stack at 0x4020fffc used in s_init (below xloader). -# The run time stack is (above xloader, 2k below) -# If any globals exist there needs to be room for them also -TEXT_BASE = 0x40200800 diff --git a/x-loader/board/omap3530beagle/omap3530beagle.c b/x-loader/board/omap3530beagle/omap3530beagle.c deleted file mode 100644 index 073e35a..0000000 --- a/x-loader/board/omap3530beagle/omap3530beagle.c +++ /dev/null @@ -1,1081 +0,0 @@ -/* - * (C) Copyright 2006 - * Texas Instruments, <www.ti.com> - * Jian Zhang <jzhang@ti.com> - * Richard Woodruff <r-woodruff2@ti.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <command.h> -#include <part.h> -#include <fat.h> -#include <asm/arch/cpu.h> -#include <asm/arch/bits.h> -#include <asm/arch/mux.h> -#include <asm/arch/gpio.h> -#include <asm/arch/sys_proto.h> -#include <asm/arch/sys_info.h> -#include <asm/arch/clocks.h> -#include <asm/arch/mem.h> - -/* params for XM */ -#define CORE_DPLL_PARAM_M2 0x09 -#define CORE_DPLL_PARAM_M 0x360 -#define CORE_DPLL_PARAM_N 0xC - -/* BeagleBoard revisions */ -#define REVISION_AXBX 0x7 -#define REVISION_CX 0x6 -#define REVISION_C4 0x5 -#define REVISION_XM 0x0 - -/* Used to index into DPLL parameter tables */ -struct dpll_param { - unsigned int m; - unsigned int n; - unsigned int fsel; - unsigned int m2; -}; - -typedef struct dpll_param dpll_param; - -/* Following functions are exported from lowlevel_init.S */ -extern dpll_param *get_mpu_dpll_param(); -extern dpll_param *get_iva_dpll_param(); -extern dpll_param *get_core_dpll_param(); -extern dpll_param *get_per_dpll_param(); - -#define __raw_readl(a) (*(volatile unsigned int *)(a)) -#define __raw_writel(v, a) (*(volatile unsigned int *)(a) = (v)) -#define __raw_readw(a) (*(volatile unsigned short *)(a)) -#define __raw_writew(v, a) (*(volatile unsigned short *)(a) = (v)) - -/******************************************************* - * Routine: delay - * Description: spinning delay to use before udelay works - ******************************************************/ -static inline void delay(unsigned long loops) -{ - __asm__ volatile ("1:\n" "subs %0, %1, #1\n" - "bne 1b":"=r" (loops):"0"(loops)); -} - -void udelay (unsigned long usecs) { - delay(usecs); -} - -/***************************************** - * Routine: board_init - * Description: Early hardware init. - *****************************************/ -int board_init(void) -{ - return 0; -} - -/************************************************************* - * get_device_type(): tell if GP/HS/EMU/TST - *************************************************************/ -u32 get_device_type(void) -{ - int mode; - mode = __raw_readl(CONTROL_STATUS) & (DEVICE_MASK); - return mode >>= 8; -} - -/************************************************ - * get_sysboot_value(void) - return SYS_BOOT[4:0] - ************************************************/ -u32 get_sysboot_value(void) -{ - int mode; - mode = __raw_readl(CONTROL_STATUS) & (SYSBOOT_MASK); - return mode; -} - -/************************************************************* - * Routine: get_mem_type(void) - returns the kind of memory connected - * to GPMC that we are trying to boot form. Uses SYS BOOT settings. - *************************************************************/ -u32 get_mem_type(void) -{ - - if (beagle_revision() == REVISION_XM) - return GPMC_NONE; - - u32 mem_type = get_sysboot_value(); - switch (mem_type) { - case 0: - case 2: - case 4: - case 16: - case 22: - return GPMC_ONENAND; - - case 1: - case 12: - case 15: - case 21: - case 27: - return GPMC_NAND; - - case 3: - case 6: - return MMC_ONENAND; - - case 8: - case 11: - case 14: - case 20: - case 26: - return GPMC_MDOC; - - case 17: - case 18: - case 24: - return MMC_NAND; - - case 7: - case 10: - case 13: - case 19: - case 25: - default: - return GPMC_NOR; - } -} - -/****************************************** - * get_cpu_rev(void) - extract version info - ******************************************/ -u32 get_cpu_rev(void) -{ - u32 cpuid = 0; - /* On ES1.0 the IDCODE register is not exposed on L4 - * so using CPU ID to differentiate - * between ES2.0 and ES1.0. - */ - __asm__ __volatile__("mrc p15, 0, %0, c0, c0, 0":"=r" (cpuid)); - if ((cpuid & 0xf) == 0x0) - return CPU_3430_ES1; - else - return CPU_3430_ES2; - -} - -/****************************************** - * cpu_is_3410(void) - returns true for 3410 - ******************************************/ -u32 cpu_is_3410(void) -{ - int status; - if (get_cpu_rev() < CPU_3430_ES2) { - return 0; - } else { - /* read scalability status and return 1 for 3410*/ - status = __raw_readl(CONTROL_SCALABLE_OMAP_STATUS); - /* Check whether MPU frequency is set to 266 MHz which - * is nominal for 3410. If yes return true else false - */ - if (((status >> 8) & 0x3) == 0x2) - return 1; - else - return 0; - } -} - -/****************************************** - * beagle_identify - * Description: Detect if we are running on a Beagle revision Ax/Bx, - * C1/2/3, C4 or D. This can be done by reading - * the level of GPIO173, GPIO172 and GPIO171. This should - * result in - * GPIO173, GPIO172, GPIO171: 1 1 1 => Ax/Bx - * GPIO173, GPIO172, GPIO171: 1 1 0 => C1/2/3 - * GPIO173, GPIO172, GPIO171: 1 0 1 => C4 - * GPIO173, GPIO172, GPIO171: 0 0 0 => XM - ******************************************/ -int beagle_revision(void) -{ - int rev; - - omap_request_gpio(171); - omap_request_gpio(172); - omap_request_gpio(173); - omap_set_gpio_direction(171, 1); - omap_set_gpio_direction(172, 1); - omap_set_gpio_direction(173, 1); - - rev = omap_get_gpio_datain(173) << 2 | - omap_get_gpio_datain(172) << 1 | - omap_get_gpio_datain(171); - omap_free_gpio(171); - omap_free_gpio(172); - omap_free_gpio(173); - - return rev; -} - -/***************************************************************** - * sr32 - clear & set a value in a bit range for a 32 bit address - *****************************************************************/ -void sr32(u32 addr, u32 start_bit, u32 num_bits, u32 value) -{ - u32 tmp, msk = 0; - msk = 1 << num_bits; - --msk; - tmp = __raw_readl(addr) & ~(msk << start_bit); - tmp |= value << start_bit; - __raw_writel(tmp, addr); -} - -/********************************************************************* - * wait_on_value() - common routine to allow waiting for changes in - * volatile regs. - *********************************************************************/ -u32 wait_on_value(u32 read_bit_mask, u32 match_value, u32 read_addr, u32 bound) -{ - u32 i = 0, val; - do { - ++i; - val = __raw_readl(read_addr) & read_bit_mask; - if (val == match_value) - return 1; - if (i == bound) - return 0; - } while (1); -} - -#ifdef CFG_3430SDRAM_DDR - -#define MICRON_DDR 0 -#define NUMONYX_MCP 1 -int identify_xm_ddr() -{ - int mfr, id; - - __raw_writel(M_NAND_GPMC_CONFIG1, GPMC_CONFIG1 + GPMC_CONFIG_CS0); - __raw_writel(M_NAND_GPMC_CONFIG2, GPMC_CONFIG2 + GPMC_CONFIG_CS0); - __raw_writel(M_NAND_GPMC_CONFIG3, GPMC_CONFIG3 + GPMC_CONFIG_CS0); - __raw_writel(M_NAND_GPMC_CONFIG4, GPMC_CONFIG4 + GPMC_CONFIG_CS0); - __raw_writel(M_NAND_GPMC_CONFIG5, GPMC_CONFIG5 + GPMC_CONFIG_CS0); - __raw_writel(M_NAND_GPMC_CONFIG6, GPMC_CONFIG6 + GPMC_CONFIG_CS0); - - /* Enable the GPMC Mapping */ - __raw_writel((((OMAP34XX_GPMC_CS0_SIZE & 0xF)<<8) | - ((NAND_BASE_ADR>>24) & 0x3F) | - (1<<6)), (GPMC_CONFIG7 + GPMC_CONFIG_CS0)); - delay(2000); - - nand_readid(&mfr, &id); - if (mfr == 0) - return MICRON_DDR; - if ((mfr == 0x20) && (id == 0xba)) - return NUMONYX_MCP; -} -/********************************************************************* - * config_3430sdram_ddr() - Init DDR on 3430SDP dev board. - *********************************************************************/ -void config_3430sdram_ddr(void) -{ - /* reset sdrc controller */ - __raw_writel(SOFTRESET, SDRC_SYSCONFIG); - wait_on_value(BIT0, BIT0, SDRC_STATUS, 12000000); - __raw_writel(0, SDRC_SYSCONFIG); - - /* setup sdrc to ball mux */ - __raw_writel(SDP_SDRC_SHARING, SDRC_SHARING); - - switch(beagle_revision()) { - case REVISION_C4: - if (identify_xm_ddr() == NUMONYX_MCP) { - __raw_writel(0x4, SDRC_CS_CFG); /* 512MB/bank */ - __raw_writel(SDP_SDRC_MDCFG_0_DDR_NUMONYX_XM, SDRC_MCFG_0); - __raw_writel(SDP_SDRC_MDCFG_0_DDR_NUMONYX_XM, SDRC_MCFG_1); - __raw_writel(NUMONYX_V_ACTIMA_165, SDRC_ACTIM_CTRLA_0); - __raw_writel(NUMONYX_V_ACTIMB_165, SDRC_ACTIM_CTRLB_0); - __raw_writel(NUMONYX_V_ACTIMA_165, SDRC_ACTIM_CTRLA_1); - __raw_writel(NUMONYX_V_ACTIMB_165, SDRC_ACTIM_CTRLB_1); - __raw_writel(SDP_3430_SDRC_RFR_CTRL_165MHz, SDRC_RFR_CTRL_0); - __raw_writel(SDP_3430_SDRC_RFR_CTRL_165MHz, SDRC_RFR_CTRL_1); - } else { - __raw_writel(0x1, SDRC_CS_CFG); /* 128MB/bank */ - __raw_writel(SDP_SDRC_MDCFG_0_DDR, SDRC_MCFG_0); - __raw_writel(SDP_SDRC_MDCFG_0_DDR, SDRC_MCFG_1); - __raw_writel(MICRON_V_ACTIMA_165, SDRC_ACTIM_CTRLA_0); - __raw_writel(MICRON_V_ACTIMB_165, SDRC_ACTIM_CTRLB_0); - __raw_writel(MICRON_V_ACTIMA_165, SDRC_ACTIM_CTRLA_1); - __raw_writel(MICRON_V_ACTIMB_165, SDRC_ACTIM_CTRLB_1); - __raw_writel(SDP_3430_SDRC_RFR_CTRL_165MHz, SDRC_RFR_CTRL_0); - __raw_writel(SDP_3430_SDRC_RFR_CTRL_165MHz, SDRC_RFR_CTRL_1); - } - break; - case REVISION_XM: - if (identify_xm_ddr() == MICRON_DDR) { - __raw_writel(0x2, SDRC_CS_CFG); /* 256MB/bank */ - __raw_writel(SDP_SDRC_MDCFG_0_DDR_MICRON_XM, SDRC_MCFG_0); - __raw_writel(SDP_SDRC_MDCFG_0_DDR_MICRON_XM, SDRC_MCFG_1); - __raw_writel(MICRON_V_ACTIMA_200, SDRC_ACTIM_CTRLA_0); - __raw_writel(MICRON_V_ACTIMB_200, SDRC_ACTIM_CTRLB_0); - __raw_writel(MICRON_V_ACTIMA_200, SDRC_ACTIM_CTRLA_1); - __raw_writel(MICRON_V_ACTIMB_200, SDRC_ACTIM_CTRLB_1); - __raw_writel(SDP_3430_SDRC_RFR_CTRL_200MHz, SDRC_RFR_CTRL_0); - __raw_writel(SDP_3430_SDRC_RFR_CTRL_200MHz, SDRC_RFR_CTRL_1); - } else { - __raw_writel(0x4, SDRC_CS_CFG); /* 512MB/bank */ - __raw_writel(SDP_SDRC_MDCFG_0_DDR_NUMONYX_XM, SDRC_MCFG_0); - __raw_writel(SDP_SDRC_MDCFG_0_DDR_NUMONYX_XM, SDRC_MCFG_1); - __raw_writel(NUMONYX_V_ACTIMA_165, SDRC_ACTIM_CTRLA_0); - __raw_writel(NUMONYX_V_ACTIMB_165, SDRC_ACTIM_CTRLB_0); - __raw_writel(NUMONYX_V_ACTIMA_165, SDRC_ACTIM_CTRLA_1); - __raw_writel(NUMONYX_V_ACTIMB_165, SDRC_ACTIM_CTRLB_1); - __raw_writel(SDP_3430_SDRC_RFR_CTRL_165MHz, SDRC_RFR_CTRL_0); - __raw_writel(SDP_3430_SDRC_RFR_CTRL_165MHz, SDRC_RFR_CTRL_1); - } - break; - default: - __raw_writel(0x1, SDRC_CS_CFG); /* 128MB/bank */ - __raw_writel(SDP_SDRC_MDCFG_0_DDR, SDRC_MCFG_0); - __raw_writel(SDP_SDRC_MDCFG_0_DDR, SDRC_MCFG_1); - __raw_writel(MICRON_V_ACTIMA_165, SDRC_ACTIM_CTRLA_0); - __raw_writel(MICRON_V_ACTIMB_165, SDRC_ACTIM_CTRLB_0); - __raw_writel(MICRON_V_ACTIMA_165, SDRC_ACTIM_CTRLA_1); - __raw_writel(MICRON_V_ACTIMB_165, SDRC_ACTIM_CTRLB_1); - __raw_writel(SDP_3430_SDRC_RFR_CTRL_165MHz, SDRC_RFR_CTRL_0); - __raw_writel(SDP_3430_SDRC_RFR_CTRL_165MHz, SDRC_RFR_CTRL_1); - } - - __raw_writel(SDP_SDRC_POWER_POP, SDRC_POWER); - - /* init sequence for mDDR/mSDR using manual commands (DDR is different) */ - __raw_writel(CMD_NOP, SDRC_MANUAL_0); - __raw_writel(CMD_NOP, SDRC_MANUAL_1); - - delay(5000); - - __raw_writel(CMD_PRECHARGE, SDRC_MANUAL_0); - __raw_writel(CMD_PRECHARGE, SDRC_MANUAL_1); - - __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0); - __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_1); - - __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0); - __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_1); - - /* set mr0 */ - __raw_writel(SDP_SDRC_MR_0_DDR, SDRC_MR_0); - __raw_writel(SDP_SDRC_MR_0_DDR, SDRC_MR_1); - - /* set up dll */ - __raw_writel(SDP_SDRC_DLLAB_CTRL, SDRC_DLLA_CTRL); - delay(0x2000); /* give time to lock */ - -} -#endif /* CFG_3430SDRAM_DDR */ - -/************************************************************* - * get_sys_clk_speed - determine reference oscillator speed - * based on known 32kHz clock and gptimer. - *************************************************************/ -u32 get_osc_clk_speed(void) -{ - u32 start, cstart, cend, cdiff, cdiv, val; - - val = __raw_readl(PRM_CLKSRC_CTRL); - - if (val & SYSCLKDIV_2) - cdiv = 2; - else - cdiv = 1; - - /* enable timer2 */ - val = __raw_readl(CM_CLKSEL_WKUP) | BIT0; - __raw_writel(val, CM_CLKSEL_WKUP); /* select sys_clk for GPT1 */ - - /* Enable I and F Clocks for GPT1 */ - val = __raw_readl(CM_ICLKEN_WKUP) | BIT0 | BIT2; - __raw_writel(val, CM_ICLKEN_WKUP); - val = __raw_readl(CM_FCLKEN_WKUP) | BIT0; - __raw_writel(val, CM_FCLKEN_WKUP); - - __raw_writel(0, OMAP34XX_GPT1 + TLDR); /* start counting at 0 */ - __raw_writel(GPT_EN, OMAP34XX_GPT1 + TCLR); /* enable clock */ - /* enable 32kHz source */ - /* enabled out of reset */ - /* determine sys_clk via gauging */ - - start = 20 + __raw_readl(S32K_CR); /* start time in 20 cycles */ - while (__raw_readl(S32K_CR) < start) ; /* dead loop till start time */ - cstart = __raw_readl(OMAP34XX_GPT1 + TCRR); /* get start sys_clk count */ - while (__raw_readl(S32K_CR) < (start + 20)) ; /* wait for 40 cycles */ - cend = __raw_readl(OMAP34XX_GPT1 + TCRR); /* get end sys_clk count */ - cdiff = cend - cstart; /* get elapsed ticks */ - cdiff *= cdiv; - - /* based on number of ticks assign speed */ - if (cdiff > 19000) - return S38_4M; - else if (cdiff > 15200) - return S26M; - else if (cdiff > 13000) - return S24M; - else if (cdiff > 9000) - return S19_2M; - else if (cdiff > 7600) - return S13M; - else - return S12M; -} - -/****************************************************************************** - * get_sys_clkin_sel() - returns the sys_clkin_sel field value based on - * -- input oscillator clock frequency. - * - *****************************************************************************/ -void get_sys_clkin_sel(u32 osc_clk, u32 *sys_clkin_sel) -{ - if (osc_clk == S38_4M) - *sys_clkin_sel = 4; - else if (osc_clk == S26M) - *sys_clkin_sel = 3; - else if (osc_clk == S19_2M) - *sys_clkin_sel = 2; - else if (osc_clk == S13M) - *sys_clkin_sel = 1; - else if (osc_clk == S12M) - *sys_clkin_sel = 0; -} - -/****************************************************************************** - * prcm_init() - inits clocks for PRCM as defined in clocks.h - * -- called from SRAM, or Flash (using temp SRAM stack). - *****************************************************************************/ -void prcm_init(void) -{ - u32 osc_clk = 0, sys_clkin_sel; - dpll_param *dpll_param_p; - u32 clk_index, sil_index; - - /* Gauge the input clock speed and find out the sys_clkin_sel - * value corresponding to the input clock. - */ - osc_clk = get_osc_clk_speed(); - get_sys_clkin_sel(osc_clk, &sys_clkin_sel); - - sr32(PRM_CLKSEL, 0, 3, sys_clkin_sel); /* set input crystal speed */ - - /* If the input clock is greater than 19.2M always divide/2 */ - if (sys_clkin_sel > 2) { - sr32(PRM_CLKSRC_CTRL, 6, 2, 2); /* input clock divider */ - clk_index = sys_clkin_sel / 2; - } else { - sr32(PRM_CLKSRC_CTRL, 6, 2, 1); /* input clock divider */ - clk_index = sys_clkin_sel; - } - - sr32(PRM_CLKSRC_CTRL, 0, 2, 0);/* Bypass mode: T2 inputs a square clock */ - - /* The DPLL tables are defined according to sysclk value and - * silicon revision. The clk_index value will be used to get - * the values for that input sysclk from the DPLL param table - * and sil_index will get the values for that SysClk for the - * appropriate silicon rev. - */ - sil_index = get_cpu_rev() - 1; - - /* Unlock MPU DPLL (slows things down, and needed later) */ - sr32(CM_CLKEN_PLL_MPU, 0, 3, PLL_LOW_POWER_BYPASS); - wait_on_value(BIT0, 0, CM_IDLEST_PLL_MPU, LDELAY); - - /* Getting the base address of Core DPLL param table */ - dpll_param_p = (dpll_param *) get_core_dpll_param(); - /* Moving it to the right sysclk and ES rev base */ - dpll_param_p = dpll_param_p + 3 * clk_index + sil_index; - /* CORE DPLL */ - /* sr32(CM_CLKSEL2_EMU) set override to work when asleep */ - sr32(CM_CLKEN_PLL, 0, 3, PLL_FAST_RELOCK_BYPASS); - wait_on_value(BIT0, 0, CM_IDLEST_CKGEN, LDELAY); - - /* For 3430 ES1.0 Errata 1.50, default value directly doesnt - work. write another value and then default value. */ - sr32(CM_CLKSEL1_EMU, 16, 5, CORE_M3X2 + 1); /* m3x2 */ - sr32(CM_CLKSEL1_EMU, 16, 5, CORE_M3X2); /* m3x2 */ - sr32(CM_CLKSEL1_PLL, 27, 2, dpll_param_p->m2); /* Set M2 */ - sr32(CM_CLKSEL1_PLL, 16, 11, dpll_param_p->m); /* Set M */ - sr32(CM_CLKSEL1_PLL, 8, 7, dpll_param_p->n); /* Set N */ - sr32(CM_CLKSEL1_PLL, 6, 1, 0); /* 96M Src */ - sr32(CM_CLKSEL_CORE, 8, 4, CORE_SSI_DIV); /* ssi */ - sr32(CM_CLKSEL_CORE, 4, 2, CORE_FUSB_DIV); /* fsusb */ - sr32(CM_CLKSEL_CORE, 2, 2, CORE_L4_DIV); /* l4 */ - sr32(CM_CLKSEL_CORE, 0, 2, CORE_L3_DIV); /* l3 */ - sr32(CM_CLKSEL_GFX, 0, 3, GFX_DIV); /* gfx */ - sr32(CM_CLKSEL_WKUP, 1, 2, WKUP_RSM); /* reset mgr */ - sr32(CM_CLKEN_PLL, 4, 4, dpll_param_p->fsel); /* FREQSEL */ - sr32(CM_CLKEN_PLL, 0, 3, PLL_LOCK); /* lock mode */ - wait_on_value(BIT0, 1, CM_IDLEST_CKGEN, LDELAY); - - /* Getting the base address to PER DPLL param table */ - dpll_param_p = (dpll_param *) get_per_dpll_param(); - /* Moving it to the right sysclk base */ - dpll_param_p = dpll_param_p + clk_index; - /* PER DPLL */ - sr32(CM_CLKEN_PLL, 16, 3, PLL_STOP); - wait_on_value(BIT1, 0, CM_IDLEST_CKGEN, LDELAY); - sr32(CM_CLKSEL1_EMU, 24, 5, PER_M6X2); /* set M6 */ - sr32(CM_CLKSEL_CAM, 0, 5, PER_M5X2); /* set M5 */ - sr32(CM_CLKSEL_DSS, 0, 5, PER_M4X2); /* set M4 */ - sr32(CM_CLKSEL_DSS, 8, 5, PER_M3X2); /* set M3 */ - - if (beagle_revision() == REVISION_XM) { - sr32(CM_CLKSEL3_PLL, 0, 5, CORE_DPLL_PARAM_M2); /* set M2 */ - sr32(CM_CLKSEL2_PLL, 8, 11, CORE_DPLL_PARAM_M); /* set m */ - sr32(CM_CLKSEL2_PLL, 0, 7, CORE_DPLL_PARAM_N); /* set n */ - } else { - sr32(CM_CLKSEL3_PLL, 0, 5, dpll_param_p->m2); /* set M2 */ - sr32(CM_CLKSEL2_PLL, 8, 11, dpll_param_p->m); /* set m */ - sr32(CM_CLKSEL2_PLL, 0, 7, dpll_param_p->n); /* set n */ - } - - sr32(CM_CLKEN_PLL, 20, 4, dpll_param_p->fsel); /* FREQSEL */ - sr32(CM_CLKEN_PLL, 16, 3, PLL_LOCK); /* lock mode */ - wait_on_value(BIT1, 2, CM_IDLEST_CKGEN, LDELAY); - - /* Getting the base address to MPU DPLL param table */ - dpll_param_p = (dpll_param *) get_mpu_dpll_param(); - - /* Moving it to the right sysclk and ES rev base */ - dpll_param_p = dpll_param_p + 3 * clk_index + sil_index; - - /* MPU DPLL (unlocked already) */ - sr32(CM_CLKSEL2_PLL_MPU, 0, 5, dpll_param_p->m2); /* Set M2 */ - sr32(CM_CLKSEL1_PLL_MPU, 8, 11, dpll_param_p->m); /* Set M */ - sr32(CM_CLKSEL1_PLL_MPU, 0, 7, dpll_param_p->n); /* Set N */ - sr32(CM_CLKEN_PLL_MPU, 4, 4, dpll_param_p->fsel); /* FREQSEL */ - sr32(CM_CLKEN_PLL_MPU, 0, 3, PLL_LOCK); /* lock mode */ - wait_on_value(BIT0, 1, CM_IDLEST_PLL_MPU, LDELAY); - - /* Getting the base address to IVA DPLL param table */ - dpll_param_p = (dpll_param *) get_iva_dpll_param(); - /* Moving it to the right sysclk and ES rev base */ - dpll_param_p = dpll_param_p + 3 * clk_index + sil_index; - /* IVA DPLL (set to 12*20=240MHz) */ - sr32(CM_CLKEN_PLL_IVA2, 0, 3, PLL_STOP); - wait_on_value(BIT0, 0, CM_IDLEST_PLL_IVA2, LDELAY); - sr32(CM_CLKSEL2_PLL_IVA2, 0, 5, dpll_param_p->m2); /* set M2 */ - sr32(CM_CLKSEL1_PLL_IVA2, 8, 11, dpll_param_p->m); /* set M */ - sr32(CM_CLKSEL1_PLL_IVA2, 0, 7, dpll_param_p->n); /* set N */ - sr32(CM_CLKEN_PLL_IVA2, 4, 4, dpll_param_p->fsel); /* FREQSEL */ - sr32(CM_CLKEN_PLL_IVA2, 0, 3, PLL_LOCK); /* lock mode */ - wait_on_value(BIT0, 1, CM_IDLEST_PLL_IVA2, LDELAY); - - /* Set up GPTimers to sys_clk source only */ - sr32(CM_CLKSEL_PER, 0, 8, 0xff); - sr32(CM_CLKSEL_WKUP, 0, 1, 1); - - delay(5000); -} - -/***************************************** - * Routine: secure_unlock - * Description: Setup security registers for access - * (GP Device only) - *****************************************/ -void secure_unlock(void) -{ - /* Permission values for registers -Full fledged permissions to all */ -#define UNLOCK_1 0xFFFFFFFF -#define UNLOCK_2 0x00000000 -#define UNLOCK_3 0x0000FFFF - /* Protection Module Register Target APE (PM_RT) */ - __raw_writel(UNLOCK_1, RT_REQ_INFO_PERMISSION_1); - __raw_writel(UNLOCK_1, RT_READ_PERMISSION_0); - __raw_writel(UNLOCK_1, RT_WRITE_PERMISSION_0); - __raw_writel(UNLOCK_2, RT_ADDR_MATCH_1); - - __raw_writel(UNLOCK_3, GPMC_REQ_INFO_PERMISSION_0); - __raw_writel(UNLOCK_3, GPMC_READ_PERMISSION_0); - __raw_writel(UNLOCK_3, GPMC_WRITE_PERMISSION_0); - - __raw_writel(UNLOCK_3, OCM_REQ_INFO_PERMISSION_0); - __raw_writel(UNLOCK_3, OCM_READ_PERMISSION_0); - __raw_writel(UNLOCK_3, OCM_WRITE_PERMISSION_0); - __raw_writel(UNLOCK_2, OCM_ADDR_MATCH_2); - - /* IVA Changes */ - __raw_writel(UNLOCK_3, IVA2_REQ_INFO_PERMISSION_0); - __raw_writel(UNLOCK_3, IVA2_READ_PERMISSION_0); - __raw_writel(UNLOCK_3, IVA2_WRITE_PERMISSION_0); - - __raw_writel(UNLOCK_1, SMS_RG_ATT0); /* SDRC region 0 public */ -} - -/********************************************************** - * Routine: try_unlock_sram() - * Description: If chip is GP type, unlock the SRAM for - * general use. - ***********************************************************/ -void try_unlock_memory(void) -{ - int mode; - - /* if GP device unlock device SRAM for general use */ - /* secure code breaks for Secure/Emulation device - HS/E/T */ - mode = get_device_type(); - if (mode == GP_DEVICE) - secure_unlock(); - return; -} - -/********************************************************** - * Routine: s_init - * Description: Does early system init of muxing and clocks. - * - Called at time when only stack is available. - **********************************************************/ - -void s_init(void) -{ - watchdog_init(); -#ifdef CONFIG_3430_AS_3410 - /* setup the scalability control register for - * 3430 to work in 3410 mode - */ - __raw_writel(0x5ABF, CONTROL_SCALABLE_OMAP_OCP); -#endif - try_unlock_memory(); - set_muxconf_regs(); - delay(100); - per_clocks_enable(); - prcm_init(); - config_3430sdram_ddr(); -} - -/******************************************************* - * Routine: misc_init_r - * Description: Init ethernet (done here so udelay works) - ********************************************************/ -int misc_init_r(void) -{ - int rev; - - rev = beagle_revision(); - switch (rev) { - case REVISION_AXBX: - printf("Beagle Rev Ax/Bx\n"); - break; - case REVISION_CX: - printf("Beagle Rev C1/C2/C3\n"); - break; - case REVISION_C4: - if (identify_xm_ddr() == NUMONYX_MCP) - printf("Beagle Rev C4 from Special Computing\n"); - else - printf("Beagle Rev C4\n"); - break; - case REVISION_XM: - printf("Beagle xM Rev A\n"); - break; - default: - printf("Beagle unknown 0x%02x\n", rev); - } - - return 0; -} - -/****************************************************** - * Routine: wait_for_command_complete - * Description: Wait for posting to finish on watchdog - ******************************************************/ -void wait_for_command_complete(unsigned int wd_base) -{ - int pending = 1; - do { - pending = __raw_readl(wd_base + WWPS); - } while (pending); -} - -/**************************************** - * Routine: watchdog_init - * Description: Shut down watch dogs - *****************************************/ -void watchdog_init(void) -{ - /* There are 3 watch dogs WD1=Secure, WD2=MPU, WD3=IVA. WD1 is - * either taken care of by ROM (HS/EMU) or not accessible (GP). - * We need to take care of WD2-MPU or take a PRCM reset. WD3 - * should not be running and does not generate a PRCM reset. - */ - sr32(CM_FCLKEN_WKUP, 5, 1, 1); - sr32(CM_ICLKEN_WKUP, 5, 1, 1); - wait_on_value(BIT5, 0x20, CM_IDLEST_WKUP, 5); /* some issue here */ - - __raw_writel(WD_UNLOCK1, WD2_BASE + WSPR); - wait_for_command_complete(WD2_BASE); - __raw_writel(WD_UNLOCK2, WD2_BASE + WSPR); -} - -/********************************************** - * Routine: dram_init - * Description: sets uboots idea of sdram size - **********************************************/ -int dram_init(void) -{ - return 0; -} - -/***************************************************************** - * Routine: peripheral_enable - * Description: Enable the clks & power for perifs (GPT2, UART1,...) - ******************************************************************/ -void per_clocks_enable(void) -{ - /* Enable GP2 timer. */ - sr32(CM_CLKSEL_PER, 0, 1, 0x1); /* GPT2 = sys clk */ - sr32(CM_ICLKEN_PER, 3, 1, 0x1); /* ICKen GPT2 */ - sr32(CM_FCLKEN_PER, 3, 1, 0x1); /* FCKen GPT2 */ - -#ifdef CFG_NS16550 - /* UART1 clocks */ - sr32(CM_FCLKEN1_CORE, 13, 1, 0x1); - sr32(CM_ICLKEN1_CORE, 13, 1, 0x1); - - /* UART 3 Clocks */ - sr32(CM_FCLKEN_PER, 11, 1, 0x1); - sr32(CM_ICLKEN_PER, 11, 1, 0x1); - -#endif - -#ifdef CONFIG_DRIVER_OMAP34XX_I2C - /* Turn on all 3 I2C clocks */ - sr32(CM_FCLKEN1_CORE, 15, 3, 0x7); - sr32(CM_ICLKEN1_CORE, 15, 3, 0x7); /* I2C1,2,3 = on */ -#endif - - /* Enable the ICLK for 32K Sync Timer as its used in udelay */ - sr32(CM_ICLKEN_WKUP, 2, 1, 0x1); - - sr32(CM_FCLKEN_IVA2, 0, 32, FCK_IVA2_ON); - sr32(CM_FCLKEN1_CORE, 0, 32, FCK_CORE1_ON); - sr32(CM_ICLKEN1_CORE, 0, 32, ICK_CORE1_ON); - sr32(CM_ICLKEN2_CORE, 0, 32, ICK_CORE2_ON); - sr32(CM_FCLKEN_WKUP, 0, 32, FCK_WKUP_ON); - sr32(CM_ICLKEN_WKUP, 0, 32, ICK_WKUP_ON); - sr32(CM_FCLKEN_DSS, 0, 32, FCK_DSS_ON); - sr32(CM_ICLKEN_DSS, 0, 32, ICK_DSS_ON); - sr32(CM_FCLKEN_CAM, 0, 32, FCK_CAM_ON); - sr32(CM_ICLKEN_CAM, 0, 32, ICK_CAM_ON); - sr32(CM_FCLKEN_PER, 0, 32, FCK_PER_ON); - sr32(CM_ICLKEN_PER, 0, 32, ICK_PER_ON); - - /* Enable GPIO 5 & GPIO 6 clocks */ - sr32(CM_FCLKEN_PER, 17, 2, 0x3); - sr32(CM_ICLKEN_PER, 17, 2, 0x3); - - delay(1000); -} - -/* Set MUX for UART, GPMC, SDRC, GPIO */ - -#define MUX_VAL(OFFSET,VALUE)\ - __raw_writew((VALUE), OMAP34XX_CTRL_BASE + (OFFSET)); - -#define CP(x) (CONTROL_PADCONF_##x) -/* - * IEN - Input Enable - * IDIS - Input Disable - * PTD - Pull type Down - * PTU - Pull type Up - * DIS - Pull type selection is inactive - * EN - Pull type selection is active - * M0 - Mode 0 - * The commented string gives the final mux configuration for that pin - */ -#define MUX_DEFAULT()\ - MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /*SDRC_D0*/\ - MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /*SDRC_D1*/\ - MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /*SDRC_D2*/\ - MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /*SDRC_D3*/\ - MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /*SDRC_D4*/\ - MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /*SDRC_D5*/\ - MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /*SDRC_D6*/\ - MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /*SDRC_D7*/\ - MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /*SDRC_D8*/\ - MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /*SDRC_D9*/\ - MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /*SDRC_D10*/\ - MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /*SDRC_D11*/\ - MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /*SDRC_D12*/\ - MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /*SDRC_D13*/\ - MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /*SDRC_D14*/\ - MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /*SDRC_D15*/\ - MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /*SDRC_D16*/\ - MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /*SDRC_D17*/\ - MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /*SDRC_D18*/\ - MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /*SDRC_D19*/\ - MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /*SDRC_D20*/\ - MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /*SDRC_D21*/\ - MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /*SDRC_D22*/\ - MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /*SDRC_D23*/\ - MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /*SDRC_D24*/\ - MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /*SDRC_D25*/\ - MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /*SDRC_D26*/\ - MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /*SDRC_D27*/\ - MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /*SDRC_D28*/\ - MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /*SDRC_D29*/\ - MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /*SDRC_D30*/\ - MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /*SDRC_D31*/\ - MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /*SDRC_CLK*/\ - MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /*SDRC_DQS0*/\ - MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /*SDRC_DQS1*/\ - MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /*SDRC_DQS2*/\ - MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /*SDRC_DQS3*/\ - MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0)) /*GPMC_A1*/\ - MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0)) /*GPMC_A2*/\ - MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0)) /*GPMC_A3*/\ - MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0)) /*GPMC_A4*/\ - MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0)) /*GPMC_A5*/\ - MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0)) /*GPMC_A6*/\ - MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0)) /*GPMC_A7*/\ - MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0)) /*GPMC_A8*/\ - MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M0)) /*GPMC_A9*/\ - MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0)) /*GPMC_A10*/\ - MUX_VAL(CP(GPMC_D0), (IEN | PTD | DIS | M0)) /*GPMC_D0*/\ - MUX_VAL(CP(GPMC_D1), (IEN | PTD | DIS | M0)) /*GPMC_D1*/\ - MUX_VAL(CP(GPMC_D2), (IEN | PTD | DIS | M0)) /*GPMC_D2*/\ - MUX_VAL(CP(GPMC_D3), (IEN | PTD | DIS | M0)) /*GPMC_D3*/\ - MUX_VAL(CP(GPMC_D4), (IEN | PTD | DIS | M0)) /*GPMC_D4*/\ - MUX_VAL(CP(GPMC_D5), (IEN | PTD | DIS | M0)) /*GPMC_D5*/\ - MUX_VAL(CP(GPMC_D6), (IEN | PTD | DIS | M0)) /*GPMC_D6*/\ - MUX_VAL(CP(GPMC_D7), (IEN | PTD | DIS | M0)) /*GPMC_D7*/\ - MUX_VAL(CP(GPMC_D8), (IEN | PTD | DIS | M0)) /*GPMC_D8*/\ - MUX_VAL(CP(GPMC_D9), (IEN | PTD | DIS | M0)) /*GPMC_D9*/\ - MUX_VAL(CP(GPMC_D10), (IEN | PTD | DIS | M0)) /*GPMC_D10*/\ - MUX_VAL(CP(GPMC_D11), (IEN | PTD | DIS | M0)) /*GPMC_D11*/\ - MUX_VAL(CP(GPMC_D12), (IEN | PTD | DIS | M0)) /*GPMC_D12*/\ - MUX_VAL(CP(GPMC_D13), (IEN | PTD | DIS | M0)) /*GPMC_D13*/\ - MUX_VAL(CP(GPMC_D14), (IEN | PTD | DIS | M0)) /*GPMC_D14*/\ - MUX_VAL(CP(GPMC_D15), (IEN | PTD | DIS | M0)) /*GPMC_D15*/\ - MUX_VAL(CP(GPMC_nCS0), (IDIS | PTU | EN | M0)) /*GPMC_nCS0*/\ - MUX_VAL(CP(GPMC_nCS1), (IDIS | PTU | EN | M0)) /*GPMC_nCS1*/\ - MUX_VAL(CP(GPMC_nCS2), (IDIS | PTU | EN | M0)) /*GPMC_nCS2*/\ - MUX_VAL(CP(GPMC_nCS3), (IDIS | PTU | EN | M0)) /*GPMC_nCS3*/\ - MUX_VAL(CP(GPMC_nCS4), (IDIS | PTU | EN | M0)) /*GPMC_nCS4*/\ - MUX_VAL(CP(GPMC_nCS5), (IDIS | PTD | DIS | M0)) /*GPMC_nCS5*/\ - MUX_VAL(CP(GPMC_nCS6), (IEN | PTD | DIS | M1)) /*GPMC_nCS6*/\ - MUX_VAL(CP(GPMC_nCS7), (IEN | PTU | EN | M1)) /*GPMC_nCS7*/\ - MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M0)) /*GPMC_CLK*/\ - MUX_VAL(CP(GPMC_nADV_ALE), (IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\ - MUX_VAL(CP(GPMC_nOE), (IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\ - MUX_VAL(CP(GPMC_nWE), (IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\ - MUX_VAL(CP(GPMC_nBE0_CLE), (IDIS | PTD | DIS | M0)) /*GPMC_nBE0_CLE*/\ - MUX_VAL(CP(GPMC_nBE1), (IEN | PTD | DIS | M0)) /*GPIO_61*/\ - MUX_VAL(CP(GPMC_nWP), (IEN | PTD | DIS | M0)) /*GPMC_nWP*/\ - MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) /*GPMC_WAIT0*/\ - MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)) /*GPMC_WAIT1*/\ - MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M0)) /*GPIO_64*/\ - MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M0)) /*GPIO_65*/\ - MUX_VAL(CP(DSS_DATA18), (IEN | PTD | DIS | M4)) /*GPIO_88*/\ - MUX_VAL(CP(DSS_DATA19), (IEN | PTD | DIS | M4)) /*GPIO_89*/\ - MUX_VAL(CP(DSS_DATA20), (IEN | PTD | DIS | M4)) /*GPIO_90*/\ - MUX_VAL(CP(DSS_DATA21), (IEN | PTD | DIS | M4)) /*GPIO_91*/\ - MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4)) /*GPIO_167*/\ - MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)) /*MMC1_CLK*/\ - MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)) /*MMC1_CMD*/\ - MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)) /*MMC1_DAT0*/\ - MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)) /*MMC1_DAT1*/\ - MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)) /*MMC1_DAT2*/\ - MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)) /*MMC1_DAT3*/\ - MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M0)) /*MMC1_DAT4*/\ - MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M0)) /*MMC1_DAT5*/\ - MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M0)) /*MMC1_DAT6*/\ - MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M0)) /*MMC1_DAT7*/\ - MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /*UART1_TX*/\ - MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M4)) /*GPIO_149*/\ - MUX_VAL(CP(UART1_CTS), (IDIS | PTD | DIS | M4)) /*GPIO_150*/\ - MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /*UART1_RX*/\ - MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | EN | M0)) /*UART3_CTS_RCTX */\ - MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0)) /*UART3_RTS_SD */\ - MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) /*UART3_RX_IRRX*/\ - MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) /*UART3_TX_IRTX*/\ - MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) /*I2C1_SCL*/\ - MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) /*I2C1_SDA*/\ - MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)) /*I2C2_SCL*/\ - MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)) /*I2C2_SDA*/\ - MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) /*I2C3_SCL*/\ - MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) /*I2C3_SDA*/\ - MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) /*I2C4_SCL*/\ - MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) /*I2C4_SDA*/\ - MUX_VAL(CP(McSPI1_CLK), (IEN | PTU | EN | M4)) /*GPIO_171*/\ - MUX_VAL(CP(McSPI1_SIMO), (IEN | PTU | EN | M4)) /*GPIO_172*/\ - MUX_VAL(CP(McSPI1_SOMI), (IEN | PTU | EN | M4)) /*GPIO_173*/\ - MUX_VAL(CP(McBSP1_DX), (IEN | PTD | DIS | M4)) /*GPIO_158*/\ - MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) /*SYS_32K*/\ - MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /*GPIO_2 */\ - MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) /*GPIO_3 */\ - MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /*GPIO_4 */\ - MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) /*GPIO_5 */\ - MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /*GPIO_6 */\ - MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /*GPIO_7 */\ - MUX_VAL(CP(SYS_BOOT6), (IEN | PTD | DIS | M4)) /*GPIO_8 */\ - MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M4)) /*GPIO_186*/\ - MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0)) /*JTAG_nTRST*/\ - MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)) /*JTAG_TCK*/\ - MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)) /*JTAG_TMS*/\ - MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)) /*JTAG_TDI*/\ - MUX_VAL(CP(JTAG_EMU0), (IEN | PTD | DIS | M0)) /*JTAG_EMU0*/\ - MUX_VAL(CP(JTAG_EMU1), (IEN | PTD | DIS | M0)) /*JTAG_EMU1*/\ - MUX_VAL(CP(ETK_CLK), (IEN | PTD | DIS | M4)) /*GPIO_12*/\ - MUX_VAL(CP(ETK_CTL), (IEN | PTD | DIS | M4)) /*GPIO_13*/\ - MUX_VAL(CP(ETK_D0), (IEN | PTD | DIS | M4)) /*GPIO_14*/\ - MUX_VAL(CP(ETK_D1), (IEN | PTD | DIS | M4)) /*GPIO_15*/\ - MUX_VAL(CP(ETK_D2), (IEN | PTD | DIS | M4)) /*GPIO_16*/\ - MUX_VAL(CP(ETK_D11), (IEN | PTD | DIS | M4)) /*GPIO_25*/\ - MUX_VAL(CP(ETK_D12), (IEN | PTD | DIS | M4)) /*GPIO_26*/\ - MUX_VAL(CP(ETK_D13), (IEN | PTD | DIS | M4)) /*GPIO_27*/\ - MUX_VAL(CP(ETK_D14), (IEN | PTD | DIS | M4)) /*GPIO_28*/\ - MUX_VAL(CP(ETK_D15), (IEN | PTD | DIS | M4)) /*GPIO_29 */\ - MUX_VAL(CP(sdrc_cke0), (IDIS | PTU | EN | M0)) /*sdrc_cke0 */\ - MUX_VAL(CP(sdrc_cke1), (IDIS | PTD | DIS | M7)) /*sdrc_cke1 not used*/ - -/********************************************************** - * Routine: set_muxconf_regs - * Description: Setting up the configuration Mux registers - * specific to the hardware. Many pins need - * to be moved from protect to primary mode. - *********************************************************/ -void set_muxconf_regs(void) -{ - MUX_DEFAULT(); -} - -/********************************************************** - * Routine: nand+_init - * Description: Set up nand for nand and jffs2 commands - *********************************************************/ - -int nand_init(void) -{ - /* global settings */ - __raw_writel(0x10, GPMC_SYSCONFIG); /* smart idle */ - __raw_writel(0x0, GPMC_IRQENABLE); /* isr's sources masked */ - __raw_writel(0, GPMC_TIMEOUT_CONTROL);/* timeout disable */ - - /* Set the GPMC Vals, NAND is mapped at CS0, oneNAND at CS0. - * We configure only GPMC CS0 with required values. Configiring other devices - * at other CS is done in u-boot. So we don't have to bother doing it here. - */ - __raw_writel(0 , GPMC_CONFIG7 + GPMC_CONFIG_CS0); - delay(1000); - -#ifdef CFG_NAND_K9F1G08R0A - if ((get_mem_type() == GPMC_NAND) || (get_mem_type() == MMC_NAND)) { - __raw_writel(M_NAND_GPMC_CONFIG1, GPMC_CONFIG1 + GPMC_CONFIG_CS0); - __raw_writel(M_NAND_GPMC_CONFIG2, GPMC_CONFIG2 + GPMC_CONFIG_CS0); - __raw_writel(M_NAND_GPMC_CONFIG3, GPMC_CONFIG3 + GPMC_CONFIG_CS0); - __raw_writel(M_NAND_GPMC_CONFIG4, GPMC_CONFIG4 + GPMC_CONFIG_CS0); - __raw_writel(M_NAND_GPMC_CONFIG5, GPMC_CONFIG5 + GPMC_CONFIG_CS0); - __raw_writel(M_NAND_GPMC_CONFIG6, GPMC_CONFIG6 + GPMC_CONFIG_CS0); - - /* Enable the GPMC Mapping */ - __raw_writel((((OMAP34XX_GPMC_CS0_SIZE & 0xF)<<8) | - ((NAND_BASE_ADR>>24) & 0x3F) | - (1<<6)), (GPMC_CONFIG7 + GPMC_CONFIG_CS0)); - delay(2000); - - if (nand_chip()) { -#ifdef CFG_PRINTF - printf("Unsupported Chip!\n"); -#endif - return 1; - } - } -#endif - -#ifdef CFG_ONENAND - if ((get_mem_type() == GPMC_ONENAND) || (get_mem_type() == MMC_ONENAND)) { - __raw_writel(ONENAND_GPMC_CONFIG1, GPMC_CONFIG1 + GPMC_CONFIG_CS0); - __raw_writel(ONENAND_GPMC_CONFIG2, GPMC_CONFIG2 + GPMC_CONFIG_CS0); - __raw_writel(ONENAND_GPMC_CONFIG3, GPMC_CONFIG3 + GPMC_CONFIG_CS0); - __raw_writel(ONENAND_GPMC_CONFIG4, GPMC_CONFIG4 + GPMC_CONFIG_CS0); - __raw_writel(ONENAND_GPMC_CONFIG5, GPMC_CONFIG5 + GPMC_CONFIG_CS0); - __raw_writel(ONENAND_GPMC_CONFIG6, GPMC_CONFIG6 + GPMC_CONFIG_CS0); - - /* Enable the GPMC Mapping */ - __raw_writel((((OMAP34XX_GPMC_CS0_SIZE & 0xF)<<8) | - ((ONENAND_BASE>>24) & 0x3F) | - (1<<6)), (GPMC_CONFIG7 + GPMC_CONFIG_CS0)); - delay(2000); - - if (onenand_chip()) { -#ifdef CFG_PRINTF - printf("OneNAND Unsupported !\n"); -#endif - return 1; - } - } -#endif - return 0; -} - -#define DEBUG_LED1 149 /* gpio */ -#define DEBUG_LED2 150 /* gpio */ - -void blinkLEDs() -{ - void *p; - - /* Alternately turn the LEDs on and off */ - p = (unsigned long *)OMAP34XX_GPIO5_BASE; - while (1) { - /* turn LED1 on and LED2 off */ - *(unsigned long *)(p + 0x94) = 1 << (DEBUG_LED1 % 32); - *(unsigned long *)(p + 0x90) = 1 << (DEBUG_LED2 % 32); - - /* delay for a while */ - delay(1000); - - /* turn LED1 off and LED2 on */ - *(unsigned long *)(p + 0x90) = 1 << (DEBUG_LED1 % 32); - *(unsigned long *)(p + 0x94) = 1 << (DEBUG_LED2 % 32); - - /* delay for a while */ - delay(1000); - } -} - -/* optionally do something like blinking LED */ -void board_hang(void) -{ - while (1) - blinkLEDs(); -} - -/****************************************************************************** - * Dummy function to handle errors for EABI incompatibility - *****************************************************************************/ -void raise(void) -{ -} - -/****************************************************************************** - * Dummy function to handle errors for EABI incompatibility - *****************************************************************************/ -void abort(void) -{ -} diff --git a/x-loader/board/omap3530beagle/platform.S b/x-loader/board/omap3530beagle/platform.S deleted file mode 100644 index 5869270..0000000 --- a/x-loader/board/omap3530beagle/platform.S +++ /dev/null @@ -1,360 +0,0 @@ -/* - * Board specific setup info - * - * (C) Copyright 2004-2006 - * Texas Instruments, <www.ti.com> - * Richard Woodruff <r-woodruff2@ti.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <config.h> -#include <asm/arch/cpu.h> -#include <asm/arch/mem.h> -#include <asm/arch/clocks.h> - -_TEXT_BASE: - .word TEXT_BASE /* sdram load addr from config.mk */ - -#if !defined(CFG_NAND_BOOT) && !defined(CFG_NAND_BOOT) -/************************************************************************** - * cpy_clk_code: relocates clock code into SRAM where its safer to execute - * R1 = SRAM destination address. - *************************************************************************/ -.global cpy_clk_code - cpy_clk_code: - /* Copy DPLL code into SRAM */ - adr r0, go_to_speed /* get addr of clock setting code */ - mov r2, #384 /* r2 size to copy (div by 32 bytes) */ - mov r1, r1 /* r1 <- dest address (passed in) */ - add r2, r2, r0 /* r2 <- source end address */ -next2: - ldmia r0!, {r3-r10} /* copy from source address [r0] */ - stmia r1!, {r3-r10} /* copy to target address [r1] */ - cmp r0, r2 /* until source end address [r2] */ - bne next2 - mov pc, lr /* back to caller */ - -/* **************************************************************************** - * NOTE: 3430 X-loader currently does not use this code. -* It could be removed its is kept for compatabily with u-boot. - * - * go_to_speed: -Moves to bypass, -Commits clock dividers, -puts dpll at speed - * -executed from SRAM. - * R0 = CM_CLKEN_PLL-bypass value - * R1 = CM_CLKSEL1_PLL-m, n, and divider values - * R2 = CM_CLKSEL_CORE-divider values - * R3 = CM_IDLEST_CKGEN - addr dpll lock wait - * - * Note: If core unlocks/relocks and SDRAM is running fast already it gets - * confused. A reset of the controller gets it back. Taking away its - * L3 when its not in self refresh seems bad for it. Normally, this code - * runs from flash before SDR is init so that should be ok. - ******************************************************************************/ -.global go_to_speed - go_to_speed: - stmfd sp!, {r4-r6} - - /* move into fast relock bypass */ - ldr r4, pll_ctl_add - str r0, [r4] -wait1: - ldr r5, [r3] /* get status */ - and r5, r5, #0x1 /* isolate core status */ - cmp r5, #0x1 /* still locked? */ - beq wait1 /* if lock, loop */ - - /* set new dpll dividers _after_ in bypass */ - ldr r5, pll_div_add1 - str r1, [r5] /* set m, n, m2 */ - ldr r5, pll_div_add2 - str r2, [r5] /* set l3/l4/.. dividers*/ - ldr r5, pll_div_add3 /* wkup */ - ldr r2, pll_div_val3 /* rsm val */ - str r2, [r5] - ldr r5, pll_div_add4 /* gfx */ - ldr r2, pll_div_val4 - str r2, [r5] - ldr r5, pll_div_add5 /* emu */ - ldr r2, pll_div_val5 - str r2, [r5] - - /* now prepare GPMC (flash) for new dpll speed */ - /* flash needs to be stable when we jump back to it */ - ldr r5, flash_cfg3_addr - ldr r2, flash_cfg3_val - str r2, [r5] - ldr r5, flash_cfg4_addr - ldr r2, flash_cfg4_val - str r2, [r5] - ldr r5, flash_cfg5_addr - ldr r2, flash_cfg5_val - str r2, [r5] - ldr r5, flash_cfg1_addr - ldr r2, [r5] - orr r2, r2, #0x3 /* up gpmc divider */ - str r2, [r5] - - /* lock DPLL3 and wait a bit */ - orr r0, r0, #0x7 /* set up for lock mode */ - str r0, [r4] /* lock */ - nop /* ARM slow at this point working at sys_clk */ - nop - nop - nop -wait2: - ldr r5, [r3] /* get status */ - and r5, r5, #0x1 /* isolate core status */ - cmp r5, #0x1 /* still locked? */ - bne wait2 /* if lock, loop */ - nop - nop - nop - nop - ldmfd sp!, {r4-r6} - mov pc, lr /* back to caller, locked */ - -_go_to_speed: .word go_to_speed - -/* these constants need to be close for PIC code */ -/* The Nor has to be in the Flash Base CS0 for this condition to happen */ -flash_cfg1_addr: - .word (GPMC_CONFIG_CS0 + GPMC_CONFIG1) -flash_cfg3_addr: - .word (GPMC_CONFIG_CS0 + GPMC_CONFIG3) -flash_cfg3_val: - .word STNOR_GPMC_CONFIG3 -flash_cfg4_addr: - .word (GPMC_CONFIG_CS0 + GPMC_CONFIG4) -flash_cfg4_val: - .word STNOR_GPMC_CONFIG4 -flash_cfg5_val: - .word STNOR_GPMC_CONFIG5 -flash_cfg5_addr: - .word (GPMC_CONFIG_CS0 + GPMC_CONFIG5) -pll_ctl_add: - .word CM_CLKEN_PLL -pll_div_add1: - .word CM_CLKSEL1_PLL -pll_div_add2: - .word CM_CLKSEL_CORE -pll_div_add3: - .word CM_CLKSEL_WKUP -pll_div_val3: - .word (WKUP_RSM << 1) -pll_div_add4: - .word CM_CLKSEL_GFX -pll_div_val4: - .word (GFX_DIV << 0) -pll_div_add5: - .word CM_CLKSEL1_EMU -pll_div_val5: - .word CLSEL1_EMU_VAL - -#endif - -.globl lowlevel_init -lowlevel_init: - ldr sp, SRAM_STACK - str ip, [sp] /* stash old link register */ - mov ip, lr /* save link reg across call */ - bl s_init /* go setup pll,mux,memory */ - ldr ip, [sp] /* restore save ip */ - mov lr, ip /* restore link reg */ - - /* back to arch calling code */ - mov pc, lr - - /* the literal pools origin */ - .ltorg - -REG_CONTROL_STATUS: - .word CONTROL_STATUS -SRAM_STACK: - .word LOW_LEVEL_SRAM_STACK - -/* DPLL(1-4) PARAM TABLES */ -/* Each of the tables has M, N, FREQSEL, M2 values defined for nominal - * OPP (1.2V). The fields are defined according to dpll_param struct(clock.c). - * The values are defined for all possible sysclk and for ES1 and ES2. - */ - -mpu_dpll_param: -/* 12MHz */ -/* ES1 */ -.word 0x0FE,0x07,0x05,0x01 -/* ES2 */ -.word 0x0FA,0x05,0x07,0x01 -/* 3410 */ -.word 0x085,0x05,0x07,0x01 - -/* 13MHz */ -/* ES1 */ -.word 0x17D,0x0C,0x03,0x01 -/* ES2 */ -.word 0x1F4,0x0C,0x03,0x01 -/* 3410 */ -.word 0x10A,0x0C,0x03,0x01 - -/* 19.2MHz */ -/* ES1 */ -.word 0x179,0x12,0x04,0x01 -/* ES2 */ -.word 0x271,0x17,0x03,0x01 -/* 3410 */ -.word 0x14C,0x17,0x03,0x01 - -/* 26MHz */ -/* ES1 */ -.word 0x17D,0x19,0x03,0x01 -/* ES2 */ -.word 0x0FA,0x0C,0x07,0x01 -/* 3410 */ -.word 0x085,0x0C,0x07,0x01 - -/* 38.4MHz */ -/* ES1 */ -.word 0x1FA,0x32,0x03,0x01 -/* ES2 */ -.word 0x271,0x2F,0x03,0x01 -/* 3410 */ -.word 0x14C,0x2F,0x03,0x01 - - -.globl get_mpu_dpll_param -get_mpu_dpll_param: - adr r0, mpu_dpll_param - mov pc, lr - -iva_dpll_param: -/* 12MHz */ -/* ES1 */ -.word 0x07D,0x05,0x07,0x01 -/* ES2 */ -.word 0x0B4,0x05,0x07,0x01 -/* 3410 */ -.word 0x085,0x05,0x07,0x01 - -/* 13MHz */ -/* ES1 */ -.word 0x0FA,0x0C,0x03,0x01 -/* ES2 */ -.word 0x168,0x0C,0x03,0x01 -/* 3410 */ -.word 0x10A,0x0C,0x03,0x01 - -/* 19.2MHz */ -/* ES1 */ -.word 0x082,0x09,0x07,0x01 -/* ES2 */ -.word 0x0E1,0x0B,0x06,0x01 -/* 3410 */ -.word 0x14C,0x17,0x03,0x01 - -/* 26MHz */ -/* ES1 */ -.word 0x07D,0x0C,0x07,0x01 -/* ES2 */ -.word 0x0B4,0x0C,0x07,0x01 -/* 3410 */ -.word 0x085,0x0C,0x07,0x01 - -/* 38.4MHz */ -/* ES1 */ -.word 0x13F,0x30,0x03,0x01 -/* ES2 */ -.word 0x0E1,0x17,0x06,0x01 -/* 3410 */ -.word 0x14C,0x2F,0x03,0x01 - - -.globl get_iva_dpll_param -get_iva_dpll_param: - adr r0, iva_dpll_param - mov pc, lr - -/* Core DPLL targets for L3 at 166 & L133 */ -core_dpll_param: -/* 12MHz */ -/* ES1 */ -.word M_12_ES1,M_12_ES1,FSL_12_ES1,M2_12_ES1 -/* ES2 */ -.word M_12,N_12,FSEL_12,M2_12 -/* 3410 */ -.word M_12,N_12,FSEL_12,M2_12 - -/* 13MHz */ -/* ES1 */ -.word M_13_ES1,N_13_ES1,FSL_13_ES1,M2_13_ES1 -/* ES2 */ -.word M_13,N_13,FSEL_13,M2_13 -/* 3410 */ -.word M_13,N_13,FSEL_13,M2_13 - -/* 19.2MHz */ -/* ES1 */ -.word M_19p2_ES1,N_19p2_ES1,FSL_19p2_ES1,M2_19p2_ES1 -/* ES2 */ -.word M_19p2,N_19p2,FSEL_19p2,M2_19p2 -/* 3410 */ -.word M_19p2,N_19p2,FSEL_19p2,M2_19p2 - -/* 26MHz */ -/* ES1 */ -.word M_26_ES1,N_26_ES1,FSL_26_ES1,M2_26_ES1 -/* ES2 */ -.word M_26,N_26,FSEL_26,M2_26 -/* 3410 */ -.word M_26,N_26,FSEL_26,M2_26 - -/* 38.4MHz */ -/* ES1 */ -.word M_38p4_ES1,N_38p4_ES1,FSL_38p4_ES1,M2_38p4_ES1 -/* ES2 */ -.word M_38p4,N_38p4,FSEL_38p4,M2_38p4 -/* 3410 */ -.word M_38p4,N_38p4,FSEL_38p4,M2_38p4 - -.globl get_core_dpll_param -get_core_dpll_param: - adr r0, core_dpll_param - mov pc, lr - -/* PER DPLL values are same for both ES1 and ES2 */ -per_dpll_param: -/* 12MHz */ -.word 0xD8,0x05,0x07,0x09 - -/* 13MHz */ -.word 0x1B0,0x0C,0x03,0x09 - -/* 19.2MHz */ -.word 0xE1,0x09,0x07,0x09 - -/* 26MHz */ -.word 0xD8,0x0C,0x07,0x09 - -/* 38.4MHz */ -.word 0xE1,0x13,0x07,0x09 - -.globl get_per_dpll_param -get_per_dpll_param: - adr r0, per_dpll_param - mov pc, lr - diff --git a/x-loader/board/omap3530beagle/platform.S_old b/x-loader/board/omap3530beagle/platform.S_old deleted file mode 100644 index 8368487..0000000 --- a/x-loader/board/omap3530beagle/platform.S_old +++ /dev/null @@ -1,435 +0,0 @@ -/* - * Board specific setup info - * - * (C) Copyright 2004-2006 - * Texas Instruments, <www.ti.com> - * Richard Woodruff <r-woodruff2@ti.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <config.h> -#include <asm/arch/cpu.h> -#include <asm/arch/mem.h> -#include <asm/arch/clocks.h> - -_TEXT_BASE: - .word TEXT_BASE /* sdram load addr from config.mk */ - -#if !defined(CFG_NAND_BOOT) && !defined(CFG_NAND_BOOT) -/************************************************************************** - * cpy_clk_code: relocates clock code into SRAM where its safer to execute - * R1 = SRAM destination address. - *************************************************************************/ -.global cpy_clk_code - cpy_clk_code: - /* Copy DPLL code into SRAM */ - adr r0, go_to_speed /* get addr of clock setting code */ - mov r2, #384 /* r2 size to copy (div by 32 bytes) */ - mov r1, r1 /* r1 <- dest address (passed in) */ - add r2, r2, r0 /* r2 <- source end address */ -next2: - ldmia r0!, {r3-r10} /* copy from source address [r0] */ - stmia r1!, {r3-r10} /* copy to target address [r1] */ - cmp r0, r2 /* until source end address [r2] */ - bne next2 - mov pc, lr /* back to caller */ - -/* **************************************************************************** - * NOTE: 3430 X-loader currently does not use this code. -* It could be removed its is kept for compatabily with u-boot. - * - * go_to_speed: -Moves to bypass, -Commits clock dividers, -puts dpll at speed - * -executed from SRAM. - * R0 = CM_CLKEN_PLL-bypass value - * R1 = CM_CLKSEL1_PLL-m, n, and divider values - * R2 = CM_CLKSEL_CORE-divider values - * R3 = CM_IDLEST_CKGEN - addr dpll lock wait - * - * Note: If core unlocks/relocks and SDRAM is running fast already it gets - * confused. A reset of the controller gets it back. Taking away its - * L3 when its not in self refresh seems bad for it. Normally, this code - * runs from flash before SDR is init so that should be ok. - ******************************************************************************/ -.global go_to_speed - go_to_speed: - stmfd sp!, {r4-r6} - - /* move into fast relock bypass */ - ldr r4, pll_ctl_add - str r0, [r4] -wait1: - ldr r5, [r3] /* get status */ - and r5, r5, #0x1 /* isolate core status */ - cmp r5, #0x1 /* still locked? */ - beq wait1 /* if lock, loop */ - - /* set new dpll dividers _after_ in bypass */ - ldr r5, pll_div_add1 - str r1, [r5] /* set m, n, m2 */ - ldr r5, pll_div_add2 - str r2, [r5] /* set l3/l4/.. dividers*/ - ldr r5, pll_div_add3 /* wkup */ - ldr r2, pll_div_val3 /* rsm val */ - str r2, [r5] - ldr r5, pll_div_add4 /* gfx */ - ldr r2, pll_div_val4 - str r2, [r5] - ldr r5, pll_div_add5 /* emu */ - ldr r2, pll_div_val5 - str r2, [r5] - - /* now prepare GPMC (flash) for new dpll speed */ - /* flash needs to be stable when we jump back to it */ - ldr r5, flash_cfg3_addr - ldr r2, flash_cfg3_val - str r2, [r5] - ldr r5, flash_cfg4_addr - ldr r2, flash_cfg4_val - str r2, [r5] - ldr r5, flash_cfg5_addr - ldr r2, flash_cfg5_val - str r2, [r5] - ldr r5, flash_cfg1_addr - ldr r2, [r5] - orr r2, r2, #0x3 /* up gpmc divider */ - str r2, [r5] - - /* lock DPLL3 and wait a bit */ - orr r0, r0, #0x7 /* set up for lock mode */ - str r0, [r4] /* lock */ - nop /* ARM slow at this point working at sys_clk */ - nop - nop - nop -wait2: - ldr r5, [r3] /* get status */ - and r5, r5, #0x1 /* isolate core status */ - cmp r5, #0x1 /* still locked? */ - bne wait2 /* if lock, loop */ - nop - nop - nop - nop - ldmfd sp!, {r4-r6} - mov pc, lr /* back to caller, locked */ - -_go_to_speed: .word go_to_speed - -/* these constants need to be close for PIC code */ -/* The Nor has to be in the Flash Base CS0 for this condition to happen */ -flash_cfg1_addr: - .word (GPMC_CONFIG_CS0 + GPMC_CONFIG1) -flash_cfg3_addr: - .word (GPMC_CONFIG_CS0 + GPMC_CONFIG3) -flash_cfg3_val: - .word STNOR_GPMC_CONFIG3 -flash_cfg4_addr: - .word (GPMC_CONFIG_CS0 + GPMC_CONFIG4) -flash_cfg4_val: - .word STNOR_GPMC_CONFIG4 -flash_cfg5_val: - .word STNOR_GPMC_CONFIG5 -flash_cfg5_addr: - .word (GPMC_CONFIG_CS0 + GPMC_CONFIG5) -pll_ctl_add: - .word CM_CLKEN_PLL -pll_div_add1: - .word CM_CLKSEL1_PLL -pll_div_add2: - .word CM_CLKSEL_CORE -pll_div_add3: - .word CM_CLKSEL_WKUP -pll_div_val3: - .word (WKUP_RSM << 1) -pll_div_add4: - .word CM_CLKSEL_GFX -pll_div_val4: - .word (GFX_DIV << 0) -pll_div_add5: - .word CM_CLKSEL1_EMU -pll_div_val5: - .word CLSEL1_EMU_VAL - -#endif - -.globl lowlevel_init -lowlevel_init: - ldr sp, SRAM_STACK - str ip, [sp] /* stash old link register */ - mov ip, lr /* save link reg across call */ - bl s_init /* go setup pll,mux,memory */ - ldr ip, [sp] /* restore save ip */ - mov lr, ip /* restore link reg */ - - /* back to arch calling code */ - mov pc, lr - - /* the literal pools origin */ - .ltorg - -REG_CONTROL_STATUS: - .word CONTROL_STATUS -SRAM_STACK: - .word LOW_LEVEL_SRAM_STACK - - -/* DPLL(1-4) PARAM TABLES */ -/* Each of the tables has M, N, FREQSEL, M2 values defined for nominal - * OPP (1.2V). The fields are defined according to dpll_param struct(clock.c). - * The values are defined for all possible sysclk and for ES1 and ES2. - */ - -mpu_dpll_param: -/* 12MHz */ -/* ES1 */ -.word 0x0FE -.word 0x07 -.word 0x05 -.word 0x01 -/* ES2 */ -.word 0x0FA -.word 0x05 -.word 0x07 -.word 0x01 - -/* 13MHz */ -/* ES1 */ -.word 0x17D -.word 0x0C -.word 0x03 -.word 0x01 -/* ES2 */ -.word 0x1F4 -.word 0x0C -.word 0x03 -.word 0x01 - -/* 19.2MHz */ -/* ES1 */ -.word 0x179 -.word 0x12 -.word 0x04 -.word 0x01 -/* ES2 */ -.word 0x271 -.word 0x17 -.word 0x03 -.word 0x01 - -/* 26MHz */ -/* ES1 */ -.word 0x17D -.word 0x19 -.word 0x03 -.word 0x01 -/* ES2 */ -.word 0x0FA -.word 0x0C -.word 0x07 -.word 0x01 - -/* 38.4MHz */ -/* ES1 */ -.word 0x1FA -.word 0x32 -.word 0x03 -.word 0x01 -/* ES2 */ -.word 0x271 -.word 0x2F -.word 0x03 -.word 0x01 - - -.globl get_mpu_dpll_param -get_mpu_dpll_param: - adr r0, mpu_dpll_param - mov pc, lr - -iva_dpll_param: -/* 12MHz */ -/* ES1 */ -.word 0x07D -.word 0x05 -.word 0x07 -.word 0x01 -/* ES2 */ -.word 0x0B4 -.word 0x05 -.word 0x07 -.word 0x01 - -/* 13MHz */ -/* ES1 */ -.word 0x0FA -.word 0x0C -.word 0x03 -.word 0x01 -/* ES2 */ -.word 0x168 -.word 0x0C -.word 0x03 -.word 0x01 - -/* 19.2MHz */ -/* ES1 */ -.word 0x082 -.word 0x09 -.word 0x07 -.word 0x01 -/* ES2 */ -.word 0x0E1 -.word 0x0B -.word 0x06 -.word 0x01 - -/* 26MHz */ -/* ES1 */ -.word 0x07D -.word 0x0C -.word 0x07 -.word 0x01 -/* ES2 */ -.word 0x0B4 -.word 0x0C -.word 0x07 -.word 0x01 - -/* 38.4MHz */ -/* ES1 */ -.word 0x13F -.word 0x30 -.word 0x03 -.word 0x01 -/* ES2 */ -.word 0x0E1 -.word 0x17 -.word 0x06 -.word 0x01 - - -.globl get_iva_dpll_param -get_iva_dpll_param: - adr r0, iva_dpll_param - mov pc, lr - -core_dpll_param: -/* 12MHz */ -/* ES1 */ -.word 0x19F -.word 0x0E -.word 0x03 -.word 0x01 -/* ES2 */ -.word 0x0A6 -.word 0x05 -.word 0x07 -.word 0x01 - -/* 13MHz */ -/* ES1 */ -.word 0x1B2 -.word 0x10 -.word 0x03 -.word 0x01 -/* ES2 */ -.word 0x14C -.word 0x0C -.word 0x03 -.word 0x01 - -/* 19.2MHz */ -/* ES1 */ -.word 0x19F -.word 0x17 -.word 0x03 -.word 0x01 -/* ES2 */ -.word 0x19F -.word 0x17 -.word 0x03 -.word 0x01 - -/* 26MHz */ -/* ES1 */ -.word 0x1B2 -.word 0x21 -.word 0x03 -.word 0x01 -/* ES2 */ -.word 0x0A6 -.word 0x0C -.word 0x07 -.word 0x01 - -/* 38.4MHz */ -/* ES1 */ -.word 0x19F -.word 0x2F -.word 0x03 -.word 0x01 -/* ES2 */ -.word 0x19F -.word 0x2F -.word 0x03 -.word 0x01 - -.globl get_core_dpll_param -get_core_dpll_param: - adr r0, core_dpll_param - mov pc, lr - -/* PER DPLL values are same for both ES1 and ES2 */ -per_dpll_param: -/* 12MHz */ -.word 0xD8 -.word 0x05 -.word 0x07 -.word 0x09 - -/* 13MHz */ -.word 0x1B0 -.word 0x0C -.word 0x03 -.word 0x09 - -/* 19.2MHz */ -.word 0xE1 -.word 0x09 -.word 0x07 -.word 0x09 - -/* 26MHz */ -.word 0xD8 -.word 0x0C -.word 0x07 -.word 0x09 - -/* 38.4MHz */ -.word 0xE1 -.word 0x13 -.word 0x07 -.word 0x09 - -.globl get_per_dpll_param -get_per_dpll_param: - adr r0, per_dpll_param - mov pc, lr - diff --git a/x-loader/board/omap3530beagle/x-load.lds b/x-loader/board/omap3530beagle/x-load.lds deleted file mode 100644 index 9402f74..0000000 --- a/x-loader/board/omap3530beagle/x-load.lds +++ /dev/null @@ -1,54 +0,0 @@ -/* - * November 2006 - Changed to support 3430sdp device - * Copyright (c) 2004-2006 Texas Instruments - * - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, <gj@denx.de> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN(4); - .text : - { - cpu/omap3/start.o (.text) - *(.text) - } - - . = ALIGN(4); - .rodata : { *(.rodata) } - - . = ALIGN(4); - .data : { *(.data) } - - . = ALIGN(4); - .got : { *(.got) } - - . = ALIGN(4); - __bss_start = .; - .bss : { *(.bss) } - _end = .; -} diff --git a/x-loader/board/omap3530gta04/Makefile b/x-loader/board/omap3530gta04/Makefile deleted file mode 100644 index 436d974..0000000 --- a/x-loader/board/omap3530gta04/Makefile +++ /dev/null @@ -1,51 +0,0 @@ -# -# (C) Copyright 2000, 2001, 2002 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).a - -COBJS := omap3530gta04.o -SOBJS := platform.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) $(SOBJS) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak $(obj).depend - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/x-loader/board/omap3530gta04/config.mk b/x-loader/board/omap3530gta04/config.mk deleted file mode 100644 index 01eafc1..0000000 --- a/x-loader/board/omap3530gta04/config.mk +++ /dev/null @@ -1,23 +0,0 @@ -# -# (C) Copyright 2006 -# Texas Instruments, <www.ti.com> -# -# Beagle board uses TI OMAP3530 (ARM-CortexA8) cpu -# see http://www.ti.com/ for more information on Texas Instruments -# -# Beagle has 1 bank of 128MB mPOP-SDRAM on CS0 -# Physical Address: -# 8000'0000 (bank0) - -# For use if you want X-Loader to relocate from SRAM to DDR -#TEXT_BASE = 0x80e80000 - -# if you want X-Loader to load to RAM through peripheral boot -#TEXT_BASE = 0x40200000 # for serial loader - -# For XIP in 64K of SRAM or debug (GP device has it all availabe) -# SRAM 40200000-4020FFFF base -# initial stack at 0x4020fffc used in s_init (below xloader). -# The run time stack is (above xloader, 2k below) -# If any globals exist there needs to be room for them also -TEXT_BASE = 0x40208800 diff --git a/x-loader/board/omap3530gta04/omap3530gta04.c b/x-loader/board/omap3530gta04/omap3530gta04.c deleted file mode 100644 index 04f310d..0000000 --- a/x-loader/board/omap3530gta04/omap3530gta04.c +++ /dev/null @@ -1,1279 +0,0 @@ -/* - * (C) Copyright 2006 - * Texas Instruments, <www.ti.com> - * Jian Zhang <jzhang@ti.com> - * Richard Woodruff <r-woodruff2@ti.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <command.h> -#include <part.h> -#include <fat.h> -#include <i2c.h> -#include <asm/arch/cpu.h> -#include <asm/arch/bits.h> -#include <asm/arch/mux.h> -#include <asm/arch/gpio.h> -#include <asm/arch/sys_proto.h> -#include <asm/arch/sys_info.h> -#include <asm/arch/clocks.h> -#include <asm/arch/mem.h> - -/* params for 37XX */ -#define CORE_DPLL_PARAM_M2 0x09 -#define CORE_DPLL_PARAM_M 0x360 -#define CORE_DPLL_PARAM_N 0xC - -/* Used to index into DPLL parameter tables */ -struct dpll_param { - unsigned int m; - unsigned int n; - unsigned int fsel; - unsigned int m2; -}; - -typedef struct dpll_param dpll_param; - -/* Following functions are exported from lowlevel_init.S */ -extern dpll_param *get_mpu_dpll_param(void); -extern dpll_param *get_iva_dpll_param(void); -extern dpll_param *get_core_dpll_param(void); -extern dpll_param *get_per_dpll_param(void); - -#define __raw_readl(a) (*(volatile unsigned int *)(a)) -#define __raw_writel(v, a) (*(volatile unsigned int *)(a) = (v)) -#define __raw_readw(a) (*(volatile unsigned short *)(a)) -#define __raw_writew(v, a) (*(volatile unsigned short *)(a) = (v)) - -static char *rev_s[CPU_3XX_MAX_REV] = { - "1.0", - "2.0", - "2.1", - "3.0", - "3.1", - "UNKNOWN", - "UNKNOWN", - "3.1.2"}; - -/******************************************************* - * Routine: delay - * Description: spinning delay to use before udelay works - ******************************************************/ -static inline void delay(unsigned long loops) -{ - __asm__ volatile ("1:\n" "subs %0, %1, #1\n" - "bne 1b":"=r" (loops):"0"(loops)); -} - -void udelay (unsigned long usecs) { - delay(usecs); -} - -/***************************************** - * Routine: board_init - * Description: Early hardware init. - *****************************************/ -int board_init(void) -{ - /* - use code like this to early enable USB charging! - so that the board boots with no battery but USB power - - if i2c does not work at this position, - try to move this code to gta04_revision() - - I2C_SET_BUS(0); - data = 0x01; - i2c_write(0x4B, 0x29, 1, &data, 1); - data = 0x0c; - i2c_write(0x4B, 0x2b, 1, &data, 1); - i2c_read(0x4B, 0x2a, 1, &data, 1); - -*/ - -#if 0 /* no - does not work as expected */ - - /* - For charging using USB, the software must enable the USB automatic - charge by forcing the BOOT_BCI[1] BCIAUTOUSB bit to 1. When the USB - charger is plugged in, the software detects the type of device - (USB charger or carkit charger). The software must set the POWER_CTRL[5] - OTG_EN bit to 1 at least 50 ms before forcing the BCIMFSTS4[2] USBFASTMCHG - bit to 1. - */ - - u8 data; - int i; - - I2C_SET_BUS(0); - - /* enable access to BCIIREF1 */ - data = 0xE7; - i2c_write(0x4A, 0x85, 1, &data, 1); // write BCIMFKEY - - /* set charging current = 852mA */ - data = 0xFF; - i2c_write(0x4A, 0x9B, 1, &data, 1); // write BCIIREF1 - - /* forcing the field BCIAUTOUSB (BOOT_BCI[1]) to 1 */ - i2c_read(0x4B, 0x3D, 1, &data, 1); // read BOOT_BCI - data |= 0x33; // CONFIG_DONE | BCIAUTOWEN | BCIAUTOUSB | BCIAUTOAC - i2c_write(0x4B, 0x3D, 1, &data, 1); // write BOOT_BCI - - /* Enabling interfacing with usb through OCP */ - i2c_read(0x48, 0xFE, 1, &data, 1); // read BOOT_BCI - data |= 0x01; // PHY_DPLL_CLK - i2c_write(0x48, 0xFE, 1, &data, 1); // write BOOT_BCI - - do { - udelay(10); - i2c_read(0x48, 0xFE, 1, &data, 1); // read PHY_CLK_CTRL_STS - } while (!(data & 0x01)); /* loop until PHY DPLL is locked */ - - /* OTG_EN (POWER_CTRL[5]) to 1 */ - data = 0x20; - i2c_write(0x48, 0xAD, 1, &data, 1); // write POWER_CTRL_SET - - for(i=0; i<50; i++) - udelay(1000); - - /* forcing USBFASTMCHG(BCIMFSTS4[2]) to 1 */ - i2c_read(0x4A, 0x84, 1, &data, 1); // read BCIMFSTS4 - data |= 0x04; // USBFASTMCHG - i2c_write(0x4A, 0x84, 1, &data, 1); // write BCIMFSTS4 - -#endif - return 0; -} - -/************************************************************* - * get_device_type(): tell if GP/HS/EMU/TST - *************************************************************/ -u32 get_device_type(void) -{ - int mode; - mode = __raw_readl(CONTROL_STATUS) & (DEVICE_MASK); - return mode >>= 8; -} - -/************************************************ - * get_sysboot_value(void) - return SYS_BOOT[4:0] - ************************************************/ -u32 get_sysboot_value(void) -{ - int mode; - mode = __raw_readl(CONTROL_STATUS) & (SYSBOOT_MASK); - return mode; -} - -/************************************************************* - * Routine: get_mem_type(void) - returns the kind of memory connected - * to GPMC that we are trying to boot form. Uses SYS BOOT settings. - *************************************************************/ -u32 get_mem_type(void) -{ - u32 mem_type = get_sysboot_value(); - switch (mem_type) { - case 0: - case 2: - case 4: - case 16: - case 22: - return GPMC_ONENAND; - - case 1: - case 12: - case 15: - case 21: - case 27: - return GPMC_NAND; - - case 3: - case 6: - return MMC_ONENAND; - - case 8: - case 11: - case 14: - case 20: - case 26: - return GPMC_MDOC; - - case 17: - case 18: - case 24: - return MMC_NAND; - - case 7: - case 10: - case 13: - case 19: - case 25: - default: - return GPMC_NOR; - } -} - -/****************************************** - * get_cpu_type(void) - extract cpu info - ******************************************/ -u32 get_cpu_type(void) -{ - return __raw_readl(CONTROL_OMAP_STATUS); -} - -/****************************************** - * get_cpu_id(void) - extract cpu id - * returns 0 for ES1.0, cpuid otherwise - ******************************************/ -u32 get_cpu_id(void) -{ - u32 cpuid = 0; - - /* - * On ES1.0 the IDCODE register is not exposed on L4 - * so using CPU ID to differentiate between ES1.0 and > ES1.0. - */ - __asm__ __volatile__("mrc p15, 0, %0, c0, c0, 0":"=r"(cpuid)); - if ((cpuid & 0xf) == 0x0) { - return 0; - } else { - /* Decode the IDs on > ES1.0 */ - cpuid = __raw_readl(CONTROL_IDCODE); - } - - return cpuid; -} - -/****************************************** - * get_cpu_family(void) - extract cpu info - ******************************************/ -u32 get_cpu_family(void) -{ - u16 hawkeye; - u32 cpu_family; - u32 cpuid = get_cpu_id(); - - if (cpuid == 0) - return CPU_OMAP34XX; - - hawkeye = (cpuid >> HAWKEYE_SHIFT) & 0xffff; - switch (hawkeye) { - case HAWKEYE_OMAP34XX: - cpu_family = CPU_OMAP34XX; - break; - case HAWKEYE_AM35XX: - cpu_family = CPU_AM35XX; - break; - case HAWKEYE_OMAP36XX: - cpu_family = CPU_OMAP36XX; - break; - default: - cpu_family = CPU_OMAP34XX; - } - - return cpu_family; -} - -/****************************************** - * get_cpu_rev(void) - extract version info - ******************************************/ -u32 get_cpu_rev(void) -{ - u32 cpuid = 0; - /* On ES1.0 the IDCODE register is not exposed on L4 - * so using CPU ID to differentiate - * between ES2.0 and ES1.0. - */ - __asm__ __volatile__("mrc p15, 0, %0, c0, c0, 0":"=r" (cpuid)); - if ((cpuid & 0xf) == 0x0) - return CPU_3430_ES1; - else - return CPU_3430_ES2; - -} - -/****************************************** - * Print CPU information - ******************************************/ -int print_cpuinfo (void) -{ - char *cpu_family_s, *cpu_s, *sec_s; - - switch (get_cpu_family()) { - case CPU_OMAP34XX: - cpu_family_s = "OMAP"; - switch (get_cpu_type()) { - case OMAP3503: - cpu_s = "3503"; - break; - case OMAP3515: - cpu_s = "3515"; - break; - case OMAP3525: - cpu_s = "3525"; - break; - case OMAP3530: - cpu_s = "3530"; - break; - default: - cpu_s = "35XX"; - break; - } - break; - case CPU_AM35XX: - cpu_family_s = "AM"; - switch (get_cpu_type()) { - case AM3505: - cpu_s = "3505"; - break; - case AM3517: - cpu_s = "3517"; - break; - default: - cpu_s = "35XX"; - break; - } - break; - case CPU_OMAP36XX: - cpu_family_s = "OMAP"; - switch (get_cpu_type()) { - case OMAP3730: - cpu_s = "3630/3730"; - break; - default: - cpu_s = "36XX/37XX"; - break; - } - break; - default: - cpu_family_s = "OMAP"; - cpu_s = "35XX"; - } - - switch (get_device_type()) { - case TST_DEVICE: - sec_s = "TST"; - break; - case EMU_DEVICE: - sec_s = "EMU"; - break; - case HS_DEVICE: - sec_s = "HS"; - break; - case GP_DEVICE: - sec_s = "GP"; - break; - default: - sec_s = "?"; - } - - printf("%s%s-%s ES%s\n", - cpu_family_s, cpu_s, sec_s, rev_s[get_cpu_rev()]); - - return 0; -} - -/****************************************** - * cpu_is_3410(void) - returns true for 3410 - ******************************************/ -u32 cpu_is_3410(void) -{ - int status; - if (get_cpu_rev() < CPU_3430_ES2) { - return 0; - } else { - /* read scalability status and return 1 for 3410*/ - status = __raw_readl(CONTROL_SCALABLE_OMAP_STATUS); - /* Check whether MPU frequency is set to 266 MHz which - * is nominal for 3410. If yes return true else false - */ - if (((status >> 8) & 0x3) == 0x2) - return 1; - else - return 0; - } -} - -int gta04_revision(void) -{ - int rev; - static char revision[8] = { /* revision table defined by pull-down R305, R306, R307 */ - 9, - 6, - 7, - 3, - 8, - 4, - 5, - 2 - }; - omap_request_gpio(171); - omap_request_gpio(172); - omap_request_gpio(173); - omap_set_gpio_direction(171, 1); - omap_set_gpio_direction(172, 1); - omap_set_gpio_direction(173, 1); - - rev = omap_get_gpio_datain(173) << 2 | - omap_get_gpio_datain(172) << 1 | - omap_get_gpio_datain(171) << 0; - omap_free_gpio(171); - omap_free_gpio(172); - omap_free_gpio(173); - - return revision[rev]; /* 000 means GTA04A2 */ -} - -/***************************************************************** - * sr32 - clear & set a value in a bit range for a 32 bit address - *****************************************************************/ -void sr32(u32 addr, u32 start_bit, u32 num_bits, u32 value) -{ - u32 tmp, msk = 0; - msk = 1 << num_bits; - --msk; - tmp = __raw_readl(addr) & ~(msk << start_bit); - tmp |= value << start_bit; - __raw_writel(tmp, addr); -} - -/********************************************************************* - * wait_on_value() - common routine to allow waiting for changes in - * volatile regs. - *********************************************************************/ -u32 wait_on_value(u32 read_bit_mask, u32 match_value, u32 read_addr, u32 bound) -{ - u32 i = 0, val; - do { - ++i; - val = __raw_readl(read_addr) & read_bit_mask; - if (val == match_value) - return 1; - if (i == bound) - return 0; - } while (1); -} - -#ifdef CFG_3430SDRAM_DDR - -#define MICRON_DDR 0 -#define NUMONYX_MCP 1 -#define MICRON_MCP 2 - -int identify_xm_ddr(void) -{ -#ifdef CONFIG_NAND - - int mfr, id; - extern int nand_readid(int *mfr, int *id); - - __raw_writel(M_NAND_GPMC_CONFIG1, GPMC_CONFIG1 + GPMC_CONFIG_CS0); - __raw_writel(M_NAND_GPMC_CONFIG2, GPMC_CONFIG2 + GPMC_CONFIG_CS0); - __raw_writel(M_NAND_GPMC_CONFIG3, GPMC_CONFIG3 + GPMC_CONFIG_CS0); - __raw_writel(M_NAND_GPMC_CONFIG4, GPMC_CONFIG4 + GPMC_CONFIG_CS0); - __raw_writel(M_NAND_GPMC_CONFIG5, GPMC_CONFIG5 + GPMC_CONFIG_CS0); - __raw_writel(M_NAND_GPMC_CONFIG6, GPMC_CONFIG6 + GPMC_CONFIG_CS0); - - /* Enable the GPMC Mapping */ - __raw_writel((((OMAP34XX_GPMC_CS0_SIZE & 0xF)<<8) | - ((NAND_BASE_ADR>>24) & 0x3F) | - (1<<6)), (GPMC_CONFIG7 + GPMC_CONFIG_CS0)); - delay(2000); - - nand_readid(&mfr, &id); - if (mfr == 0) - return MICRON_DDR; - if ((mfr == 0x20) && (id == 0xba)) - return NUMONYX_MCP; - if ((mfr == 0x2c) && (id == 0xbc)) - return MICRON_MCP; -#endif - return 0; -} - -/********************************************************************* - * config_3430sdram_ddr() - Init DDR on 3430SDP dev board. - *********************************************************************/ -void config_3430sdram_ddr(void) -{ - /* reset sdrc controller */ - __raw_writel(SOFTRESET, SDRC_SYSCONFIG); - wait_on_value(BIT0, BIT0, SDRC_STATUS, 12000000); - __raw_writel(0, SDRC_SYSCONFIG); - - /* setup sdrc to ball mux */ - __raw_writel(SDP_SDRC_SHARING, SDRC_SHARING); - - // FIXME: can we not only read the chip maker but also bus clock speed and bank size??? - - switch (identify_xm_ddr()) { - case NUMONYX_MCP: - // should not be used on GTA04 - __raw_writel(0x4, SDRC_CS_CFG); /* 512MB/bank */ - __raw_writel(SDP_SDRC_MDCFG_0_DDR_NUMONYX_XM, SDRC_MCFG_0); - __raw_writel(SDP_SDRC_MDCFG_0_DDR_NUMONYX_XM, SDRC_MCFG_1); - __raw_writel(NUMONYX_V_ACTIMA_165, SDRC_ACTIM_CTRLA_0); - __raw_writel(NUMONYX_V_ACTIMB_165, SDRC_ACTIM_CTRLB_0); - __raw_writel(NUMONYX_V_ACTIMA_165, SDRC_ACTIM_CTRLA_1); - __raw_writel(NUMONYX_V_ACTIMB_165, SDRC_ACTIM_CTRLB_1); - __raw_writel(SDP_3430_SDRC_RFR_CTRL_165MHz, SDRC_RFR_CTRL_0); - __raw_writel(SDP_3430_SDRC_RFR_CTRL_165MHz, SDRC_RFR_CTRL_1); - break; - case MICRON_MCP: - // big Micron - __raw_writel(0x2, SDRC_CS_CFG); /* 256MB/bank */ - __raw_writel(SDP_SDRC_MDCFG_0_DDR_MICRON_XM, SDRC_MCFG_0); - __raw_writel(SDP_SDRC_MDCFG_0_DDR_MICRON_XM, SDRC_MCFG_1); - __raw_writel(MICRON_V_ACTIMA_200, SDRC_ACTIM_CTRLA_0); - __raw_writel(MICRON_V_ACTIMB_200, SDRC_ACTIM_CTRLB_0); - __raw_writel(MICRON_V_ACTIMA_200, SDRC_ACTIM_CTRLA_1); - __raw_writel(MICRON_V_ACTIMB_200, SDRC_ACTIM_CTRLB_1); - __raw_writel(SDP_3430_SDRC_RFR_CTRL_200MHz, SDRC_RFR_CTRL_0); - __raw_writel(SDP_3430_SDRC_RFR_CTRL_200MHz, SDRC_RFR_CTRL_1); - break; - case MICRON_DDR: - default: - // small micron - __raw_writel(0x1, SDRC_CS_CFG); /* 128MB/bank */ - __raw_writel(SDP_SDRC_MDCFG_0_DDR, SDRC_MCFG_0); - __raw_writel(SDP_SDRC_MDCFG_0_DDR, SDRC_MCFG_1); - __raw_writel(MICRON_V_ACTIMA_165, SDRC_ACTIM_CTRLA_0); - __raw_writel(MICRON_V_ACTIMB_165, SDRC_ACTIM_CTRLB_0); - __raw_writel(MICRON_V_ACTIMA_165, SDRC_ACTIM_CTRLA_1); - __raw_writel(MICRON_V_ACTIMB_165, SDRC_ACTIM_CTRLB_1); - __raw_writel(SDP_3430_SDRC_RFR_CTRL_165MHz, SDRC_RFR_CTRL_0); - __raw_writel(SDP_3430_SDRC_RFR_CTRL_165MHz, SDRC_RFR_CTRL_1); - break; - } - - __raw_writel(SDP_SDRC_POWER_POP, SDRC_POWER); - - /* init sequence for mDDR/mSDR using manual commands (DDR is different) */ - __raw_writel(CMD_NOP, SDRC_MANUAL_0); - __raw_writel(CMD_NOP, SDRC_MANUAL_1); - - delay(5000); - - __raw_writel(CMD_PRECHARGE, SDRC_MANUAL_0); - __raw_writel(CMD_PRECHARGE, SDRC_MANUAL_1); - - __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0); - __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_1); - - __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0); - __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_1); - - /* set mr0 */ - __raw_writel(SDP_SDRC_MR_0_DDR, SDRC_MR_0); - __raw_writel(SDP_SDRC_MR_0_DDR, SDRC_MR_1); - - /* set up dll */ - __raw_writel(SDP_SDRC_DLLAB_CTRL, SDRC_DLLA_CTRL); - delay(0x2000); /* give time to lock */ - -} -#endif /* CFG_3430SDRAM_DDR */ - -/************************************************************* - * get_sys_clk_speed - determine reference oscillator speed - * based on known 32kHz clock and gptimer. - *************************************************************/ -u32 get_osc_clk_speed(void) -{ - u32 start, cstart, cend, cdiff, cdiv, val; - - val = __raw_readl(PRM_CLKSRC_CTRL); - - if (val & SYSCLKDIV_2) - cdiv = 2; - else - cdiv = 1; - - /* enable timer2 */ - val = __raw_readl(CM_CLKSEL_WKUP) | BIT0; - __raw_writel(val, CM_CLKSEL_WKUP); /* select sys_clk for GPT1 */ - - /* Enable I and F Clocks for GPT1 */ - val = __raw_readl(CM_ICLKEN_WKUP) | BIT0 | BIT2; - __raw_writel(val, CM_ICLKEN_WKUP); - val = __raw_readl(CM_FCLKEN_WKUP) | BIT0; - __raw_writel(val, CM_FCLKEN_WKUP); - - __raw_writel(0, OMAP34XX_GPT1 + TLDR); /* start counting at 0 */ - __raw_writel(GPT_EN, OMAP34XX_GPT1 + TCLR); /* enable clock */ - /* enable 32kHz source */ - /* enabled out of reset */ - /* determine sys_clk via gauging */ - - start = 20 + __raw_readl(S32K_CR); /* start time in 20 cycles */ - while (__raw_readl(S32K_CR) < start) ; /* dead loop till start time */ - cstart = __raw_readl(OMAP34XX_GPT1 + TCRR); /* get start sys_clk count */ - while (__raw_readl(S32K_CR) < (start + 20)) ; /* wait for 40 cycles */ - cend = __raw_readl(OMAP34XX_GPT1 + TCRR); /* get end sys_clk count */ - cdiff = cend - cstart; /* get elapsed ticks */ - cdiff *= cdiv; - - /* based on number of ticks assign speed */ - if (cdiff > 19000) - return S38_4M; - else if (cdiff > 15200) - return S26M; - else if (cdiff > 13000) - return S24M; - else if (cdiff > 9000) - return S19_2M; - else if (cdiff > 7600) - return S13M; - else - return S12M; -} - -/****************************************************************************** - * get_sys_clkin_sel() - returns the sys_clkin_sel field value based on - * -- input oscillator clock frequency. - * - *****************************************************************************/ -void get_sys_clkin_sel(u32 osc_clk, u32 *sys_clkin_sel) -{ - if (osc_clk == S38_4M) - *sys_clkin_sel = 4; - else if (osc_clk == S26M) - *sys_clkin_sel = 3; - else if (osc_clk == S19_2M) - *sys_clkin_sel = 2; - else if (osc_clk == S13M) - *sys_clkin_sel = 1; - else if (osc_clk == S12M) - *sys_clkin_sel = 0; -} - -/****************************************************************************** - * prcm_init() - inits clocks for PRCM as defined in clocks.h - * -- called from SRAM, or Flash (using temp SRAM stack). - *****************************************************************************/ -void prcm_init(void) -{ - u32 osc_clk = 0, sys_clkin_sel; - dpll_param *dpll_param_p; - u32 clk_index, sil_index; - - /* Gauge the input clock speed and find out the sys_clkin_sel - * value corresponding to the input clock. - */ - osc_clk = get_osc_clk_speed(); - get_sys_clkin_sel(osc_clk, &sys_clkin_sel); - - sr32(PRM_CLKSEL, 0, 3, sys_clkin_sel); /* set input crystal speed */ - - /* If the input clock is greater than 19.2M always divide/2 */ - if (sys_clkin_sel > 2) { - sr32(PRM_CLKSRC_CTRL, 6, 2, 2); /* input clock divider */ - clk_index = sys_clkin_sel / 2; - } else { - sr32(PRM_CLKSRC_CTRL, 6, 2, 1); /* input clock divider */ - clk_index = sys_clkin_sel; - } - - sr32(PRM_CLKSRC_CTRL, 0, 2, 0);/* Bypass mode: T2 inputs a square clock */ - - /* The DPLL tables are defined according to sysclk value and - * silicon revision. The clk_index value will be used to get - * the values for that input sysclk from the DPLL param table - * and sil_index will get the values for that SysClk for the - * appropriate silicon rev. - */ - sil_index = get_cpu_rev() - 1; - - /* Unlock MPU DPLL (slows things down, and needed later) */ - sr32(CM_CLKEN_PLL_MPU, 0, 3, PLL_LOW_POWER_BYPASS); - wait_on_value(BIT0, 0, CM_IDLEST_PLL_MPU, LDELAY); - - /* Getting the base address of Core DPLL param table */ - dpll_param_p = (dpll_param *) get_core_dpll_param(); - /* Moving it to the right sysclk and ES rev base */ - dpll_param_p = dpll_param_p + 3 * clk_index + sil_index; - /* CORE DPLL */ - /* sr32(CM_CLKSEL2_EMU) set override to work when asleep */ - sr32(CM_CLKEN_PLL, 0, 3, PLL_FAST_RELOCK_BYPASS); - wait_on_value(BIT0, 0, CM_IDLEST_CKGEN, LDELAY); - - /* For 3430 ES1.0 Errata 1.50, default value directly doesnt - work. write another value and then default value. */ - sr32(CM_CLKSEL1_EMU, 16, 5, CORE_M3X2 + 1); /* m3x2 */ - sr32(CM_CLKSEL1_EMU, 16, 5, CORE_M3X2); /* m3x2 */ - sr32(CM_CLKSEL1_PLL, 27, 2, dpll_param_p->m2); /* Set M2 */ - sr32(CM_CLKSEL1_PLL, 16, 11, dpll_param_p->m); /* Set M */ - sr32(CM_CLKSEL1_PLL, 8, 7, dpll_param_p->n); /* Set N */ - sr32(CM_CLKSEL1_PLL, 6, 1, 0); /* 96M Src */ - sr32(CM_CLKSEL_CORE, 8, 4, CORE_SSI_DIV); /* ssi */ - sr32(CM_CLKSEL_CORE, 4, 2, CORE_FUSB_DIV); /* fsusb */ - sr32(CM_CLKSEL_CORE, 2, 2, CORE_L4_DIV); /* l4 */ - sr32(CM_CLKSEL_CORE, 0, 2, CORE_L3_DIV); /* l3 */ - sr32(CM_CLKSEL_GFX, 0, 3, GFX_DIV); /* gfx */ - sr32(CM_CLKSEL_WKUP, 1, 2, WKUP_RSM); /* reset mgr */ - sr32(CM_CLKEN_PLL, 4, 4, dpll_param_p->fsel); /* FREQSEL */ - sr32(CM_CLKEN_PLL, 0, 3, PLL_LOCK); /* lock mode */ - wait_on_value(BIT0, 1, CM_IDLEST_CKGEN, LDELAY); - - /* Getting the base address to PER DPLL param table */ - dpll_param_p = (dpll_param *) get_per_dpll_param(); - /* Moving it to the right sysclk base */ - dpll_param_p = dpll_param_p + clk_index; - /* PER DPLL */ - sr32(CM_CLKEN_PLL, 16, 3, PLL_STOP); - wait_on_value(BIT1, 0, CM_IDLEST_CKGEN, LDELAY); - sr32(CM_CLKSEL1_EMU, 24, 5, PER_M6X2); /* set M6 */ - sr32(CM_CLKSEL_CAM, 0, 5, PER_M5X2); /* set M5 */ - sr32(CM_CLKSEL_DSS, 0, 5, PER_M4X2); /* set M4 */ - sr32(CM_CLKSEL_DSS, 8, 5, PER_M3X2); /* set M3 */ - - if (get_cpu_family() == CPU_OMAP36XX) { - sr32(CM_CLKSEL3_PLL, 0, 5, CORE_DPLL_PARAM_M2); /* set M2 */ - sr32(CM_CLKSEL2_PLL, 8, 11, CORE_DPLL_PARAM_M); /* set m */ - sr32(CM_CLKSEL2_PLL, 0, 7, CORE_DPLL_PARAM_N); /* set n */ - } else { - sr32(CM_CLKSEL3_PLL, 0, 5, dpll_param_p->m2); /* set M2 */ - sr32(CM_CLKSEL2_PLL, 8, 11, dpll_param_p->m); /* set m */ - sr32(CM_CLKSEL2_PLL, 0, 7, dpll_param_p->n); /* set n */ - } - - sr32(CM_CLKEN_PLL, 20, 4, dpll_param_p->fsel); /* FREQSEL */ - sr32(CM_CLKEN_PLL, 16, 3, PLL_LOCK); /* lock mode */ - wait_on_value(BIT1, 2, CM_IDLEST_CKGEN, LDELAY); - - /* Getting the base address to MPU DPLL param table */ - dpll_param_p = (dpll_param *) get_mpu_dpll_param(); - - /* Moving it to the right sysclk and ES rev base */ - dpll_param_p = dpll_param_p + 3 * clk_index + sil_index; - - /* MPU DPLL (unlocked already) */ - sr32(CM_CLKSEL2_PLL_MPU, 0, 5, dpll_param_p->m2); /* Set M2 */ - sr32(CM_CLKSEL1_PLL_MPU, 8, 11, dpll_param_p->m); /* Set M */ - sr32(CM_CLKSEL1_PLL_MPU, 0, 7, dpll_param_p->n); /* Set N */ - sr32(CM_CLKEN_PLL_MPU, 4, 4, dpll_param_p->fsel); /* FREQSEL */ - sr32(CM_CLKEN_PLL_MPU, 0, 3, PLL_LOCK); /* lock mode */ - wait_on_value(BIT0, 1, CM_IDLEST_PLL_MPU, LDELAY); - - /* Getting the base address to IVA DPLL param table */ - dpll_param_p = (dpll_param *) get_iva_dpll_param(); - /* Moving it to the right sysclk and ES rev base */ - dpll_param_p = dpll_param_p + 3 * clk_index + sil_index; - /* IVA DPLL (set to 12*20=240MHz) */ - sr32(CM_CLKEN_PLL_IVA2, 0, 3, PLL_STOP); - wait_on_value(BIT0, 0, CM_IDLEST_PLL_IVA2, LDELAY); - sr32(CM_CLKSEL2_PLL_IVA2, 0, 5, dpll_param_p->m2); /* set M2 */ - sr32(CM_CLKSEL1_PLL_IVA2, 8, 11, dpll_param_p->m); /* set M */ - sr32(CM_CLKSEL1_PLL_IVA2, 0, 7, dpll_param_p->n); /* set N */ - sr32(CM_CLKEN_PLL_IVA2, 4, 4, dpll_param_p->fsel); /* FREQSEL */ - sr32(CM_CLKEN_PLL_IVA2, 0, 3, PLL_LOCK); /* lock mode */ - wait_on_value(BIT0, 1, CM_IDLEST_PLL_IVA2, LDELAY); - - /* Set up GPTimers to sys_clk source only */ - sr32(CM_CLKSEL_PER, 0, 8, 0xff); - sr32(CM_CLKSEL_WKUP, 0, 1, 1); - - delay(5000); -} - -/***************************************** - * Routine: secure_unlock - * Description: Setup security registers for access - * (GP Device only) - *****************************************/ -void secure_unlock(void) -{ - /* Permission values for registers -Full fledged permissions to all */ -#define UNLOCK_1 0xFFFFFFFF -#define UNLOCK_2 0x00000000 -#define UNLOCK_3 0x0000FFFF - /* Protection Module Register Target APE (PM_RT) */ - __raw_writel(UNLOCK_1, RT_REQ_INFO_PERMISSION_1); - __raw_writel(UNLOCK_1, RT_READ_PERMISSION_0); - __raw_writel(UNLOCK_1, RT_WRITE_PERMISSION_0); - __raw_writel(UNLOCK_2, RT_ADDR_MATCH_1); - - __raw_writel(UNLOCK_3, GPMC_REQ_INFO_PERMISSION_0); - __raw_writel(UNLOCK_3, GPMC_READ_PERMISSION_0); - __raw_writel(UNLOCK_3, GPMC_WRITE_PERMISSION_0); - - __raw_writel(UNLOCK_3, OCM_REQ_INFO_PERMISSION_0); - __raw_writel(UNLOCK_3, OCM_READ_PERMISSION_0); - __raw_writel(UNLOCK_3, OCM_WRITE_PERMISSION_0); - __raw_writel(UNLOCK_2, OCM_ADDR_MATCH_2); - - /* IVA Changes */ - __raw_writel(UNLOCK_3, IVA2_REQ_INFO_PERMISSION_0); - __raw_writel(UNLOCK_3, IVA2_READ_PERMISSION_0); - __raw_writel(UNLOCK_3, IVA2_WRITE_PERMISSION_0); - - __raw_writel(UNLOCK_1, SMS_RG_ATT0); /* SDRC region 0 public */ -} - -/********************************************************** - * Routine: try_unlock_sram() - * Description: If chip is GP type, unlock the SRAM for - * general use. - ***********************************************************/ -void try_unlock_memory(void) -{ - int mode; - - /* if GP device unlock device SRAM for general use */ - /* secure code breaks for Secure/Emulation device - HS/E/T */ - mode = get_device_type(); - if (mode == GP_DEVICE) - secure_unlock(); - return; -} - -/********************************************************** - * Routine: s_init - * Description: Does early system init of muxing and clocks. - * - Called at time when only stack is available. - **********************************************************/ - -void s_init(void) -{ - watchdog_init(); -#ifdef CONFIG_3430_AS_3410 - /* setup the scalability control register for - * 3430 to work in 3410 mode - */ - __raw_writel(0x5ABF, CONTROL_SCALABLE_OMAP_OCP); -#endif - try_unlock_memory(); - set_muxconf_regs(); - delay(100); - per_clocks_enable(); - prcm_init(); - config_3430sdram_ddr(); -} - -/******************************************************* - * Routine: misc_init_r - * Description: Init ethernet (done here so udelay works) - ********************************************************/ -int misc_init_r(void) -{ - int rev; - print_cpuinfo(); - rev = gta04_revision(); - printf("Board detected: GTA04A%d\n", rev); - switch (identify_xm_ddr()) { - case NUMONYX_MCP: printf("Memory: Numonyx MCP 512MB/bank\n"); break; - case MICRON_MCP: printf("Memory: Micron MCP 256MB/bank\n"); break; - case MICRON_DDR: printf("Memory: Micron DDR 128MB/bank\n"); break; - default: printf("Memory: unknown 128MB/bank\n"); break; - } - return 0; -} - -/****************************************************** - * Routine: wait_for_command_complete - * Description: Wait for posting to finish on watchdog - ******************************************************/ -void wait_for_command_complete(unsigned int wd_base) -{ - int pending = 1; - do { - pending = __raw_readl(wd_base + WWPS); - } while (pending); -} - -/**************************************** - * Routine: watchdog_init - * Description: Shut down watch dogs - *****************************************/ -void watchdog_init(void) -{ - /* There are 3 watch dogs WD1=Secure, WD2=MPU, WD3=IVA. WD1 is - * either taken care of by ROM (HS/EMU) or not accessible (GP). - * We need to take care of WD2-MPU or take a PRCM reset. WD3 - * should not be running and does not generate a PRCM reset. - */ - sr32(CM_FCLKEN_WKUP, 5, 1, 1); - sr32(CM_ICLKEN_WKUP, 5, 1, 1); - wait_on_value(BIT5, 0x20, CM_IDLEST_WKUP, 5); /* some issue here */ - - __raw_writel(WD_UNLOCK1, WD2_BASE + WSPR); - wait_for_command_complete(WD2_BASE); - __raw_writel(WD_UNLOCK2, WD2_BASE + WSPR); -} - -/********************************************** - * Routine: dram_init - * Description: sets uboots idea of sdram size - **********************************************/ -int dram_init(void) -{ - return 0; -} - -/***************************************************************** - * Routine: peripheral_enable - * Description: Enable the clks & power for perifs (GPT2, UART1,...) - ******************************************************************/ -void per_clocks_enable(void) -{ - /* Enable GP2 timer. */ - sr32(CM_CLKSEL_PER, 0, 1, 0x1); /* GPT2 = sys clk */ - sr32(CM_ICLKEN_PER, 3, 1, 0x1); /* ICKen GPT2 */ - sr32(CM_FCLKEN_PER, 3, 1, 0x1); /* FCKen GPT2 */ - -#ifdef CFG_NS16550 - /* UART1 clocks */ - sr32(CM_FCLKEN1_CORE, 13, 1, 0x1); - sr32(CM_ICLKEN1_CORE, 13, 1, 0x1); - - /* UART 3 Clocks */ - sr32(CM_FCLKEN_PER, 11, 1, 0x1); - sr32(CM_ICLKEN_PER, 11, 1, 0x1); - -#endif - -#ifdef CONFIG_DRIVER_OMAP34XX_I2C - /* Turn on all 3 I2C clocks */ - sr32(CM_FCLKEN1_CORE, 15, 3, 0x7); - sr32(CM_ICLKEN1_CORE, 15, 3, 0x7); /* I2C1,2,3 = on */ -#endif - - /* Enable the ICLK for 32K Sync Timer as its used in udelay */ - sr32(CM_ICLKEN_WKUP, 2, 1, 0x1); - - sr32(CM_FCLKEN_IVA2, 0, 32, FCK_IVA2_ON); - sr32(CM_FCLKEN1_CORE, 0, 32, FCK_CORE1_ON); - sr32(CM_ICLKEN1_CORE, 0, 32, ICK_CORE1_ON); - sr32(CM_ICLKEN2_CORE, 0, 32, ICK_CORE2_ON); - sr32(CM_FCLKEN_WKUP, 0, 32, FCK_WKUP_ON); - sr32(CM_ICLKEN_WKUP, 0, 32, ICK_WKUP_ON); - sr32(CM_FCLKEN_DSS, 0, 32, FCK_DSS_ON); - sr32(CM_ICLKEN_DSS, 0, 32, ICK_DSS_ON); - sr32(CM_FCLKEN_CAM, 0, 32, FCK_CAM_ON); - sr32(CM_ICLKEN_CAM, 0, 32, ICK_CAM_ON); - sr32(CM_FCLKEN_PER, 0, 32, FCK_PER_ON); - sr32(CM_ICLKEN_PER, 0, 32, ICK_PER_ON); - - /* Enable GPIO 5 & GPIO 6 clocks */ - sr32(CM_FCLKEN_PER, 17, 2, 0x3); - sr32(CM_ICLKEN_PER, 17, 2, 0x3); - - delay(1000); -} - -/* Set MUX for UART, GPMC, SDRC, GPIO */ - -#define MUX_VAL(OFFSET,VALUE)\ - __raw_writew((VALUE), OMAP34XX_CTRL_BASE + (OFFSET)); - -#define CP(x) (CONTROL_PADCONF_##x) -/* - * IEN - Input Enable - * IDIS - Input Disable - * PTD - Pull type Down - * PTU - Pull type Up - * DIS - Pull type selection is inactive - * EN - Pull type selection is active - * M0 - Mode 0 - * The commented string gives the final mux configuration for that pin - */ -#define MUX_DEFAULT()\ - MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /*SDRC_D0*/\ - MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /*SDRC_D1*/\ - MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /*SDRC_D2*/\ - MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /*SDRC_D3*/\ - MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /*SDRC_D4*/\ - MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /*SDRC_D5*/\ - MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /*SDRC_D6*/\ - MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /*SDRC_D7*/\ - MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /*SDRC_D8*/\ - MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /*SDRC_D9*/\ - MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /*SDRC_D10*/\ - MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /*SDRC_D11*/\ - MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /*SDRC_D12*/\ - MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /*SDRC_D13*/\ - MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /*SDRC_D14*/\ - MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /*SDRC_D15*/\ - MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /*SDRC_D16*/\ - MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /*SDRC_D17*/\ - MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /*SDRC_D18*/\ - MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /*SDRC_D19*/\ - MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /*SDRC_D20*/\ - MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /*SDRC_D21*/\ - MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /*SDRC_D22*/\ - MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /*SDRC_D23*/\ - MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /*SDRC_D24*/\ - MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /*SDRC_D25*/\ - MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /*SDRC_D26*/\ - MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /*SDRC_D27*/\ - MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /*SDRC_D28*/\ - MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /*SDRC_D29*/\ - MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /*SDRC_D30*/\ - MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /*SDRC_D31*/\ - MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /*SDRC_CLK*/\ - MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /*SDRC_DQS0*/\ - MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /*SDRC_DQS1*/\ - MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /*SDRC_DQS2*/\ - MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /*SDRC_DQS3*/\ - MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0)) /*GPMC_A1*/\ - MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0)) /*GPMC_A2*/\ - MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0)) /*GPMC_A3*/\ - MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0)) /*GPMC_A4*/\ - MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0)) /*GPMC_A5*/\ - MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0)) /*GPMC_A6*/\ - MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0)) /*GPMC_A7*/\ - MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0)) /*GPMC_A8*/\ - MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M0)) /*GPMC_A9*/\ - MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0)) /*GPMC_A10*/\ - MUX_VAL(CP(GPMC_D0), (IEN | PTD | DIS | M0)) /*GPMC_D0*/\ - MUX_VAL(CP(GPMC_D1), (IEN | PTD | DIS | M0)) /*GPMC_D1*/\ - MUX_VAL(CP(GPMC_D2), (IEN | PTD | DIS | M0)) /*GPMC_D2*/\ - MUX_VAL(CP(GPMC_D3), (IEN | PTD | DIS | M0)) /*GPMC_D3*/\ - MUX_VAL(CP(GPMC_D4), (IEN | PTD | DIS | M0)) /*GPMC_D4*/\ - MUX_VAL(CP(GPMC_D5), (IEN | PTD | DIS | M0)) /*GPMC_D5*/\ - MUX_VAL(CP(GPMC_D6), (IEN | PTD | DIS | M0)) /*GPMC_D6*/\ - MUX_VAL(CP(GPMC_D7), (IEN | PTD | DIS | M0)) /*GPMC_D7*/\ - MUX_VAL(CP(GPMC_D8), (IEN | PTD | DIS | M0)) /*GPMC_D8*/\ - MUX_VAL(CP(GPMC_D9), (IEN | PTD | DIS | M0)) /*GPMC_D9*/\ - MUX_VAL(CP(GPMC_D10), (IEN | PTD | DIS | M0)) /*GPMC_D10*/\ - MUX_VAL(CP(GPMC_D11), (IEN | PTD | DIS | M0)) /*GPMC_D11*/\ - MUX_VAL(CP(GPMC_D12), (IEN | PTD | DIS | M0)) /*GPMC_D12*/\ - MUX_VAL(CP(GPMC_D13), (IEN | PTD | DIS | M0)) /*GPMC_D13*/\ - MUX_VAL(CP(GPMC_D14), (IEN | PTD | DIS | M0)) /*GPMC_D14*/\ - MUX_VAL(CP(GPMC_D15), (IEN | PTD | DIS | M0)) /*GPMC_D15*/\ - MUX_VAL(CP(GPMC_nCS0), (IDIS | PTU | EN | M0)) /*GPMC_nCS0*/\ - MUX_VAL(CP(GPMC_nCS1), (IDIS | PTU | EN | M0)) /*GPMC_nCS1*/\ - MUX_VAL(CP(GPMC_nCS2), (IDIS | PTU | EN | M0)) /*GPMC_nCS2*/\ - MUX_VAL(CP(GPMC_nCS3), (IDIS | PTU | EN | M0)) /*GPMC_nCS3*/\ - MUX_VAL(CP(GPMC_nCS4), (IDIS | PTU | EN | M0)) /*GPMC_nCS4*/\ - MUX_VAL(CP(GPMC_nCS5), (IDIS | PTD | DIS | M0)) /*GPMC_nCS5*/\ -MUX_VAL(CP(GPMC_nCS6), (IEN | PTD | DIS | M4)) /*GPMC_nCS6=gpio_57=gpt11_pwm*/\ - MUX_VAL(CP(GPMC_nCS7), (IEN | PTU | EN | M1)) /*GPMC_nCS7*/\ - MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M0)) /*GPMC_CLK*/\ - MUX_VAL(CP(GPMC_nADV_ALE), (IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\ - MUX_VAL(CP(GPMC_nOE), (IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\ - MUX_VAL(CP(GPMC_nWE), (IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\ - MUX_VAL(CP(GPMC_nBE0_CLE), (IDIS | PTD | DIS | M0)) /*GPMC_nBE0_CLE*/\ - MUX_VAL(CP(GPMC_nBE1), (IEN | PTD | DIS | M0)) /*GPIO_61*/\ - MUX_VAL(CP(GPMC_nWP), (IEN | PTD | DIS | M0)) /*GPMC_nWP*/\ - MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) /*GPMC_WAIT0*/\ - MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)) /*GPMC_WAIT1*/\ - MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M0)) /*GPIO_64*/\ - MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M0)) /*GPIO_65*/\ - MUX_VAL(CP(DSS_DATA18), (IEN | PTD | DIS | M4)) /*GPIO_88*/\ - MUX_VAL(CP(DSS_DATA19), (IEN | PTD | DIS | M4)) /*GPIO_89*/\ - MUX_VAL(CP(DSS_DATA20), (IEN | PTD | DIS | M4)) /*GPIO_90*/\ - MUX_VAL(CP(DSS_DATA21), (IEN | PTD | DIS | M4)) /*GPIO_91*/\ - MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4)) /*GPIO_167*/\ - MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)) /*MMC1_CLK*/\ - MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)) /*MMC1_CMD*/\ - MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)) /*MMC1_DAT0*/\ - MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)) /*MMC1_DAT1*/\ - MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)) /*MMC1_DAT2*/\ - MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)) /*MMC1_DAT3*/\ - MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M0)) /*MMC1_DAT4*/\ - MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M0)) /*MMC1_DAT5*/\ - MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M0)) /*MMC1_DAT6*/\ - MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M0)) /*MMC1_DAT7*/\ - MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /*UART1_TX*/\ - MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M4)) /*GPIO_149*/\ - MUX_VAL(CP(UART1_CTS), (IDIS | PTD | DIS | M4)) /*GPIO_150*/\ - MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /*UART1_RX*/\ -MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | EN | M4)) /*UART3_CTS_RCTX */\ -MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M4)) /*UART3_RTS_SD */\ - MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) /*UART3_RX_IRRX*/\ - MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) /*UART3_TX_IRTX*/\ - MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) /*I2C1_SCL*/\ - MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) /*I2C1_SDA*/\ - MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)) /*I2C2_SCL*/\ - MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)) /*I2C2_SDA*/\ - MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) /*I2C3_SCL*/\ - MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) /*I2C3_SDA*/\ - MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) /*I2C4_SCL*/\ - MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) /*I2C4_SDA*/\ - MUX_VAL(CP(McSPI1_CLK), (IEN | PTU | EN | M4)) /*GPIO_171*/\ - MUX_VAL(CP(McSPI1_SIMO), (IEN | PTU | EN | M4)) /*GPIO_172*/\ - MUX_VAL(CP(McSPI1_SOMI), (IEN | PTU | EN | M4)) /*GPIO_173*/\ - MUX_VAL(CP(McBSP1_DX), (IEN | PTD | DIS | M4)) /*GPIO_158*/\ - MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) /*SYS_32K*/\ - MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /*GPIO_2 */\ - MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) /*GPIO_3 */\ - MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /*GPIO_4 */\ - MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) /*GPIO_5 */\ - MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /*GPIO_6 */\ - MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /*GPIO_7 */\ - MUX_VAL(CP(SYS_BOOT6), (IEN | PTD | DIS | M4)) /*GPIO_8 */\ - MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTD | DIS | M4)) /*GPIO_186*/\ - MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0)) /*JTAG_nTRST*/\ - MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)) /*JTAG_TCK*/\ - MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)) /*JTAG_TMS*/\ - MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)) /*JTAG_TDI*/\ - MUX_VAL(CP(JTAG_EMU0), (IEN | PTD | DIS | M0)) /*JTAG_EMU0*/\ - MUX_VAL(CP(JTAG_EMU1), (IEN | PTD | DIS | M0)) /*JTAG_EMU1*/\ - MUX_VAL(CP(ETK_CLK), (IEN | PTD | DIS | M4)) /*GPIO_12*/\ -MUX_VAL(CP(ETK_CTL), (IEN | PTU | DIS | M4)) /*GPIO_13*/\ - MUX_VAL(CP(ETK_D0), (IEN | PTD | DIS | M4)) /*GPIO_14*/\ - MUX_VAL(CP(ETK_D1), (IEN | PTD | DIS | M4)) /*GPIO_15*/\ - MUX_VAL(CP(ETK_D2), (IEN | PTD | DIS | M4)) /*GPIO_16*/\ - MUX_VAL(CP(ETK_D11), (IEN | PTD | DIS | M4)) /*GPIO_25*/\ - MUX_VAL(CP(ETK_D12), (IEN | PTD | DIS | M4)) /*GPIO_26*/\ - MUX_VAL(CP(ETK_D13), (IEN | PTD | DIS | M4)) /*GPIO_27*/\ - MUX_VAL(CP(ETK_D14), (IEN | PTD | DIS | M4)) /*GPIO_28*/\ - MUX_VAL(CP(ETK_D15), (IEN | PTD | DIS | M4)) /*GPIO_29 */\ - MUX_VAL(CP(sdrc_cke0), (IDIS | PTU | EN | M0)) /*sdrc_cke0 */\ - MUX_VAL(CP(sdrc_cke1), (IDIS | PTD | DIS | M7)) /*sdrc_cke1 not used*/ - -/********************************************************** - * Routine: set_muxconf_regs - * Description: Setting up the configuration Mux registers - * specific to the hardware. Many pins need - * to be moved from protect to primary mode. - *********************************************************/ -void set_muxconf_regs(void) -{ - MUX_DEFAULT(); -#if 1 // enable backlight as first boot indication - MUX_VAL(CP(GPMC_nCS6), (IEN | PTU | EN | M4)); /*GPMC_nCS6=gpio_57=gpt11_pwm*/ -#endif -} - -/********************************************************** - * Routine: nand+_init - * Description: Set up nand for nand and jffs2 commands - *********************************************************/ - -int nand_init(void) -{ -#ifdef CONFIG_NAND - /* global settings */ - __raw_writel(0x10, GPMC_SYSCONFIG); /* smart idle */ - __raw_writel(0x0, GPMC_IRQENABLE); /* isr's sources masked */ - __raw_writel(0, GPMC_TIMEOUT_CONTROL);/* timeout disable */ - - /* Set the GPMC Vals, NAND is mapped at CS0, oneNAND at CS0. - * We configure only GPMC CS0 with required values. Configiring other devices - * at other CS is done in u-boot. So we don't have to bother doing it here. - */ - __raw_writel(0 , GPMC_CONFIG7 + GPMC_CONFIG_CS0); - delay(1000); - -#ifdef CFG_NAND_K9F1G08R0A - if ((get_mem_type() == GPMC_NAND) || (get_mem_type() == MMC_NAND)) { - __raw_writel(M_NAND_GPMC_CONFIG1, GPMC_CONFIG1 + GPMC_CONFIG_CS0); - __raw_writel(M_NAND_GPMC_CONFIG2, GPMC_CONFIG2 + GPMC_CONFIG_CS0); - __raw_writel(M_NAND_GPMC_CONFIG3, GPMC_CONFIG3 + GPMC_CONFIG_CS0); - __raw_writel(M_NAND_GPMC_CONFIG4, GPMC_CONFIG4 + GPMC_CONFIG_CS0); - __raw_writel(M_NAND_GPMC_CONFIG5, GPMC_CONFIG5 + GPMC_CONFIG_CS0); - __raw_writel(M_NAND_GPMC_CONFIG6, GPMC_CONFIG6 + GPMC_CONFIG_CS0); - - /* Enable the GPMC Mapping */ - __raw_writel((((OMAP34XX_GPMC_CS0_SIZE & 0xF)<<8) | - ((NAND_BASE_ADR>>24) & 0x3F) | - (1<<6)), (GPMC_CONFIG7 + GPMC_CONFIG_CS0)); - delay(2000); - - if (nand_chip()) { -#ifdef CFG_PRINTF - printf("Unsupported Chip!\n"); -#endif - return 1; - } - } -#endif - -#ifdef CFG_ONENAND - if ((get_mem_type() == GPMC_ONENAND) || (get_mem_type() == MMC_ONENAND)) { - __raw_writel(ONENAND_GPMC_CONFIG1, GPMC_CONFIG1 + GPMC_CONFIG_CS0); - __raw_writel(ONENAND_GPMC_CONFIG2, GPMC_CONFIG2 + GPMC_CONFIG_CS0); - __raw_writel(ONENAND_GPMC_CONFIG3, GPMC_CONFIG3 + GPMC_CONFIG_CS0); - __raw_writel(ONENAND_GPMC_CONFIG4, GPMC_CONFIG4 + GPMC_CONFIG_CS0); - __raw_writel(ONENAND_GPMC_CONFIG5, GPMC_CONFIG5 + GPMC_CONFIG_CS0); - __raw_writel(ONENAND_GPMC_CONFIG6, GPMC_CONFIG6 + GPMC_CONFIG_CS0); - - /* Enable the GPMC Mapping */ - __raw_writel((((OMAP34XX_GPMC_CS0_SIZE & 0xF)<<8) | - ((ONENAND_BASE>>24) & 0x3F) | - (1<<6)), (GPMC_CONFIG7 + GPMC_CONFIG_CS0)); - delay(2000); - - if (onenand_chip()) { -#ifdef CFG_PRINTF - printf("OneNAND Unsupported !\n"); -#endif - return 1; - } - } -#endif -#endif - return 0; -} - -// 57 for backlight - -#define DEBUG_LED1 149 /* gpio */ -// #define DEBUG_LED2 150 /* gpio */ - -void blinkLEDs(void) -{ - void *p; - - /* Alternately turn the LEDs on and off */ - p = (unsigned long *)OMAP34XX_GPIO5_BASE; - while (1) { - /* turn LED1 on and LED2 off */ - *(unsigned long *)(p + 0x94) = 1 << (DEBUG_LED1 % 32); -#ifdef DEBUG_LED2 - *(unsigned long *)(p + 0x90) = 1 << (DEBUG_LED2 % 32); -#endif - /* delay for a while */ - delay(1000); - - /* turn LED1 off and LED2 on */ - *(unsigned long *)(p + 0x90) = 1 << (DEBUG_LED1 % 32); -#ifdef DEBUG_LED2 - *(unsigned long *)(p + 0x94) = 1 << (DEBUG_LED2 % 32); -#endif - /* delay for a while */ - delay(1000); - } -} - -/* optionally do something like blinking LED */ -void board_hang(void) -{ - while (1) - blinkLEDs(); -} - -/****************************************************************************** - * Dummy function to handle errors for EABI incompatibility - *****************************************************************************/ -void raise(void) -{ -} - -/****************************************************************************** - * Dummy function to handle errors for EABI incompatibility - *****************************************************************************/ -void abort(void) -{ -} diff --git a/x-loader/board/omap3530gta04/platform.S b/x-loader/board/omap3530gta04/platform.S deleted file mode 100644 index 5869270..0000000 --- a/x-loader/board/omap3530gta04/platform.S +++ /dev/null @@ -1,360 +0,0 @@ -/* - * Board specific setup info - * - * (C) Copyright 2004-2006 - * Texas Instruments, <www.ti.com> - * Richard Woodruff <r-woodruff2@ti.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <config.h> -#include <asm/arch/cpu.h> -#include <asm/arch/mem.h> -#include <asm/arch/clocks.h> - -_TEXT_BASE: - .word TEXT_BASE /* sdram load addr from config.mk */ - -#if !defined(CFG_NAND_BOOT) && !defined(CFG_NAND_BOOT) -/************************************************************************** - * cpy_clk_code: relocates clock code into SRAM where its safer to execute - * R1 = SRAM destination address. - *************************************************************************/ -.global cpy_clk_code - cpy_clk_code: - /* Copy DPLL code into SRAM */ - adr r0, go_to_speed /* get addr of clock setting code */ - mov r2, #384 /* r2 size to copy (div by 32 bytes) */ - mov r1, r1 /* r1 <- dest address (passed in) */ - add r2, r2, r0 /* r2 <- source end address */ -next2: - ldmia r0!, {r3-r10} /* copy from source address [r0] */ - stmia r1!, {r3-r10} /* copy to target address [r1] */ - cmp r0, r2 /* until source end address [r2] */ - bne next2 - mov pc, lr /* back to caller */ - -/* **************************************************************************** - * NOTE: 3430 X-loader currently does not use this code. -* It could be removed its is kept for compatabily with u-boot. - * - * go_to_speed: -Moves to bypass, -Commits clock dividers, -puts dpll at speed - * -executed from SRAM. - * R0 = CM_CLKEN_PLL-bypass value - * R1 = CM_CLKSEL1_PLL-m, n, and divider values - * R2 = CM_CLKSEL_CORE-divider values - * R3 = CM_IDLEST_CKGEN - addr dpll lock wait - * - * Note: If core unlocks/relocks and SDRAM is running fast already it gets - * confused. A reset of the controller gets it back. Taking away its - * L3 when its not in self refresh seems bad for it. Normally, this code - * runs from flash before SDR is init so that should be ok. - ******************************************************************************/ -.global go_to_speed - go_to_speed: - stmfd sp!, {r4-r6} - - /* move into fast relock bypass */ - ldr r4, pll_ctl_add - str r0, [r4] -wait1: - ldr r5, [r3] /* get status */ - and r5, r5, #0x1 /* isolate core status */ - cmp r5, #0x1 /* still locked? */ - beq wait1 /* if lock, loop */ - - /* set new dpll dividers _after_ in bypass */ - ldr r5, pll_div_add1 - str r1, [r5] /* set m, n, m2 */ - ldr r5, pll_div_add2 - str r2, [r5] /* set l3/l4/.. dividers*/ - ldr r5, pll_div_add3 /* wkup */ - ldr r2, pll_div_val3 /* rsm val */ - str r2, [r5] - ldr r5, pll_div_add4 /* gfx */ - ldr r2, pll_div_val4 - str r2, [r5] - ldr r5, pll_div_add5 /* emu */ - ldr r2, pll_div_val5 - str r2, [r5] - - /* now prepare GPMC (flash) for new dpll speed */ - /* flash needs to be stable when we jump back to it */ - ldr r5, flash_cfg3_addr - ldr r2, flash_cfg3_val - str r2, [r5] - ldr r5, flash_cfg4_addr - ldr r2, flash_cfg4_val - str r2, [r5] - ldr r5, flash_cfg5_addr - ldr r2, flash_cfg5_val - str r2, [r5] - ldr r5, flash_cfg1_addr - ldr r2, [r5] - orr r2, r2, #0x3 /* up gpmc divider */ - str r2, [r5] - - /* lock DPLL3 and wait a bit */ - orr r0, r0, #0x7 /* set up for lock mode */ - str r0, [r4] /* lock */ - nop /* ARM slow at this point working at sys_clk */ - nop - nop - nop -wait2: - ldr r5, [r3] /* get status */ - and r5, r5, #0x1 /* isolate core status */ - cmp r5, #0x1 /* still locked? */ - bne wait2 /* if lock, loop */ - nop - nop - nop - nop - ldmfd sp!, {r4-r6} - mov pc, lr /* back to caller, locked */ - -_go_to_speed: .word go_to_speed - -/* these constants need to be close for PIC code */ -/* The Nor has to be in the Flash Base CS0 for this condition to happen */ -flash_cfg1_addr: - .word (GPMC_CONFIG_CS0 + GPMC_CONFIG1) -flash_cfg3_addr: - .word (GPMC_CONFIG_CS0 + GPMC_CONFIG3) -flash_cfg3_val: - .word STNOR_GPMC_CONFIG3 -flash_cfg4_addr: - .word (GPMC_CONFIG_CS0 + GPMC_CONFIG4) -flash_cfg4_val: - .word STNOR_GPMC_CONFIG4 -flash_cfg5_val: - .word STNOR_GPMC_CONFIG5 -flash_cfg5_addr: - .word (GPMC_CONFIG_CS0 + GPMC_CONFIG5) -pll_ctl_add: - .word CM_CLKEN_PLL -pll_div_add1: - .word CM_CLKSEL1_PLL -pll_div_add2: - .word CM_CLKSEL_CORE -pll_div_add3: - .word CM_CLKSEL_WKUP -pll_div_val3: - .word (WKUP_RSM << 1) -pll_div_add4: - .word CM_CLKSEL_GFX -pll_div_val4: - .word (GFX_DIV << 0) -pll_div_add5: - .word CM_CLKSEL1_EMU -pll_div_val5: - .word CLSEL1_EMU_VAL - -#endif - -.globl lowlevel_init -lowlevel_init: - ldr sp, SRAM_STACK - str ip, [sp] /* stash old link register */ - mov ip, lr /* save link reg across call */ - bl s_init /* go setup pll,mux,memory */ - ldr ip, [sp] /* restore save ip */ - mov lr, ip /* restore link reg */ - - /* back to arch calling code */ - mov pc, lr - - /* the literal pools origin */ - .ltorg - -REG_CONTROL_STATUS: - .word CONTROL_STATUS -SRAM_STACK: - .word LOW_LEVEL_SRAM_STACK - -/* DPLL(1-4) PARAM TABLES */ -/* Each of the tables has M, N, FREQSEL, M2 values defined for nominal - * OPP (1.2V). The fields are defined according to dpll_param struct(clock.c). - * The values are defined for all possible sysclk and for ES1 and ES2. - */ - -mpu_dpll_param: -/* 12MHz */ -/* ES1 */ -.word 0x0FE,0x07,0x05,0x01 -/* ES2 */ -.word 0x0FA,0x05,0x07,0x01 -/* 3410 */ -.word 0x085,0x05,0x07,0x01 - -/* 13MHz */ -/* ES1 */ -.word 0x17D,0x0C,0x03,0x01 -/* ES2 */ -.word 0x1F4,0x0C,0x03,0x01 -/* 3410 */ -.word 0x10A,0x0C,0x03,0x01 - -/* 19.2MHz */ -/* ES1 */ -.word 0x179,0x12,0x04,0x01 -/* ES2 */ -.word 0x271,0x17,0x03,0x01 -/* 3410 */ -.word 0x14C,0x17,0x03,0x01 - -/* 26MHz */ -/* ES1 */ -.word 0x17D,0x19,0x03,0x01 -/* ES2 */ -.word 0x0FA,0x0C,0x07,0x01 -/* 3410 */ -.word 0x085,0x0C,0x07,0x01 - -/* 38.4MHz */ -/* ES1 */ -.word 0x1FA,0x32,0x03,0x01 -/* ES2 */ -.word 0x271,0x2F,0x03,0x01 -/* 3410 */ -.word 0x14C,0x2F,0x03,0x01 - - -.globl get_mpu_dpll_param -get_mpu_dpll_param: - adr r0, mpu_dpll_param - mov pc, lr - -iva_dpll_param: -/* 12MHz */ -/* ES1 */ -.word 0x07D,0x05,0x07,0x01 -/* ES2 */ -.word 0x0B4,0x05,0x07,0x01 -/* 3410 */ -.word 0x085,0x05,0x07,0x01 - -/* 13MHz */ -/* ES1 */ -.word 0x0FA,0x0C,0x03,0x01 -/* ES2 */ -.word 0x168,0x0C,0x03,0x01 -/* 3410 */ -.word 0x10A,0x0C,0x03,0x01 - -/* 19.2MHz */ -/* ES1 */ -.word 0x082,0x09,0x07,0x01 -/* ES2 */ -.word 0x0E1,0x0B,0x06,0x01 -/* 3410 */ -.word 0x14C,0x17,0x03,0x01 - -/* 26MHz */ -/* ES1 */ -.word 0x07D,0x0C,0x07,0x01 -/* ES2 */ -.word 0x0B4,0x0C,0x07,0x01 -/* 3410 */ -.word 0x085,0x0C,0x07,0x01 - -/* 38.4MHz */ -/* ES1 */ -.word 0x13F,0x30,0x03,0x01 -/* ES2 */ -.word 0x0E1,0x17,0x06,0x01 -/* 3410 */ -.word 0x14C,0x2F,0x03,0x01 - - -.globl get_iva_dpll_param -get_iva_dpll_param: - adr r0, iva_dpll_param - mov pc, lr - -/* Core DPLL targets for L3 at 166 & L133 */ -core_dpll_param: -/* 12MHz */ -/* ES1 */ -.word M_12_ES1,M_12_ES1,FSL_12_ES1,M2_12_ES1 -/* ES2 */ -.word M_12,N_12,FSEL_12,M2_12 -/* 3410 */ -.word M_12,N_12,FSEL_12,M2_12 - -/* 13MHz */ -/* ES1 */ -.word M_13_ES1,N_13_ES1,FSL_13_ES1,M2_13_ES1 -/* ES2 */ -.word M_13,N_13,FSEL_13,M2_13 -/* 3410 */ -.word M_13,N_13,FSEL_13,M2_13 - -/* 19.2MHz */ -/* ES1 */ -.word M_19p2_ES1,N_19p2_ES1,FSL_19p2_ES1,M2_19p2_ES1 -/* ES2 */ -.word M_19p2,N_19p2,FSEL_19p2,M2_19p2 -/* 3410 */ -.word M_19p2,N_19p2,FSEL_19p2,M2_19p2 - -/* 26MHz */ -/* ES1 */ -.word M_26_ES1,N_26_ES1,FSL_26_ES1,M2_26_ES1 -/* ES2 */ -.word M_26,N_26,FSEL_26,M2_26 -/* 3410 */ -.word M_26,N_26,FSEL_26,M2_26 - -/* 38.4MHz */ -/* ES1 */ -.word M_38p4_ES1,N_38p4_ES1,FSL_38p4_ES1,M2_38p4_ES1 -/* ES2 */ -.word M_38p4,N_38p4,FSEL_38p4,M2_38p4 -/* 3410 */ -.word M_38p4,N_38p4,FSEL_38p4,M2_38p4 - -.globl get_core_dpll_param -get_core_dpll_param: - adr r0, core_dpll_param - mov pc, lr - -/* PER DPLL values are same for both ES1 and ES2 */ -per_dpll_param: -/* 12MHz */ -.word 0xD8,0x05,0x07,0x09 - -/* 13MHz */ -.word 0x1B0,0x0C,0x03,0x09 - -/* 19.2MHz */ -.word 0xE1,0x09,0x07,0x09 - -/* 26MHz */ -.word 0xD8,0x0C,0x07,0x09 - -/* 38.4MHz */ -.word 0xE1,0x13,0x07,0x09 - -.globl get_per_dpll_param -get_per_dpll_param: - adr r0, per_dpll_param - mov pc, lr - diff --git a/x-loader/board/omap3evm/Makefile b/x-loader/board/omap3evm/Makefile deleted file mode 100644 index d83f45e..0000000 --- a/x-loader/board/omap3evm/Makefile +++ /dev/null @@ -1,51 +0,0 @@ -# -# (C) Copyright 2000, 2001, 2002 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).a - -COBJS := omap3evm.o -SOBJS := platform.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) $(SOBJS) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak $(obj).depend - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/x-loader/board/omap3evm/config.mk b/x-loader/board/omap3evm/config.mk deleted file mode 100644 index a45ec22..0000000 --- a/x-loader/board/omap3evm/config.mk +++ /dev/null @@ -1,19 +0,0 @@ -# (C) Copyright 2006 -# Texas Instruments, <www.ti.com> -# -# OMAP3EVM board uses OMAP3430 (ARM-CortexA8) cpu -# see http://www.ti.com/ for more information on Texas Instruments# -# -# OMAP3EVM has 1 bank of 128MB mPOP-SDRAM on CS0 -# Physical Address: -# 8000'0000 (bank0) - -# For use if you want X-Loader to relocate from SRAM to DDR -#TEXT_BASE = 0x80e80000 - -# For XIP in 64K of SRAM or debug (GP device has it all availabe) -# SRAM 40200000-4020FFFF base -# initial stack at 0x4020fffc used in s_init (below xloader). -# The run time stack is (above xloader, 2k below) -# If any globals exist there needs to be room for them also -TEXT_BASE = 0x40200800 diff --git a/x-loader/board/omap3evm/omap3evm.c b/x-loader/board/omap3evm/omap3evm.c deleted file mode 100644 index 16c1f70..0000000 --- a/x-loader/board/omap3evm/omap3evm.c +++ /dev/null @@ -1,814 +0,0 @@ -/* - * (C) Copyright 2006 - * Texas Instruments, <www.ti.com> - * Jian Zhang <jzhang@ti.com> - * Richard Woodruff <r-woodruff2@ti.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#include <common.h> -#include <command.h> -#include <part.h> -#include <fat.h> -#include <asm/arch/cpu.h> -#include <asm/arch/bits.h> -#include <asm/arch/mux.h> -#include <asm/arch/sys_proto.h> -#include <asm/arch/sys_info.h> -#include <asm/arch/clocks.h> -#include <asm/arch/mem.h> - -/* Used to index into DPLL parameter tables */ -struct dpll_param { - unsigned int m; - unsigned int n; - unsigned int fsel; - unsigned int m2; -}; - -typedef struct dpll_param dpll_param; - -/* Following functions are exported from lowlevel_init.S */ -extern dpll_param * get_mpu_dpll_param(); -extern dpll_param * get_iva_dpll_param(); -extern dpll_param * get_core_dpll_param(); -extern dpll_param * get_per_dpll_param(); - -#define __raw_readl(a) (*(volatile unsigned int *)(a)) -#define __raw_writel(v,a) (*(volatile unsigned int *)(a) = (v)) -#define __raw_readw(a) (*(volatile unsigned short *)(a)) -#define __raw_writew(v,a) (*(volatile unsigned short *)(a) = (v)) - -/******************************************************* - * Routine: delay - * Description: spinning delay to use before udelay works - ******************************************************/ -static inline void delay(unsigned long loops) -{ - __asm__ volatile ("1:\n" "subs %0, %1, #1\n" - "bne 1b":"=r" (loops):"0"(loops)); -} - -void udelay (unsigned long usecs) { - delay(usecs); -} - -/***************************************** - * Routine: board_init - * Description: Early hardware init. - *****************************************/ -int board_init (void) -{ - return 0; -} - -/************************************************************* - * get_device_type(): tell if GP/HS/EMU/TST - *************************************************************/ -u32 get_device_type(void) -{ - int mode; - mode = __raw_readl(CONTROL_STATUS) & (DEVICE_MASK); - return(mode >>= 8); -} - -/************************************************ - * get_sysboot_value(void) - return SYS_BOOT[4:0] - ************************************************/ -u32 get_sysboot_value(void) -{ - int mode; - mode = __raw_readl(CONTROL_STATUS) & (SYSBOOT_MASK); - return mode; -} -/************************************************************* - * Routine: get_mem_type(void) - returns the kind of memory connected - * to GPMC that we are trying to boot form. Uses SYS BOOT settings. - *************************************************************/ -u32 get_mem_type(void) -{ - u32 mem_type = get_sysboot_value(); - switch (mem_type){ - case 0: - case 2: - case 4: - case 16: - case 22: return GPMC_ONENAND; - - case 1: - case 12: - case 15: - case 21: - case 27: return GPMC_NAND; - - case 3: - case 6: return MMC_ONENAND; - - case 8: - case 11: - case 14: - case 20: - case 26: return GPMC_MDOC; - - case 17: - case 18: - case 24: return MMC_NAND; - - case 7: - case 10: - case 13: - case 19: - case 25: - default: return GPMC_NOR; - } -} - -/****************************************** - * get_cpu_rev(void) - extract version info - ******************************************/ -u32 get_cpu_rev(void) -{ - u32 cpuid=0; - /* On ES1.0 the IDCODE register is not exposed on L4 - * so using CPU ID to differentiate - * between ES2.0 and ES1.0. - */ - __asm__ __volatile__("mrc p15, 0, %0, c0, c0, 0":"=r" (cpuid)); - if((cpuid & 0xf) == 0x0) - return CPU_3430_ES1; - else - return CPU_3430_ES2; - -} - -/****************************************** - * cpu_is_3410(void) - returns true for 3410 - ******************************************/ -u32 cpu_is_3410(void) -{ - int status; - if(get_cpu_rev() < CPU_3430_ES2) { - return 0; - } else { - /* read scalability status and return 1 for 3410*/ - status = __raw_readl(CONTROL_SCALABLE_OMAP_STATUS); - /* Check whether MPU frequency is set to 266 MHz which - * is nominal for 3410. If yes return true else false - */ - if (((status >> 8) & 0x3) == 0x2) - return 1; - else - return 0; - } -} - -/***************************************************************** - * sr32 - clear & set a value in a bit range for a 32 bit address - *****************************************************************/ -void sr32(u32 addr, u32 start_bit, u32 num_bits, u32 value) -{ - u32 tmp, msk = 0; - msk = 1 << num_bits; - --msk; - tmp = __raw_readl(addr) & ~(msk << start_bit); - tmp |= value << start_bit; - __raw_writel(tmp, addr); -} - -/********************************************************************* - * wait_on_value() - common routine to allow waiting for changes in - * volatile regs. - *********************************************************************/ -u32 wait_on_value(u32 read_bit_mask, u32 match_value, u32 read_addr, u32 bound) -{ - u32 i = 0, val; - do { - ++i; - val = __raw_readl(read_addr) & read_bit_mask; - if (val == match_value) - return (1); - if (i == bound) - return (0); - } while (1); -} - -#ifdef CFG_3430SDRAM_DDR -/********************************************************************* - * config_3430sdram_ddr() - Init DDR on 3430SDP dev board. - *********************************************************************/ -void config_3430sdram_ddr(void) -{ - /* reset sdrc controller */ - __raw_writel(SOFTRESET, SDRC_SYSCONFIG); - wait_on_value(BIT0, BIT0, SDRC_STATUS, 12000000); - __raw_writel(0, SDRC_SYSCONFIG); - - /* setup sdrc to ball mux */ - __raw_writel(SDP_SDRC_SHARING, SDRC_SHARING); - - /* set mdcfg */ - __raw_writel(SDP_SDRC_MDCFG_0_DDR, SDRC_MCFG_0); - - /* set timing */ - if ((get_mem_type() == GPMC_ONENAND) || (get_mem_type() == MMC_ONENAND)){ - __raw_writel(INFINEON_SDRC_ACTIM_CTRLA_0, SDRC_ACTIM_CTRLA_0); - __raw_writel(INFINEON_SDRC_ACTIM_CTRLB_0, SDRC_ACTIM_CTRLB_0); - } - if ((get_mem_type() == GPMC_NAND) ||(get_mem_type() == MMC_NAND)){ - __raw_writel(MICRON_SDRC_ACTIM_CTRLA_0, SDRC_ACTIM_CTRLA_0); - __raw_writel(MICRON_SDRC_ACTIM_CTRLB_0, SDRC_ACTIM_CTRLB_0); - } - - __raw_writel(SDP_3430_SDRC_RFR_CTRL_165MHz, SDRC_RFR_CTRL_0); - __raw_writel(SDP_SDRC_POWER_POP, SDRC_POWER); - - /* init sequence for mDDR/mSDR using manual commands (DDR is different) */ - __raw_writel(CMD_NOP, SDRC_MANUAL_0); - delay(5000); - __raw_writel(CMD_PRECHARGE, SDRC_MANUAL_0); - __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0); - __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0); - - /* set mr0 */ - __raw_writel(SDP_SDRC_MR_0_DDR, SDRC_MR_0); - - /* set up dll */ - __raw_writel(SDP_SDRC_DLLAB_CTRL, SDRC_DLLA_CTRL); - delay(0x2000); /* give time to lock */ - -} -#endif // CFG_3430SDRAM_DDR - -/************************************************************* - * get_sys_clk_speed - determine reference oscillator speed - * based on known 32kHz clock and gptimer. - *************************************************************/ -u32 get_osc_clk_speed(void) -{ - u32 start, cstart, cend, cdiff, val; - - val = __raw_readl(PRM_CLKSRC_CTRL); - /* If SYS_CLK is being divided by 2, remove for now */ - val = (val & (~BIT7)) | BIT6; - __raw_writel(val, PRM_CLKSRC_CTRL); - - /* enable timer2 */ - val = __raw_readl(CM_CLKSEL_WKUP) | BIT0; - __raw_writel(val, CM_CLKSEL_WKUP); /* select sys_clk for GPT1 */ - - /* Enable I and F Clocks for GPT1 */ - val = __raw_readl(CM_ICLKEN_WKUP) | BIT0 | BIT2; - __raw_writel(val, CM_ICLKEN_WKUP); - val = __raw_readl(CM_FCLKEN_WKUP) | BIT0; - __raw_writel(val, CM_FCLKEN_WKUP); - - __raw_writel(0, OMAP34XX_GPT1 + TLDR); /* start counting at 0 */ - __raw_writel(GPT_EN, OMAP34XX_GPT1 + TCLR); /* enable clock */ - /* enable 32kHz source *//* enabled out of reset */ - /* determine sys_clk via gauging */ - - start = 20 + __raw_readl(S32K_CR); /* start time in 20 cycles */ - while (__raw_readl(S32K_CR) < start); /* dead loop till start time */ - cstart = __raw_readl(OMAP34XX_GPT1 + TCRR); /* get start sys_clk count */ - while (__raw_readl(S32K_CR) < (start + 20)); /* wait for 40 cycles */ - cend = __raw_readl(OMAP34XX_GPT1 + TCRR); /* get end sys_clk count */ - cdiff = cend - cstart; /* get elapsed ticks */ - - /* based on number of ticks assign speed */ - if (cdiff > 19000) - return (S38_4M); - else if (cdiff > 15200) - return (S26M); - else if (cdiff > 13000) - return (S24M); - else if (cdiff > 9000) - return (S19_2M); - else if (cdiff > 7600) - return (S13M); - else - return (S12M); -} - -/****************************************************************************** - * get_sys_clkin_sel() - returns the sys_clkin_sel field value based on - * -- input oscillator clock frequency. - * - *****************************************************************************/ -void get_sys_clkin_sel(u32 osc_clk, u32 *sys_clkin_sel) -{ - if(osc_clk == S38_4M) - *sys_clkin_sel= 4; - else if(osc_clk == S26M) - *sys_clkin_sel = 3; - else if(osc_clk == S19_2M) - *sys_clkin_sel = 2; - else if(osc_clk == S13M) - *sys_clkin_sel = 1; - else if(osc_clk == S12M) - *sys_clkin_sel = 0; -} - -/****************************************************************************** - * prcm_init() - inits clocks for PRCM as defined in clocks.h - * -- called from SRAM, or Flash (using temp SRAM stack). - *****************************************************************************/ -void prcm_init(void) -{ - u32 osc_clk=0, sys_clkin_sel; - dpll_param *dpll_param_p; - u32 clk_index, sil_index; - - /* Gauge the input clock speed and find out the sys_clkin_sel - * value corresponding to the input clock. - */ - osc_clk = get_osc_clk_speed(); - get_sys_clkin_sel(osc_clk, &sys_clkin_sel); - - sr32(PRM_CLKSEL, 0, 3, sys_clkin_sel); /* set input crystal speed */ - - /* If the input clock is greater than 19.2M always divide/2 */ - if(sys_clkin_sel > 2) { - sr32(PRM_CLKSRC_CTRL, 6, 2, 2);/* input clock divider */ - clk_index = sys_clkin_sel/2; - } else { - sr32(PRM_CLKSRC_CTRL, 6, 2, 1);/* input clock divider */ - clk_index = sys_clkin_sel; - } - - /* The DPLL tables are defined according to sysclk value and - * silicon revision. The clk_index value will be used to get - * the values for that input sysclk from the DPLL param table - * and sil_index will get the values for that SysClk for the - * appropriate silicon rev. - */ - sil_index = get_cpu_rev() - 1; - - /* Unlock MPU DPLL (slows things down, and needed later) */ - sr32(CM_CLKEN_PLL_MPU, 0, 3, PLL_LOW_POWER_BYPASS); - wait_on_value(BIT0, 0, CM_IDLEST_PLL_MPU, LDELAY); - - /* Getting the base address of Core DPLL param table*/ - dpll_param_p = (dpll_param *)get_core_dpll_param(); - /* Moving it to the right sysclk and ES rev base */ - dpll_param_p = dpll_param_p + 2*clk_index + sil_index; - /* CORE DPLL */ - /* sr32(CM_CLKSEL2_EMU) set override to work when asleep */ - sr32(CM_CLKEN_PLL, 0, 3, PLL_FAST_RELOCK_BYPASS); - wait_on_value(BIT0, 0, CM_IDLEST_CKGEN, LDELAY); - sr32(CM_CLKSEL1_EMU, 16, 5, CORE_M3X2); /* m3x2 */ - sr32(CM_CLKSEL1_PLL, 27, 2, dpll_param_p->m2); /* Set M2 */ - sr32(CM_CLKSEL1_PLL, 16, 11, dpll_param_p->m); /* Set M */ - sr32(CM_CLKSEL1_PLL, 8, 7, dpll_param_p->n); /* Set N */ - sr32(CM_CLKSEL1_PLL, 6, 1, 0); /* 96M Src */ - sr32(CM_CLKSEL_CORE, 8, 4, CORE_SSI_DIV); /* ssi */ - sr32(CM_CLKSEL_CORE, 4, 2, CORE_FUSB_DIV); /* fsusb */ - sr32(CM_CLKSEL_CORE, 2, 2, CORE_L4_DIV); /* l4 */ - sr32(CM_CLKSEL_CORE, 0, 2, CORE_L3_DIV); /* l3 */ - sr32(CM_CLKSEL_GFX, 0, 3, GFX_DIV); /* gfx */ - sr32(CM_CLKSEL_WKUP, 1, 2, WKUP_RSM); /* reset mgr */ - sr32(CM_CLKEN_PLL, 4, 4, dpll_param_p->fsel); /* FREQSEL */ - sr32(CM_CLKEN_PLL, 0, 3, PLL_LOCK); /* lock mode */ - wait_on_value(BIT0, 1, CM_IDLEST_CKGEN, LDELAY); - - /* Getting the base address to PER DPLL param table*/ - dpll_param_p = (dpll_param *)get_per_dpll_param(); - /* Moving it to the right sysclk base */ - dpll_param_p = dpll_param_p + clk_index; - /* PER DPLL */ - sr32(CM_CLKEN_PLL, 16, 3, PLL_STOP); - wait_on_value(BIT1, 0, CM_IDLEST_CKGEN, LDELAY); - sr32(CM_CLKSEL1_EMU, 24, 5, PER_M6X2); /* set M6 */ - sr32(CM_CLKSEL_CAM, 0, 5, PER_M5X2); /* set M5 */ - sr32(CM_CLKSEL_DSS, 0, 5, PER_M4X2); /* set M4 */ - sr32(CM_CLKSEL_DSS, 8, 5, PER_M3X2); /* set M3 */ - sr32(CM_CLKSEL3_PLL, 0, 5, dpll_param_p->m2); /* set M2 */ - sr32(CM_CLKSEL2_PLL, 8, 11, dpll_param_p->m); /* set m */ - sr32(CM_CLKSEL2_PLL, 0, 7, dpll_param_p->n); /* set n */ - sr32(CM_CLKEN_PLL, 20, 4, dpll_param_p->fsel);/* FREQSEL */ - sr32(CM_CLKEN_PLL, 16, 3, PLL_LOCK); /* lock mode */ - wait_on_value(BIT1, 2, CM_IDLEST_CKGEN, LDELAY); - - /* Getting the base address to MPU DPLL param table*/ - dpll_param_p = (dpll_param *)get_mpu_dpll_param(); - /* Moving it to the right sysclk and ES rev base */ - dpll_param_p = dpll_param_p + 2*clk_index + sil_index; - /* MPU DPLL (unlocked already) */ - sr32(CM_CLKSEL2_PLL_MPU, 0, 5, dpll_param_p->m2); /* Set M2 */ - sr32(CM_CLKSEL1_PLL_MPU, 8, 11, dpll_param_p->m); /* Set M */ - sr32(CM_CLKSEL1_PLL_MPU, 0, 7, dpll_param_p->n); /* Set N */ - sr32(CM_CLKEN_PLL_MPU, 4, 4, dpll_param_p->fsel); /* FREQSEL */ - sr32(CM_CLKEN_PLL_MPU, 0, 3, PLL_LOCK); /* lock mode */ - wait_on_value(BIT0, 1, CM_IDLEST_PLL_MPU, LDELAY); - - /* Getting the base address to IVA DPLL param table*/ - dpll_param_p = (dpll_param *)get_iva_dpll_param(); - /* Moving it to the right sysclk and ES rev base */ - dpll_param_p = dpll_param_p + 2*clk_index + sil_index; - /* IVA DPLL (set to 12*20=240MHz) */ - sr32(CM_CLKEN_PLL_IVA2, 0, 3, PLL_STOP); - wait_on_value(BIT0, 0, CM_IDLEST_PLL_IVA2, LDELAY); - sr32(CM_CLKSEL2_PLL_IVA2, 0, 5, dpll_param_p->m2); /* set M2 */ - sr32(CM_CLKSEL1_PLL_IVA2, 8, 11, dpll_param_p->m); /* set M */ - sr32(CM_CLKSEL1_PLL_IVA2, 0, 7, dpll_param_p->n); /* set N */ - sr32(CM_CLKEN_PLL_IVA2, 4, 4, dpll_param_p->fsel); /* FREQSEL */ - sr32(CM_CLKEN_PLL_IVA2, 0, 3, PLL_LOCK); /* lock mode */ - wait_on_value(BIT0, 1, CM_IDLEST_PLL_IVA2, LDELAY); - - /* Set up GPTimers to sys_clk source only */ - sr32(CM_CLKSEL_PER, 0, 8, 0xff); - sr32(CM_CLKSEL_WKUP, 0, 1, 1); - - delay(5000); -} - -/***************************************** - * Routine: secure_unlock - * Description: Setup security registers for access - * (GP Device only) - *****************************************/ -void secure_unlock(void) -{ - /* Permission values for registers -Full fledged permissions to all */ - #define UNLOCK_1 0xFFFFFFFF - #define UNLOCK_2 0x00000000 - #define UNLOCK_3 0x0000FFFF - /* Protection Module Register Target APE (PM_RT)*/ - __raw_writel(UNLOCK_1, RT_REQ_INFO_PERMISSION_1); - __raw_writel(UNLOCK_1, RT_READ_PERMISSION_0); - __raw_writel(UNLOCK_1, RT_WRITE_PERMISSION_0); - __raw_writel(UNLOCK_2, RT_ADDR_MATCH_1); - - __raw_writel(UNLOCK_3, GPMC_REQ_INFO_PERMISSION_0); - __raw_writel(UNLOCK_3, GPMC_READ_PERMISSION_0); - __raw_writel(UNLOCK_3, GPMC_WRITE_PERMISSION_0); - - __raw_writel(UNLOCK_3, OCM_REQ_INFO_PERMISSION_0); - __raw_writel(UNLOCK_3, OCM_READ_PERMISSION_0); - __raw_writel(UNLOCK_3, OCM_WRITE_PERMISSION_0); - __raw_writel(UNLOCK_2, OCM_ADDR_MATCH_2); - - /* IVA Changes */ - __raw_writel(UNLOCK_3, IVA2_REQ_INFO_PERMISSION_0); - __raw_writel(UNLOCK_3, IVA2_READ_PERMISSION_0); - __raw_writel(UNLOCK_3, IVA2_WRITE_PERMISSION_0); - - __raw_writel(UNLOCK_1, SMS_RG_ATT0); /* SDRC region 0 public */ -} - -/********************************************************** - * Routine: try_unlock_sram() - * Description: If chip is GP type, unlock the SRAM for - * general use. - ***********************************************************/ -void try_unlock_memory(void) -{ - int mode; - - /* if GP device unlock device SRAM for general use */ - /* secure code breaks for Secure/Emulation device - HS/E/T*/ - mode = get_device_type(); - if (mode == GP_DEVICE) { - secure_unlock(); - } - return; -} - -/********************************************************** - * Routine: s_init - * Description: Does early system init of muxing and clocks. - * - Called at time when only stack is available. - **********************************************************/ - -void s_init(void) -{ - watchdog_init(); -#ifdef CONFIG_3430_AS_3410 - /* setup the scalability control register for - * 3430 to work in 3410 mode - */ - __raw_writel(0x5ABF,CONTROL_SCALABLE_OMAP_OCP); -#endif - try_unlock_memory(); - set_muxconf_regs(); - delay(100); - prcm_init(); - per_clocks_enable(); - config_3430sdram_ddr(); -} - -/******************************************************* - * Routine: misc_init_r - * Description: Init ethernet (done here so udelay works) - ********************************************************/ -int misc_init_r (void) -{ - return(0); -} - -/****************************************************** - * Routine: wait_for_command_complete - * Description: Wait for posting to finish on watchdog - ******************************************************/ -void wait_for_command_complete(unsigned int wd_base) -{ - int pending = 1; - do { - pending = __raw_readl(wd_base + WWPS); - } while (pending); -} - -/**************************************** - * Routine: watchdog_init - * Description: Shut down watch dogs - *****************************************/ -void watchdog_init(void) -{ - /* There are 3 watch dogs WD1=Secure, WD2=MPU, WD3=IVA. WD1 is - * either taken care of by ROM (HS/EMU) or not accessible (GP). - * We need to take care of WD2-MPU or take a PRCM reset. WD3 - * should not be running and does not generate a PRCM reset. - */ - sr32(CM_FCLKEN_WKUP, 5, 1, 1); - sr32(CM_ICLKEN_WKUP, 5, 1, 1); - wait_on_value(BIT5, 0x20, CM_IDLEST_WKUP, 5); /* some issue here */ - - __raw_writel(WD_UNLOCK1, WD2_BASE + WSPR); - wait_for_command_complete(WD2_BASE); - __raw_writel(WD_UNLOCK2, WD2_BASE + WSPR); -} - -/********************************************** - * Routine: dram_init - * Description: sets uboots idea of sdram size - **********************************************/ -int dram_init (void) -{ - return 0; -} - -/***************************************************************** - * Routine: peripheral_enable - * Description: Enable the clks & power for perifs (GPT2, UART1,...) - ******************************************************************/ -void per_clocks_enable(void) -{ - /* Enable GP2 timer. */ - sr32(CM_CLKSEL_PER, 0, 1, 0x1); /* GPT2 = sys clk */ - sr32(CM_ICLKEN_PER, 3, 1, 0x1); /* ICKen GPT2 */ - sr32(CM_FCLKEN_PER, 3, 1, 0x1); /* FCKen GPT2 */ - -#ifdef CFG_NS16550 - /* Enable UART1 clocks */ - sr32(CM_FCLKEN1_CORE, 13, 1, 0x1); - sr32(CM_ICLKEN1_CORE, 13, 1, 0x1); -#endif - delay(1000); -} - -/* Set MUX for UART, GPMC, SDRC, GPIO */ - -#define MUX_VAL(OFFSET,VALUE)\ - __raw_writew((VALUE), OMAP34XX_CTRL_BASE + (OFFSET)); - -#define CP(x) (CONTROL_PADCONF_##x) -/* - * IEN - Input Enable - * IDIS - Input Disable - * PTD - Pull type Down - * PTU - Pull type Up - * DIS - Pull type selection is inactive - * EN - Pull type selection is active - * M0 - Mode 0 - * The commented string gives the final mux configuration for that pin - */ -#define MUX_DEFAULT()\ - MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /*SDRC_D0*/\ - MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /*SDRC_D1*/\ - MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /*SDRC_D2*/\ - MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /*SDRC_D3*/\ - MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /*SDRC_D4*/\ - MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /*SDRC_D5*/\ - MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /*SDRC_D6*/\ - MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /*SDRC_D7*/\ - MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /*SDRC_D8*/\ - MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /*SDRC_D9*/\ - MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /*SDRC_D10*/\ - MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /*SDRC_D11*/\ - MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /*SDRC_D12*/\ - MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /*SDRC_D13*/\ - MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /*SDRC_D14*/\ - MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /*SDRC_D15*/\ - MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /*SDRC_D16*/\ - MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /*SDRC_D17*/\ - MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /*SDRC_D18*/\ - MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /*SDRC_D19*/\ - MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /*SDRC_D20*/\ - MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /*SDRC_D21*/\ - MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /*SDRC_D22*/\ - MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /*SDRC_D23*/\ - MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /*SDRC_D24*/\ - MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /*SDRC_D25*/\ - MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /*SDRC_D26*/\ - MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /*SDRC_D27*/\ - MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /*SDRC_D28*/\ - MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /*SDRC_D29*/\ - MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /*SDRC_D30*/\ - MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /*SDRC_D31*/\ - MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /*SDRC_CLK*/\ - MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /*SDRC_DQS0*/\ - MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /*SDRC_DQS1*/\ - MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /*SDRC_DQS2*/\ - MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /*SDRC_DQS3*/\ - MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0)) /*GPMC_A1*/\ - MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0)) /*GPMC_A2*/\ - MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0)) /*GPMC_A3*/\ - MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0)) /*GPMC_A4*/\ - MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0)) /*GPMC_A5*/\ - MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0)) /*GPMC_A6*/\ - MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0)) /*GPMC_A7*/\ - MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0)) /*GPMC_A8*/\ - MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M0)) /*GPMC_A9*/\ - MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0)) /*GPMC_A10*/\ - MUX_VAL(CP(GPMC_D0), (IEN | PTD | DIS | M0)) /*GPMC_D0*/\ - MUX_VAL(CP(GPMC_D1), (IEN | PTD | DIS | M0)) /*GPMC_D1*/\ - MUX_VAL(CP(GPMC_D2), (IEN | PTD | DIS | M0)) /*GPMC_D2*/\ - MUX_VAL(CP(GPMC_D3), (IEN | PTD | DIS | M0)) /*GPMC_D3*/\ - MUX_VAL(CP(GPMC_D4), (IEN | PTD | DIS | M0)) /*GPMC_D4*/\ - MUX_VAL(CP(GPMC_D5), (IEN | PTD | DIS | M0)) /*GPMC_D5*/\ - MUX_VAL(CP(GPMC_D6), (IEN | PTD | DIS | M0)) /*GPMC_D6*/\ - MUX_VAL(CP(GPMC_D7), (IEN | PTD | DIS | M0)) /*GPMC_D7*/\ - MUX_VAL(CP(GPMC_D8), (IEN | PTD | DIS | M0)) /*GPMC_D8*/\ - MUX_VAL(CP(GPMC_D9), (IEN | PTD | DIS | M0)) /*GPMC_D9*/\ - MUX_VAL(CP(GPMC_D10), (IEN | PTD | DIS | M0)) /*GPMC_D10*/\ - MUX_VAL(CP(GPMC_D11), (IEN | PTD | DIS | M0)) /*GPMC_D11*/\ - MUX_VAL(CP(GPMC_D12), (IEN | PTD | DIS | M0)) /*GPMC_D12*/\ - MUX_VAL(CP(GPMC_D13), (IEN | PTD | DIS | M0)) /*GPMC_D13*/\ - MUX_VAL(CP(GPMC_D14), (IEN | PTD | DIS | M0)) /*GPMC_D14*/\ - MUX_VAL(CP(GPMC_D15), (IEN | PTD | DIS | M0)) /*GPMC_D15*/\ - MUX_VAL(CP(GPMC_nCS0), (IDIS | PTU | EN | M0)) /*GPMC_nCS0*/\ - MUX_VAL(CP(GPMC_nCS1), (IDIS | PTU | EN | M0)) /*GPMC_nCS1*/\ - MUX_VAL(CP(GPMC_nCS2), (IDIS | PTU | EN | M0)) /*GPMC_nCS2*/\ - MUX_VAL(CP(GPMC_nCS3), (IDIS | PTU | EN | M0)) /*GPMC_nCS3*/\ - MUX_VAL(CP(GPMC_nCS4), (IDIS | PTU | EN | M0)) /*GPMC_nCS4*/\ - MUX_VAL(CP(GPMC_nCS5), (IDIS | PTU | EN | M0)) /*GPMC_nCS5*/\ - MUX_VAL(CP(GPMC_nCS6), (IDIS | PTU | EN | M0)) /*GPMC_nCS6*/\ - MUX_VAL(CP(GPMC_nCS7), (IDIS | PTU | EN | M0)) /*GPMC_nCS7*/\ - MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M0)) /*GPMC_CLK*/\ - MUX_VAL(CP(GPMC_nADV_ALE), (IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\ - MUX_VAL(CP(GPMC_nOE), (IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\ - MUX_VAL(CP(GPMC_nWE), (IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\ - MUX_VAL(CP(GPMC_nBE0_CLE), (IDIS | PTD | DIS | M0)) /*GPMC_nBE0_CLE*/\ - MUX_VAL(CP(GPMC_nBE1), (IDIS | PTD | DIS | M4)) /*GPIO_61*/\ - MUX_VAL(CP(GPMC_nWP), (IEN | PTD | DIS | M0)) /*GPMC_nWP*/\ - MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) /*GPMC_WAIT0*/\ - MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)) /*GPMC_WAIT1*/\ - MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4)) /*GPIO_64*/\ - MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M4)) /*GPIO_65*/\ - MUX_VAL(CP(DSS_DATA18), (IEN | PTD | DIS | M4)) /*GPIO_88*/\ - MUX_VAL(CP(DSS_DATA19), (IEN | PTD | DIS | M4)) /*GPIO_89*/\ - MUX_VAL(CP(DSS_DATA20), (IEN | PTD | DIS | M4)) /*GPIO_90*/\ - MUX_VAL(CP(DSS_DATA21), (IEN | PTD | DIS | M4)) /*GPIO_91*/\ - MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4)) /*GPIO_167*/\ - MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /*UART1_TX*/\ - MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0)) /*UART1_RTS*/\ - MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M0)) /*UART1_CTS*/\ - MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /*UART1_RX*/\ - MUX_VAL(CP(McBSP1_DX), (IEN | PTD | DIS | M4)) /*GPIO_158*/\ - MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) /*SYS_32K*/\ - MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /*GPIO_2 */\ - MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) /*GPIO_3 */\ - MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /*GPIO_4 */\ - MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) /*GPIO_5 */\ - MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /*GPIO_6 */\ - MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /*GPIO_7 */\ - MUX_VAL(CP(SYS_BOOT6), (IEN | PTD | DIS | M4)) /*GPIO_8 */\ - MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M4)) /*GPIO_186*/\ - MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0)) /*JTAG_nTRST*/\ - MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)) /*JTAG_TCK*/\ - MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)) /*JTAG_TMS*/\ - MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)) /*JTAG_TDI*/\ - MUX_VAL(CP(JTAG_EMU0), (IEN | PTD | DIS | M0)) /*JTAG_EMU0*/\ - MUX_VAL(CP(JTAG_EMU1), (IEN | PTD | DIS | M0)) /*JTAG_EMU1*/\ - MUX_VAL(CP(ETK_CLK), (IEN | PTD | DIS | M4)) /*GPIO_12*/\ - MUX_VAL(CP(ETK_CTL), (IEN | PTD | DIS | M4)) /*GPIO_13*/\ - MUX_VAL(CP(ETK_D0 ), (IEN | PTD | DIS | M4)) /*GPIO_14*/\ - MUX_VAL(CP(ETK_D1 ), (IEN | PTD | DIS | M4)) /*GPIO_15*/\ - MUX_VAL(CP(ETK_D2 ), (IEN | PTD | DIS | M4)) /*GPIO_16*/\ - MUX_VAL(CP(ETK_D10), (IEN | PTD | DIS | M4)) /*GPIO_24*/\ - MUX_VAL(CP(ETK_D11), (IEN | PTD | DIS | M4)) /*GPIO_25*/\ - MUX_VAL(CP(ETK_D12), (IEN | PTD | DIS | M4)) /*GPIO_26*/\ - MUX_VAL(CP(ETK_D13), (IEN | PTD | DIS | M4)) /*GPIO_27*/\ - MUX_VAL(CP(ETK_D14), (IEN | PTD | DIS | M4)) /*GPIO_28*/\ - MUX_VAL(CP(ETK_D15), (IEN | PTD | DIS | M4)) /*GPIO_29*/ - -/********************************************************** - * Routine: set_muxconf_regs - * Description: Setting up the configuration Mux registers - * specific to the hardware. Many pins need - * to be moved from protect to primary mode. - *********************************************************/ -void set_muxconf_regs(void) -{ - MUX_DEFAULT(); -} - -/********************************************************** - * Routine: nand+_init - * Description: Set up nand for nand and jffs2 commands - *********************************************************/ - -int nand_init(void) -{ - /* global settings */ - __raw_writel(0x10, GPMC_SYSCONFIG); /* smart idle */ - __raw_writel(0x0, GPMC_IRQENABLE); /* isr's sources masked */ - __raw_writel(0, GPMC_TIMEOUT_CONTROL);/* timeout disable */ - - /* Set the GPMC Vals . For NAND boot on 3430SDP, NAND is mapped at CS0 - * , NOR at CS1 and MPDB at CS3. And oneNAND boot, we map oneNAND at CS0. - * We configure only GPMC CS0 with required values. Configiring other devices - * at other CS in done in u-boot anyway. So we don't have to bother doing it here. - */ - __raw_writel(0 , GPMC_CONFIG7 + GPMC_CONFIG_CS0); - delay(1000); - - if ((get_mem_type() == GPMC_NAND) || (get_mem_type() == MMC_NAND)){ - __raw_writel( M_NAND_GPMC_CONFIG1, GPMC_CONFIG1 + GPMC_CONFIG_CS0); - __raw_writel( M_NAND_GPMC_CONFIG2, GPMC_CONFIG2 + GPMC_CONFIG_CS0); - __raw_writel( M_NAND_GPMC_CONFIG3, GPMC_CONFIG3 + GPMC_CONFIG_CS0); - __raw_writel( M_NAND_GPMC_CONFIG4, GPMC_CONFIG4 + GPMC_CONFIG_CS0); - __raw_writel( M_NAND_GPMC_CONFIG5, GPMC_CONFIG5 + GPMC_CONFIG_CS0); - __raw_writel( M_NAND_GPMC_CONFIG6, GPMC_CONFIG6 + GPMC_CONFIG_CS0); - - /* Enable the GPMC Mapping */ - __raw_writel(( ((OMAP34XX_GPMC_CS0_SIZE & 0xF)<<8) | - ((NAND_BASE_ADR>>24) & 0x3F) | - (1<<6) ), (GPMC_CONFIG7 + GPMC_CONFIG_CS0)); - delay(2000); - - if (nand_chip()){ -#ifdef CFG_PRINTF - printf("Unsupported Chip!\n"); -#endif - return 1; - } - - } - - if ((get_mem_type() == GPMC_ONENAND) || (get_mem_type() == MMC_ONENAND)){ - __raw_writel( ONENAND_GPMC_CONFIG1, GPMC_CONFIG1 + GPMC_CONFIG_CS0); - __raw_writel( ONENAND_GPMC_CONFIG2, GPMC_CONFIG2 + GPMC_CONFIG_CS0); - __raw_writel( ONENAND_GPMC_CONFIG3, GPMC_CONFIG3 + GPMC_CONFIG_CS0); - __raw_writel( ONENAND_GPMC_CONFIG4, GPMC_CONFIG4 + GPMC_CONFIG_CS0); - __raw_writel( ONENAND_GPMC_CONFIG5, GPMC_CONFIG5 + GPMC_CONFIG_CS0); - __raw_writel( ONENAND_GPMC_CONFIG6, GPMC_CONFIG6 + GPMC_CONFIG_CS0); - - /* Enable the GPMC Mapping */ - __raw_writel(( ((OMAP34XX_GPMC_CS0_SIZE & 0xF)<<8) | - ((ONENAND_BASE>>24) & 0x3F) | - (1<<6) ), (GPMC_CONFIG7 + GPMC_CONFIG_CS0)); - delay(2000); - - if (onenand_chip()){ -#ifdef CFG_PRINTF - printf("OneNAND Unsupported !\n"); -#endif - return 1; - } - } - return 0; -} - -/* optionally do something like blinking LED */ -void board_hang (void) -{ while (0) {};} - -/****************************************************************************** - * Dummy function to handle errors for EABI incompatibility - *****************************************************************************/ -void raise(void) -{ -} - -/****************************************************************************** - * Dummy function to handle errors for EABI incompatibility - *****************************************************************************/ -void abort(void) -{ -} diff --git a/x-loader/board/omap3evm/platform.S b/x-loader/board/omap3evm/platform.S deleted file mode 100644 index 8368487..0000000 --- a/x-loader/board/omap3evm/platform.S +++ /dev/null @@ -1,435 +0,0 @@ -/* - * Board specific setup info - * - * (C) Copyright 2004-2006 - * Texas Instruments, <www.ti.com> - * Richard Woodruff <r-woodruff2@ti.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <config.h> -#include <asm/arch/cpu.h> -#include <asm/arch/mem.h> -#include <asm/arch/clocks.h> - -_TEXT_BASE: - .word TEXT_BASE /* sdram load addr from config.mk */ - -#if !defined(CFG_NAND_BOOT) && !defined(CFG_NAND_BOOT) -/************************************************************************** - * cpy_clk_code: relocates clock code into SRAM where its safer to execute - * R1 = SRAM destination address. - *************************************************************************/ -.global cpy_clk_code - cpy_clk_code: - /* Copy DPLL code into SRAM */ - adr r0, go_to_speed /* get addr of clock setting code */ - mov r2, #384 /* r2 size to copy (div by 32 bytes) */ - mov r1, r1 /* r1 <- dest address (passed in) */ - add r2, r2, r0 /* r2 <- source end address */ -next2: - ldmia r0!, {r3-r10} /* copy from source address [r0] */ - stmia r1!, {r3-r10} /* copy to target address [r1] */ - cmp r0, r2 /* until source end address [r2] */ - bne next2 - mov pc, lr /* back to caller */ - -/* **************************************************************************** - * NOTE: 3430 X-loader currently does not use this code. -* It could be removed its is kept for compatabily with u-boot. - * - * go_to_speed: -Moves to bypass, -Commits clock dividers, -puts dpll at speed - * -executed from SRAM. - * R0 = CM_CLKEN_PLL-bypass value - * R1 = CM_CLKSEL1_PLL-m, n, and divider values - * R2 = CM_CLKSEL_CORE-divider values - * R3 = CM_IDLEST_CKGEN - addr dpll lock wait - * - * Note: If core unlocks/relocks and SDRAM is running fast already it gets - * confused. A reset of the controller gets it back. Taking away its - * L3 when its not in self refresh seems bad for it. Normally, this code - * runs from flash before SDR is init so that should be ok. - ******************************************************************************/ -.global go_to_speed - go_to_speed: - stmfd sp!, {r4-r6} - - /* move into fast relock bypass */ - ldr r4, pll_ctl_add - str r0, [r4] -wait1: - ldr r5, [r3] /* get status */ - and r5, r5, #0x1 /* isolate core status */ - cmp r5, #0x1 /* still locked? */ - beq wait1 /* if lock, loop */ - - /* set new dpll dividers _after_ in bypass */ - ldr r5, pll_div_add1 - str r1, [r5] /* set m, n, m2 */ - ldr r5, pll_div_add2 - str r2, [r5] /* set l3/l4/.. dividers*/ - ldr r5, pll_div_add3 /* wkup */ - ldr r2, pll_div_val3 /* rsm val */ - str r2, [r5] - ldr r5, pll_div_add4 /* gfx */ - ldr r2, pll_div_val4 - str r2, [r5] - ldr r5, pll_div_add5 /* emu */ - ldr r2, pll_div_val5 - str r2, [r5] - - /* now prepare GPMC (flash) for new dpll speed */ - /* flash needs to be stable when we jump back to it */ - ldr r5, flash_cfg3_addr - ldr r2, flash_cfg3_val - str r2, [r5] - ldr r5, flash_cfg4_addr - ldr r2, flash_cfg4_val - str r2, [r5] - ldr r5, flash_cfg5_addr - ldr r2, flash_cfg5_val - str r2, [r5] - ldr r5, flash_cfg1_addr - ldr r2, [r5] - orr r2, r2, #0x3 /* up gpmc divider */ - str r2, [r5] - - /* lock DPLL3 and wait a bit */ - orr r0, r0, #0x7 /* set up for lock mode */ - str r0, [r4] /* lock */ - nop /* ARM slow at this point working at sys_clk */ - nop - nop - nop -wait2: - ldr r5, [r3] /* get status */ - and r5, r5, #0x1 /* isolate core status */ - cmp r5, #0x1 /* still locked? */ - bne wait2 /* if lock, loop */ - nop - nop - nop - nop - ldmfd sp!, {r4-r6} - mov pc, lr /* back to caller, locked */ - -_go_to_speed: .word go_to_speed - -/* these constants need to be close for PIC code */ -/* The Nor has to be in the Flash Base CS0 for this condition to happen */ -flash_cfg1_addr: - .word (GPMC_CONFIG_CS0 + GPMC_CONFIG1) -flash_cfg3_addr: - .word (GPMC_CONFIG_CS0 + GPMC_CONFIG3) -flash_cfg3_val: - .word STNOR_GPMC_CONFIG3 -flash_cfg4_addr: - .word (GPMC_CONFIG_CS0 + GPMC_CONFIG4) -flash_cfg4_val: - .word STNOR_GPMC_CONFIG4 -flash_cfg5_val: - .word STNOR_GPMC_CONFIG5 -flash_cfg5_addr: - .word (GPMC_CONFIG_CS0 + GPMC_CONFIG5) -pll_ctl_add: - .word CM_CLKEN_PLL -pll_div_add1: - .word CM_CLKSEL1_PLL -pll_div_add2: - .word CM_CLKSEL_CORE -pll_div_add3: - .word CM_CLKSEL_WKUP -pll_div_val3: - .word (WKUP_RSM << 1) -pll_div_add4: - .word CM_CLKSEL_GFX -pll_div_val4: - .word (GFX_DIV << 0) -pll_div_add5: - .word CM_CLKSEL1_EMU -pll_div_val5: - .word CLSEL1_EMU_VAL - -#endif - -.globl lowlevel_init -lowlevel_init: - ldr sp, SRAM_STACK - str ip, [sp] /* stash old link register */ - mov ip, lr /* save link reg across call */ - bl s_init /* go setup pll,mux,memory */ - ldr ip, [sp] /* restore save ip */ - mov lr, ip /* restore link reg */ - - /* back to arch calling code */ - mov pc, lr - - /* the literal pools origin */ - .ltorg - -REG_CONTROL_STATUS: - .word CONTROL_STATUS -SRAM_STACK: - .word LOW_LEVEL_SRAM_STACK - - -/* DPLL(1-4) PARAM TABLES */ -/* Each of the tables has M, N, FREQSEL, M2 values defined for nominal - * OPP (1.2V). The fields are defined according to dpll_param struct(clock.c). - * The values are defined for all possible sysclk and for ES1 and ES2. - */ - -mpu_dpll_param: -/* 12MHz */ -/* ES1 */ -.word 0x0FE -.word 0x07 -.word 0x05 -.word 0x01 -/* ES2 */ -.word 0x0FA -.word 0x05 -.word 0x07 -.word 0x01 - -/* 13MHz */ -/* ES1 */ -.word 0x17D -.word 0x0C -.word 0x03 -.word 0x01 -/* ES2 */ -.word 0x1F4 -.word 0x0C -.word 0x03 -.word 0x01 - -/* 19.2MHz */ -/* ES1 */ -.word 0x179 -.word 0x12 -.word 0x04 -.word 0x01 -/* ES2 */ -.word 0x271 -.word 0x17 -.word 0x03 -.word 0x01 - -/* 26MHz */ -/* ES1 */ -.word 0x17D -.word 0x19 -.word 0x03 -.word 0x01 -/* ES2 */ -.word 0x0FA -.word 0x0C -.word 0x07 -.word 0x01 - -/* 38.4MHz */ -/* ES1 */ -.word 0x1FA -.word 0x32 -.word 0x03 -.word 0x01 -/* ES2 */ -.word 0x271 -.word 0x2F -.word 0x03 -.word 0x01 - - -.globl get_mpu_dpll_param -get_mpu_dpll_param: - adr r0, mpu_dpll_param - mov pc, lr - -iva_dpll_param: -/* 12MHz */ -/* ES1 */ -.word 0x07D -.word 0x05 -.word 0x07 -.word 0x01 -/* ES2 */ -.word 0x0B4 -.word 0x05 -.word 0x07 -.word 0x01 - -/* 13MHz */ -/* ES1 */ -.word 0x0FA -.word 0x0C -.word 0x03 -.word 0x01 -/* ES2 */ -.word 0x168 -.word 0x0C -.word 0x03 -.word 0x01 - -/* 19.2MHz */ -/* ES1 */ -.word 0x082 -.word 0x09 -.word 0x07 -.word 0x01 -/* ES2 */ -.word 0x0E1 -.word 0x0B -.word 0x06 -.word 0x01 - -/* 26MHz */ -/* ES1 */ -.word 0x07D -.word 0x0C -.word 0x07 -.word 0x01 -/* ES2 */ -.word 0x0B4 -.word 0x0C -.word 0x07 -.word 0x01 - -/* 38.4MHz */ -/* ES1 */ -.word 0x13F -.word 0x30 -.word 0x03 -.word 0x01 -/* ES2 */ -.word 0x0E1 -.word 0x17 -.word 0x06 -.word 0x01 - - -.globl get_iva_dpll_param -get_iva_dpll_param: - adr r0, iva_dpll_param - mov pc, lr - -core_dpll_param: -/* 12MHz */ -/* ES1 */ -.word 0x19F -.word 0x0E -.word 0x03 -.word 0x01 -/* ES2 */ -.word 0x0A6 -.word 0x05 -.word 0x07 -.word 0x01 - -/* 13MHz */ -/* ES1 */ -.word 0x1B2 -.word 0x10 -.word 0x03 -.word 0x01 -/* ES2 */ -.word 0x14C -.word 0x0C -.word 0x03 -.word 0x01 - -/* 19.2MHz */ -/* ES1 */ -.word 0x19F -.word 0x17 -.word 0x03 -.word 0x01 -/* ES2 */ -.word 0x19F -.word 0x17 -.word 0x03 -.word 0x01 - -/* 26MHz */ -/* ES1 */ -.word 0x1B2 -.word 0x21 -.word 0x03 -.word 0x01 -/* ES2 */ -.word 0x0A6 -.word 0x0C -.word 0x07 -.word 0x01 - -/* 38.4MHz */ -/* ES1 */ -.word 0x19F -.word 0x2F -.word 0x03 -.word 0x01 -/* ES2 */ -.word 0x19F -.word 0x2F -.word 0x03 -.word 0x01 - -.globl get_core_dpll_param -get_core_dpll_param: - adr r0, core_dpll_param - mov pc, lr - -/* PER DPLL values are same for both ES1 and ES2 */ -per_dpll_param: -/* 12MHz */ -.word 0xD8 -.word 0x05 -.word 0x07 -.word 0x09 - -/* 13MHz */ -.word 0x1B0 -.word 0x0C -.word 0x03 -.word 0x09 - -/* 19.2MHz */ -.word 0xE1 -.word 0x09 -.word 0x07 -.word 0x09 - -/* 26MHz */ -.word 0xD8 -.word 0x0C -.word 0x07 -.word 0x09 - -/* 38.4MHz */ -.word 0xE1 -.word 0x13 -.word 0x07 -.word 0x09 - -.globl get_per_dpll_param -get_per_dpll_param: - adr r0, per_dpll_param - mov pc, lr - diff --git a/x-loader/board/omap3evm/x-load.lds b/x-loader/board/omap3evm/x-load.lds deleted file mode 100644 index 5f352d3..0000000 --- a/x-loader/board/omap3evm/x-load.lds +++ /dev/null @@ -1,54 +0,0 @@ -/* - * November 2006 - Changed to support 3430sdp device - * Copyright (c) 2004-2006 Texas Instruments - * - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, <gj@denx.de> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN(4); - .text : - { - cpu/omap3/start.o (.text) - *(.text) - } - - . = ALIGN(4); - .rodata : { *(.rodata) } - - . = ALIGN(4); - .data : { *(.data) } - - . = ALIGN(4); - .got : { *(.got) } - - . = ALIGN(4); - __bss_start = .; - .bss : { *(.bss) } - _end = .; -} diff --git a/x-loader/board/omap4430panda/Makefile b/x-loader/board/omap4430panda/Makefile deleted file mode 100644 index 6b6f9be..0000000 --- a/x-loader/board/omap4430panda/Makefile +++ /dev/null @@ -1,53 +0,0 @@ -# -# (C) Copyright 2009 -# Texas Instruments, <www.ti.com> -# -# (C) Copyright 2000, 2001, 2002 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License -# version 2 as published by the Free Software Foundation. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).a - -COBJS := omap4430panda.o clock.o syslib.o -SOBJS := platform.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) $(SOBJS) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak $(obj).depend - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/x-loader/board/omap4430panda/clock.c b/x-loader/board/omap4430panda/clock.c deleted file mode 100644 index 792e5d6..0000000 --- a/x-loader/board/omap4430panda/clock.c +++ /dev/null @@ -1,804 +0,0 @@ -/* - * (C) Copyright 2009 - * Texas Instruments, <www.ti.com> - * Richard Woodruff <r-woodruff2@ti.com> - * Rajendra Nayak <rnayak@ti.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <asm/arch/cpu.h> -#include <asm/io.h> -#include <asm/arch/bits.h> -#include <asm/arch/clocks.h> -#include <asm/arch/mem.h> -#include <asm/arch/sys_proto.h> -#include <asm/arch/sys_info.h> -#include <asm/arch/clocks443x.h> -#include <command.h> - -#define CONFIG_OMAP4_SDC 1 - -/* Used to index into DPLL parameter tables */ -struct dpll_param { - unsigned int m; - unsigned int n; - unsigned int m2; - unsigned int m3; - unsigned int m4; - unsigned int m5; - unsigned int m6; - unsigned int m7; -}; - -/* Tables having M,N,M2 et al values for different sys_clk speeds - * This table is generated only for OPP100 - * The tables are organized as follows: - * Rows : 1 - 12M, 2 - 13M, 3 - 16.8M, 4 - 19.2M, 5 - 26M, 6 - 27M, 7 - 38.4M - */ - -/* MPU parameters */ -struct dpll_param mpu_dpll_param[7] = { - /* 12M values */ - {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, - /* 13M values */ - {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, - /* 16.8M values */ - {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, - /* 19.2M values */ - {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, - /* 26M values */ - {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, - /* 27M values */ - {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, - /* 38.4M values */ -#ifdef CONFIG_MPU_600 - /* RUN MPU @ 600 MHz */ - {0x7d, 0x07, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00}, -#elif CONFIG_MPU_1000 - {0x69, 0x03, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00}, -#else - {0x1a, 0x02, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00}, -#endif -}; - -/* IVA parameters */ -struct dpll_param iva_dpll_param[7] = { - /* 12M values */ - {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, - /* 13M values */ - {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, - /* 16.8M values */ - {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, - /* 19.2M values */ - {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, - /* 26M values */ - {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, - /* 27M values */ - {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, - /* 38.4M values */ -#ifdef CONFIG_OMAP4_SDC - {0x61, 0x03, 0x00, 0x00, 0x04, 0x07, 0x00, 0x00}, -#else - {0x61, 0x03, 0x00, 0x00, 0x04, 0x07, 0x00, 0x00}, -#endif -}; - -/* CORE parameters */ -struct dpll_param core_dpll_param[7] = { - /* 12M values */ - {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, - /* 13M values */ - {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, - /* 16.8M values */ - {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, - /* 19.2M values */ - {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, - /* 26M values */ - {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, - /* 27M values */ - {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, - /* 38.4M values - DDR@200MHz*/ - {0x7d, 0x05, 0x02, 0x05, 0x08, 0x04, 0x06, 0x05}, -}; - -/* CORE parameters - ES2.1 */ -struct dpll_param core_dpll_param_ddr400[7] = { - /* 12M values */ - {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, - /* 13M values */ - {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, - /* 16.8M values */ - {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, - /* 19.2M values */ - {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, - /* 26M values */ - {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, - /* 27M values */ - {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, - /* 38.4M values - DDR@400MHz*/ - {0x7d, 0x05, 0x01, 0x05, 0x08, 0x04, 0x06, 0x05}, -}; - -/* CORE parameters for L3 at 190 MHz - For ES1 only*/ -struct dpll_param core_dpll_param_l3_190[7] = { - /* 12M values */ - {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, - /* 13M values */ - {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, - /* 16.8M values */ - {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, - /* 19.2M values */ - {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, - /* 26M values */ - {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, - /* 27M values */ - {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, - /* 38.4M values */ -#ifdef CONFIG_OMAP4_SDC -#ifdef CORE_190MHZ - {0x1f0, 0x18, 0x01, 0x05, 0x08, 0x04, 0x06, 0x05}, -#else /* Default CORE @166MHz */ - {0x1b0, 0x18, 0x01, 0x05, 0x08, 0x04, 0x06, 0x05}, -#endif -#else - {0x7d, 0x05, 0x01, 0x05, 0x08, 0x04, 0x06, 0x08}, -#endif -}; - -/* PER parameters */ -struct dpll_param per_dpll_param[7] = { - /* 12M values */ - {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, - /* 13M values */ - {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, - /* 16.8M values */ - {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, - /* 19.2M values */ - {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, - /* 26M values */ - {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, - /* 27M values */ - {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, - /* 38.4M values */ -#if 0 - /* SDC settings */ - {0x0a, 0x00, 0x04, 0x03, 0x06, 0x05, 0x02, 0x03}, -#endif - {0x14, 0x00, 0x08, 0x06, 0x0c, 0x09, 0x04, 0x05}, -}; - -/* ABE parameters */ -struct dpll_param abe_dpll_param[7] = { - /* 12M values */ - {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, - /* 13M values */ - {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, - /* 16.8M values */ - {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, - /* 19.2M values */ - {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, - /* 26M values */ - {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, - /* 27M values */ - {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, - /* 38.4M values */ -#ifdef CONFIG_OMAP4_SDC - {0x40, 0x18, 0x1, 0x1, 0x0, 0x0, 0x0, 0x0}, -#else - {0x40, 0x18, 0x1, 0x1, 0x0, 0x0, 0x0, 0x0}, -#endif -}; - -/* USB parameters */ -struct dpll_param usb_dpll_param[7] = { - /* 12M values */ - {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, - /* 13M values */ - {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, - /* 16.8M values */ - {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, - /* 19.2M values */ - {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, - /* 26M values */ - {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, - /* 27M values */ - {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, - /* 38.4M values */ -#ifdef CONFIG_OMAP4_SDC - {0x32, 0x1, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0}, -#else - {0x32, 0x1, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0}, -#endif -}; - -typedef struct dpll_param dpll_param; - -static void configure_mpu_dpll(u32 clk_index) -{ - dpll_param *dpll_param_p; - - /* Unlock the MPU dpll */ - sr32(CM_CLKMODE_DPLL_MPU, 0, 3, PLL_MN_POWER_BYPASS); - wait_on_value(BIT0, 0, CM_IDLEST_DPLL_MPU, LDELAY); - - /* Program MPU DPLL */ - dpll_param_p = &mpu_dpll_param[clk_index]; - - sr32(CM_AUTOIDLE_DPLL_MPU, 0, 3, 0x0); /* Disable DPLL autoidle */ - - /* Set M,N,M2 values */ - sr32(CM_CLKSEL_DPLL_MPU, 8, 11, dpll_param_p->m); - sr32(CM_CLKSEL_DPLL_MPU, 0, 6, dpll_param_p->n); - sr32(CM_DIV_M2_DPLL_MPU, 0, 5, dpll_param_p->m2); - sr32(CM_DIV_M2_DPLL_MPU, 8, 1, 0x1); - - /* Lock the mpu dpll */ - sr32(CM_CLKMODE_DPLL_MPU, 0, 3, PLL_LOCK | 0x10); - wait_on_value(BIT0, 1, CM_IDLEST_DPLL_MPU, LDELAY); - - return; -} - -static void configure_iva_dpll(u32 clk_index) -{ - dpll_param *dpll_param_p; - - /* Unlock the IVA dpll */ - sr32(CM_CLKMODE_DPLL_IVA, 0, 3, PLL_MN_POWER_BYPASS); - wait_on_value(BIT0, 0, CM_IDLEST_DPLL_IVA, LDELAY); - - /* CM_BYPCLK_DPLL_IVA = CORE_X2_CLK/2 */ - sr32(CM_BYPCLK_DPLL_IVA, 0, 2, 0x1); - - /* Program IVA DPLL */ - dpll_param_p = &iva_dpll_param[clk_index]; - - sr32(CM_AUTOIDLE_DPLL_IVA, 0, 3, 0x0); /* Disable DPLL autoidle */ - - /* Set M,N,M4,M5 */ - sr32(CM_CLKSEL_DPLL_IVA, 8, 11, dpll_param_p->m); - sr32(CM_CLKSEL_DPLL_IVA, 0, 7, dpll_param_p->n); - sr32(CM_DIV_M4_DPLL_IVA, 0, 5, dpll_param_p->m4); - sr32(CM_DIV_M4_DPLL_IVA, 8, 1, 0x1); - sr32(CM_DIV_M5_DPLL_IVA, 0, 5, dpll_param_p->m5); - sr32(CM_DIV_M5_DPLL_IVA, 8, 1, 0x1); - - /* Lock the iva dpll */ - sr32(CM_CLKMODE_DPLL_IVA, 0, 3, PLL_LOCK); - wait_on_value(BIT0, 1, CM_IDLEST_DPLL_IVA, LDELAY); - - return; -} - -static void configure_per_dpll(u32 clk_index) -{ - dpll_param *dpll_param_p; - - /* Unlock the PER dpll */ - sr32(CM_CLKMODE_DPLL_PER, 0, 3, PLL_MN_POWER_BYPASS); - wait_on_value(BIT0, 0, CM_IDLEST_DPLL_PER, LDELAY); - - /* Program PER DPLL */ - dpll_param_p = &per_dpll_param[clk_index]; - - /* Disable autoidle */ - sr32(CM_AUTOIDLE_DPLL_PER, 0, 3, 0x0); - - sr32(CM_CLKSEL_DPLL_PER, 8, 11, dpll_param_p->m); - sr32(CM_CLKSEL_DPLL_PER, 0, 6, dpll_param_p->n); - sr32(CM_DIV_M2_DPLL_PER, 0, 5, dpll_param_p->m2); - sr32(CM_DIV_M3_DPLL_PER, 0, 5, dpll_param_p->m3); - sr32(CM_DIV_M4_DPLL_PER, 0, 5, dpll_param_p->m4); - sr32(CM_DIV_M5_DPLL_PER, 0, 5, dpll_param_p->m5); - sr32(CM_DIV_M6_DPLL_PER, 0, 5, dpll_param_p->m6); - sr32(CM_DIV_M7_DPLL_PER, 0, 5, dpll_param_p->m7); - -// if(omap_revision() == OMAP4430_ES1_0) -// { - /* Do this only on ES1.0 */ - sr32(CM_DIV_M2_DPLL_PER, 8, 1, 0x1); - sr32(CM_DIV_M3_DPLL_PER, 8, 1, 0x1); - sr32(CM_DIV_M4_DPLL_PER, 8, 1, 0x1); - sr32(CM_DIV_M5_DPLL_PER, 8, 1, 0x1); - sr32(CM_DIV_M6_DPLL_PER, 8, 1, 0x1); - sr32(CM_DIV_M7_DPLL_PER, 8, 1, 0x1); -// } - - /* Lock the per dpll */ - sr32(CM_CLKMODE_DPLL_PER, 0, 3, PLL_LOCK); - wait_on_value(BIT0, 1, CM_IDLEST_DPLL_PER, LDELAY); - - return; -} - -static void configure_abe_dpll(u32 clk_index) -{ - dpll_param *dpll_param_p; - - /* Select sys_clk as ref clk for ABE dpll */ - sr32(CM_ABE_PLL_REF_CLKSEL, 0, 32, 0x0); - - /* Enable slimbus and pad clocks */ - sr32(CM_CLKSEL_ABE, 0, 32, 0x500); - - /* Unlock the ABE dpll */ - sr32(CM_CLKMODE_DPLL_ABE, 0, 3, PLL_MN_POWER_BYPASS); - wait_on_value(BIT0, 0, CM_IDLEST_DPLL_ABE, LDELAY); - - /* Program ABE DPLL */ - dpll_param_p = &abe_dpll_param[clk_index]; - - /* Disable autoidle */ - sr32(CM_AUTOIDLE_DPLL_ABE, 0, 3, 0x0); - - sr32(CM_CLKSEL_DPLL_ABE, 8, 11, dpll_param_p->m); - sr32(CM_CLKSEL_DPLL_ABE, 0, 6, dpll_param_p->n); - - /* Force DPLL CLKOUTHIF to stay enabled */ - sr32(CM_DIV_M2_DPLL_ABE, 0, 32, 0x500); - sr32(CM_DIV_M2_DPLL_ABE, 0, 5, dpll_param_p->m2); - sr32(CM_DIV_M2_DPLL_ABE, 8, 1, 0x1); - /* Force DPLL CLKOUTHIF to stay enabled */ - sr32(CM_DIV_M3_DPLL_ABE, 0, 32, 0x100); - sr32(CM_DIV_M3_DPLL_ABE, 0, 5, dpll_param_p->m3); - sr32(CM_DIV_M3_DPLL_ABE, 8, 1, 0x1); - - /* Lock the abe dpll */ - sr32(CM_CLKMODE_DPLL_ABE, 0, 3, PLL_LOCK); - wait_on_value(BIT0, 1, CM_IDLEST_DPLL_ABE, LDELAY); - - return; -} - -static void configure_usb_dpll(u32 clk_index) -{ - dpll_param *dpll_param_p; - - /* Select the 60Mhz clock 480/8 = 60*/ - sr32(CM_CLKSEL_USB_60MHz, 0, 32, 0x1); - - /* Unlock the USB dpll */ - sr32(CM_CLKMODE_DPLL_USB, 0, 3, PLL_MN_POWER_BYPASS); - wait_on_value(BIT0, 0, CM_IDLEST_DPLL_USB, LDELAY); - - /* Program USB DPLL */ - dpll_param_p = &usb_dpll_param[clk_index]; - - /* Disable autoidle */ - sr32(CM_AUTOIDLE_DPLL_USB, 0, 3, 0x0); - - sr32(CM_CLKSEL_DPLL_USB, 8, 11, dpll_param_p->m); - sr32(CM_CLKSEL_DPLL_USB, 0, 6, dpll_param_p->n); - - /* Force DPLL CLKOUT to stay active */ - sr32(CM_DIV_M2_DPLL_USB, 0, 32, 0x100); - sr32(CM_DIV_M2_DPLL_USB, 0, 5, dpll_param_p->m2); - sr32(CM_DIV_M2_DPLL_USB, 8, 1, 0x1); - sr32(CM_CLKDCOLDO_DPLL_USB, 8, 1, 0x1); - - /* Lock the usb dpll */ - sr32(CM_CLKMODE_DPLL_USB, 0, 3, PLL_LOCK); - wait_on_value(BIT0, 1, CM_IDLEST_DPLL_USB, LDELAY); - - /* force enable the CLKDCOLDO clock */ - sr32(CM_CLKDCOLDO_DPLL_USB, 0, 32, 0x100); - - return; -} - -static void configure_core_dpll(clk_index) -{ - dpll_param *dpll_param_p; - - /* Get the sysclk speed from cm_sys_clksel - * Set it to 38.4 MHz, in case ROM code is bypassed - */ - if (!clk_index) - return; - - /* CORE_CLK=CORE_X2_CLK/2, L3_CLK=CORE_CLK/2, L4_CLK=L3_CLK/2 */ - sr32(CM_CLKSEL_CORE, 0, 32, 0x110); - - /* Unlock the CORE dpll */ - sr32(CM_CLKMODE_DPLL_CORE, 0, 3, PLL_MN_POWER_BYPASS); - wait_on_value(BIT0, 0, CM_IDLEST_DPLL_CORE, LDELAY); - - /* Program Core DPLL */ - if(omap_revision() == OMAP4430_ES1_0) - dpll_param_p = &core_dpll_param_l3_190[clk_index]; - else if(omap_revision() == OMAP4430_ES2_0) - dpll_param_p = &core_dpll_param[clk_index]; - else if(omap_revision() == OMAP4430_ES2_1) - dpll_param_p = &core_dpll_param_ddr400[clk_index]; - - /* Disable autoidle */ - sr32(CM_AUTOIDLE_DPLL_CORE, 0, 3, 0x0); - - sr32(CM_CLKSEL_DPLL_CORE, 8, 11, dpll_param_p->m); - sr32(CM_CLKSEL_DPLL_CORE, 0, 6, dpll_param_p->n); - sr32(CM_DIV_M2_DPLL_CORE, 0, 5, dpll_param_p->m2); - sr32(CM_DIV_M3_DPLL_CORE, 0, 5, dpll_param_p->m3); - sr32(CM_DIV_M4_DPLL_CORE, 0, 5, dpll_param_p->m4); - sr32(CM_DIV_M5_DPLL_CORE, 0, 5, dpll_param_p->m5); - sr32(CM_DIV_M6_DPLL_CORE, 0, 5, dpll_param_p->m6); - sr32(CM_DIV_M7_DPLL_CORE, 0, 5, dpll_param_p->m7); - - if(omap_revision() == OMAP4430_ES1_0) - { - /* Do this only on ES1.0 */ - sr32(CM_DIV_M2_DPLL_CORE, 8, 1, 0x1); - sr32(CM_DIV_M3_DPLL_CORE, 8, 1, 0x1); - sr32(CM_DIV_M4_DPLL_CORE, 8, 1, 0x1); - sr32(CM_DIV_M5_DPLL_CORE, 8, 1, 0x1); - sr32(CM_DIV_M6_DPLL_CORE, 8, 1, 0x1); - sr32(CM_DIV_M7_DPLL_CORE, 8, 1, 0x1); - } - - - /* Lock the core dpll */ - sr32(CM_CLKMODE_DPLL_CORE, 0, 3, PLL_LOCK); - wait_on_value(BIT0, 1, CM_IDLEST_DPLL_CORE, LDELAY); - - return; -} - - -void configure_core_dpll_no_lock(void) -{ - dpll_param *dpll_param_p; - u32 clk_index; - - /* Get the sysclk speed from cm_sys_clksel - * Set it to 38.4 MHz, in case ROM code is bypassed - */ - __raw_writel(0x7,CM_SYS_CLKSEL); - clk_index = 7; - - clk_index = clk_index - 1; - /* CORE_CLK=CORE_X2_CLK/2, L3_CLK=CORE_CLK/2, L4_CLK=L3_CLK/2 */ - sr32(CM_CLKSEL_CORE, 0, 32, 0x110); - - /* Unlock the CORE dpll */ - sr32(CM_CLKMODE_DPLL_CORE, 0, 3, PLL_MN_POWER_BYPASS); - wait_on_value(BIT0, 0, CM_IDLEST_DPLL_CORE, LDELAY); - - /* Program Core DPLL */ - if(omap_revision() == OMAP4430_ES1_0) - dpll_param_p = &core_dpll_param_l3_190[clk_index]; - else if(omap_revision() == OMAP4430_ES2_0) - dpll_param_p = &core_dpll_param[clk_index]; - else if(omap_revision() == OMAP4430_ES2_1) - dpll_param_p = &core_dpll_param_ddr400[clk_index]; - - /* Disable autoidle */ - sr32(CM_AUTOIDLE_DPLL_CORE, 0, 3, 0x0); - - sr32(CM_CLKSEL_DPLL_CORE, 8, 11, dpll_param_p->m); - sr32(CM_CLKSEL_DPLL_CORE, 0, 6, dpll_param_p->n); - sr32(CM_DIV_M2_DPLL_CORE, 0, 5, dpll_param_p->m2); - sr32(CM_DIV_M3_DPLL_CORE, 0, 5, dpll_param_p->m3); - sr32(CM_DIV_M4_DPLL_CORE, 0, 5, dpll_param_p->m4); - sr32(CM_DIV_M5_DPLL_CORE, 0, 5, dpll_param_p->m5); - sr32(CM_DIV_M6_DPLL_CORE, 0, 5, dpll_param_p->m6); - sr32(CM_DIV_M7_DPLL_CORE, 0, 5, dpll_param_p->m7); - -// if(omap_revision() == OMAP4430_ES1_0) -// { - /* Do this only on ES1.0 */ - sr32(CM_DIV_M2_DPLL_CORE, 8, 1, 0x1); - sr32(CM_DIV_M3_DPLL_CORE, 8, 1, 0x1); - sr32(CM_DIV_M4_DPLL_CORE, 8, 1, 0x1); - sr32(CM_DIV_M5_DPLL_CORE, 8, 1, 0x1); - sr32(CM_DIV_M6_DPLL_CORE, 8, 1, 0x1); - sr32(CM_DIV_M7_DPLL_CORE, 8, 1, 0x1); -// } - - return; -} - -void lock_core_dpll(void) -{ - /* Lock the core dpll */ - sr32(CM_CLKMODE_DPLL_CORE, 0, 3, PLL_LOCK); - wait_on_value(BIT0, 1, CM_IDLEST_DPLL_CORE, LDELAY); - - return; -} - -void lock_core_dpll_shadow(void) -{ - dpll_param *dpll_param_p; - /* Lock the core dpll using freq update method */ - *(volatile int*)0x4A004120 = 10; //(CM_CLKMODE_DPLL_CORE) - - if(omap_revision() == OMAP4430_ES1_0) - dpll_param_p = &core_dpll_param_l3_190[6]; - else if(omap_revision() == OMAP4430_ES2_0) - dpll_param_p = &core_dpll_param[6]; - else if(omap_revision() == OMAP4430_ES2_1) - dpll_param_p = &core_dpll_param_ddr400[6]; - - /* CM_SHADOW_FREQ_CONFIG1: DLL_OVERRIDE = 1(hack), DLL_RESET = 1, - * DPLL_CORE_M2_DIV =1, DPLL_CORE_DPLL_EN = 0x7, FREQ_UPDATE = 1 - */ - *(volatile int*)0x4A004260 = 0x70D | (dpll_param_p->m2 << 11); - - /* Wait for Freq_Update to get cleared: CM_SHADOW_FREQ_CONFIG1 */ - while( ( (*(volatile int*)0x4A004260) & 0x1) == 0x1 ); - - /* Wait for DPLL to Lock : CM_IDLEST_DPLL_CORE */ - wait_on_value(BIT0, 1, CM_IDLEST_DPLL_CORE, LDELAY); - //lock_core_dpll(); - - return; -} - -static void enable_all_clocks(void) -{ - volatile int regvalue = 0; - - /* Enable Ducati clocks */ - sr32(CM_DUCATI_DUCATI_CLKCTRL, 0, 32, 0x1); - sr32(CM_DUCATI_CLKSTCTRL, 0, 32, 0x2); - - wait_on_value(BIT8, BIT8, CM_DUCATI_CLKSTCTRL, LDELAY); - //wait_on_value(BIT18|BIT17|BIT16, 0, CM_DUCATI_DUCATI_CLKCTRL, LDELAY); - - /* Enable ivahd and sl2 clocks */ - sr32(IVAHD_IVAHD_CLKCTRL, 0, 32, 0x1); - sr32(IVAHD_SL2_CLKCTRL, 0, 32, 0x1); - sr32(IVAHD_CLKSTCTRL, 0, 32, 0x2); - - wait_on_value(BIT8, BIT8, IVAHD_CLKSTCTRL, LDELAY); - - /* wait for ivahd to become accessible */ - //wait_on_value(BIT18|BIT17|BIT16, 0, IVAHD_IVAHD_CLKCTRL, LDELAY); - /* wait for sl2 to become accessible */ - //wait_on_value(BIT17|BIT16, 0, IVAHD_SL2_CLKCTRL, LDELAY); - - /* Enable Tesla clocks */ - sr32(DSP_DSP_CLKCTRL, 0, 32, 0x1); - sr32(DSP_CLKSTCTRL, 0, 32, 0x2); - - wait_on_value(BIT8, BIT8, DSP_CLKSTCTRL, LDELAY); - - /* wait for tesla to become accessible */ - //wait_on_value(BIT18|BIT17|BIT16, 0, DSP_DSP_CLKCTRL, LDELAY); - - /* TODO: Some hack needed by MM: Clean this */ - #if 0 /* Doesn't work on some Zebu */ - *(volatile int*)0x4a306910 = 0x00000003; - *(volatile int*)0x550809a0 = 0x00000001; - *(volatile int*)0x55080a20 = 0x00000007; - #endif - - /* ABE clocks */ - sr32(CM1_ABE_CLKSTCTRL, 0, 32, 0x3); - sr32(CM1_ABE_AESS_CLKCTRL, 0, 32, 0x2); - //wait_on_value(BIT18|BIT17|BIT16, 0, CM1_ABE_AESS_CLKCTRL, LDELAY); - sr32(CM1_ABE_PDM_CLKCTRL, 0, 32, 0x2); - //wait_on_value(BIT17|BIT16, 0, CM1_ABE_PDM_CLKCTRL, LDELAY); - sr32(CM1_ABE_DMIC_CLKCTRL, 0, 32, 0x2); - //wait_on_value(BIT17|BIT16, 0, CM1_ABE_DMIC_CLKCTRL, LDELAY); - sr32(CM1_ABE_MCASP_CLKCTRL, 0, 32, 0x2); - //wait_on_value(BIT17|BIT16, 0, CM1_ABE_MCASP_CLKCTRL, LDELAY); - sr32(CM1_ABE_MCBSP1_CLKCTRL, 0, 32, 0x08000002); - //wait_on_value(BIT17|BIT16, 0, CM1_ABE_MCBSP1_CLKCTRL, LDELAY); - sr32(CM1_ABE_MCBSP2_CLKCTRL, 0, 32, 0x08000002); - //wait_on_value(BIT17|BIT16, 0, CM1_ABE_MCBSP2_CLKCTRL, LDELAY); - sr32(CM1_ABE_MCBSP3_CLKCTRL, 0, 32, 0x08000002); - //wait_on_value(BIT17|BIT16, 0, CM1_ABE_MCBSP3_CLKCTRL, LDELAY); - sr32(CM1_ABE_SLIMBUS_CLKCTRL, 0, 32, 0xf02); - //wait_on_value(BIT17|BIT16, 0, CM1_ABE_SLIMBUS_CLKCTRL, LDELAY); - sr32(CM1_ABE_TIMER5_CLKCTRL, 0, 32, 0x2); - //wait_on_value(BIT17|BIT16, 0, CM1_ABE_TIMER5_CLKCTRL, LDELAY); - sr32(CM1_ABE_TIMER6_CLKCTRL, 0, 32, 0x2); - //wait_on_value(BIT17|BIT16, 0, CM1_ABE_TIMER6_CLKCTRL, LDELAY); - sr32(CM1_ABE_TIMER7_CLKCTRL, 0, 32, 0x2); - //wait_on_value(BIT17|BIT16, 0, CM1_ABE_TIMER7_CLKCTRL, LDELAY); - sr32(CM1_ABE_TIMER8_CLKCTRL, 0, 32, 0x2); - //wait_on_value(BIT17|BIT16, 0, CM1_ABE_TIMER8_CLKCTRL, LDELAY); - sr32(CM1_ABE_WDT3_CLKCTRL, 0, 32, 0x2); - //wait_on_value(BIT17|BIT16, 0, CM1_ABE_WDT3_CLKCTRL, LDELAY); - /* Disable sleep transitions */ - sr32(CM1_ABE_CLKSTCTRL, 0, 32, 0x0); - - /* L4PER clocks */ - sr32(CM_L4PER_CLKSTCTRL, 0, 32, 0x2); - sr32(CM_L4PER_DMTIMER10_CLKCTRL, 0, 32, 0x2); - wait_on_value(BIT17|BIT16, 0, CM_L4PER_DMTIMER10_CLKCTRL, LDELAY); - sr32(CM_L4PER_DMTIMER11_CLKCTRL, 0, 32, 0x2); - wait_on_value(BIT17|BIT16, 0, CM_L4PER_DMTIMER11_CLKCTRL, LDELAY); - sr32(CM_L4PER_DMTIMER2_CLKCTRL, 0, 32, 0x2); - wait_on_value(BIT17|BIT16, 0, CM_L4PER_DMTIMER2_CLKCTRL, LDELAY); - sr32(CM_L4PER_DMTIMER3_CLKCTRL, 0, 32, 0x2); - wait_on_value(BIT17|BIT16, 0, CM_L4PER_DMTIMER3_CLKCTRL, LDELAY); - sr32(CM_L4PER_DMTIMER4_CLKCTRL, 0, 32, 0x2); - wait_on_value(BIT17|BIT16, 0, CM_L4PER_DMTIMER4_CLKCTRL, LDELAY); - sr32(CM_L4PER_DMTIMER9_CLKCTRL, 0, 32, 0x2); - wait_on_value(BIT17|BIT16, 0, CM_L4PER_DMTIMER9_CLKCTRL, LDELAY); - - /* GPIO clocks */ - sr32(CM_L4PER_GPIO2_CLKCTRL, 0 ,32, 0x1); - wait_on_value(BIT17|BIT16, 0, CM_L4PER_GPIO2_CLKCTRL, LDELAY); - sr32(CM_L4PER_GPIO3_CLKCTRL, 0, 32, 0x1); - wait_on_value(BIT17|BIT16, 0, CM_L4PER_GPIO3_CLKCTRL, LDELAY); - sr32(CM_L4PER_GPIO4_CLKCTRL, 0, 32, 0x1); - wait_on_value(BIT17|BIT16, 0, CM_L4PER_GPIO4_CLKCTRL, LDELAY); - sr32(CM_L4PER_GPIO5_CLKCTRL, 0, 32, 0x1); - wait_on_value(BIT17|BIT16, 0, CM_L4PER_GPIO5_CLKCTRL, LDELAY); - sr32(CM_L4PER_GPIO6_CLKCTRL, 0, 32, 0x1); - wait_on_value(BIT17|BIT16, 0, CM_L4PER_GPIO6_CLKCTRL, LDELAY); - - sr32(CM_L4PER_HDQ1W_CLKCTRL, 0, 32, 0x2); - - /* I2C clocks */ - sr32(CM_L4PER_I2C1_CLKCTRL, 0, 32, 0x2); - wait_on_value(BIT17|BIT16, 0, CM_L4PER_I2C1_CLKCTRL, LDELAY); - sr32(CM_L4PER_I2C2_CLKCTRL, 0, 32, 0x2); - wait_on_value(BIT17|BIT16, 0, CM_L4PER_I2C2_CLKCTRL, LDELAY); - sr32(CM_L4PER_I2C3_CLKCTRL, 0, 32, 0x2); - wait_on_value(BIT17|BIT16, 0, CM_L4PER_I2C3_CLKCTRL, LDELAY); - sr32(CM_L4PER_I2C4_CLKCTRL, 0, 32, 0x2); - wait_on_value(BIT17|BIT16, 0, CM_L4PER_I2C4_CLKCTRL, LDELAY); - - sr32(CM_L4PER_MCBSP4_CLKCTRL, 0, 32, 0x2); - wait_on_value(BIT17|BIT16, 0, CM_L4PER_MCBSP4_CLKCTRL, LDELAY); - - /* MCSPI clocks */ - sr32(CM_L4PER_MCSPI1_CLKCTRL, 0, 32, 0x2); - wait_on_value(BIT17|BIT16, 0, CM_L4PER_MCSPI1_CLKCTRL, LDELAY); - sr32(CM_L4PER_MCSPI2_CLKCTRL, 0, 32, 0x2); - wait_on_value(BIT17|BIT16, 0, CM_L4PER_MCSPI2_CLKCTRL, LDELAY); - sr32(CM_L4PER_MCSPI3_CLKCTRL, 0, 32, 0x2); - wait_on_value(BIT17|BIT16, 0, CM_L4PER_MCSPI3_CLKCTRL, LDELAY); - sr32(CM_L4PER_MCSPI4_CLKCTRL, 0, 32, 0x2); - wait_on_value(BIT17|BIT16, 0, CM_L4PER_MCSPI4_CLKCTRL, LDELAY); - - /* MMC clocks */ - sr32(CM_L3INIT_HSMMC1_CLKCTRL, 0, 2, 0x2); - sr32(CM_L3INIT_HSMMC1_CLKCTRL, 24, 1, 0x1); - //wait_on_value(BIT18|BIT17|BIT16, 0, CM_L3INIT_HSMMC1_CLKCTRL, LDELAY); - sr32(CM_L3INIT_HSMMC2_CLKCTRL, 0, 2, 0x2); - sr32(CM_L3INIT_HSMMC2_CLKCTRL, 24, 1, 0x1); - //wait_on_value(BIT18|BIT17|BIT16, 0, CM_L3INIT_HSMMC2_CLKCTRL, LDELAY); - sr32(CM_L4PER_MMCSD3_CLKCTRL, 0, 32, 0x2); - wait_on_value(BIT18|BIT17|BIT16, 0, CM_L4PER_MMCSD3_CLKCTRL, LDELAY); - sr32(CM_L4PER_MMCSD4_CLKCTRL, 0, 32, 0x2); - wait_on_value(BIT18|BIT17|BIT16, 0, CM_L4PER_MMCSD4_CLKCTRL, LDELAY); - sr32(CM_L4PER_MMCSD5_CLKCTRL, 0, 32, 0x2); - wait_on_value(BIT17|BIT16, 0, CM_L4PER_MMCSD5_CLKCTRL, LDELAY); - - /* UART clocks */ - sr32(CM_L4PER_UART1_CLKCTRL, 0, 32, 0x2); - wait_on_value(BIT17|BIT16, 0, CM_L4PER_UART1_CLKCTRL, LDELAY); - sr32(CM_L4PER_UART2_CLKCTRL, 0, 32, 0x2); - wait_on_value(BIT17|BIT16, 0, CM_L4PER_UART2_CLKCTRL, LDELAY); - sr32(CM_L4PER_UART3_CLKCTRL, 0, 32, 0x2); - wait_on_value(BIT17|BIT16, 0, CM_L4PER_UART3_CLKCTRL, LDELAY); - sr32(CM_L4PER_UART4_CLKCTRL, 0, 32, 0x2); - wait_on_value(BIT17|BIT16, 0, CM_L4PER_UART4_CLKCTRL, LDELAY); - - /* WKUP clocks */ - sr32(CM_WKUP_GPIO1_CLKCTRL, 0, 32, 0x1); - wait_on_value(BIT17|BIT16, 0, CM_WKUP_GPIO1_CLKCTRL, LDELAY); - sr32(CM_WKUP_TIMER1_CLKCTRL, 0, 32, 0x01000002); - wait_on_value(BIT17|BIT16, 0, CM_WKUP_TIMER1_CLKCTRL, LDELAY); - - sr32(CM_WKUP_KEYBOARD_CLKCTRL, 0, 32, 0x2); - wait_on_value(BIT17|BIT16, 0, CM_WKUP_KEYBOARD_CLKCTRL, LDELAY); - - sr32(CM_SDMA_CLKSTCTRL, 0, 32, 0x0); - sr32(CM_MEMIF_CLKSTCTRL, 0, 32, 0x3); - sr32(CM_MEMIF_EMIF_1_CLKCTRL, 0, 32, 0x1); - wait_on_value(BIT17|BIT16, 0, CM_MEMIF_EMIF_1_CLKCTRL, LDELAY); - sr32(CM_MEMIF_EMIF_2_CLKCTRL, 0, 32, 0x1); - wait_on_value(BIT17|BIT16, 0, CM_MEMIF_EMIF_2_CLKCTRL, LDELAY); - sr32(CM_D2D_CLKSTCTRL, 0, 32, 0x3); - sr32(CM_L3_2_GPMC_CLKCTRL, 0, 32, 0x1); - wait_on_value(BIT17|BIT16, 0, CM_L3_2_GPMC_CLKCTRL, LDELAY); - sr32(CM_L3INSTR_L3_3_CLKCTRL, 0, 32, 0x1); - wait_on_value(BIT17|BIT16, 0, CM_L3INSTR_L3_3_CLKCTRL, LDELAY); - sr32(CM_L3INSTR_L3_INSTR_CLKCTRL, 0, 32, 0x1); - wait_on_value(BIT17|BIT16, 0, CM_L3INSTR_L3_INSTR_CLKCTRL, LDELAY); - sr32(CM_L3INSTR_OCP_WP1_CLKCTRL, 0, 32, 0x1); - wait_on_value(BIT17|BIT16, 0, CM_L3INSTR_OCP_WP1_CLKCTRL, LDELAY); - - /* WDT clocks */ - sr32(CM_WKUP_WDT2_CLKCTRL, 0, 32, 0x2); - wait_on_value(BIT17|BIT16, 0, CM_WKUP_WDT2_CLKCTRL, LDELAY); - - /* Enable Camera clocks */ - sr32(CM_CAM_CLKSTCTRL, 0, 32, 0x3); - sr32(CM_CAM_ISS_CLKCTRL, 0, 32, 0x102); - //wait_on_value(BIT18|BIT17|BIT16, 0, CM_CAM_ISS_CLKCTRL, LDELAY); - sr32(CM_CAM_FDIF_CLKCTRL, 0, 32, 0x2); - //wait_on_value(BIT18|BIT17|BIT16, 0, CM_CAM_FDIF_CLKCTRL, LDELAY); - sr32(CM_CAM_CLKSTCTRL, 0, 32, 0x0); - - /* Enable DSS clocks */ - /* PM_DSS_PWRSTCTRL ON State and LogicState = 1 (Retention) */ - *(volatile int*)0x4A307100 = 0x7; //DSS_PRM - sr32(CM_DSS_CLKSTCTRL, 0, 32, 0x2); - sr32(CM_DSS_DSS_CLKCTRL, 0, 32, 0xf02); - //wait_on_value(BIT18|BIT17|BIT16, 0, CM_DSS_DSS_CLKCTRL, LDELAY); - sr32(CM_DSS_DEISS_CLKCTRL, 0, 32, 0x2); - //wait_on_value(BIT18|BIT17|BIT16, 0, CM_DSS_DEISS_CLKCTRL, LDELAY); - /* Check for DSS Clocks */ - while (((*(volatile int*)0x4A009100) & 0xF00) != 0xE00) - /* Set HW_AUTO transition mode */ - sr32(CM_DSS_CLKSTCTRL, 0, 32, 0x3); - - /* Enable SGX clocks */ - sr32(CM_SGX_CLKSTCTRL, 0, 32, 0x2); - sr32(CM_SGX_SGX_CLKCTRL, 0, 32, 0x2); - //wait_on_value(BIT18|BIT17|BIT16, 0, CM_SGX_SGX_CLKCTRL, LDELAY); - /* Check for SGX FCLK and ICLK */ - while ( (*(volatile int*)0x4A009200) != 0x302 ); - //sr32(CM_SGX_CLKSTCTRL, 0, 32, 0x0); - /* Enable hsi/unipro/usb clocks */ - sr32(CM_L3INIT_HSI_CLKCTRL, 0, 32, 0x1); - //wait_on_value(BIT18|BIT17|BIT16, 0, CM_L3INIT_HSI_CLKCTRL, LDELAY); - sr32(CM_L3INIT_UNIPRO1_CLKCTRL, 0, 32, 0x2); - //wait_on_value(BIT18|BIT17|BIT16, 0, CM_L3INIT_UNIPRO1_CLKCTRL, LDELAY); - sr32(CM_L3INIT_HSUSBHOST_CLKCTRL, 0, 32, 0x2); - //wait_on_value(BIT18|BIT17|BIT16, 0, CM_L3INIT_HSUSBHOST_CLKCTRL, LDELAY); - sr32(CM_L3INIT_HSUSBOTG_CLKCTRL, 0, 32, 0x1); - //wait_on_value(BIT18|BIT17|BIT16, 0, CM_L3INIT_HSUSBOTG_CLKCTRL, LDELAY); - sr32(CM_L3INIT_HSUSBTLL_CLKCTRL, 0, 32, 0x1); - //wait_on_value(BIT17|BIT16, 0, CM_L3INIT_HSUSBTLL_CLKCTRL, LDELAY); - sr32(CM_L3INIT_FSUSB_CLKCTRL, 0, 32, 0x2); - //wait_on_value(BIT18|BIT17|BIT16, 0, CM_L3INIT_FSUSB_CLKCTRL, LDELAY); - /* enable the 32K, 48M optional clocks and enable the module */ - sr32(CM_L3INIT_USBPHY_CLKCTRL, 0, 32, 0x301); - //wait_on_value(BIT17|BIT16, 0, CM_L3INIT_USBPHY_CLKCTRL, LDELAY); - return; -} - -/****************************************************************************** - * prcm_init() - inits clocks for PRCM as defined in clocks.h - * -- called from SRAM, or Flash (using temp SRAM stack). - *****************************************************************************/ -void prcm_init(void) -{ - u32 clk_index; - - /* Get the sysclk speed from cm_sys_clksel - * Set the CM_SYS_CLKSEL in case ROM code has not set - */ - __raw_writel(0x7,CM_SYS_CLKSEL); - clk_index = readl(CM_SYS_CLKSEL); - if (!clk_index) - return; /* Sys clk uninitialized */ - /* Core DPLL is locked using FREQ update method */ - /* configure_core_dpll(clk_index - 1); */ - - /* Configure all DPLL's at 100% OPP */ - configure_mpu_dpll(clk_index - 1); - configure_iva_dpll(clk_index - 1); - configure_per_dpll(clk_index - 1); - configure_abe_dpll(clk_index - 1); - configure_usb_dpll(clk_index - 1); - -#ifdef CONFIG_OMAP4_SDC - /* Enable all clocks */ - enable_all_clocks(); -#endif - - return; -} diff --git a/x-loader/board/omap4430panda/config.mk b/x-loader/board/omap4430panda/config.mk deleted file mode 100644 index 01173eb..0000000 --- a/x-loader/board/omap4430panda/config.mk +++ /dev/null @@ -1,21 +0,0 @@ -# -# (C) Copyright 2006-2009 -# Texas Instruments, <www.ti.com> -# -# SDP4430 board uses ARM-CortexA9 cpu -# see http://www.ti.com/ for more information on Texas Instruments -# -# Physical Address: -# 8000'0000 (bank0) -# A000/0000 (bank1) -# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000 -# (mem base + reserved) - -# For use with external or internal boots. -TEXT_BASE = 0x40304350 - - -# Handy to get symbols to debug ROM version. -#TEXT_BASE = 0x0 -#TEXT_BASE = 0x08000000 -#TEXT_BASE = 0x04000000 diff --git a/x-loader/board/omap4430panda/omap4430panda.c b/x-loader/board/omap4430panda/omap4430panda.c deleted file mode 100644 index 5695733..0000000 --- a/x-loader/board/omap4430panda/omap4430panda.c +++ /dev/null @@ -1,1235 +0,0 @@ -/* - * (C) Copyright 2004-2009 - * Texas Instruments, <www.ti.com> - * Richard Woodruff <r-woodruff2@ti.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#include <common.h> -#include <asm/arch/cpu.h> -#include <asm/io.h> -#include <asm/arch/bits.h> -#include <asm/arch/mux.h> -#include <asm/arch/sys_proto.h> -#include <asm/arch/sys_info.h> -#include <asm/arch/clocks.h> -#include <asm/arch/mem.h> -#include <i2c.h> -#if (CONFIG_COMMANDS & CFG_CMD_NAND) && defined(CFG_NAND_LEGACY) -#include <linux/mtd/nand_legacy.h> -#endif - -/* EMIF and DMM registers */ -#define EMIF1_BASE 0x4c000000 -#define EMIF2_BASE 0x4d000000 -#define DMM_BASE 0x4e000000 -/* EMIF */ -#define EMIF_MOD_ID_REV 0x0000 -#define EMIF_STATUS 0x0004 -#define EMIF_SDRAM_CONFIG 0x0008 -#define EMIF_LPDDR2_NVM_CONFIG 0x000C -#define EMIF_SDRAM_REF_CTRL 0x0010 -#define EMIF_SDRAM_REF_CTRL_SHDW 0x0014 -#define EMIF_SDRAM_TIM_1 0x0018 -#define EMIF_SDRAM_TIM_1_SHDW 0x001C -#define EMIF_SDRAM_TIM_2 0x0020 -#define EMIF_SDRAM_TIM_2_SHDW 0x0024 -#define EMIF_SDRAM_TIM_3 0x0028 -#define EMIF_SDRAM_TIM_3_SHDW 0x002C -#define EMIF_LPDDR2_NVM_TIM 0x0030 -#define EMIF_LPDDR2_NVM_TIM_SHDW 0x0034 -#define EMIF_PWR_MGMT_CTRL 0x0038 -#define EMIF_PWR_MGMT_CTRL_SHDW 0x003C -#define EMIF_LPDDR2_MODE_REG_DATA 0x0040 -#define EMIF_LPDDR2_MODE_REG_CFG 0x0050 -#define EMIF_L3_CONFIG 0x0054 -#define EMIF_L3_CFG_VAL_1 0x0058 -#define EMIF_L3_CFG_VAL_2 0x005C -#define IODFT_TLGC 0x0060 -#define EMIF_PERF_CNT_1 0x0080 -#define EMIF_PERF_CNT_2 0x0084 -#define EMIF_PERF_CNT_CFG 0x0088 -#define EMIF_PERF_CNT_SEL 0x008C -#define EMIF_PERF_CNT_TIM 0x0090 -#define EMIF_READ_IDLE_CTRL 0x0098 -#define EMIF_READ_IDLE_CTRL_SHDW 0x009c -#define EMIF_ZQ_CONFIG 0x00C8 -#define EMIF_DDR_PHY_CTRL_1 0x00E4 -#define EMIF_DDR_PHY_CTRL_1_SHDW 0x00E8 -#define EMIF_DDR_PHY_CTRL_2 0x00EC - -#define DMM_LISA_MAP_0 0x0040 -#define DMM_LISA_MAP_1 0x0044 -#define DMM_LISA_MAP_2 0x0048 -#define DMM_LISA_MAP_3 0x004C - -#define MR0_ADDR 0 -#define MR1_ADDR 1 -#define MR2_ADDR 2 -#define MR4_ADDR 4 -#define MR10_ADDR 10 -#define MR16_ADDR 16 -#define REF_EN 0x40000000 -/* defines for MR1 */ -#define MR1_BL4 2 -#define MR1_BL8 3 -#define MR1_BL16 4 - -#define MR1_BT_SEQ 0 -#define BT_INT 1 - -#define MR1_WC 0 -#define MR1_NWC 1 - -#define MR1_NWR3 1 -#define MR1_NWR4 2 -#define MR1_NWR5 3 -#define MR1_NWR6 4 -#define MR1_NWR7 5 -#define MR1_NWR8 6 - -#define MR1_VALUE (MR1_NWR3 << 5) | (MR1_WC << 4) | (MR1_BT_SEQ << 3) \ - | (MR1_BL8 << 0) - -/* defines for MR2 */ -#define MR2_RL3_WL1 1 -#define MR2_RL4_WL2 2 -#define MR2_RL5_WL2 3 -#define MR2_RL6_WL3 4 - -/* defines for MR10 */ -#define MR10_ZQINIT 0xFF -#define MR10_ZQRESET 0xC3 -#define MR10_ZQCL 0xAB -#define MR10_ZQCS 0x56 - - -/* TODO: FREQ update method is not working so shadow registers programming - * is just for same of completeness. This would be safer if auto - * trasnitions are working - */ -#define FREQ_UPDATE_EMIF -/* EMIF Needs to be configured@19.2 MHz and shadow registers - * should be programmed for new OPP. - */ -/* Elpida 2x2Gbit */ -#define SDRAM_CONFIG_INIT 0x80800EB1 -#define DDR_PHY_CTRL_1_INIT 0x849FFFF5 -#define READ_IDLE_CTRL 0x000501FF -#define PWR_MGMT_CTRL 0x4000000f -#define PWR_MGMT_CTRL_OPP100 0x4000000f -#define ZQ_CONFIG 0x500b3215 - -#define CS1_MR(mr) ((mr) | 0x80000000) -struct ddr_regs{ - u32 tim1; - u32 tim2; - u32 tim3; - u32 phy_ctrl_1; - u32 ref_ctrl; - u32 config_init; - u32 config_final; - u32 zq_config; - u8 mr1; - u8 mr2; -}; -const struct ddr_regs ddr_regs_380_mhz = { - .tim1 = 0x10cb061a, - .tim2 = 0x20350d52, - .tim3 = 0x00b1431f, - .phy_ctrl_1 = 0x849FF408, - .ref_ctrl = 0x000005ca, - .config_init = 0x80000eb1, - .config_final = 0x80001ab1, - .zq_config = 0x500b3215, - .mr1 = 0x83, - .mr2 = 0x4 -}; - -/* - * Unused timings - but we may need them later - * Keep them commented - */ -#if 0 -const struct ddr_regs ddr_regs_400_mhz = { - .tim1 = 0x10eb065a, - .tim2 = 0x20370dd2, - .tim3 = 0x00b1c33f, - .phy_ctrl_1 = 0x849FF408, - .ref_ctrl = 0x00000618, - .config_init = 0x80000eb1, - .config_final = 0x80001ab1, - .zq_config = 0x500b3215, - .mr1 = 0x83, - .mr2 = 0x4 -}; - -const struct ddr_regs ddr_regs_200_mhz = { - .tim1 = 0x08648309, - .tim2 = 0x101b06ca, - .tim3 = 0x0048a19f, - .phy_ctrl_1 = 0x849FF405, - .ref_ctrl = 0x0000030c, - .config_init = 0x80000eb1, - .config_final = 0x80000eb1, - .zq_config = 0x500b3215, - .mr1 = 0x23, - .mr2 = 0x1 -}; -#endif - -const struct ddr_regs ddr_regs_200_mhz_2cs = { - .tim1 = 0x08648309, - .tim2 = 0x101b06ca, - .tim3 = 0x0048a19f, - .phy_ctrl_1 = 0x849FF405, - .ref_ctrl = 0x0000030c, - .config_init = 0x80000eb9, - .config_final = 0x80000eb9, - .zq_config = 0xD00b3215, - .mr1 = 0x23, - .mr2 = 0x1 -}; - -const struct ddr_regs ddr_regs_400_mhz_2cs = { - /* tRRD changed from 10ns to 12.5ns because of the tFAW requirement*/ - .tim1 = 0x10eb0662, - .tim2 = 0x20370dd2, - .tim3 = 0x00b1c33f, - .phy_ctrl_1 = 0x849FF408, - .ref_ctrl = 0x00000618, - .config_init = 0x80000eb9, - .config_final = 0x80001ab9, - .zq_config = 0xD00b3215, - .mr1 = 0x83, - .mr2 = 0x4 -}; - -/******************************************************* - * Routine: delay - * Description: spinning delay to use before udelay works - ******************************************************/ -static inline void delay(unsigned long loops) -{ - __asm__ volatile ("1:\n" "subs %0, %1, #1\n" - "bne 1b" : "=r" (loops) : "0"(loops)); -} - - -void big_delay(unsigned int count) -{ - int i; - for (i=0; i<count; i++) - delay(1); -} - -/* TODO: FREQ update method is not working so shadow registers programming - * is just for same of completeness. This would be safer if auto - * trasnitions are working - */ -static int emif_config(unsigned int base) -{ - unsigned int reg_value, rev; - const struct ddr_regs *ddr_regs; - rev = omap_revision(); - - if(rev == OMAP4430_ES1_0) - ddr_regs = &ddr_regs_380_mhz; - else if (rev == OMAP4430_ES2_0) - ddr_regs = &ddr_regs_200_mhz_2cs; - else if (rev == OMAP4430_ES2_1) - ddr_regs = &ddr_regs_400_mhz_2cs; - /* - * set SDRAM CONFIG register - * EMIF_SDRAM_CONFIG[31:29] REG_SDRAM_TYPE = 4 for LPDDR2-S4 - * EMIF_SDRAM_CONFIG[28:27] REG_IBANK_POS = 0 - * EMIF_SDRAM_CONFIG[13:10] REG_CL = 3 - * EMIF_SDRAM_CONFIG[6:4] REG_IBANK = 3 - 8 banks - * EMIF_SDRAM_CONFIG[3] REG_EBANK = 0 - CS0 - * EMIF_SDRAM_CONFIG[2:0] REG_PAGESIZE = 2 - 512- 9 column - * JDEC specs - S4-2Gb --8 banks -- R0-R13, C0-c8 - */ - *(volatile int*)(base + EMIF_LPDDR2_NVM_CONFIG) &= 0xBFFFFFFF; - *(volatile int*)(base + EMIF_SDRAM_CONFIG) = ddr_regs->config_init; - - /* PHY control values */ - *(volatile int*)(base + EMIF_DDR_PHY_CTRL_1) = DDR_PHY_CTRL_1_INIT; - *(volatile int*)(base + EMIF_DDR_PHY_CTRL_1_SHDW)= ddr_regs->phy_ctrl_1; - - /* - * EMIF_READ_IDLE_CTRL - */ - *(volatile int*)(base + EMIF_READ_IDLE_CTRL) = READ_IDLE_CTRL; - *(volatile int*)(base + EMIF_READ_IDLE_CTRL_SHDW) = READ_IDLE_CTRL; - - /* - * EMIF_SDRAM_TIM_1 - */ - *(volatile int*)(base + EMIF_SDRAM_TIM_1) = ddr_regs->tim1; - *(volatile int*)(base + EMIF_SDRAM_TIM_1_SHDW) = ddr_regs->tim1; - - /* - * EMIF_SDRAM_TIM_2 - */ - *(volatile int*)(base + EMIF_SDRAM_TIM_2) = ddr_regs->tim2; - *(volatile int*)(base + EMIF_SDRAM_TIM_2_SHDW) = ddr_regs->tim2; - - /* - * EMIF_SDRAM_TIM_3 - */ - *(volatile int*)(base + EMIF_SDRAM_TIM_3) = ddr_regs->tim3; - *(volatile int*)(base + EMIF_SDRAM_TIM_3_SHDW) = ddr_regs->tim3; - - *(volatile int*)(base + EMIF_ZQ_CONFIG) = ddr_regs->zq_config; - /* - * EMIF_PWR_MGMT_CTRL - */ - //*(volatile int*)(base + EMIF_PWR_MGMT_CTRL) = PWR_MGMT_CTRL; - //*(volatile int*)(base + EMIF_PWR_MGMT_CTRL_SHDW) = PWR_MGMT_CTRL_OPP100; - /* - * poll MR0 register (DAI bit) - * REG_CS[31] = 0 -- Mode register command to CS0 - * REG_REFRESH_EN[30] = 1 -- Refresh enable after MRW - * REG_ADDRESS[7:0] = 00 -- Refresh enable after MRW - */ - - *(volatile int*)(base + EMIF_LPDDR2_MODE_REG_CFG) = MR0_ADDR; - do { - reg_value = *(volatile int*)(base + EMIF_LPDDR2_MODE_REG_DATA); - } while ((reg_value & 0x1) != 0); - - *(volatile int*)(base + EMIF_LPDDR2_MODE_REG_CFG) = CS1_MR(MR0_ADDR); - do { - reg_value = *(volatile int*)(base + EMIF_LPDDR2_MODE_REG_DATA); - } while ((reg_value & 0x1) != 0); - - - /* set MR10 register */ - *(volatile int*)(base + EMIF_LPDDR2_MODE_REG_CFG)= MR10_ADDR; - *(volatile int*)(base + EMIF_LPDDR2_MODE_REG_DATA) = MR10_ZQINIT; - *(volatile int*)(base + EMIF_LPDDR2_MODE_REG_CFG) = CS1_MR(MR10_ADDR); - *(volatile int*)(base + EMIF_LPDDR2_MODE_REG_DATA) = MR10_ZQINIT; - - /* wait for tZQINIT=1us */ - delay(10); - - /* set MR1 register */ - *(volatile int*)(base + EMIF_LPDDR2_MODE_REG_CFG)= MR1_ADDR; - *(volatile int*)(base + EMIF_LPDDR2_MODE_REG_DATA) = ddr_regs->mr1; - *(volatile int*)(base + EMIF_LPDDR2_MODE_REG_CFG) = CS1_MR(MR1_ADDR); - *(volatile int*)(base + EMIF_LPDDR2_MODE_REG_DATA) = ddr_regs->mr1; - - - /* set MR2 register RL=6 for OPP100 */ - *(volatile int*)(base + EMIF_LPDDR2_MODE_REG_CFG)= MR2_ADDR; - *(volatile int*)(base + EMIF_LPDDR2_MODE_REG_DATA) = ddr_regs->mr2; - *(volatile int*)(base + EMIF_LPDDR2_MODE_REG_CFG) = CS1_MR(MR2_ADDR); - *(volatile int*)(base + EMIF_LPDDR2_MODE_REG_DATA) = ddr_regs->mr2; - - /* Set SDRAM CONFIG register again here with final RL-WL value */ - *(volatile int*)(base + EMIF_SDRAM_CONFIG) = ddr_regs->config_final; - *(volatile int*)(base + EMIF_DDR_PHY_CTRL_1) = ddr_regs->phy_ctrl_1; - - /* - * EMIF_SDRAM_REF_CTRL - * refresh rate = DDR_CLK / reg_refresh_rate - * 3.9 uS = (400MHz) / reg_refresh_rate - */ - *(volatile int*)(base + EMIF_SDRAM_REF_CTRL) = ddr_regs->ref_ctrl; - *(volatile int*)(base + EMIF_SDRAM_REF_CTRL_SHDW) = ddr_regs->ref_ctrl; - - /* set MR16 register */ - *(volatile int*)(base + EMIF_LPDDR2_MODE_REG_CFG)= MR16_ADDR | REF_EN; - *(volatile int*)(base + EMIF_LPDDR2_MODE_REG_DATA) = 0; - *(volatile int*)(base + EMIF_LPDDR2_MODE_REG_CFG) = - CS1_MR(MR16_ADDR | REF_EN); - *(volatile int*)(base + EMIF_LPDDR2_MODE_REG_DATA) = 0; - /* LPDDR2 init complete */ - -} -/***************************************** - * Routine: ddr_init - * Description: Configure DDR - * EMIF1 -- CS0 -- DDR1 (256 MB) - * EMIF2 -- CS0 -- DDR2 (256 MB) - *****************************************/ -static void ddr_init(void) -{ - unsigned int base_addr, rev; - rev = omap_revision(); - - if (rev == OMAP4430_ES1_0) - { - /* Configurte the Control Module DDRIO device */ - __raw_writel(0x1c1c1c1c, 0x4A100638); - __raw_writel(0x1c1c1c1c, 0x4A10063c); - __raw_writel(0x1c1c1c1c, 0x4A100640); - __raw_writel(0x1c1c1c1c, 0x4A100648); - __raw_writel(0x1c1c1c1c, 0x4A10064c); - __raw_writel(0x1c1c1c1c, 0x4A100650); - /* LPDDR2IO set to NMOS PTV */ - __raw_writel(0x00ffc000, 0x4A100704); - } else if (rev == OMAP4430_ES2_0) { - __raw_writel(0x9e9e9e9e, 0x4A100638); - __raw_writel(0x9e9e9e9e, 0x4A10063c); - __raw_writel(0x9e9e9e9e, 0x4A100640); - __raw_writel(0x9e9e9e9e, 0x4A100648); - __raw_writel(0x9e9e9e9e, 0x4A10064c); - __raw_writel(0x9e9e9e9e, 0x4A100650); - /* LPDDR2IO set to NMOS PTV */ - __raw_writel(0x00ffc000, 0x4A100704); - } - - /* - * DMM Configuration - */ - - /* Both EMIFs 128 byte interleaved*/ - if (rev == OMAP4430_ES1_0) - *(volatile int*)(DMM_BASE + DMM_LISA_MAP_0) = 0x80540300; - else - *(volatile int*)(DMM_BASE + DMM_LISA_MAP_0) = 0x80640300; - - /* EMIF2 only at 0x90000000 */ - //*(volatile int*)(DMM_BASE + DMM_LISA_MAP_1) = 0x90400200; - - *(volatile int*)(DMM_BASE + DMM_LISA_MAP_2) = 0x00000000; - *(volatile int*)(DMM_BASE + DMM_LISA_MAP_3) = 0xFF020100; - - /* DDR needs to be initialised @ 19.2 MHz - * So put core DPLL in bypass mode - * Configure the Core DPLL but don't lock it - */ - configure_core_dpll_no_lock(); - - /* No IDLE: BUG in SDC */ - //sr32(CM_MEMIF_CLKSTCTRL, 0, 32, 0x2); - //while(((*(volatile int*)CM_MEMIF_CLKSTCTRL) & 0x700) != 0x700); - *(volatile int*)(EMIF1_BASE + EMIF_PWR_MGMT_CTRL) = 0x0; - *(volatile int*)(EMIF2_BASE + EMIF_PWR_MGMT_CTRL) = 0x0; - - base_addr = EMIF1_BASE; - emif_config(base_addr); - - /* Configure EMIF24D */ - base_addr = EMIF2_BASE; - emif_config(base_addr); - /* Lock Core using shadow CM_SHADOW_FREQ_CONFIG1 */ - lock_core_dpll_shadow(); - /* TODO: SDC needs few hacks to get DDR freq update working */ - - /* Set DLL_OVERRIDE = 0 */ - *(volatile int*)CM_DLL_CTRL = 0x0; - - delay(200); - - /* Check for DDR PHY ready for EMIF1 & EMIF2 */ - while((((*(volatile int*)(EMIF1_BASE + EMIF_STATUS))&(0x04)) != 0x04) \ - || (((*(volatile int*)(EMIF2_BASE + EMIF_STATUS))&(0x04)) != 0x04)); - - /* Reprogram the DDR PYHY Control register */ - /* PHY control values */ - - sr32(CM_MEMIF_EMIF_1_CLKCTRL, 0, 32, 0x1); - sr32(CM_MEMIF_EMIF_2_CLKCTRL, 0, 32, 0x1); - - /* Put the Core Subsystem PD to ON State */ - - /* No IDLE: BUG in SDC */ - //sr32(CM_MEMIF_CLKSTCTRL, 0, 32, 0x2); - //while(((*(volatile int*)CM_MEMIF_CLKSTCTRL) & 0x700) != 0x700); - *(volatile int*)(EMIF1_BASE + EMIF_PWR_MGMT_CTRL) = 0x80000000; - *(volatile int*)(EMIF2_BASE + EMIF_PWR_MGMT_CTRL) = 0x80000000; - - /* SYSTEM BUG: - * In n a specific situation, the OCP interface between the DMM and - * EMIF may hang. - * 1. A TILER port is used to perform 2D burst writes of - * width 1 and height 8 - * 2. ELLAn port is used to perform reads - * 3. All accesses are routed to the same EMIF controller - * - * Work around to avoid this issue REG_SYS_THRESH_MAX value should - * be kept higher than default 0x7. As per recommondation 0x0A will - * be used for better performance with REG_LL_THRESH_MAX = 0x00 - */ - if (rev == OMAP4430_ES1_0) { - *(volatile int*)(EMIF1_BASE + EMIF_L3_CONFIG) = 0x0A0000FF; - *(volatile int*)(EMIF2_BASE + EMIF_L3_CONFIG) = 0x0A0000FF; - } - - /* - * DMM : DMM_LISA_MAP_0(Section_0) - * [31:24] SYS_ADDR 0x80 - * [22:20] SYS_SIZE 0x7 - 2Gb - * [19:18] SDRC_INTLDMM 0x1 - 128 byte - * [17:16] SDRC_ADDRSPC 0x0 - * [9:8] SDRC_MAP 0x3 - * [7:0] SDRC_ADDR 0X0 - */ - reset_phy(EMIF1_BASE); - reset_phy(EMIF2_BASE); - - *((volatile int *)0x80000000) = 0; - *((volatile int *)0x80000080) = 0; - //*((volatile int *)0x90000000) = 0; -} -/***************************************** - * Routine: board_init - * Description: Early hardware init. - *****************************************/ -int board_init(void) -{ - return 0; -} - -/************************************************************* - * Routine: get_mem_type(void) - returns the kind of memory connected - * to GPMC that we are trying to boot form. Uses SYS BOOT settings. - *************************************************************/ -u32 get_mem_type(void) -{ - /* no nand, so return GPMC_NONE */ - return GPMC_NONE; -} - -/***************************************** - * Routine: secure_unlock - * Description: Setup security registers for access - * (GP Device only) - *****************************************/ -void secure_unlock_mem(void) -{ - /* Permission values for registers -Full fledged permissions to all */ - #define UNLOCK_1 0xFFFFFFFF - #define UNLOCK_2 0x00000000 - #define UNLOCK_3 0x0000FFFF - - /* Protection Module Register Target APE (PM_RT)*/ - __raw_writel(UNLOCK_1, RT_REQ_INFO_PERMISSION_1); - __raw_writel(UNLOCK_1, RT_READ_PERMISSION_0); - __raw_writel(UNLOCK_1, RT_WRITE_PERMISSION_0); - __raw_writel(UNLOCK_2, RT_ADDR_MATCH_1); - - __raw_writel(UNLOCK_3, GPMC_REQ_INFO_PERMISSION_0); - __raw_writel(UNLOCK_3, GPMC_READ_PERMISSION_0); - __raw_writel(UNLOCK_3, GPMC_WRITE_PERMISSION_0); - - __raw_writel(UNLOCK_3, OCM_REQ_INFO_PERMISSION_0); - __raw_writel(UNLOCK_3, OCM_READ_PERMISSION_0); - __raw_writel(UNLOCK_3, OCM_WRITE_PERMISSION_0); - __raw_writel(UNLOCK_2, OCM_ADDR_MATCH_2); - - /* IVA Changes */ - __raw_writel(UNLOCK_3, IVA2_REQ_INFO_PERMISSION_0); - __raw_writel(UNLOCK_3, IVA2_READ_PERMISSION_0); - __raw_writel(UNLOCK_3, IVA2_WRITE_PERMISSION_0); - - __raw_writel(UNLOCK_1, SMS_RG_ATT0); /* SDRC region 0 public */ -} - -/********************************************************** - * Routine: try_unlock_sram() - * Description: If chip is GP/EMU(special) type, unlock the SRAM for - * general use. - ***********************************************************/ -void try_unlock_memory(void) -{ - int mode; - - /* if GP device unlock device SRAM for general use */ - /* secure code breaks for Secure/Emulation device - HS/E/T*/ - return; -} - - -#if defined(CONFIG_MPU_600) || defined(CONFIG_MPU_1000) -static scale_vcores(void) -{ - unsigned int rev = omap_revision(); - /* For VC bypass only VCOREx_CGF_FORCE is necessary and - * VCOREx_CFG_VOLTAGE changes can be discarded - */ - /* PRM_VC_CFG_I2C_MODE */ - *(volatile int*)(0x4A307BA8) = 0x0; - /* PRM_VC_CFG_I2C_CLK */ - *(volatile int*)(0x4A307BAC) = 0x6026; - - /* set VCORE1 force VSEL */ - /* PRM_VC_VAL_BYPASS) */ - if(rev == OMAP4430_ES1_0) - *(volatile int*)(0x4A307BA0) = 0x3B5512; - else - *(volatile int*)(0x4A307BA0) = 0x3A5512; - - *(volatile int*)(0x4A307BA0) |= 0x1000000; - while((*(volatile int*)(0x4A307BA0)) & 0x1000000); - - /* PRM_IRQSTATUS_MPU */ - *(volatile int*)(0x4A306010) = *(volatile int*)(0x4A306010); - - - /* FIXME: set VCORE2 force VSEL, Check the reset value */ - /* PRM_VC_VAL_BYPASS) */ - if(rev == OMAP4430_ES1_0) - *(volatile int*)(0x4A307BA0) = 0x315B12; - else - *(volatile int*)(0x4A307BA0) = 0x295B12; - *(volatile int*)(0x4A307BA0) |= 0x1000000; - while((*(volatile int*)(0x4A307BA0)) & 0x1000000); - - /* PRM_IRQSTATUS_MPU */ - *(volatile int*)(0x4A306010) = *(volatile int*)(0x4A306010); - - /*/set VCORE3 force VSEL */ - /* PRM_VC_VAL_BYPASS */ - if(rev == OMAP4430_ES1_0) - *(volatile int*)(0x4A307BA0) = 0x316112; - else if (rev == OMAP4430_ES2_0) - *(volatile int*)(0x4A307BA0) = 0x296112; - else if (rev == OMAP4430_ES2_1) - *(volatile int*)(0x4A307BA0) = 0x2A6112; - *(volatile int*)(0x4A307BA0) |= 0x1000000; - while((*(volatile int*)(0x4A307BA0)) & 0x1000000); - - /* PRM_IRQSTATUS_MPU */ - *(volatile int*)(0x4A306010) = *(volatile int*)(0x4A306010); - -} -#endif - -/********************************************************** - * Routine: s_init - * Description: Does early system init of muxing and clocks. - * - Called path is with SRAM stack. - **********************************************************/ - -void s_init(void) -{ - unsigned int rev = omap_revision(); - - set_muxconf_regs(); - delay(100); - - /* Writing to AuxCR in U-boot using SMI for GP/EMU DEV */ - /* Currently SMI in Kernel on ES2 devices seems to have an isse - * Once that is resolved, we can postpone this config to kernel - */ - //setup_auxcr(get_device_type(), external_boot); - - ddr_init(); - -/* Set VCORE1 = 1.3 V, VCORE2 = VCORE3 = 1.21V */ -#if defined(CONFIG_MPU_600) || defined(CONFIG_MPU_1000) - scale_vcores(); -#endif - prcm_init(); - - if(rev != OMAP4430_ES1_0) { - if (__raw_readl(0x4805D138) & (1<<22)) { - sr32(0x4A30a31C, 8, 1, 0x1); /* enable software ioreq */ - sr32(0x4A30a31C, 1, 2, 0x0); /* set for sys_clk (38.4MHz) */ - sr32(0x4A30a31C, 16, 4, 0x1); /* set divisor to 2 */ - sr32(0x4A30a110, 0, 1, 0x1); /* set the clock source to active */ - sr32(0x4A30a110, 2, 2, 0x3); /* enable clocks */ - } - else { - sr32(0x4A30a314, 8, 1, 0x1); /* enable software ioreq */ - sr32(0x4A30a314, 1, 2, 0x2); /* set for PER_DPLL */ - sr32(0x4A30a314, 16, 4, 0xf); /* set divisor to 16 */ - sr32(0x4A30a110, 0, 1, 0x1); /* set the clock source to active */ - sr32(0x4A30a110, 2, 2, 0x3); /* enable clocks */ - } - } - -} - -/******************************************************* - * Routine: misc_init_r - * Description: Init ethernet (done here so udelay works) - ********************************************************/ -int misc_init_r(void) -{ - return 0; -} - -/****************************************************** - * Routine: wait_for_command_complete - * Description: Wait for posting to finish on watchdog - ******************************************************/ -void wait_for_command_complete(unsigned int wd_base) -{ - int pending = 1; - do { - pending = __raw_readl(wd_base + WWPS); - } while (pending); -} - -/******************************************************************* - * Routine:ether_init - * Description: take the Ethernet controller out of reset and wait - * for the EEPROM load to complete. - ******************************************************************/ - -/********************************************** - * Routine: dram_init - * Description: sets uboots idea of sdram size - **********************************************/ -int dram_init(void) -{ - return 0; -} - -#define OMAP44XX_WKUP_CTRL_BASE 0x4A31E000 -#if 1 -#define M0_SAFE M0 -#define M1_SAFE M1 -#define M2_SAFE M2 -#define M4_SAFE M4 -#define M7_SAFE M7 -#define M3_SAFE M3 -#define M5_SAFE M5 -#define M6_SAFE M6 -#else -#define M0_SAFE M7 -#define M1_SAFE M7 -#define M2_SAFE M7 -#define M4_SAFE M7 -#define M7_SAFE M7 -#define M3_SAFE M7 -#define M5_SAFE M7 -#define M6_SAFE M7 -#endif -#define MV(OFFSET, VALUE)\ - __raw_writew((VALUE), OMAP44XX_CTRL_BASE + (OFFSET)); -#define MV1(OFFSET, VALUE)\ - __raw_writew((VALUE), OMAP44XX_WKUP_CTRL_BASE + (OFFSET)); - -#define CP(x) (CONTROL_PADCONF_##x) -#define WK(x) (CONTROL_WKUP_##x) -/* - * IEN - Input Enable - * IDIS - Input Disable - * PTD - Pull type Down - * PTU - Pull type Up - * DIS - Pull type selection is inactive - * EN - Pull type selection is active - * M0 - Mode 0 - * The commented string gives the final mux configuration for that pin - */ - -#define MUX_DEFAULT_OMAP4() \ - MV(CP(GPMC_AD0) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* sdmmc2_dat0 */ \ - MV(CP(GPMC_AD1) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* sdmmc2_dat1 */ \ - MV(CP(GPMC_AD2) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* sdmmc2_dat2 */ \ - MV(CP(GPMC_AD3) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* sdmmc2_dat3 */ \ - MV(CP(GPMC_AD4) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* sdmmc2_dat4 */ \ - MV(CP(GPMC_AD5) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* sdmmc2_dat5 */ \ - MV(CP(GPMC_AD6) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* sdmmc2_dat6 */ \ - MV(CP(GPMC_AD7) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* sdmmc2_dat7 */ \ - MV(CP(GPMC_AD8) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M3)) /* gpio_32 */ \ - MV(CP(GPMC_AD9) , ( PTU | IEN | M3)) /* gpio_33 */ \ - MV(CP(GPMC_AD10) , ( PTU | IEN | M3)) /* gpio_34 */ \ - MV(CP(GPMC_AD11) , ( PTU | IEN | M3)) /* gpio_35 */ \ - MV(CP(GPMC_AD12) , ( PTU | IEN | M3)) /* gpio_36 */ \ - MV(CP(GPMC_AD13) , ( PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)) /* gpio_37 */ \ - MV(CP(GPMC_AD14) , ( PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)) /* gpio_38 */ \ - MV(CP(GPMC_AD15) , ( PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)) /* gpio_39 */ \ - MV(CP(GPMC_A16) , ( M3)) /* gpio_40 */ \ - MV(CP(GPMC_A17) , ( PTD | M3)) /* gpio_41 */ \ - MV(CP(GPMC_A18) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_row6 */ \ - MV(CP(GPMC_A19) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_row7 */ \ - MV(CP(GPMC_A20) , ( IEN | M3)) /* gpio_44 */ \ - MV(CP(GPMC_A21) , ( M3)) /* gpio_45 */ \ - MV(CP(GPMC_A22) , ( M3)) /* gpio_46 */ \ - MV(CP(GPMC_A23) , ( OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_col7 */ \ - MV(CP(GPMC_A24) , ( PTD | M3)) /* gpio_48 */ \ - MV(CP(GPMC_A25) , ( PTD | M3)) /* gpio_49 */ \ - MV(CP(GPMC_NCS0) , ( M3)) /* gpio_50 */ \ - MV(CP(GPMC_NCS1) , ( IEN | M3)) /* gpio_51 */ \ - MV(CP(GPMC_NCS2) , ( IEN | M3)) /* gpio_52 */ \ - MV(CP(GPMC_NCS3) , ( IEN | M3)) /* gpio_53 */ \ - MV(CP(GPMC_NWP) , ( M3)) /* gpio_54 */ \ - MV(CP(GPMC_CLK) , ( PTD | M3)) /* gpio_55 */ \ - MV(CP(GPMC_NADV_ALE) , ( M3)) /* gpio_56 */ \ - MV(CP(GPMC_NOE) , ( PTU | IEN | OFF_EN | OFF_OUT_PTD | M1)) /* sdmmc2_clk */ \ - MV(CP(GPMC_NWE) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* sdmmc2_cmd */ \ - MV(CP(GPMC_NBE0_CLE) , ( M3)) /* gpio_59 */ \ - MV(CP(GPMC_NBE1) , ( PTD | M3)) /* gpio_60 */ \ - MV(CP(GPMC_WAIT0) , ( PTU | IEN | M3)) /* gpio_61 */ \ - MV(CP(GPMC_WAIT1), (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)) /* gpio_62 */ \ - MV(CP(C2C_DATA11) , ( PTD | M3)) /* gpio_100 */ \ - MV(CP(C2C_DATA12) , ( PTD | IEN | M3)) /* gpio_101 */ \ - MV(CP(C2C_DATA13) , ( PTD | M3)) /* gpio_102 */ \ - MV(CP(C2C_DATA14) , ( M1)) /* dsi2_te0 */ \ - MV(CP(C2C_DATA15) , ( PTD | M3)) /* gpio_104 */ \ - MV(CP(HDMI_HPD) , ( M0)) /* hdmi_hpd */ \ - MV(CP(HDMI_CEC) , ( M0)) /* hdmi_cec */ \ - MV(CP(HDMI_DDC_SCL) , ( PTU | M0)) /* hdmi_ddc_scl */ \ - MV(CP(HDMI_DDC_SDA) , ( PTU | IEN | M0)) /* hdmi_ddc_sda */ \ - MV(CP(CSI21_DX0) , ( IEN | M0)) /* csi21_dx0 */ \ - MV(CP(CSI21_DY0) , ( IEN | M0)) /* csi21_dy0 */ \ - MV(CP(CSI21_DX1) , ( IEN | M0)) /* csi21_dx1 */ \ - MV(CP(CSI21_DY1) , ( IEN | M0)) /* csi21_dy1 */ \ - MV(CP(CSI21_DX2) , ( IEN | M0)) /* csi21_dx2 */ \ - MV(CP(CSI21_DY2) , ( IEN | M0)) /* csi21_dy2 */ \ - MV(CP(CSI21_DX3) , ( PTD | M7)) /* csi21_dx3 */ \ - MV(CP(CSI21_DY3) , ( PTD | M7)) /* csi21_dy3 */ \ - MV(CP(CSI21_DX4) , ( PTD | OFF_EN | OFF_PD | OFF_IN | M7)) /* csi21_dx4 */ \ - MV(CP(CSI21_DY4) , ( PTD | OFF_EN | OFF_PD | OFF_IN | M7)) /* csi21_dy4 */ \ - MV(CP(CSI22_DX0) , ( IEN | M0)) /* csi22_dx0 */ \ - MV(CP(CSI22_DY0) , ( IEN | M0)) /* csi22_dy0 */ \ - MV(CP(CSI22_DX1) , ( IEN | M0)) /* csi22_dx1 */ \ - MV(CP(CSI22_DY1) , ( IEN | M0)) /* csi22_dy1 */ \ - MV(CP(CAM_SHUTTER) , ( OFF_EN | OFF_PD | OFF_OUT_PTD | M0)) /* cam_shutter */ \ - MV(CP(CAM_STROBE) , ( OFF_EN | OFF_PD | OFF_OUT_PTD | M0)) /* cam_strobe */ \ - MV(CP(CAM_GLOBALRESET) , ( PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)) /* gpio_83 */ \ - MV(CP(USBB1_ULPITLL_CLK) , ( PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4)) /* usbb1_ulpiphy_clk */ \ - MV(CP(USBB1_ULPITLL_STP) , ( OFF_EN | OFF_OUT_PTD | M4)) /* usbb1_ulpiphy_stp */ \ - MV(CP(USBB1_ULPITLL_DIR) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M4)) /* usbb1_ulpiphy_dir */ \ - MV(CP(USBB1_ULPITLL_NXT) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M4)) /* usbb1_ulpiphy_nxt */ \ - MV(CP(USBB1_ULPITLL_DAT0) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M4)) /* usbb1_ulpiphy_dat0 */ \ - MV(CP(USBB1_ULPITLL_DAT1) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M4)) /* usbb1_ulpiphy_dat1 */ \ - MV(CP(USBB1_ULPITLL_DAT2) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M4)) /* usbb1_ulpiphy_dat2 */ \ - MV(CP(USBB1_ULPITLL_DAT3) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M4)) /* usbb1_ulpiphy_dat3 */ \ - MV(CP(USBB1_ULPITLL_DAT4) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M4)) /* usbb1_ulpiphy_dat4 */ \ - MV(CP(USBB1_ULPITLL_DAT5) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M4)) /* usbb1_ulpiphy_dat5 */ \ - MV(CP(USBB1_ULPITLL_DAT6) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M4)) /* usbb1_ulpiphy_dat6 */ \ - MV(CP(USBB1_ULPITLL_DAT7) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M4)) /* usbb1_ulpiphy_dat7 */ \ - MV(CP(USBB1_HSIC_DATA) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* usbb1_hsic_data */ \ - MV(CP(USBB1_HSIC_STROBE) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* usbb1_hsic_strobe */ \ - MV(CP(USBC1_ICUSB_DP) , ( IEN | M0)) /* usbc1_icusb_dp */ \ - MV(CP(USBC1_ICUSB_DM) , ( IEN | M0)) /* usbc1_icusb_dm */ \ - MV(CP(SDMMC1_CLK) , ( PTU | OFF_EN | OFF_OUT_PTD | M0)) /* sdmmc1_clk */ \ - MV(CP(SDMMC1_CMD) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc1_cmd */ \ - MV(CP(SDMMC1_DAT0) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc1_dat0 */ \ - MV(CP(SDMMC1_DAT1) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc1_dat1 */ \ - MV(CP(SDMMC1_DAT2) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc1_dat2 */ \ - MV(CP(SDMMC1_DAT3) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc1_dat3 */ \ - MV(CP(SDMMC1_DAT4) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc1_dat4 */ \ - MV(CP(SDMMC1_DAT5) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc1_dat5 */ \ - MV(CP(SDMMC1_DAT6) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc1_dat6 */ \ - MV(CP(SDMMC1_DAT7) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc1_dat7 */ \ - MV(CP(ABE_MCBSP2_CLKX) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* abe_mcbsp2_clkx */ \ - MV(CP(ABE_MCBSP2_DR) , ( IEN | OFF_EN | OFF_OUT_PTD | M0)) /* abe_mcbsp2_dr */ \ - MV(CP(ABE_MCBSP2_DX) , ( OFF_EN | OFF_OUT_PTD | M0)) /* abe_mcbsp2_dx */ \ - MV(CP(ABE_MCBSP2_FSX) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* abe_mcbsp2_fsx */ \ - MV(CP(ABE_MCBSP1_CLKX) , ( IEN | M1)) /* abe_slimbus1_clock */ \ - MV(CP(ABE_MCBSP1_DR) , ( IEN | M1)) /* abe_slimbus1_data */ \ - MV(CP(ABE_MCBSP1_DX) , ( OFF_EN | OFF_OUT_PTD | M0)) /* abe_mcbsp1_dx */ \ - MV(CP(ABE_MCBSP1_FSX) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* abe_mcbsp1_fsx */ \ - MV(CP(ABE_PDM_UL_DATA) , ( PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* abe_pdm_ul_data */ \ - MV(CP(ABE_PDM_DL_DATA) , ( PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* abe_pdm_dl_data */ \ - MV(CP(ABE_PDM_FRAME) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* abe_pdm_frame */ \ - MV(CP(ABE_PDM_LB_CLK) , ( PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* abe_pdm_lb_clk */ \ - MV(CP(ABE_CLKS) , ( PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* abe_clks */ \ - MV(CP(ABE_DMIC_CLK1) , ( M0)) /* abe_dmic_clk1 */ \ - MV(CP(ABE_DMIC_DIN1) , ( IEN | M0)) /* abe_dmic_din1 */ \ - MV(CP(ABE_DMIC_DIN2) , ( IEN | M0)) /* abe_dmic_din2 */ \ - MV(CP(ABE_DMIC_DIN3) , ( IEN | M0)) /* abe_dmic_din3 */ \ - MV(CP(UART2_CTS) , ( PTU | IEN | M0)) /* uart2_cts */ \ - MV(CP(UART2_RTS) , ( M0)) /* uart2_rts */ \ - MV(CP(UART2_RX) , ( PTU | IEN | M0)) /* uart2_rx */ \ - MV(CP(UART2_TX) , ( M0)) /* uart2_tx */ \ - MV(CP(HDQ_SIO) , ( M3)) /* gpio_127 */ \ - MV(CP(I2C1_SCL) , ( PTU | IEN | M0)) /* i2c1_scl */ \ - MV(CP(I2C1_SDA) , ( PTU | IEN | M0)) /* i2c1_sda */ \ - MV(CP(I2C2_SCL) , ( PTU | IEN | M0)) /* i2c2_scl */ \ - MV(CP(I2C2_SDA) , ( PTU | IEN | M0)) /* i2c2_sda */ \ - MV(CP(I2C3_SCL) , ( PTU | IEN | M0)) /* i2c3_scl */ \ - MV(CP(I2C3_SDA) , ( PTU | IEN | M0)) /* i2c3_sda */ \ - MV(CP(I2C4_SCL) , ( PTU | IEN | M0)) /* i2c4_scl */ \ - MV(CP(I2C4_SDA) , ( PTU | IEN | M0)) /* i2c4_sda */ \ - MV(CP(MCSPI1_CLK) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* mcspi1_clk */ \ - MV(CP(MCSPI1_SOMI) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* mcspi1_somi */ \ - MV(CP(MCSPI1_SIMO) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* mcspi1_simo */ \ - MV(CP(MCSPI1_CS0) , ( PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* mcspi1_cs0 */ \ - MV(CP(MCSPI1_CS1) , ( PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M3)) /* mcspi1_cs1 */ \ - MV(CP(MCSPI1_CS2) , ( PTU | OFF_EN | OFF_OUT_PTU | M3)) /* gpio_139 */ \ - MV(CP(MCSPI1_CS3) , ( PTU | IEN | M3)) /* gpio_140 */ \ - MV(CP(UART3_CTS_RCTX) , ( PTU | IEN | M0)) /* uart3_tx */ \ - MV(CP(UART3_RTS_SD) , ( M0)) /* uart3_rts_sd */ \ - MV(CP(UART3_RX_IRRX) , ( IEN | M0)) /* uart3_rx */ \ - MV(CP(UART3_TX_IRTX) , ( M0)) /* uart3_tx */ \ - MV(CP(SDMMC5_CLK) , ( PTU | IEN | OFF_EN | OFF_OUT_PTD | M0)) /* sdmmc5_clk */ \ - MV(CP(SDMMC5_CMD) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc5_cmd */ \ - MV(CP(SDMMC5_DAT0) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc5_dat0 */ \ - MV(CP(SDMMC5_DAT1) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc5_dat1 */ \ - MV(CP(SDMMC5_DAT2) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc5_dat2 */ \ - MV(CP(SDMMC5_DAT3) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc5_dat3 */ \ - MV(CP(MCSPI4_CLK) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* mcspi4_clk */ \ - MV(CP(MCSPI4_SIMO) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* mcspi4_simo */ \ - MV(CP(MCSPI4_SOMI) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* mcspi4_somi */ \ - MV(CP(MCSPI4_CS0) , ( PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* mcspi4_cs0 */ \ - MV(CP(UART4_RX) , ( IEN | M0)) /* uart4_rx */ \ - MV(CP(UART4_TX) , ( M0)) /* uart4_tx */ \ - MV(CP(USBB2_ULPITLL_CLK) , ( IEN | M3)) /* gpio_157 */ \ - MV(CP(USBB2_ULPITLL_STP) , ( IEN | M5)) /* dispc2_data23 */ \ - MV(CP(USBB2_ULPITLL_DIR) , ( IEN | M5)) /* dispc2_data22 */ \ - MV(CP(USBB2_ULPITLL_NXT) , ( IEN | M5)) /* dispc2_data21 */ \ - MV(CP(USBB2_ULPITLL_DAT0) , ( IEN | M5)) /* dispc2_data20 */ \ - MV(CP(USBB2_ULPITLL_DAT1) , ( IEN | M5)) /* dispc2_data19 */ \ - MV(CP(USBB2_ULPITLL_DAT2) , ( IEN | M5)) /* dispc2_data18 */ \ - MV(CP(USBB2_ULPITLL_DAT3) , ( IEN | M5)) /* dispc2_data15 */ \ - MV(CP(USBB2_ULPITLL_DAT4) , ( IEN | M5)) /* dispc2_data14 */ \ - MV(CP(USBB2_ULPITLL_DAT5) , ( IEN | M5)) /* dispc2_data13 */ \ - MV(CP(USBB2_ULPITLL_DAT6) , ( IEN | M5)) /* dispc2_data12 */ \ - MV(CP(USBB2_ULPITLL_DAT7) , ( IEN | M5)) /* dispc2_data11 */ \ - MV(CP(USBB2_HSIC_DATA) , ( PTD | OFF_EN | OFF_OUT_PTU | M3)) /* gpio_169 */ \ - MV(CP(USBB2_HSIC_STROBE) , ( PTD | OFF_EN | OFF_OUT_PTU | M3)) /* gpio_170 */ \ - MV(CP(UNIPRO_TX0) , ( PTD | IEN | M3)) /* gpio_171 */ \ - MV(CP(UNIPRO_TY0) , ( OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_col1 */ \ - MV(CP(UNIPRO_TX1) , ( OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_col2 */ \ - MV(CP(UNIPRO_TY1) , ( OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_col3 */ \ - MV(CP(UNIPRO_TX2) , ( PTU | IEN | M3)) /* gpio_0 */ \ - MV(CP(UNIPRO_TY2) , ( PTU | IEN | M3)) /* gpio_1 */ \ - MV(CP(UNIPRO_RX0) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_row0 */ \ - MV(CP(UNIPRO_RY0) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_row1 */ \ - MV(CP(UNIPRO_RX1) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_row2 */ \ - MV(CP(UNIPRO_RY1) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_row3 */ \ - MV(CP(UNIPRO_RX2) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_row4 */ \ - MV(CP(UNIPRO_RY2) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_row5 */ \ - MV(CP(USBA0_OTG_CE) , ( PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M0)) /* usba0_otg_ce */ \ - MV(CP(USBA0_OTG_DP) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* usba0_otg_dp */ \ - MV(CP(USBA0_OTG_DM) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* usba0_otg_dm */ \ - MV(CP(FREF_CLK1_OUT) , ( M0)) /* fref_clk1_out */ \ - MV(CP(FREF_CLK2_OUT) , ( PTD | IEN | M3)) /* gpio_182 */ \ - MV(CP(SYS_NIRQ1) , ( PTU | IEN | M0)) /* sys_nirq1 */ \ - MV(CP(SYS_NIRQ2) , ( PTU | IEN | M0)) /* sys_nirq2 */ \ - MV(CP(SYS_BOOT0) , ( PTU | IEN | M3)) /* gpio_184 */ \ - MV(CP(SYS_BOOT1) , ( M3)) /* gpio_185 */ \ - MV(CP(SYS_BOOT2) , ( PTD | IEN | M3)) /* gpio_186 */ \ - MV(CP(SYS_BOOT3) , ( M3)) /* gpio_187 */ \ - MV(CP(SYS_BOOT4) , ( M3)) /* gpio_188 */ \ - MV(CP(SYS_BOOT5) , ( PTD | IEN | M3)) /* gpio_189 */ \ - MV(CP(DPM_EMU0) , ( IEN | M0)) /* dpm_emu0 */ \ - MV(CP(DPM_EMU1) , ( IEN | M0)) /* dpm_emu1 */ \ - MV(CP(DPM_EMU2) , ( IEN | M0)) /* dpm_emu2 */ \ - MV(CP(DPM_EMU3) , ( IEN | M5)) /* dispc2_data10 */ \ - MV(CP(DPM_EMU4) , ( IEN | M5)) /* dispc2_data9 */ \ - MV(CP(DPM_EMU5) , ( IEN | M5)) /* dispc2_data16 */ \ - MV(CP(DPM_EMU6) , ( IEN | M5)) /* dispc2_data17 */ \ - MV(CP(DPM_EMU7) , ( IEN | M5)) /* dispc2_hsync */ \ - MV(CP(DPM_EMU8) , ( IEN | M5)) /* dispc2_pclk */ \ - MV(CP(DPM_EMU9) , ( IEN | M5)) /* dispc2_vsync */ \ - MV(CP(DPM_EMU10) , ( IEN | M5)) /* dispc2_de */ \ - MV(CP(DPM_EMU11) , ( IEN | M5)) /* dispc2_data8 */ \ - MV(CP(DPM_EMU12) , ( IEN | M5)) /* dispc2_data7 */ \ - MV(CP(DPM_EMU13) , ( IEN | M5)) /* dispc2_data6 */ \ - MV(CP(DPM_EMU14) , ( IEN | M5)) /* dispc2_data5 */ \ - MV(CP(DPM_EMU15) , ( IEN | M5)) /* dispc2_data4 */ \ - MV(CP(DPM_EMU16) , ( M3)) /* gpio_27 */ \ - MV(CP(DPM_EMU17) , ( IEN | M5)) /* dispc2_data2 */ \ - MV(CP(DPM_EMU18) , ( IEN | M5)) /* dispc2_data1 */ \ - MV(CP(DPM_EMU19) , ( IEN | M5)) /* dispc2_data0 */ \ - MV1(WK(PAD0_SIM_IO) , ( IEN | M0)) /* sim_io */ \ - MV1(WK(PAD1_SIM_CLK) , ( M0)) /* sim_clk */ \ - MV1(WK(PAD0_SIM_RESET) , ( M0)) /* sim_reset */ \ - MV1(WK(PAD1_SIM_CD) , ( PTU | IEN | M0)) /* sim_cd */ \ - MV1(WK(PAD0_SIM_PWRCTRL) , ( M0)) /* sim_pwrctrl */ \ - MV1(WK(PAD1_SR_SCL) , ( PTU | IEN | M0)) /* sr_scl */ \ - MV1(WK(PAD0_SR_SDA) , ( PTU | IEN | M0)) /* sr_sda */ \ - MV1(WK(PAD1_FREF_XTAL_IN) , ( M0)) /* # */ \ - MV1(WK(PAD0_FREF_SLICER_IN) , ( M0)) /* fref_slicer_in */ \ - MV1(WK(PAD1_FREF_CLK_IOREQ) , ( M0)) /* fref_clk_ioreq */ \ - MV1(WK(PAD0_FREF_CLK0_OUT) , ( M2)) /* sys_drm_msecure */ \ - MV1(WK(PAD1_FREF_CLK3_REQ) , ( PTU | IEN | M0)) /* # */ \ - MV1(WK(PAD0_FREF_CLK3_OUT) , ( M0)) /* fref_clk3_out */ \ - MV1(WK(PAD1_FREF_CLK4_REQ) , ( PTU | IEN | M0)) /* # */ \ - MV1(WK(PAD0_FREF_CLK4_OUT) , ( M0)) /* # */ \ - MV1(WK(PAD1_SYS_32K) , ( IEN | M0)) /* sys_32k */ \ - MV1(WK(PAD0_SYS_NRESPWRON) , ( M0)) /* sys_nrespwron */ \ - MV1(WK(PAD1_SYS_NRESWARM) , ( M0)) /* sys_nreswarm */ \ - MV1(WK(PAD0_SYS_PWR_REQ) , ( PTU | M0)) /* sys_pwr_req */ \ - MV1(WK(PAD1_SYS_PWRON_RESET) , ( M3)) /* gpio_wk29 */ \ - MV1(WK(PAD0_SYS_BOOT6) , ( IEN | M3)) /* gpio_wk9 */ \ - MV1(WK(PAD1_SYS_BOOT7) , ( IEN | M3)) /* gpio_wk10 */ \ - MV1(WK(PAD1_FREF_CLK3_REQ), (M3)) /* gpio_wk30 */ \ - MV1(WK(PAD1_FREF_CLK4_REQ), (M3)) /* gpio_wk7 */ \ - MV1(WK(PAD0_FREF_CLK4_OUT), (M3)) /* gpio_wk8 */ - -#define MUX_DEFAULT_OMAP4_ALL() \ - MV(CP(GPMC_AD0), (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* sdmmc2_dat0 */ \ - MV(CP(GPMC_AD1), (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* sdmmc2_dat1 */ \ - MV(CP(GPMC_AD2), (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* sdmmc2_dat2 */ \ - MV(CP(GPMC_AD3), (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* sdmmc2_dat3 */ \ - MV(CP(GPMC_AD4), (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* sdmmc2_dat4 */ \ - MV(CP(GPMC_AD5), (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* sdmmc2_dat5 */ \ - MV(CP(GPMC_AD6), (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* sdmmc2_dat6 */ \ - MV(CP(GPMC_AD7), (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* sdmmc2_dat7 */ \ - MV(CP(GPMC_AD8), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M3)) /* gpio_32 */ \ - MV(CP(GPMC_AD9), (M3_SAFE)) /* gpio_33 */ \ - MV(CP(GPMC_AD10), (M3_SAFE)) /* gpio_34 */ \ - MV(CP(GPMC_AD11), (M3_SAFE)) /* gpio_35 */ \ - MV(CP(GPMC_AD12), (M3_SAFE)) /* gpio_36 */ \ - MV(CP(GPMC_AD13), (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)) /* gpio_37 */ \ - MV(CP(GPMC_AD14), (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)) /* gpio_38 */ \ - MV(CP(GPMC_AD15), (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)) /* gpio_39 */ \ - MV(CP(GPMC_A16), (M3_SAFE)) /* gpio_40 */ \ - MV(CP(GPMC_A17), (M3_SAFE)) /* gpio_41 */ \ - MV(CP(GPMC_A18), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_row6 */ \ - MV(CP(GPMC_A19), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_row7 */ \ - MV(CP(GPMC_A20), (M3_SAFE)) /* gpio_44 */ \ - MV(CP(GPMC_A21), (M3_SAFE)) /* gpio_45 */ \ - MV(CP(GPMC_A22), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_col6 */ \ - MV(CP(GPMC_A23), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_col7 */ \ - MV(CP(GPMC_A24), (M3_SAFE)) /* gpio_48 */ \ - MV(CP(GPMC_A25), (M3_SAFE)) /* gpio_49 */ \ - MV(CP(GPMC_NCS0), (M0)) /* gpmc_ncs0 */ \ - MV(CP(GPMC_NCS1), (M3_SAFE)) /* gpio_51 */ \ - MV(CP(GPMC_NCS2), (M3_SAFE)) /* gpio_52 */ \ - MV(CP(GPMC_NCS3), (M3_SAFE)) /* gpio_53 */ \ - MV(CP(GPMC_NWP), (M0_SAFE)) /* gpmc_nwp */ \ - MV(CP(GPMC_CLK), (M3_SAFE)) /* gpio_55 */ \ - MV(CP(GPMC_NADV_ALE), (M0)) /* gpmc_nadv_ale */ \ - MV(CP(GPMC_NOE), (PTU | OFF_EN | OFF_OUT_PTD | M1)) /* sdmmc2_clk */ \ - MV(CP(GPMC_NWE), (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* sdmmc2_cmd */ \ - MV(CP(GPMC_NBE0_CLE), (M0)) /* gpmc_nbe0_cle*/ \ - MV(CP(GPMC_NBE1), (M3_SAFE)) /* gpio_60 */ \ - MV(CP(GPMC_WAIT0), (M0)) /* gpmc_wait */ \ - MV(CP(GPMC_WAIT1), (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)) /* gpio_39 */ \ - MV(CP(C2C_DATA11), (M3_SAFE)) /* gpio_100 */ \ - MV(CP(C2C_DATA12), (M1_SAFE)) /* dsi1_te0 */ \ - MV(CP(C2C_DATA13), (M3_SAFE)) /* gpio_102 */ \ - MV(CP(C2C_DATA14), (M1_SAFE)) /* dsi2_te0 */ \ - MV(CP(C2C_DATA15), (M3_SAFE)) /* gpio_104 */ \ - MV(CP(HDMI_HPD), (M0_SAFE)) /* hdmi_hpd */ \ - MV(CP(HDMI_CEC), (M0_SAFE)) /* hdmi_cec */ \ - MV(CP(HDMI_DDC_SCL), (M0_SAFE)) /* hdmi_ddc_scl */ \ - MV(CP(HDMI_DDC_SDA), (M0_SAFE)) /* hdmi_ddc_sda */ \ - MV(CP(CSI21_DX0), (M0_SAFE)) /* csi21_dx0 */ \ - MV(CP(CSI21_DY0), (M0_SAFE)) /* csi21_dy0 */ \ - MV(CP(CSI21_DX1), (M0_SAFE)) /* csi21_dx1 */ \ - MV(CP(CSI21_DY1), (M0_SAFE)) /* csi21_dy1 */ \ - MV(CP(CSI21_DX2), (M0_SAFE)) /* csi21_dx2 */ \ - MV(CP(CSI21_DY2), (M0_SAFE)) /* csi21_dy2 */ \ - MV(CP(CSI21_DX3), (M0_SAFE)) /* csi21_dx3 */ \ - MV(CP(CSI21_DY3), (M0_SAFE)) /* csi21_dy3 */ \ - MV(CP(CSI21_DX4), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M3)) /* gpi_75 */ \ - MV(CP(CSI21_DY4), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M3)) /* gpi_76 */ \ - MV(CP(CSI22_DX0), (M0_SAFE)) /* csi22_dx0 */ \ - MV(CP(CSI22_DY0), (M0_SAFE)) /* csi22_dy0 */ \ - MV(CP(CSI22_DX1), (M0_SAFE)) /* csi22_dx1 */ \ - MV(CP(CSI22_DY1), (M0_SAFE)) /* csi22_dy1 */ \ - MV(CP(CAM_SHUTTER), (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M0)) /* cam_shutter */ \ - MV(CP(CAM_STROBE), (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M0)) /* cam_strobe */ \ - MV(CP(CAM_GLOBALRESET), (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)) /* gpio_83 */ \ - MV(CP(USBB1_ULPITLL_CLK), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4)) /* usbb1_ulpiphy_clk */ \ - MV(CP(USBB1_ULPITLL_STP), (PTU | OFF_EN | OFF_OUT_PTD | M4)) /* usbb1_ulpiphy_stp */ \ - MV(CP(USBB1_ULPITLL_DIR), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4)) /* usbb1_ulpiphy_dir */ \ - MV(CP(USBB1_ULPITLL_NXT), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4)) /* usbb1_ulpiphy_nxt */ \ - MV(CP(USBB1_ULPITLL_DAT0), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4)) /* usbb1_ulpiphy_dat0 */ \ - MV(CP(USBB1_ULPITLL_DAT1), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4)) /* usbb1_ulpiphy_dat1 */ \ - MV(CP(USBB1_ULPITLL_DAT2), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4)) /* usbb1_ulpiphy_dat2 */ \ - MV(CP(USBB1_ULPITLL_DAT3), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4)) /* usbb1_ulpiphy_dat3 */ \ - MV(CP(USBB1_ULPITLL_DAT4), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4)) /* usbb1_ulpiphy_dat4 */ \ - MV(CP(USBB1_ULPITLL_DAT5), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4)) /* usbb1_ulpiphy_dat5 */ \ - MV(CP(USBB1_ULPITLL_DAT6), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4)) /* usbb1_ulpiphy_dat6 */ \ - MV(CP(USBB1_ULPITLL_DAT7), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4)) /* usbb1_ulpiphy_dat7 */ \ - MV(CP(USBB1_HSIC_DATA), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* usbb1_hsic_data */ \ - MV(CP(USBB1_HSIC_STROBE), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* usbb1_hsic_strobe */ \ - MV(CP(USBC1_ICUSB_DP), (M0_SAFE)) /* usbc1_icusb_dp */ \ - MV(CP(USBC1_ICUSB_DM), (M0_SAFE)) /* usbc1_icusb_dm */ \ - MV(CP(SDMMC1_CLK), (PTU | OFF_EN | OFF_OUT_PTD | M0)) /* sdmmc1_clk */ \ - MV(CP(SDMMC1_CMD), (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc1_cmd */ \ - MV(CP(SDMMC1_DAT0), (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc1_dat0 */ \ - MV(CP(SDMMC1_DAT1), (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc1_dat1 */ \ - MV(CP(SDMMC1_DAT2), (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc1_dat2 */ \ - MV(CP(SDMMC1_DAT3), (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc1_dat3 */ \ - MV(CP(SDMMC1_DAT4), (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc1_dat4 */ \ - MV(CP(SDMMC1_DAT5), (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc1_dat5 */ \ - MV(CP(SDMMC1_DAT6), (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc1_dat6 */ \ - MV(CP(SDMMC1_DAT7), (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc1_dat7 */ \ - MV(CP(ABE_MCBSP2_CLKX), (IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* abe_mcbsp2_clkx */ \ - MV(CP(ABE_MCBSP2_DR), (IEN | OFF_EN | OFF_OUT_PTD | M0)) /* abe_mcbsp2_dr */ \ - MV(CP(ABE_MCBSP2_DX), (OFF_EN | OFF_OUT_PTD | M0)) /* abe_mcbsp2_dx */ \ - MV(CP(ABE_MCBSP2_FSX), (IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* abe_mcbsp2_fsx */ \ - MV(CP(ABE_MCBSP1_CLKX), (M1_SAFE)) /* abe_slimbus1_clock */ \ - MV(CP(ABE_MCBSP1_DR), (M1_SAFE)) /* abe_slimbus1_data */ \ - MV(CP(ABE_MCBSP1_DX), (OFF_EN | OFF_OUT_PTD | M0)) /* abe_mcbsp1_dx */ \ - MV(CP(ABE_MCBSP1_FSX), (IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* abe_mcbsp1_fsx */ \ - MV(CP(ABE_PDM_UL_DATA), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0_SAFE)) /* abe_pdm_ul_data */ \ - MV(CP(ABE_PDM_DL_DATA), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0_SAFE)) /* abe_pdm_dl_data */ \ - MV(CP(ABE_PDM_FRAME), (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0_SAFE)) /* abe_pdm_frame */ \ - MV(CP(ABE_PDM_LB_CLK), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0_SAFE)) /* abe_pdm_lb_clk */ \ - MV(CP(ABE_CLKS), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0_SAFE)) /* abe_clks */ \ - MV(CP(ABE_DMIC_CLK1), (M0_SAFE)) /* abe_dmic_clk1 */ \ - MV(CP(ABE_DMIC_DIN1), (M0_SAFE)) /* abe_dmic_din1 */ \ - MV(CP(ABE_DMIC_DIN2), (M0_SAFE)) /* abe_dmic_din2 */ \ - MV(CP(ABE_DMIC_DIN3), (M0_SAFE)) /* abe_dmic_din3 */ \ - MV(CP(UART2_CTS), (PTU | IEN | M0)) /* uart2_cts */ \ - MV(CP(UART2_RTS), (M0)) /* uart2_rts */ \ - MV(CP(UART2_RX), (PTU | IEN | M0)) /* uart2_rx */ \ - MV(CP(UART2_TX), (M0)) /* uart2_tx */ \ - MV(CP(HDQ_SIO), (M3_SAFE)) /* gpio_127 */ \ - MV(CP(I2C1_SCL), (PTU | IEN | M0)) /* i2c1_scl */ \ - MV(CP(I2C1_SDA), (PTU | IEN | M0)) /* i2c1_sda */ \ - MV(CP(I2C2_SCL), (PTU | IEN | M0)) /* i2c2_scl */ \ - MV(CP(I2C2_SDA), (PTU | IEN | M0)) /* i2c2_sda */ \ - MV(CP(I2C3_SCL), (PTU | IEN | M0)) /* i2c3_scl */ \ - MV(CP(I2C3_SDA), (PTU | IEN | M0)) /* i2c3_sda */ \ - MV(CP(I2C4_SCL), (PTU | IEN | M0)) /* i2c4_scl */ \ - MV(CP(I2C4_SDA), (PTU | IEN | M0)) /* i2c4_sda */ \ - MV(CP(MCSPI1_CLK), (IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* mcspi1_clk */ \ - MV(CP(MCSPI1_SOMI), (IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* mcspi1_somi */ \ - MV(CP(MCSPI1_SIMO), (IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* mcspi1_simo */ \ - MV(CP(MCSPI1_CS0), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* mcspi1_cs0 */ \ - MV(CP(MCSPI1_CS1), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0_SAFE)) /* mcspi1_cs1 */ \ - MV(CP(MCSPI1_CS2), (OFF_EN | OFF_OUT_PTU | M3)) /* gpio_139 */ \ - MV(CP(MCSPI1_CS3), (M3_SAFE)) /* gpio_140 */ \ - MV(CP(UART3_CTS_RCTX), (PTU | IEN | M0)) /* uart3_tx */ \ - MV(CP(UART3_RTS_SD), (M0)) /* uart3_rts_sd */ \ - MV(CP(UART3_RX_IRRX), (IEN | M0)) /* uart3_rx */ \ - MV(CP(UART3_TX_IRTX), (M0)) /* uart3_tx */ \ - MV(CP(SDMMC5_CLK), (PTU | OFF_EN | OFF_OUT_PTD | M0)) /* sdmmc5_clk */ \ - MV(CP(SDMMC5_CMD), (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc5_cmd */ \ - MV(CP(SDMMC5_DAT0), (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc5_dat0 */ \ - MV(CP(SDMMC5_DAT1), (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc5_dat1 */ \ - MV(CP(SDMMC5_DAT2), (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc5_dat2 */ \ - MV(CP(SDMMC5_DAT3), (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc5_dat3 */ \ - MV(CP(MCSPI4_CLK), (IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* mcspi4_clk */ \ - MV(CP(MCSPI4_SIMO), (IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* mcspi4_simo */ \ - MV(CP(MCSPI4_SOMI), (IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* mcspi4_somi */ \ - MV(CP(MCSPI4_CS0), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* mcspi4_cs0 */ \ - MV(CP(UART4_RX), (IEN | M0)) /* uart4_rx */ \ - MV(CP(UART4_TX), (M0)) /* uart4_tx */ \ - MV(CP(USBB2_ULPITLL_CLK), (M3)) /* gpio_157 */ \ - MV(CP(USBB2_ULPITLL_STP), (M5)) /* dispc2_data23 */ \ - MV(CP(USBB2_ULPITLL_DIR), (M5)) /* dispc2_data22 */ \ - MV(CP(USBB2_ULPITLL_NXT), (M5)) /* dispc2_data21 */ \ - MV(CP(USBB2_ULPITLL_DAT0), (M5)) /* dispc2_data20 */ \ - MV(CP(USBB2_ULPITLL_DAT1), (M5)) /* dispc2_data19 */ \ - MV(CP(USBB2_ULPITLL_DAT2), (M5)) /* dispc2_data18 */ \ - MV(CP(USBB2_ULPITLL_DAT3), (M5)) /* dispc2_data15 */ \ - MV(CP(USBB2_ULPITLL_DAT4), (M5)) /* dispc2_data14 */ \ - MV(CP(USBB2_ULPITLL_DAT5), (M5)) /* dispc2_data13 */ \ - MV(CP(USBB2_ULPITLL_DAT6), (M5)) /* dispc2_data12 */ \ - MV(CP(USBB2_ULPITLL_DAT7), (M5)) /* dispc2_data11 */ \ - MV(CP(USBB2_HSIC_DATA), (OFF_EN | OFF_OUT_PTU | M3)) /* gpio_169 */ \ - MV(CP(USBB2_HSIC_STROBE), (OFF_EN | OFF_OUT_PTU | M3)) /* gpio_170 */ \ - MV(CP(UNIPRO_TX0), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_col0 */ \ - MV(CP(UNIPRO_TY0), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_col1 */ \ - MV(CP(UNIPRO_TX1), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_col2 */ \ - MV(CP(UNIPRO_TY1), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_col3 */ \ - MV(CP(UNIPRO_TX2), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M3)) /* gpio_0 */ \ - MV(CP(UNIPRO_TY2), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M3)) /* gpio_1 */ \ - MV(CP(UNIPRO_RX0), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_row0 */ \ - MV(CP(UNIPRO_RY0), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_row1 */ \ - MV(CP(UNIPRO_RX1), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_row2 */ \ - MV(CP(UNIPRO_RY1), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_row3 */ \ - MV(CP(UNIPRO_RX2), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_row4 */ \ - MV(CP(UNIPRO_RY2), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_row5 */ \ - MV(CP(USBA0_OTG_CE), (PTU | OFF_EN | OFF_PD | OFF_OUT_PTD | M0)) /* usba0_otg_ce */ \ - MV(CP(USBA0_OTG_DP), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* usba0_otg_dp */ \ - MV(CP(USBA0_OTG_DM), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* usba0_otg_dm */ \ - MV(CP(FREF_CLK1_OUT), (M0_SAFE)) /* fref_clk1_out */ \ - MV(CP(FREF_CLK2_OUT), (M0_SAFE)) /* fref_clk2_out */ \ - MV(CP(SYS_NIRQ1), (PTU | IEN | M0)) /* sys_nirq1 */ \ - MV(CP(SYS_NIRQ2), (PTU | IEN | M0)) /* sys_nirq2 */ \ - MV(CP(SYS_BOOT0), (M3_SAFE)) /* gpio_184 */ \ - MV(CP(SYS_BOOT1), (M3_SAFE)) /* gpio_185 */ \ - MV(CP(SYS_BOOT2), (M3_SAFE)) /* gpio_186 */ \ - MV(CP(SYS_BOOT3), (M3_SAFE)) /* gpio_187 */ \ - MV(CP(SYS_BOOT4), (M3_SAFE)) /* gpio_188 */ \ - MV(CP(SYS_BOOT5), (M3_SAFE)) /* gpio_189 */ \ - MV(CP(DPM_EMU0), (M0_SAFE)) /* dpm_emu0 */ \ - MV(CP(DPM_EMU1), (M0_SAFE)) /* dpm_emu1 */ \ - MV(CP(DPM_EMU2), (M0_SAFE)) /* dpm_emu2 */ \ - MV(CP(DPM_EMU3), (M5)) /* dispc2_data10 */ \ - MV(CP(DPM_EMU4), (M5)) /* dispc2_data9 */ \ - MV(CP(DPM_EMU5), (M5)) /* dispc2_data16 */ \ - MV(CP(DPM_EMU6), (M5)) /* dispc2_data17 */ \ - MV(CP(DPM_EMU7), (M5)) /* dispc2_hsync */ \ - MV(CP(DPM_EMU8), (M5)) /* dispc2_pclk */ \ - MV(CP(DPM_EMU9), (M5)) /* dispc2_vsync */ \ - MV(CP(DPM_EMU10), (M5)) /* dispc2_de */ \ - MV(CP(DPM_EMU11), (M5)) /* dispc2_data8 */ \ - MV(CP(DPM_EMU12), (M5)) /* dispc2_data7 */ \ - MV(CP(DPM_EMU13), (M5)) /* dispc2_data6 */ \ - MV(CP(DPM_EMU14), (M5)) /* dispc2_data5 */ \ - MV(CP(DPM_EMU15), (M5)) /* dispc2_data4 */ \ - MV(CP(DPM_EMU16), (M5)) /* dispc2_data3/dmtimer8_pwm_evt */ \ - MV(CP(DPM_EMU17), (M5)) /* dispc2_data2 */ \ - MV(CP(DPM_EMU18), (M5)) /* dispc2_data1 */ \ - MV(CP(DPM_EMU19), (M5)) /* dispc2_data0 */ \ - MV1(WK(PAD0_SIM_IO), (M0_SAFE)) /* sim_io */ \ - MV1(WK(PAD1_SIM_CLK), (M0_SAFE)) /* sim_clk */ \ - MV1(WK(PAD0_SIM_RESET), (M0_SAFE)) /* sim_reset */ \ - MV1(WK(PAD1_SIM_CD), (M0_SAFE)) /* sim_cd */ \ - MV1(WK(PAD0_SIM_PWRCTRL), (M0_SAFE)) /* sim_pwrctrl */ \ - MV1(WK(PAD1_SR_SCL), (PTU | IEN | M0)) /* sr_scl */ \ - MV1(WK(PAD0_SR_SDA), (PTU | IEN | M0)) /* sr_sda */ \ - MV1(WK(PAD1_FREF_XTAL_IN), (M0_SAFE)) /* # */ \ - MV1(WK(PAD0_FREF_SLICER_IN), (M0_SAFE)) /* fref_slicer_in */ \ - MV1(WK(PAD1_FREF_CLK_IOREQ), (M0_SAFE)) /* fref_clk_ioreq */ \ - MV1(WK(PAD0_FREF_CLK0_OUT), (M0)) /* sys_drm_msecure */ \ - MV1(WK(PAD1_FREF_CLK3_REQ), (M0)) /* # */ \ - MV1(WK(PAD0_FREF_CLK3_OUT), (M0_SAFE)) /* fref_clk3_out */ \ - MV1(WK(PAD1_FREF_CLK4_REQ), (M0_SAFE)) /* # */ \ - MV1(WK(PAD0_FREF_CLK4_OUT), (M0_SAFE)) /* # */ \ - MV1(WK(PAD1_SYS_32K), (IEN | M0_SAFE)) /* sys_32k */ \ - MV1(WK(PAD0_SYS_NRESPWRON), (IEN | M0_SAFE)) /* sys_nrespwron */ \ - MV1(WK(PAD1_SYS_NRESWARM), (IEN | M0_SAFE)) /* sys_nreswarm */ \ - MV1(WK(PAD0_SYS_PWR_REQ), (M0_SAFE)) /* sys_pwr_req */ \ - MV1(WK(PAD1_SYS_PWRON_RESET), (M3_SAFE)) /* gpio_wk29 */ \ - MV1(WK(PAD0_SYS_BOOT6), (M3_SAFE)) /* gpio_wk9 */ \ - MV1(WK(PAD1_SYS_BOOT7), (M3_SAFE)) /* gpio_wk10 */ \ - MV1(WK(PAD1_JTAG_TCK), (IEN | M0)) /* jtag_tck */ \ - MV1(WK(PAD0_JTAG_RTCK), (M0)) /* jtag_rtck */ \ - MV1(WK(PAD1_JTAG_TMS_TMSC), (IEN | M0)) /* jtag_tms_tmsc */ \ - MV1(WK(PAD0_JTAG_TDI), (IEN | M0)) /* jtag_tdi */ \ - MV1(WK(PAD1_JTAG_TDO), (M0)) /* jtag_tdo */ - -/********************************************************** - * Routine: set_muxconf_regs - * Description: Setting up the configuration Mux registers - * specific to the hardware. Many pins need - * to be moved from protect to primary mode. - *********************************************************/ -void set_muxconf_regs(void) -{ - MUX_DEFAULT_OMAP4(); - return; -} - -/****************************************************************************** - * Routine: update_mux() - * Description:Update balls which are different between boards. All should be - * updated to match functionality. However, I'm only updating ones - * which I'll be using for now. When power comes into play they - * all need updating. - *****************************************************************************/ -void update_mux(u32 btype, u32 mtype) -{ - /* REVISIT */ - return; - -} - -/* optionally do something like blinking LED */ -void board_hang (void) -{ while (0) {};} - -int nand_init(void) -{ - return 0; -} -void reset_phy(unsigned int base) -{ - *(volatile int*)(base + IODFT_TLGC) |= (1 << 10); -} diff --git a/x-loader/board/omap4430panda/syslib.c b/x-loader/board/omap4430panda/syslib.c deleted file mode 100644 index 2b16cc4..0000000 --- a/x-loader/board/omap4430panda/syslib.c +++ /dev/null @@ -1,73 +0,0 @@ -/* - * (C) Copyright 2006 - * Texas Instruments, <www.ti.com> - * Richard Woodruff <r-woodruff2@ti.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <asm/arch/cpu.h> -#include <asm/io.h> -#include <asm/arch/bits.h> -#include <asm/arch/mem.h> -#include <asm/arch/clocks.h> -#include <asm/arch/sys_proto.h> -#include <asm/arch/sys_info.h> - -/************************************************************ - * sdelay() - simple spin loop. Will be constant time as - * its generally used in bypass conditions only. This - * is necessary until timers are accessible. - * - * not inline to increase chances its in cache when called - *************************************************************/ -void sdelay(unsigned long loops) -{ - __asm__ volatile ("1:\n" "subs %0, %1, #1\n" - "bne 1b":"=r" (loops):"0"(loops)); -} - -/***************************************************************** - * sr32 - clear & set a value in a bit range for a 32 bit address - *****************************************************************/ -void sr32(u32 addr, u32 start_bit, u32 num_bits, u32 value) -{ - u32 tmp, msk = 0; - msk = 1 << num_bits; - --msk; - tmp = __raw_readl(addr) & ~(msk << start_bit); - tmp |= value << start_bit; - __raw_writel(tmp, addr); -} - -/********************************************************************* - * wait_on_value() - common routine to allow waiting for changes in - * volatile regs. - *********************************************************************/ -u32 wait_on_value(u32 read_bit_mask, u32 match_value, u32 read_addr, u32 bound) -{ - u32 i = 0, val; - do { - ++i; - val = __raw_readl(read_addr) & read_bit_mask; - if (val == match_value) - return (1); - if (i == bound) - return (0); - } while (1); -} - diff --git a/x-loader/board/overo/Makefile b/x-loader/board/overo/Makefile deleted file mode 100644 index 32f9bf1..0000000 --- a/x-loader/board/overo/Makefile +++ /dev/null @@ -1,51 +0,0 @@ -# -# (C) Copyright 2000, 2001, 2002 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).a - -COBJS := overo.o -SOBJS := platform.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) $(SOBJS) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak $(obj).depend - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/x-loader/board/overo/config.mk b/x-loader/board/overo/config.mk deleted file mode 100644 index 7ee3014..0000000 --- a/x-loader/board/overo/config.mk +++ /dev/null @@ -1,20 +0,0 @@ -# -# (C) Copyright 2006 -# Texas Instruments, <www.ti.com> -# -# Overo board uses TI OMAP35xx (ARM-CortexA8) cpu -# see http://www.ti.com/ for more information on Texas Instruments -# -# Overo has 1 bank of 128MB mPOP-SDRAM on CS0 -# Physical Address: -# 8000'0000 (bank0) - -# For use if you want X-Loader to relocate from SRAM to DDR -#TEXT_BASE = 0x80e80000 - -# For XIP in 64K of SRAM or debug (GP device has it all availabe) -# SRAM 40200000-4020FFFF base -# initial stack at 0x4020fffc used in s_init (below xloader). -# The run time stack is (above xloader, 2k below) -# If any globals exist there needs to be room for them also -TEXT_BASE = 0x40200800 diff --git a/x-loader/board/overo/overo.c b/x-loader/board/overo/overo.c deleted file mode 100644 index 8df53e5..0000000 --- a/x-loader/board/overo/overo.c +++ /dev/null @@ -1,1148 +0,0 @@ -/* - * (C) Copyright 2006 - * Texas Instruments, <www.ti.com> - * Jian Zhang <jzhang@ti.com> - * Richard Woodruff <r-woodruff2@ti.com> - * - * Modified for overo - * Steve Sakoman <steve@sakoman.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <command.h> -#include <part.h> -#include <fat.h> -#include <i2c.h> -#include <asm/arch/cpu.h> -#include <asm/arch/bits.h> -#include <asm/arch/gpio.h> -#include <asm/arch/mux.h> -#include <asm/arch/sys_proto.h> -#include <asm/arch/sys_info.h> -#include <asm/arch/clocks.h> -#include <asm/arch/mem.h> - -/* params for 37XX */ -#define CORE_DPLL_PARAM_M2 0x09 -#define CORE_DPLL_PARAM_M 0x360 -#define CORE_DPLL_PARAM_N 0xC - -/* Used to index into DPLL parameter tables */ -struct dpll_param { - unsigned int m; - unsigned int n; - unsigned int fsel; - unsigned int m2; -}; - -typedef struct dpll_param dpll_param; - -/* Following functions are exported from lowlevel_init.S */ -extern dpll_param *get_mpu_dpll_param(); -extern dpll_param *get_iva_dpll_param(); -extern dpll_param *get_core_dpll_param(); -extern dpll_param *get_per_dpll_param(); - -#define __raw_readl(a) (*(volatile unsigned int *)(a)) -#define __raw_writel(v, a) (*(volatile unsigned int *)(a) = (v)) -#define __raw_readw(a) (*(volatile unsigned short *)(a)) -#define __raw_writew(v, a) (*(volatile unsigned short *)(a) = (v)) - -static char *rev_s[CPU_3XX_MAX_REV] = { - "1.0", - "2.0", - "2.1", - "3.0", - "3.1", - "UNKNOWN", - "UNKNOWN", - "3.1.2"}; - -/******************************************************* - * Routine: delay - * Description: spinning delay to use before udelay works - ******************************************************/ -static inline void delay(unsigned long loops) -{ - __asm__ volatile ("1:\n" "subs %0, %1, #1\n" - "bne 1b":"=r" (loops):"0"(loops)); -} - -void udelay (unsigned long usecs) { - delay(usecs); -} - -/***************************************** - * Routine: board_init - * Description: Early hardware init. - *****************************************/ -int board_init(void) -{ - return 0; -} - -/************************************************************* - * get_device_type(): tell if GP/HS/EMU/TST - *************************************************************/ -u32 get_device_type(void) -{ - int mode; - mode = __raw_readl(CONTROL_STATUS) & (DEVICE_MASK); - return mode >>= 8; -} - -/************************************************ - * get_sysboot_value(void) - return SYS_BOOT[4:0] - ************************************************/ -u32 get_sysboot_value(void) -{ - int mode; - mode = __raw_readl(CONTROL_STATUS) & (SYSBOOT_MASK); - return mode; -} - -/************************************************************* - * Routine: get_mem_type(void) - returns the kind of memory connected - * to GPMC that we are trying to boot form. Uses SYS BOOT settings. - *************************************************************/ -u32 get_mem_type(void) -{ - u32 mem_type = get_sysboot_value(); - - switch (mem_type) { - case 0: - case 2: - case 4: - case 16: - case 22: - return GPMC_ONENAND; - - case 1: - case 12: - case 15: - case 21: - case 27: - return GPMC_NAND; - - case 3: - case 6: - return MMC_ONENAND; - - case 8: - case 11: - case 14: - case 20: - case 26: - return GPMC_MDOC; - - case 17: - case 18: - case 24: - return MMC_NAND; - - case 7: - case 10: - case 13: - case 19: - case 25: - default: - return GPMC_NOR; - } -} - -/****************************************** - * get_cpu_type(void) - extract cpu info - ******************************************/ -u32 get_cpu_type(void) -{ - return __raw_readl(CONTROL_OMAP_STATUS); -} - -/****************************************** - * get_cpu_id(void) - extract cpu id - * returns 0 for ES1.0, cpuid otherwise - ******************************************/ -u32 get_cpu_id(void) -{ - u32 cpuid = 0; - - /* - * On ES1.0 the IDCODE register is not exposed on L4 - * so using CPU ID to differentiate between ES1.0 and > ES1.0. - */ - __asm__ __volatile__("mrc p15, 0, %0, c0, c0, 0":"=r"(cpuid)); - if ((cpuid & 0xf) == 0x0) { - return 0; - } else { - /* Decode the IDs on > ES1.0 */ - cpuid = __raw_readl(CONTROL_IDCODE); - } - - return cpuid; -} - -/****************************************** - * get_cpu_family(void) - extract cpu info - ******************************************/ -u32 get_cpu_family(void) -{ - u16 hawkeye; - u32 cpu_family; - u32 cpuid = get_cpu_id(); - - if (cpuid == 0) - return CPU_OMAP34XX; - - hawkeye = (cpuid >> HAWKEYE_SHIFT) & 0xffff; - switch (hawkeye) { - case HAWKEYE_OMAP34XX: - cpu_family = CPU_OMAP34XX; - break; - case HAWKEYE_AM35XX: - cpu_family = CPU_AM35XX; - break; - case HAWKEYE_OMAP36XX: - cpu_family = CPU_OMAP36XX; - break; - default: - cpu_family = CPU_OMAP34XX; - } - - return cpu_family; -} - -/****************************************** - * get_cpu_rev(void) - extract version info - ******************************************/ -u32 get_cpu_rev(void) -{ - u32 cpuid = get_cpu_id(); - - if (cpuid == 0) - return CPU_3XX_ES10; - else - return (cpuid >> CPU_3XX_ID_SHIFT) & 0xf; -} - -/****************************************** - * Print CPU information - ******************************************/ -int print_cpuinfo (void) -{ - char *cpu_family_s, *cpu_s, *sec_s; - - switch (get_cpu_family()) { - case CPU_OMAP34XX: - cpu_family_s = "OMAP"; - switch (get_cpu_type()) { - case OMAP3503: - cpu_s = "3503"; - break; - case OMAP3515: - cpu_s = "3515"; - break; - case OMAP3525: - cpu_s = "3525"; - break; - case OMAP3530: - cpu_s = "3530"; - break; - default: - cpu_s = "35XX"; - break; - } - break; - case CPU_AM35XX: - cpu_family_s = "AM"; - switch (get_cpu_type()) { - case AM3505: - cpu_s = "3505"; - break; - case AM3517: - cpu_s = "3517"; - break; - default: - cpu_s = "35XX"; - break; - } - break; - case CPU_OMAP36XX: - cpu_family_s = "OMAP"; - switch (get_cpu_type()) { - case OMAP3730: - cpu_s = "3630/3730"; - break; - default: - cpu_s = "36XX/37XX"; - break; - } - break; - default: - cpu_family_s = "OMAP"; - cpu_s = "35XX"; - } - - switch (get_device_type()) { - case TST_DEVICE: - sec_s = "TST"; - break; - case EMU_DEVICE: - sec_s = "EMU"; - break; - case HS_DEVICE: - sec_s = "HS"; - break; - case GP_DEVICE: - sec_s = "GP"; - break; - default: - sec_s = "?"; - } - - printf("%s%s-%s ES%s\n", - cpu_family_s, cpu_s, sec_s, rev_s[get_cpu_rev()]); - - return 0; -} - -/****************************************** - * cpu_is_3410(void) - returns true for 3410 - ******************************************/ -u32 cpu_is_3410(void) -{ - int status; - if (get_cpu_rev() < CPU_3430_ES2) { - return 0; - } else { - /* read scalability status and return 1 for 3410*/ - status = __raw_readl(CONTROL_SCALABLE_OMAP_STATUS); - /* Check whether MPU frequency is set to 266 MHz which - * is nominal for 3410. If yes return true else false - */ - if (((status >> 8) & 0x3) == 0x2) - return 1; - else - return 0; - } -} - -/***************************************************************** - * Routine: get_board_revision - * Description: Returns the board revision - *****************************************************************/ -int get_board_revision(void) -{ - int revision; - unsigned char data; - - /* board revisions <= R2410 connect 4030 irq_1 to gpio112 */ - /* these boards should return a revision number of 0 */ - /* the code below forces a 4030 RTC irq to ensure that gpio112 is low */ - data = 0x01; - i2c_write(0x4B, 0x29, 1, &data, 1); - data = 0x0c; - i2c_write(0x4B, 0x2b, 1, &data, 1); - i2c_read(0x4B, 0x2a, 1, &data, 1); - - if (!omap_request_gpio(112) && - !omap_request_gpio(113) && - !omap_request_gpio(115)) { - - omap_set_gpio_direction(112, 1); - omap_set_gpio_direction(113, 1); - omap_set_gpio_direction(115, 1); - - revision = omap_get_gpio_datain(115) << 2 | - omap_get_gpio_datain(113) << 1 | - omap_get_gpio_datain(112); - - omap_free_gpio(112); - omap_free_gpio(113); - omap_free_gpio(115); - } else { - printf("Error: unable to acquire board revision GPIOs\n"); - revision = -1; - } - - return revision; -} - -/***************************************************************** - * sr32 - clear & set a value in a bit range for a 32 bit address - *****************************************************************/ -void sr32(u32 addr, u32 start_bit, u32 num_bits, u32 value) -{ - u32 tmp, msk = 0; - msk = 1 << num_bits; - --msk; - tmp = __raw_readl(addr) & ~(msk << start_bit); - tmp |= value << start_bit; - __raw_writel(tmp, addr); -} - -/********************************************************************* - * wait_on_value() - common routine to allow waiting for changes in - * volatile regs. - *********************************************************************/ -u32 wait_on_value(u32 read_bit_mask, u32 match_value, u32 read_addr, u32 bound) -{ - u32 i = 0, val; - do { - ++i; - val = __raw_readl(read_addr) & read_bit_mask; - if (val == match_value) - return 1; - if (i == bound) - return 0; - } while (1); -} - -#ifdef CFG_3430SDRAM_DDR -/********************************************************************* - * config_3430sdram_ddr() - Init DDR on 3430SDP dev board. - *********************************************************************/ -void config_3430sdram_ddr(void) -{ - /* reset sdrc controller */ - __raw_writel(SOFTRESET, SDRC_SYSCONFIG); - wait_on_value(BIT0, BIT0, SDRC_STATUS, 12000000); - __raw_writel(0, SDRC_SYSCONFIG); - - /* setup sdrc to ball mux */ - __raw_writel(SDP_SDRC_SHARING, SDRC_SHARING); - - switch (get_board_revision()) { - case 0: /* Micron 1286MB/256MB, 1/2 banks of 128MB */ - __raw_writel(0x1, SDRC_CS_CFG); /* 128MB/bank */ - __raw_writel(SDP_SDRC_MDCFG_0_DDR, SDRC_MCFG_0); - __raw_writel(SDP_SDRC_MDCFG_0_DDR, SDRC_MCFG_1); - __raw_writel(MICRON_V_ACTIMA_165, SDRC_ACTIM_CTRLA_0); - __raw_writel(MICRON_V_ACTIMB_165, SDRC_ACTIM_CTRLB_0); - __raw_writel(MICRON_V_ACTIMA_165, SDRC_ACTIM_CTRLA_1); - __raw_writel(MICRON_V_ACTIMB_165, SDRC_ACTIM_CTRLB_1); - __raw_writel(SDP_3430_SDRC_RFR_CTRL_165MHz, SDRC_RFR_CTRL_0); - __raw_writel(SDP_3430_SDRC_RFR_CTRL_165MHz, SDRC_RFR_CTRL_1); - break; - case 1: /* Micron 256MB/512MB, 1/2 banks of 256MB */ - __raw_writel(0x2, SDRC_CS_CFG); /* 256MB/bank */ - __raw_writel(SDP_SDRC_MDCFG_0_DDR_MICRON_XM, SDRC_MCFG_0); - __raw_writel(SDP_SDRC_MDCFG_0_DDR_MICRON_XM, SDRC_MCFG_1); - __raw_writel(MICRON_V_ACTIMA_165, SDRC_ACTIM_CTRLA_0); - __raw_writel(MICRON_V_ACTIMB_165, SDRC_ACTIM_CTRLB_0); - __raw_writel(MICRON_V_ACTIMA_165, SDRC_ACTIM_CTRLA_1); - __raw_writel(MICRON_V_ACTIMB_165, SDRC_ACTIM_CTRLB_1); - __raw_writel(SDP_3430_SDRC_RFR_CTRL_165MHz, SDRC_RFR_CTRL_0); - __raw_writel(SDP_3430_SDRC_RFR_CTRL_165MHz, SDRC_RFR_CTRL_1); - break; - case 2: /* Hynix 256MB/512MB, 1/2 banks of 256MB */ - __raw_writel(0x2, SDRC_CS_CFG); /* 256MB/bank */ - __raw_writel(SDP_SDRC_MDCFG_0_DDR_HYNIX, SDRC_MCFG_0); - __raw_writel(SDP_SDRC_MDCFG_0_DDR_HYNIX, SDRC_MCFG_1); - __raw_writel(HYNIX_V_ACTIMA_165, SDRC_ACTIM_CTRLA_0); - __raw_writel(HYNIX_V_ACTIMB_165, SDRC_ACTIM_CTRLB_0); - __raw_writel(HYNIX_V_ACTIMA_165, SDRC_ACTIM_CTRLA_1); - __raw_writel(HYNIX_V_ACTIMB_165, SDRC_ACTIM_CTRLB_1); - __raw_writel(SDP_3430_SDRC_RFR_CTRL_165MHz, SDRC_RFR_CTRL_0); - __raw_writel(SDP_3430_SDRC_RFR_CTRL_165MHz, SDRC_RFR_CTRL_1); - break; - default: - __raw_writel(0x1, SDRC_CS_CFG); /* 128MB/bank */ - __raw_writel(SDP_SDRC_MDCFG_0_DDR, SDRC_MCFG_0); - __raw_writel(SDP_SDRC_MDCFG_0_DDR, SDRC_MCFG_1); - __raw_writel(MICRON_V_ACTIMA_165, SDRC_ACTIM_CTRLA_0); - __raw_writel(MICRON_V_ACTIMB_165, SDRC_ACTIM_CTRLB_0); - __raw_writel(MICRON_V_ACTIMA_165, SDRC_ACTIM_CTRLA_1); - __raw_writel(MICRON_V_ACTIMB_165, SDRC_ACTIM_CTRLB_1); - __raw_writel(SDP_3430_SDRC_RFR_CTRL_165MHz, SDRC_RFR_CTRL_0); - __raw_writel(SDP_3430_SDRC_RFR_CTRL_165MHz, SDRC_RFR_CTRL_1); - } - - __raw_writel(SDP_SDRC_POWER_POP, SDRC_POWER); - - /* init sequence for mDDR/mSDR using manual commands (DDR is different) */ - __raw_writel(CMD_NOP, SDRC_MANUAL_0); - __raw_writel(CMD_NOP, SDRC_MANUAL_1); - - delay(5000); - - __raw_writel(CMD_PRECHARGE, SDRC_MANUAL_0); - __raw_writel(CMD_PRECHARGE, SDRC_MANUAL_1); - - __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0); - __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_1); - - __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0); - __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_1); - - /* set mr0 */ - __raw_writel(SDP_SDRC_MR_0_DDR, SDRC_MR_0); - __raw_writel(SDP_SDRC_MR_0_DDR, SDRC_MR_1); - - /* set up dll */ - __raw_writel(SDP_SDRC_DLLAB_CTRL, SDRC_DLLA_CTRL); - delay(0x2000); /* give time to lock */ -} -#endif /* CFG_3430SDRAM_DDR */ - -/************************************************************* - * get_sys_clk_speed - determine reference oscillator speed - * based on known 32kHz clock and gptimer. - *************************************************************/ -u32 get_osc_clk_speed(void) -{ - u32 start, cstart, cend, cdiff, cdiv, val; - - val = __raw_readl(PRM_CLKSRC_CTRL); - - if (val & SYSCLKDIV_2) - cdiv = 2; - else - cdiv = 1; - - /* enable timer2 */ - val = __raw_readl(CM_CLKSEL_WKUP) | BIT0; - __raw_writel(val, CM_CLKSEL_WKUP); /* select sys_clk for GPT1 */ - - /* Enable I and F Clocks for GPT1 */ - val = __raw_readl(CM_ICLKEN_WKUP) | BIT0 | BIT2; - __raw_writel(val, CM_ICLKEN_WKUP); - val = __raw_readl(CM_FCLKEN_WKUP) | BIT0; - __raw_writel(val, CM_FCLKEN_WKUP); - - __raw_writel(0, OMAP34XX_GPT1 + TLDR); /* start counting at 0 */ - __raw_writel(GPT_EN, OMAP34XX_GPT1 + TCLR); /* enable clock */ - /* enable 32kHz source */ - /* enabled out of reset */ - /* determine sys_clk via gauging */ - - start = 20 + __raw_readl(S32K_CR); /* start time in 20 cycles */ - while (__raw_readl(S32K_CR) < start); /* dead loop till start time */ - cstart = __raw_readl(OMAP34XX_GPT1 + TCRR); /* get start sys_clk count */ - while (__raw_readl(S32K_CR) < (start + 20)); /* wait for 40 cycles */ - cend = __raw_readl(OMAP34XX_GPT1 + TCRR); /* get end sys_clk count */ - cdiff = cend - cstart; /* get elapsed ticks */ - cdiff *= cdiv; - - /* based on number of ticks assign speed */ - if (cdiff > 19000) - return S38_4M; - else if (cdiff > 15200) - return S26M; - else if (cdiff > 13000) - return S24M; - else if (cdiff > 9000) - return S19_2M; - else if (cdiff > 7600) - return S13M; - else - return S12M; -} - -/****************************************************************************** - * get_sys_clkin_sel() - returns the sys_clkin_sel field value based on - * -- input oscillator clock frequency. - * - *****************************************************************************/ -void get_sys_clkin_sel(u32 osc_clk, u32 *sys_clkin_sel) -{ - if (osc_clk == S38_4M) - *sys_clkin_sel = 4; - else if (osc_clk == S26M) - *sys_clkin_sel = 3; - else if (osc_clk == S19_2M) - *sys_clkin_sel = 2; - else if (osc_clk == S13M) - *sys_clkin_sel = 1; - else if (osc_clk == S12M) - *sys_clkin_sel = 0; -} - -/****************************************************************************** - * prcm_init() - inits clocks for PRCM as defined in clocks.h - * -- called from SRAM, or Flash (using temp SRAM stack). - *****************************************************************************/ -void prcm_init(void) -{ - u32 osc_clk = 0, sys_clkin_sel; - dpll_param *dpll_param_p; - u32 clk_index, sil_index; - - /* Gauge the input clock speed and find out the sys_clkin_sel - * value corresponding to the input clock. - */ - osc_clk = get_osc_clk_speed(); - get_sys_clkin_sel(osc_clk, &sys_clkin_sel); - - sr32(PRM_CLKSEL, 0, 3, sys_clkin_sel); /* set input crystal speed */ - - /* If the input clock is greater than 19.2M always divide/2 */ - if (sys_clkin_sel > 2) { - sr32(PRM_CLKSRC_CTRL, 6, 2, 2); /* input clock divider */ - clk_index = sys_clkin_sel / 2; - } else { - sr32(PRM_CLKSRC_CTRL, 6, 2, 1); /* input clock divider */ - clk_index = sys_clkin_sel; - } - - sr32(PRM_CLKSRC_CTRL, 0, 2, 0);/* Bypass mode: T2 inputs a square clock */ - - /* The DPLL tables are defined according to sysclk value and - * silicon revision. The clk_index value will be used to get - * the values for that input sysclk from the DPLL param table - * and sil_index will get the values for that SysClk for the - * appropriate silicon rev. - */ - sil_index = get_cpu_rev() - 1; - - /* Unlock MPU DPLL (slows things down, and needed later) */ - sr32(CM_CLKEN_PLL_MPU, 0, 3, PLL_LOW_POWER_BYPASS); - wait_on_value(BIT0, 0, CM_IDLEST_PLL_MPU, LDELAY); - - /* Getting the base address of Core DPLL param table */ - dpll_param_p = (dpll_param *) get_core_dpll_param(); - /* Moving it to the right sysclk and ES rev base */ - dpll_param_p = dpll_param_p + 3 * clk_index + sil_index; - /* CORE DPLL */ - /* sr32(CM_CLKSEL2_EMU) set override to work when asleep */ - sr32(CM_CLKEN_PLL, 0, 3, PLL_FAST_RELOCK_BYPASS); - wait_on_value(BIT0, 0, CM_IDLEST_CKGEN, LDELAY); - - /* For 3430 ES1.0 Errata 1.50, default value directly doesnt - work. write another value and then default value. */ - sr32(CM_CLKSEL1_EMU, 16, 5, CORE_M3X2 + 1); /* m3x2 */ - sr32(CM_CLKSEL1_EMU, 16, 5, CORE_M3X2); /* m3x2 */ - sr32(CM_CLKSEL1_PLL, 27, 2, dpll_param_p->m2); /* Set M2 */ - sr32(CM_CLKSEL1_PLL, 16, 11, dpll_param_p->m); /* Set M */ - sr32(CM_CLKSEL1_PLL, 8, 7, dpll_param_p->n); /* Set N */ - sr32(CM_CLKSEL1_PLL, 6, 1, 0); /* 96M Src */ - sr32(CM_CLKSEL_CORE, 8, 4, CORE_SSI_DIV); /* ssi */ - sr32(CM_CLKSEL_CORE, 4, 2, CORE_FUSB_DIV); /* fsusb */ - sr32(CM_CLKSEL_CORE, 2, 2, CORE_L4_DIV); /* l4 */ - sr32(CM_CLKSEL_CORE, 0, 2, CORE_L3_DIV); /* l3 */ - sr32(CM_CLKSEL_GFX, 0, 3, GFX_DIV); /* gfx */ - sr32(CM_CLKSEL_WKUP, 1, 2, WKUP_RSM); /* reset mgr */ - sr32(CM_CLKEN_PLL, 4, 4, dpll_param_p->fsel); /* FREQSEL */ - sr32(CM_CLKEN_PLL, 0, 3, PLL_LOCK); /* lock mode */ - wait_on_value(BIT0, 1, CM_IDLEST_CKGEN, LDELAY); - - /* Getting the base address to PER DPLL param table */ - dpll_param_p = (dpll_param *) get_per_dpll_param(); - /* Moving it to the right sysclk base */ - dpll_param_p = dpll_param_p + clk_index; - /* PER DPLL */ - sr32(CM_CLKEN_PLL, 16, 3, PLL_STOP); - wait_on_value(BIT1, 0, CM_IDLEST_CKGEN, LDELAY); - sr32(CM_CLKSEL1_EMU, 24, 5, PER_M6X2); /* set M6 */ - sr32(CM_CLKSEL_CAM, 0, 5, PER_M5X2); /* set M5 */ - sr32(CM_CLKSEL_DSS, 0, 5, PER_M4X2); /* set M4 */ - sr32(CM_CLKSEL_DSS, 8, 5, PER_M3X2); /* set M3 */ - - if (get_cpu_family() == CPU_OMAP36XX) { - sr32(CM_CLKSEL3_PLL, 0, 5, CORE_DPLL_PARAM_M2); /* set M2 */ - sr32(CM_CLKSEL2_PLL, 8, 11, CORE_DPLL_PARAM_M); /* set m */ - sr32(CM_CLKSEL2_PLL, 0, 7, CORE_DPLL_PARAM_N); /* set n */ - } else { - sr32(CM_CLKSEL3_PLL, 0, 5, dpll_param_p->m2); /* set M2 */ - sr32(CM_CLKSEL2_PLL, 8, 11, dpll_param_p->m); /* set m */ - sr32(CM_CLKSEL2_PLL, 0, 7, dpll_param_p->n); /* set n */ - } - - sr32(CM_CLKEN_PLL, 20, 4, dpll_param_p->fsel); /* FREQSEL */ - sr32(CM_CLKEN_PLL, 16, 3, PLL_LOCK); /* lock mode */ - wait_on_value(BIT1, 2, CM_IDLEST_CKGEN, LDELAY); - - /* Getting the base address to MPU DPLL param table */ - dpll_param_p = (dpll_param *) get_mpu_dpll_param(); - - /* Moving it to the right sysclk and ES rev base */ - dpll_param_p = dpll_param_p + 3 * clk_index + sil_index; - - /* MPU DPLL (unlocked already) */ - sr32(CM_CLKSEL2_PLL_MPU, 0, 5, dpll_param_p->m2); /* Set M2 */ - sr32(CM_CLKSEL1_PLL_MPU, 8, 11, dpll_param_p->m); /* Set M */ - sr32(CM_CLKSEL1_PLL_MPU, 0, 7, dpll_param_p->n); /* Set N */ - sr32(CM_CLKEN_PLL_MPU, 4, 4, dpll_param_p->fsel); /* FREQSEL */ - sr32(CM_CLKEN_PLL_MPU, 0, 3, PLL_LOCK); /* lock mode */ - wait_on_value(BIT0, 1, CM_IDLEST_PLL_MPU, LDELAY); - - /* Getting the base address to IVA DPLL param table */ - dpll_param_p = (dpll_param *) get_iva_dpll_param(); - /* Moving it to the right sysclk and ES rev base */ - dpll_param_p = dpll_param_p + 3 * clk_index + sil_index; - /* IVA DPLL (set to 12*20=240MHz) */ - sr32(CM_CLKEN_PLL_IVA2, 0, 3, PLL_STOP); - wait_on_value(BIT0, 0, CM_IDLEST_PLL_IVA2, LDELAY); - sr32(CM_CLKSEL2_PLL_IVA2, 0, 5, dpll_param_p->m2); /* set M2 */ - sr32(CM_CLKSEL1_PLL_IVA2, 8, 11, dpll_param_p->m); /* set M */ - sr32(CM_CLKSEL1_PLL_IVA2, 0, 7, dpll_param_p->n); /* set N */ - sr32(CM_CLKEN_PLL_IVA2, 4, 4, dpll_param_p->fsel); /* FREQSEL */ - sr32(CM_CLKEN_PLL_IVA2, 0, 3, PLL_LOCK); /* lock mode */ - wait_on_value(BIT0, 1, CM_IDLEST_PLL_IVA2, LDELAY); - - /* Set up GPTimers to sys_clk source only */ - sr32(CM_CLKSEL_PER, 0, 8, 0xff); - sr32(CM_CLKSEL_WKUP, 0, 1, 1); - - delay(5000); -} - -/***************************************** - * Routine: secure_unlock - * Description: Setup security registers for access - * (GP Device only) - *****************************************/ -void secure_unlock(void) -{ - /* Permission values for registers -Full fledged permissions to all */ - #define UNLOCK_1 0xFFFFFFFF - #define UNLOCK_2 0x00000000 - #define UNLOCK_3 0x0000FFFF - /* Protection Module Register Target APE (PM_RT)*/ - __raw_writel(UNLOCK_1, RT_REQ_INFO_PERMISSION_1); - __raw_writel(UNLOCK_1, RT_READ_PERMISSION_0); - __raw_writel(UNLOCK_1, RT_WRITE_PERMISSION_0); - __raw_writel(UNLOCK_2, RT_ADDR_MATCH_1); - - __raw_writel(UNLOCK_3, GPMC_REQ_INFO_PERMISSION_0); - __raw_writel(UNLOCK_3, GPMC_READ_PERMISSION_0); - __raw_writel(UNLOCK_3, GPMC_WRITE_PERMISSION_0); - - __raw_writel(UNLOCK_3, OCM_REQ_INFO_PERMISSION_0); - __raw_writel(UNLOCK_3, OCM_READ_PERMISSION_0); - __raw_writel(UNLOCK_3, OCM_WRITE_PERMISSION_0); - __raw_writel(UNLOCK_2, OCM_ADDR_MATCH_2); - - /* IVA Changes */ - __raw_writel(UNLOCK_3, IVA2_REQ_INFO_PERMISSION_0); - __raw_writel(UNLOCK_3, IVA2_READ_PERMISSION_0); - __raw_writel(UNLOCK_3, IVA2_WRITE_PERMISSION_0); - - __raw_writel(UNLOCK_1, SMS_RG_ATT0); /* SDRC region 0 public */ -} - -/********************************************************** - * Routine: try_unlock_sram() - * Description: If chip is GP type, unlock the SRAM for - * general use. - ***********************************************************/ -void try_unlock_memory(void) -{ - int mode; - - /* if GP device unlock device SRAM for general use */ - /* secure code breaks for Secure/Emulation device - HS/E/T*/ - mode = get_device_type(); - if (mode == GP_DEVICE) - secure_unlock(); - return; -} - -/********************************************************** - * Routine: s_init - * Description: Does early system init of muxing and clocks. - * - Called at time when only stack is available. - **********************************************************/ - -void s_init(void) -{ - watchdog_init(); -#ifdef CONFIG_3430_AS_3410 - /* setup the scalability control register for - * 3430 to work in 3410 mode - */ - __raw_writel(0x5ABF, CONTROL_SCALABLE_OMAP_OCP); -#endif - try_unlock_memory(); - set_muxconf_regs(); - delay(100); - prcm_init(); - per_clocks_enable(); - config_3430sdram_ddr(); -} - -/******************************************************* - * Routine: misc_init_r - ********************************************************/ -int misc_init_r(void) -{ - print_cpuinfo(); - printf("Board revision: %d\n", get_board_revision()); - return 0; -} - -/****************************************************** - * Routine: wait_for_command_complete - * Description: Wait for posting to finish on watchdog - ******************************************************/ -void wait_for_command_complete(unsigned int wd_base) -{ - int pending = 1; - do { - pending = __raw_readl(wd_base + WWPS); - } while (pending); -} - -/**************************************** - * Routine: watchdog_init - * Description: Shut down watch dogs - *****************************************/ -void watchdog_init(void) -{ - /* There are 3 watch dogs WD1=Secure, WD2=MPU, WD3=IVA. WD1 is - * either taken care of by ROM (HS/EMU) or not accessible (GP). - * We need to take care of WD2-MPU or take a PRCM reset. WD3 - * should not be running and does not generate a PRCM reset. - */ - sr32(CM_FCLKEN_WKUP, 5, 1, 1); - sr32(CM_ICLKEN_WKUP, 5, 1, 1); - wait_on_value(BIT5, 0x20, CM_IDLEST_WKUP, 5); /* some issue here */ - - __raw_writel(WD_UNLOCK1, WD2_BASE + WSPR); - wait_for_command_complete(WD2_BASE); - __raw_writel(WD_UNLOCK2, WD2_BASE + WSPR); -} - -/********************************************** - * Routine: dram_init - * Description: sets uboots idea of sdram size - **********************************************/ -int dram_init(void) -{ - return 0; -} - -/***************************************************************** - * Routine: peripheral_enable - * Description: Enable the clks & power for perifs (GPT2, UART1,...) - ******************************************************************/ -void per_clocks_enable(void) -{ - /* Enable GP2 timer. */ - sr32(CM_CLKSEL_PER, 0, 1, 0x1); /* GPT2 = sys clk */ - sr32(CM_ICLKEN_PER, 3, 1, 0x1); /* ICKen GPT2 */ - sr32(CM_FCLKEN_PER, 3, 1, 0x1); /* FCKen GPT2 */ - -#ifdef CFG_NS16550 - /* UART1 clocks */ - sr32(CM_FCLKEN1_CORE, 13, 1, 0x1); - sr32(CM_ICLKEN1_CORE, 13, 1, 0x1); - - /* UART 3 Clocks */ - sr32(CM_FCLKEN_PER, 11, 1, 0x1); - sr32(CM_ICLKEN_PER, 11, 1, 0x1); - -#endif - - /* Enable GPIO 4, 5, & 6 clocks */ - sr32(CM_FCLKEN_PER, 17, 3, 0x7); - sr32(CM_ICLKEN_PER, 17, 3, 0x7); - -#ifdef CONFIG_DRIVER_OMAP34XX_I2C - /* Turn on all 3 I2C clocks */ - sr32(CM_FCLKEN1_CORE, 15, 3, 0x7); - sr32(CM_ICLKEN1_CORE, 15, 3, 0x7); /* I2C1,2,3 = on */ -#endif - - /* Enable the ICLK for 32K Sync Timer as its used in udelay */ - sr32(CM_ICLKEN_WKUP, 2, 1, 0x1); - - sr32(CM_FCLKEN_IVA2, 0, 32, FCK_IVA2_ON); - sr32(CM_FCLKEN1_CORE, 0, 32, FCK_CORE1_ON); - sr32(CM_ICLKEN1_CORE, 0, 32, ICK_CORE1_ON); - sr32(CM_ICLKEN2_CORE, 0, 32, ICK_CORE2_ON); - sr32(CM_FCLKEN_WKUP, 0, 32, FCK_WKUP_ON); - sr32(CM_ICLKEN_WKUP, 0, 32, ICK_WKUP_ON); - sr32(CM_FCLKEN_DSS, 0, 32, FCK_DSS_ON); - sr32(CM_ICLKEN_DSS, 0, 32, ICK_DSS_ON); - sr32(CM_FCLKEN_CAM, 0, 32, FCK_CAM_ON); - sr32(CM_ICLKEN_CAM, 0, 32, ICK_CAM_ON); - sr32(CM_FCLKEN_PER, 0, 32, FCK_PER_ON); - sr32(CM_ICLKEN_PER, 0, 32, ICK_PER_ON); - - delay(1000); -} - -/* Set MUX for UART, GPMC, SDRC, GPIO */ - -#define MUX_VAL(OFFSET,VALUE)\ - __raw_writew((VALUE), OMAP34XX_CTRL_BASE + (OFFSET)); - -#define CP(x) (CONTROL_PADCONF_##x) -/* - * IEN - Input Enable - * IDIS - Input Disable - * PTD - Pull type Down - * PTU - Pull type Up - * DIS - Pull type selection is inactive - * EN - Pull type selection is active - * M0 - Mode 0 - * The commented string gives the final mux configuration for that pin - */ -#define MUX_DEFAULT()\ - MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /*SDRC_D0*/\ - MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /*SDRC_D1*/\ - MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /*SDRC_D2*/\ - MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /*SDRC_D3*/\ - MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /*SDRC_D4*/\ - MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /*SDRC_D5*/\ - MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /*SDRC_D6*/\ - MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /*SDRC_D7*/\ - MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /*SDRC_D8*/\ - MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /*SDRC_D9*/\ - MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /*SDRC_D10*/\ - MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /*SDRC_D11*/\ - MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /*SDRC_D12*/\ - MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /*SDRC_D13*/\ - MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /*SDRC_D14*/\ - MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /*SDRC_D15*/\ - MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /*SDRC_D16*/\ - MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /*SDRC_D17*/\ - MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /*SDRC_D18*/\ - MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /*SDRC_D19*/\ - MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /*SDRC_D20*/\ - MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /*SDRC_D21*/\ - MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /*SDRC_D22*/\ - MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /*SDRC_D23*/\ - MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /*SDRC_D24*/\ - MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /*SDRC_D25*/\ - MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /*SDRC_D26*/\ - MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /*SDRC_D27*/\ - MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /*SDRC_D28*/\ - MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /*SDRC_D29*/\ - MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /*SDRC_D30*/\ - MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /*SDRC_D31*/\ - MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /*SDRC_CLK*/\ - MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /*SDRC_DQS0*/\ - MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /*SDRC_DQS1*/\ - MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /*SDRC_DQS2*/\ - MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /*SDRC_DQS3*/\ - MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0)) /*GPMC_A1*/\ - MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0)) /*GPMC_A2*/\ - MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0)) /*GPMC_A3*/\ - MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0)) /*GPMC_A4*/\ - MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0)) /*GPMC_A5*/\ - MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0)) /*GPMC_A6*/\ - MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0)) /*GPMC_A7*/\ - MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0)) /*GPMC_A8*/\ - MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M0)) /*GPMC_A9*/\ - MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0)) /*GPMC_A10*/\ - MUX_VAL(CP(GPMC_D0), (IEN | PTD | DIS | M0)) /*GPMC_D0*/\ - MUX_VAL(CP(GPMC_D1), (IEN | PTD | DIS | M0)) /*GPMC_D1*/\ - MUX_VAL(CP(GPMC_D2), (IEN | PTD | DIS | M0)) /*GPMC_D2*/\ - MUX_VAL(CP(GPMC_D3), (IEN | PTD | DIS | M0)) /*GPMC_D3*/\ - MUX_VAL(CP(GPMC_D4), (IEN | PTD | DIS | M0)) /*GPMC_D4*/\ - MUX_VAL(CP(GPMC_D5), (IEN | PTD | DIS | M0)) /*GPMC_D5*/\ - MUX_VAL(CP(GPMC_D6), (IEN | PTD | DIS | M0)) /*GPMC_D6*/\ - MUX_VAL(CP(GPMC_D7), (IEN | PTD | DIS | M0)) /*GPMC_D7*/\ - MUX_VAL(CP(GPMC_D8), (IEN | PTD | DIS | M0)) /*GPMC_D8*/\ - MUX_VAL(CP(GPMC_D9), (IEN | PTD | DIS | M0)) /*GPMC_D9*/\ - MUX_VAL(CP(GPMC_D10), (IEN | PTD | DIS | M0)) /*GPMC_D10*/\ - MUX_VAL(CP(GPMC_D11), (IEN | PTD | DIS | M0)) /*GPMC_D11*/\ - MUX_VAL(CP(GPMC_D12), (IEN | PTD | DIS | M0)) /*GPMC_D12*/\ - MUX_VAL(CP(GPMC_D13), (IEN | PTD | DIS | M0)) /*GPMC_D13*/\ - MUX_VAL(CP(GPMC_D14), (IEN | PTD | DIS | M0)) /*GPMC_D14*/\ - MUX_VAL(CP(GPMC_D15), (IEN | PTD | DIS | M0)) /*GPMC_D15*/\ - MUX_VAL(CP(GPMC_nCS0), (IDIS | PTU | EN | M0)) /*GPMC_nCS0*/\ - MUX_VAL(CP(GPMC_nCS1), (IDIS | PTU | EN | M0)) /*GPMC_nCS1*/\ - MUX_VAL(CP(GPMC_nCS2), (IDIS | PTU | EN | M0)) /*GPMC_nCS2*/\ - MUX_VAL(CP(GPMC_nCS3), (IDIS | PTU | EN | M0)) /*GPMC_nCS3*/\ - MUX_VAL(CP(GPMC_nCS4), (IDIS | PTU | EN | M0)) /*GPMC_nCS4*/\ - MUX_VAL(CP(GPMC_nCS5), (IDIS | PTU | EN | M0)) /*GPMC_nCS5*/\ - MUX_VAL(CP(GPMC_nCS6), (IDIS | PTU | EN | M0)) /*GPMC_nCS6*/\ - MUX_VAL(CP(GPMC_nCS7), (IDIS | PTU | EN | M0)) /*GPMC_nCS7*/\ - MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M0)) /*GPMC_CLK*/\ - MUX_VAL(CP(GPMC_nADV_ALE), (IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\ - MUX_VAL(CP(GPMC_nOE), (IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\ - MUX_VAL(CP(GPMC_nWE), (IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\ - MUX_VAL(CP(GPMC_nBE0_CLE), (IDIS | PTD | DIS | M0)) /*GPMC_nBE0_CLE*/\ - MUX_VAL(CP(GPMC_nBE1), (IDIS | PTD | DIS | M4)) /*GPIO_61*/\ - MUX_VAL(CP(GPMC_nWP), (IEN | PTD | DIS | M0)) /*GPMC_nWP*/\ - MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) /*GPMC_WAIT0*/\ - MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)) /*GPMC_WAIT1*/\ - MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4)) /*GPIO_64*/\ - MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M4)) /*GPIO_65*/\ - MUX_VAL(CP(DSS_DATA18), (IEN | PTD | DIS | M4)) /*GPIO_88*/\ - MUX_VAL(CP(DSS_DATA19), (IEN | PTD | DIS | M4)) /*GPIO_89*/\ - MUX_VAL(CP(DSS_DATA20), (IEN | PTD | DIS | M4)) /*GPIO_90*/\ - MUX_VAL(CP(DSS_DATA21), (IEN | PTD | DIS | M4)) /*GPIO_91*/\ - MUX_VAL(CP(CSI2_DX0), (IEN | PTD | EN | M4)) /*GPIO_112*/\ - MUX_VAL(CP(CSI2_DY0), (IEN | PTD | EN | M4)) /*GPIO_113*/\ - MUX_VAL(CP(CSI2_DX1), (IEN | PTD | EN | M4)) /*GPIO_114*/\ - /* - PEN_DOWN*/\ - MUX_VAL(CP(CSI2_DY1), (IEN | PTD | EN | M4)) /*GPIO_115*/\ - MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4)) /*GPIO_167*/\ - MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)) /*MMC1_CLK*/\ - MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)) /*MMC1_CMD*/\ - MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)) /*MMC1_DAT0*/\ - MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)) /*MMC1_DAT1*/\ - MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)) /*MMC1_DAT2*/\ - MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)) /*MMC1_DAT3*/\ - MUX_VAL(CP(MMC1_DAT4), (IEN | PTD | EN | M4)) /*GPIO_126*/\ - MUX_VAL(CP(MMC1_DAT5), (IEN | PTD | EN | M4)) /*GPIO_127*/\ - MUX_VAL(CP(MMC1_DAT6), (IEN | PTD | EN | M4)) /*GPIO_128*/\ - MUX_VAL(CP(MMC1_DAT7), (IEN | PTD | EN | M4)) /*GPIO_129*/\ - MUX_VAL(CP(MMC2_CLK), (IEN | PTU | EN | M4)) /*GPIO_130*/\ - MUX_VAL(CP(MMC2_DAT7), (IEN | PTU | EN | M4)) /*GPIO_139*/\ - MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /*UART1_TX*/\ - MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0)) /*UART1_RTS*/\ - MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M0)) /*UART1_CTS*/\ - MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /*UART1_RX*/\ - MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | EN | M0)) /*UART3_CTS_RCTX */\ - MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0)) /*UART3_RTS_SD */\ - MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) /*UART3_RX_IRRX*/\ - MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) /*UART3_TX_IRTX*/\ - MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) /*I2C1_SCL*/\ - MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) /*I2C1_SDA*/\ - MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)) /*I2C2_SCL*/\ - MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)) /*I2C2_SDA*/\ - MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) /*I2C3_SCL*/\ - MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) /*I2C3_SDA*/\ - MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) /*I2C4_SCL*/\ - MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) /*I2C4_SDA*/\ - MUX_VAL(CP(McBSP1_DX), (IEN | PTD | DIS | M4)) /*GPIO_158*/\ - MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) /*SYS_32K*/\ - MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /*GPIO_2 */\ - MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) /*GPIO_3 */\ - MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /*GPIO_4 */\ - MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) /*GPIO_5 */\ - MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /*GPIO_6 */\ - MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /*GPIO_7 */\ - MUX_VAL(CP(SYS_BOOT6), (IEN | PTD | DIS | M4)) /*GPIO_8 */\ - MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M4)) /*GPIO_186*/\ - MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0)) /*JTAG_nTRST*/\ - MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)) /*JTAG_TCK*/\ - MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)) /*JTAG_TMS*/\ - MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)) /*JTAG_TDI*/\ - MUX_VAL(CP(JTAG_EMU0), (IEN | PTD | DIS | M0)) /*JTAG_EMU0*/\ - MUX_VAL(CP(JTAG_EMU1), (IEN | PTD | DIS | M0)) /*JTAG_EMU1*/\ - MUX_VAL(CP(ETK_CLK), (IEN | PTD | DIS | M4)) /*GPIO_12*/\ - MUX_VAL(CP(ETK_CTL), (IEN | PTD | DIS | M4)) /*GPIO_13*/\ - MUX_VAL(CP(ETK_D0), (IEN | PTD | DIS | M4)) /*GPIO_14*/\ - MUX_VAL(CP(ETK_D1), (IEN | PTD | DIS | M4)) /*GPIO_15*/\ - MUX_VAL(CP(ETK_D2), (IEN | PTD | DIS | M4)) /*GPIO_16*/\ - MUX_VAL(CP(ETK_D10), (IEN | PTD | DIS | M4)) /*GPIO_24*/\ - MUX_VAL(CP(ETK_D11), (IEN | PTD | DIS | M4)) /*GPIO_25*/\ - MUX_VAL(CP(ETK_D12), (IEN | PTD | DIS | M4)) /*GPIO_26*/\ - MUX_VAL(CP(ETK_D13), (IEN | PTD | DIS | M4)) /*GPIO_27*/\ - MUX_VAL(CP(ETK_D14), (IEN | PTD | DIS | M4)) /*GPIO_28*/\ - MUX_VAL(CP(ETK_D15), (IEN | PTD | DIS | M4)) /*GPIO_29*/ - -/********************************************************** - * Routine: set_muxconf_regs - * Description: Setting up the configuration Mux registers - * specific to the hardware. Many pins need - * to be moved from protect to primary mode. - *********************************************************/ -void set_muxconf_regs(void) -{ - MUX_DEFAULT(); -} - -/********************************************************** - * Routine: nand+_init - * Description: Set up nand for nand and jffs2 commands - *********************************************************/ - -int nand_init(void) -{ - /* global settings */ - __raw_writel(0x10, GPMC_SYSCONFIG); /* smart idle */ - __raw_writel(0x0, GPMC_IRQENABLE); /* isr's sources masked */ - __raw_writel(0, GPMC_TIMEOUT_CONTROL);/* timeout disable */ - - /* Set the GPMC Vals, NAND is mapped at CS0, oneNAND at CS0. - * We configure only GPMC CS0 with required values. Configiring other devices - * at other CS is done in u-boot. So we don't have to bother doing it here. - */ - __raw_writel(0 , GPMC_CONFIG7 + GPMC_CONFIG_CS0); - delay(1000); - -#ifdef CFG_NAND_K9F1G08R0A - if ((get_mem_type() == GPMC_NAND) || (get_mem_type() == MMC_NAND)) { - __raw_writel(M_NAND_GPMC_CONFIG1, GPMC_CONFIG1 + GPMC_CONFIG_CS0); - __raw_writel(M_NAND_GPMC_CONFIG2, GPMC_CONFIG2 + GPMC_CONFIG_CS0); - __raw_writel(M_NAND_GPMC_CONFIG3, GPMC_CONFIG3 + GPMC_CONFIG_CS0); - __raw_writel(M_NAND_GPMC_CONFIG4, GPMC_CONFIG4 + GPMC_CONFIG_CS0); - __raw_writel(M_NAND_GPMC_CONFIG5, GPMC_CONFIG5 + GPMC_CONFIG_CS0); - __raw_writel(M_NAND_GPMC_CONFIG6, GPMC_CONFIG6 + GPMC_CONFIG_CS0); - - /* Enable the GPMC Mapping */ - __raw_writel((((OMAP34XX_GPMC_CS0_SIZE & 0xF)<<8) | - ((NAND_BASE_ADR>>24) & 0x3F) | - (1<<6)), (GPMC_CONFIG7 + GPMC_CONFIG_CS0)); - delay(2000); - - if (nand_chip()) { -#ifdef CFG_PRINTF - printf("Unsupported Chip!\n"); -#endif - return 1; - } - } -#endif - -#ifdef CFG_ONENAND - if ((get_mem_type() == GPMC_ONENAND) || (get_mem_type() == MMC_ONENAND)) { - __raw_writel(ONENAND_GPMC_CONFIG1, GPMC_CONFIG1 + GPMC_CONFIG_CS0); - __raw_writel(ONENAND_GPMC_CONFIG2, GPMC_CONFIG2 + GPMC_CONFIG_CS0); - __raw_writel(ONENAND_GPMC_CONFIG3, GPMC_CONFIG3 + GPMC_CONFIG_CS0); - __raw_writel(ONENAND_GPMC_CONFIG4, GPMC_CONFIG4 + GPMC_CONFIG_CS0); - __raw_writel(ONENAND_GPMC_CONFIG5, GPMC_CONFIG5 + GPMC_CONFIG_CS0); - __raw_writel(ONENAND_GPMC_CONFIG6, GPMC_CONFIG6 + GPMC_CONFIG_CS0); - - /* Enable the GPMC Mapping */ - __raw_writel((((OMAP34XX_GPMC_CS0_SIZE & 0xF)<<8) | - ((ONENAND_BASE>>24) & 0x3F) | - (1<<6)), (GPMC_CONFIG7 + GPMC_CONFIG_CS0)); - delay(2000); - - if (onenand_chip()) { -#ifdef CFG_PRINTF - printf("OneNAND Unsupported !\n"); -#endif - return 1; - } - } -#endif - - return 0; -} - -/* optionally do something like blinking LED */ -void board_hang(void) -{ - while (0) - ; -} - -/****************************************************************************** - * Dummy function to handle errors for EABI incompatibility - *****************************************************************************/ -void raise(void) -{ -} - -/****************************************************************************** - * Dummy function to handle errors for EABI incompatibility - *****************************************************************************/ -void abort(void) -{ -} diff --git a/x-loader/board/overo/platform.S b/x-loader/board/overo/platform.S deleted file mode 100644 index 5869270..0000000 --- a/x-loader/board/overo/platform.S +++ /dev/null @@ -1,360 +0,0 @@ -/* - * Board specific setup info - * - * (C) Copyright 2004-2006 - * Texas Instruments, <www.ti.com> - * Richard Woodruff <r-woodruff2@ti.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <config.h> -#include <asm/arch/cpu.h> -#include <asm/arch/mem.h> -#include <asm/arch/clocks.h> - -_TEXT_BASE: - .word TEXT_BASE /* sdram load addr from config.mk */ - -#if !defined(CFG_NAND_BOOT) && !defined(CFG_NAND_BOOT) -/************************************************************************** - * cpy_clk_code: relocates clock code into SRAM where its safer to execute - * R1 = SRAM destination address. - *************************************************************************/ -.global cpy_clk_code - cpy_clk_code: - /* Copy DPLL code into SRAM */ - adr r0, go_to_speed /* get addr of clock setting code */ - mov r2, #384 /* r2 size to copy (div by 32 bytes) */ - mov r1, r1 /* r1 <- dest address (passed in) */ - add r2, r2, r0 /* r2 <- source end address */ -next2: - ldmia r0!, {r3-r10} /* copy from source address [r0] */ - stmia r1!, {r3-r10} /* copy to target address [r1] */ - cmp r0, r2 /* until source end address [r2] */ - bne next2 - mov pc, lr /* back to caller */ - -/* **************************************************************************** - * NOTE: 3430 X-loader currently does not use this code. -* It could be removed its is kept for compatabily with u-boot. - * - * go_to_speed: -Moves to bypass, -Commits clock dividers, -puts dpll at speed - * -executed from SRAM. - * R0 = CM_CLKEN_PLL-bypass value - * R1 = CM_CLKSEL1_PLL-m, n, and divider values - * R2 = CM_CLKSEL_CORE-divider values - * R3 = CM_IDLEST_CKGEN - addr dpll lock wait - * - * Note: If core unlocks/relocks and SDRAM is running fast already it gets - * confused. A reset of the controller gets it back. Taking away its - * L3 when its not in self refresh seems bad for it. Normally, this code - * runs from flash before SDR is init so that should be ok. - ******************************************************************************/ -.global go_to_speed - go_to_speed: - stmfd sp!, {r4-r6} - - /* move into fast relock bypass */ - ldr r4, pll_ctl_add - str r0, [r4] -wait1: - ldr r5, [r3] /* get status */ - and r5, r5, #0x1 /* isolate core status */ - cmp r5, #0x1 /* still locked? */ - beq wait1 /* if lock, loop */ - - /* set new dpll dividers _after_ in bypass */ - ldr r5, pll_div_add1 - str r1, [r5] /* set m, n, m2 */ - ldr r5, pll_div_add2 - str r2, [r5] /* set l3/l4/.. dividers*/ - ldr r5, pll_div_add3 /* wkup */ - ldr r2, pll_div_val3 /* rsm val */ - str r2, [r5] - ldr r5, pll_div_add4 /* gfx */ - ldr r2, pll_div_val4 - str r2, [r5] - ldr r5, pll_div_add5 /* emu */ - ldr r2, pll_div_val5 - str r2, [r5] - - /* now prepare GPMC (flash) for new dpll speed */ - /* flash needs to be stable when we jump back to it */ - ldr r5, flash_cfg3_addr - ldr r2, flash_cfg3_val - str r2, [r5] - ldr r5, flash_cfg4_addr - ldr r2, flash_cfg4_val - str r2, [r5] - ldr r5, flash_cfg5_addr - ldr r2, flash_cfg5_val - str r2, [r5] - ldr r5, flash_cfg1_addr - ldr r2, [r5] - orr r2, r2, #0x3 /* up gpmc divider */ - str r2, [r5] - - /* lock DPLL3 and wait a bit */ - orr r0, r0, #0x7 /* set up for lock mode */ - str r0, [r4] /* lock */ - nop /* ARM slow at this point working at sys_clk */ - nop - nop - nop -wait2: - ldr r5, [r3] /* get status */ - and r5, r5, #0x1 /* isolate core status */ - cmp r5, #0x1 /* still locked? */ - bne wait2 /* if lock, loop */ - nop - nop - nop - nop - ldmfd sp!, {r4-r6} - mov pc, lr /* back to caller, locked */ - -_go_to_speed: .word go_to_speed - -/* these constants need to be close for PIC code */ -/* The Nor has to be in the Flash Base CS0 for this condition to happen */ -flash_cfg1_addr: - .word (GPMC_CONFIG_CS0 + GPMC_CONFIG1) -flash_cfg3_addr: - .word (GPMC_CONFIG_CS0 + GPMC_CONFIG3) -flash_cfg3_val: - .word STNOR_GPMC_CONFIG3 -flash_cfg4_addr: - .word (GPMC_CONFIG_CS0 + GPMC_CONFIG4) -flash_cfg4_val: - .word STNOR_GPMC_CONFIG4 -flash_cfg5_val: - .word STNOR_GPMC_CONFIG5 -flash_cfg5_addr: - .word (GPMC_CONFIG_CS0 + GPMC_CONFIG5) -pll_ctl_add: - .word CM_CLKEN_PLL -pll_div_add1: - .word CM_CLKSEL1_PLL -pll_div_add2: - .word CM_CLKSEL_CORE -pll_div_add3: - .word CM_CLKSEL_WKUP -pll_div_val3: - .word (WKUP_RSM << 1) -pll_div_add4: - .word CM_CLKSEL_GFX -pll_div_val4: - .word (GFX_DIV << 0) -pll_div_add5: - .word CM_CLKSEL1_EMU -pll_div_val5: - .word CLSEL1_EMU_VAL - -#endif - -.globl lowlevel_init -lowlevel_init: - ldr sp, SRAM_STACK - str ip, [sp] /* stash old link register */ - mov ip, lr /* save link reg across call */ - bl s_init /* go setup pll,mux,memory */ - ldr ip, [sp] /* restore save ip */ - mov lr, ip /* restore link reg */ - - /* back to arch calling code */ - mov pc, lr - - /* the literal pools origin */ - .ltorg - -REG_CONTROL_STATUS: - .word CONTROL_STATUS -SRAM_STACK: - .word LOW_LEVEL_SRAM_STACK - -/* DPLL(1-4) PARAM TABLES */ -/* Each of the tables has M, N, FREQSEL, M2 values defined for nominal - * OPP (1.2V). The fields are defined according to dpll_param struct(clock.c). - * The values are defined for all possible sysclk and for ES1 and ES2. - */ - -mpu_dpll_param: -/* 12MHz */ -/* ES1 */ -.word 0x0FE,0x07,0x05,0x01 -/* ES2 */ -.word 0x0FA,0x05,0x07,0x01 -/* 3410 */ -.word 0x085,0x05,0x07,0x01 - -/* 13MHz */ -/* ES1 */ -.word 0x17D,0x0C,0x03,0x01 -/* ES2 */ -.word 0x1F4,0x0C,0x03,0x01 -/* 3410 */ -.word 0x10A,0x0C,0x03,0x01 - -/* 19.2MHz */ -/* ES1 */ -.word 0x179,0x12,0x04,0x01 -/* ES2 */ -.word 0x271,0x17,0x03,0x01 -/* 3410 */ -.word 0x14C,0x17,0x03,0x01 - -/* 26MHz */ -/* ES1 */ -.word 0x17D,0x19,0x03,0x01 -/* ES2 */ -.word 0x0FA,0x0C,0x07,0x01 -/* 3410 */ -.word 0x085,0x0C,0x07,0x01 - -/* 38.4MHz */ -/* ES1 */ -.word 0x1FA,0x32,0x03,0x01 -/* ES2 */ -.word 0x271,0x2F,0x03,0x01 -/* 3410 */ -.word 0x14C,0x2F,0x03,0x01 - - -.globl get_mpu_dpll_param -get_mpu_dpll_param: - adr r0, mpu_dpll_param - mov pc, lr - -iva_dpll_param: -/* 12MHz */ -/* ES1 */ -.word 0x07D,0x05,0x07,0x01 -/* ES2 */ -.word 0x0B4,0x05,0x07,0x01 -/* 3410 */ -.word 0x085,0x05,0x07,0x01 - -/* 13MHz */ -/* ES1 */ -.word 0x0FA,0x0C,0x03,0x01 -/* ES2 */ -.word 0x168,0x0C,0x03,0x01 -/* 3410 */ -.word 0x10A,0x0C,0x03,0x01 - -/* 19.2MHz */ -/* ES1 */ -.word 0x082,0x09,0x07,0x01 -/* ES2 */ -.word 0x0E1,0x0B,0x06,0x01 -/* 3410 */ -.word 0x14C,0x17,0x03,0x01 - -/* 26MHz */ -/* ES1 */ -.word 0x07D,0x0C,0x07,0x01 -/* ES2 */ -.word 0x0B4,0x0C,0x07,0x01 -/* 3410 */ -.word 0x085,0x0C,0x07,0x01 - -/* 38.4MHz */ -/* ES1 */ -.word 0x13F,0x30,0x03,0x01 -/* ES2 */ -.word 0x0E1,0x17,0x06,0x01 -/* 3410 */ -.word 0x14C,0x2F,0x03,0x01 - - -.globl get_iva_dpll_param -get_iva_dpll_param: - adr r0, iva_dpll_param - mov pc, lr - -/* Core DPLL targets for L3 at 166 & L133 */ -core_dpll_param: -/* 12MHz */ -/* ES1 */ -.word M_12_ES1,M_12_ES1,FSL_12_ES1,M2_12_ES1 -/* ES2 */ -.word M_12,N_12,FSEL_12,M2_12 -/* 3410 */ -.word M_12,N_12,FSEL_12,M2_12 - -/* 13MHz */ -/* ES1 */ -.word M_13_ES1,N_13_ES1,FSL_13_ES1,M2_13_ES1 -/* ES2 */ -.word M_13,N_13,FSEL_13,M2_13 -/* 3410 */ -.word M_13,N_13,FSEL_13,M2_13 - -/* 19.2MHz */ -/* ES1 */ -.word M_19p2_ES1,N_19p2_ES1,FSL_19p2_ES1,M2_19p2_ES1 -/* ES2 */ -.word M_19p2,N_19p2,FSEL_19p2,M2_19p2 -/* 3410 */ -.word M_19p2,N_19p2,FSEL_19p2,M2_19p2 - -/* 26MHz */ -/* ES1 */ -.word M_26_ES1,N_26_ES1,FSL_26_ES1,M2_26_ES1 -/* ES2 */ -.word M_26,N_26,FSEL_26,M2_26 -/* 3410 */ -.word M_26,N_26,FSEL_26,M2_26 - -/* 38.4MHz */ -/* ES1 */ -.word M_38p4_ES1,N_38p4_ES1,FSL_38p4_ES1,M2_38p4_ES1 -/* ES2 */ -.word M_38p4,N_38p4,FSEL_38p4,M2_38p4 -/* 3410 */ -.word M_38p4,N_38p4,FSEL_38p4,M2_38p4 - -.globl get_core_dpll_param -get_core_dpll_param: - adr r0, core_dpll_param - mov pc, lr - -/* PER DPLL values are same for both ES1 and ES2 */ -per_dpll_param: -/* 12MHz */ -.word 0xD8,0x05,0x07,0x09 - -/* 13MHz */ -.word 0x1B0,0x0C,0x03,0x09 - -/* 19.2MHz */ -.word 0xE1,0x09,0x07,0x09 - -/* 26MHz */ -.word 0xD8,0x0C,0x07,0x09 - -/* 38.4MHz */ -.word 0xE1,0x13,0x07,0x09 - -.globl get_per_dpll_param -get_per_dpll_param: - adr r0, per_dpll_param - mov pc, lr - diff --git a/x-loader/board/overo/x-load.lds b/x-loader/board/overo/x-load.lds deleted file mode 100644 index 5f352d3..0000000 --- a/x-loader/board/overo/x-load.lds +++ /dev/null @@ -1,54 +0,0 @@ -/* - * November 2006 - Changed to support 3430sdp device - * Copyright (c) 2004-2006 Texas Instruments - * - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, <gj@denx.de> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN(4); - .text : - { - cpu/omap3/start.o (.text) - *(.text) - } - - . = ALIGN(4); - .rodata : { *(.rodata) } - - . = ALIGN(4); - .data : { *(.data) } - - . = ALIGN(4); - .got : { *(.got) } - - . = ALIGN(4); - __bss_start = .; - .bss : { *(.bss) } - _end = .; -} |