tree moved to a better location

9 files changed, 0 insertions, 1681 deletions

diff --git a/x-loader/include/configs/omap2420h4.h b/x-loader/include/configs/omap2420h4.h
deleted file mode 100644
index 7495d7f..0000000
--- a/x-loader/include/configs/omap2420h4.h
+++ /dev/null
@@ -1,140 +0,0 @@
-/*
- * Copyright (C) 2004 - 2005 Texas Instruments.
- * 
- * X-Loader Configuation settings for the TI OMAP H4 board.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/* serial printf facility takes about 3.5K */
-#define CFG_PRINTF 
-//#undef CFG_PRINTF 
-
-/* uncomment it if you need timer based udelay(). it takes about 250 bytes */
-//#define CFG_UDELAY
- 
-/*
- * High Level Configuration Options
- */
-#define CONFIG_ARM1136           1    /* This is an arm1136 CPU core */
-#define CONFIG_OMAP              1    /* in a TI OMAP core */
-#define CONFIG_OMAP2420	         1    /* which is in a 2420 */
-#define CONFIG_OMAP2420H4        1    /* and on a H4 board */
-
-#define CONFIG_OMAP242X
-
-#define PRCM_CONFIG_II           1    
-//#define PRCM_CONFIG_III           1    
-#define CONFIG_PARTIAL_SRAM      1
-
-//#define CFG_SDRAM_DDR			1
-#define CFG_SDRAM_COMBO		2
-//#define CFG_SDRAM_SDR			3
-//#define CFG_SDRAM_STACKED		4
-	 
-/* Chipselect and NAND information :
-   Since we share the mem.h from u-boot, we define few macros here
-   so as to pick the right gpmc values from there for the macros in mem.h
-*/
-/* NAND fixed at CS5 */
-#define OMAP24XX_GPMC_CS0 SMNAND
-#define OMAP24XX_GPMC_CS0_SIZE GPMC_SIZE_64M
-#define OMAP24XX_GPMC_CS0_MAP CFG_FLASH_BASE
-#define CFG_NAND_BOOT
-#define NAND_LEGACY
-
-#include <asm/arch/omap2420.h>        /* get chip and board defs */
-
-#define V_SCLK                   12000000
-/* input clock of PLL */
-/* the OMAP2420 H4 has 12MHz, 13MHz, or 19.2Mhz crystal input */
-#define CONFIG_SYS_CLK_FREQ      V_SCLK
-
-#ifdef CFG_PRINTF
-
-#define CFG_NS16550
-#define CFG_NS16550_SERIAL
-#define CFG_NS16550_REG_SIZE	(-4)
-#define CFG_NS16550_CLK		(48000000)	/* can be 12M/32Khz or 48Mhz */
-#define CFG_NS16550_COM1         OMAP2420_UART1
- 
-/*
- * select serial console configuration
- */
-#define CONFIG_SERIAL1           1    /* UART1 on H4 */
-
-#define CONFIG_CONS_INDEX        1
-#define CONFIG_BAUDRATE          115200
-#define CFG_PBSIZE	256
-
-#endif /* CFG_PRINTF */
-
-/*
- * Miscellaneous configurable options
- */
-#define CFG_LOADADDR 	0x80000000
-  
-#undef	CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */
- 
-/*-----------------------------------------------------------------------
- * Stack sizes
- *
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE	(128*1024)	/* regular stack */
-
-/*-----------------------------------------------------------------------
- * Board NAND Info.
- */
-#define CFG_NAND_K9K1216    /* Samsung 16-bit 64MB chip */
-
-#define NAND_ADDR 0x04000000  /* physical address to access nand at CS0*/
- 
-/* H4 NAND is partitioned:
- * 0x0000000 - 0x0010000 	Booting Image
- * 0x0010000 - 0x0050000 	U-Boot Image
- * 0x0050000 - 0x0080000 	U-Boot Env Data (X-loader doesn't care)
- * 0x0080000 - 0x4000000 	depends on application
- */
-#define NAND_UBOOT_START	0x0040000
-#define NAND_UBOOT_END		0x0080000
-#define NAND_BLOCK_SIZE		0x4000
-  
-#define WRITE_NAND_COMMAND(d, adr) do {*(volatile u16 *)0x6800A07C = d;} while(0)
-#define WRITE_NAND_ADDRESS(d, adr) do {*(volatile u16 *)0x6800A080 = d;} while(0)
-#define WRITE_NAND(d, adr) do {*(volatile u16 *)0x6800A084 = d;} while(0)
-#define READ_NAND(adr) (*(volatile u16 *)0x6800A084)
-
-#define NAND_WAIT_READY()
-  
-#define NAND_WP_OFF()  do {*(volatile u32 *)(0x6800A050) |= 0x00000010;} while(0)
-#define NAND_WP_ON()  do {*(volatile u32 *)(0x6800A050) &= ~0x00000010;} while(0)
-  
-#define NAND_CTL_CLRALE(adr)    
-#define NAND_CTL_SETALE(adr)    
-#define NAND_CTL_CLRCLE(adr)         
-#define NAND_CTL_SETCLE(adr)         
-#define NAND_DISABLE_CE()     
-#define NAND_ENABLE_CE()       
-
-
-#endif							/* __CONFIG_H */
diff --git a/x-loader/include/configs/omap2430sdp.h b/x-loader/include/configs/omap2430sdp.h
deleted file mode 100644
index 3fda61f..0000000
--- a/x-loader/include/configs/omap2430sdp.h
+++ /dev/null
@@ -1,178 +0,0 @@
-/*
- * (C) Copyright 2004 Texas Instruments.
- * 
- * X-Loader Configuation settings for the TI OMAP H4 board.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/* serial printf facility takes about 3.5K */
-#define CFG_PRINTF 
-//#undef CFG_PRINTF 
-
-/* uncomment it if you need timer based udelay(). it takes about 250 bytes */
-//#define CFG_UDELAY
- 
-/*
- * High Level Configuration Options
- */
-#define CONFIG_ARM1136           1    /* This is an arm1136 CPU core */
-#define CONFIG_OMAP              1    /* in a TI OMAP core */
-#define CONFIG_OMAP2430H4        1    /* and on a H4 board */
-
-#define CONFIG_OMAP243X 1
-
-//#define PRCM_CONFIG_5A		 1
-#define PRCM_CONFIG_2           1 /* 2430 ES2+330ARM+DDR-165-PISMO */
-
-#define OMAP2430_SQUARE_CLOCK_INPUT 1
-
-/* Memory type */
-//#define CFG_SDRAM_DDR			1 /* not tested */
-//#define CFG_SDRAM_COMBO		2 /* not tested */
-#define CFG_2430SDRAM_DDR		3
-//#define CFG_SDRAM_STACKED		4 /* not tested */
-
-/* The actual register values are defined in u-boot- mem.h */
-/* SDRAM Bank Allocation method */
-//#define SDRC_B_R_C          1
-//#define SDRC_B1_R_B0_C      1
-#define SDRC_R_B_C            1
-
-/* Boot type */
-//#define CFG_NAND 1
-#define CFG_ONENAND 1
-
-# define NAND_BASE            0x0C000000  /* NAND flash */
-# define ONENAND_BASE	      0x20000000  /* OneNand flash */
-
-#ifdef CFG_NAND
-#define NAND_LEGACY
-#define OMAP24XX_GPMC_CS0_SIZE GPMC_SIZE_64M
-#define OMAP24XX_GPMC_CS0_MAP NAND_BASE
-#else
-#define OMAP24XX_GPMC_CS0_SIZE GPMC_SIZE_128M
-#define OMAP24XX_GPMC_CS0_MAP ONENAND_BASE
-#define ONENAND_ADDR ONENAND_BASE  /* physical address to access OneNAND at CS0*/
-#endif
-
-/* Another dependency on u-boot */
-#define sdelay delay
-	 
-#include <asm/arch/omap2430.h>        /* get chip and board defs */
-
-#define V_SCLK                   13000000
-/* input clock of PLL */
-/* the OMAP2420 H4 has 12MHz, 13MHz, or 19.2Mhz crystal input */
-#define CONFIG_SYS_CLK_FREQ      V_SCLK
-
-#ifdef CFG_PRINTF
-
-#define CFG_NS16550
-#define CFG_NS16550_SERIAL
-#define CFG_NS16550_REG_SIZE	(-4)
-#define CFG_NS16550_CLK		(48000000)	/* can be 12M/32Khz or 48Mhz */
-#define CFG_NS16550_COM1         OMAP2430_UART1
- 
-/*
- * select serial console configuration
- */
-#define CONFIG_SERIAL1           1    /* UART1 on 2430SDP */
-#define CONFIG_CONS_INDEX        1
-#define CONFIG_BAUDRATE          115200
-#define CFG_PBSIZE	256
-
-#endif /* CFG_PRINTF */
-
-/*
- * Miscellaneous configurable options
- */
-#define CFG_LOADADDR 	0x80008000
-  
-#undef	CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */
- 
-/*-----------------------------------------------------------------------
- * Stack sizes
- *
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE	(128*1024)	/* regular stack */
-
-#ifdef CFG_NAND
-
-/*-----------------------------------------------------------------------
- * Board NAND Info.
- */
-#define CFG_NAND_K9K1216    /* Samsung 16-bit 64MB chip */
-
-/* NAND is partitioned:
- * 0x0000000 - 0x0010000 	Booting Image
- * 0x0010000 - 0x0050000 	U-Boot Image
- * 0x0050000 - 0x0080000 	U-Boot Env Data (X-loader doesn't care)
- * 0x0080000 - 0x00B0000 	Kernel Image
- * 0x00B0000 - 0x4000000 	depends on application
- */
-#define NAND_UBOOT_START	0x0040000
-#define NAND_UBOOT_END		0x0080000
-#define NAND_BLOCK_SIZE		0x4000
-  
-#define GPMC_CONFIG		(OMAP24XX_GPMC_BASE+0x50)
-#define GPMC_NAND_COMMAND_0	(OMAP24XX_GPMC_BASE+0x7C)
-#define GPMC_NAND_ADDRESS_0	(OMAP24XX_GPMC_BASE+0x80)
-#define GPMC_NAND_DATA_0	(OMAP24XX_GPMC_BASE+0x84)
-
-#define WRITE_NAND_COMMAND(d, adr) do {*(volatile u16 *)GPMC_NAND_COMMAND_0 = d;} while(0)
-#define WRITE_NAND_ADDRESS(d, adr) do {*(volatile u16 *)GPMC_NAND_ADDRESS_0 = d;} while(0)
-#define WRITE_NAND(d, adr) do {*(volatile u16 *)GPMC_NAND_DATA_0 = d;} while(0)
-#define READ_NAND(adr) (*(volatile u16 *)GPMC_NAND_DATA_0)
-#define NAND_WAIT_READY()
-#define NAND_WP_OFF()  do {*(volatile u32 *)(GPMC_CONFIG) |= 0x00000010;} while(0)
-#define NAND_WP_ON()  do {*(volatile u32 *)(GPMC_CONFIG) &= ~0x00000010;} while(0)
-
-#define NAND_CTL_CLRALE(adr)    
-#define NAND_CTL_SETALE(adr)    
-#define NAND_CTL_CLRCLE(adr)         
-#define NAND_CTL_SETCLE(adr)         
-#define NAND_DISABLE_CE()     
-#define NAND_ENABLE_CE()       
-
-#else
-/*-----------------------------------------------------------------------
- * Board oneNAND Info.
- */
-#define CFG_SYNC_BURST_READ     1
-
-/* OneNAND is partitioned:
- *   0x0000000 - 0x0080000        X-Loader 
- *   0x0080000 - 0x00c0000        U-boot Image
- *   0x00c0000 - 0x00e0000        U-Boot Env Data (X-loader doesn't care)
- *   0x00e0000 - 0x0120000        Kernel Image
- *   0x0120000 - 0x4000000        depends on application
- */
-
-#define ONENAND_START_BLOCK             4
-#define ONENAND_END_BLOCK             	6
-#define ONENAND_PAGE_SIZE               2048            /* 2KB */
-#define ONENAND_BLOCK_SIZE              0x20000         /* 128KB */
-
-#endif // oneNAND
-#endif							/* __CONFIG_H */
diff --git a/x-loader/include/configs/omap3430labrador.h b/x-loader/include/configs/omap3430labrador.h
deleted file mode 100644
index b5a9c54..0000000
--- a/x-loader/include/configs/omap3430labrador.h
+++ /dev/null
@@ -1,211 +0,0 @@
-/*
- * (C) Copyright 2006 
- * Texas Instruments <www.ti.com>
- * Richard Woodruff <r-woodruff2@ti.com>
- *
- * X-Loader Configuation settings for the TI OMAP SDP3430 board.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/* configure for GTA04 with DM3730 */
-#define CONFIG_OMAP36XX			 1	  /* or 36XX (DM3730) */
-#define PRCM_CLK_CFG2_400MHZ     1
-
-/* serial printf facility takes about 3.5K */
-#define CFG_PRINTF 
-//#undef CFG_PRINTF 
-
-/*
- * High Level Configuration Options
- */
-#define CONFIG_ARMCORTEXA8       1    /* This is an ARM V7 CPU core */
-#define CONFIG_OMAP              1    /* in a TI OMAP core */
-#define CONFIG_OMAP34XX          1    /* which is a 34XX */
-#define CONFIG_OMAP3430          1    /* which is in a 3430 */
-#define CONFIG_3430LABRADOR      1    /* working on Labrador */
-//#define CONFIG_3430_AS_3410    1    /* true for 3430 in 3410 mode */
-
-#include <asm/arch/cpu.h>        /* get chip and board defs */
-
-/* uncomment it if you need timer based udelay(). it takes about 250 bytes */
-//#define CFG_UDELAY
- 
-/* Clock Defines */
-#define V_OSCK                   26000000  /* Clock output from T2 */
-
-#if (V_OSCK > 19200000)          
-#define V_SCLK                   (V_OSCK >> 1)
-#else
-#define V_SCLK                   V_OSCK
-#endif
-
-#define PRCM_CLK_CFG2_266MHZ     1    /* VDD2=1.15v - 133MHz DDR */
-//#define PRCM_CLK_CFG2_332MHZ   1    /* VDD2=1.15v - 166MHz DDR */
-#define PRCM_PCLK_OPP2           1    /* ARM=500MHz - VDD1=1.20v */
-
-/* Memory type */
-#define CFG_3430SDRAM_DDR        1
-
-/* The actual register values are defined in u-boot- mem.h */
-/* SDRAM Bank Allocation method */
-//#define SDRC_B_R_C             1
-//#define SDRC_B1_R_B0_C         1
-#define SDRC_R_B_C               1
-
-/* Boot type */
-#define CFG_NAND 1
-//#define CFG_ONENAND 1
-
-# define NAND_BASE_ADR           NAND_BASE  /* NAND flash */
-# define ONENAND_BASE            ONENAND_MAP  /* OneNand flash */
-
-#ifdef CFG_NAND
-#define OMAP34XX_GPMC_CS0_SIZE GPMC_SIZE_128M  /* u = ofdon't need so much for nand port */
-#define OMAP34XX_GPMC_CS0_MAP NAND_BASE_ADR
-#else
-#define OMAP34XX_GPMC_CS0_SIZE GPMC_SIZE_128M
-#define OMAP34XX_GPMC_CS0_MAP ONENAND_BASE
-#define ONENAND_ADDR ONENAND_BASE  /* physical address of OneNAND at CS0*/
-#endif
-
-
-#ifdef CFG_PRINTF
-
-#define CFG_NS16550
-#define CFG_NS16550_SERIAL
-#define CFG_NS16550_REG_SIZE     (-4)
-#define CFG_NS16550_CLK          (48000000)
-#define CFG_NS16550_COM3         OMAP34XX_UART3
- 
-/*
- * select serial console configuration
- */
-#define CONFIG_SERIAL3           3    /* UART3 on board */
-#define CONFIG_CONS_INDEX        3
-
-#define CONFIG_BAUDRATE          115200
-#define CFG_PBSIZE               256
-
-#endif /* CFG_PRINTF */
-
-/*
- * Miscellaneous configurable options
- */
-#define CFG_LOADADDR             0x80008000
-  
-#undef	CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */
- 
-/*-----------------------------------------------------------------------
- * Stack sizes
- *
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE         (128*1024) /* regular stack */
-
-#ifdef CFG_NAND
-
-/*-----------------------------------------------------------------------
- * Board NAND Info.
- */
-
-
-#define CFG_NAND_K9F1G08R0A    /* Micron 16-bit 256MB chip large page NAND chip*/
-#define NAND_16BIT
-
-/* NAND is partitioned:
- * 0x00000000 - 0x0007FFFF  Booting Image
- * 0x00080000 - 0x000BFFFF  U-Boot Image
- * 0x000C0000 - 0x000FFFFF  U-Boot Env Data (X-loader doesn't care)
- * 0x00100000 - 0x002FFFFF  Kernel Image
- * 0x00300000 - 0x08000000  depends on application
- */
-#define NAND_UBOOT_START         0x0080000 /* Leaving first 4 blocks for x-load */
-#define NAND_UBOOT_END           0x00C0000 /* Giving a space of 2 blocks = 256KB */
-#define NAND_BLOCK_SIZE          0x20000
-  
-#define GPMC_CONFIG              (OMAP34XX_GPMC_BASE+0x50)
-#define GPMC_NAND_COMMAND_0      (OMAP34XX_GPMC_BASE+0x7C)
-#define GPMC_NAND_ADDRESS_0      (OMAP34XX_GPMC_BASE+0x80)
-#define GPMC_NAND_DATA_0         (OMAP34XX_GPMC_BASE+0x84)
-
-#ifdef NAND_16BIT
-#define WRITE_NAND_COMMAND(d, adr) \
-        do {*(volatile u16 *)GPMC_NAND_COMMAND_0 = d;} while(0)
-#define WRITE_NAND_ADDRESS(d, adr) \
-        do {*(volatile u16 *)GPMC_NAND_ADDRESS_0 = d;} while(0)
-#define WRITE_NAND(d, adr) \
-        do {*(volatile u16 *)GPMC_NAND_DATA_0 = d;} while(0)
-#define READ_NAND(adr) \
-        (*(volatile u16 *)GPMC_NAND_DATA_0)
-#define NAND_WAIT_READY()
-#define NAND_WP_OFF()  \
-        do {*(volatile u32 *)(GPMC_CONFIG) |= 0x00000010;} while(0)
-#define NAND_WP_ON()  \
-        do {*(volatile u32 *)(GPMC_CONFIG) &= ~0x00000010;} while(0)
-
-#else /* to support 8-bit NAND devices */
-#define WRITE_NAND_COMMAND(d, adr) \
-        do {*(volatile u8 *)GPMC_NAND_COMMAND_0 = d;} while(0)
-#define WRITE_NAND_ADDRESS(d, adr) \
-        do {*(volatile u8 *)GPMC_NAND_ADDRESS_0 = d;} while(0)
-#define WRITE_NAND(d, adr) \
-        do {*(volatile u8 *)GPMC_NAND_DATA_0 = d;} while(0)
-#define READ_NAND(adr) \
-        (*(volatile u8 *)GPMC_NAND_DATA_0);
-#define NAND_WAIT_READY()
-#define NAND_WP_OFF()  \
-        do {*(volatile u32 *)(GPMC_CONFIG) |= 0x00000010;} while(0)
-#define NAND_WP_ON()  \
-        do {*(volatile u32 *)(GPMC_CONFIG) &= ~0x00000010;} while(0)
-
-#endif
-
-#define NAND_CTL_CLRALE(adr) 
-#define NAND_CTL_SETALE(adr) 
-#define NAND_CTL_CLRCLE(adr) 
-#define NAND_CTL_SETCLE(adr) 
-#define NAND_DISABLE_CE() 
-#define NAND_ENABLE_CE() 
-
-#else
-/*-----------------------------------------------------------------------
- * Board oneNAND Info.
- */
-#define CFG_SYNC_BURST_READ      1
-
-/* OneNAND is partitioned:
- *   0x0000000 - 0x0080000  X-Loader 
- *   0x0080000 - 0x00c0000   U-boot Image
- *   0x00c0000 - 0x00e0000   U-Boot Env Data (X-loader doesn't care)
- *   0x00e0000 - 0x0120000   Kernel Image
- *   0x0120000 - 0x4000000   depends on application
- */
-
-#define ONENAND_START_BLOCK      4
-#define ONENAND_END_BLOCK        6
-#define ONENAND_PAGE_SIZE        2048     /* 2KB */
-#define ONENAND_BLOCK_SIZE       0x20000  /* 128KB */
-
-#endif  /* oneNAND */
-#endif /* __CONFIG_H */
-
diff --git a/x-loader/include/configs/omap3430sdp.h b/x-loader/include/configs/omap3430sdp.h
deleted file mode 100644
index ad880ed..0000000
--- a/x-loader/include/configs/omap3430sdp.h
+++ /dev/null
@@ -1,213 +0,0 @@
-/*
- * (C) Copyright 2006 
- * Texas Instruments <www.ti.com>
- * Richard Woodruff <r-woodruff2@ti.com>
- *
- * X-Loader Configuation settings for the TI OMAP SDP3430 board.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/* serial printf facility takes about 3.5K */
-#define CFG_PRINTF 
-//#undef CFG_PRINTF 
-
-/*
- * High Level Configuration Options
- */
-#define CONFIG_ARMCORTEXA8       1    /* This is an ARM V7 CPU core */
-#define CONFIG_OMAP              1    /* in a TI OMAP core */
-#define CONFIG_OMAP34XX          1    /* which is a 34XX */
-#define CONFIG_OMAP3430          1    /* which is in a 3430 */
-#define CONFIG_3430SDP           1    /* working with SDP */
-//#define CONFIG_3430_AS_3410	 1    /* true for 3430 in 3410 mode */
-
-/* Enable the below macro if MMC boot support is required */
-//#define CONFIG_MMC               1
-#if defined(CONFIG_MMC)
-	#define CFG_CMD_MMC              1
-	#define CFG_CMD_FAT              1
-#endif
-
-#include <asm/arch/cpu.h>        /* get chip and board defs */
-
-/* uncomment it if you need timer based udelay(). it takes about 250 bytes */
-//#define CFG_UDELAY
- 
-/* Clock Defines */
-#define V_OSCK                   19200000  /* Clock output from T2 */
-
-#if (V_OSCK > 19200000)          
-#define V_SCLK                   (V_OSCK >> 1)
-#else
-#define V_SCLK                   V_OSCK
-#endif
-
-//#define PRCM_CLK_CFG2_266MHZ   1    /* VDD2=1.15v - 133MHz DDR */
-#define PRCM_CLK_CFG2_332MHZ     1    /* VDD2=1.15v - 166MHz DDR */
-#define PRCM_PCLK_OPP2           1    /* ARM=381MHz - VDD1=1.20v */
-
-/* Memory type */
-#define CFG_3430SDRAM_DDR        1
-
-/* The actual register values are defined in u-boot- mem.h */
-/* SDRAM Bank Allocation method */
-//#define SDRC_B_R_C             1
-//#define SDRC_B1_R_B0_C         1
-#define SDRC_R_B_C               1
-
-/* Boot type */
-#define CFG_NAND 1
-//#define CFG_ONENAND 1
-
-# define NAND_BASE_ADR           NAND_BASE  /* NAND flash */
-# define ONENAND_BASE            ONENAND_MAP  /* OneNand flash */
-
-#ifdef CFG_NAND
-#define OMAP34XX_GPMC_CS0_SIZE GPMC_SIZE_128M
-#define OMAP34XX_GPMC_CS0_MAP NAND_BASE_ADR
-#else
-#define OMAP34XX_GPMC_CS0_SIZE GPMC_SIZE_128M
-#define OMAP34XX_GPMC_CS0_MAP ONENAND_BASE
-#define ONENAND_ADDR ONENAND_BASE  /* physical address of OneNAND at CS0*/
-#endif
- 
-#ifdef CFG_PRINTF
-
-#define CFG_NS16550
-#define CFG_NS16550_SERIAL
-#define CFG_NS16550_REG_SIZE     (-4)
-#define CFG_NS16550_CLK          (48000000)
-#define CFG_NS16550_COM1         OMAP34XX_UART1
- 
-/*
- * select serial console configuration
- */
-#define CONFIG_SERIAL1           1    /* UART1 on 3430SDP */
-#define CONFIG_CONS_INDEX        1
-
-#define CONFIG_BAUDRATE          115200
-#define CFG_PBSIZE               256
-
-#endif /* CFG_PRINTF */
-
-/*
- * Miscellaneous configurable options
- */
-#define CFG_LOADADDR             0x80008000
-  
-#undef	CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */
- 
-/*-----------------------------------------------------------------------
- * Stack sizes
- *
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE         (128*1024) /* regular stack */
-
-#ifdef CFG_NAND
-
-/*-----------------------------------------------------------------------
- * Board NAND Info.
- */
-
-
-#define CFG_NAND_K9F1G08R0A    /* Samsung 8-bit 128MB chip large page NAND chip*/
-#define NAND_8BIT
-
-/* NAND is partitioned:
- * 0x00000000 - 0x0007FFFF  Booting Image
- * 0x00080000 - 0x000BFFFF  U-Boot Image
- * 0x000C0000 - 0x000FFFFF  U-Boot Env Data (X-loader doesn't care)
- * 0x00100000 - 0x002FFFFF  Kernel Image
- * 0x00300000 - 0x08000000  depends on application
- */
-#define NAND_UBOOT_START         0x0080000 /* Leaving first 4 blocks for x-load */
-#define NAND_UBOOT_END           0x00C0000 /* Giving a space of 2 blocks = 256KB */
-#define NAND_BLOCK_SIZE          0x20000
-  
-#define GPMC_CONFIG              (OMAP34XX_GPMC_BASE+0x50)
-#define GPMC_NAND_COMMAND_0      (OMAP34XX_GPMC_BASE+0x7C)
-#define GPMC_NAND_ADDRESS_0      (OMAP34XX_GPMC_BASE+0x80)
-#define GPMC_NAND_DATA_0         (OMAP34XX_GPMC_BASE+0x84)
-
-#ifdef NAND_16BIT
-#define WRITE_NAND_COMMAND(d, adr) \
-        do {*(volatile u16 *)GPMC_NAND_COMMAND_0 = d;} while(0)
-#define WRITE_NAND_ADDRESS(d, adr) \
-        do {*(volatile u16 *)GPMC_NAND_ADDRESS_0 = d;} while(0)
-#define WRITE_NAND(d, adr) \
-        do {*(volatile u16 *)GPMC_NAND_DATA_0 = d;} while(0)
-#define READ_NAND(adr) \
-        (*(volatile u16 *)GPMC_NAND_DATA_0)
-#define NAND_WAIT_READY()
-#define NAND_WP_OFF()  \
-        do {*(volatile u32 *)(GPMC_CONFIG) |= 0x00000010;} while(0)
-#define NAND_WP_ON()  \
-        do {*(volatile u32 *)(GPMC_CONFIG) &= ~0x00000010;} while(0)
-
-#else /* to support 8-bit NAND devices */
-#define WRITE_NAND_COMMAND(d, adr) \
-        do {*(volatile u8 *)GPMC_NAND_COMMAND_0 = d;} while(0)
-#define WRITE_NAND_ADDRESS(d, adr) \
-        do {*(volatile u8 *)GPMC_NAND_ADDRESS_0 = d;} while(0)
-#define WRITE_NAND(d, adr) \
-        do {*(volatile u8 *)GPMC_NAND_DATA_0 = d;} while(0)
-#define READ_NAND(adr) \
-        (*(volatile u8 *)GPMC_NAND_DATA_0);
-#define NAND_WAIT_READY()
-#define NAND_WP_OFF()  \
-        do {*(volatile u32 *)(GPMC_CONFIG) |= 0x00000010;} while(0)
-#define NAND_WP_ON()  \
-        do {*(volatile u32 *)(GPMC_CONFIG) &= ~0x00000010;} while(0)
-
-#endif
-
-#define NAND_CTL_CLRALE(adr) 
-#define NAND_CTL_SETALE(adr) 
-#define NAND_CTL_CLRCLE(adr) 
-#define NAND_CTL_SETCLE(adr) 
-#define NAND_DISABLE_CE() 
-#define NAND_ENABLE_CE() 
-
-#else
-/*-----------------------------------------------------------------------
- * Board oneNAND Info.
- */
-#define CFG_SYNC_BURST_READ      1
-
-/* OneNAND is partitioned:
- *   0x0000000 - 0x0080000  X-Loader 
- *   0x0080000 - 0x00c0000   U-boot Image
- *   0x00c0000 - 0x00e0000   U-Boot Env Data (X-loader doesn't care)
- *   0x00e0000 - 0x0120000   Kernel Image
- *   0x0120000 - 0x4000000   depends on application
- */
-
-#define ONENAND_START_BLOCK      4
-#define ONENAND_END_BLOCK        6
-#define ONENAND_PAGE_SIZE        2048     /* 2KB */
-#define ONENAND_BLOCK_SIZE       0x20000  /* 128KB */
-
-#endif  /* oneNAND */
-#endif /* __CONFIG_H */
-
diff --git a/x-loader/include/configs/omap3530beagle.h b/x-loader/include/configs/omap3530beagle.h
deleted file mode 100644
index 5625417..0000000
--- a/x-loader/include/configs/omap3530beagle.h
+++ /dev/null
@@ -1,205 +0,0 @@
-/*
- * (C) Copyright 2006 
- * Texas Instruments <www.ti.com>
- * Richard Woodruff <r-woodruff2@ti.com>
- *
- * X-Loader Configuation settings for the TI OMAP SDP3430 board.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/* serial printf facility takes about 3.5K */
-#define CFG_PRINTF 
-//#undef CFG_PRINTF 
-
-/*
- * High Level Configuration Options
- */
-#define CONFIG_ARMCORTEXA8	1	/* This is an ARM V7 CPU core */
-#define CONFIG_OMAP		1	/* in a TI OMAP core */
-#define CONFIG_OMAP34XX		1	/* which is a 34XX */
-#define CONFIG_OMAP3430		1	/* which is in a 3430 */
-#define CONFIG_OMAP3_BEAGLE	1	/* working with BEAGLE */
-
-#define CONFIG_BEAGLE_REV2	1
-
-/* Enable the below macro if MMC boot support is required */
-#define CONFIG_MMC	1
-#if defined(CONFIG_MMC)
-	#define CFG_CMD_MMC		1
-	#define CFG_CMD_FAT		1
-	#define CFG_I2C_SPEED		100000
-	#define CFG_I2C_SLAVE		1
-	#define CFG_I2C_BUS		0
-	#define CFG_I2C_BUS_SELECT	1
-	#define CONFIG_DRIVER_OMAP34XX_I2C 1
-#endif
-
-#include <asm/arch/cpu.h>        /* get chip and board defs */
-
-/* uncomment it if you need timer based udelay(). it takes about 250 bytes */
-//#define CFG_UDELAY
- 
-/* Clock Defines */
-#define V_OSCK	26000000  /* Clock output from T2 */
-
-#if (V_OSCK > 19200000)
-#define V_SCLK	(V_OSCK >> 1)
-#else
-#define V_SCLK	V_OSCK
-#endif
-
-//#define PRCM_CLK_CFG2_266MHZ	1	/* VDD2=1.15v - 133MHz DDR */
-#define PRCM_CLK_CFG2_332MHZ	1	/* VDD2=1.15v - 166MHz DDR */
-#define PRCM_PCLK_OPP2		1	/* ARM=381MHz - VDD1=1.20v */
-
-/* Memory type */
-#define CFG_3430SDRAM_DDR	1
-
-/* The actual register values are defined in u-boot- mem.h */
-/* SDRAM Bank Allocation method */
-//#define SDRC_B_R_C		1
-//#define SDRC_B1_R_B0_C	1
-#define SDRC_R_B_C		1
-
-#define NAND_BASE_ADR	NAND_BASE
-#define ONENAND_BASE	ONENAND_MAP
-#define ONENAND_ADDR	ONENAND_BASE
-
-#define OMAP34XX_GPMC_CS0_SIZE GPMC_SIZE_128M
-
-#ifdef CFG_PRINTF
-
-#define CFG_NS16550
-#define CFG_NS16550_SERIAL
-#define CFG_NS16550_REG_SIZE	-4
-#define CFG_NS16550_CLK		48000000
-#define CFG_NS16550_COM3	OMAP34XX_UART3
-
-/*
- * select serial console configuration
- */
-#define CONFIG_SERIAL1		3	/* use UART3 */
-#define CONFIG_CONS_INDEX	3
-
-#define CONFIG_BAUDRATE		115200
-#define CFG_PBSIZE		256
-
-#endif /* CFG_PRINTF */
-
-/*
- * Miscellaneous configurable options
- */
-#define CFG_LOADADDR		0x80008000
-  
-#undef	CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */
- 
-/*-----------------------------------------------------------------------
- * Stack sizes
- *
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE	(128*1024) /* regular stack */
-
-/*-----------------------------------------------------------------------
- * Board NAND Info.
- */
-
-
-#define CFG_NAND_K9F1G08R0A
-#define NAND_16BIT
-
-/* NAND is partitioned:
- * 0x00000000 - 0x0007FFFF  Booting Image
- * 0x00080000 - 0x000BFFFF  U-Boot Image
- * 0x000C0000 - 0x000FFFFF  U-Boot Env Data (X-loader doesn't care)
- * 0x00100000 - 0x002FFFFF  Kernel Image
- * 0x00300000 - 0x08000000  depends on application
- */
-#define NAND_UBOOT_START	0x0080000 /* Leaving first 4 blocks for x-load */
-#define NAND_UBOOT_END		0x0160000 /* Giving a space of 2 blocks = 256KB */
-#define NAND_BLOCK_SIZE		0x20000
-  
-#define GPMC_CONFIG 		(OMAP34XX_GPMC_BASE+0x50)
-#define GPMC_NAND_COMMAND_0	(OMAP34XX_GPMC_BASE+0x7C)
-#define GPMC_NAND_ADDRESS_0	(OMAP34XX_GPMC_BASE+0x80)
-#define GPMC_NAND_DATA_0	(OMAP34XX_GPMC_BASE+0x84)
-
-#ifdef NAND_16BIT
-#define WRITE_NAND_COMMAND(d, adr) \
-	do {*(volatile u16 *)GPMC_NAND_COMMAND_0 = d; } while (0)
-#define WRITE_NAND_ADDRESS(d, adr) \
-	do {*(volatile u16 *)GPMC_NAND_ADDRESS_0 = d; } while (0)
-#define WRITE_NAND(d, adr) \
-	do {*(volatile u16 *)GPMC_NAND_DATA_0 = d; } while (0)
-#define READ_NAND(adr) \
-	(*(volatile u16 *)GPMC_NAND_DATA_0)
-#define NAND_WAIT_READY()
-#define NAND_WP_OFF()  \
-	do {*(volatile u32 *)(GPMC_CONFIG) |= 0x00000010; } while (0)
-#define NAND_WP_ON()  \
-	 do {*(volatile u32 *)(GPMC_CONFIG) &= ~0x00000010; } while (0)
-
-#else /* to support 8-bit NAND devices */
-#define WRITE_NAND_COMMAND(d, adr) \
-	do {*(volatile u8 *)GPMC_NAND_COMMAND_0 = d; } while (0)
-#define WRITE_NAND_ADDRESS(d, adr) \
-	 do {*(volatile u8 *)GPMC_NAND_ADDRESS_0 = d; } while (0)
-#define WRITE_NAND(d, adr) \
-	do {*(volatile u8 *)GPMC_NAND_DATA_0 = d; } while (0)
-#define READ_NAND(adr) \
-	(*(volatile u8 *)GPMC_NAND_DATA_0);
-#define NAND_WAIT_READY()
-#define NAND_WP_OFF()  \
-	do {*(volatile u32 *)(GPMC_CONFIG) |= 0x00000010; } while (0)
-#define NAND_WP_ON()  \
-	do {*(volatile u32 *)(GPMC_CONFIG) &= ~0x00000010; } while (0)
-
-#endif
-
-#define NAND_CTL_CLRALE(adr) 
-#define NAND_CTL_SETALE(adr) 
-#define NAND_CTL_CLRCLE(adr) 
-#define NAND_CTL_SETCLE(adr) 
-#define NAND_DISABLE_CE() 
-#define NAND_ENABLE_CE() 
-
-/*-----------------------------------------------------------------------
- * Board oneNAND Info.
- */
-#define CFG_SYNC_BURST_READ	1
-
-/* OneNAND is partitioned:
- *   0x0000000 - 0x0080000  X-Loader 
- *   0x0080000 - 0x00c0000   U-boot Image
- *   0x00c0000 - 0x00e0000   U-Boot Env Data (X-loader doesn't care)
- *   0x00e0000 - 0x0120000   Kernel Image
- *   0x0120000 - 0x4000000   depends on application
- */
-
-#define ONENAND_START_BLOCK 	4
-#define ONENAND_END_BLOCK	6
-#define ONENAND_PAGE_SIZE	2048     /* 2KB */
-#define ONENAND_BLOCK_SIZE	0x20000  /* 128KB */
-
-#endif /* __CONFIG_H */
-
diff --git a/x-loader/include/configs/omap3530gta04.h b/x-loader/include/configs/omap3530gta04.h
deleted file mode 100644
index 3e6ef21..0000000
--- a/x-loader/include/configs/omap3530gta04.h
+++ /dev/null
@@ -1,216 +0,0 @@
-/*
- * (C) Copyright 2006 
- * Texas Instruments <www.ti.com>
- * Richard Woodruff <r-woodruff2@ti.com>
- *
- * X-Loader Configuation settings for the TI OMAP SDP3430 board.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/* configure for GTA04 with DM3730 */
-#define CONFIG_OMAP36XX			 1	  /* or 36XX (DM3730) */
-#define PRCM_CLK_CFG2_400MHZ     1
-
-/* serial printf facility takes about 3.5K */
-#define CFG_PRINTF 
-//#undef CFG_PRINTF 
-
-/*
- * High Level Configuration Options
- */
-#define CONFIG_ARMCORTEXA8	1	/* This is an ARM V7 CPU core */
-#define CONFIG_OMAP		1	/* in a TI OMAP core */
-#define CONFIG_OMAP34XX		1	/* which is a 34XX */
-//#define CONFIG_OMAP3430		1	/* which is in a 3430 */
-#define CONFIG_OMAP3_BEAGLE	1	/* working with BEAGLE */
-
-#define CONFIG_BEAGLE_REV2	1
-
-/* Enable the below macro if MMC boot support is required */
-//#define CONFIG_MMC 1
-#if defined(CONFIG_MMC)
-	#define CFG_CMD_MMC		1
-	#define CFG_CMD_FAT		1
-	#define CFG_I2C_SPEED		100000
-	#define CFG_I2C_SLAVE		1
-	#define CFG_I2C_BUS		0
-	#define CFG_I2C_BUS_SELECT	1
-	#define CONFIG_DRIVER_OMAP34XX_I2C 1
-#endif
-
-#include <asm/arch/cpu.h>        /* get chip and board defs */
-
-/* uncomment it if you need timer based udelay(). it takes about 250 bytes */
-//#define CFG_UDELAY
- 
-/* Clock Defines */
-#define V_OSCK	26000000  /* Clock output from T2 */
-
-#if (V_OSCK > 19200000)
-#define V_SCLK	(V_OSCK >> 1)
-#else
-#define V_SCLK	V_OSCK
-#endif
-
-//#define PRCM_CLK_CFG2_266MHZ	1	/* VDD2=1.15v - 133MHz DDR */
-#define PRCM_CLK_CFG2_332MHZ	1	/* VDD2=1.15v - 166MHz DDR */
-#define PRCM_PCLK_OPP2		1	/* ARM=381MHz - VDD1=1.20v */
-
-/* Memory type */
-#define CFG_3430SDRAM_DDR	1
-
-/* The actual register values are defined in u-boot- mem.h */
-/* SDRAM Bank Allocation method */
-//#define SDRC_B_R_C		1
-//#define SDRC_B1_R_B0_C	1
-#define SDRC_R_B_C		1
-
-/* Enable the below macro if NAND boot support is required */
-//#define CONFIG_NAND 1
-
-#define NAND_BASE_ADR	NAND_BASE
-#define ONENAND_BASE	ONENAND_MAP
-#define ONENAND_ADDR	ONENAND_BASE
-
-#define OMAP34XX_GPMC_CS0_SIZE GPMC_SIZE_128M
-
-#ifdef CFG_PRINTF
-
-#define CFG_NS16550
-#define CFG_NS16550_SERIAL
-#define CFG_NS16550_REG_SIZE	-4
-#define CFG_NS16550_CLK		48000000
-#define CFG_NS16550_COM3	OMAP34XX_UART3
-
-/*
- * select serial console configuration
- */
-#define CONFIG_SERIAL1		3	/* use UART3 */
-#define CONFIG_CONS_INDEX	3
-
-#define CONFIG_BAUDRATE		115200
-#define CFG_PBSIZE		256
-
-#endif /* CFG_PRINTF */
-
-/*
- * Miscellaneous configurable options
- */
-#define CFG_LOADADDR		0x80008000
-  
-#undef	CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */
- 
-/*-----------------------------------------------------------------------
- * Stack sizes
- *
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE	(128*1024) /* regular stack */
-
-#if defined(CONFIG_NAND)
-
-/*-----------------------------------------------------------------------
- * Board NAND Info.
- */
-
-
-#define CFG_NAND_K9F1G08R0A
-#define NAND_16BIT
-
-/* NAND is partitioned:
- * 0x00000000 - 0x0007FFFF  Booting Image
- * 0x00080000 - 0x000BFFFF  U-Boot Image
- * 0x000C0000 - 0x000FFFFF  U-Boot Env Data (X-loader doesn't care)
- * 0x00100000 - 0x002FFFFF  Kernel Image
- * 0x00300000 - 0x08000000  depends on application
- */
-#define NAND_UBOOT_START	0x0080000 /* Leaving first 4 blocks for x-load */
-#define NAND_UBOOT_END		0x0160000 /* Giving a space of 2 blocks = 256KB */
-#define NAND_BLOCK_SIZE		0x20000
-  
-#define GPMC_CONFIG 		(OMAP34XX_GPMC_BASE+0x50)
-#define GPMC_NAND_COMMAND_0	(OMAP34XX_GPMC_BASE+0x7C)
-#define GPMC_NAND_ADDRESS_0	(OMAP34XX_GPMC_BASE+0x80)
-#define GPMC_NAND_DATA_0	(OMAP34XX_GPMC_BASE+0x84)
-
-#ifdef NAND_16BIT
-#define WRITE_NAND_COMMAND(d, adr) \
-	do {*(volatile u16 *)GPMC_NAND_COMMAND_0 = d; } while (0)
-#define WRITE_NAND_ADDRESS(d, adr) \
-	do {*(volatile u16 *)GPMC_NAND_ADDRESS_0 = d; } while (0)
-#define WRITE_NAND(d, adr) \
-	do {*(volatile u16 *)GPMC_NAND_DATA_0 = d; } while (0)
-#define READ_NAND(adr) \
-	(*(volatile u16 *)GPMC_NAND_DATA_0)
-#define NAND_WAIT_READY()
-#define NAND_WP_OFF()  \
-	do {*(volatile u32 *)(GPMC_CONFIG) |= 0x00000010; } while (0)
-#define NAND_WP_ON()  \
-	 do {*(volatile u32 *)(GPMC_CONFIG) &= ~0x00000010; } while (0)
-
-#else /* to support 8-bit NAND devices */
-#define WRITE_NAND_COMMAND(d, adr) \
-	do {*(volatile u8 *)GPMC_NAND_COMMAND_0 = d; } while (0)
-#define WRITE_NAND_ADDRESS(d, adr) \
-	 do {*(volatile u8 *)GPMC_NAND_ADDRESS_0 = d; } while (0)
-#define WRITE_NAND(d, adr) \
-	do {*(volatile u8 *)GPMC_NAND_DATA_0 = d; } while (0)
-#define READ_NAND(adr) \
-	(*(volatile u8 *)GPMC_NAND_DATA_0);
-#define NAND_WAIT_READY()
-#define NAND_WP_OFF()  \
-	do {*(volatile u32 *)(GPMC_CONFIG) |= 0x00000010; } while (0)
-#define NAND_WP_ON()  \
-	do {*(volatile u32 *)(GPMC_CONFIG) &= ~0x00000010; } while (0)
-
-#endif
-
-#define NAND_CTL_CLRALE(adr) 
-#define NAND_CTL_SETALE(adr) 
-#define NAND_CTL_CLRCLE(adr) 
-#define NAND_CTL_SETCLE(adr) 
-#define NAND_DISABLE_CE() 
-#define NAND_ENABLE_CE() 
-
-/*-----------------------------------------------------------------------
- * Board oneNAND Info.
- */
-#define CFG_SYNC_BURST_READ	1
-
-/* OneNAND is partitioned:
- *   0x0000000 - 0x0080000  X-Loader 
- *   0x0080000 - 0x00c0000   U-boot Image
- *   0x00c0000 - 0x00e0000   U-Boot Env Data (X-loader doesn't care)
- *   0x00e0000 - 0x0120000   Kernel Image
- *   0x0120000 - 0x4000000   depends on application
- */
-
-#define ONENAND_START_BLOCK 	4
-#define ONENAND_END_BLOCK	6
-#define ONENAND_PAGE_SIZE	2048     /* 2KB */
-#define ONENAND_BLOCK_SIZE	0x20000  /* 128KB */
-
-#endif
-
-#endif /* __CONFIG_H */
-
diff --git a/x-loader/include/configs/omap3evm.h b/x-loader/include/configs/omap3evm.h
deleted file mode 100644
index 10e48ba..0000000
--- a/x-loader/include/configs/omap3evm.h
+++ /dev/null
@@ -1,207 +0,0 @@
-/*
- * Copyright (C) 2007 Mistral Solutions Pvt Ltd.
- *
- * X-Loader Configuation settings for the OMAP3EVM board.
- *
- * Derived from /include/configs/omap3430sdp.h
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/* serial printf facility takes about 3.5K */
-#define CFG_PRINTF
-//#undef CFG_PRINTF
-
-/*
- * High Level Configuration Options
- */
-#define CONFIG_ARMCORTEXA8       1    /* This is an ARM V7 CPU core */
-#define CONFIG_OMAP              1    /* in a TI OMAP core */
-#define CONFIG_OMAP34XX          1    /* which is a 34XX */
-#define CONFIG_OMAP3430          1    /* which is in a 3430 */
-//#define CONFIG_3430SDP           1    /* working with SDP */
-//#define CONFIG_3430_AS_3410	 1    /* true for 3430 in 3410 mode */
-
-#define CONFIG_OMAP3EVM          1    /* working with EVM */
-
-/* Enable the below macro if MMC boot support is required */
-#define CONFIG_MMC	1
-#if defined(CONFIG_MMC)
-	#define CFG_CMD_MMC	1
-	#define CFG_CMD_FAT	1
-	#define CFG_I2C_SPEED		100000
-	#define CFG_I2C_SLAVE		1
-	#define CFG_I2C_BUS		0
-	#define CFG_I2C_BUS_SELECT	1
-	#define CONFIG_DRIVER_OMAP34XX_I2C 1
-#endif
-
-#include <asm/arch/cpu.h>        /* get chip and board defs */
-
-/* uncomment it if you need timer based udelay(). it takes about 250 bytes */
-//#define CFG_UDELAY
-
-/* Clock Defines */
-#define V_OSCK                   26000000  /* Clock output from T2 */
-
-#if (V_OSCK > 19200000)
-#define V_SCLK                   (V_OSCK >> 1)
-#else
-#define V_SCLK                   V_OSCK
-#endif
-
-//#define PRCM_CLK_CFG2_266MHZ   1    /* VDD2=1.15v - 133MHz DDR */
-#define PRCM_CLK_CFG2_332MHZ     1    /* VDD2=1.15v - 166MHz DDR */
-#define PRCM_PCLK_OPP2           1    /* ARM=381MHz - VDD1=1.20v */
-
-/* Memory type */
-#define CFG_3430SDRAM_DDR        1
-
-/* The actual register values are defined in u-boot- mem.h */
-/* SDRAM Bank Allocation method */
-//#define SDRC_B_R_C             1
-//#define SDRC_B1_R_B0_C         1
-#define SDRC_R_B_C               1
-
-
-# define NAND_BASE_ADR           NAND_BASE  /* NAND flash */
-# define ONENAND_BASE            ONENAND_MAP  /* OneNand flash */
-
-#define OMAP34XX_GPMC_CS0_SIZE GPMC_SIZE_128M
-#define ONENAND_ADDR ONENAND_BASE  /* physical address of OneNAND at CS0*/
-
-#ifdef CFG_PRINTF
-
-#define CFG_NS16550
-#define CFG_NS16550_SERIAL
-#define CFG_NS16550_REG_SIZE     (-4)
-#define CFG_NS16550_CLK          (48000000)
-#define CFG_NS16550_COM1         OMAP34XX_UART1
-
-/*
- * select serial console configuration
- */
-#define CONFIG_SERIAL1           1    /* UART1 on OMAP3EVM */
-#define CONFIG_CONS_INDEX        1
-
-#define CONFIG_BAUDRATE          115200
-#define CFG_PBSIZE               256
-
-#endif /* CFG_PRINTF */
-
-/*
- * Miscellaneous configurable options
- */
-#define CFG_LOADADDR             0x80008000
-
-#undef	CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */
-
-/*-----------------------------------------------------------------------
- * Stack sizes
- *
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE         (128*1024) /* regular stack */
-
-/*-----------------------------------------------------------------------
- * Board NAND Info.
- */
-
-
-#define CFG_NAND_K9F1G08R0A    /* Samsung 8-bit 128MB chip large page NAND chip*/
-#define NAND_16BIT
-
-/* NAND is partitioned:
- * 0x00000000 - 0x0007FFFF  Booting Image
- * 0x00080000 - 0x0023FFFF  U-Boot Image
- * 0x00240000 - 0x0027FFFF  U-Boot Env Data (X-loader doesn't care)
- * 0x00280000 - 0x0077FFFF  Kernel Image
- * 0x00780000 - 0x08000000  depends on application
- */
-#define NAND_UBOOT_START         0x0080000 /* Leaving first 4 blocks for x-load */
-#define NAND_UBOOT_END           0x0240000 /* Giving a space of 2 blocks = 256KB */
-#define NAND_BLOCK_SIZE          0x20000
-
-#define GPMC_CONFIG              (OMAP34XX_GPMC_BASE+0x50)
-#define GPMC_NAND_COMMAND_0      (OMAP34XX_GPMC_BASE+0x7C)
-#define GPMC_NAND_ADDRESS_0      (OMAP34XX_GPMC_BASE+0x80)
-#define GPMC_NAND_DATA_0         (OMAP34XX_GPMC_BASE+0x84)
-
-#ifdef NAND_16BIT
-#define WRITE_NAND_COMMAND(d, adr) \
-        do {*(volatile u16 *)GPMC_NAND_COMMAND_0 = d;} while(0)
-#define WRITE_NAND_ADDRESS(d, adr) \
-        do {*(volatile u16 *)GPMC_NAND_ADDRESS_0 = d;} while(0)
-#define WRITE_NAND(d, adr) \
-        do {*(volatile u16 *)GPMC_NAND_DATA_0 = d;} while(0)
-#define READ_NAND(adr) \
-        (*(volatile u16 *)GPMC_NAND_DATA_0)
-#define NAND_WAIT_READY()
-#define NAND_WP_OFF()  \
-        do {*(volatile u32 *)(GPMC_CONFIG) |= 0x00000010;} while(0)
-#define NAND_WP_ON()  \
-        do {*(volatile u32 *)(GPMC_CONFIG) &= ~0x00000010;} while(0)
-
-#else /* to support 8-bit NAND devices */
-#define WRITE_NAND_COMMAND(d, adr) \
-        do {*(volatile u8 *)GPMC_NAND_COMMAND_0 = d;} while(0)
-#define WRITE_NAND_ADDRESS(d, adr) \
-        do {*(volatile u8 *)GPMC_NAND_ADDRESS_0 = d;} while(0)
-#define WRITE_NAND(d, adr) \
-        do {*(volatile u8 *)GPMC_NAND_DATA_0 = d;} while(0)
-#define READ_NAND(adr) \
-        (*(volatile u8 *)GPMC_NAND_DATA_0);
-#define NAND_WAIT_READY()
-#define NAND_WP_OFF()  \
-        do {*(volatile u32 *)(GPMC_CONFIG) |= 0x00000010;} while(0)
-#define NAND_WP_ON()  \
-        do {*(volatile u32 *)(GPMC_CONFIG) &= ~0x00000010;} while(0)
-
-#endif
-
-#define NAND_CTL_CLRALE(adr)
-#define NAND_CTL_SETALE(adr)
-#define NAND_CTL_CLRCLE(adr)
-#define NAND_CTL_SETCLE(adr)
-#define NAND_DISABLE_CE()
-#define NAND_ENABLE_CE()
-
-/*-----------------------------------------------------------------------
- * Board oneNAND Info.
- */
-#define CFG_SYNC_BURST_READ      1
-
-/* OneNAND is partitioned:
- *   0x0000000 - 0x0080000  X-Loader
- *   0x0080000 - 0x0240000   U-boot Image
- *   0x0240000 - 0x0280000   U-Boot Env Data (X-loader doesn't care)
- *   0x0280000 - 0x0780000   Kernel Image
- *   0x0780000 - 0x8000000   depends on application
- */
-
-#define ONENAND_START_BLOCK      4
-#define ONENAND_END_BLOCK        18
-#define ONENAND_PAGE_SIZE        2048     /* 2KB */
-#define ONENAND_BLOCK_SIZE       0x20000  /* 128KB */
-
-#endif /* __CONFIG_H */
-
diff --git a/x-loader/include/configs/omap4430panda.h b/x-loader/include/configs/omap4430panda.h
deleted file mode 100644
index 74e2f42..0000000
--- a/x-loader/include/configs/omap4430panda.h
+++ /dev/null
@@ -1,106 +0,0 @@
-/*
- * (C) Copyright 2006 
- * Texas Instruments <www.ti.com>
- * Richard Woodruff <r-woodruff2@ti.com>
- *
- * X-Loader Configuation settings for the TI OMAP SDP3430 board.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/* serial printf facility takes about 3.5K */
-#define CFG_PRINTF 
-//#undef CFG_PRINTF 
-
-/*
- * High Level Configuration Options
- */
-#define CONFIG_ARMCORTEXA9       1    /* This is an ARM V7 CPU core */
-#define CONFIG_OMAP              1    /* in a TI OMAP core */
-#define CONFIG_OMAP44XX          1    /* which is a 34XX */
-#define CONFIG_OMAP4430          1    /* which is in a 3430 */
-#define CONFIG_4430PANDA         1    /* working with SDP */
-
-/* Keep Default @ 33MHz at boot loader level
- * On Phoenix board vlotage needs to be bumped up
- * before scaling the MPU up
- */
-#define CONFIG_MPU_600		1
-#define CORE_190MHZ		1
-/* Enable the below macro if MMC boot support is required */
-#define CONFIG_MMC               1
-#if defined(CONFIG_MMC)
-	/* To Enable MMC boot for OMAP4430 Panda */
-	//#define CONFIG_MMC1		1
-	/* To Enable EMMC boot for OMAP4430 Panda */
-	#define CONFIG_MMC2		1
-	#define CFG_CMD_MMC		1
-	#define CFG_CMD_FAT		1
-#endif
-
-#include <asm/arch/cpu.h>        /* get chip and board defs */
-
-/* uncomment it if you need timer based udelay(). it takes about 250 bytes */
-//#define CFG_UDELAY
- 
-/* Clock Defines */
-#define V_OSCK                   19200000  /* Clock output from T2 */
-#define V_SCLK                   V_OSCK
-
-/* Memory type */
-#define CFG_4430SDRAM_DDR        1
-
-#ifdef CFG_PRINTF
-
-#define CFG_NS16550
-#define CFG_NS16550_SERIAL
-#define CFG_NS16550_REG_SIZE     (-4)
-#define CFG_NS16550_CLK          (48000000)
-#define CFG_NS16550_COM3         OMAP44XX_UART3
- 
-/*
- * select serial console configuration
- */
-#define CONFIG_SERIAL1           1    /* UART1 on 3430SDP */
-#define CONFIG_CONS_INDEX        3
-
-#define CONFIG_BAUDRATE          115200
-#define CFG_PBSIZE               256
-
-#endif /* CFG_PRINTF */
-
-/*
- * Miscellaneous configurable options
- */
-#define CFG_LOADADDR             0x80e80000
-  
-#undef	CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */
-#define CFG_ENV_SIZE		0x100 
-/*-----------------------------------------------------------------------
- * Stack sizes
- *
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE         (128*1024) /* regular stack */
-
-#endif /* __CONFIG_H */
-
diff --git a/x-loader/include/configs/overo.h b/x-loader/include/configs/overo.h
deleted file mode 100644
index 70e3683..0000000
--- a/x-loader/include/configs/overo.h
+++ /dev/null
@@ -1,205 +0,0 @@
-/*
- * (C) Copyright 2006 
- * Texas Instruments <www.ti.com>
- * Richard Woodruff <r-woodruff2@ti.com>
- *
- * X-Loader Configuation settings for the overo board.
- *
- * Derived from /include/configs/omap3evm.h
- * Steve Sakoman <steve@sakoman.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/* serial printf facility takes about 3.5K */
-#define CFG_PRINTF
-//#undef CFG_PRINTF
-
-/*
- * High Level Configuration Options
- */
-#define CONFIG_ARMCORTEXA8	1	/* This is an ARM V7 CPU core */
-#define CONFIG_OMAP		1	/* in a TI OMAP core */
-#define CONFIG_OMAP34XX		1	/* which is a 34XX */
-#define CONFIG_OMAP3430		1	/* which is in a 3430 */
-#define CONFIG_OVERO		1	/* working with overo */
-
-/* Enable the below macro if MMC boot support is required */
-#define CONFIG_MMC	1
-#if defined(CONFIG_MMC)
-	#define CFG_CMD_MMC	1
-	#define CFG_CMD_FAT	1
-	#define CFG_I2C_SPEED		100000
-	#define CFG_I2C_SLAVE		1
-	#define CFG_I2C_BUS		0
-	#define CFG_I2C_BUS_SELECT	1
-	#define CONFIG_DRIVER_OMAP34XX_I2C 1
-#endif
-
-#include <asm/arch/cpu.h>        /* get chip and board defs */
-
-/* uncomment it if you need timer based udelay(). it takes about 250 bytes */
-//#define CFG_UDELAY
-
-/* Clock Defines */
-#define V_OSCK	26000000  /* Clock output from T2 */
-
-#if (V_OSCK > 19200000)
-#define V_SCLK	(V_OSCK >> 1)
-#else
-#define V_SCLK	V_OSCK
-#endif
-
-//#define PRCM_CLK_CFG2_266MHZ	1	/* VDD2=1.15v - 133MHz DDR */
-#define PRCM_CLK_CFG2_332MHZ	1	/* VDD2=1.15v - 166MHz DDR */
-#define PRCM_PCLK_OPP2		1	/* ARM=381MHz - VDD1=1.20v */
-
-/* Memory type */
-#define CFG_3430SDRAM_DDR	1
-
-/* The actual register values are defined in u-boot- mem.h */
-/* SDRAM Bank Allocation method */
-//#define SDRC_B_R_C		1
-//#define SDRC_B1_R_B0_C	1
-#define SDRC_R_B_C		1
-
-#define NAND_BASE_ADR	NAND_BASE
-#define ONENAND_BASE	ONENAND_MAP
-#define ONENAND_ADDR	ONENAND_BASE
-
-#define OMAP34XX_GPMC_CS0_SIZE GPMC_SIZE_128M
-
-#ifdef CFG_PRINTF
-
-#define CFG_NS16550
-#define CFG_NS16550_SERIAL
-#define CFG_NS16550_REG_SIZE	-4
-#define CFG_NS16550_CLK		48000000
-#define CFG_NS16550_COM3	OMAP34XX_UART3
-
-/*
- * select serial console configuration
- */
-#define CONFIG_SERIAL1		3	/* use UART3 */
-#define CONFIG_CONS_INDEX	3
-
-#define CONFIG_BAUDRATE		115200
-#define CFG_PBSIZE		256
-
-#endif /* CFG_PRINTF */
-
-/*
- * Miscellaneous configurable options
- */
-#define CFG_LOADADDR		0x80008000
-
-#undef	CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */
-
-/*-----------------------------------------------------------------------
- * Stack sizes
- *
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE	(128*1024) /* regular stack */
-
-/*-----------------------------------------------------------------------
- * Board NAND Info.
- */
-
-#define CFG_NAND_K9F1G08R0A
-#define NAND_16BIT
-
-/* NAND is partitioned:
- * 0x00000000 - 0x0007FFFF  Booting Image
- * 0x00080000 - 0x0023FFFF  U-Boot Image
- * 0x00240000 - 0x0027FFFF  U-Boot Env Data (X-loader doesn't care)
- * 0x00280000 - 0x0077FFFF  Kernel Image
- * 0x00780000 - 0x08000000  depends on application
- */
-#define NAND_UBOOT_START	0x0080000 /* Leaving first 4 blocks for x-load */
-#define NAND_UBOOT_END		0x0240000 /* Giving a space of 2 blocks = 256KB */
-#define NAND_BLOCK_SIZE		0x20000
-
-#define GPMC_CONFIG		(OMAP34XX_GPMC_BASE+0x50)
-#define GPMC_NAND_COMMAND_0	(OMAP34XX_GPMC_BASE+0x7C)
-#define GPMC_NAND_ADDRESS_0	(OMAP34XX_GPMC_BASE+0x80)
-#define GPMC_NAND_DATA_0	(OMAP34XX_GPMC_BASE+0x84)
-
-#ifdef NAND_16BIT
-#define WRITE_NAND_COMMAND(d, adr) \
-	do {*(volatile u16 *)GPMC_NAND_COMMAND_0 = d; } while (0)
-#define WRITE_NAND_ADDRESS(d, adr) \
-	do {*(volatile u16 *)GPMC_NAND_ADDRESS_0 = d; } while (0)
-#define WRITE_NAND(d, adr) \
-	do {*(volatile u16 *)GPMC_NAND_DATA_0 = d; } while (0)
-#define READ_NAND(adr) \
-	(*(volatile u16 *)GPMC_NAND_DATA_0)
-#define NAND_WAIT_READY()
-#define NAND_WP_OFF()  \
-	do {*(volatile u32 *)(GPMC_CONFIG) |= 0x00000010; } while (0)
-#define NAND_WP_ON()  \
-	 do {*(volatile u32 *)(GPMC_CONFIG) &= ~0x00000010; } while (0)
-
-#else /* to support 8-bit NAND devices */
-#define WRITE_NAND_COMMAND(d, adr) \
-	do {*(volatile u8 *)GPMC_NAND_COMMAND_0 = d; } while (0)
-#define WRITE_NAND_ADDRESS(d, adr) \
-	 do {*(volatile u8 *)GPMC_NAND_ADDRESS_0 = d; } while (0)
-#define WRITE_NAND(d, adr) \
-	do {*(volatile u8 *)GPMC_NAND_DATA_0 = d; } while (0)
-#define READ_NAND(adr) \
-	(*(volatile u8 *)GPMC_NAND_DATA_0);
-#define NAND_WAIT_READY()
-#define NAND_WP_OFF()  \
-	do {*(volatile u32 *)(GPMC_CONFIG) |= 0x00000010; } while (0)
-#define NAND_WP_ON()  \
-	do {*(volatile u32 *)(GPMC_CONFIG) &= ~0x00000010; } while (0)
-
-#endif
-
-#define NAND_CTL_CLRALE(adr)
-#define NAND_CTL_SETALE(adr)
-#define NAND_CTL_CLRCLE(adr)
-#define NAND_CTL_SETCLE(adr)
-#define NAND_DISABLE_CE()
-#define NAND_ENABLE_CE()
-
-/*-----------------------------------------------------------------------
- * Board oneNAND Info.
- */
-#define CFG_SYNC_BURST_READ	1
-
-/* OneNAND is partitioned:
- *   0x0000000 - 0x0080000  X-Loader
- *   0x0080000 - 0x0240000   U-boot Image
- *   0x0240000 - 0x0280000   U-Boot Env Data (X-loader doesn't care)
- *   0x0280000 - 0x0780000   Kernel Image
- *   0x0780000 - 0x8000000   depends on application
- */
-
-#define ONENAND_START_BLOCK	4
-#define ONENAND_END_BLOCK	18
-#define ONENAND_PAGE_SIZE	2048     /* 2KB */
-#define ONENAND_BLOCK_SIZE	0x20000  /* 128KB */
-
-#endif /* __CONFIG_H */
-