diff options
Diffstat (limited to 'uart-loader/include/asm/arch-arm1136')
| -rw-r--r-- | uart-loader/include/asm/arch-arm1136/bits.h | 49 | ||||
| l--------- | uart-loader/include/asm/arch-arm1136/clocks.h | 1 | ||||
| l--------- | uart-loader/include/asm/arch-arm1136/clocks242x.h | 1 | ||||
| l--------- | uart-loader/include/asm/arch-arm1136/clocks243x.h | 1 | ||||
| l--------- | uart-loader/include/asm/arch-arm1136/mem.h | 1 | ||||
| -rw-r--r-- | uart-loader/include/asm/arch-arm1136/omap2420.h | 223 | ||||
| -rw-r--r-- | uart-loader/include/asm/arch-arm1136/omap2430.h | 255 | ||||
| -rw-r--r-- | uart-loader/include/asm/arch-arm1136/sizes.h | 50 | ||||
| -rw-r--r-- | uart-loader/include/asm/arch-arm1136/sys_info.h | 139 |
9 files changed, 0 insertions, 720 deletions
diff --git a/uart-loader/include/asm/arch-arm1136/bits.h b/uart-loader/include/asm/arch-arm1136/bits.h deleted file mode 100644 index dc3273e..0000000 --- a/uart-loader/include/asm/arch-arm1136/bits.h +++ /dev/null @@ -1,49 +0,0 @@ -/* bits.h - * Copyright (c) 2004 Texas Instruments - * - * This package is free software; you can redistribute it and/or - * modify it under the terms of the license found in the file - * named COPYING that should have accompanied this file. - * - * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED - * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. - */ -#ifndef __bits_h -#define __bits_h 1 - -#define BIT0 (1<<0) -#define BIT1 (1<<1) -#define BIT2 (1<<2) -#define BIT3 (1<<3) -#define BIT4 (1<<4) -#define BIT5 (1<<5) -#define BIT6 (1<<6) -#define BIT7 (1<<7) -#define BIT8 (1<<8) -#define BIT9 (1<<9) -#define BIT10 (1<<10) -#define BIT11 (1<<11) -#define BIT12 (1<<12) -#define BIT13 (1<<13) -#define BIT14 (1<<14) -#define BIT15 (1<<15) -#define BIT16 (1<<16) -#define BIT17 (1<<17) -#define BIT18 (1<<18) -#define BIT19 (1<<19) -#define BIT20 (1<<20) -#define BIT21 (1<<21) -#define BIT22 (1<<22) -#define BIT23 (1<<23) -#define BIT24 (1<<24) -#define BIT25 (1<<25) -#define BIT26 (1<<26) -#define BIT27 (1<<27) -#define BIT28 (1<<28) -#define BIT29 (1<<29) -#define BIT30 (1<<30) -#define BIT31 (1<<31) - -#endif - diff --git a/uart-loader/include/asm/arch-arm1136/clocks.h b/uart-loader/include/asm/arch-arm1136/clocks.h deleted file mode 120000 index c4b03ba..0000000 --- a/uart-loader/include/asm/arch-arm1136/clocks.h +++ /dev/null @@ -1 +0,0 @@ -../../../../u-boot/include/asm-arm/arch-arm1136/clocks.h
\ No newline at end of file diff --git a/uart-loader/include/asm/arch-arm1136/clocks242x.h b/uart-loader/include/asm/arch-arm1136/clocks242x.h deleted file mode 120000 index f080726..0000000 --- a/uart-loader/include/asm/arch-arm1136/clocks242x.h +++ /dev/null @@ -1 +0,0 @@ -../../../../u-boot/include/asm-arm/arch-arm1136/clocks242x.h
\ No newline at end of file diff --git a/uart-loader/include/asm/arch-arm1136/clocks243x.h b/uart-loader/include/asm/arch-arm1136/clocks243x.h deleted file mode 120000 index 703bdce..0000000 --- a/uart-loader/include/asm/arch-arm1136/clocks243x.h +++ /dev/null @@ -1 +0,0 @@ -../../../../u-boot/include/asm-arm/arch-arm1136/clocks243x.h
\ No newline at end of file diff --git a/uart-loader/include/asm/arch-arm1136/mem.h b/uart-loader/include/asm/arch-arm1136/mem.h deleted file mode 120000 index dd453b2..0000000 --- a/uart-loader/include/asm/arch-arm1136/mem.h +++ /dev/null @@ -1 +0,0 @@ -../../../../u-boot/include/asm-arm/arch-arm1136/mem.h
\ No newline at end of file diff --git a/uart-loader/include/asm/arch-arm1136/omap2420.h b/uart-loader/include/asm/arch-arm1136/omap2420.h deleted file mode 100644 index 2164b68..0000000 --- a/uart-loader/include/asm/arch-arm1136/omap2420.h +++ /dev/null @@ -1,223 +0,0 @@ -/* - * Copyright (C) 2005 Texas Instruments, <www.ti.com> - * - * (C) Copyright 2004 - * Texas Instruments, <www.ti.com> - * Richard Woodruff <r-woodruff2@ti.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _OMAP2420_SYS_H_ -#define _OMAP2420_SYS_H_ - -#include <asm/arch/sizes.h> - - -#define __raw_writeb(v,a) (*(volatile unsigned char *)(a) = (v)) -#define __raw_writew(v,a) (*(volatile unsigned short *)(a) = (v)) -#define __raw_writel(v,a) (*(volatile unsigned int *)(a) = (v)) - -#define __raw_readb(a) (*(volatile unsigned char *)(a)) -#define __raw_readw(a) (*(volatile unsigned short *)(a)) -#define __raw_readl(a) (*(volatile unsigned int *)(a)) - - -/* - * 2420 specific Section - */ - -/* CONTROL */ -#define OMAP2420_CTRL_BASE (0x48000000) -#define CONTROL_STATUS (OMAP2420_CTRL_BASE + 0x2F8) - -/* TAP information */ -#define OMAP2420_TAP_BASE (0x48014000) -#define TAP_IDCODE_REG (OMAP2420_TAP_BASE+0x204) - -/* GPMC */ -#define OMAP2420_GPMC_BASE (0x6800A000) -#define GPMC_SYSCONFIG (OMAP2420_GPMC_BASE+0x10) -#define GPMC_SYSSTATUS (OMAP2420_GPMC_BASE+0x14) -#define GPMC_IRQENABLE (OMAP2420_GPMC_BASE+0x1C) -#define GPMC_TIMEOUT_CONTROL (OMAP2420_GPMC_BASE+0x40) -#define GPMC_CONFIG (OMAP2420_GPMC_BASE+0x50) -#define GPMC_CONFIG1_0 (OMAP2420_GPMC_BASE+0x60) -#define GPMC_CONFIG2_0 (OMAP2420_GPMC_BASE+0x64) -#define GPMC_CONFIG3_0 (OMAP2420_GPMC_BASE+0x68) -#define GPMC_CONFIG4_0 (OMAP2420_GPMC_BASE+0x6C) -#define GPMC_CONFIG5_0 (OMAP2420_GPMC_BASE+0x70) -#define GPMC_CONFIG6_0 (OMAP2420_GPMC_BASE+0x74) -#define GPMC_CONFIG7_0 (OMAP2420_GPMC_BASE+0x78) -#define GPMC_CONFIG1_1 (OMAP2420_GPMC_BASE+0x90) -#define GPMC_CONFIG2_1 (OMAP2420_GPMC_BASE+0x94) -#define GPMC_CONFIG3_1 (OMAP2420_GPMC_BASE+0x98) -#define GPMC_CONFIG4_1 (OMAP2420_GPMC_BASE+0x9C) -#define GPMC_CONFIG5_1 (OMAP2420_GPMC_BASE+0xA0) -#define GPMC_CONFIG6_1 (OMAP2420_GPMC_BASE+0xA4) -#define GPMC_CONFIG7_1 (OMAP2420_GPMC_BASE+0xA8) - -/* SMS */ -#define OMAP2420_SMS_BASE 0x68008000 -#define SMS_SYSCONFIG (OMAP2420_SMS_BASE+0x10) - -/* SDRC */ -#define OMAP2420_SDRC_BASE 0x68009000 -#define SDRC_SYSCONFIG (OMAP2420_SDRC_BASE+0x10) -#define SDRC_STATUS (OMAP2420_SDRC_BASE+0x14) -#define SDRC_SHARING (OMAP2420_SDRC_BASE+0x44) -#define SDRC_DLLA_CTRL (OMAP2420_SDRC_BASE+0x60) -#define SDRC_DLLA_STATUS (OMAP2420_SDRC_BASE+0x64) -#define SDRC_DLLB_CTRL (OMAP2420_SDRC_BASE+0x68) -#define SDRC_POWER (OMAP2420_SDRC_BASE+0x70) -#define SDRC_MCFG_0 (OMAP2420_SDRC_BASE+0x80) -#define SDRC_MR_0 (OMAP2420_SDRC_BASE+0x84) -#define SDRC_ACTIM_CTRLA_0 (OMAP2420_SDRC_BASE+0x9C) -#define SDRC_ACTIM_CTRLB_0 (OMAP2420_SDRC_BASE+0xA0) -#define SDRC_MCFG_1 (OMAP2420_SDRC_BASE+0xB0) -#define SDRC_MR_1 (OMAP2420_SDRC_BASE+0xB4) -#define SDRC_EMR2_1 (OMAP2420_SDRC_BASE+0xBC) -#define SDRC_ACTIM_CTRLA_1 (OMAP2420_SDRC_BASE+0xC4) -#define SDRC_ACTIM_CTRLB_1 (OMAP2420_SDRC_BASE+0xC8) -#define SDRC_RFR_CTRL (OMAP2420_SDRC_BASE+0xA4) -#define SDRC_MANUAL_0 (OMAP2420_SDRC_BASE+0xA8) -#define SDRC_RFR_CTRL1 (OMAP2420_SDRC_BASE+0xD4) -#define SDRC_MANUAL_1 (OMAP2420_SDRC_BASE+0xD8) - -#define OMAP2420_SDRC_CS0 0x80000000 -#define OMAP2420_SDRC_CS1 0xA0000000 - -#define LOADDLL BIT2 -#define CMD_NOP 0x0 -#define CMD_PRECHARGE 0x1 -#define CMD_AUTOREFRESH 0x2 -#define CMD_ENTR_PWRDOWN 0x3 -#define CMD_EXIT_PWRDOWN 0x4 -#define CMD_ENTR_SRFRSH 0x5 -#define CMD_CKE_HIGH 0x6 -#define CMD_CKE_LOW 0x7 -#define SOFTRESET BIT1 -#define SMART_IDLE (0x2 << 3) -#define REF_ON_IDLE (0x1 << 6) - - -/* UART */ -#define OMAP2420_UART1 0x4806A000 -#define OMAP2420_UART2 0x4806C000 -#define OMAP2420_UART3 0x4806E000 - -/* General Purpose Timers */ -#define OMAP2420_GPT1 0x48028000 -#define OMAP2420_GPT2 0x4802A000 -#define OMAP2420_GPT3 0x48078000 -#define OMAP2420_GPT4 0x4807A000 -#define OMAP2420_GPT5 0x4807C000 -#define OMAP2420_GPT6 0x4807E000 -#define OMAP2420_GPT7 0x48080000 -#define OMAP2420_GPT8 0x48082000 -#define OMAP2420_GPT9 0x48084000 -#define OMAP2420_GPT10 0x48086000 -#define OMAP2420_GPT11 0x48088000 -#define OMAP2420_GPT12 0x4808A000 - -/* timer regs offsets (32 bit regs) */ -#define TIDR 0x0 /* r */ -#define TIOCP_CFG 0x10 /* rw */ -#define TISTAT 0x14 /* r */ -#define TISR 0x18 /* rw */ -#define TIER 0x1C /* rw */ -#define TWER 0x20 /* rw */ -#define TCLR 0x24 /* rw */ -#define TCRR 0x28 /* rw */ -#define TLDR 0x2C /* rw */ -#define TTGR 0x30 /* rw */ -#define TWPS 0x34 /* r */ -#define TMAR 0x38 /* rw */ -#define TCAR1 0x3c /* r */ -#define TSICR 0x40 /* rw */ -#define TCAR2 0x44 /* r */ - -/* WatchDog Timers (1 secure, 3 GP) */ -#define WD1_BASE 0x48020000 -#define WD2_BASE 0x48022000 -#define WD3_BASE 0x48024000 -#define WD4_BASE 0x48026000 -#define WWPS 0x34 /* r */ -#define WSPR 0x48 /* rw */ -#define WD_UNLOCK1 0xAAAA -#define WD_UNLOCK2 0x5555 - -/* PRCM */ -#define OMAP2420_CM_BASE 0x48008000 -#define PRCM_CLKCFG_CTRL (OMAP2420_CM_BASE+0x080) -#define CM_CLKSEL_MPU (OMAP2420_CM_BASE+0x140) -#define CM_FCLKEN1_CORE (OMAP2420_CM_BASE+0x200) -#define CM_FCLKEN2_CORE (OMAP2420_CM_BASE+0x204) -#define CM_ICLKEN1_CORE (OMAP2420_CM_BASE+0x210) -#define CM_ICLKEN2_CORE (OMAP2420_CM_BASE+0x214) -#define CM_CLKSEL1_CORE (OMAP2420_CM_BASE+0x240) -#define CM_CLKSEL_WKUP (OMAP2420_CM_BASE+0x440) -#define CM_CLKSEL2_CORE (OMAP2420_CM_BASE+0x244) -#define CM_CLKSEL_GFX (OMAP2420_CM_BASE+0x340) -#define PM_RSTCTRL_WKUP (OMAP2420_CM_BASE+0x450) -#define CM_CLKEN_PLL (OMAP2420_CM_BASE+0x500) -#define CM_IDLEST_CKGEN (OMAP2420_CM_BASE+0x520) -#define CM_CLKSEL1_PLL (OMAP2420_CM_BASE+0x540) -#define CM_CLKSEL2_PLL (OMAP2420_CM_BASE+0x544) -#define CM_CLKSEL_DSP (OMAP2420_CM_BASE+0x840) - -/* - * H4 specific Section - */ - -/* - * The 2420's chip selects are programmable. The mask ROM - * does configure CS0 to 0x08000000 before dispatch. So, if - * you want your code to live below that address, you have to - * be prepared to jump though hoops, to reset the base address. - */ -#if defined(CONFIG_OMAP2420H4) -/* GPMC */ -#ifdef CONFIG_VIRTIO_A /* Pre version B */ -# define H4_CS0_BASE 0x08000000 /* flash (64 Meg aligned) */ -# define H4_CS1_BASE 0x04000000 /* debug board */ -# define H4_CS2_BASE 0x0A000000 /* wifi board */ -#else -# define H4_CS0_BASE 0x04000000 /* flash (64 Meg aligned) */ -# define H4_CS1_BASE 0x08000000 /* debug board */ -# define H4_CS2_BASE 0x0A000000 /* wifi board */ -#endif - -/* base address for indirect vectors (internal boot mode) */ -#define SRAM_OFFSET0 0x40000000 -#define SRAM_OFFSET1 0x00200000 -#define SRAM_OFFSET2 0x0000F800 -#define SRAM_VECT_CODE (SRAM_OFFSET0|SRAM_OFFSET1|SRAM_OFFSET2) - -#define LOW_LEVEL_SRAM_STACK 0x4020FFFC - -#define PERIFERAL_PORT_BASE 0x480FE003 - -/* FPGA on Debug board.*/ -#define ETH_CONTROL_REG (H4_CS1_BASE+0x30b) -#define LAN_RESET_REGISTER (H4_CS1_BASE+0x1c) -#endif /* endif CONFIG_2420H4 */ - -#endif - diff --git a/uart-loader/include/asm/arch-arm1136/omap2430.h b/uart-loader/include/asm/arch-arm1136/omap2430.h deleted file mode 100644 index cf2b0f9..0000000 --- a/uart-loader/include/asm/arch-arm1136/omap2430.h +++ /dev/null @@ -1,255 +0,0 @@ -/* - * (C) Copyright 2004-2005 - * Texas Instruments, <www.ti.com> - * Richard Woodruff <r-woodruff2@ti.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _OMAP2430_SYS_H_ -#define _OMAP2430_SYS_H_ - -#include <asm/arch/sizes.h> - - -#define __raw_writeb(v,a) (*(volatile unsigned char *)(a) = (v)) -#define __raw_writew(v,a) (*(volatile unsigned short *)(a) = (v)) -#define __raw_writel(v,a) (*(volatile unsigned int *)(a) = (v)) - -#define __raw_readb(a) (*(volatile unsigned char *)(a)) -#define __raw_readw(a) (*(volatile unsigned short *)(a)) -#define __raw_readl(a) (*(volatile unsigned int *)(a)) - -/* device type */ -#define DEVICE_MASK (BIT8|BIT9|BIT10) -#define TST_DEVICE 0x0 -#define EMU_DEVICE 0x1 -#define HS_DEVICE 0x2 -#define GP_DEVICE 0x3 - -/* - * 2430 specific Section - */ -#define OMAP243X_CORE_L4_IO_BASE 0x48000000 -#define OMAP243X_WAKEUP_L4_IO_BASE 0x49000000 -#define OMAP24XX_L4_IO_BASE OMAP243X_CORE_L4_IO_BASE - - -/* CONTROL */ -#define OMAP24XX_CTRL_BASE (OMAP243X_WAKEUP_L4_IO_BASE+0x2000) -#define CONTROL_STATUS (OMAP24XX_CTRL_BASE + 0x2F8) - -/* TAP information */ -#define OMAP24XX_TAP_BASE (OMAP243X_WAKEUP_L4_IO_BASE+0xA000) -#define TAP_IDCODE_REG (OMAP24XX_TAP_BASE+0x204) - -/* - GPMC : In 2430 NOR and NAND can coexist. - During NAND booting , NAND is at CS0 and NOR at CS1 - and Debug FPGA is GPMC_CS5 -*/ -#define OMAP24XX_GPMC_BASE (0x6E000000) - -#define GPMC_SYSCONFIG (OMAP24XX_GPMC_BASE+0x10) -#define GPMC_SYSSTATUS (OMAP24XX_GPMC_BASE+0x14) -#define GPMC_IRQENABLE (OMAP24XX_GPMC_BASE+0x1C) -#define GPMC_TIMEOUT_CONTROL (OMAP24XX_GPMC_BASE+0x40) -#define GPMC_CONFIG (OMAP24XX_GPMC_BASE+0x50) -#define GPMC_CONFIG1_0 (OMAP24XX_GPMC_BASE+0x60) -#define GPMC_CONFIG2_0 (OMAP24XX_GPMC_BASE+0x64) -#define GPMC_CONFIG3_0 (OMAP24XX_GPMC_BASE+0x68) -#define GPMC_CONFIG4_0 (OMAP24XX_GPMC_BASE+0x6C) -#define GPMC_CONFIG5_0 (OMAP24XX_GPMC_BASE+0x70) -#define GPMC_CONFIG6_0 (OMAP24XX_GPMC_BASE+0x74) -#define GPMC_CONFIG7_0 (OMAP24XX_GPMC_BASE+0x78) -#define GPMC_CONFIG1_1 (OMAP24XX_GPMC_BASE+0x90) -#define GPMC_CONFIG2_1 (OMAP24XX_GPMC_BASE+0x94) -#define GPMC_CONFIG3_1 (OMAP24XX_GPMC_BASE+0x98) -#define GPMC_CONFIG4_1 (OMAP24XX_GPMC_BASE+0x9C) -#define GPMC_CONFIG5_1 (OMAP24XX_GPMC_BASE+0xA0) -#define GPMC_CONFIG6_1 (OMAP24XX_GPMC_BASE+0xA4) -#define GPMC_CONFIG7_1 (OMAP24XX_GPMC_BASE+0xA8) -#define GPMC_CONFIG1_5 (OMAP24XX_GPMC_BASE+0x150) -#define GPMC_CONFIG2_5 (OMAP24XX_GPMC_BASE+0x154) -#define GPMC_CONFIG3_5 (OMAP24XX_GPMC_BASE+0x158) -#define GPMC_CONFIG4_5 (OMAP24XX_GPMC_BASE+0x15C) -#define GPMC_CONFIG5_5 (OMAP24XX_GPMC_BASE+0x160) -#define GPMC_CONFIG6_5 (OMAP24XX_GPMC_BASE+0x164) -#define GPMC_CONFIG7_5 (OMAP24XX_GPMC_BASE+0x168) - - -/* SMS */ -#define OMAP24XX_SMS_BASE 0x6C000000 -#define SMS_SYSCONFIG (OMAP24XX_SMS_BASE+0x10) - -/* SDRC */ -#define OMAP24XX_SDRC_BASE 0x6D000000 -#define OMAP24XX_SDRC_CS0 0x80000000 -#define OMAP24XX_SDRC_CS1 0xA0000000 -#define SDRC_SYSCONFIG (OMAP24XX_SDRC_BASE+0x10) -#define SDRC_STATUS (OMAP24XX_SDRC_BASE+0x14) -#define SDRC_SHARING (OMAP24XX_SDRC_BASE+0x44) -#define SDRC_DLLA_CTRL (OMAP24XX_SDRC_BASE+0x60) -#define SDRC_DLLA_STATUS (OMAP24XX_SDRC_BASE+0x64) -#define SDRC_DLLB_CTRL (OMAP24XX_SDRC_BASE+0x68) -#define SDRC_POWER (OMAP24XX_SDRC_BASE+0x70) -#define SDRC_MCFG_0 (OMAP24XX_SDRC_BASE+0x80) -#define SDRC_MR_0 (OMAP24XX_SDRC_BASE+0x84) -#define SDRC_ACTIM_CTRLA_0 (OMAP24XX_SDRC_BASE+0x9C) -#define SDRC_ACTIM_CTRLB_0 (OMAP24XX_SDRC_BASE+0xA0) -#define SDRC_MCFG_1 (OMAP24XX_SDRC_BASE+0xB0) -#define SDRC_ACTIM_CTRLA_1 (OMAP24XX_SDRC_BASE+0xC4) -#define SDRC_ACTIM_CTRLB_1 (OMAP24XX_SDRC_BASE+0xC8) -#define SDRC_RFR_CTRL (OMAP24XX_SDRC_BASE+0xA4) -#define SDRC_MANUAL_0 (OMAP24XX_SDRC_BASE+0xA8) -#define SDRC_RFR_CTRL1 (OMAP24XX_SDRC_BASE+0xD4) - -#define LOADDLL BIT2 -#define CMD_NOP 0x0 -#define CMD_PRECHARGE 0x1 -#define CMD_AUTOREFRESH 0x2 -#define CMD_ENTR_PWRDOWN 0x3 -#define CMD_EXIT_PWRDOWN 0x4 -#define CMD_ENTR_SRFRSH 0x5 -#define CMD_CKE_HIGH 0x6 -#define CMD_CKE_LOW 0x7 -#define SOFTRESET BIT1 -#define SMART_IDLE (0x2 << 3) -#define REF_ON_IDLE (0x1 << 6) - - -/* UART */ -#define OMAP2430_UART1 0x4806A000 -#define OMAP2430_UART2 0x4806C000 -#define OMAP2430_UART3 0x4806E000 - -/* General Purpose Timers */ -#define OMAP24XX_GPT1 (OMAP243X_WAKEUP_L4_IO_BASE+0x18000) -#define OMAP24XX_GPT2 (OMAP24XX_L4_IO_BASE+0x2A000) -#define OMAP24XX_GPT3 (OMAP24XX_L4_IO_BASE+0x78000) -#define OMAP24XX_GPT4 (OMAP24XX_L4_IO_BASE+0x7A000) -#define OMAP24XX_GPT5 (OMAP24XX_L4_IO_BASE+0x7C000) -#define OMAP24XX_GPT6 (OMAP24XX_L4_IO_BASE+0x7E000) -#define OMAP24XX_GPT7 (OMAP24XX_L4_IO_BASE+0x80000) -#define OMAP24XX_GPT8 (OMAP24XX_L4_IO_BASE+0x82000) -#define OMAP24XX_GPT9 (OMAP24XX_L4_IO_BASE+0x84000) -#define OMAP24XX_GPT10 (OMAP24XX_L4_IO_BASE+0x86000) -#define OMAP24XX_GPT11 (OMAP24XX_L4_IO_BASE+0x88000) -#define OMAP24XX_GPT12 (OMAP24XX_L4_IO_BASE+0x8A000 - -/* timer regs offsets (32 bit regs) */ -#define TIDR 0x0 /* r */ -#define TIOCP_CFG 0x10 /* rw */ -#define TISTAT 0x14 /* r */ -#define TISR 0x18 /* rw */ -#define TIER 0x1C /* rw */ -#define TWER 0x20 /* rw */ -#define TCLR 0x24 /* rw */ -#define TCRR 0x28 /* rw */ -#define TLDR 0x2C /* rw */ -#define TTGR 0x30 /* rw */ -#define TWPS 0x34 /* r */ -#define TMAR 0x38 /* rw */ -#define TCAR1 0x3c /* r */ -#define TSICR 0x40 /* rw */ -#define TCAR2 0x44 /* r */ - -/* WatchDog Timers (1 secure, 3 GP) */ -#define WD1_BASE (OMAP243X_WAKEUP_L4_IO_BASE+0x14000) -#define WD2_BASE (OMAP243X_WAKEUP_L4_IO_BASE+0x16000) -#define WD3_BASE (OMAP24XX_L4_IO_BASE+0x24000) /* not present */ -#define WD4_BASE (OMAP24XX_L4_IO_BASE+0x26000) - -/* 32KTIMER */ -#define SYNC_32KTIMER_BASE (OMAP243X_WAKEUP_L4_IO_BASE+0x20000) -#define S32K_CR (SYNC_32KTIMER_BASE+0x10) - -#define WWPS 0x34 /* r */ -#define WSPR 0x48 /* rw */ -#define WD_UNLOCK1 0xAAAA -#define WD_UNLOCK2 0x5555 - -/* PRCM */ -#define OMAP24XX_CM_BASE (OMAP243X_WAKEUP_L4_IO_BASE+0x06000) - -#define PRCM_CLKSRC_CTRL (OMAP24XX_CM_BASE+0x060) -#define PRCM_CLKOUT_CTRL (OMAP24XX_CM_BASE+0x070) -#define PRCM_CLKEMUL_CTRL (OMAP24XX_CM_BASE+0x078) -#define PRCM_CLKCFG_CTRL (OMAP24XX_CM_BASE+0x080) -#define PRCM_CLKCFG_STATUS (OMAP24XX_CM_BASE+0x084) -#define CM_CLKSEL_MPU (OMAP24XX_CM_BASE+0x140) -#define CM_FCLKEN1_CORE (OMAP24XX_CM_BASE+0x200) -#define CM_FCLKEN2_CORE (OMAP24XX_CM_BASE+0x204) -#define CM_ICLKEN1_CORE (OMAP24XX_CM_BASE+0x210) -#define CM_ICLKEN2_CORE (OMAP24XX_CM_BASE+0x214) -#define CM_CLKSEL1_CORE (OMAP24XX_CM_BASE+0x240) -#define CM_CLKSEL_WKUP (OMAP24XX_CM_BASE+0x440) -#define CM_CLKSEL2_CORE (OMAP24XX_CM_BASE+0x244) -#define CM_FCLKEN_GFX (OMAP24XX_CM_BASE+0x300) -#define CM_ICLKEN_GFX (OMAP24XX_CM_BASE+0x310) -#define CM_CLKSEL_GFX (OMAP24XX_CM_BASE+0x340) -#define RM_RSTCTRL_GFX (OMAP24XX_CM_BASE+0x350) -#define CM_FCLKEN_WKUP (OMAP24XX_CM_BASE+0x400) -#define CM_ICLKEN_WKUP (OMAP24XX_CM_BASE+0x410) -#define PM_RSTCTRL_WKUP (OMAP24XX_CM_BASE+0x450) -#define CM_CLKEN_PLL (OMAP24XX_CM_BASE+0x500) -#define CM_IDLEST_CKGEN (OMAP24XX_CM_BASE+0x520) -#define CM_CLKSEL1_PLL (OMAP24XX_CM_BASE+0x540) -#define CM_CLKSEL2_PLL (OMAP24XX_CM_BASE+0x544) -#define CM_CLKSEL_DSP (OMAP24XX_CM_BASE+0x840) -#define CM_CLKSEL_MDM (OMAP24XX_CM_BASE+0xC40) - -/* SMX-APE */ -#define SMX_APE_BASE 0x68000000 -#define PM_RT_APE_BASE_ADDR_ARM (SMX_APE_BASE + 0x10000) -#define PM_GPMC_BASE_ADDR_ARM (SMX_APE_BASE + 0x12400) -#define PM_OCM_RAM_BASE_ADDR_ARM (SMX_APE_BASE + 0x12800) -#define PM_OCM_ROM_BASE_ADDR_ARM (SMX_APE_BASE + 0x12C00) - -/* IVA2 */ -#define PM_IVA2_BASE_ADDR_ARM (SMX_APE_BASE + 0x14000) - -/* - * The 2430's chip selects are programmable. The mask ROM - * does configure CS0 to 0x08000000 before dispatch. So, if - * you want your code to live below that address, you have to - * be prepared to jump though hoops, to reset the base address. - */ -#if defined(CONFIG_OMAP243X) - -/* GPMC */ -/* This is being used by the macros in mem.h. PHYS_FLASH_1 is defined to H4_CS0_BASE */ -# define H4_CS1_BASE 0x09000000 /* flash (64 Meg aligned) */ -#define CFG_FLASH_BASE H4_CS1_BASE -#define DEBUG_BASE 0x08000000 - -/* base address for indirect vectors (internal boot mode) */ -#define SRAM_OFFSET0 0x40000000 -#define SRAM_OFFSET1 0x00200000 -#define SRAM_OFFSET2 0x0000F800 -#define SRAM_VECT_CODE (SRAM_OFFSET0|SRAM_OFFSET1|SRAM_OFFSET2) - -#define LOW_LEVEL_SRAM_STACK 0x4020FFFC - -#define PERIFERAL_PORT_BASE 0x480FE003 - -#endif /* endif CONFIG_2430SDP */ - -#endif - diff --git a/uart-loader/include/asm/arch-arm1136/sizes.h b/uart-loader/include/asm/arch-arm1136/sizes.h deleted file mode 100644 index 3dddd8e..0000000 --- a/uart-loader/include/asm/arch-arm1136/sizes.h +++ /dev/null @@ -1,50 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -/* Size defintions - * Copyright (C) ARM Limited 1998. All rights reserved. - */ - -#ifndef __sizes_h -#define __sizes_h 1 - -/* handy sizes */ -#define SZ_1K 0x00000400 -#define SZ_4K 0x00001000 -#define SZ_8K 0x00002000 -#define SZ_16K 0x00004000 -#define SZ_32K 0x00008000 -#define SZ_64K 0x00010000 -#define SZ_128K 0x00020000 -#define SZ_256K 0x00040000 -#define SZ_512K 0x00080000 - -#define SZ_1M 0x00100000 -#define SZ_2M 0x00200000 -#define SZ_4M 0x00400000 -#define SZ_8M 0x00800000 -#define SZ_16M 0x01000000 -#define SZ_31M 0x01F00000 -#define SZ_32M 0x02000000 -#define SZ_64M 0x04000000 -#define SZ_128M 0x08000000 -#define SZ_256M 0x10000000 -#define SZ_512M 0x20000000 - -#define SZ_1G 0x40000000 -#define SZ_2G 0x80000000 - -#endif /* __sizes_h */ - diff --git a/uart-loader/include/asm/arch-arm1136/sys_info.h b/uart-loader/include/asm/arch-arm1136/sys_info.h deleted file mode 100644 index 94a09cd..0000000 --- a/uart-loader/include/asm/arch-arm1136/sys_info.h +++ /dev/null @@ -1,139 +0,0 @@ -/* - * Copyright 2005 (C) Texas Instruments, <www.ti.com> - * (C) Copyright 2004 - * Texas Instruments, <www.ti.com> - * Richard Woodruff <r-woodruff2@ti.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _OMAP24XX_SYS_INFO_H_ -#define _OMAP24XX_SYS_INFO_H_ - -#if 0 -typedef struct h4_system_data { - /* base board info */ - u32 base_b_rev; /* rev from base board i2c */ - /* cpu board info */ - u32 cpu_b_rev; /* rev from cpu board i2c */ - u32 cpu_b_mux; /* mux type on daughter board */ - u32 cpu_b_ddr_type; /* mem type */ - u32 cpu_b_ddr_speed; /* ddr speed rating */ - u32 cpu_b_switches; /* boot ctrl switch settings */ - /* cpu info */ - u32 cpu_type; /* type of cpu; 2420, 2422, 2430,...*/ - u32 cpu_rev; /* rev of given cpu; ES1, ES2,...*/ -} h4_sys_data; - -#endif - -#define XDR_POP 5 /* package on package part */ -#define SDR_DISCRETE 4 /* 128M memory SDR module*/ -#define DDR_STACKED 3 /* stacked part on 2422 */ -#define DDR_COMBO 2 /* combo part on cpu daughter card (menalaeus) */ -#define DDR_DISCRETE 1 /* 2x16 parts on daughter card */ - -#define DDR_100 100 /* type found on most mem d-boards */ -#define DDR_111 111 /* some combo parts */ -#define DDR_133 133 /* most combo, some mem d-boards */ -#define DDR_165 165 /* future parts */ - -#define CPU_2420 0x2420 -#define CPU_2422 0x2422 /* 2420 + 64M stacked */ -#define CPU_2423 0x2423 /* 2420 + 96M stacked */ -#define CPU_2430 0x2430 - -/* 242x real hardware: - * ES1 = rev 0 - * ES2 = rev 1 - * ES2.05 = rev 2 - * ES2.1 = rev 3 - * ES2.1.1 = rev 4 - */ - -/* 242x code defines: - * ES1 = 0+1 = 1 - * ES2 = 1+1 = 2 - * ES2.05 = 2+1 = 3 - * ES2.1 = 3+1 = 4 - * Es2.1.1 = 4+1 = 5 - */ -#define CPU_2422_ES1 1 -#define CPU_2422_ES2 2 -#define CPU_2422_ES2_05 3 -#define CPU_2422_ES2_1 4 -#define CPU_2422_ES2_1_1 5 - -#define CPU_2420_ES1 1 -#define CPU_2420_ES2 2 -#define CPU_2420_ES2_05 3 -#define CPU_2420_ES2_1 4 -#define CPU_2420_ES2_1_1 5 - -#define CPU_242X_ES1 1 -#define CPU_242X_ES2 2 -#define CPU_242X_ES2_05 3 -#define CPU_242X_ES2_1 4 -#define CPU_242X_ES2_1_1 5 - -#define CPU_2420_2422_ES1 1 -#define CPU_2420_2422_ES2_1 4 - -/* 243x real hardware: - * ES1 = rev 0 - * ES2 = rev 1 - * - * 243x code defines: - * ES1 = 0+1 = 1 - * ES2 = 1+1 = 2 - */ -#define CPU_2430_ES1 1 -#define CPU_2430_ES2 2 - -#ifdef VPOM2430 -# define CPU_2430_VIRTIO 3 -#else -# define CPU_2430_VIRTIO 1 -#endif -#define CPU_2430_ZEBU 0xD - -#define CPU_2420_CHIPID 0x0B5D9000 -#define CPU_2430_CHIPID 0x0B68A000 -#define CPU_24XX_ID_MASK 0x0FFFF000 -#define CPU_242X_REV_MASK 0xF0000000 -#define CPU_242X_PID_MASK 0x000F0000 - -#define BOARD_H4_MENELAUS 1 -#define BOARD_H4_SDP 2 -#define BOARD_H4_MENELAUS_HRP 3 -#define BOARD_SDP_2430 4 - -#define GPMC_MUXED 1 -#define GPMC_NONMUXED 0 - -#define TYPE_NAND 0x800 /* bit pos for nand in gpmc reg */ -#define TYPE_NOR 0x000 -#define TYPE_ONENAND 0x800 - -#define WIDTH_8BIT 0x0000 -#define WIDTH_16BIT 0x1000 /* bit pos for 16 bit in gpmc */ - -#define I2C_MENELAUS 0x72 /* i2c id for companion chip */ - -#endif |