diff options
Diffstat (limited to 'x-loader/include/asm/arch-omap3')
| m--------- | x-loader | 0 | ||||
| -rw-r--r-- | x-loader/include/asm/arch-omap3/bits.h | 48 | ||||
| -rw-r--r-- | x-loader/include/asm/arch-omap3/clocks.h | 48 | ||||
| -rw-r--r-- | x-loader/include/asm/arch-omap3/clocks343x.h | 155 | ||||
| -rw-r--r-- | x-loader/include/asm/arch-omap3/cpu.h | 257 | ||||
| -rw-r--r-- | x-loader/include/asm/arch-omap3/gpio.h | 86 | ||||
| -rw-r--r-- | x-loader/include/asm/arch-omap3/i2c.h | 128 | ||||
| -rw-r--r-- | x-loader/include/asm/arch-omap3/mem.h | 509 | ||||
| -rw-r--r-- | x-loader/include/asm/arch-omap3/mmc.h | 235 | ||||
| -rw-r--r-- | x-loader/include/asm/arch-omap3/mmc_host_def.h | 164 | ||||
| -rw-r--r-- | x-loader/include/asm/arch-omap3/mux.h | 437 | ||||
| -rw-r--r-- | x-loader/include/asm/arch-omap3/omap3430.h | 141 | ||||
| -rwxr-xr-x | x-loader/include/asm/arch-omap3/rev.h | 43 | ||||
| -rw-r--r-- | x-loader/include/asm/arch-omap3/sizes.h | 49 | ||||
| -rw-r--r-- | x-loader/include/asm/arch-omap3/sys_info.h | 77 | ||||
| -rw-r--r-- | x-loader/include/asm/arch-omap3/sys_proto.h | 59 |
16 files changed, 2436 insertions, 0 deletions
diff --git a/x-loader b/x-loader deleted file mode 160000 -Subproject 1c9276af4d6a5b7014a7630a1abeddf3b317756 diff --git a/x-loader/include/asm/arch-omap3/bits.h b/x-loader/include/asm/arch-omap3/bits.h new file mode 100644 index 0000000..8522335 --- /dev/null +++ b/x-loader/include/asm/arch-omap3/bits.h @@ -0,0 +1,48 @@ +/* bits.h + * Copyright (c) 2004 Texas Instruments + * + * This package is free software; you can redistribute it and/or + * modify it under the terms of the license found in the file + * named COPYING that should have accompanied this file. + * + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. + */ +#ifndef __bits_h +#define __bits_h 1 + +#define BIT0 (1<<0) +#define BIT1 (1<<1) +#define BIT2 (1<<2) +#define BIT3 (1<<3) +#define BIT4 (1<<4) +#define BIT5 (1<<5) +#define BIT6 (1<<6) +#define BIT7 (1<<7) +#define BIT8 (1<<8) +#define BIT9 (1<<9) +#define BIT10 (1<<10) +#define BIT11 (1<<11) +#define BIT12 (1<<12) +#define BIT13 (1<<13) +#define BIT14 (1<<14) +#define BIT15 (1<<15) +#define BIT16 (1<<16) +#define BIT17 (1<<17) +#define BIT18 (1<<18) +#define BIT19 (1<<19) +#define BIT20 (1<<20) +#define BIT21 (1<<21) +#define BIT22 (1<<22) +#define BIT23 (1<<23) +#define BIT24 (1<<24) +#define BIT25 (1<<25) +#define BIT26 (1<<26) +#define BIT27 (1<<27) +#define BIT28 (1<<28) +#define BIT29 (1<<29) +#define BIT30 (1<<30) +#define BIT31 (1<<31) + +#endif diff --git a/x-loader/include/asm/arch-omap3/clocks.h b/x-loader/include/asm/arch-omap3/clocks.h new file mode 100644 index 0000000..4f93a96 --- /dev/null +++ b/x-loader/include/asm/arch-omap3/clocks.h @@ -0,0 +1,48 @@ +/* + * (C) Copyright 2006 + * Texas Instruments, <www.ti.com> + * Richard Woodruff <r-woodruff2@ti.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _OMAP34XX_CLOCKS_H_ +#define _OMAP34XX_CLOCKS_H_ + +#define LDELAY 12000000 + +#define S12M 12000000 +#define S13M 13000000 +#define S19_2M 19200000 +#define S24M 24000000 +#define S26M 26000000 +#define S38_4M 38400000 + +#define FCK_IVA2_ON 0x00000001 +#define FCK_CORE1_ON 0x03fffe29 +#define ICK_CORE1_ON 0x3ffffffb +#define ICK_CORE2_ON 0x0000001f +#define FCK_WKUP_ON 0x000000e9 +#define ICK_WKUP_ON 0x0000003f +#define FCK_DSS_ON 0x00000005 +#define ICK_DSS_ON 0x00000001 +#define FCK_CAM_ON 0x00000001 +#define ICK_CAM_ON 0x00000001 +#define FCK_PER_ON 0x0003ffff +#define ICK_PER_ON 0x0003ffff + +#include <asm/arch/clocks343x.h> + +#endif diff --git a/x-loader/include/asm/arch-omap3/clocks343x.h b/x-loader/include/asm/arch-omap3/clocks343x.h new file mode 100644 index 0000000..7aedaa1 --- /dev/null +++ b/x-loader/include/asm/arch-omap3/clocks343x.h @@ -0,0 +1,155 @@ +/* + * (C) Copyright 2006 + * Texas Instruments, <www.ti.com> + * Richard Woodruff <r-woodruff2@ti.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _OMAP343X_CLOCKS_H_ +#define _OMAP343X_CLOCKS_H_ + +#define PLL_STOP 1 /* PER & IVA */ +#define PLL_LOW_POWER_BYPASS 5 /* MPU, IVA & CORE */ +#define PLL_FAST_RELOCK_BYPASS 6 /* CORE */ +#define PLL_LOCK 7 /* MPU, IVA, CORE & PER */ + +/* The following configurations are OPP and SysClk value independant + * and hence are defined here. All the other DPLL related values are + * tabulated in lowlevel_init.S. + */ + +/* CORE DPLL */ +# define CORE_M3X2 2 /* 332MHz : CM_CLKSEL1_EMU */ +# define CORE_SSI_DIV 3 /* 221MHz : CM_CLKSEL_CORE */ +# define CORE_FUSB_DIV 2 /* 41.5MHz: */ +# define CORE_L4_DIV 2 /* 83MHz : L4 */ +# define CORE_L3_DIV 2 /* 166MHz : L3 {DDR} */ +# define GFX_DIV 2 /* 83MHz : CM_CLKSEL_GFX */ +# define WKUP_RSM 2 /* 41.5MHz: CM_CLKSEL_WKUP */ + +/* PER DPLL */ +# define PER_M6X2 3 /* 288MHz: CM_CLKSEL1_EMU */ +# define PER_M5X2 4 /* 216MHz: CM_CLKSEL_CAM */ +# define PER_M4X2 9 /* 96MHz : CM_CLKSEL_DSS-dss1 */ +# define PER_M3X2 16 /* 54MHz : CM_CLKSEL_DSS-tv */ + +# define CLSEL1_EMU_VAL ((CORE_M3X2 << 16) | (PER_M6X2 << 24) | (0x0a50)) + +#ifdef PRCM_CLK_CFG2_332MHZ +# define M_12 0xA6 +# define N_12 0x05 +# define FSEL_12 0x07 +# define M2_12 0x01 /* M3 of 2 */ + +# define M_12_ES1 0x19F +# define N_12_ES1 0x0E +# define FSL_12_ES1 0x03 +# define M2_12_ES1 0x1 /* M3 of 2 */ + +# define M_13 0x14C +# define N_13 0x0C +# define FSEL_13 0x03 +# define M2_13 0x01 /* M3 of 2 */ + +# define M_13_ES1 0x1B2 +# define N_13_ES1 0x10 +# define FSL_13_ES1 0x03 +# define M2_13_ES1 0x01 /* M3 of 2 */ + +# define M_19p2 0x19F +# define N_19p2 0x17 +# define FSEL_19p2 0x03 +# define M2_19p2 0x01 /* M3 of 2 */ + +# define M_19p2_ES1 0x19F +# define N_19p2_ES1 0x17 +# define FSL_19p2_ES1 0x03 +# define M2_19p2_ES1 0x01 /* M3 of 2 */ + +# define M_26 0xA6 +# define N_26 0x0C +# define FSEL_26 0x07 +# define M2_26 0x01 /* M3 of 2 */ + +# define M_26_ES1 0x1B2 +# define N_26_ES1 0x21 +# define FSL_26_ES1 0x03 +# define M2_26_ES1 0x01 /* M3 of 2 */ + +# define M_38p4 0x19F +# define N_38p4 0x2F +# define FSEL_38p4 0x03 +# define M2_38p4 0x01 /* M3 of 2 */ + +# define M_38p4_ES1 0x19F +# define N_38p4_ES1 0x2F +# define FSL_38p4_ES1 0x03 +# define M2_38p4_ES1 0x01 /* M3 of 2 */ + +#elif defined(PRCM_CLK_CFG2_266MHZ) +# define M_12 0x85 +# define N_12 0x05 +# define FSEL_12 0x07 +# define M2_12 0x02 /* M3 of 2 */ + +# define M_12_ES1 0x85 /* 0x10A */ +# define N_12_ES1 0x05 /* 0x05 */ +# define FSL_12_ES1 0x07 /* 0x7 */ +# define M2_12_ES1 0x2 /* 0x2 with an M3 of 4*/ + +# define M_13 0x10A +# define N_13 0x0C +# define FSEL_13 0x3 +# define M2_13 0x1 /* M3 of 2 */ + +# define M_13_ES1 0x10A /* 0x214 */ +# define N_13_ES1 0x0C /* 0xC */ +# define FSL_13_ES1 0x3 /* 0x3 */ +# define M2_13_ES1 0x1 /* 0x2 with an M3 of 4*/ + +# define M_19p2 0x115 +# define N_19p2 0x13 +# define FSEL_19p2 0x03 +# define M2_19p2 0x01 /* M3 of 2 */ + +# define M_19p2_ES1 0x115 /* 0x299 */ +# define N_19p2_ES1 0x13 /* 0x17 */ +# define FSL_19p2_ES1 0x03 /* 0x03 */ +# define M2_19p2_ES1 0x01 /* 0x2 with M3 of 4 */ + +# define M_26 0x85 +# define N_26 0x0C +# define FSEL_26 0x07 +# define M2_26 0x01 /* M3 of 2 */ + +# define M_26_ES1 0x85 /* 0x10A */ +# define N_26_ES1 0x0C /* 0xC */ +# define FSL_26_ES1 0x07 /* 0x7 */ +# define M2_26_ES1 0x01 /* 0x2 with an M3 of 4 */ + +# define M_38p4 0x11C +# define N_38p4 0x28 +# define FSEL_38p4 0x03 +# define M2_38p4 0x01 /* M3 of 2 */ + +# define M_38p4_ES1 0x11C /* 0x299 */ +# define N_38p4_ES1 0x28 /* 0x2f */ +# define FSL_38p4_ES1 0x03 /* 0x3 */ +# define M2_38p4_ES1 0x01 /* 0x2 with an M3 of 4*/ + + # endif + +#endif /* endif _OMAP343X_CLOCKS_H_ */ diff --git a/x-loader/include/asm/arch-omap3/cpu.h b/x-loader/include/asm/arch-omap3/cpu.h new file mode 100644 index 0000000..0828e73 --- /dev/null +++ b/x-loader/include/asm/arch-omap3/cpu.h @@ -0,0 +1,257 @@ +/* + * (C) Copyright 2006 + * Texas Instruments, <www.ti.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#ifndef _OMAP34XX_CPU_H +#define _OMAP34XX_CPU_H +#include <asm/arch/omap3430.h> + +/* Register offsets of common modules */ +/* Control */ +#define CONTROL_STATUS (OMAP34XX_CTRL_BASE + 0x2F0) +#define OMAP34XX_MCR (OMAP34XX_CTRL_BASE + 0x8C) +#define CONTROL_SCALABLE_OMAP_STATUS (OMAP34XX_CTRL_BASE + 0x44C) +#define CONTROL_SCALABLE_OMAP_OCP (OMAP34XX_CTRL_BASE + 0x534) + + +/* Tap Information */ +#define TAP_IDCODE_REG (OMAP34XX_TAP_BASE+0x204) +#define PRODUCTION_ID (OMAP34XX_TAP_BASE+0x208) + +/* device type */ +#define DEVICE_MASK (BIT8|BIT9|BIT10) +#define TST_DEVICE 0x0 +#define EMU_DEVICE 0x1 +#define HS_DEVICE 0x2 +#define GP_DEVICE 0x3 + +/* We are not concerned with BIT5 as it only determines + * the prirotiy between memory or perpheral booting + */ +#define SYSBOOT_MASK (BIT0|BIT1|BIT2|BIT3|BIT4) + +/* GPMC CS3/cs4/cs6 not avaliable */ +#define GPMC_BASE (OMAP34XX_GPMC_BASE) +#define GPMC_SYSCONFIG (OMAP34XX_GPMC_BASE+0x10) +#define GPMC_IRQSTATUS (OMAP34XX_GPMC_BASE+0x18) +#define GPMC_IRQENABLE (OMAP34XX_GPMC_BASE+0x1C) +#define GPMC_TIMEOUT_CONTROL (OMAP34XX_GPMC_BASE+0x40) +#define GPMC_CONFIG (OMAP34XX_GPMC_BASE+0x50) +#define GPMC_STATUS (OMAP34XX_GPMC_BASE+0x54) + +#define GPMC_CONFIG_CS0 (OMAP34XX_GPMC_BASE+0x60) +#define GPMC_CONFIG_WIDTH (0x30) + +#define GPMC_CONFIG1 (0x00) +#define GPMC_CONFIG2 (0x04) +#define GPMC_CONFIG3 (0x08) +#define GPMC_CONFIG4 (0x0C) +#define GPMC_CONFIG5 (0x10) +#define GPMC_CONFIG6 (0x14) +#define GPMC_CONFIG7 (0x18) +#define GPMC_NAND_CMD (0x1C) +#define GPMC_NAND_ADR (0x20) +#define GPMC_NAND_DAT (0x24) + +#define GPMC_ECC_CONFIG (0x1F4) +#define GPMC_ECC_CONTROL (0x1F8) +#define GPMC_ECC_SIZE_CONFIG (0x1FC) +#define GPMC_ECC1_RESULT (0x200) +#define GPMC_ECC2_RESULT (0x204) +#define GPMC_ECC3_RESULT (0x208) +#define GPMC_ECC4_RESULT (0x20C) +#define GPMC_ECC5_RESULT (0x210) +#define GPMC_ECC6_RESULT (0x214) +#define GPMC_ECC7_RESULT (0x218) +#define GPMC_ECC8_RESULT (0x21C) +#define GPMC_ECC9_RESULT (0x220) + + +/* GPMC Mapping */ +# define FLASH_BASE 0x10000000 /* NOR flash (aligned to 256 Meg) */ +# define FLASH_BASE_SDPV1 0x04000000 /* NOR flash (aligned to 64 Meg) */ +# define FLASH_BASE_SDPV2 0x10000000 /* NOR flash (aligned to 256 Meg) */ +# define DEBUG_BASE 0x08000000 /* debug board */ +# define NAND_BASE 0x30000000 /* NAND addr (actual size small port)*/ +# define PISMO2_BASE 0x18000000 /* PISMO2 CS1/2 */ +# define ONENAND_MAP 0x20000000 /* OneNand addr (actual size small port */ + +/* SMS */ +#define SMS_SYSCONFIG (OMAP34XX_SMS_BASE+0x10) +#define SMS_RG_ATT0 (OMAP34XX_SMS_BASE+0x48) +#define SMS_CLASS_ARB0 (OMAP34XX_SMS_BASE+0xD0) +#define BURSTCOMPLETE_GROUP7 BIT31 + +/* SDRC */ +#define SDRC_SYSCONFIG (OMAP34XX_SDRC_BASE+0x10) +#define SDRC_STATUS (OMAP34XX_SDRC_BASE+0x14) +#define SDRC_CS_CFG (OMAP34XX_SDRC_BASE+0x40) +#define SDRC_SHARING (OMAP34XX_SDRC_BASE+0x44) +#define SDRC_DLLA_CTRL (OMAP34XX_SDRC_BASE+0x60) +#define SDRC_DLLA_STATUS (OMAP34XX_SDRC_BASE+0x64) +#define SDRC_DLLB_CTRL (OMAP34XX_SDRC_BASE+0x68) +#define SDRC_DLLB_STATUS (OMAP34XX_SDRC_BASE+0x6C) +#define DLLPHASE BIT1 +#define LOADDLL BIT2 +#define DLL_DELAY_MASK 0xFF00 +#define DLL_NO_FILTER_MASK (BIT8|BIT9) + +#define SDRC_POWER (OMAP34XX_SDRC_BASE+0x70) +#define WAKEUPPROC BIT26 + +#define SDRC_MCFG_0 (OMAP34XX_SDRC_BASE+0x80) +#define SDRC_MCFG_1 (OMAP34XX_SDRC_BASE+0xB0) +#define SDRC_MR_0 (OMAP34XX_SDRC_BASE+0x84) +#define SDRC_MR_1 (OMAP34XX_SDRC_BASE+0xB4) +#define SDRC_ACTIM_CTRLA_0 (OMAP34XX_SDRC_BASE+0x9C) +#define SDRC_ACTIM_CTRLB_0 (OMAP34XX_SDRC_BASE+0xA0) +#define SDRC_ACTIM_CTRLA_1 (OMAP34XX_SDRC_BASE+0xC4) +#define SDRC_ACTIM_CTRLB_1 (OMAP34XX_SDRC_BASE+0xC8) +#define SDRC_RFR_CTRL_0 (OMAP34XX_SDRC_BASE+0xA4) +#define SDRC_RFR_CTRL_1 (OMAP34XX_SDRC_BASE+0xD4) +#define SDRC_MANUAL_0 (OMAP34XX_SDRC_BASE+0xA8) +#define SDRC_MANUAL_1 (OMAP34XX_SDRC_BASE+0xD8) +#define OMAP34XX_SDRC_CS0 0x80000000 +#define OMAP34XX_SDRC_CS1 0xA0000000 +#define CMD_NOP 0x0 +#define CMD_PRECHARGE 0x1 +#define CMD_AUTOREFRESH 0x2 +#define CMD_ENTR_PWRDOWN 0x3 +#define CMD_EXIT_PWRDOWN 0x4 +#define CMD_ENTR_SRFRSH 0x5 +#define CMD_CKE_HIGH 0x6 +#define CMD_CKE_LOW 0x7 +#define SOFTRESET BIT1 +#define SMART_IDLE (0x2 << 3) +#define REF_ON_IDLE (0x1 << 6) + +/* timer regs offsets (32 bit regs) */ +#define TIDR 0x0 /* r */ +#define TIOCP_CFG 0x10 /* rw */ +#define TISTAT 0x14 /* r */ +#define TISR 0x18 /* rw */ +#define TIER 0x1C /* rw */ +#define TWER 0x20 /* rw */ +#define TCLR 0x24 /* rw */ +#define TCRR 0x28 /* rw */ +#define TLDR 0x2C /* rw */ +#define TTGR 0x30 /* rw */ +#define TWPS 0x34 /* r */ +#define TMAR 0x38 /* rw */ +#define TCAR1 0x3c /* r */ +#define TSICR 0x40 /* rw */ +#define TCAR2 0x44 /* r */ +#define GPT_EN ((0<<2)|BIT1|BIT0) /* enable sys_clk NO-prescale /1 */ + +/* Watchdog */ +#define WWPS 0x34 /* r */ +#define WSPR 0x48 /* rw */ +#define WD_UNLOCK1 0xAAAA +#define WD_UNLOCK2 0x5555 + +/* PRCM */ +#define CM_FCLKEN_IVA2 0x48004000 +#define CM_CLKEN_PLL_IVA2 0x48004004 +#define CM_IDLEST_PLL_IVA2 0x48004024 +#define CM_CLKSEL1_PLL_IVA2 0x48004040 +#define CM_CLKSEL2_PLL_IVA2 0x48004044 +#define CM_CLKEN_PLL_MPU 0x48004904 +#define CM_IDLEST_PLL_MPU 0x48004924 +#define CM_CLKSEL1_PLL_MPU 0x48004940 +#define CM_CLKSEL2_PLL_MPU 0x48004944 +#define CM_FCLKEN1_CORE 0x48004a00 +#define CM_ICLKEN1_CORE 0x48004a10 +#define CM_ICLKEN2_CORE 0x48004a14 +#define CM_CLKSEL_CORE 0x48004a40 +#define CM_FCLKEN_GFX 0x48004b00 +#define CM_ICLKEN_GFX 0x48004b10 +#define CM_CLKSEL_GFX 0x48004b40 +#define CM_FCLKEN_WKUP 0x48004c00 +#define CM_ICLKEN_WKUP 0x48004c10 +#define CM_CLKSEL_WKUP 0x48004c40 +#define CM_IDLEST_WKUP 0x48004c20 +#define CM_CLKEN_PLL 0x48004d00 +#define CM_IDLEST_CKGEN 0x48004d20 +#define CM_CLKSEL1_PLL 0x48004d40 +#define CM_CLKSEL2_PLL 0x48004d44 +#define CM_CLKSEL3_PLL 0x48004d48 +#define CM_FCLKEN_DSS 0x48004e00 +#define CM_ICLKEN_DSS 0x48004e10 +#define CM_CLKSEL_DSS 0x48004e40 +#define CM_FCLKEN_CAM 0x48004f00 +#define CM_ICLKEN_CAM 0x48004f10 +#define CM_CLKSEL_CAM 0x48004F40 +#define CM_FCLKEN_PER 0x48005000 +#define CM_ICLKEN_PER 0x48005010 +#define CM_CLKSEL_PER 0x48005040 +#define CM_CLKSEL1_EMU 0x48005140 + +#define PRM_CLKSEL 0x48306d40 +#define PRM_RSTCTRL 0x48307250 +#define PRM_CLKSRC_CTRL 0x48307270 + +#define SYSCLKDIV_2 (0x1 << 7) + +/* SMX-APE */ +#define PM_RT_APE_BASE_ADDR_ARM (SMX_APE_BASE + 0x10000) +#define PM_GPMC_BASE_ADDR_ARM (SMX_APE_BASE + 0x12400) +#define PM_OCM_RAM_BASE_ADDR_ARM (SMX_APE_BASE + 0x12800) +#define PM_OCM_ROM_BASE_ADDR_ARM (SMX_APE_BASE + 0x12C00) +#define PM_IVA2_BASE_ADDR_ARM (SMX_APE_BASE + 0x14000) + +#define RT_REQ_INFO_PERMISSION_1 (PM_RT_APE_BASE_ADDR_ARM + 0x68) +#define RT_READ_PERMISSION_0 (PM_RT_APE_BASE_ADDR_ARM + 0x50) +#define RT_WRITE_PERMISSION_0 (PM_RT_APE_BASE_ADDR_ARM + 0x58) +#define RT_ADDR_MATCH_1 (PM_RT_APE_BASE_ADDR_ARM + 0x60) + +#define GPMC_REQ_INFO_PERMISSION_0 (PM_GPMC_BASE_ADDR_ARM + 0x48) +#define GPMC_READ_PERMISSION_0 (PM_GPMC_BASE_ADDR_ARM + 0x50) +#define GPMC_WRITE_PERMISSION_0 (PM_GPMC_BASE_ADDR_ARM + 0x58) + +#define OCM_REQ_INFO_PERMISSION_0 (PM_OCM_RAM_BASE_ADDR_ARM + 0x48) +#define OCM_READ_PERMISSION_0 (PM_OCM_RAM_BASE_ADDR_ARM + 0x50) +#define OCM_WRITE_PERMISSION_0 (PM_OCM_RAM_BASE_ADDR_ARM + 0x58) +#define OCM_ADDR_MATCH_2 (PM_OCM_RAM_BASE_ADDR_ARM + 0x80) + +#define IVA2_REQ_INFO_PERMISSION_0 (PM_IVA2_BASE_ADDR_ARM + 0x48) +#define IVA2_READ_PERMISSION_0 (PM_IVA2_BASE_ADDR_ARM + 0x50) +#define IVA2_WRITE_PERMISSION_0 (PM_IVA2_BASE_ADDR_ARM + 0x58) + +#define IVA2_REQ_INFO_PERMISSION_1 (PM_IVA2_BASE_ADDR_ARM + 0x68) +#define IVA2_READ_PERMISSION_1 (PM_IVA2_BASE_ADDR_ARM + 0x70) +#define IVA2_WRITE_PERMISSION_1 (PM_IVA2_BASE_ADDR_ARM + 0x78) + +#define IVA2_REQ_INFO_PERMISSION_2 (PM_IVA2_BASE_ADDR_ARM + 0x88) +#define IVA2_READ_PERMISSION_2 (PM_IVA2_BASE_ADDR_ARM + 0x90) +#define IVA2_WRITE_PERMISSION_2 (PM_IVA2_BASE_ADDR_ARM + 0x98) + +#define IVA2_REQ_INFO_PERMISSION_3 (PM_IVA2_BASE_ADDR_ARM + 0xA8) +#define IVA2_READ_PERMISSION_3 (PM_IVA2_BASE_ADDR_ARM + 0xB0) +#define IVA2_WRITE_PERMISSION_3 (PM_IVA2_BASE_ADDR_ARM + 0xB8) + +/* I2C base */ +#define I2C_BASE1 (OMAP34XX_CORE_L4_IO_BASE + 0x70000) +#define I2C_BASE2 (OMAP34XX_CORE_L4_IO_BASE + 0x72000) +#define I2C_BASE3 (OMAP34XX_CORE_L4_IO_BASE + 0x60000) + +#endif diff --git a/x-loader/include/asm/arch-omap3/gpio.h b/x-loader/include/asm/arch-omap3/gpio.h new file mode 100644 index 0000000..30f633c --- /dev/null +++ b/x-loader/include/asm/arch-omap3/gpio.h @@ -0,0 +1,86 @@ +/* + * Copyright (c) 2009 Wind River Systems, Inc. + * Tom Rix <Tom.Rix@windriver.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * This work is derived from the linux 2.6.27 kernel source + * To fetch, use the kernel repository + * git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6.git + * Use the v2.6.27 tag. + * + * Below is the original's header including its copyright + * + * linux/arch/arm/plat-omap/gpio.c + * + * Support functions for OMAP GPIO + * + * Copyright (C) 2003-2005 Nokia Corporation + * Written by Juha Yrjölä <juha.yrjola@nokia.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef _GPIO_H +#define _GPIO_H + +#define OMAP24XX_GPIO_REVISION 0x0000 +#define OMAP24XX_GPIO_SYSCONFIG 0x0010 +#define OMAP24XX_GPIO_SYSSTATUS 0x0014 +#define OMAP24XX_GPIO_IRQSTATUS1 0x0018 +#define OMAP24XX_GPIO_IRQSTATUS2 0x0028 +#define OMAP24XX_GPIO_IRQENABLE2 0x002c +#define OMAP24XX_GPIO_IRQENABLE1 0x001c +#define OMAP24XX_GPIO_WAKE_EN 0x0020 +#define OMAP24XX_GPIO_CTRL 0x0030 +#define OMAP24XX_GPIO_OE 0x0034 +#define OMAP24XX_GPIO_DATAIN 0x0038 +#define OMAP24XX_GPIO_DATAOUT 0x003c +#define OMAP24XX_GPIO_LEVELDETECT0 0x0040 +#define OMAP24XX_GPIO_LEVELDETECT1 0x0044 +#define OMAP24XX_GPIO_RISINGDETECT 0x0048 +#define OMAP24XX_GPIO_FALLINGDETECT 0x004c +#define OMAP24XX_GPIO_DEBOUNCE_EN 0x0050 +#define OMAP24XX_GPIO_DEBOUNCE_VAL 0x0054 +#define OMAP24XX_GPIO_CLEARIRQENABLE1 0x0060 +#define OMAP24XX_GPIO_SETIRQENABLE1 0x0064 +#define OMAP24XX_GPIO_CLEARWKUENA 0x0080 +#define OMAP24XX_GPIO_SETWKUENA 0x0084 +#define OMAP24XX_GPIO_CLEARDATAOUT 0x0090 +#define OMAP24XX_GPIO_SETDATAOUT 0x0094 + +struct gpio_bank { + void *base; + int method; +}; + +#define METHOD_GPIO_24XX 4 + +/* This is the interface */ + +/* Request a gpio before using it */ +int omap_request_gpio(int gpio); +/* Reset and free a gpio after using it */ +void omap_free_gpio(int gpio); +/* Sets the gpio as input or output */ +void omap_set_gpio_direction(int gpio, int is_input); +/* Set or clear a gpio output */ +void omap_set_gpio_dataout(int gpio, int enable); +/* Get the value of a gpio input */ +int omap_get_gpio_datain(int gpio); + +#endif /* _GPIO_H_ */ diff --git a/x-loader/include/asm/arch-omap3/i2c.h b/x-loader/include/asm/arch-omap3/i2c.h new file mode 100644 index 0000000..5fb0979 --- /dev/null +++ b/x-loader/include/asm/arch-omap3/i2c.h @@ -0,0 +1,128 @@ +/* + * (C) Copyright 2004-2008 + * Texas Instruments, <www.ti.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _I2C_H_ +#define _I2C_H_ + +#define I2C_DEFAULT_BASE I2C_BASE1 + +#define I2C_REV (I2C_DEFAULT_BASE + 0x00) +#define I2C_IE (I2C_DEFAULT_BASE + 0x04) +#define I2C_STAT (I2C_DEFAULT_BASE + 0x08) +#define I2C_IV (I2C_DEFAULT_BASE + 0x0c) +#define I2C_BUF (I2C_DEFAULT_BASE + 0x14) +#define I2C_CNT (I2C_DEFAULT_BASE + 0x18) +#define I2C_DATA (I2C_DEFAULT_BASE + 0x1c) +#define I2C_SYSC (I2C_DEFAULT_BASE + 0x20) +#define I2C_CON (I2C_DEFAULT_BASE + 0x24) +#define I2C_OA (I2C_DEFAULT_BASE + 0x28) +#define I2C_SA (I2C_DEFAULT_BASE + 0x2c) +#define I2C_PSC (I2C_DEFAULT_BASE + 0x30) +#define I2C_SCLL (I2C_DEFAULT_BASE + 0x34) +#define I2C_SCLH (I2C_DEFAULT_BASE + 0x38) +#define I2C_SYSTEST (I2C_DEFAULT_BASE + 0x3c) + +/* I2C masks */ + +/* I2C Interrupt Enable Register (I2C_IE): */ +#define I2C_IE_GC_IE (1 << 5) +#define I2C_IE_XRDY_IE (1 << 4) /* Transmit data ready interrupt enable */ +#define I2C_IE_RRDY_IE (1 << 3) /* Receive data ready interrupt enable */ +#define I2C_IE_ARDY_IE (1 << 2) /* Register access ready interrupt enable */ +#define I2C_IE_NACK_IE (1 << 1) /* No acknowledgment interrupt enable */ +#define I2C_IE_AL_IE (1 << 0) /* Arbitration lost interrupt enable */ + +/* I2C Status Register (I2C_STAT): */ + +#define I2C_STAT_SBD (1 << 15) /* Single byte data */ +#define I2C_STAT_BB (1 << 12) /* Bus busy */ +#define I2C_STAT_ROVR (1 << 11) /* Receive overrun */ +#define I2C_STAT_XUDF (1 << 10) /* Transmit underflow */ +#define I2C_STAT_AAS (1 << 9) /* Address as slave */ +#define I2C_STAT_GC (1 << 5) +#define I2C_STAT_XRDY (1 << 4) /* Transmit data ready */ +#define I2C_STAT_RRDY (1 << 3) /* Receive data ready */ +#define I2C_STAT_ARDY (1 << 2) /* Register access ready */ +#define I2C_STAT_NACK (1 << 1) /* No acknowledgment interrupt enable */ +#define I2C_STAT_AL (1 << 0) /* Arbitration lost interrupt enable */ + +/* I2C Interrupt Code Register (I2C_INTCODE): */ + +#define I2C_INTCODE_MASK 7 +#define I2C_INTCODE_NONE 0 +#define I2C_INTCODE_AL 1 /* Arbitration lost */ +#define I2C_INTCODE_NAK 2 /* No acknowledgement/general call */ +#define I2C_INTCODE_ARDY 3 /* Register access ready */ +#define I2C_INTCODE_RRDY 4 /* Rcv data ready */ +#define I2C_INTCODE_XRDY 5 /* Xmit data ready */ + +/* I2C Buffer Configuration Register (I2C_BUF): */ + +#define I2C_BUF_RDMA_EN (1 << 15) /* Receive DMA channel enable */ +#define I2C_BUF_XDMA_EN (1 << 7) /* Transmit DMA channel enable */ + +/* I2C Configuration Register (I2C_CON): */ + +#define I2C_CON_EN (1 << 15) /* I2C module enable */ +#define I2C_CON_BE (1 << 14) /* Big endian mode */ +#define I2C_CON_STB (1 << 11) /* Start byte mode (master mode only) */ +#define I2C_CON_MST (1 << 10) /* Master/slave mode */ +#define I2C_CON_TRX (1 << 9) /* Transmitter/receiver mode /* + /* (master mode only) */ +#define I2C_CON_XA (1 << 8) /* Expand address */ +#define I2C_CON_STP (1 << 1) /* Stop condition (master mode only) */ +#define I2C_CON_STT (1 << 0) /* Start condition (master mode only) */ + +/* I2C System Test Register (I2C_SYSTEST): */ + +#define I2C_SYSTEST_ST_EN (1 << 15) /* System test enable */ +#define I2C_SYSTEST_FREE (1 << 14) /* Free running mode, on brkpoint) */ +#define I2C_SYSTEST_TMODE_MASK (3 << 12) /* Test mode select */ +#define I2C_SYSTEST_TMODE_SHIFT (12) /* Test mode select */ +#define I2C_SYSTEST_SCL_I (1 << 3) /* SCL line sense input value */ +#define I2C_SYSTEST_SCL_O (1 << 2) /* SCL line drive output value */ +#define I2C_SYSTEST_SDA_I (1 << 1) /* SDA line sense input value */ +#define I2C_SYSTEST_SDA_O (1 << 0) /* SDA line drive output value */ + +#define I2C_SCLL_SCLL (0) +#define I2C_SCLL_SCLL_M (0xFF) +#define I2C_SCLL_HSSCLL (8) +#define I2C_SCLH_HSSCLL_M (0xFF) +#define I2C_SCLH_SCLH (0) +#define I2C_SCLH_SCLH_M (0xFF) +#define I2C_SCLH_HSSCLH (8) +#define I2C_SCLH_HSSCLH_M (0xFF) + +#define OMAP_I2C_STANDARD 100 +#define OMAP_I2C_FAST_MODE 400 +#define OMAP_I2C_HIGH_SPEED 3400 + +#define SYSTEM_CLOCK_12 12000 +#define SYSTEM_CLOCK_13 13000 +#define SYSTEM_CLOCK_192 19200 +#define SYSTEM_CLOCK_96 96000 + +#define I2C_IP_CLK SYSTEM_CLOCK_96 +#define I2C_PSC_MAX (0x0f) +#define I2C_PSC_MIN (0x00) + +#endif /* _I2C_H_ */ diff --git a/x-loader/include/asm/arch-omap3/mem.h b/x-loader/include/asm/arch-omap3/mem.h new file mode 100644 index 0000000..cba4c6f --- /dev/null +++ b/x-loader/include/asm/arch-omap3/mem.h @@ -0,0 +1,509 @@ +/* + * (C) Copyright 2006 + * Texas Instruments, <www.ti.com> + * Richard Woodruff <r-woodruff2@ti.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _OMAP34XX_MEM_H_ +#define _OMAP34XX_MEM_H_ + +#define SDRC_CS0_OSET 0x0 +#define SDRC_CS1_OSET 0x30 /* mirror CS1 regs appear offset 0x30 from CS0 */ + +#ifndef __ASSEMBLY__ + +typedef enum { + STACKED = 0, + IP_DDR = 1, + COMBO_DDR = 2, + IP_SDR = 3, +} mem_t; + + +/* Memory that can be connected to GPMC */ +#define GPMC_NOR 0 +#define GPMC_NAND 1 +#define GPMC_MDOC 2 +#define GPMC_ONENAND 3 +#define MMC_NAND 4 +#define MMC_ONENAND 5 +#define GPMC_NONE 6 + +#endif + +/* set the 343x-SDRC incoming address convention */ +#if defined(SDRC_B_R_C) +#define B_ALL (0 << 6) /* bank-row-column */ +#elif defined(SDRC_B1_R_B0_C) +#define B_ALL (1 << 6) /* bank1-row-bank0-column */ +#elif defined(SDRC_R_B_C) +#define B_ALL (2 << 6) /* row-bank-column */ +#endif + +/* Future memory combinations based on past */ +#define SDP_SDRC_MDCFG_MONO_DDR 0x0 +#define SDP_COMBO_MDCFG_0_DDR 0x0 +#define SDP_SDRC_MDCFG_0_SDR 0x0 + +/* Slower full frequency range default timings for x32 operation*/ +#define SDP_SDRC_SHARING 0x00000100 +#define SDP_SDRC_MR_0_SDR 0x00000031 + +#ifdef CONFIG_3430ZEBU +#define SDP_SDRC_MDCFG_0_DDR (0x02582019|B_ALL) /* Infin ddr module */ +#else +#define SDP_SDRC_MDCFG_0_DDR (0x02584019|B_ALL) +#define SDP_SDRC_MDCFG_0_DDR_XM (0x03588019|B_ALL) +#endif + +#define SDP_SDRC_MR_0_DDR 0x00000032 + +/* Diabling power down mode using CKE pin */ +#define SDP_SDRC_POWER_POP 0x00000081 + +/* optimized timings good for current shipping parts */ +#define SDP_3430_SDRC_RFR_CTRL_100MHz 0x0002da01 +#define SDP_3430_SDRC_RFR_CTRL_133MHz 0x0003de01 /* 7.8us/7.5ns - 50=0x3de */ +#define SDP_3430_SDRC_RFR_CTRL_165MHz 0x0004e201 /* 7.8us/6ns - 50=0x4e2 */ +#define SDP_3430_SDRC_RFR_CTRL_200MHz 0x0005e601 /* 7.8us/5ns - 50=0x5e6 */ + +#define DLL_OFFSET 0 +#define DLL_WRITEDDRCLKX2DIS 1 +#define DLL_ENADLL 1 +#define DLL_LOCKDLL 0 +#define DLL_DLLPHASE_72 0 +#define DLL_DLLPHASE_90 1 + +// rkw - need to find of 90/72 degree recommendation for speed like before. +#define SDP_SDRC_DLLAB_CTRL ((DLL_ENADLL << 3) | \ + (DLL_LOCKDLL << 2) | (DLL_DLLPHASE_90 << 1)) + +/* Infineon part of 3430SDP (133MHz optimized) ~ 7.5ns + * TDAL = Twr/Tck + Trp/tck = 15/7.5 + 22.5/7.5 = 2 + 3 = 5 + * TDPL = 15/7.5 = 2 + * TRRD = 15/2.5 = 2 + * TRCD = 22.5/7.5 = 3 + * TRP = 22.5/7.5 = 3 + * TRAS = 45/7.5 = 6 + * TRC = 65/7.5 = 8.6->9 + * TRFC = 75/7.5 = 10 + * ACTIMB + * TCKE = 2 + * XSR = 120/7.5 = 16 + */ +#define INFINEON_TDAL_133 5 +#define INFINEON_TDPL_133 2 +#define INFINEON_TRRD_133 2 +#define INFINEON_TRCD_133 3 +#define INFINEON_TRP_133 3 +#define INFINEON_TRAS_133 6 +#define INFINEON_TRC_133 9 +#define INFINEON_TRFC_133 10 +#define INFINEON_V_ACTIMA_133 ((INFINEON_TRFC_133 << 27) | (INFINEON_TRC_133 << 22) | (INFINEON_TRAS_133 << 18) \ + |(INFINEON_TRP_133 << 15) | (INFINEON_TRCD_133 << 12) |(INFINEON_TRRD_133 << 9) |(INFINEON_TDPL_133 << 6) \ + | (INFINEON_TDAL_133)) + +#define INFINEON_TWTR_133 1 +#define INFINEON_TCKE_133 2 +#define INFINEON_TXP_133 2 +#define INFINEON_XSR_133 16 +#define INFINEON_V_ACTIMB_133 ((INFINEON_TCKE_133 << 12) | (INFINEON_XSR_133 << 0)) | \ + (INFINEON_TXP_133 << 8) | (INFINEON_TWTR_133 << 16) + +#define INFINEON_V_ACTIMA_100 INFINEON_V_ACTIMA_133 +#define INFINEON_V_ACTIMB_100 INFINEON_V_ACTIMB_133 + + +/* Infineon part of 3430SDP (165MHz optimized) 6.06ns + * ACTIMA + * TDAL = Twr/Tck + Trp/tck = 15/6 + 18/6 = 2.5 + 3 = 5.5 -> 6 + * TDPL (Twr) = 15/6 = 2.5 -> 3 + * TRRD = 12/6 = 2 + * TRCD = 18/6 = 3 + * TRP = 18/6 = 3 + * TRAS = 42/6 = 7 + * TRC = 60/6 = 10 + * TRFC = 72/6 = 12 + * ACTIMB + * TCKE = 2 + * XSR = 120/6 = 20 + */ +#define INFINEON_TDAL_165 6 +#define INFINEON_TDPL_165 3 +#define INFINEON_TRRD_165 2 +#define INFINEON_TRCD_165 3 +#define INFINEON_TRP_165 3 +#define INFINEON_TRAS_165 7 +#define INFINEON_TRC_165 10 +#define INFINEON_TRFC_165 12 +#define INFINEON_V_ACTIMA_165 ((INFINEON_TRFC_165 << 27) | (INFINEON_TRC_165 << 22) | (INFINEON_TRAS_165 << 18) \ + | (INFINEON_TRP_165 << 15) | (INFINEON_TRCD_165 << 12) |(INFINEON_TRRD_165 << 9) | \ + (INFINEON_TDPL_165 << 6) | (INFINEON_TDAL_165)) + +#define INFINEON_TWTR_165 1 +#define INFINEON_TCKE_165 2 +#define INFINEON_TXP_165 2 +#define INFINEON_XSR_165 20 +#define INFINEON_V_ACTIMB_165 ((INFINEON_TCKE_165 << 12) | (INFINEON_XSR_165 << 0)) | \ + (INFINEON_TXP_165 << 8) | (INFINEON_TWTR_165 << 16) + +/* Micron part of 3430 EVM (133MHz optimized) ~ 7.5ns + * TDAL = Twr/Tck + Trp/tck = 15/7.5 + 22.5/7.5 = 2 + 3 = 5 + * TDPL = 15/7.5 = 2 + * TRRD = 15/7.5 = 2 + * TRCD = 22.5/7.5 = 3 + * TRP = 22.5/7.5 = 3 + * TRAS = 45/7.5 = 6 + * TRC = 75/7.5 = 10 + * TRFC = 125/7.5 = 16.6->17 + * ACTIMB + * TWTR = 1 + * TCKE = 1 + * TXSR = 138/7.5 = 18.3->19 + * TXP = 25/7.5 = 3.3->4 + */ +#define MICRON_TDAL_133 5 +#define MICRON_TDPL_133 2 +#define MICRON_TRRD_133 2 +#define MICRON_TRCD_133 3 +#define MICRON_TRP_133 3 +#define MICRON_TRAS_133 6 +#define MICRON_TRC_133 10 +#define MICRON_TRFC_133 17 +#define MICRON_V_ACTIMA_133 ((MICRON_TRFC_133 << 27) | (MICRON_TRC_133 << 22) | (MICRON_TRAS_133 << 18) \ + |(MICRON_TRP_133 << 15) | (MICRON_TRCD_133 << 12) |(MICRON_TRRD_133 << 9) |(MICRON_TDPL_133 << 6) \ + | (MICRON_TDAL_133)) + +#define MICRON_TWTR_133 1 +#define MICRON_TCKE_133 1 +#define MICRON_TXSR_133 19 +#define MICRON_TXP_133 4 +#define MICRON_V_ACTIMB_133 ((MICRON_TWTR_133 << 16) | (MICRON_TCKE_133 << 12) | (MICRON_TXP_133 << 8) \ + | (MICRON_TXSR_133 << 0)) + +#define MICRON_V_ACTIMA_100 MICRON_V_ACTIMA_133 +#define MICRON_V_ACTIMB_100 MICRON_V_ACTIMB_133 + +/* Micron part of 3430 EVM (165MHz optimized) 6.06ns + * ACTIMA + * TDAL = Twr/Tck + Trp/tck = 15/6 + 18 /6 = 2.5 + 3 = 5.5 -> 6 + * TDPL (Twr) = 15/6 = 2.5 -> 3 + * TRRD = 12/6 = 2 + * TRCD = 18/6 = 3 + * TRP = 18/6 = 3 + * TRAS = 42/6 = 7 + * TRC = 60/6 = 10 + * TRFC = 125/6 = 21 + * ACTIMB + * TWTR = 1 + * TCKE = 1 + * TXSR = 138/6 = 23 + * TXP = 25/6 = 4.1 ~5 + */ +#define MICRON_TDAL_165 6 +#define MICRON_TDPL_165 3 +#define MICRON_TRRD_165 2 +#define MICRON_TRCD_165 3 +#define MICRON_TRP_165 3 +#define MICRON_TRAS_165 7 +#define MICRON_TRC_165 10 +#define MICRON_TRFC_165 21 +#define MICRON_V_ACTIMA_165 ((MICRON_TRFC_165 << 27) | (MICRON_TRC_165 << 22) | (MICRON_TRAS_165 << 18) \ + | (MICRON_TRP_165 << 15) | (MICRON_TRCD_165 << 12) |(MICRON_TRRD_165 << 9) | \ + (MICRON_TDPL_165 << 6) | (MICRON_TDAL_165)) + +#define MICRON_TWTR_165 1 +#define MICRON_TCKE_165 1 +#define MICRON_TXP_165 5 +#define MICRON_XSR_165 23 +#define MICRON_V_ACTIMB_165 ((MICRON_TCKE_165 << 12) | (MICRON_XSR_165 << 0)) | \ + (MICRON_TXP_165 << 8) | (MICRON_TWTR_165 << 16) + +/* Micron part (200MHz optimized) 5 ns + */ +#define MICRON_TDAL_200 6 +#define MICRON_TDPL_200 3 +#define MICRON_TRRD_200 2 +#define MICRON_TRCD_200 3 +#define MICRON_TRP_200 3 +#define MICRON_TRAS_200 8 +#define MICRON_TRC_200 11 +#define MICRON_TRFC_200 15 +#define MICRON_V_ACTIMA_200 ((MICRON_TRFC_200 << 27) | (MICRON_TRC_200 << 22) | (MICRON_TRAS_200 << 18) \ + | (MICRON_TRP_200 << 15) | (MICRON_TRCD_200 << 12) |(MICRON_TRRD_200 << 9) | \ + (MICRON_TDPL_200 << 6) | (MICRON_TDAL_200)) + +#define MICRON_TWTR_200 2 +#define MICRON_TCKE_200 1 +#define MICRON_TXP_200 2 +#define MICRON_XSR_200 23 +#define MICRON_V_ACTIMB_200 ((MICRON_TCKE_200 << 12) | (MICRON_XSR_200 << 0)) | \ + (MICRON_TXP_200 << 8) | (MICRON_TWTR_200 << 16) + +/* New and compatability speed defines */ +#if defined(PRCM_CLK_CFG2_200MHZ) || defined(PRCM_CONFIG_II) || defined(PRCM_CONFIG_5B) +# define L3_100MHZ /* Use with <= 100MHz SDRAM */ +#elif defined (PRCM_CLK_CFG2_266MHZ) || defined(PRCM_CONFIG_III) || defined(PRCM_CONFIG_5A) +# define L3_133MHZ /* Use with <= 133MHz SDRAM*/ +#elif defined(PRCM_CLK_CFG2_332MHZ) || defined(PRCM_CONFIG_I) || defined(PRCM_CONFIG_2) +# define L3_165MHZ /* Use with <= 165MHz SDRAM (L3=166 on 3430) */ +#endif + +#if defined(L3_100MHZ) +# define MICRON_SDRC_ACTIM_CTRLA_0 MICRON_V_ACTIMA_100 +# define MICRON_SDRC_ACTIM_CTRLB_0 MICRON_V_ACTIMB_100 +#elif defined(L3_133MHZ) +# define MICRON_SDRC_ACTIM_CTRLA_0 MICRON_V_ACTIMA_133 +# define MICRON_SDRC_ACTIM_CTRLB_0 MICRON_V_ACTIMB_133 +#elif defined(L3_165MHZ) +# define MICRON_SDRC_ACTIM_CTRLA_0 MICRON_V_ACTIMA_165 +# define MICRON_SDRC_ACTIM_CTRLB_0 MICRON_V_ACTIMB_165 +#endif + + +#if defined(L3_100MHZ) +# define INFINEON_SDRC_ACTIM_CTRLA_0 INFINEON_V_ACTIMA_100 +# define INFINEON_SDRC_ACTIM_CTRLB_0 INFINEON_V_ACTIMB_100 +#elif defined(L3_133MHZ) +# define INFINEON_SDRC_ACTIM_CTRLA_0 INFINEON_V_ACTIMA_133 +# define INFINEON_SDRC_ACTIM_CTRLB_0 INFINEON_V_ACTIMB_133 +#elif defined(L3_165MHZ) +# define INFINEON_SDRC_ACTIM_CTRLA_0 INFINEON_V_ACTIMA_165 +# define INFINEON_SDRC_ACTIM_CTRLB_0 INFINEON_V_ACTIMB_165 +#endif + +#if defined(L3_100MHZ) +# define SDP_SDRC_RFR_CTRL SDP_3430_SDRC_RFR_CTRL_100MHz +#elif defined(L3_133MHZ) +# define SDP_SDRC_RFR_CTRL SDP_3430_SDRC_RFR_CTRL_133MHz +#elif defined(L3_165MHZ) +# define SDP_SDRC_RFR_CTRL SDP_3430_SDRC_RFR_CTRL_165MHz +#endif + +/* + * GPMC settings - + * Definitions is as per the following format + * # define <PART>_GPMC_CONFIG<x> <value> + * Where: + * PART is the part name e.g. STNOR - Intel Strata Flash + * x is GPMC config registers from 1 to 6 (there will be 6 macros) + * Value is corresponding value + * + * For every valid PRCM configuration there should be only one definition of + * the same. if values are independent of the board, this definition will be + * present in this file if values are dependent on the board, then this should + * go into corresponding mem-boardName.h file + * + * Currently valid part Names are (PART): + * STNOR - Intel Strata Flash + * SMNAND - Samsung NAND + * M_NAND - Micron Large page x16 NAND + * MPDB - H4 MPDB board + * SBNOR - Sibley NOR + * ONNAND - Samsung One NAND + * + * include/configs/file.h contains the defn - for all CS we are interested + * #define OMAP34XX_GPMC_CSx PART + * #define OMAP34XX_GPMC_CSx_SIZE Size + * #define OMAP34XX_GPMC_CSx_MAP Map + * Where: + * x - CS number + * PART - Part Name as defined above + * SIZE - how big is the mapping to be + * GPMC_SIZE_128M - 0x8 + * GPMC_SIZE_64M - 0xC + * GPMC_SIZE_32M - 0xE + * GPMC_SIZE_16M - 0xF + * MAP - Map this CS to which address(GPMC address space)- Absolute address + * >>24 before being used. + */ +#define GPMC_SIZE_128M 0x8 +#define GPMC_SIZE_64M 0xC +#define GPMC_SIZE_32M 0xE +#define GPMC_SIZE_16M 0xF + +#if defined(L3_100MHZ) +# define SMNAND_GPMC_CONFIG1 0x0 +# define SMNAND_GPMC_CONFIG2 0x00141400 +# define SMNAND_GPMC_CONFIG3 0x00141400 +# define SMNAND_GPMC_CONFIG4 0x0F010F01 +# define SMNAND_GPMC_CONFIG5 0x010C1414 +# define SMNAND_GPMC_CONFIG6 0x00000A80 + +# define M_NAND_GPMC_CONFIG1 0x00001800 +# define M_NAND_GPMC_CONFIG2 SMNAND_GPMC_CONFIG2 +# define M_NAND_GPMC_CONFIG3 SMNAND_GPMC_CONFIG3 +# define M_NAND_GPMC_CONFIG4 SMNAND_GPMC_CONFIG4 +# define M_NAND_GPMC_CONFIG5 SMNAND_GPMC_CONFIG5 +# define M_NAND_GPMC_CONFIG6 SMNAND_GPMC_CONFIG6 +# define STNOR_GPMC_CONFIG1 0x3 +# define STNOR_GPMC_CONFIG2 0x000f0f01 +# define STNOR_GPMC_CONFIG3 0x00050502 +# define STNOR_GPMC_CONFIG4 0x0C060C06 +# define STNOR_GPMC_CONFIG5 0x01131F1F +# define STNOR_GPMC_CONFIG6 0x0 /* 0? */ +# define MPDB_GPMC_CONFIG1 0x00011000 +# define MPDB_GPMC_CONFIG2 0x001F1F00 +# define MPDB_GPMC_CONFIG3 0x00080802 +# define MPDB_GPMC_CONFIG4 0x1C091C09 +# define MPDB_GPMC_CONFIG5 0x031A1F1F +# define MPDB_GPMC_CONFIG6 0x000003C2 +#endif + +#if defined(L3_133MHZ) +# define SMNAND_GPMC_CONFIG1 0x00000800 +# define SMNAND_GPMC_CONFIG2 0x00141400 +# define SMNAND_GPMC_CONFIG3 0x00141400 +# define SMNAND_GPMC_CONFIG4 0x0F010F01 +# define SMNAND_GPMC_CONFIG5 0x010C1414 +# define SMNAND_GPMC_CONFIG6 0x00000A80 +# define SMNAND_GPMC_CONFIG7 0x00000C44 + +# define M_NAND_GPMC_CONFIG1 0x00001800 +# define M_NAND_GPMC_CONFIG2 SMNAND_GPMC_CONFIG2 +# define M_NAND_GPMC_CONFIG3 SMNAND_GPMC_CONFIG3 +# define M_NAND_GPMC_CONFIG4 SMNAND_GPMC_CONFIG4 +# define M_NAND_GPMC_CONFIG5 SMNAND_GPMC_CONFIG5 +# define M_NAND_GPMC_CONFIG6 SMNAND_GPMC_CONFIG6 +# define M_NAND_GPMC_CONFIG7 SMNAND_GPMC_CONFIG7 + +# define STNOR_GPMC_CONFIG1 0x1203 +# define STNOR_GPMC_CONFIG2 0x00151501 +# define STNOR_GPMC_CONFIG3 0x00060602 +# define STNOR_GPMC_CONFIG4 0x10081008 +# define STNOR_GPMC_CONFIG5 0x01131F1F +# define STNOR_GPMC_CONFIG6 0x000004c4 + +# define SIBNOR_GPMC_CONFIG1 0x1200 +# define SIBNOR_GPMC_CONFIG2 0x001f1f00 +# define SIBNOR_GPMC_CONFIG3 0x00080802 +# define SIBNOR_GPMC_CONFIG4 0x1C091C09 +# define SIBNOR_GPMC_CONFIG5 0x01131F1F +# define SIBNOR_GPMC_CONFIG6 0x000003C2 + +# define MPDB_GPMC_CONFIG1 0x00011000 +# define MPDB_GPMC_CONFIG2 0x001f1f01 +# define MPDB_GPMC_CONFIG3 0x00080803 +# define MPDB_GPMC_CONFIG4 0x1C091C09 +# define MPDB_GPMC_CONFIG5 0x041f1F1F +# define MPDB_GPMC_CONFIG6 0x000004C4 + +# define P2_GPMC_CONFIG1 0x0 +# define P2_GPMC_CONFIG2 0x0 +# define P2_GPMC_CONFIG3 0x0 +# define P2_GPMC_CONFIG4 0x0 +# define P2_GPMC_CONFIG5 0x0 +# define P2_GPMC_CONFIG6 0x0 + +# define ONENAND_GPMC_CONFIG1 0x00001200 +# define ONENAND_GPMC_CONFIG2 0x000c0c01 +# define ONENAND_GPMC_CONFIG3 0x00030301 +# define ONENAND_GPMC_CONFIG4 0x0c040c04 +# define ONENAND_GPMC_CONFIG5 0x010C1010 +# define ONENAND_GPMC_CONFIG6 0x00000000 + +#endif /* endif L3_133MHZ */ + +#if defined (L3_165MHZ) +# define SMNAND_GPMC_CONFIG1 0x00000800 +# define SMNAND_GPMC_CONFIG2 0x00141400 +# define SMNAND_GPMC_CONFIG3 0x00141400 +# define SMNAND_GPMC_CONFIG4 0x0F010F01 +# define SMNAND_GPMC_CONFIG5 0x010C1414 +# define SMNAND_GPMC_CONFIG6 0x1F0F0A80 +# define SMNAND_GPMC_CONFIG7 0x00000C44 + +# define M_NAND_GPMC_CONFIG1 0x00001800 +# define M_NAND_GPMC_CONFIG2 SMNAND_GPMC_CONFIG2 +# define M_NAND_GPMC_CONFIG3 SMNAND_GPMC_CONFIG3 +# define M_NAND_GPMC_CONFIG4 SMNAND_GPMC_CONFIG4 +# define M_NAND_GPMC_CONFIG5 SMNAND_GPMC_CONFIG5 +# define M_NAND_GPMC_CONFIG6 SMNAND_GPMC_CONFIG6 +# define M_NAND_GPMC_CONFIG7 SMNAND_GPMC_CONFIG7 + +# define STNOR_GPMC_CONFIG1 0x3 +# define STNOR_GPMC_CONFIG2 0x00151501 +# define STNOR_GPMC_CONFIG3 0x00060602 +# define STNOR_GPMC_CONFIG4 0x11091109 +# define STNOR_GPMC_CONFIG5 0x01141F1F +# define STNOR_GPMC_CONFIG6 0x000004c4 + +# define SIBNOR_GPMC_CONFIG1 0x1200 +# define SIBNOR_GPMC_CONFIG2 0x001f1f00 +# define SIBNOR_GPMC_CONFIG3 0x00080802 +# define SIBNOR_GPMC_CONFIG4 0x1C091C09 +# define SIBNOR_GPMC_CONFIG5 0x01131F1F +# define SIBNOR_GPMC_CONFIG6 0x1F0F03C2 + +# define SDPV2_MPDB_GPMC_CONFIG1 0x00611200 +# define SDPV2_MPDB_GPMC_CONFIG2 0x001F1F01 +# define SDPV2_MPDB_GPMC_CONFIG3 0x00080803 +# define SDPV2_MPDB_GPMC_CONFIG4 0x1D091D09 +# define SDPV2_MPDB_GPMC_CONFIG5 0x041D1F1F +# define SDPV2_MPDB_GPMC_CONFIG6 0x1D0904C4 + +# define MPDB_GPMC_CONFIG1 0x00011000 +# define MPDB_GPMC_CONFIG2 0x001f1f01 +# define MPDB_GPMC_CONFIG3 0x00080803 +# define MPDB_GPMC_CONFIG4 0x1c0b1c0a +# define MPDB_GPMC_CONFIG5 0x041f1F1F +# define MPDB_GPMC_CONFIG6 0x1F0F04C4 + +# define P2_GPMC_CONFIG1 0x0 +# define P2_GPMC_CONFIG2 0x0 +# define P2_GPMC_CONFIG3 0x0 +# define P2_GPMC_CONFIG4 0x0 +# define P2_GPMC_CONFIG5 0x0 +# define P2_GPMC_CONFIG6 0x0 + +# define ONENAND_GPMC_CONFIG1 0x00001200 +# define ONENAND_GPMC_CONFIG2 0x000F0F01 +# define ONENAND_GPMC_CONFIG3 0x00030301 +# define ONENAND_GPMC_CONFIG4 0x0F040F04 +# define ONENAND_GPMC_CONFIG5 0x010F1010 +# define ONENAND_GPMC_CONFIG6 0x1F060000 + +#endif + +/* max number of GPMC Chip Selects */ +#define GPMC_MAX_CS 8 +/* max number of GPMC regs */ +#define GPMC_MAX_REG 7 + +#define PISMO1_NOR 1 +#define PISMO1_NAND 2 +#define PISMO2_CS0 3 +#define PISMO2_CS1 4 +#define PISMO1_ONENAND 5 +#define POP_ONENAND 5 +#define DBG_MPDB 6 +#define PISMO2_NAND_CS0 7 +#define PISMO2_NAND_CS1 8 + +/* make it readable for the gpmc_init */ +#define PISMO1_NOR_BASE FLASH_BASE +#define PISMO1_NAND_BASE NAND_BASE +#define PISMO2_CS0_BASE PISMO2_MAP1 +#define PISMO1_ONEN_BASE ONENAND_MAP +#define POP_ONEN_BASE ONENAND_MAP +#define DBG_MPDB_BASE DEBUG_BASE + +#endif /* endif _OMAP34XX_MEM_H_ */ diff --git a/x-loader/include/asm/arch-omap3/mmc.h b/x-loader/include/asm/arch-omap3/mmc.h new file mode 100644 index 0000000..8631aae --- /dev/null +++ b/x-loader/include/asm/arch-omap3/mmc.h @@ -0,0 +1,235 @@ +/* + * (C) Copyright 2008 + * Texas Instruments, <www.ti.com> + * Syed Mohammed Khasim <khasim@ti.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation's version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef MMC_H +#define MMC_H + +#include "mmc_host_def.h" + +/* Responses */ +#define RSP_TYPE_NONE (RSP_TYPE_NORSP | CCCE_NOCHECK | CICE_NOCHECK) +#define RSP_TYPE_R1 (RSP_TYPE_LGHT48 | CCCE_CHECK | CICE_CHECK) +#define RSP_TYPE_R1B (RSP_TYPE_LGHT48B | CCCE_CHECK | CICE_CHECK) +#define RSP_TYPE_R2 (RSP_TYPE_LGHT136 | CCCE_CHECK | CICE_NOCHECK) +#define RSP_TYPE_R3 (RSP_TYPE_LGHT48 | CCCE_NOCHECK | CICE_NOCHECK) +#define RSP_TYPE_R4 (RSP_TYPE_LGHT48 | CCCE_NOCHECK | CICE_NOCHECK) +#define RSP_TYPE_R5 (RSP_TYPE_LGHT48 | CCCE_CHECK | CICE_CHECK) +#define RSP_TYPE_R6 (RSP_TYPE_LGHT48 | CCCE_CHECK | CICE_CHECK) +#define RSP_TYPE_R7 (RSP_TYPE_LGHT48 | CCCE_CHECK | CICE_CHECK) + +/* All supported commands */ +#define MMC_CMD0 (INDEX(0) | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE) +#define MMC_CMD1 (INDEX(1) | RSP_TYPE_R3 | DP_NO_DATA | DDIR_WRITE) +#define MMC_CMD2 (INDEX(2) | RSP_TYPE_R2 | DP_NO_DATA | DDIR_WRITE) +#define MMC_CMD3 (INDEX(3) | RSP_TYPE_R1 | DP_NO_DATA | DDIR_WRITE) +#define MMC_SDCMD3 (INDEX(3) | RSP_TYPE_R6 | DP_NO_DATA | DDIR_WRITE) +#define MMC_CMD4 (INDEX(4) | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE) +#define MMC_CMD6 (INDEX(6) | RSP_TYPE_R1B | DP_NO_DATA | DDIR_WRITE) +#define MMC_CMD7_SELECT (INDEX(7) | RSP_TYPE_R1B | DP_NO_DATA | DDIR_WRITE) +#define MMC_CMD7_DESELECT (INDEX(7) | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE) +#define MMC_CMD8 (INDEX(8) | RSP_TYPE_R1 | DP_DATA | DDIR_READ) +#define MMC_SDCMD8 (INDEX(8) | RSP_TYPE_R7 | DP_NO_DATA | DDIR_WRITE) +#define MMC_CMD9 (INDEX(9) | RSP_TYPE_R2 | DP_NO_DATA | DDIR_WRITE) +#define MMC_CMD12 (INDEX(12) | RSP_TYPE_R1B | DP_NO_DATA | DDIR_WRITE) +#define MMC_CMD13 (INDEX(13) | RSP_TYPE_R1 | DP_NO_DATA | DDIR_WRITE) +#define MMC_CMD15 (INDEX(15) | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE) +#define MMC_CMD16 (INDEX(16) | RSP_TYPE_R1 | DP_NO_DATA | DDIR_WRITE) +#define MMC_CMD17 (INDEX(17) | RSP_TYPE_R1 | DP_DATA | DDIR_READ) +#define MMC_CMD24 (INDEX(24) | RSP_TYPE_R1 | DP_DATA | DDIR_WRITE) +#define MMC_ACMD6 (INDEX(6) | RSP_TYPE_R1 | DP_NO_DATA | DDIR_WRITE) +#define MMC_ACMD41 (INDEX(41) | RSP_TYPE_R3 | DP_NO_DATA | DDIR_WRITE) +#define MMC_ACMD51 (INDEX(51) | RSP_TYPE_R1 | DP_DATA | DDIR_READ) +#define MMC_CMD55 (INDEX(55) | RSP_TYPE_R1 | DP_NO_DATA | DDIR_WRITE) + +#define MMC_AC_CMD_RCA_MASK (unsigned int)(0xFFFF << 16) +#define MMC_BC_CMD_DSR_MASK (unsigned int)(0xFFFF << 16) +#define MMC_DSR_DEFAULT (0x0404) +#define SD_CMD8_CHECK_PATTERN (0xAA) +#define SD_CMD8_2_7_3_6_V_RANGE (0x01 << 8) + +/* Clock Configurations and Macros */ + +#define MMC_CLOCK_REFERENCE (96) +#define MMC_RELATIVE_CARD_ADDRESS (0x1234) +#define MMC_INIT_SEQ_CLK (MMC_CLOCK_REFERENCE * 1000 / 80) +#define MMC_400kHz_CLK (MMC_CLOCK_REFERENCE * 1000 / 400) +#define CLKDR(r, f, u) ((((r)*100) / ((f)*(u))) + 1) +#define CLKD(f, u) (CLKDR(MMC_CLOCK_REFERENCE, f, u)) + +#define MMC_OCR_REG_ACCESS_MODE_MASK (0x3 << 29) +#define MMC_OCR_REG_ACCESS_MODE_BYTE (0x0 << 29) +#define MMC_OCR_REG_ACCESS_MODE_SECTOR (0x2 << 29) + +#define MMC_OCR_REG_HOST_CAPACITY_SUPPORT_MASK (0x1 << 30) +#define MMC_OCR_REG_HOST_CAPACITY_SUPPORT_BYTE (0x0 << 30) +#define MMC_OCR_REG_HOST_CAPACITY_SUPPORT_SECTOR (0x1 << 30) + +#define MMC_SD2_CSD_C_SIZE_LSB_MASK (0xFFFF) +#define MMC_SD2_CSD_C_SIZE_MSB_MASK (0x003F) +#define MMC_SD2_CSD_C_SIZE_MSB_OFFSET (16) +#define MMC_CSD_C_SIZE_LSB_MASK (0x0003) +#define MMC_CSD_C_SIZE_MSB_MASK (0x03FF) +#define MMC_CSD_C_SIZE_MSB_OFFSET (2) + +#define MMC_CSD_TRAN_SPEED_UNIT_MASK (0x07 << 0) +#define MMC_CSD_TRAN_SPEED_FACTOR_MASK (0x0F << 3) +#define MMC_CSD_TRAN_SPEED_UNIT_100MHZ (0x3 << 0) +#define MMC_CSD_TRAN_SPEED_FACTOR_1_0 (0x01 << 3) +#define MMC_CSD_TRAN_SPEED_FACTOR_8_0 (0x0F << 3) + +typedef struct { + unsigned not_used:1; + unsigned crc:7; + unsigned ecc:2; + unsigned file_format:2; + unsigned tmp_write_protect:1; + unsigned perm_write_protect:1; + unsigned copy:1; + unsigned file_format_grp:1; + unsigned content_prot_app:1; + unsigned reserved_1:4; + unsigned write_bl_partial:1; + unsigned write_bl_len:4; + unsigned r2w_factor:3; + unsigned default_ecc:2; + unsigned wp_grp_enable:1; + unsigned wp_grp_size:5; + unsigned erase_grp_mult:5; + unsigned erase_grp_size:5; + unsigned c_size_mult:3; + unsigned vdd_w_curr_max:3; + unsigned vdd_w_curr_min:3; + unsigned vdd_r_curr_max:3; + unsigned vdd_r_curr_min:3; + unsigned c_size_lsb:2; + unsigned c_size_msb:10; + unsigned reserved_2:2; + unsigned dsr_imp:1; + unsigned read_blk_misalign:1; + unsigned write_blk_misalign:1; + unsigned read_bl_partial:1; + unsigned read_bl_len:4; + unsigned ccc:12; + unsigned tran_speed:8; + unsigned nsac:8; + unsigned taac:8; + unsigned reserved_3:2; + unsigned spec_vers:4; + unsigned csd_structure:2; +} mmc_csd_reg_t; + +/* csd for sd2.0 */ +typedef struct { + unsigned not_used:1; + unsigned crc:7; + unsigned reserved_1:2; + unsigned file_format:2; + unsigned tmp_write_protect:1; + unsigned perm_write_protect:1; + unsigned copy:1; + unsigned file_format_grp:1; + unsigned reserved_2:5; + unsigned write_bl_partial:1; + unsigned write_bl_len:4; + unsigned r2w_factor:3; + unsigned reserved_3:2; + unsigned wp_grp_enable:1; + unsigned wp_grp_size:7; + unsigned sector_size:7; + unsigned erase_blk_len:1; + unsigned reserved_4:1; + unsigned c_size_lsb:16; + unsigned c_size_msb:6; + unsigned reserved_5:6; + unsigned dsr_imp:1; + unsigned read_blk_misalign:1; + unsigned write_blk_misalign:1; + unsigned read_bl_partial:1; + unsigned read_bl_len:4; + unsigned ccc:12; + unsigned tran_speed:8; + unsigned nsac:8; + unsigned taac:8; + unsigned reserved_6:6; + unsigned csd_structure:2; +} mmc_sd2_csd_reg_t; + +/* extended csd - 512 bytes long */ +typedef struct { + unsigned char reserved_1[181]; + unsigned char erasedmemorycontent; + unsigned char reserved_2; + unsigned char buswidthmode; + unsigned char reserved_3; + unsigned char highspeedinterfacetiming; + unsigned char reserved_4; + unsigned char powerclass; + unsigned char reserved_5; + unsigned char commandsetrevision; + unsigned char reserved_6; + unsigned char commandset; + unsigned char extendedcsdrevision; + unsigned char reserved_7; + unsigned char csdstructureversion; + unsigned char reserved_8; + unsigned char cardtype; + unsigned char reserved_9[3]; + unsigned char powerclass_52mhz_1_95v; + unsigned char powerclass_26mhz_1_95v; + unsigned char powerclass_52mhz_3_6v; + unsigned char powerclass_26mhz_3_6v; + unsigned char reserved_10; + unsigned char minreadperf_4b_26mhz; + unsigned char minwriteperf_4b_26mhz; + unsigned char minreadperf_8b_26mhz_4b_52mhz; + unsigned char minwriteperf_8b_26mhz_4b_52mhz; + unsigned char minreadperf_8b_52mhz; + unsigned char minwriteperf_8b_52mhz; + unsigned char reserved_11; + unsigned int sectorcount; + unsigned char reserved_12[288]; + unsigned char supportedcommandsets; + unsigned char reserved_13[7]; +} mmc_extended_csd_reg_t; + +/* mmc sd responce */ +typedef struct { + unsigned int ocr; +} mmc_resp_r3; + +typedef struct { + unsigned short cardstatus; + unsigned short newpublishedrca; +} mmc_resp_r6; + +extern mmc_card_data mmc_dev; + +unsigned char mmc_lowlevel_init(void); +unsigned char mmc_send_command(unsigned int cmd, unsigned int arg, + unsigned int *response); +unsigned char mmc_setup_clock(unsigned int iclk, unsigned short clkd); +unsigned char mmc_set_opendrain(unsigned char state); +unsigned char mmc_read_data(unsigned int *output_buf); + +#endif /* MMC_H */ diff --git a/x-loader/include/asm/arch-omap3/mmc_host_def.h b/x-loader/include/asm/arch-omap3/mmc_host_def.h new file mode 100644 index 0000000..408d1e2 --- /dev/null +++ b/x-loader/include/asm/arch-omap3/mmc_host_def.h @@ -0,0 +1,164 @@ +/* + * (C) Copyright 2008 + * Texas Instruments, <www.ti.com> + * Syed Mohammed Khasim <khasim@ti.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation's version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef MMC_HOST_DEF_H +#define MMC_HOST_DEF_H + +/* + * OMAP HSMMC register definitions + */ +#define OMAP_HSMMC_SYSCONFIG (*(volatile unsigned int *) 0x4809C010) +#define OMAP_HSMMC_SYSSTATUS (*(volatile unsigned int *) 0x4809C014) +#define OMAP_HSMMC_CON (*(volatile unsigned int *) 0x4809C02C) +#define OMAP_HSMMC_BLK (*(volatile unsigned int *) 0x4809C104) +#define OMAP_HSMMC_ARG (*(volatile unsigned int *) 0x4809C108) +#define OMAP_HSMMC_CMD (*(volatile unsigned int *) 0x4809C10C) +#define OMAP_HSMMC_RSP10 (*(volatile unsigned int *) 0x4809C110) +#define OMAP_HSMMC_RSP32 (*(volatile unsigned int *) 0x4809C114) +#define OMAP_HSMMC_RSP54 (*(volatile unsigned int *) 0x4809C118) +#define OMAP_HSMMC_RSP76 (*(volatile unsigned int *) 0x4809C11C) +#define OMAP_HSMMC_DATA (*(volatile unsigned int *) 0x4809C120) +#define OMAP_HSMMC_PSTATE (*(volatile unsigned int *) 0x4809C124) +#define OMAP_HSMMC_HCTL (*(volatile unsigned int *) 0x4809C128) +#define OMAP_HSMMC_SYSCTL (*(volatile unsigned int *) 0x4809C12C) +#define OMAP_HSMMC_STAT (*(volatile unsigned int *) 0x4809C130) +#define OMAP_HSMMC_IE (*(volatile unsigned int *) 0x4809C134) +#define OMAP_HSMMC_CAPA (*(volatile unsigned int *) 0x4809C140) + +/* T2 Register definitions */ +#define CONTROL_DEV_CONF0 (*(volatile unsigned int *) 0x48002274) +#define CONTROL_PBIAS_LITE (*(volatile unsigned int *) 0x48002520) + +/* + * OMAP HS MMC Bit definitions + */ +#define MMC_SOFTRESET (0x1 << 1) +#define RESETDONE (0x1 << 0) +#define NOOPENDRAIN (0x0 << 0) +#define OPENDRAIN (0x1 << 0) +#define OD (0x1 << 0) +#define INIT_NOINIT (0x0 << 1) +#define INIT_INITSTREAM (0x1 << 1) +#define HR_NOHOSTRESP (0x0 << 2) +#define STR_BLOCK (0x0 << 3) +#define MODE_FUNC (0x0 << 4) +#define DW8_1_4BITMODE (0x0 << 5) +#define MIT_CTO (0x0 << 6) +#define CDP_ACTIVEHIGH (0x0 << 7) +#define WPP_ACTIVEHIGH (0x0 << 8) +#define RESERVED_MASK (0x3 << 9) +#define CTPL_MMC_SD (0x0 << 11) +#define BLEN_512BYTESLEN (0x200 << 0) +#define NBLK_STPCNT (0x0 << 16) +#define DE_DISABLE (0x0 << 0) +#define BCE_DISABLE (0x0 << 1) +#define ACEN_DISABLE (0x0 << 2) +#define DDIR_OFFSET (4) +#define DDIR_MASK (0x1 << 4) +#define DDIR_WRITE (0x0 << 4) +#define DDIR_READ (0x1 << 4) +#define MSBS_SGLEBLK (0x0 << 5) +#define RSP_TYPE_OFFSET (16) +#define RSP_TYPE_MASK (0x3 << 16) +#define RSP_TYPE_NORSP (0x0 << 16) +#define RSP_TYPE_LGHT136 (0x1 << 16) +#define RSP_TYPE_LGHT48 (0x2 << 16) +#define RSP_TYPE_LGHT48B (0x3 << 16) +#define CCCE_NOCHECK (0x0 << 19) +#define CCCE_CHECK (0x1 << 19) +#define CICE_NOCHECK (0x0 << 20) +#define CICE_CHECK (0x1 << 20) +#define DP_OFFSET (21) +#define DP_MASK (0x1 << 21) +#define DP_NO_DATA (0x0 << 21) +#define DP_DATA (0x1 << 21) +#define CMD_TYPE_NORMAL (0x0 << 22) +#define INDEX_OFFSET (24) +#define INDEX_MASK (0x3f << 24) +#define INDEX(i) (i << 24) +#define DATI_MASK (0x1 << 1) +#define DATI_CMDDIS (0x1 << 1) +#define DTW_1_BITMODE (0x0 << 1) +#define DTW_4_BITMODE (0x1 << 1) +#define SDBP_PWROFF (0x0 << 8) +#define SDBP_PWRON (0x1 << 8) +#define SDVS_1V8 (0x5 << 9) +#define SDVS_3V0 (0x6 << 9) +#define ICE_MASK (0x1 << 0) +#define ICE_STOP (0x0 << 0) +#define ICS_MASK (0x1 << 1) +#define ICS_NOTREADY (0x0 << 1) +#define ICE_OSCILLATE (0x1 << 0) +#define CEN_MASK (0x1 << 2) +#define CEN_DISABLE (0x0 << 2) +#define CEN_ENABLE (0x1 << 2) +#define CLKD_OFFSET (6) +#define CLKD_MASK (0x3FF << 6) +#define DTO_MASK (0xF << 16) +#define DTO_15THDTO (0xE << 16) +#define SOFTRESETALL (0x1 << 24) +#define CC_MASK (0x1 << 0) +#define TC_MASK (0x1 << 1) +#define BWR_MASK (0x1 << 4) +#define BRR_MASK (0x1 << 5) +#define ERRI_MASK (0x1 << 15) +#define IE_CC (0x01 << 0) +#define IE_TC (0x01 << 1) +#define IE_BWR (0x01 << 4) +#define IE_BRR (0x01 << 5) +#define IE_CTO (0x01 << 16) +#define IE_CCRC (0x01 << 17) +#define IE_CEB (0x01 << 18) +#define IE_CIE (0x01 << 19) +#define IE_DTO (0x01 << 20) +#define IE_DCRC (0x01 << 21) +#define IE_DEB (0x01 << 22) +#define IE_CERR (0x01 << 28) +#define IE_BADA (0x01 << 29) + +#define VS30_3V0SUP (1 << 25) +#define VS18_1V8SUP (1 << 26) + +/* Driver definitions */ +#define MMCSD_SECTOR_SIZE (512) +#define MMC_CARD 0 +#define SD_CARD 1 +#define BYTE_MODE 0 +#define SECTOR_MODE 1 +#define CLK_INITSEQ 0 +#define CLK_400KHZ 1 +#define CLK_MISC 2 + +typedef struct { + unsigned int card_type; + unsigned int version; + unsigned int mode; + unsigned int size; + unsigned int RCA; +} mmc_card_data; + +#define mmc_reg_out(addr, mask, val)\ + (addr) = (((addr)) & (~(mask))) | ((val) & (mask)); + +#endif /* MMC_HOST_DEF_H */ diff --git a/x-loader/include/asm/arch-omap3/mux.h b/x-loader/include/asm/arch-omap3/mux.h new file mode 100644 index 0000000..ca140a9 --- /dev/null +++ b/x-loader/include/asm/arch-omap3/mux.h @@ -0,0 +1,437 @@ +/* + * (C) Copyright 2006 + * Texas Instruments, <www.ti.com> + * Syed Mohammed Khasim <x0khasim@ti.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _OMAP3430_MUX_H_ +#define _OMAP3430_MUX_H_ + +/* + * OFF_PD - Off mode pull type down + * OFF_PU - Off mode pull type up + * OFF_OUT_PTD - Off Mode Mux low for OUT + * OFF_OUT_PTU - Off Mode Mux high for OUT + * OFF_IN - Off Mode Mux set to IN + * OFF_OUT - Off Mode Mux set to OUT + * OFF_EN - Off Mode Mux Enable + * IEN - Input Enable + * IDIS - Input Disable + * PTD - Pull type Down + * PTU - Pull type Up + * DIS - Pull type selection is inactive + * EN - Pull type selection is active + * M0 - Mode 0 + */ + +#define OFF_PD (1 << 12) +#define OFF_PU (3 << 12) +#define OFF_OUT_PTD (0 << 11) +#define OFF_OUT_PTU (1 << 11) +#define OFF_IN (1 << 10) +#define OFF_OUT (0 << 10) +#define OFF_EN (1 << 9) + +#define IEN (1 << 8) + +#define IDIS (0 << 8) +#define PTU (1 << 4) +#define PTD (0 << 4) +#define EN (1 << 3) +#define DIS (0 << 3) + +#define M0 0 +#define M1 1 +#define M2 2 +#define M3 3 +#define M4 4 +#define M5 5 +#define M6 6 +#define M7 7 + +#ifdef CONFIG_OFF_PADCONF +#define OFF_IN_PD (OFF_PD | OFF_IN | OFF_EN) +#define OFF_IN_PU (OFF_PU | OFF_IN | OFF_EN) +#define OFF_OUT_PD (OFF_OUT_PTD | OFF_OUT | OFF_EN) +#define OFF_OUT_PU (OFF_OUT_PTU | OFF_OUT | OFF_EN) +#else +#define OFF_IN_PD 0 +#define OFF_IN_PU 0 +#define OFF_OUT_PD 0 +#define OFF_OUT_PU 0 +#endif /* #ifdef CONFIG_OFF_PADCONF */ + +/* + * To get the actual address the offset has to added + * with OMAP34XX_CTRL_BASE to get the actual address + */ + +/*SDRC*/ +#define CONTROL_PADCONF_SDRC_D0 0x0030 +#define CONTROL_PADCONF_SDRC_D1 0x0032 +#define CONTROL_PADCONF_SDRC_D2 0x0034 +#define CONTROL_PADCONF_SDRC_D3 0x0036 +#define CONTROL_PADCONF_SDRC_D4 0x0038 +#define CONTROL_PADCONF_SDRC_D5 0x003A +#define CONTROL_PADCONF_SDRC_D6 0x003C +#define CONTROL_PADCONF_SDRC_D7 0x003E +#define CONTROL_PADCONF_SDRC_D8 0x0040 +#define CONTROL_PADCONF_SDRC_D9 0x0042 +#define CONTROL_PADCONF_SDRC_D10 0x0044 +#define CONTROL_PADCONF_SDRC_D11 0x0046 +#define CONTROL_PADCONF_SDRC_D12 0x0048 +#define CONTROL_PADCONF_SDRC_D13 0x004A +#define CONTROL_PADCONF_SDRC_D14 0x004C +#define CONTROL_PADCONF_SDRC_D15 0x004E +#define CONTROL_PADCONF_SDRC_D16 0x0050 +#define CONTROL_PADCONF_SDRC_D17 0x0052 +#define CONTROL_PADCONF_SDRC_D18 0x0054 +#define CONTROL_PADCONF_SDRC_D19 0x0056 +#define CONTROL_PADCONF_SDRC_D20 0x0058 +#define CONTROL_PADCONF_SDRC_D21 0x005A +#define CONTROL_PADCONF_SDRC_D22 0x005C +#define CONTROL_PADCONF_SDRC_D23 0x005E +#define CONTROL_PADCONF_SDRC_D24 0x0060 +#define CONTROL_PADCONF_SDRC_D25 0x0062 +#define CONTROL_PADCONF_SDRC_D26 0x0064 +#define CONTROL_PADCONF_SDRC_D27 0x0066 +#define CONTROL_PADCONF_SDRC_D28 0x0068 +#define CONTROL_PADCONF_SDRC_D29 0x006A +#define CONTROL_PADCONF_SDRC_D30 0x006C +#define CONTROL_PADCONF_SDRC_D31 0x006E +#define CONTROL_PADCONF_SDRC_CLK 0x0070 +#define CONTROL_PADCONF_SDRC_DQS0 0x0072 +#define CONTROL_PADCONF_SDRC_DQS1 0x0074 +#define CONTROL_PADCONF_SDRC_DQS2 0x0076 +#define CONTROL_PADCONF_SDRC_DQS3 0x0078 +/*GPMC*/ +#define CONTROL_PADCONF_GPMC_A1 0x007A +#define CONTROL_PADCONF_GPMC_A2 0x007C +#define CONTROL_PADCONF_GPMC_A3 0x007E +#define CONTROL_PADCONF_GPMC_A4 0x0080 +#define CONTROL_PADCONF_GPMC_A5 0x0082 +#define CONTROL_PADCONF_GPMC_A6 0x0084 +#define CONTROL_PADCONF_GPMC_A7 0x0086 +#define CONTROL_PADCONF_GPMC_A8 0x0088 +#define CONTROL_PADCONF_GPMC_A9 0x008A +#define CONTROL_PADCONF_GPMC_A10 0x008C +#define CONTROL_PADCONF_GPMC_D0 0x008E +#define CONTROL_PADCONF_GPMC_D1 0x0090 +#define CONTROL_PADCONF_GPMC_D2 0x0092 +#define CONTROL_PADCONF_GPMC_D3 0x0094 +#define CONTROL_PADCONF_GPMC_D4 0x0096 +#define CONTROL_PADCONF_GPMC_D5 0x0098 +#define CONTROL_PADCONF_GPMC_D6 0x009A +#define CONTROL_PADCONF_GPMC_D7 0x009C +#define CONTROL_PADCONF_GPMC_D8 0x009E +#define CONTROL_PADCONF_GPMC_D9 0x00A0 +#define CONTROL_PADCONF_GPMC_D10 0x00A2 +#define CONTROL_PADCONF_GPMC_D11 0x00A4 +#define CONTROL_PADCONF_GPMC_D12 0x00A6 +#define CONTROL_PADCONF_GPMC_D13 0x00A8 +#define CONTROL_PADCONF_GPMC_D14 0x00AA +#define CONTROL_PADCONF_GPMC_D15 0x00AC +#define CONTROL_PADCONF_GPMC_nCS0 0x00AE +#define CONTROL_PADCONF_GPMC_nCS1 0x00B0 +#define CONTROL_PADCONF_GPMC_nCS2 0x00B2 +#define CONTROL_PADCONF_GPMC_nCS3 0x00B4 +#define CONTROL_PADCONF_GPMC_nCS4 0x00B6 +#define CONTROL_PADCONF_GPMC_nCS5 0x00B8 +#define CONTROL_PADCONF_GPMC_nCS6 0x00BA +#define CONTROL_PADCONF_GPMC_nCS7 0x00BC +#define CONTROL_PADCONF_GPMC_CLK 0x00BE +#define CONTROL_PADCONF_GPMC_nADV_ALE 0x00C0 +#define CONTROL_PADCONF_GPMC_nOE 0x00C2 +#define CONTROL_PADCONF_GPMC_nWE 0x00C4 +#define CONTROL_PADCONF_GPMC_nBE0_CLE 0x00C6 +#define CONTROL_PADCONF_GPMC_nBE1 0x00C8 +#define CONTROL_PADCONF_GPMC_nWP 0x00CA +#define CONTROL_PADCONF_GPMC_WAIT0 0x00CC +#define CONTROL_PADCONF_GPMC_WAIT1 0x00CE +#define CONTROL_PADCONF_GPMC_WAIT2 0x00D0 +#define CONTROL_PADCONF_GPMC_WAIT3 0x00D2 +/*DSS*/ +#define CONTROL_PADCONF_DSS_PCLK 0x00D4 +#define CONTROL_PADCONF_DSS_HSYNC 0x00D6 +#define CONTROL_PADCONF_DSS_VSYNC 0x00D8 +#define CONTROL_PADCONF_DSS_ACBIAS 0x00DA +#define CONTROL_PADCONF_DSS_DATA0 0x00DC +#define CONTROL_PADCONF_DSS_DATA1 0x00DE +#define CONTROL_PADCONF_DSS_DATA2 0x00E0 +#define CONTROL_PADCONF_DSS_DATA3 0x00E2 +#define CONTROL_PADCONF_DSS_DATA4 0x00E4 +#define CONTROL_PADCONF_DSS_DATA5 0x00E6 +#define CONTROL_PADCONF_DSS_DATA6 0x00E8 +#define CONTROL_PADCONF_DSS_DATA7 0x00EA +#define CONTROL_PADCONF_DSS_DATA8 0x00EC +#define CONTROL_PADCONF_DSS_DATA9 0x00EE +#define CONTROL_PADCONF_DSS_DATA10 0x00F0 +#define CONTROL_PADCONF_DSS_DATA11 0x00F2 +#define CONTROL_PADCONF_DSS_DATA12 0x00F4 +#define CONTROL_PADCONF_DSS_DATA13 0x00F6 +#define CONTROL_PADCONF_DSS_DATA14 0x00F8 +#define CONTROL_PADCONF_DSS_DATA15 0x00FA +#define CONTROL_PADCONF_DSS_DATA16 0x00FC +#define CONTROL_PADCONF_DSS_DATA17 0x00FE +#define CONTROL_PADCONF_DSS_DATA18 0x0100 +#define CONTROL_PADCONF_DSS_DATA19 0x0102 +#define CONTROL_PADCONF_DSS_DATA20 0x0104 +#define CONTROL_PADCONF_DSS_DATA21 0x0106 +#define CONTROL_PADCONF_DSS_DATA22 0x0108 +#define CONTROL_PADCONF_DSS_DATA23 0x010A +/*CAMERA*/ +#define CONTROL_PADCONF_CAM_HS 0x010C +#define CONTROL_PADCONF_CAM_VS 0x010E +#define CONTROL_PADCONF_CAM_XCLKA 0x0110 +#define CONTROL_PADCONF_CAM_PCLK 0x0112 +#define CONTROL_PADCONF_CAM_FLD 0x0114 +#define CONTROL_PADCONF_CAM_D0 0x0116 +#define CONTROL_PADCONF_CAM_D1 0x0118 +#define CONTROL_PADCONF_CAM_D2 0x011A +#define CONTROL_PADCONF_CAM_D3 0x011C +#define CONTROL_PADCONF_CAM_D4 0x011E +#define CONTROL_PADCONF_CAM_D5 0x0120 +#define CONTROL_PADCONF_CAM_D6 0x0122 +#define CONTROL_PADCONF_CAM_D7 0x0124 +#define CONTROL_PADCONF_CAM_D8 0x0126 +#define CONTROL_PADCONF_CAM_D9 0x0128 +#define CONTROL_PADCONF_CAM_D10 0x012A +#define CONTROL_PADCONF_CAM_D11 0x012C +#define CONTROL_PADCONF_CAM_XCLKB 0x012E +#define CONTROL_PADCONF_CAM_WEN 0x0130 +#define CONTROL_PADCONF_CAM_STROBE 0x0132 +#define CONTROL_PADCONF_CSI2_DX0 0x0134 +#define CONTROL_PADCONF_CSI2_DY0 0x0136 +#define CONTROL_PADCONF_CSI2_DX1 0x0138 +#define CONTROL_PADCONF_CSI2_DY1 0x013A +/*Audio Interface */ +#define CONTROL_PADCONF_McBSP2_FSX 0x013C +#define CONTROL_PADCONF_McBSP2_CLKX 0x013E +#define CONTROL_PADCONF_McBSP2_DR 0x0140 +#define CONTROL_PADCONF_McBSP2_DX 0x0142 +#define CONTROL_PADCONF_ +#define CONTROL_PADCONF_MMC1_CLK 0x0144 +#define CONTROL_PADCONF_MMC1_CMD 0x0146 +#define CONTROL_PADCONF_MMC1_DAT0 0x0148 +#define CONTROL_PADCONF_MMC1_DAT1 0x014A +#define CONTROL_PADCONF_MMC1_DAT2 0x014C +#define CONTROL_PADCONF_MMC1_DAT3 0x014E +#define CONTROL_PADCONF_MMC1_DAT4 0x0150 +#define CONTROL_PADCONF_MMC1_DAT5 0x0152 +#define CONTROL_PADCONF_MMC1_DAT6 0x0154 +#define CONTROL_PADCONF_MMC1_DAT7 0x0156 +/*Wireless LAN */ +#define CONTROL_PADCONF_MMC2_CLK 0x0158 +#define CONTROL_PADCONF_MMC2_CMD 0x015A +#define CONTROL_PADCONF_MMC2_DAT0 0x015C +#define CONTROL_PADCONF_MMC2_DAT1 0x015E +#define CONTROL_PADCONF_MMC2_DAT2 0x0160 +#define CONTROL_PADCONF_MMC2_DAT3 0x0162 +#define CONTROL_PADCONF_MMC2_DAT4 0x0164 +#define CONTROL_PADCONF_MMC2_DAT5 0x0166 +#define CONTROL_PADCONF_MMC2_DAT6 0x0168 +#define CONTROL_PADCONF_MMC2_DAT7 0x016A +/*Bluetooth*/ +#define CONTROL_PADCONF_McBSP3_DX 0x016C +#define CONTROL_PADCONF_McBSP3_DR 0x016E +#define CONTROL_PADCONF_McBSP3_CLKX 0x0170 +#define CONTROL_PADCONF_McBSP3_FSX 0x0172 +#define CONTROL_PADCONF_UART2_CTS 0x0174 +#define CONTROL_PADCONF_UART2_RTS 0x0176 +#define CONTROL_PADCONF_UART2_TX 0x0178 +#define CONTROL_PADCONF_UART2_RX 0x017A +/*Modem Interface */ +#define CONTROL_PADCONF_UART1_TX 0x017C +#define CONTROL_PADCONF_UART1_RTS 0x017E +#define CONTROL_PADCONF_UART1_CTS 0x0180 +#define CONTROL_PADCONF_UART1_RX 0x0182 +#define CONTROL_PADCONF_McBSP4_CLKX 0x0184 +#define CONTROL_PADCONF_McBSP4_DR 0x0186 +#define CONTROL_PADCONF_McBSP4_DX 0x0188 +#define CONTROL_PADCONF_McBSP4_FSX 0x018A +#define CONTROL_PADCONF_McBSP1_CLKR 0x018C +#define CONTROL_PADCONF_McBSP1_FSR 0x018E +#define CONTROL_PADCONF_McBSP1_DX 0x0190 +#define CONTROL_PADCONF_McBSP1_DR 0x0192 +#define CONTROL_PADCONF_McBSP_CLKS 0x0194 +#define CONTROL_PADCONF_McBSP1_FSX 0x0196 +#define CONTROL_PADCONF_McBSP1_CLKX 0x0198 +/*Serial Interface*/ +#define CONTROL_PADCONF_UART3_CTS_RCTX 0x019A +#define CONTROL_PADCONF_UART3_RTS_SD 0x019C +#define CONTROL_PADCONF_UART3_RX_IRRX 0x019E +#define CONTROL_PADCONF_UART3_TX_IRTX 0x01A0 +#define CONTROL_PADCONF_HSUSB0_CLK 0x01A2 +#define CONTROL_PADCONF_HSUSB0_STP 0x01A4 +#define CONTROL_PADCONF_HSUSB0_DIR 0x01A6 +#define CONTROL_PADCONF_HSUSB0_NXT 0x01A8 +#define CONTROL_PADCONF_HSUSB0_DATA0 0x01AA +#define CONTROL_PADCONF_HSUSB0_DATA1 0x01AC +#define CONTROL_PADCONF_HSUSB0_DATA2 0x01AE +#define CONTROL_PADCONF_HSUSB0_DATA3 0x01B0 +#define CONTROL_PADCONF_HSUSB0_DATA4 0x01B2 +#define CONTROL_PADCONF_HSUSB0_DATA5 0x01B4 +#define CONTROL_PADCONF_HSUSB0_DATA6 0x01B6 +#define CONTROL_PADCONF_HSUSB0_DATA7 0x01B8 +#define CONTROL_PADCONF_I2C1_SCL 0x01BA +#define CONTROL_PADCONF_I2C1_SDA 0x01BC +#define CONTROL_PADCONF_I2C2_SCL 0x01BE +#define CONTROL_PADCONF_I2C2_SDA 0x01C0 +#define CONTROL_PADCONF_I2C3_SCL 0x01C2 +#define CONTROL_PADCONF_I2C3_SDA 0x01C4 +#define CONTROL_PADCONF_I2C4_SCL 0x0A00 +#define CONTROL_PADCONF_I2C4_SDA 0x0A02 +#define CONTROL_PADCONF_HDQ_SIO 0x01C6 +#define CONTROL_PADCONF_McSPI1_CLK 0x01C8 +#define CONTROL_PADCONF_McSPI1_SIMO 0x01CA +#define CONTROL_PADCONF_McSPI1_SOMI 0x01CC +#define CONTROL_PADCONF_McSPI1_CS0 0x01CE +#define CONTROL_PADCONF_McSPI1_CS1 0x01D0 +#define CONTROL_PADCONF_McSPI1_CS2 0x01D2 +#define CONTROL_PADCONF_McSPI1_CS3 0x01D4 +#define CONTROL_PADCONF_McSPI2_CLK 0x01D6 +#define CONTROL_PADCONF_McSPI2_SIMO 0x01D8 +#define CONTROL_PADCONF_McSPI2_SOMI 0x01DA +#define CONTROL_PADCONF_McSPI2_CS0 0x01DC +#define CONTROL_PADCONF_McSPI2_CS1 0x01DE +/*Control and debug */ +#define CONTROL_PADCONF_SYS_32K 0x0A04 +#define CONTROL_PADCONF_SYS_CLKREQ 0x0A06 +#define CONTROL_PADCONF_SYS_nIRQ 0x01E0 +#define CONTROL_PADCONF_SYS_BOOT0 0x0A0A +#define CONTROL_PADCONF_SYS_BOOT1 0x0A0C +#define CONTROL_PADCONF_SYS_BOOT2 0x0A0E +#define CONTROL_PADCONF_SYS_BOOT3 0x0A10 +#define CONTROL_PADCONF_SYS_BOOT4 0x0A12 +#define CONTROL_PADCONF_SYS_BOOT5 0x0A14 +#define CONTROL_PADCONF_SYS_BOOT6 0x0A16 +#define CONTROL_PADCONF_SYS_OFF_MODE 0x0A18 +#define CONTROL_PADCONF_SYS_CLKOUT1 0x0A1A +#define CONTROL_PADCONF_SYS_CLKOUT2 0x01E2 +#define CONTROL_PADCONF_JTAG_nTRST 0x0A1C +#define CONTROL_PADCONF_JTAG_TCK 0x0A1E +#define CONTROL_PADCONF_JTAG_TMS 0x0A20 +#define CONTROL_PADCONF_JTAG_TDI 0x0A22 +#define CONTROL_PADCONF_JTAG_EMU0 0x0A24 +#define CONTROL_PADCONF_JTAG_EMU1 0x0A26 +#define CONTROL_PADCONF_ETK_CLK 0x0A28 +#define CONTROL_PADCONF_ETK_CTL 0x0A2A +#define CONTROL_PADCONF_ETK_D0 0x0A2C +#define CONTROL_PADCONF_ETK_D1 0x0A2E +#define CONTROL_PADCONF_ETK_D2 0x0A30 +#define CONTROL_PADCONF_ETK_D3 0x0A32 +#define CONTROL_PADCONF_ETK_D4 0x0A34 +#define CONTROL_PADCONF_ETK_D5 0x0A36 +#define CONTROL_PADCONF_ETK_D6 0x0A38 +#define CONTROL_PADCONF_ETK_D7 0x0A3A +#define CONTROL_PADCONF_ETK_D8 0x0A3C +#define CONTROL_PADCONF_ETK_D9 0x0A3E +#define CONTROL_PADCONF_ETK_D10 0x0A40 +#define CONTROL_PADCONF_ETK_D11 0x0A42 +#define CONTROL_PADCONF_ETK_D12 0x0A44 +#define CONTROL_PADCONF_ETK_D13 0x0A46 +#define CONTROL_PADCONF_ETK_D14 0x0A48 +#define CONTROL_PADCONF_ETK_D15 0x0A4A + +#define CONTROL_PADCONF_ETK_CLK_ES2 0x05D8 +#define CONTROL_PADCONF_ETK_CTL_ES2 0x05DA +#define CONTROL_PADCONF_ETK_D0_ES2 0x05DC +#define CONTROL_PADCONF_ETK_D1_ES2 0x05DE +#define CONTROL_PADCONF_ETK_D2_ES2 0x05E0 +#define CONTROL_PADCONF_ETK_D3_ES2 0x05E2 +#define CONTROL_PADCONF_ETK_D4_ES2 0x05E4 +#define CONTROL_PADCONF_ETK_D5_ES2 0x05E6 +#define CONTROL_PADCONF_ETK_D6_ES2 0x05E8 +#define CONTROL_PADCONF_ETK_D7_ES2 0x05EA +#define CONTROL_PADCONF_ETK_D8_ES2 0x05EC +#define CONTROL_PADCONF_ETK_D9_ES2 0x05EE +#define CONTROL_PADCONF_ETK_D10_ES2 0x05F0 +#define CONTROL_PADCONF_ETK_D11_ES2 0x05F2 +#define CONTROL_PADCONF_ETK_D12_ES2 0x05F4 +#define CONTROL_PADCONF_ETK_D13_ES2 0x05F6 +#define CONTROL_PADCONF_ETK_D14_ES2 0x05F8 +#define CONTROL_PADCONF_ETK_D15_ES2 0x05FA + +/*Die to Die */ +#define CONTROL_PADCONF_d2d_mcad0 0x01E4 +#define CONTROL_PADCONF_d2d_mcad1 0x01E6 +#define CONTROL_PADCONF_d2d_mcad2 0x01E8 +#define CONTROL_PADCONF_d2d_mcad3 0x01EA +#define CONTROL_PADCONF_d2d_mcad4 0x01EC +#define CONTROL_PADCONF_d2d_mcad5 0x01EE +#define CONTROL_PADCONF_d2d_mcad6 0x01F0 +#define CONTROL_PADCONF_d2d_mcad7 0x01F2 +#define CONTROL_PADCONF_d2d_mcad8 0x01F4 +#define CONTROL_PADCONF_d2d_mcad9 0x01F6 +#define CONTROL_PADCONF_d2d_mcad10 0x01F8 +#define CONTROL_PADCONF_d2d_mcad11 0x01FA +#define CONTROL_PADCONF_d2d_mcad12 0x01FC +#define CONTROL_PADCONF_d2d_mcad13 0x01FE +#define CONTROL_PADCONF_d2d_mcad14 0x0200 +#define CONTROL_PADCONF_d2d_mcad15 0x0202 +#define CONTROL_PADCONF_d2d_mcad16 0x0204 +#define CONTROL_PADCONF_d2d_mcad17 0x0206 +#define CONTROL_PADCONF_d2d_mcad18 0x0208 +#define CONTROL_PADCONF_d2d_mcad19 0x020A +#define CONTROL_PADCONF_d2d_mcad20 0x020C +#define CONTROL_PADCONF_d2d_mcad21 0x020E +#define CONTROL_PADCONF_d2d_mcad22 0x0210 +#define CONTROL_PADCONF_d2d_mcad23 0x0212 +#define CONTROL_PADCONF_d2d_mcad24 0x0214 +#define CONTROL_PADCONF_d2d_mcad25 0x0216 +#define CONTROL_PADCONF_d2d_mcad26 0x0218 +#define CONTROL_PADCONF_d2d_mcad27 0x021A +#define CONTROL_PADCONF_d2d_mcad28 0x021C +#define CONTROL_PADCONF_d2d_mcad29 0x021E +#define CONTROL_PADCONF_d2d_mcad30 0x0220 +#define CONTROL_PADCONF_d2d_mcad31 0x0222 +#define CONTROL_PADCONF_d2d_mcad32 0x0224 +#define CONTROL_PADCONF_d2d_mcad33 0x0226 +#define CONTROL_PADCONF_d2d_mcad34 0x0228 +#define CONTROL_PADCONF_d2d_mcad35 0x022A +#define CONTROL_PADCONF_d2d_mcad36 0x022C +#define CONTROL_PADCONF_d2d_clk26mi 0x022E +#define CONTROL_PADCONF_d2d_nrespwron 0x0230 +#define CONTROL_PADCONF_d2d_nreswarm 0x0232 +#define CONTROL_PADCONF_d2d_arm9nirq 0x0234 +#define CONTROL_PADCONF_d2d_uma2p6fiq 0x0236 +#define CONTROL_PADCONF_d2d_spint 0x0238 +#define CONTROL_PADCONF_d2d_frint 0x023A +#define CONTROL_PADCONF_d2d_dmareq0 0x023C +#define CONTROL_PADCONF_d2d_dmareq1 0x023E +#define CONTROL_PADCONF_d2d_dmareq2 0x0240 +#define CONTROL_PADCONF_d2d_dmareq3 0x0242 +#define CONTROL_PADCONF_d2d_n3gtrst 0x0244 +#define CONTROL_PADCONF_d2d_n3gtdi 0x0246 +#define CONTROL_PADCONF_d2d_n3gtdo 0x0248 +#define CONTROL_PADCONF_d2d_n3gtms 0x024A +#define CONTROL_PADCONF_d2d_n3gtck 0x024C +#define CONTROL_PADCONF_d2d_n3grtck 0x024E +#define CONTROL_PADCONF_d2d_mstdby 0x0250 +#define CONTROL_PADCONF_d2d_swakeup 0x0A4C +#define CONTROL_PADCONF_d2d_idlereq 0x0252 +#define CONTROL_PADCONF_d2d_idleack 0x0254 +#define CONTROL_PADCONF_d2d_mwrite 0x0256 +#define CONTROL_PADCONF_d2d_swrite 0x0258 +#define CONTROL_PADCONF_d2d_mread 0x025A +#define CONTROL_PADCONF_d2d_sread 0x025C +#define CONTROL_PADCONF_d2d_mbusflag 0x025E +#define CONTROL_PADCONF_d2d_sbusflag 0x0260 +#define CONTROL_PADCONF_sdrc_cke0 0x0262 +#define CONTROL_PADCONF_sdrc_cke1 0x0264 + +#endif diff --git a/x-loader/include/asm/arch-omap3/omap3430.h b/x-loader/include/asm/arch-omap3/omap3430.h new file mode 100644 index 0000000..3c583ae --- /dev/null +++ b/x-loader/include/asm/arch-omap3/omap3430.h @@ -0,0 +1,141 @@ +/* + * (C) Copyright 2006 + * Texas Instruments, <www.ti.com> + * Richard Woodruff <r-woodruff2@ti.com> + * Syed Mohammed Khasim <x0khasim@ti.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _OMAP3430_SYS_H_ +#define _OMAP3430_SYS_H_ + +#include <asm/arch/sizes.h> + +/* + * 3430 specific Section + */ + +/* Stuff on L3 Interconnect */ +#define SMX_APE_BASE 0x68000000 + +/* L3 Firewall */ +#define A_REQINFOPERM0 (SMX_APE_BASE + 0x05048) +#define A_READPERM0 (SMX_APE_BASE + 0x05050) +#define A_WRITEPERM0 (SMX_APE_BASE + 0x05058) + +/* GPMC */ +#define OMAP34XX_GPMC_BASE (0x6E000000) + +/* SMS */ +#define OMAP34XX_SMS_BASE 0x6C000000 + +/* SDRC */ +#define OMAP34XX_SDRC_BASE 0x6D000000 + +/* + * L4 Peripherals - L4 Wakeup and L4 Core now + */ +#define OMAP34XX_CORE_L4_IO_BASE 0x48000000 + +#define OMAP34XX_WAKEUP_L4_IO_BASE 0x48300000 + +#define OMAP34XX_L4_PER 0x49000000 + +#define OMAP34XX_L4_IO_BASE OMAP34XX_CORE_L4_IO_BASE + +/* CONTROL */ +#define OMAP34XX_CTRL_BASE (OMAP34XX_L4_IO_BASE+0x2000) + +/* TAP information dont know for 3430*/ +#define OMAP34XX_TAP_BASE (0x49000000) /*giving some junk for virtio */ + +/* UART */ +#define OMAP34XX_UART1 (OMAP34XX_L4_IO_BASE+0x6a000) +#define OMAP34XX_UART2 (OMAP34XX_L4_IO_BASE+0x6c000) +#define OMAP34XX_UART3 (OMAP34XX_L4_PER+0x20000) + +/* General Purpose Timers */ +#define OMAP34XX_GPT1 0x48318000 +#define OMAP34XX_GPT2 0x49032000 +#define OMAP34XX_GPT3 0x49034000 +#define OMAP34XX_GPT4 0x49036000 +#define OMAP34XX_GPT5 0x49038000 +#define OMAP34XX_GPT6 0x4903A000 +#define OMAP34XX_GPT7 0x4903C000 +#define OMAP34XX_GPT8 0x4903E000 +#define OMAP34XX_GPT9 0x49040000 +#define OMAP34XX_GPT10 0x48086000 +#define OMAP34XX_GPT11 0x48088000 +#define OMAP34XX_GPT12 0x48304000 + +/* WatchDog Timers (1 secure, 3 GP) */ +#define WD1_BASE (0x4830C000) +#define WD2_BASE (0x48314000) +#define WD3_BASE (0x49030000) + +/* 32KTIMER */ +#define SYNC_32KTIMER_BASE (0x48320000) +#define S32K_CR (SYNC_32KTIMER_BASE+0x10) + +/* omap3 GPIO registers */ +#define OMAP34XX_GPIO1_BASE 0x48310000 +#define OMAP34XX_GPIO2_BASE 0x49050000 +#define OMAP34XX_GPIO3_BASE 0x49052000 +#define OMAP34XX_GPIO4_BASE 0x49054000 +#define OMAP34XX_GPIO5_BASE 0x49056000 +#define OMAP34XX_GPIO6_BASE 0x49058000 + +/* + * SDP3430 specific Section + */ + +/* + * The 343x's chip selects are programmable. The mask ROM + * does configure CS0 to 0x08000000 before dispatch. So, if + * you want your code to live below that address, you have to + * be prepared to jump though hoops, to reset the base address. + * Same as in SDP3430 + */ +#ifdef CONFIG_OMAP34XX +/* base address for indirect vectors (internal boot mode) */ +#define SRAM_OFFSET0 0x40000000 +#define SRAM_OFFSET1 0x00200000 +#define SRAM_OFFSET2 0x0000F800 +#define SRAM_VECT_CODE (SRAM_OFFSET0|SRAM_OFFSET1|SRAM_OFFSET2) + +#define LOW_LEVEL_SRAM_STACK 0x4020FFFC +#endif + +#if defined(CONFIG_3430SDP) || defined(CONFIG_OMAP3EVM) +/* FPGA on Debug board.*/ +#define ETH_CONTROL_REG (DEBUG_BASE+0x30b) +#define LAN_RESET_REGISTER (DEBUG_BASE+0x1c) + +#define DIP_SWITCH_INPUT_REG2 (DEBUG_BASE+0x60) +#define LED_REGISTER (DEBUG_BASE+0x40) +#define FPGA_REV_REGISTER (DEBUG_BASE+0x10) +#define EEPROM_MAIN_BRD (DEBUG_BASE+0x10000+0x1800) +#define EEPROM_CONN_BRD (DEBUG_BASE+0x10000+0x1900) +#define EEPROM_UI_BRD (DEBUG_BASE+0x10000+0x1A00) +#define EEPROM_MCAM_BRD (DEBUG_BASE+0x10000+0x1B00) +#define ENHANCED_UI_EE_NAME "750-2075" +#endif + +#endif /* _OMAP3430_SYS_H_ */ diff --git a/x-loader/include/asm/arch-omap3/rev.h b/x-loader/include/asm/arch-omap3/rev.h new file mode 100755 index 0000000..c0e95d4 --- /dev/null +++ b/x-loader/include/asm/arch-omap3/rev.h @@ -0,0 +1,43 @@ +/* + * (C) Copyright 2006 + * Texas Instruments, <www.ti.com> + * + * Richard Woodruff <r-woodruff2@ti.com> + * Syed Mohammed Khasim <x0khasim@ti.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _OMAP34XX_REV_H_ +#define _OMAP34XX_REV_H_ + +#define CDB_DDR_COMBO /* combo part on cpu daughter card */ +#define CDB_DDR_IPDB /* 2x16 parts on daughter card */ + +#define DDR_100 100 /* type found on most mem d-boards */ +#define DDR_111 111 /* some combo parts */ +#define DDR_133 133 /* most combo, some mem d-boards */ +#define DDR_165 165 /* future parts */ + +#define CPU_3430 0x3430 + +#define CPU_3430_ES1 1 +#define CPU_3430_ES2 1 + +#endif diff --git a/x-loader/include/asm/arch-omap3/sizes.h b/x-loader/include/asm/arch-omap3/sizes.h new file mode 100644 index 0000000..aaba18f --- /dev/null +++ b/x-loader/include/asm/arch-omap3/sizes.h @@ -0,0 +1,49 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +/* Size defintions + * Copyright (C) ARM Limited 1998. All rights reserved. + */ + +#ifndef __sizes_h +#define __sizes_h 1 + +/* handy sizes */ +#define SZ_1K 0x00000400 +#define SZ_4K 0x00001000 +#define SZ_8K 0x00002000 +#define SZ_16K 0x00004000 +#define SZ_32K 0x00008000 +#define SZ_64K 0x00010000 +#define SZ_128K 0x00020000 +#define SZ_256K 0x00040000 +#define SZ_512K 0x00080000 + +#define SZ_1M 0x00100000 +#define SZ_2M 0x00200000 +#define SZ_4M 0x00400000 +#define SZ_8M 0x00800000 +#define SZ_16M 0x01000000 +#define SZ_31M 0x01F00000 +#define SZ_32M 0x02000000 +#define SZ_64M 0x04000000 +#define SZ_128M 0x08000000 +#define SZ_256M 0x10000000 +#define SZ_512M 0x20000000 + +#define SZ_1G 0x40000000 +#define SZ_2G 0x80000000 + +#endif /* __sizes_h */ diff --git a/x-loader/include/asm/arch-omap3/sys_info.h b/x-loader/include/asm/arch-omap3/sys_info.h new file mode 100644 index 0000000..18e2b49 --- /dev/null +++ b/x-loader/include/asm/arch-omap3/sys_info.h @@ -0,0 +1,77 @@ +/* + * (C) Copyright 2006 + * Texas Instruments, <www.ti.com> + * Richard Woodruff <r-woodruff2@ti.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _OMAP34XX_SYS_INFO_H_ +#define _OMAP34XX_SYS_INFO_H_ + +#define XDR_POP 5 /* package on package part */ +#define SDR_DISCRETE 4 /* 128M memory SDR module*/ +#define DDR_STACKED 3 /* stacked part on 2422 */ +#define DDR_COMBO 2 /* combo part on cpu daughter card (menalaeus) */ +#define DDR_DISCRETE 1 /* 2x16 parts on daughter card */ + +#define DDR_100 100 /* type found on most mem d-boards */ +#define DDR_111 111 /* some combo parts */ +#define DDR_133 133 /* most combo, some mem d-boards */ +#define DDR_165 165 /* future parts */ + +#define CPU_3430 0x3430 + +/* 343x real hardware: + * ES1 = rev 0 + */ + +/* 343x code defines: + * ES1 = 0+1 = 1 + * ES1 = 1+1 = 1 + */ +#define CPU_3430_ES1 1 +#define CPU_3430_ES2 2 + +/* Currently Virtio models this one */ +#define CPU_3430_CHIPID 0x0B68A000 + +#define GPMC_MUXED 1 +#define GPMC_NONMUXED 0 + +#define TYPE_NAND 0x800 /* bit pos for nand in gpmc reg */ +#define TYPE_NOR 0x000 +#define TYPE_ONENAND 0x800 + +#define WIDTH_8BIT 0x0000 +#define WIDTH_16BIT 0x1000 /* bit pos for 16 bit in gpmc */ + +#define I2C_MENELAUS 0x72 /* i2c id for companion chip */ +#define I2C_TRITON2 0x4B /* addres of power group */ + +#define BOOT_FAST_XIP 0x1f + +/* SDP definitions according to FPGA Rev. Is this OK?? */ +#define SDP_3430_V1 0x1 +#define SDP_3430_V2 0x2 + +#define BOARD_3430_LABRADOR 0x80 +#define BOARD_3430_LABRADOR_V1 0x1 + +#endif diff --git a/x-loader/include/asm/arch-omap3/sys_proto.h b/x-loader/include/asm/arch-omap3/sys_proto.h new file mode 100644 index 0000000..7ac53a2 --- /dev/null +++ b/x-loader/include/asm/arch-omap3/sys_proto.h @@ -0,0 +1,59 @@ +/* + * (C) Copyright 2004-2006 + * Texas Instruments, <www.ti.com> + * Richard Woodruff <r-woodruff2@ti.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _OMAP34XX_SYS_PROTO_H_ +#define _OMAP34XX_SYS_PROTO_H_ + +void prcm_init(void); +void per_clocks_enable(void); + +void memif_init(void); +void sdrc_init(void); +void do_sdrc_init(u32,u32); +void gpmc_init(void); + +void ether_init(void); +void watchdog_init(void); +void set_muxconf_regs(void); + +u32 get_cpu_type(void); +u32 get_cpu_rev(void); +u32 cpu_is_3410(void); +u32 get_mem_type(void); +u32 get_sysboot_value(void); +u32 get_gpmc0_base(void); +u32 is_gpmc_muxed(void); +u32 get_gpmc0_type(void); +u32 get_gpmc0_width(void); +u32 get_board_type(void); +void display_board_info(u32); +void update_mux(u32,u32); +u32 get_sdr_cs_size(u32 offset); +u32 running_in_sdram(void); +u32 running_in_sram(void); +u32 running_in_flash(void); +u32 running_from_internal_boot(void); +u32 get_device_type(void); + +void sr32(u32 addr, u32 start_bit, u32 num_bits, u32 value); +u32 wait_on_value(u32 read_bit_mask, u32 match_value, u32 read_addr, u32 bound); +void sdelay(unsigned long loops); + +#endif |