diff options
Diffstat (limited to 'x-loader/include/asm')
49 files changed, 0 insertions, 7596 deletions
diff --git a/x-loader/include/asm/arch-arm1136/bits.h b/x-loader/include/asm/arch-arm1136/bits.h deleted file mode 100644 index dc3273e..0000000 --- a/x-loader/include/asm/arch-arm1136/bits.h +++ /dev/null @@ -1,49 +0,0 @@ -/* bits.h - * Copyright (c) 2004 Texas Instruments - * - * This package is free software; you can redistribute it and/or - * modify it under the terms of the license found in the file - * named COPYING that should have accompanied this file. - * - * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED - * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. - */ -#ifndef __bits_h -#define __bits_h 1 - -#define BIT0 (1<<0) -#define BIT1 (1<<1) -#define BIT2 (1<<2) -#define BIT3 (1<<3) -#define BIT4 (1<<4) -#define BIT5 (1<<5) -#define BIT6 (1<<6) -#define BIT7 (1<<7) -#define BIT8 (1<<8) -#define BIT9 (1<<9) -#define BIT10 (1<<10) -#define BIT11 (1<<11) -#define BIT12 (1<<12) -#define BIT13 (1<<13) -#define BIT14 (1<<14) -#define BIT15 (1<<15) -#define BIT16 (1<<16) -#define BIT17 (1<<17) -#define BIT18 (1<<18) -#define BIT19 (1<<19) -#define BIT20 (1<<20) -#define BIT21 (1<<21) -#define BIT22 (1<<22) -#define BIT23 (1<<23) -#define BIT24 (1<<24) -#define BIT25 (1<<25) -#define BIT26 (1<<26) -#define BIT27 (1<<27) -#define BIT28 (1<<28) -#define BIT29 (1<<29) -#define BIT30 (1<<30) -#define BIT31 (1<<31) - -#endif - diff --git a/x-loader/include/asm/arch-arm1136/clocks.h b/x-loader/include/asm/arch-arm1136/clocks.h deleted file mode 100644 index 8e00d2e..0000000 --- a/x-loader/include/asm/arch-arm1136/clocks.h +++ /dev/null @@ -1,51 +0,0 @@ -/* - * (C) Copyright 2004 - * Texas Instruments, <www.ti.com> - * Richard Woodruff <r-woodruff2@ti.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#ifndef _OMAP24XX_CLOCKS_H_ -#define _OMAP24XX_CLOCKS_H_ - -#define COMMIT_DIVIDERS 0x1 -#define MODE_BYPASS_FAST 0x2 -#define APLL_LOCK 0xc -#define DPLL_LOCK 0x3 /* DPLL lock */ -#define LDELAY 12000000 - -#if defined(CONFIG_OMAP242X) -#include <asm/arch/clocks242x.h> -#elif defined(CONFIG_OMAP243X) -#include <asm/arch/clocks243x.h> -#endif - -#define S12M 12000000 -#define S13M 13000000 -#define S19_2M 19200000 -#define S24M 24000000 -#define S26M 26000000 -#define S38_4M 38400000 - -#endif - - - - - - - - diff --git a/x-loader/include/asm/arch-arm1136/clocks242x.h b/x-loader/include/asm/arch-arm1136/clocks242x.h deleted file mode 100644 index 0ae1c4e..0000000 --- a/x-loader/include/asm/arch-arm1136/clocks242x.h +++ /dev/null @@ -1,147 +0,0 @@ -/* - * (C) Copyright 2004 - * Texas Instruments, <www.ti.com> - * Richard Woodruff <r-woodruff2@ti.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#ifndef _OMAP242X_CLOCKS_H_ -#define _OMAP242X_CLOCKS_H_ - -/****************************************************************************; -; PRCM Scheme I -; -; Enable clocks and DPLL for: -; DPLL=330, DPLLout=660 M=1,N=55 CM_CLKSEL1_PLL[21:8] 12/2*55 -; Core=660 (core domain) DPLLx2 CM_CLKSEL2_PLL[1:0] -; MPUF=330 (mpu domain) 2 CM_CLKSEL_MPU[4:0] -; DSPF=220 (dsp domain) 3 CM_CLKSEL_DSP[4:0] -; DSPI=110 6 CM_CLKSEL_DSP[6:5] -; DSP_S activated CM_CLKSEL_DSP[7] -; IVAF=165 (dsp domain) 4 CM_CLKSEL_DSP[12:8] -; IVAF=82.5 auto -; IVAI auto -; IVA_MPU auto -; IVA_S bypass CM_CLKSEL_DSP[13] -; GFXF=82.5 (gfx domain) 8 CM_CLKSEL_FGX[2:0] -; SSI_SSRF=220 3 CM_CLKSEL1_CORE[24:20] -; SSI_SSTF=110 auto -; L3=165Mhz (sdram) 4 CM_CLKSEL1_CORE[4:0] -; L4=82.5Mhz 8 -; C_L4_USB=41.25 16 CM_CLKSEL1_CORE[6:5] -***************************************************************************/ -#define I_DPLL_OUT_X2 0x2 /* x2 core out */ -#define I_MPU_DIV 0x2 /* mpu = core/2 */ -#define I_DSP_DIV 0x3c3 /* dsp & iva divider */ -#define I_GFX_DIV 0x2 -#define I_BUS_DIV 0x04601044 -#ifdef INPUT_CLK_13MHZ -#define I_DPLL_330 0x0114AC00 /* 13MHz */ -#else -#define I_DPLL_330 0x01837100 /* 12MHz */ -#endif - -/****************************************************************************; -; PRCM Scheme II <tested> -; -; Enable clocks and DPLL for: -; DPLL=300, DPLLout=600 M=1,N=50 CM_CLKSEL1_PLL[21:8] 12/2*50 -; Core=600 (core domain) DPLLx2 CM_CLKSEL2_PLL[1:0] -; MPUF=300 (mpu domain) 2 CM_CLKSEL_MPU[4:0] -; DSPF=200 (dsp domain) 3 CM_CLKSEL_DSP[4:0] -; DSPI=100 6 CM_CLKSEL_DSP[6:5] -; DSP_S bypass CM_CLKSEL_DSP[7] -; IVAF=200 (dsp domain) 3 CM_CLKSEL_DSP[12:8] -; IVAF=100 auto -; IVAI auto -; IVA_MPU auto -; IVA_S bypass CM_CLKSEL_DSP[13] -; GFXF=50 (gfx domain) 12 CM_CLKSEL_FGX[2:0] -; SSI_SSRF=200 3 CM_CLKSEL1_CORE[24:20] -; SSI_SSTF=100 auto -; L3=100Mhz (sdram) 6 CM_CLKSEL1_CORE[4:0] -; L4=100Mhz 6 -; C_L4_USB=50 12 CM_CLKSEL1_CORE[6:5] -***************************************************************************/ -#define II_DPLL_OUT_X2 0x2 /* x2 core out */ -#define II_MPU_DIV 0x2 /* mpu = core/2 */ -#define II_DSP_DIV 0x343 /* dsp & iva divider */ -#define II_GFX_DIV 0x2 -#define II_BUS_DIV 0x04601026 -#ifdef INPUT_CLK_13MHZ -#define II_DPLL_300 0x0112CC00 /* 13MHz */ -#else -#define II_DPLL_300 0x01832100 /* 12MHz */ -#endif - -/****************************************************************************; -; PRCM Scheme III <tested> -; -; Enable clocks and DPLL for: -; DPLL=266, DPLLout=532 M=5+1,N=133 CM_CLKSEL1_PLL[21:8] 12/6*133=266 -; Core=532 (core domain) DPLLx2 CM_CLKSEL2_PLL[1:0] -; MPUF=266 (mpu domain) /2 CM_CLKSEL_MPU[4:0] -; DSPF=177.3 (dsp domain) /3 CM_CLKSEL_DSP[4:0] -; DSPI=88.67 /6 CM_CLKSEL_DSP[6:5] -; DSP_S ACTIVATED CM_CLKSEL_DSP[7] -; IVAF=88.67 (dsp domain) /3 CM_CLKSEL_DSP[12:8] -; IVAF=88.67 auto -; IVAI auto -; IVA_MPU auto -; IVA_S ACTIVATED CM_CLKSEL_DSP[13] -; GFXF=66.5 (gfx domain) /8 CM_CLKSEL_FGX[2:0]: -; SSI_SSRF=177.3 /3 CM_CLKSEL1_CORE[24:20] -; SSI_SSTF=88.67 auto -; L3=133Mhz (sdram) /4 CM_CLKSEL1_CORE[4:0] -; L4=66.5Mhz /8 -; C_L4_USB=33.25 /16 CM_CLKSEL1_CORE[6:5] -***************************************************************************/ -#define III_DPLL_OUT_X2 0x2 /* x2 core out */ -#define III_MPU_DIV 0x2 /* mpu = core/2 */ -#define III_DSP_DIV 0x23C3 /* dsp & iva divider sych enabled*/ -#define III_GFX_DIV 0x2 -#define III_BUS_DIV 0x08301044 -#ifdef INPUT_CLK_13MHZ -#define III_DPLL_266 0x0110AC00 /* 13MHz */ -#else -#define III_DPLL_266 0x01885500 /* 12MHz */ -#endif - -/* set defaults for boot up */ -#ifdef PRCM_CONFIG_I -# define DPLL_OUT I_DPLL_OUT_X2 -# define MPU_DIV I_MPU_DIV -# define DSP_DIV I_DSP_DIV -# define GFX_DIV I_GFX_DIV -# define BUS_DIV I_BUS_DIV -# define DPLL_VAL I_DPLL_266 -#elif PRCM_CONFIG_II -# define DPLL_OUT II_DPLL_OUT_X2 -# define MPU_DIV II_MPU_DIV -# define DSP_DIV II_DSP_DIV -# define GFX_DIV II_GFX_DIV -# define BUS_DIV II_BUS_DIV -# define DPLL_VAL II_DPLL_300 -#elif PRCM_CONFIG_III -# define DPLL_OUT III_DPLL_OUT_X2 -# define MPU_DIV III_MPU_DIV -# define DSP_DIV III_DSP_DIV -# define GFX_DIV III_GFX_DIV -# define BUS_DIV III_BUS_DIV -# define DPLL_VAL III_DPLL_266 -#endif - -#endif diff --git a/x-loader/include/asm/arch-arm1136/clocks243x.h b/x-loader/include/asm/arch-arm1136/clocks243x.h deleted file mode 100644 index 18d2e46..0000000 --- a/x-loader/include/asm/arch-arm1136/clocks243x.h +++ /dev/null @@ -1,223 +0,0 @@ -/* - * (C) Copyright 2005 - * Texas Instruments, <www.ti.com> - * Richard Woodruff <r-woodruff2@ti.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#ifndef _OMAP243X_CLOCKS_H_ -#define _OMAP243X_CLOCKS_H_ - -/* cm_clksel core fields not ratio governed */ -#define RX_CLKSEL_DSS1 (0x10 << 8) -#define RX_CLKSEL_DSS2 (0x0 << 13) -#define RX_CLKSEL_SSI (0x5 << 20) - -/* 2430 Ratio's */ -/* 2430-Ratio Config 1 */ -#define R1_CLKSEL_L3 (4 << 0) -#define R1_CLKSEL_L4 (2 << 5) -#define R1_CLKSEL_USB (4 << 25) -#define R1_CM_CLKSEL1_CORE_VAL R1_CLKSEL_USB | RX_CLKSEL_SSI | RX_CLKSEL_DSS2 \ - | RX_CLKSEL_DSS1 | R1_CLKSEL_L4 | R1_CLKSEL_L3 -#define R1_CLKSEL_MPU (2 << 0) -#define R1_CM_CLKSEL_MPU_VAL R1_CLKSEL_MPU -#define R1_CLKSEL_DSP (2 << 0) -#define R1_CLKSEL_DSP_IF (2 << 5) -#define R1_CM_CLKSEL_DSP_VAL R1_CLKSEL_DSP | R1_CLKSEL_DSP_IF -#define R1_CLKSEL_GFX (2 << 0) -#define R1_CM_CLKSEL_GFX_VAL R1_CLKSEL_GFX -#define R1_CLKSEL_MDM (4 << 0) -#define R1_CM_CLKSEL_MDM_VAL R1_CLKSEL_MDM - -/* 2430-Ratio Config 2 */ -#define R2_CLKSEL_L3 (6 << 0) -#define R2_CLKSEL_L4 (2 << 5) -#define R2_CLKSEL_USB (2 << 25) -#define R2_CM_CLKSEL1_CORE_VAL R2_CLKSEL_USB | RX_CLKSEL_SSI | RX_CLKSEL_DSS2 \ - | RX_CLKSEL_DSS1 | R2_CLKSEL_L4 | R2_CLKSEL_L3 -#define R2_CLKSEL_MPU (2 << 0) -#define R2_CM_CLKSEL_MPU_VAL R2_CLKSEL_MPU -#define R2_CLKSEL_DSP (2 << 0) -#define R2_CLKSEL_DSP_IF (3 << 5) -#define R2_CM_CLKSEL_DSP_VAL R2_CLKSEL_DSP | R2_CLKSEL_DSP_IF -#define R2_CLKSEL_GFX (2 << 0) -#define R2_CM_CLKSEL_GFX_VAL R2_CLKSEL_GFX -#define R2_CLKSEL_MDM (6 << 0) -#define R2_CM_CLKSEL_MDM_VAL R2_CLKSEL_MDM - -/* 2430-Ratio Boot */ -#define RB_CLKSEL_L3 (1 << 0) -#define RB_CLKSEL_L4 (1 << 5) -#define RB_CLKSEL_USB (1 << 25) -#define RB_CM_CLKSEL1_CORE_VAL RB_CLKSEL_USB | RX_CLKSEL_SSI | RX_CLKSEL_DSS2 \ - | RX_CLKSEL_DSS1 | RB_CLKSEL_L4 | RB_CLKSEL_L3 -#define RB_CLKSEL_MPU (1 << 0) -#define RB_CM_CLKSEL_MPU_VAL RB_CLKSEL_MPU -#define RB_CLKSEL_DSP (1 << 0) -#define RB_CLKSEL_DSP_IF (1 << 5) -#define RB_CM_CLKSEL_DSP_VAL RB_CLKSEL_DSP | RB_CLKSEL_DSP_IF -#define RB_CLKSEL_GFX (1 << 0) -#define RB_CM_CLKSEL_GFX_VAL RB_CLKSEL_GFX -#define RB_CLKSEL_MDM (1 << 0) -#define RB_CM_CLKSEL_MDM_VAL RB_CLKSEL_MDM - -/* 2430 Target modes: Along with each configuration the CPU has several modes - * which goes along with them. Modes mainly are the addition of descrite DPLL - * combinations to go along with a ratio. - */ -/* hardware goverend */ -#define MX_48M_SRC (0 << 3) -#define MX_54M_SRC (0 << 5) -#define MX_APLLS_CLIKIN_12 (3 << 23) -#define MX_APLLS_CLIKIN_13 (2 << 23) -#define MX_APLLS_CLIKIN_19_2 (0 << 23) - -/* 2430 - standalone, 2*ref*M/(n+1), M/N is for exactness not relock speed */ - -/* boot (boot) */ -#define MB_DPLL_MULT (1 << 12) -#define MB_DPLL_DIV (0 << 8) -#define MB_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV \ - | MB_DPLL_MULT | MX_APLLS_CLIKIN_12 - -#define MB_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV \ - | MB_DPLL_MULT | MX_APLLS_CLIKIN_13 - -#define MB_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV \ - | MB_DPLL_MULT | MX_APLLS_CLIKIN_19 - -/* #2 (ratio1) DPLL = 330*2 = 660MHz, L3=165MHz */ - -#define M2_DPLL_MULT_12 (55 << 12) -#define M2_DPLL_DIV_12 (1 << 8) -#define M2_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | M2_DPLL_DIV_12 \ - | M2_DPLL_MULT_12 | MX_APLLS_CLIKIN_12 -/* Use 658.7MHz instead of 660MHz for LP-Refresh M=76 N=2, relock time issue */ -#define M2_DPLL_MULT_13 (330 << 12) -#define M2_DPLL_DIV_13 (12 << 8) -#define M2_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | M2_DPLL_DIV_13 \ - | M2_DPLL_MULT_13 | MX_APLLS_CLIKIN_13 -#define M2_DPLL_MULT_19 (275 << 12) -#define M2_DPLL_DIV_19 (15 << 8) -#define M2_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | M2_DPLL_DIV_19 \ - | M2_DPLL_MULT_19 | MX_APLLS_CLIKIN_19_2 - -/* #3 (ratio2) DPLL = 330*2 = 660MHz, L3=110MHz */ -#define M3_DPLL_MULT_12 (55 << 12) -#define M3_DPLL_DIV_12 (1 << 8) -#define M3_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | M3_DPLL_DIV_12 \ - | M3_DPLL_MULT_12 | MX_APLLS_CLIKIN_12 -#define M3_DPLL_MULT_13 (330 << 12) -#define M3_DPLL_DIV_13 (12 << 8) -#define M3_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | M3_DPLL_DIV_13 \ - | M3_DPLL_MULT_13 | MX_APLLS_CLIKIN_13 -#define M3_DPLL_MULT_19 (275 << 12) -#define M3_DPLL_DIV_19 (15 << 8) -#define M3_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | M3_DPLL_DIV_19 \ - | M3_DPLL_MULT_19 | MX_APLLS_CLIKIN_19_2 - -/* #4 (ratio2), DPLL = 399*2 = 798MHz, L3=133MHz*/ -#define M4_DPLL_MULT_12 (133 << 12) -#define M4_DPLL_DIV_12 (3 << 8) -#define M4_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | M4_DPLL_DIV_12 \ - | M4_DPLL_MULT_12 | MX_APLLS_CLIKIN_12 -#define M4_DPLL_MULT_13 (399 << 12) -#define M4_DPLL_DIV_13 (12 << 8) -#define M4_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | M4_DPLL_DIV_13 \ - | M4_DPLL_MULT_13 | MX_APLLS_CLIKIN_13 -#define M4_DPLL_MULT_19 (145 << 12) -#define M4_DPLL_DIV_19 (6 << 8) -#define M4_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | M4_DPLL_DIV_19 \ - | M4_DPLL_MULT_19 | MX_APLLS_CLIKIN_19_2 - -/* #5a (ratio1) baseport-target, target DPLL = 266*2 = 532MHz, L3=133MHz */ -#define M5A_DPLL_MULT_12 (133 << 12) -#define M5A_DPLL_DIV_12 (5 << 8) -#define M5A_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | M5A_DPLL_DIV_12 \ - | M5A_DPLL_MULT_12 | MX_APLLS_CLIKIN_12 -#define M5A_DPLL_MULT_13 (266 << 12) -#define M5A_DPLL_DIV_13 (12 << 8) -#define M5A_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | M5A_DPLL_DIV_13 \ - | M5A_DPLL_MULT_13 | MX_APLLS_CLIKIN_13 -#define M5A_DPLL_MULT_19 (180 << 12) -#define M5A_DPLL_DIV_19 (12 << 8) -#define M5A_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | M5A_DPLL_DIV_19 \ - | M5A_DPLL_MULT_19 | MX_APLLS_CLIKIN_19_2 - -/* #5b (ratio1) target DPLL = 200*2 = 400MHz, L3=100MHz */ -#define M5B_DPLL_MULT_12 (50 << 12) -#define M5B_DPLL_DIV_12 (2 << 8) -#define M5B_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | M5B_DPLL_DIV_12 \ - | M5B_DPLL_MULT_12 | MX_APLLS_CLIKIN_12 -#define M5B_DPLL_MULT_13 (200 << 12) -#define M5B_DPLL_DIV_13 (12 << 8) - -#define M5B_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | M5B_DPLL_DIV_13 \ - | M5B_DPLL_MULT_13 | MX_APLLS_CLIKIN_13 -#define M5B_DPLL_MULT_19 (125 << 12) -#define M5B_DPLL_DIV_19 (31 << 8) -#define M5B_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | M5B_DPLL_DIV_19 \ - | M5B_DPLL_MULT_19 | MX_APLLS_CLIKIN_19_2 - -/* 2430 - chassis (sedna) */ - /* 165 (ratio1) same as above #2 */ - /* 150 (ratio1)*/ - /* 133 (ratio2) same as above #4 */ - /* 110 (ratio2) same as above #3*/ - /* 104 (ratio2)*/ - /* boot (boot) */ - -/* high and low operation value */ -#define MX_CLKSEL2_PLL_2x_VAL (2 << 0) -#define MX_CLKSEL2_PLL_1x_VAL (1 << 0) - -/* set defaults for boot up */ -#if defined(PRCM_CONFIG_2) /* ARM-330MHz IVA2-330MHz L3-165MHz */ -# define DPLL_OUT MX_CLKSEL2_PLL_2x_VAL -# define MPU_DIV R1_CLKSEL_MPU -# define DSP_DIV R1_CM_CLKSEL_DSP_VAL -# define GFX_DIV R1_CM_CLKSEL_GFX_VAL -# define BUS_DIV R1_CM_CLKSEL1_CORE_VAL -# define DPLL_VAL M2_CM_CLKSEL1_PLL_13_VAL -# define MDM_DIV R2_CM_CLKSEL_MDM_VAL -#elif defined(PRCM_CONFIG_3) /* ARM-330MHz IVA2-330MHz L3-110MHz */ -# define DPLL_OUT MX_CLKSEL2_PLL_2x_VAL -# define MPU_DIV R2_CLKSEL_MPU -# define DSP_DIV R2_CM_CLKSEL_DSP_VAL -# define GFX_DIV R2_CM_CLKSEL_GFX_VAL -# define BUS_DIV R2_CM_CLKSEL1_CORE_VAL -# define DPLL_VAL M3_CM_CLKSEL1_PLL_13_VAL -# define MDM_DIV R2_CM_CLKSEL_MDM_VAL -#elif defined(PRCM_CONFIG_5A) /* ARM-266MHz IVA2-266MHz L3-133MHz */ -# define DPLL_OUT MX_CLKSEL2_PLL_2x_VAL -# define MPU_DIV R1_CLKSEL_MPU -# define DSP_DIV R1_CM_CLKSEL_DSP_VAL -# define GFX_DIV R1_CM_CLKSEL_GFX_VAL -# define BUS_DIV R1_CM_CLKSEL1_CORE_VAL -# define DPLL_VAL M5A_CM_CLKSEL1_PLL_13_VAL -# define MDM_DIV R2_CM_CLKSEL_MDM_VAL -#elif defined(PRCM_CONFIG_5B) /* ARM-200MHz IVA2-200MHz L3-100MHz */ -# define DPLL_OUT MX_CLKSEL2_PLL_2x_VAL -# define MPU_DIV R1_CLKSEL_MPU -# define DSP_DIV R1_CM_CLKSEL_DSP_VAL -# define GFX_DIV R1_CM_CLKSEL_GFX_VAL -# define BUS_DIV R1_CM_CLKSEL1_CORE_VAL -# define DPLL_VAL M5B_CM_CLKSEL1_PLL_13_VAL -# define MDM_DIV R1_CM_CLKSEL_MDM_VAL -#endif - -#endif diff --git a/x-loader/include/asm/arch-arm1136/mem.h b/x-loader/include/asm/arch-arm1136/mem.h deleted file mode 100644 index 2a3da73..0000000 --- a/x-loader/include/asm/arch-arm1136/mem.h +++ /dev/null @@ -1,383 +0,0 @@ - -/* - * (C) Copyright 2004-2005 - * Texas Instruments, <www.ti.com> - * Richard Woodruff <r-woodruff2@ti.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _OMAP24XX_MEM_H_ -#define _OMAP24XX_MEM_H_ - -#define SDRC_CS0_OSET 0x0 -#define SDRC_CS1_OSET 0x30 /* mirror CS1 regs appear offset 0x30 from CS0 */ - -#ifndef __ASSEMBLY__ -/* struct's for holding data tables for current boards, they are getting used - early in init when NO global access are there */ -struct sdrc_data_s { - u32 sdrc_sharing; - u32 sdrc_mdcfg_0_ddr; - u32 sdrc_mdcfg_0_sdr; - u32 sdrc_actim_ctrla_0; - u32 sdrc_actim_ctrlb_0; - u32 sdrc_rfr_ctrl; - u32 sdrc_mr_0_ddr; - u32 sdrc_mr_0_sdr; - u32 sdrc_dllab_ctrl; -} /*__attribute__ ((packed))*/; -typedef struct sdrc_data_s sdrc_data_t; - -typedef enum { - STACKED = 0, - IP_DDR = 1, - COMBO_DDR = 2, - IP_SDR = 3, -} mem_t; - -#endif - -/* set the 243x-SDRC incoming address convention */ -#if defined(SDRC_B_R_C) -#define B_ALL (0 << 6) /* bank-row-column */ -#elif defined(SDRC_B1_R_B0_C) -#define B_ALL (1 << 6) /* bank1-row-bank0-column */ -#elif defined(SDRC_R_B_C) -#define B_ALL (2 << 6) /* row-bank-column */ -#endif - -/* Slower full frequency range default timings for x32 operation*/ -#define H4_2420_SDRC_SHARING 0x00000100 -#define H4_2420_SDRC_MDCFG_0_SDR 0x00D04010 /* discrete sdr module */ -#define H4_2420_SDRC_MR_0_SDR 0x00000031 -#define H4_2420_SDRC_MDCFG_0_DDR 0x01702011 /* descrite ddr module */ -#define SDP_2430_SDRC_MDCFG_0_DDR (0x02584019|B_ALL) /* Infin ddr module */ -#define H4_2420_COMBO_MDCFG_0_DDR 0x00801011 /* combo module */ -#define H4_2420_SDRC_MR_0_DDR 0x00000032 - -#define H4_2422_SDRC_SHARING 0x00004b00 -#define H4_2422_SDRC_MDCFG_MONO_DDR 0x01A02011 /* stacked mono die ddr on 2422 */ -#define H4_2422_SDRC_MDCFG_0_DDR 0x00801011 /* stacked dual die ddr on 2422 */ -#define H4_2422_SDRC_MR_0_DDR 0x00000032 - -#define H4_2423_SDRC_SHARING 0x00004900 /* 2420POP board cke1 not connected */ -#define H4_2423_SDRC_MDCFG_0_DDR 0x01A02011 /* stacked dual die ddr on 2423 */ -#define H4_2423_SDRC_MDCFG_1_DDR 0x00801011 /* stacked dual die ddr on 2423 */ - -/* ES1 work around timings */ -#define H4_242x_SDRC_ACTIM_CTRLA_0_ES1 0x9bead909 /* 165Mhz for use with 100/133 */ -#define H4_242x_SDRC_ACTIM_CTRLB_0_ES1 0x00000020 -#define H4_242x_SDRC_RFR_CTRL_ES1 0x00002401 /* use over refresh for ES1 */ - -/* optimized timings good for current shipping parts */ -#define H4_242X_SDRC_ACTIM_CTRLA_0_100MHz 0x5A59B485 -#define H4_242X_SDRC_ACTIM_CTRLB_0_100MHz 0x0000000e -#define H4_242X_SDRC_ACTIM_CTRLA_0_133MHz 0x8BA6E6C8 /* temp warn 0 settings */ -#define H4_242X_SDRC_ACTIM_CTRLB_0_133MHz 0x00000010 /* temp warn 0 settings */ -#define H4_242X_SDRC_RFR_CTRL_100MHz 0x0002da01 -#define H4_242X_SDRC_RFR_CTRL_133MHz 0x0003de01 /* 7.8us/7.5ns - 50 = 0x3de */ -#define SDP_24XX_SDRC_RFR_CTRL_165MHz 0x0004e201 /* 7.8us/6ns - 50 = 0x4e2 */ -#define H4_242X_SDRC_DLLAB_CTRL_100MHz 0x0000980E /* 90deg, allow DPLLout*1 to work (combo)*/ -#define H4_242X_SDRC_DLLAB_CTRL_133MHz 0x0000690E /* 90deg, for ES2 */ -#define SDP_24XX_SDRC_DLLAB_CTRL_165MHz 0x0000170C /* 72deg, code will recalc dll load */ - -/* Infineon part of 2430SDP (133MHz optimized) ~ 7.5ns - * TDAL = Twr/Tck + Trp/tck = 15/7.5 + 22.5/7.5 = 2 + 3 = 5 - * TDPL = 15/7.5 = 2 - * TRRD = 15/2.5 = 2 - * TRCD = 22.5/7.5 = 3 - * TRP = 22.5/7.5 = 3 - * TRAS = 45/7.5 = 6 - * TRC = 65/7.5 = 8.6->9 - * TRFC = 75/7.5 = 10 - * ACTIMB - * TCKE = 2 <new in 2430> - * XSR = 120/7.5 = 16 - */ -#define TDAL_133 5 -#define TDPL_133 2 -#define TRRD_133 2 -#define TRCD_133 3 -#define TRP_133 3 -#define TRAS_133 6 -#define TRC_133 9 -#define TRFC_133 10 -#define V_ACTIMA_133 ((TRFC_133 << 27) | (TRC_133 << 22) | (TRAS_133 << 18) |(TRP_133 << 15) | \ - (TRCD_133 << 12) |(TRRD_133 << 9) |(TDPL_133 << 6) | (TDAL_133)) - -#define TCKE_133 2 -#define XSR_133 16 -#define V_ACTIMB_133 ((TCKE_133 << 12) | (XSR_133 << 0)) - -/* Infineon part of 2430SDP (165MHz optimized) 6.06ns - * ACTIMA - * TDAL = Twr/Tck + Trp/tck = 15/6 + 18/6 = 2.5 + 3 = 5.5 -> 6 - * TDPL (Twr) = 15/6 = 2.5 -> 3 - * TRRD = 12/6 = 2 - * TRCD = 18/6 = 3 - * TRP = 18/6 = 3 - * TRAS = 42/6 = 7 - * TRC = 60/6 = 10 - * TRFC = 72/6 = 12 - * ACTIMB - * TCKE = 2 <new in 2430> - * XSR = 120/6 = 20 - */ -#define TDAL_165 6 -#define TDPL_165 3 -#define TRRD_165 2 -#define TRCD_165 3 -#define TRP_165 3 -#define TRAS_165 7 -#define TRC_165 10 -#define TRFC_165 12 -#define V_ACTIMA_165 ((TRFC_165 << 27) | (TRC_165 << 22) | (TRAS_165 << 18) |(TRP_165 << 15) | \ - (TRCD_165 << 12) |(TRRD_165 << 9) |(TDPL_165 << 6) | (TDAL_165)) - -#define TCKE_165 2 -#define XSR_165 20 -#define V_ACTIMB_165 ((TCKE_165 << 12) | (XSR_165 << 0)) - -#if defined(PRCM_CONFIG_II) || defined(PRCM_CONFIG_5B) -# define H4_2420_SDRC_ACTIM_CTRLA_0 H4_242X_SDRC_ACTIM_CTRLA_0_100MHz -# define SDP_2430_SDRC_ACTIM_CTRLA_0 V_ACTIMA_133 -# define H4_2420_SDRC_ACTIM_CTRLB_0 H4_242X_SDRC_ACTIM_CTRLB_0_100MHz -# define H4_2420_SDRC_RFR_CTRL H4_242X_SDRC_RFR_CTRL_100MHz -# define H4_2420_SDRC_DLLAB_CTRL H4_242X_SDRC_DLLAB_CTRL_100MHz -# define SDP_2430_SDRC_DLLAB_CTRL 0x0000730E -# define H4_2422_SDRC_ACTIM_CTRLA_0 H4_242X_SDRC_ACTIM_CTRLA_0_100MHz -# define H4_2422_SDRC_ACTIM_CTRLB_0 H4_242X_SDRC_ACTIM_CTRLB_0_100MHz -# define H4_2422_SDRC_RFR_CTRL H4_242X_SDRC_RFR_CTRL_100MHz -# define H4_2422_SDRC_DLLAB_CTRL H4_242X_SDRC_DLLAB_CTRL_100MHz -#elif defined(PRCM_CONFIG_III) || defined(PRCM_CONFIG_5A) || defined(PRCM_CONFIG_3) -# define H4_2420_SDRC_ACTIM_CTRLA_0 H4_242X_SDRC_ACTIM_CTRLA_0_133MHz -# define SDP_2430_SDRC_ACTIM_CTRLA_0 V_ACTIMA_133 -# define H4_2420_SDRC_ACTIM_CTRLB_0 H4_242X_SDRC_ACTIM_CTRLB_0_133MHz -# define H4_2420_SDRC_RFR_CTRL H4_242X_SDRC_RFR_CTRL_133MHz -# define H4_2420_SDRC_DLLAB_CTRL H4_242X_SDRC_DLLAB_CTRL_133MHz -# define SDP_2430_SDRC_DLLAB_CTRL 0x0000730E -# define H4_2422_SDRC_ACTIM_CTRLA_0 H4_242X_SDRC_ACTIM_CTRLA_0_133MHz -# define H4_2422_SDRC_ACTIM_CTRLB_0 H4_242X_SDRC_ACTIM_CTRLB_0_133MHz -# define H4_2422_SDRC_RFR_CTRL H4_242X_SDRC_RFR_CTRL_133MHz -# define H4_2422_SDRC_DLLAB_CTRL H4_242X_SDRC_DLLAB_CTRL_133MHz -#elif defined(PRCM_CONFIG_I) || defined(PRCM_CONFIG_2) -# define H4_2420_SDRC_ACTIM_CTRLA_0 V_ACTIMA_165 -# define SDP_2430_SDRC_ACTIM_CTRLA_0 V_ACTIMA_165 -# define H4_2420_SDRC_ACTIM_CTRLB_0 V_ACTIMB_165 -# define H4_2420_SDRC_RFR_CTRL SDP_24XX_SDRC_RFR_CTRL_165MHz -# define H4_2420_SDRC_DLLAB_CTRL SDP_24XX_SDRC_DLLAB_CTRL_165MHz -# define SDP_2430_SDRC_DLLAB_CTRL SDP_24XX_SDRC_DLLAB_CTRL_165MHz -# define H4_2422_SDRC_ACTIM_CTRLA_0 V_ACTIMA_165 -# define H4_2422_SDRC_ACTIM_CTRLB_0 V_ACTIMB_165 -# define H4_2422_SDRC_RFR_CTRL SDP_24XX_SDRC_RFR_CTRL_165MHz -# define H4_2422_SDRC_DLLAB_CTRL SDP_24XX_SDRC_DLLAB_CTRL_165MHz -#endif - -/* - * GPMC settings - - * Definitions is as per the following format - * # define <PART>_GPMC_CONFIG<x> <value> - * Where: - * PART is the part name e.g. STNOR - Intel Strata Flash - * x is GPMC config registers from 1 to 6 (there will be 6 macros) - * Value is corresponding value - * - * For every valid PRCM configuration there should be only one definition of the same. - * if values are independent of the board, this definition will be present in this file - * if values are dependent on the board, then this should go into corresponding mem-boardName.h file - * - * Currently valid part Names are (PART): - * STNOR - Intel Strata Flash - * SMNAND - Samsung NAND - * MPDB - H4 MPDB board - * SBNOR - Sibley NOR - * ONNAND - Samsung One NAND - * - * include/configs/file.h contains the following defn - for all CS we are interested - * #define OMAP24XX_GPMC_CSx PART - * #define OMAP24XX_GPMC_CSx_SIZE Size - * #define OMAP24XX_GPMC_CSx_MAP Map - * Where: - * x - CS number - * PART - Part Name as defined above - * SIZE - how big is the mapping to be - * GPMC_SIZE_128M - 0x8 - * GPMC_SIZE_64M - 0xC - * GPMC_SIZE_32M - 0xE - * GPMC_SIZE_16M - 0xF - * MAP - Map this CS to which address(GPMC address space)- Absolute address - * >>24 before being used. - */ - -#define GPMC_SIZE_256M 0x0 -#define GPMC_SIZE_128M 0x8 -#define GPMC_SIZE_64M 0xC -#define GPMC_SIZE_32M 0xE -#define GPMC_SIZE_16M 0xF - -#if defined(PRCM_CONFIG_II) || defined(PRCM_CONFIG_5B) /* L3 at 100MHz */ -# define SMNAND_GPMC_CONFIG1 0x0 -# define SMNAND_GPMC_CONFIG2 0x00141400 -# define SMNAND_GPMC_CONFIG3 0x00141400 -# define SMNAND_GPMC_CONFIG4 0x0F010F01 -# define SMNAND_GPMC_CONFIG5 0x010C1414 -# define SMNAND_GPMC_CONFIG6 0x00000A80 -# define STNOR_GPMC_CONFIG1 0x3 -# define STNOR_GPMC_CONFIG2 0x000f0f01 -# define STNOR_GPMC_CONFIG3 0x00050502 -# define STNOR_GPMC_CONFIG4 0x0C060C06 -# define STNOR_GPMC_CONFIG5 0x01131F1F -# define STNOR_GPMC_CONFIG6 0x0 /* 0? Not defined so far... this value is reset val as per gpmc doc */ -# define MPDB_GPMC_CONFIG1 0x00011000 -# define MPDB_GPMC_CONFIG2 0x001F1F00 -# define MPDB_GPMC_CONFIG3 0x00080802 -# define MPDB_GPMC_CONFIG4 0x1C091C09 -# define MPDB_GPMC_CONFIG5 0x031A1F1F -# define MPDB_GPMC_CONFIG6 0x000003C2 -#endif - -#if defined(PRCM_CONFIG_III) || defined(PRCM_CONFIG_5A) || defined(PRCM_CONFIG_3) /* L3 at 133MHz */ -# define SMNAND_GPMC_CONFIG1 0x00001800 -# define SMNAND_GPMC_CONFIG2 0x00141400 -# define SMNAND_GPMC_CONFIG3 0x00141400 -# define SMNAND_GPMC_CONFIG4 0x0F010F01 -# define SMNAND_GPMC_CONFIG5 0x010C1414 -# define SMNAND_GPMC_CONFIG6 0x00000A80 -# define SMNAND_GPMC_CONFIG7 0x00000C44 - -# define STNOR_GPMC_CONFIG1 0x3 -# define STNOR_GPMC_CONFIG2 0x00151501 -# define STNOR_GPMC_CONFIG3 0x00060602 -# define STNOR_GPMC_CONFIG4 0x10081008 -# define STNOR_GPMC_CONFIG5 0x01131F1F -# define STNOR_GPMC_CONFIG6 0x000004c4 - -# define MPDB_GPMC_CONFIG1 0x00011000 -# define MPDB_GPMC_CONFIG2 0x001f1f01 -# define MPDB_GPMC_CONFIG3 0x00080803 -# define MPDB_GPMC_CONFIG4 0x1C091C09 -# define MPDB_GPMC_CONFIG5 0x041f1F1F -# define MPDB_GPMC_CONFIG6 0x000004C4 - -# define SIBNOR_GPMC_CONFIG1 0x3 -# define SIBNOR_GPMC_CONFIG2 0x00151501 -# define SIBNOR_GPMC_CONFIG3 0x00060602 -# define SIBNOR_GPMC_CONFIG4 0x10081008 -# define SIBNOR_GPMC_CONFIG5 0x01131F1F -# define SIBNOR_GPMC_CONFIG6 0x00000000 - -# define ONENAND_GPMC_CONFIG1 0x00001200 -# define ONENAND_GPMC_CONFIG2 0x000c0c01 -# define ONENAND_GPMC_CONFIG3 0x00030301 -# define ONENAND_GPMC_CONFIG4 0x0c040c04 -# define ONENAND_GPMC_CONFIG5 0x010C1010 -# define ONENAND_GPMC_CONFIG6 0x00000000 - -# define PCMCIA_GPMC_CONFIG1 0x01E91200 -# define PCMCIA_GPMC_CONFIG2 0x001E1E01 -# define PCMCIA_GPMC_CONFIG3 0x00020203 -# define PCMCIA_GPMC_CONFIG4 0x1D041D04 -# define PCMCIA_GPMC_CONFIG5 0x031D1F1F -# define PCMCIA_GPMC_CONFIG6 0x000004C4 -#endif /* endif CFG_PRCM_III */ - -#if defined (PRCM_CONFIG_I) || defined(PRCM_CONFIG_2) /* L3 at 165MHz */ -# define SMNAND_GPMC_CONFIG1 0x00001800 -# define SMNAND_GPMC_CONFIG2 0x00141400 -# define SMNAND_GPMC_CONFIG3 0x00141400 -# define SMNAND_GPMC_CONFIG4 0x0F010F01 -# define SMNAND_GPMC_CONFIG5 0x010C1414 -# define SMNAND_GPMC_CONFIG6 0x00000A80 -# define SMNAND_GPMC_CONFIG7 0x00000C44 - -# define STNOR_GPMC_CONFIG1 0x3 -# define STNOR_GPMC_CONFIG2 0x00151501 -# define STNOR_GPMC_CONFIG3 0x00060602 -# define STNOR_GPMC_CONFIG4 0x11091109 -# define STNOR_GPMC_CONFIG5 0x01141F1F -# define STNOR_GPMC_CONFIG6 0x000004c4 - -# define MPDB_GPMC_CONFIG1 0x00011000 -# define MPDB_GPMC_CONFIG2 0x001f1f01 -# define MPDB_GPMC_CONFIG3 0x00080803 -# define MPDB_GPMC_CONFIG4 0x1c0b1c0a -# define MPDB_GPMC_CONFIG5 0x041f1F1F -# define MPDB_GPMC_CONFIG6 0x000004C4 - -# define SIBNOR_GPMC_CONFIG1 0x3 -# define SIBNOR_GPMC_CONFIG2 0x00151501 -# define SIBNOR_GPMC_CONFIG3 0x00060602 -# define SIBNOR_GPMC_CONFIG4 0x11091109 -# define SIBNOR_GPMC_CONFIG5 0x01141F1F -# define SIBNOR_GPMC_CONFIG6 0x00000000 - -# define ONENAND_GPMC_CONFIG1 0x00001200 -# define ONENAND_GPMC_CONFIG2 0x000F0F01 -# define ONENAND_GPMC_CONFIG3 0x00030301 -# define ONENAND_GPMC_CONFIG4 0x0F040F04 -# define ONENAND_GPMC_CONFIG5 0x010F1010 -# define ONENAND_GPMC_CONFIG6 0x00000000 - -# define PCMCIA_GPMC_CONFIG1 0x01E91200 -# define PCMCIA_GPMC_CONFIG2 0x001E1E01 -# define PCMCIA_GPMC_CONFIG3 0x00020203 -# define PCMCIA_GPMC_CONFIG4 0x1D041D04 -# define PCMCIA_GPMC_CONFIG5 0x031D1F1F -# define PCMCIA_GPMC_CONFIG6 0x000004C4 - -#endif - -#if 0 -/* Board Specific Settings for each of the configurations for chips - * whose values change as per platform. - None currently - */ -#if CONFIG_OMAP24XXH4 -#include <asm/arch/mem-h4.h> -#endif - -#if CONFIG_2430SDP -#include <asm/arch/mem-sdp2430.h> -#endif - -#endif /* if 0 */ - -/* max number of GPMC Chip Selects */ -#define GPMC_MAX_CS 8 -/* max number of GPMC regs */ -#define GPMC_MAX_REG 7 - -#define PROC_NOR 1 -#define PROC_NAND 2 -#define PISMO_SIBLEY0 3 -#define PISMO_SIBLEY1 4 -#define PISMO_ONENAND 5 -#define DBG_MPDB 6 -#define PISMO_PCMCIA 7 - -/* make it readable for the gpmc_init */ -#define PROC_NOR_BASE FLASH_BASE -#define PROC_NAND_BASE NAND_BASE -#define PISMO_SIB0_BASE SIBLEY_MAP1 -#define PISMO_SIB1_BASE SIBLEY_MAP2 -#define PISMO_ONEN_BASE ONENAND_MAP -#define DBG_MPDB_BASE DEBUG_BASE -#define PISMO_PCMCIA_BASE PCMCIA_BASE - -#endif /* endif _OMAP24XX_MEM_H_ */ diff --git a/x-loader/include/asm/arch-arm1136/omap2420.h b/x-loader/include/asm/arch-arm1136/omap2420.h deleted file mode 100644 index 2164b68..0000000 --- a/x-loader/include/asm/arch-arm1136/omap2420.h +++ /dev/null @@ -1,223 +0,0 @@ -/* - * Copyright (C) 2005 Texas Instruments, <www.ti.com> - * - * (C) Copyright 2004 - * Texas Instruments, <www.ti.com> - * Richard Woodruff <r-woodruff2@ti.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _OMAP2420_SYS_H_ -#define _OMAP2420_SYS_H_ - -#include <asm/arch/sizes.h> - - -#define __raw_writeb(v,a) (*(volatile unsigned char *)(a) = (v)) -#define __raw_writew(v,a) (*(volatile unsigned short *)(a) = (v)) -#define __raw_writel(v,a) (*(volatile unsigned int *)(a) = (v)) - -#define __raw_readb(a) (*(volatile unsigned char *)(a)) -#define __raw_readw(a) (*(volatile unsigned short *)(a)) -#define __raw_readl(a) (*(volatile unsigned int *)(a)) - - -/* - * 2420 specific Section - */ - -/* CONTROL */ -#define OMAP2420_CTRL_BASE (0x48000000) -#define CONTROL_STATUS (OMAP2420_CTRL_BASE + 0x2F8) - -/* TAP information */ -#define OMAP2420_TAP_BASE (0x48014000) -#define TAP_IDCODE_REG (OMAP2420_TAP_BASE+0x204) - -/* GPMC */ -#define OMAP2420_GPMC_BASE (0x6800A000) -#define GPMC_SYSCONFIG (OMAP2420_GPMC_BASE+0x10) -#define GPMC_SYSSTATUS (OMAP2420_GPMC_BASE+0x14) -#define GPMC_IRQENABLE (OMAP2420_GPMC_BASE+0x1C) -#define GPMC_TIMEOUT_CONTROL (OMAP2420_GPMC_BASE+0x40) -#define GPMC_CONFIG (OMAP2420_GPMC_BASE+0x50) -#define GPMC_CONFIG1_0 (OMAP2420_GPMC_BASE+0x60) -#define GPMC_CONFIG2_0 (OMAP2420_GPMC_BASE+0x64) -#define GPMC_CONFIG3_0 (OMAP2420_GPMC_BASE+0x68) -#define GPMC_CONFIG4_0 (OMAP2420_GPMC_BASE+0x6C) -#define GPMC_CONFIG5_0 (OMAP2420_GPMC_BASE+0x70) -#define GPMC_CONFIG6_0 (OMAP2420_GPMC_BASE+0x74) -#define GPMC_CONFIG7_0 (OMAP2420_GPMC_BASE+0x78) -#define GPMC_CONFIG1_1 (OMAP2420_GPMC_BASE+0x90) -#define GPMC_CONFIG2_1 (OMAP2420_GPMC_BASE+0x94) -#define GPMC_CONFIG3_1 (OMAP2420_GPMC_BASE+0x98) -#define GPMC_CONFIG4_1 (OMAP2420_GPMC_BASE+0x9C) -#define GPMC_CONFIG5_1 (OMAP2420_GPMC_BASE+0xA0) -#define GPMC_CONFIG6_1 (OMAP2420_GPMC_BASE+0xA4) -#define GPMC_CONFIG7_1 (OMAP2420_GPMC_BASE+0xA8) - -/* SMS */ -#define OMAP2420_SMS_BASE 0x68008000 -#define SMS_SYSCONFIG (OMAP2420_SMS_BASE+0x10) - -/* SDRC */ -#define OMAP2420_SDRC_BASE 0x68009000 -#define SDRC_SYSCONFIG (OMAP2420_SDRC_BASE+0x10) -#define SDRC_STATUS (OMAP2420_SDRC_BASE+0x14) -#define SDRC_SHARING (OMAP2420_SDRC_BASE+0x44) -#define SDRC_DLLA_CTRL (OMAP2420_SDRC_BASE+0x60) -#define SDRC_DLLA_STATUS (OMAP2420_SDRC_BASE+0x64) -#define SDRC_DLLB_CTRL (OMAP2420_SDRC_BASE+0x68) -#define SDRC_POWER (OMAP2420_SDRC_BASE+0x70) -#define SDRC_MCFG_0 (OMAP2420_SDRC_BASE+0x80) -#define SDRC_MR_0 (OMAP2420_SDRC_BASE+0x84) -#define SDRC_ACTIM_CTRLA_0 (OMAP2420_SDRC_BASE+0x9C) -#define SDRC_ACTIM_CTRLB_0 (OMAP2420_SDRC_BASE+0xA0) -#define SDRC_MCFG_1 (OMAP2420_SDRC_BASE+0xB0) -#define SDRC_MR_1 (OMAP2420_SDRC_BASE+0xB4) -#define SDRC_EMR2_1 (OMAP2420_SDRC_BASE+0xBC) -#define SDRC_ACTIM_CTRLA_1 (OMAP2420_SDRC_BASE+0xC4) -#define SDRC_ACTIM_CTRLB_1 (OMAP2420_SDRC_BASE+0xC8) -#define SDRC_RFR_CTRL (OMAP2420_SDRC_BASE+0xA4) -#define SDRC_MANUAL_0 (OMAP2420_SDRC_BASE+0xA8) -#define SDRC_RFR_CTRL1 (OMAP2420_SDRC_BASE+0xD4) -#define SDRC_MANUAL_1 (OMAP2420_SDRC_BASE+0xD8) - -#define OMAP2420_SDRC_CS0 0x80000000 -#define OMAP2420_SDRC_CS1 0xA0000000 - -#define LOADDLL BIT2 -#define CMD_NOP 0x0 -#define CMD_PRECHARGE 0x1 -#define CMD_AUTOREFRESH 0x2 -#define CMD_ENTR_PWRDOWN 0x3 -#define CMD_EXIT_PWRDOWN 0x4 -#define CMD_ENTR_SRFRSH 0x5 -#define CMD_CKE_HIGH 0x6 -#define CMD_CKE_LOW 0x7 -#define SOFTRESET BIT1 -#define SMART_IDLE (0x2 << 3) -#define REF_ON_IDLE (0x1 << 6) - - -/* UART */ -#define OMAP2420_UART1 0x4806A000 -#define OMAP2420_UART2 0x4806C000 -#define OMAP2420_UART3 0x4806E000 - -/* General Purpose Timers */ -#define OMAP2420_GPT1 0x48028000 -#define OMAP2420_GPT2 0x4802A000 -#define OMAP2420_GPT3 0x48078000 -#define OMAP2420_GPT4 0x4807A000 -#define OMAP2420_GPT5 0x4807C000 -#define OMAP2420_GPT6 0x4807E000 -#define OMAP2420_GPT7 0x48080000 -#define OMAP2420_GPT8 0x48082000 -#define OMAP2420_GPT9 0x48084000 -#define OMAP2420_GPT10 0x48086000 -#define OMAP2420_GPT11 0x48088000 -#define OMAP2420_GPT12 0x4808A000 - -/* timer regs offsets (32 bit regs) */ -#define TIDR 0x0 /* r */ -#define TIOCP_CFG 0x10 /* rw */ -#define TISTAT 0x14 /* r */ -#define TISR 0x18 /* rw */ -#define TIER 0x1C /* rw */ -#define TWER 0x20 /* rw */ -#define TCLR 0x24 /* rw */ -#define TCRR 0x28 /* rw */ -#define TLDR 0x2C /* rw */ -#define TTGR 0x30 /* rw */ -#define TWPS 0x34 /* r */ -#define TMAR 0x38 /* rw */ -#define TCAR1 0x3c /* r */ -#define TSICR 0x40 /* rw */ -#define TCAR2 0x44 /* r */ - -/* WatchDog Timers (1 secure, 3 GP) */ -#define WD1_BASE 0x48020000 -#define WD2_BASE 0x48022000 -#define WD3_BASE 0x48024000 -#define WD4_BASE 0x48026000 -#define WWPS 0x34 /* r */ -#define WSPR 0x48 /* rw */ -#define WD_UNLOCK1 0xAAAA -#define WD_UNLOCK2 0x5555 - -/* PRCM */ -#define OMAP2420_CM_BASE 0x48008000 -#define PRCM_CLKCFG_CTRL (OMAP2420_CM_BASE+0x080) -#define CM_CLKSEL_MPU (OMAP2420_CM_BASE+0x140) -#define CM_FCLKEN1_CORE (OMAP2420_CM_BASE+0x200) -#define CM_FCLKEN2_CORE (OMAP2420_CM_BASE+0x204) -#define CM_ICLKEN1_CORE (OMAP2420_CM_BASE+0x210) -#define CM_ICLKEN2_CORE (OMAP2420_CM_BASE+0x214) -#define CM_CLKSEL1_CORE (OMAP2420_CM_BASE+0x240) -#define CM_CLKSEL_WKUP (OMAP2420_CM_BASE+0x440) -#define CM_CLKSEL2_CORE (OMAP2420_CM_BASE+0x244) -#define CM_CLKSEL_GFX (OMAP2420_CM_BASE+0x340) -#define PM_RSTCTRL_WKUP (OMAP2420_CM_BASE+0x450) -#define CM_CLKEN_PLL (OMAP2420_CM_BASE+0x500) -#define CM_IDLEST_CKGEN (OMAP2420_CM_BASE+0x520) -#define CM_CLKSEL1_PLL (OMAP2420_CM_BASE+0x540) -#define CM_CLKSEL2_PLL (OMAP2420_CM_BASE+0x544) -#define CM_CLKSEL_DSP (OMAP2420_CM_BASE+0x840) - -/* - * H4 specific Section - */ - -/* - * The 2420's chip selects are programmable. The mask ROM - * does configure CS0 to 0x08000000 before dispatch. So, if - * you want your code to live below that address, you have to - * be prepared to jump though hoops, to reset the base address. - */ -#if defined(CONFIG_OMAP2420H4) -/* GPMC */ -#ifdef CONFIG_VIRTIO_A /* Pre version B */ -# define H4_CS0_BASE 0x08000000 /* flash (64 Meg aligned) */ -# define H4_CS1_BASE 0x04000000 /* debug board */ -# define H4_CS2_BASE 0x0A000000 /* wifi board */ -#else -# define H4_CS0_BASE 0x04000000 /* flash (64 Meg aligned) */ -# define H4_CS1_BASE 0x08000000 /* debug board */ -# define H4_CS2_BASE 0x0A000000 /* wifi board */ -#endif - -/* base address for indirect vectors (internal boot mode) */ -#define SRAM_OFFSET0 0x40000000 -#define SRAM_OFFSET1 0x00200000 -#define SRAM_OFFSET2 0x0000F800 -#define SRAM_VECT_CODE (SRAM_OFFSET0|SRAM_OFFSET1|SRAM_OFFSET2) - -#define LOW_LEVEL_SRAM_STACK 0x4020FFFC - -#define PERIFERAL_PORT_BASE 0x480FE003 - -/* FPGA on Debug board.*/ -#define ETH_CONTROL_REG (H4_CS1_BASE+0x30b) -#define LAN_RESET_REGISTER (H4_CS1_BASE+0x1c) -#endif /* endif CONFIG_2420H4 */ - -#endif - diff --git a/x-loader/include/asm/arch-arm1136/omap2430.h b/x-loader/include/asm/arch-arm1136/omap2430.h deleted file mode 100644 index cf2b0f9..0000000 --- a/x-loader/include/asm/arch-arm1136/omap2430.h +++ /dev/null @@ -1,255 +0,0 @@ -/* - * (C) Copyright 2004-2005 - * Texas Instruments, <www.ti.com> - * Richard Woodruff <r-woodruff2@ti.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _OMAP2430_SYS_H_ -#define _OMAP2430_SYS_H_ - -#include <asm/arch/sizes.h> - - -#define __raw_writeb(v,a) (*(volatile unsigned char *)(a) = (v)) -#define __raw_writew(v,a) (*(volatile unsigned short *)(a) = (v)) -#define __raw_writel(v,a) (*(volatile unsigned int *)(a) = (v)) - -#define __raw_readb(a) (*(volatile unsigned char *)(a)) -#define __raw_readw(a) (*(volatile unsigned short *)(a)) -#define __raw_readl(a) (*(volatile unsigned int *)(a)) - -/* device type */ -#define DEVICE_MASK (BIT8|BIT9|BIT10) -#define TST_DEVICE 0x0 -#define EMU_DEVICE 0x1 -#define HS_DEVICE 0x2 -#define GP_DEVICE 0x3 - -/* - * 2430 specific Section - */ -#define OMAP243X_CORE_L4_IO_BASE 0x48000000 -#define OMAP243X_WAKEUP_L4_IO_BASE 0x49000000 -#define OMAP24XX_L4_IO_BASE OMAP243X_CORE_L4_IO_BASE - - -/* CONTROL */ -#define OMAP24XX_CTRL_BASE (OMAP243X_WAKEUP_L4_IO_BASE+0x2000) -#define CONTROL_STATUS (OMAP24XX_CTRL_BASE + 0x2F8) - -/* TAP information */ -#define OMAP24XX_TAP_BASE (OMAP243X_WAKEUP_L4_IO_BASE+0xA000) -#define TAP_IDCODE_REG (OMAP24XX_TAP_BASE+0x204) - -/* - GPMC : In 2430 NOR and NAND can coexist. - During NAND booting , NAND is at CS0 and NOR at CS1 - and Debug FPGA is GPMC_CS5 -*/ -#define OMAP24XX_GPMC_BASE (0x6E000000) - -#define GPMC_SYSCONFIG (OMAP24XX_GPMC_BASE+0x10) -#define GPMC_SYSSTATUS (OMAP24XX_GPMC_BASE+0x14) -#define GPMC_IRQENABLE (OMAP24XX_GPMC_BASE+0x1C) -#define GPMC_TIMEOUT_CONTROL (OMAP24XX_GPMC_BASE+0x40) -#define GPMC_CONFIG (OMAP24XX_GPMC_BASE+0x50) -#define GPMC_CONFIG1_0 (OMAP24XX_GPMC_BASE+0x60) -#define GPMC_CONFIG2_0 (OMAP24XX_GPMC_BASE+0x64) -#define GPMC_CONFIG3_0 (OMAP24XX_GPMC_BASE+0x68) -#define GPMC_CONFIG4_0 (OMAP24XX_GPMC_BASE+0x6C) -#define GPMC_CONFIG5_0 (OMAP24XX_GPMC_BASE+0x70) -#define GPMC_CONFIG6_0 (OMAP24XX_GPMC_BASE+0x74) -#define GPMC_CONFIG7_0 (OMAP24XX_GPMC_BASE+0x78) -#define GPMC_CONFIG1_1 (OMAP24XX_GPMC_BASE+0x90) -#define GPMC_CONFIG2_1 (OMAP24XX_GPMC_BASE+0x94) -#define GPMC_CONFIG3_1 (OMAP24XX_GPMC_BASE+0x98) -#define GPMC_CONFIG4_1 (OMAP24XX_GPMC_BASE+0x9C) -#define GPMC_CONFIG5_1 (OMAP24XX_GPMC_BASE+0xA0) -#define GPMC_CONFIG6_1 (OMAP24XX_GPMC_BASE+0xA4) -#define GPMC_CONFIG7_1 (OMAP24XX_GPMC_BASE+0xA8) -#define GPMC_CONFIG1_5 (OMAP24XX_GPMC_BASE+0x150) -#define GPMC_CONFIG2_5 (OMAP24XX_GPMC_BASE+0x154) -#define GPMC_CONFIG3_5 (OMAP24XX_GPMC_BASE+0x158) -#define GPMC_CONFIG4_5 (OMAP24XX_GPMC_BASE+0x15C) -#define GPMC_CONFIG5_5 (OMAP24XX_GPMC_BASE+0x160) -#define GPMC_CONFIG6_5 (OMAP24XX_GPMC_BASE+0x164) -#define GPMC_CONFIG7_5 (OMAP24XX_GPMC_BASE+0x168) - - -/* SMS */ -#define OMAP24XX_SMS_BASE 0x6C000000 -#define SMS_SYSCONFIG (OMAP24XX_SMS_BASE+0x10) - -/* SDRC */ -#define OMAP24XX_SDRC_BASE 0x6D000000 -#define OMAP24XX_SDRC_CS0 0x80000000 -#define OMAP24XX_SDRC_CS1 0xA0000000 -#define SDRC_SYSCONFIG (OMAP24XX_SDRC_BASE+0x10) -#define SDRC_STATUS (OMAP24XX_SDRC_BASE+0x14) -#define SDRC_SHARING (OMAP24XX_SDRC_BASE+0x44) -#define SDRC_DLLA_CTRL (OMAP24XX_SDRC_BASE+0x60) -#define SDRC_DLLA_STATUS (OMAP24XX_SDRC_BASE+0x64) -#define SDRC_DLLB_CTRL (OMAP24XX_SDRC_BASE+0x68) -#define SDRC_POWER (OMAP24XX_SDRC_BASE+0x70) -#define SDRC_MCFG_0 (OMAP24XX_SDRC_BASE+0x80) -#define SDRC_MR_0 (OMAP24XX_SDRC_BASE+0x84) -#define SDRC_ACTIM_CTRLA_0 (OMAP24XX_SDRC_BASE+0x9C) -#define SDRC_ACTIM_CTRLB_0 (OMAP24XX_SDRC_BASE+0xA0) -#define SDRC_MCFG_1 (OMAP24XX_SDRC_BASE+0xB0) -#define SDRC_ACTIM_CTRLA_1 (OMAP24XX_SDRC_BASE+0xC4) -#define SDRC_ACTIM_CTRLB_1 (OMAP24XX_SDRC_BASE+0xC8) -#define SDRC_RFR_CTRL (OMAP24XX_SDRC_BASE+0xA4) -#define SDRC_MANUAL_0 (OMAP24XX_SDRC_BASE+0xA8) -#define SDRC_RFR_CTRL1 (OMAP24XX_SDRC_BASE+0xD4) - -#define LOADDLL BIT2 -#define CMD_NOP 0x0 -#define CMD_PRECHARGE 0x1 -#define CMD_AUTOREFRESH 0x2 -#define CMD_ENTR_PWRDOWN 0x3 -#define CMD_EXIT_PWRDOWN 0x4 -#define CMD_ENTR_SRFRSH 0x5 -#define CMD_CKE_HIGH 0x6 -#define CMD_CKE_LOW 0x7 -#define SOFTRESET BIT1 -#define SMART_IDLE (0x2 << 3) -#define REF_ON_IDLE (0x1 << 6) - - -/* UART */ -#define OMAP2430_UART1 0x4806A000 -#define OMAP2430_UART2 0x4806C000 -#define OMAP2430_UART3 0x4806E000 - -/* General Purpose Timers */ -#define OMAP24XX_GPT1 (OMAP243X_WAKEUP_L4_IO_BASE+0x18000) -#define OMAP24XX_GPT2 (OMAP24XX_L4_IO_BASE+0x2A000) -#define OMAP24XX_GPT3 (OMAP24XX_L4_IO_BASE+0x78000) -#define OMAP24XX_GPT4 (OMAP24XX_L4_IO_BASE+0x7A000) -#define OMAP24XX_GPT5 (OMAP24XX_L4_IO_BASE+0x7C000) -#define OMAP24XX_GPT6 (OMAP24XX_L4_IO_BASE+0x7E000) -#define OMAP24XX_GPT7 (OMAP24XX_L4_IO_BASE+0x80000) -#define OMAP24XX_GPT8 (OMAP24XX_L4_IO_BASE+0x82000) -#define OMAP24XX_GPT9 (OMAP24XX_L4_IO_BASE+0x84000) -#define OMAP24XX_GPT10 (OMAP24XX_L4_IO_BASE+0x86000) -#define OMAP24XX_GPT11 (OMAP24XX_L4_IO_BASE+0x88000) -#define OMAP24XX_GPT12 (OMAP24XX_L4_IO_BASE+0x8A000 - -/* timer regs offsets (32 bit regs) */ -#define TIDR 0x0 /* r */ -#define TIOCP_CFG 0x10 /* rw */ -#define TISTAT 0x14 /* r */ -#define TISR 0x18 /* rw */ -#define TIER 0x1C /* rw */ -#define TWER 0x20 /* rw */ -#define TCLR 0x24 /* rw */ -#define TCRR 0x28 /* rw */ -#define TLDR 0x2C /* rw */ -#define TTGR 0x30 /* rw */ -#define TWPS 0x34 /* r */ -#define TMAR 0x38 /* rw */ -#define TCAR1 0x3c /* r */ -#define TSICR 0x40 /* rw */ -#define TCAR2 0x44 /* r */ - -/* WatchDog Timers (1 secure, 3 GP) */ -#define WD1_BASE (OMAP243X_WAKEUP_L4_IO_BASE+0x14000) -#define WD2_BASE (OMAP243X_WAKEUP_L4_IO_BASE+0x16000) -#define WD3_BASE (OMAP24XX_L4_IO_BASE+0x24000) /* not present */ -#define WD4_BASE (OMAP24XX_L4_IO_BASE+0x26000) - -/* 32KTIMER */ -#define SYNC_32KTIMER_BASE (OMAP243X_WAKEUP_L4_IO_BASE+0x20000) -#define S32K_CR (SYNC_32KTIMER_BASE+0x10) - -#define WWPS 0x34 /* r */ -#define WSPR 0x48 /* rw */ -#define WD_UNLOCK1 0xAAAA -#define WD_UNLOCK2 0x5555 - -/* PRCM */ -#define OMAP24XX_CM_BASE (OMAP243X_WAKEUP_L4_IO_BASE+0x06000) - -#define PRCM_CLKSRC_CTRL (OMAP24XX_CM_BASE+0x060) -#define PRCM_CLKOUT_CTRL (OMAP24XX_CM_BASE+0x070) -#define PRCM_CLKEMUL_CTRL (OMAP24XX_CM_BASE+0x078) -#define PRCM_CLKCFG_CTRL (OMAP24XX_CM_BASE+0x080) -#define PRCM_CLKCFG_STATUS (OMAP24XX_CM_BASE+0x084) -#define CM_CLKSEL_MPU (OMAP24XX_CM_BASE+0x140) -#define CM_FCLKEN1_CORE (OMAP24XX_CM_BASE+0x200) -#define CM_FCLKEN2_CORE (OMAP24XX_CM_BASE+0x204) -#define CM_ICLKEN1_CORE (OMAP24XX_CM_BASE+0x210) -#define CM_ICLKEN2_CORE (OMAP24XX_CM_BASE+0x214) -#define CM_CLKSEL1_CORE (OMAP24XX_CM_BASE+0x240) -#define CM_CLKSEL_WKUP (OMAP24XX_CM_BASE+0x440) -#define CM_CLKSEL2_CORE (OMAP24XX_CM_BASE+0x244) -#define CM_FCLKEN_GFX (OMAP24XX_CM_BASE+0x300) -#define CM_ICLKEN_GFX (OMAP24XX_CM_BASE+0x310) -#define CM_CLKSEL_GFX (OMAP24XX_CM_BASE+0x340) -#define RM_RSTCTRL_GFX (OMAP24XX_CM_BASE+0x350) -#define CM_FCLKEN_WKUP (OMAP24XX_CM_BASE+0x400) -#define CM_ICLKEN_WKUP (OMAP24XX_CM_BASE+0x410) -#define PM_RSTCTRL_WKUP (OMAP24XX_CM_BASE+0x450) -#define CM_CLKEN_PLL (OMAP24XX_CM_BASE+0x500) -#define CM_IDLEST_CKGEN (OMAP24XX_CM_BASE+0x520) -#define CM_CLKSEL1_PLL (OMAP24XX_CM_BASE+0x540) -#define CM_CLKSEL2_PLL (OMAP24XX_CM_BASE+0x544) -#define CM_CLKSEL_DSP (OMAP24XX_CM_BASE+0x840) -#define CM_CLKSEL_MDM (OMAP24XX_CM_BASE+0xC40) - -/* SMX-APE */ -#define SMX_APE_BASE 0x68000000 -#define PM_RT_APE_BASE_ADDR_ARM (SMX_APE_BASE + 0x10000) -#define PM_GPMC_BASE_ADDR_ARM (SMX_APE_BASE + 0x12400) -#define PM_OCM_RAM_BASE_ADDR_ARM (SMX_APE_BASE + 0x12800) -#define PM_OCM_ROM_BASE_ADDR_ARM (SMX_APE_BASE + 0x12C00) - -/* IVA2 */ -#define PM_IVA2_BASE_ADDR_ARM (SMX_APE_BASE + 0x14000) - -/* - * The 2430's chip selects are programmable. The mask ROM - * does configure CS0 to 0x08000000 before dispatch. So, if - * you want your code to live below that address, you have to - * be prepared to jump though hoops, to reset the base address. - */ -#if defined(CONFIG_OMAP243X) - -/* GPMC */ -/* This is being used by the macros in mem.h. PHYS_FLASH_1 is defined to H4_CS0_BASE */ -# define H4_CS1_BASE 0x09000000 /* flash (64 Meg aligned) */ -#define CFG_FLASH_BASE H4_CS1_BASE -#define DEBUG_BASE 0x08000000 - -/* base address for indirect vectors (internal boot mode) */ -#define SRAM_OFFSET0 0x40000000 -#define SRAM_OFFSET1 0x00200000 -#define SRAM_OFFSET2 0x0000F800 -#define SRAM_VECT_CODE (SRAM_OFFSET0|SRAM_OFFSET1|SRAM_OFFSET2) - -#define LOW_LEVEL_SRAM_STACK 0x4020FFFC - -#define PERIFERAL_PORT_BASE 0x480FE003 - -#endif /* endif CONFIG_2430SDP */ - -#endif - diff --git a/x-loader/include/asm/arch-arm1136/sizes.h b/x-loader/include/asm/arch-arm1136/sizes.h deleted file mode 100644 index 3dddd8e..0000000 --- a/x-loader/include/asm/arch-arm1136/sizes.h +++ /dev/null @@ -1,50 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -/* Size defintions - * Copyright (C) ARM Limited 1998. All rights reserved. - */ - -#ifndef __sizes_h -#define __sizes_h 1 - -/* handy sizes */ -#define SZ_1K 0x00000400 -#define SZ_4K 0x00001000 -#define SZ_8K 0x00002000 -#define SZ_16K 0x00004000 -#define SZ_32K 0x00008000 -#define SZ_64K 0x00010000 -#define SZ_128K 0x00020000 -#define SZ_256K 0x00040000 -#define SZ_512K 0x00080000 - -#define SZ_1M 0x00100000 -#define SZ_2M 0x00200000 -#define SZ_4M 0x00400000 -#define SZ_8M 0x00800000 -#define SZ_16M 0x01000000 -#define SZ_31M 0x01F00000 -#define SZ_32M 0x02000000 -#define SZ_64M 0x04000000 -#define SZ_128M 0x08000000 -#define SZ_256M 0x10000000 -#define SZ_512M 0x20000000 - -#define SZ_1G 0x40000000 -#define SZ_2G 0x80000000 - -#endif /* __sizes_h */ - diff --git a/x-loader/include/asm/arch-arm1136/sys_info.h b/x-loader/include/asm/arch-arm1136/sys_info.h deleted file mode 100644 index 94a09cd..0000000 --- a/x-loader/include/asm/arch-arm1136/sys_info.h +++ /dev/null @@ -1,139 +0,0 @@ -/* - * Copyright 2005 (C) Texas Instruments, <www.ti.com> - * (C) Copyright 2004 - * Texas Instruments, <www.ti.com> - * Richard Woodruff <r-woodruff2@ti.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _OMAP24XX_SYS_INFO_H_ -#define _OMAP24XX_SYS_INFO_H_ - -#if 0 -typedef struct h4_system_data { - /* base board info */ - u32 base_b_rev; /* rev from base board i2c */ - /* cpu board info */ - u32 cpu_b_rev; /* rev from cpu board i2c */ - u32 cpu_b_mux; /* mux type on daughter board */ - u32 cpu_b_ddr_type; /* mem type */ - u32 cpu_b_ddr_speed; /* ddr speed rating */ - u32 cpu_b_switches; /* boot ctrl switch settings */ - /* cpu info */ - u32 cpu_type; /* type of cpu; 2420, 2422, 2430,...*/ - u32 cpu_rev; /* rev of given cpu; ES1, ES2,...*/ -} h4_sys_data; - -#endif - -#define XDR_POP 5 /* package on package part */ -#define SDR_DISCRETE 4 /* 128M memory SDR module*/ -#define DDR_STACKED 3 /* stacked part on 2422 */ -#define DDR_COMBO 2 /* combo part on cpu daughter card (menalaeus) */ -#define DDR_DISCRETE 1 /* 2x16 parts on daughter card */ - -#define DDR_100 100 /* type found on most mem d-boards */ -#define DDR_111 111 /* some combo parts */ -#define DDR_133 133 /* most combo, some mem d-boards */ -#define DDR_165 165 /* future parts */ - -#define CPU_2420 0x2420 -#define CPU_2422 0x2422 /* 2420 + 64M stacked */ -#define CPU_2423 0x2423 /* 2420 + 96M stacked */ -#define CPU_2430 0x2430 - -/* 242x real hardware: - * ES1 = rev 0 - * ES2 = rev 1 - * ES2.05 = rev 2 - * ES2.1 = rev 3 - * ES2.1.1 = rev 4 - */ - -/* 242x code defines: - * ES1 = 0+1 = 1 - * ES2 = 1+1 = 2 - * ES2.05 = 2+1 = 3 - * ES2.1 = 3+1 = 4 - * Es2.1.1 = 4+1 = 5 - */ -#define CPU_2422_ES1 1 -#define CPU_2422_ES2 2 -#define CPU_2422_ES2_05 3 -#define CPU_2422_ES2_1 4 -#define CPU_2422_ES2_1_1 5 - -#define CPU_2420_ES1 1 -#define CPU_2420_ES2 2 -#define CPU_2420_ES2_05 3 -#define CPU_2420_ES2_1 4 -#define CPU_2420_ES2_1_1 5 - -#define CPU_242X_ES1 1 -#define CPU_242X_ES2 2 -#define CPU_242X_ES2_05 3 -#define CPU_242X_ES2_1 4 -#define CPU_242X_ES2_1_1 5 - -#define CPU_2420_2422_ES1 1 -#define CPU_2420_2422_ES2_1 4 - -/* 243x real hardware: - * ES1 = rev 0 - * ES2 = rev 1 - * - * 243x code defines: - * ES1 = 0+1 = 1 - * ES2 = 1+1 = 2 - */ -#define CPU_2430_ES1 1 -#define CPU_2430_ES2 2 - -#ifdef VPOM2430 -# define CPU_2430_VIRTIO 3 -#else -# define CPU_2430_VIRTIO 1 -#endif -#define CPU_2430_ZEBU 0xD - -#define CPU_2420_CHIPID 0x0B5D9000 -#define CPU_2430_CHIPID 0x0B68A000 -#define CPU_24XX_ID_MASK 0x0FFFF000 -#define CPU_242X_REV_MASK 0xF0000000 -#define CPU_242X_PID_MASK 0x000F0000 - -#define BOARD_H4_MENELAUS 1 -#define BOARD_H4_SDP 2 -#define BOARD_H4_MENELAUS_HRP 3 -#define BOARD_SDP_2430 4 - -#define GPMC_MUXED 1 -#define GPMC_NONMUXED 0 - -#define TYPE_NAND 0x800 /* bit pos for nand in gpmc reg */ -#define TYPE_NOR 0x000 -#define TYPE_ONENAND 0x800 - -#define WIDTH_8BIT 0x0000 -#define WIDTH_16BIT 0x1000 /* bit pos for 16 bit in gpmc */ - -#define I2C_MENELAUS 0x72 /* i2c id for companion chip */ - -#endif diff --git a/x-loader/include/asm/arch-arm926ejs/sizes.h b/x-loader/include/asm/arch-arm926ejs/sizes.h deleted file mode 100644 index ef0b99b..0000000 --- a/x-loader/include/asm/arch-arm926ejs/sizes.h +++ /dev/null @@ -1,51 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA0 2111-1307 - * USA - */ -/* DO NOT EDIT!! - this file automatically generated - * from .s file by awk -f s2h.awk - */ -/* Size defintions - * Copyright (C) ARM Limited 1998. All rights reserved. - */ - -#ifndef __sizes_h -#define __sizes_h 1 - -/* handy sizes */ -#define SZ_1K 0x00000400 -#define SZ_4K 0x00001000 -#define SZ_8K 0x00002000 -#define SZ_16K 0x00004000 -#define SZ_64K 0x00010000 -#define SZ_128K 0x00020000 -#define SZ_256K 0x00040000 -#define SZ_512K 0x00080000 - -#define SZ_1M 0x00100000 -#define SZ_2M 0x00200000 -#define SZ_4M 0x00400000 -#define SZ_8M 0x00800000 -#define SZ_16M 0x01000000 -#define SZ_32M 0x02000000 -#define SZ_64M 0x04000000 -#define SZ_128M 0x08000000 -#define SZ_256M 0x10000000 -#define SZ_512M 0x20000000 - -#define SZ_1G 0x40000000 -#define SZ_2G 0x80000000 - -#endif /* __sizes_h */ diff --git a/x-loader/include/asm/arch-omap3/bits.h b/x-loader/include/asm/arch-omap3/bits.h deleted file mode 100644 index 8522335..0000000 --- a/x-loader/include/asm/arch-omap3/bits.h +++ /dev/null @@ -1,48 +0,0 @@ -/* bits.h - * Copyright (c) 2004 Texas Instruments - * - * This package is free software; you can redistribute it and/or - * modify it under the terms of the license found in the file - * named COPYING that should have accompanied this file. - * - * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED - * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. - */ -#ifndef __bits_h -#define __bits_h 1 - -#define BIT0 (1<<0) -#define BIT1 (1<<1) -#define BIT2 (1<<2) -#define BIT3 (1<<3) -#define BIT4 (1<<4) -#define BIT5 (1<<5) -#define BIT6 (1<<6) -#define BIT7 (1<<7) -#define BIT8 (1<<8) -#define BIT9 (1<<9) -#define BIT10 (1<<10) -#define BIT11 (1<<11) -#define BIT12 (1<<12) -#define BIT13 (1<<13) -#define BIT14 (1<<14) -#define BIT15 (1<<15) -#define BIT16 (1<<16) -#define BIT17 (1<<17) -#define BIT18 (1<<18) -#define BIT19 (1<<19) -#define BIT20 (1<<20) -#define BIT21 (1<<21) -#define BIT22 (1<<22) -#define BIT23 (1<<23) -#define BIT24 (1<<24) -#define BIT25 (1<<25) -#define BIT26 (1<<26) -#define BIT27 (1<<27) -#define BIT28 (1<<28) -#define BIT29 (1<<29) -#define BIT30 (1<<30) -#define BIT31 (1<<31) - -#endif diff --git a/x-loader/include/asm/arch-omap3/clocks.h b/x-loader/include/asm/arch-omap3/clocks.h deleted file mode 100644 index 4f93a96..0000000 --- a/x-loader/include/asm/arch-omap3/clocks.h +++ /dev/null @@ -1,48 +0,0 @@ -/* - * (C) Copyright 2006 - * Texas Instruments, <www.ti.com> - * Richard Woodruff <r-woodruff2@ti.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#ifndef _OMAP34XX_CLOCKS_H_ -#define _OMAP34XX_CLOCKS_H_ - -#define LDELAY 12000000 - -#define S12M 12000000 -#define S13M 13000000 -#define S19_2M 19200000 -#define S24M 24000000 -#define S26M 26000000 -#define S38_4M 38400000 - -#define FCK_IVA2_ON 0x00000001 -#define FCK_CORE1_ON 0x03fffe29 -#define ICK_CORE1_ON 0x3ffffffb -#define ICK_CORE2_ON 0x0000001f -#define FCK_WKUP_ON 0x000000e9 -#define ICK_WKUP_ON 0x0000003f -#define FCK_DSS_ON 0x00000005 -#define ICK_DSS_ON 0x00000001 -#define FCK_CAM_ON 0x00000001 -#define ICK_CAM_ON 0x00000001 -#define FCK_PER_ON 0x0003ffff -#define ICK_PER_ON 0x0003ffff - -#include <asm/arch/clocks343x.h> - -#endif diff --git a/x-loader/include/asm/arch-omap3/clocks343x.h b/x-loader/include/asm/arch-omap3/clocks343x.h deleted file mode 100644 index 7aedaa1..0000000 --- a/x-loader/include/asm/arch-omap3/clocks343x.h +++ /dev/null @@ -1,155 +0,0 @@ -/* - * (C) Copyright 2006 - * Texas Instruments, <www.ti.com> - * Richard Woodruff <r-woodruff2@ti.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#ifndef _OMAP343X_CLOCKS_H_ -#define _OMAP343X_CLOCKS_H_ - -#define PLL_STOP 1 /* PER & IVA */ -#define PLL_LOW_POWER_BYPASS 5 /* MPU, IVA & CORE */ -#define PLL_FAST_RELOCK_BYPASS 6 /* CORE */ -#define PLL_LOCK 7 /* MPU, IVA, CORE & PER */ - -/* The following configurations are OPP and SysClk value independant - * and hence are defined here. All the other DPLL related values are - * tabulated in lowlevel_init.S. - */ - -/* CORE DPLL */ -# define CORE_M3X2 2 /* 332MHz : CM_CLKSEL1_EMU */ -# define CORE_SSI_DIV 3 /* 221MHz : CM_CLKSEL_CORE */ -# define CORE_FUSB_DIV 2 /* 41.5MHz: */ -# define CORE_L4_DIV 2 /* 83MHz : L4 */ -# define CORE_L3_DIV 2 /* 166MHz : L3 {DDR} */ -# define GFX_DIV 2 /* 83MHz : CM_CLKSEL_GFX */ -# define WKUP_RSM 2 /* 41.5MHz: CM_CLKSEL_WKUP */ - -/* PER DPLL */ -# define PER_M6X2 3 /* 288MHz: CM_CLKSEL1_EMU */ -# define PER_M5X2 4 /* 216MHz: CM_CLKSEL_CAM */ -# define PER_M4X2 9 /* 96MHz : CM_CLKSEL_DSS-dss1 */ -# define PER_M3X2 16 /* 54MHz : CM_CLKSEL_DSS-tv */ - -# define CLSEL1_EMU_VAL ((CORE_M3X2 << 16) | (PER_M6X2 << 24) | (0x0a50)) - -#ifdef PRCM_CLK_CFG2_332MHZ -# define M_12 0xA6 -# define N_12 0x05 -# define FSEL_12 0x07 -# define M2_12 0x01 /* M3 of 2 */ - -# define M_12_ES1 0x19F -# define N_12_ES1 0x0E -# define FSL_12_ES1 0x03 -# define M2_12_ES1 0x1 /* M3 of 2 */ - -# define M_13 0x14C -# define N_13 0x0C -# define FSEL_13 0x03 -# define M2_13 0x01 /* M3 of 2 */ - -# define M_13_ES1 0x1B2 -# define N_13_ES1 0x10 -# define FSL_13_ES1 0x03 -# define M2_13_ES1 0x01 /* M3 of 2 */ - -# define M_19p2 0x19F -# define N_19p2 0x17 -# define FSEL_19p2 0x03 -# define M2_19p2 0x01 /* M3 of 2 */ - -# define M_19p2_ES1 0x19F -# define N_19p2_ES1 0x17 -# define FSL_19p2_ES1 0x03 -# define M2_19p2_ES1 0x01 /* M3 of 2 */ - -# define M_26 0xA6 -# define N_26 0x0C -# define FSEL_26 0x07 -# define M2_26 0x01 /* M3 of 2 */ - -# define M_26_ES1 0x1B2 -# define N_26_ES1 0x21 -# define FSL_26_ES1 0x03 -# define M2_26_ES1 0x01 /* M3 of 2 */ - -# define M_38p4 0x19F -# define N_38p4 0x2F -# define FSEL_38p4 0x03 -# define M2_38p4 0x01 /* M3 of 2 */ - -# define M_38p4_ES1 0x19F -# define N_38p4_ES1 0x2F -# define FSL_38p4_ES1 0x03 -# define M2_38p4_ES1 0x01 /* M3 of 2 */ - -#elif defined(PRCM_CLK_CFG2_266MHZ) -# define M_12 0x85 -# define N_12 0x05 -# define FSEL_12 0x07 -# define M2_12 0x02 /* M3 of 2 */ - -# define M_12_ES1 0x85 /* 0x10A */ -# define N_12_ES1 0x05 /* 0x05 */ -# define FSL_12_ES1 0x07 /* 0x7 */ -# define M2_12_ES1 0x2 /* 0x2 with an M3 of 4*/ - -# define M_13 0x10A -# define N_13 0x0C -# define FSEL_13 0x3 -# define M2_13 0x1 /* M3 of 2 */ - -# define M_13_ES1 0x10A /* 0x214 */ -# define N_13_ES1 0x0C /* 0xC */ -# define FSL_13_ES1 0x3 /* 0x3 */ -# define M2_13_ES1 0x1 /* 0x2 with an M3 of 4*/ - -# define M_19p2 0x115 -# define N_19p2 0x13 -# define FSEL_19p2 0x03 -# define M2_19p2 0x01 /* M3 of 2 */ - -# define M_19p2_ES1 0x115 /* 0x299 */ -# define N_19p2_ES1 0x13 /* 0x17 */ -# define FSL_19p2_ES1 0x03 /* 0x03 */ -# define M2_19p2_ES1 0x01 /* 0x2 with M3 of 4 */ - -# define M_26 0x85 -# define N_26 0x0C -# define FSEL_26 0x07 -# define M2_26 0x01 /* M3 of 2 */ - -# define M_26_ES1 0x85 /* 0x10A */ -# define N_26_ES1 0x0C /* 0xC */ -# define FSL_26_ES1 0x07 /* 0x7 */ -# define M2_26_ES1 0x01 /* 0x2 with an M3 of 4 */ - -# define M_38p4 0x11C -# define N_38p4 0x28 -# define FSEL_38p4 0x03 -# define M2_38p4 0x01 /* M3 of 2 */ - -# define M_38p4_ES1 0x11C /* 0x299 */ -# define N_38p4_ES1 0x28 /* 0x2f */ -# define FSL_38p4_ES1 0x03 /* 0x3 */ -# define M2_38p4_ES1 0x01 /* 0x2 with an M3 of 4*/ - - # endif - -#endif /* endif _OMAP343X_CLOCKS_H_ */ diff --git a/x-loader/include/asm/arch-omap3/cpu.h b/x-loader/include/asm/arch-omap3/cpu.h deleted file mode 100644 index 0828e73..0000000 --- a/x-loader/include/asm/arch-omap3/cpu.h +++ /dev/null @@ -1,257 +0,0 @@ -/* - * (C) Copyright 2006 - * Texas Instruments, <www.ti.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - */ - -#ifndef _OMAP34XX_CPU_H -#define _OMAP34XX_CPU_H -#include <asm/arch/omap3430.h> - -/* Register offsets of common modules */ -/* Control */ -#define CONTROL_STATUS (OMAP34XX_CTRL_BASE + 0x2F0) -#define OMAP34XX_MCR (OMAP34XX_CTRL_BASE + 0x8C) -#define CONTROL_SCALABLE_OMAP_STATUS (OMAP34XX_CTRL_BASE + 0x44C) -#define CONTROL_SCALABLE_OMAP_OCP (OMAP34XX_CTRL_BASE + 0x534) - - -/* Tap Information */ -#define TAP_IDCODE_REG (OMAP34XX_TAP_BASE+0x204) -#define PRODUCTION_ID (OMAP34XX_TAP_BASE+0x208) - -/* device type */ -#define DEVICE_MASK (BIT8|BIT9|BIT10) -#define TST_DEVICE 0x0 -#define EMU_DEVICE 0x1 -#define HS_DEVICE 0x2 -#define GP_DEVICE 0x3 - -/* We are not concerned with BIT5 as it only determines - * the prirotiy between memory or perpheral booting - */ -#define SYSBOOT_MASK (BIT0|BIT1|BIT2|BIT3|BIT4) - -/* GPMC CS3/cs4/cs6 not avaliable */ -#define GPMC_BASE (OMAP34XX_GPMC_BASE) -#define GPMC_SYSCONFIG (OMAP34XX_GPMC_BASE+0x10) -#define GPMC_IRQSTATUS (OMAP34XX_GPMC_BASE+0x18) -#define GPMC_IRQENABLE (OMAP34XX_GPMC_BASE+0x1C) -#define GPMC_TIMEOUT_CONTROL (OMAP34XX_GPMC_BASE+0x40) -#define GPMC_CONFIG (OMAP34XX_GPMC_BASE+0x50) -#define GPMC_STATUS (OMAP34XX_GPMC_BASE+0x54) - -#define GPMC_CONFIG_CS0 (OMAP34XX_GPMC_BASE+0x60) -#define GPMC_CONFIG_WIDTH (0x30) - -#define GPMC_CONFIG1 (0x00) -#define GPMC_CONFIG2 (0x04) -#define GPMC_CONFIG3 (0x08) -#define GPMC_CONFIG4 (0x0C) -#define GPMC_CONFIG5 (0x10) -#define GPMC_CONFIG6 (0x14) -#define GPMC_CONFIG7 (0x18) -#define GPMC_NAND_CMD (0x1C) -#define GPMC_NAND_ADR (0x20) -#define GPMC_NAND_DAT (0x24) - -#define GPMC_ECC_CONFIG (0x1F4) -#define GPMC_ECC_CONTROL (0x1F8) -#define GPMC_ECC_SIZE_CONFIG (0x1FC) -#define GPMC_ECC1_RESULT (0x200) -#define GPMC_ECC2_RESULT (0x204) -#define GPMC_ECC3_RESULT (0x208) -#define GPMC_ECC4_RESULT (0x20C) -#define GPMC_ECC5_RESULT (0x210) -#define GPMC_ECC6_RESULT (0x214) -#define GPMC_ECC7_RESULT (0x218) -#define GPMC_ECC8_RESULT (0x21C) -#define GPMC_ECC9_RESULT (0x220) - - -/* GPMC Mapping */ -# define FLASH_BASE 0x10000000 /* NOR flash (aligned to 256 Meg) */ -# define FLASH_BASE_SDPV1 0x04000000 /* NOR flash (aligned to 64 Meg) */ -# define FLASH_BASE_SDPV2 0x10000000 /* NOR flash (aligned to 256 Meg) */ -# define DEBUG_BASE 0x08000000 /* debug board */ -# define NAND_BASE 0x30000000 /* NAND addr (actual size small port)*/ -# define PISMO2_BASE 0x18000000 /* PISMO2 CS1/2 */ -# define ONENAND_MAP 0x20000000 /* OneNand addr (actual size small port */ - -/* SMS */ -#define SMS_SYSCONFIG (OMAP34XX_SMS_BASE+0x10) -#define SMS_RG_ATT0 (OMAP34XX_SMS_BASE+0x48) -#define SMS_CLASS_ARB0 (OMAP34XX_SMS_BASE+0xD0) -#define BURSTCOMPLETE_GROUP7 BIT31 - -/* SDRC */ -#define SDRC_SYSCONFIG (OMAP34XX_SDRC_BASE+0x10) -#define SDRC_STATUS (OMAP34XX_SDRC_BASE+0x14) -#define SDRC_CS_CFG (OMAP34XX_SDRC_BASE+0x40) -#define SDRC_SHARING (OMAP34XX_SDRC_BASE+0x44) -#define SDRC_DLLA_CTRL (OMAP34XX_SDRC_BASE+0x60) -#define SDRC_DLLA_STATUS (OMAP34XX_SDRC_BASE+0x64) -#define SDRC_DLLB_CTRL (OMAP34XX_SDRC_BASE+0x68) -#define SDRC_DLLB_STATUS (OMAP34XX_SDRC_BASE+0x6C) -#define DLLPHASE BIT1 -#define LOADDLL BIT2 -#define DLL_DELAY_MASK 0xFF00 -#define DLL_NO_FILTER_MASK (BIT8|BIT9) - -#define SDRC_POWER (OMAP34XX_SDRC_BASE+0x70) -#define WAKEUPPROC BIT26 - -#define SDRC_MCFG_0 (OMAP34XX_SDRC_BASE+0x80) -#define SDRC_MCFG_1 (OMAP34XX_SDRC_BASE+0xB0) -#define SDRC_MR_0 (OMAP34XX_SDRC_BASE+0x84) -#define SDRC_MR_1 (OMAP34XX_SDRC_BASE+0xB4) -#define SDRC_ACTIM_CTRLA_0 (OMAP34XX_SDRC_BASE+0x9C) -#define SDRC_ACTIM_CTRLB_0 (OMAP34XX_SDRC_BASE+0xA0) -#define SDRC_ACTIM_CTRLA_1 (OMAP34XX_SDRC_BASE+0xC4) -#define SDRC_ACTIM_CTRLB_1 (OMAP34XX_SDRC_BASE+0xC8) -#define SDRC_RFR_CTRL_0 (OMAP34XX_SDRC_BASE+0xA4) -#define SDRC_RFR_CTRL_1 (OMAP34XX_SDRC_BASE+0xD4) -#define SDRC_MANUAL_0 (OMAP34XX_SDRC_BASE+0xA8) -#define SDRC_MANUAL_1 (OMAP34XX_SDRC_BASE+0xD8) -#define OMAP34XX_SDRC_CS0 0x80000000 -#define OMAP34XX_SDRC_CS1 0xA0000000 -#define CMD_NOP 0x0 -#define CMD_PRECHARGE 0x1 -#define CMD_AUTOREFRESH 0x2 -#define CMD_ENTR_PWRDOWN 0x3 -#define CMD_EXIT_PWRDOWN 0x4 -#define CMD_ENTR_SRFRSH 0x5 -#define CMD_CKE_HIGH 0x6 -#define CMD_CKE_LOW 0x7 -#define SOFTRESET BIT1 -#define SMART_IDLE (0x2 << 3) -#define REF_ON_IDLE (0x1 << 6) - -/* timer regs offsets (32 bit regs) */ -#define TIDR 0x0 /* r */ -#define TIOCP_CFG 0x10 /* rw */ -#define TISTAT 0x14 /* r */ -#define TISR 0x18 /* rw */ -#define TIER 0x1C /* rw */ -#define TWER 0x20 /* rw */ -#define TCLR 0x24 /* rw */ -#define TCRR 0x28 /* rw */ -#define TLDR 0x2C /* rw */ -#define TTGR 0x30 /* rw */ -#define TWPS 0x34 /* r */ -#define TMAR 0x38 /* rw */ -#define TCAR1 0x3c /* r */ -#define TSICR 0x40 /* rw */ -#define TCAR2 0x44 /* r */ -#define GPT_EN ((0<<2)|BIT1|BIT0) /* enable sys_clk NO-prescale /1 */ - -/* Watchdog */ -#define WWPS 0x34 /* r */ -#define WSPR 0x48 /* rw */ -#define WD_UNLOCK1 0xAAAA -#define WD_UNLOCK2 0x5555 - -/* PRCM */ -#define CM_FCLKEN_IVA2 0x48004000 -#define CM_CLKEN_PLL_IVA2 0x48004004 -#define CM_IDLEST_PLL_IVA2 0x48004024 -#define CM_CLKSEL1_PLL_IVA2 0x48004040 -#define CM_CLKSEL2_PLL_IVA2 0x48004044 -#define CM_CLKEN_PLL_MPU 0x48004904 -#define CM_IDLEST_PLL_MPU 0x48004924 -#define CM_CLKSEL1_PLL_MPU 0x48004940 -#define CM_CLKSEL2_PLL_MPU 0x48004944 -#define CM_FCLKEN1_CORE 0x48004a00 -#define CM_ICLKEN1_CORE 0x48004a10 -#define CM_ICLKEN2_CORE 0x48004a14 -#define CM_CLKSEL_CORE 0x48004a40 -#define CM_FCLKEN_GFX 0x48004b00 -#define CM_ICLKEN_GFX 0x48004b10 -#define CM_CLKSEL_GFX 0x48004b40 -#define CM_FCLKEN_WKUP 0x48004c00 -#define CM_ICLKEN_WKUP 0x48004c10 -#define CM_CLKSEL_WKUP 0x48004c40 -#define CM_IDLEST_WKUP 0x48004c20 -#define CM_CLKEN_PLL 0x48004d00 -#define CM_IDLEST_CKGEN 0x48004d20 -#define CM_CLKSEL1_PLL 0x48004d40 -#define CM_CLKSEL2_PLL 0x48004d44 -#define CM_CLKSEL3_PLL 0x48004d48 -#define CM_FCLKEN_DSS 0x48004e00 -#define CM_ICLKEN_DSS 0x48004e10 -#define CM_CLKSEL_DSS 0x48004e40 -#define CM_FCLKEN_CAM 0x48004f00 -#define CM_ICLKEN_CAM 0x48004f10 -#define CM_CLKSEL_CAM 0x48004F40 -#define CM_FCLKEN_PER 0x48005000 -#define CM_ICLKEN_PER 0x48005010 -#define CM_CLKSEL_PER 0x48005040 -#define CM_CLKSEL1_EMU 0x48005140 - -#define PRM_CLKSEL 0x48306d40 -#define PRM_RSTCTRL 0x48307250 -#define PRM_CLKSRC_CTRL 0x48307270 - -#define SYSCLKDIV_2 (0x1 << 7) - -/* SMX-APE */ -#define PM_RT_APE_BASE_ADDR_ARM (SMX_APE_BASE + 0x10000) -#define PM_GPMC_BASE_ADDR_ARM (SMX_APE_BASE + 0x12400) -#define PM_OCM_RAM_BASE_ADDR_ARM (SMX_APE_BASE + 0x12800) -#define PM_OCM_ROM_BASE_ADDR_ARM (SMX_APE_BASE + 0x12C00) -#define PM_IVA2_BASE_ADDR_ARM (SMX_APE_BASE + 0x14000) - -#define RT_REQ_INFO_PERMISSION_1 (PM_RT_APE_BASE_ADDR_ARM + 0x68) -#define RT_READ_PERMISSION_0 (PM_RT_APE_BASE_ADDR_ARM + 0x50) -#define RT_WRITE_PERMISSION_0 (PM_RT_APE_BASE_ADDR_ARM + 0x58) -#define RT_ADDR_MATCH_1 (PM_RT_APE_BASE_ADDR_ARM + 0x60) - -#define GPMC_REQ_INFO_PERMISSION_0 (PM_GPMC_BASE_ADDR_ARM + 0x48) -#define GPMC_READ_PERMISSION_0 (PM_GPMC_BASE_ADDR_ARM + 0x50) -#define GPMC_WRITE_PERMISSION_0 (PM_GPMC_BASE_ADDR_ARM + 0x58) - -#define OCM_REQ_INFO_PERMISSION_0 (PM_OCM_RAM_BASE_ADDR_ARM + 0x48) -#define OCM_READ_PERMISSION_0 (PM_OCM_RAM_BASE_ADDR_ARM + 0x50) -#define OCM_WRITE_PERMISSION_0 (PM_OCM_RAM_BASE_ADDR_ARM + 0x58) -#define OCM_ADDR_MATCH_2 (PM_OCM_RAM_BASE_ADDR_ARM + 0x80) - -#define IVA2_REQ_INFO_PERMISSION_0 (PM_IVA2_BASE_ADDR_ARM + 0x48) -#define IVA2_READ_PERMISSION_0 (PM_IVA2_BASE_ADDR_ARM + 0x50) -#define IVA2_WRITE_PERMISSION_0 (PM_IVA2_BASE_ADDR_ARM + 0x58) - -#define IVA2_REQ_INFO_PERMISSION_1 (PM_IVA2_BASE_ADDR_ARM + 0x68) -#define IVA2_READ_PERMISSION_1 (PM_IVA2_BASE_ADDR_ARM + 0x70) -#define IVA2_WRITE_PERMISSION_1 (PM_IVA2_BASE_ADDR_ARM + 0x78) - -#define IVA2_REQ_INFO_PERMISSION_2 (PM_IVA2_BASE_ADDR_ARM + 0x88) -#define IVA2_READ_PERMISSION_2 (PM_IVA2_BASE_ADDR_ARM + 0x90) -#define IVA2_WRITE_PERMISSION_2 (PM_IVA2_BASE_ADDR_ARM + 0x98) - -#define IVA2_REQ_INFO_PERMISSION_3 (PM_IVA2_BASE_ADDR_ARM + 0xA8) -#define IVA2_READ_PERMISSION_3 (PM_IVA2_BASE_ADDR_ARM + 0xB0) -#define IVA2_WRITE_PERMISSION_3 (PM_IVA2_BASE_ADDR_ARM + 0xB8) - -/* I2C base */ -#define I2C_BASE1 (OMAP34XX_CORE_L4_IO_BASE + 0x70000) -#define I2C_BASE2 (OMAP34XX_CORE_L4_IO_BASE + 0x72000) -#define I2C_BASE3 (OMAP34XX_CORE_L4_IO_BASE + 0x60000) - -#endif diff --git a/x-loader/include/asm/arch-omap3/gpio.h b/x-loader/include/asm/arch-omap3/gpio.h deleted file mode 100644 index 30f633c..0000000 --- a/x-loader/include/asm/arch-omap3/gpio.h +++ /dev/null @@ -1,86 +0,0 @@ -/* - * Copyright (c) 2009 Wind River Systems, Inc. - * Tom Rix <Tom.Rix@windriver.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - * This work is derived from the linux 2.6.27 kernel source - * To fetch, use the kernel repository - * git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6.git - * Use the v2.6.27 tag. - * - * Below is the original's header including its copyright - * - * linux/arch/arm/plat-omap/gpio.c - * - * Support functions for OMAP GPIO - * - * Copyright (C) 2003-2005 Nokia Corporation - * Written by Juha Yrjölä <juha.yrjola@nokia.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#ifndef _GPIO_H -#define _GPIO_H - -#define OMAP24XX_GPIO_REVISION 0x0000 -#define OMAP24XX_GPIO_SYSCONFIG 0x0010 -#define OMAP24XX_GPIO_SYSSTATUS 0x0014 -#define OMAP24XX_GPIO_IRQSTATUS1 0x0018 -#define OMAP24XX_GPIO_IRQSTATUS2 0x0028 -#define OMAP24XX_GPIO_IRQENABLE2 0x002c -#define OMAP24XX_GPIO_IRQENABLE1 0x001c -#define OMAP24XX_GPIO_WAKE_EN 0x0020 -#define OMAP24XX_GPIO_CTRL 0x0030 -#define OMAP24XX_GPIO_OE 0x0034 -#define OMAP24XX_GPIO_DATAIN 0x0038 -#define OMAP24XX_GPIO_DATAOUT 0x003c -#define OMAP24XX_GPIO_LEVELDETECT0 0x0040 -#define OMAP24XX_GPIO_LEVELDETECT1 0x0044 -#define OMAP24XX_GPIO_RISINGDETECT 0x0048 -#define OMAP24XX_GPIO_FALLINGDETECT 0x004c -#define OMAP24XX_GPIO_DEBOUNCE_EN 0x0050 -#define OMAP24XX_GPIO_DEBOUNCE_VAL 0x0054 -#define OMAP24XX_GPIO_CLEARIRQENABLE1 0x0060 -#define OMAP24XX_GPIO_SETIRQENABLE1 0x0064 -#define OMAP24XX_GPIO_CLEARWKUENA 0x0080 -#define OMAP24XX_GPIO_SETWKUENA 0x0084 -#define OMAP24XX_GPIO_CLEARDATAOUT 0x0090 -#define OMAP24XX_GPIO_SETDATAOUT 0x0094 - -struct gpio_bank { - void *base; - int method; -}; - -#define METHOD_GPIO_24XX 4 - -/* This is the interface */ - -/* Request a gpio before using it */ -int omap_request_gpio(int gpio); -/* Reset and free a gpio after using it */ -void omap_free_gpio(int gpio); -/* Sets the gpio as input or output */ -void omap_set_gpio_direction(int gpio, int is_input); -/* Set or clear a gpio output */ -void omap_set_gpio_dataout(int gpio, int enable); -/* Get the value of a gpio input */ -int omap_get_gpio_datain(int gpio); - -#endif /* _GPIO_H_ */ diff --git a/x-loader/include/asm/arch-omap3/i2c.h b/x-loader/include/asm/arch-omap3/i2c.h deleted file mode 100644 index 28ae5ca..0000000 --- a/x-loader/include/asm/arch-omap3/i2c.h +++ /dev/null @@ -1,128 +0,0 @@ -/* - * (C) Copyright 2004-2008 - * Texas Instruments, <www.ti.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#ifndef _I2C_H_ -#define _I2C_H_ - -#define I2C_DEFAULT_BASE I2C_BASE1 - -#define I2C_REV (I2C_DEFAULT_BASE + 0x00) -#define I2C_IE (I2C_DEFAULT_BASE + 0x04) -#define I2C_STAT (I2C_DEFAULT_BASE + 0x08) -#define I2C_IV (I2C_DEFAULT_BASE + 0x0c) -#define I2C_BUF (I2C_DEFAULT_BASE + 0x14) -#define I2C_CNT (I2C_DEFAULT_BASE + 0x18) -#define I2C_DATA (I2C_DEFAULT_BASE + 0x1c) -#define I2C_SYSC (I2C_DEFAULT_BASE + 0x20) -#define I2C_CON (I2C_DEFAULT_BASE + 0x24) -#define I2C_OA (I2C_DEFAULT_BASE + 0x28) -#define I2C_SA (I2C_DEFAULT_BASE + 0x2c) -#define I2C_PSC (I2C_DEFAULT_BASE + 0x30) -#define I2C_SCLL (I2C_DEFAULT_BASE + 0x34) -#define I2C_SCLH (I2C_DEFAULT_BASE + 0x38) -#define I2C_SYSTEST (I2C_DEFAULT_BASE + 0x3c) - -/* I2C masks */ - -/* I2C Interrupt Enable Register (I2C_IE): */ -#define I2C_IE_GC_IE (1 << 5) -#define I2C_IE_XRDY_IE (1 << 4) /* Transmit data ready interrupt enable */ -#define I2C_IE_RRDY_IE (1 << 3) /* Receive data ready interrupt enable */ -#define I2C_IE_ARDY_IE (1 << 2) /* Register access ready interrupt enable */ -#define I2C_IE_NACK_IE (1 << 1) /* No acknowledgment interrupt enable */ -#define I2C_IE_AL_IE (1 << 0) /* Arbitration lost interrupt enable */ - -/* I2C Status Register (I2C_STAT): */ - -#define I2C_STAT_SBD (1 << 15) /* Single byte data */ -#define I2C_STAT_BB (1 << 12) /* Bus busy */ -#define I2C_STAT_ROVR (1 << 11) /* Receive overrun */ -#define I2C_STAT_XUDF (1 << 10) /* Transmit underflow */ -#define I2C_STAT_AAS (1 << 9) /* Address as slave */ -#define I2C_STAT_GC (1 << 5) -#define I2C_STAT_XRDY (1 << 4) /* Transmit data ready */ -#define I2C_STAT_RRDY (1 << 3) /* Receive data ready */ -#define I2C_STAT_ARDY (1 << 2) /* Register access ready */ -#define I2C_STAT_NACK (1 << 1) /* No acknowledgment interrupt enable */ -#define I2C_STAT_AL (1 << 0) /* Arbitration lost interrupt enable */ - -/* I2C Interrupt Code Register (I2C_INTCODE): */ - -#define I2C_INTCODE_MASK 7 -#define I2C_INTCODE_NONE 0 -#define I2C_INTCODE_AL 1 /* Arbitration lost */ -#define I2C_INTCODE_NAK 2 /* No acknowledgement/general call */ -#define I2C_INTCODE_ARDY 3 /* Register access ready */ -#define I2C_INTCODE_RRDY 4 /* Rcv data ready */ -#define I2C_INTCODE_XRDY 5 /* Xmit data ready */ - -/* I2C Buffer Configuration Register (I2C_BUF): */ - -#define I2C_BUF_RDMA_EN (1 << 15) /* Receive DMA channel enable */ -#define I2C_BUF_XDMA_EN (1 << 7) /* Transmit DMA channel enable */ - -/* I2C Configuration Register (I2C_CON): */ - -#define I2C_CON_EN (1 << 15) /* I2C module enable */ -#define I2C_CON_BE (1 << 14) /* Big endian mode */ -#define I2C_CON_STB (1 << 11) /* Start byte mode (master mode only) */ -#define I2C_CON_MST (1 << 10) /* Master/slave mode */ -#define I2C_CON_TRX (1 << 9) /* Transmitter/receiver mode */ - /* (master mode only) */ -#define I2C_CON_XA (1 << 8) /* Expand address */ -#define I2C_CON_STP (1 << 1) /* Stop condition (master mode only) */ -#define I2C_CON_STT (1 << 0) /* Start condition (master mode only) */ - -/* I2C System Test Register (I2C_SYSTEST): */ - -#define I2C_SYSTEST_ST_EN (1 << 15) /* System test enable */ -#define I2C_SYSTEST_FREE (1 << 14) /* Free running mode, on brkpoint) */ -#define I2C_SYSTEST_TMODE_MASK (3 << 12) /* Test mode select */ -#define I2C_SYSTEST_TMODE_SHIFT (12) /* Test mode select */ -#define I2C_SYSTEST_SCL_I (1 << 3) /* SCL line sense input value */ -#define I2C_SYSTEST_SCL_O (1 << 2) /* SCL line drive output value */ -#define I2C_SYSTEST_SDA_I (1 << 1) /* SDA line sense input value */ -#define I2C_SYSTEST_SDA_O (1 << 0) /* SDA line drive output value */ - -#define I2C_SCLL_SCLL (0) -#define I2C_SCLL_SCLL_M (0xFF) -#define I2C_SCLL_HSSCLL (8) -#define I2C_SCLH_HSSCLL_M (0xFF) -#define I2C_SCLH_SCLH (0) -#define I2C_SCLH_SCLH_M (0xFF) -#define I2C_SCLH_HSSCLH (8) -#define I2C_SCLH_HSSCLH_M (0xFF) - -#define OMAP_I2C_STANDARD 100 -#define OMAP_I2C_FAST_MODE 400 -#define OMAP_I2C_HIGH_SPEED 3400 - -#define SYSTEM_CLOCK_12 12000 -#define SYSTEM_CLOCK_13 13000 -#define SYSTEM_CLOCK_192 19200 -#define SYSTEM_CLOCK_96 96000 - -#define I2C_IP_CLK SYSTEM_CLOCK_96 -#define I2C_PSC_MAX (0x0f) -#define I2C_PSC_MIN (0x00) - -#endif /* _I2C_H_ */ diff --git a/x-loader/include/asm/arch-omap3/mem.h b/x-loader/include/asm/arch-omap3/mem.h deleted file mode 100644 index 284c665..0000000 --- a/x-loader/include/asm/arch-omap3/mem.h +++ /dev/null @@ -1,589 +0,0 @@ -/* - * (C) Copyright 2006 - * Texas Instruments, <www.ti.com> - * Richard Woodruff <r-woodruff2@ti.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _OMAP34XX_MEM_H_ -#define _OMAP34XX_MEM_H_ - -#define SDRC_CS0_OSET 0x0 -#define SDRC_CS1_OSET 0x30 /* mirror CS1 regs appear offset 0x30 from CS0 */ - -#ifndef __ASSEMBLY__ - -typedef enum { - STACKED = 0, - IP_DDR = 1, - COMBO_DDR = 2, - IP_SDR = 3, -} mem_t; - - -/* Memory that can be connected to GPMC */ -#define GPMC_NOR 0 -#define GPMC_NAND 1 -#define GPMC_MDOC 2 -#define GPMC_ONENAND 3 -#define MMC_NAND 4 -#define MMC_ONENAND 5 -#define GPMC_NONE 6 -#define GPMC_ONENAND_TRY 7 - -#endif - -/* set the 343x-SDRC incoming address convention */ -#if defined(SDRC_B_R_C) -#define B_ALL (0 << 6) /* bank-row-column */ -#elif defined(SDRC_B1_R_B0_C) -#define B_ALL (1 << 6) /* bank1-row-bank0-column */ -#elif defined(SDRC_R_B_C) -#define B_ALL (2 << 6) /* row-bank-column */ -#endif - -/* Future memory combinations based on past */ -#define SDP_SDRC_MDCFG_MONO_DDR 0x0 -#define SDP_COMBO_MDCFG_0_DDR 0x0 -#define SDP_SDRC_MDCFG_0_SDR 0x0 - -/* Slower full frequency range default timings for x32 operation*/ -#define SDP_SDRC_SHARING 0x00000100 -#define SDP_SDRC_MR_0_SDR 0x00000031 - -#ifdef CONFIG_3430ZEBU -#define SDP_SDRC_MDCFG_0_DDR (0x02582019|B_ALL) /* Infin ddr module */ -#else -#define SDP_SDRC_MDCFG_0_DDR (0x02584019|B_ALL) -#define SDP_SDRC_MDCFG_0_DDR_MICRON_XM (0x03588019|B_ALL) -#define SDP_SDRC_MDCFG_0_DDR_NUMONYX_XM (0x04590019|B_ALL) -#define SDP_SDRC_MDCFG_0_DDR_HYNIX (0x03588019|B_ALL) -#endif - -#define SDP_SDRC_MR_0_DDR 0x00000032 - -/* Diabling power down mode using CKE pin */ -#define SDP_SDRC_POWER_POP 0x00000081 - -/* optimized timings good for current shipping parts */ -#define SDP_3430_SDRC_RFR_CTRL_100MHz 0x0002da01 -#define SDP_3430_SDRC_RFR_CTRL_133MHz 0x0003de01 /* 7.8us/7.5ns - 50=0x3de */ -#define SDP_3430_SDRC_RFR_CTRL_165MHz 0x0004e201 /* 7.8us/6ns - 50=0x4e2 */ -#define SDP_3430_SDRC_RFR_CTRL_200MHz 0x0005e601 /* 7.8us/5ns - 50=0x5e6 */ - -#define DLL_OFFSET 0 -#define DLL_WRITEDDRCLKX2DIS 1 -#define DLL_ENADLL 1 -#define DLL_LOCKDLL 0 -#define DLL_DLLPHASE_72 0 -#define DLL_DLLPHASE_90 1 - -// rkw - need to find of 90/72 degree recommendation for speed like before. -#define SDP_SDRC_DLLAB_CTRL ((DLL_ENADLL << 3) | \ - (DLL_LOCKDLL << 2) | (DLL_DLLPHASE_90 << 1)) - -/* Infineon part of 3430SDP (133MHz optimized) ~ 7.5ns - * TDAL = Twr/Tck + Trp/tck = 15/7.5 + 22.5/7.5 = 2 + 3 = 5 - * TDPL = 15/7.5 = 2 - * TRRD = 15/2.5 = 2 - * TRCD = 22.5/7.5 = 3 - * TRP = 22.5/7.5 = 3 - * TRAS = 45/7.5 = 6 - * TRC = 65/7.5 = 8.6->9 - * TRFC = 75/7.5 = 10 - * ACTIMB - * TCKE = 2 - * XSR = 120/7.5 = 16 - */ -#define INFINEON_TDAL_133 5 -#define INFINEON_TDPL_133 2 -#define INFINEON_TRRD_133 2 -#define INFINEON_TRCD_133 3 -#define INFINEON_TRP_133 3 -#define INFINEON_TRAS_133 6 -#define INFINEON_TRC_133 9 -#define INFINEON_TRFC_133 10 -#define INFINEON_V_ACTIMA_133 ((INFINEON_TRFC_133 << 27) | (INFINEON_TRC_133 << 22) | (INFINEON_TRAS_133 << 18) \ - |(INFINEON_TRP_133 << 15) | (INFINEON_TRCD_133 << 12) |(INFINEON_TRRD_133 << 9) |(INFINEON_TDPL_133 << 6) \ - | (INFINEON_TDAL_133)) - -#define INFINEON_TWTR_133 1 -#define INFINEON_TCKE_133 2 -#define INFINEON_TXP_133 2 -#define INFINEON_XSR_133 16 -#define INFINEON_V_ACTIMB_133 ((INFINEON_TCKE_133 << 12) | (INFINEON_XSR_133 << 0)) | \ - (INFINEON_TXP_133 << 8) | (INFINEON_TWTR_133 << 16) - -#define INFINEON_V_ACTIMA_100 INFINEON_V_ACTIMA_133 -#define INFINEON_V_ACTIMB_100 INFINEON_V_ACTIMB_133 - - -/* Infineon part of 3430SDP (165MHz optimized) 6.06ns - * ACTIMA - * TDAL = Twr/Tck + Trp/tck = 15/6 + 18/6 = 2.5 + 3 = 5.5 -> 6 - * TDPL (Twr) = 15/6 = 2.5 -> 3 - * TRRD = 12/6 = 2 - * TRCD = 18/6 = 3 - * TRP = 18/6 = 3 - * TRAS = 42/6 = 7 - * TRC = 60/6 = 10 - * TRFC = 72/6 = 12 - * ACTIMB - * TCKE = 2 - * XSR = 120/6 = 20 - */ -#define INFINEON_TDAL_165 6 -#define INFINEON_TDPL_165 3 -#define INFINEON_TRRD_165 2 -#define INFINEON_TRCD_165 3 -#define INFINEON_TRP_165 3 -#define INFINEON_TRAS_165 7 -#define INFINEON_TRC_165 10 -#define INFINEON_TRFC_165 12 -#define INFINEON_V_ACTIMA_165 ((INFINEON_TRFC_165 << 27) | (INFINEON_TRC_165 << 22) | (INFINEON_TRAS_165 << 18) \ - | (INFINEON_TRP_165 << 15) | (INFINEON_TRCD_165 << 12) |(INFINEON_TRRD_165 << 9) | \ - (INFINEON_TDPL_165 << 6) | (INFINEON_TDAL_165)) - -#define INFINEON_TWTR_165 1 -#define INFINEON_TCKE_165 2 -#define INFINEON_TXP_165 2 -#define INFINEON_XSR_165 20 -#define INFINEON_V_ACTIMB_165 ((INFINEON_TCKE_165 << 12) | (INFINEON_XSR_165 << 0)) | \ - (INFINEON_TXP_165 << 8) | (INFINEON_TWTR_165 << 16) - -/* Micron part of 3430 EVM (133MHz optimized) ~ 7.5ns - * TDAL = Twr/Tck + Trp/tck = 15/7.5 + 22.5/7.5 = 2 + 3 = 5 - * TDPL = 15/7.5 = 2 - * TRRD = 15/7.5 = 2 - * TRCD = 22.5/7.5 = 3 - * TRP = 22.5/7.5 = 3 - * TRAS = 45/7.5 = 6 - * TRC = 75/7.5 = 10 - * TRFC = 125/7.5 = 16.6->17 - * ACTIMB - * TWTR = 1 - * TCKE = 1 - * TXSR = 138/7.5 = 18.3->19 - * TXP = 25/7.5 = 3.3->4 - */ -#define MICRON_TDAL_133 5 -#define MICRON_TDPL_133 2 -#define MICRON_TRRD_133 2 -#define MICRON_TRCD_133 3 -#define MICRON_TRP_133 3 -#define MICRON_TRAS_133 6 -#define MICRON_TRC_133 10 -#define MICRON_TRFC_133 17 -#define MICRON_V_ACTIMA_133 ((MICRON_TRFC_133 << 27) | (MICRON_TRC_133 << 22) | (MICRON_TRAS_133 << 18) \ - |(MICRON_TRP_133 << 15) | (MICRON_TRCD_133 << 12) |(MICRON_TRRD_133 << 9) |(MICRON_TDPL_133 << 6) \ - | (MICRON_TDAL_133)) - -#define MICRON_TWTR_133 1 -#define MICRON_TCKE_133 1 -#define MICRON_TXSR_133 19 -#define MICRON_TXP_133 4 -#define MICRON_V_ACTIMB_133 ((MICRON_TWTR_133 << 16) | (MICRON_TCKE_133 << 12) | (MICRON_TXP_133 << 8) \ - | (MICRON_TXSR_133 << 0)) - -#define MICRON_V_ACTIMA_100 MICRON_V_ACTIMA_133 -#define MICRON_V_ACTIMB_100 MICRON_V_ACTIMB_133 - -/* Micron part of 3430 EVM (165MHz optimized) 6.06ns - * ACTIMA - * TDAL = Twr/Tck + Trp/tck = 15/6 + 18 /6 = 2.5 + 3 = 5.5 -> 6 - * TDPL (Twr) = 15/6 = 2.5 -> 3 - * TRRD = 12/6 = 2 - * TRCD = 18/6 = 3 - * TRP = 18/6 = 3 - * TRAS = 42/6 = 7 - * TRC = 60/6 = 10 - * TRFC = 125/6 = 21 - * ACTIMB - * TWTR = 1 - * TCKE = 1 - * TXSR = 138/6 = 23 - * TXP = 25/6 = 4.1 ~5 - */ -#define MICRON_TDAL_165 6 -#define MICRON_TDPL_165 3 -#define MICRON_TRRD_165 2 -#define MICRON_TRCD_165 3 -#define MICRON_TRP_165 3 -#define MICRON_TRAS_165 7 -#define MICRON_TRC_165 10 -#define MICRON_TRFC_165 21 -#define MICRON_V_ACTIMA_165 ((MICRON_TRFC_165 << 27) | (MICRON_TRC_165 << 22) | (MICRON_TRAS_165 << 18) \ - | (MICRON_TRP_165 << 15) | (MICRON_TRCD_165 << 12) |(MICRON_TRRD_165 << 9) | \ - (MICRON_TDPL_165 << 6) | (MICRON_TDAL_165)) - -#define MICRON_TWTR_165 1 -#define MICRON_TCKE_165 1 -#define MICRON_TXP_165 5 -#define MICRON_XSR_165 23 -#define MICRON_V_ACTIMB_165 ((MICRON_TCKE_165 << 12) | (MICRON_XSR_165 << 0)) | \ - (MICRON_TXP_165 << 8) | (MICRON_TWTR_165 << 16) - -/* Micron part (200MHz optimized) 5 ns - */ -#define MICRON_TDAL_200 6 -#define MICRON_TDPL_200 3 -#define MICRON_TRRD_200 2 -#define MICRON_TRCD_200 3 -#define MICRON_TRP_200 3 -#define MICRON_TRAS_200 8 -#define MICRON_TRC_200 11 -#define MICRON_TRFC_200 15 -#define MICRON_V_ACTIMA_200 ((MICRON_TRFC_200 << 27) | (MICRON_TRC_200 << 22) | (MICRON_TRAS_200 << 18) \ - | (MICRON_TRP_200 << 15) | (MICRON_TRCD_200 << 12) |(MICRON_TRRD_200 << 9) | \ - (MICRON_TDPL_200 << 6) | (MICRON_TDAL_200)) - -#define MICRON_TWTR_200 2 -#define MICRON_TCKE_200 4 -#define MICRON_TXP_200 2 -#define MICRON_XSR_200 23 -#define MICRON_V_ACTIMB_200 ((MICRON_TCKE_200 << 12) | (MICRON_XSR_200 << 0)) | \ - (MICRON_TXP_200 << 8) | (MICRON_TWTR_200 << 16) - -/* NUMONYX part of IGEP0020 (165MHz optimized) 6.06ns - * ACTIMA - * TDAL = Twr/Tck + Trp/tck = 15/6 + 18/6 = 2.5 + 3 = 5.5 -> 6 - * TDPL (Twr) = 15/6 = 2.5 -> 3 - * TRRD = 12/6 = 2 - * TRCD = 22.5/6 = 3.75 -> 4 - * TRP = 18/6 = 3 - * TRAS = 42/6 = 7 - * TRC = 60/6 = 10 - * TRFC = 140/6 = 23.3 -> 24 - * ACTIMB - * TWTR = 2 - * TCKE = 2 - * TXSR = 200/6 = 33.3 -> 34 - * TXP = 1.0 + 1.1 = 2.1 -> 3 ¿? - */ -#define NUMONYX_TDAL_165 6 -#define NUMONYX_TDPL_165 3 -#define NUMONYX_TRRD_165 2 -#define NUMONYX_TRCD_165 4 -#define NUMONYX_TRP_165 3 -#define NUMONYX_TRAS_165 7 -#define NUMONYX_TRC_165 10 -#define NUMONYX_TRFC_165 24 -#define NUMONYX_V_ACTIMA_165 ((NUMONYX_TRFC_165 << 27) | (NUMONYX_TRC_165 << 22) | (NUMONYX_TRAS_165 << 18) \ - | (NUMONYX_TRP_165 << 15) | (NUMONYX_TRCD_165 << 12) |(NUMONYX_TRRD_165 << 9) | \ - (NUMONYX_TDPL_165 << 6) | (NUMONYX_TDAL_165)) - -#define NUMONYX_TWTR_165 2 -#define NUMONYX_TCKE_165 2 -#define NUMONYX_TXP_165 3 -#define NUMONYX_XSR_165 34 -#define NUMONYX_V_ACTIMB_165 ((NUMONYX_TCKE_165 << 12) | (NUMONYX_XSR_165 << 0)) | \ - (NUMONYX_TXP_165 << 8) | (NUMONYX_TWTR_165 << 16) - -/* - * Hynix part of Overo (165MHz optimized) 6.06ns - * ACTIMA - * ACTIMA - * TDAL = Twr/Tck + Trp/tck = 15/6 + 18/6 = 2.5 + 3 = 5.5 -> 6 - * TDPL (Twr) = 15/6 = 2.5 -> 3 - * TRRD = 12/6 = 2 - * TRCD = 18/6 = 3 - * TRP = 18/6 = 3 - * TRAS = 42/6 = 7 - * TRC = 60/6 = 10 - * TRFC = 97.5/6 = 17 - * ACTIMB - * TWTR = 1 - * TCKE = 1 - * TXP = 1+1 - * XSR = 140/6 = 24 - */ -#define HYNIX_TDAL_165 6 -#define HYNIX_TDPL_165 3 -#define HYNIX_TRRD_165 2 -#define HYNIX_TRCD_165 3 -#define HYNIX_TRP_165 3 -#define HYNIX_TRAS_165 7 -#define HYNIX_TRC_165 10 -#define HYNIX_TRFC_165 21 -#define HYNIX_V_ACTIMA_165 ((HYNIX_TRFC_165 << 27) | \ - (HYNIX_TRC_165 << 22) | (HYNIX_TRAS_165 << 18) | \ - (HYNIX_TRP_165 << 15) | (HYNIX_TRCD_165 << 12) | \ - (HYNIX_TRRD_165 << 9) | (HYNIX_TDPL_165 << 6) | \ - (HYNIX_TDAL_165)) - -#define HYNIX_TWTR_165 1 -#define HYNIX_TCKE_165 1 -#define HYNIX_TXP_165 2 -#define HYNIX_XSR_165 24 -#define HYNIX_V_ACTIMB_165 ((HYNIX_TCKE_165 << 12) | \ - (HYNIX_XSR_165 << 0) | (HYNIX_TXP_165 << 8) | \ - (HYNIX_TWTR_165 << 16)) - -/* New and compatability speed defines */ -#if defined(PRCM_CLK_CFG2_200MHZ) || defined(PRCM_CONFIG_II) || defined(PRCM_CONFIG_5B) -# define L3_100MHZ /* Use with <= 100MHz SDRAM */ -#elif defined (PRCM_CLK_CFG2_266MHZ) || defined(PRCM_CONFIG_III) || defined(PRCM_CONFIG_5A) -# define L3_133MHZ /* Use with <= 133MHz SDRAM*/ -#elif defined(PRCM_CLK_CFG2_332MHZ) || defined(PRCM_CONFIG_I) || defined(PRCM_CONFIG_2) -# define L3_165MHZ /* Use with <= 165MHz SDRAM (L3=166 on 3430) */ -#endif - -#if defined(L3_100MHZ) -# define MICRON_SDRC_ACTIM_CTRLA_0 MICRON_V_ACTIMA_100 -# define MICRON_SDRC_ACTIM_CTRLB_0 MICRON_V_ACTIMB_100 -#elif defined(L3_133MHZ) -# define MICRON_SDRC_ACTIM_CTRLA_0 MICRON_V_ACTIMA_133 -# define MICRON_SDRC_ACTIM_CTRLB_0 MICRON_V_ACTIMB_133 -#elif defined(L3_165MHZ) -# define MICRON_SDRC_ACTIM_CTRLA_0 MICRON_V_ACTIMA_165 -# define MICRON_SDRC_ACTIM_CTRLB_0 MICRON_V_ACTIMB_165 -# define NUMONYX_SDRC_ACTIM_CTRLA_0 NUMONYX_V_ACTIMA_165 -# define NUMONYX_SDRC_ACTIM_CTRLB_0 NUMONYX_V_ACTIMB_165 -#endif - - -#if defined(L3_100MHZ) -# define INFINEON_SDRC_ACTIM_CTRLA_0 INFINEON_V_ACTIMA_100 -# define INFINEON_SDRC_ACTIM_CTRLB_0 INFINEON_V_ACTIMB_100 -#elif defined(L3_133MHZ) -# define INFINEON_SDRC_ACTIM_CTRLA_0 INFINEON_V_ACTIMA_133 -# define INFINEON_SDRC_ACTIM_CTRLB_0 INFINEON_V_ACTIMB_133 -#elif defined(L3_165MHZ) -# define INFINEON_SDRC_ACTIM_CTRLA_0 INFINEON_V_ACTIMA_165 -# define INFINEON_SDRC_ACTIM_CTRLB_0 INFINEON_V_ACTIMB_165 -#endif - -#if defined(L3_100MHZ) -# define SDP_SDRC_RFR_CTRL SDP_3430_SDRC_RFR_CTRL_100MHz -#elif defined(L3_133MHZ) -# define SDP_SDRC_RFR_CTRL SDP_3430_SDRC_RFR_CTRL_133MHz -#elif defined(L3_165MHZ) -# define SDP_SDRC_RFR_CTRL SDP_3430_SDRC_RFR_CTRL_165MHz -#endif - -/* - * GPMC settings - - * Definitions is as per the following format - * # define <PART>_GPMC_CONFIG<x> <value> - * Where: - * PART is the part name e.g. STNOR - Intel Strata Flash - * x is GPMC config registers from 1 to 6 (there will be 6 macros) - * Value is corresponding value - * - * For every valid PRCM configuration there should be only one definition of - * the same. if values are independent of the board, this definition will be - * present in this file if values are dependent on the board, then this should - * go into corresponding mem-boardName.h file - * - * Currently valid part Names are (PART): - * STNOR - Intel Strata Flash - * SMNAND - Samsung NAND - * M_NAND - Micron Large page x16 NAND - * MPDB - H4 MPDB board - * SBNOR - Sibley NOR - * ONNAND - Samsung One NAND - * - * include/configs/file.h contains the defn - for all CS we are interested - * #define OMAP34XX_GPMC_CSx PART - * #define OMAP34XX_GPMC_CSx_SIZE Size - * #define OMAP34XX_GPMC_CSx_MAP Map - * Where: - * x - CS number - * PART - Part Name as defined above - * SIZE - how big is the mapping to be - * GPMC_SIZE_128M - 0x8 - * GPMC_SIZE_64M - 0xC - * GPMC_SIZE_32M - 0xE - * GPMC_SIZE_16M - 0xF - * MAP - Map this CS to which address(GPMC address space)- Absolute address - * >>24 before being used. - */ -#define GPMC_SIZE_128M 0x8 -#define GPMC_SIZE_64M 0xC -#define GPMC_SIZE_32M 0xE -#define GPMC_SIZE_16M 0xF - -#if defined(L3_100MHZ) -# define SMNAND_GPMC_CONFIG1 0x0 -# define SMNAND_GPMC_CONFIG2 0x00141400 -# define SMNAND_GPMC_CONFIG3 0x00141400 -# define SMNAND_GPMC_CONFIG4 0x0F010F01 -# define SMNAND_GPMC_CONFIG5 0x010C1414 -# define SMNAND_GPMC_CONFIG6 0x00000A80 - -# define M_NAND_GPMC_CONFIG1 0x00001800 -# define M_NAND_GPMC_CONFIG2 SMNAND_GPMC_CONFIG2 -# define M_NAND_GPMC_CONFIG3 SMNAND_GPMC_CONFIG3 -# define M_NAND_GPMC_CONFIG4 SMNAND_GPMC_CONFIG4 -# define M_NAND_GPMC_CONFIG5 SMNAND_GPMC_CONFIG5 -# define M_NAND_GPMC_CONFIG6 SMNAND_GPMC_CONFIG6 -# define STNOR_GPMC_CONFIG1 0x3 -# define STNOR_GPMC_CONFIG2 0x000f0f01 -# define STNOR_GPMC_CONFIG3 0x00050502 -# define STNOR_GPMC_CONFIG4 0x0C060C06 -# define STNOR_GPMC_CONFIG5 0x01131F1F -# define STNOR_GPMC_CONFIG6 0x0 /* 0? */ -# define MPDB_GPMC_CONFIG1 0x00011000 -# define MPDB_GPMC_CONFIG2 0x001F1F00 -# define MPDB_GPMC_CONFIG3 0x00080802 -# define MPDB_GPMC_CONFIG4 0x1C091C09 -# define MPDB_GPMC_CONFIG5 0x031A1F1F -# define MPDB_GPMC_CONFIG6 0x000003C2 -#endif - -#if defined(L3_133MHZ) -# define SMNAND_GPMC_CONFIG1 0x00000800 -# define SMNAND_GPMC_CONFIG2 0x00141400 -# define SMNAND_GPMC_CONFIG3 0x00141400 -# define SMNAND_GPMC_CONFIG4 0x0F010F01 -# define SMNAND_GPMC_CONFIG5 0x010C1414 -# define SMNAND_GPMC_CONFIG6 0x00000A80 -# define SMNAND_GPMC_CONFIG7 0x00000C44 - -# define M_NAND_GPMC_CONFIG1 0x00001800 -# define M_NAND_GPMC_CONFIG2 SMNAND_GPMC_CONFIG2 -# define M_NAND_GPMC_CONFIG3 SMNAND_GPMC_CONFIG3 -# define M_NAND_GPMC_CONFIG4 SMNAND_GPMC_CONFIG4 -# define M_NAND_GPMC_CONFIG5 SMNAND_GPMC_CONFIG5 -# define M_NAND_GPMC_CONFIG6 SMNAND_GPMC_CONFIG6 -# define M_NAND_GPMC_CONFIG7 SMNAND_GPMC_CONFIG7 - -# define STNOR_GPMC_CONFIG1 0x1203 -# define STNOR_GPMC_CONFIG2 0x00151501 -# define STNOR_GPMC_CONFIG3 0x00060602 -# define STNOR_GPMC_CONFIG4 0x10081008 -# define STNOR_GPMC_CONFIG5 0x01131F1F -# define STNOR_GPMC_CONFIG6 0x000004c4 - -# define SIBNOR_GPMC_CONFIG1 0x1200 -# define SIBNOR_GPMC_CONFIG2 0x001f1f00 -# define SIBNOR_GPMC_CONFIG3 0x00080802 -# define SIBNOR_GPMC_CONFIG4 0x1C091C09 -# define SIBNOR_GPMC_CONFIG5 0x01131F1F -# define SIBNOR_GPMC_CONFIG6 0x000003C2 - -# define MPDB_GPMC_CONFIG1 0x00011000 -# define MPDB_GPMC_CONFIG2 0x001f1f01 -# define MPDB_GPMC_CONFIG3 0x00080803 -# define MPDB_GPMC_CONFIG4 0x1C091C09 -# define MPDB_GPMC_CONFIG5 0x041f1F1F -# define MPDB_GPMC_CONFIG6 0x000004C4 - -# define P2_GPMC_CONFIG1 0x0 -# define P2_GPMC_CONFIG2 0x0 -# define P2_GPMC_CONFIG3 0x0 -# define P2_GPMC_CONFIG4 0x0 -# define P2_GPMC_CONFIG5 0x0 -# define P2_GPMC_CONFIG6 0x0 - -# define ONENAND_GPMC_CONFIG1 0x00001200 -# define ONENAND_GPMC_CONFIG2 0x000c0c01 -# define ONENAND_GPMC_CONFIG3 0x00030301 -# define ONENAND_GPMC_CONFIG4 0x0c040c04 -# define ONENAND_GPMC_CONFIG5 0x010C1010 -# define ONENAND_GPMC_CONFIG6 0x00000000 - -#endif /* endif L3_133MHZ */ - -#if defined (L3_165MHZ) -# define SMNAND_GPMC_CONFIG1 0x00000800 -# define SMNAND_GPMC_CONFIG2 0x00141400 -# define SMNAND_GPMC_CONFIG3 0x00141400 -# define SMNAND_GPMC_CONFIG4 0x0F010F01 -# define SMNAND_GPMC_CONFIG5 0x010C1414 -# define SMNAND_GPMC_CONFIG6 0x1F0F0A80 -# define SMNAND_GPMC_CONFIG7 0x00000C44 - -# define M_NAND_GPMC_CONFIG1 0x00001800 -# define M_NAND_GPMC_CONFIG2 SMNAND_GPMC_CONFIG2 -# define M_NAND_GPMC_CONFIG3 SMNAND_GPMC_CONFIG3 -# define M_NAND_GPMC_CONFIG4 SMNAND_GPMC_CONFIG4 -# define M_NAND_GPMC_CONFIG5 SMNAND_GPMC_CONFIG5 -# define M_NAND_GPMC_CONFIG6 SMNAND_GPMC_CONFIG6 -# define M_NAND_GPMC_CONFIG7 SMNAND_GPMC_CONFIG7 - -# define STNOR_GPMC_CONFIG1 0x3 -# define STNOR_GPMC_CONFIG2 0x00151501 -# define STNOR_GPMC_CONFIG3 0x00060602 -# define STNOR_GPMC_CONFIG4 0x11091109 -# define STNOR_GPMC_CONFIG5 0x01141F1F -# define STNOR_GPMC_CONFIG6 0x000004c4 - -# define SIBNOR_GPMC_CONFIG1 0x1200 -# define SIBNOR_GPMC_CONFIG2 0x001f1f00 -# define SIBNOR_GPMC_CONFIG3 0x00080802 -# define SIBNOR_GPMC_CONFIG4 0x1C091C09 -# define SIBNOR_GPMC_CONFIG5 0x01131F1F -# define SIBNOR_GPMC_CONFIG6 0x1F0F03C2 - -# define SDPV2_MPDB_GPMC_CONFIG1 0x00611200 -# define SDPV2_MPDB_GPMC_CONFIG2 0x001F1F01 -# define SDPV2_MPDB_GPMC_CONFIG3 0x00080803 -# define SDPV2_MPDB_GPMC_CONFIG4 0x1D091D09 -# define SDPV2_MPDB_GPMC_CONFIG5 0x041D1F1F -# define SDPV2_MPDB_GPMC_CONFIG6 0x1D0904C4 - -# define MPDB_GPMC_CONFIG1 0x00011000 -# define MPDB_GPMC_CONFIG2 0x001f1f01 -# define MPDB_GPMC_CONFIG3 0x00080803 -# define MPDB_GPMC_CONFIG4 0x1c0b1c0a -# define MPDB_GPMC_CONFIG5 0x041f1F1F -# define MPDB_GPMC_CONFIG6 0x1F0F04C4 - -# define P2_GPMC_CONFIG1 0x0 -# define P2_GPMC_CONFIG2 0x0 -# define P2_GPMC_CONFIG3 0x0 -# define P2_GPMC_CONFIG4 0x0 -# define P2_GPMC_CONFIG5 0x0 -# define P2_GPMC_CONFIG6 0x0 - -# define ONENAND_GPMC_CONFIG1 0x00001200 -# define ONENAND_GPMC_CONFIG2 0x000F0F01 -# define ONENAND_GPMC_CONFIG3 0x00030301 -# define ONENAND_GPMC_CONFIG4 0x0F040F04 -# define ONENAND_GPMC_CONFIG5 0x010F1010 -# define ONENAND_GPMC_CONFIG6 0x1F060000 - -#endif - -/* max number of GPMC Chip Selects */ -#define GPMC_MAX_CS 8 -/* max number of GPMC regs */ -#define GPMC_MAX_REG 7 - -#define PISMO1_NOR 1 -#define PISMO1_NAND 2 -#define PISMO2_CS0 3 -#define PISMO2_CS1 4 -#define PISMO1_ONENAND 5 -#define POP_ONENAND 5 -#define DBG_MPDB 6 -#define PISMO2_NAND_CS0 7 -#define PISMO2_NAND_CS1 8 - -/* make it readable for the gpmc_init */ -#define PISMO1_NOR_BASE FLASH_BASE -#define PISMO1_NAND_BASE NAND_BASE -#define PISMO2_CS0_BASE PISMO2_MAP1 -#define PISMO1_ONEN_BASE ONENAND_MAP -#define POP_ONEN_BASE ONENAND_MAP -#define DBG_MPDB_BASE DEBUG_BASE - -#endif /* endif _OMAP34XX_MEM_H_ */ diff --git a/x-loader/include/asm/arch-omap3/mmc.h b/x-loader/include/asm/arch-omap3/mmc.h deleted file mode 100644 index 8631aae..0000000 --- a/x-loader/include/asm/arch-omap3/mmc.h +++ /dev/null @@ -1,235 +0,0 @@ -/* - * (C) Copyright 2008 - * Texas Instruments, <www.ti.com> - * Syed Mohammed Khasim <khasim@ti.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation's version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef MMC_H -#define MMC_H - -#include "mmc_host_def.h" - -/* Responses */ -#define RSP_TYPE_NONE (RSP_TYPE_NORSP | CCCE_NOCHECK | CICE_NOCHECK) -#define RSP_TYPE_R1 (RSP_TYPE_LGHT48 | CCCE_CHECK | CICE_CHECK) -#define RSP_TYPE_R1B (RSP_TYPE_LGHT48B | CCCE_CHECK | CICE_CHECK) -#define RSP_TYPE_R2 (RSP_TYPE_LGHT136 | CCCE_CHECK | CICE_NOCHECK) -#define RSP_TYPE_R3 (RSP_TYPE_LGHT48 | CCCE_NOCHECK | CICE_NOCHECK) -#define RSP_TYPE_R4 (RSP_TYPE_LGHT48 | CCCE_NOCHECK | CICE_NOCHECK) -#define RSP_TYPE_R5 (RSP_TYPE_LGHT48 | CCCE_CHECK | CICE_CHECK) -#define RSP_TYPE_R6 (RSP_TYPE_LGHT48 | CCCE_CHECK | CICE_CHECK) -#define RSP_TYPE_R7 (RSP_TYPE_LGHT48 | CCCE_CHECK | CICE_CHECK) - -/* All supported commands */ -#define MMC_CMD0 (INDEX(0) | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE) -#define MMC_CMD1 (INDEX(1) | RSP_TYPE_R3 | DP_NO_DATA | DDIR_WRITE) -#define MMC_CMD2 (INDEX(2) | RSP_TYPE_R2 | DP_NO_DATA | DDIR_WRITE) -#define MMC_CMD3 (INDEX(3) | RSP_TYPE_R1 | DP_NO_DATA | DDIR_WRITE) -#define MMC_SDCMD3 (INDEX(3) | RSP_TYPE_R6 | DP_NO_DATA | DDIR_WRITE) -#define MMC_CMD4 (INDEX(4) | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE) -#define MMC_CMD6 (INDEX(6) | RSP_TYPE_R1B | DP_NO_DATA | DDIR_WRITE) -#define MMC_CMD7_SELECT (INDEX(7) | RSP_TYPE_R1B | DP_NO_DATA | DDIR_WRITE) -#define MMC_CMD7_DESELECT (INDEX(7) | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE) -#define MMC_CMD8 (INDEX(8) | RSP_TYPE_R1 | DP_DATA | DDIR_READ) -#define MMC_SDCMD8 (INDEX(8) | RSP_TYPE_R7 | DP_NO_DATA | DDIR_WRITE) -#define MMC_CMD9 (INDEX(9) | RSP_TYPE_R2 | DP_NO_DATA | DDIR_WRITE) -#define MMC_CMD12 (INDEX(12) | RSP_TYPE_R1B | DP_NO_DATA | DDIR_WRITE) -#define MMC_CMD13 (INDEX(13) | RSP_TYPE_R1 | DP_NO_DATA | DDIR_WRITE) -#define MMC_CMD15 (INDEX(15) | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE) -#define MMC_CMD16 (INDEX(16) | RSP_TYPE_R1 | DP_NO_DATA | DDIR_WRITE) -#define MMC_CMD17 (INDEX(17) | RSP_TYPE_R1 | DP_DATA | DDIR_READ) -#define MMC_CMD24 (INDEX(24) | RSP_TYPE_R1 | DP_DATA | DDIR_WRITE) -#define MMC_ACMD6 (INDEX(6) | RSP_TYPE_R1 | DP_NO_DATA | DDIR_WRITE) -#define MMC_ACMD41 (INDEX(41) | RSP_TYPE_R3 | DP_NO_DATA | DDIR_WRITE) -#define MMC_ACMD51 (INDEX(51) | RSP_TYPE_R1 | DP_DATA | DDIR_READ) -#define MMC_CMD55 (INDEX(55) | RSP_TYPE_R1 | DP_NO_DATA | DDIR_WRITE) - -#define MMC_AC_CMD_RCA_MASK (unsigned int)(0xFFFF << 16) -#define MMC_BC_CMD_DSR_MASK (unsigned int)(0xFFFF << 16) -#define MMC_DSR_DEFAULT (0x0404) -#define SD_CMD8_CHECK_PATTERN (0xAA) -#define SD_CMD8_2_7_3_6_V_RANGE (0x01 << 8) - -/* Clock Configurations and Macros */ - -#define MMC_CLOCK_REFERENCE (96) -#define MMC_RELATIVE_CARD_ADDRESS (0x1234) -#define MMC_INIT_SEQ_CLK (MMC_CLOCK_REFERENCE * 1000 / 80) -#define MMC_400kHz_CLK (MMC_CLOCK_REFERENCE * 1000 / 400) -#define CLKDR(r, f, u) ((((r)*100) / ((f)*(u))) + 1) -#define CLKD(f, u) (CLKDR(MMC_CLOCK_REFERENCE, f, u)) - -#define MMC_OCR_REG_ACCESS_MODE_MASK (0x3 << 29) -#define MMC_OCR_REG_ACCESS_MODE_BYTE (0x0 << 29) -#define MMC_OCR_REG_ACCESS_MODE_SECTOR (0x2 << 29) - -#define MMC_OCR_REG_HOST_CAPACITY_SUPPORT_MASK (0x1 << 30) -#define MMC_OCR_REG_HOST_CAPACITY_SUPPORT_BYTE (0x0 << 30) -#define MMC_OCR_REG_HOST_CAPACITY_SUPPORT_SECTOR (0x1 << 30) - -#define MMC_SD2_CSD_C_SIZE_LSB_MASK (0xFFFF) -#define MMC_SD2_CSD_C_SIZE_MSB_MASK (0x003F) -#define MMC_SD2_CSD_C_SIZE_MSB_OFFSET (16) -#define MMC_CSD_C_SIZE_LSB_MASK (0x0003) -#define MMC_CSD_C_SIZE_MSB_MASK (0x03FF) -#define MMC_CSD_C_SIZE_MSB_OFFSET (2) - -#define MMC_CSD_TRAN_SPEED_UNIT_MASK (0x07 << 0) -#define MMC_CSD_TRAN_SPEED_FACTOR_MASK (0x0F << 3) -#define MMC_CSD_TRAN_SPEED_UNIT_100MHZ (0x3 << 0) -#define MMC_CSD_TRAN_SPEED_FACTOR_1_0 (0x01 << 3) -#define MMC_CSD_TRAN_SPEED_FACTOR_8_0 (0x0F << 3) - -typedef struct { - unsigned not_used:1; - unsigned crc:7; - unsigned ecc:2; - unsigned file_format:2; - unsigned tmp_write_protect:1; - unsigned perm_write_protect:1; - unsigned copy:1; - unsigned file_format_grp:1; - unsigned content_prot_app:1; - unsigned reserved_1:4; - unsigned write_bl_partial:1; - unsigned write_bl_len:4; - unsigned r2w_factor:3; - unsigned default_ecc:2; - unsigned wp_grp_enable:1; - unsigned wp_grp_size:5; - unsigned erase_grp_mult:5; - unsigned erase_grp_size:5; - unsigned c_size_mult:3; - unsigned vdd_w_curr_max:3; - unsigned vdd_w_curr_min:3; - unsigned vdd_r_curr_max:3; - unsigned vdd_r_curr_min:3; - unsigned c_size_lsb:2; - unsigned c_size_msb:10; - unsigned reserved_2:2; - unsigned dsr_imp:1; - unsigned read_blk_misalign:1; - unsigned write_blk_misalign:1; - unsigned read_bl_partial:1; - unsigned read_bl_len:4; - unsigned ccc:12; - unsigned tran_speed:8; - unsigned nsac:8; - unsigned taac:8; - unsigned reserved_3:2; - unsigned spec_vers:4; - unsigned csd_structure:2; -} mmc_csd_reg_t; - -/* csd for sd2.0 */ -typedef struct { - unsigned not_used:1; - unsigned crc:7; - unsigned reserved_1:2; - unsigned file_format:2; - unsigned tmp_write_protect:1; - unsigned perm_write_protect:1; - unsigned copy:1; - unsigned file_format_grp:1; - unsigned reserved_2:5; - unsigned write_bl_partial:1; - unsigned write_bl_len:4; - unsigned r2w_factor:3; - unsigned reserved_3:2; - unsigned wp_grp_enable:1; - unsigned wp_grp_size:7; - unsigned sector_size:7; - unsigned erase_blk_len:1; - unsigned reserved_4:1; - unsigned c_size_lsb:16; - unsigned c_size_msb:6; - unsigned reserved_5:6; - unsigned dsr_imp:1; - unsigned read_blk_misalign:1; - unsigned write_blk_misalign:1; - unsigned read_bl_partial:1; - unsigned read_bl_len:4; - unsigned ccc:12; - unsigned tran_speed:8; - unsigned nsac:8; - unsigned taac:8; - unsigned reserved_6:6; - unsigned csd_structure:2; -} mmc_sd2_csd_reg_t; - -/* extended csd - 512 bytes long */ -typedef struct { - unsigned char reserved_1[181]; - unsigned char erasedmemorycontent; - unsigned char reserved_2; - unsigned char buswidthmode; - unsigned char reserved_3; - unsigned char highspeedinterfacetiming; - unsigned char reserved_4; - unsigned char powerclass; - unsigned char reserved_5; - unsigned char commandsetrevision; - unsigned char reserved_6; - unsigned char commandset; - unsigned char extendedcsdrevision; - unsigned char reserved_7; - unsigned char csdstructureversion; - unsigned char reserved_8; - unsigned char cardtype; - unsigned char reserved_9[3]; - unsigned char powerclass_52mhz_1_95v; - unsigned char powerclass_26mhz_1_95v; - unsigned char powerclass_52mhz_3_6v; - unsigned char powerclass_26mhz_3_6v; - unsigned char reserved_10; - unsigned char minreadperf_4b_26mhz; - unsigned char minwriteperf_4b_26mhz; - unsigned char minreadperf_8b_26mhz_4b_52mhz; - unsigned char minwriteperf_8b_26mhz_4b_52mhz; - unsigned char minreadperf_8b_52mhz; - unsigned char minwriteperf_8b_52mhz; - unsigned char reserved_11; - unsigned int sectorcount; - unsigned char reserved_12[288]; - unsigned char supportedcommandsets; - unsigned char reserved_13[7]; -} mmc_extended_csd_reg_t; - -/* mmc sd responce */ -typedef struct { - unsigned int ocr; -} mmc_resp_r3; - -typedef struct { - unsigned short cardstatus; - unsigned short newpublishedrca; -} mmc_resp_r6; - -extern mmc_card_data mmc_dev; - -unsigned char mmc_lowlevel_init(void); -unsigned char mmc_send_command(unsigned int cmd, unsigned int arg, - unsigned int *response); -unsigned char mmc_setup_clock(unsigned int iclk, unsigned short clkd); -unsigned char mmc_set_opendrain(unsigned char state); -unsigned char mmc_read_data(unsigned int *output_buf); - -#endif /* MMC_H */ diff --git a/x-loader/include/asm/arch-omap3/mmc_host_def.h b/x-loader/include/asm/arch-omap3/mmc_host_def.h deleted file mode 100644 index 408d1e2..0000000 --- a/x-loader/include/asm/arch-omap3/mmc_host_def.h +++ /dev/null @@ -1,164 +0,0 @@ -/* - * (C) Copyright 2008 - * Texas Instruments, <www.ti.com> - * Syed Mohammed Khasim <khasim@ti.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation's version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef MMC_HOST_DEF_H -#define MMC_HOST_DEF_H - -/* - * OMAP HSMMC register definitions - */ -#define OMAP_HSMMC_SYSCONFIG (*(volatile unsigned int *) 0x4809C010) -#define OMAP_HSMMC_SYSSTATUS (*(volatile unsigned int *) 0x4809C014) -#define OMAP_HSMMC_CON (*(volatile unsigned int *) 0x4809C02C) -#define OMAP_HSMMC_BLK (*(volatile unsigned int *) 0x4809C104) -#define OMAP_HSMMC_ARG (*(volatile unsigned int *) 0x4809C108) -#define OMAP_HSMMC_CMD (*(volatile unsigned int *) 0x4809C10C) -#define OMAP_HSMMC_RSP10 (*(volatile unsigned int *) 0x4809C110) -#define OMAP_HSMMC_RSP32 (*(volatile unsigned int *) 0x4809C114) -#define OMAP_HSMMC_RSP54 (*(volatile unsigned int *) 0x4809C118) -#define OMAP_HSMMC_RSP76 (*(volatile unsigned int *) 0x4809C11C) -#define OMAP_HSMMC_DATA (*(volatile unsigned int *) 0x4809C120) -#define OMAP_HSMMC_PSTATE (*(volatile unsigned int *) 0x4809C124) -#define OMAP_HSMMC_HCTL (*(volatile unsigned int *) 0x4809C128) -#define OMAP_HSMMC_SYSCTL (*(volatile unsigned int *) 0x4809C12C) -#define OMAP_HSMMC_STAT (*(volatile unsigned int *) 0x4809C130) -#define OMAP_HSMMC_IE (*(volatile unsigned int *) 0x4809C134) -#define OMAP_HSMMC_CAPA (*(volatile unsigned int *) 0x4809C140) - -/* T2 Register definitions */ -#define CONTROL_DEV_CONF0 (*(volatile unsigned int *) 0x48002274) -#define CONTROL_PBIAS_LITE (*(volatile unsigned int *) 0x48002520) - -/* - * OMAP HS MMC Bit definitions - */ -#define MMC_SOFTRESET (0x1 << 1) -#define RESETDONE (0x1 << 0) -#define NOOPENDRAIN (0x0 << 0) -#define OPENDRAIN (0x1 << 0) -#define OD (0x1 << 0) -#define INIT_NOINIT (0x0 << 1) -#define INIT_INITSTREAM (0x1 << 1) -#define HR_NOHOSTRESP (0x0 << 2) -#define STR_BLOCK (0x0 << 3) -#define MODE_FUNC (0x0 << 4) -#define DW8_1_4BITMODE (0x0 << 5) -#define MIT_CTO (0x0 << 6) -#define CDP_ACTIVEHIGH (0x0 << 7) -#define WPP_ACTIVEHIGH (0x0 << 8) -#define RESERVED_MASK (0x3 << 9) -#define CTPL_MMC_SD (0x0 << 11) -#define BLEN_512BYTESLEN (0x200 << 0) -#define NBLK_STPCNT (0x0 << 16) -#define DE_DISABLE (0x0 << 0) -#define BCE_DISABLE (0x0 << 1) -#define ACEN_DISABLE (0x0 << 2) -#define DDIR_OFFSET (4) -#define DDIR_MASK (0x1 << 4) -#define DDIR_WRITE (0x0 << 4) -#define DDIR_READ (0x1 << 4) -#define MSBS_SGLEBLK (0x0 << 5) -#define RSP_TYPE_OFFSET (16) -#define RSP_TYPE_MASK (0x3 << 16) -#define RSP_TYPE_NORSP (0x0 << 16) -#define RSP_TYPE_LGHT136 (0x1 << 16) -#define RSP_TYPE_LGHT48 (0x2 << 16) -#define RSP_TYPE_LGHT48B (0x3 << 16) -#define CCCE_NOCHECK (0x0 << 19) -#define CCCE_CHECK (0x1 << 19) -#define CICE_NOCHECK (0x0 << 20) -#define CICE_CHECK (0x1 << 20) -#define DP_OFFSET (21) -#define DP_MASK (0x1 << 21) -#define DP_NO_DATA (0x0 << 21) -#define DP_DATA (0x1 << 21) -#define CMD_TYPE_NORMAL (0x0 << 22) -#define INDEX_OFFSET (24) -#define INDEX_MASK (0x3f << 24) -#define INDEX(i) (i << 24) -#define DATI_MASK (0x1 << 1) -#define DATI_CMDDIS (0x1 << 1) -#define DTW_1_BITMODE (0x0 << 1) -#define DTW_4_BITMODE (0x1 << 1) -#define SDBP_PWROFF (0x0 << 8) -#define SDBP_PWRON (0x1 << 8) -#define SDVS_1V8 (0x5 << 9) -#define SDVS_3V0 (0x6 << 9) -#define ICE_MASK (0x1 << 0) -#define ICE_STOP (0x0 << 0) -#define ICS_MASK (0x1 << 1) -#define ICS_NOTREADY (0x0 << 1) -#define ICE_OSCILLATE (0x1 << 0) -#define CEN_MASK (0x1 << 2) -#define CEN_DISABLE (0x0 << 2) -#define CEN_ENABLE (0x1 << 2) -#define CLKD_OFFSET (6) -#define CLKD_MASK (0x3FF << 6) -#define DTO_MASK (0xF << 16) -#define DTO_15THDTO (0xE << 16) -#define SOFTRESETALL (0x1 << 24) -#define CC_MASK (0x1 << 0) -#define TC_MASK (0x1 << 1) -#define BWR_MASK (0x1 << 4) -#define BRR_MASK (0x1 << 5) -#define ERRI_MASK (0x1 << 15) -#define IE_CC (0x01 << 0) -#define IE_TC (0x01 << 1) -#define IE_BWR (0x01 << 4) -#define IE_BRR (0x01 << 5) -#define IE_CTO (0x01 << 16) -#define IE_CCRC (0x01 << 17) -#define IE_CEB (0x01 << 18) -#define IE_CIE (0x01 << 19) -#define IE_DTO (0x01 << 20) -#define IE_DCRC (0x01 << 21) -#define IE_DEB (0x01 << 22) -#define IE_CERR (0x01 << 28) -#define IE_BADA (0x01 << 29) - -#define VS30_3V0SUP (1 << 25) -#define VS18_1V8SUP (1 << 26) - -/* Driver definitions */ -#define MMCSD_SECTOR_SIZE (512) -#define MMC_CARD 0 -#define SD_CARD 1 -#define BYTE_MODE 0 -#define SECTOR_MODE 1 -#define CLK_INITSEQ 0 -#define CLK_400KHZ 1 -#define CLK_MISC 2 - -typedef struct { - unsigned int card_type; - unsigned int version; - unsigned int mode; - unsigned int size; - unsigned int RCA; -} mmc_card_data; - -#define mmc_reg_out(addr, mask, val)\ - (addr) = (((addr)) & (~(mask))) | ((val) & (mask)); - -#endif /* MMC_HOST_DEF_H */ diff --git a/x-loader/include/asm/arch-omap3/mux.h b/x-loader/include/asm/arch-omap3/mux.h deleted file mode 100644 index ca140a9..0000000 --- a/x-loader/include/asm/arch-omap3/mux.h +++ /dev/null @@ -1,437 +0,0 @@ -/* - * (C) Copyright 2006 - * Texas Instruments, <www.ti.com> - * Syed Mohammed Khasim <x0khasim@ti.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#ifndef _OMAP3430_MUX_H_ -#define _OMAP3430_MUX_H_ - -/* - * OFF_PD - Off mode pull type down - * OFF_PU - Off mode pull type up - * OFF_OUT_PTD - Off Mode Mux low for OUT - * OFF_OUT_PTU - Off Mode Mux high for OUT - * OFF_IN - Off Mode Mux set to IN - * OFF_OUT - Off Mode Mux set to OUT - * OFF_EN - Off Mode Mux Enable - * IEN - Input Enable - * IDIS - Input Disable - * PTD - Pull type Down - * PTU - Pull type Up - * DIS - Pull type selection is inactive - * EN - Pull type selection is active - * M0 - Mode 0 - */ - -#define OFF_PD (1 << 12) -#define OFF_PU (3 << 12) -#define OFF_OUT_PTD (0 << 11) -#define OFF_OUT_PTU (1 << 11) -#define OFF_IN (1 << 10) -#define OFF_OUT (0 << 10) -#define OFF_EN (1 << 9) - -#define IEN (1 << 8) - -#define IDIS (0 << 8) -#define PTU (1 << 4) -#define PTD (0 << 4) -#define EN (1 << 3) -#define DIS (0 << 3) - -#define M0 0 -#define M1 1 -#define M2 2 -#define M3 3 -#define M4 4 -#define M5 5 -#define M6 6 -#define M7 7 - -#ifdef CONFIG_OFF_PADCONF -#define OFF_IN_PD (OFF_PD | OFF_IN | OFF_EN) -#define OFF_IN_PU (OFF_PU | OFF_IN | OFF_EN) -#define OFF_OUT_PD (OFF_OUT_PTD | OFF_OUT | OFF_EN) -#define OFF_OUT_PU (OFF_OUT_PTU | OFF_OUT | OFF_EN) -#else -#define OFF_IN_PD 0 -#define OFF_IN_PU 0 -#define OFF_OUT_PD 0 -#define OFF_OUT_PU 0 -#endif /* #ifdef CONFIG_OFF_PADCONF */ - -/* - * To get the actual address the offset has to added - * with OMAP34XX_CTRL_BASE to get the actual address - */ - -/*SDRC*/ -#define CONTROL_PADCONF_SDRC_D0 0x0030 -#define CONTROL_PADCONF_SDRC_D1 0x0032 -#define CONTROL_PADCONF_SDRC_D2 0x0034 -#define CONTROL_PADCONF_SDRC_D3 0x0036 -#define CONTROL_PADCONF_SDRC_D4 0x0038 -#define CONTROL_PADCONF_SDRC_D5 0x003A -#define CONTROL_PADCONF_SDRC_D6 0x003C -#define CONTROL_PADCONF_SDRC_D7 0x003E -#define CONTROL_PADCONF_SDRC_D8 0x0040 -#define CONTROL_PADCONF_SDRC_D9 0x0042 -#define CONTROL_PADCONF_SDRC_D10 0x0044 -#define CONTROL_PADCONF_SDRC_D11 0x0046 -#define CONTROL_PADCONF_SDRC_D12 0x0048 -#define CONTROL_PADCONF_SDRC_D13 0x004A -#define CONTROL_PADCONF_SDRC_D14 0x004C -#define CONTROL_PADCONF_SDRC_D15 0x004E -#define CONTROL_PADCONF_SDRC_D16 0x0050 -#define CONTROL_PADCONF_SDRC_D17 0x0052 -#define CONTROL_PADCONF_SDRC_D18 0x0054 -#define CONTROL_PADCONF_SDRC_D19 0x0056 -#define CONTROL_PADCONF_SDRC_D20 0x0058 -#define CONTROL_PADCONF_SDRC_D21 0x005A -#define CONTROL_PADCONF_SDRC_D22 0x005C -#define CONTROL_PADCONF_SDRC_D23 0x005E -#define CONTROL_PADCONF_SDRC_D24 0x0060 -#define CONTROL_PADCONF_SDRC_D25 0x0062 -#define CONTROL_PADCONF_SDRC_D26 0x0064 -#define CONTROL_PADCONF_SDRC_D27 0x0066 -#define CONTROL_PADCONF_SDRC_D28 0x0068 -#define CONTROL_PADCONF_SDRC_D29 0x006A -#define CONTROL_PADCONF_SDRC_D30 0x006C -#define CONTROL_PADCONF_SDRC_D31 0x006E -#define CONTROL_PADCONF_SDRC_CLK 0x0070 -#define CONTROL_PADCONF_SDRC_DQS0 0x0072 -#define CONTROL_PADCONF_SDRC_DQS1 0x0074 -#define CONTROL_PADCONF_SDRC_DQS2 0x0076 -#define CONTROL_PADCONF_SDRC_DQS3 0x0078 -/*GPMC*/ -#define CONTROL_PADCONF_GPMC_A1 0x007A -#define CONTROL_PADCONF_GPMC_A2 0x007C -#define CONTROL_PADCONF_GPMC_A3 0x007E -#define CONTROL_PADCONF_GPMC_A4 0x0080 -#define CONTROL_PADCONF_GPMC_A5 0x0082 -#define CONTROL_PADCONF_GPMC_A6 0x0084 -#define CONTROL_PADCONF_GPMC_A7 0x0086 -#define CONTROL_PADCONF_GPMC_A8 0x0088 -#define CONTROL_PADCONF_GPMC_A9 0x008A -#define CONTROL_PADCONF_GPMC_A10 0x008C -#define CONTROL_PADCONF_GPMC_D0 0x008E -#define CONTROL_PADCONF_GPMC_D1 0x0090 -#define CONTROL_PADCONF_GPMC_D2 0x0092 -#define CONTROL_PADCONF_GPMC_D3 0x0094 -#define CONTROL_PADCONF_GPMC_D4 0x0096 -#define CONTROL_PADCONF_GPMC_D5 0x0098 -#define CONTROL_PADCONF_GPMC_D6 0x009A -#define CONTROL_PADCONF_GPMC_D7 0x009C -#define CONTROL_PADCONF_GPMC_D8 0x009E -#define CONTROL_PADCONF_GPMC_D9 0x00A0 -#define CONTROL_PADCONF_GPMC_D10 0x00A2 -#define CONTROL_PADCONF_GPMC_D11 0x00A4 -#define CONTROL_PADCONF_GPMC_D12 0x00A6 -#define CONTROL_PADCONF_GPMC_D13 0x00A8 -#define CONTROL_PADCONF_GPMC_D14 0x00AA -#define CONTROL_PADCONF_GPMC_D15 0x00AC -#define CONTROL_PADCONF_GPMC_nCS0 0x00AE -#define CONTROL_PADCONF_GPMC_nCS1 0x00B0 -#define CONTROL_PADCONF_GPMC_nCS2 0x00B2 -#define CONTROL_PADCONF_GPMC_nCS3 0x00B4 -#define CONTROL_PADCONF_GPMC_nCS4 0x00B6 -#define CONTROL_PADCONF_GPMC_nCS5 0x00B8 -#define CONTROL_PADCONF_GPMC_nCS6 0x00BA -#define CONTROL_PADCONF_GPMC_nCS7 0x00BC -#define CONTROL_PADCONF_GPMC_CLK 0x00BE -#define CONTROL_PADCONF_GPMC_nADV_ALE 0x00C0 -#define CONTROL_PADCONF_GPMC_nOE 0x00C2 -#define CONTROL_PADCONF_GPMC_nWE 0x00C4 -#define CONTROL_PADCONF_GPMC_nBE0_CLE 0x00C6 -#define CONTROL_PADCONF_GPMC_nBE1 0x00C8 -#define CONTROL_PADCONF_GPMC_nWP 0x00CA -#define CONTROL_PADCONF_GPMC_WAIT0 0x00CC -#define CONTROL_PADCONF_GPMC_WAIT1 0x00CE -#define CONTROL_PADCONF_GPMC_WAIT2 0x00D0 -#define CONTROL_PADCONF_GPMC_WAIT3 0x00D2 -/*DSS*/ -#define CONTROL_PADCONF_DSS_PCLK 0x00D4 -#define CONTROL_PADCONF_DSS_HSYNC 0x00D6 -#define CONTROL_PADCONF_DSS_VSYNC 0x00D8 -#define CONTROL_PADCONF_DSS_ACBIAS 0x00DA -#define CONTROL_PADCONF_DSS_DATA0 0x00DC -#define CONTROL_PADCONF_DSS_DATA1 0x00DE -#define CONTROL_PADCONF_DSS_DATA2 0x00E0 -#define CONTROL_PADCONF_DSS_DATA3 0x00E2 -#define CONTROL_PADCONF_DSS_DATA4 0x00E4 -#define CONTROL_PADCONF_DSS_DATA5 0x00E6 -#define CONTROL_PADCONF_DSS_DATA6 0x00E8 -#define CONTROL_PADCONF_DSS_DATA7 0x00EA -#define CONTROL_PADCONF_DSS_DATA8 0x00EC -#define CONTROL_PADCONF_DSS_DATA9 0x00EE -#define CONTROL_PADCONF_DSS_DATA10 0x00F0 -#define CONTROL_PADCONF_DSS_DATA11 0x00F2 -#define CONTROL_PADCONF_DSS_DATA12 0x00F4 -#define CONTROL_PADCONF_DSS_DATA13 0x00F6 -#define CONTROL_PADCONF_DSS_DATA14 0x00F8 -#define CONTROL_PADCONF_DSS_DATA15 0x00FA -#define CONTROL_PADCONF_DSS_DATA16 0x00FC -#define CONTROL_PADCONF_DSS_DATA17 0x00FE -#define CONTROL_PADCONF_DSS_DATA18 0x0100 -#define CONTROL_PADCONF_DSS_DATA19 0x0102 -#define CONTROL_PADCONF_DSS_DATA20 0x0104 -#define CONTROL_PADCONF_DSS_DATA21 0x0106 -#define CONTROL_PADCONF_DSS_DATA22 0x0108 -#define CONTROL_PADCONF_DSS_DATA23 0x010A -/*CAMERA*/ -#define CONTROL_PADCONF_CAM_HS 0x010C -#define CONTROL_PADCONF_CAM_VS 0x010E -#define CONTROL_PADCONF_CAM_XCLKA 0x0110 -#define CONTROL_PADCONF_CAM_PCLK 0x0112 -#define CONTROL_PADCONF_CAM_FLD 0x0114 -#define CONTROL_PADCONF_CAM_D0 0x0116 -#define CONTROL_PADCONF_CAM_D1 0x0118 -#define CONTROL_PADCONF_CAM_D2 0x011A -#define CONTROL_PADCONF_CAM_D3 0x011C -#define CONTROL_PADCONF_CAM_D4 0x011E -#define CONTROL_PADCONF_CAM_D5 0x0120 -#define CONTROL_PADCONF_CAM_D6 0x0122 -#define CONTROL_PADCONF_CAM_D7 0x0124 -#define CONTROL_PADCONF_CAM_D8 0x0126 -#define CONTROL_PADCONF_CAM_D9 0x0128 -#define CONTROL_PADCONF_CAM_D10 0x012A -#define CONTROL_PADCONF_CAM_D11 0x012C -#define CONTROL_PADCONF_CAM_XCLKB 0x012E -#define CONTROL_PADCONF_CAM_WEN 0x0130 -#define CONTROL_PADCONF_CAM_STROBE 0x0132 -#define CONTROL_PADCONF_CSI2_DX0 0x0134 -#define CONTROL_PADCONF_CSI2_DY0 0x0136 -#define CONTROL_PADCONF_CSI2_DX1 0x0138 -#define CONTROL_PADCONF_CSI2_DY1 0x013A -/*Audio Interface */ -#define CONTROL_PADCONF_McBSP2_FSX 0x013C -#define CONTROL_PADCONF_McBSP2_CLKX 0x013E -#define CONTROL_PADCONF_McBSP2_DR 0x0140 -#define CONTROL_PADCONF_McBSP2_DX 0x0142 -#define CONTROL_PADCONF_ -#define CONTROL_PADCONF_MMC1_CLK 0x0144 -#define CONTROL_PADCONF_MMC1_CMD 0x0146 -#define CONTROL_PADCONF_MMC1_DAT0 0x0148 -#define CONTROL_PADCONF_MMC1_DAT1 0x014A -#define CONTROL_PADCONF_MMC1_DAT2 0x014C -#define CONTROL_PADCONF_MMC1_DAT3 0x014E -#define CONTROL_PADCONF_MMC1_DAT4 0x0150 -#define CONTROL_PADCONF_MMC1_DAT5 0x0152 -#define CONTROL_PADCONF_MMC1_DAT6 0x0154 -#define CONTROL_PADCONF_MMC1_DAT7 0x0156 -/*Wireless LAN */ -#define CONTROL_PADCONF_MMC2_CLK 0x0158 -#define CONTROL_PADCONF_MMC2_CMD 0x015A -#define CONTROL_PADCONF_MMC2_DAT0 0x015C -#define CONTROL_PADCONF_MMC2_DAT1 0x015E -#define CONTROL_PADCONF_MMC2_DAT2 0x0160 -#define CONTROL_PADCONF_MMC2_DAT3 0x0162 -#define CONTROL_PADCONF_MMC2_DAT4 0x0164 -#define CONTROL_PADCONF_MMC2_DAT5 0x0166 -#define CONTROL_PADCONF_MMC2_DAT6 0x0168 -#define CONTROL_PADCONF_MMC2_DAT7 0x016A -/*Bluetooth*/ -#define CONTROL_PADCONF_McBSP3_DX 0x016C -#define CONTROL_PADCONF_McBSP3_DR 0x016E -#define CONTROL_PADCONF_McBSP3_CLKX 0x0170 -#define CONTROL_PADCONF_McBSP3_FSX 0x0172 -#define CONTROL_PADCONF_UART2_CTS 0x0174 -#define CONTROL_PADCONF_UART2_RTS 0x0176 -#define CONTROL_PADCONF_UART2_TX 0x0178 -#define CONTROL_PADCONF_UART2_RX 0x017A -/*Modem Interface */ -#define CONTROL_PADCONF_UART1_TX 0x017C -#define CONTROL_PADCONF_UART1_RTS 0x017E -#define CONTROL_PADCONF_UART1_CTS 0x0180 -#define CONTROL_PADCONF_UART1_RX 0x0182 -#define CONTROL_PADCONF_McBSP4_CLKX 0x0184 -#define CONTROL_PADCONF_McBSP4_DR 0x0186 -#define CONTROL_PADCONF_McBSP4_DX 0x0188 -#define CONTROL_PADCONF_McBSP4_FSX 0x018A -#define CONTROL_PADCONF_McBSP1_CLKR 0x018C -#define CONTROL_PADCONF_McBSP1_FSR 0x018E -#define CONTROL_PADCONF_McBSP1_DX 0x0190 -#define CONTROL_PADCONF_McBSP1_DR 0x0192 -#define CONTROL_PADCONF_McBSP_CLKS 0x0194 -#define CONTROL_PADCONF_McBSP1_FSX 0x0196 -#define CONTROL_PADCONF_McBSP1_CLKX 0x0198 -/*Serial Interface*/ -#define CONTROL_PADCONF_UART3_CTS_RCTX 0x019A -#define CONTROL_PADCONF_UART3_RTS_SD 0x019C -#define CONTROL_PADCONF_UART3_RX_IRRX 0x019E -#define CONTROL_PADCONF_UART3_TX_IRTX 0x01A0 -#define CONTROL_PADCONF_HSUSB0_CLK 0x01A2 -#define CONTROL_PADCONF_HSUSB0_STP 0x01A4 -#define CONTROL_PADCONF_HSUSB0_DIR 0x01A6 -#define CONTROL_PADCONF_HSUSB0_NXT 0x01A8 -#define CONTROL_PADCONF_HSUSB0_DATA0 0x01AA -#define CONTROL_PADCONF_HSUSB0_DATA1 0x01AC -#define CONTROL_PADCONF_HSUSB0_DATA2 0x01AE -#define CONTROL_PADCONF_HSUSB0_DATA3 0x01B0 -#define CONTROL_PADCONF_HSUSB0_DATA4 0x01B2 -#define CONTROL_PADCONF_HSUSB0_DATA5 0x01B4 -#define CONTROL_PADCONF_HSUSB0_DATA6 0x01B6 -#define CONTROL_PADCONF_HSUSB0_DATA7 0x01B8 -#define CONTROL_PADCONF_I2C1_SCL 0x01BA -#define CONTROL_PADCONF_I2C1_SDA 0x01BC -#define CONTROL_PADCONF_I2C2_SCL 0x01BE -#define CONTROL_PADCONF_I2C2_SDA 0x01C0 -#define CONTROL_PADCONF_I2C3_SCL 0x01C2 -#define CONTROL_PADCONF_I2C3_SDA 0x01C4 -#define CONTROL_PADCONF_I2C4_SCL 0x0A00 -#define CONTROL_PADCONF_I2C4_SDA 0x0A02 -#define CONTROL_PADCONF_HDQ_SIO 0x01C6 -#define CONTROL_PADCONF_McSPI1_CLK 0x01C8 -#define CONTROL_PADCONF_McSPI1_SIMO 0x01CA -#define CONTROL_PADCONF_McSPI1_SOMI 0x01CC -#define CONTROL_PADCONF_McSPI1_CS0 0x01CE -#define CONTROL_PADCONF_McSPI1_CS1 0x01D0 -#define CONTROL_PADCONF_McSPI1_CS2 0x01D2 -#define CONTROL_PADCONF_McSPI1_CS3 0x01D4 -#define CONTROL_PADCONF_McSPI2_CLK 0x01D6 -#define CONTROL_PADCONF_McSPI2_SIMO 0x01D8 -#define CONTROL_PADCONF_McSPI2_SOMI 0x01DA -#define CONTROL_PADCONF_McSPI2_CS0 0x01DC -#define CONTROL_PADCONF_McSPI2_CS1 0x01DE -/*Control and debug */ -#define CONTROL_PADCONF_SYS_32K 0x0A04 -#define CONTROL_PADCONF_SYS_CLKREQ 0x0A06 -#define CONTROL_PADCONF_SYS_nIRQ 0x01E0 -#define CONTROL_PADCONF_SYS_BOOT0 0x0A0A -#define CONTROL_PADCONF_SYS_BOOT1 0x0A0C -#define CONTROL_PADCONF_SYS_BOOT2 0x0A0E -#define CONTROL_PADCONF_SYS_BOOT3 0x0A10 -#define CONTROL_PADCONF_SYS_BOOT4 0x0A12 -#define CONTROL_PADCONF_SYS_BOOT5 0x0A14 -#define CONTROL_PADCONF_SYS_BOOT6 0x0A16 -#define CONTROL_PADCONF_SYS_OFF_MODE 0x0A18 -#define CONTROL_PADCONF_SYS_CLKOUT1 0x0A1A -#define CONTROL_PADCONF_SYS_CLKOUT2 0x01E2 -#define CONTROL_PADCONF_JTAG_nTRST 0x0A1C -#define CONTROL_PADCONF_JTAG_TCK 0x0A1E -#define CONTROL_PADCONF_JTAG_TMS 0x0A20 -#define CONTROL_PADCONF_JTAG_TDI 0x0A22 -#define CONTROL_PADCONF_JTAG_EMU0 0x0A24 -#define CONTROL_PADCONF_JTAG_EMU1 0x0A26 -#define CONTROL_PADCONF_ETK_CLK 0x0A28 -#define CONTROL_PADCONF_ETK_CTL 0x0A2A -#define CONTROL_PADCONF_ETK_D0 0x0A2C -#define CONTROL_PADCONF_ETK_D1 0x0A2E -#define CONTROL_PADCONF_ETK_D2 0x0A30 -#define CONTROL_PADCONF_ETK_D3 0x0A32 -#define CONTROL_PADCONF_ETK_D4 0x0A34 -#define CONTROL_PADCONF_ETK_D5 0x0A36 -#define CONTROL_PADCONF_ETK_D6 0x0A38 -#define CONTROL_PADCONF_ETK_D7 0x0A3A -#define CONTROL_PADCONF_ETK_D8 0x0A3C -#define CONTROL_PADCONF_ETK_D9 0x0A3E -#define CONTROL_PADCONF_ETK_D10 0x0A40 -#define CONTROL_PADCONF_ETK_D11 0x0A42 -#define CONTROL_PADCONF_ETK_D12 0x0A44 -#define CONTROL_PADCONF_ETK_D13 0x0A46 -#define CONTROL_PADCONF_ETK_D14 0x0A48 -#define CONTROL_PADCONF_ETK_D15 0x0A4A - -#define CONTROL_PADCONF_ETK_CLK_ES2 0x05D8 -#define CONTROL_PADCONF_ETK_CTL_ES2 0x05DA -#define CONTROL_PADCONF_ETK_D0_ES2 0x05DC -#define CONTROL_PADCONF_ETK_D1_ES2 0x05DE -#define CONTROL_PADCONF_ETK_D2_ES2 0x05E0 -#define CONTROL_PADCONF_ETK_D3_ES2 0x05E2 -#define CONTROL_PADCONF_ETK_D4_ES2 0x05E4 -#define CONTROL_PADCONF_ETK_D5_ES2 0x05E6 -#define CONTROL_PADCONF_ETK_D6_ES2 0x05E8 -#define CONTROL_PADCONF_ETK_D7_ES2 0x05EA -#define CONTROL_PADCONF_ETK_D8_ES2 0x05EC -#define CONTROL_PADCONF_ETK_D9_ES2 0x05EE -#define CONTROL_PADCONF_ETK_D10_ES2 0x05F0 -#define CONTROL_PADCONF_ETK_D11_ES2 0x05F2 -#define CONTROL_PADCONF_ETK_D12_ES2 0x05F4 -#define CONTROL_PADCONF_ETK_D13_ES2 0x05F6 -#define CONTROL_PADCONF_ETK_D14_ES2 0x05F8 -#define CONTROL_PADCONF_ETK_D15_ES2 0x05FA - -/*Die to Die */ -#define CONTROL_PADCONF_d2d_mcad0 0x01E4 -#define CONTROL_PADCONF_d2d_mcad1 0x01E6 -#define CONTROL_PADCONF_d2d_mcad2 0x01E8 -#define CONTROL_PADCONF_d2d_mcad3 0x01EA -#define CONTROL_PADCONF_d2d_mcad4 0x01EC -#define CONTROL_PADCONF_d2d_mcad5 0x01EE -#define CONTROL_PADCONF_d2d_mcad6 0x01F0 -#define CONTROL_PADCONF_d2d_mcad7 0x01F2 -#define CONTROL_PADCONF_d2d_mcad8 0x01F4 -#define CONTROL_PADCONF_d2d_mcad9 0x01F6 -#define CONTROL_PADCONF_d2d_mcad10 0x01F8 -#define CONTROL_PADCONF_d2d_mcad11 0x01FA -#define CONTROL_PADCONF_d2d_mcad12 0x01FC -#define CONTROL_PADCONF_d2d_mcad13 0x01FE -#define CONTROL_PADCONF_d2d_mcad14 0x0200 -#define CONTROL_PADCONF_d2d_mcad15 0x0202 -#define CONTROL_PADCONF_d2d_mcad16 0x0204 -#define CONTROL_PADCONF_d2d_mcad17 0x0206 -#define CONTROL_PADCONF_d2d_mcad18 0x0208 -#define CONTROL_PADCONF_d2d_mcad19 0x020A -#define CONTROL_PADCONF_d2d_mcad20 0x020C -#define CONTROL_PADCONF_d2d_mcad21 0x020E -#define CONTROL_PADCONF_d2d_mcad22 0x0210 -#define CONTROL_PADCONF_d2d_mcad23 0x0212 -#define CONTROL_PADCONF_d2d_mcad24 0x0214 -#define CONTROL_PADCONF_d2d_mcad25 0x0216 -#define CONTROL_PADCONF_d2d_mcad26 0x0218 -#define CONTROL_PADCONF_d2d_mcad27 0x021A -#define CONTROL_PADCONF_d2d_mcad28 0x021C -#define CONTROL_PADCONF_d2d_mcad29 0x021E -#define CONTROL_PADCONF_d2d_mcad30 0x0220 -#define CONTROL_PADCONF_d2d_mcad31 0x0222 -#define CONTROL_PADCONF_d2d_mcad32 0x0224 -#define CONTROL_PADCONF_d2d_mcad33 0x0226 -#define CONTROL_PADCONF_d2d_mcad34 0x0228 -#define CONTROL_PADCONF_d2d_mcad35 0x022A -#define CONTROL_PADCONF_d2d_mcad36 0x022C -#define CONTROL_PADCONF_d2d_clk26mi 0x022E -#define CONTROL_PADCONF_d2d_nrespwron 0x0230 -#define CONTROL_PADCONF_d2d_nreswarm 0x0232 -#define CONTROL_PADCONF_d2d_arm9nirq 0x0234 -#define CONTROL_PADCONF_d2d_uma2p6fiq 0x0236 -#define CONTROL_PADCONF_d2d_spint 0x0238 -#define CONTROL_PADCONF_d2d_frint 0x023A -#define CONTROL_PADCONF_d2d_dmareq0 0x023C -#define CONTROL_PADCONF_d2d_dmareq1 0x023E -#define CONTROL_PADCONF_d2d_dmareq2 0x0240 -#define CONTROL_PADCONF_d2d_dmareq3 0x0242 -#define CONTROL_PADCONF_d2d_n3gtrst 0x0244 -#define CONTROL_PADCONF_d2d_n3gtdi 0x0246 -#define CONTROL_PADCONF_d2d_n3gtdo 0x0248 -#define CONTROL_PADCONF_d2d_n3gtms 0x024A -#define CONTROL_PADCONF_d2d_n3gtck 0x024C -#define CONTROL_PADCONF_d2d_n3grtck 0x024E -#define CONTROL_PADCONF_d2d_mstdby 0x0250 -#define CONTROL_PADCONF_d2d_swakeup 0x0A4C -#define CONTROL_PADCONF_d2d_idlereq 0x0252 -#define CONTROL_PADCONF_d2d_idleack 0x0254 -#define CONTROL_PADCONF_d2d_mwrite 0x0256 -#define CONTROL_PADCONF_d2d_swrite 0x0258 -#define CONTROL_PADCONF_d2d_mread 0x025A -#define CONTROL_PADCONF_d2d_sread 0x025C -#define CONTROL_PADCONF_d2d_mbusflag 0x025E -#define CONTROL_PADCONF_d2d_sbusflag 0x0260 -#define CONTROL_PADCONF_sdrc_cke0 0x0262 -#define CONTROL_PADCONF_sdrc_cke1 0x0264 - -#endif diff --git a/x-loader/include/asm/arch-omap3/omap3430.h b/x-loader/include/asm/arch-omap3/omap3430.h deleted file mode 100644 index 117d752..0000000 --- a/x-loader/include/asm/arch-omap3/omap3430.h +++ /dev/null @@ -1,197 +0,0 @@ -/* - * (C) Copyright 2006 - * Texas Instruments, <www.ti.com> - * Richard Woodruff <r-woodruff2@ti.com> - * Syed Mohammed Khasim <x0khasim@ti.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _OMAP3430_SYS_H_ -#define _OMAP3430_SYS_H_ - -#include <asm/arch/sizes.h> - -/* - * 3430 specific Section - */ - -/* Stuff on L3 Interconnect */ -#define SMX_APE_BASE 0x68000000 - -/* L3 Firewall */ -#define A_REQINFOPERM0 (SMX_APE_BASE + 0x05048) -#define A_READPERM0 (SMX_APE_BASE + 0x05050) -#define A_WRITEPERM0 (SMX_APE_BASE + 0x05058) - -/* GPMC */ -#define OMAP34XX_GPMC_BASE (0x6E000000) - -/* SMS */ -#define OMAP34XX_SMS_BASE 0x6C000000 - -/* SDRC */ -#define OMAP34XX_SDRC_BASE 0x6D000000 - -/* - * L4 Peripherals - L4 Wakeup and L4 Core now - */ -#define OMAP34XX_CORE_L4_IO_BASE 0x48000000 - -#define OMAP34XX_WAKEUP_L4_IO_BASE 0x48300000 - -#define OMAP34XX_L4_PER 0x49000000 - -#define OMAP34XX_L4_IO_BASE OMAP34XX_CORE_L4_IO_BASE - -/* CONTROL */ -#define OMAP34XX_CTRL_BASE (OMAP34XX_L4_IO_BASE+0x2000) - -/* TAP information dont know for 3430*/ -#define OMAP34XX_TAP_BASE (0x49000000) /*giving some junk for virtio */ - -/* UART */ -#define OMAP34XX_UART1 (OMAP34XX_L4_IO_BASE+0x6a000) -#define OMAP34XX_UART2 (OMAP34XX_L4_IO_BASE+0x6c000) -#define OMAP34XX_UART3 (OMAP34XX_L4_PER+0x20000) - -/* General Purpose Timers */ -#define OMAP34XX_GPT1 0x48318000 -#define OMAP34XX_GPT2 0x49032000 -#define OMAP34XX_GPT3 0x49034000 -#define OMAP34XX_GPT4 0x49036000 -#define OMAP34XX_GPT5 0x49038000 -#define OMAP34XX_GPT6 0x4903A000 -#define OMAP34XX_GPT7 0x4903C000 -#define OMAP34XX_GPT8 0x4903E000 -#define OMAP34XX_GPT9 0x49040000 -#define OMAP34XX_GPT10 0x48086000 -#define OMAP34XX_GPT11 0x48088000 -#define OMAP34XX_GPT12 0x48304000 - -/* WatchDog Timers (1 secure, 3 GP) */ -#define WD1_BASE (0x4830C000) -#define WD2_BASE (0x48314000) -#define WD3_BASE (0x49030000) - -/* 32KTIMER */ -#define SYNC_32KTIMER_BASE (0x48320000) -#define S32K_CR (SYNC_32KTIMER_BASE+0x10) - -/* omap3 GPIO registers */ -#define OMAP34XX_GPIO1_BASE 0x48310000 -#define OMAP34XX_GPIO2_BASE 0x49050000 -#define OMAP34XX_GPIO3_BASE 0x49052000 -#define OMAP34XX_GPIO4_BASE 0x49054000 -#define OMAP34XX_GPIO5_BASE 0x49056000 -#define OMAP34XX_GPIO6_BASE 0x49058000 - -/* - * SDP3430 specific Section - */ - -/* - * The 343x's chip selects are programmable. The mask ROM - * does configure CS0 to 0x08000000 before dispatch. So, if - * you want your code to live below that address, you have to - * be prepared to jump though hoops, to reset the base address. - * Same as in SDP3430 - */ -#ifdef CONFIG_OMAP34XX -/* base address for indirect vectors (internal boot mode) */ -#define SRAM_OFFSET0 0x40000000 -#define SRAM_OFFSET1 0x00200000 -#define SRAM_OFFSET2 0x0000F800 -#define SRAM_VECT_CODE (SRAM_OFFSET0|SRAM_OFFSET1|SRAM_OFFSET2) - -#define LOW_LEVEL_SRAM_STACK 0x4020FFFC -#endif - -#if defined(CONFIG_3430SDP) || defined(CONFIG_OMAP3EVM) -/* FPGA on Debug board.*/ -#define ETH_CONTROL_REG (DEBUG_BASE+0x30b) -#define LAN_RESET_REGISTER (DEBUG_BASE+0x1c) - -#define DIP_SWITCH_INPUT_REG2 (DEBUG_BASE+0x60) -#define LED_REGISTER (DEBUG_BASE+0x40) -#define FPGA_REV_REGISTER (DEBUG_BASE+0x10) -#define EEPROM_MAIN_BRD (DEBUG_BASE+0x10000+0x1800) -#define EEPROM_CONN_BRD (DEBUG_BASE+0x10000+0x1900) -#define EEPROM_UI_BRD (DEBUG_BASE+0x10000+0x1A00) -#define EEPROM_MCAM_BRD (DEBUG_BASE+0x10000+0x1B00) -#define ENHANCED_UI_EE_NAME "750-2075" -#endif - -/* - * 343x real hardware: - * ES1 = rev 0 - * - * ES2 onwards, the value maps to contents of IDCODE register [31:28]. - * - * Note : CPU_3XX_ES20 is used in cache.S. Please review before changing. - */ -#define CPU_3XX_ES10 0 -#define CPU_3XX_ES20 1 -#define CPU_3XX_ES21 2 -#define CPU_3XX_ES30 3 -#define CPU_3XX_ES31 4 -#define CPU_3XX_ES312 7 -#define CPU_3XX_MAX_REV 8 - -#define CPU_3XX_ID_SHIFT 28 - -#define WIDTH_8BIT 0x0000 -#define WIDTH_16BIT 0x1000 /* bit pos for 16 bit in gpmc */ - -/* - * Control idcode register contains hawkeye and revision info - */ -#define CONTROL_IDCODE 0x4830A204 -#define CONTROL_OMAP_STATUS 0x4800244C - -/* - * Hawkeye values - */ -#define HAWKEYE_OMAP34XX 0xb7ae -#define HAWKEYE_AM35XX 0xb868 -#define HAWKEYE_OMAP36XX 0xb891 - -#define HAWKEYE_SHIFT 12 - -/* - * Define CPU families - */ -#define CPU_OMAP34XX 0x3400 /* OMAP34xx/OMAP35 devices */ -#define CPU_AM35XX 0x3500 /* AM35xx devices */ -#define CPU_OMAP36XX 0x3600 /* OMAP36xx devices */ - -/* - * Control status register values corresponding to cpu variants - */ -#define OMAP3503 0x5c00 -#define OMAP3515 0x1c00 -#define OMAP3525 0x4c00 -#define OMAP3530 0x0c00 - -#define AM3505 0x5c00 -#define AM3517 0x1c00 - -#define OMAP3730 0x0c00 - -#endif /* _OMAP3430_SYS_H_ */ diff --git a/x-loader/include/asm/arch-omap3/rev.h b/x-loader/include/asm/arch-omap3/rev.h deleted file mode 100755 index c0e95d4..0000000 --- a/x-loader/include/asm/arch-omap3/rev.h +++ /dev/null @@ -1,43 +0,0 @@ -/* - * (C) Copyright 2006 - * Texas Instruments, <www.ti.com> - * - * Richard Woodruff <r-woodruff2@ti.com> - * Syed Mohammed Khasim <x0khasim@ti.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _OMAP34XX_REV_H_ -#define _OMAP34XX_REV_H_ - -#define CDB_DDR_COMBO /* combo part on cpu daughter card */ -#define CDB_DDR_IPDB /* 2x16 parts on daughter card */ - -#define DDR_100 100 /* type found on most mem d-boards */ -#define DDR_111 111 /* some combo parts */ -#define DDR_133 133 /* most combo, some mem d-boards */ -#define DDR_165 165 /* future parts */ - -#define CPU_3430 0x3430 - -#define CPU_3430_ES1 1 -#define CPU_3430_ES2 1 - -#endif diff --git a/x-loader/include/asm/arch-omap3/sizes.h b/x-loader/include/asm/arch-omap3/sizes.h deleted file mode 100644 index aaba18f..0000000 --- a/x-loader/include/asm/arch-omap3/sizes.h +++ /dev/null @@ -1,49 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -/* Size defintions - * Copyright (C) ARM Limited 1998. All rights reserved. - */ - -#ifndef __sizes_h -#define __sizes_h 1 - -/* handy sizes */ -#define SZ_1K 0x00000400 -#define SZ_4K 0x00001000 -#define SZ_8K 0x00002000 -#define SZ_16K 0x00004000 -#define SZ_32K 0x00008000 -#define SZ_64K 0x00010000 -#define SZ_128K 0x00020000 -#define SZ_256K 0x00040000 -#define SZ_512K 0x00080000 - -#define SZ_1M 0x00100000 -#define SZ_2M 0x00200000 -#define SZ_4M 0x00400000 -#define SZ_8M 0x00800000 -#define SZ_16M 0x01000000 -#define SZ_31M 0x01F00000 -#define SZ_32M 0x02000000 -#define SZ_64M 0x04000000 -#define SZ_128M 0x08000000 -#define SZ_256M 0x10000000 -#define SZ_512M 0x20000000 - -#define SZ_1G 0x40000000 -#define SZ_2G 0x80000000 - -#endif /* __sizes_h */ diff --git a/x-loader/include/asm/arch-omap3/sys_info.h b/x-loader/include/asm/arch-omap3/sys_info.h deleted file mode 100644 index 18e2b49..0000000 --- a/x-loader/include/asm/arch-omap3/sys_info.h +++ /dev/null @@ -1,77 +0,0 @@ -/* - * (C) Copyright 2006 - * Texas Instruments, <www.ti.com> - * Richard Woodruff <r-woodruff2@ti.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _OMAP34XX_SYS_INFO_H_ -#define _OMAP34XX_SYS_INFO_H_ - -#define XDR_POP 5 /* package on package part */ -#define SDR_DISCRETE 4 /* 128M memory SDR module*/ -#define DDR_STACKED 3 /* stacked part on 2422 */ -#define DDR_COMBO 2 /* combo part on cpu daughter card (menalaeus) */ -#define DDR_DISCRETE 1 /* 2x16 parts on daughter card */ - -#define DDR_100 100 /* type found on most mem d-boards */ -#define DDR_111 111 /* some combo parts */ -#define DDR_133 133 /* most combo, some mem d-boards */ -#define DDR_165 165 /* future parts */ - -#define CPU_3430 0x3430 - -/* 343x real hardware: - * ES1 = rev 0 - */ - -/* 343x code defines: - * ES1 = 0+1 = 1 - * ES1 = 1+1 = 1 - */ -#define CPU_3430_ES1 1 -#define CPU_3430_ES2 2 - -/* Currently Virtio models this one */ -#define CPU_3430_CHIPID 0x0B68A000 - -#define GPMC_MUXED 1 -#define GPMC_NONMUXED 0 - -#define TYPE_NAND 0x800 /* bit pos for nand in gpmc reg */ -#define TYPE_NOR 0x000 -#define TYPE_ONENAND 0x800 - -#define WIDTH_8BIT 0x0000 -#define WIDTH_16BIT 0x1000 /* bit pos for 16 bit in gpmc */ - -#define I2C_MENELAUS 0x72 /* i2c id for companion chip */ -#define I2C_TRITON2 0x4B /* addres of power group */ - -#define BOOT_FAST_XIP 0x1f - -/* SDP definitions according to FPGA Rev. Is this OK?? */ -#define SDP_3430_V1 0x1 -#define SDP_3430_V2 0x2 - -#define BOARD_3430_LABRADOR 0x80 -#define BOARD_3430_LABRADOR_V1 0x1 - -#endif diff --git a/x-loader/include/asm/arch-omap3/sys_proto.h b/x-loader/include/asm/arch-omap3/sys_proto.h deleted file mode 100644 index 7ac53a2..0000000 --- a/x-loader/include/asm/arch-omap3/sys_proto.h +++ /dev/null @@ -1,59 +0,0 @@ -/* - * (C) Copyright 2004-2006 - * Texas Instruments, <www.ti.com> - * Richard Woodruff <r-woodruff2@ti.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#ifndef _OMAP34XX_SYS_PROTO_H_ -#define _OMAP34XX_SYS_PROTO_H_ - -void prcm_init(void); -void per_clocks_enable(void); - -void memif_init(void); -void sdrc_init(void); -void do_sdrc_init(u32,u32); -void gpmc_init(void); - -void ether_init(void); -void watchdog_init(void); -void set_muxconf_regs(void); - -u32 get_cpu_type(void); -u32 get_cpu_rev(void); -u32 cpu_is_3410(void); -u32 get_mem_type(void); -u32 get_sysboot_value(void); -u32 get_gpmc0_base(void); -u32 is_gpmc_muxed(void); -u32 get_gpmc0_type(void); -u32 get_gpmc0_width(void); -u32 get_board_type(void); -void display_board_info(u32); -void update_mux(u32,u32); -u32 get_sdr_cs_size(u32 offset); -u32 running_in_sdram(void); -u32 running_in_sram(void); -u32 running_in_flash(void); -u32 running_from_internal_boot(void); -u32 get_device_type(void); - -void sr32(u32 addr, u32 start_bit, u32 num_bits, u32 value); -u32 wait_on_value(u32 read_bit_mask, u32 match_value, u32 read_addr, u32 bound); -void sdelay(unsigned long loops); - -#endif diff --git a/x-loader/include/asm/arch-omap4/bits.h b/x-loader/include/asm/arch-omap4/bits.h deleted file mode 100644 index 541dd97..0000000 --- a/x-loader/include/asm/arch-omap4/bits.h +++ /dev/null @@ -1,48 +0,0 @@ -/* bits.h - * Copyright (c) 2004-2009 Texas Instruments - * - * This package is free software; you can redistribute it and/or - * modify it under the terms of the license found in the file - * named COPYING that should have accompanied this file. - * - * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED - * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. - */ -#ifndef __bits_h -#define __bits_h 1 - -#define BIT0 (1<<0) -#define BIT1 (1<<1) -#define BIT2 (1<<2) -#define BIT3 (1<<3) -#define BIT4 (1<<4) -#define BIT5 (1<<5) -#define BIT6 (1<<6) -#define BIT7 (1<<7) -#define BIT8 (1<<8) -#define BIT9 (1<<9) -#define BIT10 (1<<10) -#define BIT11 (1<<11) -#define BIT12 (1<<12) -#define BIT13 (1<<13) -#define BIT14 (1<<14) -#define BIT15 (1<<15) -#define BIT16 (1<<16) -#define BIT17 (1<<17) -#define BIT18 (1<<18) -#define BIT19 (1<<19) -#define BIT20 (1<<20) -#define BIT21 (1<<21) -#define BIT22 (1<<22) -#define BIT23 (1<<23) -#define BIT24 (1<<24) -#define BIT25 (1<<25) -#define BIT26 (1<<26) -#define BIT27 (1<<27) -#define BIT28 (1<<28) -#define BIT29 (1<<29) -#define BIT30 (1<<30) -#define BIT31 (1<<31) - -#endif diff --git a/x-loader/include/asm/arch-omap4/clocks.h b/x-loader/include/asm/arch-omap4/clocks.h deleted file mode 100644 index a65cbda..0000000 --- a/x-loader/include/asm/arch-omap4/clocks.h +++ /dev/null @@ -1,36 +0,0 @@ -/* - * (C) Copyright 2006-2009 - * Texas Instruments, <www.ti.com> - * Richard Woodruff <r-woodruff2@ti.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#ifndef _OMAP44XX_CLOCKS_H_ -#define _OMAP44XX_CLOCKS_H_ - -#define LDELAY 12000000 - -#define S12M 12000000 -#define S13M 13000000 -#define S16_8M 16800000 -#define S19_2M 19200000 -#define S24M 24000000 -#define S26M 26000000 -#define S27M 27000000 -#define S38_4M 38400000 - -#include <asm/arch/clocks443x.h> - -#endif diff --git a/x-loader/include/asm/arch-omap4/clocks443x.h b/x-loader/include/asm/arch-omap4/clocks443x.h deleted file mode 100644 index 63280f7..0000000 --- a/x-loader/include/asm/arch-omap4/clocks443x.h +++ /dev/null @@ -1,154 +0,0 @@ -/* - * (C) Copyright 2006-2009 - * Texas Instruments, <www.ti.com> - * Richard Woodruff <r-woodruff2@ti.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#ifndef _OMAP443X_CLOCKS_H_ -#define _OMAP443X_CLOCKS_H_ - -#define PLL_STOP 1 /* PER & IVA */ -#define PLL_MN_POWER_BYPASS 4 -#define PLL_LOW_POWER_BYPASS 5 /* MPU, IVA & CORE */ -#define PLL_FAST_RELOCK_BYPASS 6 /* CORE */ -#define PLL_LOCK 7 /* MPU, IVA, CORE & PER */ - -/* The following configurations are OPP and SysClk value independant - * and hence are defined here. All the other DPLL related values are - * tabulated in lowlevel_init.S. - */ - -/* CORE DPLL */ -# define CORE_M3X2 2 /* 332MHz : CM_CLKSEL1_EMU */ -# define CORE_SSI_DIV 3 /* 221MHz : CM_CLKSEL_CORE */ -# define CORE_FUSB_DIV 2 /* 41.5MHz: */ -# define CORE_L4_DIV 2 /* 83MHz : L4 */ -# define CORE_L3_DIV 2 /* 166MHz : L3 {DDR} */ -# define GFX_DIV 2 /* 83MHz : CM_CLKSEL_GFX */ -# define WKUP_RSM 2 /* 41.5MHz: CM_CLKSEL_WKUP */ - -/* PER DPLL */ -# define PER_M6X2 3 /* 288MHz: CM_CLKSEL1_EMU */ -# define PER_M5X2 4 /* 216MHz: CM_CLKSEL_CAM */ -# define PER_M4X2 9 /* 96MHz : CM_CLKSEL_DSS-dss1 */ -# define PER_M3X2 16 /* 54MHz : CM_CLKSEL_DSS-tv */ - -# define CLSEL1_EMU_VAL ((CORE_M3X2 << 16) | (PER_M6X2 << 24) | (0x0a50)) - -#ifdef PRCM_CLK_CFG2_332MHZ -# define M_12 0xA6 -# define N_12 0x05 -# define FSEL_12 0x07 -# define M2_12 0x01 /* M3 of 2 */ - -# define M_12_ES1 0x0E -# define FSL_12_ES1 0x03 -# define M2_12_ES1 0x1 /* M3 of 2 */ - -# define M_13 0x14C -# define N_13 0x0C -# define FSEL_13 0x03 -# define M2_13 0x01 /* M3 of 2 */ - -# define M_13_ES1 0x1B2 -# define N_13_ES1 0x10 -# define FSL_13_ES1 0x03 -# define M2_13_ES1 0x01 /* M3 of 2 */ - -# define M_19p2 0x19F -# define N_19p2 0x17 -# define FSEL_19p2 0x03 -# define M2_19p2 0x01 /* M3 of 2 */ - -# define M_19p2_ES1 0x19F -# define N_19p2_ES1 0x17 -# define FSL_19p2_ES1 0x03 -# define M2_19p2_ES1 0x01 /* M3 of 2 */ - -# define M_26 0xA6 -# define N_26 0x0C -# define FSEL_26 0x07 -# define M2_26 0x01 /* M3 of 2 */ - -# define M_26_ES1 0x1B2 -# define N_26_ES1 0x21 -# define FSL_26_ES1 0x03 -# define M2_26_ES1 0x01 /* M3 of 2 */ - -# define M_38p4 0x19F -# define N_38p4 0x2F -# define FSEL_38p4 0x03 -# define M2_38p4 0x01 /* M3 of 2 */ - -# define M_38p4_ES1 0x19F -# define N_38p4_ES1 0x2F -# define FSL_38p4_ES1 0x03 -# define M2_38p4_ES1 0x01 /* M3 of 2 */ - -#elif defined(PRCM_CLK_CFG2_266MHZ) -# define M_12 0x85 -# define N_12 0x05 -# define FSEL_12 0x07 -# define M2_12 0x02 /* M3 of 2 */ - -# define M_12_ES1 0x85 /* 0x10A */ -# define N_12_ES1 0x05 /* 0x05 */ -# define FSL_12_ES1 0x07 /* 0x7 */ -# define M2_12_ES1 0x2 /* 0x2 with an M3 of 4*/ - -# define M_13 0x10A -# define N_13 0x0C -# define FSEL_13 0x3 -# define M2_13 0x1 /* M3 of 2 */ - -# define M_13_ES1 0x10A /* 0x214 */ -# define N_13_ES1 0x0C /* 0xC */ -# define FSL_13_ES1 0x3 /* 0x3 */ -# define M2_13_ES1 0x1 /* 0x2 with an M3 of 4*/ - -# define M_19p2 0x115 -# define N_19p2 0x13 -# define FSEL_19p2 0x03 -# define M2_19p2 0x01 /* M3 of 2 */ - -# define M_19p2_ES1 0x115 /* 0x299 */ -# define N_19p2_ES1 0x13 /* 0x17 */ -# define FSL_19p2_ES1 0x03 /* 0x03 */ -# define M2_19p2_ES1 0x01 /* 0x2 with M3 of 4 */ - -# define M_26 0x85 -# define N_26 0x0C -# define FSEL_26 0x07 -# define M2_26 0x01 /* M3 of 2 */ - -# define M_26_ES1 0x85 /* 0x10A */ -# define N_26_ES1 0x0C /* 0xC */ -# define FSL_26_ES1 0x07 /* 0x7 */ -# define M2_26_ES1 0x01 /* 0x2 with an M3 of 4 */ - -# define M_38p4 0x11C -# define N_38p4 0x28 -# define FSEL_38p4 0x03 -# define M2_38p4 0x01 /* M3 of 2 */ - -# define M_38p4_ES1 0x11C /* 0x299 */ -# define N_38p4_ES1 0x28 /* 0x2f */ -# define FSL_38p4_ES1 0x03 /* 0x3 */ -# define M2_38p4_ES1 0x01 /* 0x2 with an M3 of 4*/ - -#endif - -#endif /* endif _OMAP443X_CLOCKS_H_ */ diff --git a/x-loader/include/asm/arch-omap4/cpu.h b/x-loader/include/asm/arch-omap4/cpu.h deleted file mode 100644 index 94aeb9f..0000000 --- a/x-loader/include/asm/arch-omap4/cpu.h +++ /dev/null @@ -1,464 +0,0 @@ -/* - * (C) Copyright 2006-2009 - * Texas Instruments, <www.ti.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - */ - -#ifndef _OMAP44XX_CPU_H -#define _OMAP44XX_CPU_H -#include <asm/arch/omap4430.h> - -/* Register offsets of common modules */ -/* Control */ -#define CONTROL_STATUS (OMAP44XX_CTRL_BASE + 0x2F0) -#define OMAP44XX_MCR (OMAP44XX_CTRL_BASE + 0x8C) -#define CONTROL_SCALABLE_OMAP_STATUS (OMAP44XX_CTRL_BASE + 0x44C) -#define CONTROL_SCALABLE_OMAP_OCP (OMAP44XX_CTRL_BASE + 0x534) - - -/* Tap Information */ -#define TAP_IDCODE_REG (OMAP44XX_TAP_BASE+0x204) -#define PRODUCTION_ID (OMAP44XX_TAP_BASE+0x208) - -/* device type */ -#define DEVICE_MASK (BIT8|BIT9|BIT10) -#define TST_DEVICE 0x0 -#define EMU_DEVICE 0x1 -#define HS_DEVICE 0x2 -#define GP_DEVICE 0x3 - -/* GPMC CS3/cs4/cs6 not avaliable */ -#define GPMC_BASE (OMAP44XX_GPMC_BASE) -#define GPMC_SYSCONFIG (OMAP44XX_GPMC_BASE+0x10) -#define GPMC_IRQSTATUS (OMAP44XX_GPMC_BASE+0x18) -#define GPMC_IRQENABLE (OMAP44XX_GPMC_BASE+0x1C) -#define GPMC_TIMEOUT_CONTROL (OMAP44XX_GPMC_BASE+0x40) -#define GPMC_CONFIG (OMAP44XX_GPMC_BASE+0x50) -#define GPMC_STATUS (OMAP44XX_GPMC_BASE+0x54) - -#define GPMC_CONFIG_CS0 (OMAP44XX_GPMC_BASE+0x60) -#define GPMC_CONFIG_WIDTH (0x30) - -#define GPMC_CONFIG1 (0x00) -#define GPMC_CONFIG2 (0x04) -#define GPMC_CONFIG3 (0x08) -#define GPMC_CONFIG4 (0x0C) -#define GPMC_CONFIG5 (0x10) -#define GPMC_CONFIG6 (0x14) -#define GPMC_CONFIG7 (0x18) -#define GPMC_NAND_CMD (0x1C) -#define GPMC_NAND_ADR (0x20) -#define GPMC_NAND_DAT (0x24) - -#define GPMC_ECC_CONFIG (0x1F4) -#define GPMC_ECC_CONTROL (0x1F8) -#define GPMC_ECC_SIZE_CONFIG (0x1FC) -#define GPMC_ECC1_RESULT (0x200) -#define GPMC_ECC2_RESULT (0x204) -#define GPMC_ECC3_RESULT (0x208) -#define GPMC_ECC4_RESULT (0x20C) -#define GPMC_ECC5_RESULT (0x210) -#define GPMC_ECC6_RESULT (0x214) -#define GPMC_ECC7_RESULT (0x218) -#define GPMC_ECC8_RESULT (0x21C) -#define GPMC_ECC9_RESULT (0x220) - -#define GPMC_PREFETCH_CONFIG1 (0x1e0) -#define GPMC_PREFETCH_CONFIG2 (0x1e4) -#define GPMC_PREFETCH_CONTROL (0x1ec) -#define GPMC_PREFETCH_STATUS (0x1f0) - -/* GPMC Mapping */ -# define FLASH_BASE 0x10000000 /* NOR flash (aligned to 256 Meg) */ -# define FLASH_BASE_SDPV1 0x04000000 /* NOR flash (aligned to 64 Meg) */ -# define FLASH_BASE_SDPV2 0x10000000 /* NOR flash (aligned to 256 Meg) */ -# define DEBUG_BASE 0x08000000 /* debug board */ -# define NAND_BASE 0x30000000 /* NAND addr (actual size small port)*/ -# define PISMO2_BASE 0x18000000 /* PISMO2 CS1/2 */ -# define ONENAND_MAP 0x20000000 /* OneNand addr (actual size small port */ - -/* DMM */ -#define DMM_SYSCONFIG (OMAP44XX_DMM_BASE+0x10) -#define DMM_LISA_MAP (OMAP44XX_DMM_BASE+0x100) - -/* SMS */ -#define SMS_SYSCONFIG (OMAP44XX_SMS_BASE+0x10) -#define SMS_RG_ATT0 (OMAP44XX_SMS_BASE+0x48) -#define SMS_CLASS_ARB0 (OMAP44XX_SMS_BASE+0xD0) -#define BURSTCOMPLETE_GROUP7 BIT31 - -#define SDRC_CS_CFG (OMAP44XX_SDRC_BASE+0x40) -#define OMAP44XX_SDRC_CS0 0x80000000 -#define SDRC_POWER (OMAP44XX_SDRC_BASE+0x70) -#define SDRC_MCFG_0 (OMAP44XX_SDRC_BASE+0x80) -#define SDRC_MR_0 (OMAP44XX_SDRC_BASE+0x84) - -/* timer regs offsets (32 bit regs) */ -#define TIDR 0x0 /* r */ -#define TIOCP_CFG 0x10 /* rw */ -#define TISTAT 0x14 /* r */ -#define TISR 0x18 /* rw */ -#define TIER 0x1C /* rw */ -#define TWER 0x20 /* rw */ -#define TCLR 0x24 /* rw */ -#define TCRR 0x28 /* rw */ -#define TLDR 0x2C /* rw */ -#define TTGR 0x30 /* rw */ -#define TWPS 0x34 /* r */ -#define TMAR 0x38 /* rw */ -#define TCAR1 0x3c /* r */ -#define TSICR 0x40 /* rw */ -#define TCAR2 0x44 /* r */ -#define GPT_EN ((0<<2)|BIT1|BIT0) /* enable sys_clk NO-prescale /1 */ - -/* Watchdog */ -#define WWPS 0x34 /* r */ -#define WSPR 0x48 /* rw */ -#define WD_UNLOCK1 0xAAAA -#define WD_UNLOCK2 0x5555 - -/* FIXME */ -#define PRM_RSTCTRL 0x48307250 - /* PRCM */ -#define CM_SYS_CLKSEL 0x4a306110 - -/* PRM.CKGEN module registers */ -#define CM_ABE_PLL_REF_CLKSEL 0x4a30610c - - -/* PRM.WKUP_CM module registers */ -#define CM_WKUP_CLKSTCTRL 0x4a307800 -#define CM_WKUP_L4WKUP_CLKCTRL 0x4a307820 -#define CM_WKUP_WDT1_CLKCTRL 0x4a307828 -#define CM_WKUP_WDT2_CLKCTRL 0x4a307830 -#define CM_WKUP_GPIO1_CLKCTRL 0x4a307838 -#define CM_WKUP_TIMER1_CLKCTRL 0x4a307840 -#define CM_WKUP_TIMER12_CLKCTRL 0x4a307848 -#define CM_WKUP_SYNCTIMER_CLKCTRL 0x4a307850 -#define CM_WKUP_USIM_CLKCTRL 0x4a307858 -#define CM_WKUP_SARRAM_CLKCTRL 0x4a307860 -#define CM_WKUP_KEYBOARD_CLKCTRL 0x4a307878 -#define CM_WKUP_RTC_CLKCTRL 0x4a307880 -#define CM_WKUP_BANDGAP_CLKCTRL 0x4a307888 - -/* CM1.CKGEN module registers */ -#define CM_CLKSEL_CORE 0x4a004100 -#define CM_CLKSEL_ABE 0x4a004108 -#define CM_DLL_CTRL 0x4a004110 -#define CM_CLKMODE_DPLL_CORE 0x4a004120 -#define CM_IDLEST_DPLL_CORE 0x4a004124 -#define CM_AUTOIDLE_DPLL_CORE 0x4a004128 -#define CM_CLKSEL_DPLL_CORE 0x4a00412c -#define CM_DIV_M2_DPLL_CORE 0x4a004130 -#define CM_DIV_M3_DPLL_CORE 0x4a004134 -#define CM_DIV_M4_DPLL_CORE 0x4a004138 -#define CM_DIV_M5_DPLL_CORE 0x4a00413c -#define CM_DIV_M6_DPLL_CORE 0x4a004140 -#define CM_DIV_M7_DPLL_CORE 0x4a004144 -#define CM_SSC_DELTAMSTEP_DPLL_CORE 0x4a004148 -#define CM_SSC_MODFREQDIV_DPLL_CORE 0x4a00414c -#define CM_EMU_OVERRIDE_DPLL_CORE 0x4a004150 -#define CM_CLKMODE_DPLL_MPU 0x4a004160 -#define CM_IDLEST_DPLL_MPU 0x4a004164 -#define CM_AUTOIDLE_DPLL_MPU 0x4a004168 -#define CM_CLKSEL_DPLL_MPU 0x4a00416c -#define CM_DIV_M2_DPLL_MPU 0x4a004170 -#define CM_SSC_DELTAMSTEP_DPLL_MPU 0x4a004188 -#define CM_SSC_MODFREQDIV_DPLL_MPU 0x4a00418c -#define CM_BYPCLK_DPLL_MPU 0x4a00419c -#define CM_CLKMODE_DPLL_IVA 0x4a0041a0 -#define CM_IDLEST_DPLL_IVA 0x4a0041a4 -#define CM_AUTOIDLE_DPLL_IVA 0x4a0041a8 -#define CM_CLKSEL_DPLL_IVA 0x4a0041ac -#define CM_DIV_M4_DPLL_IVA 0x4a0041b8 -#define CM_DIV_M5_DPLL_IVA 0x4a0041bc -#define CM_SSC_DELTAMSTEP_DPLL_IVA 0x4a0041c8 -#define CM_SSC_MODFREQDIV_DPLL_IVA 0x4a0041cc -#define CM_BYPCLK_DPLL_IVA 0x4a0041dc -#define CM_CLKMODE_DPLL_ABE 0x4a0041e0 -#define CM_IDLEST_DPLL_ABE 0x4a0041e4 -#define CM_AUTOIDLE_DPLL_ABE 0x4a0041e8 -#define CM_CLKSEL_DPLL_ABE 0x4a0041ec -#define CM_DIV_M2_DPLL_ABE 0x4a0041f0 -#define CM_DIV_M3_DPLL_ABE 0x4a0041f4 -#define CM_SSC_DELTAMSTEP_DPLL_ABE 0x4a004208 -#define CM_SSC_MODFREQDIV_DPLL_ABE 0x4a00420c -#define CM_CLKMODE_DPLL_DDRPHY 0x4a004220 -#define CM_IDLEST_DPLL_DDRPHY 0x4a004224 -#define CM_AUTOIDLE_DPLL_DDRPHY 0x4a004228 -#define CM_CLKSEL_DPLL_DDRPHY 0x4a00422c -#define CM_DIV_M2_DPLL_DDRPHY 0x4a004230 -#define CM_DIV_M4_DPLL_DDRPHY 0x4a004238 -#define CM_DIV_M5_DPLL_DDRPHY 0x4a00423c -#define CM_DIV_M6_DPLL_DDRPHY 0x4a004240 -#define CM_SSC_DELTAMSTEP_DPLL_DDRPHY 0x4a004248 - -/* CM1.ABE register offsets */ -#define CM1_ABE_CLKSTCTRL 0x4a004500 -#define CM1_ABE_L4ABE_CLKCTRL 0x4a004520 -#define CM1_ABE_AESS_CLKCTRL 0x4a004528 -#define CM1_ABE_PDM_CLKCTRL 0x4a004530 -#define CM1_ABE_DMIC_CLKCTRL 0x4a004538 -#define CM1_ABE_MCASP_CLKCTRL 0x4a004540 -#define CM1_ABE_MCBSP1_CLKCTRL 0x4a004548 -#define CM1_ABE_MCBSP2_CLKCTRL 0x4a004550 -#define CM1_ABE_MCBSP3_CLKCTRL 0x4a004558 -#define CM1_ABE_SLIMBUS_CLKCTRL 0x4a004560 -#define CM1_ABE_TIMER5_CLKCTRL 0x4a004568 -#define CM1_ABE_TIMER6_CLKCTRL 0x4a004570 -#define CM1_ABE_TIMER7_CLKCTRL 0x4a004578 -#define CM1_ABE_TIMER8_CLKCTRL 0x4a004580 -#define CM1_ABE_WDT3_CLKCTRL 0x4a004588 - -/* CM1.DSP register offsets */ -#define DSP_CLKSTCTRL 0x4a004400 -#define DSP_DSP_CLKCTRL 0x4a004420 - -/* CM2.CKGEN module registers */ -#define CM_CLKSEL_DUCATI_ISS_ROOT 0x4a008100 -#define CM_CLKSEL_USB_60MHz 0x4a008104 -#define CM_SCALE_FCLK 0x4a008108 -#define CM_CORE_DVFS_PERF1 0x4a008110 -#define CM_CORE_DVFS_PERF2 0x4a008114 -#define CM_CORE_DVFS_PERF3 0x4a008118 -#define CM_CORE_DVFS_PERF4 0x4a00811c -#define CM_CORE_DVFS_CURRENT 0x4a008124 -#define CM_IVA_DVFS_PERF_TESLA 0x4a008128 -#define CM_IVA_DVFS_PERF_IVAHD 0x4a00812c -#define CM_IVA_DVFS_PERF_ABE 0x4a008130 -#define CM_IVA_DVFS_CURRENT 0x4a008138 -#define CM_CLKMODE_DPLL_PER 0x4a008140 -#define CM_IDLEST_DPLL_PER 0x4a008144 -#define CM_AUTOIDLE_DPLL_PER 0x4a008148 -#define CM_CLKSEL_DPLL_PER 0x4a00814c -#define CM_DIV_M2_DPLL_PER 0x4a008150 -#define CM_DIV_M3_DPLL_PER 0x4a008154 -#define CM_DIV_M4_DPLL_PER 0x4a008158 -#define CM_DIV_M5_DPLL_PER 0x4a00815c -#define CM_DIV_M6_DPLL_PER 0x4a008160 -#define CM_DIV_M7_DPLL_PER 0x4a008164 -#define CM_SSC_DELTAMSTEP_DPLL_PER 0x4a008168 -#define CM_SSC_MODFREQDIV_DPLL_PER 0x4a00816c -#define CM_EMU_OVERRIDE_DPLL_PER 0x4a008170 -#define CM_CLKMODE_DPLL_USB 0x4a008180 -#define CM_IDLEST_DPLL_USB 0x4a008184 -#define CM_AUTOIDLE_DPLL_USB 0x4a008188 -#define CM_CLKSEL_DPLL_USB 0x4a00818c -#define CM_DIV_M2_DPLL_USB 0x4a008190 -#define CM_SSC_DELTAMSTEP_DPLL_USB 0x4a0081a8 -#define CM_SSC_MODFREQDIV_DPLL_USB 0x4a0081ac -#define CM_CLKDCOLDO_DPLL_USB 0x4a0081b4 -#define CM_CLKMODE_DPLL_UNIPRO 0x4a0081c0 -#define CM_IDLEST_DPLL_UNIPRO 0x4a0081c4 -#define CM_AUTOIDLE_DPLL_UNIPRO 0x4a0081c8 -#define CM_CLKSEL_DPLL_UNIPRO 0x4a0081cc -#define CM_DIV_M2_DPLL_UNIPRO 0x4a0081d0 -#define CM_SSC_DELTAMSTEP_DPLL_UNIPRO 0x4a0081e8 -#define CM_SSC_MODFREQDIV_DPLL_UNIPRO 0x4a0081ec - -/* CM2.CORE module registers */ -#define CM_L3_1_CLKSTCTRL 0x4a008700 -#define CM_L3_1_DYNAMICDEP 0x4a008708 -#define CM_L3_1_L3_1_CLKCTRL 0x4a008720 -#define CM_L3_2_CLKSTCTRL 0x4a008800 -#define CM_L3_2_DYNAMICDEP 0x4a008808 -#define CM_L3_2_L3_2_CLKCTRL 0x4a008820 -#define CM_L3_2_GPMC_CLKCTRL 0x4a008828 -#define CM_L3_2_OCMC_RAM_CLKCTRL 0x4a008830 -#define CM_DUCATI_CLKSTCTRL 0x4a008900 -#define CM_DUCATI_STATICDEP 0x4a008904 -#define CM_DUCATI_DYNAMICDEP 0x4a008908 -#define CM_DUCATI_DUCATI_CLKCTRL 0x4a008920 -#define CM_SDMA_CLKSTCTRL 0x4a008a00 -#define CM_SDMA_STATICDEP 0x4a008a04 -#define CM_SDMA_DYNAMICDEP 0x4a008a08 -#define CM_SDMA_SDMA_CLKCTRL 0x4a008a20 -#define CM_MEMIF_CLKSTCTRL 0x4a008b00 -#define CM_MEMIF_DMM_CLKCTRL 0x4a008b20 -#define CM_MEMIF_EMIF_FW_CLKCTRL 0x4a008b28 -#define CM_MEMIF_EMIF_1_CLKCTRL 0x4a008b30 -#define CM_MEMIF_EMIF_2_CLKCTRL 0x4a008b38 -#define CM_MEMIF_DLL_CLKCTRL 0x4a008b40 -#define CM_MEMIF_EMIF_H1_CLKCTRL 0x4a008b50 -#define CM_MEMIF_EMIF_H2_CLKCTRL 0x4a008b58 -#define CM_MEMIF_DLL_H_CLKCTRL 0x4a008b60 -#define CM_D2D_CLKSTCTRL 0x4a008c00 -#define CM_D2D_STATICDEP 0x4a008c04 -#define CM_D2D_DYNAMICDEP 0x4a008c08 -#define CM_D2D_SAD2D_CLKCTRL 0x4a008c20 -#define CM_D2D_MODEM_ICR_CLKCTRL 0x4a008c28 -#define CM_D2D_SAD2D_FW_CLKCTRL 0x4a008c30 -#define CM_L4CFG_CLKSTCTRL 0x4a008d00 -#define CM_L4CFG_DYNAMICDEP 0x4a008d08 -#define CM_L4CFG_L4_CFG_CLKCTRL 0x4a008d20 -#define CM_L4CFG_HW_SEM_CLKCTRL 0x4a008d28 -#define CM_L4CFG_MAILBOX_CLKCTRL 0x4a008d30 -#define CM_L4CFG_SAR_ROM_CLKCTRL 0x4a008d38 -#define CM_L3INSTR_CLKSTCTRL 0x4a008e00 -#define CM_L3INSTR_L3_3_CLKCTRL 0x4a008e20 -#define CM_L3INSTR_L3_INSTR_CLKCTRL 0x4a008e28 -#define CM_L3INSTR_OCP_WP1_CLKCTRL 0x4a008e40 - -/* CM2.L4PER register offsets */ -#define CM_L4PER_CLKSTCTRL 0x4a009400 -#define CM_L4PER_DYNAMICDEP 0x4a009408 -#define CM_L4PER_ADC_CLKCTRL 0x4a009420 -#define CM_L4PER_DMTIMER10_CLKCTRL 0x4a009428 -#define CM_L4PER_DMTIMER11_CLKCTRL 0x4a009430 -#define CM_L4PER_DMTIMER2_CLKCTRL 0x4a009438 -#define CM_L4PER_DMTIMER3_CLKCTRL 0x4a009440 -#define CM_L4PER_DMTIMER4_CLKCTRL 0x4a009448 -#define CM_L4PER_DMTIMER9_CLKCTRL 0x4a009450 -#define CM_L4PER_ELM_CLKCTRL 0x4a009458 -#define CM_L4PER_GPIO2_CLKCTRL 0x4a009460 -#define CM_L4PER_GPIO3_CLKCTRL 0x4a009468 -#define CM_L4PER_GPIO4_CLKCTRL 0x4a009470 -#define CM_L4PER_GPIO5_CLKCTRL 0x4a009478 -#define CM_L4PER_GPIO6_CLKCTRL 0x4a009480 -#define CM_L4PER_HDQ1W_CLKCTRL 0x4a009488 -#define CM_L4PER_HECC1_CLKCTRL 0x4a009490 -#define CM_L4PER_HECC2_CLKCTRL 0x4a009498 -#define CM_L4PER_I2C1_CLKCTRL 0x4a0094a0 -#define CM_L4PER_I2C2_CLKCTRL 0x4a0094a8 -#define CM_L4PER_I2C3_CLKCTRL 0x4a0094b0 -#define CM_L4PER_I2C4_CLKCTRL 0x4a0094b8 -#define CM_L4PER_L4PER_CLKCTRL 0x4a0094c0 -#define CM_L4PER_MCASP2_CLKCTRL 0x4a0094d0 -#define CM_L4PER_MCASP3_CLKCTRL 0x4a0094d8 -#define CM_L4PER_MCBSP4_CLKCTRL 0x4a0094e0 -#define CM_L4PER_MGATE_CLKCTRL 0x4a0094e8 -#define CM_L4PER_MCSPI1_CLKCTRL 0x4a0094f0 -#define CM_L4PER_MCSPI2_CLKCTRL 0x4a0094f8 -#define CM_L4PER_MCSPI3_CLKCTRL 0x4a009500 -#define CM_L4PER_MCSPI4_CLKCTRL 0x4a009508 -#define CM_L4PER_MMCSD3_CLKCTRL 0x4a009520 -#define CM_L4PER_MMCSD4_CLKCTRL 0x4a009528 -#define CM_L4PER_MSPROHG_CLKCTRL 0x4a009530 -#define CM_L4PER_SLIMBUS2_CLKCTRL 0x4a009538 -#define CM_L4PER_UART1_CLKCTRL 0x4a009540 -#define CM_L4PER_UART2_CLKCTRL 0x4a009548 -#define CM_L4PER_UART3_CLKCTRL 0x4a009550 -#define CM_L4PER_UART4_CLKCTRL 0x4a009558 -#define CM_L4PER_MMCSD5_CLKCTRL 0x4a009560 -#define CM_L4PER_I2C5_CLKCTRL 0x4a009568 -#define CM_L4SEC_CLKSTCTRL 0x4a009580 -#define CM_L4SEC_STATICDEP 0x4a009584 -#define CM_L4SEC_DYNAMICDEP 0x4a009588 -#define CM_L4SEC_AES1_CLKCTRL 0x4a0095a0 -#define CM_L4SEC_AES2_CLKCTRL 0x4a0095a8 -#define CM_L4SEC_DES3DES_CLKCTRL 0x4a0095b0 -#define CM_L4SEC_PKAEIP29_CLKCTRL 0x4a0095b8 -#define CM_L4SEC_RNG_CLKCTRL 0x4a0095c0 -#define CM_L4SEC_SHA2MD51_CLKCTRL 0x4a0095c8 -#define CM_L4SEC_CRYPTODMA_CLKCTRL 0x4a0095d8 - -/* CM2.IVAHD */ -#define IVAHD_CLKSTCTRL 0x4a008f00 -#define IVAHD_IVAHD_CLKCTRL 0x4a008f20 -#define IVAHD_SL2_CLKCTRL 0x4a008f28 - -/* CM2.L3INIT */ -#define CM_L3INIT_HSMMC1_CLKCTRL 0x4a009328 -#define CM_L3INIT_HSMMC2_CLKCTRL 0x4a009330 -#define CM_L3INIT_HSI_CLKCTRL 0x4a009338 -#define CM_L3INIT_UNIPRO1_CLKCTRL 0x4a009340 -#define CM_L3INIT_HSUSBHOST_CLKCTRL 0x4a009358 -#define CM_L3INIT_HSUSBOTG_CLKCTRL 0x4a009360 -#define CM_L3INIT_HSUSBTLL_CLKCTRL 0x4a009368 -#define CM_L3INIT_P1500_CLKCTRL 0x4a009378 -#define CM_L3INIT_FSUSB_CLKCTRL 0x4a0093d0 -#define CM_L3INIT_USBPHY_CLKCTRL 0x4a0093e0 - -/* CM2.CAM */ -#define CM_CAM_CLKSTCTRL 0x4a009000 -#define CM_CAM_ISS_CLKCTRL 0x4a009020 -#define CM_CAM_FDIF_CLKCTRL 0x4a009028 - -/* CM2.DSS */ -#define CM_DSS_CLKSTCTRL 0x4a009100 -#define CM_DSS_DSS_CLKCTRL 0x4a009120 -#define CM_DSS_DEISS_CLKCTRL 0x4a009128 - -/* CM2.SGX */ -#define CM_SGX_CLKSTCTRL 0x4a009200 -#define CM_SGX_SGX_CLKCTRL 0x4a009220 - -/* SMX-APE */ -#define PM_RT_APE_BASE_ADDR_ARM (SMX_APE_BASE + 0x10000) -#define PM_GPMC_BASE_ADDR_ARM (SMX_APE_BASE + 0x12400) -#define PM_OCM_RAM_BASE_ADDR_ARM (SMX_APE_BASE + 0x12800) -#define PM_OCM_ROM_BASE_ADDR_ARM (SMX_APE_BASE + 0x12C00) -#define PM_IVA2_BASE_ADDR_ARM (SMX_APE_BASE + 0x14000) - -#define RT_REQ_INFO_PERMISSION_1 (PM_RT_APE_BASE_ADDR_ARM + 0x68) -#define RT_READ_PERMISSION_0 (PM_RT_APE_BASE_ADDR_ARM + 0x50) -#define RT_WRITE_PERMISSION_0 (PM_RT_APE_BASE_ADDR_ARM + 0x58) -#define RT_ADDR_MATCH_1 (PM_RT_APE_BASE_ADDR_ARM + 0x60) - -#define GPMC_REQ_INFO_PERMISSION_0 (PM_GPMC_BASE_ADDR_ARM + 0x48) -#define GPMC_READ_PERMISSION_0 (PM_GPMC_BASE_ADDR_ARM + 0x50) -#define GPMC_WRITE_PERMISSION_0 (PM_GPMC_BASE_ADDR_ARM + 0x58) - -#define OCM_REQ_INFO_PERMISSION_0 (PM_OCM_RAM_BASE_ADDR_ARM + 0x48) -#define OCM_READ_PERMISSION_0 (PM_OCM_RAM_BASE_ADDR_ARM + 0x50) -#define OCM_WRITE_PERMISSION_0 (PM_OCM_RAM_BASE_ADDR_ARM + 0x58) -#define OCM_ADDR_MATCH_2 (PM_OCM_RAM_BASE_ADDR_ARM + 0x80) - -#define IVA2_REQ_INFO_PERMISSION_0 (PM_IVA2_BASE_ADDR_ARM + 0x48) -#define IVA2_READ_PERMISSION_0 (PM_IVA2_BASE_ADDR_ARM + 0x50) -#define IVA2_WRITE_PERMISSION_0 (PM_IVA2_BASE_ADDR_ARM + 0x58) - -#define IVA2_REQ_INFO_PERMISSION_1 (PM_IVA2_BASE_ADDR_ARM + 0x68) -#define IVA2_READ_PERMISSION_1 (PM_IVA2_BASE_ADDR_ARM + 0x70) -#define IVA2_WRITE_PERMISSION_1 (PM_IVA2_BASE_ADDR_ARM + 0x78) - -#define IVA2_REQ_INFO_PERMISSION_2 (PM_IVA2_BASE_ADDR_ARM + 0x88) -#define IVA2_READ_PERMISSION_2 (PM_IVA2_BASE_ADDR_ARM + 0x90) -#define IVA2_WRITE_PERMISSION_2 (PM_IVA2_BASE_ADDR_ARM + 0x98) - -#define IVA2_REQ_INFO_PERMISSION_3 (PM_IVA2_BASE_ADDR_ARM + 0xA8) -#define IVA2_READ_PERMISSION_3 (PM_IVA2_BASE_ADDR_ARM + 0xB0) -#define IVA2_WRITE_PERMISSION_3 (PM_IVA2_BASE_ADDR_ARM + 0xB8) - -/* I2C base */ -#define I2C_BASE1 (OMAP44XX_L4_PER + 0x70000) -#define I2C_BASE2 (OMAP44XX_L4_PER + 0x72000) -#define I2C_BASE3 (OMAP44XX_L4_PER + 0x60000) - -#ifdef CONFIG_LCD - extern void lcd_disable(void); - extern void lcd_panel_disable(void); -#endif - -/* Silicon revisions */ -#define OMAP4430_SILICON_ID_INVALID 0 -#define OMAP4430_ES1_0 1 -#define OMAP4430_ES2_0 2 -#define OMAP4430_ES2_1 3 - -#ifndef __ASSEMBLY__ -/*Functions for silicon revision */ -unsigned int omap_revision(void); -unsigned int cortex_a9_rev(void); - -void big_delay(unsigned int count); -#endif - -#endif diff --git a/x-loader/include/asm/arch-omap4/mem.h b/x-loader/include/asm/arch-omap4/mem.h deleted file mode 100644 index e277eca..0000000 --- a/x-loader/include/asm/arch-omap4/mem.h +++ /dev/null @@ -1,285 +0,0 @@ -/* - * (C) Copyright 2006-2009 - * Texas Instruments, <www.ti.com> - * Richard Woodruff <r-woodruff2@ti.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _OMAP44XX_MEM_H_ -#define _OMAP44XX_MEM_H_ - -#ifndef __ASSEMBLY__ - -typedef enum { - STACKED = 0, - IP_DDR = 1, - COMBO_DDR = 2, - IP_SDR = 3, -} mem_t; - -/* Memory that can be connected to GPMC */ -#define GPMC_NOR 0 -#define GPMC_NAND 1 -#define GPMC_MDOC 2 -#define GPMC_ONENAND 3 -#define MMC_NAND 4 -#define MMC_ONENAND 5 -#define GPMC_NONE 6 -#define GPMC_ONENAND_TRY 7 - -#endif - - -/* New and compatability speed defines */ -#if defined(PRCM_CLK_CFG2_200MHZ) || defined(PRCM_CONFIG_II)\ - || defined(PRCM_CONFIG_5B) -# define L3_100MHZ /* Use with <= 100MHz SDRAM */ -#elif defined(PRCM_CLK_CFG2_266MHZ) || defined(PRCM_CONFIG_III)\ - || defined(PRCM_CONFIG_5A) -# define L3_133MHZ /* Use with <= 133MHz SDRAM*/ -#elif defined(PRCM_CLK_CFG2_332MHZ) || defined(PRCM_CONFIG_I) \ - || defined(PRCM_CONFIG_2) -# define L3_165MHZ /* Use with <= 165MHz SDRAM (L3=166 on 4430) */ -#endif - -/* - * GPMC settings - - * Definitions is as per the following format - * # define <PART>_GPMC_CONFIG<x> <value> - * Where: - * PART is the part name e.g. STNOR - Intel Strata Flash - * x is GPMC config registers from 1 to 6 (there will be 6 macros) - * Value is corresponding value - * - * For every valid PRCM configuration there should be only one definition of - * the same. if values are independent of the board, this definition will be - * present in this file if values are dependent on the board, then this should - * go into corresponding mem-boardName.h file - * - * Currently valid part Names are (PART): - * STNOR - Intel Strata Flash - * SMNAND - Samsung NAND - * M_NAND - Micron Large page x16 NAND - * MPDB - H4 MPDB board - * SBNOR - Sibley NOR - * ONNAND - Samsung One NAND - * - * include/configs/file.h contains the defn - for all CS we are interested - * #define OMAP44XX_GPMC_CSx PART - * #define OMAP44XX_GPMC_CSx_SIZE Size - * #define OMAP44XX_GPMC_CSx_MAP Map - * Where: - * x - CS number - * PART - Part Name as defined above - * SIZE - how big is the mapping to be - * GPMC_SIZE_128M - 0x8 - * GPMC_SIZE_64M - 0xC - * GPMC_SIZE_32M - 0xE - * GPMC_SIZE_16M - 0xF - * MAP - Map this CS to which address(GPMC address space)- Absolute address - * >>24 before being used. - */ -#define GPMC_SIZE_128M 0x8 -#define GPMC_SIZE_64M 0xC -#define GPMC_SIZE_32M 0xE -#define GPMC_SIZE_16M 0xF - -#if defined(L3_100MHZ) -# define SMNAND_GPMC_CONFIG1 0x0 -# define SMNAND_GPMC_CONFIG2 0x00141400 -# define SMNAND_GPMC_CONFIG3 0x00141400 -# define SMNAND_GPMC_CONFIG4 0x0F010F01 -# define SMNAND_GPMC_CONFIG5 0x010C1414 -# define SMNAND_GPMC_CONFIG6 0x00000A80 - -# define M_NAND_GPMC_CONFIG1 0x00001800 -# define M_NAND_GPMC_CONFIG2 0x00141400 -# define M_NAND_GPMC_CONFIG3 0x00141400 -# define M_NAND_GPMC_CONFIG4 0x0F010F01 -# define M_NAND_GPMC_CONFIG5 0x010C1414 -# define M_NAND_GPMC_CONFIG6 0x1f0f0A80 - -# define STNOR_GPMC_CONFIG1 0x3 -# define STNOR_GPMC_CONFIG2 0x000f0f01 -# define STNOR_GPMC_CONFIG3 0x00050502 -# define STNOR_GPMC_CONFIG4 0x0C060C06 -# define STNOR_GPMC_CONFIG5 0x01131F1F -# define STNOR_GPMC_CONFIG6 0x1F0F0000 - -# define MPDB_GPMC_CONFIG1 0x00011000 -# define MPDB_GPMC_CONFIG2 0x001F1F00 -# define MPDB_GPMC_CONFIG3 0x00080802 -# define MPDB_GPMC_CONFIG4 0x1C091C09 -# define MPDB_GPMC_CONFIG5 0x031A1F1F -# define MPDB_GPMC_CONFIG6 0x000003C2 -#endif - -#if defined(L3_133MHZ) -# define SMNAND_GPMC_CONFIG1 0x00000800 -# define SMNAND_GPMC_CONFIG2 0x00141400 -# define SMNAND_GPMC_CONFIG3 0x00141400 -# define SMNAND_GPMC_CONFIG4 0x0F010F01 -# define SMNAND_GPMC_CONFIG5 0x010C1414 -# define SMNAND_GPMC_CONFIG6 0x1F0F0A80 -# define SMNAND_GPMC_CONFIG7 0x00000C44 - -# define M_NAND_GPMC_CONFIG1 0x00001800 /* might reuse smnand, with |= 1000 */ -# define M_NAND_GPMC_CONFIG2 0x00141400 -# define M_NAND_GPMC_CONFIG3 0x00141400 -# define M_NAND_GPMC_CONFIG4 0x0F010F01 -# define M_NAND_GPMC_CONFIG5 0x010C1414 -# define M_NAND_GPMC_CONFIG6 0x1F0F0A80 -# define M_NAND_GPMC_CONFIG7 0x00000C44 - -# define STNOR_GPMC_CONFIG1 0x1203 -# define STNOR_GPMC_CONFIG2 0x00151501 -# define STNOR_GPMC_CONFIG3 0x00060602 -# define STNOR_GPMC_CONFIG4 0x10081008 -# define STNOR_GPMC_CONFIG5 0x01131F1F -# define STNOR_GPMC_CONFIG6 0x1F0F04c4 - -# define SIBNOR_GPMC_CONFIG1 0x1200 -# define SIBNOR_GPMC_CONFIG2 0x001f1f00 -# define SIBNOR_GPMC_CONFIG3 0x00080802 -# define SIBNOR_GPMC_CONFIG4 0x1C091C09 -# define SIBNOR_GPMC_CONFIG5 0x01131F1F -# define SIBNOR_GPMC_CONFIG6 0x1F0F03C2 - -/* ES1 SDP and ES1 chip Debug FPGA */ -# define MPDB_GPMC_CONFIG1 0x00011000 -# define MPDB_GPMC_CONFIG2 0x001f1f01 -# define MPDB_GPMC_CONFIG3 0x00080803 -# define MPDB_GPMC_CONFIG4 0x1C091C09 -# define MPDB_GPMC_CONFIG5 0x041f1F1F -# define MPDB_GPMC_CONFIG6 0x000004C4 - -/* ES2 SDP and ES2 chip Debug FPGA */ -# define SDPV2_MPDB_GPMC_CONFIG1 0x00611200 -# define SDPV2_MPDB_GPMC_CONFIG2 0x001F1F01 -# define SDPV2_MPDB_GPMC_CONFIG3 0x00080803 -# define SDPV2_MPDB_GPMC_CONFIG4 0x1D091D09 -# define SDPV2_MPDB_GPMC_CONFIG5 0x041D1F1F -# define SDPV2_MPDB_GPMC_CONFIG6 0x1D0904C4 - -# define P2_GPMC_CONFIG1 0x0 -# define P2_GPMC_CONFIG2 0x0 -# define P2_GPMC_CONFIG3 0x0 -# define P2_GPMC_CONFIG4 0x0 -# define P2_GPMC_CONFIG5 0x0 -# define P2_GPMC_CONFIG6 0x0 - -# define ONENAND_GPMC_CONFIG1 0x00001200 -# define ONENAND_GPMC_CONFIG2 0x000c0c01 -# define ONENAND_GPMC_CONFIG3 0x00030301 -# define ONENAND_GPMC_CONFIG4 0x0c040c04 -# define ONENAND_GPMC_CONFIG5 0x010C1010 -# define ONENAND_GPMC_CONFIG6 0x1F060000 - -#endif /* endif L3_133MHZ */ - -#if defined(L3_165MHZ) -# define SMNAND_GPMC_CONFIG1 0x00000800 -# define SMNAND_GPMC_CONFIG2 0x00060600 -# define SMNAND_GPMC_CONFIG3 0x00060401 -# define SMNAND_GPMC_CONFIG4 0x05010801 -# define SMNAND_GPMC_CONFIG5 0x00090B0B -# define SMNAND_GPMC_CONFIG6 0x050001C0 -# define SMNAND_GPMC_CONFIG7 0x00000C44 - -# define M_NAND_GPMC_CONFIG1 0x00001800 -# define M_NAND_GPMC_CONFIG2 0x00141400 -# define M_NAND_GPMC_CONFIG3 0x00141400 -# define M_NAND_GPMC_CONFIG4 0x0F010F01 -# define M_NAND_GPMC_CONFIG5 0x010C1414 -# define M_NAND_GPMC_CONFIG6 0x1F0F0A80 -# define M_NAND_GPMC_CONFIG7 0x00000C44 - -# define STNOR_GPMC_CONFIG1 0x3 -# define STNOR_GPMC_CONFIG2 0x00151501 -# define STNOR_GPMC_CONFIG3 0x00060602 -# define STNOR_GPMC_CONFIG4 0x11091109 -# define STNOR_GPMC_CONFIG5 0x01141F1F -# define STNOR_GPMC_CONFIG6 0x1F0F04c4 - -# define SIBNOR_GPMC_CONFIG1 0x1200 -# define SIBNOR_GPMC_CONFIG2 0x001f1f00 -# define SIBNOR_GPMC_CONFIG3 0x00080802 -# define SIBNOR_GPMC_CONFIG4 0x1C091C09 -# define SIBNOR_GPMC_CONFIG5 0x01131F1F -# define SIBNOR_GPMC_CONFIG6 0x1F0F03C2 - -# define SDPV2_MPDB_GPMC_CONFIG1 0x00611200 -# define SDPV2_MPDB_GPMC_CONFIG2 0x001F1F01 -# define SDPV2_MPDB_GPMC_CONFIG3 0x00080803 -# define SDPV2_MPDB_GPMC_CONFIG4 0x1D091D09 -# define SDPV2_MPDB_GPMC_CONFIG5 0x041D1F1F -# define SDPV2_MPDB_GPMC_CONFIG6 0x1D0904C4 - -# define MPDB_GPMC_CONFIG1 0x00011000 -# define MPDB_GPMC_CONFIG2 0x001f1f01 -# define MPDB_GPMC_CONFIG3 0x00080803 -# define MPDB_GPMC_CONFIG4 0x1c0b1c0a -# define MPDB_GPMC_CONFIG5 0x041f1F1F -# define MPDB_GPMC_CONFIG6 0x1F0F04C4 - -# define LAB_ENET_GPMC_CONFIG1 0x00611000 -# define LAB_ENET_GPMC_CONFIG2 0x001F1F01 -# define LAB_ENET_GPMC_CONFIG3 0x00080803 -# define LAB_ENET_GPMC_CONFIG4 0x1D091D09 -# define LAB_ENET_GPMC_CONFIG5 0x041D1F1F -# define LAB_ENET_GPMC_CONFIG6 0x1D0904C4 - -# define P2_GPMC_CONFIG1 0x0 -# define P2_GPMC_CONFIG2 0x0 -# define P2_GPMC_CONFIG3 0x0 -# define P2_GPMC_CONFIG4 0x0 -# define P2_GPMC_CONFIG5 0x0 -# define P2_GPMC_CONFIG6 0x0 - -# define ONENAND_GPMC_CONFIG1 0x00001200 -# define ONENAND_GPMC_CONFIG2 0x000F0F01 -# define ONENAND_GPMC_CONFIG3 0x00030301 -# define ONENAND_GPMC_CONFIG4 0x0F040F04 -# define ONENAND_GPMC_CONFIG5 0x010F1010 -# define ONENAND_GPMC_CONFIG6 0x1F060000 - -#endif - -/* max number of GPMC Chip Selects */ -#define GPMC_MAX_CS 8 -/* max number of GPMC regs */ -#define GPMC_MAX_REG 7 - -#define PISMO1_NOR 1 -#define PISMO1_NAND 2 -#define PISMO2_CS0 3 -#define PISMO2_CS1 4 -#define PISMO1_ONENAND 5 -#define DBG_MPDB 6 -#define PISMO2_NAND_CS0 7 -#define PISMO2_NAND_CS1 8 - -/* make it readable for the gpmc_init */ -#define PISMO1_NOR_BASE FLASH_BASE -#define PISMO1_NAND_BASE NAND_BASE -#define PISMO2_CS0_BASE PISMO2_MAP1 -#define PISMO1_ONEN_BASE ONENAND_MAP -#define DBG_MPDB_BASE DEBUG_BASE - -#endif /* endif _OMAP44XX_MEM_H_ */ diff --git a/x-loader/include/asm/arch-omap4/mmc.h b/x-loader/include/asm/arch-omap4/mmc.h deleted file mode 100644 index 8631aae..0000000 --- a/x-loader/include/asm/arch-omap4/mmc.h +++ /dev/null @@ -1,235 +0,0 @@ -/* - * (C) Copyright 2008 - * Texas Instruments, <www.ti.com> - * Syed Mohammed Khasim <khasim@ti.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation's version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef MMC_H -#define MMC_H - -#include "mmc_host_def.h" - -/* Responses */ -#define RSP_TYPE_NONE (RSP_TYPE_NORSP | CCCE_NOCHECK | CICE_NOCHECK) -#define RSP_TYPE_R1 (RSP_TYPE_LGHT48 | CCCE_CHECK | CICE_CHECK) -#define RSP_TYPE_R1B (RSP_TYPE_LGHT48B | CCCE_CHECK | CICE_CHECK) -#define RSP_TYPE_R2 (RSP_TYPE_LGHT136 | CCCE_CHECK | CICE_NOCHECK) -#define RSP_TYPE_R3 (RSP_TYPE_LGHT48 | CCCE_NOCHECK | CICE_NOCHECK) -#define RSP_TYPE_R4 (RSP_TYPE_LGHT48 | CCCE_NOCHECK | CICE_NOCHECK) -#define RSP_TYPE_R5 (RSP_TYPE_LGHT48 | CCCE_CHECK | CICE_CHECK) -#define RSP_TYPE_R6 (RSP_TYPE_LGHT48 | CCCE_CHECK | CICE_CHECK) -#define RSP_TYPE_R7 (RSP_TYPE_LGHT48 | CCCE_CHECK | CICE_CHECK) - -/* All supported commands */ -#define MMC_CMD0 (INDEX(0) | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE) -#define MMC_CMD1 (INDEX(1) | RSP_TYPE_R3 | DP_NO_DATA | DDIR_WRITE) -#define MMC_CMD2 (INDEX(2) | RSP_TYPE_R2 | DP_NO_DATA | DDIR_WRITE) -#define MMC_CMD3 (INDEX(3) | RSP_TYPE_R1 | DP_NO_DATA | DDIR_WRITE) -#define MMC_SDCMD3 (INDEX(3) | RSP_TYPE_R6 | DP_NO_DATA | DDIR_WRITE) -#define MMC_CMD4 (INDEX(4) | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE) -#define MMC_CMD6 (INDEX(6) | RSP_TYPE_R1B | DP_NO_DATA | DDIR_WRITE) -#define MMC_CMD7_SELECT (INDEX(7) | RSP_TYPE_R1B | DP_NO_DATA | DDIR_WRITE) -#define MMC_CMD7_DESELECT (INDEX(7) | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE) -#define MMC_CMD8 (INDEX(8) | RSP_TYPE_R1 | DP_DATA | DDIR_READ) -#define MMC_SDCMD8 (INDEX(8) | RSP_TYPE_R7 | DP_NO_DATA | DDIR_WRITE) -#define MMC_CMD9 (INDEX(9) | RSP_TYPE_R2 | DP_NO_DATA | DDIR_WRITE) -#define MMC_CMD12 (INDEX(12) | RSP_TYPE_R1B | DP_NO_DATA | DDIR_WRITE) -#define MMC_CMD13 (INDEX(13) | RSP_TYPE_R1 | DP_NO_DATA | DDIR_WRITE) -#define MMC_CMD15 (INDEX(15) | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE) -#define MMC_CMD16 (INDEX(16) | RSP_TYPE_R1 | DP_NO_DATA | DDIR_WRITE) -#define MMC_CMD17 (INDEX(17) | RSP_TYPE_R1 | DP_DATA | DDIR_READ) -#define MMC_CMD24 (INDEX(24) | RSP_TYPE_R1 | DP_DATA | DDIR_WRITE) -#define MMC_ACMD6 (INDEX(6) | RSP_TYPE_R1 | DP_NO_DATA | DDIR_WRITE) -#define MMC_ACMD41 (INDEX(41) | RSP_TYPE_R3 | DP_NO_DATA | DDIR_WRITE) -#define MMC_ACMD51 (INDEX(51) | RSP_TYPE_R1 | DP_DATA | DDIR_READ) -#define MMC_CMD55 (INDEX(55) | RSP_TYPE_R1 | DP_NO_DATA | DDIR_WRITE) - -#define MMC_AC_CMD_RCA_MASK (unsigned int)(0xFFFF << 16) -#define MMC_BC_CMD_DSR_MASK (unsigned int)(0xFFFF << 16) -#define MMC_DSR_DEFAULT (0x0404) -#define SD_CMD8_CHECK_PATTERN (0xAA) -#define SD_CMD8_2_7_3_6_V_RANGE (0x01 << 8) - -/* Clock Configurations and Macros */ - -#define MMC_CLOCK_REFERENCE (96) -#define MMC_RELATIVE_CARD_ADDRESS (0x1234) -#define MMC_INIT_SEQ_CLK (MMC_CLOCK_REFERENCE * 1000 / 80) -#define MMC_400kHz_CLK (MMC_CLOCK_REFERENCE * 1000 / 400) -#define CLKDR(r, f, u) ((((r)*100) / ((f)*(u))) + 1) -#define CLKD(f, u) (CLKDR(MMC_CLOCK_REFERENCE, f, u)) - -#define MMC_OCR_REG_ACCESS_MODE_MASK (0x3 << 29) -#define MMC_OCR_REG_ACCESS_MODE_BYTE (0x0 << 29) -#define MMC_OCR_REG_ACCESS_MODE_SECTOR (0x2 << 29) - -#define MMC_OCR_REG_HOST_CAPACITY_SUPPORT_MASK (0x1 << 30) -#define MMC_OCR_REG_HOST_CAPACITY_SUPPORT_BYTE (0x0 << 30) -#define MMC_OCR_REG_HOST_CAPACITY_SUPPORT_SECTOR (0x1 << 30) - -#define MMC_SD2_CSD_C_SIZE_LSB_MASK (0xFFFF) -#define MMC_SD2_CSD_C_SIZE_MSB_MASK (0x003F) -#define MMC_SD2_CSD_C_SIZE_MSB_OFFSET (16) -#define MMC_CSD_C_SIZE_LSB_MASK (0x0003) -#define MMC_CSD_C_SIZE_MSB_MASK (0x03FF) -#define MMC_CSD_C_SIZE_MSB_OFFSET (2) - -#define MMC_CSD_TRAN_SPEED_UNIT_MASK (0x07 << 0) -#define MMC_CSD_TRAN_SPEED_FACTOR_MASK (0x0F << 3) -#define MMC_CSD_TRAN_SPEED_UNIT_100MHZ (0x3 << 0) -#define MMC_CSD_TRAN_SPEED_FACTOR_1_0 (0x01 << 3) -#define MMC_CSD_TRAN_SPEED_FACTOR_8_0 (0x0F << 3) - -typedef struct { - unsigned not_used:1; - unsigned crc:7; - unsigned ecc:2; - unsigned file_format:2; - unsigned tmp_write_protect:1; - unsigned perm_write_protect:1; - unsigned copy:1; - unsigned file_format_grp:1; - unsigned content_prot_app:1; - unsigned reserved_1:4; - unsigned write_bl_partial:1; - unsigned write_bl_len:4; - unsigned r2w_factor:3; - unsigned default_ecc:2; - unsigned wp_grp_enable:1; - unsigned wp_grp_size:5; - unsigned erase_grp_mult:5; - unsigned erase_grp_size:5; - unsigned c_size_mult:3; - unsigned vdd_w_curr_max:3; - unsigned vdd_w_curr_min:3; - unsigned vdd_r_curr_max:3; - unsigned vdd_r_curr_min:3; - unsigned c_size_lsb:2; - unsigned c_size_msb:10; - unsigned reserved_2:2; - unsigned dsr_imp:1; - unsigned read_blk_misalign:1; - unsigned write_blk_misalign:1; - unsigned read_bl_partial:1; - unsigned read_bl_len:4; - unsigned ccc:12; - unsigned tran_speed:8; - unsigned nsac:8; - unsigned taac:8; - unsigned reserved_3:2; - unsigned spec_vers:4; - unsigned csd_structure:2; -} mmc_csd_reg_t; - -/* csd for sd2.0 */ -typedef struct { - unsigned not_used:1; - unsigned crc:7; - unsigned reserved_1:2; - unsigned file_format:2; - unsigned tmp_write_protect:1; - unsigned perm_write_protect:1; - unsigned copy:1; - unsigned file_format_grp:1; - unsigned reserved_2:5; - unsigned write_bl_partial:1; - unsigned write_bl_len:4; - unsigned r2w_factor:3; - unsigned reserved_3:2; - unsigned wp_grp_enable:1; - unsigned wp_grp_size:7; - unsigned sector_size:7; - unsigned erase_blk_len:1; - unsigned reserved_4:1; - unsigned c_size_lsb:16; - unsigned c_size_msb:6; - unsigned reserved_5:6; - unsigned dsr_imp:1; - unsigned read_blk_misalign:1; - unsigned write_blk_misalign:1; - unsigned read_bl_partial:1; - unsigned read_bl_len:4; - unsigned ccc:12; - unsigned tran_speed:8; - unsigned nsac:8; - unsigned taac:8; - unsigned reserved_6:6; - unsigned csd_structure:2; -} mmc_sd2_csd_reg_t; - -/* extended csd - 512 bytes long */ -typedef struct { - unsigned char reserved_1[181]; - unsigned char erasedmemorycontent; - unsigned char reserved_2; - unsigned char buswidthmode; - unsigned char reserved_3; - unsigned char highspeedinterfacetiming; - unsigned char reserved_4; - unsigned char powerclass; - unsigned char reserved_5; - unsigned char commandsetrevision; - unsigned char reserved_6; - unsigned char commandset; - unsigned char extendedcsdrevision; - unsigned char reserved_7; - unsigned char csdstructureversion; - unsigned char reserved_8; - unsigned char cardtype; - unsigned char reserved_9[3]; - unsigned char powerclass_52mhz_1_95v; - unsigned char powerclass_26mhz_1_95v; - unsigned char powerclass_52mhz_3_6v; - unsigned char powerclass_26mhz_3_6v; - unsigned char reserved_10; - unsigned char minreadperf_4b_26mhz; - unsigned char minwriteperf_4b_26mhz; - unsigned char minreadperf_8b_26mhz_4b_52mhz; - unsigned char minwriteperf_8b_26mhz_4b_52mhz; - unsigned char minreadperf_8b_52mhz; - unsigned char minwriteperf_8b_52mhz; - unsigned char reserved_11; - unsigned int sectorcount; - unsigned char reserved_12[288]; - unsigned char supportedcommandsets; - unsigned char reserved_13[7]; -} mmc_extended_csd_reg_t; - -/* mmc sd responce */ -typedef struct { - unsigned int ocr; -} mmc_resp_r3; - -typedef struct { - unsigned short cardstatus; - unsigned short newpublishedrca; -} mmc_resp_r6; - -extern mmc_card_data mmc_dev; - -unsigned char mmc_lowlevel_init(void); -unsigned char mmc_send_command(unsigned int cmd, unsigned int arg, - unsigned int *response); -unsigned char mmc_setup_clock(unsigned int iclk, unsigned short clkd); -unsigned char mmc_set_opendrain(unsigned char state); -unsigned char mmc_read_data(unsigned int *output_buf); - -#endif /* MMC_H */ diff --git a/x-loader/include/asm/arch-omap4/mmc_host_def.h b/x-loader/include/asm/arch-omap4/mmc_host_def.h deleted file mode 100644 index 0abc841..0000000 --- a/x-loader/include/asm/arch-omap4/mmc_host_def.h +++ /dev/null @@ -1,168 +0,0 @@ -/* - * (C) Copyright 2008 - * Texas Instruments, <www.ti.com> - * Syed Mohammed Khasim <khasim@ti.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation's version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef MMC_HOST_DEFINITIONS_H -#define MMC_HOST_DEFINITIONS_H - -#define OMAP_HSMMC1_BASE 0x4809C100 -#define OMAP_HSMMC2_BASE 0x480B4100 - -/* - * OMAP HSMMC register definitions - */ - -#define OMAP_HSMMC_SYSCONFIG (*(volatile unsigned int *) (OMAP_HSMMC1_BASE+0x010)) -#define OMAP_HSMMC_SYSSTATUS (*(volatile unsigned int *) (OMAP_HSMMC1_BASE+0x014)) -#define OMAP_HSMMC_CON (*(volatile unsigned int *) (OMAP_HSMMC1_BASE+0x02C)) -#define OMAP_HSMMC_BLK (*(volatile unsigned int *) (OMAP_HSMMC1_BASE+0x104)) -#define OMAP_HSMMC_ARG (*(volatile unsigned int *) (OMAP_HSMMC1_BASE+0x108)) -#define OMAP_HSMMC_CMD (*(volatile unsigned int *) (OMAP_HSMMC1_BASE+0x10C)) -#define OMAP_HSMMC_RSP10 (*(volatile unsigned int *) (OMAP_HSMMC1_BASE+0x110)) -#define OMAP_HSMMC_RSP32 (*(volatile unsigned int *) (OMAP_HSMMC1_BASE+0x114)) -#define OMAP_HSMMC_RSP54 (*(volatile unsigned int *) (OMAP_HSMMC1_BASE+0x118)) -#define OMAP_HSMMC_RSP76 (*(volatile unsigned int *) (OMAP_HSMMC1_BASE+0x11C)) -#define OMAP_HSMMC_DATA (*(volatile unsigned int *) (OMAP_HSMMC1_BASE+0x120)) -#define OMAP_HSMMC_PSTATE (*(volatile unsigned int *) (OMAP_HSMMC1_BASE+0x124)) -#define OMAP_HSMMC_HCTL (*(volatile unsigned int *) (OMAP_HSMMC1_BASE+0x128)) -#define OMAP_HSMMC_SYSCTL (*(volatile unsigned int *) (OMAP_HSMMC1_BASE+0x12C)) -#define OMAP_HSMMC_STAT (*(volatile unsigned int *) (OMAP_HSMMC1_BASE+0x130)) -#define OMAP_HSMMC_IE (*(volatile unsigned int *) (OMAP_HSMMC1_BASE+0x134)) -#define OMAP_HSMMC_CAPA (*(volatile unsigned int *) (OMAP_HSMMC1_BASE+0x140)) - -/* T2 Register definitions */ -#define CONTROL_PBIAS_LITE (*(volatile unsigned int *) 0x4A100600) -#define CONTROL_CONF_MMC1 (*(volatile unsigned int *) 0x4A100628) - -/* - * OMAP HS MMC Bit definitions - */ -#define MMC_SOFTRESET (0x1 << 1) -#define RESETDONE (0x1 << 0) -#define NOOPENDRAIN (0x0 << 0) -#define OPENDRAIN (0x1 << 0) -#define OD (0x1 << 0) -#define INIT_NOINIT (0x0 << 1) -#define INIT_INITSTREAM (0x1 << 1) -#define HR_NOHOSTRESP (0x0 << 2) -#define STR_BLOCK (0x0 << 3) -#define MODE_FUNC (0x0 << 4) -#define DW8_1_4BITMODE (0x0 << 5) -#define MIT_CTO (0x0 << 6) -#define CDP_ACTIVEHIGH (0x0 << 7) -#define WPP_ACTIVEHIGH (0x0 << 8) -#define RESERVED_MASK (0x3 << 9) -#define CTPL_MMC_SD (0x0 << 11) -#define BLEN_512BYTESLEN (0x200 << 0) -#define NBLK_STPCNT (0x0 << 16) -#define DE_DISABLE (0x0 << 0) -#define BCE_DISABLE (0x0 << 1) -#define ACEN_DISABLE (0x0 << 2) -#define DDIR_OFFSET (4) -#define DDIR_MASK (0x1 << 4) -#define DDIR_WRITE (0x0 << 4) -#define DDIR_READ (0x1 << 4) -#define MSBS_SGLEBLK (0x0 << 5) -#define RSP_TYPE_OFFSET (16) -#define RSP_TYPE_MASK (0x3 << 16) -#define RSP_TYPE_NORSP (0x0 << 16) -#define RSP_TYPE_LGHT136 (0x1 << 16) -#define RSP_TYPE_LGHT48 (0x2 << 16) -#define RSP_TYPE_LGHT48B (0x3 << 16) -#define CCCE_NOCHECK (0x0 << 19) -#define CCCE_CHECK (0x1 << 19) -#define CICE_NOCHECK (0x0 << 20) -#define CICE_CHECK (0x1 << 20) -#define DP_OFFSET (21) -#define DP_MASK (0x1 << 21) -#define DP_NO_DATA (0x0 << 21) -#define DP_DATA (0x1 << 21) -#define CMD_TYPE_NORMAL (0x0 << 22) -#define INDEX_OFFSET (24) -#define INDEX_MASK (0x3f << 24) -#define INDEX(i) (i << 24) -#define DATI_MASK (0x1 << 1) -#define DATI_CMDDIS (0x1 << 1) -#define DTW_1_BITMODE (0x0 << 1) -#define DTW_4_BITMODE (0x1 << 1) -#define SDBP_PWROFF (0x0 << 8) -#define SDBP_PWRON (0x1 << 8) -#define SDVS_1V8 (0x5 << 9) -#define SDVS_3V0 (0x6 << 9) -#define ICE_MASK (0x1 << 0) -#define ICE_STOP (0x0 << 0) -#define ICS_MASK (0x1 << 1) -#define ICS_NOTREADY (0x0 << 1) -#define ICE_OSCILLATE (0x1 << 0) -#define CEN_MASK (0x1 << 2) -#define CEN_DISABLE (0x0 << 2) -#define CEN_ENABLE (0x1 << 2) -#define CLKD_OFFSET (6) -#define CLKD_MASK (0x3FF << 6) -#define DTO_MASK (0xF << 16) -#define DTO_15THDTO (0xE << 16) -#define SOFTRESETALL (0x1 << 24) -#define CC_MASK (0x1 << 0) -#define TC_MASK (0x1 << 1) -#define BWR_MASK (0x1 << 4) -#define BRR_MASK (0x1 << 5) -#define ERRI_MASK (0x1 << 15) -#define IE_CC (0x01 << 0) -#define IE_TC (0x01 << 1) -#define IE_BWR (0x01 << 4) -#define IE_BRR (0x01 << 5) -#define IE_CTO (0x01 << 16) -#define IE_CCRC (0x01 << 17) -#define IE_CEB (0x01 << 18) -#define IE_CIE (0x01 << 19) -#define IE_DTO (0x01 << 20) -#define IE_DCRC (0x01 << 21) -#define IE_DEB (0x01 << 22) -#define IE_CERR (0x01 << 28) -#define IE_BADA (0x01 << 29) - -#define VS30_3V0SUP (1 << 25) -#define VS18_1V8SUP (1 << 26) - -/* Driver definitions */ -#define MMCSD_SECTOR_SIZE (512) -#define MMC_CARD 0 -#define SD_CARD 1 -#define BYTE_MODE 0 -#define SECTOR_MODE 1 -#define CLK_INITSEQ 0 -#define CLK_400KHZ 1 -#define CLK_MISC 2 - -typedef struct { - unsigned int card_type; - unsigned int version; - unsigned int mode; - unsigned int size; - unsigned int RCA; -} mmc_card_data; - -#define mmc_reg_out(addr, mask, val) \ - (addr) = (((addr)) & (~(mask)) ) | ( (val) & (mask)); - -#endif /* MMC_HOST_DEFINITIONS_H */ diff --git a/x-loader/include/asm/arch-omap4/mux.h b/x-loader/include/asm/arch-omap4/mux.h deleted file mode 100644 index d6505bf..0000000 --- a/x-loader/include/asm/arch-omap4/mux.h +++ /dev/null @@ -1,392 +0,0 @@ -/* Copyright 2009 - * Texas Instruments, <www.ti.com> - * Syed Rafiuddin <rafiuddin.syed@ti.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#ifndef _OMAP4430_MUX_H_ -#define _OMAP4430_MUX_H_ - -/* - * OFF_PD - Off mode pull type down - * OFF_PU - Off mode pull type up - * OFF_OUT_PTD - Off Mode Mux low for OUT - * OFF_OUT_PTU - Off Mode Mux high for OUT - * OFF_IN - Off Mode Mux set to IN - * OFF_OUT - Off Mode Mux set to OUT - * OFF_EN - Off Mode Mux Enable - * IEN - Input Enable - * IDIS - Input Disable - * PTD - Pull type Down - * PTU - Pull type Up - * DIS - Pull type selection is inactive - * EN - Pull type selection is active - * M0 - Mode 0 - */ -#ifdef CONFIG_OFF_PADCONF -#define OFF_PD (1 << 12) -#define OFF_PU (3 << 12) -#define OFF_OUT_PTD (0 << 10) -#define OFF_OUT_PTU (2 << 10) -#define OFF_IN (1 << 10) -#define OFF_OUT (0 << 10) -#define OFF_EN (1 << 9) -#else -#define OFF_PD (0 << 12) -#define OFF_PU (0 << 12) -#define OFF_OUT_PTD (0 << 10) -#define OFF_OUT_PTU (0 << 10) -#define OFF_IN (0 << 10) -#define OFF_OUT (0 << 10) -#define OFF_EN (0 << 9) -#endif - -#define IEN (1 << 8) -#define IDIS (0 << 8) -#define PTU (3 << 3) -#define PTD (1 << 3) -#define EN (1 << 3) -#define DIS (0 << 3) - -#define M0 0 -#define M1 1 -#define M2 2 -#define M3 3 -#define M4 4 -#define M5 5 -#define M6 6 -#define M7 7 - -#ifdef CONFIG_OFF_PADCONF -#define OFF_IN_PD (OFF_PD | OFF_IN | OFF_EN) -#define OFF_IN_PU (OFF_PU | OFF_IN | OFF_EN) -#define OFF_OUT_PD (OFF_OUT_PTD | OFF_OUT | OFF_EN) -#define OFF_OUT_PU (OFF_OUT_PTU | OFF_OUT | OFF_EN) -#else -#define OFF_IN_PD 0 -#define OFF_IN_PU 0 -#define OFF_OUT_PD 0 -#define OFF_OUT_PU 0 -#endif /* #ifdef CONFIG_OFF_PADCONF */ - -/* - * To get the actual address the offset has to added - * with OMAP44XX_CTRL_BASE to get the actual address - */ - -/* OMAP4 SPECIFIC PADCONF REGISTERS */ - -#define CONTROL_PADCONF_CORE_REVISION 0x0000 -#define CONTROL_PADCONF_CORE_HWINFO 0x0004 -#define CONTROL_PADCONF_CORE_SYSCONFIG 0x0010 -#define CONTROL_PADCONF_GPMC_AD0 0x0040 -#define CONTROL_PADCONF_GPMC_AD1 0x0042 -#define CONTROL_PADCONF_GPMC_AD2 0x0044 -#define CONTROL_PADCONF_GPMC_AD3 0x0046 -#define CONTROL_PADCONF_GPMC_AD4 0x0048 -#define CONTROL_PADCONF_GPMC_AD5 0x004A -#define CONTROL_PADCONF_GPMC_AD6 0x004C -#define CONTROL_PADCONF_GPMC_AD7 0x004E -#define CONTROL_PADCONF_GPMC_AD8 0x0050 -#define CONTROL_PADCONF_GPMC_AD9 0x0052 -#define CONTROL_PADCONF_GPMC_AD10 0x0054 -#define CONTROL_PADCONF_GPMC_AD11 0x0056 -#define CONTROL_PADCONF_GPMC_AD12 0x0058 -#define CONTROL_PADCONF_GPMC_AD13 0x005A -#define CONTROL_PADCONF_GPMC_AD14 0x005C -#define CONTROL_PADCONF_GPMC_AD15 0x005E -#define CONTROL_PADCONF_GPMC_A16 0x0060 -#define CONTROL_PADCONF_GPMC_A17 0x0062 -#define CONTROL_PADCONF_GPMC_A18 0x0064 -#define CONTROL_PADCONF_GPMC_A19 0x0066 -#define CONTROL_PADCONF_GPMC_A20 0x0068 -#define CONTROL_PADCONF_GPMC_A21 0x006A -#define CONTROL_PADCONF_GPMC_A22 0x006C -#define CONTROL_PADCONF_GPMC_A23 0x006E -#define CONTROL_PADCONF_GPMC_A24 0x0070 -#define CONTROL_PADCONF_GPMC_A25 0x0072 -#define CONTROL_PADCONF_GPMC_NCS0 0x0074 -#define CONTROL_PADCONF_GPMC_NCS1 0x0076 -#define CONTROL_PADCONF_GPMC_NCS2 0x0078 -#define CONTROL_PADCONF_GPMC_NCS3 0x007A -#define CONTROL_PADCONF_GPMC_NWP 0x007C -#define CONTROL_PADCONF_GPMC_CLK 0x007E -#define CONTROL_PADCONF_GPMC_NADV_ALE 0x0080 -#define CONTROL_PADCONF_GPMC_NOE 0x0082 -#define CONTROL_PADCONF_GPMC_NWE 0x0084 -#define CONTROL_PADCONF_GPMC_NBE0_CLE 0x0086 -#define CONTROL_PADCONF_GPMC_NBE1 0x0088 -#define CONTROL_PADCONF_GPMC_WAIT0 0x008A -#define CONTROL_PADCONF_GPMC_WAIT1 0x008C -#define CONTROL_PADCONF_C2C_DATA11 0x008E -#define CONTROL_PADCONF_C2C_DATA12 0x0090 -#define CONTROL_PADCONF_C2C_DATA13 0x0092 -#define CONTROL_PADCONF_C2C_DATA14 0x0094 -#define CONTROL_PADCONF_C2C_DATA15 0x0096 -#define CONTROL_PADCONF_HDMI_HPD 0x0098 -#define CONTROL_PADCONF_HDMI_CEC 0x009A -#define CONTROL_PADCONF_HDMI_DDC_SCL 0x009C -#define CONTROL_PADCONF_HDMI_DDC_SDA 0x009E -#define CONTROL_PADCONF_CSI21_DX0 0x00A0 -#define CONTROL_PADCONF_CSI21_DY0 0x00A2 -#define CONTROL_PADCONF_CSI21_DX1 0x00A4 -#define CONTROL_PADCONF_CSI21_DY1 0x00A6 -#define CONTROL_PADCONF_CSI21_DX2 0x00A8 -#define CONTROL_PADCONF_CSI21_DY2 0x00AA -#define CONTROL_PADCONF_CSI21_DX3 0x00AC -#define CONTROL_PADCONF_CSI21_DY3 0x00AE -#define CONTROL_PADCONF_CSI21_DX4 0x00B0 -#define CONTROL_PADCONF_CSI21_DY4 0x00B2 -#define CONTROL_PADCONF_CSI22_DX0 0x00B4 -#define CONTROL_PADCONF_CSI22_DY0 0x00B6 -#define CONTROL_PADCONF_CSI22_DX1 0x00B8 -#define CONTROL_PADCONF_CSI22_DY1 0x00BA -#define CONTROL_PADCONF_CAM_SHUTTER 0x00BC -#define CONTROL_PADCONF_CAM_STROBE 0x00BE -#define CONTROL_PADCONF_CAM_GLOBALRESET 0x00C0 -#define CONTROL_PADCONF_USBB1_ULPITLL_CLK 0x00C2 -#define CONTROL_PADCONF_USBB1_ULPITLL_STP 0x00C4 -#define CONTROL_PADCONF_USBB1_ULPITLL_DIR 0x00C6 -#define CONTROL_PADCONF_USBB1_ULPITLL_NXT 0x00C8 -#define CONTROL_PADCONF_USBB1_ULPITLL_DAT0 0x00CA -#define CONTROL_PADCONF_USBB1_ULPITLL_DAT1 0x00CC -#define CONTROL_PADCONF_USBB1_ULPITLL_DAT2 0x00CE -#define CONTROL_PADCONF_USBB1_ULPITLL_DAT3 0x00D0 -#define CONTROL_PADCONF_USBB1_ULPITLL_DAT4 0x00D2 -#define CONTROL_PADCONF_USBB1_ULPITLL_DAT5 0x00D4 -#define CONTROL_PADCONF_USBB1_ULPITLL_DAT6 0x00D6 -#define CONTROL_PADCONF_USBB1_ULPITLL_DAT7 0x00D8 -#define CONTROL_PADCONF_USBB1_HSIC_DATA 0x00DA -#define CONTROL_PADCONF_USBB1_HSIC_STROBE 0x00DC -#define CONTROL_PADCONF_USBC1_ICUSB_DP 0x00DE -#define CONTROL_PADCONF_USBC1_ICUSB_DM 0x00E0 -#define CONTROL_PADCONF_SDMMC1_CLK 0x00E2 -#define CONTROL_PADCONF_SDMMC1_CMD 0x00E4 -#define CONTROL_PADCONF_SDMMC1_DAT0 0x00E6 -#define CONTROL_PADCONF_SDMMC1_DAT1 0x00E8 -#define CONTROL_PADCONF_SDMMC1_DAT2 0x00EA -#define CONTROL_PADCONF_SDMMC1_DAT3 0x00EC -#define CONTROL_PADCONF_SDMMC1_DAT4 0x00EE -#define CONTROL_PADCONF_SDMMC1_DAT5 0x00F0 -#define CONTROL_PADCONF_SDMMC1_DAT6 0x00F2 -#define CONTROL_PADCONF_SDMMC1_DAT7 0x00F4 -#define CONTROL_PADCONF_ABE_MCBSP2_CLKX 0x00F6 -#define CONTROL_PADCONF_ABE_MCBSP2_DR 0x00F8 -#define CONTROL_PADCONF_ABE_MCBSP2_DX 0x00FA -#define CONTROL_PADCONF_ABE_MCBSP2_FSX 0x00FC -#define CONTROL_PADCONF_ABE_MCBSP1_CLKX 0x00FE -#define CONTROL_PADCONF_ABE_MCBSP1_DR 0x0100 -#define CONTROL_PADCONF_ABE_MCBSP1_DX 0x0102 -#define CONTROL_PADCONF_ABE_MCBSP1_FSX 0x0104 -#define CONTROL_PADCONF_ABE_PDM_UL_DATA 0x0106 -#define CONTROL_PADCONF_ABE_PDM_DL_DATA 0x0108 -#define CONTROL_PADCONF_ABE_PDM_FRAME 0x010A -#define CONTROL_PADCONF_ABE_PDM_LB_CLK 0x010C -#define CONTROL_PADCONF_ABE_CLKS 0x010E -#define CONTROL_PADCONF_ABE_DMIC_CLK1 0x0110 -#define CONTROL_PADCONF_ABE_DMIC_DIN1 0x0112 -#define CONTROL_PADCONF_ABE_DMIC_DIN2 0x0114 -#define CONTROL_PADCONF_ABE_DMIC_DIN3 0x0116 -#define CONTROL_PADCONF_UART2_CTS 0x0118 -#define CONTROL_PADCONF_UART2_RTS 0x011A -#define CONTROL_PADCONF_UART2_RX 0x011C -#define CONTROL_PADCONF_UART2_TX 0x011E -#define CONTROL_PADCONF_HDQ_SIO 0x0120 -#define CONTROL_PADCONF_I2C1_SCL 0x0122 -#define CONTROL_PADCONF_I2C1_SDA 0x0124 -#define CONTROL_PADCONF_I2C2_SCL 0x0126 -#define CONTROL_PADCONF_I2C2_SDA 0x0128 -#define CONTROL_PADCONF_I2C3_SCL 0x012A -#define CONTROL_PADCONF_I2C3_SDA 0x012C -#define CONTROL_PADCONF_I2C4_SCL 0x012E -#define CONTROL_PADCONF_I2C4_SDA 0x0130 -#define CONTROL_PADCONF_MCSPI1_CLK 0x0132 -#define CONTROL_PADCONF_MCSPI1_SOMI 0x0134 -#define CONTROL_PADCONF_MCSPI1_SIMO 0x0136 -#define CONTROL_PADCONF_MCSPI1_CS0 0x0138 -#define CONTROL_PADCONF_MCSPI1_CS1 0x013A -#define CONTROL_PADCONF_MCSPI1_CS2 0x013C -#define CONTROL_PADCONF_MCSPI1_CS3 0x013E -#define CONTROL_PADCONF_UART3_CTS_RCTX 0x0140 -#define CONTROL_PADCONF_UART3_RTS_SD 0x0142 -#define CONTROL_PADCONF_UART3_RX_IRRX 0x0144 -#define CONTROL_PADCONF_UART3_TX_IRTX 0x0146 -#define CONTROL_PADCONF_SDMMC5_CLK 0x0148 -#define CONTROL_PADCONF_SDMMC5_CMD 0x014A -#define CONTROL_PADCONF_SDMMC5_DAT0 0x014C -#define CONTROL_PADCONF_SDMMC5_DAT1 0x014E -#define CONTROL_PADCONF_SDMMC5_DAT2 0x0150 -#define CONTROL_PADCONF_SDMMC5_DAT3 0x0152 -#define CONTROL_PADCONF_MCSPI4_CLK 0x0154 -#define CONTROL_PADCONF_MCSPI4_SIMO 0x0156 -#define CONTROL_PADCONF_MCSPI4_SOMI 0x0158 -#define CONTROL_PADCONF_MCSPI4_CS0 0x015A -#define CONTROL_PADCONF_UART4_RX 0x015C -#define CONTROL_PADCONF_UART4_TX 0x015E -#define CONTROL_PADCONF_USBB2_ULPITLL_CLK 0x0160 -#define CONTROL_PADCONF_USBB2_ULPITLL_STP 0x0162 -#define CONTROL_PADCONF_USBB2_ULPITLL_DIR 0x0164 -#define CONTROL_PADCONF_USBB2_ULPITLL_NXT 0x0166 -#define CONTROL_PADCONF_USBB2_ULPITLL_DAT0 0x0168 -#define CONTROL_PADCONF_USBB2_ULPITLL_DAT1 0x016A -#define CONTROL_PADCONF_USBB2_ULPITLL_DAT2 0x016C -#define CONTROL_PADCONF_USBB2_ULPITLL_DAT3 0x016E -#define CONTROL_PADCONF_USBB2_ULPITLL_DAT4 0x0170 -#define CONTROL_PADCONF_USBB2_ULPITLL_DAT5 0x0172 -#define CONTROL_PADCONF_USBB2_ULPITLL_DAT6 0x0174 -#define CONTROL_PADCONF_USBB2_ULPITLL_DAT7 0x0176 -#define CONTROL_PADCONF_USBB2_HSIC_DATA 0x0178 -#define CONTROL_PADCONF_USBB2_HSIC_STROBE 0x017A -#define CONTROL_PADCONF_UNIPRO_TX0 0x017C -#define CONTROL_PADCONF_UNIPRO_TY0 0x017E -#define CONTROL_PADCONF_UNIPRO_TX1 0x0180 -#define CONTROL_PADCONF_UNIPRO_TY1 0x0182 -#define CONTROL_PADCONF_UNIPRO_TX2 0x0184 -#define CONTROL_PADCONF_UNIPRO_TY2 0x0186 -#define CONTROL_PADCONF_UNIPRO_RX0 0x0188 -#define CONTROL_PADCONF_UNIPRO_RY0 0x018A -#define CONTROL_PADCONF_UNIPRO_RX1 0x018C -#define CONTROL_PADCONF_UNIPRO_RY1 0x018E -#define CONTROL_PADCONF_UNIPRO_RX2 0x0190 -#define CONTROL_PADCONF_UNIPRO_RY2 0x0192 -#define CONTROL_PADCONF_USBA0_OTG_CE 0x0194 -#define CONTROL_PADCONF_USBA0_OTG_DP 0x0196 -#define CONTROL_PADCONF_USBA0_OTG_DM 0x0198 -#define CONTROL_PADCONF_FREF_CLK1_OUT 0x019A -#define CONTROL_PADCONF_FREF_CLK2_OUT 0x019C -#define CONTROL_PADCONF_SYS_NIRQ1 0x019E -#define CONTROL_PADCONF_SYS_NIRQ2 0x01A0 -#define CONTROL_PADCONF_SYS_BOOT0 0x01A2 -#define CONTROL_PADCONF_SYS_BOOT1 0x01A4 -#define CONTROL_PADCONF_SYS_BOOT2 0x01A6 -#define CONTROL_PADCONF_SYS_BOOT3 0x01A8 -#define CONTROL_PADCONF_SYS_BOOT4 0x01AA -#define CONTROL_PADCONF_SYS_BOOT5 0x01AC -#define CONTROL_PADCONF_DPM_EMU0 0x01AE -#define CONTROL_PADCONF_DPM_EMU1 0x01B0 -#define CONTROL_PADCONF_DPM_EMU2 0x01B2 -#define CONTROL_PADCONF_DPM_EMU3 0x01B4 -#define CONTROL_PADCONF_DPM_EMU4 0x01B6 -#define CONTROL_PADCONF_DPM_EMU5 0x01B8 -#define CONTROL_PADCONF_DPM_EMU6 0x01BA -#define CONTROL_PADCONF_DPM_EMU7 0x01BC -#define CONTROL_PADCONF_DPM_EMU8 0x01BE -#define CONTROL_PADCONF_DPM_EMU9 0x01C0 -#define CONTROL_PADCONF_DPM_EMU10 0x01C2 -#define CONTROL_PADCONF_DPM_EMU11 0x01C4 -#define CONTROL_PADCONF_DPM_EMU12 0x01C6 -#define CONTROL_PADCONF_DPM_EMU13 0x01C8 -#define CONTROL_PADCONF_DPM_EMU14 0x01CA -#define CONTROL_PADCONF_DPM_EMU15 0x01CC -#define CONTROL_PADCONF_DPM_EMU16 0x01CE -#define CONTROL_PADCONF_DPM_EMU17 0x01D0 -#define CONTROL_PADCONF_DPM_EMU18 0x01D2 -#define CONTROL_PADCONF_DPM_EMU19 0x01D4 -#define CONTROL_PADCONF_WAKEUPEVENT_0 0x01D8 -#define CONTROL_PADCONF_WAKEUPEVENT_1 0x01DC -#define CONTROL_PADCONF_WAKEUPEVENT_2 0x01E0 -#define CONTROL_PADCONF_WAKEUPEVENT_3 0x01E4 -#define CONTROL_PADCONF_WAKEUPEVENT_4 0x01E8 -#define CONTROL_PADCONF_WAKEUPEVENT_5 0x01EC -#define CONTROL_PADCONF_WAKEUPEVENT_6 0x01F0 - -#define CONTROL_PADCONF_GLOBAL 0x05A2 -#define CONTROL_PADCONF_MODE 0x05A4 -#define CONTROL_SMART1IO_PADCONF_0 0x05A8 -#define CONTROL_SMART1IO_PADCONF_1 0x05AC -#define CONTROL_SMART2IO_PADCONF_0 0x05B0 -#define CONTROL_SMART2IO_PADCONF_1 0x05B4 -#define CONTROL_SMART3IO_PADCONF_0 0x05B8 -#define CONTROL_SMART3IO_PADCONF_1 0x05BC -#define CONTROL_SMART3IO_PADCONF_2 0x05C0 -#define CONTROL_USBB_HSIC 0x05C4 -#define CONTROL_SLIMBUS 0x05C8 -#define CONTROL_PBIASLITE 0x0600 -#define CONTROL_I2C_0 0x0604 -#define CONTROL_CAMERA_RX 0x0608 -#define CONTROL_AVDAC 0x060C -#define CONTROL_HDMI_TX_PHY 0x0610 -#define CONTROL_MMC2 0x0614 -#define CONTROL_DSIPHY 0x0618 -#define CONTROL_MCBSPLP 0x061C -#define CONTROL_USB2PHYCORE 0x0620 -#define CONTROL_I2C_1 0x0624 -#define CONTROL_MMC1 0x0628 -#define CONTROL_HSI 0x062C -#define CONTROL_USB 0x0630 -#define CONTROL_HDQ 0x0634 -#define CONTROL_LPDDR2IO1_0 0x0638 -#define CONTROL_LPDDR2IO1_1 0x063C -#define CONTROL_LPDDR2IO1_2 0x0640 -#define CONTROL_LPDDR2IO1_3 0x0644 -#define CONTROL_LPDDR2IO2_0 0x0648 -#define CONTROL_LPDDR2IO2_1 0x064C -#define CONTROL_LPDDR2IO2_2 0x0650 -#define CONTROL_LPDDR2IO2_3 0x0654 -#define CONTROL_BUS_HOLD 0x0658 -#define CONTROL_C2C 0x065C -#define CONTROL_CORE_CONTROL_SPARE_RW 0x0660 -#define CONTROL_CORE_CONTROL_SPARE_R 0x0664 -#define CONTROL_CORE_CONTROL_SPARE_R_C0 0x0668 -#define CONTROL_EFUSE_1 0x0700 -#define CONTROL_EFUSE_2 0x0704 -#define CONTROL_EFUSE_3 0x0708 -#define CONTROL_EFUSE_4 0x070C - -#define CONTROL_PADCONF_WKUP_REVISION 0x0000 -#define CONTROL_PADCONF_WKUP_HWINFO 0x0004 -#define CONTROL_PADCONF_WKUP_SYSCONFIG 0x0010 -#define CONTROL_WKUP_PAD0_SIM_IO 0x0040 -#define CONTROL_WKUP_PAD1_SIM_CLK 0x0042 -#define CONTROL_WKUP_PAD0_SIM_RESET 0x0044 -#define CONTROL_WKUP_PAD1_SIM_CD 0x0046 -#define CONTROL_WKUP_PAD0_SIM_PWRCTRL 0x0048 -#define CONTROL_WKUP_PAD1_SR_SCL 0x004A -#define CONTROL_WKUP_PAD0_SR_SDA 0x004C -#define CONTROL_WKUP_PAD1_FREF_XTAL_IN 0x004E -#define CONTROL_WKUP_PAD0_FREF_SLICER_IN 0x0050 -#define CONTROL_WKUP_PAD1_FREF_CLK_IOREQ 0x0052 -#define CONTROL_WKUP_PAD0_FREF_CLK0_OUT 0x0054 -#define CONTROL_WKUP_PAD1_FREF_CLK3_REQ 0x0056 -#define CONTROL_WKUP_PAD0_FREF_CLK3_OUT 0x0058 -#define CONTROL_WKUP_PAD1_FREF_CLK4_REQ 0x005A -#define CONTROL_WKUP_PAD0_FREF_CLK4_OUT 0x005C -#define CONTROL_WKUP_PAD1_SYS_32K 0x005E -#define CONTROL_WKUP_PAD0_SYS_NRESPWRON 0x0060 -#define CONTROL_WKUP_PAD1_SYS_NRESWARM 0x0062 -#define CONTROL_WKUP_PAD0_SYS_PWR_REQ 0x0064 -#define CONTROL_WKUP_PAD1_SYS_PWRON_RESET 0x0066 -#define CONTROL_WKUP_PAD0_SYS_BOOT6 0x0068 -#define CONTROL_WKUP_PAD1_SYS_BOOT7 0x006A -#define CONTROL_WKUP_PAD0_JTAG_NTRST 0x006C -#define CONTROL_WKUP_PAD1_JTAG_TCK 0x006D -#define CONTROL_WKUP_PAD0_JTAG_RTCK 0x0070 -#define CONTROL_WKUP_PAD1_JTAG_TMS_TMSC 0x0072 -#define CONTROL_WKUP_PAD0_JTAG_TDI 0x0074 -#define CONTROL_WKUP_PAD1_JTAG_TDO 0x0076 -#define CONTROL_PADCONF_WAKEUPEVENT_0 0x007C -#define CONTROL_SMART1NOPMIO_PADCONF_0 0x05A0 -#define CONTROL_SMART1NOPMIO_PADCONF_1 0x05A4 -#define CONTROL_PADCONF_MODE 0x05A8 -#define CONTROL_XTAL_OSCILLATOR 0x05AC -#define CONTROL_CONTROL_I2C_2 0x0604 -#define CONTROL_CONTROL_JTAG 0x0608 -#define CONTROL_CONTROL_SYS 0x060C -#define CONTROL_WKUP_CONTROL_SPARE_RW 0x0614 -#define CONTROL_WKUP_CONTROL_SPARE_R 0x0618 -#define CONTROL_WKUP_CONTROL_SPARE_R_C0 0x061C - -#endif diff --git a/x-loader/include/asm/arch-omap4/omap4430.h b/x-loader/include/asm/arch-omap4/omap4430.h deleted file mode 100644 index 2f83621..0000000 --- a/x-loader/include/asm/arch-omap4/omap4430.h +++ /dev/null @@ -1,137 +0,0 @@ -/* - * (C) Copyright 2006-2009 - * Texas Instruments, <www.ti.com> - * Richard Woodruff <r-woodruff2@ti.com> - * Syed Mohammed Khasim <x0khasim@ti.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _OMAP4430_SYS_H_ -#define _OMAP4430_SYS_H_ - -#include <asm/arch/sizes.h> - -/* - * 4430 specific Section - */ - -/* Stuff on L3 Interconnect */ -#define SMX_APE_BASE 0x68000000 - -/* L3 Firewall */ -#define A_REQINFOPERM0 (SMX_APE_BASE + 0x05048) -#define A_READPERM0 (SMX_APE_BASE + 0x05050) -#define A_WRITEPERM0 (SMX_APE_BASE + 0x05058) - -/* GPMC */ -#define OMAP44XX_GPMC_BASE (0x50000000) - -/* DMM */ -#define OMAP44XX_DMM_BASE 0x4E000000 - -/* SMS */ -#define OMAP44XX_SMS_BASE 0x6C000000 - -/* SDRC */ -#define OMAP44XX_SDRC_BASE 0x6D000000 - - -/* - * L4 Peripherals - L4 Wakeup and L4 Core now - */ -#define OMAP44XX_CORE_L4_IO_BASE 0x4A000000 - -#define OMAP44XX_WAKEUP_L4_IO_BASE 0x4A300000 - -#define OMAP44XX_L4_PER 0x48000000 - -#define OMAP44XX_L4_IO_BASE OMAP44XX_CORE_L4_IO_BASE - -/* CONTROL */ -//#define OMAP44XX_CTRL_BASE (OMAP44XX_L4_IO_BASE+0x2000) -#define OMAP44XX_CTRL_BASE 0x4a100000 - -/* TAP information dont know for 3430*/ -#define OMAP44XX_TAP_BASE (0x49000000) /*giving some junk for virtio */ - -/* UART */ -#define OMAP44XX_UART1 (OMAP44XX_L4_PER+0x6a000) -#define OMAP44XX_UART2 (OMAP44XX_L4_PER+0x6c000) -#define OMAP44XX_UART3 (OMAP44XX_L4_PER+0x20000) - -/* General Purpose Timers */ -#define OMAP44XX_GPT1 0x48318000 -#define OMAP44XX_GPT2 0x48032000 -#define OMAP44XX_GPT3 0x48034000 -#define OMAP44XX_GPT4 0x48036000 -#define OMAP44XX_GPT5 0x40138000 -#define OMAP44XX_GPT6 0x4013A000 -#define OMAP44XX_GPT7 0x4013C000 -#define OMAP44XX_GPT8 0x4013E000 -#define OMAP44XX_GPT9 0x48040000 -#define OMAP44XX_GPT10 0x48086000 -#define OMAP44XX_GPT11 0x48088000 -#define OMAP44XX_GPT12 0x48304000 - -/* WatchDog Timers (1 secure, 3 GP) */ -#define WD1_BASE (0x4A322000) -#define WD2_BASE (0x4A314000) -#define WD3_BASE (0x40130000) - -/* 32KTIMER */ -#define SYNC_32KTIMER_BASE (0x48320000) -#define S32K_CR (SYNC_32KTIMER_BASE+0x10) - -/* - * SDP4430 specific Section - */ - -/* - * The 443x's chip selects are programmable. The mask ROM - * does configure CS0 to 0x08000000 before dispatch. So, if - * you want your code to live below that address, you have to - * be prepared to jump though hoops, to reset the base address. - * Same as in SDP4430 - */ -#ifdef CONFIG_OMAP44XX -/* base address for indirect vectors (internal boot mode) */ -#define SRAM_OFFSET0 0x40000000 -#define SRAM_OFFSET1 0x00300000 -#define SRAM_OFFSET2 0x0000D000 -#define SRAM_OFFSET3 0x00000800 -#define SRAM_VECT_CODE (SRAM_OFFSET0|SRAM_OFFSET1|SRAM_OFFSET2|SRAM_OFFSET3) -#define LOW_LEVEL_SRAM_STACK 0x4030DFFC -#endif - -#if defined(CONFIG_4430SDP) -/* FPGA on Debug board.*/ -# define ETH_CONTROL_REG (DEBUG_BASE+0x30b) -# define LAN_RESET_REGISTER (DEBUG_BASE+0x1c) - -# define DIP_SWITCH_INPUT_REG2 (DEBUG_BASE+0x60) -# define LED_REGISTER (DEBUG_BASE+0x40) -# define FPGA_REV_REGISTER (DEBUG_BASE+0x10) -# define EEPROM_MAIN_BRD (DEBUG_BASE+0x10000+0x1800) -# define EEPROM_CONN_BRD (DEBUG_BASE+0x10000+0x1900) -# define EEPROM_UI_BRD (DEBUG_BASE+0x10000+0x1A00) -# define EEPROM_MCAM_BRD (DEBUG_BASE+0x10000+0x1B00) -# define ENHANCED_UI_EE_NAME "750-2075" -#endif - -#endif /* _OMAP4430_SYS_H_ */ diff --git a/x-loader/include/asm/arch-omap4/rev.h b/x-loader/include/asm/arch-omap4/rev.h deleted file mode 100644 index 18498bb..0000000 --- a/x-loader/include/asm/arch-omap4/rev.h +++ /dev/null @@ -1,41 +0,0 @@ -/* - * (C) Copyright 2006-2009 - * Texas Instruments, <www.ti.com> - * - * Richard Woodruff <r-woodruff2@ti.com> - * Syed Mohammed Khasim <x0khasim@ti.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _OMAP44XX_REV_H_ -#define _OMAP44XX_REV_H_ - -#define CDB_DDR_COMBO /* combo part on cpu daughter card */ -#define CDB_DDR_IPDB /* 2x16 parts on daughter card */ - -#define DDR_100 100 /* type found on most mem d-boards */ -#define DDR_111 111 /* some combo parts */ -#define DDR_133 133 /* most combo, some mem d-boards */ -#define DDR_165 165 /* future parts */ - -#define CPU_4430 0x4430 - -#define CPU_4430_ES1 1 - -#endif diff --git a/x-loader/include/asm/arch-omap4/sizes.h b/x-loader/include/asm/arch-omap4/sizes.h deleted file mode 100644 index f4e57f5..0000000 --- a/x-loader/include/asm/arch-omap4/sizes.h +++ /dev/null @@ -1,48 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -/* Size defintions - * Copyright (C) ARM Limited 1998. All rights reserved. - */ - -#ifndef __sizes_h -#define __sizes_h 1 - -/* handy sizes */ -#define SZ_1K 0x00000400 -#define SZ_4K 0x00001000 -#define SZ_8K 0x00002000 -#define SZ_16K 0x00004000 -#define SZ_32K 0x00008000 -#define SZ_64K 0x00010000 -#define SZ_128K 0x00020000 -#define SZ_256K 0x00040000 -#define SZ_512K 0x00080000 - -#define SZ_1M 0x00100000 -#define SZ_2M 0x00200000 -#define SZ_4M 0x00400000 -#define SZ_8M 0x00800000 -#define SZ_16M 0x01000000 -#define SZ_31M 0x01F00000 -#define SZ_32M 0x02000000 -#define SZ_64M 0x04000000 -#define SZ_128M 0x08000000 -#define SZ_256M 0x10000000 -#define SZ_512M 0x20000000 - -#define SZ_1G 0x40000000 -#define SZ_2G 0x80000000 - -#endif /* __sizes_h */ diff --git a/x-loader/include/asm/arch-omap4/sys_info.h b/x-loader/include/asm/arch-omap4/sys_info.h deleted file mode 100644 index bd90397..0000000 --- a/x-loader/include/asm/arch-omap4/sys_info.h +++ /dev/null @@ -1,75 +0,0 @@ -/* - * (C) Copyright 2006-2009 - * Texas Instruments, <www.ti.com> - * Richard Woodruff <r-woodruff2@ti.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _OMAP44XX_SYS_INFO_H_ -#define _OMAP44XX_SYS_INFO_H_ - -#define XDR_POP 5 /* package on package part */ -#define SDR_DISCRETE 4 /* 128M memory SDR module*/ -#define DDR_STACKED 3 /* stacked part on 2422 */ -#define DDR_COMBO 2 /* combo part on cpu daughter card (menalaeus) */ -#define DDR_DISCRETE 1 /* 2x16 parts on daughter card */ - -#define DDR_100 100 /* type found on most mem d-boards */ -#define DDR_111 111 /* some combo parts */ -#define DDR_133 133 /* most combo, some mem d-boards */ -#define DDR_165 165 /* future parts */ - -#define CPU_4430 0x4430 - -/* 343x real hardware: - * ES1 = rev 0 - */ - -/* 343x code defines: - * ES1 = 0+1 = 1 - * ES1 = 1+1 = 1 - */ -#define CPU_4430_ES1 1 - -/* Currently Virtio models this one */ -#define CPU_4430_CHIPID 0x0B68A000 - -#define GPMC_MUXED 1 -#define GPMC_NONMUXED 0 - -#define TYPE_NAND 0x800 /* bit pos for nand in gpmc reg */ -#define TYPE_NOR 0x000 -#define TYPE_ONENAND 0x800 - -#define WIDTH_8BIT 0x0000 -#define WIDTH_16BIT 0x1000 /* bit pos for 16 bit in gpmc */ - -#define I2C_MENELAUS 0x72 /* i2c id for companion chip */ -#define I2C_TRITON2 0x4B /* addres of power group */ - -#define BOOT_FAST_XIP 0x1f - -/* SDP definitions according to FPGA Rev. Is this OK?? */ -#define SDP_4430_VIRTIO 0x1 -#define SDP_4430_V1 0x2 - -#define BOARD_4430_LABRADOR 0x80 -#define BOARD_4430_LABRADOR_V1 0x1 - -#endif diff --git a/x-loader/include/asm/arch-omap4/sys_proto.h b/x-loader/include/asm/arch-omap4/sys_proto.h deleted file mode 100644 index eda9c5e..0000000 --- a/x-loader/include/asm/arch-omap4/sys_proto.h +++ /dev/null @@ -1,60 +0,0 @@ -/* - * (C) Copyright 2004-2009 - * Texas Instruments, <www.ti.com> - * Richard Woodruff <r-woodruff2@ti.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#ifndef _OMAP44XX_SYS_PROTO_H_ -#define _OMAP44XX_SYS_PROTO_H_ - -void prcm_init(void); -void per_clocks_enable(void); -void configure_core_dpll_no_lock(void); -void lock_core_dpll(void); -void lock_core_dpll_shadow(void); - -void memif_init(void); -void sdrc_init(void); -void do_sdrc_init(u32, u32); -void gpmc_init(void); - -void ether_init(void); -void watchdog_init(void); -void set_muxconf_regs(void); - -u32 get_cpu_type(void); -u32 get_cpu_rev(void); -u32 get_mem_type(void); -u32 get_sysboot_value(void); -u32 get_gpmc0_base(void); -u32 is_gpmc_muxed(void); -u32 get_gpmc0_type(void); -u32 get_gpmc0_width(void); -u32 get_board_type(void); -void display_board_info(u32); -void update_mux(u32, u32); -u32 get_sdr_cs_size(u32 offset); -u32 running_in_sdram(void); -u32 running_in_sram(void); -u32 running_in_flash(void); -u32 running_from_internal_boot(void); -u32 get_device_type(void); - -void sr32(u32 addr, u32 start_bit, u32 num_bits, u32 value); -u32 wait_on_value(u32 read_bit_mask, u32 match_value, u32 read_addr, u32 bound); -void sdelay(unsigned long loops); - -#endif diff --git a/x-loader/include/asm/atomic.h b/x-loader/include/asm/atomic.h deleted file mode 100644 index ba9e4b7..0000000 --- a/x-loader/include/asm/atomic.h +++ /dev/null @@ -1,113 +0,0 @@ -/* - * linux/include/asm-arm/atomic.h - * - * Copyright (c) 1996 Russell King. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * Changelog: - * 27-06-1996 RMK Created - * 13-04-1997 RMK Made functions atomic! - * 07-12-1997 RMK Upgraded for v2.1. - * 26-08-1998 PJB Added #ifdef __KERNEL__ - */ -#ifndef __ASM_ARM_ATOMIC_H -#define __ASM_ARM_ATOMIC_H - -#include <linux/config.h> - -#ifdef CONFIG_SMP -#error SMP not supported -#endif - -typedef struct { volatile int counter; } atomic_t; - -#define ATOMIC_INIT(i) { (i) } - -#ifdef __KERNEL__ -#include <asm/proc/system.h> - -#define atomic_read(v) ((v)->counter) -#define atomic_set(v,i) (((v)->counter) = (i)) - -static inline void atomic_add(int i, volatile atomic_t *v) -{ - unsigned long flags; - - local_irq_save(flags); - v->counter += i; - local_irq_restore(flags); -} - -static inline void atomic_sub(int i, volatile atomic_t *v) -{ - unsigned long flags; - - local_irq_save(flags); - v->counter -= i; - local_irq_restore(flags); -} - -static inline void atomic_inc(volatile atomic_t *v) -{ - unsigned long flags; - - local_irq_save(flags); - v->counter += 1; - local_irq_restore(flags); -} - -static inline void atomic_dec(volatile atomic_t *v) -{ - unsigned long flags; - - local_irq_save(flags); - v->counter -= 1; - local_irq_restore(flags); -} - -static inline int atomic_dec_and_test(volatile atomic_t *v) -{ - unsigned long flags; - int val; - - local_irq_save(flags); - val = v->counter; - v->counter = val -= 1; - local_irq_restore(flags); - - return val == 0; -} - -static inline int atomic_add_negative(int i, volatile atomic_t *v) -{ - unsigned long flags; - int val; - - local_irq_save(flags); - val = v->counter; - v->counter = val += i; - local_irq_restore(flags); - - return val < 0; -} - -static inline void atomic_clear_mask(unsigned long mask, unsigned long *addr) -{ - unsigned long flags; - - local_irq_save(flags); - *addr &= ~mask; - local_irq_restore(flags); -} - -/* Atomic operations are already serializing on ARM */ -#define smp_mb__before_atomic_dec() barrier() -#define smp_mb__after_atomic_dec() barrier() -#define smp_mb__before_atomic_inc() barrier() -#define smp_mb__after_atomic_inc() barrier() - -#endif -#endif diff --git a/x-loader/include/asm/byteorder.h b/x-loader/include/asm/byteorder.h deleted file mode 100755 index c3489f1..0000000 --- a/x-loader/include/asm/byteorder.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - * linux/include/asm-arm/byteorder.h - * - * ARM Endian-ness. In little endian mode, the data bus is connected such - * that byte accesses appear as: - * 0 = d0...d7, 1 = d8...d15, 2 = d16...d23, 3 = d24...d31 - * and word accesses (data or instruction) appear as: - * d0...d31 - * - * When in big endian mode, byte accesses appear as: - * 0 = d24...d31, 1 = d16...d23, 2 = d8...d15, 3 = d0...d7 - * and word accesses (data or instruction) appear as: - * d0...d31 - */ -#ifndef __ASM_ARM_BYTEORDER_H -#define __ASM_ARM_BYTEORDER_H - - -#include <asm/types.h> - -#if !defined(__STRICT_ANSI__) || defined(__KERNEL__) -# define __BYTEORDER_HAS_U64__ -# define __SWAB_64_THRU_32__ -#endif - -#ifdef __ARMEB__ -#include <linux/byteorder/big_endian.h> -#else -#include <linux/byteorder/little_endian.h> -#endif - -#endif diff --git a/x-loader/include/asm/errno.h b/x-loader/include/asm/errno.h deleted file mode 100644 index 39dc515..0000000 --- a/x-loader/include/asm/errno.h +++ /dev/null @@ -1,155 +0,0 @@ -/* - * U-boot - errno.h Error number defines - * - * Copyright (c) 2005-2007 Analog Devices Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -#ifndef _GENERIC_ERRNO_H -#define _GENERIC_ERRNO_H - -#define EPERM 1 /* Operation not permitted */ -#define ENOENT 2 /* No such file or directory */ -#define ESRCH 3 /* No such process */ -#define EINTR 4 /* Interrupted system call */ -#define EIO 5 /* I/O error */ -#define ENXIO 6 /* No such device or address */ -#define E2BIG 7 /* Argument list too long */ -#define ENOEXEC 8 /* Exec format error */ -#define EBADF 9 /* Bad file number */ -#define ECHILD 10 /* No child processes */ -#define EAGAIN 11 /* Try again */ -#define ENOMEM 12 /* Out of memory */ -#define EACCES 13 /* Permission denied */ -#define EFAULT 14 /* Bad address */ -#define ENOTBLK 15 /* Block device required */ -#define EBUSY 16 /* Device or resource busy */ -#define EEXIST 17 /* File exists */ -#define EXDEV 18 /* Cross-device link */ -#define ENODEV 19 /* No such device */ -#define ENOTDIR 20 /* Not a directory */ -#define EISDIR 21 /* Is a directory */ -#define EINVAL 22 /* Invalid argument */ -#define ENFILE 23 /* File table overflow */ -#define EMFILE 24 /* Too many open files */ -#define ENOTTY 25 /* Not a typewriter */ -#define ETXTBSY 26 /* Text file busy */ -#define EFBIG 27 /* File too large */ -#define ENOSPC 28 /* No space left on device */ -#define ESPIPE 29 /* Illegal seek */ -#define EROFS 30 /* Read-only file system */ -#define EMLINK 31 /* Too many links */ -#define EPIPE 32 /* Broken pipe */ -#define EDOM 33 /* Math argument out of domain of func */ -#define ERANGE 34 /* Math result not representable */ -#define EDEADLK 35 /* Resource deadlock would occur */ -#define ENAMETOOLONG 36 /* File name too long */ -#define ENOLCK 37 /* No record locks available */ -#define ENOSYS 38 /* Function not implemented */ -#define ENOTEMPTY 39 /* Directory not empty */ -#define ELOOP 40 /* Too many symbolic links encountered */ -#define EWOULDBLOCK EAGAIN /* Operation would block */ -#define ENOMSG 42 /* No message of desired type */ -#define EIDRM 43 /* Identifier removed */ -#define ECHRNG 44 /* Channel number out of range */ -#define EL2NSYNC 45 /* Level 2 not synchronized */ -#define EL3HLT 46 /* Level 3 halted */ -#define EL3RST 47 /* Level 3 reset */ -#define ELNRNG 48 /* Link number out of range */ -#define EUNATCH 49 /* Protocol driver not attached */ -#define ENOCSI 50 /* No CSI structure available */ -#define EL2HLT 51 /* Level 2 halted */ -#define EBADE 52 /* Invalid exchange */ -#define EBADR 53 /* Invalid request descriptor */ -#define EXFULL 54 /* Exchange full */ -#define ENOANO 55 /* No anode */ -#define EBADRQC 56 /* Invalid request code */ -#define EBADSLT 57 /* Invalid slot */ - -#define EDEADLOCK EDEADLK - -#define EBFONT 59 /* Bad font file format */ -#define ENOSTR 60 /* Device not a stream */ -#define ENODATA 61 /* No data available */ -#define ETIME 62 /* Timer expired */ -#define ENOSR 63 /* Out of streams resources */ -#define ENONET 64 /* Machine is not on the network */ -#define ENOPKG 65 /* Package not installed */ -#define EREMOTE 66 /* Object is remote */ -#define ENOLINK 67 /* Link has been severed */ -#define EADV 68 /* Advertise error */ -#define ESRMNT 69 /* Srmount error */ -#define ECOMM 70 /* Communication error on send */ -#define EPROTO 71 /* Protocol error */ -#define EMULTIHOP 72 /* Multihop attempted */ -#define EDOTDOT 73 /* RFS specific error */ -#define EBADMSG 74 /* Not a data message */ -#define EOVERFLOW 75 /* Value too large for defined data type */ -#define ENOTUNIQ 76 /* Name not unique on network */ -#define EBADFD 77 /* File descriptor in bad state */ -#define EREMCHG 78 /* Remote address changed */ -#define ELIBACC 79 /* Can not access a needed shared library */ -#define ELIBBAD 80 /* Accessing a corrupted shared library */ -#define ELIBSCN 81 /* .lib section in a.out corrupted */ -#define ELIBMAX 82 /* Attempting to link in too many shared libraries */ -#define ELIBEXEC 83 /* Cannot exec a shared library directly */ -#define EILSEQ 84 /* Illegal byte sequence */ -#define ERESTART 85 /* Interrupted system call should be restarted */ -#define ESTRPIPE 86 /* Streams pipe error */ -#define EUSERS 87 /* Too many users */ -#define ENOTSOCK 88 /* Socket operation on non-socket */ -#define EDESTADDRREQ 89 /* Destination address required */ -#define EMSGSIZE 90 /* Message too long */ -#define EPROTOTYPE 91 /* Protocol wrong type for socket */ -#define ENOPROTOOPT 92 /* Protocol not available */ -#define EPROTONOSUPPORT 93 /* Protocol not supported */ -#define ESOCKTNOSUPPORT 94 /* Socket type not supported */ -#define EOPNOTSUPP 95 /* Operation not supported on transport endpoint */ -#define EPFNOSUPPORT 96 /* Protocol family not supported */ -#define EAFNOSUPPORT 97 /* Address family not supported by protocol */ -#define EADDRINUSE 98 /* Address already in use */ -#define EADDRNOTAVAIL 99 /* Cannot assign requested address */ -#define ENETDOWN 100 /* Network is down */ -#define ENETUNREACH 101 /* Network is unreachable */ -#define ENETRESET 102 /* Network dropped connection because of reset */ -#define ECONNABORTED 103 /* Software caused connection abort */ -#define ECONNRESET 104 /* Connection reset by peer */ -#define ENOBUFS 105 /* No buffer space available */ -#define EISCONN 106 /* Transport endpoint is already connected */ -#define ENOTCONN 107 /* Transport endpoint is not connected */ -#define ESHUTDOWN 108 /* Cannot send after transport endpoint shutdown */ -#define ETOOMANYREFS 109 /* Too many references: cannot splice */ -#define ETIMEDOUT 110 /* Connection timed out */ -#define ECONNREFUSED 111 /* Connection refused */ -#define EHOSTDOWN 112 /* Host is down */ -#define EHOSTUNREACH 113 /* No route to host */ -#define EALREADY 114 /* Operation already in progress */ -#define EINPROGRESS 115 /* Operation now in progress */ -#define ESTALE 116 /* Stale NFS file handle */ -#define EUCLEAN 117 /* Structure needs cleaning */ -#define ENOTNAM 118 /* Not a XENIX named type file */ -#define ENAVAIL 119 /* No XENIX semaphores available */ -#define EISNAM 120 /* Is a named type file */ -#define EREMOTEIO 121 /* Remote I/O error */ -#define EDQUOT 122 /* Quota exceeded */ -#define ENOMEDIUM 123 /* No medium found */ -#define EMEDIUMTYPE 124 /* Wrong medium type */ - -#endif diff --git a/x-loader/include/asm/io.h b/x-loader/include/asm/io.h deleted file mode 100644 index f4ae307..0000000 --- a/x-loader/include/asm/io.h +++ /dev/null @@ -1,335 +0,0 @@ -/* - * linux/include/asm-arm/io.h - * - * Copyright (C) 1996-2000 Russell King - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * Modifications: - * 16-Sep-1996 RMK Inlined the inx/outx functions & optimised for both - * constant addresses and variable addresses. - * 04-Dec-1997 RMK Moved a lot of this stuff to the new architecture - * specific IO header files. - * 27-Mar-1999 PJB Second parameter of memcpy_toio is const.. - * 04-Apr-1999 PJB Added check_signature. - * 12-Dec-1999 RMK More cleanups - * 18-Jun-2000 RMK Removed virt_to_* and friends definitions - */ -#ifndef __ASM_ARM_IO_H -#define __ASM_ARM_IO_H - -#ifdef __KERNEL__ - -#include <linux/types.h> -#include <asm/byteorder.h> -#include <asm/memory.h> -#if 0 /* XXX###XXX */ -#include <asm/arch/hardware.h> -#endif /* XXX###XXX */ - -static inline void sync(void) -{ -} - -/* - * Given a physical address and a length, return a virtual address - * that can be used to access the memory range with the caching - * properties specified by "flags". - */ -#define MAP_NOCACHE (0) -#define MAP_WRCOMBINE (0) -#define MAP_WRBACK (0) -#define MAP_WRTHROUGH (0) - -static inline void * -map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags) -{ - return (void *)paddr; -} - -/* - * Take down a mapping set up by map_physmem(). - */ -static inline void unmap_physmem(void *vaddr, unsigned long flags) -{ - -} - -/* - * Generic virtual read/write. Note that we don't support half-word - * read/writes. We define __arch_*[bl] here, and leave __arch_*w - * to the architecture specific code. - */ -#define __arch_getb(a) (*(volatile unsigned char *)(a)) -#define __arch_getw(a) (*(volatile unsigned short *)(a)) -#define __arch_getl(a) (*(volatile unsigned int *)(a)) - -#define __arch_putb(v,a) (*(volatile unsigned char *)(a) = (v)) -#define __arch_putw(v,a) (*(volatile unsigned short *)(a) = (v)) -#define __arch_putl(v,a) (*(volatile unsigned int *)(a) = (v)) - -extern void __raw_writesb(unsigned int addr, const void *data, int bytelen); -extern void __raw_writesw(unsigned int addr, const void *data, int wordlen); -extern void __raw_writesl(unsigned int addr, const void *data, int longlen); - -extern void __raw_readsb(unsigned int addr, void *data, int bytelen); -extern void __raw_readsw(unsigned int addr, void *data, int wordlen); -extern void __raw_readsl(unsigned int addr, void *data, int longlen); - -#define __raw_writeb(v,a) __arch_putb(v,a) -#define __raw_writew(v,a) __arch_putw(v,a) -#define __raw_writel(v,a) __arch_putl(v,a) - -#define __raw_readb(a) __arch_getb(a) -#define __raw_readw(a) __arch_getw(a) -#define __raw_readl(a) __arch_getl(a) - -#define writeb(v,a) __arch_putb(v,a) -#define writew(v,a) __arch_putw(v,a) -#define writel(v,a) __arch_putl(v,a) - -#define readb(a) __arch_getb(a) -#define readw(a) __arch_getw(a) -#define readl(a) __arch_getl(a) - -/* - * The compiler seems to be incapable of optimising constants - * properly. Spell it out to the compiler in some cases. - * These are only valid for small values of "off" (< 1<<12) - */ -#define __raw_base_writeb(val,base,off) __arch_base_putb(val,base,off) -#define __raw_base_writew(val,base,off) __arch_base_putw(val,base,off) -#define __raw_base_writel(val,base,off) __arch_base_putl(val,base,off) - -#define __raw_base_readb(base,off) __arch_base_getb(base,off) -#define __raw_base_readw(base,off) __arch_base_getw(base,off) -#define __raw_base_readl(base,off) __arch_base_getl(base,off) - -/* - * Now, pick up the machine-defined IO definitions - */ -#if 0 /* XXX###XXX */ -#include <asm/arch/io.h> -#endif /* XXX###XXX */ - -/* - * IO port access primitives - * ------------------------- - * - * The ARM doesn't have special IO access instructions; all IO is memory - * mapped. Note that these are defined to perform little endian accesses - * only. Their primary purpose is to access PCI and ISA peripherals. - * - * Note that for a big endian machine, this implies that the following - * big endian mode connectivity is in place, as described by numerous - * ARM documents: - * - * PCI: D0-D7 D8-D15 D16-D23 D24-D31 - * ARM: D24-D31 D16-D23 D8-D15 D0-D7 - * - * The machine specific io.h include defines __io to translate an "IO" - * address to a memory address. - * - * Note that we prevent GCC re-ordering or caching values in expressions - * by introducing sequence points into the in*() definitions. Note that - * __raw_* do not guarantee this behaviour. - * - * The {in,out}[bwl] macros are for emulating x86-style PCI/ISA IO space. - */ -#ifdef __io -#define outb(v,p) __raw_writeb(v,__io(p)) -#define outw(v,p) __raw_writew(cpu_to_le16(v),__io(p)) -#define outl(v,p) __raw_writel(cpu_to_le32(v),__io(p)) - -#define inb(p) ({ unsigned int __v = __raw_readb(__io(p)); __v; }) -#define inw(p) ({ unsigned int __v = le16_to_cpu(__raw_readw(__io(p))); __v; }) -#define inl(p) ({ unsigned int __v = le32_to_cpu(__raw_readl(__io(p))); __v; }) - -#define outsb(p,d,l) __raw_writesb(__io(p),d,l) -#define outsw(p,d,l) __raw_writesw(__io(p),d,l) -#define outsl(p,d,l) __raw_writesl(__io(p),d,l) - -#define insb(p,d,l) __raw_readsb(__io(p),d,l) -#define insw(p,d,l) __raw_readsw(__io(p),d,l) -#define insl(p,d,l) __raw_readsl(__io(p),d,l) -#endif - -#define outb_p(val,port) outb((val),(port)) -#define outw_p(val,port) outw((val),(port)) -#define outl_p(val,port) outl((val),(port)) -#define inb_p(port) inb((port)) -#define inw_p(port) inw((port)) -#define inl_p(port) inl((port)) - -#define outsb_p(port,from,len) outsb(port,from,len) -#define outsw_p(port,from,len) outsw(port,from,len) -#define outsl_p(port,from,len) outsl(port,from,len) -#define insb_p(port,to,len) insb(port,to,len) -#define insw_p(port,to,len) insw(port,to,len) -#define insl_p(port,to,len) insl(port,to,len) - -/* - * ioremap and friends. - * - * ioremap takes a PCI memory address, as specified in - * linux/Documentation/IO-mapping.txt. If you want a - * physical address, use __ioremap instead. - */ -extern void * __ioremap(unsigned long offset, size_t size, unsigned long flags); -extern void __iounmap(void *addr); - -/* - * Generic ioremap support. - * - * Define: - * iomem_valid_addr(off,size) - * iomem_to_phys(off) - */ -#ifdef iomem_valid_addr -#define __arch_ioremap(off,sz,nocache) \ - ({ \ - unsigned long _off = (off), _size = (sz); \ - void *_ret = (void *)0; \ - if (iomem_valid_addr(_off, _size)) \ - _ret = __ioremap(iomem_to_phys(_off),_size,0); \ - _ret; \ - }) - -#define __arch_iounmap __iounmap -#endif - -#define ioremap(off,sz) __arch_ioremap((off),(sz),0) -#define ioremap_nocache(off,sz) __arch_ioremap((off),(sz),1) -#define iounmap(_addr) __arch_iounmap(_addr) - -/* - * DMA-consistent mapping functions. These allocate/free a region of - * uncached, unwrite-buffered mapped memory space for use with DMA - * devices. This is the "generic" version. The PCI specific version - * is in pci.h - */ -extern void *consistent_alloc(int gfp, size_t size, dma_addr_t *handle); -extern void consistent_free(void *vaddr, size_t size, dma_addr_t handle); -extern void consistent_sync(void *vaddr, size_t size, int rw); - -/* - * String version of IO memory access ops: - */ -extern void _memcpy_fromio(void *, unsigned long, size_t); -extern void _memcpy_toio(unsigned long, const void *, size_t); -extern void _memset_io(unsigned long, int, size_t); - -extern void __readwrite_bug(const char *fn); - -/* - * If this architecture has PCI memory IO, then define the read/write - * macros. These should only be used with the cookie passed from - * ioremap. - */ -#ifdef __mem_pci - -#define readb(c) ({ unsigned int __v = __raw_readb(__mem_pci(c)); __v; }) -#define readw(c) ({ unsigned int __v = le16_to_cpu(__raw_readw(__mem_pci(c))); __v; }) -#define readl(c) ({ unsigned int __v = le32_to_cpu(__raw_readl(__mem_pci(c))); __v; }) - -#define writeb(v,c) __raw_writeb(v,__mem_pci(c)) -#define writew(v,c) __raw_writew(cpu_to_le16(v),__mem_pci(c)) -#define writel(v,c) __raw_writel(cpu_to_le32(v),__mem_pci(c)) - -#define memset_io(c,v,l) _memset_io(__mem_pci(c),(v),(l)) -#define memcpy_fromio(a,c,l) _memcpy_fromio((a),__mem_pci(c),(l)) -#define memcpy_toio(c,a,l) _memcpy_toio(__mem_pci(c),(a),(l)) - -#define eth_io_copy_and_sum(s,c,l,b) \ - eth_copy_and_sum((s),__mem_pci(c),(l),(b)) - -static inline int -check_signature(unsigned long io_addr, const unsigned char *signature, - int length) -{ - int retval = 0; - do { - if (readb(io_addr) != *signature) - goto out; - io_addr++; - signature++; - length--; - } while (length); - retval = 1; -out: - return retval; -} - -#elif !defined(readb) - -#define readb(addr) (__readwrite_bug("readb"),0) -#define readw(addr) (__readwrite_bug("readw"),0) -#define readl(addr) (__readwrite_bug("readl"),0) -#define writeb(v,addr) __readwrite_bug("writeb") -#define writew(v,addr) __readwrite_bug("writew") -#define writel(v,addr) __readwrite_bug("writel") - -#define eth_io_copy_and_sum(a,b,c,d) __readwrite_bug("eth_io_copy_and_sum") - -#define check_signature(io,sig,len) (0) - -#endif /* __mem_pci */ - -/* - * If this architecture has ISA IO, then define the isa_read/isa_write - * macros. - */ -#ifdef __mem_isa - -#define isa_readb(addr) __raw_readb(__mem_isa(addr)) -#define isa_readw(addr) __raw_readw(__mem_isa(addr)) -#define isa_readl(addr) __raw_readl(__mem_isa(addr)) -#define isa_writeb(val,addr) __raw_writeb(val,__mem_isa(addr)) -#define isa_writew(val,addr) __raw_writew(val,__mem_isa(addr)) -#define isa_writel(val,addr) __raw_writel(val,__mem_isa(addr)) -#define isa_memset_io(a,b,c) _memset_io(__mem_isa(a),(b),(c)) -#define isa_memcpy_fromio(a,b,c) _memcpy_fromio((a),__mem_isa(b),(c)) -#define isa_memcpy_toio(a,b,c) _memcpy_toio(__mem_isa((a)),(b),(c)) - -#define isa_eth_io_copy_and_sum(a,b,c,d) \ - eth_copy_and_sum((a),__mem_isa(b),(c),(d)) - -static inline int -isa_check_signature(unsigned long io_addr, const unsigned char *signature, - int length) -{ - int retval = 0; - do { - if (isa_readb(io_addr) != *signature) - goto out; - io_addr++; - signature++; - length--; - } while (length); - retval = 1; -out: - return retval; -} - -#else /* __mem_isa */ - -#define isa_readb(addr) (__readwrite_bug("isa_readb"),0) -#define isa_readw(addr) (__readwrite_bug("isa_readw"),0) -#define isa_readl(addr) (__readwrite_bug("isa_readl"),0) -#define isa_writeb(val,addr) __readwrite_bug("isa_writeb") -#define isa_writew(val,addr) __readwrite_bug("isa_writew") -#define isa_writel(val,addr) __readwrite_bug("isa_writel") -#define isa_memset_io(a,b,c) __readwrite_bug("isa_memset_io") -#define isa_memcpy_fromio(a,b,c) __readwrite_bug("isa_memcpy_fromio") -#define isa_memcpy_toio(a,b,c) __readwrite_bug("isa_memcpy_toio") - -#define isa_eth_io_copy_and_sum(a,b,c,d) \ - __readwrite_bug("isa_eth_io_copy_and_sum") - -#define isa_check_signature(io,sig,len) (0) - -#endif /* __mem_isa */ -#endif /* __KERNEL__ */ -#endif /* __ASM_ARM_IO_H */ diff --git a/x-loader/include/asm/memory.h b/x-loader/include/asm/memory.h deleted file mode 100644 index c3b2afd..0000000 --- a/x-loader/include/asm/memory.h +++ /dev/null @@ -1,137 +0,0 @@ -/* - * linux/include/asm-arm/memory.h - * - * Copyright (C) 2000-2002 Russell King - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * Note: this file should not be included by non-asm/.h files - */ -#ifndef __ASM_ARM_MEMORY_H -#define __ASM_ARM_MEMORY_H - -#if 0 /* XXX###XXX */ - -#include <linux/config.h> -#include <asm/arch/memory.h> - -/* - * PFNs are used to describe any physical page; this means - * PFN 0 == physical address 0. - * - * This is the PFN of the first RAM page in the kernel - * direct-mapped view. We assume this is the first page - * of RAM in the mem_map as well. - */ -#define PHYS_PFN_OFFSET (PHYS_OFFSET >> PAGE_SHIFT) - -/* - * These are *only* valid on the kernel direct mapped RAM memory. - */ -static inline unsigned long virt_to_phys(void *x) -{ - return __virt_to_phys((unsigned long)(x)); -} - -static inline void *phys_to_virt(unsigned long x) -{ - return (void *)(__phys_to_virt((unsigned long)(x))); -} - -#define __pa(x) __virt_to_phys((unsigned long)(x)) -#define __va(x) ((void *)__phys_to_virt((unsigned long)(x))) - -/* - * Virtual <-> DMA view memory address translations - * Again, these are *only* valid on the kernel direct mapped RAM - * memory. Use of these is *depreciated*. - */ -#define virt_to_bus(x) (__virt_to_bus((unsigned long)(x))) -#define bus_to_virt(x) ((void *)(__bus_to_virt((unsigned long)(x)))) - -/* - * Conversion between a struct page and a physical address. - * - * Note: when converting an unknown physical address to a - * struct page, the resulting pointer must be validated - * using VALID_PAGE(). It must return an invalid struct page - * for any physical address not corresponding to a system - * RAM address. - * - * page_to_pfn(page) convert a struct page * to a PFN number - * pfn_to_page(pfn) convert a _valid_ PFN number to struct page * - * pfn_valid(pfn) indicates whether a PFN number is valid - * - * virt_to_page(k) convert a _valid_ virtual address to struct page * - * virt_addr_valid(k) indicates whether a virtual address is valid - */ -#ifndef CONFIG_DISCONTIGMEM - -#define page_to_pfn(page) (((page) - mem_map) + PHYS_PFN_OFFSET) -#define pfn_to_page(pfn) ((mem_map + (pfn)) - PHYS_PFN_OFFSET) -#define pfn_valid(pfn) ((pfn) >= PHYS_PFN_OFFSET && (pfn) < (PHYS_PFN_OFFSET + max_mapnr)) - -#define virt_to_page(kaddr) (pfn_to_page(__pa(kaddr) >> PAGE_SHIFT)) -#define virt_addr_valid(kaddr) ((kaddr) >= PAGE_OFFSET && (kaddr) < (unsigned long)high_memory) - -#define PHYS_TO_NID(addr) (0) - -#define VALID_PAGE(page) ((page - mem_map) < max_mapnr) - -#else - -/* - * This is more complex. We have a set of mem_map arrays spread - * around in memory. - */ -#define page_to_pfn(page) \ - (((page) - page_zone(page)->zone_mem_map) \ - + (page_zone(page)->zone_start_paddr >> PAGE_SHIFT)) - -#define pfn_to_page(pfn) \ - (PFN_TO_MAPBASE(pfn) + LOCAL_MAP_NR((pfn) << PAGE_SHIFT)) - -#define pfn_valid(pfn) \ - ({ \ - unsigned int node = PFN_TO_NID(pfn); \ - struct pglist_data *nd = NODE_DATA(node); \ - ((node < NR_NODES) && \ - ((pfn - (nd->node_start_paddr >> PAGE_SHIFT)) < nd->node_size));\ - }) - -#define virt_to_page(kaddr) \ - (ADDR_TO_MAPBASE(kaddr) + LOCAL_MAP_NR(kaddr)) - -#define virt_addr_valid(kaddr) (KVADDR_TO_NID(kaddr) < NR_NODES) - -/* - * Common discontigmem stuff. - * PHYS_TO_NID is used by the ARM kernel/setup.c - */ -#define PHYS_TO_NID(addr) PFN_TO_NID((addr) >> PAGE_SHIFT) - -/* - * 2.4 compatibility - * - * VALID_PAGE returns a non-zero value if given page pointer is valid. - * This assumes all node's mem_maps are stored within the node they - * refer to. This is actually inherently buggy. - */ -#define VALID_PAGE(page) \ -({ unsigned int node = KVADDR_TO_NID(page); \ - ((node < NR_NODES) && \ - ((unsigned)((page) - NODE_MEM_MAP(node)) < NODE_DATA(node)->node_size)); \ -}) - -#endif - -/* - * We should really eliminate virt_to_bus() here - it's depreciated. - */ -#define page_to_bus(page) (virt_to_bus(page_address(page))) - -#endif /* XXX###XXX */ - -#endif /* __ASM_ARM_MEMORY_H */ diff --git a/x-loader/include/asm/posix_types.h b/x-loader/include/asm/posix_types.h deleted file mode 100644 index c412486..0000000 --- a/x-loader/include/asm/posix_types.h +++ /dev/null @@ -1,79 +0,0 @@ -/* - * linux/include/asm-arm/posix_types.h - * - * Copyright (C) 1996-1998 Russell King. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * Changelog: - * 27-06-1996 RMK Created - */ -#ifndef __ARCH_ARM_POSIX_TYPES_H -#define __ARCH_ARM_POSIX_TYPES_H - -/* - * This file is generally used by user-level software, so you need to - * be a little careful about namespace pollution etc. Also, we cannot - * assume GCC is being used. - */ - -typedef unsigned short __kernel_dev_t; -typedef unsigned long __kernel_ino_t; -typedef unsigned short __kernel_mode_t; -typedef unsigned short __kernel_nlink_t; -typedef long __kernel_off_t; -typedef int __kernel_pid_t; -typedef unsigned short __kernel_ipc_pid_t; -typedef unsigned short __kernel_uid_t; -typedef unsigned short __kernel_gid_t; -typedef unsigned int __kernel_size_t; -typedef int __kernel_ssize_t; -typedef int __kernel_ptrdiff_t; -typedef long __kernel_time_t; -typedef long __kernel_suseconds_t; -typedef long __kernel_clock_t; -typedef int __kernel_daddr_t; -typedef char * __kernel_caddr_t; -typedef unsigned short __kernel_uid16_t; -typedef unsigned short __kernel_gid16_t; -typedef unsigned int __kernel_uid32_t; -typedef unsigned int __kernel_gid32_t; - -typedef unsigned short __kernel_old_uid_t; -typedef unsigned short __kernel_old_gid_t; - -#ifdef __GNUC__ -typedef long long __kernel_loff_t; -#endif - -typedef struct { -#if defined(__KERNEL__) || defined(__USE_ALL) - int val[2]; -#else /* !defined(__KERNEL__) && !defined(__USE_ALL) */ - int __val[2]; -#endif /* !defined(__KERNEL__) && !defined(__USE_ALL) */ -} __kernel_fsid_t; - -#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) - -#undef __FD_SET -#define __FD_SET(fd, fdsetp) \ - (((fd_set *)fdsetp)->fds_bits[fd >> 5] |= (1<<(fd & 31))) - -#undef __FD_CLR -#define __FD_CLR(fd, fdsetp) \ - (((fd_set *)fdsetp)->fds_bits[fd >> 5] &= ~(1<<(fd & 31))) - -#undef __FD_ISSET -#define __FD_ISSET(fd, fdsetp) \ - ((((fd_set *)fdsetp)->fds_bits[fd >> 5] & (1<<(fd & 31))) != 0) - -#undef __FD_ZERO -#define __FD_ZERO(fdsetp) \ - (memset (fdsetp, 0, sizeof (*(fd_set *)fdsetp))) - -#endif - -#endif diff --git a/x-loader/include/asm/setup.h b/x-loader/include/asm/setup.h deleted file mode 100644 index 89df4dc..0000000 --- a/x-loader/include/asm/setup.h +++ /dev/null @@ -1,269 +0,0 @@ -/* - * linux/include/asm/setup.h - * - * Copyright (C) 1997-1999 Russell King - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * Structure passed to kernel to tell it about the - * hardware it's running on. See linux/Documentation/arm/Setup - * for more info. - * - * NOTE: - * This file contains two ways to pass information from the boot - * loader to the kernel. The old struct param_struct is deprecated, - * but it will be kept in the kernel for 5 years from now - * (2001). This will allow boot loaders to convert to the new struct - * tag way. - */ -#ifndef __ASMARM_SETUP_H -#define __ASMARM_SETUP_H - -/* - * Usage: - * - do not go blindly adding fields, add them at the end - * - when adding fields, don't rely on the address until - * a patch from me has been released - * - unused fields should be zero (for future expansion) - * - this structure is relatively short-lived - only - * guaranteed to contain useful data in setup_arch() - */ -#define COMMAND_LINE_SIZE 1024 - -/* This is the old deprecated way to pass parameters to the kernel */ -struct param_struct { - union { - struct { - unsigned long page_size; /* 0 */ - unsigned long nr_pages; /* 4 */ - unsigned long ramdisk_size; /* 8 */ - unsigned long flags; /* 12 */ -#define FLAG_READONLY 1 -#define FLAG_RDLOAD 4 -#define FLAG_RDPROMPT 8 - unsigned long rootdev; /* 16 */ - unsigned long video_num_cols; /* 20 */ - unsigned long video_num_rows; /* 24 */ - unsigned long video_x; /* 28 */ - unsigned long video_y; /* 32 */ - unsigned long memc_control_reg; /* 36 */ - unsigned char sounddefault; /* 40 */ - unsigned char adfsdrives; /* 41 */ - unsigned char bytes_per_char_h; /* 42 */ - unsigned char bytes_per_char_v; /* 43 */ - unsigned long pages_in_bank[4]; /* 44 */ - unsigned long pages_in_vram; /* 60 */ - unsigned long initrd_start; /* 64 */ - unsigned long initrd_size; /* 68 */ - unsigned long rd_start; /* 72 */ - unsigned long system_rev; /* 76 */ - unsigned long system_serial_low; /* 80 */ - unsigned long system_serial_high; /* 84 */ - unsigned long mem_fclk_21285; /* 88 */ - } s; - char unused[256]; - } u1; - union { - char paths[8][128]; - struct { - unsigned long magic; - char n[1024 - sizeof(unsigned long)]; - } s; - } u2; - char commandline[COMMAND_LINE_SIZE]; -}; - - -/* - * The new way of passing information: a list of tagged entries - */ - -/* The list ends with an ATAG_NONE node. */ -#define ATAG_NONE 0x00000000 - -struct tag_header { - u32 size; - u32 tag; -}; - -/* The list must start with an ATAG_CORE node */ -#define ATAG_CORE 0x54410001 - -struct tag_core { - u32 flags; /* bit 0 = read-only */ - u32 pagesize; - u32 rootdev; -}; - -/* it is allowed to have multiple ATAG_MEM nodes */ -#define ATAG_MEM 0x54410002 - -struct tag_mem32 { - u32 size; - u32 start; /* physical start address */ -}; - -/* VGA text type displays */ -#define ATAG_VIDEOTEXT 0x54410003 - -struct tag_videotext { - u8 x; - u8 y; - u16 video_page; - u8 video_mode; - u8 video_cols; - u16 video_ega_bx; - u8 video_lines; - u8 video_isvga; - u16 video_points; -}; - -/* describes how the ramdisk will be used in kernel */ -#define ATAG_RAMDISK 0x54410004 - -struct tag_ramdisk { - u32 flags; /* bit 0 = load, bit 1 = prompt */ - u32 size; /* decompressed ramdisk size in _kilo_ bytes */ - u32 start; /* starting block of floppy-based RAM disk image */ -}; - -/* describes where the compressed ramdisk image lives (virtual address) */ -/* - * this one accidentally used virtual addresses - as such, - * its depreciated. - */ -#define ATAG_INITRD 0x54410005 - -/* describes where the compressed ramdisk image lives (physical address) */ -#define ATAG_INITRD2 0x54420005 - -struct tag_initrd { - u32 start; /* physical start address */ - u32 size; /* size of compressed ramdisk image in bytes */ -}; - -/* board serial number. "64 bits should be enough for everybody" */ -#define ATAG_SERIAL 0x54410006 - -struct tag_serialnr { - u32 low; - u32 high; -}; - -/* board revision */ -#define ATAG_REVISION 0x54410007 - -struct tag_revision { - u32 rev; -}; - -/* initial values for vesafb-type framebuffers. see struct screen_info - * in include/linux/tty.h - */ -#define ATAG_VIDEOLFB 0x54410008 - -struct tag_videolfb { - u16 lfb_width; - u16 lfb_height; - u16 lfb_depth; - u16 lfb_linelength; - u32 lfb_base; - u32 lfb_size; - u8 red_size; - u8 red_pos; - u8 green_size; - u8 green_pos; - u8 blue_size; - u8 blue_pos; - u8 rsvd_size; - u8 rsvd_pos; -}; - -/* command line: \0 terminated string */ -#define ATAG_CMDLINE 0x54410009 - -struct tag_cmdline { - char cmdline[1]; /* this is the minimum size */ -}; - -/* acorn RiscPC specific information */ -#define ATAG_ACORN 0x41000101 - -struct tag_acorn { - u32 memc_control_reg; - u32 vram_pages; - u8 sounddefault; - u8 adfsdrives; -}; - -/* footbridge memory clock, see arch/arm/mach-footbridge/arch.c */ -#define ATAG_MEMCLK 0x41000402 - -struct tag_memclk { - u32 fmemclk; -}; - -struct tag { - struct tag_header hdr; - union { - struct tag_core core; - struct tag_mem32 mem; - struct tag_videotext videotext; - struct tag_ramdisk ramdisk; - struct tag_initrd initrd; - struct tag_serialnr serialnr; - struct tag_revision revision; - struct tag_videolfb videolfb; - struct tag_cmdline cmdline; - - /* - * Acorn specific - */ - struct tag_acorn acorn; - - /* - * DC21285 specific - */ - struct tag_memclk memclk; - } u; -}; - -struct tagtable { - u32 tag; - int (*parse)(const struct tag *); -}; - -#define __tag __attribute__((unused, __section__(".taglist"))) -#define __tagtable(tag, fn) \ -static struct tagtable __tagtable_##fn __tag = { tag, fn } - -#define tag_member_present(tag,member) \ - ((unsigned long)(&((struct tag *)0L)->member + 1) \ - <= (tag)->hdr.size * 4) - -#define tag_next(t) ((struct tag *)((u32 *)(t) + (t)->hdr.size)) -#define tag_size(type) ((sizeof(struct tag_header) + sizeof(struct type)) >> 2) - -#define for_each_tag(t,base) \ - for (t = base; t->hdr.size; t = tag_next(t)) - -/* - * Memory map description - */ -#define NR_BANKS 8 - -struct meminfo { - int nr_banks; - unsigned long end; - struct { - unsigned long start; - unsigned long size; - int node; - } bank[NR_BANKS]; -}; - -extern struct meminfo meminfo; - -#endif diff --git a/x-loader/include/asm/sizes.h b/x-loader/include/asm/sizes.h deleted file mode 100644 index f8d92ca..0000000 --- a/x-loader/include/asm/sizes.h +++ /dev/null @@ -1,52 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -/* DO NOT EDIT!! - this file automatically generated - * from .s file by awk -f s2h.awk - */ -/* Size defintions - * Copyright (C) ARM Limited 1998. All rights reserved. - */ - -#ifndef __sizes_h -#define __sizes_h 1 - -/* handy sizes */ -#define SZ_1K 0x00000400 -#define SZ_4K 0x00001000 -#define SZ_8K 0x00002000 -#define SZ_16K 0x00004000 -#define SZ_64K 0x00010000 -#define SZ_128K 0x00020000 -#define SZ_256K 0x00040000 -#define SZ_512K 0x00080000 - -#define SZ_1M 0x00100000 -#define SZ_2M 0x00200000 -#define SZ_4M 0x00400000 -#define SZ_8M 0x00800000 -#define SZ_16M 0x01000000 -#define SZ_32M 0x02000000 -#define SZ_64M 0x04000000 -#define SZ_128M 0x08000000 -#define SZ_256M 0x10000000 -#define SZ_512M 0x20000000 - -#define SZ_1G 0x40000000 -#define SZ_2G 0x80000000 - -#endif - -/* END */ diff --git a/x-loader/include/asm/string.h b/x-loader/include/asm/string.h deleted file mode 100644 index c3ea582..0000000 --- a/x-loader/include/asm/string.h +++ /dev/null @@ -1,47 +0,0 @@ -#ifndef __ASM_ARM_STRING_H -#define __ASM_ARM_STRING_H - -/* - * We don't do inline string functions, since the - * optimised inline asm versions are not small. - */ - -#undef __HAVE_ARCH_STRRCHR -extern char * strrchr(const char * s, int c); - -#undef __HAVE_ARCH_STRCHR -extern char * strchr(const char * s, int c); - -#undef __HAVE_ARCH_MEMCPY -extern void * memcpy(void *, const void *, __kernel_size_t); - -#undef __HAVE_ARCH_MEMMOVE -extern void * memmove(void *, const void *, __kernel_size_t); - -#undef __HAVE_ARCH_MEMCHR -extern void * memchr(const void *, int, __kernel_size_t); - -#undef __HAVE_ARCH_MEMZERO -#undef __HAVE_ARCH_MEMSET -extern void * memset(void *, int, __kernel_size_t); - -#if 0 -extern void __memzero(void *ptr, __kernel_size_t n); - -#define memset(p,v,n) \ - ({ \ - if ((n) != 0) { \ - if (__builtin_constant_p((v)) && (v) == 0) \ - __memzero((p),(n)); \ - else \ - memset((p),(v),(n)); \ - } \ - (p); \ - }) - -#define memzero(p,n) ({ if ((n) != 0) __memzero((p),(n)); (p); }) -#else -extern void memzero(void *ptr, __kernel_size_t n); -#endif - -#endif diff --git a/x-loader/include/asm/types.h b/x-loader/include/asm/types.h deleted file mode 100644 index efc3052..0000000 --- a/x-loader/include/asm/types.h +++ /dev/null @@ -1,51 +0,0 @@ -#ifndef __ASM_ARM_TYPES_H -#define __ASM_ARM_TYPES_H - -typedef unsigned short umode_t; - -/* - * __xx is ok: it doesn't pollute the POSIX namespace. Use these in the - * header files exported to user space - */ - -typedef __signed__ char __s8; -typedef unsigned char __u8; - -typedef __signed__ short __s16; -typedef unsigned short __u16; - -typedef __signed__ int __s32; -typedef unsigned int __u32; - -#if defined(__GNUC__) && !defined(__STRICT_ANSI__) -typedef __signed__ long long __s64; -typedef unsigned long long __u64; -#endif - -/* - * These aren't exported outside the kernel to avoid name space clashes - */ -#ifdef __KERNEL__ - -typedef signed char s8; -typedef unsigned char u8; - -typedef signed short s16; -typedef unsigned short u16; - -typedef signed int s32; -typedef unsigned int u32; - -typedef signed long long s64; -typedef unsigned long long u64; - -#define BITS_PER_LONG 32 - -/* Dma addresses are 32-bits wide. */ - -typedef u32 dma_addr_t; -typedef unsigned long phys_addr_t; - -#endif /* __KERNEL__ */ - -#endif diff --git a/x-loader/include/asm/x-load-arm.h b/x-loader/include/asm/x-load-arm.h deleted file mode 100644 index eef268e..0000000 --- a/x-loader/include/asm/x-load-arm.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - * (C) Copyright 2004 - * Texas Instruments - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Marius Groeger <mgroeger@sysgo.de> - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Alex Zuepke <azu@sysgo.de> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _X_LOAD_ARM_H_ -#define _X_LOAD_ARM_H_ 1 - -/* for the following variables, see start.S */ -extern ulong _armboot_start; /* code start */ -extern ulong _bss_start; /* code + data end == BSS start */ -extern ulong _bss_end; /* BSS end */ - -#endif /* _X_LOAD_ARM_H_ */ |