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authorNegreanu Marius Adrian <adrian.m.negreanu@intel.com>2011-09-28 17:47:50 +0300
committerAndrew Boie <andrew.p.boie@intel.com>2013-09-18 14:14:22 -0700
commitae5c0ab2726ed4b9ca7b08f9b29e3393aa0a5d40 (patch)
tree67b851a3b784d8ccaa12ba1600d33e362735b0b3 /core/combo
parent14d4310803ee2b9811a7adb381a2ca54b96aefe2 (diff)
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Extend x86 to have different arch variants
Author: Negreanu Marius Adrian <adrian.m.negreanu@intel.com> Author: Andrew Boie <andrew.p.boie@intel.com> Author: Daniel Leung <daniel.leung@intel.com> Currently, x86 target only has generic i686 and x86-atom as arch variants. This patch adds the ability to have more than two arch variants. Defining a new arch variant is similiar to ARM targets, by adding a new file in core/combo/arch/x86. These files also define what capabilities the targeting CPU has (e.g. having SSE2, SSE3, etc.). We define arch variants for Sandy Bridge, Ivy Bridge, Haswell; upcoming arches can be easily added to this set with future patches. Change-Id: Iafbce10d205e860738db4a216ff603f9a84d7311 Signed-off-by: Daniel Leung <daniel.leung@intel.com> Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Diffstat (limited to 'core/combo')
-rw-r--r--core/combo/TARGET_linux-x86.mk43
-rw-r--r--core/combo/arch/x86/haswell.mk20
-rw-r--r--core/combo/arch/x86/ivybridge.mk20
-rw-r--r--core/combo/arch/x86/sandybridge.mk18
-rw-r--r--core/combo/arch/x86/x86-atom.mk10
-rw-r--r--core/combo/arch/x86/x86.mk4
6 files changed, 96 insertions, 19 deletions
diff --git a/core/combo/TARGET_linux-x86.mk b/core/combo/TARGET_linux-x86.mk
index 159fbe1..5859bd4 100644
--- a/core/combo/TARGET_linux-x86.mk
+++ b/core/combo/TARGET_linux-x86.mk
@@ -131,7 +131,8 @@ TARGET_GLOBAL_CFLAGS += \
-fstrict-aliasing \
-funswitch-loops \
-funwind-tables \
- -fstack-protector
+ -fstack-protector \
+ -m32
android_config_h := $(call select-android-config-h,target_linux-x86)
TARGET_ANDROID_CONFIG_CFLAGS := -include $(android_config_h) -I $(dir $(android_config_h))
@@ -141,23 +142,37 @@ TARGET_GLOBAL_CFLAGS += $(TARGET_ANDROID_CONFIG_CFLAGS)
TARGET_GLOBAL_CPPFLAGS += \
-fno-use-cxa-atexit
-# XXX: Our toolchain is normally configured to always set these flags by default
-# however, there have been reports that this is sometimes not the case. So make
-# them explicit here unless we have the time to carefully check it
-#
-TARGET_GLOBAL_CFLAGS += -mstackrealign -msse3 -mfpmath=sse -m32
+TARGET_GLOBAL_CFLAGS += $(arch_variant_cflags)
-# XXX: These flags should not be defined here anymore. Instead, the Android.mk
-# of the modules that depend on these features should instead check the
-# corresponding macros (e.g. ARCH_X86_HAVE_SSE2 and ARCH_X86_HAVE_SSSE3)
-# Keep them here until this is all cleared up.
-#
+ifeq ($(ARCH_X86_HAVE_MMX),true)
+ TARGET_GLOBAL_CFLAGS += -DUSE_MMX -mmmx
+endif
+ifeq ($(ARCH_X86_HAVE_SSE),true)
+ TARGET_GLOBAL_CFLAGS += -DUSE_SSE -msse
+endif
ifeq ($(ARCH_X86_HAVE_SSE2),true)
-TARGET_GLOBAL_CFLAGS += -DUSE_SSE2
+ TARGET_GLOBAL_CFLAGS += -DUSE_SSE2 -msse2
+endif
+ifeq ($(ARCH_X86_HAVE_SSE3),true)
+ TARGET_GLOBAL_CFLAGS += -DUSE_SSE3 -msse3
endif
-
ifeq ($(ARCH_X86_HAVE_SSSE3),true) # yes, really SSSE3, not SSE3!
-TARGET_GLOBAL_CFLAGS += -DUSE_SSSE3
+ TARGET_GLOBAL_CFLAGS += -DUSE_SSSE3 -mssse3
+endif
+ifeq ($(ARCH_X86_HAVE_SSE4),true)
+ TARGET_GLOBAL_CFLAGS += -msse4
+endif
+ifeq ($(ARCH_X86_HAVE_SSE4_1),true)
+ TARGET_GLOBAL_CFLAGS += -msse4.1
+endif
+ifeq ($(ARCH_X86_HAVE_SSE4_2),true)
+ TARGET_GLOBAL_CFLAGS += -msse4.2
+endif
+ifeq ($(ARCH_X86_HAVE_AVX),true)
+ TARGET_GLOBAL_CFLAGS += -mavx
+endif
+ifeq ($(ARCH_X86_HAVE_AES_NI),true)
+ TARGET_GLOBAL_CFLAGS += -maes
endif
# XXX: This flag is probably redundant. I believe our toolchain always sets
diff --git a/core/combo/arch/x86/haswell.mk b/core/combo/arch/x86/haswell.mk
new file mode 100644
index 0000000..5cbb3b8
--- /dev/null
+++ b/core/combo/arch/x86/haswell.mk
@@ -0,0 +1,20 @@
+# Configuration for Linux on x86.
+# Generating binaries for Haswell processors.
+#
+ARCH_X86_HAVE_MMX := true
+ARCH_X86_HAVE_SSE := true
+ARCH_X86_HAVE_SSE2 := true
+ARCH_X86_HAVE_SSE3 := true
+ARCH_X86_HAVE_SSSE3 := true
+ARCH_X86_HAVE_SSE4 := true
+ARCH_X86_HAVE_SSE4_1 := true
+ARCH_X86_HAVE_SSE4_2 := true
+ARCH_X86_HAVE_AES_NI := true
+ARCH_X86_HAVE_AVX := true
+
+# CFLAGS for this arch
+arch_variant_cflags := \
+ -march=core-avx2 \
+ -mstackrealign \
+ -mfpmath=sse \
+
diff --git a/core/combo/arch/x86/ivybridge.mk b/core/combo/arch/x86/ivybridge.mk
new file mode 100644
index 0000000..c0f8d89
--- /dev/null
+++ b/core/combo/arch/x86/ivybridge.mk
@@ -0,0 +1,20 @@
+# Configuration for Linux on x86.
+# Generating binaries for Ivy Bridge processors.
+#
+ARCH_X86_HAVE_MMX := true
+ARCH_X86_HAVE_SSE := true
+ARCH_X86_HAVE_SSE2 := true
+ARCH_X86_HAVE_SSE3 := true
+ARCH_X86_HAVE_SSSE3 := true
+ARCH_X86_HAVE_SSE4 := true
+ARCH_X86_HAVE_SSE4_1 := true
+ARCH_X86_HAVE_SSE4_2 := true
+ARCH_X86_HAVE_AES_NI := true
+ARCH_X86_HAVE_AVX := true
+
+# CFLAGS for this arch
+arch_variant_cflags := \
+ -march=core-avx-i \
+ -mstackrealign \
+ -mfpmath=sse \
+
diff --git a/core/combo/arch/x86/sandybridge.mk b/core/combo/arch/x86/sandybridge.mk
new file mode 100644
index 0000000..8d5e609
--- /dev/null
+++ b/core/combo/arch/x86/sandybridge.mk
@@ -0,0 +1,18 @@
+# Configuration for Linux on x86.
+# Generating binaries for SandyBridge processors.
+#
+ARCH_X86_HAVE_MMX := true
+ARCH_X86_HAVE_SSE := true
+ARCH_X86_HAVE_SSE2 := true
+ARCH_X86_HAVE_SSE3 := true
+ARCH_X86_HAVE_SSSE3 := true
+ARCH_X86_HAVE_SSE4_1 := true
+ARCH_X86_HAVE_SSE4_2 := true
+ARCH_X86_HAVE_AVX := true
+
+# CFLAGS for this arch
+arch_variant_cflags := \
+ -march=corei7-avx \
+ -mstackrealign \
+ -mfpmath=sse \
+
diff --git a/core/combo/arch/x86/x86-atom.mk b/core/combo/arch/x86/x86-atom.mk
index 85998e7..1ea4eea 100644
--- a/core/combo/arch/x86/x86-atom.mk
+++ b/core/combo/arch/x86/x86-atom.mk
@@ -8,11 +8,13 @@ ARCH_X86_HAVE_MMX := true
ARCH_X86_HAVE_SSE := true
ARCH_X86_HAVE_SSE2 := true
ARCH_X86_HAVE_SSE3 := true
-
ARCH_X86_HAVE_SSSE3 := true
ARCH_X86_HAVE_MOVBE := true
ARCH_X86_HAVE_POPCNT := false # popcnt is not supported by current Atom CPUs
-# This flag is used to enabled Atom-specific optimizations with our toolchain
-#
-TARGET_GLOBAL_CFLAGS += -march=atom
+# CFLAGS for this arch
+arch_variant_cflags := \
+ -march=atom \
+ -mstackrealign \
+ -mfpmath=sse \
+
diff --git a/core/combo/arch/x86/x86.mk b/core/combo/arch/x86/x86.mk
index 476da45..a62d86c 100644
--- a/core/combo/arch/x86/x86.mk
+++ b/core/combo/arch/x86/x86.mk
@@ -32,4 +32,6 @@ ARCH_X86_HAVE_POPCNT := false
# not always work as intended, so keep it unless we have the time to check
# everything properly.
-TARGET_GLOBAL_CFLAGS += -march=i686
+arch_variant_cflags := \
+ -march=i686 \
+