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* Set mcpu targets based on cpu variant.Christopher Ferris2016-02-101-1/+1
| | | | | | Make cortex-a53 and cortex-a53.a57 use cortex-a7. Change-Id: I89d5b3f044c867ec99aae319eafc33f2edf1f9f2
* Apply correct, optimized mfpu compiler flag for ARMv7-A Cortex CPUsarter972015-10-271-7/+6
| | | | | | | | | | | | | | | | | For those ARMv7-A Cortex CPUs that can handle VFPv4 floating point, We can set "-mfpu=neon-vfpv4" instead of generic "-mfpu=neon" to gain extra performance improvements. References : - GCC : https://gcc.gnu.org/onlinedocs/gcc/ARM-Options.html - Cortex A15 : http://www.arm.com/products/processors/cortex-a/cortex-a15.php - Cortex A9 : http://www.arm.com/products/processors/cortex-a/cortex-a9.php - Cortex A8 : http://www.arm.com/products/processors/cortex-a/cortex-a8.php - Cortex A7 : http://www.arm.com/products/processors/cortex-a/cortex-a7.php Change-Id: I91893789ed8edabf3767e1782e494b81158332bb Signed-off-by: Park Ju Hyung <qkrwngud825@gmail.com> Signed-off-by: Maxime Poulain <maxime.poulain@student.uclouvain.be>
* core: armv7-a-neon.mk: Add missing endifArne Coucheron2015-10-061-0/+1
| | | | Change-Id: Id6f9c952d01d3c980115a52605d9c86038b3b5bd
* core: Enable -mcpu=cortex-a9 flag for Cortex-A9 cpu variantCristoforo Cataldo2015-10-061-0/+3
| | | | Change-Id: I9294a518bcdc21ccbae72eadd9f3c1a12982d028
* core: Enable -mcpu=cortex-a8 flag for Scorpion cpu variantCristoforo Cataldo2015-10-061-1/+1
| | | | | | | To be used with http://review.cyanogenmod.org/#/c/77758/ Change-Id: I7ecc4707fa45bd7098165615c0521a12c85fb087
* Add support for cortex-a53 variants when building 64-bit.Tim Murray2015-06-111-1/+5
| | | | Change-Id: I3f1fb5dbde731d9c3d6db26a46bc7f0f54d8e071
* Don't use -Wl,--fix-cortex-a8 for Cortex A7, A9, A15, Krait or DenverBernhard Rosenkränzer2015-03-251-3/+9
| | | | | | | | | | | | -Wl,--fix-cortex-a8 is a workaround for an Erratum in Cortex-A8 processors. It slightly increases code size and decreases performance, and there's no point in using it on non-A8 CPUs. Instead of forcing it unconditionally, use it when targeting Cortex-A8 or generic armv7-a (which might or might not be A8). Change-Id: Ifa59765d380445237edccfe5440a67b3ba1e459a Signed-off-by: Bernhard Rosenkränzer <Bernhard.Rosenkranzer@linaro.org>
* Update x86_64 minimal ISA instruction setMingwei Shi2015-03-121-0/+3
| | | | | Change-Id: I3ca7f8a0799e6aef09ab1dfb719d218c7338ebf8 Signed-off-by: Mingwei Shi <mingwei.shi@intel.com>
* Rename core/combo/arch/x86/x86-atom.mk to core/combo/arch/x86/atom.mk.Alexander Ivchenko2014-12-031-0/+0
| | | | | | | | | Otherwise wrong set of memory/string functions is chosen when building atom image (in Bionic we have libc/arch-x86/atom/atom.mk). Plus this naming is consistent with other x86 architectures. Change-Id: I21e899534e7ce10530474a22ceba770422b39d8d Signed-off-by: Alexander Ivchenko <alexander.ivchenko@intel.com>
* Revert "Continue to use march=i686 before fix of g++ ICE."Chih-hung Hsieh2014-10-301-6/+2
| | | | | | This reverts commit f70f009ca8b4779cc3a5f44e7d92b1c297e16c8b. Change-Id: I3e1b18cf342e747c8a8405f1fc2513e5ebafc4b6
* Continue to use march=i686 before fix of g++ ICE.Chih-Hung Hsieh2014-10-291-2/+6
| | | | | | BUG: 18174291 BUG: 18171557 Change-Id: Ica9e420e3cc1904a4298e2ab1c6201a254cbf6d1
* Specify -mcpu=krait for clang.Ian Rogers2014-10-281-1/+2
| | | | Change-Id: I64682cddf57246341c1727ca16c56f7ce0c6fd0a
* Raise x86 arch requirement to prescott.Chih-Hung Hsieh2014-10-221-6/+2
| | | | | | | | Atomic functions used in external/libcxx/include/atomic when compiled with Clang will require intrinsic functions exist only for prescott or newer CPUs. BUG: 17530542 Change-Id: I0c9660ed2ffa75b940981eb8165d88934b39aec5
* Move definition of -D__ARM_FEATURE_LPAE=1 cflag to top-level.Ian Rogers2014-10-151-0/+7
| | | | | | | | | | LPAE indicates better instructions can be used when atomicity guarantees are needed. However, LPAE's presence isn't advertised by clang/GCC. We fake an ARM feature to advertise its presence on architectures where it is. Also, add a TODO documenting that cortex-a15 is not the correct CPU variant for krait. Change-Id: I02a1248025c32d94eca0bc8a249dc524f1ac9c36
* Remove "-mstackrealign" option from all x86 builds.Alexander Ivchenko2014-10-135-5/+0
| | | | | | | | For ndk docs change, please refer to: https://android-review.googlesource.com/#/c/110100/ Change-Id: I8428e7a979eb02441066aeeee43ce693d4d0dc8d Signed-off-by: Alexander Ivchenko <alexander.ivchenko@intel.com>
* Add missing flags to x86 (both 32- and 64-bit) arch variants.Varvara Rainchik2014-08-047-13/+16
| | | | | | | Delete x86_64-atom.mk as we don't support 64-bit on old Atom. Change-Id: I0b9ab61cd9b840f32c30059cb3ba9704c733c42a Signed-off-by: Varvara Rainchik <varvara.rainchik@intel.com>
* [MIPSR6] Add mips64r6 and mips32r6 targetsDuane Sand2014-07-242-0/+19
| | | | | | | | | | | Add mips64r6 target and corresponding mips32r6 target. Defaults remain as mips64r2 and mips32r2. Apply -FP64A codegen subsetting to mips32r6 only. Access FR=0 odd-numbered 32-bit float regs only via double-prec even-numbered regs, not by single-prec ops. Change-Id: I1740a6c658304b6c41242be58d68753e6f171658
* [MIPS] Unite mipsel and mips64el 4.9 gcc toolchainsDuane Sand2014-07-2310-90/+17
| | | | | | | | | | | | Use 4.9 mips64el toolchain for both 64- and 32-bit builds. Tell ld when 32-bit links are required. Override 4.9's changed defaults for mips floating point register use, to get same assembler rules as 4.8 and earlier. Also: drop unused soft-fp build targets, cleanout redundant compiler options, and remove extraneous Android.mk file. Change-Id: I86f1075266349edb2b08a7709b9f5472d8cfda32
* add silvermont x86 architectureAndrew Boie2014-04-302-0/+37
| | | | | | | | | This is used for Baytrail targets. Change-Id: I5a2fa6dbb8217a326ee09f5ea434885718ab3f0c Signed-off-by: Andrew Boie <andrew.p.boie@intel.com> Signed-off-by: Pavel Chupin <pavel.v.chupin@intel.com> Signed-off-by: Fengwei Yin <fengwei.yin@intel.com>
* Specify -mcpu=cortex-a15 for denver CPU variants.Shu Zhang2014-03-241-1/+1
| | | | Change-Id: Ic27484c92a48b45148021a61420ffdd55a9dd945
* Select the arch_variant_cflags for the 2nd arch.Ying Wang2014-02-071-3/+3
| | | | Change-Id: Id2f9d7073a4aae3ba0fe5e5464045761f4d42b4e
* [MIPS64] Add mips64 targetChris Dearman2014-02-051-0/+14
| | | | | Change-Id: Ice1621101c0d5a3314db288542ca8020e3f406bf Signed-off-by: Duane Sand <duane.sand@imgtec.com>
* remove 2nd arch from ARCH_ARM_* definesColin Cross2014-02-042-6/+6
| | | | | | | Users of ARCH_ARM_* defines don't care about first vs. second arch, set ARCH_ARM_* regardless of which arch is arm. Change-Id: I2ae83ec5c3f839ff91a0e352c95d76ec2cbd5dc5
* Load compiler environment for a second arch.Ying Wang2014-01-242-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is the first step to build 32-bit libraries in a 64-bit product. It will work like this: 1) In the product's BoardConfig.mk, define: TARGET_2ND_ARCH, TARGET_2ND_ARCH_VARIANT, TARGET_2ND_CPU_VARIANT. The build system uses those variables to set up an additional compiler environment for the second arch. 2) When parsing Android.mks, the build system sets up rules to build a module for both the 1st arch and the 2nd arch, unless it's explicitly asked to skip so. Android.mk will be adapted if there is additional rule of generating source files. The build system will accept arch-specific LOCAL_ variables, such as LOCAL_CFLAGS_arm, LOCAL_CFLAGS_armv7-a-neon, LOCAL_CFLAGS_cortex-a15, LOCAL_CFLAGS_aarch64 etc. Modules use such variables to set up build for various archs at the same time. 3) Install binary of the 2nd arch by adding "<module_name>:32" to PRODUCT_PACKAGES. All 2nd-arch libraries linked in by "<module_name>:32" will be installed automatically. Bug: 11654773 Change-Id: I2df63cd5463a07bf5358bee2a109f8fb9590fe30 Conflicts: core/combo/TARGET_linux-arm.mk
* build: rename aarch64 target to arm64Colin Cross2014-01-231-0/+0
| | | | | | | Rename aarch64 build targets to arm64. The gcc toolchain is still aarch64. Change-Id: Ia92d8a50824e5329cf00fd6f4f92eae112b7f3a3
* am 09c6d68b: am 816af5fc: Merge "Specify -mcpu=cortex-a15 for krait CPU ↵Ian Rogers2013-10-111-1/+1
|\ | | | | | | | | | | | | variants." * commit '09c6d68b8879164f600bbe084a62cfbc4ab10850': Specify -mcpu=cortex-a15 for krait CPU variants.
| * Specify -mcpu=cortex-a15 for krait CPU variants.Ian Rogers2013-10-111-1/+1
| | | | | | | | | | | | Bug: 11178216 Change-Id: I9922e4cd5ba27e3857798aae5c84299e26e054ea
* | am 0b42554f: am 12eeb000: Merge "Add generic aarch64 board config and build ↵Ben Cheng2013-10-071-0/+1
|\ \ | |/ | | | | | | | | | | rules." * commit '0b42554fd8c7a43ca45504e4586f1eef578308de': Add generic aarch64 board config and build rules.
| * Merge "Add generic aarch64 board config and build rules."Ben Cheng2013-10-071-0/+1
| |\
| | * Add generic aarch64 board config and build rules.Ben Cheng2013-10-071-0/+1
| | | | | | | | | | | | Change-Id: I8b4a377596705dfa0a3bd234162d183ec2ae9530
* | | am a035abc5: am 1303aa28: Merge "Remove useless x86 options that were always ↵Elliott Hughes2013-10-046-42/+5
|\ \ \ | |/ / | | | | | | | | | | | | | | | hardcoded on." * commit 'a035abc55455a50da7b242dad1bca55fa28617a9': Remove useless x86 options that were always hardcoded on.
| * | Remove useless x86 options that were always hardcoded on.Elliott Hughes2013-10-046-42/+5
| |/ | | | | | | | | | | | | | | | | ARCH_X86_HAVE_MMX, ARCH_X86_HAVE_SSE, ARCH_X86_HAVE_SSE2, and ARCH_X86_HAVE_SSE3 were all always on. There are no longer any makefiles or code that are conditional on any of these, so let's just remove them rather than encourage anyone to mess with knobs that don't work. Change-Id: I5ee095e8041eecff4554ad4801894fbfca69093f
* | am ab7b53b8: am 5d92a933: Merge "x86_64: Adding new target"Ying Wang2013-10-025-0/+72
|\ \ | |/ | | | | | | * commit 'ab7b53b8e09e3d346384a5257e8f7a440a53dfc0': x86_64: Adding new target
| * x86_64: Adding new targetPavel Chupin2013-10-025-0/+72
| | | | | | | | | | | | | | | | Add x86_64 Android builds. Compiler is expected to be able to understand -m64 code generation option. Change-Id: I99e7337c5a5766afc5e528a481bd21631ff44dd5 Signed-off-by: Pavel Chupin <pavel.v.chupin@intel.com>
* | resolved conflicts for merge of 70190a2b to klp-dev-plus-aospYing Wang2013-09-195-5/+67
|\ \ | |/ | | | | Change-Id: I9abcb4e258ad95912860dcae2973c4e417b05369
| * Extend x86 to have different arch variantsNegreanu Marius Adrian2013-09-185-5/+67
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Author: Negreanu Marius Adrian <adrian.m.negreanu@intel.com> Author: Andrew Boie <andrew.p.boie@intel.com> Author: Daniel Leung <daniel.leung@intel.com> Currently, x86 target only has generic i686 and x86-atom as arch variants. This patch adds the ability to have more than two arch variants. Defining a new arch variant is similiar to ARM targets, by adding a new file in core/combo/arch/x86. These files also define what capabilities the targeting CPU has (e.g. having SSE2, SSE3, etc.). We define arch variants for Sandy Bridge, Ivy Bridge, Haswell; upcoming arches can be easily added to this set with future patches. Change-Id: Iafbce10d205e860738db4a216ff603f9a84d7311 Signed-off-by: Daniel Leung <daniel.leung@intel.com> Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
* | am 20c768d2: am c5cc2f6d: Merge "[MIPS] Add support for MXU instructions for ↵Ying Wang2013-08-191-1/+2
|\ \ | |/ | | | | | | | | | | Ingenic builds." * commit '20c768d2128364a6a9373dd8ef432bf55512bf37': [MIPS] Add support for MXU instructions for Ingenic builds.
| * [MIPS] Add support for MXU instructions for Ingenic builds.Pete Delaney2013-08-151-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | This enables an Ingenic build to use MXU asm instructions. MXU support was just recently added: ASM: https://android-review.googlesource.com/63701 GCC: https://android-review.googlesource.com/63702 BIN: https://android-review.googlesource.com/#/c/63704/ Change-Id: I2b60567a689efa70ec064dfbb0f241a6bc61aed1 Signed-off-by: Pete Delaney <piet.delaney@imgtec.com>
* | am c012edbc: am 42aaacf1: am a90d7eb6: Merge "Do not use -msynci flag for ↵Ying Wang2013-06-211-1/+0
|\ \ | |/ | | | | | | | | | | Xburst 4780 cores" * commit 'c012edbc519b74456530c26719133f96d4574de3': Do not use -msynci flag for Xburst 4780 cores
| * am a90d7eb6: Merge "Do not use -msynci flag for Xburst 4780 cores"Ying Wang2013-06-211-1/+0
| |\ | | | | | | | | | | | | * commit 'a90d7eb64fc3155c6558d9c307e0bc4a2d84dff9': Do not use -msynci flag for Xburst 4780 cores
| | * Do not use -msynci flag for Xburst 4780 coresRaghu Gandham2013-06-201-1/+0
| | | | | | | | | | | | | | | | | | | | | synci does not provide coherency between CPU's on this device Change-Id: I10e73fa49859e55d018884c6682b5a00b887e0a1 Signed-off-by: Chris Dearman <chris.dearman@imgtec.com>
* | | am 210aee35: am fa29872a: Merge "[MIPS] Disabled madd support for Ingenic ↵Ying Wang2013-05-211-0/+17
|\ \ \ | |/ / | | | | | | | | | | | | | | | Xburst CPUs." * commit '210aee35a9dec3b94ab0cfc247e6c89c1e387f19': [MIPS] Disabled madd support for Ingenic Xburst CPUs.
| * | am fa29872a: Merge "[MIPS] Disabled madd support for Ingenic Xburst CPUs."Ying Wang2013-05-211-0/+17
| |\ \ | | |/ | | | | | | | | | * commit 'fa29872ae08408f90e1282bff36a0bdba13d0fdc': [MIPS] Disabled madd support for Ingenic Xburst CPUs.
| | * [MIPS] Disabled madd support for Ingenic Xburst CPUs.Pete Delaney2013-05-201-0/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 1. Added xburst ARCH_VARIANT file 'mips32r2-fp-xburst.mk'. a) Added -mno-fused-madd GCC option. 2. Removing -mno-fused-madd GCC option for LLVM. Change-Id: I947a74eb89c05ae321417533c3c40241abc6f965 Signed-off-by: Pete Delaney <piet.delaney@imgtec.com>
* | | core: combo: arm: add cortex-a8 targetRom Lemarchand2013-05-141-0/+4
|/ / | | | | | | Change-Id: I83e409dd048762acbd2e2dec9b0095933141cff0
* | core: combo: arm: use appropriate mcpu flags for cortex-a7Dima Zavin2013-03-231-0/+4
| | | | | | | | | | Change-Id: If00577d36257e4d03f63f36b159bb2e015958d6a Signed-off-by: Dima Zavin <dima@android.com>
* | am 7ce7473f: am 5e12e60b: Merge "For the current MIPS compiler ↵Ying Wang2013-02-156-6/+12
|\ \ | |/ | | | | | | | | | | __builtin___clear_cache() generates synci instruction only with -msynci option So, add -msynci to all mips32r2 makefiles. Also add msynci to the list flags not recognized by clang." * commit '7ce7473f866fc5356291f38a3437a071ea5fd00d': For the current MIPS compiler __builtin___clear_cache() generates synci instruction only with -msynci option So, add -msynci to all mips32r2 makefiles. Also add msynci to the list flags not recognized by clang.
| * Merge "For the current MIPS compiler __builtin___clear_cache() generates ↵Ying Wang2013-02-156-6/+12
| |\ | | | | | | | | | synci instruction only with -msynci option So, add -msynci to all mips32r2 makefiles. Also add msynci to the list flags not recognized by clang."
| | * For the current MIPS compiler __builtin___clear_cache() generates synci ↵Raghu Gandham2013-02-076-6/+12
| | | | | | | | | | | | | | | | | | | | | | | | instruction only with -msynci option So, add -msynci to all mips32r2 makefiles. Also add msynci to the list flags not recognized by clang. Change-Id: I48fd6f2b0cbe80c3cd90f453ced97a2f154f7ad3 Signed-off-by: Rocky Zhang <yan@mips.com>
* | | am ea852f6e: am f6b670b7: Merge "Remove more always-true ARCH_ARM_HAVE_ flags."Elliott Hughes2013-02-143-14/+0
|\ \ \ | |/ / | | | | | | | | | | | | # Via Android Git Automerger (1) and others * commit 'ea852f6ed3e9f251eaef4f041fbc0b09229ac924': Remove more always-true ARCH_ARM_HAVE_ flags.
generated by cgit v1.1 at 2025-08-16 10:46:21 +0000