1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
|
/*
*
* Copyright 2011 Samsung Electronics S.LSI Co. LTD
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/*
* @file csc_nv12t_yuv420_uv_neon.s
* @brief SEC_OMX specific define
* @author ShinWon Lee (shinwon.lee@samsung.com)
* @version 1.0
* @history
* 2011.7.01 : Create
*/
/*
* Converts and Deinterleaves tiled data to linear
* 1. UV of NV12T to UV of YUV420P
*
* @param yuv420_u_dest
* U plane address of YUV420P[out]
*
* @param yuv420_v_dest
* V plane address of YUV420P[out]
*
* @param nv12t_src
* UV plane address of NV12T[in]
*
* @param yuv420_width
* Width of YUV420[in]
*
* @param yuv420_uv_height
* Height/2 of YUV420[in]
*/
.arch armv7-a
.text
.global csc_tiled_to_linear_deinterleave_neon
.type csc_tiled_to_linear_deinterleave_neon, %function
csc_tiled_to_linear_deinterleave_neon:
.fnstart
@r0 linear_u_dest
@r1 linear_v_dest
@r2 tiled_uv_src
@r3 linear_x_size
@r4 linear_y_size
@r5 j
@r6 i
@r7 tiled_addr
@r8 linear_addr
@r9 aligned_x_size
@r10 temp1
@r11 temp2
@r12 temp3
@r14 temp4
stmfd sp!, {r4-r12,r14} @ backup registers
ldr r4, [sp, #40] @ load linear_y_size to r4
mov r9, #0
LINEAR_X_SIZE_1024:
cmp r3, #1024
blt LINEAR_X_SIZE_512
mov r6, #0
LINEAR_X_SIZE_1024_LOOP:
mov r7, #0 @ tiled_offset = 0@
mov r5, r6, asr #5 @ tiled_y_index = i>>5@
and r10, r5, #0x1
cmp r10, #0x1
bne LINEAR_X_SIZE_1024_LOOP_EVEN
LINEAR_X_SIZE_1024_LOOP_ODD:
sub r7, r5, #1 @ tiled_offset = tiled_y_index-1@
add r10, r3, #127 @ temp1 = ((linear_x_size+127)>>7)<<7@
bic r10, #0x7F
mov r10, r10, asr #6 @ tiled_offset = tiled_offset*(temp1>>6)@
mul r7, r7, r10
mov r5, #8
mov r5, r5, lsl #11
sub r5, r5, #32
add r7, r7, #2 @ tiled_offset = tiled_offset+2@
mov r7, r7, lsl #11 @ tiled_offset = tiled_offset<<11@
add r11, r7, #2048
add r12, r7, #4096
add r14, r7, #6144
b LINEAR_X_SIZE_1024_LOOP_MEMCPY
LINEAR_X_SIZE_1024_LOOP_EVEN:
add r11, r4, #31 @ temp2 = ((linear_y_size+31)>>5)<<5@
bic r11, r11, #0x1F
add r10, r3, #127 @ temp1 = ((linear_x_size+127)>>7)<<7@
bic r10, #0x7F
mov r10, r10, asr #6 @ tiled_offset = tiled_y_index*(temp1>>6)@
mul r7, r5, r10
add r12, r6, #32
cmp r12, r11
mov r7, r7, lsl #11 @ tiled_offset = tiled_offset<<11@
add r11, r7, #2048
movlt r5, #8
addlt r12, r7, #12288
addlt r14, r7, #14336
movge r5, #4
addge r12, r7, #2048
addge r14, r7, #2048
mov r5, r5, lsl #11
sub r5, r5, #32
LINEAR_X_SIZE_1024_LOOP_MEMCPY:
and r10, r6, #0x1F
mov r10, r10, lsl #6
add r10, r2, r10
add r7, r7, r10 @ tiled_addr = tiled_src+64*(temp1)
add r11, r11, r10 @ tiled_addr1 = tiled_src+64*(temp1)
pld [r11]
vld2.8 {q0, q1}, [r7]!
pld [r11, #32]
add r12, r12, r10 @ tiled_addr2 = tiled_src+64*(temp1)
vld2.8 {q2, q3}, [r7], r5
pld [r12]
vld2.8 {q4, q5}, [r11]!
pld [r12, #32]
add r14, r14, r10 @ tiled_addr3 = tiled_src+64*(temp1)
vld2.8 {q6, q7}, [r11], r5
pld [r14]
vld2.8 {q8, q9}, [r12]!
pld [r14, #32]
mov r10, r3, asr #1
vld2.8 {q10, q11}, [r12], r5
mul r10, r10, r6
vld2.8 {q12, q13}, [r14]!
vld2.8 {q14, q15}, [r14], r5
add r8, r0, r10
vst1.8 {q0}, [r8]!
vst1.8 {q2}, [r8]!
vst1.8 {q4}, [r8]!
vst1.8 {q6}, [r8]!
vst1.8 {q8}, [r8]!
vst1.8 {q10}, [r8]!
vst1.8 {q12}, [r8]!
vst1.8 {q14}, [r8]!
add r10, r1, r10
vst1.8 {q1}, [r10]!
vst1.8 {q3}, [r10]!
vst1.8 {q5}, [r10]!
vst1.8 {q7}, [r10]!
vst1.8 {q9}, [r10]!
vst1.8 {q11}, [r10]!
pld [r7]
vst1.8 {q13}, [r10]!
pld [r7, #32]
vst1.8 {q15}, [r10]!
pld [r11]
vld2.8 {q0, q1}, [r7]!
pld [r11, #32]
vld2.8 {q2, q3}, [r7], r5
pld [r12]
vld2.8 {q4, q5}, [r11]!
pld [r12, #32]
vld2.8 {q6, q7}, [r11], r5
pld [r14]
vld2.8 {q8, q9}, [r12]!
pld [r14, #32]
vld2.8 {q10, q11}, [r12], r5
vld2.8 {q12, q13}, [r14]!
vld2.8 {q14, q15}, [r14], r5
vst1.8 {q0}, [r8]!
vst1.8 {q2}, [r8]!
vst1.8 {q4}, [r8]!
vst1.8 {q6}, [r8]!
vst1.8 {q8}, [r8]!
vst1.8 {q10}, [r8]!
vst1.8 {q12}, [r8]!
vst1.8 {q14}, [r8]!
vst1.8 {q1}, [r10]!
vst1.8 {q3}, [r10]!
vst1.8 {q5}, [r10]!
vst1.8 {q7}, [r10]!
vst1.8 {q9}, [r10]!
vst1.8 {q11}, [r10]!
pld [r7]
vst1.8 {q13}, [r10]!
pld [r7, #32]
vst1.8 {q15}, [r10]!
pld [r11]
vld2.8 {q0, q1}, [r7]!
pld [r11, #32]
vld2.8 {q2, q3}, [r7], r5
pld [r12]
vld2.8 {q4, q5}, [r11]!
pld [r12, #32]
vld2.8 {q6, q7}, [r11], r5
pld [r14]
vld2.8 {q8, q9}, [r12]!
pld [r14, #32]
vld2.8 {q10, q11}, [r12], r5
vld2.8 {q12, q13}, [r14]!
vld2.8 {q14, q15}, [r14], r5
vst1.8 {q0}, [r8]!
vst1.8 {q2}, [r8]!
vst1.8 {q4}, [r8]!
vst1.8 {q6}, [r8]!
vst1.8 {q8}, [r8]!
vst1.8 {q10}, [r8]!
vst1.8 {q12}, [r8]!
vst1.8 {q14}, [r8]!
vst1.8 {q1}, [r10]!
vst1.8 {q3}, [r10]!
vst1.8 {q5}, [r10]!
vst1.8 {q7}, [r10]!
vst1.8 {q9}, [r10]!
vst1.8 {q11}, [r10]!
pld [r7]
vst1.8 {q13}, [r10]!
pld [r7, #32]
vst1.8 {q15}, [r10]!
pld [r11]
vld2.8 {q0, q1}, [r7]!
pld [r11, #32]
vld2.8 {q2, q3}, [r7]
pld [r12]
vld2.8 {q4, q5}, [r11]!
pld [r12, #32]
vld2.8 {q6, q7}, [r11]
pld [r14]
vld2.8 {q8, q9}, [r12]!
pld [r14, #32]
vld2.8 {q10, q11}, [r12]
vld2.8 {q12, q13}, [r14]!
vld2.8 {q14, q15}, [r14]
vst1.8 {q0}, [r8]!
vst1.8 {q2}, [r8]!
vst1.8 {q4}, [r8]!
vst1.8 {q6}, [r8]!
vst1.8 {q8}, [r8]!
vst1.8 {q10}, [r8]!
vst1.8 {q12}, [r8]!
vst1.8 {q14}, [r8]!
vst1.8 {q1}, [r10]!
vst1.8 {q3}, [r10]!
vst1.8 {q5}, [r10]!
vst1.8 {q7}, [r10]!
vst1.8 {q9}, [r10]!
vst1.8 {q11}, [r10]!
add r6, #1
vst1.8 {q13}, [r10]!
cmp r6, r4
vst1.8 {q15}, [r10]!
blt LINEAR_X_SIZE_1024_LOOP
mov r9, #1024
LINEAR_X_SIZE_512:
sub r10, r3, r9
cmp r10, #512
blt LINEAR_X_SIZE_256
mov r6, #0
LINEAR_X_SIZE_512_LOOP:
mov r7, #0 @ tiled_offset = 0@
mov r5, r6, asr #5 @ tiled_y_index = i>>5@
and r10, r5, #0x1
cmp r10, #0x1
bne LINEAR_X_SIZE_512_LOOP_EVEN
LINEAR_X_SIZE_512_LOOP_ODD:
sub r7, r5, #1 @ tiled_offset = tiled_y_index-1@
add r10, r3, #127 @ temp1 = ((linear_x_size+127)>>7)<<7@
bic r10, #0x7F
mov r10, r10, asr #6 @ tiled_offset = tiled_offset*(temp1>>6)@
mul r7, r7, r10
mov r5, #8
mov r5, r5, lsl #11
add r7, r7, #2 @ tiled_offset = tiled_offset+2@
mov r10, r9, asr #5
add r7, r7, r10
mov r7, r7, lsl #11 @ tiled_offset = tiled_offset<<11@
add r11, r7, #2048
add r12, r7, #4096
add r14, r7, #6144
sub r5, r5, #32
b LINEAR_X_SIZE_512_LOOP_MEMCPY
LINEAR_X_SIZE_512_LOOP_EVEN:
add r11, r4, #31 @ temp2 = ((linear_y_size+31)>>5)<<5@
bic r11, r11, #0x1F
add r10, r3, #127 @ temp1 = ((linear_x_size+127)>>7)<<7@
bic r10, #0x7F
mov r10, r10, asr #6 @ tiled_offset = tiled_y_index*(temp1>>6)@
mul r7, r5, r10
add r12, r6, #32
cmp r12, r11
mov r7, r7, lsl #11 @ tiled_offset = tiled_offset<<11@
movlt r5, #8
movlt r10, r9, asr #5
movge r10, r9, asr #6
add r7, r7, r10, lsl #11
add r11, r7, #2048
addlt r12, r7, #12288
addlt r14, r7, #14336
movge r5, #4
addge r12, r7, #4096
addge r14, r7, #6144
mov r5, r5, lsl #11
sub r5, r5, #32
LINEAR_X_SIZE_512_LOOP_MEMCPY:
and r10, r6, #0x1F
mov r10, r10, lsl #6
add r10, r2, r10
add r7, r7, r10 @ tiled_addr = tiled_src+64*(temp1)
add r11, r11, r10 @ tiled_addr1 = tiled_src+64*(temp1)
pld [r11]
vld2.8 {q0, q1}, [r7]!
pld [r11, #32]
add r12, r12, r10 @ tiled_addr2 = tiled_src+64*(temp1)
vld2.8 {q2, q3}, [r7], r5
pld [r12]
vld2.8 {q4, q5}, [r11]!
pld [r12, #32]
add r14, r14, r10 @ tiled_addr3 = tiled_src+64*(temp1)
vld2.8 {q6, q7}, [r11], r5
pld [r14]
mov r10, r3, asr #1
vld2.8 {q8, q9}, [r12]!
pld [r14, #32]
mul r10, r10, r6
vld2.8 {q10, q11}, [r12], r5
add r8, r0, r10
vld2.8 {q12, q13}, [r14]!
add r8, r8, r9, asr #1
vld2.8 {q14, q15}, [r14], r5
vst1.8 {q0}, [r8]!
vst1.8 {q2}, [r8]!
vst1.8 {q4}, [r8]!
vst1.8 {q6}, [r8]!
vst1.8 {q8}, [r8]!
vst1.8 {q10}, [r8]!
vst1.8 {q12}, [r8]!
add r10, r1, r10
vst1.8 {q14}, [r8]!
add r10, r10, r9, asr #1
vst1.8 {q1}, [r10]!
vst1.8 {q3}, [r10]!
vst1.8 {q5}, [r10]!
vst1.8 {q7}, [r10]!
vst1.8 {q9}, [r10]!
vst1.8 {q11}, [r10]!
pld [r7]
vst1.8 {q13}, [r10]!
pld [r7, #32]
vst1.8 {q15}, [r10]!
pld [r11]
vld2.8 {q0, q1}, [r7]!
pld [r11, #32]
vld2.8 {q2, q3}, [r7]
pld [r12]
vld2.8 {q4, q5}, [r11]!
pld [r12, #32]
vld2.8 {q6, q7}, [r11]
pld [r14]
vld2.8 {q8, q9}, [r12]!
pld [r14, #32]
vld2.8 {q10, q11}, [r12]
vld2.8 {q12, q13}, [r14]!
vld2.8 {q14, q15}, [r14]
vst1.8 {q0}, [r8]!
vst1.8 {q2}, [r8]!
vst1.8 {q4}, [r8]!
vst1.8 {q6}, [r8]!
vst1.8 {q8}, [r8]!
vst1.8 {q10}, [r8]!
vst1.8 {q12}, [r8]!
vst1.8 {q14}, [r8]!
vst1.8 {q1}, [r10]!
vst1.8 {q3}, [r10]!
vst1.8 {q5}, [r10]!
vst1.8 {q7}, [r10]!
vst1.8 {q9}, [r10]!
vst1.8 {q11}, [r10]!
add r6, #1
vst1.8 {q13}, [r10]!
cmp r6, r4
vst1.8 {q15}, [r10]!
blt LINEAR_X_SIZE_512_LOOP
add r9, r9, #512
LINEAR_X_SIZE_256:
sub r10, r3, r9
cmp r10, #256
blt LINEAR_X_SIZE_128
mov r6, #0
LINEAR_X_SIZE_256_LOOP:
mov r7, #0 @ tiled_offset = 0@
mov r5, r6, asr #5 @ tiled_y_index = i>>5@
and r10, r5, #0x1
cmp r10, #0x1
bne LINEAR_X_SIZE_256_LOOP_EVEN
LINEAR_X_SIZE_256_LOOP_ODD:
sub r7, r5, #1 @ tiled_offset = tiled_y_index-1@
add r10, r3, #127 @ temp1 = ((linear_x_size+127)>>7)<<7@
bic r10, #0x7F
mov r10, r10, asr #6 @ tiled_offset = tiled_offset*(temp1>>6)@
mul r7, r7, r10
add r7, r7, #2 @ tiled_offset = tiled_offset+2@
mov r10, r9, asr #5
add r7, r7, r10
mov r7, r7, lsl #11 @ tiled_offset = tiled_offset<<11@
add r11, r7, #2048
add r12, r7, #4096
add r14, r7, #6144
b LINEAR_X_SIZE_256_LOOP_MEMCPY
LINEAR_X_SIZE_256_LOOP_EVEN:
add r11, r4, #31 @ temp2 = ((linear_y_size+31)>>5)<<5@
bic r11, r11, #0x1F
add r10, r3, #127 @ temp1 = ((linear_x_size+127)>>7)<<7@
bic r10, #0x7F
mov r10, r10, asr #6 @ tiled_offset = tiled_y_index*(temp1>>6)@
mul r7, r5, r10
mov r7, r7, lsl #11 @ tiled_offset = tiled_offset<<11@
add r12, r6, #32
cmp r12, r11
movlt r10, r9, asr #5
addlt r7, r7, r10, lsl #11
addlt r11, r7, #2048
addlt r12, r7, #12288
addlt r14, r7, #14336
movge r10, r9, asr #6
addge r7, r7, r10, lsl #11
addge r11, r7, #2048
addge r12, r7, #4096
addge r14, r7, #6144
LINEAR_X_SIZE_256_LOOP_MEMCPY:
and r10, r6, #0x1F
mov r10, r10, lsl #6
add r10, r2, r10
add r7, r7, r10 @ tiled_addr = tiled_src+64*(temp1)
add r11, r11, r10 @ tiled_addr1 = tiled_src+64*(temp1)
pld [r11]
vld2.8 {q0, q1}, [r7]!
pld [r11, #32]
add r12, r12, r10 @ tiled_addr2 = tiled_src+64*(temp1)
vld2.8 {q2, q3}, [r7]
pld [r12]
vld2.8 {q4, q5}, [r11]!
pld [r12, #32]
add r14, r14, r10 @ tiled_addr3 = tiled_src+64*(temp1)
vld2.8 {q6, q7}, [r11]
pld [r14]
vld2.8 {q8, q9}, [r12]!
pld [r14, #32]
mov r10, r3, asr #1
vld2.8 {q10, q11}, [r12]
mul r10, r10, r6
vld2.8 {q12, q13}, [r14]!
add r8, r0, r10
vld2.8 {q14, q15}, [r14]
add r8, r8, r9, asr #1
vst1.8 {q0}, [r8]!
vst1.8 {q2}, [r8]!
vst1.8 {q4}, [r8]!
vst1.8 {q6}, [r8]!
vst1.8 {q8}, [r8]!
vst1.8 {q10}, [r8]!
vst1.8 {q12}, [r8]!
add r10, r1, r10
vst1.8 {q14}, [r8]!
add r10, r10, r9, asr #1
vst1.8 {q1}, [r10]!
vst1.8 {q3}, [r10]!
vst1.8 {q5}, [r10]!
vst1.8 {q7}, [r10]!
vst1.8 {q9}, [r10]!
vst1.8 {q11}, [r10]!
add r6, #1
vst1.8 {q13}, [r10]!
cmp r6, r4
vst1.8 {q15}, [r10]!
blt LINEAR_X_SIZE_256_LOOP
add r9, r9, #256
LINEAR_X_SIZE_128:
sub r10, r3, r9
cmp r10, #128
blt LINEAR_X_SIZE_64
mov r6, #0
LINEAR_X_SIZE_128_LOOP:
mov r7, #0 @ tiled_offset = 0@
mov r5, r6, asr #5 @ tiled_y_index = i>>5@
and r10, r5, #0x1
cmp r10, #0x1
bne LINEAR_X_SIZE_128_LOOP_EVEN
LINEAR_X_SIZE_128_LOOP_ODD:
sub r7, r5, #1 @ tiled_offset = tiled_y_index-1@
add r10, r3, #127 @ temp1 = ((linear_x_size+127)>>7)<<7@
bic r10, #0x7F
mov r10, r10, asr #6 @ tiled_offset = tiled_offset*(temp1>>6)@
mul r7, r7, r10
add r7, r7, #2 @ tiled_offset = tiled_offset+2@
mov r10, r9, asr #5
add r7, r7, r10
mov r7, r7, lsl #11 @ tiled_offset = tiled_offset<<11@
add r11, r7, #2048
b LINEAR_X_SIZE_128_LOOP_MEMCPY
LINEAR_X_SIZE_128_LOOP_EVEN:
add r11, r4, #31 @ temp2 = ((linear_y_size+31)>>5)<<5@
bic r11, r11, #0x1F
add r10, r3, #127 @ temp1 = ((linear_x_size+127)>>7)<<7@
bic r10, #0x7F
mov r10, r10, asr #6 @ tiled_offset = tiled_y_index*(temp1>>6)@
mul r7, r5, r10
mov r7, r7, lsl #11 @ tiled_offset = tiled_offset<<11@
add r12, r6, #32
cmp r12, r11
movlt r10, r9, asr #5
movge r10, r9, asr #6
add r7, r7, r10, lsl #11
add r11, r7, #2048
LINEAR_X_SIZE_128_LOOP_MEMCPY:
and r10, r6, #0x1F
mov r10, r10, lsl #6
add r10, r2, r10
add r7, r7, r10 @ tiled_addr = tiled_src+64*(temp1)
add r11, r11, r10 @ tiled_addr1 = tiled_src+64*(temp1)
pld [r11]
vld2.8 {q0, q1}, [r7]!
pld [r11, #32]
vld2.8 {q2, q3}, [r7]!
pld [r7]
vld2.8 {q4, q5}, [r11]!
mov r10, r3, asr #1
pld [r7, #32]
vld2.8 {q6, q7}, [r11]!
mul r10, r10, r6
pld [r11]
vld2.8 {q8, q9}, [r7]!
add r10, r10, r9, asr #1
pld [r11, #32]
vld2.8 {q10, q11}, [r7]!
add r8, r0, r10
vld2.8 {q12, q13}, [r11]!
mov r14, r3, asr #1
vld2.8 {q14, q15}, [r11]!
sub r14, r14, #48
vst1.8 {q0}, [r8]!
vst1.8 {q2}, [r8]!
vst1.8 {q4}, [r8]!
vst1.8 {q6}, [r8], r14
vst1.8 {q8}, [r8]!
vst1.8 {q10}, [r8]!
vst1.8 {q12}, [r8]!
vst1.8 {q14}, [r8]!
add r10, r1, r10
vst1.8 {q1}, [r10]!
vst1.8 {q3}, [r10]!
vst1.8 {q5}, [r10]!
vst1.8 {q7}, [r10], r14
vst1.8 {q9}, [r10]!
vst1.8 {q11}, [r10]!
add r6, #2
vst1.8 {q13}, [r10]!
cmp r6, r4
vst1.8 {q15}, [r10]!
blt LINEAR_X_SIZE_128_LOOP
add r9, r9, #128
LINEAR_X_SIZE_64:
sub r10, r3, r9
cmp r10, #64
blt LINEAR_X_SIZE_4
mov r5, r9
mov r6, #0
LINEAR_X_SIZE_64_LOOP:
bl GET_TILED_OFFSET
LINEAR_X_SIZE_64_LOOP_MEMCPY:
and r10, r6, #0x1F
mov r14, r3, asr #1
mov r10, r10, lsl #6
sub r14, r14, #16
add r10, r2, r10
add r7, r7, r10 @ tiled_addr = tiled_src+64*(temp1)
pld [r7, #64]
vld2.8 {q0, q1}, [r7]!
mov r10, r3, asr #1
pld [r7, #64]
vld2.8 {q2, q3}, [r7]!
mul r10, r10, r6
vld2.8 {q4, q5}, [r7]!
add r10, r10, r9, asr #1
vld2.8 {q6, q7}, [r7]!
add r8, r0, r10
vst1.8 {q0}, [r8]!
vst1.8 {q2}, [r8], r14
vst1.8 {q4}, [r8]!
vst1.8 {q6}, [r8], r14
add r10, r1, r10
vst1.8 {q1}, [r10]!
vst1.8 {q3}, [r10], r14
add r6, #2
vst1.8 {q5}, [r10]!
cmp r6, r4
vst1.8 {q7}, [r10], r14
blt LINEAR_X_SIZE_64_LOOP
add r9, r9, #64
LINEAR_X_SIZE_4:
cmp r9, r3
beq RESTORE_REG
mov r6, #0 @ i = 0
LINEAR_Y_SIZE_4_LOOP:
mov r5, r9 @ j = aligned_x_size
LINEAR_X_SIZE_4_LOOP:
bl GET_TILED_OFFSET
mov r11, r3, asr #1 @ temp1 = linear_x_size/2
mul r11, r11, r6 @ temp1 = temp1*(i)
add r11, r11, r5, asr #1 @ temp1 = temp1+j/2
mov r12, r3, asr #1 @ temp2 = linear_x_size/2
sub r12, r12, #1 @ temp2 = linear_x_size-1
add r8, r0, r11 @ linear_addr = linear_dest_u+temp1
add r11, r1, r11 @ temp1 = linear_dest_v+temp1
add r7, r2, r7 @ tiled_addr = tiled_src+tiled_addr
and r14, r6, #0x1F @ temp3 = i&0x1F@
mov r14, r14, lsl #6 @ temp3 = temp3*64
add r7, r7, r14 @ tiled_addr = tiled_addr+temp3
and r14, r5, #0x3F @ temp3 = j&0x3F
add r7, r7, r14 @ tiled_addr = tiled_addr+temp3
ldrh r10, [r7], #2
ldrh r14, [r7], #62
strb r10, [r8], #1
mov r10, r10, asr #8
strb r10, [r11], #1
strb r14, [r8], r12
mov r14, r14, asr #8
strb r14, [r11], r12
ldrh r10, [r7], #2
ldrh r14, [r7], #62
strb r10, [r8], #1
mov r10, r10, asr #8
strb r10, [r11], #1
strb r14, [r8], r12
mov r14, r14, asr #8
strb r14, [r11], r12
add r5, r5, #4 @ j = j+4
cmp r5, r3 @ j<linear_x_size
blt LINEAR_X_SIZE_4_LOOP
add r6, r6, #2 @ i = i+4
cmp r6, r4 @ i<linear_y_size
blt LINEAR_Y_SIZE_4_LOOP
RESTORE_REG:
ldmfd sp!, {r4-r12,r15} @ restore registers
GET_TILED_OFFSET:
stmfd sp!, {r14}
mov r12, r6, asr #5 @ temp2 = i>>5
mov r11, r5, asr #6 @ temp1 = j>>6
and r14, r12, #0x1 @ if (temp2 & 0x1)
cmp r14, #0x1
bne GET_TILED_OFFSET_EVEN_FORMULA_1
GET_TILED_OFFSET_ODD_FORMULA:
sub r7, r12, #1 @ tiled_addr = temp2-1
add r14, r3, #127 @ temp3 = linear_x_size+127
bic r14, r14, #0x7F @ temp3 = (temp3 >>7)<<7
mov r14, r14, asr #6 @ temp3 = temp3>>6
mul r7, r7, r14 @ tiled_addr = tiled_addr*temp3
add r7, r7, r11 @ tiled_addr = tiled_addr+temp1
add r7, r7, #2 @ tiled_addr = tiled_addr+2
bic r14, r11, #0x3 @ temp3 = (temp1>>2)<<2
add r7, r7, r14 @ tiled_addr = tiled_addr+temp3
mov r7, r7, lsl #11 @ tiled_addr = tiled_addr<<11
b GET_TILED_OFFSET_RETURN
GET_TILED_OFFSET_EVEN_FORMULA_1:
add r14, r4, #31 @ temp3 = linear_y_size+31
bic r14, r14, #0x1F @ temp3 = (temp3>>5)<<5
sub r14, r14, #32 @ temp3 = temp3 - 32
cmp r6, r14 @ if (i<(temp3-32)) {
bge GET_TILED_OFFSET_EVEN_FORMULA_2
add r14, r11, #2 @ temp3 = temp1+2
bic r14, r14, #3 @ temp3 = (temp3>>2)<<2
add r7, r11, r14 @ tiled_addr = temp1+temp3
add r14, r3, #127 @ temp3 = linear_x_size+127
bic r14, r14, #0x7F @ temp3 = (temp3>>7)<<7
mov r14, r14, asr #6 @ temp3 = temp3>>6
mul r12, r12, r14 @ tiled_y_index = tiled_y_index*temp3
add r7, r7, r12 @ tiled_addr = tiled_addr+tiled_y_index
mov r7, r7, lsl #11 @
b GET_TILED_OFFSET_RETURN
GET_TILED_OFFSET_EVEN_FORMULA_2:
add r14, r3, #127 @ temp3 = linear_x_size+127
bic r14, r14, #0x7F @ temp3 = (temp3>>7)<<7
mov r14, r14, asr #6 @ temp3 = temp3>>6
mul r7, r12, r14 @ tiled_addr = temp2*temp3
add r7, r7, r11 @ tiled_addr = tiled_addr+temp3
mov r7, r7, lsl #11 @ tiled_addr = tiled_addr<<11@
GET_TILED_OFFSET_RETURN:
ldmfd sp!, {r15} @ restore registers
.fnend
|
